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Modeling, Physics and Simulation of Nano-Scale Electronic Devices

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Title:
Modeling, Physics and Simulation of Nano-Scale Electronic Devices
Creator:
Chen, Wenchao
Place of Publication:
[Gainesville, Fla.]
Florida
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University of Florida
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english
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1 online resource (136 p.)

Thesis/Dissertation Information

Degree:
Doctorate ( Ph.D.)
Degree Grantor:
University of Florida
Degree Disciplines:
Electrical and Computer Engineering
Committee Chair:
GUO,JING
Committee Co-Chair:
LAW,MARK E
Committee Members:
RINZLER,ANDREW GABRIEL
SO,FRANKY FAT KEI
Graduation Date:
8/9/2014

Subjects

Subjects / Keywords:
Carbon nanotubes ( jstor )
Electric current ( jstor )
Electric potential ( jstor )
Electrons ( jstor )
Graphene ( jstor )
Modeling ( jstor )
Oxides ( jstor )
Photovoltaic cells ( jstor )
Simulations ( jstor )
Transistors ( jstor )
Electrical and Computer Engineering -- Dissertations, Academic -- UF
device -- modeling -- nano-scale -- physics -- semiconductor -- simulation
Genre:
bibliography ( marcgt )
theses ( marcgt )
government publication (state, provincial, terriorial, dependent) ( marcgt )
born-digital ( sobekcm )
Electronic Thesis or Dissertation
Electrical and Computer Engineering thesis, Ph.D.

Notes

Abstract:
Recently, significant progress has been made in fabrication, modeling and physics of nano-scale electronic devices based on one-dimensional (1D) and two-dimensional (2D) semiconductors, such as carbon nanotube (CNT), graphene, transition metal dichalcogenides. Organic/inorganic semiconductor thin film electronic devices fabricated with solution process, like vertical field effect transistor and permeable base transistor, also provide potential applications for future technology. These emerging electronic devices have different performances compared to traditional ones due to material properties and device structure. This dissertation presents author's modeling and simulation work on CNT, graphene, transition metal dichalcogenides based electronic devices and thin film electronic devices for understanding device physics and further device engineering. Chapter 1 presents a review of recent experimental and theoretic progresses on emerging 1D and 2D materials. Chapter 2 presents a carrier dynamics study of electrolyte-induced inversion layer CNT film solar cell. Operation mechanism of the solar cell is clarified. Device optimization is performed to improve solar cell efficiency. A computational study of CNT-organic material hetero-junction enabled vertical field effect transistors is performed in Chapter 3. Tunneling induced carrier generation is introduced to current continuity equation which is solved self-consistently with drift diffusion equation and Poisson equation. The scaling behavior is investigated for device engineering. In Chapter 4, vertical field effect transistor with porous graphene as source contact is investigated. Punching holes in the graphene sheet can improve current performance significantly. Operation mechanism and device optimization are carried out. Chapter 5 performs electro-thermal study of CNT-contacted phase change memory. Device scaling analysis is presented. Chapter 6 presents modeling and simulation study of permeable metal base transistor. Reasons for excellent saturation and high gain are presented. Intrinsic delay analysis is performed to guide design for GHz devices. Atomically thin MoS2-WSe2 vertical p-n junctions are studied in Chapter 7. Carrier recombination between two semiconductor layers plays critical role in determining I-V characteristics. Device physics and scaling behavior of monolayer MoS2 photodetectors with respect to gate oxide, channel length and hole mobility are investigated in Chapter 8. Finally, Chapter 9 concludes the dissertation and presents suggestions for future work. ( en )
General Note:
In the series University of Florida Digital Collections.
General Note:
Includes vita.
Bibliography:
Includes bibliographical references.
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Description based on online resource; title from PDF title page.
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This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Thesis:
Thesis (Ph.D.)--University of Florida, 2014.
Local:
Adviser: GUO,JING.
Local:
Co-adviser: LAW,MARK E.
Electronic Access:
RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2015-02-28
Statement of Responsibility:
by Wenchao Chen.

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UFRGP
Rights Management:
Copyright Chen, Wenchao. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Embargo Date:
2/28/2015
Resource Identifier:
969976906 ( OCLC )
Classification:
LD1780 2014 ( lcc )

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MODELING , PHYSICS AND SIMULATION OF NANO SCALE ELECTRONIC DEVICES By WENCHAO CHEN A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2014

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© 2014 Wenchao Chen

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To my family

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4 ACKNOWLEDGMENTS I would like to express my deep gr atitude and thanks to my advisor Prof. Jing Guo for his guidance and support to my research works. His insight and vision in device physics, modeling and simulation field are always illuminating and inspiring me to overco me all the obstacles and make this work possible. Besides these , Prof. Guo also creates opportunities to cooperate with, learn and benefit from top researchers in this field. This wonderful experience working with Prof. Guo, which I have been cherish ing th roughout , will benefit my whole life. I t is a great pleasure to thank Prof . Mark Law, Prof . Andrew G. Rinzler and Prof . Franky So for serving on my advisory committee and their helpful suggestions on my research. I am also very grateful for the fruitful collaborations and helpful discussions with Prof . Andrew G. Rinzler, Prof . Franky So, Hyeonggeun Yu , Bo Liu, Pooja Wadhwa, Maxime Lemaitre and Po Hsiang Wang at University of Florida , Prof. Philip Kim and Dr. Chul Ho Lee at Columbia University . I am also pleased to express my thanks to my colleagues Dr. Yijian Ouyang, Dr. Jyotsna Chauhan, Dr. Bala Kumar, Dr. Kai Tak Lam, Yang Lu, Qun Gao, Gyungseon Seol, Leitao Liu, Dukjin Kim, Xi Cao, Zhipeng Dong, Runlai Wan for their h elp and collaboration. The experience is pleasant and enjoyable. Finally, I want to thank my parents for their encouragement and support.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ .. 4 LIST OF TABLES ................................ ................................ ................................ ............ 7 LIST OF FIGURES ................................ ................................ ................................ .......... 8 LIST OF ABBREVIATIONS ................................ ................................ ........................... 11 ABSTRACT ................................ ................................ ................................ ................... 13 CHAPTER 1 INTRODUCTION ................................ ................................ ................................ .... 15 Carbon Nanotube and Carbon Nanotube Thin Film ................................ ................ 15 Graphene Electronics ................................ ................................ ............................. 17 Monolayer Transition Metal Dichalcogenides ................................ ......................... 17 Simulation Methodology ................................ ................................ .......................... 18 2 ELCTROLYTE ENHANCED CARBON NANOTUBE THIN FILM SILICON SCHOTTKY JUNCTION SOLAR CELL ................................ ................................ .. 19 Modeling and Simulation Approach ................................ ................................ ........ 20 Carrier Dynamics ................................ ................................ ................................ .... 21 Efficiency Optim ization Design ................................ ................................ ............... 24 Summary ................................ ................................ ................................ ................ 26 3 CARBON NANOTUBE ENABLED VERTICAL FIELD EFFECT TRANSISTOR ..... 31 Modeling and Simulation Approach ................................ ................................ ........ 32 Physical Mechanisms and Performance Analysis ................................ ................... 37 Device Scaling Design ................................ ................................ ............................ 38 Summary ................................ ................................ ................................ ................ 42 4 POROUS GRAPHENE ENHANCED VERTICAL FIELD EFFECT TRANSISTOR . 51 Modeling and Simulation Approach ................................ ................................ ........ 52 Physical Mechanisms for Performance Enhancement ................................ ............ 55 Performance Optimization Design ................................ ................................ .......... 56 Summary ................................ ................................ ................................ ................ 58 5 PERFORMANCE ENHANCEMENT OF PHASE CHANGE MEMORY BY CARBON NANOTUBE CONTACTS ................................ ................................ ....... 64 Modeling and Simulation Approach ................................ ................................ ........ 65

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6 Simplify 3D Structure to 2D Structure ................................ ................................ ..... 67 Comparison to State of the art PCM ................................ ................................ ...... 69 Design Optimization ................................ ................................ ................................ 71 Summary ................................ ................................ ................................ ................ 75 6 MODELING AND SIMULATION OF HIGH GAIN PERMEABLE BASE TRANSISTORS ................................ ................................ ................................ ...... 82 Mechanisms for Excellent Saturat ion and High Gain ................................ .............. 83 Intrinsic Delay of Permeable Base Transistor ................................ ......................... 87 Intrinsic Delay Optimization Design ................................ ................................ ........ 89 Summary ................................ ................................ ................................ ................ 92 7 ELECTRONIC CHARACTERIS TICS OF ATOMICALLY THIN VERTICAL P N JUNCTION ................................ ................................ ................................ .............. 99 Modeling and Simulation of Monolayer p n Junction ................................ ............ 100 Device Physics of Monolayer p n Junction ................................ ........................... 103 Graphene Sandwiched p n Junctions ................................ ................................ ... 105 Summary ................................ ................................ ................................ .............. 106 8 SCALING BEHAVIOR OF HIGH GAIN MONOLAYER MOS 2 PHOTODETECTOR ................................ ................................ ............................. 113 Modeling and Simulation Approach ................................ ................................ ...... 114 Physical Mechanisms for Ultrahigh Photoresponsivity ................................ .......... 115 MoS 2 Photodetector Scaling Design ................................ ................................ ..... 119 Summary ................................ ................................ ................................ .............. 120 9 CONCLUSION AND OUTLOOK ................................ ................................ ........... 125 Conclu sion ................................ ................................ ................................ ............ 125 Outlook ................................ ................................ ................................ ................. 125 LIST OF REFERENCES ................................ ................................ ............................. 126 BIOGRAPHICAL SKETCH ................................ ................................ .......................... 136

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7 LIST OF TABLES Table page 5 1 Performance comparison between CCPCM and the state of the art PCM including nanowire PCM (NWPCM) and thin film PCM (TFPCM). ...................... 70

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8 LIST OF FIG URES Fig ure page 2 1 Metal insulator semiconductor solar cell device structure. ................................ . 27 2 2 Energy band profile for metal insulator semiconductor solar cell. ...................... 27 2 3 Electrolyte enhanced CNT thin film solar cell structure, band profile and carrier density distribution. ................................ ................................ .................. 28 2 4 Calculated current components under short circuit condition and IV characteristics. ................................ ................................ ................................ .... 29 2 5 Carrier density for device with hole block layer and IV comparison. ................... 30 3 1 Device structure of CNT enabled vertical field effect transistor. ......................... 44 3 2 Description for taking tunneling current into consideration. ................................ 44 3 3 Barrier height as a function of gate bias and band profile for different gat e bias. ................................ ................................ ................................ .................... 45 3 4 Jd Vg characteristics.. ................................ ................................ ........................ 45 3 5 Scaling of CNT diameter. ................................ ................................ ................... 46 3 6 Scaling of oxide. ................................ ................................ ................................ . 46 3 7 Comparison of two different oxide scaling methodologies. One is to vary oxide permittivity with fixed oxide thickness. The other is to vary oxide thickness with fixed oxide permittivity. ................................ ................................ 47 3 8 Effect of channel mobility. Jd Vg curves with different mobility of the active channel layer. ................................ ................................ ................................ ..... 47 3 9 Effect of channel length scaling: Jd Vg curves for different channel length. ....... 48 3 10 Effect of SWNT spacing.. ................................ ................................ ................... 49 3 11 Effect of the number of metallic SWNTs in a 5nm diameter bundle. .................. 50 4 1 Device structure and band profile for graphene vertical field effect transistor. ... 60 4 2 Current density profile in the x y plane at the beginning of the channel. The effective region is around the punched hole edge. ................................ ............. 61 4 3 Band profile and Jd Vg characteristics for device with different hole size. ......... 61

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9 4 4 Band profile and Jd Vg characteristics for device with different number of graphene layers. ................................ ................................ ............................... 62 4 5 Band profile and Jd Vg characteristics for device with different hole area percentage. ................................ ................................ ................................ ......... 62 4 6 Jd vs. Vg characteristics for the different effective mass of the channel material. ................................ ................................ ................................ .............. 63 5 1 Cross Schematic 3D structure of CNT contacted phase change m emory . ......... 76 5 2 Simplified 2D structure for simulating the 3D device as shown in Fig ure 5 1 without losing accuracy. ................................ ................................ ..................... 76 5 3 Temperature profile for CNT PCM. ................................ ................................ ..... 77 5 4 Temperature profiles along a certain direction. ................................ ................... 78 5 5 Transient set process temperature profiles of carbon nanotube contac ted PCM (CCPCM), nanowire PCM (NWPCM) and thin film CPM (TFPCM). .......... 79 5 6 The highest temperature change as a function of the resistivity of amorphous phase change material and the thermal boundary resistance with applied voltage 3.5V. ................................ ................................ ................................ ....... 79 5 7 Programming po wer as a function of gap size and CNT length. ......................... 80 5 8 M inimum gap size determined by E quation 5 8 as a function of GST resistivity w ith different electrode resistance. ................................ ..................... 80 5 9 Set/Reset power as a function of the CNT diameter. The corresponding TBR is 35 ×10 9 m 2 K/W . The length of the CNTs is 2.4µm. The gap size is 35nm. ...... 81 6 1 Cross section of experimental device structure. ................................ ................. 93 6 2 Device structure, simulated band profile and simulated JV characteristics. ....... 94 6 3 Description for base current calculation. ................................ ............................. 95 6 4 Modeled permeable base transistor schematic with uniform pore array. ............ 95 6 5 IV characteristics and band profiles.. ................................ ................................ .. 96 6 6 Charge in base, collector and emitter as a function of bias. ............................... 97 6 7 Intrinsic delay as a function of emitter thickness and base thickness. ................ 97

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10 6 8 Intrinsic delay for collector (t c ), emitter(t e ), base(t b ) and the whole device t tot as a function of emitter barrier height with L e =60nm, L b =10nm, L c =400nm, mobility 5cm 2 /V/s, V e =0V, V b =0.5V and V c =1V. ................................ .................. 98 6 9 Intrinsic delay for collector (t c ), emitter(t e ), base(t b ) and the whole device t tot as a function of carrier mobility with L e =10nm, L b =10nm and L c =400nm, em itter barrier height 0.3eV. ................................ ................................ ............... 98 7 1 Device schematics. ................................ ................................ ........................... 108 7 2 Simulated device structure with a 280nm thick SiO 2 gate dielectric and 200nm thick source/drain electrodes. ................................ ............................... 108 7 3 B and profiles obtained from device simulation. Electrons in conduction band of MoS 2 and holes in valence band of WSe 2 get combined through SRH or Langevin mechanism, contributing to dark current. ................................ .......... 109 7 4 Band diagrams in the lateral direction at V s d = 0.6 V (top), 0 V (middle) and 0.6 V (bottom) obtained from self consistent simulation. ................................ .. 110 7 5 Comparison of the measured and the simulated I V curves in the dark at V g = 0 V. SRH and Langevin mechanisms are considered separately. .................... 111 7 6 Simulated bell sha pe current characteristics. ................................ ................... 111 7 7 Modeling method for multi layer graphene contacted pn junctions. .................. 112 8 1 Schematic structure of a MoS 2 photodetector. ................................ ................. 121 8 2 Band profile and hole density distribution. ................................ ........................ 121 8 3 IV characteristics. ................................ ................................ ............................. 122 8 4 Photoresponsivity with respect to gate bias and carrier lifetime. ...................... 122 8 5 Current and photoresponsivity as a function of gate oxide thickness. .............. 123 8 6 Photorespons ivity (PR) as a function of hole mobility for different gate bias. ... 123 8 7 Photoresponsivity (PR) as a function of channel length with different gate bias. ................................ ................................ ................................ .................. 124

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11 LIST OF ABBREVIATIONS 1D One dimensional 2D Two dimensional 3D Three dimensional BHM Barrier Height Modulation CNT Carbon nanotube CNT VFET Carbon nanotube enabled vertical field effect transistor DD Drift diffusion DIBL Drain induced barrier lowering DOS Density of states FEM Finite element method FET Field effect transistor FVM Finite volume method GVFET Graphene enhanced v ertical field effect transistor HAP Hole area percentage I V Current voltage J V Current density voltage m CNT Metallic carbon nanotube MIS Metal insulator semiconductor OFET Organic field effect transistor PBT Permeable base transistor P CM Phase change memory P R Photoresponsivity S RH Shockley Read Hall SS Sub threshold Swing

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12 SW NT Single walled carbon nanotube T BR Thermal boundary resistance TFT Thin film transistor TMM Transfer matrix method TMD Transition metal dichalcogenide VFET Vertical field effect transistor WKB Wentzel Kramers Brillouin

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13 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy MODELING , PHYSICS AND SIMULATION OF NANO SCALE ELECTRONIC DEVICES By Wenchao Chen A ugust 2014 Chair: Jing Guo Major: Electrical and Computer Engineering Recently, significant progress has been ma de in fabrication, modeling and physics of nano scale electronic devices ba sed on one dimensional ( 1D) and two dimensional ( 2D) semiconductor s , such as carbon nanotube ( CNT), graphene , transition metal dichalcogenides . Organic /inorganic semiconductor thin film electronic devices fabricated with solution process , like vertical field effect transistor and permeable base transistor , also provide potential applications for future technology . These emerging electronic devices have different performances compared to traditional ones due to material properties and devic e structure . This dissertation presents author's modelin g and simulation work on CNT, graphene, transition metal dichalcogenides based electronic devices and thin film electronic devices for understanding device physics and further device engineering. Chap ter 1 presents a review of recent experimental and theoretic progresses on emerging 1D and 2D materials . Chapter 2 presents a carrier dynamics study of electrolyte induced inversion layer CNT film sola r cell. Operation mechanism of the solar cell is clarif ied. Device optimization is performed to improve solar cell efficiency.

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14 A computational study of CNT organic material hetero junction enabled vertical field effe ct transistors is performed in C hapter 3. Tunneling induced carrier generation is introduced t o current continuity equation which is solved self consistently with drift diffusion equation and Poisson equation. The scaling behavior is investigated for device engineering. In C hapter 4, vertical field effect transistor with porous graphene as source c ontact is investigated. Punch ing holes in the graphene sheet can improve current performance significantly. Operation mechanism and device optimization are carried out. Chapter 5 performs electro thermal study of CNT contacted phase change memory. Device s caling analysis is presented. Chapter 6 presents modeling and simulation study of permeable metal base transistor . Reasons for excellent saturation and high gain are presented . Intrinsic delay analysis is performed to guide design for GHz devices. Atomically thin MoS 2 WSe 2 vertical p n junctions are studied in C hapter 7 . Carrier recombination between two semiconductor layers plays critical role in determining I V characteristics. Device physics and scaling behavior of monolayer MoS 2 photodetectors with respect to gate oxide, channel length and hole mobility are investigated in C hapter 8 . Finally, C hapter 9 concludes the dissertation and presents suggestions for future work.

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15 CHAPTER 1 INTRODUCTION Carbon nanotube, graphene and transition metal dichalcogenides are attracting more and more attention s for their great potential in future electronic applications because of their electrical , optical or mechanical properties. In th is dissertat ion, electronic devices based on these materials will be discussed and investigated. Thus, as the beginning of the dissertation, some fundamentals of carbo n nanotube ( CNT), CNT thin film, graphene and transition metal dichalcogenides should be introduced. Besides devices based on these emerging materials, electronic devices with non traditional structures, such as vertical field effect transistor and permeable base transistor, are also studied. In order to make the dissertation well organized and concise, f undamentals of non traditionally structured devices will be introduced in relevant chapter s separately . Carbon Nanotube and Carbon Nanotube Thin Film Since 1991 when carbon nanotubes ( CNTs) were firstly discovered by Iijima [ 1 ] , a lot of efforts have been spent in exploring fundamental material physics and possible applications for engineering [ 2 ] . Carbon nanotube s ha ve quasi 1D nanostructure. Whether the CNT is metallic or semiconducting depends on its chirality [ 3 ] . Metallic CNT ( mCNT) can be applied as interconnects [ 4 6 ] . While, semiconducting CNT can be used to build transistor [ 7,8 ] . Excellent performance can be predicted for CNT transistors due to its electrical properties, like high mobility or nearly ballistic transport [ 9 13 ] . Another application of CNT is for contact of phase change memory ( PCM) [ 14 ] , which gives ultra low programming current and programming power and allows scalability of future PCM device. CNT can also be used as electrode for solar cell [ 15 ] for its nearly transparent

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16 property. In general, mCNTs are used for electrode application . Metallic CNT is also called semi metal and has relatively low density of states ( DOS) compared to metal. For the lowest subband, the density of states is listed as follows [ 16 ] , ( 1 1) Due to the low density of states, the Schottky barrier between the CNT and other semiconductor materials can be modulated by ele ctric field, which is different from conventional metal which has very large density of states and hardly can be modulated by external electric field. CNTs can be also used to form CNT thin film. The process for fabrication of ultrathin, transparent and e lectrically conducting films is described in [ 17 ] . An electric field activated optical modulator is also demonstrated as an example application. Due to CNT's large ratio of surface area to volume, electric property is very sensitive to external change, lik e molecule absorbing. Thus, it is advantageous for CNT or CNT thin film to be used as sensor [ 18,19 ] . CNT thin film is also suitable for electrodes in vertical field effect transistor in low cost display application due to its transparency and decent elect rical conductivity [ 20 ] . For different applications, CNTs functionalize differentl y. For PCM, the CNT is electrode to allow current getting through. For CNT thin film solar cell, CNT is used to not only allow light penetrating through and getting absorbed by substrate due to its transparent property but also to form a Schottky junction between substrate semiconductor material to separate electrons and holes. For CNT transistors, CNT may act as a channel. While for CNT vertical field effect transistors, CNT acts as a source

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17 contact to form a Schottky junction between the channel semiconductor which can be modulated by gate electric field. Thus, the modeling methodologies of CNT for different applications are different. In this dissertation, different CNT bas ed electronic devices are discussed and investigated. The modeling strategies for CNTs are discussed in the C hapter 2, 3 and 5 based on different applications . Graphene Electronics Monolayer graphene is a two dimensional material, which has high conductivity and is suitable for electronic applications [ 21,22 ] . Due to its high carrier mobility, graphene can be potentially used for high frequency transistor for RF application [ 23 ] . Because of its optical transpar ency which is similar to CNT, graphene can be applied as electrodes for light emitting device or solar cell [ 24 ] . Graphene has linear E k relation and low density of states. Thus, the Schottky junction between graphene and semiconductor can also be modula ted by electric field [ 25 ] . The Schottky junction between a few graphene layers and semiconductor becomes difficult to be modulated owning to strong electrostatic screening [ 25 ] . Monolayer Transition Metal Dichalcogenides Transition metal dichalcogenide materials have a common formula MX 2 , in which M is a transition metal and can be Mo, W, Nb, Ta, Ti or Re, while X can be Se, S or Te. Bulk TMD materials are formed by vertically stacking mono layers with weak bonds by van der Waals interactions between adj acent layers. Typically, m onolayer transition metal dichalcogenide is direct band semiconductor with a bandgap of 1.1eV~2.0eV [ 26, 27 ] . Monolayer TMD material transistors with decent carrier mobility have been demonstrated, either MoS 2 [ 28 ] based or WSe 2 [ 29,30 ] based. Because of the

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18 bandgap, TMD transistors demonstrate high current on/off ratio [ 28 31 ] . Due to its excellent electrical and optical properties for future technology, monolayer transition metal dichalcogenide based electronic devices have bee n a hot topic . In this dissertation, monolayer MoS 2 and WSe 2 based electronic devices will be modeled and simulated. Simulation Methodology As more and more progress is being achieved in fabrication and test of nano scale electronic devices, the need for d evice modeling and simulation to reveal device physics and further optimize device performance is demanding . In general , the idea for device simulation is to solve the transport equation self consistently with Poisson equation. It is because transport tends to rearrange carriers in the system, thus leading to variation of electrostatic potential which also introduce feedback into the transport process. After converge, the characteristics of electrostatics and transport can be obtained to further analyze device performance. In this dissertation, the transport process is described by drift diffusion ( DD) equations, and DD equations and Poisson equation are solved self consistently by finite element method ( FEM) or by finite difference me t hod ( FDM).

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19 CHAPTER 2 ELCTROLYTE ENHANCED CARBON NANOTUBE THIN FILM SILICON SCHOTTKY JUNCTION SOLAR CELL Metal insulator semiconductor ( MIS) grating solar cells were demonstrated and studied around 30 years ago. The active area efficiency can be as high as around 18% for the MIS solar cell [ 32 34 ] . The solar cell device schematic is redrawn and shown in Fig ure 2 1 as in [ 32 34 ] . An insulator layer is sandwiched between the metal contact and substrate. It should be noted here that metal conta ct only covers a fraction of semiconductor. So light can go through the metal uncovered region and generate electrons and holes. However, if the metal contact covers small fraction of the semiconductor to allow more light to penetrate into semiconductor , the lack of Schottky junction area between metal and semiconductor results in low efficiency to separate electrons and holes. On the other hand, if the metal contact covers large fraction of the semiconductor, less light can go through and generate carriers, thus also gives low efficiency. Hence there should be a n optimized value for the coverage of the metal or use transparent metal to overcome this drawback . The band profile for the MIS solar cell is illustrated in Fig ure 2 2 for the n type semiconductor substrat e [ 32 34 ] . The holes and electrons are separated in the depletion region. E lectrons are collected by the metal contact after tunneling through the thin insulator, while holes are collected by the bottom contact. Trapped charge is introduced to the insulato r layer to induce an inversion layer, which helps the collection of photo generated carriers [ 34 ] . On the other hand, the insulating layer tends to improve the surface recombination, thus leading to a higher efficiency by reducing carrier loss [ 35 ] . The in sulating layer should be very thin to allow

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20 carriers to tunnel through, otherwise it will block the way for carriers to get collected by metal contact and does not help to achieve performance improvement. Although the MIS solar cell can give satisfactory e fficiency, it is still not commercialized due to its vital drawbacks [ 35 37 ] . One of them is that the surface properties are unstable under exposure to sunlight, thus leading to unstable device performance. Another is degradation of fixed charge in the ins ulating layer, which causes degradation or even disappearance of inversion layer and may lower solar cell efficiency significantly. In order to get rid of these main drawbacks, non traditionally structured solar cell s with carbon nanotube thin film as contact are demonstrated and studied [ 38,39 ] . In this kind of solar cell, CNT film partially covers the Si surface and forming a Schottky junction in between . An inversion layer in the uncovered surfaces is induced by electrolyte, whi ch is more stable than the fixed charge induced inversion layer for the MIS solar cell. Hence, it remedies the instability problem of MIS grating solar cells. Some semi analytical models for silicon MIS grating solar cells have been developed [ 34,40 42 ] . T hey are based on simplified assumptions that are necessary for semi analytical solutions but compromise the accuracy and predictive power of the model. On the other hand, modeling of the electrolyte induced inversion solar cell is limited to electrostatic calculations only [ 39 ] . So a comprehensive study of the carrier dynamics is necessary to elucidate the device operation mechanism and further optimize the device performance. Modeling and Simulation Approach The solar cell device structure for modeling is similar to that in a recent experiment on electrolyte induced inversion layer solar cell [ 39 ] , as presented in Fig ure

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21 2 3 A. Similarly, the electrolyte is modeled as a material with very high dielectric constant due to its very short Debye length [ 39 ] . The length ratio between the CNT covered and uncovered regions is 50 150 . The electrode on top of SiO 2 is treated as a floating gate for simplicity. Interface carrier recombination is neglected. The lifetime of electrons and holes is set as and , consistent with the values of high quality single crystal Si, and it is tested that further increase of the lifetime only quantitatively perturbs the results slightly, approaching the performance of solar cell almost without ( Shockley Read Hall) S RH recombination. The CNT film is modeled as an optically partly transparent, electrically conductive metal film which forms a Schottky barrier contact with Si [ 39 ] . This is a simplified treatment without c onsidering the interface trap charges between CNT and Si and low density of states of the CNT film. The device operation mechanisms of interest here, however, are insensitive to the exact details of the CNT film. For optical property, 20% of input light po wer is reflected and the other 80% power is absorbed by the CNT covered Si. By using the device simulation package Synopsys TCAD Sentaurus [ 43 ] , optical generation is solved by the transfer matrix method ( TMM) . A two dimensional Poisson equation is solved to describe electrostatics of the complex device structure, self consistently with a numerical solution of two dimensional drift diffusion equations and continuity equation . Carrier Dynamics In this section, interplay of electrostatics and current flow in the electrolyte induced inversion layer CNT Si solar cell is investigated to clarify the device operation

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22 mechanism. Two cases for the solar cell with and without electrolyte are compared by detailed numerical simulations. The results provide clear explan ation and visualization of the carrier flow pattern, which is useful for understanding the operation principle of the solar cell and the physical mechanisms that limit the efficiency. Finally, a heavily doped layer is introduced to operate as a hole block layer for performance optimization. The conduction band energy profile is pre sented in Fig ure 2 3 B . T he highlighted curve is the edge of carrier depletion region, which becomes narrow as approaching the right edge. An x component ( along the horizontal dire ction) of the electric field, which is the gradient of equal potential lines, can be identified in the CNT uncovered region near the surface. In addition, the narrower depletion region at a larger x position results in less efficient electron hole pair sep aration. Fig ure 2 3 C and 2 3 D compare hole density distribution around depletion region under AM1.5g sun spectrum illumination between solar cell with and without electrolyte. It is assumed the photon absorption for CNT covered silicon is 80% of that of CN T uncovered silicon. A hole inversion layer is formed in the solar cell with e lectrolyte as shown in Fig ure 2 3 C , in which the holes tend to drift to the CNT covered region due to the x component of electric field as mentioned above. On the other hand, the holes also diffuse from the CNT uncovered region to the CNT covered region because of the density gradient in the horizontal direction. An undesired diffusion path for holes also exists. The hole density gradient in the region outside the depletion region around the right edge makes a path for the hole to diffuse and leak out to the bottom. It is mainly due to the narrow depletion region, which is not wide enough to separate electrons and holes. I n comparison, for the solar cell wi thout the electrolyte ( Figure 2 3 D), hole

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23 inversion layer only appears in the CNT covered region. The holes in the CNT uncovered region cannot be collected by the CNT contact without electrolyte due to lack of either diff usion or drift mechanisms along x direction as identified from the density and band profile plots with electrolyte described above. Next, carrier dynamics and I V characteristics of the solar cell are investigated. The carrier flow pattern for the cell wit h el ectrolyte is shown in Figure 2 4 A D. The total current density is broken down to electron and hole currents, along the horizontal direction ( denoted as the x component) and the vertical direction ( denoted as the y component), which helps to clarify how photo generated carriers are separated and collected, especially in the region where top c ontact does not exist. Fig ure 2 4A and Fig ure 2 4B are the y component of photon current for holes and electrons, respectively. The simulation results which break th e total current down to the drift and diffusion components indicate that the hole current along the vertical direction is driven domi nantly by the drift. Fig ure 2 4A also has non preferred positive current density in the region around the right edge, which means that the holes move to the bottom because of inefficient electron hole separation. The total photon y current component is plotted in Fig ure 2 4C , which is generated by adding Fig ure 2 4A and Fig ure 2 4B The x component of the hole pho ton current density in Fig ure 2 4D has a very large magnitude in the thin inversion layer as inferred above. Breaking down the x compo nent to the drift and diffusion currents shows that the diffusion component is more dominant in the inversion layer. The x component of total photon current density, which is addition of the hole contribution and the electron contribution that is

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24 considera bly smaller, is app roximately the same as Fig ure 2 4D . The results clarify how the photo generated holes are separated and collected in the uncontacted region. In the CNT uncovered region in the presence of electrolyte, the photo generated holes, after its separation with electrons in the depletion layer, is first driven dominantly be drift vertically to the inversion layer, and subsequently driven dominantly by diffusion along the horizontal direction, to be collected by the partially covered CNT contact. In comparison, Fig ure 2 4E is the y component of photon current flow for the solar cell without electrolyte, which shows no y direction current density in the CNT uncovered region. Simulation shows that the x component of photon current density can be negl ected due to its small magnitude ( not shown). The current flow pattern is drastically different from that in the presence of electrolyte, which lacks any carrier collection mechanism in the uncontacted region. Fig ure 2 4F shows the J V curve for the solar cells with and without electrolyte. The normalized current density on the CNT contact under short circuit condition increases from 5.43 for cell without electrolyte to 15.51 for cell with electrolyte. The J V curve for solar cell with electrolyte has a slope from 0 to 0.4V. It is because the depletion region in the CNT uncovered region shrinks as the applied voltage increases, and it even disappears around the right edge 4 as the applied voltage increas es. Efficiency Optimization Design Inefficiency of carrier separation in the region far aw ay from the contact in Fig ure 2 4C is due to an undesired path for holes to leak out to the bottom contact as shown in Fig ure 2 4A . To fix this problem, we propose a heavily doped thin layer as a hole block

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25 layer to cut this path off to improve the solar cell efficiency. A heavily doped thin layer is normally used to reduce the carrier surface recombination and contact resistance in a solar cell design [ 44 ] , however we emphasize a different mechanism here as a hole blocking layer which is particularly useful for partially contacted solar cells with an induced inversion layer, such as the electrolyte induced inversion layer solar cell or the MIS grating solar cell . A 1 n silicon layer with n type doping density is introduced at the bottom as shown in Fig ure 2 5A , to create a hole barrier between the lowly doped silicon and highly doped silicon. The hole d ensity distrib ution in Fig ure 2 5A shows that holes accumulate at the right side region because of the hole barrier created by hole block layer, and diffuse to the CNT covered region to be collected by the CNT contact. T he normalized J V characterization s of the solar c ell with and without the hole block l ayer with dimension as Fig ure 2 3A are shown in Fig ure 2 5B. The short circuit current density boosts from 15.51 to 26.84 by a factor of 73. 1 %, with the corresponding carrier collection efficiency improvement from 48.2 % to 8 3 . 5 % for the cell without and with the hole block layer , respectively. For comparison, a solar cell with a shorter CNT uncovered length of 75 and the same CNT covered length 50 is simulated for comparison . T he simulated normalized short circuit current density increases from 21.81 to 25.98 with corresponding carrier collection efficiency improvement from 7 0.0 % to 8 3 . 4 % , by a factor of 19.1%, if a hole block layer is used . Hence, the efficiency improvement is considerably more significant for the cell with a larger CNT uncovered length because of its larger fraction of holes leakage without the hole block layer. The fill factor is also improved because in the presence of the hole block layer, the hole current from Si to the back electron contact is blocked regardless

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26 of the applied voltage. Hence, in spite of change of the depletion region thickness that would have vary the photocurrent without the hole block layer, the current density keeps nearly unchanged as the applied voltage increases from 0 to 0.45V in the presence of the hole block layer. The hole block layer can significantly improve the sola r cell efficiency by preventing holes from leaking to the bottom contact. Summary In summary, the hole current in the bulk Si is dominantly delivered by a vertical current flow driven by drift, but delivered by a horizontal flow driven by diffusion at the inversion layer near the surface. The hole current density along the horizontal direction in the inversion layer is orders of magnitude larger than that in bulk, indicating the important role of improving carrier transport properties of the inversion layer , such as the inversion layer mobility for reducing the series resistance of the solar cell. It is also demonstrated that a heavily doped back layer operates as a hole block layer that improves the device performance. The improvement is more significant wh en the CNT uncovered region is larger, which indicates the usage of the hole block layer could allow a larger uncovered region that absorbs light better than the contacted Si surface region. The qualitative physical insights obtained here for electrolyte i nduced inversion layer solar cells can be applied to MIS grating silicon solar cell s , which ha ve similar operation mechanisms.

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27 Fig ure 2 1. Metal insulator semiconductor solar cell device structure , redrawn according to [ 32 34 ] . Fig ure 2 2. Energy band profile for metal insulator semiconductor solar cell , redrawn according to [ 32 34 ] .

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28 A B C D Fig ure 2 3. Electrolyte enhanced CNT thin film solar cell structure, band profile and carrier density distribution. A) Solar cell structure. Work function of carbon nanotube is 4.9eV. Doping concentration of n Si is 1×10 15 /cm 3 . B) Conduction band energy . C) Hole density around the depletion region for cell with electrolyte . D ) Hole density around the depletion region for cell without electrolyte . Both C and D are under short circuit with illumination of AM1.5g sun spectrum.

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29 A B C D E F Fig ure 2 4. Calculated current components under s hort circuit condition and IV characteristics . A ) y component of the hole photon current density . B ) y component of the electron photon current density . C ) y component of the total photon current density . D) The x component of the hole photon current density . A D are for the solar cell with electrolyte. E ) For comparison, y component of total photon current density for solar cell without electrolyte. F ) Normalized J V curve comparison of the solar cells with and without electrolyte.

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30 A B Fig ure 2 5. Carrier density for device with hole block layer and IV comparison. A) Hole density distribution for the solar cell with electrolyte and hole block layer under short circuit with illumination of AM1.5g sun spectrum. The doping density for the hole block layer ( the bottom layer) is 1×10 20 /cm 3 , and that of the rest part is 1×10 15 /cm 3 . B) Normalized J V curve comparison between solar cell with and without hole block layer ( BL) for th e cell with dimen sion as Fig ure 2 3 A .

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31 CHAPTER 3 CARBON NANOTUBE ENABLED VERTICAL FIELD EFFECT TRANSISTOR In this chapter, carbon nanotube ( CNT) organic semiconductor heterojunction enabled vertical field effect transistors are modeled and simulated. The device scaling behavior s are comprehensively examined by two dimensional consistent simulations. Tunneling current is modeled by introducing tunneling induced carrier generation into the current continuity equation. Modulation of both the CNT semiconductor Shottk y barrier height and thickness are examined. The tunneling current and thermionic current dominate at on state and off state, respectively. Barrier height modulation plays an important role and improves the on off current ratio and sub threshold swing ( SS ) considerably. Small diameter CNT is preferred for enhancing gate control on the CNT channel barrier height. Reducing the effective gate oxide thickness by either a thin oxide or a high gate insulator gives improvement of device performance . But the fo rmer one works more efficiently. High carrier mobility channel material is preferable to get high on off current ratio due to its different effects on on current and off current. The channel length and CNT spacing should be carefully engineered due to the trade off between device characteristics in the sub threshold and above threshold region. Thin film transistors ( TFTs) [ 45 ] based on inorganic materials like Si are the current mainstream and widely used for display devices and solar cells . However, the organic semiconductor material based TFTs have been vigorously investigated for over two decades in an effort to allow for flexible displays and low temperature, low cost processing [ 46 49 ] . Since the performance of organic TFTs is limited by its low carri er mobility [ 46,50 ] , a planar organic TFT should be fabricated by patterning the source and

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32 the drain in close proximity for a short channel length, thus leading to cost of high resolution lithography. Recently, vertical organic TFTs, in which the gate, so urce, channel and drain are vertically stacked, have been demonstrated using either a thin metal film or a carbon nanotube ( CNT) film as a source electrode [ 20,51 53 ] . CNT film has been wi d e ly investigated for its applications by forming Schottky junction [ 17,38 , 54,55 ] , like transistor, solar cell and etc . The schematic structure of CNT enabled vertical organic field effect transis tor ( OFET) is shown in Fig ure 3 1A . The CNT thin film forms a dilute source electrode on a gate insulator. A thin organic semico nductor is deposited onto the CNT film as the channel. The CNT film is well above the percolation threshold to act as the source electrode [ 56,57 ] , an d meanwhile it is sufficiently dilute to allow gate electric field to penetrate through for modulating the CNT channel Schottky barrier and the band profile in organic layer. A significant operation difference between the vertical OFET and the horizontal one is that the former is a tunneling device. Thus, modulation of the CNT channel Schottky barrier height due to the low density of states of CNT plays an important role in determining both tunneling current and thermionic current to characterize the device performance. The se differences in operation mechanism s and device structure make the commonly applied scaling laws and optimization methodologies for horizontal field effect transistors inapplicable. Hence, device modeling and numerical simulation are necessary to elucidate device physics and scaling principl es in order to optimize device performance. Modeling and Simulation Approach In order to understand the device operation mechanism and explore the design optimization, the CNT enabled vertical OFET is modeled and simulated . A schematic

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33 device structure is presented in Fig ure 3 1A , for which the gate, oxide, source, channel and drain are vertically deposited [ 52,53 ] . The CNT thin film, which acts as the carrier source, needs to be dilute enough to allow the gate electric field to penetrate into the organic c hannel region. Since the CNT thin film is dilute, we make the following assumptions to simplify the modeling , with the device structure as shown in Fig ure 3 1B . ( i) The CNTs in actual devices are bundles of CNTs but these are modeled as a single metallic C NT with a diameter of 5nm ( the average bundle diameter observed experimentally) which acts as the carrier source. ( ii) Periodic boundary condition is used to set the left and right boundaries. ( iii) The device is uniform in CNT length direction. The nomina l device parameters are listed as follows. The metallic CNT diameter is D CNT = 5nm, and only one CNT exists within a neighboring distance of 200nm in the horizontal direction. The thickness of the active organic semiconductor layer, which is the channel le 1.5x10 4 m 2 ch = 6. A 20nm thick insulator layer ox =4 is used as gate insulator. The applied voltage s for source and drain are V s =0, V d = 1V, respectively. The above parameters are nominal, and they may be varied to explore scaling characteristics. The device shown as Fig ure 3 1B can be characterized by solving the two dimensional drift diffusion equation self consistently with Poisson equation. Due to the p type unipolar conduction of the device, the electron conduction is neglected [ 52 ] . The Poisson equation is expressed as follows, , ( 3 1)

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34 w here p is the hole density, V is the voltage r 0 are the relative dielectric constant and vacuum permittivity, respectively. The drift diffusion equation and continuity equation are as follows, , ( 3 2) ( 3 3) where J p p is the hole mobility, D p is the hole diffusion coefficient, respectively. The recombination rate is set to zero. What should be noted here is G T , which account for tunneling induced carrier and will be discuss ed in detail a s follows. To capture the details of tunneling current and thermionic current, we use the m eshing method shown as Fig ure 3 2A to g et the transport path. It should be noticed that each tunneling path as shown in Fig ure 3 2A can have different potential profiles if the metallic CNT is gated by a planar gate. For each tunneling path as schematically shown in Fig ure 3 2B, the tunneling current density is calculated and converted to an equivalent carrier generation rate. All t unneling paths are calculated, resulting in equivalent carrier generation rates dependent on the position in the 2D plane as shown in Fig ure 3 2A. Starting from the Landauer formula, we get for the tunneling current ( note the lower integration limit which goes only to the top of the barrier), ( 3 4) with ( 3 5)

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35 where h, , , , , , are Planck's constant, transmission coefficient for hole, hole effective mass, Boltzmann constant, temperature, Fermi level of CNT and hole quasi Fermi level in channel, respectively. T he position dependent tunneling induced carrier generation is obtained by using an approach similar to that in [ 58 ] , ( 3 6) where ,E are Richardson constant and electric field, respectively. can be got by using WKB method , ( 3 7) After the position dependent tunneling induced carrier generation for each tunneling path is obtained, we map all generation rate to the 2D grid in which E quation 3 1 to 3 3 are solved self consistently. Similarly, we can get the thermionic current by changing the in tegration interval of Equation 3 4 and setting transmission coefficient to be 1. ( 3 8 )

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36 Since the drift diffusi need to transfer thermionic current into ge neration rate and couple it to E quation 3 3 . The use of this thermionic current is to separate the tunneling component and the thermionic component from the total drain current. For example, the thermionic component of the total drain current can be written as, ( 3 9 ) where is the drain current which is got after E quation 3 1 to 3 3 self consistently solved. The Schottky barrier formed between the metallic CNT contact and the active channel is different from the conventional metal semiconductor contacts. First, due to lack of covalent bonding between the fully passivated CNT and the active layer, the density of metal induced gap states [ 59 ] , the effect of Fermi level pining is significantly reduced. Second, the work function of the CNT, which is the difference between the Fermi level and the vacuum level, can be modulated by the gate voltage due to the low quasi 1D density of states ( DOS), resulting in Schottky barrier height modulation [ 52 ] . The switching characteristics of the vertical OFET originate from the combined effect s of modulating the Schottky barrier height and the barrier width . We use the same method as proposed in [ 52 ] t o capture the behavior of CNT channel Schottky barrier modulation , in which the potential profile of the CNT source is determined by the self consistent electrostatics between the Poission equation and the equilibrium carrier statistics in the CNT with the source Fermi energy level. The density of states of metallic CNTs is taken into consideration to get the charge density and model the Schottky barrier modulation. After the barrier height as a function of applied

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37 gate voltage is obtained, we use this barr ier height as an input to set the boundary conditions for the Poisson and drift diffusion equations. For device simulation, the drift diffusion equation and current continuity equation with tunneling induced carrier generation are solved by using the Schar fetter Gummel discritization [ 60 ] self consistently with the Poisson equation using the finite volume method ( FVM). The current is computed once the self consistency is achieved. Physical Mechanisms and Performance Analysis In this section, device physics and device optimization will be presented based on the simulation results by the method described above. We first investigate barrier height modulation as shown in Fig ure 3 3A . The potential barrier for holes decreases as applied gate voltage decreases, bu t tends to saturate for further lowing gate voltage due to the screening effect of high ho le density around CNT. Fig ure 3 3B presents the valance band profile around the CNT along y axis at x=0 for different gate voltage. As we can see, both the barrier height and barrier thickness are modulated by gate voltage. The potential barrier is lower and thinner for negative gate volta ge than for positive voltage. Thus, a much larger current is expected for negative gate voltage due to the low and thin potential barrier. The important role of the barrier height modulation on the current is examined next. Fig ure 3 4A compares the Jd Vg c urve for the case with and without barrier height modulation. The case without barrier height modulation can be viewed as a type of conventional VFET which uses metal as the source contact. For both cases, the barrier height at Vg=0 is set to be 0.5eV. The difference is that one has modulated barrier height as a function of ga te voltage as shown in Fig ure 3 3A , while the other has barrier

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38 height fixed at 0.5eV. A larger on current is obtained for the case with barrier height modulation compared to that with out barrier height modulation due to lower barrier height for negative gate voltage. Furthermore, a smaller off current is also obtained due to higher barrier height for positive gate voltage. Thus, with barrier height modulation taken into consideration, both on current and sub threshold swing can be improved. It should be noted here all the Jd Vg curves after Fig ure 3 4A are with barrier height modulation. Compared to experimental results [ 53 ] , the on current magnitude is about two orders higher because t he relatively high mobility we use in the simulation. Effect of the carrier mobility will also be discussed later. Next we break the total current into the tunneling and thermionic emission components as shown in Fig ure 3 4B to elucidate their respective c ontributions to the device operation. Due to the saturating modulation of the barrier height with decreasing gate voltage the thermionic component tends to saturate, while the tunneling component becomes dominant. The latter continues to supply increasing current due to the band profile modulation in the channel region which makes the barrier thinner and thinner. The tunneling current thus dominates in the device on state. The thermionic component dominates in the sub threshold region where the increasing positive gate voltage makes a very thick and high barrier which tends to kill the tunneling component. Thermionic emission thus dominates in the device off state. Device Scaling Design Device design based on simulation capability is performed in this secti on. Fig ure 3 5 shows the device scaling for changing CNT diameter. A smaller CNT ( or bundle) diameter gets a higher on current and a better sub threshold swing as shown in Fig ure

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39 3 5A. This phenomenon can be explained by Fig ure 3 5B which shows the modulat ed barrier height as a function of gate voltage for each CNT diameter shown in Fig ure 3 5A. The Schottky barrier for device with large CNT diameter is inertia to be tuned due to the large density of states caused by smaller subband spacings and self electr ostatic screening caused by a larger CNT diameter . The gate oxide capacitance can be increased either by reducing the physical oxide thickness or using a high dielectric. To compare these two approaches, Fig ure 3 6A shows Jd Vg curves for oxide with diff erent permittivity but the same thickness, while Fig ure 3 6B presents Jd Vg curves for oxide with different thickness but the same permittivity. Qualitatively speaking, both increasing oxide permittivity and decreasing oxide thickness increase the capacitance between gate and channel, and the capacitance between gate and CNT. This makes the band profile in the channel and the CNT channel barrier height more controllable by the gate voltage. Thus, a preferable on current and sub threshold swing is ob tained by large oxide permittivity and small oxide thickness. To better understand the difference of the two oxide scaling methodologies as discussed above, we compare them in Fig ure 3 7. The on current is plotted as a function of the ratio between oxide relative permittivity and oxide thickness, which is defined as inverse effective gate oxide thickness, ox /t ox , by varying either the gate oxide thickness or the gate oxide dielectric constant. The on current is selected at Vg= 2.5V. As the effective gate oxide thickness decreases by either reducing the oxide thickness or using a high gate insulator, the sub threshold swing decreases and on current increases, leading to a better transistor performance. However, the performance gain

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40 achieved by using a thi nner gate oxide is not equivalently achieved by using a high gate insulator with the same effective gate insulator thickness which is defined as t eff =t ox / ox , for the vertical FET. Reducing the oxide thickness gives better improvement, which is preferred if no significant gate leakage current occurs due to carrier tunneling through thin gate oxide. The mobility of the organic active layer can vary by orders of magnitude, depending on the choice of channel material [ 46,50 ] . Fig ure 3 8 presents Jd Vg characteristics for different mobility values. The mobility has direct effect on the on current. However, the mobility draws less significant effect on the off current. This is because a very large resistance is led to by the high and thick barrier at the off state. This large resistance plays a dominant role in determining the off current. Thus, further lowering carrier mobility affects the off current slightly unless the resistance rising from mobility is much larger than the barrier resistance. In genera l, high mobility maximizes the on current, thus improves on off current ratio. Hence, large channel mobility is desired. The effect of channel length scaling on the device characteristics is explored in Fig ure 3 9 . A shorter channel length is beneficial in terms of on current because it reduces the channel resistance in the diffusive transport regime. A short channel length, however, increases the sub threshold swing at the same time, because a shorter channel leng th increases the electrostatic coupling between the drain and the organic channel close to the source , and therefore, leading to more severe electrostatic short channel effect . A careful design of the channel length, therefore, is need ed to achieve a

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41 trade off between the above threshold characteristics and the sub threshold characteristics. The spacing between each SWNT in horizontal direction is investigated in Fig ure 3 1 0. Fig ure 3 10 A shows the barrier height for different spacing ( S) as a function of g ate voltage. For the off state, barrier height modulation becomes inertia due to screening from adjacent nanotube. However, barrier height modulation does not degrade too much for on state because the large screening from channel inversion layer is dominan t. Fig ure 3 10 B shows the Jd Vg curve for different spacing. Sub threshold characteristics degrade for small spacing as expected from the barrier height for off state in Fig ure 3 10 A . Fig ure 3 10 C presents relation between Jd and CNT spacing for different gate voltage. At first, the on state current increases as the spacing the number of CNT per unit area because of the screening from adjacen t CNTs which affects Schottky barrier height and thickness. If we further decrease spacing, the on current will not increase any more or even decrease due to the large screening from adjacent nanotubes which screens the gate electric field or even make the gate lose control of channel region. Simulation result shows the largest on current happen around spacing 75nm. In general, the spacing between adjacent CNTs gives a tradeoff between on current and sub threshold swing for relatively sparse CNT network. Fo r dense network, the gate will lose control of channel, both the on current and sub threshold swing are degraded. In experiment, the average diameter of the SWNT bundles is about 5nm. In above simulations, the CNT source contact is modeled as an individual SWNT for

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42 simplicity. We also examined the effect of multiple metallic SW NTs in a bundle with a diameter of 5nm as shown in Fig ure 3 11. Here, we neglect the layout detail of multiple metallic SWNTs in a bundle and treat the bundle as a cylinder with large r density of states than single SWNT. In Fig ure 3 11 A , the qualitative behavior of barrier height modulation remains the same but the barrier height modulation becomes weaker due to a larger density of states in the source contact contributed by multiple m etallic SW NTs. For comparison, the band profiles with same applied voltage are also presented in Fig ure 3 11 B , which indicates smaller SB height lowering at the on state for a larger number of metallic SWNTs in the bundle . Summary In this chapter, the scal ing behaviors of CNT enabled vertical field effect transistors are comprehensively studied by solving two dimensional drift diffusion transport equation self consistently with Poisson equation. The operation mechanism of vertical OFET is very different to the horizontal devices. Modulation of both barrier height and band profile gives orders of magnitude variation of drain current. Tunneling current and thermio nic current are separated and studied by introducing tunneling generation term into continuity equation. The tunneling component dominates at on state, while the thermionic component dominates at off state. In order to improve the device performance, a sma ll diameter CNT and a large channel carrier mobility are helpful since the small diameter CNT makes the CNT channel barrier height more controllable due to low density of states and large carrier mobility improves on current significantly. The effect of ga te oxide is also explored, reducing the effective gate oxide thickness by either a thinner gate oxide thickness or a high gate insulator results in improvement of

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43 the transistor performance on both the on current and sub threshold swing. However, a thinn er oxide improves the performance more efficiently. Careful channel length scaling is required for vertical OFETs because short channel is desired for high on current but increases sub threshold swing simultaneously. Large CNT spacing gives better sub thre shold swing. An optimum CNT spacing gives largest on current.

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44 A B Fig ure 3 1. Device structure of CNT enabled vertical field effect transistor. A) Schematic structure of a vertical heterojunction field effect transistor. Gate, source, channel, and drain are vertically stacked up. Dilute enough, percolating carbon nanotube ( CNT) network, which forms the source electrode, allows gate electric field to pene trate into the channel region. B) Cross section of the simulated device structure . A B Fig ure 3 2. Description for taking tunneling current into consideration. A) Local mesh aro und CNT to get tr ansport path. B) Details for a certain transport path.

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4 5 A B Fig ure 3 3 . Barrier height as a function of gate bias and band profile for different gate bias. A) Hole barrier height as a function of applied gate voltage. B) Vacuum energy level shifted by ionization energy of the channel material with respect to the source Fermi level along the vertical direction y at x=0 at the on state of V g = 2 V and off state of V g = 1 V for the modeled device structure as shown in Fig ure 3 1B . This shows valence band level in the channel region ( y> 5 nm) , and the difference between shifted vacuum level and Fermi level in the source electrode ( CNT) region ( 0
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46 A B Fig ure 3 5. Scaling of CNT diameter . A) Jd Vg curves for vertical OFETs with different CNT diameters. B) Barrier height for devices with different CNT diameters as a function of applied gate voltage. A B Fig ure 3 6. Scaling of oxide . A) Jd Vg curves for different oxide permittivity with fixed oxide thickness 20nm. B ) Jd Vg curves for different oxide thickness with fixed relative oxide permittivity 4.

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47 Fig ure 3 7. Comparison of two different oxide scaling methodologies. One is to vary oxide permittivity with fixed oxide thickness. The other is to vary oxide thickness with fixed oxide permittivity. Fig ure 3 8. Effect of channel mobility . Jd Vg curves with different mobility of the active channel layer.

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48 Fig ure 3 9. Effect of channel length scaling : Jd Vg curves for different channel length .

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49 A B C Fig ure 3 10. Effect of SWNT spacing. A ) Barrier height modulation as a function of applied gate voltage fo r different SWNT spacing ( S). B ) Jd Vg curves for different SWNT spacing. C ) Plot of Jd against CNT spacing for different gate voltage.

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50 A B Fig ure 3 11 . Effect of the number of metallic SWNTs in a 5nm diameter bundle . A ) Barrier height modulation as a function of the applied gate voltage for 1, 2, and 3 metallic SWNTs in the bundle . B ) Valence band profiles plotted in the same way as Fig ure 3 3 B for bundles with different numbers of metallic SWNTs at the on state.

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51 CHAPTER 4 POROUS GRAPHENE ENHA NCED VERTICAL FIELD EFFECT TRANSISTOR In this chapter, we discuss another type of vertical field effect transistor ( VFET) , graphene based VFET ( GVFET). 3D numerical simulations are applied to obtain device operation mechanisms and further device optimizati on. Vertical field effect organic material thin film transistors has been demonstrated, in which the gate, source, channel and drain are vertically stacked [ 20,52,53 ] . A thin metal film or thin carbon nanotube film is used as source contact. There is a significant operation difference between the vertical stacked transistors and the traditional horizontal one, which is that the former is a tunneling device. Recently , g raphene based Schottky junction organic material field effect transistors were fabricated [ 61 ] . Graphene has been widely investigated for its potential applications in next generation electronic devices or new structural devices due to its unique physical properties, such as two dimensional structure, high carrier mobility and low density of states [ 21 23, 62 ] . A Schottky junction is usually formed between graphene and semiconductor materials to functionalize the devices. Experimental results presented in [ 61 ] show orders magnitude of on off current ratio improvement can be achieved by using porous graphene sheet, which allows more gate electric field penetrating into the channel region to modulate the graphene channel Schottky barrier. In addition to th e modulation of band profile in the channel region, the graphene channel Schottky barrier height can also be modulated due to the low density of states of graphene. Due to the difference of device structure and operation mechanism compared to conventional horizontal field effect transistors, device modeling

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52 and simulation is necessary for elucidating device physics and further device engineering. In this chapter , three dimensional device structure is numerically studied by solving drift diffusion equati on and Poisson equation self consistently. The Schottky barrier modulation is also taken into consideration by treating the graphene as two dimensional charge sheet. Landau er formula is then used for calculating tunneling current. Punched holes in the grap hene sheet give orders of current improvement by introducing barrier thinning and lowing just around the edge of the punched hole region. The scaling of punched hole size and the effect of hole area percentage are explored for device performance optimizati on. Due to the large difference of effective mass for the channel from material to material [ 63,64 ] , how the effective mass affects the device performance is also carried out. Modeling and Simulation Approach In order to model the graphene enhanced vertical field effect transistors which have been demonstrated in [ 61 ] , the schematic device str ucture is presented in Fig ure 4 1 A. The porous graphene sandwiched between gate oxide and organic material channel acts as the carrier source contact. The devi ce is p type unipolar conduction because the conduction band of the channel material is far away from the Dirac point of graphene [ 52,53 ] , which makes electrons not play a role in transport and only holes participate in the transport. The simulated structu re is shown in Fig ure 4 1 B . Periodic boundary condition is applied to the side surfaces. The nominal device parameters are listed as follows. The graphene sheet is a 200nm × 200nm square with a 100nm diameter punched hole. The channel length which is the thi ckness of organic semiconductor layer is 200nm. The thickness of gate oxide is 50nm. The relative

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53 ch ox =4 respectively. The source and drain applied voltage are V s =0 and V d = 2V. Three dimensional drift diffusion equation and Poisson equation are solved self consistently to characterize the device described above. Since the device is p type conduction, only holes contribute to the electrostatics and transport, the Poisson equa tion is expressed as follows, , ( 4 1) r 0 are the relative dielectric constant and vacuum permittivity, respectively, V is the voltage , q is the elementary charge and p is the hole density. The drift diffusion equation and continuity equation are listed as follows, , ( 4 2 ) ( 4 3) where J p p , D p are the hole current density, the hole mobility and the hole diffusion coefficient, respectively. It should be noted that the recombination rate is set to zero due to the relatively short channel length which makes it negligible. The graphene semicon ductor Schottky barrier is different from conventional metal semiconductor Schottky barrier due to graphene's low density of states. The barrier height between the graphene sheet and semiconductor can be easily modulated by the gate electric field [ 25 ] . To capture this property of the graphene sheet, the carrier statistics is expressed as, ( 4 4)

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54 where p and n are hole and electron density respectively, E D and E F are the Dirac point and Fermi level of graphene sheet, and are the reduced Plank's constant and the Fermi velocity of graphene. Eq. ( 4 4) assumes Fermi temperature is larger than room temperature, which is the case for the modeled devices. The Poisson equation with consideration of graphene's carrier statistics is solved by finite element method ( FEM) self consistently with drift diffusion equation and continuity equation [ 65 ] , which are solved by finite volume m ethod by using Scharfetter Gummel discre tization [ 60 ] . Once we get the band profile from above mentioned processes, the tunneling current can be obtained by the Landau er formula based on the calculated band profile, which will be further discussed in t he next section. For the tunneling current, ( 4 5) with ( 4 6) where , , , are transmission coefficient for hole, hole effective mass, Fermi level of graphene and hole quasi Fermi level in channel, respectively. can be got by using WKB method , ( 4 7) Based on the modeling and simulation methodologies described above, the performance of VGFET can be characterized. The simulated results and find ings will be presented and discussed in the next section.

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55 Physical Mechanisms for Performance Enhancement Simulations results and device optimization are discussed in this section. We start with the discussion of band profile to explore the barrier modulat ion behavior and further elucidate the operatio n mechanism of VGFET. Fig ure 4 1 C shows the valence band profile sliced in the x z plane right at the middle of y dimension scale y=100nm, which indicates the band profile modulation around the punched hole edge due to the gate electric field. The band profile of the device without punched hole is presented for comparison purpose in Fig ure 4 1 D . For comparison, the band profile at the graphene channel Schottky contact of the device without punched hole and th e device with punc hed hole is plotted in Fig ure 4 1 E . The dotted line, dashed line and solid line are corresponding to the band profile for without punched hole, away from hole edge and just at the hole edge. It should be noted that the dotted line and the dashed line are obtained by plotting the band profile of the contact along the vertical dir ection ( z direction in Fig ure 4 1 B for the device without punched hole and the region which is far away from the punched hole because the electric field at the cont act is along the z direction, while the solid line is obtained by plotting the band profile along the horizontal direction because the electric field is approximately in the horizontal direction right at the edge of the punched hole. The comparison in Fig ure 4 1 E shows negligible difference for the dotted and dashed line, while on the other hand barrier lowing and significant barrier thinning occurs right around the edge. The effect of barrier modulation around the punched hole may allow significant improv ement current injecting into the channel, which will be verified as follows. After getting the band profiles, the Landau er formula as listed in Eq. ( 4 5) is used to calculate the current for each tunneling path, which includes both the thermal -

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56 assisted tun neling current and the thermionic emission current. The tunneling path is chosen in the electrical field direction. The current density pattern at the beginning of the channel is carried out as in Fig ure 4 2. The most effective region is at the punched hol e edge, which gives orders of magnitude higher current density to boost the overall current due to thinner contact barriers as shown in Fig ure 4 1 E . Performance Optimization Design Next we examine the effect of contact hole size on the contact barrier and J V characteristi cs. Fig ure 4 3A shows the band profile comparison for the devices with different hole size, meanwhile the hole area percentage is kept as the same. For example, the device with punched hole D=100nm has a 200nm × 200nm graphene sheet , while the device with punched hole D=50nm has a 1 00nm ×1 00nm graphene sheet . Simulation results show the electric field around the hole edge is larger for the device with small punched holes compared to large punched holes because of the large curva ture for small circle. Fig ure 4 3B gives the JV characteristics for comparison. Significant current improvement can be obtained by reducing punched hole size. The reasons are listed as follows. Firstly, as mentioned above, small holes tends to get more significant barri er thinning and lowing around the hole edge due to its large curvature. Secondly, as the hole size shrinking while keeping the hole area percentage unchanged, the overall perimeter of the holes is increasing, thus leading to more effective area which is ju st around the hole edge. The effect of using monolayer versus few layer graphene source contacts is presented in Fig ure 4 4. In multiple graphene layers, each layer is modeled as an individual monolayer graphene, which corresponds to non commensurate stack ing of layers. We expect the qualitative results remain the same for Moire stacking, which

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57 keeps the Dirac band structure with a Fermi velocity renormalization. The band profiles around the same punched hole edge for the monolayer, bilayer and trilayer gra phene contacts are shown and compared as Fig ure 4 4A . Both the barrier height and barrier thickness at the punched hole edge become increasingly difficult to be modulated as the number of graphene layers increases due to stronger electrostatic screening ef fect. Thus, the on current of the device decreases as the number of graphene layers in the source contact increases as shown in Fig ure 4 4B . It is noted that the simulation assumes that the parasitic sheet resistance of the graphene layer is much smaller t han the intrinsic resistance of the device, and thereby, is neglected. Fig ure 4 5 shows the effect of the area percentage of the punched holes of the monolayer graphene source contact on the device performance. The band profiles for different hole area per centage ( HAP) but with the same hole size are shown in Fig ure 4 5A . High HAP tends to give more barrier thinning and lowing around the hole edge due to less screening from graphene. Correspondingly, the current performance can be improved by usin g high HAP as shown in Fig ure 4 5B , which is also verified by experiments [ 61 ] . The effective mass for the organic semiconductor layer can vary a lot depending on the choice of channel material [ 63,64 ] . Fig ure 4 6 presents Jd Vg characteristics for different effective mass values. We can unders tand the behavior by examining E quation 4 5 which has two components related with effective mass. One is linearly dependent on effective mass, the other is exponentia lly dependent on effective mass. At off state, the effect of linear dependence on effective mass is dominant due to the very thick Schottky barrier which kills the thermal assisted tunneling and makes the

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58 thermionic emission dominant. So, large effective m ass increases the off state current. While, at on state, the barrier thinning around the punched hole edge boosts the thermal assisted tunneling which is exponentially dependent on effective mass and makes the thermionic emission negligible. Thus, due to t he 's exponential dependence on effective mass, large effective mass decreases the on state current. In general, low effective mass improves on off current ratio and is preferred. Summary In this chapter, Poisson and drift diffusion equations are solved in a three dimensional device structure to simulate graphene enhanced vertical field effect transistors ( GVFETs). The meshing grid is prism. Equivalently it is a 2D triangular meshing grid in x y plane plus 1D non uniform grid in z direction. In order to capture the 2D characteristics of carriers in graphene, fine grid is used around graphene in z direction. On the ot her hand, coarse grid is used for regions far away from graphene semiconductor interface to save computational cost. The graphene channel Schottky barrier can be modulated by gate electric field due to graphene's low density of states. The contact barrier thinning and lowing around porous graphene edge allows orders of magnitude higher tunneling current compared to the region away from the punched hole edge, which is responsible for significant performance improvement as already verified by experiments. Sm all hole size is preferred due to its large curvature which gives large electric field around the punched hole edge, thus leading to a thinner and lower barrier. Bilayer and trilayer graphene as the source contact degrade the performance improvement becaus e stronger electrostatic screening leads to smaller contact barrier lowering and thinning. High porous area percentage improves current performance by

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59 allowing more gate electric field to modulate the graphene channel barrier. Low effective mass channel ma terial gives better on off current ratio.

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60 A B C D E Fig ure 4 1 . Device structure and band profile for graphene vertical field effect transistor. A) Device structure of graphene vertical field effect transistor. T he graphene sheet is not drawn to scale . B) The schematic structure of one unit cell ( period) of the modeled vertical graphene based field effect transistor. The nominal device dimension is listed as follows, a 50nm gate oxide, 200nm ch annel length, 200nm × 200nm graphene sheet with 100nm diameter hole region. It should be noted that the graphene sheet is not drawn to scale . C) Valence band energy profile for the nominal device in x z plane at y=100nm . D) Valence band energy profile for th e device without hole region. E ) Valence band energy profile comparison at the hole edge, away from the hole and without hole . The dotted and dashed line are along z direction, while the solid line is along x direction due to different direction of electri c field. The position 0 is positioned right at the interface of graphene and channel.

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61 Fig ure 4 2. Current density profile in the x y plane at the beginning of the channel. The effective region is around the punched hole edge. A B Fig ure 4 3. Band profile and Jd Vg characteristics for device with different hole size. A) Valence band profile comparison between different hole sizes. B) Current density Jd vs. the gate voltage Vg for the devices with different punched hole size and d evice without punched hole.

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62 A B Fig ure 4 4. Band profile and Jd Vg characteristics for device with different number of graphene layers. A) Valence band profile for monolayer, bilayer and trilayer graphene source contact with the same hole size D=100nm . B) Jd vs. Vg characteristics for monolayer, bilayer and trilayer graphene devices . A B Fig ure 4 5. Band profile and Jd Vg characteristics for device with different hole area percentage . A) Valence band profile for the devices with the same hole size D=100nm but different hole area percentage ( HAP). One is the device with a 200nm × 200nm graphene sheet and 100nm diameter punched hole, corresponding to HAP= 20%. The other is a 150 nm ×150 nm graphene sheet with 100nm diameter punched h ole, corresponding to HAP=35%. B) J d V g characteristics for devices with different HAP but the same hole size devices .

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63 Fig ure 4 6. Jd vs. Vg characteristics for the different effective mass of the channel ma terial.

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64 CHAPTER 5 PERFORMANCE ENHANCEMENT OF PHASE CHANGE MEMORY BY CARBON NANOTUBE CONTACTS Carbon nanotube (CNT) has drawn more and more attention for future application in integrated circuit community because of its high current capability, excellent thermal and mechanical properties. A number of CNT based electronic devices have been proposed and tested, such as CNT field effect transistor, CNT interconnect, CNT based solar cell and so on. Among them, CNT based nonvolatile memory is a promi sing candidate for next generation data storage devices [14,66,67 ].CNT based phase change memory has the advantages of state of the art phase change memory ,such as the potential for scaling below the size limits of flash memory [68,69 ], fast programming d ue to the discovery of fast crystallizing materials such as (GST) which can crystallize in less than 100 ns [70 ], low power consumption [7 1 73 ] and good cycling endurance [74,75 ]. CNT based molecular memory is proposed in [66 ], CNT contacted phase change memory is established and tested in [14,67 ] in order to develop nonvolatile memory with ultra low power consumption and high scalability. The electro thermal properties of CNT and phase change materials are the most important issues in CNT contacted phase change memory. Thermal conductivity, electrical thermal transport and thermal breakdown of CNT have been investigated in [76 78 ]. Carbon nanotube (CNT) contacted GST phase change memories realized in [67 ] demonstrate ultra lo w programming current in tens of µA order. Further reduction of the set/reset current to as low as 0.5 µA /5 µA is presented in [ 14 ], which is about two order s of magnitude less than state of the art PCM devices [ 79,80 ] . In [14 ], the active

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65 phase change m aterial (the gap) is sandwiched between two CNTs which act as contacts, as shown in Fig ure 5 1. In order to optimize the programming energy efficiency and current of the CNT Contacted PCM (CCPCM), it is necessary to systematically understand the temperatur e distribution with respect to the electrical and thermal properties of the applied materials and device dimensions. In this paper, a three dimensional (3D) simulation of CCPCM is performed first, then, a method for simplifying this 3D structure into 2D st ructure is developed by using the finite element method without losing accuracy. The behaviors of temperature, programming current and power with respect to the resistivity of phase change material which is dependent on doping [81,82 ], thermal boundary res istance (TBR) [83 ], CNT length, CNT diameter and gap size, are examined. Transient analysis is also carried out to investigate the behavior of temperature response to programming current by time domain finite element method. Modeling and Simulation Approac h To better understand heating and crystallization processes in CCPCM, 3D simulation by COMSOL [84 ] and by the simulator developed by ourselves is performed to couple the electrical and thermal interactions. Furthermore, a simplified 2D model agreeing well with the 3D simulation is proposed with less time consumption. The schematic device structure is as shown in Fig ure 5 1. The diameter of CNTs is 3 nm. 10nm GST amorphous film is on top of the CNT. The thickness of SiO2 is 70 nm. The total CNT length is . The gap size is 35nm. For electrical boundary settings, the applied voltage to phase change material thin film and CNTs is 3.5V, all the other boundaries are set as electrical insulation. For

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66 thermal boundary conditions, the lef t and right surface where the CNTs terminate are set as temperature boundary where the temperature change is 0; all the other thermal boundaries are set as thermal insulation boundaries. Fig ure 5 2 shows the simplified 2D structure of CNT Contacted PCM. Th e CNT and phase change material are surrounded by electrical insulator instead of GST film and SiO 2 as shown in Fig ure 5 1. The reason for doing this will be presented in next section. For this axial symmetric structure, the time dependent thermal conduct ion equation is as follows: , (5 1) where is thermal conductivity, T is temperature change, is heat generation rate and C is specific heat capacity . Time domain finite element method is applied to solve this time dependent thermal conduction equation. By using the weak formulation of Equation 5 1 in reference [85 ], the corresponding matrix form for time dependent thermal conduction equation is , ( 5 2) where is the matrix for time dependent term, and correspond to thermal conduction term and boundary condition respectively, is overlap matrix. By using backward difference method which is unconditionally stable [86 ], one can get . ( 5 3)

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67 T he matrix form of steady state thermal conduction equation is shown below by eliminating the time dependent term in Equation 5 2 , . ( 5 4) The thermal boundary conditions are set as follows. The top and bottom are set as temperature boundary which has 0 temperature change. The axis and the outmost boundary are set as thermal insulation boundaries. Thermal boundary resistance is added to th e CNT Gap, Gap Insulator, CNT Insulator interface. On the other hand, the current continuity equation is , ( 5 5) where is electrical conductivity, V is voltage. The corresponding matrix form is, . ( 5 6) where is the matrix for the left hand term in ( 5 5) , is boundary condition. The boundary conditions for current continuity equation are as follows. The bottom and the top are Dirichlet boundaries. One is set as electric ground; the other is set as applie d voltage. All the other boundaries are set as electric insulation boundaries . The temperature distribution is obtained by solving the thermal conduction equation and current continuity equation consistently . The results will be d iscussed in the next section. Simplify 3D Structure to 2D Structure The rules for mapping the 3D structure to 2D are as follows. 1) The CNT and the gap (phase change material) are surrounded by electrical insulator instead of GST film and SiO 2 . 2) The scal e of the gap doesn't change. 3) The length of CNT is shrunk by a

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68 certain ratio n without changing the total resistance. The reason for keeping the total resistance as a constant is to keep the programming current unchanged when shrinking the CNTs. For exam ple, CNT in Fig ure 5 1 with length 2.4 µm is shrunk to 2.4 µm/40 =60nm (n=40), which is comparable to the length of the gap. 4) The thermal conductivity of shrunk CNT is 1/40 of the original one to make sure the temperature at the middle point is the same. This simplified 2D structure has programming current and voltage as 1 µA and 3.5V, respectively, which is consistent with the experiment in [14 ] for the corresponding structure with CNT length 2.4 µm, gap size 35nm in Fig ure 5 1. For mapping the 3D model to 2D model, we keep all the parameters the same as 3D model including the electrical resistance and thermal resistance of the CNTs, the gap size and thermal boundary resistance, only except the length of CNT and the surrounding ma terial. Scaling down the CNT length by a factor of n is to facilitate the simulation by reducing the device size. The electrical and thermal conductivities are scaled by a factor of 1/n to keep the electrical and thermal resistance unchanged after the mapp ing. A device simulator for simulating 3D device structure is also developed by applying the mapping law discussed above. The temperature profiles are plotted in Fig ure 5 3A and B. A large fraction of heat is confined in the gap region as we can see from F ig ure 5 3 and Fig ure 5 4 . Changing the surrounding material into insulator only slightly affect the simulation results as shown in Fig ure 5 4C and D, for the temperature profile along both the axis direction and the radial direction. In addition, for elect rical transport, the current mainly flows along the CNT transport direction, and an insulator surrounding is a reasonable approximation in this case.

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69 The advantages for doing this mapping are as follows. First, the problem is reduced from three dimensiona l problem to two dimensional problem without losing physical meaning. So it is much easier to be implemented and has less computational time consumption. Second, the CNT is shrunk without affecting the temperature in gap region. So we can focus more on the gap region with much shorter CNT regions after the mapping. Comparison to State of the art PCM After applying the simulation approach for 3D and 2D devices discussed in the previous section, the simulation results of the two structures should be compared to see if the simplified 2D model is valid for producing accurate results. The validity and applications of this 2D model is presented in this section in detail as follows. Fig ure 5 4A and B show the temperature change along the axis and radial direction by using the 2D model, which agrees well with the 3D simulation result as shown in Fig ure 5 4C and D. Thus, the validity of this 2D model is verified by comparison with 3D simulation. Here, we choose 350 as the temperature for amo rphous GST being transformed into the stable hexagonal phase [87 ]. Fig ure 5 4E and F show the temperature profiles for crystalline GST as the reset current is 5µA consistent with [14 ], and the melting point is set as 632 [88 ]. Table 5 1 shows comparison of the set process performance between CCPCM and state of the art PCMs including the nanowire PCM (NWPCM) and thin film PCM (TFPCM). All the PCMs discussed are GST based. The results indicate that the CCPCM outperforms both NWPCM and TFPCM in programming current, power, and

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70 rising time. The rising time is defined as the time needed to rise up to 90% of the crystallization temperature in steady state, which is obtained by time domain FE M. Table 5 1. Performance comparison between CCPCM and the state of the art PCM including nanowire PCM (NWPCM) and thin film PCM (TFPCM). The set/reset current and set power for CCPCM, NWPCM and TFPCM are directly from experiments performed in [14], [89] and [90 ], respectively. The rising time is obtained by using time domain finite element method Set Current Reset Current Set Power Set Rising Time Contact Area Diameter CCPCM 1 µ A 5 µ A 3.5 µ W 2 ns 3nm TFPCM 0.5 mA 1mA 0.23mW 20ns 50nm NWPCM 0.22mA 0.4mA 0.39mW 22ns 60nm Transient temperature profiles as shown in Fig ure 5 are obtained by solving the time dependent thermal conduction equation with time domain FEM. It is shown CCPCM responses to programming current pulse much quicker than state of the art PCM devices, alt hough it has much smaller programming power. It is mainly due to the small size of CCPCM which has only 3 nm diameter. While the GST nanowire is 60nm thick [89 ] and the GST TFPCM [90] is based on 0.18 µm technology . The quick response can make the programmi ng time shorter if the crystallization time remains the same, which is less than 100ns. CCPCM, therefore, has the potential to lower the programming time for making faster programming PCM device. The lower energy consumption for small size device is can be achieved by small diameter because the volume of GST material needed to melt is much smaller. Small cross section of the contacts is crucial for faster operation speed and lower energy consumption which can be realized with carbon nanotube s whose diameter can be as

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71 low as about 1nm, still with excellent carrier transport properties . However, it would be difficult to get such small size PCM with other contacts, such as TiN contacts . The access device provides the read and write current for ea ch PCM cell. The access device for PCM based on 90 nm technology was able to supply 1.8mA at 1.8V [91 ]. It is required to make the access device larger for the cell with high programming current so that it can drive a larger current [68 ]. However, this sac rifices memory density and consequently increases the cost per bit. While the programming current for CCPCM is in the order of µA, thus making the corresponding access device area reduce significantly. Design Optimization Fig ure 5 6A shows the highest temp erature change behavior as a function of the resistivity of amorphous phase change material which is doping dependent [81 , 82 ]. As we can see, there is an optimum resistivity for the highest temperature change. It is because the heat generation of phase cha nge material has its maximum value when we vary its resistivity with fixed applied voltage and resistance of contact. At the optimum point, the gap resistance is equal to the contacted resistance including CNT resistance and electrode resistance. Whether s uch a small resistivity is available or not is determined by the physical property of the GST material and today's doping technology. Moreover, for the optimum resistivity, there could be a problem in differentiating amorphous state and crystalline state, because the resistance ratio between the two states is less than 2. Fig ure 5 6B is the temperature behavior with respect to thermal boundary resistance (TBR). The highest temperature change keeps going up with increasing TBR. TBR which results from the int erface of different materials plays a very important

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72 role in confining heat in phase change material. Although it is valuable to analyze the interface by ab initio method, the details at the heterogeneous interface in this case is too complex. For example, the atomistic lattice structure of the amorphous GST material and how the carbon atoms at the interface are passivated are unclear, which are beyond the scope of this study . To describe the experiment in [ 14 ], w e obtain the thermal boundary resistance fro m matching the simulation results to experiments then vary it around this nominal value to analyze the thermal behavior of CCPCMs. Here, it seems a large TBR is preferred in PCM design. However, an interface with high TBR typically reduces the electrical t ransport, thus leading to a large resistance at the interface, then increasing programming power. So, there should be a balance between heat confinement and electrical transport for the material interface in designing PCM device with good performance. To better analyze the performance dependence on gap size and CNT length. The programming power should be taken into consideration. Fig ure 7 illustrates the programming power as a function of gap size and CNT length. The reset power in Fig ure 7A varies slightl y when the gap size is in range of 20 50nm . I t is mainly because the resistance of crystalline phase change material is much smaller than that of the contacts and electrodes. With further reduction of the gap size, the reset power increases rapidly due to large r fraction of heat dissipation to the contact. In Fig ure 7A the minimum set power occurs if the resistance of phase change material is comparable to the resistance of CNT. Here, the minimum power is preferred. But the corresponding gap size may be relatively small and the corresponding reset power is large . So there is a tradeoff. Decreasing gap size means the resistance ratio between amorphous state

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73 and crystalline state is also decreasing because the resistance of CNT is fixed. Hence, this may cau se a problem in differentiating the two states. Let's discuss this case in more detail. Assume there is a critical resistance ratio (or sensitivity) for differentiating the amorphous state from the crystalline state. If the resis tance ratio is greater than , the amorphous state and crystalline state can be detected without causing any logic error. In general, we write the resistance ratio as: ( 5 7) where and are the amorphous and crystalline resistance of active region (the gap), is the total conta ct resistance including the CNT resistance and other contact resistance such as electrodes , is the resistance of access device. The access device (a MOSFET, BJT, or diode) plays an important role in a PCM cell. In order to provid e the level of RESET current required in the conventional PCM cell, the size of the access device has to be sufficiently large, which imposes challenges for scaling down the cell size. On the other hand, the RESET current of the modeled CCPCM cell is only 5 A. Due to about two order of magnitude lower current level required, the access device can be significantly narrower in CCPCM. Furthermore, alternative technologies could be conceived for the access device. For example, a natural choice for CCPCM is to use a carbon nanotube transistor as an access device. The issue of inte gration is out of the scope of this work. However, CNTFETs with an on current of about 25uA have been reported, which is larger than the required RESET current of 5uA. The exact value of the access device resistance ( in Eq. ( 5 7) is dependent on the exact access device), and a value of 100 , which is typical for a

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74 silicon nanowire or carbon nanotube transistor that delivers the required current, is used for the analysis here. So, the requirement becomes . Substitute and i nto Equation 5 7 , one can get the length of gap size as, ( 5 8) Thus, the opti mum gap size can be determined by Equation 5 8 and Fig ure 7A. Fig ure 7B shows that the set power decreases as the length of CNT decreases with a fixed gap size of 35nm. Thus, short CNT is preferred for achieving a better performance. But the CNT length dependence of programming power is not so apparently in this case. It is mainly because the r esistance of gap region is much larger than that of CNT. So the total resistance decreases slightly with decreasing CNT length. Let's consider the case of CCPCM with a very short CNT. If the CNTs are short enough to make ballistic transport possible, we c an still get a large enough with a sm aller gap size by referring to Equation 5 8 due to the small resistance of two contacted CNTs. Fig ure 8 shows the minimum gap size determined by Equation 5 8 as a function of GST resistivity w ith different electrode resistance. Here, we assume =10 is enough to distinguish the amorphous state from crystalline state and the resistivity of crystalline GST is three orders lower than amorphous GST. Furthermore, another adva ntage for short CNTs is much smaller programming power due to decrease of total resistance. Here, we propose a CCPCM with 60nm CNTs and 15nm gap without changing other parameters. The simulation results show that the set/reset power is reduced from 3.5 µW /1 4.6 µW to 1.9 µW /6.9 µW . The set/reset

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75 power is improved by 45% /52 % compared to the one with 2.4 µm long CNTs and 35nm gap. The dependence of the programming power on the CNT diameter is examined next as shown in Fig ure 9 . As the CNT diameter decreases, th e volume of the active GST region decreases, which results in a smaller set/reset power even as low as 1 µW /1 . 5 µW . Summary In summary, CCPCM shows good potential for future technology with about two orders lower of programming current and power compared with state of the art PCMs. A valid 2D model mapped from 3D structure for CCPCM is proposed and applied to investigate device performance with respect to resistivity of phase change material, thermal boundary resistance (TBR), CNT length and gap size. The transient analysis shows CCPCM has faster response time to programming current pulse to rise to the crystallization temperatu re. There is an optimum design for the resistivity, however the availability of this optimum resistivity is determined by the physical property of GST, doping technology and detection. Moreover, the interface property which is related to the heat confineme nt (TBR) and electrical transport (resistance) is also discussed. A critical gap length is carried out by considering detecting sensitivity. So an optimum gap size can be determined by the balance between optimum power effect and detection. Shorter CNT can offer lower programming power in CCPCM. Scaling analysis is also performed , which shows set/reset power as low as 1 µW /1 . 5 µW with 1nm CNT diameter .

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76 Figure 5 1. Cross Schematic 3D structure of CNT contacted phase change memory, which has been fabr icated in [14 ]. Amorphous GST film is sputtered on top of the gapped CNT which is created by electrical breakdown in advance. Here, the active region (the gap) is marked with green color . Figure 5 2. Simplified 2D structure for simulating the 3D device as shown in Fig ure 1 without losing accuracy .

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77 A B Figure 5 3. Temperature profile for CNT PCM. A) Temperature profile in x y plane cutting in the middle of nanotube. B) Temperature profile in x z plane cutting at the middle of the gap region .

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78 A B C D E F Figure 5 4. Temperature profiles along a certain direction. Comparison between A),B) the simplified 2D model and C ) ,D) the 3D model for temperature as a function of position. A) and C) are the temperature along axis direction . It should be noted that C is a zoom in picture, only shows the temperature near the gap. It is just because CNT length is 2.4 µm which is much large r than the gap size. The reference temperature is the same for both cases. B) and D ) are temperature in radial direction at the middle of the gap. Applied voltage and programming current are 3.5V, 1µA respectively, which is consistent with the experiment performed in [14 ] for CCPCM with 35 nm gap, 2.4 µm CNT length. The TBR is set as . The total resistance of CNT is . The resistivity of amorphous GST material corresponding to threshold voltage is set as . The resistance of contact is set as . Thermal conductivity of CNT is . E) and F ) are temperature profiles for the reset process. The reset current is 5 µA , the resistance is 0.5 , and both are consistent with the experiments in [14 ]. The resistivity of crystalline GST material is .

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79 Figure 5 5 . Transient set process temperature profiles of carbon nanotube contacted PCM (CCPCM), nanowire PCM (NWPCM) an d thin film CPM (TFPCM) . A B Figure 5 6 . The highest temperature change as a function of the resistivity of amorphous phase change material A) and the thermal boundary resistance B) with applied voltage 3.5V. The resistance of contact is set as , thermal conductivity of CNT is for both cases. For A) , the total resistance of the 2.4 µm long CNT contact is . It is assumed that the resi stance of CNT is linearly dependent on CNT length. The TBR is set as . For B) , the resistivity of amorphous GST material is set as .

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80 A B Figure 5 7 . Programming power as a function of gap size and CNT length. A ) Set and reset programming power as a function of the gap size , B ) set programming power as a function of CNT length with the same crystallization temperature 350 . For A ), the TBR is set as . For B ), the corresponding TBR from bottom to top is 25 , 35 , 45 ( ), the gap size is fixed at 35nm. Figure 5 8. Minimum gap size determined by Equation 5 8 as a function of GST resistivity with different electrode resistance. Ballistic transport is available for two contacted CNTs, the total resistance of CNTs is . Re is the resistance of electrodes. is set as 100 . The extreme case with 0 electrode resistance is also presented.

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81 Figure 5 9. Set /Reset power as a function of the CNT diameter. The corresponding TBR is 35 . The length of the CNTs is 2.4 µm . The gap size is 35nm .

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82 CHAPTER 6 MODELING AND SIMULATION OF HIGH GAIN PERMEABLE BASE TRANSISTOR S In this chapter, permeable metal base transistors ( PBTs) fabricated with low cost solution process but with excellent current saturation and high gain will be modeled and simulated. Reasons for current saturation and high gain are revealed based on simulation results. Intrinsic delay is also investigated and optimized for high frequency applications. Permeable base transistor ( PBT) was pro posed more than 30 years ago [ 92 ] , which was fabricated by sandwiching metal base grid between emitter semiconductor layer and collector semiconductor layer. PBTs based on inorganic semiconductor can be operated at tens of or hundreds of GHz [ 93 ] due to it s short channel and PBTs which are based on either organic semiconductor or inorganic semiconductor materials [ 94 97 ] because of their advantages of low cost fabrication a nd great potential for high frequency applications. Although high output current density and high frequency operation for PBTs were reported [ 98,99 ] , to design and fabricate PBTs with both high current gain and good current saturation behavior was a signif icant challenge. Recently, using porous metal base grids by deposition of thin metal film instead of fabricating metal base grids by photolithography has been demonstrated [ 100 ] . High density pores in scale of tens of nanometers in metal base are introduce d. With this porous metal base, PBT with high current gain around 500 and excellent current saturation behavior has been achieved and demonstrated [ 101 ] . As will be pointed out later, the potential pinning effect in base emitter interface due to the small pore size is responsible for current saturation; and the thin oxide layer wrapping around aluminum

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83 base which is formed during annealing process degrades base current significantly and gives high current gain. After the d emonstration of PBTs with high current gain and excellent current saturation which are fabricated by low cost solution process without photolithography, questions about frequency performance will be raised subsequently. What factors affect frequency perfor mance of PBT? How to improve its frequency performance and how high the frequency can be? The answers to these questions need detailed device modeling and simulation to reveal the physics behind it. In this chapter, detailed modeling and simulation will be presented to elucidate operation mechanism and frequency performance analysis of PBTs. T hree dimensional finite element method is used to solve Poisson equation and drift diffusion equations self consistently to carry out simulation . Carrier behavior s are investigated to get intrinsic delay of PBT. Optimization of intrinsic delay is also performed with respect to device scaling, emitter barrier height and carrier mobility. Mechanisms for Excellent Saturation and High Gain The cross section of experiment al device s tructure is shown in Fig ure 6 1 with porous aluminum ( Al) acting as the base of transistor. The schematic device structure for device modeling is shown in Fig ure 6 2A . Periodic boundary condition is satisfied for all the lateral surfaces. Thus, Fig ure 6 2A is essentially a unit cell in the x y plane for the whole device. The emitter and collector region are with thickness of 60nm and 500nm, respectively. The base aluminum thin layer is 10nm thick and with 3nm aluminum oxide all around. The dimens ion in the x y plane of unit cell in Fig ure 6 2A is 40nm×40nm. The pore is modeled as a square with nominal size 20nm×20nm. So, the porous area percentage is 25%.

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84 The permeable base transistor reported in this paper is n type unipolar conduction device because the valence band of the emitter and collector is far away from work function of emitter or collector contact, which results in much less hole density compared with electron density and makes holes not play a role in current transport. Three dimensi onal Poisson equation and drift diffusion equation are solved self consistently by finite element method and finite volume method in the same meshing grid to characterize the device performance. Since only electrons play a role in determining device perfor mance, the Poisson equation is listed as follows, , ( 6 1) r 0 are the relative dielectric constant and vacuum permittivity, respec tively. V is the voltage, q is the elementary charge and n is the electron density. The drift diffusion equation and current continuity equation are shown as follows, , ( 6 2) , ( 6 3) where J n n , and D n are the electron current density, the electron mobility and the electron diffusion coefficient, respectively. Since the thickness of emitter and collector is relatively thin, recombination rate is negligible and set as zero. Boundary conditions for Poisso n equation at the emitter contact, base contact and collector contact are Dirichlet boundary. Periodic boundary conditions are assumed for all the other boundaries for Poisson equation in the lateral direction. Boundary conditions for drift diffusion equat ion at emitter contact and collector contact are

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85 Dirichlet boundary. The base contact is excluded from drift diffusion transport due to aluminum oxide around. Equivalently, the current in z direction at oxide channel interface is set as zero. Periodic boun dary conditions are used for all the other boundaries of the drift diffusion equation. To understand the detail ed device physics, three dimensional ( 3D) device simulation is performed to determine the effect of pore size on current tra nsport in our devices . Fig ure 6 2A illustrates the schematic diagram of the modeled device structure which shows the base region is surrounded by an insulator layer of aluminum oxide. A periodic boundary condition is used in the horizontal directions so that a periodic array o f pores is simulated. Details of the device simulation are provided in th e Supplementary Section. Fig ure 6 2B and 6 2C are the potential profiles in the x z plane cutting through the center of the 20 nm × 20 nm pore in a 40 nm × 40 nm base and the center o f the 200 nm × 200 nm pore in a 400 nm × 400 nm base. Note that the percentage of pores is the same for both cases. The potential around the pores is more sensitive to the changes in the collector bias for a large pore device ( LPD) compared to a small pore device ( SPD). Fig ure 6 2D shows the potential profiles of the two devices through the center of the pore along z direction for different collector bias voltages with a fixed base voltage. For SPD, the potential in the pore region is more sensitive to the base bias. At high collect or biases, the potential at the base is pinned by the base bias regardless of the collector bias. Hence, the electric field in the emitter region i s also pinned as shown in Fig ure 6 2D , and the emitter current is constant regardless of the collector bias, leading to collector current saturation. On the other hand, there is no potential pinning at the base for LPD, resulting in no current saturation. Fig ure 6 2E

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86 demonstrates the potential energy at the center of the pore region as a function of a collector b ias for different pore sizes. As the pore size decreases from 200 nm to 10 nm, the potential pinning effect at the center of the pore region becomes more prominent. Fig ure 6 2F shows the collector current against the collector bias for the devices under th e common emitter con f ig uration. A device with SPD shows a strong current saturation as expected from Fig ure 6 2E . The results of our simulation are consistent with our device data that the collector current saturation is due to the potential pinning effect in the pore area due to the small pore size. Hence, the pore size is critical for ac hieving current saturation in P BTs. In the above simulation, the base current is set to zero due to the thin oxide layer around base contact. However, electrons can tunnel through thin oxide layer, and hence base current still exists. After simulation procedures discussed above, we can get potential profile after the Poisson equation and drift diffusion equation are self consistently solved. The base current can be calculat ed according to the potential profile. The schematic potential profile around base contact has been shown in Fig ure 6 3A . The base to emitter tunneling current can be obtained by Landauer formula, , ( 6 4) where , ( 6 5) and . ( 6 6)

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87 Similarly, the base to collector tunneling current can be written as, , ( 6 7) where is transmission coefficient through oxide barrier and obtained by WKB method, , and are quasi Fermi level at emitter oxide interface, quasi Fermi level at collector oxide interface and base Fermi level, respectively. t ox is oxide thickness. m c is electron effective mass. The base current is computed as follows, . ( 6 8) The simulated base current is shown in Fig ure 6 3B . Base current is significantly degraded due to the oxide layer around base contact, which makes high current gain possible. Intrinsic Delay of Permeable Base Transistor In this section, frequency performance of PBTs will be discussed. Fig ure 6 4 shows the modeled device structure with nominal device dimensions , which is slightly different from last section . The pores in the base region are modeled as uniform array for simplicity. The nominal device dimensions are listed as follows. Emitter, base and collector thickness are L e =60nm, L b =10nm and L c =400nm, respectively. The thickness of base oxide layer is 3nm. By using the same simulation methodology as last section, three dimensional Poisson equation and drift diffusion equation are solved self consistently by finite element method ( FEM). After the simulation gets converged, we can get the intrinsic delay for emitter t e , base t b and collector t c , respectively, , ( 6 9 )

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88 , ( 6 10 ) , ( 6 11 ) where and are the emitter charge for off state and on state. is the saturated current magnitude for on state. Since the device drives current by depleting electron carriers in the channel which will be detailed explained later , the charge at off state is greater than that of the on state and is a positive number. We add each delay component to get the total intrinsic delay as, , ( 6 12 ) which determines up limit for frequency performance of the transistor. I V charact eristics are presented in Fig ure 6 5A and Fig ure 6 5B . Fig ure 6 5A is collector current as a function of base bias for different collector bias. At low base bias, collector current increases exponentially as base bias increases because the carrier density in base region is modulated by base voltage and shows exponential dependence. However, at high base bias, the current behavior deviates from exponential dependence on V b . It is because the increasing carrier density in base region gives significant screening to base bias. Fig ure 6 5B gives collector current as a function of collector bias for different base bias. The current curve shows decent saturation behavior similar as experiments [101] . The potential profile and quasi Fermi level through the center of the device along vertical direction for different collecto r volta ge is presented in Fig ure 6 5C, which is similar to Fig ure 6 2D . The potential and electric field in emitter region is pinned regardless of collector voltage if V c is greater

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89 than a critical value V c,sat . This potential pinning effect is responsible for cu rrent saturation as discussed earlier . Fig ure 6 5D is the corresponding electron density. At off state ( V c =0V), the quasi Fermi level is flat and the corresponding self consistent calculation gives largest carrier density in the device, especially around b ase region. As the collector voltage increases, the channel keeps depleting carriers. Therefore, electron density in emitter, base and collector at off state is higher than that of on state. Fig ure 6 6A gives carriers in emitter, base, collector and the w hole device as collector bias varies at fixed V b =0.5V. The carriers in emitter cannot be depleted anymore until the current gets saturated due to potential pinning in the emitter region. But the carriers in base and collector keeps being depleted since the quasi Fermi level operation mechanism is quite different from conventional BJTs or MOSFETs. Fig ure 6 6B is carriers in emitter, base, collector and the whole device as a funct ion of base bias at fixed V c =1V. Base carriers increase exponentially as base bias increases at low base bias, and then deviates from exponential behavior at high base bias due to carrier screening as expected above. Emitter carriers show weaker dependence on base bias because only the emitter region close to base can be affected by base bias. Collector carriers have even weaker dependence on base bias because most of the carriers in collector are located far from base for V c =1V as shown in Fig ure 6 5D . Intrinsic Delay Optimization Design Once we get the carrier density for off state and on state respectively, we can obtain the intrinsic delay t e , t b , t c and t tot by using Equation 6 9 to 6 12 . It should be

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90 noted that all the parameters for on state in E qu ation 6 9 to 6 12 such as , are chosen to be at collector voltage V c =1V. The intrinsic delay vs. emitter thickness scaling is plotted in Fig ure 6 7A . As emitter thickness increases, all the delay components are increasing linearly. It is because of that electric field in emitter decreases as emitter thickness increases. Given this low electric field, the saturation current for the device with thicker emitter is lower than that with thinner emitter. H ence, more time is needed to deplete the carriers in channel for device with thicker emitter. In general, thin emitter length is preferred for lower intrinsic delay. Fig ure 6 7B illustrates intrinsic delay as a function of base thickness. Since the pore size, porosity and emitter thickness are all fixed when changing base thickness, electric field in emitter region keeps the same, and hence keeps the same. The emitter charge and co llector charge are also independent of base thickness. Therefore, as base thickness increases, the delay components t e and t c do not vary. On the other hand, the electron density peak for off state is sitting in ba se region as shown in Fig ure 6 5D . The tot al charge in base region is increasing with increasing base thickness, while the on current is independent of base thickness as discussed above. Therefore, delay component t b increases as base thickness increases. Thin base can improve frequency performanc e of the device. However, currently, when fabricating the base for PBT, porosity and pore size are highly dependent on base thickness as shown by experiments , consequently these combined effects affect on current and carrier distribution. So, careful desig n is needed for base thickness.

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91 Intrinsic delay with respect to collector thickness scaling is also investigated . From Fig ure 6 5D , we can see electrons for off state in collector region are mainly crowded around base collector interface. The off state electron density around base collector interface is independent of collector thickness unless the collector is very thin and collector electric field penetrates into pore and emitter, under which condition base will lose control of the pore emitter interfa ce and degrade current saturation. Thus, we use relatively thick collector in the simulation to prevent the device from getting bad current saturation. Under this condition, carrier density in collector is independent of collector thickness, collector scal ing gives no effect on intrinsic delay. Fig ure 6 8 shows intrinsic delay with respect to emitter barrier height. Schottky barrier is formed between emitter contact and emitter semiconductor . Experiments show different emitter contacts result in different o n current [101] . Low emitter emitter contact barrier allows carrier injection from emitter contact to emitter more easily and gives large on current. Since the on current increases as emitter barrier height decreases, intrinsic delay decreases with decreas ing emitter barrier height as shown in Fig ure 6 8 . From the simulation results we discussed above, thin emitter, thin base and low emitter barrier height are preferred for better frequency performance. Here, we use L e =10nm, L b =10nm, and emitter barrier hei ght 0.3eV to explore the intrinsic delay variation with respect to mobility scaling. The results are plotted in Fig ure 6 9 . Intrinsic delay decreases as electron mobility increases due to large on current for high electron mobility. Intrinsic delay in sub nano second with electron mobility 10cm 2 /V/s is achievable if we carefully engineer emitter thickness, base thickness and emitter barrier

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92 height. Solution processed IGZO with mobility greater than 30 cm2/V/s is reported [ 102 ], thus providing bright future for GHz PBT with low cost process. Summary It has been demonstrated recently that excellent current saturation and large current gain can be achieved in solution processed permeable base transistors ( PBTs). Potential pinning due to small pore size is resp onsible for excellent current saturation. Aluminum oxide around Al base only allows carrier to tunnel through, thus leading to small base current and high gain. Intrinsic delay of PBTs, which characterizes the speed of the transistor, is investigated by so lving three dimensional Poisson equation and drift diffusion equation self consistently using finite element method. Decreasing the Emitter thickness lowers the intrinsic delay by improving on current, and a thinner base is also preferred for low intrinsic delay because of fewer carriers in the base region at off state. The intrinsic delay exponentially decreases as the emitter contact Schottky barrier height decreases, and it linearly depends on the carrier mobility. A sub nano second intrinsic delay can b e achieved with a carrier mobility of ~10cm 2 /V/s, which indicates the potential of solution processed PBTs for GHz operations.

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93 Fig ure 6 1. Cross section of experimental device structure according to [101 ] .

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94 A B C D E F Fig ure 6 2 . Device structure, simulated band profile and simulated JV characteristics. A ) Simulated device structure. Square shaped pore and 3nm thick oxide around base are assumed. More details are in the supplementary section. B ) Conduction band profile of X Z plane cutting at the middle of y axis for 20nm×20nm pore in 40nm×40nm base and C ) 200nm×200nm pore in 400nm×400nm base . V E , V B , and V C are fixed at 0V, 0.5V, and 1V respectively for both cases. D ) Conduction band contours from the emitter to the collector through the center of the pore. V E and V B are kept constant as 0V and 0.5V respectively. V C is varied from 0V to 2V in 1V step. The potential for 20nm sized pore is pinned when V CE > 1V. E ) Condu ction band energy at the center of the pore region with different pore size between 10nm and 200nm. V E and V B are kept constant as 0V and 0.5V respectively. F ) Common emitter characteristic of simulated device. V E and V B are kept constant as 0V and 0.5V re spectively .

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95 A B Fig ure 6 3. Description for base current calculation. A) Schematic potential profile around Al base for calculating the base tunneling current. Oxide thickness is 3nm. B) Base current as a function of base voltage . Fig ure 6 4 . Modeled permeable base transistor schematic with uniform pore array. The device is with nominal emitter thickness L e =60nm, collector thickness L c =400nm, Al base thickness L b =10nm. It should be noted that a 3nm aluminum oxide layer is wrapping all around base. The unit cell for the device is 40nm×40nm in horizontal plane with a 20nm×20nm square pore .

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96 A B C D Fig ure 6 5 . IV characteristics and band profiles. A) Collector current as a function of V b for different V c . B) Collector current as a function of V c for different V b . C) Potential profile and quasi Fermi level F n through the center of the device along z direction for different V c . D) Electron density through the center of the de vice along z direction for different V c .

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97 A B Fig ure 6 6 . Charge in base, collector and emitter as a function of bias. A) Emitter, base, collector and total charge as a function of V c . All the results are with mobility 5cm 2 /V/s, V e =0V and V b =0.5V. B) Emitter, base, collector and total charge as a function of V b . All the results are with mobility 5cm 2 /V/s, V e =0V and V c =1V . A B Fig ure 6 7. Intrinsic delay as a function of emitter thickness and base thickness. A) Intrinsic delay for collector ( t c ), emitter ( t e ), base ( t b ) and the whole device t tot as a function of emitter thickness L e with L c =400nm, L b =10nm, mobility 5cm 2 /V/s, V e =0V, V b =0.5V and V c =1V. B)Intrinsic delay for collector ( t c ), emitter ( t e ), base ( t b ) and the whole device t tot as a function of base thickness L b with L c =400nm, L e =60nm, mobility 5cm 2 /V/s, V e =0V, V b =0.5V and V c =1V.

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98 Fig ure 6 8. Intrinsic delay for collector ( t c ), emitter ( t e ), base ( t b ) and the whole device t tot as a function of emitter barrier height with L e =60nm, L b =10nm, L c =400nm, mobility 5cm 2 /V/s, V e =0V, V b =0.5V and V c =1V. Fig ure 6 9. Intrinsic delay for collector ( t c ), emitter ( t e ), base ( t b ) and the whole device t tot as a function of ca rrier mobility with L e =10nm, L b =10nm and L c =400nm, e mitter barrier height 0.3eV .

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99 CHAPTER 7 ELECTRONIC CHARACTERISTICS OF ATOMICALLY THIN VERTICAL P N JUNCTION In this chapter, atomically thin vertical p n junction based on two dimensional transition metal dichalcogenide ( TMD) material , MoS 2 and W S e 2 , is modeled and studied . The recombination mechanisms between two monolayers are critical in determining I V characteristics of devices, which are detailed investigated. Graphene sandwiched TMD p n junctio ns are also modeled and discussed. Bulk TMD materials are formed by vertically stacking mono layers with weak bonds by van der Waals ( vdW) interactions between adjacent layers [26,27] . Recently, emerging two dimensional materials from transition metal dichalcogenide ( TMD) family are used to build fundamental electronic devices, such as field effect transistors, p n junctions [ 28 30 ] . These materials have great potential for future electronic applications due to excellent electrical properties [ 26 31 ] . F urthermore, the lack of dangling bonds on the surfaces of TMD materials makes high quality heterointerfaces possible [ 103 ] . Monolayer TMDs have various band gaps and work functions which provide sufficient choices for band gap engineering of heterostructur es [ 104 ] . The carrier density in monolayer TMDs can be tuned electro statically [ 105,106 ] , which makes devices with non traditional characteristics and gives more possibilities for future technology. Atomically thin MoS 2 WSe 2 p n junctions have be en demonstrated [ 107 ] . The schematic device structure is shown in Fig ure 7 1A. Monolayer MoS 2 and monolayer WSe 2 are vertically stacked. Measured I V characteristics for various gate voltage present significant gate voltage dependence [107] . Graphene sandwic hed vdW p n heterojunctions are also fabricated and measured, whose IV characteristics show strong

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100 layer number dependence [107] . The schematic device structure is shown in Fig ure 7 1 B [ 107 ] . To understand the physics behind monolayer TMD based devices , device modeling and simulation is a must. Modeling and Simulation of Monolayer p n Junction Fig ure 7 2 shows a schematic structure of the simulated device where thicknesses of t he gate oxide and metal electrodes are 280 nm and 200 nm , respectively . The spacing between source and drain electrodes is 9 m and the length of the MoS 2 / WSe 2 junction is L j = 3 m, closely following the device dimension in [107]. The interlayer spacing between WSe 2 and MoS 2 is 7 Å, assuming the vdW distance between the layers. The width of the device ( in the out of plane direction ) is W = S j /L j 2.93 m, where S j 8.8 m 2 is the junction area of the experimental device. Since the p n junction in horizontal direction is in the or der of µm which is large compared to vertical direction in scale of several angstrom, a scaling factor of 1/S F is used in the horizontal transport direction, as discussed and validated later, for computational efficiency. Poisson equation and drift diffusi on equation are solved self consistently by a 2D finite difference method to investigate device operation mechanisms. Poisson equation is listed as follows , , ( 7 1) The drift diffusion equation and current continuity equation are shown as follows , , ( 7 2)

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101 , ( 7 3) , ( 7 4) , ( 7 5) where J n n , D n are the electron current density, the electron mobility and the electron diffusion coefficient, respectively. J p p , D p are corresponding to hole. G n and G p are electron and hole generation rate by optical illumination. G n and G p become zero in the dark . R n and R p are electron and hole recombination rate, which plays an important role in determining the photocurrent as well as the dark current . Fig ure 7 3 is band profiles in the lateral and the vertical directions at a forward bias of 0.6 V , which indicates that most of the applied voltage is across the vertical p n junction . T he forward bias current is completely governed by interlayer recombination between majority carriers of two monolayers ( electrons of MoS 2 and holes of WSe 2 ). Since the r ecombination process is significantly important for determining current behavior, it is detailed modeled as follows . Considering possible presence of trap states and low photoluminescence ( PL) quantum yield of semiconducting TMD s [ 108 ] , intralayer recombin ation may be dominated by the Shockley Real Hall ( SRH) recombination mechanism [ 109,110 ] , ( 7 6) where n 0 and p 0 are electron and hole density at equilibrium condition. is intralayer carrier lifetime. Meanwhile, interlayer recombination can be described by trap assisted

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102 SRH recombination or Coulomb interacting Langevin recombination proces ses [ 111 ] , equations for two recombination mechanisms are expressed as follows, ( 7 7) ( 7 8) where is int er layer tunneling life time and B is Langevin recombination constant. It should be noted that drift diffusion equations and current continuity equation s are solved in two individual monolayers ( horizontal direction) and their overlapped region ( vertical direction). In the horizontal direction, we use mobility the same as single layer material before the junction is formed. In the vertical direction, a lth ough interlayer transport is dominated by quantum tunnel ing , we use d a phenomenological interlayer carrier mobility µ inter to describe the interlayer carrier transport between MoS 2 and WSe 2 mono layer s , ( 7 9) where a is spacing between MoS 2 and WSe 2 , V is voltage drop between two monolayer materials, and is the tunneling time between two layers . The value of V can be approximately set as the difference between the conduction ( valence) band edge of MoS 2 and valence band of WSe 2 divided by elementary charge for electron ( hole) transport. Numerical calculation shows that the value varies about 10 % i n the bias range of interest. Note that phenomenological mobility used in our simulation results in faster interlayer charge transfer rate than intr a layer recombination rate as expected from experimental observation of strong PL quenching in the MoS 2 /WSe 2 heterojunction .

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103 Because the large aspect ratio between the lateral size and the vertical interlayer distance, numerical challenges need to be taken care of in the simulation. We developed and validated a scaling method, which scales down the dimension in the transport direction by a scaling factor of 1/S F to reduce computational cost. The intralayer mobility in the horizontal direction is scaled down by factor 1/S F to maintain same parasitic resistance. The recombination and generation rates are scaled up by factor S F to maintain same current per unit width. The phenomenological interlayer mobility is scaled up by a factor of S F . We have numerically tested that the physical quantities of interest, including the dark and photoresponse I V characteristics of the junction and the charge density in the junction region, are insensitive to the scaling factor if S F 30. The electrostatic screening length in the horizontal direction is considerably shorter than 100 nm due to atomic thickness of WSe 2 and MoS 2 . To further speed up simulation, a non uniform numerical grid is used in the vertical direction for the numerical solution of Poisson equation. Device Physics of Monolayer p n Junction Fig ure 7 4 presents band diagrams in the lateral dire ction under reverse, zero, forward source drain biases at V g = 0 V , respectively. At a reverse bias, holes in p doped WSe 2 and electrons in n doped MoS 2 are depleted, and the quasi Fermi level of MoS 2 in the non overlapped region is close to the conduction band edge, and that of WSe 2 is close to the valence band edge. Depletion in the junction region and quasi Fermi level splitting at the reverse bias results in large band bending between overlapped region and non overlapped region in the horizontal directio n. On the other hand, at a forward bias, both holes in p doped WSe 2 and electrons in n doped MoS 2 are accumulated.

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104 Therefore, b and bending in the lateral direction is small as shown in middle panel of Fig ure 7 4 . In a conventional bulk p n junction, the fo rward bias current is determined by recombination followed by diffusion of majority carriers over electrical potential barrier s across the depletion region, resulting in an exponential I V characteristic . In contrast, due to lack of the depletion region, c harge transport in an atomically thin junction is governed dominantly by interlayer recombination processes between two majority carriers accumulated in each layer , and thus I V curves do not show an exponential characteristic even for an ideal junction. We examined two recombination mechanisms described above in our model simulation. Fig ure 7 5 shows comparison of experimental and theoretical dark I V curves at V g =0 V . Both SRH and Langevin show good agreements with experimental data. For quantitative mat ching, we estimated the interlayer tunneling life time ( ) of 40 µ s and Langevin recombination constant ( B) of 1.67 × 10 13 m 2 /s. Unlike an ideal case in simulation , i n real device s , parasitic resistance s are likely to exist in both metal ( Pd) WSe 2 and metal ( Al) MoS 2 contacts, as well as lateral charge transport in WSe 2 and MoS 2 layers . We indeed found that the simulated I V characteristics is sensitive to the parasitic resistance, which can reduce the splitt ing of quasi Fermi energy levels of majority carriers in the overlapp ed junction region and thereby results in lower majority carrier densities. For example , current decreases especially at large biases when we include the Schottky barrier of 0.3 eV at the Pd WSe 2 junction. Consequently, we estimate d smaller tunnelling lifetime ( ~microsecond time scale ( > 1µ s)) and larger Langevin recombination constant ( ~2.0 × 10 10 m 2 /s), in

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105 order to obtain the forward bias current measured in our device. Although it is very difficult to get a quantitative number precisely, it should be noted that the microsecond time sale estimated here is much longer than those of any other competing processes including intralayer radiative ( or nonradiative) recombination rates. This interlayer tunneling recombination also plays a dominant role in determining the photocurrent as in Fig ure 7 6 . Fig ure 7 6 A shows plots of the simulated densities of majority and minority carriers in each layer as a function of gate voltages ( top panel ). Th e interlayer recombination would be directly proportional to n M × p W ( middle panel in Fig ure 7 6 A and/ or n M × p W / ( n M + p W ) ( bottom panel in Fig ure 7 6 A ), depending on the dominant recombination mechanism follows the Langevin type and/or SRH type, respectively . These quantities spatially averaged over the junction area become a minimum around V g = 0V , and increase as sweeping the gate voltage to either positive or negative due to accumulation of one of majo rity carriers . This leads to the consistent bell shaped behavior of photocurrent observed in experiments [ 107 ] , as shown in Fig ure 7 6 B . Note that both Langevin and SRH mechanisms are reasonable to qualitatively explain the experimental data, Langevin type shows the excellent quantitative agreement with the recombination constant ( B) of ~2.0 × 10 10 m 2 /s, as shown in Fig ure 7 6 B . Graphene Sandwiched p n Junction s The photo response I V characteristics of vertical ly graphene contacted p n junctions in [107] are mode led by a simple circuit model as shown in Fig ure 7 7 A . R s and R t are series resistance and the tunnelling resistance between two graphene contacts , respectively . I 0 is current source related to light generated current. Despite

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106 simplicity of the model, it explains the qualitative features of the I V characteristics depending on the number of layers as shown in Figure 7 7B. The shunt resistance is due to tunneling between two graphene contacts separated by the semiconducting junct ion layers. Since tunnelling current is exponentially dependent on tunnelling distance, the shunt resistance exponentially depends on the number of layers as shown below, , ( 7 10) where N is number of layers. By carefully choosing parameters, we can get the simulation results with quantitative agreement to experimental measurement as [107] . The parameters used are and , where I N is a normalization current. The diode has an I V characteristic same as the multilayer p n junction without light illumination, but with a normalization unit that results in I ( at V = 0.7 V) / I N 80. Piecewise function is used to fit the dark I V characteristics. The simple model captures the qualitative features of the nearly linear I V characteristics of the monolayer junction, the increase of the open circuit voltage and the transition to the diode like I V with increasing the number of layers . Summary Atomically thin TMD vertical p n junction operates in a way significantly different from traditional ones. Detailed modeling and simulation approach are carried out to study and characterize the device, trying to re veal physics behind. The p n junction also exhibits rectifying electrical characteristics, which is mainly because of interlayer recombination between majority carriers of two mono layers. The recombination can be SRH or Langevin, both can be tuned by gate electric field and lead to a bell shape

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107 photocurrent. Graphene sandwiched vertical junction is modeled by lumped element circuit, which provides good agreement with experiments although the model is relatively simple.

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108 A B Figure 7 1. Device schemat ics. A) Schematic structure of vertical stack of monolayer MoS 2 and monolayer WSe 2 , m etal contacted vertical p n junction [107] .B) Schematic of a vdW heterostructure of the p WSe 2 /n MoS 2 junction sandwiched between top and bottom graphene electrodes [107]. Fig ure 7 2 . Simulated device structure with a 280nm thick SiO 2 gate dielectric and 200nm thick source/drain electrode s .

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109 Fig ure 7 3 . B and profiles obtained from device simulation . E l ectrons in conduction band of M o S 2 and holes in valence band of WSe 2 get combined through SRH or Langevin mechanism, contributing to dark current.

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110 Fig ure 7 4 . B and diagram s in the lateral direction at V sd = 0.6 V ( top), 0 V ( middle) and 0.6 V ( bottom ) obtained from self consistent simulation .

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111 Fig ure 7 5 . Comparison of the measured [ 107 ] and the simulated I V curves in the dark at V g = 0 V. SRH and Langevin mechanisms are considered separately. Both give good agreements with the measured I V curve . The experimental curve is reproduced from Ref. [107]. A B Fig ure 7 6 . Simulated bell shape current characteristics. A) Simulated g ate dependent plots of majority and minority carrier densities in each layer ( top), spatially averaged n M × p W ( middle) and n M × p W / ( n M + p W ) ( bottom) . B) S imulated photocurrent as a function of gate voltages show s a good agreement to the experiment [ 107 ] by Langevin recombination mechanism ( B = ~ 2 × 10 10 m 2 /s ) . The experiment data is reproduced from Ref. [107].

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112 A B Fig ure 7 7 . Modeling method for multi layer graphene contacted pn junctions. A) Circuit diagram for mode ling the vertical junction device as in Fig ure 7 1B , where the series resistance ( R s ) and shunt tunneling resistance ( R t ) are included . B) Simulated I V curves of the vertical p n junctions with different thicknesses show good agreement with experiments.

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113 CHAPTER 8 SCALING BEHAVIOR OF HIGH GAIN MONOLAYER MOS 2 PHOTODETECTOR A monolayer mo lybdenum disulphide (MoS 2 ) is a two dimensional (2D) semiconductor material with a direct band gap of 1.8 eV [108 , 11 2]. Monolayer MoS 2 transistors with high on/off current ratio, nearly ideal subthreshold swing, and small scale integrated circuits have be en demonstrated experimentally and theoretically [28, 31, 113, 114 ]. The direct band gap of monolayer MoS 2 also makes it a promising material for optoelectronic applications because light absorption is more effective for the material with direct band gap. Monolayer MoS 2 based photodetectors have been demonstrated and studied [115 117 ]. Recently, ultrasensitive photodetectors based on monolayer MoS 2 has been reported, which shows an external photoresponsivity as high as 880 A/W [118 ]. Scaling behaviors of monolayer MoS 2 photodetectors, however, remain unclear. To better understand the device physics and further optimize device performance, modeling and simulation of monolayer MoS 2 photodetectors is necessary. In this chapter, a comprehensive computational study on the scaling behaviors of monolayer MoS 2 photodetectors is presented. The drift diffusion transport e quation in the presence of light illumination for monolayer MoS 2 channel is self consistently solved with two dimensional Poisson equation for the two dimensional cross section of the MoS 2 photodetector. The physical mechanisms that are responsible for ult rahigh photoresponsivity of MoS 2 photodetectors are studied. The scaling characteristics with respect to gate oxide thickness, hole mobility and channel length are explored. The results are useful for understanding the physical mechanisms that determine th e photoresponsivity of monolayer MoS 2 photodetectors, and for further optimization of

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114 device designs of photodetectors based on monolayer dichacolgenide materials in general. Modeling and Simulation Approach A schematic cross section of the device structur e of the MoS 2 photodetector is shown in Fig ure 8 1, for which the monolayer MoS 2 , oxide and gate are vertically stacked, similar to the experimental device structure as reported in [118 ]. The nominal oxide thickness t ox and channel length L c are 270nm and 1µm, respectively. The source and drain electron barrier height between MoS 2 channel are 0.1eV. The device can be characterized by solving the two dimensional Poisson equation self consistently with one dimensional drift diffusion equation. The Poisson equ ation is expressed as follows , ( 8 1) where V is the voltage r 0 are the relative dielectric constant and vacuum permittivity, n and p are electron and hole density respectively. The monolayer is p doped with doping concentration N A =5×10 14 /m 2 . Carrier transport in monolayer MoS 2 can be described by the drift diffusion equations as follows , ( 8 2) , ( 8 3) where J n (J p ) is the electron (hole) current n p ) is the electron (hole) mobility, D n (D p ) is the electron (hole ) diffusion coefficient, respectively. Current continuity should be satisfied for current transport.

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115 , ( 8 4) . ( 8 5) G n (G p ) is electron (hole) generation due to light illumination. In the simulation, we use incident power density as 17.28 W/m 2 , correspond ing to 3×10 18 /(m 2 s) carrier generation if light absorption efficiency is 5% which is in a reasonable range as reported [119 ]. R is the carrier recombination rate which is dominant by Shockley Red Hall (SRH) recombination in state of the art monolayer MoS 2 devices , , ( 8 6) n p electron and hole lifetime. The finite element method is applied to solve two dimensional Poisson equation for device cross section self consistently with the one dimensional drift diffusion equation and current continuity equation in monolayer MoS 2 . The I V characteristics are obtained once the self consistency is achieved. Physical Mechanisms for Ultrahigh Phot oresponsivity The device simulation is firstly used to study the physical mechanisms responsible for ultrahigh photoresponsivity of monolayer MoS 2 photodetectors as observed in experiment [118 ]. We investigate the operation mechanism of the photodetector by comparing the potential profile between dark and under light illumination . The potential barrier between source and drain for electron is lowered as shown in Fig ure 8 2 A , which can be explained by optical ly generated holes as shown in Fig ure 8 2 B . The h ole density

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116 increased significantly as a result of light illumination. The optically generated holes are trapped in the electrostatic potential well in the channel region due to potential confinement as shown in Fig ure 8 2 A . As a result, self consistent po tential generated by trapped holes lowers the potential barrier between source and drain . The barrier lowering due to optical ly generated holes increas es the photocurrent. Carrier recombination reduces optically generated holes in the monolayer MoS 2 channel and results in less potential barr ier lowering as compared in Fig ure 8 2 A . It should be noted the recombination mechanism considered here is Shockley Read Hall (SRH) recombination with an electron and hole lifetime of 10ns . The assumed lifetime of SRH recombination is longer than that in a state of the art MoS 2 sample, whose recombination lifetime is decreased by low material quality. The results indicate that in addition to directly generated photocurrent, self consistent electrostatics of optical ly generated but subsequently trapped carriers play an important role in the photoresponse of the monolayer MoS 2 photodetector. Similar mechanisms have been shown to play an important role in Si nanowire photodetectors [12 0 ]. The I V characteristics are ex amined next. I V curves of the photodetector are presented in Fig ure 7 3 A and B in linear sale and logarithmic scale respectively. In the linear scale plot, the on current difference between dark and light is clear to see. While in the logarithmic scale, t he off current difference is easier to be noticed. T he light current for off state can be several orders of magnitude higher than dark current because strong hole confinement results in much larger barrier lowering at off state . However, t he hole confineme nt by the potential well in the channel becomes weaker as the gate bias increases since increasing gate bias leads to a shallower potential

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117 confinement well. An interesting observation is that although the relative change of the current due to light illumi nation is significantly larger in the subthreshold region of the MoS 2 phototransistor, the absolute value of the current change is maximized in the above threshold gate voltage range. An approximate analytical argument is developed below for qualitative un derstanding on the photoresponsivity of the device. With light illumination, lowering of the source drain potential barrier due to self consistent electrostatics leads to a current as follows, , ( 8 7) where is barrier lowering caused by hole confinement. The photoresponsivity (PR) is defined as the current difference between light and dark divided by input light power as . ( 8 8) Thus, by combining Equation 8 7 and 8 8 , PR can be analytically expressed as, . ( 8 9) Fig ure 8 4 A shows PR has high dependence on the gate bias. In the subthreshold region, the dark current of the phototransistor is exponentially sensitive to the gate bias. Operating the phototransistor in the above threshold regi on leads to a dark current exponentially larger than that in the subthreshold region. The large above threshold results in a large absolute value of PR although the barrier lowering and relative change of the current are smaller compared to the subthreshold gate

PAGE 118

118 bias range. The simulated device is compared to experimental device in Ref. [118 ] and shows comparable PR performance. The sensitive PR characteristics of monolayer MoS 2 photodetector is observed in simulation. Fig ure 8 4 B presents PR as a function of carrier recombination lifetime for SRH recombination with a fixed gate voltage for each curve. Increase of the recombination lifetime results in increase of PR. High quality monolayer MoS 2 with less recombination defects is desired for better photodetector performance. However, the PR tends to saturate at larger lifetime values, which indicates that recombination no longer plays a role in the density of holes in the channel region. When the recombination lifetime is sufficiently long, the hole density is likely to be dominantly determined by the photogeneration rate and the transport time of the holes from the channel to the source and drain contacts. In addition to the SRH recombination, the effect of radiative band to band recombination is also studied. The radiative recombination rate is described by , ( 8 10) where B is band to band recombination coefficient. The radiative band to band recombination may play a role as MoS 2 quality gets better which makes SRH recombination less important. Since the quantum yield of photoluminescence for monolayer MoS 2 is less than 1% [108 ], it is reas onable to assume that the radiative recombination lifetime is 2~3 orders higher than that of SRH lifetime. A radiative recombination time ~100ns, corresponding to value of the B in the range of 2×10 10m 2 /s according to [121 ], is used to examine the radiati ve recombination effect on PR.

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119 The simulation results indicate that the PR decreases by 39.6% for the modeled device at V G =0.7V. MoS 2 Photodetector Scaling Design A systematic simulation study of device scaling characteristics with respect to oxide thickness, hole mobility and channel length are performed next. To simplify the discussion, we examine the scaling behavior in the absence of carrier recombination. It ha s been examined that the inclusion of carrier recombination does not change the qualitative conclusions of the scaling behaviors. Fig ure 8 5 presents the device scaling behavior with respect to the gate oxide thickness. With a fixed dark current, the curre nt under light illumination increases at all modeled dark current values, as shown in Fig ure 8 5A. As shown in Fig ure 8 5B, The PR value increases from about 1000A/W to nearly 1400 A/W at a fixed dark current of 5.5 A/W as the ga te insulator thickness increases from 150nm to 450nm. The barrier lowering term in Eq. ( 8 7) due to the change of charge density can be written as , ( 8 11) where Q is light generated hole, C ox is oxide capacitance. C ox decreases as oxide thickness increases. Hence thicker oxide results in larger barrier lowering and larger and improved photoresponsivity. The PR as a function of hole mobility is presented in Fig ure 8 6 . In the coefficient. As hole mobility decreases, the transport time of photogenerated holes to the contacts increases, which leads to increase of the hole density and lowering of the

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120 potential barrier. As shown in Fig ure 8 6, the PR increases approximately inverse proportionally as the channel mobility decreases. The channel length scaling behavior is shown in Fig ure 8 7 with ho le mobility 0.1 cm 2 /V/s. In the modeled channel length range, it demonstrates that PR increases as the channel length increases. The transport time of photogenerated holes from the channel to the source and drain contacts becomes longer as channel increase s, thus leading to high hole density which results in larger barrier lowering. In general, long channel monolayer MoS 2 leads to larger PR. Summary Monolayer MoS 2 photodetectors are modeled by self consistently solving the diffusive transport equation in the presence of light illumination and recombination self consistently with the two dimensional Poisson equation. The simulation results indicate that the very hig h photoresponsivity of ~880A/W observed in experiment [118 ] can be explained by strong electrostatic effect of optically generated holes, efficient optical absorption, and relatively low mobility of monolayer MoS 2 . It is found that the photoresponsivity is sensitive to the DC gate bias voltage, and it can be improved by orders of magnitude in a channel with lower mobility. High quality monolayer MoS 2 with less Shockley Read Hall recombination defects is desired for high performance. The photoresponsivity in creases as the gate insulator thickness increases and the channel length increases. The optimization designs of monolayer MoS 2 photodetectors are also applicable to other monolayer transition metal dichalco genide materials in general.

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121 Figure 8 1. Sche matic structure of a MoS 2 photodetector. The device is with oxide thickness t ox and channel length L c . The source and drain contact barriers between MoS 2 channel are 0.1 eV A B Fig ure 8 2. Band profile and hole density distribution. A) Potential profile for dark, light with/without Shockley Read Hall ( SRH ) recombination under bias V G =0.1V and V D =4V. B) Hole density distribution under bias V G =0.1V and V D =4V in the channel for dark, light with/without SRH recombination respectively. Hole and electron life time are set as 10ns.

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122 A B Figure 8 3. IV characteristics. A) Linear plot and B) logarithmic plot for current as a function of gate voltage for dark, light with/without recombination under bias V D =4V . The incident light power densi ty is 17.28 W/m 2 , corresponding to 3×10 18 /(m 2 s) carrier generation with light absorption efficiency is 5%. The recombination rate is determined by Shockley Read Hall ( SRH ) recombination . A B Fig ure 8 4. Photoresponsivity with respect to gate bias and carrier lifetime. A) Photoresponsivity (PR) for with/ with out recombination as a function of gate voltage. The recombination rate is determined by SRH recombination with electron and hole lifetime 500ns . B) PR as a function of carrier lifetime at different gate bias with SRH recombination . The drain bias is V D =4V. The incident light power density is 17.28 W/m 2 , corresponding to 3×10 18 /(m 2 s) carrier generation with light absorption efficiency is 5%.

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123 A B Fig ure 8 5. Current and photo responsivity as a function of gate oxide thickness. A) Light current as a function of gate oxide thickness with fixed dark current for each curve. B) Photoresponsivity (PR) as a function of oxide thickness for different fixed dark current. The drain bias is V D =4V. The incident light power density is 17.28 W/m 2 , correspondi ng to 3×10 18 /(m 2 s) carrier generation if light absorption efficiency is 5%. Figure 8 6. Photoresponsivity (PR) as a function of hole mobility for different gate bias. The PR is obtained by setting fixed gate bias for each set of curve. The drain voltage is V D =4V . The incident light power density is 17.28 W/m 2 , corresponding to 3×10 18 /(m 2 s) carrier generation with light absorption efficiency is 5%.

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124 Figure 8 7. Photoresponsivity (PR) as a function of channel length with different gate bias. The PR is obtained by setting fixed gate bias for each set of curve. The channel is in scale of micrometers to prevent drain induced barrier lowering. The drain voltage is V D = 4V . The incident light power density is 17.28 W/m 2 , corresponding to 3×10 18 /(m 2 s) carrier generation with light absorption efficiency is 5% .

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125 CHAPTER 9 CONCLUSION AND OUTLOOK Conclusion In this dissertation, nano scale electronic devices based on emerging semiconductor s , such as carbon nanotube, graphene, monolayer transition metal dichalcogenides , are numerically studied. Electrolyte enabled carbon nanotube thin film silicon Schottky junction solar cell has high efficiency due to transparency of CNT thin film and electrolyte induced electrostatic coupling. Carbon nanotube enabled and porous graphene enhanced vertical field effect transistors work differently from conventional vertical field effect transistors due to barrier height modulation. Phase change memory by using carbon naotube as contact leads to low programming current and power consumption due to its small size. Permeable base transistors fabricated by solution process have high current gain and good current saturation, which have potential for GHz applications with careful device engineering. Atomically thin pn junctions have been fabricated by using monolayer Mo S 2 and WSe 2 , which function through interlayer carrier recombination and are quite different from conventional pn junctions. Monolayer MoS 2 photodetector has ultrahigh gain because of electrostatic effect of optically generated holes. Outlook As device sca le decreases , thermal effect may become a significant concern due to high power density. Thermal effect in emerging semiconductor devices is a suggestion for future work.

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136 BIOGRAPHICAL SKETCH Wenchao Chen was born and raised in Qufu, a small but fa mous city of Shandong province in China. He received the B.E. degree in information engineering from Xi'an Jiaotong University, Xi'an, China in 2006 and M.E. degree in electromagnetics and microwave technology from Shanghai Jiao Tong University, Shanghai, China in 2009. He started working towards h is PhD degree in Dr. Jing Guo's group at University of Florida from 2009. His research focuses on physics, modeling and simulation of nano scale electronic devices.