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Low Power Circuits and Systems for Brain Machine Interfaces

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Title:
Low Power Circuits and Systems for Brain Machine Interfaces
Creator:
Xiao, Zhiming
Place of Publication:
[Gainesville, Fla.]
Florida
Publisher:
University of Florida
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Language:
english
Physical Description:
1 online resource (149 p.)

Thesis/Dissertation Information

Degree:
Doctorate ( Ph.D.)
Degree Grantor:
University of Florida
Degree Disciplines:
Electrical and Computer Engineering
Committee Chair:
BASHIRULLAH,RIZWAN
Committee Co-Chair:
HARRIS,JOHN GREGORY
Committee Members:
BOSMAN,GIJSBERTUS
VAN OOSTROM,JOHANNES H
Graduation Date:
5/3/2014

Subjects

Subjects / Keywords:
Amplifiers ( jstor )
Bandwidth ( jstor )
Capacitors ( jstor )
Current amplifiers ( jstor )
Electric current ( jstor )
Electric potential ( jstor )
Low noise ( jstor )
Noise measurement ( jstor )
Noise reduction ( jstor )
Signals ( jstor )
Electrical and Computer Engineering -- Dissertations, Academic -- UF
analog -- bmi -- neural
Genre:
bibliography ( marcgt )
theses ( marcgt )
government publication (state, provincial, terriorial, dependent) ( marcgt )
born-digital ( sobekcm )
Electronic Thesis or Dissertation
Electrical and Computer Engineering thesis, Ph.D.

Notes

Abstract:
Establishing adirect pathway between the brain and a machine is a promising technique for assisting, augmenting, or repairing human cognitive or sensory-motor functions.The core of this emerging paradigm is a low power and highly integrated brain–machine interface (BMI) that can less invasively sense neural signals above a minimum duration. This work focuses on the design of low-power circuits and systems for optimizing the energy efficiency, recording lifetime, size, and transmission range of BMI systems.  This dissertation first provides an overview of BMI systems and then discusses each BMI building block in terms of power dissipation, noise, size, and reliability requirements. The neural amplifier, typically the first stage of a neural acquisition system, is given particular attention, and, with the goal of achieving both low noise and energy efficiency in amplifier design, this work presents three new amplifier structures: (1) a cascading structure that helps reduce power consumption without sacrificing noise performance by sharing the bias current between two channels; (2) a time multiplexing structure that helps reduce the die size and power consumption by sharing a single operational transconductance amplifier among multiple input channels; and (3) a supply current modulation structure that decreases the amplifier’s average power consumption using atrack and hold function. To analyze switching effects in both the time-multiplexed and supply current–modulated amplifiers, detailed derivations of their respective transfer functions and noise aliasing characteristics are carried out. These derivation procedures are simplified by equating the switched amplifier to a switched RC filter model, and the results show that both schemes cause noise from higher frequency bands to alias down to the base band. The overall noise efficiency factor, however, remains unchanged because of the power saving benefits of the two architectures. This dissertation also presents two new neural recording systems. The first is a battery powered, four-channel device with an analog front end, a digital signalprocessor, and a wireless transceiver. The second system is a single channel neural recording tag that can be powered through a battery or wirelessly from an external resource. ( en )
General Note:
In the series University of Florida Digital Collections.
General Note:
Includes vita.
Bibliography:
Includes bibliographical references.
Source of Description:
Description based on online resource; title from PDF title page.
Source of Description:
This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Thesis:
Thesis (Ph.D.)--University of Florida, 2014.
Local:
Adviser: BASHIRULLAH,RIZWAN.
Local:
Co-adviser: HARRIS,JOHN GREGORY.
Electronic Access:
RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2014-11-30
Statement of Responsibility:
by Zhiming Xiao.

Record Information

Source Institution:
UFRGP
Rights Management:
Applicable rights reserved.
Embargo Date:
11/30/2014
Resource Identifier:
907379579 ( OCLC )
Classification:
LD1780 2014 ( lcc )

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1 LOW POWER CIRCUIT S AND SYSTEM S FOR BRAIN MACHINE INTERFACE S By ZHIMING XIAO A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 201 4

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2 201 4 Zhiming Xiao

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3 To my family

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4 ACKNOWLEDGMENTS I would like to first thank my supervisor Dr. Rizwan Bashirullah for giving me this great opportunity to work towards a Ph.D. His kind guidance and encouragement lead to my growth of technical skills and attitude towards research. I have truly enjoyed working with him over the years in his splendid group that offers me sufficient sources of experience I would also like to thank Dr. John Harris Dr. Gijs Bosman and Dr. Van Oostrom for their valuable time and for being on my Ph.D. committee. I feel very fortunate to have worked together with all my colleagues, especially Chun M ing Tang, Pengfei Li, Hong Yu, Yan Hu, Walker Turner and Chris Dougherty in our group Finally, I would like to acknowledge the love and continuous encourageme nt from my parents and wife to whom I dedicate this work.

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5 TABLE OF CONTENT S Page ACKNOWLEDGMENTS ................................ ................................ ................................ .............. 4 LIST OF TABLES ................................ ................................ ................................ .......................... 7 LIST OF FIGURES ................................ ................................ ................................ ........................ 8 ABSTRACT ................................ ................................ ................................ ................................ .. 12 CH AP TER 1 INTRODUCTION ................................ ................................ ................................ ................. 14 1.1 Background ................................ ................................ ................................ ....................... 14 1.2 Brain Machine Interface ................................ ................................ ................................ ... 15 1.3 Recent Progress towards the Low Power BMI Systems ................................ .................. 17 1.4 Dissertation Organization ................................ ................................ ................................ 21 2 SYSTEM OVERVI EW OF LOW POWER BRAIN MACHINE INTERFACES ................ 24 2.1 Powering and Biasing Block ................................ ................................ ............................ 24 2.1.1 Direct Tethered Powering ................................ ................................ ........................ 25 2.1.2 Battery Powering ................................ ................................ ................................ ..... 25 2.1.3 Wireless Powering ................................ ................................ ................................ ... 26 2.2 Signal Conditioning Block ................................ ................................ ............................... 27 2.2.1 Challenges and Motivation ................................ ................................ ..................... 27 2.2.2 Noise Considera tions of Neural Amplifier ................................ .............................. 31 2.2.3 Comparison among Modern Neural Amplifiers ................................ ...................... 32 2.3 Transceiver Block ................................ ................................ ................................ ............. 36 2.3.1 Active Transmitter ................................ ................................ ................................ ... 37 2.3.2 Backscattered Transmitt er ................................ ................................ ....................... 37 2.3.3 Receiver ................................ ................................ ................................ ................... 38 2.3.4 Modulation Scheme ................................ ................................ ................................ 39 3 ENERGY EFFICIENT AMPLIFIERS ................................ ................................ .................. 42 3.1 Cascaded Amplifiers for Multi Channel Recording ................................ ......................... 43 3.1.1 Current Reuse Amplifier Structure ................................ ................................ ......... 44 3.1.2 Measurement Result ................................ ................................ ................................ 50 3.2 Time Multiplexed Amplifie r ................................ ................................ ............................. 52 3.2.1 The Structure of 4 Channel Time Multiplexed AFE ................................ ............... 54 3.2.2 Operation of Time Multiplexing ................................ ................................ ............. 57 3.2.3 Measurement Result ................................ ................................ ................................ 59 3.3 Supply Current Modulated Amplifier ................................ ................................ ............... 62 3.3.1 Fully Differential Amplifier with Supply Current Modulation ............................... 62

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6 3.3.2 Supply Current Mo dulated OTA ................................ ................................ ............. 63 3.3.3 Measurement Result ................................ ................................ ................................ 65 4 MATHEMATICAL ANALYSIS OF T/H AMPLIFIER ................................ ........................ 71 4.1 Equivalen ce between T/H_Amp and T/H_RC Filter ................................ ....................... 71 4.2 Transfer Function of T/H_RC Filter ................................ ................................ ................. 73 4.2.1 Step 1: Output Voltage at the End of a Single Pulse Switching Signal ................... 73 4.2.2 Step 2: Output Voltage at the End of a Pulse Train Switching Signal .................... 75 4. 2.3 Step 3: Frequency Response of the Sampled Output ................................ .............. 78 4.2.4 Step 4: Transfer Function of T/H_RC Filter ................................ ........................... 79 4.3 Noise Aliasing of T/H_RC Filter ................................ ................................ ...................... 82 4.4 Transfer Function of T/H_Amp ................................ ................................ ........................ 84 4.5 Noise Aliasing of T/H_Amp ................................ ................................ ............................. 87 4.6 Energy Efficiency of the Proposed Amplifiers ................................ ................................ 92 5 915 MHz ACTIVE NEURAL TRANSPONDER WITH 4 CHANNEL TIME MULTIPLEXED ANALOG FRONT END ................................ ................................ ........... 97 5.1 Motivation ................................ ................................ ................................ ........................ 97 5.2 System Functionality ................................ ................................ ................................ ........ 99 5.3 Transmitter Chain ................................ ................................ ................................ ........... 101 5.3.1 High Pass Filter and Buffer Stage ................................ ................................ ......... 102 5.3.2 Middle Voltage Generator ................................ ................................ ..................... 104 5.3.3 Low Power SAR ADC ................................ ................................ .......................... 105 5.3.4 Transmitter Chain Logic ................................ ................................ ....................... 110 5.3.5 System Clocking and Modulation ................................ ................................ ......... 112 5.4 Low Power Receiver Chain ................................ ................................ ............................ 113 5.5 Measurement Result ................................ ................................ ................................ ....... 115 5.6 Design Summary ................................ ................................ ................................ ............ 119 6 ................................ ................................ .................. 121 6.1 Motivation ................................ ................................ ................................ ...................... 121 6.2 System Level Design Considerations ................................ ................................ ............. 123 6.3 System Powe ring ................................ ................................ ................................ ............ 126 6.4 Receiver Chain and Full Duplex Operation ................................ ................................ ... 127 6.5 Trans mitter Chain ................................ ................................ ................................ ........... 129 6.6 Measurement Result ................................ ................................ ................................ ....... 131 6.7 Design Summary ................................ ................................ ................................ ............ 137 7 CONCLUSION ................................ ................................ ................................ .................... 138 LIST OF REFERENCES ................................ ................................ ................................ ............ 142 BIOGRAPHICAL SKETCH ................................ ................................ ................................ ...... 149

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7 LIST OF TABLES T able page 2 1 Comparison among modern neural acquisition systems ................................ .................... 40 3 1 Transistor sizes in both P stage and N stage amplifiers ................................ .................... 49 3 2 Comparison between P stage and N stage amplifiers by simulation ................................ 49 3 3 Transistor sizes for the OTA in time multiplexed amplifier ................................ .............. 56 3 4 Characteristic of 4 channel time multiplexed amplifier ................................ ..................... 61 3 5 Transistor sizes for the OTA in supply current modulated amplifier ................................ 64 3 6 Noise performance comparison among different duty cycles ................................ ............ 66 3 7 Characteristic of supply current modulation amplifier ................................ ...................... 68 4 1 Comparison between the proposed amplifiers and the state of the art .............................. 94 5 1 Performance summary of active neural transponder ................................ ....................... 119 6 1 Performance summary of neural recording tag ................................ ................................ 135 6 2 Performance comparison between the proposed systems and the state of the art ........... 136

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8 LIST OF FIGURES Figure page 1 1 The extracellular potential demonstration ................................ ................................ ......... 15 1 2 Brain machine interface illustration. ................................ ................................ .................. 16 1 3 Comparison among three neural recording modalities. ................................ ..................... 17 2 1 An example block diagram of the neural recoding system. ................................ ............... 24 2 2 Example of small batteries ................................ ................................ ................................ 25 2 3 Wireless coupling comparison ................................ ................................ ........................... 27 2 4 Simplified diagram of the T/H amplifier ................................ ................................ ........... 29 2 5 Supply current modulation in multiplexed track and hold system. ................................ ... 31 2 6 Neural amplifier structures ................................ ................................ ................................ 33 2 7 Schematic of the operational transconductance amplifier ................................ ................. 34 2 8 Comparison among different modulation modalities. ................................ ........................ 39 3 1 Measurement setup for amplifier. ................................ ................................ ...................... 42 3 2 Comparison of the instrumental amplifier topologies ................................ ....................... 44 3 3 The proposed amplifier structure ................................ ................................ ....................... 46 3 4 The structure of 32 channel IA array. ................................ ................................ ................. 47 3 5 The schematic of the reference generator. ................................ ................................ ......... 48 3 6 The schematic of the local reference buffer. ................................ ................................ ...... 48 3 7 Die picture of the 4X8 amplifier array. ................................ ................................ .............. 50 3 8 Measured P stage amplifier performance ................................ ................................ .......... 51 3 9 Measured input referred voltage noise (squared) versus the source resistance. ................ 52 3 10 Comparison among the multiplexing strategies at different stages. ................................ .. 53 3 11 Schematic of the 4 channel AFE. ................................ ................................ ....................... 54 3 12 Schematic of the four channel time multiplexed OTA. ................................ ..................... 55

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9 3 13 Equivalent schematic of one chann el. ................................ ................................ ................ 58 3 14 Die picture of the 4 channel time multiplexed AFE. ................................ ......................... 59 3 15 M easurement result of the 4 ch time multiplexed amplifier and the single channel amplifier without time multiplexing ................................ ................................ .................. 60 3 16 The cross talk measurement between two nearby channels. ................................ ............. 61 3 17 Schematic of the T/H_Amp and the buffer stage. ................................ .............................. 62 3 18 Schematic of the supply current modulated OTA. ................................ ............................. 63 3 19 Die picture. ................................ ................................ ................................ ......................... 65 3 20 Measured transfer function of T/H_Amp with different duty cycles. ................................ 65 3 21 Measured input referred noise of T/H_Amp with different duty cycles. ........................... 66 3 22 Noise comparison between operation with and without supply current modulation for the same current consumption. ................................ ................................ .......................... 67 3 23 NEF comparison between directly reducing of bias current and supply current modulation ................................ ................................ ................................ ......................... 69 3 24 Measured transfer function of T/H_Amp with different T/H frequencies. ........................ 70 3 25 Measured input referred noise of T/H_Amp with different T/H Frequencies. .................. 70 4 1 Simplified RC model for amplifier ................................ ................................ .................... 71 4 2 Resistive effect in the track and hold RC filter. ................................ ................................ 72 4 3 Demonstration of the derivation procedure ................................ ................................ ....... 74 4 4 Comparison of the frequency response among dif ferent duty cycles ................................ 81 4 5 Noise PSD comparison between simulated result and calculated result. ........................... 84 4 6 The RC model of the supply current modulated amplifier. ................................ ............... 85 4 7 Comparison of the transfer functions among calculated result of RC model, simulated result of RC model, and measured result of amplifier. ................................ ...................... 87 4 8 Comparison of the input referred noise among simulated result of RC model, simulated result of amplifier, measured result of amplifier, and simulated result of amplifier without flicker noise. ................................ ................................ .......................... 91 4 9 Comparison of the noise efficiency factor among the state of the art. ............................... 95

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10 5 1 System block d iagram. ................................ ................................ ................................ ..... 100 5 2 Schematic of the high pass filter and the buffer stage. ................................ .................... 102 5 3 Schematic of the middle voltage generator. ................................ ................................ ..... 104 5 4 Schematic of low power SAR ADC. ................................ ................................ ................ 105 5 5 Layout of the capacitor array ................................ ................................ ........................... 106 5 6 Comparator of the ADC. ................................ ................................ ................................ .. 107 5 7 SAR logic diagram. ................................ ................................ ................................ .......... 108 5 8 Schematic of the latch for the capacitor array. ................................ ................................ 108 5 9 Timing diagram of ADC operation. ................................ ................................ ................. 109 5 10 Schematic of the power on reset circuit. ................................ ................................ .......... 110 5 11 Data p attern of one p acket. ................................ ................................ .............................. 111 5 12 Four phase non overlapping clock generator. ................................ ................................ .. 112 5 13 Block diagram of the r eceiver chain. ................................ ................................ ............... 113 5 14 Schematic of the envelop detector ................................ ................................ .................. 113 5 15 DC sweeping of the u nbalanced s ource c oupler. ................................ ............................. 114 5 16 Die picture. ................................ ................................ ................................ ....................... 115 5 17 Measurement setup for system characterization. ................................ ............................. 116 5 18 Measured w aveforms in r eceiver c hain. ................................ ................................ .......... 116 5 19 Measured t ransmitter p erformance ................................ ................................ .................. 117 5 20 Comparison between a mplified and w ireless r ecovered s ignal. ................................ ...... 118 5 21 Pie chart of the power distribution. ................................ ................................ .................. 119 6 1 System block diagram. ................................ ................................ ................................ ..... 125 6 2 Schematic of the rectifier, limiter and storage capacitor. ................................ ................. 126 6 3 Schematic of the bias generator and the low dropout regulato r. ................................ ...... 127 6 4 Schematic of the envelop detector. ................................ ................................ .................. 128

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11 6 5 Schematic of frequency to digital decoder. ................................ ................................ ...... 129 6 6 Schematic of clock generator. ................................ ................................ .......................... 130 6 7 Die picture. ................................ ................................ ................................ ....................... 131 6 8 Wireless measurement ................................ ................................ ................................ ..... 132 6 9 Components of the example prototype ................................ ................................ ............ 133 6 10 Assembled prototype ................................ ................................ ................................ ....... 134 6 11 In Vivo measurement of the neural signal ................................ ................................ ....... 135

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12 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy LOW POWER CIRCUIT S AND SYSTEM S FOR BRAIN MACHINE INTERFACE S By Zhiming Xiao May 201 4 Chair: Rizwan Bashirullah Major: Electrical and Computer Engineering Establishing a direct pathway between the brain and a machine is a promising technique for assisting, augmenting, or repairing human cognitive or sensory motor functions. The core of this emerging paradigm is a low power and highly integrated brain machine interface (BMI) that can less invasively sense neural signals above a minimum duration. This work focuses on the design of low power circuits and systems for optimizing the energy efficiency, recording lifetime, size, and transmission range of BMI systems This dissertation first provides an overview of BMI systems and then discusses each BMI building block in terms of power dissipation, noise, size, and reliability requirements. The neural amplifier, typically the first stage of a neural acquisition syst em, is given particular attention, and, with the goal of achieving both low noise and energy efficiency in amplifier design, this work presents three new amplifier structures: (1) a cascading structure that helps reduce power consumption without sacrificin g noise performance by sharing the bias current between two channels; (2) a time multiplexing structure that helps reduce the die size and power consumption by sharing a single operational transconductance amplifier among multiple input channels; and (3) a

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13 consumption using a track and hold function. To analyze switching effects in both the time multiplexed and supply current modulated amplifiers, detailed derivations of their respective transfer functions and noise aliasing characteristics are carried out. These derivation procedures are simplified by equating the switched amplifier to a switched RC filter model, and the results show that both schemes cause noise from higher f requency bands to alias down to the base band. The ov erall noise efficiency factor however, remain s unchanged because of the power saving benefits of the two architectures This dissertation also presents two new neural recording systems. The first is a b attery powered, four channel device with an analog front end, a digital signal processor, and a wireless transceiver. The second system is a single channel neural recording tag that can be powered through a battery or wirelessly from an external resource.

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14 CHAPTER 1 1 INTRODUCTION 1.1 Background Neuroscientists study neuronal information by monitor ing electrical signals produced by neurons in the br ain of behavior animals in order to restore neurological function or treat disease The information being studied is acquired by recording the extracellular pulses. Th ose researches exhibit great potential with a pplications ran ge from neuromuscular disorders, spinal injuries, to treating epilepsy. For instance, the neural prosthesis can e xtract information by neural recordings with the goal of creating predictive models for the subject's intent of motor movement to directly control a robotic de vice However, much of the brain function is still unknown and there calls for longer neural reco rding lifetime and the capability of recoding from multi neural sites simultaneously Besides, there also demands a better recording environment that causes less irritation or infection and more freedom for the behaving animal being studied. One of the mo st widely recorded neural signals is the extracellular bio potential generated electrochemically from individual neur ons. The change in the extracellular single unit potential exhibits a shape of a spike or action potential with peak to peak amplitude of 50 V 500 V [1] and frequency ranges from 100 Hz to 6 KHz [2] depending on how far the electrode is from the neuron and what part of the neuron is closest to the electrode An illustration drawing is shown in Figure 1 1 (A) and (B) which give the labeled drawing of the neuron and the spike amplitude that attenuates as propagates from the soma (cell body) along the axon [3] respectively A single recording site may record from as many as four to six neurons but there will be many more distant neurons whose signals become part of the noise on the signal [4] The typical noise floor is around 10Vrms 20 Vrms [5] Noticing that the neural action potential is the same level of the background noise, the total input referred noise of the entir e neural recoding systems is

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15 always the primary design consideration In addition, a s the brain moves, the distance between the electrode and the neurons may also change so the spike shape (amplitude and width) may chang e over time To make matter worse unavoidable electrochemical eff ects at the electrode tissue interface introduce the DC offsets up to 1 2 V across the recording sites [6] Thus, those DC offset must be removed during the neural signal acquisition lest the usef ul action potential is overwhelmed or the neural recoding system may be saturated by the large DC offset A B Figure 1 1 The e xtracellular potential demonstration A) Sketch of a neuron with the parts labeled B) w aveforms recorded from the soma (cell body) along the axon [3] 1.2 Brain Machine Interface T he enabling devices for neural recording require a highly reliable brain to machine interface (BMI) b eing capable of recording neural activities at the cellular leve l for enough period of time [7] A s shown in Figure 1 2 the BMI s serve as a bridging technique con necting the neurons to external machines. The study of BMIs is currently an interdisciplinary of biological science b y collaborat ing with other fields such as chemistry electrical engineering psychology [8] BMI s can be implemented by using various recording modalities such as EEG

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16 (Electroencephalograph) over the scalp, ECoG (electrocorticography) that us es the subdural electrodes and Single Unit Activities (SUA) that us es the penetrating microwire arrays. A brief compar ison among those three modalities is shown in Figure 1 3 The least invasive method is the EEG but the signal to noise ratio (SNR) is the lowest, while the SUA being the most invasive way but the signal recorded has a high SNR, better resolution an d accuracy. This dissertation targets animal studies by using the microelectrode due to its localized, high spectral range and high SNR action potential recordings. Figure 1 2 Brain m achine i nterface i llustration The BMI systems that target for clinical diagnostic and therapeutic applications require high rel iability and safety [9] Recently BMI devices call for high integration and wireless transmission to minimize the ri sk caused by infection an d to increase the mobility of animal under test The development of BMI devices is confronted with technical and physical constraints such as size, power dissipation, heat sinking, recording lifetime and telemetry bandwidth. The refore the implantable electronics for this application must be small in scale and hence highly integrated;

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17 very low power and energy efficient to minimize the heat damage ; low noise to condition the weak neural signals; and capable of wirelessly transmitt ing the neural information Figure 1 3 Comparison among t hree n eural r ecording m odalities The BMI systems consist of both on chip and off chip components as an example block diagram shown in Figure 1 2 The front end component is typically the electrodes, which is the interface between the biological recording site and the electrical components on chip [10] Another possible off chip compenent is the battery which provides the power of the entire BMI system T he wireless powered system may not include a battery so the restriction on the implant size or the implant lifetime is a lleviated but it suffers the limited power budget and transmission range. The on chip part typically (may not necessarily) consists of the function s including amplification, analog to digital conversion, DSP, and wireless transmission The back end of the BMI system may be the tethered wire a coil or an antenna, which are used to communate with the external device by a certain transmission scheme 1.3 Recent Progress towards the Low Power BMI S ystems The B M I systems ha ve gone through many trials and im provements over years Researchers are trying to find ways to acquire the neural signal with higher quality and longer period but being less invasive. There are majorly three building blocks make large performance difference among recent designs: the syste m powering block, the neural signal amplifier and the transmitter (TX) chain

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18 The system powering strategy determines the recording lifetime, the system robustly and the communication range. Systems utilizing a small battery [11] [12] [13] [14] successfully eliminate the hardwire connection for powering but has limited recording lifetime and requires replacement after operates for a while For permanently powering the device without using a battery, the BMI systems can utilize a low frequency and clos e proximity inductive link for the power delivery [6] [15] [16] Nevertheless this kind of powering method require s a coil, and the powering range is limited within several tens of centimeters [17] [18] [19] Noticing that the wireless data link is capable of transmitting the signals for meters easily the inductive link for powering act s as a bottleneck which may cause inconvenience for both external reader and the animal s under test. An improved method includes a rechargea ble battery that can be powered through a short range and send/ receive the signal at a much larger distance [16] But this type of batteries, such as nickel metal hydride, lithium iron usually ha s relative small energy density and call for extra control of the voltage levels. More recently, the attempt of constructing a single channel system with only low power elements (AMP, ADC, TX & RX) exhibits great efficiency improvement which makes the far field wireless powering and comm unication feasible [20] [21] Th e far field wireless link increases the animal mobility and reduces the size of the final prototype by using the single antenna approach However, far field powering with a relatively small energy provision suffers the limited amount of power deliverable to the system and also limits the number of channel s The proposed system described in Chapter 5 has a total power consumption of 190 W wh ile fully functioning so the entire device can be continuously powered through a high density battery for month s such as zinc air, silver oxide, which are as much as necessary for the bench top neural studies Another proposed system described in Chapter 6 has a total power

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19 consumption of 20 W Thus this system can be powered through the far field wireless link which shows great improvement for the recording lifetime and the measurement set up. This system also has the option of local powering through a battery which allows for larger communication range. Another critical building block in modern BMI system s is the neural signal amplifier which determines the BMI system parameters including the input sensitivity, the area and the overall system power budget. First, there lies in a tradeoff between the current consumption and the input referred thermal noise of the neural amplifier. In order to achieve better noise performance for a given power bu dget a folded cascade O TA structure utilized in [22] allocates larger bias current for the input differential pair to maximize the transconductance and help reduce the noise contribution from the transistors other than the input different pair Second, n oticing the bandwidth of the neural signal is within around 10 kHz, the flicker noise contributes a large portion of the entire noise power So, a chopper technique based amplifier in [23] removes the flicker noise from baseband and realizes a much lower flicker noise corner frequency. Third, the neural amplifier should also be able to eliminate the effect s of DC potential shifting at the tissue electrode interface and the local field potential that accompanies the useful neural spikes [24] The architecture described in [6] utilizes the diode connected pseudo resistor in the feedbac k loop to form a high pass corner frequency and set the DC operating point. The design in [25] uses the chopper stabilization topology that achieves high input impedance and rejects the large electrode offsets The design in [26] exhibits well controlled frequency corners, which is set by the capacitor ratios and the SC clocks, simplifying its usage and making it more robust and predictable in practical experimental settings. The design in [27] has tunable gain and bandwidth by changing the tail current. Fourth, since the maximum allowable input referred noise

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20 sets the lower limit of the current consumption of the front end amplifier and also the thermal noise floor is determined by the neural signal levels (typically 100V), the power consumption of the neural amplifier occupies large portion of the entire system power budget In order to save power but without sacrificing the noise performance. The design in [28] can adaptively turn on/off the ampl ifiers in order to save power while any of the channels is un used. During turn on transient, the amplifier consumes large instantaneous power and the speed is boosted up. The design described in [29] combines the dc coupled inputs with an architecture that uses the mixed signal feedback for filtering and offset suppression to achieve a compact area while requiring only a 0.5V supply. Since the stringent noise requirement forces the hard limit on the amplifier current consumption and also the power consumption is almost proportional to the channel counts, the e ffort on optimizing the tradeoff between noise and power n ever ends On the o ther hand the entire BMI device has limit ed power and area available due to the diminutive recording space, the amplifier power consumption will affect the entire BMI performance by setting the higher limit on the number of channel counts, the range of co mmunication, or the lifetime of neural recording. T he proposed amplifier described in section 3 1 focuses on t he structural improvement Two independent channels share the bias current so the averaged power consumption is reduced but without sacrificing th e noise performance. The proposed amplifier in section 3 2 uses a time multiplexing scheme to share one single OTA among channels, thus the averaged area and the current consumption is much reduced. Noticing the neural amplifier is utilized as the pre stag e of an ADC with the sample and hold function The proposed amplifier described in section 3 3 uses a supply current modulation scheme to allocate large current consumption during track phase for large instantaneous bandwidth and slew rate for charg ing the holding capacitor, while during

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21 hold phase the amplifier is shut down with minimal current consumption. Thus the proposed amplifier achieves larger effective bandwidth and slew rate compared to the conventional amplifier with the same power consumption. The transmitter (TX) block influences the BMI performance by affecting the system power consumption and the wireless communication range. There are two widely used TX structures in modern BMI systems, the active transmitter and the backscattered transmitt er. Active transmitting is a straightforward method of conveying the neural signal wirelessly to the external reader. The transmission range by this approach is high enough but may consume very high power in order to generate the highest RF signal on chip. In the reported systems [17] and [16] that use the active transmitting method their active transmitters consume nearly half of the total power budget of the entire system. A more energy efficient data link is realized by utilizing the backscattered transmitter. This type of transmission has much lower power consumption by shifting the burden of generating the highest frequency to the external device. The systems [21] [20] [11] that utilizing the backscattered transmitter achieve a total power consumption below 1mW. However, the range of transmission is limited since the received signal at the reader side suffers bo th up link and down link power loss. The two proposed systems described in Chapter 5 and Chapter 6 are both using the backscattered transmitter. Thus those two systems achieve very low power consumption among the state of the art. The system in Chapter 6 also uses a matching network for impedance matching between the antenna and the backend of the BMI system for higher input sensitivity The transmission range of both systems was measured to be at least one meter which is enough for laboratory research. 1.4 D issertation Organization In this dissertation w e begin in C hapter 2 by giving a system level overview of the neural

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22 recording systems with challenges and techniques being addressed specifically in three major building blocks: the powering and biasing block the signal conditioning block and the transceiver block Chapter 3 focuses on the discussion of energy efficient neural amplifiers. It first introduces the conventional techniques used in neural amplifiers. Then t hree new amplifier architectures are presented with design considerations and measurement results. The first one is the cascaded amplifier that reuse s the supply current between two channels The second one is the time multiplexed amplifier that share s the operational transconductance amplifier (OTA) among multiple inputs The third one is t he supply current modulat ed amplifier that reduce s the average current consumption by track and hold function T he performance of those amplifiers including the nois e, bandwidth, gain, power consumption, and the size is presented and the tradeoffs among them are investigated. C hapter 4 describes the derivation procedure of solving the transfer function and the noise aliasing in track and hold amplifiers It begins with simplifying the track and hold amplifier to a simplified model of track and hold RC filter Then the transfer function and the noise aliasing of the track and hold RC filter are solved in frequency domain. T he result is then applied to the track and hold amplifier to find the switching effects in both time multiplex ed and supply current modulated amplifiers Chapter 5 and Chapter 6 present two neural recording systems: (1) a battery powered four c hannel neural recording s ystem with a total power consumption of 19 0 W and is capable of wireless transmission by backscatt ered modulator ; (2) an extremely low power neural recording tag based on RFID protocol which can be powered by either a battery or a wireless source. The total power c onsumption is around 20 W while fully functioning The performance

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23 of those two systems at the system level is given by measuring the parameters including total power consumption, size data rate, etc. The overall functionalities of both systems are checke d by compari ng the pre recorded neural signal being fed into the front end and the wireless reconstruct ed signal at the external backend. Chapter 7 first gives a brief conclusion of this dissertation and then discusses the contribution of this work towards improving the performance of BMI system s regarding several specific designing challenges.

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24 CHAPTER 2 2 SYSTEM OVERVIEW OF LOW POW E R BRAIN MACHINE INTERFACE S Over the past few years, various neural recording systems have been reported with advances in modern integrated circuit s An example system functional diagram for BMI systems is shown in Figure 2 1 The diagram entail s three major blocks : (1) t he powering and biasing block that provides the supply and reference for the entire chip This block may incorporate the reference generator for bias ing of the analog circuits, the regulator for stabilizing the supply a nd the oscillator for the system clocking ; (2) t he signal conditioning block that deals with the weak neural signal and incorporates the functions including amplification, filtering, analog to digital conversion and DSP ; (3) t he transceiver block that communicates with the external devices The example system diagram shown in Figure 2 1 is capable of both transmitting t he neural signal information and receiving the external command Figure 2 1 An example block diagram of the neural recoding system. 2.1 Powering and Biasing Block As reporte d by most of the neural recording systems up to date the B MI systems can be

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25 powered by various methods including tethered wires, batteries and wireless link Each has its own pros and cons regarding several design tradeoffs. 2.1.1 Direct Tethered Powering Direct Tethered Powering is t he easiest way by using t he direct wired connection for power ing the system It is flexible and allows for user control of turn ing on/off/up/down the supply voltage. However, it suffers the risks of skin irritations and the pos sibility of infections. Furthermore, the use of wired connections and bulky external prosthetic devices can create many inconveniences to neuroscientists in animal behavioral studies during electrophysiology experimentation. On the other side, the animals under test might provide abnormal information if they are aware of the existence of the attachment to their body. So, powering from direct wired connection is not often used in modern BMI designs 2.1.2 Battery Powering A B Figure 2 2 Example of small b atteries A) Coin batteries, B) b attery h older s The s econd method incorporates a small battery for supply instead of direct connection which successfully avoids the side effects caused by direct tethering B ut the battery has limited capacity and lifetime, which needs replacement after operating for a certain period of time However battery with larger capacity corresponds to larger size, which increase s the difficulty for surgery or implantation For instance, the systems that use a battery a s power source [14] [12]

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26 [27] [30] have total power consumption limited within several milliwatts Figure 2 2 (A) and (B) give an example picture of both coin batteries and the battery holders respectively 2.1.3 Wireless Powering C ompar ed to the battery powered system, the wireless powered device can facilitate the experimentation s while minimizing the possibility of infections and the hardware damage. However, wireless powering has limitation on the maximum power deliver able to the device for a fixed distance which gives large constraints on the power consumption of the BMI system Therefore, the combination of rechargeable battery and wireless link shows its own merits. I t entails an inductor or antenna for energy coupling and a battery for power storage By using a rechargeable battery and refreshing through the wireless connection, the recording duration of the neural signal is theoretically unlimited. Furthermore, a system that can be powered by either a battery or the wireless link has th e option of choosing either the longer time of operation or the larger range of transmission, at the expenses of system complexity and more area required for both battery and antenna There are t wo widely utilized wireless link s in BMI systems : near field inductive coupling and far field electromagnetic coupling. If the antenna size is compatible to the wavelength (UHF/Microwave RFID), the boundary between near field and far field is given as r = 2D 2 / where D is the maximum of antenna size and is the wavelength of the carrier [31, 32] However, for electrically small antennas (LF/HF RFID and Biomedical applications), t he boundary between near field and far field is defined as The near field frequenc y is usually from one hundred kHz to ten MHz. Near field coupling experience s less absorption in human body tissue than the far field coupling. As a result, the near field coupling is widely used in wireless implant. The f ar field coupling is utilized in ultra high frequencies (UHF) and microwave frequencies, such as

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27 ISM 900 MHz and 2.4 GHz bands. Figure 2 3 shows an example functional block diagram for b oth two kinds of wireless links. The DC limiter is used for protection of the internal circuit from over voltage, and the matching network works for maximizing the power delivery to internal V SUPPLY The designs in [18] [17] [33] [28] are using the inductive powering method which greatly increases the implantation lifetime. While the designs in [21] and [20] are us ing the far field wireless powering method and their entire system power consumption s are limited to 9 W and 20 W, respectively. A B Figure 2 3 Wireless c oupling comparison. A ) Near field inductive coupling, B) f ar f ield c oupling 2.2 Signal Conditioning Block 2.2.1 Challenges and Motivation O ne of the most important parts in the brain machine interface is the front end amplifier that sense s the weak neural sig nals with magnitude range from 5 0 V to 500 V. Besides the useful but weak neural signal, there also exhibit s a background noise of around 10 V rms 20 V rms at the cellular level thus the input referred noise of the pre amplifier is always the primary design

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28 con sideration Moreover, the local field potential as large as 5mV and the drift of DC potential as large as 1~2V at the electrode tissue interface must be removed from amplification to avoid saturati on Another design consideration lies in the interface between the electrodes and the input of the neural amplifier. The impedance of the electrodes ranges from 10 k to 1 M at 1 kHz as reported by recent published designs [34] [35] [36] [37] [38] [39] The input impedance of the amplifier must be high er than the electrodes to avoid the neural signal attenuation by the electrodes. On the other hand the amplifier should have the input current noise low enough so that the electrodes will not contribute too much noise to t he amplifier output. On the system level the neural signal is required to be digitiz ed at the front end for further pro cessing and transmitting ; therefore an ADC is usually incorporated. In order for a better SNR and accuracy during digitization, the neural signal is pre amplified to the level that match es the conversion range of ADC. Another common concern lies in the fact that the input level of an ADC should not vary too much during each conversion. Typically, the input may not change by more than 1 LSB during conversion lest the process be corrupted this either sets a relative low frequency limits on such ADCs, or requires a track and hold mechanism to hold the input during each conversion. Therefore, utilizing a track and hold amplifier, or T/H_A mp as the first stage in the BMI system can meet both two requirements. T he performance of T/H_Amp is critical to the ove rall dynamic performance of the analog front end (AFE), and plays a major role in determining the SFDR, SNR, etc of the system [40] The typical structure of a t rack and hold amplifier is shown in Figure 2 4 (a) which is commonly used as the pre stage of a sample and hold ADC. However, there are some designing issues with the track and hold amplifier. First, the switches used for T/H can be made by CMOS,

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29 FET, or Diode Bridge, but there are several common problems for them: the feedthrough which means the input signal still pass ing through the switch during hold state; the noise generated by the switch s ig nal and coupled to the output ; the leakage in the holding capacitor that changes the output voltage during holding state. Those errors are inevitable but can be largely attenuated by increasing the value of the holding capacitance. However a large holdi ng capacitor (C H ) requires sufficient bandwidth (small signal) or slew rate (large signal) of the amplifier to charge the C H within a certain error during the track time Therefore, either the shorter duty cycle (track time) or larger capacitance results i n a higher requirement on both BW and s lew r ate of the amplifier The BW and the slew rate also affect the propagation delay, the acquisition delay, and the distortion. This type of error cannot be eliminated but can be improved by increasing the BW of the amplifier. Overall there lies in the tradeoff among the power consumption, the value of C H and the speed of the amplifier. A B Figure 2 4 Simplified d iagram of the T/H amplifier. A ) Conventional T/H a mplifier B ) s upply c urrent m odulated T/H a mplifier This work presents an idea that during the track time, the amplifier consumes full power and

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30 achieves large instantaneous speed to sense and transfer the input signal onto the holding capacitor, while du ring hold time the amplifier consumes negligible current to save power. As shown in Figure 2 4 (b), the signal s that control the supply current and the T/H switch are synchronized, therefore the average current consumption is reduced by a factor of T/H duty cycle D. This method theoret ically shows larger charging ability for the holding capacitor for a given current consumption and thus allows for using a larger holding capacitor to help attenuate those errors described in hold time. For the example amplifier described in [6] d uring track time when the T/H switch is closed and the active amplifier consumes full of the bias current, the instant slew rate and bandwidth is shown as below: ( 2 1 ) ( 2 2 ) Conventional track and hold amplifier at the same average current consumption I AVE has the SR=I AVE / ( 2C H ) and BW INSTANT = I AVE / ( 4A U T C H ) Thus the instant slew rate and bandwidth of the current modulated amplifier are both increased by a factor of (1/D) Those benefit s are achieved by instantaneously turning on the bias current to charge the holding capacitor during track time, and shut do wn the current consumption during hold time to save power. Thus, if the bias consumption is kept the same as for both current modulated amplifier and the conventional amplifier, the supply current modulated amplifier allows for choosing larger holding capa citor but result s the same bandwidth and slew rate, which helps reduce the error in holding state such as the leakage, feedthrough, and switching noise As for a digital acquisition system with multiple channels, several inputs are digitized and processed in parallel and finally converted into a serial data stream. In general, increased channel

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31 count s results in larger power and area consumption as well as higher data rates which poses many difficult challenges. The synchronizing technique described above gives a channel sharing idea to reduce both the area and the power consumption As shown in Figure 2 5 four channels ha ve the pre amplifier stage s with the supply current modulation scheme and the bias current for them are shared. Since the T/H clock and the supply current modulation clock a re synchronized, the inputs of four channels are amplified sequentially Thus the amplification stage can be serially process ed by the succeeding ADC stage. Figure 2 5 Supply c urrent m odulation in m ultipl exed t rack and h old s ystem 2.2.2 Noise Consideration s of Neural Amplifier There are majorly two types of noise need to be considered in amplifier design The first one is the flicker noise, which has a power spectral density inverse proportional to the frequency. Thus the flicker noise is the dominant noise contributor at a lower frequency. The second one is the thermal noise, which has a flat band power spectral density and can be reshaped by the

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32 bandwidth of the amplifier. As to the design perspective, the input referred thermal noise is determined by the current consumption and the structure of the amplifier. In order to evaluate the energy efficiency of the amplifier regarding the noise, power, and bandwidth it is important to consider noise efficiency factor first defined in [41] ( 2 3 ) Here, the I total refers to the total or effective current consumption of the amplifier, V ni_rms is the input referred noise by root mean square, U T refers to the thermal voltage, T mp is the absolute temperature in Kelvin, and k is the B olt z man constant. The amplif ier with lower NEF shows better noise performance for a given current consumption. The difference of NEF among designs is determined by the structure of amplifier, sizes of transistors, the bias current allocation, etc. 2.2.3 Comparison among Modern Neural Ampl ifiers There are majorly three types of amplifier structure widely utilized in modern neural recording amplifiers. The first type is shown in Figure 2 6 (A) which uses the capacitive coupling for amplification. This architecture remove s the DC potential at the cellular level In the feedback path, the resistor and the capacitor form a zero th at has high pass function and helps attenuate the LFP accompanying the useful neural signal [6] The second structure is shown in Figure 2 6 (B) which is similar to Figure 2 6 (A) but uses a fully differential structure so as to achieve a better common mode noise rejection. The third t ype is shown in Figure 2 6 (C) which uses a chopper stabilized technique that shifts the low frequency flicker noise to higher band and can be filtered out by following stages. There are several types of operational t ransconductance amplifier (OTA) utilized in the neural amplifier. Here two most widely used structures are introduced, as shown in Figure 2 7

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33 The first one is the cur rent mirror structure as shown in Figure 2 7 (A). The input differential pair transistors use a large W/L ratio to maximize its transconductance, so that the noise fr om other transistors contributes negligible to the total input referred noise The output stage is cascaded in order for the higher output impedance. The second type is a folded cascade structure as shown in Figure 2 7 (B). By proper sizing, larger portion of current is flown through the input different pair for a higher transconductance and thus achieves better noise performance at a given power budget [22] A B C Figure 2 6 Neural amplifier structures. A) Conventional differential to single ended amplifier, B) fully differential amplifier and C) chopper stabilized amplifier. H owever, the ratio of the bias current in the input differential pair over the bias current in

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34 the output current mirror pair cannot be set too high. Regarding the process variation which causes the mismatch between the top bias current and the bottom bias current, the bottom bias current I BIASN may be less than the half of t he top bias current I BIASP which will result in no current flow ing through the output current mirror transistors. Therefore the folded cascode structure shows better NEF performance at the expenses of higher vulnerability to the process variations. A B Figure 2 7 Schematic of the operational transconductance amplifier. A) Current mirror OTA, B) folded cascade OTA.

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35 Modern neural amplifiers address the design changes by utilizing various novel techniques. The architecture described in [6] utilizes the diode connected pseudo resistor in the feedback loop to form a high pass corner frequency and set the DC operating point. It also uses a current mirror structure for operational transconductance amplifier (OTA) and achieves a NEF of 4. In order for a better energy efficien cy a folded cascade s tructure of O TA is adopt in [22] which allocates large r bias current at the input differential pair to maximize its transconductance and therefore achieves better noise performance. Noticing the neural signal has the bandwidth up to aournd 10 kHz, the flicker noise has a large portion of entire noise power So, a chop per technique based amplifier in [23] removes the flicker noise from baseband and realized a much lower noise corner frequency. A n improved folded cascade architecture described in [42] uses the recycling scheme and report s an NEF of 5.1. The design in [25] uses the chopper stabilization topology that achieves a high input imp edance and rejects large electrode offsets The design in [43] uses a folded cascade structure to i mprove the noise power tradeoff. T he low noise OTA with both current scaling and current splitting techniques successfully avoid s the transconductance reduction in folded structure. The design in [44] employs a capacitive coupled chopper topology to achieve a rail to rail input common mode range as well as high power efficiency. A positive feedback loop is also employed in that design to boost its input impedance, while a ripple reduction loop suppresses the chopping ripple. To facilitate bio potential sensing, an optional DC servo loop is employed to suppress the electrode offset The design in [45] uses a fully integrated HPF with sub fF capacitive tuning to maximize the CMRR and a bootstrap structure that realizes large input impedance. The design in [46] significantly improves the perfor mance of any existing neural amplifier in terms of NEF by implementing a novel architecture based on partial sharing of the OTA structure among consecutive recording

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36 channels. An NEF of 3.35 is achieved for an array of four amplifiers. Moreover, a 37.5% im provement in power consumption and a reduction of the occupied silicon area are also achieved in that proposed architecture. This dissertation introduces two new structure s of track and hold amplifier, in which the current consumption of the amplifier is synchronized to the track and hold clock. During the track period, the amplifier turns on and draws current from the supply, while the input signal is amplified and transferred on to the holding capacitor. During the holding period, the amplifier freezes an d the current supply is cut off while the previous amplified signal is kept constant on the holding capacitor. Therefore, during the holding period, the entire amplifier is in off state and can be viewed as a high impedance path from the input to the holding capacitor, which provides a better isolation and less feedthrough. On the other hand, the amplifier only consumes current during the tracking period, therefore for a given power budget, the bias current of the amplifier is boosted up d u ring tracking period, which result s in larger instantaneously slew rate and BW. So the amplifier acquires a better charging ability to the holding capacitor, which allows for using a larger holding capacitor to achieve less pedestal error and switching no ise compared to the conventional amplifier for the same power budget. To test this idea, we built two types of T/H_A mp by using the UMC 130nm technology, the supply curre nt modulated amplifier and the four channel time multiplex ed amplifier. The ir measurem ents result shows the performance at various duty cycles and T/H frequencies as described in Chapter 3 2.3 Trans ceiver Block F or a long term implantable neural recording system the w ireless telemetry is an essential building block. It helps reduce the risk of infection or skin irritation increase the mobility of the

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37 behavi ng animal under test and extend the duration of the recording lifetime However, there exist several challenges for the wireless link. First, t he transmitted signal often require s s ufficient data rates to convey the information from the electrode tissue interface with enough resolution. Second the power consumption of the transmitter and the receiver is added to the entire system power budget. The recent designs of the transceiver e xhibit a significant portion of entire system power consumption Thus t he design in [47] uses an efficient approach which makes t he transceiver link optimized as an asymmetric link where the minimal power is draw from the recording side but t he complexity and high power is applied to the external side. In this section we will show several wireless communication strategies and present their pros and cons In general, there shows i ncreasing demands on low power, high data rate, and transcutaneous for wireless telemetry interfaces In the remaining of this section two types of transmitter are described: the active transmitter an d the backscattered transmitter. Also introduced is the receiver block and its modulation sc heme. 2.3.1 Active Transmitt er Active transmitting is a straightforward method of conveying the neural signal wirelessly to the external reader. It utilizes a high frequency oscillator on chip and up converts the digitized data onto the RF band and deliver the n eural signal out of the chip. The transmission range by this approach is much higher than the backscattering method since the uplink signal only encounter s one way loss. However, active transmitter consumes very high power in order to generate the highest RF signal on chip. In the reported systems [17] and [16] that use active transmitter, their active transmitters consume nearly half of the total power consumption of the entire system 2.3.2 Backscattered T ransmitter Compared to the active transmitter, the backscattered transmitter shows better energy efficien cy. It transmits the signal by toggling the matching states between the antenna and the tag

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38 so that the reader can demodulate the reflected power and extract the useful data This method has much lower power consumption by shifting the burden of generating the highest frequency to the external device, while the transponder is only required to generate a reference clock to create a side band at the RF c arrier. However, the communication range of the backscattered transmitter is much lower than the active transmitter since the received signal at reader side suffers both up link and down link power loss. The backscatter transmitters reported in the systems [21] [20] [11] contribute negligible power to the entire system power budget 2.3.3 Receiver There are kinds of settings in neural recording systems that may require ex ternal control by user, for instance, the gain and the bandwidth of amplifier the sampling rate of the data conversion, channel selection, and so forth. It is necessary to set up a wireless data link from the external reader to the recording transponder. For example, the system in [17] can adaptively choose one of the 100 amplifiers to sense the neural signal by external control through the receiver chain The receiver may probably entail the function s including rectifier, buffer, clock & data recovery (CDR), decoder, and some register s for the storage of the transmitted data. T h e data being captured by the receiver chain has various patterns that form a packet T he header is often included in the data packet to mark the boundary of the serial data. To make sure the recovere d data is correct before upgrading the system setting s the C yclic R edundancy Check (CRC) can be appended to the system controlling data to verify the validity of the received signal [16] In a full duplex operation system there must be sufficient attenuation of the TX noise being coupled into the receiver chain To distinguish the TX noise and the useful RX signal, one way is to locat e them at different band s so that they can be filtered out separately [13] [33]

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39 2.3.4 Modulation Scheme There are lots of modulation schemes used in the wireless communication realm however only a portion of them are suitable for the low power neural recording application. The different modulation schemes are shown in Figure 2 8 Figure 2 8 Comparison among different modulation modalities. The most widely used modulation scheme s are the ASK and OOK which change the amplitude of the carrier The example designs in [18] [33] [28] are using the OOK for the receiver data link It is popular due to its simplicity and energy efficiency Other methods such as FSK by switching the frequency and the PSK by switching the phase of the carrier is not as popular as AS K scheme since they require more complicated de modulator and thus more power consumption especially in a passive transponder. However, t he FSK and PSK are able to provide continuous power to the device compared to the ASK if the carrier is also used for powering For example, t he

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40 design in [17] that utiliz es the FSK modulation for the data link takes the advantage of continuous delivery of the wireless energy while the designs in [14] [12] are using the FSK modulation scheme for the battery powered system Table 2 1 Comparison among modern neural acquisition systems Author Wise [18] Harrison [17] Judy [14] Najafi [12] Najafi [33] Year 2008 2007 2006 2005 2004 No. of Channel 64 100 6 7 64 Power Source Inductive Inductive Battery Battery Inductive Forward Data Telemetry FSK ASK ASK Carrier Frequency 4MHz/8MHz 2.64MHz 5.12MHz Receiver Data Telemetry OOK FSK FSK F SK OOK Carrier Frequency 70 200MHz 433MHz 916MHz 94 98MHz 88 108MHz Front End Gain 60dB 60dB 46dB 43.7dB 40dB Low Cutoff (Hz) 10 100Hz 300 a few Hz a few Hz 10 High Cutoff (Hz) 9.1K 5k 1k 5k 10k Power Consumption 14.4mW 13.5mW 66mW 2.05mW 12.7mW Table 2 1. Continued Author Mohseni [27] Ghovanloo [28] Liu [30] Otis [11] Otis [21] Year 2011 2010 2009 2009 2010 No. of Channel 8 32 128 1 1 Power Source Battery inductive Battery Battery Far Field Forward Data Telemetry FSK FSK UWB FSK UID Carrier Frequency 433MHz 433MHz 4GHz 300 450MHz 900MHz Receiver Data Telemetry OOK PIE Carrier Frequency 915MHz 900MHz Front End Gain 51 66 67.8/78dB 60dB 38.3dB 38.5dB Low Cutoff (Hz) 1.1 525 0.1 1000 0.1 200 0.023 0.2 High Cutoff (Hz) 5.1 12 8k 2k 20k 11.5k 230 Power Consumption 375uW 5.85mW 6mW 0.5mW 9.2 W Another modulation scheme also used in BMI system is t he PWM method which encode s the data by different duty cycle s of the modulation signal This type of non coherent demodulation

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41 scheme can further lower the power consumption at the transponder side by incorporating the clock information into the carrier. Instead of changing t he pulse width like PWM t he PPM by switching the position of a short pulse provides a better continuous power delivery for a passive transponder To compare the performance at the system level, Table 2 1 lists some important specifications among the state of the art. In this work, we present two neural recording systems that both use the ASK modulation in the receiver chain and their detailed performance will be descr ibed in Chapter 5 and Chapter 6, respectively.

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42 CHAPTER 3 3 ENERGY EFFICIENT AMPLIFIERS This chapter focuses on the design of low noise energy efficient neural amplifier s Three new amplifier topologies are described ; each is described in detail in a section. Those three amplifiers are characterized with parameters including gain, bandwidth, total harmonic distortion, power consumption, input referred noise, CMRR, PSRR, crosstalk, and the noise efficiency factor. Before introducin g the new amplifier st ructures, the test setup for the amplifier s is shown in Figure 3 1 and the measurement procedure is described as below. Figure 3 1 Measurement s etup for a mplifier The gain and bandwidth is tested by the Dynamic Signal Analyzer (DSA) a s shown in Figure 3 1 by closed switches S1 S3 and open ed switches S2 S4. T hen u se the source terminal of the DSA to feed the pseudo random noise to the input of the amplifier. Because the neural amplifier is ea sy to be saturate d even at several mV, the attenuator with 40dB is inserted between the dynamic signal analyzer and the input of the amplifier The dynamic signal analyzer has the division math function, so the bandwidt h and gain is acquired by dividing th e output spectrum with the input source spectrum. The Total Harmonic Distortion (THD) and crosstalk are also tested by the DSA as shown in Figure 3 1 by closed switches S1, S3 and open ed switches S2, S4 By feeding a sinusoid signal of

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43 1 k Hz (or the pass band signal) into the amplifier, the output spectrum will show the amplitude at all it s harmonic frequencies. By s umming up the power of all the harmonic s at the output and dividing the summed power by the input power, the result is the total harmonic distortion at 1 kHz The cross talk is measured in a similar way but by recording the outp ut spectrum due to the input of a nearby channel. The cross talk result is acquired by dividing the cross gain between channels with the nominated differential gain The input referred noise is measured by the DSA as shown in Figure 3 1 by closed switches S1, S3 and open ed switches S2, S4 By shorting the input terminal and the reference terminal of the amplifier together, the output spectrum through DSA is then measur e d Then the input referred no ise can be acquired by dividing the output spectrum with the differential gain. The noise must be measured in a shielded cage and the amplifier must be powered through a battery. The CMRR is measured by the DSA as shown in Figure 3 1 by closed switches S1, S2 and opened switches S3, S4 F irst short the input and the reference terminals of the amplifier Second, f eed a sinusoid signal of 1 k Hz (or the pass band signal) into the amplifier. T hird, divide the output spectrum at 1 k Hz by the input amplitude at 1 kHz and then further divide the result by the differential gain the result is CMRR at 1 KHz The PS RR is measured by the DSA as shown in Figure 3 1 by closed switches S2, S3, S4 and opened switch S1 First, s hort both input and reference terminal s of the amplifier to ground. Second, f ee d a sinusoid signal of 1 k Hz (or the pass band signal) in series with the power supply Third, divide the output spectrum at 1 k Hz by the input amplitude at 1 k Hz and then further divide the result by the differential gain t he result is PSRR at 1 KHz 3.1 Cascaded Amplifiers for Multi Channel Rec ording The first methodology presented in this chapter focus on the structural improvement of the neural amplifier. Noticing that the neural acquisition system aims at simultaneous ly rec ording of

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44 neural signal from multi sites, this section introduce s a topology that reuses the bias current between channels. 3.1.1 C urrent Reuse Amplifier Structure A B Figure 3 2 Comparison of the i nstrumental a mplifier t opologies A) C onventional s tructure B) p roposed s tructure Figure 3 2 (A) shows a conventional topological arrangement of two independent amplifier channels, each consisting of a high input transconductance ( G m ) stage followed by a high output impedance stage. A high Gm is required for the input stage transistors to optimize the input referred thermal noise performance This can be accomplished by using of large W/L input transistors and operating them in the subthreshold regime. The output stage will typically consist

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45 of cascaded transistors operated in strong inversion. From a biasing viewpoint, a larger portion of the current consumption is budgeted for the input stages whereas the output can be biased at lower current levels. This suggests that a simple current reuse strategy can potentially yield significant power savings over a large number of amplifier channels. In the proposed amplifier design, shown conceptua lly in Figure 3 2 (B) the input stages of the two independent instrumental amplifier ( IA ) channels are cascaded (or stacked) and the current from the top input cell is reused by the bottom input amplifier cell. The corresponding P stage and N stage amplifier implementations are shown in Figure 3 3 (A) and (B) respectively. The sizes and the bias current of all the transistors for both P stage and N stage amplifiers are listed on Table 3 1 The P stage input operates from VDD to V MID (nominal ly (VDD+VSS)/2) and the N stage input operates from V MID to VSS. The input to output stage bias current ratio is chosen to be approximately 2.5 :1. Therefore, the power savings by using the current reuse technique is ~35% over the conventional approach. In addition, the stacked input stages maintain high input transconductance for good noise perf ormance and high open loop gain The gain and bandwidth is approximately to be Eq. ( 3 1 ) and Eq. ( 3 2 ) respectively. ( 3 1 ) ( 3 2 ) Here CL is the effective capacitance at the output of the first stage amplifier, Gm is the transconductance of the input differential pair. The topological arrangement of the amplifiers is in part enabled by the Li ion cell battery supply of 3 4V, which provides sufficient headroom for the cascaded input stages. The output stage operates from the full supply range and additional dc level conversion is not required. Each IA consists of a high gain P input (or N input) st age that is

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46 input ac coupled to reject the dc offset, and a second lower gain P input (or N input) stage. A B Figure 3 3 The p roposed a mplifier s tructure A) P s tage amplifier, B) N s tage amplifier In order for multi site recording simultaneously, an 8 rows and 4 columns IA array has been built with the structure shown in Figure 3 4 and the layout shown in Figure 3 7 Each row has two P stage amplifiers and two N stage amplifiers cas caded with dedicating biasing generated on chip A voltage regulator is shared among all 32 (8x4) IA channels to generate V MID for the

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47 internal mid dle point reference, and incurs in negligible power dissipation overhead. Each amplifier site measures 250 m by 788 m and contains a bond pad for flip chip connection onto an underlying substrate or electrodes. For i nitial bench top testing the IC can be assembled in a QFP package and mounted onto a PCB with 4 IA channels accessible. Figure 3 4 The structure of 32 channel IA array The schematic of the reference generator is shown in Figure 3 5 The constant GM current gene rator provides the bias current for the analog parts The V MID reference is generated and used as the ground for P stage and the supply for N stage. The V MID reference must be able to both source and sink current because of the random mismatch between the P stage and N stage amplifiers. Therefore the V MID generator uses a complementary structure with both PMOS and NMOS input differential pairs The simulated output impedance is around 0.8 Ohm, which is low

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48 enough for stabilizing the reference. The simulated noise on V MID reference is around 25 V, which is negligible since the noise is in common mode to amplifiers The V MID reference generator consumes around 125 A current which is very large compared to the current consumption of the amplifiers so future revision may be required for less power consumption since larger output impedance and noise are still acceptable Figure 3 5 The schematic of the reference generator. Figure 3 6 The schematic of the local reference buffer. As shown in Figure 3 4 each row of the IA array is biased by a local reference buffer The

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49 local reference buffer is used to reduce the mismatch between amplifiers due to long distance routing. As shown in Figure 3 6 the references VB1 VB4 for the ampli fiers in the same row are locally generated by a single reference B ias P. Table 3 1 Transistor sizes in both P stage and N stage amplifiers Devices P stage Amplifier W/L (m) I D (A) Devices N stage Amplifier W/L (m) I D (A) M0 45/7.5 8.34 M0 45/7.5 8.34 M 1 M2 432 / 4.2 4.17 M 1 M2 432 / 4.2 4.17 M3, M4 60/21 .0 4.17 M3, M4 60/18 4.17 M5, M6 9/7.5 1.67 M5, M6 9/7.5 1.67 M7, M8 384/0.6 1.67 M7, M8 384/0.6 1.67 M9, M10 12/2. 3 1.67 M9, M10 12/2.25 1.67 M11, M12 5.4/18 .0 1.67 M11, M12 5.4/18 1.67 Table 3 2 Comparison between P stage and N stage amplifiers by simulation Parameter P stage N stage Current Consumption 7.5 A 7.5 A Gain 59.3 dB 59.4 dB HPF Corner frequency 2. 2 Hz 2. 2 Hz Bandwidth 7.1 kHz 7.9 kHz Noise Floor Integrated Noise 4.0 V 4.7 V NEF 5.1 5.6 Input Impedance at 1 kHz 62.0 M 62.0 M VMID Noise Attenuation 72.4 dB 72.5 dB PSRR 71.3 dB 69.9 dB CMRR 87.3 dB 87.5 dB The comparison of the simulation result between the N stage and the P stage amplifiers is shown in Table 3 2 B oth amplifier s draw the same bias current and result in similar parameters including closed loop gain, HPF corner frequency, PSRR CMRR and rejection to VMID noise But the bandwidth and the input referred noise are slightly different. The P Channel amplifier uses the PMOS as the input differential pair which has much less flicker noise compared to the N stage amplifier while the N stage amplifier uses NMOS as the input differential pair that results in larger transconductan ce compared to PMOS transistor for the same size and bias current. As indicated in Eq. ( 3 2 ) the bandwidth is proportional to the transconductance of the

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50 input diffe rential pair and inverse proportional to the output capacitance. Regarding both P stage and N stage amplifiers have the sane value of output capacitance, the N stage amplifier has larger bandwidth due to larger transconductance. Both P stage and N stage am plifiers have simulated input impedance around 62.0 M at 1 kHz, which is much higher than the impedance of the electrodes to avoid the neural signal being attenuated. 3.1.2 Measurement Result Figure 3 7 Die p icture of the 4X8 a mplifier a rray T h is design was fabricated through 2P CMOS process with die picture shown in Figure 3 7 The measured IA transfer funct ion of P stage amplifier is shown in Figure 3 8 ( A ) The amplifier ha s a measured mid band gain of 56dB and bandwidth of 25m Hz 1.25k Hz The power dissipat ion of 22.5 W/ channel is not measured directly but estimated from the simulation result The total equivalent input noise of the amplifier can be expressed as : ( 3 3 ) H ere E t is the thermal noise of the source resistance RS E n and I n are the equivalent input voltage and current noise sources of the amplifier respectively Figure 3 8 ( B ) shows the measured input referred noise spectrum. Integration under this curve from 25 mHz to 100 kHz

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51 yields Eni ~ 100Hz. A B Figure 3 8 Measured P stage a mplifier p erformance A) G ain and p hase B) i nput r eferred voltage n oise The equivalent voltage ( En ) and current ( I n ) noise parameters are found by measuring E ni 2 at 1 kHz as a function of R S as shown in Figure 3 9 Setting R S =0 yields E n =70.7 nV/ Hz. The I n component is found for large R S resulting in I n =73 fA/ Hz, which yields an optimal noise source resistance R OPT of ~1M suitable for high electrod e impedance.

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52 Figure 3 9 Measured i nput r eferred v oltage n oise ( s quared) versus the s ource r esistance 3.2 T ime Multiplex ed A mplifier Th is section describe s another way of improving the energy efficiency in amplifier design Modern n euroscientists and researchers in biomedical engineering require the BMI systems being capable of acquiring the neural information from a large population of neurons simultaneously. Thus the transition or multiplexing of neural signals from parallel channels into serial data stream is required for signal processing and wireless transmission. In general increased channel count s results in larger power and area consumption as well as higher data rates which pose many difficult cha llenges. Different approaches of multiplexing show different performance regarding the tradeoffs among area, power, noise and number of channels. Several multiplexing strategies used in analog front end (AFE) are compared in Figure 3 10 The MUX at an earlier stage leads to better area and power saving since the stages succeeding the MUX do not replica with channel counts and are shared among all the channels. However multiplexing at earlier stage may require more noise considerations while switching among

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53 channels. For example the design in [19] uses the structure shown in Figure 3 10 (A ) that has a separated amp lifier and ADC for each channel, while the designs in [16] and [30] have a MUX at the output of the amplifier and share a single ADC as s hown in Figure 3 10 ( B ) The former does not exhibit area and power efficient as the latter but the multiplexing happens at the digital signal levels which shows better immunity to switching noise. If the MUX stage locates at the first stage, as shown in Figure 3 10 ( C ), the system may have th e best area and power saving, however this method will generate switch ing noise directly to the weak neural signal (20V 500V) level and may even saturate the amplifier. A B C D Figure 3 10 Comparison among the m ultiplexing s trateg ies at d ifferent s tages A) MUX at ADC output, B) MUX at amplifier output, C) MUX at amplifier input and D) MUX inside the amplifier. In this section we will introduce the method shown in Figure 3 10 ( D ) which has multiplexing function merged inside the amplifier. The front end has large transconductance (Gm) at the input stage of the amplifier and the switch ing behavior happens after the Gm stage, which

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54 will generate the switching current noise at the amplified current level We also use differential structure inside the amplifier to force the switching noise in common mode. 3.2.1 The Structure of 4 Channel Time M ultiplexed AFE Figure 3 11 Schematic of the 4 c hannel AFE The entire AFE is comprised of two gain stages and one 8 bits SAR ADC as shown in Figure 3 11 The shared OTA is time multiplexed with four independent input channels, controlled by four non overlapping clocks S1 S 4 and their complements S1b S4b Each of the four channels takes turn s to occupy the OTA to amplify the input signal and store the signal onto its output capacitor C H during track phase. When the input of any channel is not connected to the OTA, the output voltage on C H of that channel is hold constant. The mid band gain, n ominally 40dB, is set by (

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55 3 4 ) The d iode connected PMOS pseudo resistor R and the capacitor C2 implement a high pass filter that helps attenuate the local field potential accompanying the useful neural signal. F ollow ing the first stage amplifier is a passive tuning filter which is controlled by four bits. The second stage amplifier utilizes a conventional structure and consumes much less power S ince the noise contribution at the second stage is almost negligible while referred to the input of the AFE this stage can be biased at lower current level The second stage provides an additional gain of 14dB. As shown in Figure 3 11 t he REF terminals of all four channels are shorted together in the layout so only one reference electrode is required for all four channel s. If different reference levels are required for sensing four input channels the REF terminals can be separated with four electrodes so that each channel can work independently with different reference voltages Figure 3 12 Schematic of the f our c hannel t ime m ultiplexed OTA Throughout a sampling period (T), each channel in the time multiplexed AFE operates in

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56 either track (T/4) or ho ld (3T/4) phase For the channel in track time the path through the the appropriate clock signals and th is selected channel utili zes all of the OTA bias current. By averaging the power consumption over the entire T/H period, time multiplexing approach effectively decreasing the current consumption per channel by one fourth Table 3 3 Transistor s izes for the OTA in t ime m ultiplexed a mplifier Devices W/L (m) I D (A) Gm (A/V) Inv. Coeff. Gm/I D (V 1 ) V EFF (mV) MP0 80/2 .0 4 102 2.1 18.1 38 MP1_1/2/3/4, MP2_1/2/3/4 240/0.5 2 6 8 0. 1 23.5 2 MP3_1/2/3/4, MP4_1/2/3/4 4/0.8 2 4 8.6 1.5 502 MP5/6 6/4 .0 2 22 28.7 7.7 187 MP7/8 48/1 .0 2 58 0.9 20.2 18 MN1/2/3/4 4/6 .0 2 3 2 20.9 11.1 114 MN5/6 36/1 .0 2 67 0.4 23.3 5 Figure 3 12 shows the schematic of the current mirror OTA used in the 4 ch time multiplexed amplifier. The bias current and the reference voltages were generated on chip Although the circuit topology has 4 input channels sharing a single OTA, each channel has the standard structure when this channel is selected active during on time. The sizing of the transistors is critical for achieving low noise for a given low power budget. The bias current is set to 4A, giving all devices drain currents of 2A. The parameters for the transistors in the O TA are listed on Table 3 3 The transconductance Gm and V EFF are acquired by simulation result (since hand calculation is not right in th is UMC130nm process at such low power level). In order to evaluate each transisto r operation region in either weak, moderate, or strong inversion, we calculate the moderate in version characteristic current given by ( 3 5 ) Where U T is the thermal voltage K T mp /q and is the subthreshold gate coupling coefficient.

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57 The inversion coefficient ( IC ) for each transistor may then be calculated by the ratio of the drain current to the moderate inversion characteristic current, as follows: ( 3 6 ) A device having IC >10 operates in the strong inversion region and has a transconductance proportional to the square root of the drain current. A device having IC < 0.1 operates in the weak inversion (subthreshold) region and has a transconductance proportional to the drain current. From Table 3 3 the input differential pair tran sistors (MP1/2) are both operating in weak inversion. The current mirror transistors MN1/2/3/4 and MP5/6 are al l in strong inversion. As described in Chpater2 transistor that works in deep weak inversion achieves larger transconductance for a given curren t consumption compared in strong inversion. Thus the transconductance ratio of MP1/2 over the current mirror transistors is maximized, which means this OTA is sized in order to attenuate the noise contribution of the transistors other tha n the input differ ential pair. For each of the four channel s the simulated input impedance of the amplifier is around 16.7 M at 1 kHz, which is much higher than the impedance of the electrodes so the neural signal will not be attenuated by the electrodes Moreover, the noise simulation shows that the noise floor is negligibly increased by connecting a input current noise of the amplifier can be neglected by using the e lectrodes with impedance up to 3.2.2 Operation of Time Multiplex ing 3.2.2.1 Operation d uring H old Time T he effective circuit for one of the four channel s is shown in Figure 3 13 The switch S and S B have duty cycle of 25% and 75%, respectively. During hold phase, switch S is open and S B is closed. T he feedback loop is broken, and the previously sampled voltage is held constant on

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58 capacitor C H1 at the output of the OTA. Since the switch disengages the feedback loop, the signal coupling from the input to C H1 is largely attenuated by a high impedance path which is formed by R and C 2 in parallel However there is large parasitic capacitance at the input of the OTA C PAR N ote that the volta ge on C PAR effectively follows the input voltage through the capacitive divider C 1 and C PAR during hold ing time; however, the overall operation is negatively affected due to the isolation prov ided by the high impedance path Figure 3 13 Equivalent s chematic of o ne c hannel This topology also eliminates switches from the sensitive input path and converts these switches, as shown in Figure 3 12 to a common mode topology by placing them inside the OTA. The switching noise is added to the amplified current level instead of the sensitive input node, so the noise is slightly amplified and the output voltage on the hold ing capacitor is less affected During hold time, t he second gain stage amplifies the voltage from C H1 and store it on to capacitor C H2 At this time, the ADC is disconnected to this inactive channel. 3.2.2.2 Operation d uring T rack Time During track time, t he switch S is closed and S B is open, thus the feedback path is enable d The negative feedback loop forces the inverting terminal of the OTA (a nd thus the voltage on

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59 Cpar ) to be the same potential as the non inverting terminal known as virtual shorting. Therefore, the charge stored on C PAR during holding time is transferred to C 2 right after the loop is formed. Since there is negligible charge leaking to ground during holding time, all the extra charge stored on C PAR by voltage divider of C 1 and C PAR during holding time will be coupled to C 2 The capacitor coupling will keep the gain ratio to be C 1 /C 2 so the final gain from input to output C H1 remains the same. The second stage amplifier is disconnected from C H2 during track time and t he voltage on C H2 of this active channel is digitizes by ADC 3.2.3 Measurement Result Figure 3 14 Die p icture of the 4 c h annel t ime m ultiplexed AFE To test the energy efficiency of the proposed structure the amplifier was fabricated by using UMC130 nm technology The die picture is shown in Figure 3 14 the averaged core area for each channel is around 0.06 mm 2

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60 A B Figure 3 15 M easurement result of the 4 ch time multiplexed amplifier and the single channel amplifier without time multiplexing. A ) F requency r esponse B ) input referred n oise Figure 3 15 (A ) shows the measured frequency response of the AFE The measured mid band gain is 53.5dB. To compare, also shown in Figure 3 15 (A ) is the Gain Bandwidth of the amplifier without time multiplexing which has the bias current kept on for the entire period As will be explained later in section 4 4 the 4 channel time multiplexing will result in the

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61 bandwidth reduced to 1/4 of the original non multiplexed The noise spectr al density is shown in Figure 3 15 (B ) I t supports the fact that channel s multiplexing increase s the thermal noise floor due to high frequency noise being alias ed down to the baseband as will be described in section 4 5 However, the overall noise efficiency factor remains the same by using time multiplexing. From the measurement result the overall noise spectr al density is dominat ed by the flicker noise and the final NEF is 5.8 Figure 3 16 The c ross t alk measurement b etween t wo nearby c hannels Table 3 4 Characteristic of 4 c hannel t ime m ultiplexed a mplifier Parameter Value Technology UMC 130nm Supply voltage 1 V Supply current per channel 8/4 A Modulation duty cycle 25% Channel # of Multiplexing 4 Gain (1 st stage) 40 dB Bandwidth 9.5 kHz Low frequency cutoff ~100 Hz Input referred noise 10.5 V Noise efficiency factor 5.8 THD ( 1 .5mVpp input) 0.6 % CMRR > 50 dB PSRR > 6 0 dB Crosstalk >50 dB

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62 The crosstalk is measur ed by feed ing the 1 k Hz signal into a selected channel and measure the output at 1 kHz from both this channel and its adjacent channel. Figure 3 16 shows the attenuation between those two channels is larger than 50dB The Summarize d performance is list in Table 3 4 To compare, the simulated CMRR and PSRR are 46 dB and 41 dB, respectively. 3.3 S upply Current Modulated Amplifier Th is subsection describe s the third way of improving energy efficiency in amplif ier design by merging the role of track and hold function with supply current modulation. 3.3.1 Fully Differential Amplifier with S upply C urrent M odulat ion Figure 3 17 Schematic of the T/H_Amp and the b uffer stage. Figure 3 17 shows the structure of the proposed two stage amplifier T he first stage uses a fully differential structure. The coupling ratio of C1 over C2 sets the gain of the a mplifier. The resistor R implements a DC feedback and sets the DC output operating point The feedback resistor R is implemented by a diode connected pseudo resistor. There are two switches at each of the differential outputs which perform the task of T/H mechanism with the holding capacitor C H

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63 The capacitor C H is also used as the compensation capacitor for stabili zing the first stage amplifie r. The second stage amplifier uses a conventional current mirror structure which provides additional gain and converts the differential input to a single ended output. T he output of the T/H mechanism contains the noise at harmonics of the T/H frequency (see section 4 5 ) By setting the bandwidth of the second stage amplifier l ower than the T/H frequency effectively attenuate s both the output non zero harmonics and the switching noise generated in the first stage. As the conclusion of section 4 5 suggests we use a much higher T/H frequency than the bandwidt h of the first stage amplifier, so the higher order input harmonics are attenuated by a SINC function that has a zero crossing frequency inversely proportional to the T/H duty cycle. 3.3.2 S upply Current Modulated OTA Figure 3 18 Schematic of the s upply c urrent m odulated OTA Figure 3 18 shows the schematic of the OTA used in the T/H_A mp T he size s and bias current of all transistors are liste d in Table 3 5 The OTA uses a folded casc o de structure to allocate larger bias current to the input differential pair than the output stage The common mode feedback depicted on the right maintains the common mode output voltage at half of the supply so as to maximize the output dynamic range. The fully differential structure a nd the matched layout

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64 attenuate the switching noise in common mode The input differential pair P1 and P2 are large PMOS transistors ( W/L ) in order to maximiz e their own t ransconductance at a given bias current and thereby attenuat e the noise contribution f rom other transistors The large size PMOS also helps red uce their own flicker noise. Table 3 5 Transistor sizes for the OTA in supply current modulated amplifier Devices W/L (m) I D (A) P7 2/1 4.4 P1 P2 48 0/ 2 2.2 N1, N2 2/20 3.4 N3, N4 0.5/20 0.9 N5, N6, N7, N8 2/10 0.4 N9, N10 40/0.5 1.2 P3, P4 3/4 1.2 P5, P6 2/10 0.9 P7, P8 8/0.5 1.2 The main difference of the proposed OTA used in a T/H_A mp from the OTA used in conventional amplifiers lies in that the former modulates the bias current between two levels, as shown on the left of Figure 3 18 The modulation sig nal is synchronized to the controlling signal of the T/H switch S D During track time the amplifier is fully on the OTA consumes full of the bias current, and the input signal is amplified and stored onto the holding capacitor C H D uring hold time, the output of the OTA is disconnected from C H and the amplifier consume s only a little bias current to maintain its DC operating point so as to avoid large signal slew ing during the transition between modes. For our design, we set the bias current ratio of I B 1 /I B2 to be 25 for high/low biasing T he current modulation scheme reduces the total current consumption by averaging the entire period. For example, if the T/H mechanism uses a 10% duty cycle then the average current consumption drop s to around 10% of it s peak value. The simulated input impedance of the supply current modulated amplifier is around 25 M at 1 kHz, which is much higher than the impedance of the electrodes so the neural signal will not be

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65 attenuated by the electrodes. Moreover, the noise simulation shows that the noise floor is negligibly increased by connecting a f the amplifier, which means the input current noise of the amplifier can be neglected by using the e lectrodes with impedance up to 3.3.3 M easurement R esult Figure 3 19 Die p icture Figure 3 20 Me asured transfer function of T/H_ Amp with d ifferent d uty c ycles To test the energy efficiency of the proposed structure the amplifier was fabricated by using

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66 UMC130 nm technology The die picture is shown in Figure 3 19 It has a total area of 0.7 mm 2 with the core area of T/H_A mp occupying only 0.14mm 2 The measured trans fer functions are shown in Figure 3 20 which has the gain by both the first stage and the second stage amplification The effective low pass corner frequency is proportional to the duty cycle ( see section 4 4) The high pass corner frequency set by the time constant of R and C 2 (shown in Figure 3 17 ) is located at around 100Hz which helps filter the local field potential ( LFP ) that accompanying the neural signals. Figure 3 21 Measured i nput r eferred n oise of T /H_Amp with d ifferent d uty c ycles Table 3 6 Noise p erformance c omparison among different d uty c ycles D uty Cycle BW Bias Current Noise NEF 6.25 % 5. 3 kHz 0.9 A 5.9 V 2. 9 12.5 % 7.8 kHz 1.4 A 5.6 V 2. 9 25 .0 % 11.6 kHz 2.4 A 5. 4 V 3.0 50 .0 % 18.9 kHz 4.4 A 5.1 V 3. 0 100 % 24.1 kHz 8.5 A 4.6 V 3. 3 low power 10 .0 kHz 1.4 A 8.4 V 3.8 14.1 % 8.0 kHz 1. 4 A 5. 8 V 2.9 The input referred voltage noise is compared among different T/H duty cycles in the bode plot shown in Figure 3 21 with the values listed in Table 3 6 T h e duty cycle of 100% represents the

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67 supply current being kep t on for the entire period without supply current modulation. The NEF is almost the same among different duty cycles, which supports the analysis in section 4 5 Table 3 6 also indicates that the amplifier without employ ing the supply current modulation (100% duty cycle) has a higher NEF compared to the one with supply current modulation This is because transi stor level modulation lowers the flicker noise. Figure 3 22 Noise comparison between operation with and w ithout s upply c urrent m odulation for the s ame current c onsumption T o further support the analysis in C hapter 4 we tested the amplifier biased at a directly reduced current level ~1 A Figure 3 22 shows the comparison result of two input referred noise spectrum s, one uses direct reduction of bias current and the other uses supply current modulation. A s listed in the last two rows of the Table 3 6 both methods consume about 1. 4 A have measured bandwidth s of 10k and 8k, have total input referred noise s of 8. 4 8 and have NEF s of 3.8 and 2.9 resp ectively. The reasons for the improvement s by using the supply current modulation scheme are twofold : first, the cycling of a MOS transistor from strong inversion to

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68 accumulation region reduces its intrinsic 1/f noise [ 5 ], and second, supply current modulation reduces the noise contri bution from the transistors other than the input differential pair Figure 3 23 further supports this explanation by comparing the NEF by both simulation and experimental results Table 3 7 summarizes the performance of the T/H_A mp by using the supply current modulation scheme with a duty cycle of 12.5 %. The total gain of 61.2dB includes 40 dB for the first stage and 21.2 dB for the second stage To compare, the simulated CMRR and PSRR are higher than 100 dB and 86dB, respectively. Table 3 7 Characteristic of s upply c urrent m odulation a mplifier Parameter Value Technology UMC 130nm Supply voltage 0.8V~1.5V Channel number 1 Supply current 1. 4 A Modulation duty cycle 12.5% Gain (first stage) 40 dB Bandwidth 7.8 kHz Low frequency cutoff ~100 Hz Input referred noise 5. 6 V Noise efficiency factor 2.9 THD (0.5mVpp input) >40 dB CMRR >65 dB PSRR >50 dB Area 0.15 mm 2 Th e proposed amplifier uses a more scaled down technology (130nm) and exhibits the advantages at the system level for the entire brain machine interface since the power dissipation for digital signal processing and wireless communication is also reduced by advanced technology In addition, such low power dissipation allows the system to use large r channel numbers and improves the performance of the wireless powering or increases the com munication range as an example application shown in [13].

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69 A B Figure 3 23 NEF c omparison between d irectly reducing of bias current and s upply c urrent modulation. A) Simulation result, B) measurement result. To support our fundamental assumption that the NEF is maintained only if the T/H frequency is much higher than the intrinsic bandwidth of the amplifier upon which the entire analysis in Chapter 4 rests Figure 3 24 and Figure 3 25 show, respectively, the measured transfer function and the input noise PSD at different sampling frequencies The total input referred noise falls at a higher T/H frequency because the SINC function attenuat es the input harmonics (see

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70 section 4 4) Thus, only i f the T/H frequency is much higher than the i ntrinsic bandwidth of the am plifier is the conclusion of maintaining the NEF by using the supply current modulation scheme true Figure 3 24 Me asured t ransfer f unction of T/H_A mp with d ifferent T/H f requencies Figure 3 25 Measu red i nput r eferred n oise of T/H_Amp with d ifferent T/H Frequencies

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71 CHAPTER 4 4 M ATH E MATICAL ANALYSIS OF T/H AMPLIFIER In order to investigate the switching effect s in the time multiplexed and supply current modulated amplifiers, this chapter investigate s their transfer function and the noise performance. T he four channel time multiplex ed amplifier senses each input signal for one fourth of the entire period and then fr eezes the output for another three fourth of the period. T he supply current modulat ed amplifier senses the input signal during the on phase and freezes the output during the off phase. Therefore, those two amplifier s ha ve the same behavior of track and hol d function. So in this work they are both called track and hold amplifier (T/H_Amp) and are analyzed together in this chapter. 4.1 Equivalence between T/H_Amp and T/H_RC Filter The T/H_Amp could not sense the input with infinite speed and is limited by its o wn effective transconductance. Therefore the overall behavior of amplifier serves as a resistive conduction path with a nominated gain. In order to explain the resistive effect of the amplifier, it is important to first compare the transfer function between an amplifier and a RC filter. A B C D Figure 4 1 Simplified RC model for amplifier. A) Amplifier structure, B) RC f ilter structure C) T/H_Amp structure and D) T/H_RC f ilter structu re. Figure 4 1 (A ) shows a typical amplifier consisting of an OTA with transconductance G m a feedback path with ratio of and a n output capacitor C Assuming an ideal case where the loop

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72 gain is infinity, the transfer function of Figure 4 1 (A) and (B ) can be expressed respectively as ( 4 1 ) Therefore, the loop in Figure 4 1 (A ) can be described equivalently by the loop shown in Figure 4 1 (B ) with the value of the resistor given by. ( 4 2 ) If the loop gain is much greater than 1, the closed loop gain of the amplifier is approximately To maintain simplicity, only the dominant pole formed by C is taken into account for this section By using the same loop analysis in Figure 4 1 (A) and Figure 4 1 (B) the T/H_Amp shown in Figure 4 1 (C) can also be modeled by the switched RC filter (T/H_RC) shown in Figure 4 1 (d) with equivalent R value represented in Eq. ( 4 2 ) Figure 4 2 Resistive e ffect in the t rack and h old RC f ilter To check the resistive effect in T/H_RC filter, Figure 4 2 shows the simulation results of the output waveforms with R=0 and R=1M Ohm. In the track p hase for the ideal case ( R=0 ) the capacitor voltage is the same as the input voltage. In the non ide al case ( ) the capacitor

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73 voltage is unable to follow the input voltage right after the switch is closed due to the low pass natu re of the resulting RC circuit. These differences in tracking behavior cause differences in holding behavior as well. The T/ H_RC filter with negligible R can capture the instantaneous voltage of the input signal and store the voltage on to holding capacitor at the falling edge of the switch The T/H_RC filter with a non negligible R may not necessarily capture the correct voltage at the switching off moment. 4.2 Transfer Function of T/H_RC Filter The T/H_RC filter shown in Figure 4 1 (D ) has input been modulated into replicas located at multiples of the T/H frequencies. Thus the T/H_RC filter behaves as a linear periodical time varying (LPTV) system. The LTPV system can be characterized by solving the harmonic transfer function (HTF) of the system which is given by: ( 4 3 ) Here H n ( ) is the HTF of the system, and are the input and output, respectively, and the T/H frequency is S where T is the period of the T/H clock The overall frequency response of the track and hold RC filter is derived in a step by step manner. Analysi s first begins in the time domain. S ince this is a cyclostationary [48] system with period of T, initially only a single period is analyzed. This single period solution is then applied to multiple periods which are then summed together to find the total time domain representation. Finally, Fourier tr an sform is deployed to express the solution in the frequency domain T he complete derivation can be accomplished in 4 steps. 4.2.1 Step 1 : Output V oltage at the E nd of a S ingle Pulse Switching Signal The first step of the derivation is to find the capacitor voltage at the end of a single track pulse as shown in Figure 4 3 (B ) An arbitrary frequency single tone signal x n (t) is applied to the input of

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74 the T/H_RC filter ( 4 4 ) Here S is s (the sample rate or T/H frequency in rad/s ) and is the arbitrary frequency of the baseband input signal. To clarify the meaning of integer n : from elementary sampling theory, if an ideal impulse sampler oversamples an input signal the resulting frequency response is that of the input signal but with replicas at integer multiples of the sampling frequency ( n*f s ). These n th f s or as the n th image of the input signal after sampling has occurred. Here the baseband input frequency ( n=0 ) and its image s ( ) are applied to the system separately such that their effects on the T/H_RC frequency response can be considered independently. A B C D E F G Figure 4 3 Demonstration of the d erivation p rocedure A ) T/H_ RC f ilter B) single pulse signal, C) sampling of the T/H_RC filter, D) pulse train signal, E) reconstruction of the sampled signal, F) sampling signal and G) reconstruction window.

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75 When the switch is closed (during the on time), the circuit in Figure 4 3 (A ) takes the form of a conventional RC filter with an impulse response of ( 4 5 ) T he output can be seen as the summation of the zero state and zero input responses. For the zero state response, the capacitor initial voltage is assumed to be zero for t< DT T he zero state output y n_zs for is the convolution of the input signal and the impulse respons e as ( 4 6 ) At the falling edge of the single pulse ( t= 0 ) the result of the convolution is ( 4 7 ) Here is the RC time constan t and y n_zs ( t =0 ) represents the zero state output at t= 0 If the initial voltage across C is y n ( DT ) then the output is the superposition of both the zero state response and the zero input response which is caused by the discharge of the RC filter with an initial voltage of y n ( DT ) ( 4 8 ) 4.2.2 Step 2 : Output Voltage at the E nd of a P ulse T rain S witch ing S ignal As shown in Figure 4 3 ( D ) the T/H switch is controlled by a pulse train s(t) with period T and on time DT Assuming no charge leakage during the hold state, the output at t= kT DT (where k is an integer ) is equal to the voltage at the end o f the previous tracking period t = ( k+ 1) T T h us the outp ut at t= 0 in Eq. ( 4 8 ) can be expressed by replacing y n ( DT ) with y n ( T). ( 4 9 ) Then t he output at any falling edge t= kT of the pulse train can be obtained the same way of

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76 Eq. ( 4 6 ) but with a time shift of kT applied ; ( 4 10 ) Eq. ( 4 10 ) provides an expression for the output voltage a t any falling edge However, Eq. ( 4 10 ) requires the knowledge of the output voltage at previous falling edge. For an explicit solution by representing the output in terms of the input only, recursion is applied to Eq. ( 4 9 ) and E q. ( 4 10 ) and each side of the k th recursive equation is scaled by exp( kDT/ ( 4 11 ) By adding all the left side of the Eq. ( 4 11 ) the result can be simplifi ed to ( 4 12 ) After a significant number of switching cycles being progressed ( ), the second term of Eq. ( 4 12 ) can be neglected and the remaining summation (a geometric series) converges T h us, ( 4 13 ) A c ombination of Eq. ( 4 7 ) and Eq. ( 4 13 ) gives the output at t= 0 to be ( 4 14 ) To simplify Eq. ( 4 14 ) first c onsider the baseband frequency input (when n=0)

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77 ( 4 15 ) Based on the assumption that the T/H frequency is much higher than the RC corner frequency s >> 1/ ) the T/H period is much less than the RC time constant, T<< and (D T/ <<1 Therefore the T/H period T is much less than the base band frequency ( 1/2 S < 1/2 S ) then we can assume T<<1 and So we can use the Taylor series approximation: e x if x<1 then Eq. ( 4 15 ) can be approximated to: ( 4 16 ) ( 4 17 ) Now consider Eq. ( 4 14 ) for n 0 B ecause n s >> 0 Eq. ( 4 14 ) can be simplified : ( 4 18 ) Since the T/H period is much less than the RC time constant (T<< ) and thus (D T/ <<1 t hen we can assume exp( 1 and s = So the Eq. ( 4 18 ) can be further simplified to: ( 4 19 ) ( 4 2 0 ) Because e =cos( we can reformat the Eq. ( 4 2 0 ) to be:

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78 ( 4 21 ) ( 4 22 ) ( 4 23 ) Eq. ( 4 23 ) is derived when n 0 the result matches the case in Eq. ( 4 17 ) when n = 0 so the above t wo cases (when n=0 and 0 ) can be combined as : ( 4 24 ) Eq. ( 4 24 ) represent s the output exclusively at t=0 while accounting in source impedance and T/H duty cycles T he output at any falling edge t= kT can be calculated by applying a time shift of kT to Eq. ( 4 24 ) ( 4 25 ) Eq. ( 4 25 ) represents the output voltage at the falling edge of the k th switching period of s(t) Thus y n (kT) is a discrete time signal with values defined only at t= kT N ext step will convert the discrete time signal to the continuous time signal using the Dirac delta impulse function. 4.2.3 Step 3 : Frequency R esponse of the Sampl ed Output To convert the Eq. ( 4 25 ) into a discrete time signal representing the sampled voltage at each falling edge of s(t) for all k Figure 4 3 ( C ) samples the output of T/H_RC by the D irac D elta function which result s an impulse train in the continuous time domain, q n (t) ; ( 4 26 ) Here q n (t) can be viewed as the ideally sampled non ideal voltage stored on hold capacitor C at

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79 all the falling edges of s(t) D ue to the effectiv e filtering via duty cycling, the RC filtering and the aliasing t he cap acitor voltage is n ot precisely equal to the input at the falling edges of the tracking period when To convert the result of Eq. ( 4 26 ) to frequency domain, the continuous time Fourier transform of q n (t) gives ( 4 27 ) Here m represents the output image s generated by the sampling mechanism. Eq ( 4 27 ) describes how a given input frequency, either in the baseband ( n=0 ) or within the bandwidth of an anticipated image ( ) is mapped (with associated weighing factor) to a given output image m For example, if an input frequency with n=2 is applied to the system, even though the resulting baseband output ( m=0 ) is of primary interest, the use of Eq. ( 4 27 ) p rovides information about how this input (n=2) contributes energy to the output at harmonic bands with m 4.2.4 Step 4 : Transfer F unction of T /H _RC Filter The value of q n (t) in Eq. ( 4 26 ) is a valid description of the capacitor voltage only at the sampling instant (t=kT) F or the rest of a given period the output consists of the sample phase and the hold phase as expected. During the hold phase ( s(t ) = low ), the ca pacitor holds the sampled voltage constant across the entire phase During the track phase ( s(t ) = high ), th e capacitor voltage shows a quasi exponential charging/discharging behavior (due to and D ). U nder the a ssumption of fast sampling the track duration is much less than the RC time constant, therefore any voltage variation (detailed behavior) during the track phase can be ignored as long as th e voltage is valid at the holding phase Thus, the capacitor volta ge is approximated as a piece wise constant zero order hold value across the entire period

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80 Mathematically, to create the zero order hold output q n (t) is convolved with a single rectangular pulse g(t) with on time (duration) equal to the period T This is accomplished by using the multiplication in the frequency domain of Eq. ( 4 27 ) and the Fourier transform of the pulse window (a SINC function with period of T ) Assum ing G( is the Fourier transform of g(t) which is the reconstruction window with the time length of T ; ( 4 28 ) The Fourier transform of g(t) gives ( 4 29 ) Therefore the output in Figure 4 3 (E) is the convolution of the reconstruction window and the impulse train q n (t) in time domain: ( 4 30 ) So, i n frequency domain the output due to the n th input image is ( 4 31 ) By inserting the Eq. ( 4 27 ) and Eq ( 4 29 ) into Eq. ( 4 31 ) the output of the T/H_RC filter in frequency domain due to the n th input image can be expressed : ( 4 32 ) The output at images with 0 in Eq. ( 4 32 ) can be neglected since higher order terms are naturally attenuat ed by the rightmost SINC function in the Eq. ( 4 32 ) and an additional low pass filter function can be applied by succeeding stages of the T/H_RC filter We can t herefore only consider the aliasing of T/H_RC filter from all input images of n down to the baseband m =0 Thus, t he Eq. ( 4 32 ) can be approximated with m=0 as

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81 ( 4 33 ) Regarding the output frequency only within the baseband ( 0 /2 < 0 /2 ), t he transfer function from a specific n th input harmonic to the baseband output (the harmonic transfer function HTF) is ( 4 34 ) The result of Eq. ( 4 34 ) represents the harmonic transfer function (HTF) of the linear periodical time varying ( LPTV ) system. A B C D Figure 4 4 Comparison of the f requency r esponse among different d uty c ycles A) Duty cycle of 10%, B) duty cycle of 20%, C) duty cycle of 50 % and D) d uty c ycle of 80%

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82 In order to support the harmonic transfer function of T/H_RC filter at any input harmonic with various duty cycles, a simulation is run by Cadence Spectre with the schematic shown in Figure 4 3 (A) T h e value s of resistance R and capacitance C are 2M Ohms and 10 Pico Faro respectively, and the T/H frequency is 100 kHz which is much higher than the intrinsic RC corner frequency of ~8k Hz B ased on the solution of the periodical steady state (PSS) by the simulator for 30 harmonics, the Periodic AC analysis gives the result shown in Figure 4 4 The simulation result indicates three important characteristics of t he T/H mechanism: (1) the effective bandwidth at any input harmonic is reduced by a factor of duty cycle D ; (2) the pass band magnitude s of the input harmonics follow the trend of a S INC function attenuation with the notch frequency located at the ratio of T/H frequency over the duty cycle f s / D ; and (3) all the input harmonics is folded down to the baseband of output with a frequency shift of n f s 4.3 Noise Aliasing of T/H_RC Filter Assuming the noise in a T/H_ RC filter is generated only by the thermal noise of the resistor in the T/H_RC filter Thus t he noise model of the T/H circuit can be represented by a voltage noise source in series with an ideal resistor T he noise power spectral density (PSD) of the resistor is V ni 2 =4kTR with the flicker noise ignored here since it provide s negligible value s at high er harmonic frequencies Moreover, in low duty cycle cases, the flicker noise corner frequency is reduced du e to the thermal noise incremental by aliasing, as will be explained later The output nois e is calculated by the harmonic transfer function Eq. ( 4 34 ) The total output noise PSD is calculated by adding all the output power components due to all input harmonics Since t he noise source of a resistor is white noise with infinite bandwidth, all the input harmonics from n= to contribute. Thus the output noise power spectral density is

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83 ( 4 35 ) The limit of the summation shows ( 4 36 ) So, the total output noise is ( 4 37 ) Therefore, the noise floor in the pass band is approximated to be ( 4 38 ) The result indicates that the noise power floor due to T/H mechanism is increased by a factor of the inverse of the duty cycle, and the noise bandwidth is reduced by a factor of duty cycle. Thus, t he total output noise can be calculated by integrating the noise power over band ; ( 4 39 ) Recalling that the integrated thermal noise in a standard RC filter without the track and hold switch is also KT/C which means the T/H mechanism will maintain the integrated thermal noise, but the difference lies in that the noise floor is increased and the noise band width is reduced, both by a factor of duty cycle. Figure 4 5 shows the noise PSD comparison between the simulat e d result and the calculated result by Eq. ( 4 37 ) Different lines with the same color represent different duty cycles: 100%, 50%, 25%, 12.5%, and 6.25%. We can see fr om the figure that the calculated noise is a little bit higher than the s imulated result at low duty cycles This is because the PSS and PNOISE simulation was set with maximum number of harmonics to be 100. The ideal simulation should

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84 have unlimited number of harmonics being analyzed, since the resistor generates the white noise with unlimited bandwidth. Larger number of harmonics results in better accuracy but takes longer time for simulation. Figure 4 5 Noise PSD comparison between simulated result and calculated result. 4.4 Transfer Function of T/H_Amp B ased on the assumption that (T/H frequency is much higher than the amplifier 3dB bandwidth) the transfer function o f Figure 4 1 ( C ) is ( 4 40 )

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85 Here, A is the mid band closed loop gain of the amplifier, is the phase delay from input to output 0 is the track and hold (T/H) radian frequency D is the duty cycle of the T/H clock is the equivalent time constant eq H =C H and n refers to the input harmonic Under the assumption of T<<1 t he magnitude of the baseband transfer function of Eq. ( 4 40 ) when n=0 can be simplified to ( 4 41 ) T he 3dB bandwidth of this transfer function is ( 4 42 ) Recalling the bandwidth of a conventional amplifier with the same structure but excluding a T/H mechanism is gm / ( C H A ) s o the bandwidth is reduced by a factor of D due to the T/H mechanism For instance, if the T/H _Amp uses 10% duty cycle, the bandwidth is 10% of a conventional amplifier without a T/H mechanism. On the other hand, for a specific bandwidth requirement, reducing the value of C H by the ratio of D from its original value will counter act the bandwidth reduction due to T/H function For our specific application of neural signal acquisition with bandwidth requirement from 100Hz to 7 kHz, we pick the output capacitor value of 1.5 pF for T /H _A mp instead of 15 pF used in conventional amplif iers if the T/H duty cycle is 10% Figure 4 6 The RC model of the supply current modulated amplifier In order to support the transfer function analysis of the T/H_Amp we use the supply current modulated amplifier shown in Figure 3 17 as an example to compare the simulation result and the measurement result. The supply current mod ulated amplifier and the buffer stage in Figure 3 17

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86 can be modeled by the schematic shown in Figure 4 6 The values of the resistor s and the capacitors are: R0=30k, R1=2.5M, R2=50G, R3=50G, R4=6M, C1=2.4p, C2=100fF, C3=100fF, C4=6pF, Cpar=150fF. Here R0 is the resistor that generates the thermal noise which is equal to the input referred thermal noise of the supply current modulated amplifier In Figure 4 6 only R0 generates the noise, all other resistors are set to be ideal with the noise generation turn ed off by the simulator. The first the gain of 63dB which is the total gain of the amplifier and the buffer stage The switch S(t) performs the supply current modulation function. The R2 / C2 and R3 / C3 implement the high pass function of the amplifier and the buffer stage respectively. The R4 and C4 implement the buffer stage low pass function. The Cpar represents the summed parasitic capacitance at the drain s of the t ransistors MN3, MN4, MP5, and MP 6 in the supply current modulated OTA shown in Figure 3 18 In Figure 4 7 the black lines are the simulated transfer function of the RC model. The red lines are the simulat ed transfer function of the supply current modulated amplifier. The blue lines are the measured transfer function of the supply current modulated amplifier. Different lines with the same color represent different duty cycles: 1 00%, 50%, 25%, 12.5%, and 6.25% The mid band gain of the amplifier is determined by the capacitors coupling ratio, C1/C2 as shown in Figure 3 17 The measured pass band gain is a little bit less than the simulated result This is because C1 has the value of 10pF and C2 has the value of around 100fF thus the parasitic capacitance in the layout affect s C2 much more compared to C1, which r esult s the gain ratio to be less than predicted In Figure 4 7 the measurement result matches the simulated result well. In Figure 4 4 the simulated result matches the calculated T/H_RC model result well. However, there is significant

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87 difference between the T/H_Amp and the ideal T/H_RC model which is the parasitic capacitance between the amplifier output and the track and hold switch, as labeled Cpar shown in Figure 4 6 This parasitic capacitance affect s the transfer function and causes the bandwidth does not follow the track duty cycle proportionally Figure 4 7 Comparison of the transfer functions among calculated result of RC model, simulated result of RC model, and measured result of amplifier 4.5 N oise Aliasing of T/H_Amp In this subsection, we ta ke the supply current modulated amplifier as an example for the noise aliasing analysis as shown in Figure 3 18 The conclusion can be easily applied to the time multiplex ed amplifier as well Figure 4 1 (C ) depic ts the amplifier with an input noise volt age source which refers to all the noise generated inside the OTA, as labeled V n

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88 ( 4 43 ) The combination of the OTA and the feedback give s an equivalent transconductance of Geq=gm p1 so the noise can be remodeled by Figure 4 1 (D ) with a n equivalent damping resistance Req=1/Geq As discussed in section 3 3 for noise optimization, the input differential pair transistors P1 and P2 are biased at weak inversion while N1, N2, P3, and P4 are biased at strong inversion. The transconductance gm is represented by the EKV model, which is valid for transis tors in all regions of operation [31] ( 4 44 ) U T is the thermal voltage k T mp /q and is the subthreshold coupling coefficient, which has a value of 0.72 in UMC130 nm technology. IC refers to the inversion coefficient which is calculated by the ratio of the drain current to the moderate inversion characteristic current IC=I D /I S and can be expressed as ( 4 45 ) T ransist ors P1 and P2 shown in Figure 3 18 work in weak inversion with IC P1 << 1 and transistor s N1, N2 P3, and P4 work in strong inversion with IC N1, P3 >> 1 Their transconductance can be approximated as ( 4 46 ) I nserting Eq. ( 4 46 ) into Eq. ( 4 43 ) results in a total input thermal noise spectral density of

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89 ( 4 47 ) T he ratio of bias current in N1 2 and P3, 4 over P1, 2 has a fixed value in our design so the Eq. ( 4 47 ) can be rewritten as ( 4 48 ) A s demonstrated in section 4 3 the output noise power of a T/H_RC filter is expressed by Eq. ( 4 37 ) with all input noise harmonics (from for n) aliased up. A ll the non zero output harmonics ( ) are neglected due to the filter effect by the second stage amplifier So the output noise power spectral density (PSD) when k=0 in the pass band (
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90 same current consumption, we apply the total current consumption by the average d current consumption of I ave divided by duty cycle D to Eq. ( 4 51 ) Therefore Eq. ( 4 51 ) can be reformatted to ( 4 52 ) The result of Eq. ( 4 52 ) indicates that the supply current modulation scheme reduce s the noise contribution s of the transistors other than the input differe ntial pair while retaining the same power consumption. This result also indicates the superiority of the supply current modulation scheme in terms of energy efficiency. Unlike the strategy of reducing the bias current directly, supply current modulation reduces power consumption while maintaining the NEF theoretic ally The noise aliasing analysis in this chapter takes only the thermal noise generated inside the OTA into consideration. The aliasing of flicker noise is negligible a t high T/H harmonic frequencies. T he background noise at the cellular level is pre fil tered out before aliasing happens by the mega ohm electrode s and the input capacitance (~ 1 0pF) of the first stage amplifier which generate the low pass corner frequency much less than 10 kHz. Therefore the aliasing of the background noise can also be negl igible. In order to support the noise aliasing analysis of the T/H_Amp, we use the supply current modulated amplifier shown in Figure 3 17 as an example to compare the measurement result with the simulated result of the RC model The RC model of the supply current modulated amplifier is shown in Figure 4 6 We set the track and hold switching frequency to be 50 kHz which is higher than the intrinsic R1/C1 corner frequency. The flicker noise of the amplifier is hard to be model ed in a switched RC filter, b ut we can remo ve the flicker noise affection of the amplifier in simulation for comparison

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91 We set the noise parameters NOIA=NOIB=NOIC=0 for both NMOS and PMOS to acquire the simulated input referred noise of the supply current modulated ampli fier without flicker noise. Figure 4 8 Comparison of the input referred noise among simulated result of RC model, simulated result of amplifier, measured result of amplifier, and simulated result of ampli fier without flicker noise In Figure 4 8 the green lines are the measured input referred noise of the supply current modulated amplifier. The black lines are the simulated input referred noise of the supply current modulated amplif ier. The red lines are the simulated input referred noise of the supply current modulated amplifier without flicker noise. The blue lines are the simulated input referred noise of the RC model. In this figure, different lines with the same color represent different duty cycles: 100%, 50%, 25%, 12.5%, and 6.25%.

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92 We can see from Figure 4 8 that the simulated result matches the measurement result well, except that the meas ured flicker noise is a little bit higher than the simulated flicker noise Without flicker noise affection, the simulated amplifier input referred noise matches the RC model well. Additionally, as described in section 4 3 the simulat ed noise PSD of the T /H_RC filter matches the calculated noise by Eq. ( 4 37 ) as shown in Figure 4 5 However there lie a significant difference between the amplifier RC model and the T/H_RC filter model, which is the parasitic capacitor between the amplifier output and the track and hold switch, Cpar as shown in Figure 4 6 Therefore the input referred noise PSD of the supply current modulated amplifier is not exactly proportional to the 1/D. 4.6 Energy Efficiency of the Proposed Amplifiers Modern neural prosthes es aim at monitoring and stimulating the selective regions of the brain to restore neurological function or to treat disease. The enabling devices require a highly reliable brai n to machine interface being capable of record ing the cellular level neuron act ivity continuously for enough p eriod of time To achieve better reliability for the entire neural acquisition system, the neural signal is always digitized at the fr ont end for further processing so that an ADC is usually integrated at the front end In or der for better SNR and accuracy during digitization, the neural signal is pre amplified to match the conversion range of ADC. Figure 2 4 in Chapter 2 shows the structure of a track and hold amplifier that is commonly used as the pre stage of a n ADC. H owever, there are some design issues with the switches for sampling First, t he feedthrough problem that the input signal still passes through the switch during off state Second, the noise generate d by the switch signal may be coupled to both side s of the switch. Third, the charge leakage of the holding capacitor changes the volta ge during holding state. Those errors are inevitable but can be largely attenuated by increasing the value of the holding capacitor Another consider ation lies in the fact that the amplifier must have sufficient bandwi dth (BW) and

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93 slew rate to charge the C H to a certain error during the tracking period as discussed in Chapter 2 Th is work presents two type s of T/H_A mp the time multiplexed amplifier and the supply current modulated amplifier. Both amplifier s ha ve a key feature: the current consumption of the channel is synchronized to the track period During the track period, the amplification function of this channel is active and the amplifier draws current from the supply, while the input signal is amplified and stored on to the holding capacitor. During t he holding period, the amplification function is turned off and the current consumption is also cutoff for this channel while the previous amplified signal is kept constant on the holding capacitor. Therefore, during the holding period, the entire amplifier can be viewed as high impedance path from the input to the holding capacitor, which provides a better isolation and less feedthrough. On the other hand, the amplifier only consumes current during t he tracking period, thus for a given average power budget, the bias current of the T/H_Amp is boosted up during the tracking period, which result s in a larger instantaneously slew rate and BW. So the proposed amplifier s achieve a better charging ability to the holding capacitor In other words, for the same power budget, the proposed amplifiers allow for choosing a larger value of holding capacitor and thus result in less pedestal error and the switching noise affection Table 4 1 compares the specifications of the proposed first stage amplifier s and t he state of the art. The amplifiers chosen in the table are the best among the recent published designs regarding the p ower the area and the noise performance As shown in the table, different topologies and structures result in different performance of the neural amplifiers. Theoretically, the folded cascode amplifier shows better NEF compared to current mirror amplifie r since larger portion of the bias current is consumed by the input differential pair which helps reduce the noise contribution from the transistor s other than the input differential pair. However, the current mirror

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94 topology has better immunity to the pr ocess variation s compared to the folded cascode structure as described in section 2 2. The t elescopic topology shows the best area saving due to the least transistors being used. However the input and output common voltage range and the output dynamic swin g of the telescopic topology are much less compared to other topologies. Thus the telescopic topology is not often used in recent neural amplifier design s. Table 4 1 Comparison between the p roposed a mplifier s and the s tate of the a rt Harrison [6] Sarpesh kar [22] Carlen [49] Thakor [50] Section 3 1 Section 3 2 Section 3 3 0.5 0.5 0.35 0.5 0.5 0.13 0.13 Topology Current Mirror Folded Cascode Telescop ic Folded Cascode Folded Cascode Current Mirror Folded Cascode Structure Single E nded Single E nded Single E nded Fully Diff Single E nded Single E nded Fully Dif f Voltage (V) 5 2.8 3 3.3 3 1 0.8 1.5 16 2.7 1.4 8 7.5 2 1. 4 Gain (dB) 40 40.85 34 39.6 40 40 40 rms ) 2.2 3.06 7 1.94 3.5 10.5 5.6 BW (kHz) 7.2 5.3 5 8.2 1.25 7.8 7.8 CMRR (dB) >83 66 >76 >50 >65 PSRR (dB) >85 75 >70 >60 >50 Area (mm 2 ) 0.16 0.16 0.02 0.18 0.06 0.15 NEF 4.0 2.67 4.6 2.9 8.8 5.8 2.9 The main difference between the single ended and the fully differential structure lies in the common mode noise rejection. The fully differential structure shows better rejection to the common mode noise and the supply noise, which is more important if the amplifier is integrated in the BMI system since the switching noise from the digital blocks may be coupled to the amplifier an d the supply. But the fully differential structure requires additional common mode feedback circuits that may add additional power consumption.

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95 Figure 4 9 Comparison of the noise efficiency factor among the state of the art. The proposed amplifier in Section 3 1 should have better NEF as predicted by design, but the transistor sizes are not optimized for the noise performance and the current consumption is not measured directly but estimated by the simula tion result which may cause large difference in the NEF result. The proposed amplifier in Section 3 2 shows much better area saving by sharing the single OTA among four independent channels with time multiplexing technique. But the transistor sizes are not chosen to be the best for optimizing the noise performance. The proposed amplifier in section 3 3 achieves a very low NEF due to the supply current modulation scheme which helps

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96 attenuate the noise contribution from the transistors other than the input di fferential pair. But this amplifier require s additional control circuits to generate the clock for the supply current modulation. Figure 4 9 shows the NEF comparison among the state of art. The lower NEF represents a better achievement over the tradeoff between the power consumption and the noise performance. F or most of the designs showed in Figure 4 9 the NEFs are achieved below 10. The three proposed amplifiers are also labeled in this figure.

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97 CHAPTER 5 5 915 MHz A CTIVE NEURAL TRANSPONDER WITH 4 CHANNEL TIME MULTIPLEXED ANALOG FRONT END This chapter reports a highly integrated neural tag for the constant recording of the bio signal data. The analog front end (AFE) uses the time multiplexed architecture for sensing the four independent neural channels The AFE include s a front end amplifier with tunab le bandwidth four low power buffer stage s and an 8 bit Successive Approximation R egister (SAR) ADC T he amplifier and the buffer stages together measure a mid band gain of 53 dB and an input referred noise of 12 .5 V with a noise efficiency factor (NEF) of 8.6 D igitized s treaming signal from AFE are packetized and transmitted via a low power 915MHz backscattered modulator. This system also includes an ASK/PWM receiver that allows for user contro l of the system configuration s The entire system dissipates 190 W wh ile fully operational which enables the device functioning for months without replacing the battery The chip was fabricated by using UMC 130nm process, with a total die area of 1.64mm 2 5.1 Motivation The Brain Machine Interface (BMI) provides a direct communication pathway between the human brain and an external device for the transfer of neural information, ideally conveying human intent. The BMI is a promising technology that can partial ly restor e the mo tor function for patients suffering spinal cord injury neuromuscular disorders or epilepsy [51] BMI systems can be implemented by using various recording modalities such as EEG ( Electroencephalography) over the scalp, ECoG ( electrocorticography) that us es the subdural electrodes, or Single Unit Activities that utiliz es the penetrating micro wire arrays. The proposed system targets at animal studies that employ micro wire arrays for their localized high spectral range and high SNR action potential recording capabilities [52] Chronic measur ements of the physiological neural signals require the low power

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98 micro systems incorporating the functions including amplification, DSP, and wireless transmission The analog front end (AFE) should be capable of record ing lo w level biological signals with amplitude from 5 to The AFE should be able to eliminate the effect of DC potential shifting at tissue electrode interface and the local field potential that accompanies the useful neural spikes [24] The entire BMI system must be small in scale and hence highly integrated; very low power and energy efficient to minimize heat generated by the device ; low noise to condition the weak neural signals; and capable of wirelessly transmitting. Over the past few decades, plenty of neural rec ording micro systems are focusing on decr easing or even eliminating the hardwire connection to minimize the risk of infection and to increase the mobility of behavior animals [ 37 ] [4 7 ]. A significant challenge for those systems lies in the powering strategies which have the option of powering through a wireless inductive link or a miniature battery. T he inductive link is able to deliver sufficient power (several milliwatt s) through a small size coil, however the range of th e wireless link is limit ed within tens of centimeters [17] [18] [19] Noticing the data link of TX and RX is capable of transmitting signals wirelessly for meters, the inductive link for powering act s as a bottleneck which may caus e inconvenience for both external reader and the animal s under test. The use of a small size battery greatly extends the range of communication but it suffers limited amount of capacity and requires rep lacement of the battery for a certain period [53] [12] An improved method includes a rechargeable battery that can be powered in a short range and send/ receive sign al at a much larger distance [16] But this type of batt eries, such as nickel m etal hydride, lithium iron usually ha ve relative smaller energy density and call for extra control of the voltage levels. I n this chapter we propose a system that entails low power components performing the task of neural recording but consumes less than 200 W while full functioning so the entire device can be

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99 conti nuously powered through a high density battery for month s such as zinc air, silver oxide, which are as much as necessary for the bench top neural studies. T his design ac hieves energy efficiency by utilizing the time multiplexed AFE and a passive wireless transmitter, since those two blocks are usually the dominant portion of the entire system power budget The low noise AFE has a single primary operational transconductanc e amplifier (OTA) that is shared by four independent input channels in order to decrease the power consumption on average and to save area as well (see section 3 2) The digitized data from the output of the AFE is further processed via pack etizing logic, modulation, buffer ing and wireless transmission by a 915 MHz modulator T h e system is also capable of updat ing the chip settings by external control through a low power receiver. This chapter is organized as below: in section 5 2 the function of the entire system is described, in section 5 3 the operation of the multiplexed analog front end is briefly introduced section 5 4 and 5 5 describe the transmitter chain and receiver chain, respectively, section 5 6 shows the measurement setup and the test result, in section 5 7 a brief conclusion is drawn 5.2 System Functionality The proposed neural transponder architecture is shown in Figure 5 1 The on chip part consists of a transmitter (TX) chain and a receiver (RX) chain. The complete system also includes several external components: a 1.2V battery (not shown), a 915MHz ISM band antenna which is matched to the input of the receiver and the electrodes for probing the neural signals at the cellular level T he frontage of the transmitter chain is a 4 channel time multiplexed AFE that amplifies and digitizes four channels sequentially. The primary purpose of using time multiplexing technique is to achieve energy efficiency under low bias condition, as explained in section 3 2 Secondly, multiplexing is apparently more area economic al by sharing one core OTA and ADC

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100 among four channels T hirdly, the output from the AFE is an already serialized and digitized data stream that can be easy process ed by following stages. Figure 5 1 S ystem block d iagram T he digitized data from the output of the AFE is further packetiz ed into a certain data pattern in order for external reader to discern the boundaries of the four channel s A MUX therea fter selects between the output from the packet l ogic and the output from the pseudo ransom bit sequence (PRBS) generator The PRBS is used to characterize the performance of the wireless transmitter and is shut down with no power consumption during normal operation of neural signal acquisition The output of the MUX is first modulated by an on chip oscillator and then buffered through several inverting stages to drive a large backscattering switch The TX transmits the streaming data via modulating the incident RF carrier by toggling the impeda nce of the antenna. T he receiver (RX) chain utilized in this system allows for external control of chip settings such as bandwidth, sampling frequency and oscillating frequency The front end of the RX chain

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101 is a back scatter cancelling circuit used to minimize the TX switching noise been couple into the receiver chain and thus helps the full duplex operation The following stage is an envelop detector that extracts the RX signal from the pulse width modulated (PWM) RF carrier. The buffer sta ge further converts the envelop into a rail to rail signal. Since the RX signal is transmitted without the accompanying clock information there is a clock and data recovery (CDR) circuit which generates a corresponding clock aligned to the edge of the data. T herefore the RX data is readily available and can be further stored into the register bank to control the internal chip settings. Continuous operation of the R X chain enables constant refreshing of the register ban k Power dissipation in modern wireless mi cro systems is largely dictated by the transmitter and the AFE. Different transmitter topologies may consume the power in the range of milliwatts while the AFE draws power proportional to the number of channel s [17] [12] [18] To decrease the power dissipation associated with data transmission, it is important to limit or possibly eli minate the high est frequency generated on chip which is required for the up c onversion of TX signal onto the RF band On the other hand a h igher carrier frequenc y is still preferred due to its larger bandwidth and smaller wavelength which refers to a smaller size of antenna In this design we employ a low complexity backscattered transmi tter which shifts the high est frequency generat ion to external device So, the on chip side only generate s the clock reference that creat es the sidebands on the RF carrier [21] [13] which show s significant frequency and power reduction 5.3 Transmitter Chain This transmitter chain utiliz e s the time multiplexed analog front end (AFE) shown in Figure 3 11 in section 3 2. The bandwidth and the sampling frequency of the AFE are tunable by external user through the receiver chain.

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102 5.3.1 High Pass Filter and Buffer Stage Figure 5 2 shows the schematic of the high pass filter and the buffer stage utilized in the AFE. This stage consumes much less current compared to the first stage amplifier, since the first stage amplif ier has a gain of 40dB which helps attenuate the noise contribution of th is stage while being referred to the input of the first stage. The second stage amplifier consumes the total current of 600nA, with 100nA and 500nA flow through MP0 and MP4 respective ly. The output leg MP4 and MN3 consumes higher current which is required to flow t hrough the feedback resistors (R1, R2 ) and to drive the following stage Figure 5 2 S chematic of the high pass filter and the buffer stage The input of this stage is AC coupled and is filtered at the front end. The corner frequency is determined by the values of the resistor and the capacitor as shown in Figure 5 2 Adaptive tuning of the resistance gives the flexibility of choosing the corner frequency which helps attenuate the l ocal f ield p otential accompanying the useful neural signa l. The switches t hat control the resist ance are four MOSFETs in parallel and have resistor The controlling signal s for those switches are applied by external user and is extracted by

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103 the receiver chain. The output DC operatin g voltage is set to V MID which is half of the supply voltage in order to maximize the output dynamic range. The gain of this stage is determined by the resistor ratio, (R1+R2)/R1. There are tradeoffs for choosing the resistor values. First, the feedback r esistor R1 and the gate parasitic capacitance of MP1 form a low pass filter, but this amplifier is used for neural application with input signal within tens of kHz, so the corner frequency is high enough and can be neglected. Second, the resistance of R2 s ets the lower limit of the DC bias current of MP4 and MN3, because the OTA must supply enough current to flow through R1 and R2. For example, if the output voltage is 0. 8 V and V MID is 0.5V, there is 0.3V voltage drop across R1 and R2, thus the current flow ing through R1 and R2 is 0.3V/(R1+R2) which is supplied by M P4. T herefore the MP4 must has DC current high enough to support the maximum output swing I n low power design, the resistor value should be chosen as large as possible Third, the technology of U MC130nm uses Poly layer as resistors, which is not as area efficient as thin film layer, so there is tradeoff between the power consumption and the area. Since there are total ly 4 channels in this system, we choose the resistor value to be 320k and 1280k f or R1 and R2, respectively, to achieve both power and area efficient. The miller capacitor CC used for compensation also determines the bandwidth of the amplifier. T here is a switch formed by transmission gate to control the value of this capacitor as wel l as the bandwidth of this stage. The controlling signal of this switch is acquired from the receiver chain. The width ratio of MP4 over MP0 is around 5, so the DC current ratio of MN3 over MN1/2 is around 10. Therefore the width of the MN3 should be set t o 10 times the width of MN1 /2 for less DC offset. Figure 5 3 shows the schematic of the reference V MID generator. The V MID reference is used

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104 for both biasing the first stage amplifier and the second buffer stage. The reference must be able to source and sink current since the second stage amplifier may have positive or negative output. Therefore this regulator uses complementary structure which is able to source a nd sink large current. The half supply reference is generated by four diode connected PMOS transistors in series, as shown on the left of Figure 5 3 MP6/7/8/9. Each of the PMOS is placed in its own separated NWELL and the NWELL is tied locally to its source to avoid body effect that may cause mismatch among those four diodes. 5.3.2 Middle Voltage Generator Figure 5 3 Schem atic of t he middle voltage generator The V MID generator uses two stage structure, so there are two miller capacitors in parallel with MP3 and MN3 respectively, to compensate the second ary pole at the output (V MID ) The drawback of this circuit is that t he output leg formed by MP3 and MN3 is not biased by a fixed current source. Therefore, the DC current flow ing through M P 3 and MN3 is undetermin able regarding the process variation. For example, if there is DC offset between MP1 and MP2, the drain voltage of MN2 may

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105 slew high and command large current to flow through NM3. Since the negative feedback loop can avoid the drain voltage of MN2 from rising too high in this case, the feedback will help limit the DC current flow ing through the MN3. Ho wever, the worst case may happen if there is offset in MN4 and MN5 too. This offset may command large DC current flow through MP3. If both MN3 and MP3 are command ed for large current due to process variation (offset), the V MID regulator may consume current that exceed s our power budget. 5.3.3 Low Power SAR ADC Figure 5 4 Schematic of low power SAR ADC Following the second gain stage, the four outputs of the buffer stage s are digitized using a standard 8bit SAR ADC a s shown in Figure 5 4 The ADC digitizes four channel s sequentially For each channel in track time, the buffer output is disconnected from the holding capacitor C H2 and C H2 is connected to the plus terminal of the comparator for digitization. For the other three channels in hold time, the buffer stages are connected to the C H2 to refresh its voltage from amplifier output. The switches that connect the C H2 consis t of PMOS and NMOS transmission gate. Although the four phase controlling clocks (S1 S4) are non overlapping there is still charge

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106 redistribution between channels through the parasitic capacitance C P at the input of the comparator The holding capacitor C H2 has the value of 7.5 pF and the estimated input parasitic capacitance of C P is about 9 fF. Thus the ratio of those two capacitance is about 830 which limits the maximum possible charge redistribution error within 0.3 3 LSB The capacitor array consist s of metal to metal fringing capacit ors which have accurate value for matching in UMC130 nm technology. Since this process has 8 levels of metal available the capacitor s use 6 layers of metal to sav e area. The LSB of the array has a value of 40fF, which is app roximately equal to the parasitic capacitance at the common top net of the capacitor array. Figure 5 5 (A) shows the layout structure of the capacitor array and Figure 5 5 (B) shows the layout of the single unit of fringing capacitor. All the 8 bits of capacitors are in common central layout thus achieve better matching acros s process variations. A B Figure 5 5 Layout of the capacitor array. A) Common central layout, B) fringing capacitor. Figure 5 6 shows the schematic of the comparator used in ADC. Since the output of the buffer stage s ha s voltage swing close to the supply and the ground rail, the comparator uses a NMOS and PMOS complimentary differential structure for a rail to rail input range comparison. The comparator uses symmetric structure with matched layout to cancel the switching noise in

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107 common mode. At the output, although only the positive side is used for ADC logic, there are buffer inverters on both po sitive and negative outputs, which help reduce the offset created by the inverter input parasitic. Figure 5 6 Comparator of the ADC The clock signal (CK) controls the resetting of this comparator to avoid the affection from previous comparison result. When CK signal is high, the two top cross coupled PMOS transistors have their drain voltage be ing reset to supply voltage and the bottom two cross coupled NM OS transistors have their drain voltage s be ing shorted together. Thus the previous comparison affection is eliminated and the result of current cycle is available at net COMP after CK signal goes low. The duty cycle of CK signal is about 50%, so there is e nough time for both resetting (CK high phase ) and for comparison result to settle (CK low phase ). The output of the comparator COMP is latched to the ADC output CODE at the rising edge o f CK signal. Since four channel output s are digitized sequenti ally, the output of the ADC is the serialized digital stream which can be easily process ed by the packet logic stage. Figure 5 7 shows the SAR logic for ADC. Before each co nversion begins, there is the clear

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108 signal on net CLR to reset all the flip flops and discharge the capacitor arrays. The first flip flop at reset, flops to enable the conversion sequentially Figure 5 7 SAR l ogic diagram. Figure 5 8 Schematic of the l atch for the c apacitor a rray Figure 5 8 shows the schematic of the latch used in the SAR logic. When the CK signal is low, i t forces the output to be high. W hen CK signal is high, it latches the input signal to the output. Since all the eight latches in the SAR logic ha ve input tied to the output of the comparator on net COMP, each latch locks one bit comparison result

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109 through all the flip flops in the SAR logic, therefore those flip flops triggers eight latches sequentially and store the comparison result into each latched output bit Figure 5 9 Timing d iagram of ADC o peration The timing diagram for ADC is shown in Figure 5 9 The clock signal CK is divided down by 11 cycles t o generate the resetting signal CLR and the channel selecting signal CK4. The CLR signal is used to discharge the top plate of the capacitor arrays and to reset all the flip flops in the SAR logic. The CK4 signal is further divided down to generate the 4 p hase non overlapping clocks S1 S4, which are used to select one of the 4 multiplexed channels for ADC conversion. For each conversion, the 8 bit ADC output CODE begins at one clock cycle after CLR resetting. The ADC output CODE of four channels is packetiz ed with 8 bits header and one zero inserted between

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110 channels. The header is used for identifying the boundary of the packet for wireless reconstruction. The entire packet has 44 clock cycles as shown in the timing diagram. 5.3.4 Transmitter Chain Logic In order for proper ope ration of the packet logic circuits, PRBS and the register bank an initial reset clock with enough on time is required. Figure 5 10 shows the power on reset circuit or POR used to reset the initial states of the logic circuits Figure 5 10 Schematic of the power on reset circuit As shown in Figure 5 10 t he input of INV1 is tied to the supply voltage VDD, thus after initial power up, the output of the first stage INV1 is kept ground all the time. So the capacitor C11 has initial voltage of 0V and is charged up through the diode connected NMOS MN1. Thus the net VX1 at the output of INV3 has an initial voltage of 0V which makes the net at the output of INAN1 has an initial voltage of VDD and the net VPOR has an initial voltage of GND. After in itial power up, C22 is charged up to VDD but with a faster speed compared to C11 charging speed since the diode connected MN1 limits the charging current for C11 Once the C22 is charged across INV5 threshold and C33 is discharged to GND, the voltage on ne t VX2 is VDD. After C11 voltage rises across the threshold of INV2, the net VX1 will be VDD and the net VX2 will remain at VDD for a

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111 while, therefore the VPOR voltage will be at VDD for a while. After the C22 is discharged and C33 is charged across INV6 th reshold, the VPOR will toggle to GND again and the entire POR circuit will consume negligible power later on. To avoid chatter ing due to noise or supply bouncing, there is positive feedback transistor MP2 that charge s C11 immediately to VDD once VX0 pass es the threshold of INV2. Following the AFE, there is a packet logic block that transforms the streaming data from the ADC output to the data pattern shown in Figure 5 11 which helps the wireless recovery. Eac h data packet has 44 bit s includ ing 4 channel s ADC data and a n 8 bit header. The external reader is therefore able to extract the channel information by captur ing the header as the boundary of each packet. Figure 5 11 Data p attern of o ne p acket In order to facilitate the transmitter measurement an 8 bit on chip pseudo random bit sequence (PRBS) generator is included which is in parallel with the packet logic block as shown in Figure 5 1 A MUX is used to select either the PRBS output or t he packetized data from the AFE output During normal operation of the neural signal acquisition, the PRBS is shut down and consumes negligible power. T his design transmits the neural signal by utiliz ing a low complexity backscattered modulator to eliminate the need for the high est RF frequency generated on chip Thus on chip only a local clock reference of less than 16MHz is generated The on chip clock is provided by a 3 stage current starved ring oscillator. Four bits tuning of the oscillator allows the frequency programmable from 6 MHz to 16M H z.

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112 5.3.5 System Clocking and Modulation Figure 5 12 shows the schematic that generates the four phase non overlap clocks. The input signal CK4 is the divided down signal of CK by 11 cycles, so it has the period of one eleventh of the CK period. In order to guarantee enough time intervals between non overlap ping gap s there is a delay cell comprised of inverters with large length MOSFET s overlapping two phase clocks The non overlap ping phases non overlapping clocks S1 S4 Figure 5 12 Four p hase n on o verlapping c lock g enerat or. The c locking for each block in the transmitter chain is organized as follows: the oscillator s frequency f OSC ranges from ~6MHz to 16MHz and is tunable by four controlling bits T he clock frequency or the bit rate of ADC is f OSC / 16 which means there are 16 clock cycles modulating each ADC bit and helps separat e the modulated sideband from RF carrier with enough frequency difference T he sampling frequency of the ADC is f OSC / ( 16x11), which means the sampling clock is generated by further division of ADC clock by 11 cycles The 8 of the 11 clock cycles are used to gen erate the 8 bits of ADC output for each channel while the remaining 3 clock cycles are used to reset/ resample the logic circuits Therefore, each channel has the sampling frequency of f OSC / ( 16x11x4) which is the frequency of the non overlapping clocks S 1 S 4 Thus the total 44 clock cycles forms a data packet as shown in Figure 5 11 The proposed low power modulator transmits the packet ized data by backscattering the incident ISM band 915MHz carrier. In order to assure enough reflection energy a large

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113 backscattering switch ( 100um/0.12um ) is utilized to perform the ASK modulation by toggling the impeda nce between the two nodes of the antenna Several digital buffers are added ahead to drive the large backscattering switch at Mega H ert z frequency. 5.4 Low Power R eceiver C hain Figure 5 13 Block diagram of the r eceiver chain Figure 5 13 shows the simplified schematic of the non coherent receiver used to download external commands In order to facilitate the full duplex operation and eliminate the switching noise coupled from TX chain a set of two half sized dummy switches are placed along the receive path to cancel the TX switching noise and the charge injection from the large backscattering switch The modulated RF car rier is AC coupled to the envelop detector which is bias ed by an internally generated DC reference V B Figure 5 14 Schematic of the envelop detector

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114 The envelop detector shown in Figure 5 14 utilizes an unbalanced source coupled pair with the gate W/L ratio of 16 between the cross coupled differential pair transistors T h is topology acts as a full wave rectifier by exploiting the second order non linearity of the source coupled pairs. Figure 5 15 shows the simulated output of the unbalanced source coupler V REC by DC sweep ing the differential input voltage V T he input and output show approximately parabolic relationship within a smal l range of V ( 50mV to 50mV) [54] Therefore the envelop is rectified by using the second order effect. The rectified signal is subsequently amplified by a 20dB gain stage with cutoff frequency at around 200 kHz that helps attenuate the high frequency components especially the noise coupled from TX chain A rail to rail digital signal is extracted by comparing the unfiltered envelop signal V ENV with a low ripple filtered reference V REF Figure 5 15 DC sweeping of the u nbalanced s ource c oupler The envelop encodes the PWM data by 30% or 70% duty cycle represent ing a 0 or a 1 respectively. Since data transitions are available every cycle, the full rate NRZ clock edges are readily available and additional clock recovery circuitry is not required. Data is extracted by

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115 integrating the PWM si gnal and comparing the integrated result with a reference voltage at each falling edge. 5.5 Measurement R esult The chip was fabricated by using the UMC130nm technology, and the die picture is shown in Figure 5 16 The chip was bonded in a Plastic leaded chip carrier (PLCC) package and mounted on a 2 lay er PCB board for evaluation as shown in Figure 5 17 The AFE functionality was independently characterized by using the 3567A D ynamic S ignal A nalyzer for measur ing t he bandwidth gain and noise performance. A signal generator and an artificial spike train synthesizer were used to characterize the time domain operation of the AFE. Figure 5 16 Die p icture The transmitter measure ment was set up by connecting three 915MHz antennas to the P CB board, RF source generator, and the mixed signal analyzer (MXA), respectively. Then set the MXA input sensitivity to be 40dBm, otherwise the backscattered spectrum can not be discerned. The spectrum shown in the MXA has the side bands on both upper and lower side of 915MHz carrier

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116 Figure 5 17 Measurement setup for system characterization. Figure 5 18 Measured w aveforms in r eceiver c hain To reconstruct the TX signal, the MXA is set to the analog demodulation mode with the center frequency located at the sid eband of the carrier The demodulation BW should be set low eno ugh to void the 915MHz carrier from saturating the demodulator Use the eye diagram function of the MAX to check the robustly of the recovered digital pulses The longest time that MXA can record is 40msec. The saved data through USB connection can be load ed to the computer. Then the recovered bit sequence should match the PRBS simulation result If the AFE is selected active by the MUX as shown in Figure 5 1 the prog ram at external PC can extract the packetized header and the ADC bits and therefore reconstruct the original analog signal that fed into the AFE

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117 T he functionality of the receiver is checked by measuring the waveforms shown in Figure 5 18 with the function diagram shown in Figure 5 13 T he top waveform is the detected envelop V ENV with 30% and 70% duty cycle s representing 0 and 1 respectively. The second one shows the output voltage of the charge pump V INT which is generated b y integrating the envelop signal with different duty cycles T he bottom waveform is the recovered data resulted from the compari son between the integrated waveform V INT and a n on chip reference The recovered data is then stored in a register bank to control the system setting s A B C D Figure 5 19 Measured t ransmitter p erformance A) Measurement setup with antenna, B) b ackscattered s pectrum C) d emodulated t ime d omain p ulses and D) r ecovered e ye d iagram Figure 5 19 (A) shows an example antenna optimized at 915 ISM band. Figure 5 19 ( B ) shows the sideband of the car rier. Figure 5 19 ( C ) shows the demodulated time domain pulses Figure 5 19 ( D ) shows the recovered eye diagram. The measurement was implemented by

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118 enabling the PRBS function with the data rate of 660kb/s while the external reader antenna is placed at about one m eter a way from the chip antenna. To check the functionality of the AFE together with the wireless transmission, a pre recorded neural signal was a pplied to the input of the AFE periodically. Figure 5 20 shows the comparison between the amplifier output and the recovered waveform after wireless ly reconstruction. Figure 5 20 Comparison between a mplified and w ireless r ecovered s ignal The entire chip po wer dissipation is around 190 W while the system is fu lly functio ning A pie char t for the power distribution is shown in Figure 5 21 The power dissipation of the AFE and the TX in this chip is no longer the dominant portion of the entire power By utilizing a passive backscattered transmitter the majority power consumption in the TX chain comes from the low frequency osci llator and the digital buffer s The dominant power dissipation of this chip

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119 comes from the l ogic block that perform s the task of data packetizing which can be further optimized by using sm aller width transistors Figure 5 21 Pie c hart of the p ower d istribution Table 5 1 lists the summarized system parameters The AFE used in this system is the same design but different version of the structure described in section 3 2, so the measurement results are differen t. Table 5 1 Performance s ummary of a ctive n eural t ransponder Parameter Value Technology 0.13 Supply 0.8 1.2V Total power 19 0 Chip area 1. 64 mm 2 # of Channels 4 THD @ (1 .5 mV) <0. 6 % CMRR/PSRR >60dB 3dB freq. Low 85 300 Hz 3dB freq. High 4 8 .5 kHz Mid band gain 53.5 dB Current 1 st stage 2 .5 Input Ref. noise 12.5 (NEF~ 8.6 ) ADC res. /Samp. rate 8 bit/ 8 k 44 kHz TX Mod. Backscatter/OOK Data rate 38 0kb/s 1 Mb/s RX Mod. ASK /PWM Input sensitivity 2 8dBm 5.6 Design Summary This chapter introduced an ultra low power 4 channel neural recording system. The time multiplexed amplifie r and the ADC convert the weak neural signal into a serialized bit stream

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120 Full duplex operation is guaranteed for the passive backscattered TX and low power RX. The NEF of the time multiplexed amplifier achiev es a value of 8 .6 The entire system dissipates 190 W and occupies an area of 1.64mm 2 This system also exhibits great potential of being scal ed to a system with larger channel counts in subsequent generations.

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121 CHAPTER 6 6 A 20 N EURAL RECORDING TAG WITH SUPPLY CURRENT MODULATED AFE IN 0.13 m CMOS TECHNOLOGY This chapter describes a low power and highly integrated tag for perpetual recording of neural signal. The system achieves low power and energy efficient by utilizing a supply current modulat ed analog front end (AFE) and a low power backscattered transmitter. The syst em also includes an 8 bit SAR ADC, a low frequency oscillator, a passive receiver and a low power frequency decoder This system allows for user control of the oscillator frequency and the amplifier bandwidth. The measured total input referred noise is 14 V integrated from DC to 50 kHz with noise efficiency factor (NEF) of 6 This chip was fabricated by using UMC 130nm CM OS process with total area of 1.44 mm 2 while full functioning 6.1 Motivation During the p ast several decades, B M I ha s emerged as a promising technology that helps understand the interactions between neurons and the brain behavior relationships The implementation of B M I experiments usually involves non human animal models such as rats mice, or non human primates The experiment al achievements implicate a better insight of human pathology and neural therapy with applications range from neuromuscular disorders spinal cord injuries, to treating epilepsy. However there exists various design cons iderations for acquir ing the neural signal with higher quality and longer period but being less invasive For instance, any tethered hardwire will not only augment the risk of skin irritation and the possibility of infection, but also affect the experiment al result if the animals are aware of the existence of hardware connection T herefore modern BMI systems call for wireless communication and powering Moreover, the power consumption of the BMI system s is a nother critical design consideration which affects the system performance such as the recording lifetime, the range of wireless

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122 transmission and the heat damage to cells. Additionally, because of the limited space at the recording site, the entire BMI device should be high ly integrat ed with minimu m off chip component s The typical structure of modern neural micro system s may incorporate (not necessary) the functions including amplification, A/D conversion, digital processing, and wireless transmission through a short range. The main difference s am ong designs lie in the powering strateg ies number of channels, data rate, and the range of transmission Systems utilizing a small battery [11] [12] [13] [14] successfully eliminate the hardwire connection for powering but has limited recording lifetime due to the finite capacity. For permanently powering the device without using a battery, the systems can utilize a low frequen cy and clos e proximity inductive link [6] [15] [16] Nevertheless this kind of powering method require s a coil, and the range is limited within several tens of centimet ers. More recently, the attempt of constructing a single channel system with only low power elements (AMP, ADC, TX & RX) exhibits great efficiency improvement which makes the far field wireless powering and communication feasible [20] [21] This technique significantly increases the animal mobility and reduces the size of the final prototype by using the single antenna approach However, far field powering with a relatively small energy provision su ffers the limited power available for the system and also limits the number of channel counts Th e proposed system in this chapter utilizes an adaptive powering strategy for laboratory research which can be powered by either the wireless link or a small ba ttery In the cases of fixed animal mobility and clear wireless path, far field powering is feasible with unlimited recording time, whereas in the condition s with more restriction s switching to the b attery power mode will increas e the transponder sensitiv ity and allow for a larger range of communication. Th e proposed system also utilizes several power saving techniques that support the far field

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123 transmission: (1) the use of the supp ly current modulation amplifier to reduce the average power consumption in the analog front end (AFE) and allocat e larger instantaneous power during track time for amplification, processing, and communication; (2) an uplink communication using the far field backscattering technique which shifts the burden of generating the high e st frequency to the external devices; and (3) a low power receiver that allows for the user control of the system bandwidth and the sampling rate to reduce the redundant power consumption. This chapter is organized as follows. Section 6 2 describes the sys tem level design considerations Section 6 3 introduces the wireless powering strategy and the techniques for full duplex operation. Section 6 4 and section 6 5 demonstrate the TX and RX train operation respectively Section 6 6 presents the measurement result and s ection 6 7 draws a simple conclusion of this design. 6.2 System Level Design Consideration s There are several critical design issues and tradeoffs need to be considered at the system level: the input referred noise versus the power consumption, the gain of the pre amplifier versus the resolution of the ADC the bandwidth of the AFE versus the data rate of transmission, and the size of recording device versus the efficiency of the antenna. The following of this section describes how modern BMI system s deal with those design issues. One of the most significant design parameter s in the BMI system s is the input referred noise. According to the practical measurement results the amplitude available at the input of the system is around or below 100 V in most cases with the background noise of around total input referred noise of the BMI system should be limited within that range too The maximum allowable input referred noise sets the lower limit of the current consumption of the fron t end amplifier Since the total noise floor is around the ADC should be chosen

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124 below that value. Assuming the pre amplification stage has a gain of 60dB, a n ADC with reference of 1V and the resolution of 8 bits has the LSB of 4 the noise level and enough to discern the input signal. In order to reduce the power consumption of the amplifier without sacrificing the noise performance this design utilizes a supply current modulation scheme to lower the avera ge supply current without much reduction of the noise efficient factor (see section 3 3) To avoid redundant sampling speed and thus excess power dissipated in the digital block, this system allows for user control of the amplifier bandwidth and the sampl ing rate together Since t he Nyquist rate of sampling is determined by the bandwidth of pre amplification stage the entire on chip oscillating frequency is adjusted to follow the changing of the bandwidth of the amplifier. For instance, lowering the bandwidth of the amplifier reduces the sampling frequency required; by reducing the oscillator frequency accordingly the power consumption of all digital parts is therefore decreased. Perpetual or permanent data acqui sition necessitates the use of wireless powering from a short distance. However, the stringent implant site or the carry on size limits the size of antenna and calls for the far field wireless powering. Thus, except for reducing the power consumption of th e BMI system, it is important to improve the efficiency of the antenna and the rectifier. This design utilizes a matching network between the antenna and input of the rectifier to maximize the power delivery. To avoid the highest frequency generate d on ch ip, this design utilizes a passive backscatter ed transmitter and modulat es the instant RF carrier which results in obviously power reduction for communication The overall system function diagram is shown in Figure 6 1 which consists of the on chip

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125 part and several o f f chip components. The on chip part is comprised of three building blocks, the system powering block, the transmitter chain, and the receiver chain. The off chip part includes a switch that allow for choosing between the wireless power mode BS the battery power mode the electrodes for probing the neural cells and a matching network for impedance matching between the antenna and the r ectifier Figure 6 1 System b lock diagram The single antenna connected to the power acquisition block is also used by the transmitter chain and the receiver chain In the power acquisition block, the lim iter and the regula tor stages follow the rectifier and provid e a stable supply for the rest of the system In the transmitter chain, in order to achieve better energy efficiency, the bias current of the first stage amplifier is modulat ed by the controlling clock with 10% duty cycle, separating the amplifier from an active track mode to a low power hold state. A n on chip low fre quency oscillator (several Mega H ertz) modulates the streaming data from the ADC output. T he modulated signal drives the large backs cattering switch to short or open the two nodes of the antenna, creating a sideband around the RF carrier. The low frequency envelop of the RF source contains the controlling information of the chip setting s The passive envelop detector demodulates the en velop and is followed by the frequency to digital

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126 decoder, which extracts the command information from the frequency of the envelop The receiver chain the correspondingly sampling frequency ( f ess ) and the oscillator frequency The f ull duplex operation is ensured in th is system for both transmitting and receiving with one shared antenna 6.3 System Powering Figure 6 2 Schematic of the rectifier, limiter and storage capacitor As shown in the system function diagram in Figure 6 1 the chip has two powering modes controlled by an off chip switch. The battery mo de allows for wider transmission range but has limited recording lifetime, while the wireless power mode maximize s the recording time but at the expense of less communication range In the wireless powering chain as shown in Figure 6 2 there is a balun performing the RF signal transformation from single ended to differential ended The matching network s at both sides of the balun are used for maximizing the power deliv ery from the antenna to the rectifier. The full wave RF to DC rectifier has four stages with efficiency optimized at 915MHz ISM band. Each stage uses two low threshold NMOS transistors for low turn on voltage and large forward charging current, which helps improve the input sensitivity. Following the rectifier is a limiter that protects the circuit s from over voltage and stabilizes the supply for the rest of the system even with variable powering range. A 0.6nF PMOS capacitor after the limiter stores the ch arge delivered from the rectifier

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127 Figure 6 3 Schematic of the bias generator and the low dropout regulator To further stabilize the supply, a voltage regulator with a large size output transist or is utilized as shown in Figure 6 3 The regulator can operate with a drop out voltage as low as 150mV. 6.4 Receiver Chain and Full Duplex Operation As shown in the system f unction diagram in Figure 6 1 t his system has transmitter (TX) and receiver (RX) chains that share one single antenna. There may have several problems caused by the single antenna approach while perform ing the full duplex operation The connection of RX and TX forms a loop, therefore the TX signal may couple into the receiver chain and act as noise, which may s aturate the envelop detector and totally block the communi cation path in the RX chain. In this design two major techniques are used to help attenuate the TX noise in the RX chain as shown in Figure 6 4 First, n oticing that the backscattering switch has very large size width), which generate s large switching noise at both rising and falling edge s of the TX signal. So

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128 t wo half size dummy switches S D are placed at both positiv e and negative path of the receiver Those two switches are controlled by the inverting signal of the modulated TX signal to cancel the TX signal feed through and the charge injection from the backscattering switches S b Second, by taking advantage of the frequency difference between the TX a nd RX signals, the receiver chain uses two low pass filters with the cut off frequencies far below the TX band to further attenuate the TX signal coupled into the receiver chain. Figure 6 4 Schematic of t he envelop detector The modulated RF signal is received from the antenna and passed to a 2 stage rectifier Each stage uses the same but single ended structure as in the power rectifier stage The rectified envelop is fed into two low pass filter s (LPF) w ith different cut off frequencies, one is around 20 kHz for passing the envelop, the other is below 1 k Hz to generate a reference with much less ripple. By comparing those two filtered output s the rail to rail envelop signal is available which is then fed into the frequency to digital decoder The decoder extracts 4 bits to tun e the amplifier bandwidth and the oscillator frequency. The schematic of the frequency decode r is shown in Figure 6 5 The envelop signal V ENV acts as the clock and controls a charge pump with charge integrated on C INT to create a saw tooth waveform called V INT V INT has amplitude inverse proportional to the frequency of V ENV V INT is

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129 then sent to a peak detector, creating a reference voltage, V PEAK At the top of the schematic, the succession of flip flops creates a se ach signal activate s a different level from the bias generator for a consecutive comparison to V PEAK The flip flops at the bottom of the schematic interpret the comparison to set the corresponding one of the four co ntrol bits. These active bits are used to set the system bandwidth and the sampling rate. The latched comparator is used here to avoid chatter during comparison due to the reverse leakage of the diode in the peak detector. Figure 6 5 Schematic of f requency to d igital d ecoder 6.5 Transmitter Chain T he front end of the transmitter chain is the current modulated amplifier described in

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130 section 3 3 The ADC that follows the amplifier has the similar ADC structure utilized in the system described in Chapter 5. The bandwidth of the front end amplifier and the sampling frequency of the ADC are tunable by external user s Figure 6 6 Schematic of clock generator. The amplified and digitized neural data is first modulated by the oscillator and then buffered through a series of inverters to drive the large backscatter ing switch S B The frequency of the

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131 oscillator is tuned by 4 bits acquired from the r eceiver chain and has the rang e from 1.2 MHz to 6.4 MHz Since the highest frequency on chip is used to create the sideband of the RF carrier, this method shifts the burden of generating the RF frequency to th e external devices, greatly reduc ing the power consumption in the transmitter chain The schematic of the oscillator that provides the system clocking and modulation is shown in Figure 6 6 The frequency of the ring oscillator is controlled by the tuning bits S1 S4 and their complements S1B B4B. Each stage of the ring oscillator consists of the current starve inverter. By changing the number of current starve stages, t he frequency is tunable. For example, if S1 S4 are all shorted, there are totally 3 stages oscillati n g If S1 S4 are all open, there are totally 15 stages oscillating. The switches that either shorts or open the stages are comprised of transmission gates. The CLK signal is the further division of oscillator output by 8 cycles The ring o scillator achieves low power by limiting the maximum current that flows in each curr ent starve stage. 6.6 Measurement Result Figure 6 7 Die p icture The chip was fabricated by using the UMC130nm technology. T he die picture is shown in Figure 6 7 with the total area of 1. 5 4mm 2

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132 A B C Figure 6 8 Wireless measurement. A) Measurement s etup B) comparison between o riginal and w ireless r econstructed s ignal and C) backscattered s pectrum Figure 6 8 ( A ) show s the wireless measurement setup. A prerecorded neural signal is fed to the input of the neural t ag, and the wireless power mode is chosen. On the reader side, there is a

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133 circulator connecting the antenna to attenuat e the RF carrier coupled to the signal analyzer by 20dB. Moreover, a notch filter is placed in front of the signal analyzer which has the notch frequency centered at 915MHz The notch filter provide s an additional attenuation of 40dB to avoid the carrier from saturating the signal analyzer The modulated RF carrier is fed into a power amplifier to increase the communication range. A B C D Figure 6 9 Components of the example p rototype A ) Top v iew of PCB B ) b ottom v iew of PCB C ) t op c over of the p lastic e nclosure and D ) bottom cover of the p lastic e nclosure Figure 6 8 ( B ) shows the over lapping comparison between the original and the wireless reconstructed neural signal. Figure 6 8 ( C ) shows the measured backscattered spectrum, with two modulated side band s located at around 5 MHz apart from the carrier.

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134 Figure 6 10 A ssembled p rototype Figure 6 9 shows the components used in the example BMI prototype which includes two plastic enclosure s and a two layer PCB The top layer of the PCB is shown in Figure 6 9 ( A ) The top layer shows the footprint for the Omnetic Connector the footprint for the power option switch and the footprint for the helix antenna. The bottom layer is shown in Figure 6 9 ( B ) The bottom layer hosts the IC in the QFN32 package which has the tiny size of 5mm by 5mm The bottom layer also includes the footprint s for the matching network and a balun. The PCB measures 17mm by 16.5 mm. In order to shield the PCB from abnormal short by direct contact, the assembled PCB is covered by a custom designed plastic enclosure. The top side of the enclosure is the user control side, w hich has two slots as shown in Figure 6 9 ( C ) The rectangular slot allows user to toggle the power op tion switch T he two round slot s host the two coin batteries and allow for the re plac ement

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135 of the battery The bottom enclosure is shown in Figure 6 9 (D ) which has a groove with enough space for hosting the matching components on PCB. This design uses two commercial zinc air (ZA10) batteries with capacity of 91mA and the operation voltage around 1.2V. The populated and packaged PCB with the electrodes connected is shown in Figure 6 10 The overall weight after assembly is 2.68 grams, dominated by the weight of the plastic. Future revisions may entail the use of the specialized plastics and the components for decreased mass. The maximum length and width of the prototype is about 30mm and 17mm, respectively. T he entire prototype only utilizes standard an d low cost components that can be easily acquired from commercial distributors. Figure 6 11 In Vivo m easurement of the n eural s ignal The amplifier alone was measured at in vivo environment. Figure 6 11 shows th e measured neural waveform for about 1 sec and the zoomed in version. Table 6 1 Performance s ummar y of n eural r ecording t ag

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136 Parameter Value Technology 0.13 Supply 0.8 1V Total power 20 Chip area 1.54 mm 2 # of Channels 1 THD @ (1mV) < 0.4 % CMRR 59 dB PSRR 50 dB 3dB freq. Low/High 100 Hz/2.5 k 6.2 k Mid band gain 49 dB Current 1 st stage 0.8 Input Ref. noise 14 .5 ) ADC res. /Samp. Rate 8 bit/15 k 80 kHz TX Mod. Backscatter/OOK Data rate 150 kb/s 0.8 Mb/s RX Mod. ASK Input sensitivity 8 dBm Table 6 2 Performance comparison between the proposed systems and the state of the art Wise [18] Harrison [17] Najafi [33] Mohseni [27] Otis [21] Chapter 5 Chapter 6 Year 2009 2007 2004 2011 2010 2009 2010 No. of c hannel s 64 100 64 8 1 4 1 Power s ource Inductive Inductive Inductive Battery Far Field Battery Far Field TX d ata Telemetry FSK ASK ASK FSK UID OOK OOK TX Freq. (MHz) 200 433 ~100 900 915 915 RX d ata t elemetry OOK FSK OOK PIE ASK ASK RX Freq (MHz) 4/8 2.64 5.12 433 900 915 915 Front e nd g ain (dB) 60 60 40 51 66 38.5 53.5 49 Low c utoff Freq. (Hz) 10 100 300 10 1.1 525 0.2 85 300 100 Bandwidth (kHz) 9.1 5 10 5.1 12 0. 23 4 8.5 2.5 6.2 Input Ref. n oise ( V ) 4.8 5.1 7.8 3.12 1.25 12.5 14 Power Diss. ( mW ) 14.4 13.5 12.7 0. 375 0.00 9 2 0. 19 0.0 2 T he measured parameters of the proposed system are listed in Table 6 1 The AFE used in this system is the same design but different version of the structure described in section 3 3, so the measurement results are different. Table 6 2 lists the comparison result of the proposed two BMI systems and the state of the art. The proposed two systems in Chapter 5 and Chapter 6 are both energy efficient with the total power consumpt ion in the micro watts range. The improvement is achieved by using the passive backscattered transmitter and the energy efficient

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137 amplifiers described in section 3 2 and se ction 3 3 for those two systems respectively The design in [21] also utilizes the passive TX and has the least total power consumption, since the front end amplifier requires only 0.23 kHz bandwidth for sensing its neural inputs and thus the front end power consumption is much less com pared to our designs. 6.7 Design Summary This chapter intr oduce s a highly integrated neural recording tag which has minimum external components. The entire circuit can be powered through the wireless link or a small battery. Th is design achieves energy efficiency by ut iliz ing the supply current modulated amplifier and the backscattered transmitter The AFE bandwidth and the oscillator frequency are jointly tunable by external user to avoid excess power dissipation.

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138 CHAPTER 7 7 CONCLUSION This aim of this dissertation was to examine the design of low power circuits and systems utilized in BMIs. Each building block of a BMI system was discussed in detail. Owing to its importance in determining the overall system power consumption and noise p erformance, the AFE in particular, the neural amplifier was emphasized in this work. Other building blocks, such as reference and biasing, ADC, and the TX and RX chains, were also discussed in terms of their relevant low power design considerations. This work presented three new neural amplifier architectures. The first amplifier type employs a structural improvement in which two channels are cascaded at the input stage so that the bias current can be reused and the average current consumption reduced. The second type utilizes the switched capacitor technique to implement a multi channel BMI system in which four independent channels share one single OTA via a time multiplexing mechanism to conserve area and reduce power consumption while maintaining the noi se efficiency factor. The third architecture uses a supply current modulation technique to reduce the average amplifier power consumption without sacrificing the noise efficiency factor. Owing to the weakness of the neural signal (<1 mV), a BMI system mus t have high input sensitivity and thus low input referred noise; the maximum allowable input referred noise determines the lower limit of current consumption of the front end amplifier. The cascaded structure described in this work optimizes amplifier perf ormance in terms of the tradeoff between power consumption and noise because both the top and bottom amplifiers reuse the bias current of the input differential pair. Because the nominated bias current is shared but kept identical between two channels, noi se production is mostly unaffected but the post averaging effective current consumption of each amplifier is reduced.

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139 Because neuroscientists and researchers in biomedical engineering require BMI systems that are capable of simultaneously acquiring neural information from a large population of neurons, the transition or multiplexing of neural signals from parallel channels into a serial data stream is required for signal processing and wireless transmission in such devices. In general, increased channel co unts result in higher power and area consumption as well as higher data rates, all of which pose formidable challenges. To help address these issues, the second amplifier described in this work merges the multiplexing function with the track and hold funct ion inside of an OTA; in doing so, the stages succeeding the amplifier can be shared among multi channels to achieve optimal area and power saving. Neural amplifiers usually have a pair of large input differential transistors to maximize the transconducta nce at the given current consumption, while the other neural amplifier transistors usually have lower W/L ratios to reduce the transconductance at the given current level. Thus, the input referred noise contribution of transistors other than the input diff erential pair is attenuated. However, under extreme low bias conditions it is difficult to achieve a high transconductance ratio between the input differential pair and the other transistors. The third amplifier type described in this work uses the supply current modulation scheme to achieve a large instantaneous bias current during the track time relative to that of a conventional amplifier, and it does so without changing the average current consumption. Thus, this type of amplifier successfully attenuate s the noise contributions of transistors other than the input different pair during the track time and provides better noise performance. Because time multiplexed and supply current modulated amplifiers both utilize the track and hold function, this disser tation analyzed both types using a single simplified model in which the track and hold amplifier (T/H_Amp) was mathematically equated to a model track and hold RC

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140 filter. To analyze the transfer function and noise aliasing of track and hold RC filters, thi s work provided a detailed derivation procedure for solving the harmonic transfer function. From the derivation results, two important conclusions that also apply to track and hold amplifiers can be drawn: (1) the bandwidth of the T/H_ RC filter is reduced in proportion to the reduction in duty cycle of the T/H clock, and (2) the aliased noise power spectral density is inversely proportional to the duty cycle. Because both the time multiplexed and the supply current modulated amplifiers have their current co nsumption averaged in proportion to the duty cycle, their overall noise efficiency factors remain the same. Aside from the AFE, other major BMI components such as the system powering and wireless transmission blocks also greatly affect the overall perfor mance. Two major powering methods are used in modern BMI systems: local powering from a battery, and wireless powering through a telemetry link. Increasing the number of channels used requires more frequent replacement of a battery in locally powered syste ms, while wirelessly powered links must use a larger coil or a shorter powering range as more channels are added. Data transmission is also affected by channel count increase, which requires that higher data rates and more bandwidth be adopted. The first s 915 MHz active neural transponder with a four channel time multiplexed AFE, uses a passive backscattered transmitter that shifts the burden of generating the highest RF frequency to an external device to save power. I t uses a 915 MHz carrier that has a sufficient bandwidth of up to 16 MHz The entire four channel system high density battery for several months, a necessary cha racteristic for conducting bench top neural studies. Owing to its lower power consumption, this system shows much potential for future scalability into low power systems with larger number of channels.

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141 The second neural recording system described in this w with a supply current modulated AFE, enables the user to adaptively choose powering strategies. This BMI system has battery power and wireless power mode options and can remain permanently powered and fully functional thro ugh a far field wireless link with a current draw of only 20 A. This low power consumption is achieved by utilizing an energy efficient supply current modulated amplifier and a backscattered passive transmitter. If a larger transmission range is required, this system can be switched to a battery powered mode. To summarize, this dissertation described three new amplifier structures and discussed their respective improvements in terms of noise, area, and power consumption. Two neural recording systems were also introduced and were shown to be extremely energy efficient, with efficiencies comparable to those of state of the art systems. The two proposed systems were evaluated by comparing pre recorded neural signals fed into the front end of each with the res ulting wireless reconstructed signals. However, further work can be performed to characterize the entire BMI. The four channel system introduced in Chapter 5 can be assembled as a miniature prototype of the system described in Chapter 6. The overall system functioning of the two neural recording systems introduced here can be further evaluated within an in vivo environment that can record the action potentials at the cellular level. Finally, an augmented external reader can be designed to enable real time r ecovery of original neural signals.

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142 LIST OF REFERENCES [1] K. D. Wise, J. B. Angell, and A. Starr, "An integrated circuit approach to extracellular microelectrodes," IEEE Transactions on Biomedical Engineering, Vols. BME 22, pp. 283 247, 1 970. [2] K. Najafi and K.D.Wise, "An implantable microelectrode arrays with on chip signal processing," Journal of Solid State Circuit, Vols. SC 21, pp. 1035 1044, 1986. [3] Kenneth D. Harris, Darrell A. Henze, Jozsef Csicsvari, Hajime Hirase, and Gyorgy Buzsaki, "Accuracy of tetrode spike separation as determined by simultaneous intracellular and extracellular measurements," Journal of Neurophysiology, vol. 84, pp. 401 414. [4] C. L. Rogers, "Ultra Low power analog circuits for spike feature extration and detection from excellular neural recordings," Dissertation, THE UNIVERSITY OF FLORIDA, 2007. [5] K. Wise, D. Anderson, J. Hetke, D. Kipke, and K. Najafi, "Wireless impl antable microsystems: High density electronic interfaces to the nervous system," Proceedings of the IEEE, vol. 92, pp. 76 97, 2004. [6] R. R. Harrison and C. Charles, "A low power low noise CMOS amplifier for neural recording applications," IEEE Journal of Solid State Circuit, vol. 38, pp. 958 965, 2003. [7] O. Toneta, M. Marinellia, L. Citia, P. M. Rossinic, L. Rossinic, G. Megalia and P. Dario, "Defining brain machine interface applications by matching interface performance with device requirements, Journal of Neuroscience Methods, vol. 167, no. 1, pp. 91 104, 2008. [8] Neuralscience, "Wikipedia," 5 July 2012. [Online]. Available: http://en.wikipedia.org/wiki/Neuroscience. [9] D. R. Kipke, "Implantable neural probe systems for cortical neuroprostheses," IEEE EMBC, vol. 2, pp. 5344 5347, 2004. [10] Cameron T. Charles, Implantable Neural Recording System, The Department of Electrical and Computer Engineering, University of Utah August 2003. [11] Otis. B, "A 500W neural tag with 2Vrms AFE and frequency multiplying MICS/ISM FSK transmitter," IEEE ISSCC Dig. Tech. Papers, pp. 212 213, Feb. 2009. [12] P. Mohseni, K. Najafi, "A Battery Powered 8 Channel Wireless FM IC for Biopotential Recording Applications," IEEE ISSCC Dig. Tech. Papers, pp. 560 561, Feb. 2005.

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143 [13] Z. Xiao, C. Tang, C. Peng, R. Bashirullah, "A 190W 915MHz active neural transponder with 4 channel time multiplexed AFE," IEEE Symposium on VLSI Circuits, pp. 60 61, Jan. 2009. [14] S. Farshchi, P. H. Nuyujunkian, A. Pesterev, I. Mody, and J. W. Judy, "A TinyOS enabled MICA2 based wireless neural interface," IEEE Trans. Biomed. Eng., v ol. 53, pp. 1416 1424, 2006. [15] C. Chestek, P. Samsukha, M. Tabib Azar, R. Harrison, H. Chiel, and S. Garverick, "Wireless multi channel sensor for Neurodynamic studies," in Proc. IEEE Sensors Conf., pp. 915 918, 2004. [16] H. Yu, P. Li, Z. Xiao, C. C. Peng, and R. Bashirullah, "A Multi Channel Instrumentation System for Biosignal Recording," in IEEE EMBS Vancouver, Canada, pp. 2020 2023, Aug. 2008. [17] R. R. Harrison, P. T. Watkins, R. J. Kier, R. O. Lovejoy, D. J. Blac k, "A Low Power Integrated Circuit for a Wireless 100 Electrode Neural Recording System," IEEE J. Solid State Circuits, vol. 42, no. 1, pp. 123 133, 2007. [18] Ken Wise, K. Najafi, "An Implantable 64 Channel Wireless Microsystem for Single Unit Neural r ecording," IEEE J. Solid State Circuits, vol. 44, no. 9, pp. 2591 2604, 2009. [19] M. Ghovanloo, Seung Bae Lee, "In Vivo Testing of A Low Noise 32 Channel Wireless Neural Recording System," Proc. IEEE EMBS Conf, pp. 1608 1611, Sep. 2009. [20] Z. Xiao Supply Current IEEE ISSCC Dig. Tech. Papers, pp. 122 123, Feb. 2010. [21] nsor Tag for Biosignal Acquisition," IEEE J. Solid State Circuits, vol. 45, no. 10, pp. 2198 2209, 2010. [22] M. F. a. R. S. W. Wattanapanitch, "An Energy Efficient Micropower Neural Recording Amplifier," IEEE Trans on Biomedical circuits and systems, v ol. 1, no. 2, 2007. [23] nV/rtHz Chopper Stabilized Instrumentation Amplifier for Chronic Measurement of Neural Field Potentials," IEEE Journal of Solid State Circuit, vol. 42, no. 12, pp. 2934 2945, 2007. [24] H. H. G. S. a. C. D. T. Seese, "Characterization of tissue morphology, angiogenesis, and temperature in the adaptive response of muscle tissue to chronic heating," Lab. Invest, vol. 78, no. 12, pp. 1553 1562, 1 998.

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144 [25] Naveen Verma, Ali Shoeb, Jose Bohorquez, Member, Joel Dawson, John Guttag, and Anantha P. Chandrakasan, "A Micro Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System," Journal of Solid S tate Circuit, vol. 45, no. 4, pp. 804 816, 2010. [26] Hua Gao, Ross M. Walker, Paul Nuyujukian, Kofi A. A. Makinwa, Krishna V. Shenoy, Boris Murmann, Teresa H. Meng, "A 96 Channel Full Data Rate Direct Neural Interface in 0.13 m CMOS," Journal of Solid State Circuit, vol. 47, no. 4, pp. 1043 1055, 2012. [27] Meysam Azin, David J. Guggenmos, Scott Barbay, Randolph J. Nudo, Pedram Mohseni, "A Battery Powered Activity Dependent Intracortical Microstimulation IC for Brain Machine Brain Interface," Journal of Solid State Circuit, vol. 46, no. 4, pp. 731 745, 2011. [28] Seung Bae Lee, Hyung Min Lee, Mehdi Kiani, Uei Ming Jow, Maysam Ghovanloo, "An Inductively Powered Scalable 32 Channel Wireless Neural Recording System on a Chip for Neuroscience Applicati ons," IEEE Trans on Biomedical Circuits and Systems, vol. 4, no. 6, pp. 360 371, 2010. [29] Rikky Muller, Simone Gambini, and Jan M. Rabaey, "A 0.013 mm2, 5 uW, DC Coupled Neural Signal Acquisition IC With 0.5 V Supply," Journal of Solid State Circuit, vol. 47, no. 1, pp. 232 243, 2012. [30] Moo Sung Chae, Zhi Yang, Mehmet R. Yuce, Linh Hoang, and Wentai Liu, "A 128 Channel 6 mW Wireless Neural Recording IC With Spike Feature Extraction and UWB Transmitter," Transactions on Neural Systems and Rehabitation Engineering, vol. 17, no. 4, pp. 312 321, 2009. [31] C. C. Enz, F. Krummenacher, and E. A. Vittoz, "An analytical MOS transistor model valid in all regions of operation and dedicated to low voltage," Analo g Integrat. Circuits Signal Process, vol. 8, p. 83 114, 1995. [32] S. L. a. P. Combes, "On radiating zone boundaries of shor, lambda/2, and lambda dipoles," IEEE Antennas and Propagation Magazine, vol. 46, no. 5, pp. 53 64, 2004. [33] H. Yu, R. H. Ol sson III, K. D. Wise, and K. Najafi, "A wireless microsystem for multichannel neural recording microprobes," Solid State Sensor, Actuator, and Microsyst. Workshop pp. 107 110, June, 2004. [34] M. O. N. A. J. C. S. a. T. N. Erin Patrick, Design and F abrication of a Flexible Substrate Microelectrode Array for Brain Machine Interfaces, IEEE EMBS Conference, 2006. [35] V. S. W. R. S. F. Y. J. C. S. a. T. N. Erin Patrick, Flexible Polymer Substrate and Tungsten Microelectrode Array for an Implantable N eural Recording System, Vancouver, British Columbia, Canada: IEEE EMBS Conference, 2008.

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145 [36] M. F. M. R. D. B. P. R. Marc Olivier Heuschkel, A three dimensional multi electrode array for multi site stimulation and recording in acute brain slices, Journ al of Neuroscience Methods, 2001. [37] E. H. G. H. G. K. Istvan Ulbert, Multiple microelectrode recording system for human intracortical applications, Journal of Neuroscience Methods, 2000. [38] K. E. J. R. J. H. K. W. H. R. A. N. Patrick K. Campbell, A Silicon Based, Three Dimensional Neural Interface: Manufacturing Processes for an Intracortical Electrode Array, IEEE Transactions on Biomedial Engineering, 1991. [39] B. H. U. S. U. v. R. U. S. U. G. Jan Gimsa, Choosing electrodes for deep brain stimulation experiments electrochemical considerations, Journal of Neuroscience Methods, 2004. [40] Analog Devices, "Sample and Hold Amplifiers," MT 090 Tutorial. [41] M. S. J. Steyaert, W. M. C. Sa nsen, and C. Zhongyuan, "A micropower low noise monolithic instrumentation amplifier for medical purposes," IEEE J. Solid State Circuits, vol. 22, pp. 1163 1168, 1987. [42] Carolina Mora Lopez, Dimiter Prodanov, Dries Braeken, Ivan Gligorijevic, Wolfgan g Eberle, Carmen Bartic, Robert Puers, Georges Gielen, "A Multichannel Integrated Circuit for Electrical Recording of Neural Activity, With Independent Channel Programmability," Journal of Solid State Circuit, vol. 6, no. 2, pp. 101 110, 2012. [43] Chen gliang Qian, Jordi Parramon, Edgar Snchez Sinencio, "A Micropower Low Noise Neural Recording Front End Circuit for Epileptic Seizure Detection," Journal of Solid State Circuit, vol. 46, no. 6, pp. 1392 1405, 2011. [44] Qinwen Fan, Fabio Sebastiano, Johan H. Huijsing, Kofi A. A. Makinwa, "A 1.8 W 60 nV Hz Capacitively Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes," Journal of Solid State Circuit, vol. 46, no. 7, pp. 1534 1543, 2011. [ 45] Nick Van Helleputte, Sunyoung Kim, Hyejung Kim, Jong Pal Kim, Chris Van Hoof, Refet Motion Artifact Suppression," in IEEE, ISSCC San Francisco, 2012. [46] Vahid Majidzadeh,Alexandre Schmid, and Yusuf Leblebici, "Energy Efficient Low Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor," IEEE Transactions ON Biomedical Circuit and System, vol. 5, no. 3, pp. 262 271, 2011. [47] A. R. Kahn, E. Y. Chow, O. Abdel Latief, and P. P. Irazoqui, "Low Power, High Data Rate Transceiver System for Implantable Prostheses," Int J Telemed Appl, Jan. 3, 2011.

PAGE 146

146 [48] Joel Phillips and Ken Kundert, "An Introduction to Cyclostationary Noise," The Designer's Guide Community, 2007. [Online]. Available: http://www.designers guide.org/Theory/cyclo paper.pdf. [49] J. Aziz, R. Genov, M. Derchansky, B. Bardakjian, and P. Carlen, "256 channel neural recording microsystem with on chip 3 D electrodes," IEEE J. Solid State Circuits, vol. 44, no. 3, pp. 995 1005, 2009. [50] M. Mollazadeh, K. Murari, G. Cauwenberghs, N. Thakor, "Micropower CMOS Integrated Low Noise Amplification, Filtering, and Digitization of Multimodal Neuropotentials," IEEE Trans on Biomedical circuits and systems, vol. 3, no. 1, 2009. [51] J. Carmena, M. Lebedev, R. Crist, J. O'Doherty, D. Santucci, D. Dimitrov, P. Patil, C. Henriquez, and M. Nicolelis, "Learning to control a brain machine interface for reaching and grasping by primates," PLoS Biology, vol. 1, no. 2, pp. 193 208, 2003. [52] K. Najafi and K. D. Wise, "An implantable multielectrode array with on chip signal processing," IEEE J. Solid State Circuits, vol. 21, pp. 1035 1045, 1986. [53] H. Fischer, H. Kautz, and W. Kutsch, "A radiotelemetric 2 Channel unit for transmission of muscles during free flight of the desert locust, Schistocerca Ggregaria," J. Neurosci. Methods, vol. 64, pp. 39 45, 1996. [54] Katsuji Kimura, "A CMOS Logarithmic IF Amplifier with Unbalanced Source Coupled Pairs," IEEE J.Solid State Circuits, vol. 28, no. 1, pp. 78 83, 1993. [55] Y. Perelman and R. Ginosar, "Analog frontend for multichannel neuronal recording system with spike and LFP separation," Journal of Neuroscience Methods, vol. 153, pp. 21 26, 2006. [56] S. Mandal and R. Sarpeshkar, "Power efficient impedancemodulation wireless data links for biomedical implants," IEEE Transactions on Biomedical Circuits and Systems, vol. 2, no. 4, pp. 301 315, 2008. [57] I. Obeid, M. A. L. Nicolelis, and P. D. Wolf, "A multichannel telemetry system for single unit neural recordings," Journal of Neuroscience Methods, vol. 133, no. 1 2, pp. 33 38, 2004. [58] A. R. Chandrakasan, N. Verma, and D. C. Daly, "Ultralowpower electronics for biomedical applications," Annual Review of Biomedical Engineering, vol. 10, pp. 247 274, 2008. [59] J.Goette and C.Gobet, "Exact noise analysis of sc circuits and an approximat e computer implementation," IEEE Trans. Circuits and Systems, vol. 3, pp. 508 521, 2989. [60] C.Gobe1 and A.Knob, "Noise analysis of switched capacitor networks," IEEE Trans. Circuits and Systems, vol. 30, pp. 37 43, 1983.

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147 [61] J. H. Fischer, "Noise Sources and Calculation Techniques for Switched Capacitor Filters," IEEE J. Solid State Circuits, vol. 17, no. 4, pp. 742 752, 1982. [62] front end for portable biopotential acquisition systems," IEEE J. Solid State Circuits, vol. 42, no. 5, pp. 1100 1110, 2007. [63] G. P. a. K. Wise, "An Ultra Compact Integrated Front End for Wireless Neural Recording Microsystems," IEEE J. Solid State Circuits, vol. 19, no. 6, pp. 1409 1421, 2010. [64] J. Ji and K. D.Wise, "An implantable CMOS circuit interface for multiplexed microelectrode recording arrays," IEEE J. Solid State Circuits, vol. 27, pp. 433 443, 1992. [65] S. Takeuchi and I. Shimoyama, "A radio telemetry system with a shape memory alloy microelectrode for neural recording of freely moving insects," IEEE Trans. Biomed. Eng, vol. 51, pp. 133 137, 2004. [66] P. Mohseni, K. Najafi, S. J. Eliades, and X. Wang, "Wireless multichannel biopotential recording using an integrated FM telemetry circuit," IEEE Trans. Neural Syst. Rehab. Eng., vol. 13, pp. 263 271, 2005. [67] A. Nieder, "Miniature stereo radio transmitter for simultaneous recording of multiple single neuron signals from behaving owls," J. Neurosci. Methods, vol. 101, pp. 157 164, 2000. [68] C. Enokawa, Y. Yonezawa, H. Maki, and M. Aritomo, "A microcontroller based implantable telemetry system for sympathetic nerve activity and ECG measurement," IE EE Int. Conf. Eng. Med. Biol., pp. 2232 2234, 1997. [69] W. Liu, M. Sivaprakasam, G. Wang, M. Zhou, J. Granacki, J. Lacoss, and J. Wills, "Implantable biomimetic microelectronic systems design," IEEE Eng. Med. Biol., vol. 24, pp. 66 74, 2005. [70] T. Akin, K. Najafi, and R. M. Bradley, "An implantable multichannel digital neural recording system for a micromachined sieve electrode," Proc. Int. Conf. Solid State Sensors and Actuators, pp. 51 54, 1995. [71] C. W. Ko, Y. D. Lin, H. W. Chung, and G. J. Jan, "An EEG spike detection algorithm using artificial neural network with multi channel correlation," Proc. IEEE Eng. Med. Biol. Soc, pp. 2070 2073, 1998. [72] L. S. Pon, M. Sun, and R. J. Sclabassi, "The bi directional spike detection in EEG using mathematical morphology and wavelet transform," Proc. Int. Conf. Signal Process, vol. 2, pp. 1512 1515, 2002.

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148 [73] J. R. Tuttle, "Traditional and emerging technolog ies and applications in the radio frequency identification (RFID) industry," in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium 1997. [74] H. P. Shawn, "Electrical properties of tissue and cell suspensions," Advances in Biological and Medical Physics, vol. 5, pp. 147 209, 1957. [75] K. R. Foster and H. P. Schwan, "Dielectric properties of tissues and biological materials: A critical review," Critical reviews in biomedical Engineering, vol. 1, pp. 25 104, 1989. [76] D. C. Barber and B. H. Brown, "Applied potential tomography," Journal of Physics E: Scientific Instruments, vol. 17, pp. 723 733, 1984. [77] S. Gabriel, R. W. Lau and C. Gabriel, "The dielectric properties of biological tissues: II. Measurements in the frequency range 10 Hz to 20 GHz," Phys. Med. Biology, vol. 41, pp. 2251 2269, 1996. [78] J. Carmena, M. Lebedev, R. Crist, J. O'Doherty, D. Santucci, D. Dimitrov, P. Patil, C. Henriquez, and M. Nicolelis, "Learning to control a brain machine interface for reaching and graspi ng by primates," PLoS Biology, vol. 1, no. 2, pp. 193 208, Nov. 2003. [79] J. Gerald, Goncalo Tavares, "Wireless Transmission of Power and Data to Implants," December 2001. [Online]. Available: http://sips.inesc id.pt/. [80] M. Rizk, C. A. Bossetti, T. A. Jochum, "A fully implantable 96 channel neural data acquisition system," Journal of Neural Engineering, vol. 6, no. 2, p. Article ID 026002, 2009. [81] A. P. van der Wel, H. Wallinga, "MOSFET 1/f Noise Measurement Under Sw itched Bias Conditions," IEEE Electron Device Letters, vol. 21, no. 1, 2000.

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149 BIOGRAPHICAL SKETCH Zhiming Xiao was born in Wuhan China He received the B.S. degree from Huazhong University of Science and Technology Wuhan, China, in 2006 He received his Ph D from University of Florida in the spring of 2014 Since 2006, he has been working in the Integrated Circuits Research (ICR) Lab. His researches focus on low power analog and mixed signal circuit s for biomedical applications. From summer 2011 to spring 2012, h e joined the Linear Technology as an internship at Colorado Springs and his work focuses on power management circuit s design Since October 2012, he worked as a full time employ ee for Linear Technology on low power boost/SEPIC DC DC converters.


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