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1 DEMONSTRATION OF HIGH CURRENT CARBON NANOTUBE ENABLED VERTICAL ORGANIC FIELD EFFECT TRANSISTORS AT INDUSTRIALLY RELEVANT VOLTAGES By MITCHELL MCCARTHY A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FL ORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2010
2 2010 Mitchell McCarthy
3 To my parents
4 ACKNOWLEDGMENTS I am grateful to my research advisor, Professor Andrew Rinzler, for assisting me throughout my graduate research career. I thank him for supporting and advising me and for giving me an exciting research project. His practical approach to solving real his patience and constructive criticism have all benefitted me greatly in developing as a researcher and will continue to benefit me in my future endeavors. I thank my materials science advisor Professor Franky So for advising me and providing gracious a ssistance with my research. His ambitious spirit and results oriented attitude have assisted me in focusing my work while also keeping the big picture in mind. I thank Dr. Brent Gila for serving on my advisory committee and for the many helpful conversatio ns we had on campus concerning various technical topics. I am grateful to Dr. David Norton for serving on my advisory committee and as for teaching me electronic materials. I express by sincere thanks to Dr. Henry Hess and Dr. Jiangeng Xue for serving on m y committee. Also, I thank all of my committee members for providing useful guidance and feedback concerning my research. Also I am grateful to my undergraduate research advisor physics Professor Art Hebard. I thank Art for supporting me as an undergraduat e and for assisting and guiding me in learning how to apply physics principles in an experimental setting. I learned many things from Dr. Hebard which benefitted me greatly throughout my graduate research career. A colleague of mine that deserves great th unwavering commitment to research provided me with an ever present example of how to properly visualize and carry out detailed experiments, to which the outcomes were
5 initially unknown. It is with his help and example that I was able to make progress in my research and to never become distressed under failure. Dr. Zhuangchun Wu Dr. Svetlana Vasilyeva, Rajib Das, Evan Donoghue, Pooja Wadhw a, Po Hsiang Wang, Maureen Petterson, Ramesh Jayaraman, Yu Shen, Matt Gilbert and Tom Hayman. I would also like to thank my research colleagues in Franky Kim, Dr. Kaushi k Roy Choudhury Dr. Jegadesan Subbiah, Dr. Leo Cheung, Dr. Jaewon Lee, Dr. Neetu Chopra, Galileo Sarasqueta, Cephas Small Dongwoo Song, Michael Nesbitt, Dr. Partha Mitra, Dr Sinan Selcuk, Dr. Guneeta Singh Bhalla, Dr. Rajiv Misra, Dr. Sefaattin Tongay, Ritesh Das, Patrick Mickel, Siddhartha Ghosh, Xiaochang Miao and Kara Berke. Also I would like to thank computer engineering Professor Jing Guo and research colleague Dr. Youn gki Yoon for fruitful collaborations. I would like to thank Justin Hall Tipping and Bhabendra Pradhan from Nanoholdings LLC as well as the National Science Foundation for providing funding making it possible for me to do research and attain the degree. I a m grateful to the University of Florida machine shop staff. I am especially grateful to engineer Bill Malphurs. Bill taught me many machine related things, such as CNC machining and welding, among many others, as well as salt water fishing. Working with Bi ll has been a great pleasure, and we have co designed and built many key pieces of equipment which made the work described in this dissertation possible. I am also grateful to machine shop supervisor Marc Link and machinists Ed Storch, Mike
6 Herlevich, Raym ond (Skip) Frommeyer and John Van Leer. I would like to thank the Physics Department support staff, Darlene Latimer, Greg Labbe, Brent Nelson and John Graham and the electronics shop staff, Pete Axson and Larry Phelps. I am grateful for the helpful assista nce that was always provided to me by the materials science academic services office, I thank Martha McDonald, Jennifer Horton and Doris Harlow. Also, I would like to thank the University of Florida Nanoscale Research Facility staff for providing the train ing and equipment necessary for many of the experiments in this dissertation. I thank Dr. Bill Appleton, and engineers Bill Lewis, David Hays and Al Ogden. I would like to thank my family for giving me the foundation and values to succeed on my own and fo r always setting the best example in work and life, Mom, Dad John, Kevin and Loran. Lastly, I would like to thank my beautiful girlfriend Sophie Spratley for standing by me during the past three years during the struggles and the successes and for being a great source of joy in my life allowing me to put forth my best effort everyday.
7 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ .. 4 LIST OF TABLES ................................ ................................ ................................ .......... 10 LIST OF FIGURES ................................ ................................ ................................ ........ 11 LIST OF ABBREVIATIONS ................................ ................................ ........................... 15 ABSTRACT ................................ ................................ ................................ ................... 17 CHAPTER 1 INTRODUCTION ................................ ................................ ................................ .... 20 Organic Light Emitting Diode ( OLED ) Display Market ................................ ............ 20 Active M atrix OLED Backplane Problem ................................ ................................ 21 Potential Thin Film Transistor ( TFT ) Solutions ................................ ........................ 22 Amorphous Silicon TFTs with Threshold Voltage Shift Compensation ............. 22 Polycrystalline Silicon (Poly Si) Uniformity Improvement Effort ........................ 25 Poly Si crystallization methods ................................ ................................ .. 26 Poly Si uniformity compensation circuitry ................................ .................. 29 Transparent Oxide TFTs ................................ ................................ .................. 30 Alternative Transistor Architectures ................................ ................................ .. 31 Carbon Nanotubes, Organic Semiconductors and Opportunity .............................. 33 2 EXPERIMENTAL METHODS ................................ ................................ ................. 37 Dual Glovebox Vacuum Thermal Evaporation System ................................ ........... 37 Vacuum Thermal Evaporators of Metals and Organics ................................ .... 39 Vacuum thermal evaporation of thin films ................................ .................. 41 Metals evaporation chamber ................................ ................................ ...... 43 Organics evap oration chamber ................................ ................................ .. 44 Features Included in Both Metals and Organic Evaporation Chambers ........... 46 Adjustable source to sample distance ................................ ........................ 47 Periscope aided source viewing ................................ ................................ 47 Turbo pump block plate ................................ ................................ ............. 48 Spin Coater ................................ ................................ ................................ ...... 50 Current Voltage Luminance Measurements ................................ ........................... 52 Ambient Probestation ................................ ................................ ....................... 52 Glovebox Probestation ................................ ................................ ..................... 53 Luminance Measurements ................................ ................................ ............... 54 Capacitance Measurements ................................ ................................ ................... 56 X ray Diffraction Measurements ................................ ................................ ............. 57
8 Atomic Force Microscopy Measurements ................................ ............................... 57 Ultraviolet Visible Near Infrared Transmission Measurements ............................... 57 3 FIRST DEMONSTRATION OF CARBON NANOTUBE ENABLED VERTICAL FIELD EFFECT (CN VFET) AND LIGHT EMITTING TRANSISTORS ................... 60 Introductory Remarks ................................ ................................ .............................. 60 Carbon Nanotube Enabled Vertical Field Effect Transistor ................................ ..... 62 Experimental Detail s ................................ ................................ ........................ 62 Results and Discussions ................................ ................................ .................. 64 Carbon Nanotube Enabled Vertical Organic Light Emitting Transistor ................... 71 Experimental Details ................................ ................................ ........................ 71 Results and Discussions ................................ ................................ .................. 72 Concluding Remarks ................................ ................................ ............................... 73 4 OPTIMIZATION OF PENTACENE BASED CARBON NANOTUBE ENABLED VERTICAL FIELD EFFECT TRANSISTORS ................................ .......................... 75 Introductory Remarks ................................ ................................ .............................. 75 Experimental Details ................................ ................................ ............................... 77 Results and Discussions ................................ ................................ ......................... 78 Concluding Remarks ................................ ................................ ............................... 85 5 HIGH CURRENT, LOW VOLTAGE CARBON NANOTUBE ENABLED VERTICAL ORGANIC FIELD EFFECT TRANSISTORS ................................ ........ 86 Introductory Remarks ................................ ................................ .............................. 86 Experimental Details ................................ ................................ ............................... 90 Fabrication of the Dinaphtho Thienothiophene (DNTT) Based CN VFET ........ 90 Optical Microphotographs of the CN VFET Devices ................................ ........ 91 Metal Insulator Metal Capacitors for Al 2 O 3 Dielectric Evaluation ...................... 93 Resu lts and Discussions ................................ ................................ ......................... 93 Concluding Remarks ................................ ................................ ............................... 98 6 REORIENTATION OF THE HIGH MOBILITY PLANE IN PENTACENE BASED CARBON NANOTUBE ENABL ED VERTICAL FIELD EFFECT TRANSISTORS 101 Introductory Remarks ................................ ................................ ............................ 101 Experimental Details ................................ ................................ ............................. 103 CN VFET Samples ................................ ................................ ......................... 103 X ray Diffraction Samples and Sandwich Type Hole Only Devices ................ 104 Metal Insulator Metal Capacitors ................................ ................................ .... 106 Results and Discussions ................................ ................................ ....................... 107 Concluding Remarks ................................ ................................ ............................. 121 7 CONCLUSIONS ................................ ................................ ................................ ... 122
9 APPENDIX A DE DOPING CARBON NANOTUBES (CNTs) THROUGH BAKING .................... 125 B COMPOSITION OF CNT NETWORKS UNDER STUDY ................................ ...... 127 C EFFECT OF BAKING THE CNT SOURCE ELECTRODE ON THE DNTT BASED CN VFET ................................ ................................ ................................ 130 D EFFECTIVE CURRENT DENSITY CALCULATION FOR LATERAL CHANNEL THIN FILM TRANSISTORS ................................ ................................ .................. 132 LIST OF REFERENCES ................................ ................................ ............................. 134 BIOGRAPHICAL SKETCH ................................ ................................ .......................... 146
10 LIST OF TABLES Table page 5 1 Statistics for the 20 devices measured for uniformity in Figures 5 5A and 5 5B. ................................ ................................ ................................ ...................... 98 5 2 Compari son of the CN VFET to the highest performance, low patterning resolution devices reported. ................................ ................................ ............. 100
11 LIST OF FIGURES Figure page 1 1 Pixel level circuit diagram of an LCD and an AMOLED dis play ......................... 23 2 1 CAD rendering of the dual glovebox vacuum thermal evaporation system. ....... 39 2 2 Ima ge of the dual glovebox vacuum thermal evaporation system. ..................... 40 2 3 Image of the dual evaporation glovebox system from the back .......................... 41 2 4 Schematic depiction of the components of a vacuum thermal evaporation chamber. ................................ ................................ ................................ ............ 43 2 5 Image of the source layout in the metals evaporation chamber. ........................ 44 2 6 Image of the source layout in the organics chamber. ................................ ......... 45 2 7 Schematic of the effusion cells. .. ................................ ................................ ........ 46 2 8 CAD drawing of the substrate holder and interchangeable extension shafts for varying the source to substrate distance. ................................ ...................... 48 2 9 Images of the periscope in the metals chamber from the backsi de of the glovebox. ................................ ................................ ................................ ............ 49 2 10 Images showing the periscope and turbo pump evaporant block plate in the metals evaporation chamber and the organics evaporation chamber. ............... 50 2 11 Image of the spin used in the glovebox. Image of the spin coater used outside the glovebox. ................................ ................................ .......................... 51 2 12 Image of the current voltage measurement syste m. ................................ ........... 53 2 13 Glovebox probestation. ................................ ................................ ....................... 54 2 14 The clamping mechanism for making luminance measurements on bottom emission CN VOLETs. ................................ ................................ ...................... 56 2 15 Image of the Phillips A PD 3720 ................................ ................................ .......... 58 2 16 Image of the Digital Instruments Multi Mode AFM. ................................ ............. 58 2 17 Image of the Perkin Elmer Lambda 900 UV/VIS/NIR dual beam spectrometer. ................................ ................................ ................................ ...... 59 3 1 Schematics of a TFT, a VFET with a generalized porous source electrode depicted by a grid and the CN VFET. ................................ ................................ 62
12 3 2 Device schematic of the CN V FET. ................................ ................................ .... 64 3 3 Flat band diagram of the materials used in th e VFET and the organic molecules used as the semiconductor layer in the VFET, PF 9HK and NPD. .... 65 3 4 Transistor J V characteristics of the hole only VFETs. Source drain current as a function o f gate voltage for both material systems. ................................ ..... 66 3 5 Valence band energy level simulation vs. horizontal position x from CNT cross section center. ................................ ................................ ........................... 68 3 6 Diagrams depicting paths of current flow between the bundled nanotube source and the drain electrode in the CN VFET. ................................ ................ 70 3 7 CN VOLET layout. Scale in inches. ................................ ................................ .... 71 3 8 VOLET device with Alq3 as the emitting layer and PF 9HK inserted between the NPD layer and the CNT network. ................................ ................................ 72 3 9 Current density an d luminance vs. voltage plots for the PF 9HK modified CN VOLET device.. ................................ ................................ ................................ .. 74 4 1 Transfer curves of bare oxide CN VFETs with and without a CNT bake prior to deposition of the pentacene semicondu ctor layer. ................................ .......... 79 4 2 Comparison of transfer curves of CN VFETs with and without a BCB dielectric surface layer, both with CNT bake prior to deposition of pentacene. .. 80 4 3 Diagrams depicting charge storage on the dielectric under different ga te voltage polarities an d resulting hysteresis curve ................................ ............... 81 4 4 BCB baked and bare oxide baked CN VFETs operated under reduced gate voltage scan ranges. ................................ ................................ .......................... 84 5 1 Schematic of the CN VFET. ................................ ................................ ............... 89 5 2 Labeled full view numerous distinct DNTT CN VFETs, defined by each hexagonal drain electrode.. ................................ ................................ ................................ ........... 92 5 3 The MIM schematics for the bare Al 2 O 3 device and the Al 2 O 3 +BCB device. ...... 94 5 4 Transfer curves of the CN VFET at the indicated drain voltages. The curves show little hysteresis over the small gate voltage range of 4 V. .......................... 96 5 5 Uniformity and stability of the devices. Transfer curves of 20 devices 10 on CNT 1 and 10 on CNT 2 source electrodes.. ................................ ...................... 97
13 6 1 Schematic of the CN VFE T with arrows depicting the direction holes flow in the on state of the device. ................................ ................................ ................ 102 6 2 Optical microphotograph of the Al/pentacene/Al capacitors. A gold coated needle is used to make contact to the bottom Al electrode.. ............................ 106 6 3 Transfer curve of the CN VFET with pentacene as the semiconductor layer shows a small amount of hysteresis over a gate voltage range of 60V, with a SS slop e of 3.3V/dec.. ................................ ................................ ...................... 108 6 4 The crystal structure of pentacene. The a b plane orients itself parallel to the oxide surface. ................................ ................................ ................................ ... 109 6 5 X ray diffraction data taken in labeled next to each curve. ................................ ................................ ............... 111 6 6 AFM micrographs of a dilute CNT network on BCB/glass, pentacene on BCB/glass, p entacene on a dilute CNT network on BCB and pentacene on 45 nm thick CNT film on glass. ................................ ................................ ......... 113 6 7 Scale model depicting the mixed orientation crystallites on the CNT bundle and partially covered BCB surface. ................................ ................................ .. 115 6 8 X ray diffraction data taken in labeled next to each curve.. ................................ ................................ .............. 117 6 9 Schematics of the pentacene M*SM hole only devices fabricated for measurement of SCL ................................ ................................ ....................... 118 6 10 Capacitance vs area for each of the thicknesses of the pentacene layer used in Al/pentacene/Al MIM devices.. ................................ ................................ ...... 120 A 1 Schematics showing the ex pected position of the nanotube Fermi level. ......... 126 B 1 and a 50 nm thick CNT film. ................................ ................................ ........... 128 B 2 Histogram of the bundle diameter distribution of the 2 nm thick dilute CNT network from Figure B 1A. ................................ ................................ ................ 129 B 3 Scale model of a bundle of (10,10) nanotubes drawn in AutoCAD with a 5 nm diameter reference circle (dashed line). ................................ ........................... 129 C 1 Transfer curves of CN VFETs that had a baked nanotube source electrode (prior to DNTT deposition) compared to an unbake d nanotube source electrode device. ................................ ................................ .............................. 131
14 D 1 Interdigitated source drain electrode configuration used to calculate the figure of merit J Eff to compare current outputs of TFTs and VFETs .................. 133
15 LIST OF ABBREVIATION S a Si amorphous silicon AFM Atomic force microscopy or atomic force microscope ALD Atomic layer deposition Alq 3 Tris (8 hydroxyquinoline) aluminum AMOLED Active matrix organic light emitting diode ATO Alum inum titanium oxide BCB B enzocyclobutene CNT Single walled carbon nanotube CN VFET Carbon nanotube enabled vertical field effect transistor CN VOLET Carbon nanotube enabled vertical organic light emitting transistor DC Direct current DNTT D inaphtho [2,3 b: 2 ,3 f ]thieno[3,2 b]thiophene FET Field effect transistor FPD Flat panel display HOMO Highest occupied molecular orbital IGZO amorphous In Ga Zn O ITO Tin doped indium oxide LCD Liquid crystal display LUMO Lowest unoccupied molecular orbital MCE Mixed cel lulose ester MFPL Mean free path length NPD di(1 naphthyl) diphenyl diphenyl diamine) OLED Organic light emitting diode PF 9HK Poly[(9,9 dioctyl fluorenyl 2,7 diyl) alt co (9 hexyl 3,6 carbazole)]
16 Poly Si Polycrystalline silicon P3HT Po ly(3 hexylthiophene) rpm rotations per minute SAM Self assembled monolayer TFT Thin film transistor VFET Vertical field effect transistor VOLET Vertical organic light emitting transistor XRD X ray diffraction
17 Abstract of Dissertation Presented to the Gr aduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy DEMONSTRATION OF HIGH CURRENT CARBON NANOTUBE ENABLED VERTICAL ORGANIC FIELD EFFECT TRANSISTORS AT INDUSTRIALLY RE LEVANT VOLTAGES By Mitchell McCarthy December 2010 Chair: Franky So Major: Materials Science and Engineering The display market is presently dominated by the active matrix liquid crystal display (LCD). However, the active matrix organic light emittin g diode (AMOLED) display is argued to become the successor to the LCD, and is already beginning its way into the market, mainly in small size displays. But, for AMOLED technology to become comparable in market share to LCD, larger size displays must become available at a competitive price with their LCD counterparts. A major issue preventing low cost large AMOLED displays is the thin film transistor (TFT) technology. Unlike the voltage driven LCD, the OLEDs in the AMOLED display are current driven. Because of this, the mature amorphous silicon TFT backplane technology used in the LCD must be upgraded to a material possessing a higher mobility. Polycrystalline silicon and transparent oxide TFT technologies are being considered to fill this need. But these tec hnologies bring with them significant manufacturing complexity and cost concerns. Carbon nanotube enabled vertical organic field effect transistors (CN VFETs) offer a unique solution to this problem (now known as the AMOLED backplane problem). The CN VFET allows the use of organic semiconductors to be used for the
18 semiconductor layer. Organics are known for their low cost large area processing compatibility. Although the mobility of the best organics is only comparable to that of amorphous silicon, the CN VFET makes up for this by orienting the channel vertically, as opposed to horizontally (like in conventional TFTs). This allows the CN VFET to achieve sub micron channel lengths without expensive high resolution patterning. Additionally, because the CN VFE T can be easily converted into a light emitting transistor (called the carbon nanotube enabled vertical organic light emitting transistor CN VOLET) by essentially stacking an OLED on top of the CN VFET, more potential benefits can be realized. These potent ial benefits include, increased aperture ratio, increased OLED lifetime and the potential for an all transparent display. And because carbon nanotubes (CNTs) and organics are used, CN VFET and CN VOLET devices are compatible with flexible displays. This d issertation describes the first ever demonstration of CN VFETs and CN VOLETs and relates their performance to the specific properties of the CNTs and the new device architecture. In the work that followed, the CN VFET was systematically optimized overcomin g the problems revealed in the demonstration devices. The large undesired hysteresis was decreased by 96%, the on/off ratio was improved three orders of magnitude and the operating voltages were reduced to state of the art values. Additionally, the current output per device area of the CN VFET was demonstrated to be greater than any other low resolution patterned organic transistor by a factor of 3.9. Moreover, it was demonstrated that the CNTs induce a reorientation of the high mobility plane in small mole cule organics like pentacene to coincide with the vertical direction, giving additional explanation for the large currents observed in the CN VFET. The ability
19 to drive high currents and potentially inexpensive fabrication may provide the solution for the AMOLED backplane problem.
20 CHAPTER 1 INTRODUCTION This chapter introduces an important area of recent development in organic electronics organic light emitting diode (OLED) based displays. This chapter provides the context for the applied aspects of the work presented in this dissertation. The purpose of this chapter is to inform the reader of 1) the size of the display market and the enormous opportunity for OLEDs, 2) a major problem faced by industry in making OLED displays cost competitive, 3) the curr ent state of the intended solutions to this problem and 4) how the research presented in this dissertation can provide a compelling solution to the problem faced by industry. OLED Display Market Research in organic electronic and optoelectronic devices has exploded in recent years due to the wide range of potential applications and promise for reduced cost and increased functionality. A major industrial driver of organic electronics is the display market. In 2008 the display market surpassed $100 billion [1 ]. Active matrix liquid crystal displays (LCDs) are the dominant display type. Organic light emitting diode (OLED) displays are the expected successor to LCDs. OLED displays come in two flavors, passive matrix OLED (PMOLED) and active matrix OLED (AMOLED). PMOLED displays have been in the market since 2000 in consumer electronics with small mono color and full color displays, such as car radios, and as secondary screens in cell phones and digital assistants. The market penetration of OLED displays has been growing since 2000, and in 2006 OLED based displays accounted for 6% of the display market . PMOLED displays are only useful in small low pixel count screens and are inferior to AMOLED displays. AMOLED displays consume less power and last longer
21 than PM OLED displays and are compatible with high pixel count small displays and large displays such as televisions. In 2009 cell phones with AMOLED main screens shipped 22 million units and this number is expected to jump to 178 million in 2015 . AMOLED displ ays are attractive over LCDs because they have a wider viewing angle, are brighter, have faster response times and consume less energy. Currently AMOLED cell phone displays cost somewhat more than LCDs of comparable size, but not so much to prevent them fr om beginning to enter the market. AMOLED Backplane Problem The display industry is working hard to produce larger size AMOLED displays for use in devices such as laptop screens and flat panel display (FPD) televisions. However, a key issue preventing wide spread transition from LCDs to AMOLED displays is the need for a new TFT technology. Unlike the TFTs in LCDs which are used as voltage switches where the low mobility of a Si poses no problem, the TFTs in AMOLED backplanes must source the current required to power the self illuminating OLEDs. Because of this larger current requirement, AMOLEDs require a TFT semiconductor with higher carrier mobility than a Si. The next logical choice is polycrystalline silicon (poly Si), which has an electron mobility rangi ng from 50 to 200 cm 2 V 1 s 1 [4 6]. This is significantly larger than the electron mobility of a Si, which is in the range of 0.1 to 1.0 cm 2 V 1 s 1 [7, 8]. Poly Si however has poor TFT parameter uniformity. High uniformity is a major reason behind the usage of a Si in LCDs. Currently the display industry is devoting great effort to finding a suitable TFT technology to enable large AMOLED screens to reach the consumer market . The solutions available to industry to date, however, significantly increase the complexity of the manufacturing process, further increasing the cost, thus delaying the entry of large AMOLED displays into the market
22 . The lack of a cost effective solution to this problem has become known as the AMOLED backplane problem . Curren tly, great opportunity exists for new technologies to provide the solutions required to allow large AMOLED displays to enter the market at an affordable price. Potential TFT Solutions Industry and the academic research community are in hot pursuit of viabl e solutions to the AMOLED backplane problem. Three major TFT technologies are being pursued as well as a fourth area consisting of alternative architectures to TFTs. 1) a Si TFTs are still being considered with current research focusing on threshold voltag e shift compensation. 2) Poly Si TFTs are being considered for their high mobility with the effort focusing on uniformity improvement. 3) Transparent oxide TFTs are being explored for their higher than a Si mobility and the added benefit of transparency. 4 ) Alternative device architectures bring in the possibility of using the well known large area compatible low cost group of materials organic semiconductors. Because the mobility of organics is no better than a Si, architectural modifications to the tradit ional TFT design are being explored to cost effectively increase the current output as opposed to increasing the mobility of the semiconductor. Amorphous Silicon TFTs with Threshold Voltage Shift Compensation Due to the well known uniformity of a Si on la rge area substrates, some research groups are pursuing it as a potential solution for large displays despite its low mobility [11 16]. Moreover, a Si has a large manufacturing infrastructure and knowledgebase and can be produced at low cost [11, 12]. The p rimary issue in attempts to use a Si TFTs in current driven AMOLED displays is the threshold voltage stability [13, 15]. The limited temporal stability of a Si TFTs under bias stress is well known and was a
23 concern early on for LCDs [17, 18]. However, the solutions for improving the stability of a Si TFTs in LCDs cannot be implemented in AMOLED displays. This is due to the intrinsic differences between AMOLED displays and LCDs. These differences can be visualized in the single pixel circuit diagrams of an L CD (Figure 1 1A) and the most basic AMOLED display (Figure 1 1B). AMOLED displays have an additional transistor, Figure 1 1. Pixel level circuit diagram of an A) LCD and B) an AMOLED display. A B
24 the driving transistor, which provides and controls the curren t to the OLED to produce and modulate the light output. The address transistor (also referred to as the switching transistor) is common to both display types and is addressed every refresh cycle by the scan line connected to its gate allowing the data line to update the gate of the driving transistor with the appropriate voltage level to set the luminance of the OLED. While the threshold voltage shift of the switching transistor can be mitigated (in both display types, more below), that of the driving trans istor cannot. A simple solution to the threshold voltage shift problem inherent in a Si TFTs was implemented in LCDs that required no added complexity in manufacturing or compromises in performance. The nature of the threshold voltage shift in a Si TFTs i s such that the direction of its shift is opposite under positive and negative gate bias. This suggests that the threshold voltage drift can be cancelled out by spending the appropriate time at the opposite gate voltage polarity to undo any previous shifts from earlier gate biasing. As it turns out, the threshold voltage shift is more pronounced when the TFT is under accumulation. Therefore, to counteract the shift, the TFT must spend more time under depletion than accumulation. Serendipitously, this is alr eady the case in the addressing scheme where the duty cycle ( D ) of the pulsed addressing of the TFT gates is typically significantly less than 1%. Duty cycle can be defined as where t A = time under accumulation and t D = time under d epletion. With careful modeling and selection of the gate voltages chosen for the on and off states and the duty cycle, the threshold voltage shift in the a Si TFTs of LCDs can be designed to be insignificant for as long as 10 years .
25 This solution, w hile simple and effective for LCDs does not apply to AMOLED displays. The driving TFT in AMOLED displays is nearly under DC (direct current) operation the entire time the AMOLED display is on. The purpose of the driving TFT is to provide the current needed by the OLED to produce light. Under near constant gate biasing in accumulation, the driving transistor threshold voltage would shift uncompensated out of range in only a few days [15, 19]. Solutions to the threshold voltage shift include current source [ 13] and voltage controlled [14 16] methods and a method that also compensates for the turn on voltage shift of the OLED . None of these methods however can compare to the stability seen in LCDs. The longest stability reported was 10,000 hours (1.1 year s)  and others had stability measurements to 3 hours , 16 hours  and 600 hrs  of operation but with no estimation of the total stability. All of these methods require adding between 1 and 4 TFTs to each pixel as well as adding metal address ing lines. All of these modifications add to the manufacturing complexity, increase power consumption, reduce the aperture ratio and increase the cost of the display. Furthermore, the power consumption is already higher because of the low mobility of a Si compared to other higher mobility semiconductors such as poly Si. And the aperture ratio is already lower without the additional compensation circuitry due to the larger footprint required of lower mobility TFTs. For these reasons, a Si TFTs with threshold voltage compensation circuitry leave much to be desired and are unlikely to make AMOLED displays cost competitive with LCDs. Polycrystalline Silicon Uniformity Improvement Effort A natural TFT material choice to provide the currents required by AMOLED dis plays is poly Si. The mobility of poly Si is ~200 times that of a Si. Poly Si TFTs are
26 more stable than those with a Si [15, 20, 21] and development of poly Si TFTs for other purposes such as system on panel i circuitry has been increasing recently [6, 22]. Poly active matrix array made from poly Si TFTs is a substantial problem. Significant research effort has been devoted to improving the uniformity by various crystallization methods [4 6, 22 26] as well as compensating for the non uniformity with modified active matrix circuitry and/or driving schemes [20, 21, 27 33]. Poly Si crystallization methods Numerous crystallization methods have been investigated in an attempt, throug h process optimization, to attain a uniform and controllable poly Si grain structure that yields the highest possible TFT parameter uniformity. A first requirement for the application of FPDs is that the process occurs at low temperature allowing the usage of low cost glass substrates . Low temperature refers to the maximum process temperature used during the crystallization process and is defined as being below 600 C. Temperatures below 600 C are needed for the process to be compatible with glass subst rates [4, 24, 26]. The various methods used can be split into two main categories: laser and non laser crystallization techniques. Excimer laser crystallization is a widely utilized technique but is known to have drawbacks such as higher initial cost and p rocess complexity as well as leads to rougher surfaces and narrower process windows [23, 24]. Alternative methods include solid phase crystallization, such as metal induced lateral crystallization (MILC) [25, 35], i System on panel refers to including the external driver circuitry required by either LCDs or AMOLEDs directly onto the panel substrate. This approach is bei ng pursued with the hope that it will increase the performance and ruggedness and reduce the cost of manufacture of active matrix displays.
27 metal induced unilateral crystallization ( MIUC) [4, 24], field aided lateral crystallization (FALC)  and combinations of laser and non laser techniques such as metal induced lateral continuous wave laser crystallization (MILCLC) . MILC is a technique that avoids some of the drawbacks of l aser based crystallization processes. MILC attains crystallization at temperatures under 600 C with the help of a metal thin film pre deposited on the uncrystallized a Si film over the source/drain regions. Typically Nickel is used as the metal. The metal facilitates nucleation of crystallites which then grow laterally across the channel during the typically 10 hour long annealing period at temperatures around 500 C. The metal film is purposely not deposited over the channel region of the TFT to avoid conta mination. After annealing the metal film is removed in acid. This growth method, by nature, grows Si grains oriented with their longer direction oriented preferentially along the length of the channel enhancing the mobility compared to early solid phase cr ystallization methods. But because the grains are also larger, in an early study the TFT parameter MILC process attained a field effect mobility standard deviation of 9 % . The MILC process however is blamed for high off currents and early drain breakdown due to the presence of the boundaries near the center of the channel where grains which originated from either side of the channel come together . MIUC is a pr ocess that solves this problem. In MIUC, crystallization starts from only one side of the channel preventing defects from forming in the channel at the boundaries where oppositely growing grains meet. It is reported that a MIUC process
28 attained a field eff ect mobility standard deviation of 12 % , inferior to that of the recent MILC results of 9 %. FALC is similar to MILC but has the modification of using an electrical current to assist in the crystallization of the poly Si. This is beneficial in that it reduces the annealing time for crystallization down from the 10 hours required in MILC, to 4 hours. While this would increase manufacturing through put thereby potentially reducing costs, it has the added complexity of more process steps to deposit electr odes for applying the current which then have to be removed after crystallization. Additionally, careful optimization and consideration to ensure all transistors in the array get equal current is required, which is not trivial. It is reported that a FALC p rocess attained a field effect mobility standard deviation of 10 % . MILCLC is MILC with the addition of a laser annealing step. It is reported that the laser annealing step causes the elongated MILC poly Si grains to coalesce with each other yielding grains more equiaxed in nature leading to improved TFT parameter uniformity. After measuring TFT characteristics on 10 devices, the field effect mobility uniformity standard deviation was measured to be 3 % . While these numbers are significantly bette r than those from the MILC, MIUC or FALC methods, the comparison is not a fair one. Measuring uniformity on only 10 devices over a small substrate size is not the same as attaining the same uniformity numbers across a full size array with tens of thousands or millions of transistors where many more factors come into play to affect the uniformity. Factors such as temperature uniformity and stability during the long 12 hour annealing period, temporal stability of the laser intensity and precise movement contr ol of the laser as it spends a specified amount of time at each TFT, film thickness
29 uniformity, source drain doping level control, etc. Significantly more effort would be required before these factors could be addressed. And significantly more process comp lexity, manufacturing time and cost would be guaranteed if this method were to be enacted. The poly Si uniformity issue is a severe one with numerous complicated Poly Si uniformity compen sation circuitry With poly Si crystallization schemes insufficient to achieve the required uniformity of AMOLED display backplanes, additional measures must be used to improve the uniformity. Similar to a Si, multiple compensation methods exist. Compensati on methods include, pixel level circuitry, in the form of more TFTs and capacitors per pixel controlled by either voltage programming [21, 28, 32, 33] or current programming methods  and more complicated variants , digital pixel driving as opposed to analog , and video data correction . A known issue with the voltage programming method is that it does not improve the uniformity enough for commercial applications . While there is improvement from the non compensated AMOLED array, there ar e still significant uniformity problems in the compensated AMOLED array. The compensated AMOLED array attains an OLED current deviation of 5% . The reason voltage programmed circuitry based compensation methods are not sufficient for commercial use is due to the fact that the additional transistors used in the compensation circuitry have uniformity problems themselves preventing the required level of uniformity from being attained . Current programming methods do a better job but suffer from prolong ed charging times at low grey shade levels . A significantly more complicated circuitry compensation method is the current sensing and voltage feedback driving method that yields OLED current deviations as low as 1.7%.
30 Current deviations as low as this are sufficient for commercial products, but the degree of complexity is very high, making cost a major concern. Digital driving schemes and video data correction have similar cost concerns due to the additional cost of more complicated driver circuitry [3 0]. Additionally, in digital driving schemes multiple subframes are required along with large memories in the driver circuitry [29, 32]. Transparent Oxide TFTs Transparent oxide TFTs are at an earlier stage of implementation in active matrix optoelectronic devices than a Si and poly Si TFTs. Transparent oxide semiconductors posses an order of magnitude higher mobility than a Si [37 39] making them attractive for providing the required OLED current in AMOLED display backplanes more power efficiently than a S i and with a smaller footprint allowing a larger aperture ratio. Transparent oxide semiconductors also provide the possibility of further increasing the aperture ratio because of their transparency to visible light as well as the possibility of completely transparent displays. The two most promising candidates being pursued by industry and academia are amorphous In Ga Zn O (IGZO) [37, 38, 40 44] and amorphous ZnO [39, 45 52]. However these materials suffer from the issue of threshold voltage stability simil ar to that of a Si [19, 38, 50] which means compensation circuitry is required. Because of the transparency of these semiconductors however, the addition of more transistors per pixel would not impact the aperture ratio as adversely with a Si or poly Si. H owever, additional circuitry of any kind results in yield losses. Another area of concern for IGZO and ZnO is their photosensitivity [39, 41, 43, 48, 53]. IGZO has a band gap of 3.05 eV [41, 44] but is sensitive to light at and above ~2.75 eV (blue light) photon energy. This has to do with how the bandgap is defined (by the Tauc method). Even though the band gap is defined to be 3.05 eV, the log scale
31 absorption spectrum of IGZO shows an absorption onset at ~ 450 nm (2.75 eV)  explaining its light sens itivity in the blue region. In the case of ZnO, its band gap is ~ 3.3 eV [50, 54] but it is sensitive to lower energy light than IGZO; green light at ~ 540 nm (2.3 eV). This lower energy sensitivity is attributed to sub band gap energy transitions to mid g ap states in the ZnO semiconductor film and/or to the gate dielectric/ZnO interface [48, 53]. The possibilities with transparent oxide TFT backplanes in AMOLED displays are exciting. However, as discussed, there are still significant issues to contend with before viable commercial products can implement this transistor technology. Alternative Transistor Architectures Organic semiconductors are known for their large area, low temperature and low cost processing compatibility. And for these reasons they come to mind as potential materials for use in AMOLED display backplane circuitry. However, their mobility is low. When processed by cost effective methods (methods of deposition resulting in the polycrystalline thin film phase) the mobility of organic semicond uctors is no better than a Si. In light of this, there are a few research groups that seek to deliver the larger currents required by OLEDs not by increasing the mobility, but by modifying the architecture of the transistor. The aim is to make the channel of the transistor sufficiently short to deliver the required currents at low power without significantly impacting the cost. Within the traditional architecture of the TFT, where the channel is oriented horizontally, the only way of making the channel shor ter is by patterning the source and drain electrodes closer together. However, to make the channel sufficiently shorter, i.e. to take the channel length from tens of microns to hundreds of nanometers would not be cost effective. This would require high res olution patterning, similar to that used in Si
32 wafer fabs, which would require extraordinary costs; removing the cost focused motivation for using organics in the first place. In 2004 Yang and coworkers demonstrated a new transistor architecture that they suggested could circumvent the mobility limitations of present organic semiconductors . This architecture stacks the source and drain electrodes sandwiching the organic semiconductor in between, orienting the channel vertically, allowing sub micron cha nnel lengths to be realized at no added cost. The channel length is simply the thickness of the semiconductor thin film. This device is referred to as a vertical field effect transistor (VFET). However, this VFET relied on a carefully controlled ultrathin (< 20 nm) aluminum source electrode that required partial oxidation and an ultra high gate capacitance to switch the device on and off. For the ultra high capacitance they used an electrolyte based supercapacitor dielectric LiF that relied on humidity from the ambient air to enable the dielectric constant enhancing effects of mobile ions. While ionic based supercapacitors are known to be effective at yielding high capacitance, a significant limitation is their frequency response. Ionic relaxation is known t o be a slow process, typically losing a major fraction of the capacitance after only 1 kHz . While the optimized device exhibited ~6 orders of magnitude current modulation, the low work function aluminum source electrode required an n type semiconducto r channel restricting that device to the use of C60 as the channel material. Recently, the use of the more conventional organic semiconductor pentacene was demonstrated. This device did indeed demonstrate proof of principle with p type semiconductors, but because the rest of the device was the same as their first device, aside from addition of
33 a 7 nm vanadium oxide layer between the source and semiconductor layer, it still suffered from the drawbacks mentioned . Most recently Yang and coworkers found t hat this architecture affords important new opportunities in how OLEDs are electronically driven . By stacking their VFET with an OLED they created what is called a vertical organic light emitting transistor (VOLET). This device demonstrated proof of p rinciple of the VOLET design. The device was reported to have an on/off ratio of ~10 2 and the luminance efficiency was not reported , most likely due to lifetime issues and questionable reliability in device performance. Additionally their VOLET suffe rs from the same manufacturability, lifetime and speed issues as the VFET mentioned in the previous paragraph. Another device, similar in design to the VOLET is one that has a patterned gold source electrode in place of the partially oxidized aluminum VOLE T source. The patterned source consists of parallel gold electrodes 100 m wide on a 200 m pitch on the surface of a gate dielectric with underlying gate electrode. This device is referred to as a metal insulator semiconductor organic light emitting transistor (MIS OLET). While this device does not require a supercapacitor no r a hard to manufacture source electrode, it requires a larger operating voltage than the VOLET and has a severely obstructed aperture ratio of at most 50% due to the equal line space layout of the source electrode [59, 60]. Carbon Nanotubes, Organic Semic onductors and Opportunity functional device layer that is, i) porous to an electric field, and ii) just above percolation, reliably, on an industrial scale is unlikely. However, a material that is porous yet percolating by nature is the single walled carbon nanotube (CNT) network. And the level
34 of porosity and percolation can be simply controlled by the number density of CNTs on the surface, making for easy manufacturability. Dilut e CNT networks are highly conductive and transparent ( 5 kohm/square sheet resistance > 98 % transmi ttance in the visible Appendix A ) and are used as the enabling layer for the devices discussed in this dissertation. The first report of a carbon nanotube enabled vertical field effect transistor (CN VFET) and related nanotube enabled vertical organic light emitting transistor (CN VOLET) came out of our group in 2008 . The CN VFET operated at 2 orders of magnitude lower gate capacitance than Yang's elim inating the requirement of the super capacitor dielectric thus freeing our devices from the crippling issues that go along with such a dielectric (mentioned above). The nanotubes possess a number of physical properties that combine in a unique manner to pe rmit such benefit, some of which were recognized in our publication at the time and some of which have only been learned since then. The relevant properties of the nanotubes are listed below followed by a short overview of the benefits realized from these features. CNTs: are quasi 1 dimensional, have a high mobility, have a low density of electronics states, have a passivated surface, and have a pi conjugated surface. The CN VFET functions as a schottky barrier transistor where the majority of the current g ating effects occur in the interfacial region between the CNT source electrode
35 and the organic semiconductor layer. This interface confined gating is why the channel can be oriented in the vertical direction allowing the short channel lengths permitting th e large currents needed by OLEDs in AMOLED displays. On the contrary, in carrier density modulated TFTs, the channel must be perpendicular to the gate so the gate can create a depleted region sufficiently wide to turn the current off. Without the interface confined gating in the CN VFET and CN VOLET, the vertical channel would not be possible as screening effects would not allow the gate sufficient access throughout the majority of the channel to modulate the current sufficiently. Because the CNTs are quasi 1 demensional, when they are deposited as a dilute network, there is a high surface density of interfaces along the CNT sidewalls between the CNTs and organic semiconductor with direct access to the gating electric field. This allows for very effective fi eld gating through modulation of the schottky barrier between the CNTs and organic. Because CNTs have a high mobility, their conductivity is high despite having a low density of electronic states and being deposited in low density. Because CNTs have a low density of electronic states, their Fermi level is readily modulated by the gate, making them ideal for use in schottky barrier transistors. Because CNTs have a passivated surface, they do not form covalent bonds with materials they come into contact with, freeing them from forming metal induced gap states, further making them ideal candidates for use in schottky barrier transistors. Lastly, because CNTs have a pi conjugated surface, they interact in a preferred manner with pi conjugated organic molecules, that when deposited on top of CNTs, nucleate polycrystalline grains of the organic material with the high mobility direction oriented vertically.
36 These phenomena are expanded upon with supporting theoretical and experimental evidence in the following chap ters of this dissertation, which are laid out as follows. Chapter 2 presents the experimental methods and equipment fabricated and used for the experiments. Chapter 3 presents first demonstration of CN VFET and CN VOLET devices in a proof of principle mann er. Chapter 4 presents some important modifications to the original CN VFET that significantly reduced the undesirable hysteresis, increased the on/off ratio and expanded the range of useable organic semiconductors in the CN VFET. Chapter 5 demonstrates a state of the art implementation of the CN VFET with a high mobility organic semiconductor layer on a high capacitance gate dielectric stack yielding record current densities at low gate and drain voltages. Chapter 6 explains an important cause of the high currents realized in Chapter 5 and attributes it to a reorientation of the high mobility plane of the polycrystalline organic semiconductor deposited on the CNT source electrode. And finally, Chapter 7 summarizes the research presented, concluding the diss ertation.
37 C HAPTER 2 EXPERIMENTAL METHODS This chapter discusses the various pieces of equipment and methods used in the fabrication and measurement of carbon nanotube enabled vertical organic field effect transistors (CN VFETs) and carbon nanotube enable d vertical organic light emitting transistors (CN VOLETs). Fabrication and testing of these devices occurred, for the most part, in a double glovebox containing integrated (separate) metals and organics evaporation chamber systems where the organic layers of interest could be deposited in an inert environment free of oxygen and water and where post processing and device measurement could be performed in the same inert environment. This elaborate glovebox and the associated systems were designed and built sp ecifically for these studies. Described below are the considerations in the design of such a system and the completed product and its components. Also included, are detailed descriptions of the methods used in characterizing CN VFET and CN VOLET devices. D ual Glovebox Vacuum Thermal Evaporation System Spin coating and vacuum thermal evaporation methods are used for depositing thin organic and metallic films. Due to the air and moisture sensitivity of organic based materials, an added complication is accompl ishing thin film deposition in the absence of water and oxygen. Integrated glovebox systems including spin coating, solvent processing, annealing and vacuum thermal evaporation capabilities in an inert environment are available commercially but are expensi ve. Described here is a self designed and in house fabricated integrated glovebox system which accomplishes all the required coating and processing requirements for fabricating and electrically characterizing organic electronic devices on pre nanotube coat ed substrates entirely in
38 an inert environment. The following are the set of design constraints followed during the design and construction of the dual glovebox vacuum thermal evaporation system: System must deposit polymer, small molecule organic and meta llic, thin films without exposure to ambient air. Vacuum chambers must have two entry doors, one allowing access from the inert (glovebox) side for loading and unloading of samples and switching of evaporation boats and crucibles and the other allowing ent ry from the ambient side for periodic cleaning and chamber maintenance. Vacuum chambers must pump down to a sufficiently low pressure (< 1.0 10 6 torr) in as short a time as possible so as to not limit experimental throughput. System must adopt a simple design and work as anticipated the first time and be finished on time for minimal cost (i.e. no prototyping allowed and no wasted time and money for fixing faulty designs). The organics system must be capable of co evaporation. The metals system must have a versatile boat clamping mechanism which allows Both chambers must have a viewing window with periscope which allows viewing of the boats during deposition but does not allow depositio n material to accumulate on and obstruct the viewing window. The chambers must have a rotating substrate holder with an adjustable source to Wi th these design constraints as the guide, the author, his research advisor Professor Andrew Rinzler, UF physics machine shop engineers Bill Malphurs and Marc Link met and came up with initial designs for the system. After several meetings and design iterat ions, a design was settled upon that satisfied the above constraints. The system was designed around two already existing glovebox shells. Figure 2 1 shows the AutoCAD rendering of the system, which was drawn by the author. Everything pictured in Figure 2 1 (except for the two glovebox shells) was designed from scratch. Detailed
39 layouts of every part pictured (and of others not pictured or within view) were drawn by the author and fabricated entirely by Bill Malphurs of the machine shop. Figure 2 2 shows t he finished system from the front (glovebox side) and Figure 2 3 from the back. Figure 2 1. CAD rendering of the dual glovebox vacuum thermal evaporation system. Vacuum Thermal Evaporators of Metals and Organics Two separate vacuum chambers were fabricated for the deposition of metals and organics. Generally, metals have a substantially higher boiling point than organics. For this reason, separate evaporation chambers were fabricated, dedicated to each, to prevent the cross contamination that would likely o ccur. For instance, If a single
40 Figure 2 2. Image of the dual glovebox vacuum thermal evaporation system. chamber were used in which metals and organics were deposited, suppose organic residue from an earlier deposition run were deposited on a component of the chamber nearby a source which was used for depositing a metal. If this metal source was subsequently heated there would be a chance radiant heat emitted from this source could heat the nearby organic residue causing contamination on the substrate u nder
41 study. It would not be likely for a small amount of organics to adversely affect the bulk properties of the metal, however, it would be likely that unintended organics would affect Figure 2 3. Image of the dual evaporation glovebox system from the b ack the interface between the metal and another previously deposited organic. It is well known that interfaces are very important in electronic devices, both organic  and inorganic . Not to mention, it is generally good practice to minimize all pos sibilities of potential sources of experimental error. Vacuum thermal evaporation of thin films To grow thin films (of organics or metals) by thermal evaporation of high purity, a vacuum is required. A vacuum pressure low enough to allow the evaporant to reach the substrate unimpeded by other gas molecules as it travels from the evaporation source is
42 needed. This requires a pressure low enough such that the average distance between molecular collisions (mean free path length MFPL) be sufficiently larger than the source to sample distance. With a source to sample distance on the order of 20 30 cm, a MFPL appreciably larger than this is necessary. From the ideal gas law, at atmospheric pressure (760 torr) the MFPL for a typical gas is in the range of 100 nm . Under vacuum at a pressure of 1 10 6 torr the MFPL is in the range of 100 m . Pressures around 1 10 6 torr therefore, are typical for this application. In the method of thermal evaporation the material to be deposited the evaporant is placed in the evaporation source, typically a tungsten, molybdenum or tantalum boat, or an effusion cell. With both types of evaporation source, a current is applied through a heating element. In the case of the evaporation boat it is its own heating element. In th e case of the effusion cell, there is a heating coil wrapped around a ceramic crucible, both of which (crucible and coil) are encased in a radiation baffle. Under vacuum, upon heating, the temperature of the evaporant is increased until its vapor pressure becomes greater than the pressure inside the vacuum chamber. Once this happens, the material to be deposited evaporates and a flux of evaporant molecules is emitted from the source towards the substrate. A typical vacuum thermal evaporation chamber is pict ured in Figure 2 4. The evaporation source pictured is the evaporation boat type. Typically there is at least one shutter between the source and the substrate, and at least one quartz crystal monitor for measuring the evaporant flux in situ Also typical i s a rotating substrate for keeping the thickness as uniform as possible over the expanse of the substrate (or array of substrates which certain sample holders can accommodate). Line of sight is required between the source and substrate for the
43 flux to reac h the substrate. Not shown in Figure 2 4 are other necessary components of a vacuum chamber, such as a port connecting to a high vacuum pump (turbo pump, Figure 2 4. Schematic depiction of the components of a vacuum thermal evaporation chamber. The rectan gle encompassing everything represents the walls of the vacuum chamber. diffusion pump or cryo pump is typical), a port connecting to a vacuum gauge (for pressure measurement), and an entry door. Metals evaporation chamber The metals chamber is equipped wi th four sources as shown in Figure 2 5. The sources are equivalently referred to as pockets, and labeled 1 4. Evaporation boats are used as the sources. Copper power feedthroughs provide the heating current for the boats. Figure 2 5 is a view of the inside of the metals chamber from the glovebox side (front). Also shown is the shutter (U shaped plate above the sources). The purpose of the shutter is to block the flux of source material from reaching the substrate when
44 needed. Typically at the beginning of a growth run the shutter is closed (flux path blocked to the substrate) while the source is brought up to temperature and the desired Figure 2 5. Image of the source layout in the metals evaporation chamber. growth rate (as observed by the quartz crystal monitor) is reached. Once the growth rate is stable, the shutter is opened to allow line of sight access of the source material to the substrate. The shutter is closed upon reaching the desired thickness, thereby completing the evaporation of the layer. Or ganics evaporation chamber The organics chamber is equipped with two effusion cells and three evaporation boats. The layout of the sources is as shown in Figure 2 6. The chamber is equipped with two quartz crystal monitor sensors. Sensor 2 on the left (Fig ure 2 6) is in line of sight view of pocket 5 and effusion cell 1 and is shielded from the other three sources by a separator plate. Sensor 3 is in line of sight view of effusion cell 2 and pockets 6 and 7 and shielded from the other two sources by the sam e separator plate. This design allows for the capability of co evaporation. In co evaporation, the growth rate of
45 evaporant flux being emitted form a source on the left side of the separator plate can be independently controlled by sensor 2 while simultane ously controlling, independently, Figure 2 6. Image of the source layout in the organics chamber. the growth rate of a second source, which is located to the right of the center separator plate, by sensor 3. Co evaporation is useful for doping of organics Doping is the process by which a dopant organic material is incorporated in a dilute concentration with the organic material to be doped. This is accomplished through simultaneous thermal evaporation of the two materials where the ratio of the growth rat e of the dopant to the growth rate of the material to be doped is equal to the volume fraction of doping, which, by definition is less than 50 %. Doping can be used to enhance injection at organic interfaces [65 67] and transport through the bulk [65 67], as well as provide a means to control the color of the emitted light of OLEDs . Figure 2 7 shows the details of the effusion cell model used in the organics chamber. The windings of the heating coil (Figure 2 7A) have a non uniform winding
46 density alon g the vertical direction. The spacing betwee n windings is smaller nearest the top. This is to keep the heating profile uniform along the length of the crucible to Figure 2 7. Schematic of the effusion cells. A) Image of the Radak I effusion cell with righ tside partially cut away. B) Section drawing of the Radak I [ Images borrowed from Product Data Sheet : Radak I Evaporation Furnace, Friday Harbor, Washington: Luxel Corporation ]. prevent organic material from condensing near the opening at the top . The Radak I effusion cells in the organics chamber do not have a radiation baffle or a crucible liner (Figure 2 7B). Features Included in Both Metals and Organic Evaporation Chambers Custom features were designed into the evaporation chambers that were deemed relevant to applications of their use. An adjustable source to sample distance was implemented to increase the versatility of the evaporators. A custom periscope allowing visual monitoring of the sources during evaporation through a viewing window was A B
47 inc luded. Another feature is a plate designed to block the path of the evaporant from reaching the port connected to the turbo pump, preventing debris from flaking off and being sucked up by the turbo pump. Adjustable source to sample distance There are time s when the source to substrate distance needs to be modified. For instance, the further away the substrate is from the source the more uniform the thickness of the deposited film is over a larger area. However this comes with the expense of a greater mass of source material consumer per thickness of film deposited. If small samples are used, or if valuable source material is used, the source to sample distance can be reduced to consume less material. The substrate holder of both the metals and organic chamb ers can be adjusted to several discrete heights relative to the level of the evaporation boats. Three extension rods each of differing length were made as shown in Figur e 2 Periscope aided source viewing A viewing window was designed into the back door of both evaporation sy stems for monitoring of the evaporation boats during growths. However, without proper preventative measures, after a few deposition runs evaporant would deposit onto the viewing window obstructing viewing path. The solution for this was to design a perisco pe where the backside of the first mirror (large mirror in Figure 2 9) provided the means to block the evaporant in the line of sight path from the evaporation sources to the viewing window, and the second mirror (smaller mirror in Figure 2 9) allowed for an
48 Figure 2 8. CAD drawing of the substrate holder and interchangeable extension shafts for varying the source to substrate distance. offset view of the evaporation sources. The second mirror is in the direct path of the evaporant, which means that layers of deposited source material will get deposited on it during each growth run. However, vacuum deposited thin films are optically smooth and therefore will not impede viewing through the mirrors after layers of evaporant have been deposited. Turbo pump blo ck plate In a precautionary effort to keep debris from being sucked into the turbo pump, a block plate was placed in both chambers in the line of sight path between the turbo pump port and the evaporation sources (Figure 2 10). This plate shields evaporant from accumulating on the side walls of the chamber in the vicinity of the turbo pump. This eliminates the possibility of the turbo pump sucking up a nearby flake of accumulated
49 mixed evaporants, if one were to delaminate from the side wall. Were the turbo pump to suck up debris of this kind, severe damage would likely ensue resulting in high repair Figure 2 9. Images of the periscope in the metals chamber from the backside of the glovebox. A) A zoomed out view and B) looking from the position of the view port window the evaporation sources are visible through the periscope. A B
50 costs and long experimental downtime. The block plate in the metals chamber is mounted to the crystal monitor mount (Figure 2 10A) and the block plate in the organics chamber is mounted to a bracket attached to the periscope (Figure 2 10B). Figure 2 10. Images showing the periscope and turbo pump evaporant block plate in A) the metals evaporation chamber and B) the organics evaporation chamber. Spin Coater For depositing polymer films, spin coating is an effective method. Unlike organic small molecules, polymers cannot be thermally evaporated due to their relatively large molecular size. If a thermal evaporation of a polymer was attempted, damage to the polymer chains would likely occur during such a growth. In the spin coating method the polymer to be deposited is initially dissolved in a solvent solution. When dispensed onto the sample, the solution wets the entire surface of the substrate it is being deposited on before being taken to high speed rotation for thin film formation. If the sample is small A B
51 Figure 2 11 A) Image of the spin used in the glovebox. B) Image of the spin coater used outside the glovebox. diameter Si wafer) the substrate can be rotated slowly while dispensing the solution to the center of rotation allowing the puddle to spread out over the en tire substrate. Once fully wetted, the substrate can be spun at high speed. The spin coating process is dominated by two regimes. In the first regime the spinning substrate causes convective outflow of the polymer solution radially outward and off the edge s of the substrate leading to thinning of the viscous fluid layer. As the film thins the solvent evaporates causing the viscosity to increase leading a decreased rate of thinning by convective outflow, leading to the second regime. In the second regime, fu rther thinning of the polymer film is dominated by evaporation of the solvent . Spin speeds for spin coating of polymer solutions are typically in the range of 1000 to 4000 rotations per minute (rpm). A B
52 Pictured in Figure 2 11 are the spin coaters used f or the experiments of this dissertation. A Specialty Coatings Systems model G3P8 spin coater (Figure 2 11A) was used for spin coating films inside the glovebox. And a Laurell model WS 400B 6NPP/LITE (Figure 2 11B) was used for spin coating outside the glov ebox. Current Voltage Luminance Measurements Current voltage ( I V ) measurements for the three terminal transistor devices are made with a Keithley model 2612A Sourcemeter (Figure 2 12A). The Sourcemeter has two channels. One channel is for providing the dr ain voltage and measuring the drain current and the other channel is for providing the gate voltage and measuring the gate leakage current. The Sourcemeter is controlled by a computer (Figure 2 12A) with a program written in LabVIEW. Current voltage measur ements were carried out either at the ambient probestation (Figure 2 12) or the glovebox probestation (Figure 2 13) Ambient Probestation A Micromanipulator brand probestation was used for I V measurements. Gold coated needle probes were used for making con tact to the devices under study. In cases where the electrode in need of contact was deposited atop an organic layer (like the drain electrode of the CN VFET) a 28 m diameter gold wire was wrapped around the gold coated needle probe and used to make soft contact to the device. This avoids the possibility for penetrating the delicate underlying organic. The probestation is equipped with four needle probes in total. A microscope (Figure 2 12A) was used to view the device under investigation while placing the needle probes in contact with their respective electrodes on the device. Micromanipulators enabling motion of the needle probes in the x y and z directions throug h turning of knobs, one for each direction mentioned (Figure 2 12B) enabling, two, three and four terminal I V measurements.
53 Figure 2 12. A) Image of the current voltage measurement system. B) Up close image of the needle probes and probe manipulators for making contact to the sample. C) Image of the probestation with the electromagnetic noise shield in place. When measuring transistor devices, stray electromagnetic noise became an issue. To combat this noise, an Al foil wrapped box was used as an electrom agnetic noise shield. Glovebox Probestation A second probestation was fabricated for the experiments of this dissertation which allowed for I V characterization of devices without exposure to the ambient air. This probestation is located inside the dual gl ovebox vacuum thermal evaporation system with an inert environment consisting of argon and less than 0.1 parts per million of oxygen and water. Having two probestations, one in the ambient air and one in an inert environment, systematic investigation of th e effects of these two environments A B C
54 Figure 2 13. A) Glovebox probestation. B) Glovebox probestation with electromagnetic noise shield in place. on carbon nanotube based organic electronic devices can be explored. An optical video camera (Figure 2 13A) co nnected to a personal computer provided close up viewing of the devices allowing placement of the needle probes for making electrical contact. This probestation is also equipped with an electromagnetic noise shield made from Al foil (Figure 2 13B). This pr obestation has three probes and is capable of two terminal and three terminal I V measurements. The same Keithley 2612A Sourcemeter used for the ambient probesation was used here. Luminance Measurements For light emitting devices the probestations mentione d in the previous two sections were not used. Instead, a clamping mechanism for making electrical contact to the topside of the devices while measuring light output through the bottom of the substrate A B
55 was used. Spring loaded gold coated contact probes make electrical contact to the electrodes on the devices in pre defined locations. The sample layout is such that there are 4 devices per substrate, each with a source, drain and gate electrode. The connection board has multiple connection ports which are hard wired to every electrode contact of every device. This allows for quick switching between the four devices on the substrate. The sample remains clamped while the wires are switched between ports on the connection board to the next device. The clamping mec hanism and all of its components (except the photodiode) were designed by the author and fabricated in house. Figure 2 14A shows the components of the clamping mechanism and the Si photodiode (Advanced Photonix, Inc. model SD444 12 12 171) used for measuri ng the light output. The photodiode photocurrent was measured by a Keithley 2400 Sourcemeter and data recorded by a program written in LabVIEW. One labview program was written for simultaneous recording of the photocurrent measurement from the Keithley 240 0 and the transistor I V measurements from the Keithley 2612. The photocurrent from the Si photodiode was calibrated for luminance output of the device under test with a Minolta LS 100 luminance meter. The device under test was held at several different li ght output intensities for calibration. At each intensity the photocurrent from the photodiode and the luminance from the luminance meter were recorded. The ratio of the two values at each intensity were averaged together to yield the photocurrent to lumin ance conversion factor, which was input to the LabVIEW measurement program to automate the conversion process. The procedure for loading the samples is as follows. First the substrate is placed on the mounting plate (Figure 2 14B). This is followed by plac ement of the top clamp on the mounting plate (Figure 2
56 14C) where the spring loaded contact probes become pressed into contact with their respective electrode on the device. The top clamped mounting plate is then inverted and placed into the base (Figure 2 14D) where the photodiode is then inserted (Figure 2 14E). Figure 2 14. A) The clamping mechanism for making luminance measurements on bottom emission CN VOLETs. (B E) Images at different steps of the mounting procedure of the device. Capacitance Measur ements Capacitance was measured with an HP 4284A Precision LCR meter at 1 kHz at a voltage amplitude of 100 mV, operated in parallel capacitance resistance ( C p R p ) mode.
57 X ray Diffraction Measurements X ray diffraction samples were measured with a Philips APD 3720 operated in /2 mode (Cu K = 1.541 ). Continuous scans from 2 = 5 to 2 = 30 in increments of 0.02 with a 4 second integration time were taken on all samples. Figure 2 15 shows an image of the instrument. Atomic Force Microscopy Measurements At omic force mi croscopy images were recorded on a Digital Instruments Multi Mode AFM (Figure 2 16) operated in tapping mode at low scan speeds with the tapping force minimiz ed by keeping the amplitude set point very near the free space amplitude. Ultraviolet Visible Near Infrared Transmission Measurements Ultraviolet visible near infrared transmission spectra were recorded with a Perkin Elmer Lambda 900 dual beam (UV/VIS/NIR) spectrometer (Figure 2 17A). The dual beam allows for characterizing and subtracting out signal a bsorption from the substrate that the film of interest is deposited on. This is done by preparing two identical substrates, one with and one without the film of interest. Then the samples are mounted on the sample holders in the substrate compartment (Figu re 2 17B), one substrate per holder. In the transmission experiments in this dissertation, glass microscope slides were used as the substrates.
58 Figure 2 15. Image of the Phillips APD 3720 ( Source: htt p://maic.mse.ufl.edu/Xrds.htm Last accessed September, 2010 ) Figure 2 16. Image of the Digital Instruments Multi Mode AFM.
59 Figure 2 17. A) Image of the Perkin Elmer Lambda 900 UV/VIS/NIR dual beam spectrometer. B) Image of the sample compartment of th e spectrometer. A B
60 CHAPTER 3 FIRST DEMONSTRATION OF CARBON NANOTUBE E NABLED VERTICAL FIEL D EFFECT AND LIGHT EMI TTING TRANSISTORS This chapter reviews the initial demonstration of the carbon nanotube enabled vertical organic field effect transistor (CN VFET ) a nd carbon nanotube enabled vertical organic light emitting transistor (CN VOLET ). The inference that the devices function as Schottky barrier devices is supported by theoretical simulations conducted by our University of Florida collaborators P rofessor Jin g Guo and research assistant Youngki Yoon. Introduct ory Remarks Thin film transistors provide the drive circuitry for present and emerging active matrix displays including liquid crystal and organic light emitting diode display technologies. The dominant s emiconductor material in these devices is amorphous Silicon. However, the promise of inexpensive, solution based processing techniques, inkjet patterning and construction on flexible plastic substrates has focused much research over the past 20 years on or ganic semiconductors as replacements. There now exist a broad range of small molecule organic and polymeric compounds that have demonstrated transconductance. Unfortunately, the electronic mobilities of these compounds, which were initially about 5 6 order s of magnitude too low to be commercially useful, remain about an order of magnitude too low. Such low mobility can be compensated for by bringing the source and drain electrodes closer together reducing the semiconductor channel length ( L in Figure 3 1A), but that greatly raises the cost of patterning the devices, removing much of the motivation. As mentioned in Chapter 1, the vertical field effect transistor (VFET) architecture provides a solution. Working independently, with a material set distinct from that of the
61 VFET by Yang and coworkers , we have arrived at a similar departure from the conventional TFT architecture using single wall carbon nanotubes as the source electrode and the conventional gate dielectric silicon dioxide. The devices were fu rther elaborated upon to demonstrate a gate voltage controlled light emitting diode, also called a light emitting transistor. Here we describe the devices, highlighting the important advantages presented by using carbon nanotubes. Additionally, we communic ate some relevant properties of carbon nanotubes previously unrecognized. In a TFT, a gate electric field induces carriers in the semiconductor layer, allowing current to flow between the drain and source electrodes. Figures 3 1A and 3 1B compare, schemat ically, a conventional TFT and the new architecture. In contrast to the architecture of a TFT, in which the drain, semiconductor layer, and source are co planar with respect to the gate and gate dielectric, the new structure stacks the drain, semiconductor layer and source vertically relative to the gate, and is designated as a vertical field effect transistor (VFET). For the VFET architecture a continuous metal source electrode sheet would completely screen the gate field from the semiconductor layer, henc e a necessary requirement for its operation is that the source electrode be perforated (in a sense), making it porous to the gate electric field. The source electrode shown as a regular grid array in Figure 3 1B is meant to convey this idea but should not be taken literally. field porous source electrode by the partial oxidation of a very thin aluminum film . Our gate field porous source electrode is a network of single wall carbon nanotubes, in a dilute layer that is n evertheless well above the percolation threshold. An atomic force microscope (AFM) image is used to represent
62 the CNT source electrode in Figure 3 1C its dimensions are 1 Note, that for the VFET, the channel length L is simply the semiconductor layer film thickness. This can be made almost arbitrarily thin, without the need for high resolution electrode patterning. Our device, with a CNT source electrode, is ter med the CN VFET. Figure 3 1. Schematics of A) a TFT, B) a VFET with a generalized porous source electrode depicted by a grid and C) the CN VFET. Carbon Nanotube Enabled Vertical Field Effect Transistor Experimental Details Nanotube networks were formed on nanoporous mixed cellulose ester membranes . Pieces of the membrane with the associated nanotube networks were cut into the desired shape and size with a razor blade before transfer of the networks to a 200 nm
63 thermal SiO 2 gate dielectric on heavily p doped, < .005 ohmcm, prime silicon (Silicon Quest International), which provided the back gate. Three distinct organic semiconductor layers were used. 1) poly[(9,9 dioctyl fluorenyl 2,7 diyl) alt co (9 hexyl 3,6 carbazole)] (PF 9HK, American Dye source) was deposited by spin coating from toluene onto the nanotube networks, followed by di(1 naphthyl) diphenyl diphenyl diamine) (NPD, Lumtec Corporation) was thermally evaporated at 2 /s to a thickness of ~275nm. 3) Regio regular poly(3 hexylthiophene) (P3HT) (Sigma Aldrich) was spin coated, followed by vacuum drying, resulting in a thickness of ~ 300 nm. The drain contact in all cases was 20 nm of thermally evaporated gold. Physical la yout of a typical device is shown in Figure 3 2. The silicon substrates were diced to a size of 15 15 mm 2 The oxide was etched from one corner and Pd sputtered for the gate contact pad (split contact to confirm Ohmic behavior). Gold contact pads to prov ide the source contact (to the SWNT network) were evaporated define the source drain terminals of what would become a side by side, bottom contact, conventional planar TFT The nanotube network was transferred to lay across the Au source contacts (the two contacts to permit confirmation of Ohmic contact between the network and pads and monitor the resistance of the CNT source electrode). The semiconductor layer was deposite d over the entire substrate atop the nanotube network. Finally, Au was evaporated onto the semiconductor layer through a TEM grid shadow mask (inset photograph). The TEM grid shadow mask defined 0.035 mm 2 area hexagonally shaped drain contacts (200 m in size between parallel sides of the
64 hexagon) that could be probed individually. Gold coated needle probes were used to make electrical contact to the pads and a soft gold wire to make contact to the top drain contact to avoid piercing through the gol d drain and semiconductor layer. The Figure 3 2. Device schematic of the CN VFET. Top view. serving as the semiconductor. However the corresponding conventional TFT de vices using PF 9HK or NPD as the semiconductor layers, showed no detectable current, a consequence of their deeper lying HOMO (highest occupied molecular orbital) levels and low mobilities. Results and Discussions Initial study began with a VFET structure using a dilute CNT network as the source electrode The CN VFET structure is shown in Figure 3 1 C. It is designed as a hole only device by c hoosing a semiconducting layer material whose HOMO lies near the work functions of the nanotube source and metallic drain electrodes Figure 3 3A shows the
65 flat band alignment of an organic semiconductor that forms a hole injection barrier with CNTs. The structures for the PF 9HK and NPD are shown in Figures 3 3B and 3 3C, respectively. These materials were chosen becau se their HOMO level is several hundred meV deeper than the work function of the CNT film resulting in a barrier bh for Figure 3 3. A) Flat band diagram of the materials used in the VFET and the organic molecules used as the semiconductor layer in the VFET B) PF 9HK and C) NPD hole injection into the organic semiconductor ( bh ~ .7 eV for PF 9HK, and ~ .5 eV for N PD). It was determined in the CN VFET that materials creating a Schottky barrier with the CNT network enabled the transistor action seen in Figure 3 4 (more below). Figure 3 4 shows the transfer and output curves using PF 9HK and NPD as the organic semico nducting layer. Under positive gate voltage, bh is increased along with the width of the barrier (elaborated below). This causes a decrease in the drain current with increased positive gate voltage. Under negative gate voltage the inverse happens and the drain current increases with increasing negat ive gate voltage. As shown in Figure 3 4A the current in the VFET is modulated by over 2 orders of magnitude. Evident in the output curves of Figures 3 4B and 3 4C is that the turn on voltage (on a linear scale) lies near 4 V. This is an indication of a l arge hole injection barrier. Also
66 Figure 3 4. Transistor J V characteristics of the hole only VFETs A) Source drain current as a function of gate voltage for both material systems. The black arrows in indicate the sweep direction PF 9HK devices have not iceably larger hysteresis than the NPD devices B) Output curves for the PF 9HK VFET and C) NPD VFET at the gate voltage specified near each curve PF 9HK thickness is ~250 nm and the NPD device is ~275 nm thick The amount of hysteresis of the PF 9HK devi ce is shown in blue A) evident in the output curves is a larger current density in the NPD device than the PF 9HK device. This behavior is explained by the larger injection barrier of bh ~ .7 eV for PF 9HK vs. bh ~ .5 eV for NPD. Only slight transconducta nce (on/off ratio ~ 1.5) was observed when P3HT was used as the semiconductor layer; P3HT HOMO level ~ 5.0 eV . Counter clockwise hysteresis in the transfer curves of Figure 3 4A is present for each material system. The origin of the hysteresis is like ly charge traps in the organic semiconductor layer and is common in OLEDs  and in CNT FETs [75, 76]. The noticeable reduction in the hysteresis for the NPD device indicates that the magnitude
67 can be modified by the choice of organic layer used in the d evice. The hysteresis of the PF 9HK device is = 76 V and the NPD device = 28 V. Elect rostatic simulations on the CNT/ organic semiconductor j unction were carried out by P rofessor Jing Guo and researcher Youngki Yoon to determine the effect of the gate electric field on the band line up . A two dimensional Poisson equation was solved self consistently with the equilibrium carrier statistics of the CNT and organic semiconductor contact using the following three assumptions: i) the nanotube network is sparse so that a single nanotube wa s studied in the calculation, ii) a 2D cross section through the vertical plane perpendicular to the nanotube long axis wa s simulated, iii) the nanotube wa s an individua l single walled metallic tube. A semiconducting nano tube or a small bundle of various tubes has a different density of states but the qualitative results were expected to be the same. Figure 3 5 shows the effect on the junctio n for different gate voltages. The contact barrier is seen to thin and the barrier height, bh is lowered as the gate is made more negative. The gate voltage induced shift of the nanotube Fermi level is seen inside the nanotube about x = 0 nm. Both the barrier thinning (as a consequence of the gate induced band bending) and the barrier height l owering contribute to the to the tran sconductance seen in Figure 3 4. An important new feature demonstrated here results from the intrinsic low density of states (DOS) for the nanotubes. In contrast to metals, which possess a high DOS, the Fermi level of t he low DOS nanotubes can undergo an appreciable shift in response to the gate field. Hence, in addition to the thinning of the contact barrier due to the gate induced band bending, bh is also lowered. This is a key difference between CNT
68 semiconductor contacts and conventional metal semiconductor contacts. The high DOS of metals simply does not permit the Fermi level shift necessary for a change in the Figure 3 5. Valence band ener gy level simulation vs. horizontal position x from CNT cross section center at V G = 1 V, 10 V and 20 V taken at y = 1 nm, where the interface between the organic semiconductor and the gate oxide is defined as y = 0. The Fermi level E F is defined as zero and is represented by the horizontal dotted line. Vertical arrows indicate the barrier height bh at each voltage. The nanotube diameter is 5 nm with its center located at x = 0 and y = 2.5 nm. The inset shows the simulated structure and coordina tes barrier height. The first time a true barrier height modulation was reported was by Lonergan in 199 7 . Lonergan demonstrated an electrochemically induced barrier height modulation in an air sensitive polymer/inorganic (poly(pyrrole)/n indium phosphide) contact barrier, (although, the polymer is not a true metallic system, as are the nanotubes). The on/off ratio of the CN VFET is expected to be lower with organic materials that form an ohmic contact with CNTs because the CNTs used in these studies exist in bundles (further details of the composition of this CNT material are given in Appendix
69 B). The i nability to effectively modulate the current using P3HT led to the conclusion that it was the screening of the gate electric field from the top nanotubes in the bundles ( furthest from the gate ) that was the problem, an idea that also found support in the e lectrostatic simulations . The nanotubes in the bundle nearest the dielectric have their Fermi level readily modulated by the gate electric field; however those nanotubes screen the nanotubes in the top of the bundle from the same field. Because the CN VFET relies on the gate field induced modulation of the schottky barrier between the CNTs and the organic, the regions where the gate field is screened (i.e. at the top of the CNT bundle), do not experience a significant modulation of the schottky barrier Therefore, if an organic material forming an initially ohmic contact with the CNTs is used in the CN VFET, the regions near the top of the bundle remain ohmic and allow for charge injection even when the gate has turned the nanotubes at the bottom of the bundle off ii leading to a poor on/off ratio. This explains the poor on/off ratio when P3HT was used in the CN VFET. Figure 3 6 illustrates the phenomenon mentioned in the previous paragraph. Shown in red are possible paths taken by charge carriers inject ed from the CNT source as they travel through the organic semiconductor to the top metallic drain. Organic materials that form a normally on (ohmic) energy alignment with the nanotubes have current injection from all regions of the junction between the CNT s and the organic in the on state (Figure 3 6A). When this device is switched off (positive V G ), the top tubes in the bundle still inject carriers into the organic (Figure 3 6B), because of the screening ii Off state for the p channel CN VFET is when the gate voltage is positive (Figure 3 4). In the side and bottom regi ons of the bundle (where the CNT Fermi level is more readily modified because the gate electric field is not screened) the initially ohmic contact is expected to be transformed to a schottky barrier contact allowing for the hole injection to be reduced in the off state of the device.
70 Figure 3 6. Diagrams depicting paths of current f low between the bundled nanotube source and the drain electrode in the CN VFET. The case of i) an organic layer forming an initially ohmic contact with CNTs (A and B; device in A switched on and B switched off) and ii) an organic layer forming an initial s chottky contact with CNTs (C and D; device in C switched on and D switched off). by the nanotubes in the bottom of the bundle, leading to the poor on/off ratio. In contrast, when organic materials that form an initially off energy alignment (Schottky barri er) with CNTs are used, the nanotubes near the bottom of the bundle can be switched on (Figure 3 6C) under negative gate voltage. At positive gate voltage these bottom nanotubes are then switched off. And because of the initial barrier formed between the C NTs and the organic, under positive voltage, all regions of the bundle B C D A
71 (top, sides and bottom) are expected to be non injecting (Figure 3 6D) giving a significantly larger on/off ratio due to a lower off current. Carbon Nanotube Enabled Vertical Organic Li ght Emitting Transistor Experimental Details Following development of the CN VFET, it was realized that with two simple modifications the device could be transformed into a light emitting transistor. The drain electrode material was changed to a metal wit h a shallower work function to enable the Figure 3 7. CN VOLET layout. Scale in inches. injection of electrons. And, an electroluminescent layer was added. When these layers were added, the electrons enabled by the shallower work function drain recombined with the holes injected from the CNT source in the emitting layer creating light. A widely used OLED electroluminescent layer Alq 3 was used. Figure 3 7 shows the device layout for the CN VOLETs. Substrates were 160 nm of atomic layer deposited aluminum
72 ti tanium oxide (ATO) on un patterned ITO/glass (Planar Systems) onto which the nanotube networks were transferred. PF 9HK was deposited by spin coating from toluene followed by drying for one hour on a 95 C hot plate in a nitrogen glove box, yielding a 200 nm thick film. Figure 3 8 shows the device cross section and wiring Figure 3 8. VOLET device with Alq3 as the emitting layer and PF 9HK inserted between the NPD layer and the CNT network. schematic. NPD and Tris (8 hydroxyquinoline) aluminum (Alq 3 ) (Lumt ec Corporation) were deposited at 2 /s to thicknesses of 100nm and 50nm, respectively. These were followed by thermal evaporation of LiF (1nm) and Al (100nm). Gate contact was made by scratching through to the ITO layer and pressing onto the scratch an in dium dot. Results and Discussions Electro optic measurements on the CN VOLETs were recorded. The luminance and current density versus voltage data are shown Figures 3 9A and 3 9B, respectively. The luminance proportionally tracks the drain current. Figure 3 9C shows the device efficiency (luminance divided by the current density plotted vs. current density). The transfer curves in Figure 3 9D are similar in shape to those for the PF 9HK CN VFET in Figure 3 4A. Bright spots in the pixel zoom (inset of Figure 3 9B) are likely caused by
73 particulates that underlie the nanotube network resulting in a local thinning of the source drain channel length. This is supported by the principal failure mode in the devices of direct electrical shorts between the source drai n electrodes as the electroactive layers were thinned (for present fabrication controls). This issue also limited the performance of the VFETs and highlights the need for ultrahigh purity nanotube material and cleanliness of the environment in the network fabrication. However, it also indicates that there are improvements to be obtained from thinning the electroactive layers. Conclu ding Remarks This chapter reviewed our initial demonstration of two pot entially important new devices. The devices control the current through them by the gate modulation of a Schottky barrier between a dilute, percolating nanotube source layer and the semiconductor that coats the nanotube layer. In addition to the gate induced barrier thinning the low density of states of the qu asi 1D nanotubes results in a gate induced change in the barrier height due to the Fermi level shift in the nanotubes (an effect not previously reported between a metal and a semiconductor). T ogether, t hese effects boost the degree of current modulation in this type of device Because the semiconductor layer covers the entire source electrode it can be deposited by a number of conventional thin film deposition techniques allowing it to be made almost arbitrarily thin before deposition of the top metal drain electrode. The resulting short channel lengths mean that relatively low mobility semiconductors, such as the organic semiconductors used in the CN VFET demonstration, can be used and still result in appreciable current at relatively low source drain bias. The architecture of the CN VFET evolved in a very straight forward manner to the light emitting transistor demonstrated in
74 the CN VOLET. A number of problems were also identified; these first devices exhibited a large hysteresis, and required a large gat e voltage for a modest on off ratio of only 10 2 To become technologically relevant dramatic improvements were necessary. Figure 3 9. A) Current density and B) luminance vs. voltage plots for the PF 9HK modified CN VOLET device The p ictures of the pixel s inset in B) are taken at V D = 7 V and V G as labeled; pixel size is 2 mm by 2 mm. C) T he efficiency of the CN VOLET device under different gating conditions D) CN VOLET luminance transfer curv es at V D = 7, 10 and 13 V
75 CHAPTER 4 OPTIMIZATION OF PEN TACENE BASED CARBON NANOTUBE ENABLED VERTICAL FIELD EFFEC T TRANSISTORS This chapter presents two important modifications to the carbon nanotube enabled vertical field effect transistor (CN VFET). Baking the single walled carbon nanotube (CNT) film prior to deposition of the organic semiconductor layer modifies its work function allowing materials which would have initially formed an ohmic contact with unbaked CNTs to form the necessary Schottky barrier contact. This broadens the range of organic semiconduct ors that can be used in the CN VFET, including the well known high mobility organic, pentacene. The second modification, addition of the hydrophobizing dielectric surface layer benzocyclobutene (BCB) prior to deposition of the CNT source electrode, improve d the on/off ratio and significantly reduced the hysteresis. Current density vs. voltage ( J V ) measurements were used to characterize the effects of these treatments on the CN VFET performance. Introduct ory Remarks Chapter 3 described the initial demonstra tion of the CN VFET. Proof of principle was demonstrated but the device performance required improvement. The on/off ratio was low, ~ 100. And the hysteresis was large; 76 V over a total gate voltage scan range of 175 V required to switch the device betwee n fully on and off states. This equates to a hysteresis of ~ 40% of the total gate voltage scan range. If the CN VFET is to have commercial relevance, increasing the on/off ratio and decreasing the hysteresis are critical. This Chapter discusses two simple modifications to the CN VFET that largely accomplished these goals and resulted in further benefits that are discussed The CNTs used in these experiments are charge transfer doped by their nitric acid purification. This leaves the CNTs doped p type with a workfunction of ~ 4.9 eV. It is
76 known that baking the CNTs removes the adsorbed charge transfer dopants shif ting their work function toward their intrinsic value of ~ 4.6 eV . Upon shifting the work function of the CNTs toward their intrinsic value, organ ics with a HOMO level around ~ 4.9 eV could be expected to form the required Schottky barrier with the CNT source electrode of the CN VFET. This should thereby allow the use of materials such as pentacene (highest occupied molecular orbital (HOMO) l evel of 5.0 eV ) to be used and yield significant transconductance in the CN VFET. The relative degree of charge transfer doping in CNTs is accessible via ultraviolet visible near infrared (UV VIS NIR) spectroscopy. Spectroscopic characterization of t he baked dilute CNT networks, such as those used in the CN VFET is presented in Appendix A. J V measurements were used to investigate the effect of baking the CNT source electrode in pentacene CN VFETs. Before 2005 it was generally thought that most orga nic semiconductors were poor transporters of electrons. It was thought that the organic semiconductor was responsible for the electron trapping observed in many materials that were known to be good hole transporters. However, in 2005 Chua et al.  demon strated that it was the silicon dioxide dielectric surface that was responsible for the trapping of electrons. When they treated the silicon dioxide dielectric surface with a thin hydrophobic polymer layer or self assembled monolayer (SAM) the electron tra pping was significantly reduced. This trapping reduction was related to the removal of hydroxyl groups known to exist on the surface of silicon dioxide. BCB was one of the thin polymer layers used in their experiments and yielded a hydroxyl free surface. T his motivated us to try BCB in the CN VFET. It was expected that BCB would reduce the charge trapping induced
77 hysteresis observed in CN VFETs. CN VFETs with and without a BCB dielectric surface layer were therefore fabricated and the effects on the transis tor J V characteristics compared. Experimental Details CN VFET devices were fabricated by methods similar to those in Chapter 3. Detailed here are the steps of the procedure that differed from those in Chapter 3. Heavily doped p type (100) silicon substrat es with a 200 nm thick thermal oxide served as the bottom gate substrates for these experiments. CNT networks with the same density as those in Chapter 3 were used for these devices. Four devices were fabricated. Two devices had no BCB dielectric surface l ayer (bare oxide devices) and two devices received the BCB layer. For each of these two sets of devices, one received a CNT de doping bake (as described below) and the other did not. BCB (trade name Cyclotene 3022) from Dow Chemical Co. was diluted in trim ethylbenzene (Dow Rinse Sovent RS T1100) and spin coated to a thickness of ~ 10 nm onto the silicon dioxide dielectric of the BCB devices. The BCB layer was subsequently hard baked at 250C for 1 hour on a hotplate in the argon glovebox where it cross lin ks and becomes impervious to solvents. All four devices received Cr/Au source contacts and a subsequently deposited dilute CNT source electrode. These were transferred directly onto the silicon dioxide of the bare oxide devices and directly onto the BCB la yer for the BCB devices. Following transfer of the CNT source electrode one bare oxide device and one BCB device were baked at 225 C for 1 hr on a hotplate in the argon glovebox prior to deposition of pentacene. Evidence on the effect of baking dilute CNT networks is given in Appendix A. Without removal from the glovebox, all four devices were transferred into the organics evaporator for deposition of pentacene. Pentacene was
78 defined by a shadow mask, and deposited at a pressure of ~310 7 torr at a rate o f 3.5 /s to a thickness of 450 nm onto the room temperature substrates. The samples were transferred to a separate vacuum chamber for deposition of the Au drain electrode (without exposure to ambient). The Au deposition was through a TEM grid shadow mask defining dozens of individual, hexagonally shaped pixels each with an area of 0.035 mm 2 completing the device construction. Following deposition of the drain electrode, an indium dot gate contact was pressed into place after first scratching through the S iO 2 /BCB dielectric layer/layers to the silicon gate with a diamond scribe. This was done in the periphery of the substrate. Results and Discussions Discussed first is the effect of baking of the CNT source electrode on the operation of the bare oxide CN V FET with pentacene as the semiconductor layer. Figure 4 1 shows the drain current density ( J Drain ) vs. the gate voltage ( V G ) of the baked and unbaked devices. The on/off ratio of the baked device is 2 orders of magnitude larger than the unbaked device. Thi s can be understood on the basis of the ohmic contact between pentacene and unbaked CNTs and the Schottky barrier contact between pentacene and unbaked CNTs. As discussed in Chapter 3 the bundled nature of the CNTs making up the source electrode is respons ible for the lower on/off ratio in the unbaked (ohmic contact) device. In what should be the off state ( V G = +80 V) the electrostatically screened top CNTs in the bundles of the unbaked device continue to inject holes into the pentacene semiconductor layer due to the ohmic contact resulting in a larger off state current than the baked device. The initial Schottky barrier contact in the baked device explains its lower off state current as well as the larger required drain voltage ( V D ) needed to drive J Drain ~ 10 mA/cm 2 in the on state ( V G = 80 V). Simply
79 baking the CNT source electrode prior to deposition of the pentacene, effects a Fermi level engineering that increases the on/off ratio by two orders of magnitude. Figure 4 1. Transfer curves of bare oxide CN VFETs with and without a CNT bake prior to deposition of the pentacene semiconductor layer. In the device that incorporated a BCB layer, the hysteresis was noticeably increased (Figure 4 2 shows transfer curves of the BCB baked and bare oxide baked devi ces). This behavior was initially disappointing because it was expected that BCB would decrease the hysteresis. To interpret the observed differences between the transfer curves of the bare oxide and BCB CN VFETs we must first understand the mechanisms res ponsible for the hysteresis. The hysteresis loop for the CN VFET follows the counter clockwise direction as indicated by the arrows in Figure 4 2. For a p channel transistor, this is indicative of trapped charge injected from the semiconductor side of the dielectric onto the surface of the dielectric . Possible injection sites are from the CNT source or the pentacene semiconductor, or both. This counter clockwise
80 nature of the hysteresis can be understood as follows. Referring to Figure 4 3 (bottom), an d assuming an initially pristine (never before measured) transistor, beginning at V G = 0 V and following along red curve 1, the magnitude of J Drain begins to increase as V G is swept to 100 V. Under negative V G holes are injected from the CNT source and Figure 4 2. Comparison of transfer curves of CN VFETs with and without a BCB dielectric surface layer, both with CNT bake prior to deposition of pentacene. organic semiconductor to become trapped at the top dielectric interface (Figure 4 3, top left) iii U pon reversal (red curve 2, on to off sweep direction) the electric field from the trapped holes in the dielectric causes J Drain to follow the path of earlier turn off. Continuing to follow the on to off sweep past V G = 0 V, the trapped holes are forced out by the increasing positive V G and eventually electrons are injected to the dielectric iii Figure 4 3 is used to assist in conceptualizing the effect of trapped electrons and holes on the hysteresis. The depictions in Figure 4 3 top right and top left do not address charge accumulation or depletion in the CNT or t he organic semiconductor, the purpose of these schematics is only for the qualitative understanding of trapped charge under positive and negative gate voltage.
81 surface and trapped as V G approaches +100 V (Figure 4 3, top right). Upon reversal J Drain increases earlier along the indicated path (red curve 3, off to on sweep direct ion) in response to the electric field from the trapped electrons. Hysteresis of this nature is unique from that resulting from charges injected to the dielectric from the opposite side of the dielectric (i.e. the gate electrode) and from ferroelectric in sulators . Figure 4 3. Diagrams depicting charge storage on the dielectric under different gate voltage polarities ( A and B ) and resulting hysteresis curve C) Hysteresis in pentacene based TFTs with oxide and bi layer polymer/oxide dielectrics has bee n extensively investigated in the literature [81 85], as well as A B C
82 hysteresis in CNT based TFTs fabricated on similar dielectrics [75, 76, 86 88]. Typically the hysteresis that is seen in these types of devices is attributed to trapping of charge at the diel ectric/semiconductor interface. The hysteresis is generally larger with CNT TFTs which can be understood by an enhancement of the electric field nearest the CNTs emanating from the planar gate electrode terminating on the quasi 1 dimensional nanotubes. In the pentacene CN VFET, the dielectric surface is a mix of partial surface covering CNTs and pentacene filling in between. Therefore it is generally assumed that hysteresis in the CN VFET arises from a similar mechanism as in pentacene only and CNT only TFT s. However, the unique architecture and operating mechanism of the CN VFET compared to conventional TFTs leads to some differences in the phenomena associated with the hysteresis and their interpretation. The main difference in the case of the CN VFET is the phenomenon of unmatched subthreshold slopes for the bare oxide device between the two V G sweep directions (Figure 4 2). For the bare oxide device the subthreshold slope was extracted to be 18.1 V/dec and 8.3 V/dec for the on to off and off to on transf er curves, respectively. The values for the subthreshold slope were extracted from the steepest linear portions of the log linear transfer curves as plotted in Figure 4 2. With BCB however, this phenomenon is not observed and the substhreshold slopes are w ell matched they were extracted to be 6.6 V/dec in both directions. Also evident is the position of the BCB on to off transfer curve significantly left of the bare oxide on to off curve (Figure 4 2). This suggests that BCB stores trapped holes more efficie ntly than silicon dioxide. Indeed this is confirmed in the literature; the silicon dioxide surface is known to trap electrons . BCB on the other hand is known to store holes and electrons equally, and stably as well . This
83 agrees with the more symm etrical hysteresis loop of the BCB device (Figure 4 2) than the bare oxide device. Because of these well matched subthreshold slopes for both sweep directions when BCB is present, it was recognized (in conjunction with my colleague Bo Liu) that three impor tant new functionalities could realized: 1) the large hysteresis can be utilized to turn the CN VFET into a non volatile memory device, 2) the hysteresis can be virtually eliminated by simply reducing the gate voltage scan range, and 3) the turn on voltage can be controlled over a wide range depending on the history of the gate voltage. The first of these three functionalities has been reported elsewhere  and is not further discussed here. The latter two functionalities are demonstrated in Figure 4 4. A t first it seems contradictory, from Figure 4 2, that while the hysteresis was significantly increased with BCB it can also be significantly reduced to become almost negligible. When the total gate voltage scan range of the BCB device was limited to 60 V, the hysteresis was reduced to a mere 2 V (Figure 4 4A). This equates to 3 % percent of the minimal scan range (60 V) to switch the device between fully on and off states. This is a major improvement over the 40 % hysteresis in the initial CN VFET from our past work  (discussed in Chapter 3). Also apparent in Figure 4 4A is the controllability of the turn on voltage over a wide range. B ecause it depends on the history of the gate voltage, the turn on voltage can be modified to the desired value and rema in where placed by limiting the scan range in subsequent scans The far left curve has a turn on voltage of ~ 30 V. And the far right curve has a turn on voltage of ~ +70 V. In contrast, the bare oxide device (Figure 4 4B) has significantly less turn on v oltage controllability. The bare oxide device also suffers
84 from persistence of hysteresis even for reduced scan ranges because of the unmatched subthreshold slopes. Also, the on/off ratio was significantly reduced as well (middle Figure 4 4. A) BCB baked and B) bare oxide baked CN VFETs operated under reduced gate voltage scan ranges. curve Figure 4 4B). To recover the major frac tion of the on/off ratio (far right curve Figure 4 4B) results in an increased hysteresis of 15 20 V. Additionally, the on/off r atio of the BCB device under a reduced gate voltage scan range (Figure 4 4A) remains A B
85 larger than the bare oxide device (Figure 4 4 B ), and nearly as large as in the full range transfer scans of Figure 4 2. Conclu ding Remarks By effecting two simple modific ations to the CN VFET, the on/off ratio was increased, the hysteresis was significantly reduced, and a wider range of organic semiconductors were made available for use. Baking the CNT film modifies its workfunction increasing the on/off ratio by two order s of magnitude for a semiconductor that formed ohmic contact to unbaked nanotubes. Adding BCB beneath the CNT source reduced the hysteresis from 40 % (Chapter 3) to 3 % of the minimal V G scan range to switch the device between fully on and off states. Rem oval of the hysteresis is a major step forward for transistor applications of the CN VFET.
86 CH A PTER 5 HIGH CURRENT, LOW VO LTAGE CARBON NANOTUB E ENABLED VERTICAL ORGANIC FIELD EFFECT TRANSISTORS iv State of the art performance is demonstrated from a carbo n nanotube enabled vertical field effect transistor using an organic channel material. The device exhibits an on/off current ratio >10 5 for a gate voltage range of 4V with a current density output exceeding 50 mA/cm 2 The architecture enables sub micron ch annel lengths while avoiding high resolution patterning. The ability to drive high currents and inexpensive fabrication may provide the solution for the so called OLED backplane problem. Introduct ory Remarks In contrast to the transistors that drive the pixels of liquid crystal displays (LCDs), the transistors that drive the pixels in active matrix OLED (AMOLED) displays must source high currents. O rganic thin film transistors (TFTs) that operate with high output current s at low voltage s ha ve accordingly been a major research objective in recent years With in the constraint s of avoiding high resolution patterning ( to keep costs down ) and the limited carrier mobility of organic materials, these two requirements are difficult to achieve simultaneously The absence of an inexpensive solution for driving AMOLEDs has come to be called the OLED backplane problem. Besides ongoing efforts in the improvement of the charge transport properties of organic semiconductors, recent e fforts have focused on reduction of th e dielectric thickness and/or increasing the dielectric constant ( k ) of the gate insulator thereby increas ing the gate capacitance. Progress has been significant with groups exploiting gate capacitances ranging from 44 iv Reprinted with permission from M. A. McCarthy, B. Liu, and A. G. Rinzler, "High Current, Low V oltage Carbon Nanotube Enabled Vertical Organic Field Effect Transistors," Nano Letters, vol. 10, p. 3467, 2010.
87 to greater than 1100 nF/cm 2 TFTs emp loying a variety of active layers including pentacene [91 98], a side chain fluorinated fulleropyrrolidine (F17DOPF) , and phenyl C61 butyric acid methyl ester ( PCBM)  have been demonstrated, exhibiting on/off ratios of 10 4 to 10 6 at operating vol tages less than 5 V with output currents /mm of channel width. Recently Klauk and co workers, combining a gate capacitance of 8 00 nF/cm 2 with a recently developed air stable organic molecule (more below) demonstrated TFTs exhibiting state of the art performance: on/off ratios around 10 6 operating voltages less than 3 V and output currents of 17 channel width . Despite these advances, such output currents remain more than two orders of magnitude lower than those of polycrysta lline Si TFTs operating at less than 5 V . Competitiveness with poly Si is perhaps too much to expect of organic materials however there may be other ways to circumvent the comparatively low mobilities of the organics. A n architectural means to boost TFT currents is a transistor with a vertically oriented channel where the channel length is determined by the thickness of the semiconductor thin film layer This allows for sub micron channel lengths without the need for high resolution patterning Y ang a nd co workers demonstrated a vertical organic field effect transistor (VFET) based on a thin, partly oxidized Al source electrode using P3HT as the active layer and a LiF supercapacitor as the dielectric (with a gate 2 ). They achieved ~ 17 mA/cm 2 output current at less than 5 V operating voltages with on/off ratios on the scale of 10 3 However such devices require a humid environment for the LiF supercapacitor material to function . Other s have
88 also demonstrated VFET s of alternative [59, 60] and similar  designs, but these d id not exhibit low voltage operation. Recently we demonstrated a carbon nanotube enabled VFET (CN VFET). In this device the nanotubes are spread as a thin, percolating, source electrode layer across the gate dielectric; the nanotube layer is covered by the organic channel layer; which is in turn covered by the top drain electrode (Figure 5 1). Current modulation in our device relies on the gate field modulation of a Schottky barrier that develops between the n anotubes and the organic channel material. Because of bundled nanotubes in the source layer, p channel operation requires organic materials that form a barrier for hole injection greater than approximately 0.4 eV (e.g. for a nanotube workfunction of 4.9 e V the (highest occupied molecular orbital) HOMO level of the organic channel should be 5.3 eV or deeper) . Our initial demonstration of this architecture used organic channel layers having carrier mobilities far lower than typical organic TFT material s and a gate dielectric consisting of a 200 nm thick thermal oxide, possessing a capacitance of only 17 nF/cm 2 Nevertheless, the devices gave output currents of 3 mA/cm 2 at a drain voltage ( V D ) of only 5 V. Because of the low capacitance of the thick diel ectric layer, however, the devices required a gate voltage ( V G ) of 50 V for an on/off ratio of only 10 2 . Here we correct these deficiencies demonstrating a CN VFET employing a high carrier mobility organic channel layer fabricated on a thin dielectr ic with a capacitance of 354 nF/cm 2 These modifications yield devices that meet or exceed state of the art performance. Yamamoto and Takimiya recently reported their synthesis and application of an air stable small molecule with a high hole mobility: dina phtho [2,3 b:2 ,3 f ]thieno[3,2
89 b]thiophene (DNTT ). In conventional TFT devices on Si/SiO 2 substrates with an octadecyltrichlorosilane (OTS) self assembled monolayer (SAM), mobilities of 2.9 cm 2 /Vs were reported . The HOMO level of DNTT is at 5.4 eV. Compared to pentacene (HOMO level 5.0 eV ), the deeper HOMO of DNTT renders it air stable. Shown in Figure 5 1 is the molecular structure of DNTT. The air stability of DNTT vs pentacene in TFT devices has been investigated by Klauk and co workers. DN TT TFT devices retained 50 % of their initial performance after 8 months in air whereas pentacene devices degraded by more than an order of magnitude after only 3 months . This material combined with the 800 nF/cm 2 capacitance of a sub 6 nm bi layer Figure 5 1. Schematic of the CN VFET. The nanotube source electrode is depicted in is the wiring diagram for the device. When the drain voltage is negative, holes are injected from the nanotube source electrode (held at ground) into the semiconductor layer and travel in the vertical direction (arrows) to be carried out by the drain. Shown on the top is the molecular structure of DNTT. dielectric of aluminum oxide and a SAM yielded the record performance mentioned above [1 01].
90 The current in conventional lateral channel TFTs scales linearly with the length of the electrodes (the channel width). While the current in VFETs scales with the channel area, i.e. the area of the organic semiconductor sandwiched between the planar e lectrodes. To provide a figure of merit (FOM) that allows a direct comparison of the two types of devices we convert the linear current density of a TFT into an effective areal current density ( J Eff ). This is rationally done by assuming an interdigitated s ource drain electrode pattern where in the width of each source and drain finger is taken to be equal to the channel length of the TFT, thus preserving the resolution of the minimum feature size used for the channel. This interdigitated finger arrangement optimizes the areal usage for the lateral channel devices because every finger provides an electrode for the channel on each of its two sides (details for determination of J Eff for the lateral channel TFTs are provided in the Appendix D). The area occupied by the transistors is especially important in AMOLEDs where the drive transistor occupies pixel real estate and therefore reduces the OLED pixel aperture ratio (the fractional pixel area occupied by the OLED). Given that maximum on current for minimum dev ice area is desired, such on current/device area provides an important FOM beyond the comparison with VFETs. Using this FOM The 17 TFTs by Klauk and co workers translates to a J Eff of 28 mA/cm 2 , surpas sing the 17 mA/cm 2 of the VFET by Yang and co workers . Experimental Details Fabrication of the DNTT Based CN VFET Our device schematic is shown in Figure 5 1. The gate electrode was 60 nm of aluminum thermally evaporated onto glass substrates. An al uminum oxide dielectric layer was formed on the aluminum gate by O 2 plasma oxidation in a barrel asher, similar
91 to ref , but using longer times in the oxygen plasma to maximize the oxide thickness and thereby minimize leakage current. A thin hydrophob izing layer of a low k dielectric: benzocyclobutene (BCB) was diluted in trimethylbenzene and spin coated to a thickness of ~5 nm . The BCB layer was subsequently hard baked at 250C for 1 hour on a hotplate in an Ar glovebox where it cross links and becomes impervious to solvents. Contact to the CNT source layer was made by pre deposited Cr/Au (8/40 nm thick, respectively) source contacts. The dilute nanotube source layer was fabricated as described previously . Following nanotube layer depositio n the substrates were loaded into a dual Ar glovebox that contains separate organics and metals vacuum thermal evaporation systems permitting deposition of organic channel layers and metal contacts without exposure to ambient air. The substrates were baked on a hotplate in the glovebox at 225C for 1 hr, prior to deposition of DNTT (details on the effect of the bake in the Appendices A and C). DNTT was used as received from Nippon Kayaku Co., Ltd. It was thermally evaporated from an effusion cell at ~210 C at a growth rate of ~2.1 /s in a pressure of ~ 5.010 7 torr to a thickness of 480 nm. Substrates were subsequently transferred to the metals evaporator, where 30 nm of Au was deposited as the drain electrode. The Au deposition was through a TEM grid sha dow mask defining dozen s of individual, hexagonally shaped pixels with the size for each hexagon 2 ), completing the device construction. Optical Microphotographs of the CN VFET Devices
92 Figure 5 2A shows an optical image of the entire s ubstrate of the CN VFET devices. Outlined in red dotted lines are the CNT source electrodes which are too dilute Figure 5 2 A) Labeled full numerous distinct DNTT CN VFETs, defined by each hexagon al drain electrode. B) Zoomed in image showing the source, and gate contact probes as well as the drain contact to one CN VFET device. Images recorded in a microprobe station within the argon glovebox. A B
93 to be visible in the image. Au coated needle probes ar e used to make contact to the source and gate electrodes and an Au wire is used to make contact to the drain pixel as shown in Figure 5 2B. Metal Insulator Metal Capacitors for Al 2 O 3 Dielectric Evaluation To determine the quality and capacitance of our gat e dielectric layers metal insulator metal (MIM) capacitors were fabricated in a similar fashion except that the Au top contact was placed either directly onto the Al 2 O 3 dielectric layer or onto the BCB hydrophobizing layer. Capacitance vs. frequency curves were measured with an HP 4284A Precision LCR meter at a voltage amplitude of 100 mV. Results and Discussions Schematics of the test MIM capacitors are shown in Figures 5 3A and 5 3B. The capacitance showed little dependence on frequency (Figure 5 3C) as i s expected for the dielectrics used here. Adding an approximately 5 nm thick layer of BCB (as measured by AFM) to the Al 2 O 3 reduced the capacitance ( C ) from 1710 nF/cm 2 to 354 nF/cm 2 but improved the reliability sufficiently to warrant its use. The thickne ss ( d ) of the Al 2 O 3 was estimated from the capacitance of the bare Al 2 O 3 device using d = 0 /C assuming k = 9 , and was found to be ~4.8 nm. Figure 5 3D shows the typical leakage current density for an Al 2 O 3 and an Al 2 O 3 + BCB MIM device. Devices te nded to breakdown irreversibly once the leakage currents exceeded 3 1010 6 A/cm 2 so a gate leakage current of 210 6 A/cm 2 was selected as the upper limit for this gate dielectric in CN VFET testing. This corresponded to keeping the electric fields below 2 MV/cm, placing an upper limit of 2 V on the gate voltage. Figure 5 4A shows the transfer curves for a DNTT based CN VFET on the Al 2 O 3 /BCB dielectric at the drain voltages indicated. For the total gate voltage range of 4
94 V the device exhibits >10 5 on/of f ratio ( 0.1 V and 1.0 V drain voltage curves) or >10 4 on/off ratio ( 3 V drain voltage curve) with the latter attaining a fully on current density of 110 mA/cm 2 The output characteristics of the device are shown in Figure 5 4B for gate voltages ranging from +2 V to 2 V in 0.5 V steps. Figure 5 4C plots the on/off ratio (for V G = 2 V on, divided by V G = +2 V off) as a function of the on current density as V D was swept from 0 to 3 V. The on/off ratio of the device remains > 10 5 to 50 mA/cm 2 and is Fi gure 5 3 The MIM schematics for A) the bare Al 2 O 3 device and B) the Al 2 O 3 +BCB device. C) Capacitance vs. frequency plot for both MIM devices. D) The leakage current density vs. applied electric field. The leakage current density remains low below ~2 MV/cm applied field. A B C D
95 still above 10 4 to beyond 110 mA/cm 2 If this CN VFET were to drive an organic light emitting diode (OLED), of comparable size, with a luminance efficiency of 4 cd/A, at a drain current density ( J Drain ) of 25mA/cm 2 the luminance of the OL ED would be 1000 cd/m 2 which is 4 to 5 times brighter than a typical computer screen. What appears to be saturation in the two most on output curves ( V G = 1.5 V and V G = 2 V) of Figure 5 4B is distinct from the typical TFT saturation understood from th e gradual channel approximation . Its origin is rather explained by a voltage drop across the thin, resistive nanotube source electrode (10 15 k /sq sheet resistance) in the region between the pixel under test and the Au contact to the nanotubes, which was ~2 mm in these initial test devices. In the on state the current is limited by this resistance. With the Au source contact held at ground this resistance causes the nanotube source (in the region of the active pixel) to drift away from ground, reducing the gate voltage it sees, resulting in the apparent saturation. This series resistance is responsible for the roll off seen in the on/off ratio at high current densities (Figure 5 4C) and can be mitigated by minimizing the distance between the CN VFET pixel and its source contact. To obtain an initial sense of device to device uniformity 20 devices were characterized. Of these 20 devices, 10 shared one nanotube source electrode (CNT 1) and the other 10 shared a second, distinct, nanotube source electrode (CNT 2). Optical micro photographs of the devices are shown in Figure 5 2. Figure 5 5A overlays the transfer curves for the 20 devices and Figure 5 5B shows their on/off current ratio versus the on current density. The clear grouping of the data by the CNT electrodes suggest some variation in the nanotube source electrodes (perhaps in the nanotube
96 density, but further work is needed to understand th is). Statistics derived from these plots are shown in Table 1 (extraction of the threshold voltage is discussed below). The Figure 5 4 A) Transfer curves of the CN VFET at the indicated drain voltages. The curves show little hysteresis over the small ga te voltage range of 4 V. B) Output curves from V G = +2 V to 2 V in 0.5 V steps. C) On/off ratio as a function of the on current density, which stays above 10 5 to 50 mA/cm 2 B C A
97 standard deviation for the maximum drain current density is 7% while that for the threshold voltage is 2%. To investigate the effect of bias stress on a CN VFET, one device was cycled on and off, at a drain voltage of 1 V, 3000 times over a period of 7 hours (1 cycle every 8 seconds). Measurements were performed in an argon glovebox. Figures 5 5C and 5 5D show transfer curves for all 3000 scans (both scan directions) Figure 5 5. Uniformity (A and B) and stability (C F) of the devices. A) Transfer curves of 20 devices 10 on CNT 1 and 10 on CNT 2 source electrodes. B) On/off ratio of t he 20 devices. C) Stability of one CN VFET for 3000 transfer cycles over a period of 7 hours at V D = 1 V on a log linear plot. D) The same data on a linear linear plot. E) The on/off ratio from C) is increasing with cycling. F) The small drift in V Th from D) which appears to be saturating. A B C D E F
98 superimposed on a log linear and a linear linear scale, respectively. The on/off ratio increased slightly with cycle number during the 7 hour scan (Figure 5 5E), starting at 1.210 5 and ending at 1.810 5 Plotting the t ransfer data on a linear linear scale (Figure 5 5D) is useful for extracting the threshold voltage ( V Th ) in order to detect bias stress induced shifts (Figure 5 5F) and for assessing device to device uniformity (Table 1). For a conventional TFT the thresho ld voltage is calculated from a linear fit on an I D (1/2) vs. V G plot (based on the gradual channel approximation) and defined to be where the extracted regression line intersects the x axis. 23 Because the CN VFET is a Schottky barrier device, 17 the equati ons from the gradual channel approximation are not relevant. Instead, because the J Drain of the CN VFET follows a nearly linear dependence on V G in the on state, it is natural to extract V Th from the linear J Drain vs. V G plot (Figure 5 5D). During the cycl ing period, V Th shifts from 0.98 V to 1.02 V (Figure 5 5F). Table 5 1 Statistics for the 20 devices measured for uniformity in Figures 5 5 A and 5 5 B Each value is calculated from 10 individual devices sharing either CNT 1 source or CNT 2 source electr odes. Max J Drain (mA/cm 2 ) On/off ratio** V Th (V) SS slope (mV/dec) CNT 1 CNT 2 CNT 1 CNT 2 CNT 1 CNT 2 CNT 1 CNT 2 Avg 115 112 610 4 810 4 0.93 0.93 520 460 St. dev. 7 8 110 4 310 4 0.03 0.01 30 10 *at V D = 3.0 V, and V G = 2.0 V **at 25 mA/cm 2 on current density Conclu ding Remarks Table 2 compares the performance of state of the art, organic channel devices reported in the literature for which the criteria for inclusion were low resolution patterning (channel lengths >25 m for TFTs to preserve inexpensive manufacturing), p type channel materials (for greater air stability), on/off ratios for the TFTs > 10 4 operating voltages < 5V, and effective current densities ( J eff ) > 1 mA/cm 2 The CN VFET
99 achieves its low operating v oltage despite the comparatively modest gate capacitance, which bodes well for device reliability. The output current density of the CN VFET exceeds even the best of the other devices by a factor of 3.9. This excess current handling capacity is important f or driving the high currents required by OLED pixels. Moreover, to achieve their highest effective current densities, the TFT devices required patterning that approached the smallest feature size for inclusion in the Table (25 m). The minimum patterned feature size of the CN VFET in these studies was 200 m (the drain electrode). These results are from the initial set of devices made with the Al 2 O 3 gate dielectric and BCB, so we anticipate significant room for further optimizat ion. Additional advantages of the nanotube source electrode include imperviousness to electromigration (a potential lifetime limiting mechanism with other source electrodes) and the transparency of the thin nanotube source layer (> 98% transmittance), whic h lends itself to the construction of a light emitting transistor . Based on these results we contend that the CN VFET, requiring only materials available today, is in a promising position to solve the OLED backplane problem, accelerating the energy sa ving evolution from LCD to OLED display technology.
100 Table 5 2. Comparison of the CN VFET to the highest performance, low patterning resolution devices reported. Low patterning resolution is here defined as channel lengths > 25 m (for the TFTs). Other cr iteria for inclusion were p type devices for air stability, on/off ratios (for the TFTs) > 10 4 operating voltages < 5 V and effective current densities ( J eff ) > 1 mA/cm 2 Reference Device type Material Oper. V (V) I ON / I OFF SS slope (mV/ dec) Channel L ( m) J eff (mA/cm 2 ) Gate cap (nF/cm 2 )  TFT DNTT 3 10 6 100 30 28 800  TFT Pentacene 2 10 5 78 80 1.3 950  TFT Pentacene 5 10 5 317 70 1.1 76  TFT Pentacene 2 10 4 160 25 2.8 1100  VFET Pentacene 4 10 4 500 a 0.12 80 b 2000 c This work VFET DNTT 4 10 5 500 0.6 110 354 a estimated from output data (transfer data not shown) b at same voltages as the CN VFET, i.e. V D = 3 V, and total V G range of 4 V c capacitance at 20 Hz; the capacitance drops steadily as the frequency is increased and is ~50% o f the initial value at ~2 kHz
101 CHAPTER 6 REORIENTATION OF THE HIGH MOBILITY PLANE IN PENTACENE BASED CARBON NANOTUBE ENAB LED VERTICAL FIELD E FFECT TRANSISTORS v The large current densities attained by carbon nanotube enabled vertical field effect transistors using crystalline organic channel materials are somewhat unexpected given the known large anisotropy in the mobility of crystalline organics and their conventional ordering on dielectric surfaces which tends to orient their high mobility axes parallel to the surface. This seeming contradiction is resolved by the finding that the nanotubes induce a molecular ordering that reorients the high mobility axes to favor current flow in a direction perpendicular to the substrate surface. Introduct ory Remarks The c rystallographic stacking of organic molecules often leads to anisotropy in the electronic properties of their films which can differ by orders of magnitude along distinct crystallographic directions . The exceptional performance of pentacene in latera l channel thin film transistors owes much to a fortuitous crystallographic orientation that places its high mobility a b stacking plane parallel to the gate dielectric surface, which is also the plane in which the current must flow between the source and d rain electrodes. The mobility of pentacene in a direction perpendicular to this plane is known to be orders of magnitude lower [110 112]. Accordingly it would seem that pentacene and analogous molecules with similar stacking would be poor candidates for ve rtical field effect transistors where the source drain current must flow in a direction perpendicular to the dielectric surface. v Reprinted with permission from M. A. McCarthy, B. Liu, R. Jayaraman, S. M. Gilbert, D. Y. Kim, F. So, and A. G. Rinzler, "Reorientation of th e High Mobility Plane in Pentacene Based Carbon Nanotube Enabled Vertical Field Effect Transistors," ACS Nano, In Press.
102 Nevertheless, we recently demonstrated record high on state current densities in a carbon nanotube enabled vertical field effe ct transistor (CN VFET) employing dinaphtho thieno thiophene (DNTT ) as the organic channel . DNTT has a molecular shape, stacking and crystallographic orientation on dielectrics that is quite similar to that of pentacene [101, 105]. A high current den sity, at low source drain voltage, is anticipated for the CN VFET architecture because the channel length between the vertically stacked source and drain electrodes is just the thickness of the thin film organic layer between them (Figure 6 1): and indeed, the on state currents scaled approximately as anticipated for a simple reduction in the channel length compared to the much longer channel lengths of conventional lateral channel DNTT based FETs. Such simple scaling however ignores the anisotropy in the e lectronic properties expected from the crystallographic orientation of the DNTT molecules on dielectrics. Figure 6 1. Schematic of the CN VFET with arrows depicting the direction holes flow in the on state of the device.
103 This result suggested that the s ingle wall carbon nanotube (CNT) source electrode, despite possessing only a dilute coverage of the dielectric substrate, reoriented the crystallographic axes of DNTT to force the high mobility a b plane to lie near vertical. Since conjugated organic molec ules are known to pi stack on graphitic surfaces [114, 115], and are suggested to do so on carbon nanotubes , such reorientation of the initially deposited molecules, nucleating a near vertical reorientation of the a b plane, at least over the nanotub es, seems plausible. Here we demonstrate pentacene based CN VFETs that similarly exhibit very high on state currents. By X Ray diffraction, atomic force microscopy and mobility measurements we provide conclusive evidence that the nanotubes induce a reorien tation of the pentacene a b plane to the near vertical direction. Such reorientation further explains the high current densities afforded by the CN simple channel length scaling agrees with the measured current output. Experimental Details CN VFET Samples Carbon nanotube enabled vertical field effect transistors (CN VFETs) were fabricated atop heavily p doped Si substrates with a thermally grown 200 nm SiO 2 dielectric. Figure 6 1 shows the devi ce schematic. The low k spin on polymer benzocyclobutene (BCB) was diluted in trimethylbenzene and spin coated at 3000 rpm for 45 s inside an argon glovebox. It was soft baked at 100 C for 20 min and hard baked at 250 C for 1 hr. After the hard bake BCB cross links and becomes insoluble to the subsequent solvents used in the transfer of the single wall carbon nanotube (CNT) source electrode. The thickness of BCB was ~ 10 nm. A Cr/Au (10nm/50nm, respectively) source contact electrode was deposited on the B CB in vacuum at
104 ~ 810 7 torr, at 2.0 /s. Using the Cr/Au source contacts for alignment, a prefabricated dilute CNT network was transferred (as described previously)  to the substrate overlapping the BCB as well as the Cr/Au contact. Following CNT net work transfer, the network was baked in an Ar glovebox at 225 C for 1 hr. From this point forward through electrical characterization, the device stayed in the Ar glovebox and was not exposed to the ambient. Pentacene was deposited on the CNT film, define d by a shadow mask, in a vacuum chamber at ~ 310 7 torr at a rate of 2.75 /s to a thickness of 350 nm with the substrate at room temperature. The sample was transferred to a separate vacuum chamber for deposition of the Au drain electrode. Following depo sition of the drain electrode, indium dot gate contacts were pressed in place. A diamond scribe is used to scratch through the SiO 2 /BCB dielectric layers prior to pressing on the indium to allow contact to the silicon gate. CN VFET devices were electrical ly measured with a homebuilt probestation inside the same Ar glovebox they were fabricated in. Transistor output and transfer data were recorded with a two channel Keithley 2612A System Sourcemeter controlled by a program written in LabVIEW. X ray Diffract ion Samples and Sandwich Type Hole Only Devices For the non ITO containing samples, glass microscope slides were diced and cleaned before deposition of the next layer. For the BCB coated samples, BCB was deposited and cured the same way as in the CN VFET. For the ITO samples, 5 15 ohm/ ITO on glass from Delta Technologies was cleaned and diced before deposition of the subsequent layers. Chromium/Au contact electrodes (10nm/50nm, respectively) were deposited, by the same method as the CN VFET, onto the ITO of the three sandwich type dev ices. An ultraviolet (UV) ozone treatment for 20 min was carried out
105 on the bare ITO samples. For the dilute CNT network on BCB/glass sample and the dilute CNT network on ITO, a dilute CNT network with the same number density of CNTs/area as in the CN VFET was transferred to the sample by the same method mentioned above. On the 45 nm CNT film on glass sample and the 45 nm CNT film on ITO, a 45 nm CNT film was transferred the same way as above. The dilute CNT network and 45 nm CNT film were deposited overlap ping the Cr/Au ITO contacts and extending over the bare ITO in the area beneath where the subsequent pentacene and Au layers lie. On the three sandwich type devices, 8 nm of pentacene doped with 1 vol % tetrafluorotetracyanoquinodimethane (F4 TCNQ) was dep osited immediately following the UV ozone treatment of the bare ITO device. The doped layer was deposited by co deposition at a chamber pressure of ~ 3 10 7 torr on a room temperature substrate with a pentacene growth rate of 1 /s and an F4 TCNQ growth r ate of 0.01 /s. After the doped layer was deposited, the 5 XRD samples were loaded into the deposition chamber and the neat pentacene layer was deposited on all 8 samples simultaneously to a thickness of 560 nm at a chamber pressure of ~ 3 10 7 torr on a room temperature substrate. After the pentacene deposition, a 50 nm Au shadow mask patterned top contact with the same size and shape as the CN VFET drain contact. XRD samples were measured with a Philips APD 3720 operated in /2 mode (Cu K = 1.541 ). Continuous scans from 2 = 5 to 2 = 30 in increments of 0.02 with a 4 second integration time were taken on all samples. Also taken was a scan of a 45 nm CNT film on glass without pentacene, which showed no peaks, and a bare
106 ITO/glass sample without pentacene which showed the (211) peak associated ITO (data of neither sample shown). Sandwich type hole only devices were exposed to the ambient environment for 30 min before being electrically measured in the same environmen t current density vs. voltage. ( J V ) data was recorded with a Keithley 2612A System Sourcemeter controlled by a program written in LabVIEW. Metal Insulator Metal Capacitors Figure 6 2. Optical microphotograph of the Al/pentace ne/Al capacitors. A gold coated needle is used to make contact to the bottom Al electrode. A soft gold wire is used to make contact to the small and medium sized top circular Al electrodes.
107 Glass microscope slides were diced and cleaned and served as the s ubstrates for the metal insulator metal capacitors. The bottom and top electrodes were 60 nm of thermally evaporated Al patterned through a shadow mask. After deposition of the bottom electrode, without exposing to the ambient, pentacene was grown to 165 n m on one substrate and 330 nm on another. Pentacene was deposited at 2.6 /s at a pressure of ~3 10 7 torr Circular shaped top electrodes were defined in two diameters, 0.86 mm and 1.3 mm (optical microphotograph shown in Figure 6 2). Results and Discussi ons Figure 6 1 shows the structure of the CN VFET. The CN VFET uses a bottom gate architecture and functions as a schottky barrier transistor, where the height and width of the barrier for injecting holes from the CNT source into the pentacene layer are m odulated by the gate electric field . A thin (10 nm) hydrophobizing layer of cross linked benzocyclobutene (BCB) deposited on the silicon dioxide dielectric improves device performance [79, 90]. Figure 6 3A shows the transfer characteristics for the device. With negative gate voltage the hole injection barrier height and width are reduced allowing the drain current density to reach 2.3 mA/cm 2 at a drain voltage (relative to the grounded nanotube source electrode) of only 0.32 V. Upon sweeping the gat e voltage toward 0 V the device turns off. The relatively large gate voltage required to switch the current between the on and off state is due to the thick 200 nm SiO 2 gate dielectric used here. CN VFETs exploiting a thin, high k dielectric, switching com parable current densities for a gate voltage range of only 2 V have recently been demonstrated . The hysteresis seen in the transfer curve is due to charge traps and is virtually eliminated by limiting the gate voltage sweep range . Figure 6 3B shows the output characteristics for the
108 Figure 6 3. A) Transfer curve of the CN VFET with pentacene as the semiconductor layer shows a small amount of hysteresis over a gate voltage range of 60 V, with a SS slope of 3 .3 V/dec B) Output curves from V G = 2 0 V to 40 V in 20 V steps C) On/off ratio as a function of on current density stays above 10 4 past 225 mA/cm 2 with a peak above 10 5 at ~20 mA/cm 2 A B C
109 device. The drain current is ~225 mA/cm 2 at a drain voltage of 3 V. On the basis of the area occupied by the devices this current density approaches an order of magnitude larger current per unit device area than a recent state of the art TFT operating at a similar drain voltage [101, 113]. Figure 6 3C plots the on/off ratio versus the on state current densit y as the drain voltage changes from 0 to 3 V. The on/off ratio hovers around 10 5 to current densities of ~50 mA/cm 2 and remains above 10 4 to 225 mA/cm 2 Figure 6 4 The crystal structure of pentacene. The a b plane orients itself parallel to the oxide s urface. A) The herringbone packing arrangement of pentacene viewed from the direction perpendicular to the a b plane. B) The b axis projection showing the slight tilt of the molecules as well as the (001) inter planar spacing (d (001) ). A B
110 Figure 6 4A shows th e herringbone molecular ordering for crystalline pentacene looking along the direction perpendicular the (001) plane. Equivalent layers of molecules lie above and below the layer shown. The mobility along this direction is reported to be orders of magnitud e lower than that along directions within the a b plane (coplanar with (001)) [110 112]. The mobility also varies within the a b plane, however the ratio between the in plane highest and lowest mobilities is only 3.5 . When grown on dielectric surface s the molecules tend to assume the nearly upright orientation that places the (001) planes parallel to the surface (Figure 6 4B shows the b axis projection). This crystalline orientation is in contrast to pentacene deposited onto smooth gold and highly ord ered pyrolytic graphite where the initially deposited molecules tend to lie flat, with subsequent layers assuming the herringbone stacking that orients the high mobility a b plane to lie nearly perpendicular to the surface [115, 118, 119] To probe the cr ystalline orientation of pentacene grown on dilute nanotube networks on BCB (at a surface density relevant to CN VFETs) we acquired 2 X ray diffraction data and atomic force microscopy (AFM) images for 560 nm of pentacene grown on three types of samples: 1) bare 10 nm thick BCB on glass; 2) dilute nanotube networks on BCB (10 nm) on glass and; 3) 45 nm thick nanotube films on glass, in which case the thick nanotube film provides no line of sight access for the evaporated pentacene to the underlying glass. The pentacene was deposited on the samples during the same growth run under similar conditions used in fabrication of the CN VFET (growth rate 1 /s, pressure ~3 10 7 torr room temperature substrate).
111 Figure 6 5 shows the 2 X ray diffraction plots for these samples. The pentacene on BCB XRD curve (bottom) shows clear pairs of (001), (002), (003) and (004) plane reflections. In each pair, the left peak is from the thin film pentacene phase and the right peak is from the b ulk phase. These are consistent with the a b plane parallel to the BCB surface. The pentacene on the 45 nm thick CNT film in contrast shows none of these reflections but rather only peaks at 19.3, 24.1 and 28.3 corresponding to (110), (022) and ( 201) p lane reflections consistent with the a b plane lying nearly perpendicular to the surface. The 2 plot of the pentacene on the dilute CNT network shares reflections from both of these cases indicating a mixed orientation of the crystallites. Taken together these results confirm the idea that the nanotubes nucleate a reorientation of the pentacene a b plane to lie near perpendicular to the substrate surface in the vicinity of the nanotubes. Figure 6 5 X ray diffraction data taken in /2 mode of pentacene grown on the surfaces labeled next to each curve
112 line axes on the nanotubes has dramatic effects on the pentacene layer morphology. Figure 6 6A shows an AFM image of the dilute nanotubes on BCB/glass at the surface density used in the CN VFET and in these studies. Figures 6 6 B D show AFM images of pentac ene grown on the samples discussed above: 6 6 B pentacene on bare BCB/glass; 6 6 C pentacene on the dilute CNT/BCB/glass and; 6 6D pentacene on the 45 nm thick CNT film on glass. Also shown is the root mean square (RMS) surface roughness measured for ea ch sample. Dramatic difference between the crystallite morphology of pentacene on the bare BCB and the two nanotube samples is evident from these images and mirrored in the surface roughness. While the X Ray data evidenced regions of (001) plane crystallit es in the dilute nanotube film sample, these crystalline grains are evidently kept much smaller by their confinement between the nanotube nucleated grains (Figure 6 6C) than appear on the bare BCB sample (Figure 6 6B). Figure 6 7 illustrates a plausible molecular packing of pentacene, to scale, on the CNTs and the nearby BCB surface consistent with its ordering on graphite  and our XRD data. How, precisely, the pentacene orders in going around the nanotube bundle shown goes beyond the scope of this i nvestigation. The average bundle diameter in our material  is ~5 nm which correlates with the 7 hexagonal close packed nanotubes having individual diameters of ~1.4 nm drawn with a 1.7 nm center to center distance. From this confirmation that the nano tubes reorient the a b plane to lie near perpendicular to the substrate we can only infer that pentacene has high mobility in a direction perpendicular to the substrate (the direction of current flow) in the CN VFET. Therefore, a direct measure of the pen tacene mobility in this direction, with and without
113 the nanotubes is desirable. A method to estimate the mobility of a thin film organic layer in the direction perpendicular to the layer is by measuring and fitting J V curves at high fields in a sandwich t ype, single carrier, metal semiconductor metal (MSM) device to the Mott Gurney equation. This equation assumes ohmic injection and that the current Figure 6 6 AFM micrographs of A) a dilute CNT network on BCB/glass, B) pentacene on BCB/glass, C) pentace ne on a dilute CNT network on BCB and D) pentacene on 45 nm thick CNT film on glass. Pentacene was thermally evaporated to a thickness of 560 nm at 1 /s with the substrate at room temperature at a pressure ~3 10 7 torr A D C B
1 14 density has saturated to the space c harge limited (SCL) regime, where J V 2 The CN VFET forms such a sandwich type device. At the extreme gate voltage, where the injection barrier is minimized and the injection is most nearly ohmic we looked for a V 2 dependence for J Dra in However, as seen in the output curve of Figure 6 3B where V G = 40 V, at the higher drain voltages, J Drain saturates to a linear dependence on V D Calculating the series resistance that the slope there implies gives ~24 kohms which is close to the seri es resistance of the CNT electrode in the region between the CN VFET element under test and its remote (~2mm distant) Au source contact. This series resistance precludes extraction of the mobility by use of the Mott Gurney equation directly from CN VFET de vices. The series resistance of a remote contact to the nanotubes can be avoided if the dilute nanotube film were deposited directly onto a conductor and if this composite electrode formed one side of the M SM (M = composite electrode, S = pentacene, M= Au ) structure for the J V measurement. For such a measurement to have relevance to the mobility of the pentacene in the crystalline orientation that it assumes in the CN VFET, however, two issues must be addressed. Firstly, the pentacene must orient on the b are conductor in the same orientation it assumes on oxide, and other, dielectrics (i.e. with its a b plane parallel to the surface). Gold, which does not generally yield such an orientation, is precluded, but indium tin oxide (ITO), being both conductive a nd an oxide, came to mind as a potentially suitable candidate electrode. Below we provide X ray diffraction data showing that pentacene on bare UV Ozone treated ITO indeed assumes the needed crystalline orientation (a b plane parallel to the surface). Thus ITO can act as the surrogate for the dielectric layer (in the sense of the pentacene crystalline
115 orientation) in an M SM device permitting comparison between the mobility in a direction perpendicular to the pentacene layer, both with and without the nanot ubes present. The second issue that must be addressed in such an experiment is the Schottky barrier that develops between the pentacene and the electrode. In the MSM configuration there is no gate field available to reduce this barrier, but application of the Mott Gurney expression requires near Ohmic injection (the barrier must be small enough to allow the current to be space charge limited rather than barrier limited at the voltages used to fit the V 2 dependence). It has been shown that barriers for injec ting holes into organic semiconductors can be minimized by a dilute Figure 6 7. Scale model depicting the mixed orientation crystallites on the CNT bundle and partially covered BCB surface. Left a b plane parallel to the surface for pentacene grains nu cleated on BCB. Right the a b plane along the near vertical direction for pentacene grains nucleated on a bundle of (10,10) nanotubes.
116 tetrafluorotetracyanoquinodimethane (F4 TCNQ) doping of the organic in a thin interfacial layer between the electrode a nd the rest of the undoped organic layer . Since such doping may also modify the crystalline orientation of the pentacene on the ITO it must be confirmed that it does not do so. This then formed our strategy for the experiments performed and the data that follows: 1) Confirm by XRD that pentacene deposited on ITO with the first 8 nm doped by F4 TCNQ results in a crystalline orientation that places the pentacene a b plane parallel to the surface. 2) Confirm by XRD that a dilute nanotube layer on the ITO induces the crystalline reorientation of the pentacene (with 8 nm F4 TCNQ doped interfacial layer) over the nanotubes generating the mixed grain orientations. 3) Compare the surface morphology of these samples by AFM. 4) Construct M SM samples where M = bare ITO or ITO with a dilute nanotube layer, S = pentacene in which the first 8 nm are 1% F4 TCNQ doped and M = Au. 5) Measure the J V curves for these samples and look at high fields for a V 2 dependence to fit the mobilities using the Mott Gurney equatio n. Figure 6 8A shows the XRD data for the pentacene/ITO and pentacene/nanotube/ITO samples. Figures 6 8B and 6 8C show AFM images of these respective samples providing their surface morphology and RMS roughness. From the X ray data of the pentacene on bare ITO we find only peaks consistent with the a b plane lying parallel to the surface. The pentacene on nanotube/ITO sample in contrast shows the expected mixed phase. The pentacene crystalline grains on ITO (Figure 6 8B) are much smaller than they are on BC B (Figure 6 6B), though, the surface
117 Figure 6 8 A) X ray diffraction data taken in /2 mode of pentacene grown on the surfaces labeled next to each curve AFM micrographs of B) pentacene on ITO and C) pentacene on a dilute CNT network on ITO. Pentacene was thermally evaporated to a thickness of 560 nm at 1 /s on a room temperature substrate at a pressure ~3 10 7 torr A B C
118 roughness is comparable. This could be due to the microcrystalline nature of the underlying ITO (note the ITO (211) reflection  in the XRD data) compared to the amorphous nature of the much smoother underlying BCB (BCB RMS roughness was < 0.5 nm compared to 4.5 nm for the ITO, as measured by AFM, images not shown). The morphology of the pentacene on the nanotube/ITO sample (Figure 6 8C) and its RMS surface roughness, however, are quite similar to those of pentacene on the nanotube/BCB sample (Figure 6 6C). Figure 6 9 Schematics of the pentacene M SM hole only devices fabricated for measurement of SCL A) Pentacene on ITO device an d B) pentacene on dilute CNT/ITO device. C) J V curves of the three devices. The mobility values in the lower right corner of C) are extracted from fitting Eq. 1 to the J V curves shown. Both devices follow a V 2 dependence as indicated by the V 2 referenc e line in C) A B C
119 Figures 6 9A and 6 9B illustrate the two types of M*SM (M* = bare ITO or nanotubes on ITO) devices studied and Figure 6 9C compares the J V (log log) plots for the two types of devices. Also shown in Figure 6 9C is a line for which J V 2 At t he larger applied voltages the data clearly follow a V 2 dependence indicating the applicability of the Mott Gurney expression. In the trap free limit for SCL current density this equation is Eq. 1 where r is the relative perm ittivity, SCL the SCL mobility, V the applied voltage and L the thickness of the semiconductor layer. To determine SCL the relative permittivity of pentacene must be determined. Values cited in the literature range from 3.7 to 6 [121 123]. To obtain a m ore precise value (relevant to pentacene grown under our conditions) we fabricated parallel plate capacitors using aluminum electrodes and pentacene as the sandwiched dielectric. Al was chosen because its workfunction relative to the transport levels of pe ntacene renders it a non injecting electrode. Figure 6 10 shows capacitance plotted vs. the area of the top electrode. R p the data were forced through the origin. The slopes give the areal capacitance for the two thicknesses used. The 165 nm thick pentacene capacitor had an areal capacitance of 14.1 0.3 nF/cm 2 an d the 330 nm thick capacitor, 29.5 0.6 nF/cm 2 Using the expression for capacitance, Eq. 2 where A is the top electrode area and d the thickness of the pentacene layer, the
120 relative permittivity r can be estimated. The r esults give r 5.4 0.3 in good agreement with the values in the literature cited above. With this information, fits of Eq. 1 to the J V plots in Figure 6 9C at the higher voltages yields mobilities, in a direction perpendicular to the substrate, of 0.0052 cm 2 /(V s) for the pentacene on ITO (pentacene a b plane parallel to substrate) and 0.12 cm 2 /(V s) for the pentacene on nanotubes/ITO (pentacene a b plane grains both parallel and perpendicular to the substrate). Thus, for a pentac ene film on a substrate that normally takes on a crystalline orientation having its a b plane parallel to the Figure 6 10. Capacitance vs area for each of the thicknesses of the pentacene layer used in Al/pentacene/Al MIM devices. Linear fits are forced t hrough the origin. The slope gives the estimated areal capacitance in units of nF/cm 2 substrate, the mobility in a direction perpendicular to the substrate is 23 times greater in the presence of nanotubes (at the density used in the CN VFET), than without the nanotubes, and this difference is directly attributable to the reorientation of the pentacene crystalline orientation induced by the nanotubes. Such a difference in the mobility is less than the factors of 450 and 160 attributed to the mobility anisot ropy of
121 single crystal pentacene along the b vs. c axis and a vs. c axis, respectively , but this is readily explained by the orientationally mixed phase on the nanotube sample. Conclu ding Remarks Hence in addition to its short channel length, the ver y high on state currents seen in the pentacene based CN VFET can be (partially) attributed to a reorientation of the pentacene crystalline axes to a direction that is advantageous to the device architecture. Since as a general rule for planar crystalline o rganic molecules, the high mobility direction lies along the direction in which the molecules pi stack, such advantageous reorientation should occur for most planar organics used as the channel material in the CN VFET.
122 CHAPTER 7 CONCLUSIONS Carbon nanotub e enabled vertical organic field effect, transistors (CN VFET) and light emitting transistors (CN VOLETs) have been demonstrated. The key component of the CN VOLET, the CN VFET, was optimized to demonstrate a level of performance that makes it a viable can didate for solving the AMOLED backplane problem. In this chapter, the results of this dissertation are summarized and concluded. Proof of principle operation was demonstrated in CN VFET and CN VOLET devices. The low density of electronic states of CNTs all ows their Fermi level to be readily modified in response to the electric field from a nearby insulated gate electrode. With facile gate control of the nanotube Fermi level, the Schottky barrier height as well as its width can be modulated by the gate volta ge (the former, a phenomenon not previously reported in metal semiconductor contacts). This Schottky barrier control confines the gating to the interfacial region between the nanotubes and the organic, permitting the vertical orientation of the channel. In this architecture, the channel length is readily defined by the thickness of the deposited organic thin film. This allows sub micron channel lengths to be achieved without the expense of high resolution patterning. Additionally, the passivated surface of CNTs frees them from formation of interface states between materials placed in contact with them, further enhancing the Schottky barrier control by the gate . Following the first demonstration reported in 2008, a combination of refinements and new deve lopments greatly improved the performance of the CN VFET. Through the addition of a hydrophobizing surface layer on the silicon dioxide dielectric, the CN VFET could be operated nearly hysteresis free; important if it is to serve as the driving
123 transistor in AMOLED display backplanes. Additionally, through baking, the CNT Fermi level can be modified prior to deposition of the organic semiconductor layer enabling the use of a wider range of organic semiconductors, as demonstrated by the use of pentacene. Wit h these treatments, the on/off ratio was improved by two orders of magnitude, to 10 4 over the initial devices. To reduce the operating voltages of the CN VFET over the initial devices, two modifications were made. To reduce the gate voltage, a thinner dielectric with higher dielectric constant than silicon dioxide was used. To reduce the drain voltage, an organic material with a higher mobility was employed as the semiconductor layer. Substantial improvement was realized after these modifications. The g ate voltage range went from 50 V to 2 V. And at 3 V on the drain, the on current density was measured to be higher than any other low resolution patterned organic transistor in the literature by a factor of 3.9. The first uniformity and stability measu rements on devices not optimized for these specific characteristics gave results that were very promising This high current low voltage implementation of the CN VFET could provide the solution to the AMOLED backplane problem. Additional experiments were p erformed that provided further insight into the high currents demonstrated in Chapter 5. The pi conjugated surface of CNTs induces a preferential orientation of planar organic small molecules that are deposited on top of the CNT source. Experiments were pe rformed with pentacene, an organic semiconductor known to have a highly anisotropic mobility among various directions in its crystal lattice. The horizontal orientation of the high mobility direction for pentacene typically observed on dielectrics, while b eneficial for conventional thin film transistors,
124 would not have been ideal for the CN VFET. However, due to the similarities in the molecular structure between pentacene and CNTs, the pentacene crystallites reorient 90 degrees when grown on CNTs, placing their high mobility direction near vertical. This was confirmed by x ray diffraction. And current voltage measurements did indeed reflect a higher mobility in the vertical direction in polycrystalline thin films of pentacene grown on CNTs. To conclude, a new type of transistor was described, greatly optimized and characterized. The high current drive capability afforded by this device could provide the solution to the AMOLED backplane problem. Work toward that end continues.
125 APPENDIX A DE DOPING NANOTUBES THROUGH BAKING The single wall carbon nanotubes used in these devices are charge transfer doped by their nitric acid purification. This p dopes the nanotubes pushing their workfunction to ~ 4.9 eV. Baking the nanotubes desorbs the charge transfer dopant shifting their Fermi level back toward their intrinsic workfunction of ~ 4.6 eV . The starting workfunction difference between the nanotubes and the organic layer dictates the initial magnitude of the Schottky barrier, establishing the baseline barrie r that is modulated by the gate. Figures A 1A and A 1B depict the workfunction of the unbaked CNTs (black line) with respect to an organic layer forming a negligible initial barrier with CNTs (Figure A 1A) and one forming a non negligible initial barrier w ith CNTs (Figure A 1B). Through baking of the CNT network at the temperatures and times listed in Figure A 1C the Fermi level shifts turning an initially ohmic contact into a schottky barrier contact (Figure A 1A) or making the barrier of an initial schott ky contact even larger (Figure A 1B). To verify that baking the CNT networks on a hot plate in the Ar glovebox can de dope the nanotubes, films of the same nanotube density as used in the CN VFET were transferred to 3 glass slides. The films were squares of 1 cm sides with gold electrodes touching the four corners of the films (for 4 terminal Van der Pauw measurement determination of the film sheet resistance). One of the samples was an unbaked control sample, while the other two were baked for an hour in the Ar glove box, one at 200C and the other at 300C. Ultraviolet visible near infrared (UV VIS NIR) transmission spectra were taken over a wavelength range of 350 nm through 2100 nm. Figure A1 C shows the VIS NIR spectra for the three samples and also li sts the sheet resistance of the associated film. The changes in depth of the S1 & S2 dips in the
126 transmission along with the changes in the sheet resistance are clear signatures of effective dedoping with increasing temperature, understood on the basis of shifts in the nanotube Fermi level . Figure A 1. (A and B) Schematics showing the expected position of the nanotube Fermi level for the control (black line), 200C 1hr baked (red line) and 300C 1hr baked (blue line) films with respect to an organic semiconductor forming an initial ohmic contact A) with CNTs and to one forming an initial schottky contact to CNTs B) C) Transmission spectra of dilute CNT networks baked at the temperatures indicated. Inset in C) is the measured sheet resistances of eac h corresponding CNT network. A B C
127 APPENDIX B COMPOSITION OF CNT N ETWORKS UNDER STUDY The CNTs used in this study were grown by pulsed laser vaporization in the Smalley lab and purified in the Rinzler lab as described in ref . Once purified the material is then deposited on mixed cellulose ester (MCE) membranes by vacuum filtration as described in ref . Triton X 100 surfactant in aqueous solution is used to suspend the nanotubes in the pre filtered solution. After collection onto the MCE membrane, de io nized water is used to wash away the residual Triton X 100 surfactant from the nanotubes. This membane/nanotube sheet is then applied nanotube side down to the substrate with moisture. When the moisture has dried away the van der waals bonds between the CN Ts and the substrate hold the CNT network in place while the MCE membrane is subsequently dissolved away in an acetone vapor bath. AFM analysis is used to map out the morphology of the CNT network. The thickness of the CNT network is determined by the amou nt of material filtered through the MCE membrane. Figure B 1 shows a dilute CNT network (Figure B 1A) and 50 nm thick film (Figure B 1B). The thickness of the 50 nm film was determined by AFM stepheight analysis. The thickness of the dilute network film wa s not measured by AFM, but estimated by the relative amount of material used to make it compared to the 50 nm film. 1/25 of the CNT material to make the 50 nm film was used to make the dilute The compositi on of the CNT networks are of individual nanotubes bundled Nanotube bundle diameters are f ound by individually measuring the bundle heights relative to the substrate along sec tions of the bundle which are not overlapping other
128 bundles Figure B 2 shows the distribution of bundle diameters in the dilute nanotube network. The main distribution ranges from 1 nm to 9 nm with an average of 5 nm with outliers out to 20 nm. The diamet ers of the individual nanotubes are known to be centered around 1.4 nm , and the known center to center spacing in the bundle is 1.7 nm . With seven hexagonally close packed 1.4 nm diameter CNTs spaced by the cited center to center distance, the calculated diameter is 4.8 nm, in good agreement with the measured average bundle diameter. A scale drawing of a bundle of this kind with seven (10,10) CNTs is shown in Figure B 3. AutoCAD was used for the drawing. Figure B 1. AFM image of a 2 nm (also known as the dilute CNT nanotube network) and a 50 nm thick CNT film The thickness of the 50nm film was determined by an AFM step height 1/25 th of the material in a 50 nm film was used to (the film used in the CN VFET) A B
129 Figure B 2 Histogram of the bundle diameter distribution of the 2 nm thick dilute CNT network from Figure B 1A. Figure B 3 Scale model of a bundle of (10,10) nanotu bes drawn in AutoCAD with a 5 nm diameter reference circle (dashed line). 5 nm diameter
130 APPENDIX C EFFECT OF BAK ING THE CNT SOURCE E LECTRODE ON THE DNTT BASED CN VFET Figure 5 4 of Chapter 5 shows the transconductance data for the CN VFET in which the nanotube film was baked in the glovebox at 225 o C for an hour prior to deposition of the DNTT. Figure C 1 compares th e transfer curves for a CN VFET that did not have such a de doping bake with one that did. The device data in Figure C 1 were from devices fabricated the same way as in Chapter 5 except that the DNTT layer was 570 nm thick (as opposed to the 480 nm in Chap ter 5). That the unbaked (doped with the deeper workfunction of the doped nanotubes, possessing a smaller initial Schottky barrier with the DNTT. For a conventional tra nsistor the larger subthreshold slope for the unbaked device would be indicative of a greater density of interface traps at the nanotube/BCB interface in that device. However, the interpretation of the subthreshold slope in these devices remains under inve stigation.
131 Figure C 1 Transfer curves of CN VFETs that had a baked nanotube source electrode (prior to DNTT deposition) compared to an unbaked nanotube source electrode device. In the ON state, when V G = 1.75 V, voltage is applied to both device s until I D = 2.3 mA/cm 2 For the unbaked device this occurs at V D = 0.22 V and for the baked device at V D = 0.13 V. As a result of baking the nanotube film, the SS slope decreases significantly and the on/off ratio increases by two orders of magnitude. 980 mV/dec 350 mV/dec
132 A PPENDIX D EFFECTIVE CURRENT DE NSITY CALCULATION FO R LATERAL CHANNEL TH IN FILM TRANSISTORS To compare TFTs and VFETs in terms of the current output per unit device area, a sensible figure of merit is defined. A TFT with an interdigitated source drain elect rode configuration is assumed. The width of each source and drain electrode is taken to be the same as the channel length L from the published work, to maintain the minimum feature size (the channel length in all the TFT devices). Using the maximum on drai n current, I D per unit channel width W, and channel length L, into J Eff = I D /(2*W*L), an effective areal TFT current density is obtained. Figure D 1 shows a schematic of the interdigitated configuration where the dotted line encloses the effective area gi ven by this calculation. Calculation of the areal current density for the CN VFET does not include the area of the source contact, however, the area calculated for the lateral TFT n remains fair.
133 Figure D 1. Interdigitated source drain electrode configuration used to calculate the figure of merit J Eff to compare current outputs of TFTs and VFETs
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146 BIOGRAPHICAL SKETCH Mitchell McCarthy was born in 1983 in Tampa, Florida. Mitchell was the youngest of four, with two brothers and a sister. Mitchell grew up in Lutz, Florida, a small town outside of Tampa. There, he began his endeavors in designing, building and fixing things. At the age of 17, alone, Mitchel l took apart an automatic automobile transmission, completely, and re assembled it while he replaced worn seals and bearings. Upon re assembly, the transmission worked as good as new. Mitchell began his studies in the physical sciences in high school where he was University of Florida and chose physics as his undergraduate major. There, he worked for Professor Art Hebard where he designed modification parts for a vacuum sy stem and experimented with electric field gating of transparent conducting oxides with ionic liquids. For his leisure, Mitchell took frequent trips to the Atlantic Ocean to go surfing. He also played frisbee and volleyball during his undergraduate years. F or technical experience Mitchell was fortunate to have participated in three summer internships with Intel Corporation in Santa Clara, CA. With the eye opening experience he gained while at Intel he became excited by applying scientific knowledge to real world problems. In the fall of 2006 Mitchell joined the Materials Science and Engineering Department at the University of Florida. In the advisor. Collaboration between During the course of his research career Mitchell and his research colleagues made significant progress in not only demonstrating first ever performance of a revolutionary device architecture, but op timizing it and demonstrating its potential to the world.
147 Mitchell received his Ph.D. from the University of Florida in the fall of 2010 and continue s to work in research and development of novel CNT based organic electronic devices with the hopes of bring ing more energy efficient, lower cost, higher performance, opto electronic devices to the world.