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1 PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE FinFET-BASED MEMORY CELLS By ZHENMING ZHOU A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2010
2 2010 Zhenming Zhou
3 To my parents, brother, and wife
4 ACKNOWLEDGEMENTS I would like to express my most sincere appr eciation to my advisor, Professor Jerry G. Fossum, for his invaluable guidances, constant encouragement and gener ous support throughout the course of this work. It was a great honor and pleasure to work with him. His enthusiastic pursuit of academic excellence will se t a role model for me in my rest of life. I woul d also like to extend my sincere gratitude to the members of my supervisory committee, Dr. Jing Guo, Dr. Scott Thompson and Dr. Selman Hershfield, for their inte rests in this work, a nd their helpful advices and guidance. I am grateful to Samsung Electronics and Soit ec for their financia l and technical support offered towards this work. I would like to th ank my fellow students Weimin Zhang, Shishir Agrawal, Siddharth Chouksey Zhichao Lu, and Dabraj Sarkar fo r their insightful and technical discussions and friendships. Als o, I thank all of my friends fo r their companionship and help during years of life in University of Florida. I would like to express my heartful thanks to my father, Chengcai Zhou and my mother, Jiafang Yin for their endless en couragement, support, sacrifice, and love through these years. Without their support, this work could not have been possible. I also would like to thank my brother Liming Zhou, for his encourangement, advice, and warm contacts th at help to lift my spirits during my studies. Especially, I wish to express my gratitude to my beloved wife Xiny e. Her encouragement and support is a powerful source of inspiration and energy for me. I wa nt to say that to get married with her makes my life wonderful.
5 TABLE OF CONTENTS page ACKNOWLEDGEMENTS............................................................................................................ 4 LIST OF TABLES................................................................................................................ .......... 7 LIST OF FIGURES............................................................................................................... ......... 8 LIST OF ABBREV IATIONS....................................................................................................... 11 ABSTRACT...................................................................................................................... ............ 13 CHAPTER 1 INTRODUCTION ............................................................................................................. 15 2 COMPACT MODELING OF PAIRED-FINFET NAND FLASH CELL .......................... 20 2-1 Introduction ................................................................................................................. 20 2-2 Fin-Fin Coupling Effect and Model Development ...................................................... 22 2-3 Model Application ....................................................................................................... 27 2-4 Model Extension .......................................................................................................... 30 2-5 Summary ...................................................................................................................... 30 2 PHYSICAL INSIGHTS ON THE MEMORY MARGIN OF SCALED (FULLY DEPLETED) FLOATING-BODY 1T-DRAM CELLS........................................................42 3-1 Introduction ................................................................................................................. 42 3-2 Thin-BOX FD/SOI FBC .............................................................................................. 43 3-3 Thin-BOX DG FinFET FBC ....................................................................................... 45 3-4 Summary ............................................................................................................... .......47 4 PHYSICAL INSIGHTS ON BJT-BASED 1T CAPACITORLESS DRAM ....................... 57 4-1 Introduction ................................................................................................................. 57 4-2 Physical Insights on BJT-Based 1T DRAM Operation ............................................... 58 4-3 Bulk-Accumulation Effect on Sc alability of BJT-Based 1T DRAM .......................... 60 4-4 Viability of BJT-Based 1T DRAM .............................................................................. 62 4-5 Summary ...................................................................................................................... 63 5 A PUNCH THROUGH-BASED 2T DG-FINFET FBC ..................................................... 73 5-1 Introduction .................................................................................................................... 73 5-2 PT-Based Memory Effect in a FinFET FBC .................................................................. 74 5-3 The PT-Based 2T FinFET FBC ...................................................................................... 79
6 5-4 PT-Based Thin-BOX FD/SOI FBC ................................................................................ 81 5-5 Summary ......................................................................................................................... 82 6 SUMMARY AND FUTURE WORK .................................................................................. 97 6-1 Summary ......................................................................................................................... 97 6-2 Future Work .................................................................................................................... 99 LIST OF REFE RENCES............................................................................................................ 100 BIOGRAPHICAL SKETCH......................................................................................................106
7 LIST OF TABLES Table page 2-1Model-predicted Vt variation between the erased states, (E,E) and (E,P), and that between the programmed states, (P,E) and (P,P), for oxide, nitride, and air gaps............................31 2-2Model-predicted Best On-Cell Current, Worst On-Cell Current and Of f-Cell Current with Vread=6.0V and VCSL=0V.................................................................................................31 41Taurus-predicted write- a nd read-current se nsitivities of the 90nm PD/SOI Gen2 cell to typical variations in process-de fined structural parameters. .......................................... 65 42UFPDB-predicted write- a nd read-current sensitivities of the 90nm PD/SOI Gen2 ce ll to typical variati ons in process-defined structural parameters. ..................................66 51Performance comparison among PT-based FinFET FBC, FBGC3 and 1T FBCs ............. 84
8 LIST OF FIGURES Figure page 2-1 Structure of Paired-FinFET flash me mory (VsNAND) cell ..............................................32 22Illustration of the back-to-back IGFET structure of the pair ed-FinFET cell ..................... 33 23Simplied model-predicted ba ck-s urface potential in T2 (o r T1) versus the front gatesource voltage, for the erased and programmed states of T2 (or T1)................................ 34 24Effective back-gate bias of T1, versus the front gate-source voltage of T2, as defined in the fin-fin coupling model fo r the paired FinFETs ............................................................ 35 25Six-terminal UFDG-based s ubcircu it model for the paired-FinFET flash memory cell, including the fin-fin charge coupling................................................................................. 36 26Model-predicted current-voltage curves fo r the paired-FinFET flash memory cell in the four possible conditions: (T1,T2) = (E ,E), (E,P), (P,P) and (P,E)..................................... 37 27Model-predicted ICBL-VWL31 curves (bold black) for the 32-cell paired-FinFET flash memory string, erased (Vt < 0) and programmed (Vt > 0) devices, compared with measured data.................................................................................................................. 38 28Model-predicted IDS-VGS curves for the pa ir ed-FinFET flash memory cell, erased (Vt < 0) and programmed (Vt > 0) devices, showing composite Vt sensitivity to varying process-defined parameters................................................................................................ 39 29Schematic of a 32-cell VsNAND flash cell string with one CBL..................................... 40 210Model-predicted Worst On-Cell Current vers us VCBL fo r different values of Vread and VCSL set at 0.1V............................................................................................................... 41 31The basic (n-channel) struct ures of fully depleted planar thin-BOX FD/SOI FBCs. ...... 50 32Taurus-predicted current-signal mar gin and body-voltage variation versus UTB thickness of the 56nm FD/S OI FBC.................................................................................................. 51 33The back accumulation-onset and front thre shold voltages versus body thickness for the thin-BOX FD/SOI nMOSFET. .........................................................................................52 34The basic (n-channel) structures of fully depleted quasi-planar DG FinFET .................... 53 3-5Taurus-predicted current-voltage charact eristics of the 56nm DG nFinFET, for tSi = 28nmn and hSi = 56nm...................................................................................................... 54
9 36Taurus-predicted current-signal margin and body-voltage variation versus fin-UTB thickness of the 56nm DG FinFET FBC. .......................................................................... 55 37Taurus-predicted current-signal margin ve rsus fin-UTB thickness of the 56nm DG FinFET FBC for dif ferent fin heights.............................................................................................. 56 41Schematic of the SOI MOSFET as BJT-ba sed DRAM cell, sh owing the parasitic BJT which underlies the basi c cell operation............................................................................ 67 42Taurus-predicted BJT-based DRAM progr amming/read window fo r the 90nm PD/SOI MOSFET/BJT .................................................................................................................... 6 8 4-3Taurus-predicted BJT-based DRAM operation of the DG nFinFET, with tWB=+1ns and tWB=-1ns.......................................................................................................................... 69 4-4Taurus-predicted peak hole density (pw1) in the body, under the gate oxide, at the end of write- operation versus tWB for FinFETs with varying Lg and tSi .............................. 70 4-5Taurus-predicted write- and read currents for FinFETs with Lg=28nm and tSivarying from 12nm to 16nm; the same WL and BL voltage pul ses used in Figs. 4.3 and 4.4 were used here............................................................................................................ 71 46UFPDB -predicted BJT-based DRAM opera tion of the 90nm PD/SOI nMOSFET .......... 72 51Structure of PT-based DG FinFET FBC ............................................................................ 85 52SenTaurus-predicted DRAM operation of PT -based DG FinFET FBC............................ 86 5-3SenTaurus-predicted read- and read currents for FinFET FBC with Lg=56nm, tSi=56nm versus VGS ......................................................................................................... 87 5-4SenTaurusand model-predicted read currents of FinFET FBC versus VDS .............. 88 5-5SenTaurus-predicted electric potential di stribution in the cente r of the body of FinFET FBCs with tSi=56nm and tSi=28nm during read operations..............................................89 5-6SenTaurus-predicted read- and read currents for FinFET FBC with Lg=56nm, tSi=28nm versus VGS ......................................................................................................... 90 57Structure of PT-based 2T FinFET FBC in DRAM............................................................ 91 58SenTaurus-predicted DRAM operation of PT -based 2T FinFET FBC. ............................92 59SenTaurus-preidcted worst-case retention times of PT -based 2T and 1T FinFET FBCs under continuous and pulsi ng BL disturb.......................................................................... 93
10 510Ilustrations of how continuous BL disturb and pulsing BL disturb char ge the floating body of the PT-based 2T FinFET FBC, when is being held................................................. 94 511Structure of the PT-based thin-box FD/SOI nMOSFET FBC .......................................... 95 512SenTaurus-predicted currents of transien t DRAM operation of the PT -based 1T FD/SOI FBC............................................................................................................................ ........ 96
11 LIST OF ABBREVIATIONS 1T-DRAM one transistor dynami c random access memory 2T-DRAM two transistor dynamic random access memory BJT bipolar junction transistor BTBT band to band tunnelling CMOS complementary meta l-oxide-semiconductor CBL common bit line DG double-gate DIBL drain-induced barrier lowering DOS density of states DRAM dynamic random access memory EOT equivalent oxide thickness FB floating body FBC floating-body cell FBGC floating body/gate cell FD fully depleted FET field effect transistor GIDL gate-induced-drain leakage GSL ground-select-line HCE hot-carrier effect IG independant gate MOSFET metal-oxide-semiconductor fi eld-effect transistor nMOSFET n-type MOSFET PD partially depleted PT Punch Through SCE short-channel effect
12 SG single gate SIT Static Induction Transistor SOI silicon-on-insulator SSL string slect line UFDG University of Florida double-gate (model) UFPDB University of Florida partially depleted SOI and bulk MOS FET (model) UTB ultra-thin body Vs Vertical-structure
13 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE FinFET-BASED MEMORY CELLS By Zhenming Zhou December 2010 Chair: Jerry G. Fossum Major: Electrical and Computer Engineering This dissertation addresses physical analysis modeling, and design i ssues of nanoscale FinFET-based memory cells, including a paired -FinFET flash cell and floating-body cells (FBC), which are also known as capacitorless DRAM. The work includes compact modeling of the paired-FinFET flash cell, examining the scalabilit y of one-transistor (1T) fully depleted (FD) FBCs, physically analyzing and evaluating the BJT-based FinFET FBC, and demonstrating a novel punch through (PT)-based twotransistor (2T) FinFET FBC. The fin-fin coupling effect in the paired-FinF ET flash memory cell is physically analyzed and modeled. A UFDG-based subcircuit model for the memory cell, taking into account the finfin charge coupling, is proposed, defined, and veri fied. The model is used to check and analyze the signal margin in NAND-array operation, and the process sensitivities, as well as to aid the paired-FinFET design. Two FD devices, the planar thin-BOX FD/SOI MOSFET and the quasi -planar double-gate (DG) Si FinFET, are most promising for fu ture nanoscale CMOS technology. Their actual scalabilities as FBCs are examined in terms of the memory margin and its dependence on the
14 transistor body thickness. We find and explain the significant memory-margin losses in both devices as they are scaled to nanoscale gate length, which imply a scaling limit of 1T-DRAM FBCs. The basic operation of the BJT-based FBC is analyzed and physical insights are derived. Extreme sensitivity of the chargi ng process (write 1) to the ti me offset between the word-line and bit-line voltage pulses is revealed and explained. Gate ca pacitance is found to be the predominant charge-storage element in the BJTbased cell. Such charging underlies why a FD cell, e.g. a FinFET, can work for BJT-based DRAM without an independent bias for accumulation charge that is necessary in conventional FD-MOSFET DRAM cells for charge storage and data sensing. Further, a bulk-accumulation effect in the BJT-based DRAM cell is revealed and described. The viability of the BJ T-based FBC is generally studied. A novel PT-based 2T DG-FinFET FBC for low V DS operation is proposed. This FBC has improved reliability by avoiding hot -carrier effects (HCEs). Phys ical insights on the mechanism of the modulation of PT curren t by floating-body charge conditions in the FinFET-based FBC are provided. A strong dependence of the PT-based memory effect on the thickness of the FinFET body is physically explained. A 2T structure design is proposed fo r the PT-based FBC to reduce the hold-1 leakage current and achieve a longer wo rst-case retention time. The application of the PT-based FBC in planar thin-BOX FD/SOI MOSFET technology is explored. However, compared with its counterpart using FinFET te chnology, the thin-BOX FD/SOI FBC is shown to suffer from a lower sense margi n, less charging efficiency and worse compatibility for embedded memory applications.
15 CHAPTER 1 INTRODUCTION Current memory devices [i.e ., DRAM and non-volatile memory (NVM)] face significant scaling challenges beyond the 45 nm CMOS node due to both proc ess difficulties and physical limitations. A next-generation de vice, the ultra-thin-body (UTB) fu lly depleted FinFET, is most promising to extend the memory scalability . Th e double-gate (DG) FinF ET can be scaled to the end of SIA readmit (ITRS) due to its excellent control of s hort channel effects (SCEs) . Also, the undoped UTB implies reduced threshold voltage variation due to random-dopant fluctuations, which plagues the conventional pl anar devices (i.e., bulk-silicon and PD/SOI MOSFETs) . The research described herein se eks to explore the application of FinFETs in nanoscale memory, especially for NAND flash and DRAM. Scaling conventional planar fl oating-gate NAND flash devices below 45nm, as needed for high density and low bit cost, faces many chal lenges which include: maintaining high gatecoupling ratio (GCR), reducing floating-gate (FG) coupling between neighboring cells, controlling SCEs, and maintaining high drive cu rrent . Charge-tra pping flash i.e, SONOS devices, together with a FinFET structure can overc ome these scaling limitati ons, and is likely to be implemented to extend memory scaling belo w 30nm gate length . However, the FinFET flash cell also has scali ng limitations due to cell-cell coupling in array operation and finite fin-fin distance which mu st be large enough to contain tw o SONOS structures -. A recently reported paired-FinFET charge-trapping NAND flash cell, which utilizes two fins separately as two storage nodes in one cell, can double the integr ation density of conventional FinFET flash in the same technol ogy node . In addition, this paired-FinFET flash is also shown to be feasible for multi-bit operation . However, the coupling between the two back-toback-connected fins in one cell leads to threshold-voltage vari ation, which affect s array operation.
16 Since 3D numerical simulations ar e too time consuming , in Chapter 2 we develop a simple analytical model of the paired-F inFET NAND flash cell to facilita te the optimal de vice and circuit design. The physics/process-based model, which acc ounts for the fin-fin coupling effect, predicts memory array operation correctly. This model is also used to check the sensitivities of the NAND flash-cell threshold voltage to th e process parameter variations. Conventional 1T/1C DRAM faces signifi cant scaling challenges for sub-60nm nodes because of the increasing process and design difficulties to mainta in adequate charge storage and low level of leakage . It is difficult to scale the access tr ansistor due to the serious SCEs. A three-dimensional recess-channel array transi stor (RCAT) has been adapted for sub-70nm DRAM technology to obtain sufficient retention time by increasing cha nnel length and reducing junction leakage . Beyond the 45nm technology node, a DG FinFET access transistor is promising because it can achieve hi gh drive current due to its vertical structure, and also exhibits excellent immunity to SCEs an d relatively low junction leakage due to undoped channel . A more serious scaling problem for 1T/1C DRAM however, is to maintain adequate storage capacitance while the cap acitor gets physically smaller. Th e effective oxide thickness (EOT) needs to be scaled down, but increased electrica l field leads to high tunneling leakage current. High-k dielectric material, such as H f SiO and Al 2 O 3 (k~10-25), and new capacitor structures, e.g., a MIM (Metal-Insulat or-Metal) capacitor, have been proposed to solve this problem . In the future, however, breakthroughs in new material s with a high k value of 50 or greater will be required . Furthermore, the capacitor technologi es with these new materials and structures are not compatible with the conventional CMOS te chnology, and manufacturable solutions are not known . To overcome these difficulties of scaling conventional 1T/1C DRAM, capacitorless 1T DRAM cells on SOI, which util ize the MOSFET floating body to store charge, have been
17 proposed and developed -. These memory cells work through se nsing of the channel current, which depends on the threshold voltage that varies with the floating-body charge condition; thus, they are also called floating-body cells (FBCs). Without an additional storage capacitor, these FBCs only take a cell area of 4F 2 FBCs can also have a good compatibility with standard CMOS technology, enabling its SOC application. The FBC was first proposed and developed on patially depleted (PD) SOI, fo r which floating-body eff ects have been well acknowledged . The same conc ept has been demons trated with bulk-Si technology too, by introducing a triple well to create a floating body . The interest in fully depleted (FD) SOI devices has grown a lo t in recent years to extend the scalability of FBCs for future nanoscale CMOS [ 20]-. Two devices, i.e., the planar thinBOX FD/SOI MOSFET -[2 7] and the quasi-planar double-gate (DG) Si FinFET , are believed to be promising ca ndidates. The thin BOX enables th e FD/SOI device to function as an FBC with relatively low substrate bias for creating the accumulation layer at the back surface of the body, which is necessary for effective char ge storage and data sensing . In Chapter 3, we explore whether these two devices, as FBCs, could achieve the same good scalability as that for logic applications. We examine the actual sc alability of these devices in terms of memory margin and its dependence on UTB thickness (t Si ). We find that both devices suffer significant signal-margin loss as t Si is scaled down, implying a scaling limit of 1T-DRAM FBCs. We present new physical insights on the scaling, and explain the different reasons for the margin losses in the two devices. A recently reported BJT-based capacitorless 1T DRAM can be based on FinFETs without independent gate or substrate bias, showing good sc alability and full compatibility with standard SOI processing . This DR AM cell utilizes the parasitic BJT current in the SOI MOSFET structure for both writing and reading data. But th ere is currently no insight on how the parasitic
18 BJT works for DRAM operation, e.g., why the FinF ET can work without the independent gate bias. In Chapter 4, we present new physical in sights into the memory operation of BJT-based DRAM cells. We find and physically explain an interesting phenomenon that renders the write1 operation extremely sensitive to the time offset between the word-line (W L) and bit-line (BL) voltage pulses . We also gain insight into the role of gate capac itance in the BJT-based charging process. We further reveal a bulkaccumulation effect that undermines the BJT operation as the silicon body thickne ss scales. We show that the BJ T-based DRAM suffers from a short 0-retention time due to serious BL disturb due to the high drain voltage (V DS ) required for BJT latch. We further show that the hot-carri er reliability, also undermined by the high V DS is the major issue that threatens the viability of the BJT-based DRAM. In Chapter 5, we propose a novel punch-thr ough (PT)-based two-transistor (2T) DG FinFET FBC for low V DS operation, which as a re sult, improves the reliability by avoiding hotcarrier effects (HCEs). We show that this PT -based FBC also offers low power operation, high sense margin, long worst-case retention times, and good compatibility for embedded memory applications in future nanoscale CMOS tec hnology. We provide physical insights on the PTbased memory effects in the FinFET FBC, expl aining the modulation of PT current by floatingbody charge conditions. We also re veal that the PT-based memory effect strongly depends on the thickness of the FinFET body. We design a PT-based FinFET FBC in a 2T structure, which not only reduces the hold-1 leakage current but also achieves longer worstcase retention times. Furthermore, we explore the application of the PT-based FBC in planar thin-BOX FD/SOI MOSFET technology. However, we find that, comp ared with its counterpart using FinFET technology, the thin-BOX FD/SOI FBC suffers from a lower sense margin, less charging efficiency, and worse compatibility with l ogic CMOS technology. We ar gue that thick-body FinFETs are the best candidate s for the 2T PT-based FBC.
19 Finally, we summarize the contri butions of this work in Chapter 6. Suggestions for future work are also discussed.
20 CHAPTER 2 COMPACT MODELING OF PAIR ED-FINFET NAND FLASH CELL 2-1 Introduction Because of its small size, NAND flash has been used as the storage device for mobile and handheld applications . Al though the demand for high density a nd low-cost flash memory has increased dramatically, the current planar fl oating-gate NAND flash cell faces significant difficulties as it scal es down below 50nm . Two of the most severe difficulties are maintaining high gate coupling ratio (GCR) a nd reducing the floating-gate (FG) coupling between neighboring cells . Charge-t rapping flash, i.e, SONOS devices, has been promising for sub-45nm node because it has no GC R issue and reduced FG coupling. Variations of SONOS, e.g, the MANOS (metal-Al 2 O 3 -Nitride-Oxide-Si) device using high-k blocking oxide (Al 2 O 3 ) and TaN gate with high work function, has been reported to have better scalability because it utilizes thicker tunnel oxide (30~40) to reduce the direct tu nneling . Chargetrapping flash can also be used for multi-bi t operation to increase th e bit density without compromising area . When charge-tra pping flash scales down below 32nm node, the serious SCEs and drive current reduction make it difficult to maintain high sense margin and operation speed . The DG FinFET is promising to overcome this limitation due to its excellent immunity to SCEs and vertical side wall channel   . Beside s, the charge-trappingtype FinFET (SONOS) cell has bett er reliability and larger pr ogram/erase window due to the larger storage area compared with planar stru cture . However, the FinFET flash cell also has scaling limitations. Cell -cell coupling in array operation becomes serious and the fin-fin distance is hard to reduce because it must be large enough to contain two SONOS structures . A recently reported paired-FinFET charge-t rapping NAND flash cell, containing two
21 storage nodes in one unit by utilizing the two fins separately, can double the integration density compared with conventional FinFET flash . Th is paired-FinFET device is also shown to be feasible for multi-bit operation . Together wi th all of the other advantages of the FinFET, paired-FinFET charge-trapping flas h is one of the most promis ing candidates of future NAND flash memory. However, by introducing two bits in one cell, there is a coupling between the two back-to-back connected fins, which leads to thre shold-voltage variation a nd affects the verticalstructure NAND flash (VsNAND) array operation, e.g., the Worst On Current and Best On Current. Since the 3D numerical simulation is too time consuming , a si mple physical model, that takes the fin-fin coupling effect into account is desirable to predict correct memory array operation, and to facilitate opt imal device and circuit design. In this chapter, we physically analyze and m odel the fin-fin coupling effect in the pairedFinFET flash memory cell. We then propose and develop a UFDG -based compact model for the paired-FinFET flash cell. UFDG is a pro cess/physics-based model for generic double-gate (DG) MOSFETS . The paired-FinFET model is formulated in a UFDG/Spice3 subcircuit which defines two back-to-back independent-g ate FinFETs (IGFETs), with common gate and connected UTBs. An effective back-gate bias for each transistor is defined internally, depending on the state of the adjacent transistor, to take account of the fin-fin c oupling effect. The physics/ process-based model, which can be calibrated straightforwardly, is shown to predict erased/ programmed I-V curves that agr ee well with measured data. The model predicts the thresholdvoltage (V t ) shift due to the fin-fin char ge coupling, for oxide, nitride, and air gaps, in reasonably good accord with numerical simulations. A 32-cell VsNAND array operation is simulated using the model, giving the results of Best On-Cell Current, Worst On-Cell Current, and Off-Cell Current that generally agree well with measured data. We also show that the model reliably predicts sensitivities of the VsNAND-cell thres hold voltage to process-parameter variations.
22 Further, the application of this model to the floating ( poly)-gate flash memory cell is explored and discussed. 2-2 Fin-Fin Coupling Effect and Model Development The structure of the paired-FinFET flash memory cell, a two-bit VsNAND cell, is shown in Fig. 2.1. The cell comprises two split fins, on bulk Si, within one pitch of the technology. Each fin acts as a data-storage element based on va riation of the FinFET threshold voltage (V t ) via controlled tunneling/charge storage in the ONO di electric stack. The two fins are separated by a dielectric (e.g., SiO 2 ) gap, with a common (front) gate ove rlapping both. Herein, the thickness of the fin-separation gap is w gap = 30nm, and the front-gate di electric is a 3.85nm/6.25nm/6.95nm ONO stack. The gate length (L g ) is 60nm. The height of both fins is h Si = 100nm, and the thickness of each is w Si = 15nm. The fin-bodies are le ft undoped, and the gate is n + polysilicon. We can simply characterize paired-FinFET fl ash memory cell as two back-to-back fully depleted (FD) SOI MOSFETs with hypothetical subs trates (or back gates) if we dont consider the fin-fin coupling effect. Howe ver, since the paired FinFETs are separated by only a thin dielectric gap, the threshold volta ge variation caused by the fin-fi n coupling effect must be taken into account. To incorporate the coupling effe ct, based on insights affo rded by our numerical simulations, we propose to redefine the two paired FinFETs as IGFETs, each with an effective back-gate bias determined by the state of the ot her, as illustrated in Fig. 5.2 The two FinFETs share the same back-gate dielect ric (we initially assume oxide) and the silicon UTB of each FinFET serves as the back gate of the other. In order to describe the fin-fin coupling effect we first discuss the surface potentials in the left FinFET (T1) in Fig. 2.2, and note that the results are applicable to the right FinFET (T2). In the gradual-channel approximation, the basic MOS equations for the front and back gates  are
23 ,(2.1) and ,(2.2) where V GfS1 and V GbS1 (which is the volta ge applied to the body of T2, i.e., the bulk-Si substrate voltage, relative to th e source voltage of T1) are the fr ont and back gate-source biases, MSf1 and MSb1 are the front and back gate-body work-function differences, sf1 and sb1 are frontand back-surface potentials in the UTB (referenced to a hypotheti cal unbiased neutral body), and oxf1 and oxb1 are the potential drops in the front and back gate oxides (all referring to T1). Note that since both the back gate and th e body of T1 are undoped silicon, MSb1 = 0 in (2.2). Note also in (2.2) that we have accounted for the pot ential drop in the back gate, i.e., sb2 which is the backsurface potential of T2. However, since UFDG doe s not account for potential drops in the gates, we will define, by comparing (2.2) with (2.1) an effective back-gate bias for T1 as .(2.3) Our fin-fin coupling modeling thus is focused on how to simplify and model sb2 which should be controlled mainly by V GfS2 Based on undoped-UTB MOSFET theory , wh ich recognizes bulk inversion, when V GfS2 is greater than V t of T2 (V t2 ), the back surface of the body is strongly inverted, and sb2 is virtually pinned near ( FB + c ) 0.7V, where FB is the Fermi potential of the unintentionally doped silicon body ( 0.3V due to natural acceptor dopants), and c ( 0.4V) is a counterpart of 2 FB for undoped bodies . When V GfS2 is much less than V t2 the back surface is strongly accumulated, and sb2 is virtually pinned near ( FB c ) -0.1V. Between these onsets of strong inversion and strong accumul ation, e.g., for depletion, sb2 is approximately linear in V GfS2 or + = + + = + =
24 ,(2.4) with sb2 sf2 ; r eff = C b(eff) /C ox is the effective body factor, with C b(eff) being the effective body capacitance . Thus, in the interm ediate region of operation, we approximate (2.5) where the threshold voltage was predicted by th e preliminary model, having values of -0.51V/ 3.05V for erased/programmed (E/P) stat es of the FinFET, respectively; r eff could be estimated from the gate swing (S) of the transistor : .(2.6) From the E/P current-voltage characteristics pred icted by the preliminary model (which describes paired-FinFET flash memory cell as two back-t o-back fully depleted (FD) SOI MOSFETs with hypothetical substrates), S 180mV/dec, and so r eff ~ 2. Figure 2.3. shows sb2 -V GfS2 curves for T2 in the E/P states, as predicted by (2.5) wi th the noted pinned potentials; they are in good accord with our numerical simulation results. We note that fin-fin coupling will not si gnificantly affect the T1 current-voltage characteristics when T1 is biased to strong inversion or strong a ccumulation, since th e free-carrier charge screens the electric field from the oxide gap. From this in sight, our model for V GbS1(eff) in (2.3) could be simplifie d by using (2.5) only when T1 is in the subthreshold region, and T2 is in the same state as T1, assuming a constant sb2 otherwise. To illustrate this simplification, we describe sb2 respectively, for the four possible conditions of the two paired FinFETs: (T1,T2) = -------------------+ + = + -----------------------------++ + ----
25 (E,E), (E,P), (P,E), and (P,P). As plotted in Fig. 2.4, when T1 is in the subthreshold region, for states (E,E) and (P,P), T2 is also in the subthreshold region, and hence sb2 is defined by (2.5); for state (E,P), T2 is, fo r practical operation of the cell, in the strong-accumulation region, and sb2 = ( FB c ) = -0.1V; and for state (P,E), T2 is, for pr actical operation of th e cell, in the stronginversion region, and sb2 = ( FB + c ) = 0.7V. From our physical insight on the fin-fin couplin g, we thus see that the paired-FinFET flash memory cell can be characterized as two IG FETs, with effective back gate biases (V GbS1(eff) and V GbS2(eff) defined analogously) dependent on the state of the adjacent transistor. The cell subcircuit model, illustrated in Fig. 2.5, has six termin als: the common gate (G = Gf1 = Gf2), the common (bulk-Si) body (B = B1 = B2 ), the left-FinFET (T1) drain (D1) and source (S1), and the right-FinFET (T2) drain (D2) and source (S2); V GbS1(eff) and V GbS2(eff) are defined internally, as described above, for the four different (T1,T2) conditions. The paired-FinFET flash cell mo del, accounting for the fin-fi n charge coupling, is defined by four UFDG/Spice3 subcircuits: FL ASHCELLEE, FLASHCELLEP, FLASHCELLPE, and FLASHCELLPP. The four subcircu its account for the four possi ble (T1,T2) conditions of the paired FinFETs, i.e., states (E,E), (E,P), (P,E) and (P,P), defining V GbS1(eff) and V GbS2(eff) accordingly as described in th e previously. There are two IGF ETs in each subcircuit, modeled with UFDG. The model was used to predict the I DS -V GS characteristics at V DS = 0.8V of the left FinFET (T1), thus emulating a r ead operation. Simulation result s predict the fin-fin coupling effect: a larger V t variation between (E,E) and (E,P) than that between (P,E) and (P,P), as illustrated in Fig. 2.6., in good accord with the numerical simulation results in . This results prove that our model give accurate modeling of the fin-fin coupling effect. The UFDG model is proces s/physics-based, involving only physical and structural parameters . The parameter evaluation thus can be done systematic ally, based on knowledge
26 of the transistor technology a nd underlying physics. Thus, for mo del calibration, only a few key parameters need to be tuned via specific devi ce measurements, as exemplified and explained below. The front gate-oxide thickness TOXF is the equivalent oxi de thickness (EOT), defined by the dielectric stack (3.85nm/6.25nm/6.95nm ONO). To derive TOXF, the nitride thickness t 2 is converted to an equivalent oxide thickness t 2(eq) Then, (2.7) where t 1 and t 3 are the respective oxide-la yer thicknesses; (2.7) yields TOXF = 14nm for the stack assumed. The back gate-oxide thickness TOXB is the gap oxide thickness between the two fins. The front-oxide fixed (normalized ) charge density NQFF (= Q ox /q at the SiO 2 -Si interface) is a key parame ter that distinguishes V t of the programmed and erased transistors. It effectively accounts for th e actual charge density Q ox stored at the N-O interface. With NQFF calibrated to measured data, the nominal Q ox for the programmed transi stor was derived from Q ox as follows: ,(2.8) where the calibration yielded NQFF = -5.0x10 12 cm -2 ; the factor of 2 in (2.8) is approximately (t 1 +t 2(eq) +t 3 )/(t 1 +t 2(eq) ), as derived from the EOT analysis. The silicon fin-body of each FinFET also serves as the back gate of the adjacent transistor, and so the back-gate work function WKBG is the work function of undoped silicon (with natural acceptor doping density assumed to be 10 15 cm -3 ). The front surface-state density NSF is cons idered for the programmed status since the ++ == ----------------
27 programming/erase processes seem to affect NSF, as reflecte d by a difference between the measured subthreshold I DS -V GS slopes of the memory cell in the erased and programmed statuses. NSF is inferred from th e programmed device data, and is assumed negligible for the erased device. The body-source/drain junction recombination/ge neration current coefficient JRO and the drain and source parasitic series resistances RD and RS are tuned to match the measured I off and I on of the cells in a 32-cell string, respectively. The subcircuit-cell mode l is verified by calibr ations to measured I DS -V GS data obtained from SAIT . The measuremen t was conducted for a 32-cell string, with all the cells in the string either in (E,E) or (P,P) state. Thus, we conduct the calibrations by simulating the 32-cell VsNAND array read operation, which will be discusse d in detail in next section. The calibration results, showing model predictio ns in agreement with the measured data for programmed and erased devices, are illustrated in Fig. 2.7. 2-3 Model Application Since the model is process/phys ics based, the memory-cell mode l presented can be a useful aid to device/technology design, and give reliable performance projections. To exemplify the model utility, in this section, we introduce some of the model a pplications, i.e., to examine the impact of process-parameter va riations, to analyze the fin-fi n charging coupling effect on Vt variation, and to facilitate the circuit simulation of VsNAND FLASH array operation. First, we use the model to check the sensitivit ies of Vt to variations in crucial processdefined parameters. The model predicts I DS -V GS curves that reflect the V t sensitivity of erased and programed devices to variation in L g W si and Q ox , as shown in Fig. 2.8. The model predicts that the V t variation in erased transi stor is mainly due to variation in Si-fin thickness and/or gate length, and that larger V t variation in the programmed tr ansistor is due to additional
28 sensitivity to variation in the charge density stored in the ONO structure. Further, the model is used in fin-fin char ge coupling analysis. The fin-fin coupling can affect the integrity of paired-F inFET flash memory. A design modi fication for dealing with this problem is to use a gap material with low diel ectric constant, thereby ameliorating the coupling. Our coupling model has been defined based on an SiO 2 (oxide) gap, but it can be used for other possible dielectrics as well, e.g., Si 3 N 4 (nitride) and air . For th e other dielectrics, the gap thickness (TOXB = t gap for oxide, where t gap is the physical dielectric thickness) is defined to be the equivalent back-oxide thic kness (EOT); for nitride, EOT = 0.52t gap and for air, EOT = 3.9t gap The model predicts, correctly, that the nitride gap yields th e most coupling, while the air gap yields the least coupling, consistent with th e fact that thicker EOT reduces the coupling. The predicted V t variations caused by the fin-fin charge coupling for the programmed and erased states, with oxide, nitride, and air gaps, are tabulated in Table 2.1. All the predictions agree reasonably well with corresponding result s of numerical simulations in . The UFDG-based paired-FinFET flash me mory cell model predicts the erased/ programmed transistor current-vol tage characteristics accurate ly, including sensitivities to process-induced parameter variati ons and fin-fin charge coupling. We now demonstrate its utility in simulations of VsNAND-array read operations. Numerical simulation is not able to used in this simulation because of the too much time c onsuming because of multi devices needs to be simulated simulatneouly.A schema tic of (32-bit) VsNAND string is illustrated in Fig. 2. 9. This string has the same schematic as the one used in measurement. In the schematic, the two FinFETs included in one subcircuit model are in diff erent bit lines. Because the bit-line pitch is below the design rule, it is impossi ble to make individual contact to each bit line [ 10]. Therefore, the two bit lines share one contact and serve as a common bit line (CBL). There are two pairs of select transistors, the stringselect-line (SSL) transistors and the ground-select-line (GSL)
29 transistors, in the string. They have nearly the same structure as the memory cell, but having a larger gate length. Subcircuit m odel for these 170nm select transistors is calibrated. In this string, the signals to and from the two bit lines ar e not separated as shown in the figure. As mentioned in section 2.2, VsNAND array read simulation was conducted for calibration and verifying the cell model. Th e array simulation based on the co mpact model predicts the CBL current (I CBL ) subject to a word-line voltage sweep, i.e., the I CBL -V WL31 characteristics governed by the FinFETs in the last word line (WL31) at V CBL =0.8V, for the conditions (E,E) and (P,P) of the two paired FinFETs in the cell. A V read (=6.0V) bias is applied to the other word lines to ensure that all the other transistors are turned on. Simulation re sults agree well with measured I DS -V GS data. Further, we use the UFDG-based cell model to simulate the memory operations of the string, e.g., Best On-Cell Current (with cell on WL 31 selected and erased and all unselected cells erased with their WLs at V read ), Worst On-Cell Current (with ce ll on WL31 selected and erased, and all unselected cells programmed with their WLs at V read ), and Off-Cell Current (with cell on WL00 selected and worst-case programmed, and al l unselected cells erased with their WLs at V read ). The model predicts the (DC) CBL current versus V CBL that reflects the state of (i.e., the bit in) a selected cell. Simulation results of ar e tabulated in Table 2.2. As an example, figure 2.10. shows the predicted Worst On-Cell Current versus V CBL for different values of V read and V CSL set at 0.1V. The predictions generally conform well to measured data . It is noted that the VsNAND-Array operation differs from those of conventional planar type memory because of the fin-fi n coupling effect. It is noted th at by utilizing a VsNAND string with two pairs of SSL tr ansistors which can separate the two bi t line, we can sensed the cell in the four possible (T1,T2) conditions.
30 2-4 Model Extension Besides charge trapped type, fl oating gate (poly silicon) is another alternative for the Paired-FinFET flash memory design. Our model c ould still accounts for th e floating-gate flash memory pretty well, with only one parameter T OXF redefined. For the floating-gate memory, The ONO dielectric stack is replaced by three laye rs: Inter-Poly Oxide, Poly Floating Gate and Tunneling Oxide sequentially. Then, ,(2.9) where t 1 and t 2 are the respective oxide-layer thickne sses. And the actual charge density Q ox stored at the Floating Gate for the programmed tr ansistor could be derived from the NQFF (= Q ox /q at the SiO 2 -Si interface) as follows: .(2.10) 2-5 Summary A UFDG-based subcircuit model for the pa ired-FinFET flash memory (VsNAND) cell, taking into account the fin-fin charge coupli ng, was proposed, defined and verified. The model accurately predicted the sensitivi ties to process-induced parame ter variations and the fin-fin charge coupling. The subcircuit model was used to successfully simulate the VsNAND-array (string) operations, predicting corr ect values of Best On-Cell Curr ent, Worst On-Cell Current and Off-Cell Current. Finally, we noted that the mode l is easily extended to be applicable to the floating-gate flash. In conclusion, the compac t physics/process-based model is useful for checking and analyzing the signal margins a nd process sensitivities for the VsNAND FLASH array, as well as for ai ding the paired-FinFET design. + == ----------------+ -----------------
31 Table 2-1. Model-predicted Vt variation between the er ased states, (E,E) and (E,P), and that between the prog rammed states, (P,E) and (P,P), for oxide, nitride, and air gaps. Gap Material Vt(Erased State) Vt(Programmed State) Oxide0.37V0.09V Nitride0.57V0.18V Air0.11V0.03V Table 2-2. Model-predicted Best On-Cel l Current, Worst On-Cell Current and Off-Cell Current with Vread=6.0V and VCSL=0V. VCBL(V) Best On Cell Current( A) Worst On Cell Current( A) ff Cell Current (nA) 00.000.000.00 1.02.071.571.25 2.03.042.4273.6
32 Oxide/Nitride/Oxide (ONO) n+ Poly Oxide Silicon hSi wSi wgapFigure 2-1. Paired-FinFET flash me mory (VsNAND) cell structure.
33 Oxide/Nitride/Oxide (ONO) n+ Poly Oxide Silicon Figure 2-2. Illustration of the back-to-back IGFET structure of the paired-FinFET flash memory cell. Left FinFET (T1) GateOxideBodyOxide Gate Gate Oxide Body Oxide Gate Right FinFET(T2)
34 Erased State Programmed StateFigure 2-3. Simplified model-pred icted back-surface potential in T2 (or T1) versus the fron gate-source voltage, for the erased a nd programmed states of T2 (or T1). -5.0-4.0-3.0-2.0-1.00.01.02.03.04.05.0 -1.0 -0.5 0.0 0.5 1.0 VGfS2 (V) Slope=1/(1+reff) 0.33 sb2 (V)
35 Figure 2-4. Effective back-gate bi as of T1, versus the front ga te-source voltage of T2, as defined in the fin-fin coupling model fo r the four possible conditions of the paired FinFETs: (T1,T2) = (E ,E), (E,P), (P,P), and (P,E ). We assumed here that VGbS1 = 0, and hence VGbS1(eff) = sb2. VGfS2 (V)VGbS1(eff) (V) -5.0-4.0-3.0-2.0-1.00.01.02.03.04.05.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 (E,E) (E,P) (P,E) (P,P)
36 Figure 2-5. Six-terminal UFDG-b ased subcircuit model for the paired-FinFET flash memory cell, including the fin-fin charge coupling. The effective back-gate biases of the two IGFETs are defined internally to model the coupling effects. G B D2D1S1S2VGbS2(eff) VGbS1(eff) ++
37 Figure 2-6. Model-predicted current-voltage curves for the paired-FinFET flash memory cell in the four possible conditions: (T1,T 2) = (E,E), (E,P), (P,P) and (P,E). Note here that VGS = VGfS1 = VGfS2. -5.0-4.0-3.0-2.0-1.00.01.02.03.04.05.0 VGS(V) 10-1210-1110-1010-910-810-710-610-510-4IDS(A) (E,E) (E,P) (P,E) (P,P)
38 Figure 2-7. Model-predicted ICBL-VWL31 curves (bold black) for the 32-cell paired-FinFET flash memory string, erased (Vt < 0) a nd programmed (Vt > 0) devices, compared with measured data (light curves/points); VDS = 0.8V, with source and body grounded.
39 -5.0-4.0-3.0-2.0-1.00.01.02.03.04.05.0 VGS (V) 10-1110-1010-910-810-710-610-5IDS (A)IDS vs. VGS for erased and programmed status Figure 2-8. Model-predicted IDS-VGS curves for the paired-FinFET flash memory cell, erased (Vt < 0) and programmed (Vt > 0) devices, showing composite Vt sensitivity to varying process-defined parameters; VDS = 0.8V. For the erased device, Lg and wSi were varied +/-10%. For the programmed device, Lg and wSi were varied the same, and NQFF was varied by about +/-7%.
40 Figure 2-9. Schematic of a 32-ce ll VsNAND flash cell string with one CBL. The bias on WL31 is swept from -5.0V to +5.0V, with SSL and GSL high, to predict the (DC) CBL current versus VWL31 and thus reflect the states of (i.e ., the bit in) the tr ansistors in WL31. SSL WL31 WL30 WL01 WL00 GSL CSL Programmed State Erased StateBL2 BL1 CBL
41 Figure 2-10. Model-predicted Wors t On-Cell Current versus VCBL for different values of Vread and VCSL set at 0.1V. 0.00.20.40.60.81.01.21.126.96.36.199 VCBL (V) 0.0e+00 5.0e-07 1.0e-06 1.5e-06 2.0e-06 2.5e-06 3.0e-06ICBL (A) Vread=5.0V, VCSL=0.1V Vread=5.5V,VCSL=0.1V Vread=6.0V,VCSL=0.1V Vread=6.5V, VCSL=0.1V
42 CHAPTER 3 PHYSICAL INSIGHTS ON TH E MEMORY MARGIN OF SC ALED (FULLY DEPLETED) FLOATING-BODY 1T-DRAM CELLS 3-1 Introduction Because of the integration pr oblems associated with the stor age capacitor of conventional 1T/1C DRAM in sub-50nm CMOS t echnology, interest in capacito rless 1T DRAM, i.e., floatingbody cells (FBCs) on SOI, has grown in recent y ears -. The FBCs are based on sensing the MOSFET channel current, co rresponding to the th reshold voltage (V t ) which depends on the floating-body charge condition effected via carrier generati on or recombina tion during the write processes. While FBCs emerged initially as partially depleted (PD) SOI MOSFETs , two fully depleted (FD) devices with more potential scalability, i.e., the planar thin-BOX FD/SOI MOSFET - and the quasi-p lanar double-gate (DG) Si Fi nFET , are more promising candidates for FBCs lin ked to future nanoscale CMOS, especially for high-density and embedded applications. The thin BOX enables th e FD/SOI device to function as an FBC with relatively low substrate bias for creating the accu mulation layer at the b ack surface of the body, which is necessary for effective charge storage and data sensing . We assume that the DG FinFET is on thin BOX too, and ope rates with low substrate bias for accumulation as well , , as opposed to the independent -gate mode  (which is, elec trically, equivalent to the FD/ SOI FBC) that necessitates more complex processing. In this paper, we study, via both 2-D and 3-D numerical device simu lations using Taurus , whether acceptable memory, or current-signal, margins can be achieved in the two noted FD FBCs as they are scaled to nanoscale gate lengths (L g ). This is tantamount to examining the dependence of the signal margins on the ultra-thin-body (UTB) thickness (t Si ), which must be scaled with L g to control short-channel effects (SCEs) . We fi nd that both devices suffer significant signal-margin loss as t Si is scaled down, implying a scaling limit of 1T-DRAM
43 FBCs. We present new physical insi ghts on the scaling, and explain the different reasons for the margin losses in the two devices. 3-2 Thin-BOX FD/SOI FBC We first examine the current-signal margin of thin-BOX FD/SOI FBCs via 2-D numerical simulations using Taurus. The basi c structure of the n-channel de vice is shown in Fig. 3.1. For the simulations, we assume L g = 56nm with an EOT of t ox = 2nm, a midgap work-function gate, an undoped UTB with t Si varying from 6nm to 35nm, a thin BOX with t BOX = 10nm, and a p + Si substrate (which facilitates the needed back-s urface accumulation in the body). For nominal t Si thin enough to control SCEs ( L g /4 for thin-BOX CMOS logic  which could be relaxed some for the FBC application), we note that V t is high ( 0.7V) when the substrat e is biased for the needed strong hole accumulation . The memory -operation word-line (WL) and bit-line (BL) biases used in the simulations, which are typica l -, are given in the inset of Fig. 3.2; a typical read/write pulse time of 10ns is assumed. The substrate bias (V sub = -2.0V) is fixed for strong accumulation at the b ack of the UTB (when t Si in nominal). For write 1, the WL (V GS ) is raised to induce a channel, and the BL (V DS ) is pulsed high to drive channel current (I DS ) and induce impact-ionization current (I Gi ) to charge the body. For write 0, the WL is raised and the BL is pulsed down to forward-bias the B-D junction and discharge the body. The different charged and discharged conditions in the body define, in the read operations, a body-voltage variation ( V BS ) which causes a V t variation , (3.1) where r is the body coefficient, nominally defined by the device geometry : (3.2) where C b = Si /t Si C ox = ox /t ox Si / ox 3 has been assumed. = =
44 The signal margin is the diff erence in channel current ( I DS ) between the read-1 and read0 operations, as governed by V t in (1). In Fig. 3.2 we show, versus t Si the predicted signal margin (per m of the MOSFET width) and the corres ponding body-voltage variat ion of the thinBOX FD/SOI FBC. As t Si is scaled down, I DS first increases, but then falls off dramatically for t Si < 12nm, portending a scaling limitation. (These trends are cons istent with results in , which were given without a comprehensiv e explanation.) The initial increase of I DS is mainly due to increased r, as described in (3. 2). The s ubsequent fall-off is, we find, mainly due to (i) a reduction of the hole accumulation level during th e read operation, which leads to an effective decrease of r in (3. 1)  and (ii) an increase of V t which leads to reduction in channel current during read. Another possibly importa nt effect of the increased V t is reduction in impactionization current and body charging during write 1 . However, th is effect is not reflected by V BS (t Si ) in Fig. 3.2, which remains high and even increases with decreasing t Si for t Si < 12nm. This increase of V BS is due to increased efficiency of body discharging (lower V BS ) during write 0 as the hole accumulation leve l (and storage capacitance) decrea ses. The main reasons (i) and (ii) that we noted are in accord with Fi g. 3.2, which shows the dramatic degradation of I DS for thin t Si even though V BS remains high. The reduced accumulation in (i) defines an r eff < r in (3. 1), with r eff approaching zero when the back surface of the body becomes depleted [ 29]. The loss of accumulation is explained by basic gate-substrate charge-coupling analysis of the FD/SOI MOSFET, wh ich characterizes, for the front surface at threshold, the onset substrat e bias for back-surface accumulation , : (3.3) where c (~0.4V) is the front-surface potential at thre shold for an undoped body. Note in (3. 3) that becomes more negative as t Si decreases, meaning that for fixed V sub the accumulation ---------+ =
45 level decreases. The tendency for the higher V t in (ii) is explaine d by the same coupling analysis, which also characterizes (without SCEs) V t for accumulation at the back surface , : .(3.4) Note in (3. 4) that increases with decreasing t Si due to the increased tr ansverse electric field, meaning that for fixed WL read voltage, the i nversion level tends to decrease with scaled t Si implying reduced current a nd margin irrespective of V BS and V t We note that the actual V t effective in the read operation is lower than in (4) because of SCEs and because of the noted loss of accumulation at the back surface, but none theless it does increase with decreasing t Si as our simulations s how, and undermines I DS significantly. We note that both effects (i) and (ii) become significant for t Si < ~15nm, as reflected in Fig. 3 where plots of and versus t Si both show significantly increasing magnitudes for this range of t Si These results are consistent with I DS (t Si ) in Fig. 3.2. For scalability then, these eff ects mean that larger WL and substrate biases would be needed for acceptable memory operation, which is contra ry to the spirit of scaling. Also, for the thin-BOX FD/SOI MOSFET, with t Si scaled down and with |V sub | large enough to achieve strong accumula tion at the back surface and V GS high enough to achieve strong inversion in the front chan nel, carrier mobility ( ) degradation becomes significant due to the increased transverse electric field  The field increases with decreasing t Si quite significantly, approaching infinity as t Si goes to zero. This decreased further reduces the margin of the scaled FD/SOI FBC. 3-3 Thin-BOX DG FinFET FBC The DG FinFET is most likely to become th e future mainstream CMOS device, with -------+ + =
46 excellent scalability to the end of SIA ITRS [1 ]. There are two possible modes of FinFET-based FBC operation. One is the independent-gate (I G) mode , with one gate biased for accumulation, which, electrically, is the same de vice as the thin-BOX FD/SOI FBC that we examined in Sec. II. This FinFET mode seems le ss viable for embedded-me mory applications due to its technology complexity and in compatibility with the CMOS logi c. The other mode is the DG FinFET on thin BOX with substrate bias ,  for accumulation at the bottom of the fin, as shown in Fig. 3.3. This mode, with simpler technology, is a more pr omising alternative for future nanoscale 1T-DRAM FBCs. The FBC memory operation for this mode depends on a 2-D floating-body effect, by which the accumulation layer at the bottom of the fin-body enables the charge storage and the data sensing via sidewall -channel current dependent on the stored charge. For the latter mode, we assume a DG (n -channel) FinFET analogous to the FD/SOI MOSFET we assumed: L g = 56nm, t ox = 2nm, midgap gates, undoped fin-UTB with t Si varying from 14nm to 42nm, t BOX = 10nm, and p + Si substrate; we initially a ssume a fin height (or device width) h Si = 56nm, but will check its effect on the 2-D floating-body effect la ter. We examine the device via 3-D numerical device simulations using Taurus, and give predicted currents per m of h Si For nominal t Si thin enough to control SCEs ( L g /2 , which could be relaxed for FBCs), we find, as reflected by the predicted I DS -V GS characteristics in Fig. 3.5, that V t is slightly higher when the (p + ) substrate is biased for strong accumulation (V sub = -2.0V) than it is ( c ) for depletion in normal logic operation (with a grounded, lightly doped substrate). The higher V t (by 30mV for this case) results from a 2-D gate-s ubstrate charge-coupling effect by which the hole accumulation at the bottom of the fin increases th e electric field in the sidewall channels. The increased field also causes some mobility de gradation as evident in Fig. 3.5. This same 2-D coupling effect underlies r eff for this FinFET FBC, and since it seems to be mild, we might surmise that r eff is low and the memory margin is inferior to that of the planar FD/SOI FBC in
47 which the coupling effect is 1-D and stronger. The predicted current-signal margin of the DG FinFET FBC, and the corresponding bodyvoltage variation, versus t Si are shown in Fig. 3.6, along with th e WL and BL voltage pulses used (with 10ns read/write times) for th e simulations. Indeed, for nominal t Si I DS is smaller than that of the FD/SOI FBC, even with two gates, and it decreases as t Si is scaled down. Like for the FD/ SOI FBC, the I DS decrease is uncorrelated with V BS but it is not as abr upt like for the FD/SOI cell; it begins for relatively thick t Si and it increases gradua lly with decreasing t Si These I DS (t Si ) results are consistent with a relatively low r eff defined by the 2-D floating-body effect, which is not as strong as the 1-D effect re flected by (2). Since the coupling effect on V t is small (see Fig. 3.5), we can deduce that the margin reduction for scaled t Si is due mainly to loss of the hole accumulation, which is ea sily explained. For thin t Si the 2-D electric field induced by the sidewall gates near the bottom of the fin tends to induce depletion/invers ion there , thereby reducing the accumulation level and suppressing its effect on V t ; the 2-D r eff is decreased. A lack of DG FinFET-FBC scalability is clearly implied, and perhaps more so than that for the FD/SOI FBC. We have assumed h Si = 56nm (=L g ) for our study of the DG FinFET FBC. Since the cell performance is based on a 2-D coupling effect in the fin-body we now check wh ether varying h Si could improve the margin and the scalability of the cell. A quasi-2-D extensi on of (3. 2) suggests that increasing h Si would diminish the coupling and r eff yielding reduced margin. Decreasing h Si would enhance the coupling, but, based on our insi ght derived in Sec. II, would exacerbate the margin loss for scaled t Si ; a more abrupt fall-off of I DS would result. These insights are borne out by the simulation result s in Fig. 3.7 showing I DS versus t Si for three different values of h Si No significant scaling benefit is revealed
48 3-4 Summary The memory-margin dependences on UTB thickness of nanoscale planar thin-BOX FD/SOI and quasi-planar DG FinFET 1T-DRAM cells were examined via 2-D and 3-D numerical device simulations, and physical insights were attaine d. We found that the FD/SOI FBC suffers from abrupt current-signal margin degradation with UTB scaling because of loss of body accumulation charge, as well as loss of inversion charge due to increased threshold vo ltage. Further, thin t Si with the needed accumulation, yields high transv erse electric field, wh ich leads to mobility degradation and additional loss of margin. We noted also that the DG FinFET FBC suffers from nominally low signal margin due to a relatively low, 2-D effectiv e body coefficient, as well as gradual margin loss with fin-UTB scaling due to lo ss of accumulation charge at the base of the fin. Both 1T-DRAM cells hence seem to have limited scalability. Although scaling t Si of the two FD FBCs we examined is clearly limited, the L g scalability is not as clear. (In this discussion, L g is actually the effe ctive channel length, which is longer than the gate length when gate-source/drain underlap - is used in the device design.) The margin predictions for the FD/S OI FBC in Fig. 3.2 indicate a t Si scaling limit of ~10nm with good margin, which would translate to L g ~ 40nm for the CMOS but could imply a shorter L g limit for the FBC, depending on the SCE tolerance. For shorter L g and V t lowered due to SCEs, the required WL holding (negative) voltage would tend to be larger in magnitude, and this requirement could define the practical L g scalability. However, base d on SCE sensitivity to t Si , the L g limit would not be much shorter than the noted 40nm. Further, use of a thicker t Si for the FBC than that used for the scaled CMOS would complicate the technology for the embeddedDRAM application. The achievable margin of the DG FinFET FBC will be nominally lower, and, as indicated by the predictions in Fig. 3.6, acceptable ( 50 A/ m is assumed, based on a 3 A/ fin (i.e., per cell) need ) down to a t Si scaling limit of only ~25nm; this translates to L g ~ 50nm
49 for the CMOS, but perhaps somewhat shorter fo r the FBC as noted for the FD/SOI cell. And, whereas the predictions in Fig. 3. 7 show a tende ncy for improvement in the scalability of the FinFET FBC with decreasing h Si the benefit is not significant and such design would complicate the embedded-DRAM tec hnology since the CMOS h Si should be as high as possible. Thus, the two FD 1T-DRAM cells seem to have comparable scalability, which, unfortuna tely, is not close to the end of the SIA ITRS (e.g., L g < 10nm for high-perfor mance CMOS logic ).
50 Si Substrate BOX n+n+p-Gate tSi G (word line) (bit line) (source line) D S Sub Figure 3-1. The basic (n-channel) st ructures of fully depleted planar thin-BOX FD/SOI and quasiplanar DG FinFET (with channel perpendicula r to the figure) FBCs. The substrates of both devices are negatively bias ed for hole accumulation at the back/bottom of the Si body.
51 Write 1Write 0Read WL1.0V1.0V1.0V BL1.5V-1.0V0.2V tSi (nm) VBS (V) IDS ( A/ m) 010203040 0 20 40 60 80 100 120 140 160 180 200 220 0 5 10 15 20 25 30 35 40 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 3-2. Taurus-predicted current-si gnal margin and body-voltage variation versus UTB thickness of the 56nm FD/SOI FBC. The word-line and bi t-line voltage pulses used for the 2-D transient memory-sequence simula tion are indicated in the inset, and 10ns read/write times were assumed; Vsub = -2.0V. IDS is defined as the difference between IDS at the ends of the read- 1 and read-0 operations; VBS is defined as the difference in VBS (i.e., the quasi-Fermi-potential se paration at the source side of the body) between the two read operations.
52 Figure 3-3. The back accumulation-onset and (front) thres hold voltages versus body thickness, derived from (3) and (4) with c = 0.4V, respectively, for the thin-BOX FD/SOI nMOSFET. Note that the actual Vt in the read operations of the FBC is lower than due to SCEs and the loss of hole accumulation at the back surface of the body reflected by vs. tSi. 010203040 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 5 10 15 20 25 30 35 40 -5 -4 -3 -2 -1 0 1 VA t (V)VA sub (V)tSi (nm)
53 Figure 3-4. The basic (n-channel) st ructures of fully depleted planar thin-BOX FD/SOI and quasiplanar DG FinFET (with channel perpendicula r to the figure) FBCs. The substrates of both devices are negatively bias ed for hole accumulation at the back/bottom of the Si body. Gate SiO2Si Substrate BOX Si Fin tSi Sub
54 Vsub = 0.5V Vsub = -2.0V VGS (V) VDS = 50mV 00.10.20.30.4 0.50.6 0.70.8 0 50 100 150 200 250 300 IDS ( A/ m)Figure 3-5. Taurus-predicted current-voltage ch aracteristics of the 56nm DG nFinFET, for tSi = 28nmn and hSi = 56nm, with the (p+) substrate biased for strong accumulation (-2.0V) and for depletion (0.5V, whic h is equivalent to a grounded, lightly doped substrate) at the base of the fin. For the latter case, Vt c, whereas it is 30mV higher for the former case.
55 Write 1Write 0Read WL0.8 V0.8 V0.8 V BL1.5 V-1.0 V0.2 V tSi (nm) IDS ( A/ m) VBS (V) 10203040 50 0 10 20 30 40 50 60 70 80 90 100 10 15 20 25 30 35 40 4550 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 3-6. Taurus-predicted current-signal ma rgin and body-voltage variation versus fin-UTB thickness of the 56nm DG FinFET FBC. Th e word-line and bit-line voltage pulses used for the 3-D transient memory-sequence simulation are indicated in the inset, and 10ns read/write times were assumed; Vsub = -2.0V.
56 tSi (nm) IDS ( A/ m)hSi = 28nm hSi = 56nm hSi = 84nm 10 15 20 25 30 35 40 4550 0 20 40 60 80 100 120 140 160 180 200 IDS = 3 A/fin Figure 3-7. Taurus-predicted current-signal margin versus fin-UTB thickness of the 56nm DG FinFET FBC for different fin heights. Crude tSi scaling limits, based on an assumed needed memory margin of 3uA/cell, are indicated for each assumed value of hSi.
57 CHAPTER 4 PHYSICAL INSIGHTS ON BJT-BASED 1T CAPACITORLESS DRAM 4-1 Introduction Because of the integration limit of conventional 1T/1 C DRAM in nanoscale CMOS technology, interest in capacitorless 1T DRAM cells on SOI, which utilize the MOSFET floating body to store data, has grown in recent years 25]. Wh ile most conventional 1T DRAM cells work through sensing of the cha nnel current, dependent on the threshold voltage that varies with the floating-body charge condition, a recently reporte d 1T DRAM cell utilizes the parasitic BJT current in the SOI MOSFET struct ure for both writing and reading data -. This BJT-based 1T DRAM cell has attracted inte rest because of its fu ll compatibility with standard SOI processing and its potentially supreme performance, e.g., very high signal margin, low power consumption, and high density. The BJ T-based DRAM cell is also shown to have better scalability and compatibility than conve ntional FD-MOSFET DRAM cells because it can be effected with FinFETs without independent ga te bias or substrate bias. Although the parasitic BJT has already been studied in tensively as one of the floating-body effects in the SOI MOSFET , there is not much in sight on how it is used for DR AM operation and why a FinFET can work without an independent gate. In this chapter, using numerical device si mulations, we physically overview the basic operation of BJT-based 1T DRAM cells. We find and physically explain an interesting phenomenon that renders the writ e-1 operation extremely sensitiv e to a time offset between the word-line (WL) and bit-line (BL) voltage pulses. We also gain insight concer ning the role of gate capacitance in the BJT-based char ging process, which explains w hy a fully depleted (FD) cell, e.g., a FinFET , can be effectively charged without an independent bias for accumulation charge that is necessary in conventional FD-MOSFET DRAM cells . We also reveal a bulk-
58 accumulation effect that undermines the BJT operation as the cell-body thickness is scaled. Furthermore, we explore the viability of BJ T-based DRAM by studying its sensitivity to variations of process parameters and retention time. Based on the physical insights we get, we show that undoped, FD/SOI bodies /bases will be needed, as in SG-FD/SOI MOSFETs or DG FinFETs. Further, we note that the serious hot-c arrier reliability problems constitute the major issue that threatens the viability of BJT-base d DRAM. A capacitorless DRAM for a low-voltage operation is called for. 4-2 Physical Insights on BJT-Based 1T DRAM Operation The operation of the BJT-based DRAM cell, illustrated in Fig. 4.1 (with grounded S), is based almost exclusively on the parasitic BJT of the floa ting-body SOI n-channel MOSFET, which is driven to near the BV CEO breakdown for writing and read ing 1 (body/base charging). The memory effect is shown by a programm ing/read window shown in Fig. 4.2. This I D ( I BJT ) vs. V Gread (WL pulse) plot is derive d from transient (pulsed-V G ) simulations done with Taurus , for stored 1 (charged body/base) and stor ed 0 (uncharged body/base) states of a 90nm PD/SOI cell. The detail descript ion of memory operation, together with the now physical insight we get about it will be shown later. The programming/read window sh ows a very high sense margin mainly due to BJT latching. We also point out that I BJT increases some with the read V G for state 1. We believe this incr ease is due to BJT current gain ( increasing with V Gread due to less bulk accumulation charge (and hence lower ef fective Gummel number) within the effective thickness (t Si(eff) ) of the BJT. Later, this effect will be discussed more and shown to be an limitation of BJT-ba sed dram scaling. We first demonstrate the general BJT-base d 1T DRAM-cell operati on via 2-D numerical device simulations done with Taur us . We present results of simulating the DRAM operation of a DG (n-channel) FinFET, as illustrated in the inset of Fig. 4.3. The FinFET has a 56-nm gate
59 length (L g ) with an EOT of t ox =2nm, an undoped fin-body with thickness t Si =28nm, and midgap gates; the default fin hei ght, or gate width, is 1 m. As shown in Fig. 4.3, for write 1, the BL (V D ) is pulsed to near the breakdown voltage (BV CEO ) of the parasitic BJT, and the WL (V G ) is pulsed up to raise the body/base voltage [V BS (t)], via capacitive c oupling, enough to increase and drive the latch condition, (M 1) 1, where M is the impact-ioni zation multiplication factor. The (weak) impact-ionization current that charges the body/base is I Gi = (M 1)I BJT where I BJT is the induced BJT current. For write 0, V G is pulsed up again to raise V BS and V D is kept well below BV CEO thus effecting removal of the stor ed holes by mainly body-source junction recombination; I BJT (t) decays to zero. For the read operation, with high V D < BV CEO a smaller V G pulse is used, but high e nough to induce BJT latch, via V BS (t) > 0, when the body is charged (read 1); when the body is not charged, V BS (t) is lower and no signifi cant current is induced (read 0). In Fig. 4.3, we show predicted current, I DS (t) I BJT (t), corresponding to a complete sequential memory operation of the BJT-based DRAM cell for two different offsets ( t WB ) between the WL and BL voltage-pulse drops, t WB =+1ns and t WB =-1ns as indicated. We see an interesting phenomenon. For t WB =+1ns, i.e., the BL voltage begins to fall 1ns after the WL voltage, the predicted opera tion is normal with a high current margin about 450 A/ m. However, for t WB =-1ns, no current is sensed for the 1 state, implying a failur e of write 1. Since latchedBJT currents are seen in the write-1 process for both cases, the different charging results must be defined during the short 2ns difference in t WB This insight is confirmed by the predicted ultimate peak hole density (p w1 ) in the body/base, under the gate oxide, plotted in Fig. 4.4. versus t WB The stored hole density is quite sensitive to t WB ; p w1 increases by a factor of five as t WB increases from -1ns to +1ns. We note that when t WB =-1ns, p w1 is clearly smaller than the critical density (p crit ) for latch, even approaching the density (p w0 ) corresponding to stored 0. This
60 means that the write-1 process in this case virtually resu lts in write 0. Note also in Fig. 4.4 that t WB =0 yields tenuous results (i.e., p w1 ~p crit ); indeed, a finite WL-BL pulse offset is essential. The t WB phenomenon can be explained by consider ing the basic charging process in a floating-body 1T DRAM cell. For hole storage, th e floating body needs a substantive intrinsic dynamic capacitor . We find that the gate capacitance (C G ) serves as the predominant chargestorage element in BJT-based char ging, but its efficacy depends on t WB When the BJT is latched in the write-1 process, V G is irrelevant; the open-base BV CEO breakdown is selfsustaining . Thus, for t WB >0, i.e., when the WL pulse drops prior to the BL pulse, the BJT remains latched, with V BS (t) nearly fixed, when V G drops negative to hold the data, as shown in Fig. 4.3. Then, the latched BJT charges C G with additional holes, Q p C G V G where V G is the drop in V G However, for t WB <0, i.e., when the BL pulse ends prior to the WL pulse, the BJT unlatches when V D drops, and holes in the base/body are quickly removed by recombination in the forward-biased source a nd drain junctions. Then, there is no way to charge C G when WL ultimately drops. This insight reveals that the effective body, or C G charging occurs during the (positive) offset time. It furthe r implies that, since the BJT latch can be achieved very fast due to the positive feedback, a very short write-1 time is possible. Additional simulations confirm this implication, predictin g effective times of less than 5ns. Also we note that the utilization of C G for the charge storage is a unique property of the BJT-based cell, and enables the memory operation with FD bodies. For example, an undoped FinFET could be used , without an independent bias to induce accumulation in the body as needed in conventional 1T DRAM cells for storing holes and reading data , , . For the la tter cells, in which channel current drives the impact ionization, C G cannot be used as the storage elem ent because of the existence of the channel.
61 4-3 Bulk-Accumulation Effect on Scalability of BJT-Based 1T DRAM As mentioned, in the write-1 process with t WB >0, the BJT remains latched during the offset time. However, the current decreases a bit when V G drops, as indicated in Fig. 4.3. This is because of the added charge Q p on C G which manifests as bulk accumulation charge in the body. The hole accumulation tends to deactivate the BJT near the surfaces, or to reduce the effective thickness [t Si(eff) ] of the BJT base, and hence undermine the BJT and memory operations. We also note this t Si(eff) effect when we introduce th e generic programming/read window previously. This bulk-acc umulation effect thus portend s a scaling limitation. As t Si is scaled with the technology, t Si(eff) shrinks, ultimately pinching-of f the BJT. Additional simulation results in Fig. 4.4 illustrate this issue. For the L g =56nm cell (in the working t WB 1ns region), the write-1 process is successful, even as t Si is thinned; in fact, p w1 actually increases a bit because of reduced junction recombination after the BL drop. However, for a scaled cell with L g =28nm and t Si scaled accordingly (~L g /2), the hole density is dramatically reduced, and more so as t Si is thinned. The write-1 process is very sensitive to the assumed small t Si variation of only 2nm. This extreme sensitivit y, and the undermining of the wr ite-1 process, reflects the reduction of t Si(eff) ; ultimately, the process fails as the BJT is not latched and C G is not charged. The scaling problem is empha sized in Fig. 4.5, which shows pr edicted read-1 and write1 currents versus t Si for the L g =28nm cell. Note how the read-1 current falls off dramatically with t Si thus diminishing the margin; the current is virtually zero for t Si 13nm. Whereas our prediction of this trend is valid, the actual t Si limit noted could vary wi th the WL and BL voltage pulses used, as well as with differences in th e numerical model parameters  assumed. The write-1 current is less sensitive because the higher V G yields less bulk accumulation. We propose that the bulk-accumula tion effect could be cont rolled by not scaling t Si so much when L g is scaled for higher memory density, since shor t-channel effects are not too significant for the
62 DRAM cell. 4-4 Viability of BJT-Based 1T DRAM Since BJT-based DRAM cell is driven to near the BV CEO breakdown in the write 1 and read 1 operations, its high sensitivities to variat ions in crucial processdefined parameters are expected. We checked these sensitivities of a 90nm PD/SOI dram ce ll via 2-D numerical simulations with Taurus . We assumed a typical retrograded channel doping density, with N BL = 5x10 17 cm -3 near the surface and N BH = 10 18 cm -3 below the depletion layer, of thickness t b = 40nm; we let the SOI thickness be t Si = t f = 120nm. The simulating results show that both the highand low-doped portions of the body/base c ontribute to the BJT action. We show Tauruspredicted shifts of curren t for write 1 and read 1 due to variations in L g t b t f N BL and N BH in Table 4.1 respectively. The results show high sens itivity of memory opera tion to these expected parameter variations especially in L g and N BH This is because L g is the virtual base width of the parasitic BJT, which determines directly, and the predominant part of the BJT is in the lower, quasi-neutral part of the body, where N BH defines the Gummel number. It is noted that our process/physics-based co mpact model for partially depleted (PD) SOI MOSFETs, UFPDB , can be used to simulate the operation of BJT-based PD/SOI DRAM cell in Spice3, as shown in Fig. 4.6. Thus, we also use the UFPDB to check the BJT-based PD/SOI DRAM cells sensitivies to variat ions in process-related paramete rs. The UFPDB-predicted shifts of current for write 1 and read 1 due to variations in L g t b t f N BL and N BH are shown in Table 4.2. Although the sensitivities seem to be overestimated by UFPDB, their predicted significances are in accord with the Taurus predictions. Because of the significant random fluctu ations in the body/base doping, the PD/SOI memory cell will suffer substantiv e sensitivity degradation when scal ed down, just like the widely varying threshold voltage of the scaled PD/SOI MOSFET. As show n in Table 4.1, Taurus predicts
63 significant write-1 and read-1 current shif ts (>20%) with the assumed variations in N BH and N BL These variations will be larger and random in scaled PD/SOI, and so the results in Table 4.1 imply that PD/SOI memory cell will not be viable in the fu ture. Undoped, FD/SOI bodies/bases will be needed, as in SG-F D/SOI MOSFETs or DG FinFETs. The 0-retention time subject to BL disturb by GIDL current is another important issue that threatens BJT-based cells viability. Since a high V DS is used in BJT-based DRAM cell to achieve a BJT latch, the associated BL disturb becomes more serious than that in conventional FBC. Although a long underlap (~30nm) has been suggest ed for BJT-based cell to solve this 0retention problem , it not onl y increases cell area but also degr ades its memory compatibility for embedded application. Further, BJT-based DRAM cells suffers signifi cant hot-carrier reliability issues due to the high drain voltages (V DS ) required for BJT latch . A endurance failure after only 500 cycles for BJT-based FinFET DRAM cell has been shown in . Theref ore, this hot-carrier reliability problem is the fatal issue that th reatens BJT-based cells viability. A lower V DS operation is necessary for the capacitorless DR AM cells to achieve a high reliability. 4-5 Summary The basic operation of BJT-base d 1T DRAM cells on SOI wa s simulated numerically, and physical insights were derived. We noted that th e gate capacitance is the predominant chargestorage element, implying that fully deplet ed bodies without i ndependent biasing for accumulation charge can be used. We noted a nd explained that a pos itive WL-BL offset ( t WB ) is necessary for effective write 1, with extreme sensitivity to t WB Sensitivity to the needed t WB must be accounted for in the circuit design. We noted a bulk-accumulation effect that may undermines the BJT and cell operations for thin t Si resulting in loss of current margin and ultimate write-1 failure. Cons idering sensitivities to process parameters, we proposed that PD/
64 SOI is not viable as scaling dow n, while FD body device, such as FD/SOI or FinFET, will be needed in the future. We noted that the serious hot -carrier related reliabili ty problems, due to the high V DS for BJT latch is the major issue that thr eatens the viability of the BJT-based DRAM. A viable capacitorless DRAM cell must be able to operate at a low V DS for enough reliability.
65 Table 4-1. Taurus-predicted write-1 an d read-1current se nsitivities of the 90nm PD/SOI Gen2 cell to typical variations in process-defined structural parameters. Iwrite 1 Iread 1Lg(-10% / +10%) +14% / -19%+15% / -22% tb(-10% / +10%) -5.0% /+3.0%-7.5% / +4.7% NBL(-10% / +10%) +5.2% / -3.5%+4.9% / -4.3% NBH(-10% / +10%) +11% / -7.7%+14% / -12% tb(-20% / +20%) -8.3% / +7.0%-12% / +8.8% NBL(-20% / +20%) +10% / -8.3%+9.8% / -8.4% NBH(-20% / +20%) +22% / -15%+28% / -23%
66 Table 4-2. UFPDB-predicted write-1 and read-1curre nt sensitivities of the 90nm PD/SOI Gen2 cell to typical variations in process-defined structural parameters. Iwrite 1 Iread 1Lg(-10% / +10%) +90% / -70%+130% / -100% tb(-10% / +10%) -1.6% / +5.3%+11% / -15% tf(-10% / +10%) -4.2% / +3.5%-12% / +9.0% NBL(-10% / +10%) +7.0% / -7.0%+1.1% / -1.1% NBH(-10% / +10%) +57% / -20%+100% / -90%
67 Figure 4-1. Schematic of the SO I MOSFET as BJT-based DRAM cell, showing the parasitic BJT which underlies the basic cell operation. D (BL) G (WL) SOI nMOSFET Parasitic npn BJT Floating Body/Base S
68 Figure 4-2. Taurus-predicted BJT-based DRAM programming/read window for the 90nm PD/ SOI MOSFET/BJT. -2.0-1.5-1.0-0.50.0 VGread (V)VG(w)VG(r)-100 0 100 200 300 400 500 600 700ID ( A/ m)-200 State 1 State 0 V=0.8V
69 BL WLVoltage (V) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0102030405060708090Time (ns)Write 1HoldRead 1 Hold Write 0 HoldRead 0 tWB=+1ns tWB=-1ns 0102030405060708090 -100 0 100 200 300 400 500 600 700 800 900 1000 n+n+p(body) D S G (word line) G (word line) toxtoxtSi (bit line)Time (ns)IDS (A/m)(source line) tWB=+1ns tWB=-1ns Figure 4-3. Taurus-predicted BJT-based DR AM operation of the DG nFinFET, with tWB=+1ns and tWB=-1ns. The transient pulsings of th e word line and bit line of the cell are shown in the top plots. The tr ansient cell currents, which reflect the stored data, are shown in the bottom plot s, where the inset illustrates the basic structure of the FinFET. We note, with refe rence to the superimposed circle in the bottom figure, that in the write-1 oper ation, the BJT remains latched during the WL drop for the tWB=+1ns case.
70 -1.0-0.8-0.6-0.4-0.20.00.20.188.8.131.52 tWB (ns)0 1 2 3pw1 (1020cm-3) tSi decreasing pcrit pw0 Lg=56nm; tSi=20nm, 24nm, 28nm Lg=28nm; tSi=13nm, 14nm, 15nmFigure 4-4. Predicted peak hole density (pw1) in the body, under the gate oxide, at the end of write-1 operation versus tWB for FinFETs with varying Lg and tSi; the same WL and BL voltage pulses used in Fig. 4.3 were used here. The critical write-1 hole density (pcrit) for the FinFET with Lg=56nm and tSi=14nm is indicated. Based on simulations, if pw1>pcrit, the DRAM cell is in the 1 state, and if pw1
71 Figure 4-5. Predicted write-1 and read -1 currents for FinFETs with Lg=28nm and tSi varying from 12nm to 16nm; the same WL and BL voltage pulses used in Figs. 1 and 2 were used here. The bulkaccumulation effect reduces the read-1 current significantly as tSi decreases. The predicted lowe r sensitivity of the write-1 current to the tSi variation is due to the higher VG used in write 1, which alleviates the bulk-accumulation effect. 0 50 100 150 200 Read 1 Write 1tSi (nm)1213141516Lg=28nm IDS ( A/ m)
72 Time (ns)IDS (A/m)Figure 4-6. UFPDB -predicted BJT-based DR AM operation of the 90nm PD/SOI nMOSFET -3 -2 -1 0 1 2 3 4 5Bias (V) 0102030405060708090 Time (ns) Bit line Word line Write 1 Read 1Write 0Read 0 0102030405060708090 -200 0 200 400 600 800 1000 1200 Write 1 Read 1 Write 0Read 0
73 CHAPTER 5 A PUNCH THROUGH-BASED 2T DG-FINFET FBC 5-1 Introduction Because of the process di fficulties associated with the st orage capacitor of conventional 1T/ 1C DRAM in sub-50nm CMOS technology, capaci torless DRAM cells, i.e., SOI floating-body cells (FBCs), have attracted intensive research interest in recent years [30-32]. The first kind of FBC works through sensing of the channel current, which is dependent on the threshold voltage that varies with the floating-body charge c ondition. Either channel impactionization current or GIDL current has been us ed to charge the floating body. However, as demonstrated in Chapter 3, 1T FBCs lack scalability due to loss of sense margin caused by scaled body thickness. Furthermore, the i ndependent gate or substrate bias [which is required for charge storage and data sensing for fully depleted (FD) cells] not only limits the memory compatibility for embedded applications but also re duces the effective body coefficient (r eff ) significantly as the FBC scales down . Another ki nd of FBC, analyzed in Chapte r 4, utilizes th e parasitic BJT current in the SOI MOSFET for both write and rea d. This cell has drawn mo re attention recently because it provides high sense margin, non-de structive read, and, especially, superior compatibility without the need of any substrate or independent ga te bias. However, as discussed in Chapter 4, BJT-based FBCs as well as the 1T FBCs , suffer from hot-carrier reliability issues due to the high drain voltage (V DS ) required for impact ionization and BJT latch (>2.5V). While both of the two noted FBCs consist of one transistor, th e 2T FBGC is also promising . FBGC utilizes the floati ng body of one transistor to direct ly drive the gate of the second transistor. It offers excellent memory perfor mance including high sense margin and very long retention times, alt hough the gated-diode structure of the first transistor (T 1) increases the process complexity. In addition, in order to achieve a long 0 retention ti me under BL disturb, T1 needs a
74 very long underlap (~30nm) which not only incr eases cell area but also degrades its memory compatibility. In this chapter, we propose a novel punch through (PT)-based 2T FinFET FBC that offers low power operation, high sense margin, long worstcase retention times, im proved reliabilities, and good compatibility for embedded memory a pplications in future nanoscale CMOS technology. This PT-based FinF ET FBC utilizes GIDL for program ming and PT current for data sensing, without the need for substrate or independent gate bias. The proposed FBC design enables a low V DS (~1V) operation, which, as a result, impr oves the reliability by avoiding hotcarrier effects (HCE). We provi de physical insights on the mechan ism of the modulation of PT current by floating-body charge conditions in the Fi nFET-based FBC. We also find that the PTbased memory effect strongly depends on the thickness of the FinFET body. We design a PTbased FinFET FBC in a 2T structure by adding anot her pass transistor to block BL disturb for holding data. We show that the 2T structure also plays an important role in achieving a high I read1 /I hold 1 ratio for viable DRAM array operation, which is hard to achieve in a 1T PT-based FinFET FBC. Furthermore, we veri fy the functionality of the PT -based FBC for planar thin-BOX FD/SOI MOSFET technology. However, we find that, compared with its counterpart using FinFET technology, the thin-BOX FD/SOI FBC suff ers from a lower sense margin due to its finite body capacitance.Thus, 2T thick-body FinFETs seem to be the best candidates for the PTbased FBC. Thorough performance comparisons of the PT-based 2T FinFET FBC with other 1T and 2T FBCs are made in the final section. 5-2 PT-Based Memory Effect in a FinFET FBC In this section, we fo cus on the basic PT-based memory ef fect in DG-FinFET FBCs. The PT phenomenon is well known as a major obstacle fo r submicron CMOS tran sistor scaling . However, there are some devices, for instance, PT transistors [69-71], that utilize gate-controlled
75 PT current for high-voltage and hi gh-frequency applications. In addi tion, it has been reported that when a short-channel MOSF ET is biased with high V DS the avalanched holes can trigger not only the parasitic BJT latch but also PT current, which can be used for memory application . However, this cell works almost the same as the BJT-based FBC , and so it also suffers from serious HCE issues due to the BJT latch. While our PT-based FinFET FBC works through sensing of only the charge-modulated PT current rather than BJT current, it can operate at a remarkably low V DS (~1V) and achieve superior reliability. We first demonstrate the basic DRAM operati on of a one-transistor (1T) PT-based FinFET FBC via numerical simulation us ing SenTaurus . The 2T FB C architecture suggested for performance improvement will be di scussed later in detail in the next section. The basic structure of the n-channel DG FinFET is shown in Fig. 5.1. For the simulation, we assume L g =56nm with an EOT of t ox =3nm, a midgap work-function gate, an undoped body with t Si =56nm; the default fin height, or gate width, is 1 m. Noted that a thicker body is us ed, compared with the nominal t Si that is thin enough to control SCEs (~L g /2 ). We will show later th at this design is critical for the PT-based FinFET FBC. In Fig. 5.2, we present results of simulating the DRAM ope ration of the FinFET. The GIDL tunneling current, controlled by the WL (V G ) and the BL (V D ) voltage pulses, is used to charge the floating body, i.e., write a 1. To write a 0, V G is pulsed up to raise the body voltage (V B ) via capacitive coupling, thus effecting the rem oval of the stored holes by body-source/drain recombination. This write-0 process can be very efficient due to the strong capacitive coupling in the PT-based FinFET FBC which has a negligib le body capacitance. Fo r the read operation, V G is also pulsed up to raise V B to be high enough to turn-on the PT current when the body is charged (read 1); when the body is not charged, V B is lower and no significant PT current is induced (read 0). Since WL is negatively biased during programming and read operations, the gate
76 capacitance (C G ) serves as the charge storage element so that no substrate or independent gate bias is required. We show, also in Fig. 5.2, the predicted current, I DS (t), corresponding to a complete sequential memory ope ration. Negligible programming power is predicted since there is no channel current. The results, with nanoscale-second programming and read times, demonstrate the basic operation of the cell, show ing that stored charge can effe ctively modulate the PT current even at low V D (1V), and yield a good signal margin (~53 A/ m). The functionality of the PT-based FinFET FBC is further confirmed by the predicted programming/read window ( V GS ~ 0.4V) in Fig. 5.3. This I DS vs. V GS (WL pulse) plot is derived from transient (pulsed-V G ) simulations of the read operatio n for stored-1 and stored-0 states. The predicted read-0 curr ent becomes significant only when V GS > -0.3V; this is mainly the MOSFET subthreshold diffusion current (which is unusually hi gh because of the relatively severe SCEs in the PT-c ell FinFET). The low V t and large subthreshold sl ope (SS) are due to the serious SCEs introduced by thick body. C ontrarily, for reading 1, as the V GS increases, significant current occurs due to punch through when V GS 0.8V. For increasing V GS the read1 current is ultimately dominated by the MOSFET subthreshold current, as the read-0 current is, as implied by the disapp earing read window in Fig. 5.3. We find that the predicted read-1 current follows the behavior of space-charge limited current very well. Actually our PT-based FinF ET FBC can be generally modeled by the currentvoltage relation for the ga te-controlled punch-throug h transistor : (5.1) where L is the channel length and A is the devi ce cross-sectional area In  and , V tPT is a function of V GS For our device, V tPT is also modeled as a function of V BS due to the storedcharge modulation. As shown in Fig. 5.4, for the sa me biases as in the memory operation, the ------------(,) =
77 SenTaurus-predicted read-1 cu rrent data follows (5.1) (with calibration) very well, further confirming our conclusion that the read- 1 current is domin ated by punch through. Now we give a general physical explanation on the modulation of flow of PT current by the stored charge in the floating body of the DG FinFET. The onset of the punch-through current requires the body/source potential barrier barrier ) to be low enough for the electrons to be injected from source into the body, where they dr ift to the drain via space charge-limited flow. When the FinFET FBC is in the 1 state, its high V B raised by the stored charged will reduce barrier and turn-on the punch-through current. This is confirmed by the predicted potential distribution of the FinFET FBC from source to drain, as plotte d in Fig. 5.5 for both the 1 and 0 states. As shown in Fig. 5.5, barrier for the 1 state is lower than that for the 0 state, and leads to the noted punch-through current for the 1 state in Fig. 5.3. We also note in Fig. 5.5 that barrier for the thick-body FinFET (t Si =56nm) is much lower than that for a thin-body FinFET (t Si =28nm). The lower barrier in thick-body FinFET is due to DIBL This insight implies that the thin-body FinFET with higher barrier is not viable as a PT-based FBC, which is confirmed by predicted results in Fig. 5.6 that show no f unctional programming/read window of the FinFET (t Si =28nm). As shown in Fig. 5.6, th e read-1 and read-0 curren t curves overlap with each other, both being just the MOSF ET subthreshold current. Compar ed with the thick-body FinFET, the thin-body FinFET shows a higher V t and lower SS since the DIBL is well controlled. The enhanced DIBL effect in the thick-body FinFET pl ays a critical role in enabling a PT-based DRAM operation, even at low V DS Without the DIBL enabling, even though there are holes stored in the floating thin body of the FinFET, no PT current can be triggered. Thus, a thin-body FinFET can only work as a FBC in the BJT-based mode. We reiterate, however, that the BJT-based read operation requires high V DS (>2.5V) for transistor latch. Since the parasitic BJT current gain in the MOSFET is very sma ll (~30 for the thin-body FinFET
78 FBC), high V BS (> 0.8V) is needed to get sufficient (hol e) current margin for the BJT-based read 1. As a result, a high V DS for strong impact ionization and BJT latch is needed to maintain this high V BS otherwise the current will decay very quickly due to significant re combination current. Since PT current mainly consists of the electron current (I electron /I hole >10 5 ) for a thick-body FinFET during read 1), V BS in the PT-based read-1 operation can be much lower than that in the BJT-based read 1. Thus, the PT-based read-1 current will not decay too much during the read operation, even wit hout impact ionization. A dditional simulations conf irm this implication, predicting only a 3% decrea se of read-1 current after 10 read-1 operations. As noted, a thick body is critical for the func tionality of the PT-based FinFET FBC. This could cause a read-0 error. Since a large numbe r of unselected hold-1 cells and the intended read-0 cell share the same BL, to guarantee a valid read-0 ope ration, the total hold-1 leakage current must be significantly smaller than the read-1 current. Thus, the increased hold-1 leakage current due to thick-body c ould be a serious problem for th e viability of PT-based FinFET FBC. Additional simulati ons predict a high hold-1 leakage current (~0.1 A/ m) for the thickbody 1T FinFET FBC, which implies that the num ber of cells that could share the same BL should be less than 500 (i.e., < I read 1/ I hold 1 ). Since typically there are 256 to 1024 cells on one BL of a DRAM array , the viability of th e PT-based 1T-FinFET (with thick body) memory array could be limited. Another problem with the PT -based DRAM cell is the short 0 retention time due to GIDL-based charging under BL disturb. Because GIDL current also serves as the major leakage mechanisms for hold 0 du ring BL disturb time, ther e is little design space to realize a fast GIDLbased program and a long 0 retention . This short 0 retention tim e associated with the GIDL charging is a common problem for all FBCs using GIDL-based charging . Further, note that in the memo ry operation in Fig. 5.2, the WL voltages used for writing 1
79 and writing 0 are different, which implies that row programming is not possible. In the next section, we will propose a 2T st ructure for the PT-based FinFET FBC with new operation bias to solve all the problems noted herein. 5-3 The PT-Based 2T FinFET FBC The basic structure of PT-based 2T FinFET FBC is shown in Fig. 5.7. The cell comprises two serially connected transistors, T1 and T2. T1 works the same as the PT-based 1T FinFET FBC discussed in last section; T2 is a pass transistor that works as a switch controlled by a control line (CL). T2 is turned on to pass BL voltage to T1 during pr ogramming and read operations, and turned off to block the BL disturb to T1 when data is held. We assume T2 to have the same structure as T1; the area penalty due to 2T struct ure is thus relieved since T1 and T2 can share a common source/drain. To improve the switch perfor mance of T2, we may design it with a thinner body to control SCEs better. However, then the noted common source/drain can not be achieved due to the difference of body thickness between T1 and T2; thus, more cell area is the cost. Although the PT-based FBC utilizes FinFETs with thick bodies, its compatib ility to logic FinFET technology is not threatened too much. This is because with the vertical structure, the body thickness of the FinFET is not de termined by the planar SOI thic kness; no additiona l processing is needed for the thick-body device fabrication. Fig. 5.8 shows a SenTaurus-simulated DRAM ope ration for this 2T FBC. Generally, the memory operation is the same as wh at we assumed for the 1T cell, ex cept for the added CL bias as well as a new 2-phase WL pulse used for writing both 1 and 0 . During the first phase of WL pulse, WL is pulsed up to raise V BS and write a 0. During the s econd phase, WL is pulsed down; whether to write 1 or to keep the 0 state is determined by whether a 1V BL pulse is used. We note that the duration of the first WL phase can be very short (~2ns ) because write 0 can be very efficient for our cell. Although this 2-phase WL bias adds complexity to the memory circuit, the
80 same WL voltage can now be us ed for writing both 1 and 0 , enabling row programming and increasing the write speed while eliminating WL -disturb effects. The simulation predicts a negligible current margin drop (~ 3 A) of the 2T FBC compared with that of the 1T cell, due to only small channel resistance of T2 added in reading data. As mentioned earlier, one of the motivations of the 2T cell design is to solve the short 0 retention-time problem associated with BL disturb. The retention of the 2T FBC is e xpected to be greatly improved by introducing the pa ss transistor T2, because it blocks the BL disturb to T1 when T1 is holding data. This is demonstrated by the simulation results in Fig. 5.9, which indicate 0 retention times for the 1T and 2T FBCs under 1V continuous BL stress of 10 s and 20ms, respectively. It is much easier to use continuos BL stress for chec king the worst-case 0 retention than to use the actual pulsing BL disturb. However, we would like to stress that the 0 retention improvement of the 2T cell under ac tual, pulsing BL disturb could be more significant than that in continuous BL stress. As illustrated in Fig. 5.10, when a continuous BL stress is a pplied to the 2T FBC while holding 0, the off current of T2 will charge the parasitic capacitance (C FN ) associated with the fl oating node (FN), until V FN or V D of T1, rises to a quasi -steady level that is determined by the ratio of the re sistance of T1 and T2. This V FN induces GIDL current to charge the floating body of T1. When a pulsing BL distur b is applied, as shown in Fig. 5.10, the off current of T2 will charge C FN when the BL voltage is high, and discharge C FN when the BL voltage is low. Thus, a smaller V FN and longer retention can be expected. Although it is too computationally expensive to di rectly simulate the retention time under BL pulsing, we can estimate it based on the simulation for continuous BL disturb. If we assume a BL pulse with 50% duty cycle, then V FN could be evenly reduced by 50% compar ed with the value for continuous BL disturb, if the ratio of the resistance of T1 a nd T2 in both cases are the same. Thus, we can emulate the 1V BL-pulses distur b by assuming a 0.5V continuos BL stress. For the 1T FBC, since
81 the BL stress is applied to T1 directly, the new BL pulse with 50% dut y cycle can only double the 0 retention time of the continuous BL distur b case. The corresponding simulation results for both cells are shown in Fig. 5.9. An improved 0 retention time longer than 1s for the proposed 2T FBC under pulsing BL distur b is predicted. Even though there are uncertainties in the modeling of the carrier generation and recombin ation that imply some equivocality in the predicted retention time, the signi ficant improvement of worst-case retention time due to the 2T structure is doubtless. In Section 5.2, we showed that the thickbody PT-based FinFET FBC suffers from high hold-1 leakage current that may cause a read-0 error. This pr oblem can also be solved by the introduction of the 2T cell structure. With T2 bl ocking the high BL voltage being passed to T1, the hold-1 leakage current can be reduced signi ficantly; the simulation results predict a 2.8nA/ m for 2T versus 100nA/ m for 1T, which implies that more than 10000 2T cells can share one BL than in the 1T FBC. Thus, the proposed 2T cel l architecture is an ideal design for the PT-based FinFET FBC, not only for long retention times but also for viable memo ry array realization. 5-4 PT-Based Thin-BOX FD/SOI FBC Besides the DG FinFET, the thin-BOX FD/SOI MOSFET, illustrated in Fig. 5.11, is also a promising candidate for future CM OS technology. In this section, we explore the application of our PT-based FBC in this techno logy via numerical simulations us ing SenTaurus, and compare its performance with the counterpart FinFET FBC. We first assume a 1T thin-BOX FD/SOI MOSFET analogous to the Fi nFET we assumed: L g =56nm, t ox =3nm, midgap gates, undoped UTB with t Si =38nm, and t BOX =10nm; the default gate width is 1 m. The cell has a thicker UTB than the nominal t Si (~L g /4 ) that is thin enough to contro l SCEs in a logic cell, in order to have a strong DIBL effect for the PT-based memory effect. The predicted memory operation of this FB C is shown in Fig. 5.12, where the transient
82 pulsings of WL and BL are the same as those for the FinFET-based cell in Fig. 5.2. However, we find that, compared with the Fi nFET counterpart, the sense margin of thin-box FD/SOI FBC is much lower: 13 A/ m vs. 53 A/ m. This can be explained by further analysis of the read-1 operation, during which the WL pulse increases the body voltage via cap acitance coupling. For the FD/SOI FBC, the ultra-thin BOX brings in finite body capacitance whic h limits the increase of V BS By using a thick BOX, FD/SOI FBC exhibits a substantial sense margin increment; as shown in Fig. 5.12, the sense margin of the FBC with 60nm BOX (29 A/ m) is much higher than that for the 10nm-BOX cell. (It is noted that because of the wors e SCEs in the thick-BOX FBC, a thinner UTB (~29nm) was used to maintain a low-level r ead-0 current.) Thus, the thick-BOX FD/SOI MOSFET is more prom ising as a PT-based FBC. However, since the body thickness of the plan ar FD/SOI MOSFET is the thickness of SOI, fabricating the thick-body memory devices and the thin-body logic devices on the same chip would require added processing steps. Thus, th e PT-based planar FD/SOI FBC has a CMOS compatibility disadvantage compared with the counterpa rt FinFET FBC. Besides higher sense margin and better compat ibility, the DG FinFET also has a better GIDL-charging efficiency than that in the planar FD/SOI FBC. It has been reported that the GIDL current in a <110> channel, as common in the FinFET, could be an-order-of-magnitude larger than that in a <100> channel of a FD/SOI MO SFET . Although this advantage of the FinFET FBC is not reflected in our simulations, in wh ich we assumed a <100> channel for both FinFET and FD/SOI MOSFET, we can expect a shor ter write-1 time for the FinFET FBC. 5-5 Summary A novel PT-based 2T DG-FinFET FBC for low V DS operation was presented, and its memory operation was demonstrated and verified via numerical simulations. We noted that the stored-charge in the floating body modulat es the PT current via controlling barrier We also noted
83 that the enhanced DIBL associated with thick body is critical for PT-bas ed memory operation. We designed a PT-based FBC with a 2T structur e, which not only improves the worst-case 0 retention time under BL dist urb but also greatly reduces the hol d 1 leakage current for a viable memory array. We also verified the functionality of a PT-based planar thin-BOX FD/SOI FBC. However, this cell was also noted to suffer from low sense margin, relative to that of the FinFET cell, as well as incompatibilit y with CMOS logic devices. A performance comparison of our PT-based Fi nFET FBC has been made with other 1T or 2T FBCs in Table 5.1. Compared with 1T FBCs, our cell is not limited by the body factor r. It does not require any substrate or independent gate bias. It also shows a reliability advantage by using low V DS Although our cell is larger in size, th ese performance adva ntages nonetheless make it a promising FBC-memory competitor. Co mpared with the other 2T FBCs, i.e., FBGC , our cell shows an obvious process compatibility advantag e since it uses conventional CMOS technology, while T1 in the FBGC is actuall y a gated diode with very long G-D underlap. Although both cells consist of two transistors, our cell takes smal ler area considering the common source/drain of T1 and T2, as well as the long underlap used in FBGC. However, our cell uses a two-phase write programming which is more complex than that in FBGC. In conclusion, our PTbased 2T FinFET FBC coul d be one of the promising candidate s for future capacitorless DRAM.
84 Table 5-1. Performance compar ison among PT-based FinFET FBC, FBGC and 1T FBCs II-based 1T FBC GIDLbased 1T FBC BJT-based 1T FBC FBGC3 (2TFBC) PT-based 2T FinFET FBC Sense Margin ~50 A~30 A~500 A~80 A~50 A Retention Time ~25ms~100 s~800ms~10s~1s Write Time~10ns~10ns<2ns~10ns~15ns Cell Area4F24F24F2>8F28F2Process complexity and Compatability like CMOS like CMOS Bad (Underlap) Bad (Underlap and P+ source) like CMOS Reliabilitylike CMOS like CMOS Very Bad (hot carrier) like CMOS like CMOS
85 Figure 5-1. Structure of PT-b ased DG FinFET FBC with Lg=56nm, tSi=56nm, tox=3nm. A 2nm overlap is designed to enab le GIDL-current charging. Source (SL)Drain (BL) Gate (WL) Gate (WL) tSi pbody
86 Figure 5-2. SenTaurus-predicted DR AM operation of PT-based DG FinFET FBC. The transient pulsings of the word line and bit line of the cell are shown in the top plots. The transient cell currents, which reflect the st ored data, are shown in the bottom plots. 010203040 5060 7080Time (ns) -3 -2 -1 0 1 2 -20 -10 0 10 20 30 40 50 60 70 80 Write 1HoldRead 1 Hold Write 0 HoldRead 0BL WLVoltage (V)010203040 5060 7080Time (ns)IDS ( A/ m) Write 1HoldRead 1 Hold Write 0 HoldRead 0
87 -1-0.9-0.8-0.7 -0.6-0.5 -0.4-0.3-0.2-0.100.1VGS (V) -50 0 50 100 150 200 250IDS ( A/ m) 0.21 state 0 state Figure 5-3. SenTaurus-predicted read-1 and read-0 currents for FinFET FBC with Lg=56nm, tSi=56nm versus VGS; a functional programing/ read window is shown. FinFET w/ Lg=56nm tSi=56nm VDS=1V
88 Figure 5-4. SenTaurusand model-predicted read-1 currents of FinFET FBC versus VDS. The model is described by equation ( 5.1), in which the value of VtPT is calibrated to be 0.2V and 0.41V when VGS=-0.5V and -0.6V respectively; 9 A/L3is calibrated to have a value of 156 A/V2. 0.6 0.70.80.91184.108.40.206.4 1.5 -50 0 50 100 150 200 250 300 Model SenTaurus VDS (V)IDS(read 1) ( A/ m)VGS=-0.5V, VtPT=0.2VVGS=-0.6V, VtPT=0.41V
89 Figure 5-5. SenTaurus-predicted electric potenti al distribution in the center of the body of FinFET FBCs with tSi=56nm and tSi=28nm during read operations. The potential at source is set to be 0V as potential reference. -80 -60 -40-2002040 60 80 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 read 0 read 1 barrier VD=1V VS=0V tSi=28nm tSi=56nmx (nm)Potential (V)VGS=-0.5V
90 -1-0.8 -0.6 -0.4-0.200.20.4 -20 -10 0 10 20 30 40 50 60 70 80 90 100 0.6VGS (V)IDS ( A/ m)1 state 0 state Figure 5-6. SenTaurus-predicte d read-1 and read-0 curr ents for FinFET FBC with Lg=56nm, tSi=28nm versus VGS; no functional programing/r ead window is predicted. FinFET w/ Lg=56nm tSi=28nm VDS=1V
91 Figure 5-7. Structure of PT-based 2T FinFET FBC. T1 is the memory transistor which is serially connected to the pass transistor T2. T2 work s as a switch, that is turned on to pass BL voltage to T1 during write and read operations, and turned off to block BL disturb during hold operation. SL WL WL tSi pbody CL CL tSipbody BLT1 (memory transistor)T2 (pass transistor)Floating Node (FN)
92 Figure 5-8. SenTaurus-predicted DRAM operation of PT-based 2T FinFET FBC. The transient pulsings of the word line, bit line and cont rol line of the cell are shown in the top plots. The transient cell currents, which reflect the stored data, are shown in the bottom plots. 010 203040 5060 708090 100Time (ns)-20 -10 0 10 20 30 40 50 60 70 80IBL ( A/ m) 010 203040 5060 708090 100 -3 -2 -1 0 1 2 3 Time (ns)Voltage (V)Write 1 Read 1 Write 0 Read 0BL WL CLWrite 1Read 1 Write 0 Read 0
93 Figure 5-9. SenTaurus-preidcted worst-case retention times of PT-based 2T and 1T FinFET FBCs under continuous and pulsing BL dist urb. The bias voltage s for the memory operation are the same as those in Fig. 5.8 and Fig. 5.2. 10-910-810-710-610-510-410-310-210-11IBL ( A/ m)Time (s) -10 0 10 20 30 40 50 60 2T w/continuous disturb 2T w/pusling disturb 1T w/continus disturb 1T w/pulsing disturb read 1 read 0 BL disturb =1V for holding 0
94 WL BL SL Icharge WL CL SL IchargeIdischarge BL CL continuous BL disturb pulsing BL disturb 1V 1V 0V FN FN (VBL=1V) (VBL=0V) IGIDL IGIDL Figure 5-10. Ilustrations of how continuous BL disturb and pulsing BL disturb charge the floating body of PT-based 2T FinFET FBC, when 0 is being held.
95 Figure 5-11. Structure of PT-based thin-box FD/SOI nMOSFET FBC with Lg=56nm, tSi=38nm, tox=3nm and tbox=10nm.A 2nm overlap is designed to enable GIDL-current charging. Source (SL)Drain (BL) Gate (WL) thin BOX Substrate pbody
96 Figure 5-12. SenTaurus-predicted transient DRAM operation current s of PT-based 1T FD/SOI FBC with tbox=10n, tSi=38nm and tbox=60n, tSi=29nm. The transien t pulsings of the word line and bit line of the cells are the same as those in Fig. 5.2. 010203040 5060 7080Time (ns)IBL ( A/ m) -10 0 10 20 30 40 50 FDSOI/ tbox=10nm, tSi=38nm FDSOI/ tbox=60nm, tSi=29nm Write 1Read 1 Write 0 Read 0
97 CHAPTER 6 SUMMARY AND FUTURE WORK 6-1 Summary This dissertation is focused on physical anal ysis, modeling, and design of nanoscale DG FinFET-based flash and floating-body DRAM cells. The major contributions of the research are summarized as follows. In Chapter 2, we developed, defined and veri fied a UFDG-based subc ircuit model for the paired-FinFET flash memory (VsNAND) cell, ta king into account the fin-fin charge-coupling effect. The model accurately predicted the sensit ivities to process-induced parameter variations and the fin-fin charge coupling. The subcircuit model was used to successfully simulate the VsNAND-array (string) operations, predicting correct values of Best On-Cell Current, Worst OnCell Current, and Off-Cell Current. Finally, the m odel was easily extended to be applicable to the floating-gate flash. This compact physics/pro cess-based model is useful for checking and analyzing the signal margins and process sensitiv ities for the VsNAND FLASH array, as well as for aiding the paired-FinFET design. In Chapter 3, we examined the memory -margin dependences on UTB thickness of nanoscale planar thin-BOX FD /SOI and quasi-planar DG FinFET FBCs cells and attained physical insights. We found that the thin-BOX FD /SOI FBC suffers from abrupt current-signal margin degradation with UTB scaling because of loss of body accumulation charge, as well as loss of inversion charge due to increased threshold voltage. Further, thin t Si with the needed accumulation, yields high transver se electric field, which leads to mobility degradation and additional loss of margin. We also found that the DG FinFET FBC suffers from nominally low signal margin due to a relatively low, 2-D effect ive body coefficient, as well as gradual margin
98 loss with fin-UTB scaling due to loss of accumu lation charge at the base of the fin. Both 1TDRAM cells hence seem to have limited scalability. In Chapter 4, we analyzed the basic operati on of BJT-based 1T DRAM cells on SOI, and derived physical insights. We found that the charging process (write 1) is extremely sensitive to the time offset ( t WB ) between the word-line a nd bit-line voltage pulses. We noted and explained that a positive t WB is necessary for successful write 1 because it establishes a high gate capacitance, which is the predominant charge-sto rage element in the BJT-based cell. We noted that the role the gate capacitance plays enables fully depleted bodies without independent biasing for accumulation charge to be used. We noted a bulk-accumulation effect that may undermine the BJT and cell operations for thin t Si resulting in loss of current margin and ultimate write-1 failure. Considering sensitivities to process parameters, we argued that PD/SOI is not viable for scaling down, while a FDbody device, such as the FD/SOI MOSFET or FinFET, will be needed in the future. We noted that the serious hot-carrier reliability issues, due to the high drain voltage (V DS ) required for BJT latch, limit the viab ility of BJT-based capacitorless DRAM. In Chapter 5, we proposed a novel PT-based 2T DG-FinFET FBC for low-V DS operation, and demonstrated and verified its memory operation via numerical simulations. We showed that this FBC offers low-power operation, high sense margin, long worst-case retention times, and good compatibility for embedded memory applicat ions in future nanoscale CMOS technology. We provided physical insights on the PT-based memo ry effect that depends on the modulation of PT current by the stored-charge in the floating body via controlling barrier We noted that the enhanced DIBL associated with a thick body of the FinFET is cr itical for PT-based memory operation. We designed a PT-based FBC with a 2T structure, which not only improves the worstcase 0 retention time under BL disturb but also greatly redu ces the hold-1 leakage current for a viable memory array. We also verified the func tionality of a PT-based pl anar thin-BOX FD/SOI
99 FBC. However, we found that, compared with the FinFET counter part, FD/SOI FBC suffers from lower sense margin due to its finite body capacitance, worse CMOS compatibility, and lower GIDL-charging efficiency due to its planar structure. 6-2 Future Work In Chapter 2, we developed and verified a UF DG-based subcircuit model for the pairedFinFET flash memory cell, taking into account the fin-fin charge-coupling effect. This model is useful in simulating the flash array read operation, and for pred icting and analyzing the signal margins and process sensitivities. However, th is model is incapable of simulating the FLASH write and erase operations. Thus we had to assume a certain amount of charges stored in the nitride layer of the ONO stack to distinguish the programmed and erased transistors. This model should be extended for simulati ng the complete flash memory op erations, including the write and erase operations. In Chapter 5, we proposed a novel PT-b ased 2T DG-FinFET FBC for low-V DS operation. We used numerical simulation to demonstrate th e memory operation of this 2T FBC and predict the memory performance. In the future, experi mental demonstration of the DRAM operation of the PT-based FBC should be done to further ve rify its viability. Al though we have already proposed a 2T cell structure to im prove the retention time, optimizat ion of process should also be considerated for the actual FBC to minimize the junction recombinat ion characteristics for longer retention times. To gua rantee good yield and memory performan ce, a thorough examination of the sensitivities of the PT-based FinFET FBC to pr ocess-induced parameter variations should be made. And, since the proposed PT-based FBC ut ilizes FinFET-on-SOI technology for future embedded memory applications, the relevant circuit for the sense am plifier, and biases, should be designed based on FinFET technology.
100 LIST OF REFERENCES  I nternational Technology Roadmap for Semiconductors Semiconductor Industry Association, Austin, TX, 2007.  K. Kim and G. Jeong., Memory T echnologies for Sub-40nm Node, IEDM Tech. Dig. pp. 27-30, Dec. 2007.  J. G. Fossum, L. Q. Wang, J-W. Yang, S.-H. Kim, and V. P. Trivedi, Pragmatic Design of Nanoscale Multi-gate CMOS, IEDM Tech. Dig. pp. 613-616, Dec. 2004.  I nternational Technology Roadmap for Semiconductors Semiconductor Industry Association, Austin, TX, 2005.  K. Kim, Technology for Sub-50 nm DR AM and NAND Flash Manufacturing, IEDM Tech. Dig. pp. 323-326, Dec. 2005.  J.-M. Koo, et al., Vertical St ructure NAND Flash Array In tegration with Paried Fin FET Multi-bit Scheme for High-densit y NAND Flash Memory Application, Proc. VLSI Symp. ,pp. 120-121, June 2008.  S. Lombardo, et al., Advantages of the FinFET Architecture in SONOS and Nano crystal Memory Devices, IEDM Tech. Dig pp. 921-924, Dec. 2007.  P. Xuan, et al., FinFET SONOS Flas h Memory for Embedded Applications, IEDM Tech. Dig. pp. 609-613, Dec. 2003.  C. W. Oh, et al., Damascene Gate Fi nFET SONOS Memory Implemented on Bulk Silicon Wafer, IEDM Tech. Dig. pp. 893-896, Dec. 2004.  S. Kim, et al., Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage, Proc. VLSI Symp. pp. 104-106, June 2006.  K. Kim and J. Choi, Future Outlook of NAND Flash Technology for 40nm Node and Beyond, IEEE NVSMW pp. 9-11, 2006.  L. Perniola, et al., Physical Model fo r NAND Operation in SOI and Body-Tied Nanocrystal FinFLASH Memory, IEDM Tech. Dig pp. 943-946, Dec. 2007.  H. Lee, et al., Fully Integrated an d Functioned 44nm DRAM Technology for 1GB DRAM, Symp. VLSI Tech. Dig. pp. 86-87, June 2008.  Mat06a J.Y. Kim, et al., The Breakthrough in Da ta Retention Time of DRAM Using RecessChannel-Array Transistor (RCAT) for 88nm Featur e Size and Beyond, Symp. VLSI Tech. Dig. pp. 11-12, June 2003.  S.-W. Chung, et al, Highly Scalable Saddl e-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology, Symp. VLSI Tech. Dig., pp. 32-33, June 2008.
101  S. Jeannot et. al., Toward Next High Performance MIM Generation: up to 30fF/ m 2 with 3D Architechture and High-k Materials, IEDM Tech. Dig. pp. 997-1000, Dec. 2007.  T.S. Boscke, et al., Tetragonal Phase Stab ilization by Doping as an Enabler of Ther mally Stable HfO 2 based MIM and MIS Capacitors for Sub-50nm Deep Trench DRAM, IEDM Tech. Dig., pp. 1-4, Dec. 2006.  H.-J. Wann and C. Hu, A Capacitorl ess DRAM Cell on SOI Substrate, IEDM Tech. Dig. pp. 635-638, Dec. 1993.  S. Okhonin, M. Nagoga, J.M. Sallese, and P. Fazan, A SOI Capa citor-less 1T-DRAM Concept, Proc. IEEE Internat. SOI Conf., pp. 153-154, Oct. 2001.  I. Ban, et al., Floating Body Cell with Independently-controlled Double Gates for High Density Memory, IEDM Tech. Dig. pp. 573-576, Dec. 2006.  R. Ranica, et al., A One Transistor Ce ll on Bulk Substrate (1T-Bulk) for Low Cost and High Density eDRAM, Symp. VLSI Tech. Dig., pp. 128-129, June 2004.  T. Shino, et al.,Floating B ody RAM Technology and its Scalability to 32nm Node and Beyond, IEDM Tech. Dig., pp. 281-284, Dec. 2004.  Tri03 S. Okhonin, et al., FinFET Based Zero-C apacitor DRAM (Z-RAM) Cell for Sub 45nm Memory Generations, Proc. Internat. Conf. Memo ry Tech. and Design (ICMTD). pp. 63-65, May 2005.  T. Shino, et al., Floating Body RAM Tec hnology and Its Scalability to 32nm Node and Beyond, IEDM Tech. Dig. pp. 569-572, Dec. 2006.  Tri05b U.E. Avci, et al, Floating Body Ce ll (FBC) Memory for 16-nm Technology with Low Variation on Thin Silicon and 10nm BOX, Proc. IEEE Internat. SOI Conf. pp. 29-30, Oct. 2008..  N.Collaert, et al., Analysis of Sense Margin and Reliabil ity of 1T DRAM Fabricated on Thin-film UTBOX Substrate, Proc. IEEE Internat. SOI Conf. Oct. 2009  Lee05 I. Ban, et al., A Scaled Floating Body Cell (F BC) Memory with High-K+Metal Gate on Thin-silicon and Thin-BOX for 16nm Technology Node and Beyond, VLSI Symp. Tech. Dig., pp. 92-93, June 2008.  Kim06 M. Nagoga, et al., Retention Characteristics of Zero-capacitor RAM (Z-RAM) Cell Based on FinFET and Tri-gate Devices, Proc. IEEE Internat. SOI Conf., pp. 203204, Oct. 2005.  J. G. Fossum, Z. Lu and V. P. Trivedi, New Insights on Cap acitorless Floating-body DRAM cell, IEEE Electron Device Lett. vol. 28, pp. 513-516, June 2007.  S. Okhonin, et al.,, New Generation of Z-RAM, IEDM Tech. Dig. pp. 925-928, Dec. 2007.
102  S. Okhonin, et al.,, Ultra-scaled Z-RAM cel, Proc. IEEE Internat. SOI Conf., pp. 157-158, Oct. 2008.  K.-W. Song, et al., 55 nm Capacitor-less 1T DRAM Cell Transist or with Non-overlap Structure, IEDM Tech. Dig., pp. 797-800, Dec. 2008.  T.-S. Jang, et al., Highly Scalable Z-RAM with Remarkably Long Data Retention for DRAM Application, Proc. VLSI Symp. pp. 234-235, June 2009.  A. Singh, et al, A 2ns-read-latency 4Mb Embedded Floating-body Memory Macro in 45nm SOI Technology, ISSCC Dig. Tech. pp. 460-462, Feb. 2009.  Z. Zhou, J. G. Fossum and Z. Lu, Physical Insights on BJT-Based 1T DRAM Cells, IEEE Electron Device Lett vol. 30, pp. 565-567, May 2009.  K. Kim, The Future Prospect of Semiconductor Nonvolatile Memory, Symp. VLSITSA-Tech. pp. 88-94, Apr. 2005.  J.-D. Lee, S.-H. Hur, and J.-D. Choi, Eff ects of Floating-gate Interference on NAND Flash Memory Cell Operation, IEEE Electron Device Lett vol. 26, pp. 264-266, May 2002.  Y. Shin, et al.,A Novel NAND-type MONOS Memory using 63 nm Process Technology for Multi-gigabit Flash, IEDM Tech. Dig., pp. 327-330, Dec. 2005.  Tau98 Y. Park, et al., Highly Manufacturable 32 Gb Multi-level NAND Flash Mem ory with 0.0098 m 2 Cell Size using TANOS (Si-Oxide-Al 2 O 3 -TaN) Cell Tech nology, IEDM Tech. Dig. pp. 11-13, Dec. 2006.  T. Sugizaki, et al., Novel Multi-bit SONOS Type Flash Memory Using a Highk Charge Trapping Laye, Proc. VLSI Symp., pp. 27-28, June 2003.  S. K. Sung, et al.,SONOS-type FinFET Device Using P+ Poly-Si Gate and High-K Blocking Dielectric Integrated on Cell Array and GSL/SSL fo r Multi-Gigabit NAND Memory, Proc. VLSI Symp. ,pp. 86-87, June 2008.  J. R. Hwang, et al., 20 nm Gate Bulk-FinFET SONOS Flash, IEDM Tech. Dig. pp. 154-157, Dec. 2005.  M. Specht, et al., 20nm Tri-gate SONOS Memory Cells with Multi-level Opera tion, IEDM Tech. Dig. pp. 1083-1087, Dec. 2004.  S.-H. Lee, et al., Improved Post-c ycling Characteristic of FinFET NAND Flash, IEDM Tech. Dig. pp.33-36, Dec. 2006.  J. G. Fossum, UFDG MOSFET MODEL (Ver 3.7) Users Guide, SOI Group, Univ. Florida, Gainesville, July 2007.  Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices Cambridge, U.K.: Cambridge Univ. Press, 1998.
103  V. P. Trivedi, J. G. Fossum, and W. Zhang, Threshold Voltage and Bulk-inversion Effects in Nonclassical CMOS Device s with Undoped Ultra-thin Bodies, Solid-State Electron. vol. 51, pp. 170-178, Jan. 2007.  Z. Lu and J. G. Fossum, Short-Channe l Effects in Independent-Gate FinFETs, I EEE Electron Device Lett., vol. 28, pp.145-147, Feb. 2007.  J. W. Hyun, NAND Array/String, SAIT Document, Feb. 2007.  I.S. Joe VsNAND Array Structure, SAIT Document, Jun. 2007.  Taurus-2006 Users Manual Durham, NC: Synopsys, Inc., 2006.  V. P. Trivedi and J. G. Fossum, Scaling Fully Depleted SOI CMOS, IEEE Trans. Electron Devices vol. 50, pp. 2095-2103, Oct. 2003.  J.-W. Yang and J. G. Fossum,. On the Feas ibility of Nanoscale Triple-gate CMOS Transistors, IEEE Trans. Electron Devices vol. 52, pp. 1159-1164, June 2005.  S. Chouksey, J. G. Fossum, and S. Agrawa l, Insights on Design and Scalability of Thin-BOX FD/SOI CMOS, IEEE Trans. Electron Devices vol. 57, p. 2073-2078, Sep. 2010.  K.-R. Choi, et al., Dependen ce of Memory Margin of Ca p-less Memory Cells on Top Si Thickness, Appl. Phys. Lett. vol. 94, 023508 (online), 2009.  H. K. Lim and J. G. Fossum, Threshold Voltage of Thin-film Silicon-on-insulator (SOI) MOSFETs, IEEE Trans. Electron Devices vol. 30, pp. 1244-1251, Oct. 1983.  K. I. Na, et al., Gate-i nduced Floating-body Effect (GIFBE ) in Fully Depleted Triplegate n-MOSFETs, Solid State Electron. vol. 53, pp 150-153, Feb. 2009.  Z. Lu, et al., A Novel Two-transistor Floating-body/gate Cell for Low-power Nano scale Embedded DRAM, IEEE Trans. Electron Devices vol. 55, pp. 1511-1518, June 2008.  Z. Lu, et al., A Simplified, Supe rior Floating-body/gate DRAM Cell, IEEE Electron Device Lett. vol. 30, pp. 282-284, Mar. 2009  J. G. Fossum, et al., Anomalous Subthr eshold Current-Voltage Characteristics of n-Channel SOI MOSFET, IEEE Electron Device Lett, vol. 8, pp. 544-546, Nov. 1987.  J.-Y, Choi and J.G. Fossum, Analysis a nd Control of Floating-Body Bipolar Effects in Fully Depleted Submicrometer SOI MOSFETs, IEEE Trans. Electron Devices, vol. 38, pp. 1384-1391, June 1991.  J. G. Fossum, A Unified Process-Base d Compact Model for Scaled PD/SOI and Bulk-Si MOSFETs, Tech. Proc. Fifth Internat. C onf. on Modeling and Simulation of Microsystems (WCM) pp. 686-689, Apr. 2002.
104  A. Aoulaiche, et al, BJT Mode Endur ance on a 1T-RAM Bulk FinFET Device, IEEE Electron Device Lett vol.31, pp. 1380-1382, Dec. 2010.  R.J.T. Bunyan, M.J. Uren, N.J. Thomas a nd J.R. Davis, Degradation in Thin-Film SOI MOSFETs Caused by Si ngle-Transistor Latch, IEEE Electron Device Lett vol. 11, pp. 359-361, Sept. 1990.  Z. Zhou, J. G. Fossum, Z. Lu, "Physical Insights on the Memory Margin of Scaled (Fully Depleted) Floating-body 1T DR AM Cells," to be submitted to IEEE Trans. Electron Devices  M. Aoulaiche, et al., Reliability Study in Capacitorless 1T-RAM Cells on SOI, Proc. IEEE Internat. SOI Conf., pp. 157-158, Oct. 2010.  Z. Lu, J. G. Fossum and Z. Zhou, "A Floating-body/gate DRAM cell Upgraded for Long Retention Time," to be submitted to IEEE Electron Device Lett.  K.-Y. Fu and Y. L. Tsang, On the Pu nchthrough Phenomenon in Submicron MOS Transistors, IEEE Trans. Electron Devices vol. 44, pp. 847-855, May 1997.  B. M. Wilamowski and R. C. Jaeger, The Lateral Punch-through Transistor, IEEE Electron Device Lett. vol. 3, pp. 277-280, Oct. 1982.  B. M. Wilamowski, The Punch-through Tr ansistor with MOS Controlled Gate, phys. stat.sol. (a), vol. 79, pp. 631-637, 1983.  X. Li, et al., Gate-controlled Punch Through Transistor, University/Government/ Idustry Microelectronics Symposium, pp. 226-229, Sep. 2003.  K. E. Moselund et al., Punch-through Im pact Ionization MOSFET (PIMOS): From Devie Principle to applications, Solid-State Electronics vol. 52, pp. 1336-1344, Sep. 2008.  SenTaurus-2010 Users Manual Mountain View, CA: Synopsys, Inc., 2010.  Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices Cambridge, U.K.: Cambridge Univ. Press, 2009.  E. Yoshida and E. Tanaka, A Capacitorless 1T-DRAM Technology Using Gateinduced Drain-leakage (GIDL) Current for Low-power and High-speed Embedded Memory, IEEE Trans. Electron Devices vol. 53, p. 692-697, Apr. 2006.  R. K. Pandey et al, Crystallographicorientation-dependent Gate-induced Drain Leakage in Nanoscale MOSFETs, IEEE Electron Device Lett. vol. 57, pp. 20982105, Sep. 2010.
105 BIOGRAPHICAL SKETCH Zhenming Zhou was born in Huinan, China in 198 1. He received the Ba chelor of Science and Master of Science in in opt ical and electrical info rmation engineer from Zhejiang University, Hangzhou, China in 2004 and 2006. He did his Doctor of Philosophy in electrical and computer engineering at the University of Fl orida, Gainesville. His research interest concerns device theory, modeling and design of non-classi cal silicon-on-insulator (SOI) and multi-gate MOSFET, for both memory and l ogicapplications.