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Physical Analysis and Design of Nanoscale Floating-Body Dram Cells

Permanent Link: http://ufdc.ufl.edu/UFE0042135/00001

Material Information

Title: Physical Analysis and Design of Nanoscale Floating-Body Dram Cells
Physical Description: 1 online resource (120 p.)
Language: english
Creator: Lu, Zhichao
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2010

Subjects

Subjects / Keywords: capacitorlessdram, doublegatefinfet, floatingbodycell, floatingbodyeffects, gidl, soimosfet
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation addresses physical analysis and design issues of nanoscale floating-body cells (FBC), which are also known as capacitorless dynamic random-access memory(DRAM) cells. A novel two-transistor floating-body/gate cell (FBGC), and upgraded versions of it, are proposed and experimentally demonstrated. As the conventional one-transistor and one-capacitor (1T/1C) DRAM technology is aggressively scaled, novel device structures and materials have to be introduced to meet International Technology Roadmap for Semiconductors (ITRS) performance requirements. Novel device structures and materials bring a lot of processing and integration challenges to current complementary metal-oxide-semiconductor (CMOS) technology. To avoid these challenges, capacitorless DRAM, which is based on silicon-on-insulator (SOI) CMOS including partially depleted (PD) and fully depleted (FD) MOS transistors (MOSFETs), is attracting a lot of interest. This technology, which uses the floating body of the SOI MOSFET as the storage element, can potentially replace the conventional 1T/1C DRAM cell in the near future. The basic working principle of the FBC is to utilize the floating-body effect inherent in the PD/SOI MOSFET; the FD/SOI MOSFET also shows the floating-body effect when the substrate, or back gate is biased for accumulation. However, the physical explanation of the floating-body effect in the FD/SOI device is not clear. Based on numerical simulations, physical insights are gained on the effect and on FBC performance, e.g., the sense margin. Relying on the physical insights of the floating-body effects, a novel two-transistor(2T) FBC is proposed. By using the first transistor?s (T1) body to directly drive the second transistor?s gate, the 2T FBC eliminates the body-factor limitation on the sense margin. The memory performance is demonstrated with the University of Florida physics-based compact double-gate MOSFET model (UFDG). The predicted results show that the common impact ionization-based write method produces too much power dissipation. To resolve this problem, the 2T-FBC is refined to Ver. 1 of the floating-body/gate cell(FBGC1). The major feature of FBGC1 is the source tied source to the drain in T1. To improve the manufacturability of FBGC1, Ver. 2 (FBGC2) is proposed, which in essence is a gated diode (T1) plus a conventional transistor (T2). Gate-induced drain leakage (GIDL)current is used to write ?1? in FBGC2. The performance is demonstrated by 90nm FinFET technology and also by numerical simulation. One issue with FBGC2 is the short retention time with bit-line (BL) disturbs. Hence Ver. 3 (FBGC3) is proposed to the resolve this problem. Unlike FBGC2 which accumulates the channel to get GIDL charging current, FBGC3 inverts the channel and introduces tunneling current at the source side for charging, thereby separating the charging mechanisms for write and hold. By optimizing the device structure, FBGC3 demonstrates ~10s retention time with worst-case disturb. To make FBGC3 operate faster, Ver. 4 (FBGC4) is proposed. In FBGC4, T1 reverts back to a normal transistor. However, special designs are made at the source side; n+ and p+ regions are used to tie the source to the body. The performance, with ~100ps write/read times, is analyzed by the University of Florida physics-based compact SOI MOSFET model (UFPDB).
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Zhichao Lu.
Thesis: Thesis (Ph.D.)--University of Florida, 2010.
Local: Adviser: Fossum, Jerry G.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2011-12-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2010
System ID: UFE0042135:00001

Permanent Link: http://ufdc.ufl.edu/UFE0042135/00001

Material Information

Title: Physical Analysis and Design of Nanoscale Floating-Body Dram Cells
Physical Description: 1 online resource (120 p.)
Language: english
Creator: Lu, Zhichao
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2010

Subjects

Subjects / Keywords: capacitorlessdram, doublegatefinfet, floatingbodycell, floatingbodyeffects, gidl, soimosfet
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation addresses physical analysis and design issues of nanoscale floating-body cells (FBC), which are also known as capacitorless dynamic random-access memory(DRAM) cells. A novel two-transistor floating-body/gate cell (FBGC), and upgraded versions of it, are proposed and experimentally demonstrated. As the conventional one-transistor and one-capacitor (1T/1C) DRAM technology is aggressively scaled, novel device structures and materials have to be introduced to meet International Technology Roadmap for Semiconductors (ITRS) performance requirements. Novel device structures and materials bring a lot of processing and integration challenges to current complementary metal-oxide-semiconductor (CMOS) technology. To avoid these challenges, capacitorless DRAM, which is based on silicon-on-insulator (SOI) CMOS including partially depleted (PD) and fully depleted (FD) MOS transistors (MOSFETs), is attracting a lot of interest. This technology, which uses the floating body of the SOI MOSFET as the storage element, can potentially replace the conventional 1T/1C DRAM cell in the near future. The basic working principle of the FBC is to utilize the floating-body effect inherent in the PD/SOI MOSFET; the FD/SOI MOSFET also shows the floating-body effect when the substrate, or back gate is biased for accumulation. However, the physical explanation of the floating-body effect in the FD/SOI device is not clear. Based on numerical simulations, physical insights are gained on the effect and on FBC performance, e.g., the sense margin. Relying on the physical insights of the floating-body effects, a novel two-transistor(2T) FBC is proposed. By using the first transistor?s (T1) body to directly drive the second transistor?s gate, the 2T FBC eliminates the body-factor limitation on the sense margin. The memory performance is demonstrated with the University of Florida physics-based compact double-gate MOSFET model (UFDG). The predicted results show that the common impact ionization-based write method produces too much power dissipation. To resolve this problem, the 2T-FBC is refined to Ver. 1 of the floating-body/gate cell(FBGC1). The major feature of FBGC1 is the source tied source to the drain in T1. To improve the manufacturability of FBGC1, Ver. 2 (FBGC2) is proposed, which in essence is a gated diode (T1) plus a conventional transistor (T2). Gate-induced drain leakage (GIDL)current is used to write ?1? in FBGC2. The performance is demonstrated by 90nm FinFET technology and also by numerical simulation. One issue with FBGC2 is the short retention time with bit-line (BL) disturbs. Hence Ver. 3 (FBGC3) is proposed to the resolve this problem. Unlike FBGC2 which accumulates the channel to get GIDL charging current, FBGC3 inverts the channel and introduces tunneling current at the source side for charging, thereby separating the charging mechanisms for write and hold. By optimizing the device structure, FBGC3 demonstrates ~10s retention time with worst-case disturb. To make FBGC3 operate faster, Ver. 4 (FBGC4) is proposed. In FBGC4, T1 reverts back to a normal transistor. However, special designs are made at the source side; n+ and p+ regions are used to tie the source to the body. The performance, with ~100ps write/read times, is analyzed by the University of Florida physics-based compact SOI MOSFET model (UFPDB).
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Zhichao Lu.
Thesis: Thesis (Ph.D.)--University of Florida, 2010.
Local: Adviser: Fossum, Jerry G.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2011-12-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2010
System ID: UFE0042135:00001


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1 PHYSICAL ANALYSIS AND DESIGN OF NANOSCALE FLOATING-BODY DRAM CELLS By ZHICHAO LU A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2010

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2 2010 Zhichao Lu

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3 To my parents

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4 ACKNOWLEDGEMENTS This thesis is a collection of my five "memory" years at Gainesville. It is not only myresearchwork,butalsoadvice,encouragement,guidanceandunrelentingsupportfrom ProfessorJerryG.Fossumwhoservedasmyadvisorduringthepastfive"memory"years. Ihavemymostsinceregratitudetohim.Hisinsights,enthusiasm,approachestoproblems, and being a role model as a researcher and as a person will set the highest standards that I will be aspiring to always. Iwouldalsoliketoextendmysinceregratitudetothemembersofmysupervisory committee (Professors Robert Fox, Jing Guo, Scott E. Thompson, Amlan Biswas and Art Hebard) for their guidance and willing service. I would like to thank my mentor at IMEC, Dr. Malgorzata Jurczak, for her insightful perspective on research and encouragement. I would like to express my gratitude to my colleagues, Dr. Nadine Collaert and Marc Aoulaiche, for their technical disscusions and friendships. I am grateful to the Freescale Semiconductor Inc., Samsung Electronics and SEMATECHfortheirtechnicalandfinancialsupport.Especially,IthankDr.RustyHarris and Dr. Ji-Woon Yang at SEMATECH for providing silicon devices for measurements. I would also like to thank my fellow students, Murshed M. Chowdhury, Weimin Zhang,Seung-HwanKim,VishalTrivedi,ShishirAgrawal,SiddharthChouksey,Zhenming Zhou, Dabraj Sarkar for their insightful and technical discussions and friendships. I must sayIamfortunatetohaveknownallthefriendsherewhohaveencouragedandcheeredme upthroughoutalltheyears.Especially,IthankDr.WeiminZhangforhelpingalotwhenI first came to Gainesville.

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5 IwouldliketothanktomylovelygirlfriendMeiZhao.Iamreallygratefulforher companionship and for her being so kind and supportive. Meeting her could be one of the most wonderful things when I was in Gainesville. This work would not have been possible without the unyielding support of my parents. I am deeply indebted to them for their love and support.

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6 TABLE OF CONTENTS page ACKNOWLEDGEMENTS............................................................................................................4 LIST OF TABLES................................................................................................................ ..........8 LIST OF FIGURES............................................................................................................... .........9 LIST OF ABBREVIATIONS......................................................................................................11 ABSTRACT...................................................................................................................... ............13 CHAPTER 1 INTRODUCTION.......................................................................................................15 1.1 Scaling Difficulties with Conventional DRAM Cell..........................................15 1.2 Capacitorless DRAM.........................................................................................17 1.3 New Physical Insights on "Capacitorless" DRAM Cell......................................20 2 TWO-TRANSISTOR FLOATING-BODY/GATE CELL: A NOVEL LOW-POWER NANOSCALE EMBEDDED DRAM CELL.................................................................30 2.1 Introduction......................................................................................................30 2.2 Two-Transistor Floating-Body Cell Concept.....................................................32 2.3 Performance Evaluation of the Floating-Body/Gate Cell....................................36 2.4 Summary...........................................................................................................41 3 "P+ SOURCE" FLOATING-BODY/GATE CELL: A MANUFACTURABLE NANOSCALE EMBEDDED DRAM CELL.................................................................54 3.1 Introduction......................................................................................................54 3.2 "P+ Source" Floating-Body/Gate Cell Concept..................................................54 3.3 Operation and Performance of the "P+ Source" Floating-Body/Gate Cell...........55 3.4 Experimental Demonstration of the "P+ Source" Floating-Body/ Gate Cell.......56 3.5 Summary...........................................................................................................57 4PHYSICAL INSIGHTS AND MODELING OF GATE-INDUCED DRAIN LEAKAGE CURRENT IN FLOATING-BODY CELL...................................................................67 4.1 Introduction......................................................................................................67 4.2 Non-Quasi-Static Hole Redistribution and Its Effect on Gate-Induced Drain Leakage Current................................................................................................68 4.3 Body-Bias Dependence of Gate-Induced Drain Leakage Current.......................69 4.4 Model Development for Body Bias-Dependent Gate-Induced Drain Leakage

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7 Current..............................................................................................................71 4.5 Summary...........................................................................................................74 5FLOATING-BODY/GATE CELLS UPGRADED FOR ULTRA-LONG RETENTION TIME AND ULTRA-FAST WRITE TIME..................................................................81 5.1 Introduction......................................................................................................81 5.2 FloatingBody/Gate Cell Upgraded for Ultra Long Retention Time.................81 5.3 Floating-Body/Gate Cell Upgraded for Ultra Fast Write Time.......................... 90 5.4 Comparison of the Floating-Body DRAM Cells................................................ 92 5.5 Summary...........................................................................................................94 6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK.......................................110 6.1 Summary..........................................................................................................110 6.2 Suggestions for Future Work............................................................................113 LIST OF REFERENCES............................................................................................................ 115 BIOGRAPHICAL SKETCH......................................................................................................120

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8 LIST OF TABLES T able page 2-1Charging/discharging-current comparison between the FBGC and 1T FBCs...................53 5-1Performance comparison among the FBGC3, FBGC4 and 1T FBCs.............................109

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9 LIST OF FIGURES Figure page 1-1Predicted operation (with IGi body charging) of the IG-FinFET FBC . . 27 1-2Predicted hole density along the back surface . . . . . . . .28 1-3Sketch of the perturbation of the energy-band diagram. . . . . . .29 2-1The 2T oating-body cell (FBC) in a DRAM array. . . . . . . .43 2-2Schematic cross-sectional view of a 2T (n-channel) FBC fabricated . . . .44 2-3UFDG/Spice3-predicted transient sequential operation of a 2T FBC. . . .45 2-4Transient sequential operation of a 2T FBC. . . . . . . . . .46 2-5The FBGC structure in a DRAM array . . . . . . . . . .47 2-6Transient sequential memory operation of an FBGC as depicted in Fig. 2.5. . .48 2-7UFDG/Spice3-predicted transient sequential memory operation of a 2T FBGC .49 2-8UFDG/Spice3-predicted transient sequential memory operation of the 2T FBGC. .50 2-9Worst-case data retention/disturb characteristics of the 2T FBGC in Fig. 2.7. . .51 2-10UFDG/Spice3-predicted BL2 read-voltage and T2 read-current. . . . . .52 3-1The simplied FBGC structure, on SOI, in a DRAM array with two bit lines.. . .59 3-2Transient sequential memory operation of the new FBGC structure . . . .60 3-3Cross-section TEM of the FinFET structure used for both T1 and T2 . . .61 3-4Measured current-voltage characteristics of the p+p-n+ gated diode . . . .62 3-5Measured current-voltage characteristicsof the double-gate nFinFET. . . .63 3-6Circuit configuration of the measurement setup. . . . . . . .64 3-7Measured transient sequential write/hold/read operations for and . .65 3-8Measured transient sequential write/hold/read operations for and . .66 4-1Drain current-gate voltage characteristics of T1 and holes distribution. . .76

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10 4-2Measured dependence of the GIDL current on the body voltage . . . .77 4-3Cross section of gated diode. . . . . . . . . . . .78 4-4Band diagram at the overlap region along the vertical direction. . . . .79 4-5Band diagram along the vertical direction with accumulation and depletion .80 5-1The FBGC3 structure, on SOI, in a DRAM array with two bit lines. . . . .95 5-2SenTaurus-predicted BTB tunneling current in T1.. . . . . . . .96 5-3BTBT currents with different G-D underlap predicted by SenTaurus. . . . .97 5-4ID-VD characteristics of T1 predicted by SenTaurus.. . . . . . . .98 5-5ID-VG characteristics of T2 predicted by SenTaurus.. . . . . . . .99 5-6Transient sequential memory operation of a FBGC3 cell.. . . . . . .100 5-7Worst-case charge/data retention characteristics of the FBGC3. . . . .101 5-8TransientsequentialmemoryoperationoftheFBGC3withBL1andBL2tietogether102 5-9Transient sequential memory operation of the FBGC3 with optimal pulses. . .103 5-10Transient sequential memory operation of the FBGC3 with no spacer of T1.. . .104 5-11Data retention characteristics of FBGC3 . . . . . . . . .105 5-12Sense margin, ID of T2, and max. number of cells vs. gate work-function of T2.. .106 5-13The FBGC4 structure in a DRAM array with two BLs.. . . . . . .107 5-14Transient sequential memory operation of a FBGC4 cell.. . . . . . .108

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11 LIST OF ABBREVIATIONS 1T FBCone-transistor floating-body cell 2T FBCtwo-transistor floating-body cell BJTbipolar junction transistor BTBTband to band tunnelling CMOScomplementary metal-oxide-semiconductor DGdouble-gate DIBLdrain-induced barrier lowering DOSdensity of states DRAMdynamic random access memory FBfloating body FBCfloating-body cell FBGC1floating body/gate cell Ver. 1 FBGC2floating body/gate cell Ver. 2 FBGC3floating body/gate cell Ver. 3 FBGC4floating body/gate cell Ver. 4 FDfully depleted FETfield-effect transistor GIDLgate-induced drain leakage ITFETFinFET-based inverted-T FET LOPlow operating power LSTPlow standby power MOSFETmetal-oxide-semiconductor field-effect transistor nFETn-type field-effect transistor

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12 nFinFETn-type FinFET nITFETn-type ITFET nMOSFETn-type MOSFET PDpartially depleted pFETp-type field-effect transistor pMOSFETp-type MOSFET SCEshort-channel effect SGsingle gate SOIsilicon-on-insulator SRAMstatic random access memory SOCsystem-on-chip UFDGUniversity of Florida double-gate (MOSFET model) UFPDBUniversity of Florida partially depleted SOI and bulk (MOSFET model) UTB ultra-thin body

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13 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulllment of the Requirements for the Degree of Doctor of Philosophy PHYSICAL ANALYSIS AND DESIGN OF NANOSCALE FLOATING-BODY DRAM CELLS By Zhichao Lu December 2010 Chair: Jerry G. Fossum Major: Electrical and Computer Engineering Thisdissertationaddressesphysicalanalysisanddesignissuesofnanoscalefloatingbody cells (FBC), which are also known as capacitorless dynamic random-access memory (DRAM) cells. A novel two-transistor floating-body/gate cell (FBGC), and upgraded versions of it, are proposed and experimentally demonstrated. Astheconventionalone-transistorandone-capacitor(1T/1C)DRAMtechnologyis aggressively scaled, novel device structures and materials have to be introduced to meet InternationalTechnologyRoadmapforSemiconductors(ITRS)performancerequirements. Novel device structures and materials bring a lot of processing and integration challenges tocurrentcomplementarymetal-oxide-semiconductor(CMOS)technology.Toavoidthese challenges, capacitorless DRAM, which is based on silicon-on-insulator (SOI) CMOS including partially depleted (PD) and fully depleted (FD) MOS transistors (MOSFETs), is attracting a lot of interest. This technology, which uses the floating body of the SOI MOSFET as the storage element, can potentially replace the conventional 1T/1C DRAM cellinthenearfuture.ThebasicworkingprincipleoftheFBCistoutilizethefloating-body effectinherentinthePD/SOIMOSFET;theFD/SOIMOSFETalsoshowsthefloating-body effect when the substrate, or back gate is biased for accumulation. However, the physical explanation of the floating-body effect in the FD/SOI device is not clear. Based on

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14 numericalsimulations,physicalinsightsaregainedontheeffectandonFBCperformance, e.g., the sense margin. Relyingonthephysicalinsightsofthefloating-bodyeffects,anoveltwo-transistor (2T)FBCisproposed.Byusingthefirsttransistors(T1)bodytodirectlydrivethesecond transistorsgate,the2TFBCeliminatesthebody-factorlimitationonthesensemargin.The memoryperformanceisdemonstratedwiththeUniversityofFloridaphysics-basedcompact double-gateMOSFETmodel(UFDG).Thepredictedresultsshowthatthecommonimpact ionization-based write method produces too much power dissipation. To resolve this problem,the2T-FBCisrefinedtoVer.1ofthefloating-body/gatecell(FBGC1).Themajor feature of FBGC1 is the source tied source to the drain in T1. To improve the manufacturability of FBGC1, Ver. 2 (FBGC2) is proposed, which in essence is a gated diode(T1)plusaconventionaltransistor(T2).Gate-induceddrainleakage(GIDL)current is used to write in FBGC2. The performance is demonstrated by 90nm FinFET technologyandalsobynumericalsimulation.OneissuewithFBGC2istheshortretention time with bit-line (BL) disturbs. Hence Ver. 3 (FBGC3) is proposed to the resolve this problem. Unlike FBGC2 which accumulates the channel to get GIDL charging current, FBGC3invertsthechannelandintroducestunnelingcurrentatthesourcesideforcharging, thereby separating the charging mechanisms for write and hold. By optimizing the device structure, FBGC3 demonstrates ~10s retention time with worst-case disturb. To make FBGC3operatefaster,Ver.4(FBGC4)isproposed.InFBGC4,T1revertsbacktoanormal transistor.However,specialdesignsaremadeatthesourceside;n+andp+regionsareused to tie the source to the body. The performance, with ~100ps write/read times, is analyzed by the University of Florida physics-based compact SOI MOSFET model (UFPDB).

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15 CHAPTER 1 INTRODUCTION 1.1 Scaling Difficulties with Conventional DRAM Cell Theconventionaldynamicrandomaccessmemory(DRAM)cell,whichconsists of one transistor and one capacitor (1T/1C), has been the workhorse memory cell in the high-density memory arena for more than three decades [1]-[2]. With the innovations in DRAM structures, and utilization of new materials, the conventional 1T/1C DRAM cell is evolvingtothe60nmtechnologynodeand4Gbcapacity[3]-[6].ScalingtheDRAMcellto sub-60nmtechnologynodes,asdemandedbyhigh-densitystorageandlowbitcost,isvery challenging. Scaling issues are directly related to the requirement of storing a critical amount of charge on the capacitor for a certain time. To guarantee proper DRAM cell operation, the sensing signal should be larger than sensing noise to ensure the correct sensing in the noise environment. Generally, the requirements of the access transistor and the storage capacitance can be summarized as follows [5][7][8]: ,(1.1) fF/Cell,(1.2) a few m A/Cell,(1.3) few fA/Cell,(1.4) C s C s C BL + -----------------------V DD 2 ------------150mV C s 25 I on I off

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16 where CS is the storage capacitance, CBL is the bit-line (BL) parasitic capacitance (the typicalvalueis75fFforonebitline[9]),andVDDisthesupplyvoltage.Withregardtothe scalabilityoftheaccesstransistor,maintainingrelativelyhighthresholdvoltage(Vt),e.g., 1V, is an effective way to get less than a fA/cell leakage current and several m A/cell oncurrentsimultaneously.So-calledLocalizedAsymmetricChannelDoping(L-ASC)[10]and RecessedChannelArrayTransistor(RCAT)[11]arethetwoapproachesthatwereproposed tosolvethisproblem.L-ASCcaneliminatethejunctionleakagecurrentatthestoragenode by decreasing the doping concentration only at the storage node while maintaining the Vt. RCAT can significantly suppress short-channel effects (SCEs) by increasing the effective channellengthwithoutareapenaltyduetoitsrecessed-channelgeometrystructure.Beyond 50nm technology node, a body-tied bulk FinFET or a vertical surrouded-gate transistor could be utilized due to their excellent immunity of SCEs, relatively low junction leakage (undoped body), and high transconductance. But, the disadvantage of these approaches is less compatibility to the conventional planar CMOS logic technology. These approaches inevitably require extra fabrication steps which increase the cost of fabrication [12]. Compared with the scalability issues of the access transistor, the scaling difficulties with the storage capacitors are more serious and ambiguous. Since the DRAM storage area becomes physically smaller with scaling, the effective oxide thickness (EOT) must scale down sharply to maintain non-scalable storage capacitance (~25fF/Cell). This will lead to extraordinary large aspect ratio for trench capacitors or larger cell size in stackedcapacitors.Moreover,dielectricthicknesscannotbereducedexcessivelybecauseof concernoverhightunnelingleakagecurrent.High-kmaterial,suchasHfSiO,Al2O3,ZrO2, or Ta2O5[13], with new capacitor structure, such as Metal-Insulator-Metal [13], could be

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17 ways to resolve this problem. Many efforts have been made to investigate these new materials and structures. But, these methods involve challenges in low-temperature processing, good adhersion/deposition properties, and sufficiently low tunneling leakage current [14]. In addition, these new materials and structures are not compatible with the conventional CMOS technology and will increase the bit cost [14]. These unresolved problems with the 1T/1C DRAM cell have lead to uncertainty in industry over how far conventional 1T/1C DRAM technology can go. 1.2 Capacitorless DRAM To overcome the difficulties in scaling the conventional 1T/1C DRAM cell, 1T capacitorlessDRAM[15]-[17]hasbeenproposed.ThecapacitorlessDRAMcell,whichis simply a MOSFET with a floating body, i.e., a floating-body cell (FBC), offers several advantages: (1) no complex capacitor integration technology, which implies better scalability beyond 50nm technology node; (2) full compatibility of memory and logic technology, and 4F2 cell area; and (3) better electrical performance, such as low power dissipation, high speed, and better sense margin. Initially, there was considerable interest in the FBC based on the partially depleted (PD) SOI MOSFET [18] [19], and on the bulk-Si MOSFET [20]. Recently, the interest moved to fully depleted (FD) SOI MOSFETs [21]-[23] and FD double-gate (DG) FinFETs [24]-[26], which have more potential scalability. For the FD (n-channel) cells, it ispervasivelyacknowledged[22][25]-[28]thataholeaccumulationlayermustbeinduced by substrate or back-gate bias (VGbS) to form a deep potential well for hole storage, as thought to exist naturally in the PD cell [17][23]. The published descriptions of the capacitorless FBC operation based on the notion of a potential well, and the cell-design

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18 implications of it, are inadequate and misleading. Later in this chapter, using numerical devicesimulationsandanalyticalmodeling,wephysicallyoverviewthebasicoperationof the FBC, clarify the misleading "hole well" concept and revealing new insights that could lead to optimal cell design. TheadvancedCMOStechnology,e.g.FinFETtechnology,couldenablescaling of the 1T FBC to gate lengths (Lg) less than 10nm [27][29]-[31]. The basic current-signal margin of the 1T FBC, defined by the threshold-voltage difference corresponding to the body-voltage(VBS)variationduetobodycharging/discharging,isfundamentallyrestricted: D Vt=-r D VBSwherethebodyfactorr~0.3[32]whenSCEsarecontrolled.Thisrestriction, andotherissues,e.g.sophisticatedcurrentsensingcircuits[33],haveledtoourconception ofa2TFBC,inwhichthefloatingcharged/dischargedbodyofonetransistor(T1)directly drives the gate of a second transistor (T2), thereby removing the r-factor restriction in the signalmargin.InChapter2,wefirstpresentanovel2T-FBCconcept,andthendemonstrate a new 2T-FBC configuration, which in essence is a floating-body/gate cell (FBGC) [34]. That yields dramatic reduction in power dissipation, in addition to better signal margin, comparable data retention time, and higher density. The simulations done in Chapter 2 demonstrate that floating-body/gate DRAM cell (FBGC) which we call Ver. 1 (FBGC1), on SOI [34][35], can potentially yield better signalmargin,lesspowerdissipation,andhighereffectivedensitythanallother1Tfloatingbody DRAM cells (FBCs). However, an issue with FBGC1 is the process integration for tyingthebodyofT1tothegateofT2,whichunderminescellareaandmemorydensity[35]. We address this issue in Chapter 3, where we propose a simplified, easily manufacturable version of the FBGC, the so-called "P+ Source" FBGC [36], or Ver. 2 (FBGC2), which is

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19 compatible with conventional, planar SOI and DG-FinFET CMOS technology with ~8F2cellarea.Inessence,thesimplified"P+source"FBGCisagateddiodeconnectedtothegate of a conventional MOSFET through the P+ region. Numerical simulations and measurements of a fabricated prototype of the new cell demonstrate the basic memory concept,andalsoimplysignificantperformancesuperiorityoverthe1TFBCsaswellasthe original version of the FBGC in Chapter 2. Since the writing scenarios in FBGC [35] [negative gate (word line) voltage is used to write and positive gate voltage is used to write ] are different from the conventional impact ionization-based write methods, the holding conditions under disturb becomecomplicated.Word-line(WL)disturbshouldbecarefullytakencareofinbothstate and -state holding. In Chapters 2 and 3, we reveal two facts: (1) state under disturb is more tenuous than state under disturb; (2) GIDL current in the holding conditions is the major killer of the retention time. Even though we get longer retentiontimeunderdisturbwiththe"P+Source"FBGC(FBGC2),wefindthattheabsolute valueofretentiontimeisstillmuchshorterthanthe64msasrequiredbyITRS[7].Wealso find that the non-quasi-static hole redistribution is significant in the memory transient operation.InChapter4,weseektogainphysicalinsightsofthetransientGIDLcurrentdue to the non-quasi-static effect and body-bias dependence of GIDL current, which will determine the worst-case -state retention time. Based on our physical insights, we developananalyticalGIDLcurrentmodelanduseittopredictthe-stateretentiontime with the "P+ Source" FBGC. With better understanding of the dependence of transient GIDL current on VBgainedinChapter4,weproposetomodifythedesign,andoptimizetheperformanceofthe "P+Source"FBGC(FBGC2),includingacceptableretentiontime.Weaddressthekeyissue

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20 for FBCs using GIDL current for charging, i.e., the current ratio corresponding to the charging operation and the holding state with disturb. This ratio must be very large to achieve100msretentiontimewithreasonablewritetimeandsensemargin.Weinvestigate twonewFBGCdesignmodificationstogetthedesiredperformanceinChapter5.Toresolve the shorter worst-case retention time problem, Ver. 3 (FBGC3) is proposed and demonstrated with numerical simulations. Then, exploiting the design flexibility which is offered by the 2T FBGC cell, we upgrade FBGC3 to Ver. 4 (FBGC4) for faster speed. Besides maintaining the excellent retention time characteristics in FBGC3, FBGC4 can improve write speed, including write and to less than 1ns. These characteristics mean FBGC4 could be a good candidate to replace the cache memory cell in CMOS logicchip design. 1.3 New Physical Insights on "Capacitorless"DRAM Cell 1.3.1 Basic FBC Operation As noted, the integration problems associated with the capacitor of the conventional DRAM cell in nanoscale CMOS technology have stimulated the research interestincapacitorlessDRAMcells Thebinarystatesofthe1Tfloating-bodycells(FBCs) are defined by charging and discharging the body of an SOI MOSFET. The stored data is sensedviaadifference,orsignalmargin,inthechannelcurrent(IDS)correspondingtothe Vt variation that results from the body charging/discharging, i.e., from the varying bodysourcejunctionvoltage(VBS,thequasi-Fermipotentialseparation)[22][37].Thecharging (e.g.,byimpact-ionizationcurrentIGi)anddischarging(e.g.,bybody-drain(B-D)junction forwardbiasVBD)ofthe(n-channelwithgroundedsource)FBCaredefinedbythefloating-

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21 body nodal, or (hole) current-continuity equation, which involves discernible intrinsic, dynamic capacitors: (1.5) where CB represents the composite body capacitance that couples the body to other terminals of the MOSFET; Qp is the hole charge in the body, and IR (generally defined by the B-S/D p-n junctions [38]) and IG are hole recombination (removal) and generation (injection)currentslinkedtothebody.InthePD/SOIcell(withthickBOX)duringcharging byIG=IGi,forexample,CBcomprisestheB-S/Djunctioncapacitancesdefinedbythebody doping density (NB) [38]. Generally, the VBS-dependent B-S capacitance is predominant, includingbothdepletionanddiffusioncomponents[37][38].However,ifIGisGIDLcurrent [23],withthefrontsurfaceaccumulated,CBisaugmentedbythebody-gatecapacitance,or ~CoxWgLg.Duringwrite-charging(dQp/dt>0),CBin(1.5)governsatransientincrease in VBS ( D VBS) related to Qp: (1.6) where D Qpistheinjected,storedholechargeassociatedwith D VBSasdefinedbyCB;Qp0isdefinedbyNBforPDcells(itisthementionedVGbS-inducedaccumulationchargeforFD cells). For IGi charging, the transient can reach steady state, where IGi = IR(VBS) defines VBS (which is typically about 0.7V); for GIDL charging, VBS < 0, making IR = 0 (for no gatecurrent),andthesteadystateisnottypicallyreached[23].Duringwrite-discharging (dQp/dt < 0), IG = 0 and IR can be defined by VBS > 0 as well as VBD > 0; the transient is I G I R dQ p dt ----------C B dV BS dt --------------== Q p Q p0 D Q p +Q p0 C B V BS d D V BS+ ==

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22 thusrelativelyfast,yieldingVBS~0(<0whenVDS<0isappliedforfasterdischarging)in the steady state. Note that during the IG = IGi charging transient, the gate, or word-line voltage(VGfS)israisedtoinduceachannel,andthedrain,orbit-linevoltage(VDS)israised todriveIDSandIGi.Thus,excessivepowerisconsumedashasbeengenerallynoted;useof GIDLforIG,withoutachannel,dramaticallyreducesthispower[23].However,duringthe discharging transient, with VGfS > 0 and VDS < 0 as typically used, the write0 power dissipated by the MOSFET in the inverse mode can be excessive too, and this is not generally noted. For FD FBCs, with very low NB, CB in (1) is not so clearly defined; a depleted body renders very small B-S/D junction capacitance. For the FD/SOI MOSFET with thick BOX, the body substrate capacitance is very small too, and there is no significant holestorage element. (Note that using GIDL for IG in this case, which would require G-S/D overlap,couldmakeCBtheoxidecapacitanceasnotedabove.)ForIG=IGichargingthen, (1.5)and(1.6)showthatthesteady-stateVBSisreachedveryquickly,butwithvirtuallyno D Qp. However, we note that if the substrate is biased negatively to induce strong hole accumulation charge (Qp0) near the body-BOX interface, as typically done [21][22][27], large B-S/D junction capacitance is created within the accumulation layer. Indeed, this capacitanceemulatesthatofthep+-n+junction[38]inthePD/SOIcell,andistypicallythe predominantcomponentofCB.FortheFDDGFinFET,thesubstratecanbebiasedtoform the accumulation layer [25] and create CB in the same way. However, if the two gates are made independent (IG) [26], the back gate can be biased instead [Okh05][Ban06]. For the IGFinFETthough,wewonderwhethersuchbiasisreallyneededforCB;couldthethinback oxide (toxb = toxf ~ 2nm) yield an adequate B-Gb capacitance without any VGbS-induced accumulation?

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23 We answer this question later, but irrespective of CB, we note that the VGbSinduced accumulation is still needed for two other reasons. First, the D Qp-defined data in the cell cannot be sensed without it because Vt is not dependent on VBS. Indeed, without strong accumulation charge, Poissons equation in the FD body shows that the Gf-Gb couplingdefinesVt(VGbS),andthereisnosignificantVtdependenceonVBS[39].Weshow laterthatthisneedpersistseventhoughanaccumulationlayertendstoformasIGi(orGIDL) injects holes ( D Qp) into the body and VBS increases. Second, the VGbS-induced accumulation charge increases the stored- Vt to Vta (via dVt/dVGbS = -rd ~ -CbCoxb/ [Coxf(Cb+Coxb)]fordepletion[39],whereCb= eSi/tSi,Coxf= eox/toxf,andCoxb= eox/toxb) such that the VBS-defined lowering of it [22], (1.7) for accumulation, where ra = Cb/Coxf~ 3toxf/tSi, yields a stored- Vt that is sufficiently lower than the stored- Vt for data (current) sensing. Without the VGbS-induced accumulation,the-stateVt=Vt(VGbS)islow,and,eventhoughthestored-state D Qpcreatesanaccumulationlayer,theversusVtmarginisprohibitivelysmall,aswenow show. 1.3.2 Simulations and Discussion WedemonstrateournewinsightsregardingthegeneraloperationofFBCsvia2D numerical device simulations done with Taurus [40]. We present here results of simulatingtheFBCoperationofanFDIGFinFET,illustratedintheinsetofFig.1-1.The FinFEThasa28nmgatelength,withtoxf=toxb=2nm,undopedfin-bodywiththicknesstSi=14nm,andmidgapgates;thedefaultfinheight,orgatewidth,is1 m m.InFig.1.1weshow D V ta r a D V BS =

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24 predicted IDS(t), defined by Vt(t), reflecting the transient sequential operation of the cell (i.e.,write(chargebodybyIGi),holddata,read,holddata,write(dischargebody withVDS<0),holddata,andreadasdepictedinthefigure)fortwocases:VGbS=-1.0V, which induces a back-surface accumulation layer, and VGbS = 0V, which leaves the unbiased body fully depleted. For the first case, the predicted FBC operation is normal, albeit with a small signal margin ( D IDS as defined by D Vta in (3)) that typifies FBCs since ra<1.Thestoreddata,sensedviaIDS,reflectsthecharging/dischargingofCB,i.e., D Qp(t) as indicated by the predicted hole densities in Fig. 1-2. Note here that CB includes the accumulation-defined B-S junction capacitance, as in the FD/SOI FBC, plus the B-Gb capacitance (~CoxbWgLg), which is comparable to the junction capacitance. Note also the excessivepowerwasimpliedbyIDSduringthewrite-aswellasthewrite-operations. However,fortheVGbS=0VcaseinFig.1.1,notethatIDS(t)doesnotreflectanystoreddata, in accord with our discussion above, and the transients are very fast, implying much less D Qp stored on the B-Gb capacitance. The predicted hole densities in Fig. 1.2 confirm the small,butfinite D Qp.Sincethewrite-IDSforthiscaseimpliesarelativelyhighIGi,we infer,from(1),aneffectivelylowCBeventhoughtoxbisthin.Theseresultscanbeexplained with reference to the back-surface energy-band diagrams sketched, in accord with the simulationresults,inFig.1-3,forthiscaseandfortheVGbS=-1.0Vcase.Inthelattercase, the valence band Ev is pinned to the hole quasi-Fermi level EFp via the high hole density, andhencetheback-surfacepotentialvariesas Dfsb= D VBS,yielding(3)[22][39].However, fortheVGbS=0case, Dfsb~0.Thisisbecausetheinversionelectrondensitythatexistsin the body (bulk inversion is prevalent in undoped MOSFETs [41]) during write nearly pins the conduction band Ec to the electron quasi-Fermi level EFn as VBS [=( EFnEFp)/q] increases. Only when the injected hole density (which defines D Qp) becomes the

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25 predominant carrier near the back surface of the body does Ev begin to follow EFp, thus increasing fsbandloweringVtaccordingly[22][39].However,atthispointVBSisalready near its final, -state value, and so D Qp ~ CoxbDfsb is small and D Vt~ 0. 1.3.3 Summary Using numerical simulations and analytical modeling, we physically and generically explained the operation of FBC DRAM, comprising a PD/SOI or FD/SOI MOSFET,oranFDDGorIGFinFET.Thenotionofapotentialwellforchargestoragein the body was dismissed, and, for the first time, the predominant intrinsic, dynamic capacitors (bias-dependent CB) that store the body charge, or data, for the various devices and bias conditions were defined. For FD cells, multiple roles of the VGbS-induced accumulationlayerneededforstoringandsensingdatawasphysicallydefinedforthefirst time; it renders a significant D Vt dependent on D VBS, and, in the FD/SOI cell with thick BOX, it creates a significant B-S junction capacitance for the charge storage. For the IGFinFET cell, the created junction capacitance is augmented by the B-Gb capacitance. For GIDLcharging[23],ratherthanbyIGi,CBisaugmentedbytheB-Gfcapacitance.Thenew insightsnotedhereinimplybetterdesignsforoptimallytrading-offtheFBCsignalmargin ( D IDSdefinedby D Vtain(1.7)),dataretentiontime,writespeeds,andpower.Allthenoted metricsdependonCB,whichhasbeenclearlydefinedwithreferenceto(1.5)and(1.6)for the various FBC devices and biases. Indeed, a dynamic CB could be optimally tailored by devicedesign.Forexample,useofGIDLforbodycharging,whichreducespower[23],also makesCBin(1.5)forwritedifferentfromthatforread,aswehaveindicated.During thewrite-operation,VBS<0[23],makingIR=0in(1.5)andthusincreasing D Qpfora given write time, irrespective of CB(write). The larger D Qp implies longer retention time

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26 directly, and could also yield improved margin via D VBS = D Qp/CB(read) in the read- operation;CB(read)istheB-Sjunctioncapacitance,dependentonVBS>0.Also,notefrom (1.7)that,foragiven D VBS, D VtacanbeincreasedbydecreasingtSiorincreasingtoxf,but only the former change increases the signal margin, as experimentally shown in [27] and [28], since D IDS~ CoxfD Vta~ 1/tSi.

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27 Predictedoperation(withIGibodycharging)oftheIG-FinFETFBC withVGb=-1.0VandVGb=0V.Thetransientpulsingsoftheword lineandbitlineofthecellareshowninthetopplot,andthetransient cellcurrents,whichreflectthestoreddata,arealsoshownintheplot, theinsetofwhichillustratesthebasicstructureoftheDG-MOSFET FBC. 0.0102030405060708090100110 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6Voltage (V) Word Line Bit Line VGb=-1.0V VGb=0.0V 0.0102030405060708090100110 -250 -200 -150 -100 -50 0 50 100 150 VGb=-1.0V VGb=0.0V Time (ns)IDS ( m A/ m m)Write Read Write Read Hold Hold n+n+p(body) D S Gf(word line)Gb(back gate) toxftoxbtSi (bit line)HoldFigure 1-1.

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28 Predicted hole density along the back surface between source and drain of the IGFinFET FBC at the ends of the read- and read- transient operations, for VGb = -1.0V and VGb = 0V. For the former case,theholedensityreflects(Qp0+ D Qp),whileitreflectsonly D Qpforthelattercase.Notethat D QpismuchlargerforVGb=-1.0Vthan it is for VGb = 0V. -20-15-10-505101520 Position (nm) 103105107109101110131015101710191021Hole Density (cm-3) Read VGb=-1.0V Read VGb=-1.0V Read VGb=0.0V Read VGb=0.0V Source Channel Drain Figure 1-2.

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29 Sketch of the perturbation of the energy-band diagram across the bodysource junction at the back surface of the IG-FinFET FBC caused by VBS > 0 associated with write- (via IGi) D Qp, for VGb = -1.0V and VGb= 0V. For the latter case, the surface potential is hardly changed by VBS since EFp is not pinned to Ev as it is for the VGbS= -1.0V. EcEv qVBSEFnEFpq DfsbVGbS = -1.0V EcEv qVBSEFnEFpq DfsbVGbS = 0V SB S BFigure 1-3.

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30 CHAPTER 2 TWO-TRANSISTOR FLOATING-BODY/GATE CELL: A NOVEL LOW-POWER NANOSCALE EMBEDDED DRAM CELL 2.1 Introduction The conventional DRAM cell requires a stack capacitor or a deep-trench capacitorforstorage,whichisleadingtoprohibitiveprocessingcomplexityasthememory technology is scaled [1]. So, study and development of "capacitorless" one-transistor (1T) DRAMcellsthatutilizethefloatingbodyofanSOIMOSFETasthestorageelementhave intensified[17][21][22][28][42],mainlyforCMOSembedded-memoryapplications[43].In such1Tfloating-bodycells(FBCs),charging(byimpact-ionizationorGIDL[23]current) and discharging (by forward-biased drain/source-junction current) the MOSFET body definethememorystates,andthestoreddataaresensedviaadifference,orsignalmargin, in the channel current ( D IDS) corresponding to the threshold-voltage variation ( D Vt) that results from the body charging/discharging, i.e., from the varying body-source junction voltage(VBS)[44].ThewidespreadFBCstudies,whichbeganwithpartiallydepleted(PD) SOIMOSFETs[17],haverecentlyfocusedonfullydepleted(FD)devices,includingplanar FD/SOIMOSFETs[21][27][45]andFDdouble-gate(DG)FinFETs[26][28][46],toavoid body-doping issues [26] and to render the FBC more scalable with the CMOS. The FD devicesrequireasubstrate,orback-gatebiastocreateanaccumulationlayerthatemulates thePDbody,andenableseffectivechargestorageanddatasensingasexplainedinChapter 1 [44]. While FinFET CMOS technology could enable scaling of the 1T FBC to gate lengths(Lg)lessthan10nm[29],thereareotherissuesthatwilltendtoinhibitmainstream adaptationofthe1T-DRAMconcept:(i)itreliesoncurrent-basedsensingofthestoreddata,

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31 which is less desirable than conventional voltage-based sensing because of varying D IDS, and hence more complex sensing circuitry [33], and added power consumption; (ii) it requires the noted bias-induced accumulation, which complicates the cell/chip design, undermines reliability, and sacrifices layout area; and (iii) because the attainable D Vt is fundamentally limited, wide devices, or several paralleled fins, are needed to increase the current to get acceptable D IDS, thus undermining the memory density actually achievable. Forexample,in[46],withtheSOIsubstratebiasedat-30Vtogettheneededaccumulation, 10finsyieldedacurrentmarginoflessthat10 m AfromanLg=100nmcompositen-channel DG FinFET. In this chapter we propose and demonstrate, via process/physics-based device/ circuit simulations supported by numerical simulations, a novel two-transistor (2T) FBC [34]forembedded-DRAMapplicationsthatcanyieldmuchbetterperformancewithhigher densitythanthe1Tcells.The2Tconceptisconceivedfromaninsightfulunderstandingof thebasicFBCoperation[44],whichinfactbeliesits"capacitorless"description.Further,a modification in the 2T-FBC structure enabled by use of GIDL current for body charging, whichinessencecreatesafloating-body/gatecell(FBGC)[34],isshowntoyielddramatic reduction in discharging as well as charging [23] power dissipation, in addition to better signal margin, higher memory density, and longer data retention. Design and processing issuesthatneedtobeaddressedforoptimalperformanceandforsustainedFBGCviability in nanoscale CMOS are discussed.

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32 2.2 Two-Transistor Floating-Body Cell Concept 2.2.1 Transient Simulation Our2T-FBC[34]ideastemsfrominsightsintotheactualoperationofthe1TFBC [44].First,wenotethatthevariationinVtthatunderliesthe1T-FBCoperationistypically muchlessthanthevariationinVBSdrivenbythebodycharging/discharging: D Vt=-r D VBSwith the body factor r ~ 0.3 [32]. This means that wide devices, and large layout areas are needed for adequate D IDS, as mentioned previously. Second, we note that the commonly used"potentialwell"description[21][22][24]ofthebodychargestorageismisleading.The FBCisnotreally"capacitorless";itcanactuallyhavemorethanoneintrinsiccapacitor(CBi) supporting the charge (Qp in an nMOSFET) storage [32]: (2.1) is the floating-body nodal equation, where CBi, with i = S, D, Gf, Gb, represents the capacitivecouplingofthebodytootherterminalsofthetransistor;Qpisthemajority-hole charge in the body, and IG and IR are hole generation (or injection) and recombination (or extraction) currents. Third, as noted above, voltage-based sensing is not an option for the 1T FBC. Amemoryarraybasedonthe2TFBCisillustratedinFig.2-1.Thecellcomprises transistors T1 and T2, with the body (B1) of T1 connected to, or driving the gate (G2) of T2; Cbi in (1) is thus augmented by the gate capacitance of T2. The 2T concept is generic, applicabletoanySOItechnology.However,FinFETsofferthebestscalability,andthe2Tcellstructurecouldbefabricated,withoutareapenaltyduetotheB1-G2contact,viatheDG FinFET-based ITFET technology [44][47] as illustrated in Fig. 2-2. The planar SOI layer, I G I R dQ p dt ----------C Bi dV Bi dt ------------i==

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33 dopedp+,wouldbeusedtomaketheB1-G2connectionoftwon-channelDGFinFETs.The FinFET bodies should be left undoped for scalability [44]. Lateral diffusion of the p-type dopants in the SOI layer during activation would effectively dope the base of the T1 fin, thereby suppressing source-drain leakage current in it. The undoped FinFETs should have near-midgapmetalgates,andp+ratherthann+polysiliconmustbeusedinthegatestackto enabletheB1-G2connection.Asnotedinthefigurecaption,weestimateaunit-cellareaof 13.75F2, which implies that the potential area per signal margin is much smaller than that of a 1T counterpart cell because of the larger margin afforded by the 2T FBC, which we exemplifylater,andtheneedforawidedevice,ormultiplefins[28][46],inthe1TFBCas notedpreviously.Alternatively,astacked2Tstructure,withT2madeinpolysilicon(aswe justify later) is possible. The write/erase operations of the 2T FBC are done by charging/discharging the floating body of T1, as in the 1T FBC. But, the stored data are read via T2 with D VGS2 = D VBS1> |D Vt|,whichimpliesdirectlya(1/r)xincreasein D I,orabouta2x(1/2r)memorydensity increase for the same current-signal margin. No substrate biasing is needed, even when the transistors are designed to be FD, like DG FinFETs which we focus on here. However,twobitlines(perstring)areneeded:one(BL1)connectingalldrainnodesofthe T1transistorsinacolumnoftheDRAMarrayforprogramingthecells,andtheother(BL2) connecting all drain nodes of the T2 transistors in the column for sensing the data. As we discuss later, two bit lines will tend to improve data-retention time, as well as ameliorate read-error issues. The gate of T1 is tied to a word line (WL). The stored data are read by, in essence, driving T2 directly with VBS of T1 ( VB1/G2withS2grounded).Datacouldthereforebesensedviatheinduceddrain-current variation (gmD VB1/G2) in T2, as in the 1T FBC cells but with much better signal margin

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34 because D VB1G2 > | D Vt| as noted. However, preferred voltage-based sensing at the (precharged)drainnodeofT2(BL2),similartothesensingusedintheconventionalDRAM technology,canbeused.Inthiscase,the2T-FBCcellhastobedesignedsuchthatT2will be turned on and off by the charged/discharged T1 body in the and states, respectively.(NotethatsinceT2inverts,storedandcorrespondtotheT1bodybeing chargedanddischarged,respectively.)Forvoltage-basedsensing,thetwoFinFETscanbe designed with only one fin each, implying much less layout area than a FinFET-based 1T FBC [28][46] with multiple fins. We now simulate the basic operation of the FinFET-based 2T FBC using our process/physics-based compact model UFDG [48] in Spice3. UFDG is charge-based, and henceproperlyaccountsforallimportanttranscapacitances,ensuringchargeconservation, andiswell-suitedfordynamicFBCsimulation.TheIRandIGmodelinginUFDG,including impact-ionizationcurrent(IGi)andGIDLcurrent,isalsophysical.NotefortheT1bodyof the2TFBCthatapredominantchargingcurrentontheright-handsideof(1)isdefinedby the gate capacitance of T2: CG2(dVB1/G2/dt) where, in general, CG2 is VB1/G2-dependent. Weassumesingle-finLg=28nmDGnFinFETsforT1andT2,withundopedfin-bodywidth and height of 14nm and 56nm, respectively, midgap metal gate, and 1nm gate oxide. (We neglectgatetunnelingcurrentandparasiticcapacitanceforthispreliminarydemonstration.) We further assume an ideal B1-G2 connection, and the body of T2 is left floating like B1. TheUFDG/Spice3-predictedoperation[i.e.,write(chargeT1body),holddata/precharge BL2,read,holddata,write(dischargeT1body),holddata/prechargeBL2,andread ],forIGichargingofB1,isshowninFig.2-3;asindicated,weassumedreasonableread/ write times of 10ns including pulse rise/fall times of 1ns. The UFDG model predicts the expected trend of the B1/G2-voltage variation with gate (WL) and drain (BL1) biasing, as

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35 shown. A typical program window (or VB1/G2 signal margin) of @ 0.8V is predicted, as indicated by the difference of VB1/G2 between the read- and read- operations. NotethatappropriateWLpulsing(to0.1Vhere)forreadoperationsisneededto move VB1/G2 sufficiently above or below Vt of T2 for stored or respectively, with adequate D Qp storage needed for the former. This operation is confirmed by the predicted transientdrain(BL2)voltageofT2,whichneedstobeprechargedbeforereading(to1.0V here). Indeed, with the T1 body charged (stored ), BL2 drops quickly to 0V, as VB1/G2turns on T2; this corresponds to a read With the T1 body discharged (stored ), BL2 remains at its precharged value (1.0V) as VB1/G2 remains well below Vt; this corresponds to a read Efficient reads of both and are demonstrated with reasonable WL and BL1 voltage pulsings. Of course there is some uncertainty in the assumed (defaulted) physical model parameters in UFDG, e.g., those defining IG (including IGi) and IR. However, this uncertainty should not undermine our demonstration of the basic functionality of the 2T FBC in Fig. 2-3. We do, however, have some concern about the assumed ideal B1-G2 connectionandthenotionthatthefloatingbodyofT1caneffectivelydrivethegateofT2. Thus, for more definitive corroboration, we do a numerical mixed-mode simulation a 2TFBCstructureusingTaurus[40].Toallowa2-Dsimulation,wedefineadomainwithtwo 28nm single-gate undoped FD/SOI nMOSFETs, linked by a p+ polysilicon-TiN (with midgap work function) connect as shown in the inset of Fig. 2-4. Further, to facilitate the mixed-modesimulation,wesimplysetVDSofT2to0.1Vandmonitoritscurrent(IDS2)to check the functionality of the cell. Although the assumed 2T structure is simplified, the simulation results, shown in Fig. 4 for IGi charging of T1, do corroborate the general operationofthe2TFBCaspredictedbyUFDG/Spice3.Indeed,theresultsdemonstratethe

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36 basic operation of the cell with nanosecond-scale write/read processes, showing that the floating B1 of T1 can effectively drive G2 of T2 and yield outstanding signal margin. The marginofthecell,reflectedbythepredictedIDS2(t),issubstantivelylargerthanthatofthe 1T counterpart [32], even though it is undermined some because of the unexpected finite read-current.ThiscurrentisduetothesignificantQpstoredontheforward-biasedB-D junction of T1 during the write- (discharge) process, which is supported by substantive IGi with T1 in the inverse mode. This undermining of the current-signal margin will occur in any FBC unless the WL voltage is kept well below the MOSFET threshold voltage and/ or the BL voltage is kept near zero during the discharging process. Dataretentionofthe2TFBC,subjecttoBL1andWLdisturbs,isexpectedtobe atleastcomparabletothatofthe1Tcell,asexemplifiedforFinFET-basedFBCsin[46]and [30]. But, the enabled use of voltage-based sensing instead of current-based sensing can yield better retention in the 2T-FBC array, as we show and explain later. 2.3 Performance Evaluation of the Floating-Body/Gate Cell 2.3.1 Operation Simulations Clearly, the 2T FBC affords much more design flexibility for optimizing performance than does the 1T FBC. A good example is the FBGC [35] (Ver. 1), which stemmedfromourcheckingtheuseofGIDLcurrentforbodycharging[23]toeliminatethe substantive write- (B1-charging) power loss due to T1 channel current, which can be inferred in Figs. 2.3 and 2.4. Note, in fact, that such power loss occurs in the write- (discharging)operationaswell.For discharging,aforwardbiasisestablishedonthebody-drain junction by VDS < 0 and VGS > Vt, and thus high channel current ows in the inverse mode [32]. The body-charging power can be virtually eliminated by using GIDL current [23], rather than

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37 impact-ionization current, for charging, but the body-discharging power remains high. A key feature of the FBGC is the drain (BL1) of T1 tied to the source as illustrated in Fig. 2-5. This 2T conguration,withT1effectingaoatingbody/gateonT2,totallyeliminatesT1channelcurrent, and thus the excessive power dissipation when the body of T1 is discharged. Further, with GIDLcurrent charging, it eliminates the undermined signal margin due to IGi noted with reference toFig.2-4aswell.TheFBGChasotheradvantages.Alldrain-sourceleakagecurrentsinT1 are eliminated, meaning reduced standby power. Also, T1 can be designed primarily for GIDL current, i.e., with significant gate-source/drain overlap and Leff < Lg, without much consideration of short-channel effects since it is not crucial in the read operations. This is not true for 1T FBCs using GIDL-current charging, for which the shorter Leff will tend to limitLgscalability.And,withT1nowbeingjustatwo-terminal(WLandBL1)device,the fabrication process could be simplified, e.g., by using a stacked structure as mentioned previously. We verify and demonstrate the operation of the 2T FBGC, rst by numerical simulationsusingTaurus.The2-DstructuraldomainusedissimilartothatinFig.2-4,with28nm FD/SOItransistors.The predictedresultsforasequentialmemoryoperation,withT2current usedforsensingdata,areshowninFig.2-6,includingthefloating-B1/G2voltagetransient, whichisVGS(t)appliedtoT2(butnotnowVBSofT1sinceS1isnotgrounded).Theresults confirm the basic operation of the FBGC cell based on GIDL-current charging of T1, showinganoutstandingsignalmarginthatis about2.5xhigherthanthatachievedina1TFBC counterpartin[23]withthesamedrainbias(0.2V). Notethenegligiblewrite-powerdissipation reflected by the transient current in T1, void of any channel current. The B1-discharging currentisaboutfourorders-of-magnitudelowerthanwhatistypicalin1TFBCs[17].The charging/discharging-currentcomparisonoftheFBGCversusthe1TFBCsin[17]and[23]

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38 made in Table 2-1 clearly reflects the superiority of the FBGC with regard to power consumption.The 2T FBGC also enables data sensing via the BL2 voltage, for which VB1/ G2(t)mustswingthroughVtofT2andthestoredchargeinB1mustbehighenoughtoimage an adequate inversion charge in T2. The latter requirement is dependent on the noted nonquasi-staticeffect(Itwillberevistedinchapter4.),whichenablestheoxidecapacitanceof T1,aswellasthegatecapacitanceofT2,toaugmentCBiof(1)inthebodyofT1[32].To demonstrate this operation with realistic FinFETs, and to check the data retention/disturb characteristicswithreasonablecomputationalefficiency,weuseUFDG/Spice3.(UFDGis aquasi-staticmodel,butthenotedNQSeffecthasbeenaccountedforintheGIDL-current modeling.) We assume undoped 28nm single-fin DG nFinFETs with a midgap gate. To avoid significant gate tunneling current as well as reduce parasitic gate-source/drain capacitance,apragmaticgateoxidethickness(tox)of2nmisassumed.Thefinwidthisset to 14nm for SCE control [29], and the height is set to a reasonable 56nm. A 1.5nm G-S/D overlapinT1isassumedforreasonableGIDLcurrent,anda3nmunderlap[49]inT2isused to further reduce the parasitic (fringe) capacitance [50]. Such 2T-FBGC design is doable using the previously noted ITFET structure [47]. The predicted operation is shown in Fig. 2-7.Notethatthewrite-WLandBL1voltagepulses(neededforGIDLcurrent)arehigh, buttheoxideelectricfield,dependentontox,gate-siliconwork-functiondifferences,surface potentials,andVB1/G2,isnottooexcessiveanywhere.Thememoryoperationhereismore efficientthanthatinFig.2-6mainlybecauseoftheupgradedT2design.Notethat,withBL2 prechargedto0.5V,thefastBL2voltagetransient,goingto0Vor0.5V,faithfullyreflects thestoreddatadirectlyinthiscase.Thissolidvoltage-signalmarginimplieshigherFBGC memorydensity,sincewide(e.g.,multi-fin)devicesmustbeusedinthe1Tcellforadequate current margin [46].

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39 To demonstrate the benefit of the noted T2-design upgrade, we simulated the FBGCoperationagain,butwithT2identicaltoT1.Inthiscase,T2,withtheG-S/Doverlap, has much higher parasitic capacitance, including increased G-S/D fringe capacitance [49] as well as the added overlap capacitance. The UFDG/Spice3-predicted B1/G2 and BL2 voltagetransientsarecontrastedinFig.2-8withthoseofFig.2-7.Althoughnowtheadded parasitic capacitance of T2 must be charged during the write- process, the larger oxide capacitanceofT1,wherethepredominant D Qpisstored,stillcontrolstheVB1/G2charging transient.However,thesubsequentread-efficacyisclearlyundermined.TheWLpulse doesnotbringVB1/G2upasmuchbecauseoftheaddedparasiticcapacitanceofT2,thereby yielding slower read time. The write/read- (discharging) processes are not significantly affectedbytheaddedcapacitance.However,the-signalmargininVB1/G2isreduced substantially by the noted read- effect, which portends shortened retention time as well. A BL2 capacitance of 20fF, which is a reasonable estimate for a 512-cell BL stringinthe28nm-FinFETtechnology,wasassumedforthesimulationsofFig.2-8.Inthis regard, we have checked the simulation results for possible read errors due to channelleakage currents in unselected cells in the BL string. Looking at the predicted transient currentsintheselectedandunselectedcells,weestimatethat~1000cellswouldbeneeded to cause an error, although that number is reduced when T2 is not optimally designed to minimizetheparasiticcapacitance,andtheVB1/G2marginisreducedasinFig.2-8.These checksalsoimplyreasonablestandbypowerassociatedwithunselectedcells,partlybecause thereadandwriteoperationsaredoneviaseparatebitlinesandthesourceanddrainofT1 are tied (to BL1).

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40 2.3.2 Data Retention/Disturb Characteristics Simulations Thedataretention/disturbcharacteristicsofthe2TFBGC,governedbyGIDLand IR currents in T1, are better than those of the counterpart 1T FBC [23] due to the undoped body,andcanbeimprovedbydesignoptimizationenabledbythe2Tstructure.Also,aswe mentionedpreviously,whenGIDLcurrentisusedforcharging,thegatecapacitanceofT1 augments CBi in (1), tending to increase the stored- charge and lengthen the retention time.FortheFBGCofFig.2-7,UFDG/Spice3predictionsofread-VB1/G2(t)resultingfrom worst-case,long-timeWLandBL1disturbstoholdandholdareshowninFig.2-9. For comparison, the read-VB1/G2(t) for long-time holds without disturbs is included; these resultsimply~1sretentiontimes.Theundermininghold-(withB1discharged)disturbs result in GIDL-current charging of B1, and the undermining hold- (with B1 charged) disturbs result in drain/source-junction IR discharging of B1. The retention times are impliedbyVB1/G2(t)relativetoVtofT2,whichisindicatedinthefigure.Wenotethatthis Vt could be tailored to optimize the tradeoff between data-retention times and read/write performance. The worst cases (holding with BL1 disturb and holding with WL disturb)show~1msretentiontimes,muchlongerthanthe100msin[23].Toexemplifythe retention time directly, we show in Fig. 2-10, the sensed BL2 voltage versus time correspondingtotheworst-caseBL1hold-disturb,contrastedwiththesensedT2current versus time corresponding to the same disturb. These UFDG/Spice3 predictions give interestinginsightsregardingdataretentionforvoltage-versuscurrent-basedsensing.Note the dramatic increase in the retention time afforded by (one-fin) voltage-based sensing versus current-based sensing. The latter time is about an order-of magnitude shorter, reflecting why multi-fin devices are needed for current-based sensing. In this case, the relativelossofthecurrentmargindirectlytracksthechangeinVB1/G2relativetoVtofT2

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41 in Fig. 2-9. However, for voltage-based sensing, the loss of the relative voltage margin depends on the current-voltage characteristics of T2, as well as the BL2 capacitance, and good T2 design with typical capacitance yields a much longer retention time. 2.4 Summary A novel 2T floating-body cell on SOI for embedded-DRAM was presented, and its operation was demonstrated and verified via process/physics-based device/circuit simulations,supportedbynumericalsimulations.Themainnoveltyistheuseofthefloating body of one transistor (T1) to directly drive the gate of the second transistor (T2), thereby giving dramatic improvement in signal margin while allowing voltage-based sensing. Physical insight then led to a modification (FBGC [35]) of the basic 2T-FBC structure, enabled by using GIDL current for T1-body charging, in which the source and drain of T1 areshorted,andbothtiedtotheprogrammingbitline(BL1).TheFBGC,whichisvirtually afloating-body/gatecell,totallyeliminatesthewrite(T1charginganddischarging)-power dissipation, while yielding better signal margin, longer data retention via voltage-based sensing, and higher memory density. The simulation-based demonstration of the FBGC used undoped nanoscale DG FinFETs,orITFETs[49],whicharepotentiallyscalabletoLg<10nm[49].Wethereforebelieve that FBGC DRAM is similarly scalable, and much more so than a 1T counterpart for which the gate-source/drain overlap (Leff < Lg) needed for GIDL current will limit its scalability. Because of the design exibility afforded by the 2T FBGC, the GIDL current can be controlled via optimal design of the G-S/D overlap in T1, which is merely a two-terminal charge-storage structure,withT2beingdesignedoptimallywithunderlapasdiscussedherein.Wenotethatscaling Lg will tend to reduce the effective storage capacitance of the 2T cell, i.e., the oxide and gate

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42 capacitancesofT1andT2whichaugmenttheright-handsideof(1)forT1(althoughthenheight could be kept high to offset this reduction without undermining the increased memory density). Thus, less D Qp will be stored, although the signal margin will not be undermined. However, the scalingofthenthicknesswithLgwillreducetheS/D-junctionIRandIG,implyingthatthedata retention time will not be signicantly affected. Hence, we believe that FBGC DRAM can be scaled along with the FinFET-CMOS technology. This optimistic projection cannot be made for 1T-FBC DRAM, even if a DG FinFET is used.

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43 Figure 2-1.The2TFBC(T1andT2enclosedinthedashedsquare)inaDRAM array,whereB1/G2representsthefloating-bodystoragenodeofT1 thatistiedtothegateofT2.The2T-FBCconceptisapplicableto any SOI technology.B1/G2 T1 T2Word Line Bit Line 1Bit Line 2 (Ground)2T FBC

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44 T1 T2 Substrate BOX GND BL2 (D2) BL1 (D1) WL p+ p+ Poly P GND Metal 1 Metal 2 Metal 3 Silicon Oxide Nitride Silicide TiNFigure 2-2.Schematiccross-sectionalviewofa2T(n-channel)FBCfabricated viaITFETtechnology[47].TheplanarSOIlayer,dopedp+, providesthecontactfromthe(undoped)bodyofDGFinFETT1to the(p+poly/metal)gateofDGFinFETT2,withoutareapenalty. TheWL,BL1,BL2,andGNDmetalviasareindicated,asisthe pitch(P=2F)ofthetechnologynode.Lateraldiffusionofdopants fromtheSOIlayertothebaseoftheT1finstopsanysource-drain leakagecurrentthere.ForLg@ F/2(forwhichtfin@ Lg/2andhfin@ 4tSi[29]),weestimateaunit(two-fin)cellareaof<14F2,which impliesapotentialareapermarginmuchlessthanthatofa1T counterpart FBC [18].

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45 Figure 2-3. UFDG/Spice3-predicted transientsequentialoperationofa28nm DGnFinFET-based2TFBCcomprisingsingle-fintransistorswith height56nm;impact-ionizationcurrentwasusedforchargingB1, andgatecurrentandparasiticcapacitancewereneglected.Forthe readoperations,BL2wasprechargedto1.0V;theeffectivebit-line capacitancewasassumedtobe20fF, whichcorrespondsroughlytoa 512-bitlineinthetechnologyalludedto.NotethatVB1/G2isVBSofT1 and VGS of T2. 0.0481216202428323640444 8 Time (ns) -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 g() Write WL BL1 BL2 B1/G2Hold Hold Hold Write Read Read (Charge B1)(Discharge B1)

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46 Figure 2-4.Transientsequentialoperationofa2TFBC,analogoustothesimulation ofFig.2-3,predictedbya2-D,mixed-modesimulationusingTaurus. Theassumedrepresentativecellstructure,with28nmsingle-gateFD/ SOInMOSFETs,isshownintheinsetof(b),inwhichthedatastorage isreectedbythetransientcurrentinT2drivenbyVBSofT1.The transientpulsingsofthegate(WL)anddrain(BL1)ofT1,andtheT2 drain(BL2)voltagexedat0.1Vforthissimpliedsimulationare shownin(a).Theread-andread-operationsshowthepredicted signal margin, D IDS2@ 40 m A/ m m.(a) (b) 0.0102030405060708090100110 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0Voltage (V) Write Hold Read Write Hold Read HoldBL1 BL2 WL 0.0102030405060708090100110 Time (ns) -10 0 10 20 30 40 50 60 70 80 p+ p -p -n+n+n+n+ Word Line Bit Line 1 Bit Line 2 TiN TiNT1 T2 IDS2 ( m A/ m m)Write Hold Read Write Hold Read Hold(0.1V)

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47 Figure 2-5.TheFBGCstructureinaDRAMarray.ThegateofT2isdrivenbythe bodyofT1.ThesourceanddrainofT1aretiedtogether,thereby eliminatingT1-channelandsource-drainleakagecurrent,andeffecting a oating body/gate on T2. BL2 BL1 WL GND T2 T1 B1/G2

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48 Figure 2-6.TransientsequentialmemoryoperationofanFBGCasdepictedinFig. 2-5predictedbya2-Dmixed-modenumericalsimulationusingTaurus withastructuraldomainsimilartothatinFig.2-4,with28nmFD/SOI transistors.TheappliedWLandBL1voltagepulses,forGIDL-current charging,areshownin(a),alongwiththepredictedoating-B1/G2 voltage(relativetoground)transient(whichisVGSofT2)andtheBL2 voltage(VDS2)setto0.2V.TheT2currentin(b)reectsthebasic memoryoperation,showingacurrentmarginofabout50 m A/ m m.The T1currentin(b)reectsthenegligiblepowerdissipationduringtheB1 discharging (write ) as well as charging (write ).(a) (b) 0.0102030405060708090100110 -2.1 -1.8 -1.5 -1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9Voltage (V) BL1 BL2 B1/G2 WLWrite HoldRead Hold Write HoldRead 0.0102030405060708090100110 Time (ns) -10 -5 0.0 5 10 15 20 25 30 35 40 45 50 55Current ( m A/ m m) T1 Current T2 CurrentWrite HoldRead HoldWrite HoldRead Signal Margin @ 50 m A/ m m negligible write current

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49 Figure 2-7.UFDG/Spice3-predicted transientsequentialmemoryoperationofa 2TFBGCdesignedwithundoped28nmDGsingle-nnFinFETswith heightandwidthof56nmand14nm,respectively,and2nmgateoxide; T2isdesignedwith3nmG-S/Dunderlap,whereasT1has1.5nm overlaptoenableGIDL-currentcharging.TheappliedWLandBL1 voltagepulsesareshown,alongwiththepredictedoatingB1/G2 (relativetoground)andBL2voltagetransients;theBL2capacitance wasassumedtobe20fF.Thevoltage-basedsensing,viaBL2witha 0.5Vprecharge,showsasolidsignalmarginwithfast(<10ns)write/read times. 0.05101520253035404550Time (ns) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0Voltage (V) Write Hold Read Hold Write Read BL1 WL B1/G2 BL2 Hold

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50 Figure 2-8.UFDG/Spice3-predictedtransientsequentialmemoryoperationofthe 2TFBGCofFig.2-7,butwithT2identicaltoT1,withG-S/Doverlap. ThepredictedB1/G2andBL2voltagetransientsarecomparedwith thoseofFig.2-7.Notetheunderminedread-operationduetothe added parasitic capacitance of T2. Write Hold Read Hold Write Read B1/G2 BL2 Hold Heavy Curves: T2 w/ Overlap Light Curves: T2 w/ Underlap 0.05101520253035404550 Time (ns) -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8Voltage (V)

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51 Figure 2-9.Worst-casedataretention/disturbcharacteristicsofthe2TFBGCinFig. 2-7.reectedbyUFDG/Spice3predictionsoftheread-B1/G2voltage afterlengthydata(and)holdssubjecttocontinuousWLandBL1 disturbsasindicated.TheWLandBL1disturbsarethosethat underminethedatastorage,asgivenintheinFig.2-7.Thedataholds withoutthedisturbsareincludedforcomparison.TheT2threshold voltage is superimposed to indicate retention times. 10-710-610-510-410-3102 Time (s) 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55VB1/G2 (V) Holding w/o Disturb / Read Holding w/ BL1 Disturb / Read Holding w/ WL Disturb / Read Stored Stored Vt of T2

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52 Figure 2-10.UFDG/Spice3-predictedBL2read-voltage(after8nsreadtimeasinFig. 2-7)andT2read-current(withVDS2=0.2Vapplied)ofthe2TFBGCin Fig.2-7afterthelengthyworst-case(B1charged)holdssubjectto thecontinuousBL1disturb(-0.9V)inFig.2-8.Notethemuchlonger worst-caseretentiontime(~1ms)yieldedbythevoltage-basedsensing, whichisgovernedbythecurrent-voltagecharacteristicsofT2aswellas the BL2 capacitance (assumed to be 20fF). Voltage Sensing of Current Sensing of (BL2 is precharged to 0.5V) (VDS2 = 0.2V) 0.0 0.1 0.2 0.3 0.4 0.5BL2 Voltage (V) 10-710-610-510-410-310-2Time (s) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0T2 Current (mA/fin) Holding w/ BL1 Disturb / Read

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53 Table2-1. Charging/discharging-currentcomparisonbetweenthe FBGC and 1T FBCs Current (A/ m m)FBGC Impact ionizationGIDL Charging1.3x10-84.0x10-51.5x10-8Discharging1.2x10-78.0x10-4>1x10-3

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54 CHAPTER 3 "P+ SOURCE" FLOATING-BODY/GATE CELL: A MANUFACTURABLE NANOSCALE EMBEDDED DRAM CELL 3.1 Introduction In Chapter 2, we suggested a novel 2T FBC in which the floating charged/ discharged body of one transistor (T1) directly drives the gate of a second transistor (T2), therebyremovingthebody-factorlimitationofthesignalmargininherentin1TDRAMcells [32].Viasimulations,wedemonstratedthesuperiorsignalmarginofthe2Tcellrelativeto the 1T FBCs, and we showed how the power dissipation is reduced dramatically in a floating-body/gate version of the 2T structure (FBGC1). AnissueoftheFBGC1istheprocessintegrationfortyingthebodyofT1tothe gate of T2, which undermines cell area and memory density. We address this issue in this chapter, proposing a simplified, easily manufacturable version of the FBGC (FBGC2), whichiscompatiblewithconventional,planarSOIandDG-FinFETCMOStechnologywith @ 8F2 cell area. Numerical simulations and measurements of a fabricated prototype of the new cell demonstrate the basic memory concept, and also imply significant performance superiority over the 1T FBCs, as well as the FBGC1. 3.2 "P+ Source" Floating-Body/Gate Cell Concept ThenewversionoftheFBGCisillustratedinFig.3-1.Thedistinguishingfeature ofthissimplifiedcellisthep+regionofT1,whichreplacesthen+sourceintheoriginal2TFBGC structure [35]; T1 is now a gated diode. The p+"source" enables an easy, direct connectionoftheT1bodytothegateoftheT2MOSFETasindicatedinthefigure.Thecell can thus be easily processed in any SOI technology, using planar or quasi-planar (e.g.,

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55 FinFET)devices(oreveninbulkSiwithT1inpolysilicon).GIDLtunnelingcurrentinT1, controlledbythewordline(WL=G1)andtheprogrammingbitline(BL1=D1),isusedto chargethefloatingbody/gate(B1/G2),i.e.,writea.Aforwardbiasonthediode,defined by BL1 and the B1/G2 voltage (VB1/G2), is used to discharge B1/G2, i.e., write a The storeddatacanbesensedviavoltageorcurrentfromthereadbitline(BL2=D2)tiedtoT2. For current sensing, the BL2 voltage can be high for increased margin, unlike in 1T cells subject to read-disturbs. In addition to easing the manufacturing of the FBGC, the p+"source"enhancesthetransientG1-B1couplingviathefringe/overlapG1-"S1"capacitance, which can be exploited to improve the cell performance as we show. Indeed, the design flexibilityaffordedbythenewFBGCstructuredistinguishesitfromallthe1TDRAMcells, and can yield superior overall performance. 3.3 Operation and Performance of the "P+ Source" Floating-Body/Gate Cell We verify and demonstrate the operation of the new FBGC first by numerical simulation using Taurus [40]. The 2-D structural domain used for the (mixed-mode) simulation is what is shown in Fig. 3-1. We assume 28nm FD/SOI nMOSFET structures, with T1 being a gated diode as described above. The p+ "S1" is tied directly to G2. The assumedgaussiansource/drainlateraldopingprofiledefinesabouta2nmG-S/Doverlapin both devices; the T2 threshold voltage (Vt) is about 0.2V. Predicted results for a transient sequential memory operation are shown in Fig. 3-2, including the floating-B1/G2 voltage transient. The results, with nanosecond-scale write and read times, demonstrate the basic operationofthecell,showingthatthefloatingbodyofT1effectivelydrivesthegateofT2 andyieldsoutstandingsignalmargin.ThepredictedT2currentmargin(220 m A/ m mforVBL2

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56 = 0.2V) is more than 4 x -larger than what we predicted for the original 28nm FBGC in a similar simulation [35], and more than 10 x -larger than that predicted for the 1T-FBC counterpart [23]. We attribute the dramatic increase in the margin to the added WL-B1 capacitive coupling mentioned above, which is especially significant at times when the intrinsic gate capacitance is small during the transient operation of the cell. It results in a largerread-readmarginforVB1/G2(0.75Vvs.0.41VfortheoriginalFBGC[35]), whichcanbeoptimallypositionedrelativetoVtofT2.Thehighmargin,whichcanbemade even higher via higher VBL2 as noted, implies high effective density (margin per area) for the new FBGC. With the direct B1-G2 connection, the simplified FBGC cell size is @ 8F2, which is much smaller than the original FBGC [35] and comparable to the 1T/1C DRAM cell. Further, the predicted write-power is negligible since there is no T1 channel (or BJT [42]) current, unlike in the 1T DRAM cells. 3.4 Experimental Demonstration of the "P+ Source" Floating-Body/Gate Cell Discrete DG nFinFETs and FinFET-based gated diodes were fabricated at SEMATECH.Thedeviceshaveundoped,20nmfin-bodies,TiNgates,andHf-basedhigh-k dielectric with EOT = 1.3nm, Which is shown in Fig. 3-3. The FinFET gate length (Lg) is 120nm, and that for the p+-p--n+ gated diode is 500nm. Measured current-voltage characteristicsofthegateddiode,inFig.3-4.showadequateGIDLcurrent,withnegligible gatetunnelingcurrent(evenwiththelongLg).Measuredcurrent-voltagecharacteristicsof the FinFET with a high Vt of almost 0.5V (as for long Lg [51]) is shown in Fig. 3-5. We demonstrate the memory function of the new FBGC using a prototype created by hard-

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57 wiringB1ofagateddiodetoG2ofaFinFETataprobestation.Thecircuitconfigurationis shown in Fig. 3-6. Thedemonstrationisthusbasedonslowtransientmeasurementsbecauseof straycapacitance.Wefirstdemonstratethevoltage-basedsensingenabledbytheFBGC; measuredresultsofsequentialwrite/hold/readoperationsforand,which correspondtoFig.3-2,areshowninFig.3-7.Thefunctionalityofthenewcellisclearly exhibited;theT1bodyeffectivelydrivestheT2gate,andtheT2drain(~BL2)voltage transientindicatesthestoreddatawithasolidmarginsetbythesupplyvoltage.Such voltagesensingisperhapsthepreferredoptionforthenewFBGCbecauseoflonger retentiontimes[33],(whichcanbegenerallyoptimizedduetodesignflexibilityafforded bythe2Tcell)andlowerpower,aswellaslesssophisticatedsensingcircuitry.Alsoin Fig.3-8weshowmeasuredresultsofacurrent-sensingoperationofthenewFBGC prototype.Wehaveusedahigherbit-linevoltage(VBL2)forhighmargin,enabledbythe 2Tcellasnotedabove.TheFDbodyofT2preventsanyread-inducedVtshifts,e.g.,due toimpactionization-currentcharging.TheresultsinFig.3-8showaveryhighsignal marginof340mA/mm,evenwiththehighVt.Thisisarecordcurrentmargin,evenhigher than that reported for the BJT-based FBC [42]. 3.5 Summary Wehavedemonstratedasimplified,superiorversionoftheFBGC,by numericalsimulationandfabrication/measurement.Thenew2Tcelloffersveryhigh signalmarginandultra-lowpowerdissipation.Retentiontimesareanticipatedtobe comparableto,orlongerthan,thoseof1TFBCs.Theeasedfabricationprocessofthenew

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58 FBGCmakesitcompatiblewithplanarorquasi-planarCMOStechnology,withhigh effectivedensity.ItcanthusenablemanufactureofembeddedDRAMinthenearfuture,at low cost and with superior performance.

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59 Figure 3-1.ThesimplifiedFBGCstructure,onSOI,inaDRAMarraywithtwo bitlines.Thep+"source"ofT1(nowagateddiode)facilitatesthe B1-G2connectioninthetechnology,anditimprovesthecell performance because of additional WL-B1 capacitive coupling. p -n+n+ WL BL1 BL2 T2 B1/G2 p -n+p+T1

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60 Figure 3-2.T ransientsequentialmemoryoperationofthenewFBGCstructure(FD/ SOI-basedwithu ndopedthinbodies,midgapworkfunction(TiN) gates.)in Fig.3-1predictedbya2-Dmixed-modenumericalsimulation usingTaurus.TheappliedWLandBL1voltagepulses,forGIDL charging,areshownin(a),alongwiththepredictedoating-B1/G2 voltagetransient;theBL2voltageissetto0.2Vforcurrentsensing.The T2currentin(b)reectsthebasicmemoryoperation,showingasignal margin of 220 m A/ m m. -2.1 -1.8 -1.5 -1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2Voltage (V) 0.0102030405060708090100 Time (ns) -50 -30 -10 10 30 50 70 90 110 130 150 170 190 210 230 250T2 Current ( m A/ m m) Write HoldRead Hold Write HoldRead Write HoldRead Hold Write HoldRead BL1 WL B1/G2 Signal Margin @ 220 m A/ m m VBL2 = 0.2V

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61 Figure 3-3.Cross-sectionTEMoftheFinFETstructureusedforbothT1(gated diode)andT2(standarddiffusedDGtransistor)ofthenew-FBGC prototype.Thefindimensionsare20nmwideby80nmtall.The insetisahigh-resolutionTEMofthegatestackshowingthescaled Hf-based dielectric with ALD TiN metal.

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62 Figure 3-4.Measuredcurrent-voltagecharacteristics(pertwicenheight)ofthe p+p-n+gateddiodeformedfromadouble-gatenFinFETstructurewith ap+"source"(S=B);Lg=500nm,EOT~1.3nm,andtSi~20nm.The body current (IB) is the GIDL current. ID IB IG I (A/ m m)10-710-810-910-1010-11 VG (V) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 G D B VD=1.2V, VB=0

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63 Figure 3-5.Measuredcurrent-voltagecharacteristics(pertwicefinheight)of thedouble-gatenFinFET;Lg=120nm,EOT~1.3nm,andtSi~ 20nm. VDS=1.2V VDS=0.05V IDS (A/ m m)10-310-410-510-610-710-810-910-1010-1110-1210-13 VGS (V) 1.2 0.9 0.6 0.3 0.0 -0.3 -0.6 -0.9 -1.2

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64 Figure 3-6.Circuitconfigurationofthemeasurementsetup.ThebodyofT1is connected to the gate of T2 via cable. WL BL1 BL2 BL2 RL B1/G2 T2 T1 ~60pF (stray capacitance)

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65 Figure 3-7.Measuredtransientsequentialwrite/hold/readoperationsfor andinthenew-FBGCprototype.Thevoltage-basedsensing option(withinverselogic)isclearlydemonstratedviaVBL2,with lowRL=100K W .Thestraycapacitance(~60pF)oftheexternalB1G2 wire underlies the abnormally slow transient. 0V 0V 0V 0V -1.2V 1.7V -1.7V 0.7V -0.8V1.2V Hold Write Read Write Read Hold HoldVB1/G2VBL2 VBL1VWL Time

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66 Figure 3-8.Measuredtransientsequentialwrite/hold/readoperationsfor andinthenew-FBGCprototype,demonstratingcurrentsensing (withinverselogic).ThecircuitshowninFig.3-6wasused,with highRL=200 W andVBL2=1.2V,whichyieldsa340 m A/ m m margin reflected by the 136mV variation of VBL2. 0V 0V 0V 0V -1.2V 1.7V -1.7V 0.7V -0.8V1.2V Hold Write Read Write Read Hold HoldVB1/G2VBL2 VBL1VWL Time (250ms/div) 136mVVBL2 1.2V 0.8VVoltage Senssing Current Sensing

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67 CHAPTER 4 PHYSICAL INSIGHTS AND MODELING OF GATE-INDUCED DRAIN LEAKAGE CURRENT IN FLOATING-BODY CELLS 4.1 Introduction To avoid excessive write- power dissipation, FBCs, such as 1T cells and FBGCs, utilize the GIDL current to charge the body of the storage device [23]. However, due to the floating body of the SOI MOSFET, the formation of strong accumulation under the gate, which enables the band-to-band (BTB) tunneling process, is undermined in nanosecondsoperations.Hence,thetransientGIDLcurrentisdifferentfromtheDCGIDL current.Normally,transientGIDLcurrentissmallerthantheDCGIDLcurrent.Bykeeping theWLbiasrelativelylow,thestatecanbesafelystored.However,for-stateholding, negative WL bias and positive BL disturb voltages tend to generate GIDL current, which will charge up the body and destroy the state [23][30]. In the FBCs, especially the nonclassical-MOSFET FBCs with undoped and thin body (which significantly suppresses thethermalgenerationcurrentinthePNjunctions),GIDLcurrenthasbeenproventobethe majorkillerofthe-stateretentiontime.Itlimitsthisdisturbretentiontimeto<100msin most of the FBCs being examined. In this chapter, we study the hole redistribution in the nanoseconds transient operations and its impact on the GIDL current. Based on a better understanding of the transient GIDL current, we attain physical insights on optimizing the applied biases and device structure. The electrical performance of FBGC2 presented in Chapter 3 is heavily basedontheperformanceofT1,whichisathree-terminalgated-diode.So,itispossibleto optimize the write- time and the state retention time in the FBGC design by tuning the body bias. But due to lack of body-voltage dependence modeling, the numerical

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68 simulation tools cannot predict the BTB tunneling current reliably. To resolve this issue, based on our physical insights on the body voltage-dependent BTB tunneling current, an analyticalmodelisdevelopedtodescribetheGIDLcurrentintwocases:depletioncaseand accumulation case. The model, which is consistent with experimental data, demonstrates that, for given negative gate bias and positive drain bias, the GIDL current will increase whenthebodyvoltagedecreases,andtendstosaturatewhenthebodyvoltagebecomesmore negative, i.e., the channel becomes depleted. Due to the saturated characteristics on GIDL current, it is difficult to reduce the unwanted GIDL current in holding- state with BL disturbbytuningbodyvoltage.So,anoveldevicestructureorwritemechanismisneeded to resolve the conflict between the write- and hold- operations. 4.2 Non-Quasi-Static Hole Redistribution and Its Effect on GIDL current AnyFBCbodychargingprocessviaGIDLcurrentisassociatedwithafast,nonquasi-static(NQS)redistributionofholesinthefloatingbody.But,thisNQSredistribution hasnotbeenpreviouslyacknowledged[23].Forexample,intheFBGC,toenabletheGIDL duringcharging,WLvoltagedropstonegativevoltageandBLincreasestopositivevoltage in1ns.However,sincethebodyisisolatedfromthesubstrate,itcannotsupplyenoughholes to establish a surface accumulation condition in T1 needed for the gate-controlled BTB tunneling of electrons to the drain/source suddenly. The holes in the body to gate contact will migrate to the surface of the T1 and the body voltage drops to more negative to cause morethermalgenerationcurrenttoestablishtheaccumulationlayer.Thisphysicalprocess resultsinthetransientGIDLchargingcurrentwhichisdifferentfromtheDCGIDLcurrent, asexemplifiedinFig.4-1.Predicteddraincurrent-gatevoltagecharacteristicsofT1inthe

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69 FBGC, without T2 tied to B1, for varying VGS sweep times are shown, along with corresponding hole-density distributions across the body.Initially, the transient GIDL currentismuchsmallerthantheDCGIDLcurrentduetothelessstrongaccumulationlayer whichdegradestheelectrontunnelingprobabilityformbodytodrain.Afteracertainoftime (1ms), the strong accumulation layer is former and enables a larger tunneling proability, hence GIDL current increases. The NQS effect is reflected, revealing that fast-transient GIDL current flows, but is less than the DC GIDL current, which is hence not a reliable metric for FBC design, e.g., for defining the crucial WL and BL voltage pulses. 4.3 Body-Bias Dependence of Gate-Induced Drain Leakage Current As we described in the introduction, GIDL current is very important in the operation of FBCs and retention time prediction. Hence, a good understanding and an accuratephysicalmodelingofBTBtunnelingisneeded.Notethatthenumericalsimulation tools is inadequate to model the GIDL current with body bias [40]. It cannot predict the correctcurrentwhenVBisapproachingtoVDandeventuallyVBequalsVD.Thetunneling theory predicts that the tunneling current should drop with VB approaching VD and reach zerowhenVB=VD.ThemeasurementdataalsoexemplifytheGIDLcurrentdependenceon thebodybias,asshowninFig.4-2.However,thenumericalsimulationtoolspredictfinite current when VB=VD. 1-D BTB tunneling analytical model has been developed for GIDL current in [52].But,themodelignoresthebodybiasdependence.Quasi-2Dmodelisalsoproposedin [53][54].Modelin[53]considersthebodybiasdependencebyaddingaempiricalparameter torepresentthelateralfield.Therefore,thismodelisnotphysicsbasedmodel.Modelin[54]

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70 is a physics based model, but it is a complicated integral-form equation. No analytical dependencecanbeseenthere.Basedonthepreviouswork,wedevelopananalyticalmodel for GIDL current. Fig. 4-3 is the cross-sectional view of the gated diode which used to derive the GIDLcurrentmodel.Thebanddiagramalongtheverticaldirectionattheoverlapregionis shown in Fig. 4-4. Actually, the band-to-band tunneling process is 2-D problem. We supposetoneglectthereverse-biasedPNjunctionleakagecurrentbetweenbodyanddrain. Duetoveryhighverticalelectricalfieldattheoverlapregionnearthesurface,electroncan tunnel from the valence band to the conduction band, as shown in Fig. 4-4. Then, holes which are left in the surface are swept to the body by the lateral electrical field. From the band diagram figures in Fig. 4-4, we can see the tunneling current is determined by two factors: (1) the vertical electrical field which implies the actual tunneling path; (2) the overlap region between conduction band and valence band, which implies the tunneling probability. These two factors have dependence on VB, hence, the tunneling current is a function of VB. Refer to the measurement data in Fig. 4-2, we can qualitatively go through the GIDLcurrentdependenceonVB.Fig.4-2showsthatGIDLcurrentisalmostsaturatedwhen VB goes to more negative and demonstrate strong dependence on VBwhen VB is close to VD.Itiscanbeexplainedqualitativelylikethis.WesupposeVGisnegativeenoughandVDis positive enough to cause very high vertical electrical field for tunneling at the overlap region.Therefore,theGIDLcurrentisastrongfunctionofVB.IfVBisclosetoVD,e.g.VBgoes to VD=1.2V, it means that VGB is sufficient to induce a strong accumulation in the channel. This implies VB can tune the vertical electrical field and overlap between

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71 conduction band and valence band through the accumulation layer, as shown in Fig. 45.Viceverse,ifVBbecomesmorenegative,e.g.VBisclosetoVG,thechannelregiontends tobedepleted.ThisimpliesVBcannottunetheverticalelectricalfieldandconductionband andvalencebandoverlapduetotheabsenceoftheaccumulationlayer,asshowninFig.4-5. 4.4 Model Development for Body Bias-Dependent Gate-Induced Drain Leakage Current Based on above qualitative analysis, we build up an analytical model for the GIDLcurrent.Wewillusethemodeltophysicallyinterpretthebodybias-dependentGIDL current. The GIDL current will be separately modeled in two cases: depletion case and accumulationcase.Indepletioncase,GIDLcurrenthasveryweakornodependenceonVB. Itwillsaturatewithchannelbecomesdepleted.Inaccumulationcase,GIDLcurrentshows strong dependence on VB. A: Depletion Case: Assuming depletion[55], the overlap region forms a depletion layer and the vertical electrical field Esi can be expressed as (4.1) where N0 is the doping concentration in the drain region or overlap region, eSi is the dielectric constant of the silicon, and q is the electron charge; x is the depletion width normaltotheSi-SiO2interface.FromGaussianlaw,attheSi-SiO2interface,theelectrical displacement should be continuous: (4.2)E Si qN 0 e Si ----------x = E Si e Si E ox e ox =

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72 whereEoxistheelectricalfieldacrosstheoxide; eoxisthedielectricconstantoftheoxide. The depletion with x can be expressed as [38] (4.3) where ysisthesurfacepotentialorbandbendinginthebanddiagram.From[38],theMOS system along the vertical direction in the gate-drain overlap region can be expressed as (4.4) wheretoxisthegateoxidethickness;VFBistheG-Dflatbandvoltage.Combiningwith(1), (2), (3) and (4), we express the band bending as (4.5) From(1)-(5),theverticalelectricalfieldEsiandbandbendingcanbecalculated. Referring to [38][56], we express the three-terminal band-to-band tunneling as (4.6) where m0 is the electron mass and h is the Plank constant. B: Accumulation Case:x 2 e Si y s qN 0 -----------------= E ox V GD V FB y s t ox -------------------------------------------= y s V GD V FB () qN 0 e Si t 2 ox e 2 ox ----------V GD V FB () qN 0 e Si t 2 ox e 2 ox ----------+ 2 V GD V FB () 2 + = J 2m 0 q 3 y s E Si p h 2 E g 12 -------------------------------------8 p 2m 0 E g 12 3qE Si h --------------------------------------- exp =

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73 In the accumulation case, (4.1) is needed to be revised due to the unneglect of high hole concentration at the gate-drain overlap region. (4.1) can be rewritten as (4.7) where p is the hole concentration in the G-D overlap region. Since strong accumulation is establishedinthechannelandtheoverlapregion,wesupposetheholeconcentrationinthe channelatthecenterisalmostthesameastheholeconcentrationattheG-Doverlapregion. Then, the hole amount under the gate can be expressed as (4.8) where VFB(GB) is the gate-to-body flat-band voltage. We also have from (4.4) (4.9) whereVFB(GD)isthegate-to-drainflat-bandvoltage.Combining(4.2),(4.7),(4.8)and(4.9), we get (4.10)e Si E Si qN 0 xpxd0 x Dep+ = pxd0 x DepV GB V FBGB () y 0 () q --------------------------------------------------------------e ox t ox -------- = E ox V GD V FBGD () y s t ox ---------------------------------------------------------= y s V GD V FBGD () ()=V GB V FBGB () y 0 () qN 0 e Si t 2 ox e 2 ox -----------qN 0 e Si t 2 ox e 2 ox -----------2 2V GD V FBGD () () V GB V FBGB () y 0 () + [] qN 0 e Si t 2 ox e 2 ox -----------+ ++

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74 With (4.6), we can calculate the band-to-band tunneling current in the accumulation case. Regardingthedepletioncase,theGIDLcurrentisdeterminedby(4.5)and(4.6); (4.6) indicates GIDL is a function of band bending ( ys) which is shown in (4.5). From the expressionof ysin(4.5), ysisnotafunctionofVB.So,theGIDLcurrentisnotafunction of VB, which is consistent with the experimental data in Fig. 4-2. It implies, for a given structure, GIDL current will saturate when VB becomes negative and makes the channel depleted.Asfortheaccumulationcase,theGIDLcurrentisdeterminedby(4.6)and(4.10). Unlike the depletion case, ys is a function of VB, as indicated in (4.10) and (4.7). So, the GIDLcurrentinaccumulationcaseisafunctionofVB.Equation(4.10)alsoimpliesthat yswilldecreaseasVBbecomesmorepositive.Smaller ysresultsinsmallertunnelingcurrent asindicatedin(4.6).TheexperimentaldataasshowninFig.4-2alsodemonstratethesame trendencyasthemodelpredicts.BasedonthisqualitativeanalysiswiththeGIDLmodelin two regions, we found that the GIDL current can be significantly reduced by applying positiveVB.But,unfortunately,whentheFBGCisinhold-statewithBLdisturbs,i.e., VG is biased at < -1V and VD is biased at > 1V, the GIDL current is not a function of VBand the current level is high enough to destroy the state in several miliseconds. The model tells us it is not possible to reduce the unwanted GIDL current in the hold- state to improve the retention time. 4.5 Summary NQSholeredistributioninthenanosecondstransientoperationsanditsimpacton the GIDL current are analyzed in this chapter. Relying on a better understanding of the transient GIDL current, we get physical insights on the dependence of GIDL current on body-voltage.Byoptimizingtheappliedbiasesanddevicestructure,theperformanceofthe

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75 T1whichisathree-terminalgated-diodecanbeimproved.But,sinceGIDLcurrentisused forwrite-anditalsothemajorcurrenttodestroythe-stateinhold-,thereisnoWL and BL biases combination can realize the desire DRAM performance. In order to resolve thisproblem,innovationshavetobeproposed.Chapter5willdemonstrateanewmethodto resolve this problem.

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76 Figure 4-1.A)Draincurrent-gatevoltagecharacteristicsofT1,biasedas shownintheinset,predictedbyTaurusforsweepsofVGSfrom 1.2Vto-1.5Vwithsweeptimesrangingfrominfinite(DC)to1ns asindicated.Thenearlyconstantcurrentsseenaredisplacement currentsintheG-Dparasiticcapacitance.Thefasttransientsreflect finitetimesforholestoaccumulateatthesurfaceoftheUTB,as showninB)bythepredictedholedistributionsacrossthebody(at thecenterofthechannel)forthevarioussweeptimesinA).Note, however,thatthereisaninitial,fastNQSaccumulationofholes, whichisenhancedbymorenegativeVGS,thatsupportstheGIDL current virtually instantaneously. -1.5-1.2-0.9-0.6-0.30.00.30.60.91.2 VGS (V) 10-1310-1210-1110-1010-910-810-710-610-510-410-3IDS (A/ m m) DC 1ns 10ns 100ns 1 m s 10 m s 100 m s 1ms 1s p+ p -n+n+ TiN 0.0000.0050.0100.0150.0200.025 Distance ( m m) 1017101810191020Hole Concentration (cm-3) 0.5V VGS(t) Floating Bodyp+ Region DC 1ns 10ns 100ns 1 m s 10 m s 100 m s 1ms 1s A B

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77 Figure 4-2.MeasureddependenceoftheGIDLcurrentonthebody,orjunction voltage of the diode. -1.2-0.9-0.6-0.30.00.30.60.91.2 VB(V) 10-1210-1110-1010-910-810-7IB(A/ m m) VGVD=1.2V VB VG: -1.4V to -0.8V

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78 Figure 4-3.Cross section of gated diode. n+ p-oxide Gate + VG + VB + VD Depletion Region Metallurgical Junction Vertical Direction x

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79 Figure 4-4.Banddiagramattheoverlapregionalongtheverticaldirectionwith the equilibrium condition. EFn=EFp=EFOxide Drain Gate qVG qVGD EcEv Electron

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80 Figure 4-5.A)Banddiagramattheoverlapregionalongtheverticaldirection withaccumulationatthesurface.B)Banddiagramattheoverlap region along the vertical direction with depletion at the surface. EFnOxide Drain Gate qVG qVGD qVBD EFp EFnOxide Drain Gate qVG qVGD qVBD EFp EcEvEcEvA B

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81 CHAPTER 5 FLOATING-BODY/GATE CELLS UPGRADED FOR ULTRA-LONG RETENTION TIME AND ULTRA-FAST WRITE TIME 5.1 Introduction AswediscussedinChapter4,theGIDL-currentratioofthechargingoperationandthe holding state with disturb determines the program time and the retention time of FBCs. The ITRS requires that the charging time should be less than 10ns and the worst-case retention time should be longer than 64ms [7]. We suppose the storage capacitance of the FBCs is about 0.05fF/ cell. Based on these parameters [7][30], we can roughly estimate the charging current needed for aDRAMFBCtobe~10-7A/cell,andtheleakagecurrentunderdisturbtobe~10-15A/cell.IfGIDL current is used to charge the body in FBCs, even though the body-bias dependence and the NQS effectcanreducetheGIDLcurrentsomeintheholdingstate,itisstillverydifculttomeetthe 108currentratioshownabove.Sincea1TFBCusesonlyonetransistortoperformwriteandread, the design exibility in this regard is limited. It seems that GIDL-based 1T FBCs cannot achieve the108currentratio,andthestate-of-the-artexperimentaldataprovethis[23].However,theFBGC isadifferentcase.Duetoitsunique2Tstructure,usingonetransistortowriteandanothertransistor to read, the FBGC offers more design exibility to reach a higher GIDL-current ratio. In this chapter, we will explore two FBGC design upgrades to get a higher current ratio that will lead to longer retention time, and to faster speed as well. 5.2 Floating-Body/Gate Cell Upgraded for Ultra-Long Retention Time 5.2.1 Rationale Retentiontimeisakeyperformanceindicatortoqualifytheemergingmemorycell.The state-of-the-art experimental data have demonstrated that the worst-case retention time of most

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82 FBCs is shorter than 100ms [30]. The small storage capacitance inherent in the FBC presents a seriousconcernregardingretentiontime.Sincetheexcessholesarestoredonthegatecapacitance, whichissupportedbynegativegatebiasduringholding,themajorstoragecapacitanceoftheFBC isontheorderofafewfF/ m m,(e.g.,1fF/ m mforLg=65nmwithtox=3nm),whichisthreeorders smaller than that of the conventional 1T/1C-DRAM capacitance. In order to meet the DRAM retentiontimerequirementoftheITRS[7],i.e.,64msforworstcase,theleakagecurrentshouldbe minimized to be lower than ~ 10-14A/ m m. Two physical mechanisms, i.e., Shockley-Read-Hall (SRH) recombination and BTB tunneling, result in the loss of stored data, if we suppose the gateoxidetunnelingcurrenthasbeenwellcontrolledtobelowerthan~10-15A/ m m.Forthecaseofthe holding- state, negative BL disturb voltage leads to recombination at the drain junction which tendstodischargethebody.Infact,withacarefullydesignedjunctionproleandlessnegativeBL voltageinwrite,a-stateretentiontimelongerthan1scanbeachieved[18].Onthecontrary, for the case of holding-, due to the classical G-S/D overlap structure with conventional MOSFET-based FBCs, even with a well-dened junction, the BTB tunneling current is the killer oftheretentiontime.BTBtunnelingcurrent,i.e.,GIDLcurrent,limitsthe-stateretentiontime to be shorter than 100ms for most FBCs. Because of the writetime requirement of DRAM, state retention time in the worst case is close to ~10 m s for GIDL-based FBCs [23]. A design innovation, i.e., gate-source/drain non-overlap/underlap, has been proposed to increase -state retentiontimeintheBJT-basedFBC[57].Unfortunately,FBCswithG-S/Dnon-overlap/underlap needhigherBLvoltagetodrivetheparasiticBJTtobelatched,whichisthebasisofthememory operation.Therefore,higherBLvoltagewillalsocausehigherelectricaleldwhichleadstohigher unwantedGIDLcurrentintheBL-disturbcase,andthe-stateretentiontimetendstobelessthan

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83 100ms. Fundamentally, since G-S/D overlap is vital to perform fast charging in FBC operation, realization of long -state retention time is very challenging in FBC design. Beyond that, the relative high operation voltages (e.g., > 2.5V) needed in the FBC writing schemes lead to many concerns of the DRAM reliability [58]. For example, hot carriers generated by the high electrical eld in the write operations can cause variations in the threshold voltageortheparasiticBJTturn-onvoltage(VonorBVCEO),whichinturnunderminetheyieldof the FBC technology. At the same time, high-voltage operation will also imply higher dynamic power.ThedynamicpowerisproportionaltoCV2[8],whereCisthecapacitanceforchargingand V is the operation voltage. Since FBCs need to be refreshed periodically, decreasing V plays a signicant role in reducing the dynamic power, and therefore the total power dissipation. In summary, even though a very long gate-drain (G-D) underlap has been shown to increase the retention time (in a BJT-based FBC) by decreasing the GIDL current, it tends to underminethewrite-process,whichisenhancedbyG-Doverlap.HigherBLvoltagesarethus needed, portending cell-reliability issues and power dissipation issues. This tradeoff reects a fundamental problem of (1T) FBCs: long retention times require suppression of a mechanism needed for writing data fast (<10ns). The higher operating voltages (>2.5V) result in hot carrierandhigheld-inducedMOSFETdegradations,andhigherdynamicpower.Indeed,thereisaclear, unavoidable tradeoff among power dissipation, write time, and data retention, which, with questionable reliability, undermines the FBC viability. MoreFBCdesignexibilityisneeded.Asmentionedinpreviouschapters,the2TFBC, or floating-body/gate cells (FBGC1 and FBGC2) [35][36], which provide such flexibility, areproposed.Weshowherein,vianumericalsimulations,howtheFBGCinChapter3(i.e., FBGC2,whichsolvestheprocess-integrationproblemoftyingthebodyofonedevice(T1)

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84 to the gate of the other (T2), but does not resolve the noted short retention-time problem) canbemodified(toFBGC3)toachieveverylongretentiontimesunderworst-casedisturbs while maintaining good DRAM performance, including large signal margin and low operating power, and implying good reliability. 5.2.2 FBGC3 Concept, Operation, and Performance Our ultimate FBGC3 is evolved from FBGC2. The structure of FBGC3 (with two bit lines)isillustratedin Fig.5-1;T1andT2canbeof arbitrarySOIdesign,evenwithfullydepleted, ultra-thin bodies. The structure is almost the same as FBGC2, except for the added long G-D underlapinT1(whichisactuallyagateddiode).AkeydifferencebetweenthetwocellsishowT1 is charged (i.e., how is written). In FBGC2, the charging is done via GIDL current under an accumulation condition, dened by a negative word-line (WL) bias and a positive bit-line (BL1) bias. This operation, with G-D overlap to enhance the GIDL current, leads to short retention time under BL1 disturb, as in the 1T FBCs. Incorporating a long G-D underlap to suppress the BL1-disturb effect does not render FBGC2 generally viable because the write- operation is undermined; a write-/hold- charging-current ratio of ~108, which is needed for acceptable FBC memory operation [7], is impossible to achieve by any combination of WL and BL1 biases whentheaddedeffectofWLdisturb(tohold-)isadequatelycontrolled.Thisdilemmareects the fundamental problem noted before. ThenoteddesigndilemmaisresolvedbyFBGC3,whichseparatesoutthewrite-and hold- BTB tunneling currents. The write- process is now done by inverting the T1 channel viapositiveWLbias,inducingahigh-eldn+-p+junctionintheoverlapped-sourceregionofT1 (indicated in Fig. 5-1) where the body-charging BTB tunneling (with positive BL1 bias) now occurs.Thehold-process,withthechannelregionaccumulated(vianegativeWLbias),isnow

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85 dissociated with the write- process, and the GIDL current induced by BL1 disturb can be effectivelyminimized(viatheunderlap)togetacceptableretentiontimewithoutundermining the write- process. Further, FBGC3, unlike FBGC2, can use the same WL voltage for writing both and enabling row programming in a memory array and virtually doubling the write speed while eliminating WL-disturb effects. And, unlike FBGC2, FBGC3 enables the option of using only one bit line (i.e., tying BL1 and BL2 in Fig. 5-1), albeit with a performance tradeoff, which will be discussed later in this chapter. InFBGC3,T1isnowlikeatunnelingFET(withitssource/bodytiedtothegateofT2) in which the on-state (charging) current depends on the gate (WL) and drain (BL1) voltages, as wellasthebodyvoltage(VB1/G2)[59].ThisBTBtunnelingcurrent,comparabletoGIDLcurrent, can be adequate for fast write but the gate-source overlap is crucial. (The current could be increased signicantly by using a Ge-based heterostructure for T1 [59].) The SenTaurus [60]predicted BTB tunneling current-voltage characteristics shown in Fig. 5-2 rev eal the importance of the overlap (> 1nm) as well as sensitivity to bias (VGS). Note, in FBGC3 operation, that the charging current will decrease with increasing VB1/G2since the drain and gate voltage are effectively reduced. This is evident in the write- process as illustrated by operation-sequence simulationstobediscussedlater.So,thetunnelingFETT1hastobeasymmerticallydesignedwith overlap at the p+ source side and underlap at the n+ drain side. To get longer retention time with BL disturb, BTB tunneling current should be eliminated when WL is negative. The G-D underlap design is very important to reduce the unwanted BTB tunneling (GIDL) current effectively.ForagivenG-Soverlapof1nm,predictedBTBtunnelingcurrentswithdifferentG-D underlap are shown in Fig. 5-3. The simulation results suggest at least 20nm of G-D underlap is neededtokeepthetunnelingcurrentlowerthan10-15A/ m m,andthusyieldlong-stateretention time.NotealsothattheG-DunderlapreducestheparasiticcapacitanceassociatedwiththeWLand

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86 BL1, which is very helpful in reducing the dynamic power. Predicted I-V characteristics of the asymmetricalT1areshownin Fig.5-4. FromFig.5-4,wefindthatthethresholdvoltageofT1is relativehigh,i.e.,closeto1V.WithVGS<1V,wefindtheBTBtunnelingcurrentissmallerthan 10-7A/ m m, which implies that >1V operation is needed to guarantee FBGC3 works properly. Optimization of T2 is easier than T1. First of all, T2 should be a CMOS technologycompatibleMOSFET.ThemajorgoaloftheoptimizationistosettheVtofT2properlytoachieve highersensemargin.Inoursimulation,for28nmn-typeFD/SOIMOSFET,Vtissetat0.3V.The predictedID-VGcharacteristicsofT2areshownin Fig.5-5. AnotherimportantconstraintforT2 optimizationisthepossibleread-errorduetotheleakagecurrentinunselectedcellswhichshare theBL2.Theworstcaseisthatalltheunselectedcellsareinthe-state,whichhashigherB1/G2 voltagesandwhichtendstoturn-onT2oftheunselectedcells.Bycheckingthetransientcurrents inthesimulations,weestimated~105cellscanbeconnectedtoBL2withoutreadingerror.TheGS/Dfringecapacitances,aswellastheoverlapcapacitance,shouldalsobereducedtominimizethe dynamic power dissipation. We now demonstrate the FBGC3 memory operation via numerical simulations, showing its superior performance and data retention in Fig. 5-6.We use SenTaurus [60] for the simulations, selecting the physical and representative Hurkx BTBand trap-assisted-tunneling models (for charging) and doping-dependent carrier lifetimes with maximum values of 10-7s (for discharging). SenTaurus prediction of a basic memory sequence of FBGC3, comprising planar 28nmFD/SOIUTBdevicesinChapter3,isillustratedinFig.5-6.Oursimulationsshowedthatthe G-D underlap length in T1 must be >20nm to adequately suppress the GIDL current; so, we assumed 30nm. Note in Fig. 5-6 the novel write- process, with channel inversion induced by a +2VWLbias;a+1.2VBL1biasdrivesadequateBTBtunnelingintheinducedn+-p+junctionthat charges the T1 body (B1/G2) quickly, that is, charges all the capacitance associated with B1/G2

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87 node[35].NotethatsinceT2(withathresholdvoltageof @ 0.3V)isturnedonduringthewrite- process, its gate capacitance is predominate. However, the parasitic capacitances, e.g., the G-S/D fringingcapacitanceofT2,areimportantandmustbecontrolled[35].NotealsothatFBGC3must withstandaread(withpositiveWLbias)disturbwhenholdinga;thatis,someBTBtunneling can occur during read, which can undermine the hold This charging, due to VB1/G2 < 0 with inversion, is reected by VB1/G2(t) during the read- process in Fig. 3; it stops as VB1/G2approaches VBL1 = 0. Further, T2 is off and its gate capacitance is low, and hence very little hole charge is stored. This disturb is not a serious problem. The predicted current margin in Fig. 5-6 ( @ 70 m A/ m mwithVBL2=0.2V)isverygood.BytweakingtheWLandBL1pulses,weincreased themarginto>80 m A/ m m,but,giventheunavoidableuncertaintiesofnumericaldevicesimulation, the important message here is that FBGC3 yields much better margins that the 1-FET FBCs. We note that voltage-based sensing [35] can also be used with FBGC3. The SenTaurus-predicted worst-case retention characteristics, dened exclusively by BL1 disturbs (VBL1 = 1.2V for hold- and VBL1 = -0.8V for hold-, for the FBGC3 of Fig. 56),areshowninFig.5-7.A compositeretentiontimeof~10sispredicted!ThelongG-Dunderlap effectively suppresses the BL1 disturb-induced GIDL during hold without signicantly affectingthewrite-processasevidentinFig.5-6.Duringhold,thebody-drainforwardbias inT1duetotheBL1disturbislow,andthussoistheholerecombinationrate.Uncertaintiesinthe modeling of the carrier generation and recombination in SenTaurus imply some equivocalness in the predicted retention time, but its dramatic length, which is consistent with the experimental result in [61][62], cannot be disputed. Ofcourse,theFBGC3areaislargerthanthatof1TFBCs,butisaboutequaltothatof conventional1T/1CDRAM.Wefeelthearea-performancetradeoffiswellworthwhile.However, a stacked version of FBGC3 is feasible (even with T2 in bulk Si), which would resolve the area

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88 issue. Also, the obvious issues of scalability (with reduced storage (gate) capacitance, xed G-D underlapinT1forGIDLsuppression,andrelativelyhighoperatingvoltages)areconcerns,butnot so much as for 1T FBCs because of FBGC3 design exibility afforded by its 2T structure. BL1 and BL2 can also be tied together to perform the memory operation, as shown in Fig.5-8.The signalmarginisreduced.However,tyingBL1andBL2togetherishelpfultoreduce thecomplexityandpoweroftheperipheralcircuitsandmakesFBGC3looksliketheconventional 1T/1C DRAM. Further, it offers the possibility of utilizing current DRAM peripheral circuits without any revision. 5.2.3 Design Optimization Based on the optimization of T1 and T2, FBGC3 is re-designed for improved performance,i.e.,sensemargin,retentiontime,dynamicpower,andreliability.Bycarefully analyzingtheresultsinthepreviousFBGC3operationsequencesimulation,wefoundtwo issueswiththeFBGC3biasschemesandtheperformanceoftheFBGC3canbeoptimized by tweaking the WL and BL pulses. First, we observed two facts: VBL1 for write- is 0.8V, but can be higher to perform the same write-operation in less than 10ns; and VB1/ G2 for hold does not have to be as low as -0.6V. Based on these facts, the BL1 voltage for write can be raised to -0.4V, and the WL voltage for holding can be also raised to 0.5V.Underthesebiasingschemes,theB1/G2-to-D1PNjunctionisslightlyforward-biased intheholding-statewithBL1disturb.Itimplies-stateworst-caseretentiontimecould beverylong.And,-0.4VVB1/G2inhold-isalsolowenoughtoturnoffT2toavoidread- error. Raising WL voltage during holding can also beneficial to -state retention by reducing voltage difference between WL and BL1 which will result in unwanted GIDL current. Second, in order to increase the signal margin, a more positive WL pulse during

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89 readcanbeappliedtogethighersensemarginthroughWLtoB1/G2coupling.Withthese improvements, the memory operation sequence is re-simulated, as shown in Fig. 5-9. The results demonstrate 10 m A/ m m sense margin improvement. For the hold- state with BL1 disturb, as mentioned before, the retention time should be very long due to the slightly forward-biased B1/G2-to-D1/S1 junction. For hold- state with BL1 disturbs, the retention time should be longer than in the previous simulation, since less negative VWLsould suppress the BTB tunneling current. TheissueslistedaboveareobviousandcanbefixedbytweakingtheWLandBL pulses.But,thecapacitancecouplingbetweentheterminalsismorecomplicated.First,due toWL-to-B1/G2capacitancecouplingatthebeginningofwrite,thechargingefficiency decreasessignificantly.WhenWLisraisedforwrite,VB1/G2willincreasethroughG-S fringe capacitance and gate capacitance. With increasing VB1/G2, the effective WL-to-B1/ G2voltage,whichisVGSofT1,willreduce.EffectiveBL1-to-B1/G2voltagewhichisVDSofT1willreducetoo.BothofthesechangestendtodecreaseBTBtunnelingcurrent,andin turn decrease operation speed. Due to G1-S1 coupling, the VB1/G2 for hold is still relative negative even with the WL holding voltage of -0.5V. This is not necessary. Even thoughtheWL-to-B1/G2couplingcouldbehelpfultoraisetheB1/G2voltageinread,the totalcouplingeffectisnegative.Therefore,toresolvethecouplingissue,reducingtheG-S fringe capacitance could be considered. By adding an air spacer or void region, the G-S fringe capacitance is reduced in simulation. The predictedoperation results are shown in Fig. 5-10.Note that, in order to decrease dynamic power and improve retention time, the operation voltages for all terminals are re-designed. For example, for write VBL1 is 0.9V;forwrite,VBL1is-0.3V;forread,VWLis1.2V.Thedataretentioncharacteristics are shown in Fig. 5-11.The improvement of retention time is obvious, especially for

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90 stateretentiontimewithBLdisturb.Tuningthework-functionofT2isaneffectivewayto improve sense margin. In principle, increasing the work-function of T2, which tends to decrease the Vt of T2, results in higher sense margin, as shown in Fig. 5-12.But lower VtofT2couldcausepossibleread-error.Sincealargenumberofunselectedhold-cell andintentedread-cellsharethesameBL2,toguaranteetheread-operation,theread- current must be much greater than the hold- leakage current to avoid read- error. The read- and hold- currents for the same BL2 voltage is plotted in Fig. 5-12. With lower T2 gate work-function, the hold- current becomes close to read- current. It implies fewer memory cells can share the same BL2. The number of memory cells, which is determined by the ration of read- current to hold- current, is shown in Fig. 5-12. With the midgap gate of T2, ~105 memory cells can be loaded in the same BL2. 5.3 Floating-Body/Gate Cell Upgraded for Ultra-Fast Write Time ThewritetimeofFBGC3is~10ns.ForapotentialreplacementoftheSRAMcell,the write speed should be <1ns. In this regard,we propose another FBGC design modification (FBGC4)thatgivesultra-fastwritetimes,inadditiontogoodDRAMperformanceincluding large signal margin, low operating power, and very long charge-data retention times under worst-case conditions. Further, very good reliability is implied because of low-voltage operation enabled by FBGC4. WhereasFBGC2(Chapter3)[36]andFBGC3structuredT1asagateddiode,FBGC4 revertsbacktotheT1MOSFETstructureofFBGC1(Chapter2).ThenoveltyofFBGC4isthatT1 has a body-tied-to-source (BTS) structure; i.e., T1 is a BTS/SOI MOSFET with its B1/S1 connectedtothegate(G2)ofT2asillustratedin Fig.5-13. ThisnewdesignenablesT1tocharge and discharge G2 for write and write via channel current, which can yield ultra-fast write

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91 times(~100ps)atlowWLandBL1voltages(~1V).Forhold,theG2chargeistransferred,via fastdiffusion,toB1forstorageonthegatecapacitanceofT1,nowbiasedinaccumulation.Leaving thechargeonG2forhold,whichemulatestheconventional1T/1CDRAMcellwiththecapacitor replaced by the gate of T2, is not viable since the charge is too small. The charge must be moved fromG2toB1,andthisisenabledbytheinnovativeBTSofT1.Thistransferofthestoredcharge toB1forholdalsoavoidsafalsereadoperationwithouthavingtoaddareadaccesstransistor tothecell[63][64].ThenoveltyofFBGC4thenenablesuseofaMOSFETinlieuofthecapacitor inconventionalDRAM.Our2Tconceptallowsmemoryoperationwithsmallstoredchargesince the charge, in B1, is used to drive T2 for reading data without being signicantly expended. The other memory operations of FBGC4 are virtually the same as in the previous FBGC designs [35][36]. We demonstrate the basic memory sequence of FBGC4 using our physics-based compactmodelforPD/SOIorbulk-SinMOSFETs,UFPDB(Ver.2.5)[65],inSpice3.Weassume 90nmPD/SOIMOSFETs.UFPDB/Spice3-predictedmemorytransientsareshownin Fig.5-14. Note the novel write- and write- processes, which use T1 channel current to charge and discharge the gate of T2. This is an ultra-fast process, done with low WL and BL1 voltages as indicated in Fig. 5-14. The stored charge is moved to B1 for holding by dropping the WL voltage negative, which removes the T1 channel and creates an accumulation layer to hold the stored charge. We predict a T2 current-signal margin of approximately 30 m A/ m m, which, as for FBGC in general, is much better than margins typically achieved with 1T FBCs. We further note that the very long retention times, due in part to a long G-S/D underlap in T1 [34], can be even better in FBGC4 because of the low operational voltages enabled [66].

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92 5.4 Comparison of the Floating-Body DRAM Cells Since the first FBC was demonstrated in [15], FBC has evolved from impact ionization-basedFBCtoGIDL-basedFBC,andeventuallytothepopularBJT-basedFBC. Table5-1givesperformancecomparisonsofFBGC3andFBGC4versusrepresentative1T FBCs. The most attractive properties of the first 1T FBC, which is impact ionziationbasedFBC,arethesmallunitcellareaandthecapacitorlesstechnology.Capacitorless processintergraionoffersthepossibilityofembeddedmemorysolutionforsystem-on-chip (SoC) design. The ~4F2 unit cell area implies more memory cells can be crammed on the chip. In order to realize low-power application, GIDL-based FBC is proposed to elminate the write- power. While maintaing the good electrical characteristics of impact ionization-basedFBC,GIDL-basedFBCreducesthewrite-power.But,duetounwanted GIDLcurrentwhichiscausedbytheG-to-DoverlapdesignontheseFBCs,shortretention timeisthemajorissuewiththesetwokindsofFBCs.Besidestheshorttimeretentiontime, r-limited sense margin is also another important issue with these FBCs. By utilizing the parasitic BJT in nMOSFET, BJT-based FBC was proposed to resolve the r-limited sense marginissue.SinceBJT-basedFBCmainlyreliesontheparasiticBJT,G-to-Dunderlapis designed to improve the retention time some. In general, BJT-based resolves the inherent problems with FBCs, but due to its ultra high operation voltage which leads to hot-carrier degradation, the reliability problem becomes very serious. After several thousands of cycling or endurance test, BJT-based FBC will fail to perform the memory functionality. Therefore, in terms of the reliability, BJT-based FBC is not a promising candidate. Based ontheperformancedatainthefirstthreecolumnsinTable5-1,itisveryclearthateachof

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93 them has some disadvantages which restrict these cells from being a good replacement of the conventional DRAM cell. Unlike1TFBCs,asshowninthefourthandfifthcolumnsofTable5-1,FBGC3 and FBGC4 demonstrated superior performances. Since using body of T1 to directly drive thegateofT2,FBGC3andFBGC4demonstratethecomparablesensemarginasBJT-based FBC.But,duetotheflexibilitywhichisgivenby2Tstructure,byoptimizeT1withunderlap at drain side and overlap at souce side, FBGC3 improves the worst-case retention time dramatically without undermining sense margin. Drain-side underlap design in FBGC4 guarantees the worst-case retention time can be as long as ~10s. Besides the remarkable improvement of worst-case retention time, since channel current is used to write-/, SRAM-compariable write speed (~100ps) is achieved in FBGC4. Even though peroidical refresh is needed for FBGC4, ultra-high operation speed makes FBGC4 could be a promisingcandidatetoreplacetheSRAMonthechip.Regardingreliability,sinceFBGC3 and FBGC4 operation voltages are compatible with the current CMOS logic device operationvoltage,thereliabilityofFBGC3andFBGC4couldbethesameasCMOSlogic device. Especally, since FBGC4 relies on the channel current and its maxium operation voltage is not higher than 1V, it could be a hot carrier-free device with careful design and optimization.Finally,wehavetopointoutthattheunitcellareasofFBGC3andFBGC4are larger than 4F2. But, it is worthwhile to make the tradeoff between the electrical performance and the unit cell area. Moreover, if FBGC3 and FBGC4 can be structured vertically,i.e.,withT1sittingonT2,theareaproblemcanberesolved.Insummary,FBGC3 and FBGC4 demonstrate superior electrical performance over 1T FBCs, and the areaperformancetradeoffisworthwhile,inparticularforembeddedapplication.Duetoitslower

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94 voltage bias schemes, superior performance, and design flexibility, FBGC3 and FBGC4 could also be more scalable than 1T FBC. 5.5 Summary We believe FBGC3 has the potential to replace conventional 1T/1C DRAM in conjunction with future nanoscale CMOS technology. Its projected performance, with very long retention time and design exibility for ensuring reliability, make it superior to the 1T FBC counterparts. The long G-D underlap in T1 will improve reliability, while suppressing the GIDL current for retention, yet does not affect the tunneling current for write By optimizing the cell area, FBGC3 could be a good candidate to replace the conventional 1T/1C DRAM cell in stand-alone memory chips. FBGC4isproposedforembeddedDRAMandtobeapotentialreplacementforSRAM cell due to its ultra fast write speed, long retention time, and fully CMOS compatible processing, withonly~1/3oftheSRAMcellarea.WedemonstratedFBGC4usingPD/SOI(partiallydepleted) MOSFETs, for which much technological work has been done to optimize the BTS. We stress though, with regard to FBGC4 scalability, that the MOSFETs in FBGC4 can be FD/SOI (fully depleted) devices as well, including FinFETs, since high BTS resistance is not an issue in the memory operation.

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95 Figure 5-1.TheFBGC3structure,onSOI,inaDRAMarraywithtwobitlines.T1 isdesignedwithgateunderlapatthedrainandgateoverlapatthesource. The body/source of T1 drives the gate of T2. p -n+n+ WL BL1 T2 B1/G2 p -n+p+T1 Overlap (Tunnel Region) Underlap BL2

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96 Figure 5-2.SenTaurus-predictedBTBtunnelingcurrentinT1(Lg=28nm,tox= 2nm,tSi=14nm,tBOX=50nm,G-Dunderlap=30nm,undopedbody, andmidgapgate)versustheG-Soverlaplength;VB=0.0V,VDS=1.0V. TheGIDLcurrent(forVGS<0)iseffectivelysuppressedbythenoted underlap. -1.5-1.0-0.50.00.51.01.5 VGS (V) 10-1810-1710-1610-1510-1410-1310-1210-1110-1010-910-810-710-610-5IDS (A/mm) G-S Overlap = 1nm G-S Overlap = 0nm (abrupt) G-S Overlap = -1nm (underlap)

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97 Figure 5-3.BTBtunnelingcurrentsinT1(Lg=28nm,tox=2nm,tSi=14nm,tbox= 50nm,overlap=1nm,VDS=1.0V)withdifferentG-Dunderlap predicted by Sentaurus. -1.5-1.0-0.50.00.51.01.5 VGS (V) 10-1810-1710-1610-1510-1410-1310-1210-1110-1010-910-810-710-610-5IDS (A/ m m) 10nm 20nm 30nm

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98 Figure 5-4.ID-VDcharacteristicsofT1(Lg=28nm,tox=2nm,tSi=14nm,tbox= 50nm, overlap = 1nm) predicted by Sentaurus. 0.00.51.01.5 VDS (V) 0.00 0.05 0.10 0.15 0.20 0.25I ( m A/ m m) VGS=1.5V VGS=1.2V VGS=1.0V VGS=0.5V

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99 Figure 5-5.ID-VGcharacteristicsofT2(Lg=28nm,tox=2nm,tSi=14nm,BOX= 50nm) predicted by Sentaurus, high VDS = 1.2V, low VDS= 0.2V. -0.50.00.51.0 VGS (V) 0.0 100 200 300 400 500IDS ( m A/ m m) -0.50.00.51.0 10-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-3

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100 Figure 5-6.TransientsequentialmemoryoperationofaFBGC3cell(WL,BL1, BL2,andB1/G2voltages,andtheBL2currentshowingthesignal margin),comprisingFD/SOIUTBMOSFETswithwithLg=28nm,tox=2nm,tSi=14nm,tBOX=50nm,T1overlap=5nm,T1underlap= 30nm, undopedbodies,andmidgapgates,aspredictedvia2-D simulationwithSenTaurus.NotethatVBL2isfixedat0.2V,which causestheBL2currentduringwrite;thiscurrentwouldbe eliminatedviaBL2pulsinginactualmemoryoperation,thereby yielding very low overall dynamic power 0.020406080 Time (ns) -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4Voltage (V) 0.020406080 Time (ns) -40.0 0.0 40 80 120 160 200 240 280 320 360 400BL2 Current ( m A/ m m) BL1 WL B1/G2Write HoldRead Hold Write HoldRead Write HoldRead Hold Write HoldRead BL2 Signal Margin @ 70 m A/ m m

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101 Figure 5-7.Worst-casecharge/dataretentioncharacteristicsoftheFBGC3ofFig.3, asreectedbythepredictedreadB1/G2voltagewhileholdingand withcontinuousBL1disturbsasindicated.Thebiasvoltagesforthe memory operation are the same as those in Fig. 5-6. 10-610-510-410-310-210-1100Time (s) -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5VB1/G2 (V) hold with BL1 = -0.8V disturb hold with BL1 = +1.2V disturb 10

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102 Figure 5-8.TransientsequentialmemoryoperationoftheFBGC3withBL1and BL2 tie together. 0.020406080 Time (ns) -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4Voltage (V) 0.020406080 Time (ns) -400 -300 -200 -100 0.0 100 200 300 400 500Current (m A/ m m) Write HoldRead Hold Write HoldRead Write HoldRead Hold Write HoldRead Signal Margin@ 25 m A/ m m BL1&2 WL B1/G2

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103 Figure 5-9.TransientsequentialmemoryoperationoftheFBGC3withoptimal pulses. 0.020406080 Time (ns) -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4Voltage (V) 0.020406080 Time (ns) -40 0.0 40 80 120 160 200 240 280Current ( m A/ m m) Write HoldRead Hold Write HoldRead BL1 WL B1/G2Write HoldRead Hold Write HoldRead Signal Margin @ 81 m A/ m m

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104 Figure 5-10.TransientsequentialmemoryoperationoftheFBGC3withnospacerof T1. 0.020406080 Time (ns) -40 0.0 40 80 120 160 200 240 280Current (V) Write HoldRead Hold Write HoldRead Write HoldRead Hold Write HoldRead BL1 WL B1/G2 Signal Margin @ 80 m A/ m m 0.020406080 Time (ns) -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4Voltage (V)

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105 Figure 5-11.DataretentioncharacteristicsofFBGC3inFig.5-10.Theoperation voltages for write and read are the same as in Fig. 5-10. 10-610-510-410-310-210-1100101Time (s) -0.8 -0.6 -0.4 -0.2 0.0 0.2 VB1/G2 (V) '0'state with BL1=-0.3V disturb '1'state with BL1=0.9V disturb

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106 Figure 5-12.Sentaurus-PredictedA)sensemargin,B)draincurrentofT2inread- andhold-andC)themaximnumberofcellsinthesameBL2asthe functionofgatework-functionofT2.TheWLandBLpulsesand simulationdomainarethesameastheplusesandsimulationdomainin Fig. 5-6. 4.24.34.4 4.54.6 4.7 50 100 150 200 250 300 350 400Sense Margin (ID of T2) ( m A/ m m) 4.24.34.4 4.54.6 4.7 10 -16 10 -15 10 -14 10 -13 10 -12 10 -11 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5ID of T2 (A/ m m) Iread-'0' Ihold-'1' 4.24.34.4 4.54.6 4.7Gate Work-Function of T2 (V) 10 1 10 2 10 3 10 4 10 5 10 6 10 7Number of Cells in BL2 (=Iread-'0'/Ihold-'1')A B C

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107 Figure 5-13.TheFBGC4structureinaDRAMarraywithtwobitlines,includinga topviewofT1.Asindicated,T1isaBTS/SOIMOSFETwithitsbody tiedtoitssource.Also,T1isdesignedwithgate-source/drainunderlap tosuppressGIDLforhold-.Thebody/sourceofT1drivesthegateof T2forreadingdatawithoutsignicantlyaffectingthestoredchargein T1. p -n+n+ WL BL1 T2 B1/S1/G2 p -n+n+/p+T1 Underlap BL2 n+n+p+ B1/S1/G2

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108 Figure 5-14.TransientsequentialmemoryoperationofaFBGC4cell(WL,BL1,and B1/G2voltages,andtheBL2currentshowingthesignalmargin), comprising90nmPD/SOInMOSFETs(Lg=90nm,tox=2nm,tSi= 120nm,n+polygates;Vt@ 0.4V)as predictedbyUFPDB/Spice3 device/circuitsimulation;theBL2biasisfixedat0.2V.Notethat thefixedVBL2causestheBL2currentduringwrite;thiscurrent wouldbeeliminatedviaBL2pulsinginactualmemoryoperation, thereby yielding very low overall dynamic power. 0 0.250.50.75 1Time (ns) -40 -20 0 20 40 60 80 100 120 140 160 180 200T2 Current ( m A/ m m) 0 0.250.50.75 1Time (ns) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1Voltage (V) Write HoldRead Hold Write HoldRead Signal Margin @ 30 m A/ m m BL1 WL B1/G2Write HoldRead Hold Write HoldRead

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109 Table 5-1. Performance comparison among FBGC3, FBGC4 and 1T FBCs. II-based FBC GIDL-based FBC BJT-based FBCFBGC3FBGC4 Sense Margin~50 m A~30 m A~50 m A~80 m A~30 m A Retention Time~10ms~100 m s~800ms~10s~10s Write Time~10ns~10ns<2ns~10ns~100ps Cell Area4F24F24F2~8F2~10F2Reliabilitylike CMOSlike CMOS VeryBad(hot carrier)like CMOSlike CMOS

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110 CHAPTER 6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK 6.1 Summary This dissertation addressed physical insights and design considerations of the floating-body DRAM cell. The floating-body/gate cell (FBGC) was proposed and demonstrated with superior electrical performance over other FBCs. The major contributions of the research are summarized as follows. In Chapter 1, the floating body effect in FD/SOI and PD/SOI MOSFETs were carefullystudied.Supportedbynumericalsimulationsandanalyticalmodeling,wegained physicalinsightsandgenericallyexplainedtheoperationofFBCDRAM,comprisingaPD/ SOI or FD/SOI MOSFET, or an FD DG or IG FinFET. The notion of a potential well for chargestorageinthebodywasdismissed,and,forthefirsttime,thepredominantintrinsic, dynamiccapacitors(bias-dependentCB)thatstorethebodycharge,ordata,forthevarious devicesandbiasconditionsweredefined.ForFDcells,multiplerolesoftheVGbS-induced accumulationlayerneededforstoringandsensingdatawerephysicallydefinedforthefirst time; it renders a significant D Vt dependent on D VBS, and, in the FD/SOI cell with thick BOX, it creates a significant B-S junction capacitance for the charge storage. For the IGFinFET cell, the created junction capacitance is augmented by the B-Gb capacitance. For GIDLcharging,ratherthanbyimpactionization,CBisaugmentedbytheB-Gfcapacitance. Thenewinsightsnotedhereinimplybetterdesignsforoptimallytrading-offtheFBCsignal margin, data retention time, write speeds, and power. In Chapter 2, a novel 2T floating-body cell on SOI for embedded DRAM was presented, and its operation was demonstrated and verified via process/physics-based device/circuitsimulations,supportedbynumericalsimulations.Themainnoveltyistheuse

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111 ofthefloatingbodyofonetransistor(T1)todirectlydrivethegateofthesecondtransistor (T2),therebygivingdramaticimprovementinsignalmarginwhileallowingvoltage-based sensing.Physicalinsightthenledtoamodificationofthebasic2T-FBCstructure,enabled by using GIDL current for T1-body charging, in which the source and drain of T1 are shorted,andbothtiedtotheprogrammingbitline.ThisistheVer.1floating-body/gatecell (FBGC1). FBGC1 totally eliminates the write (T1 charging and discharging)-power dissipation, while yielding better signal margin, longer data retention via voltage-based sensing, and higher memory density. The simulation-based demonstration of the FBGC1 used undoped nanoscale DG FinFETs, or ITFETs, which are potentially scalable to Lg < 10nm. We therefore believe that FBGC1issimilarlyscalable,andmuchmoresothana1Tcounterpartforwhichthe gate-source/ drain overlap (Leff < Lg) needed for GIDL current will limit its scalability. Because ofthe designexibilityaffordedbythe2TFBC,theGIDLcurrentcanbecontrolledviaoptimaldesign oftheG-S/DoverlapinT1,whichismerelyatwo-terminalcharge-storagestructure,withT2being designedoptimallywithunderlapasdiscussedherein.WenotethatscalingLgwilltendtoreduce theeffectivestoragecapacitanceofthe2Tcell,i.e.,theoxideandgatecapacitancesofT1andT2 (although the n height could be kept high to offset this reduction without undermining the increased memory density). Thus, fewer holes will be stored, although the signal margin will not be undermined. However, the scaling of the n thickness with Lg will reduce the S/D-junction recombination current, implying that the data retention time will not be signicantly affected. Hence, we believe that FBGC1 can be scaled along with the FinFET-CMOS technology. This optimistic projection cannot be made for 1T-FBCs, even if a DG FinFET is used. InChapter3,wedemonstratedasimplified,superiorVer.2oftheFBGC,called FBGC2, by numerical simulation and fabrication/measurement. FBGC2 offers very high

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112 signal margin and ultra-low power dissipation. Retention times are anticipated to be comparableto,orlongerthan,thoseof1TFBCs.Theeasedfabricationprocessofthenew FBGC makes it compatible with planar or quasi-planar CMOS technology, with high effectivedensity.ItcanthusenablemanufactureofembeddedDRAMinthenearfuture,at low cost and with superior performance. In Chapter 4, we examined the hole redistribution in the nanoseconds transient operations and its impact on the GIDL current. Based on better understanding of the transient GIDL current, we gained physical insights to optimize the applied biases and device structure. The electrical performance of the "P+ source" FBGC is heavily based on the performance of the T1, which is a three-terminal gated-diode. However, due to lack of body voltage dependence modeling, numerical simulation tools cannot predict the BTB tunneling current reliably in the long retention time simulation. To resolve this issue, we derivedtheexpressionsfortheGIDLcurrentindepletionandaccumulationcaseswhichare determined by body bias. We found that the GIDL current increases with decreasing body voltage.Withmorenegativebodyvoltagewhichmakeschanneldepleted,theGIDLcurrent saturates. Our derivation of the GIDL current which is supported by preliminary experimental data, implies that it is impossible to reduce the unwanted GIDL current in holding-statebytuningVB.Therefore,innovationsareneededtoimprovethe-state retention time in FBGC design. In Chapter 5, to resolve the short worst-case retention time issue associated with the FBGC2,wereneditandproposedVer.3FBGC.ThekeydifferencebetweenFBGC2andFBGC3 isthechargingmethod.InFBGC3,write-isperformedbyinvertingthechannelandintroducing BTB tunneling current at source side. Therefore, the conict between write- and hold- is resolved. Its projected performance, with ultra-long retention time and design exibility for

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113 ensuringreliability,makeitsuperiortothe1TFBCcounterparts.ThelongG-DunderlapinT1will improve reliability, while suppressing the GIDL current for retention, yet does not affect the tunnelingcurrentforwrite.FBGC3hasthepotentialtoreplaceconventional1T/1CDRAMin conjunction with future nanoscale CMOS technology. Since FBGC2 and FBGC3 rely on BTB tunneling current for body charging, which is relative small, the write time is several nanoseconds. To make FBGC operate at faster speed, including write and write Ver. 4 (FBGC4) was proposed. Due to its ultra-fast write speed, FBGC4 could be a potential replacement for the SRAM cell. In FBGC4, T1 is reverted to a conventional MOSFET. The key feature is the source side design:n+andp+regionsareusedtotiethebodytothesourceofT1.Thechannelcurrent canthenbeutilizedtocharge/dischargethecell.Duringtheholdingstate,theexcessholes canbetransferredfromthegateofT2viathebody-to-sourceconnection,andarestoredon thegateofT1.Thisconfigurationcanresolvetheread-disturbissue.Wehavedemonstrated FBGC4 using PD/SOI MOSFETs, for which much technological work has been done to optimize the bodyt-source (BTS) tie. With regard to FBGC4 scalability, we note that the MOSFETs in FBGC4 can be FD/SOI devices as well, including FinFETs, since high BTS resistance is not an issue in the memory operation. 6.2 Suggestions for Future Work InChapter5,FBGC3andFBGC4werestudiedbasedonnumericalsimulations. ExperimentaldemonstrationofthesenovelDRAMcellwillbenecessarytofurthervalidate the viability. With regard to FBGC3, the demonstration of the ultra-long retention time should be the most urgent task. Our experimental work on FBGC2 shows that write- is not a problem. We need to verify the function of the underlap to reduce the GIDL current. Further, the junction and surface recombination characteristics should be minimized

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114 throughprocessing;e.g.,usingnon-silicideprocessingtogetagoodqualitybody-to-drain junction. Endurance or cycling test with FBGC3 and FBGC4 must be done to assess the reliability characteristics. Further, a good sense amplifier circuit design that utilizes the feature of quasi-nondestructive readout to effectively reduce the refresh-busy rate, and therefore can realize a low-power DRAM chip, is called for. And last, but not least, is the issue of process-induced variations of the underlap and overlap lengths of T1, as well as threshold-voltage fluctuation which can severely impact the sense margin and therefore cause failure in read. The sources of the process-induced variations must be thoroughly examined so that we can guarantee good yield and memory performance. Experimental prototyping of FBGC4 and FBGC3 is being done at Grace Semiconductor in Shanghai, China, in these regards.

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117 [29]J.G.F ossum,L.-Q.Wang,J.-W.Yang,S.-H.Kim,andV.P.Trivedi,"Pragmatic DesignofNanoscaleMulti-GateCMOS," IEDMTech.Dig. ,pp.613-616,Dec 2004. [30]I.Ban,etal.,"A ScaledFloatingBodyCell(FBC)MemoryWithHigh-K+Metal GateonThin-SiliconandThin-BOXfor16nmTechnologyNodeandBeyond," Symp. VLSI Tech. Dig. pp. 92-93, June 2008. [31]U.E.Avci,etal,"FloatingBodyCell(FBC)Memoryfor16-nmTechnology withLowVariationonThinSiliconand10nmBOX," Proc.IEEEInternat. SOI Conf. pp. 29-30, Oct. 2008. [32]J.G. Fossum,Z.LuandV.P.Trivedi,"Newinsightson"capacitorless" floating-bodyDRAMcell," IEEEElectronDeviceLett. ,vol.28,pp.513-516, June. 2007. [33]M. Blagojevic,etal.,"Capacitorless1TDRAMsensingschemewithautomatic referencegeneration et," IEEEJournalofSolid-StateCircuits. ,vol.41,pp. 1463-1470, June. 2006. [34]J.G. Fossum,etal.,"Two-transistorfloating-bodydynamicmemorycell," U.S.ProvisionalPatentApplicationNo.60/976,691,Oct.1,2007;Internat. Patent Application No. PCT/US2008/078460, Oct. 1, 2008. [35]Z.Lu,etal.,"ANovelTwo-TransisitorFloating-Body/GateCellforLowPowerNanoscaleEmbeddedMemory," IEEETrans.ElectronDevices ,vol. 55, pp. 1511-1518, June 2008. [36]Z.Lu,etal.,"ASimplified,SuperiorFloating-Body/GateCell," IEEE Electron Device Lett. Vol. 30, pp. 282-284 Mar. 2009. [37]S.KrishnanandJ.G.Fossum,"GraspingSOIFloating-BodyEffects" IEEE Circuits and Devices Magazine vol. 14, pp. 32-37, July 1998. [38]Y. TaurandT.H.Ning, FundamentalsofModernVLSIDevices .Cambridge,U.K.: Cambridge Univ. Press, 1998. [39]H.-K.LimandJ.G.Fossum.,"ThresholdVoltageofThin-FilmSilicon-onInsulator(SOI)MOSFETs,," IEEETrans.ElectronDevices .,vol.30,pp. 1244-1251, Oct 1983. [40] Taurus-2006 User s Manual Durham, NC: Synopsis, Inc., 2006. [41]S.-H.Kim,etal.,"Modelingandsignificanceoffringecapacitancein nonclassicalCMOSdeviceswithgate-source/drainunderlap,," IEEETrans. Electron Devices ., vol. 53, pp. 2143-2150, Sept 2006. [42]S.Okhonin,etal.,"NewGenerationofZ-RAM," IEDMTech.Dig. ,pp.925928, Dec 2007. [43]S.K.Moore.,"MastersofMemory," IEEESpectrum. ,Vol.44,pp.45-49,Jan 2007.

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119 [59]T. Krishnamohan,etal.,"Double-gatestrained-GeheterostructuretunnelingFET (TFET)withrecordhighdrivecurrentsand<60mv/decsubthresholdslope," IEDM Tech. Dig. pp. 947-949, Dec 2008. [60] Sentaurus-2007 User s Manual Mountain, CA: Synopsis, Inc., 2007. [61]T .-S.Jang,etal.,"HighlyscalableZ-RAMwithremarkablylongdataretentionfor DRAM application," Symp. VLSI Tech. Dig. pp. 234-235, June 2009 [62]J.S.Kim,etal.,"VerticalDoubleGateZ-RAMTechnologywithRemarkable LowVoltageOperationforDRAMApplications," Symp.VLSITech.Dig. ,pp. 163-164, June 2010. [63]D. Somasekhar,etal.,"2GHz2Mb2Tgain-cellmemorymacrowith128GB/s bandwidthina65nmlogicprocess," InternationalSolidStateCircuit Conference. Dig. pp. 274-276, Dec 2008. [64]W. Luk,etal.,"A3-transistorDRAMcellwithgated-diodeforenhancedspeedand retention time," Symp. VLSI Circuits. Dig. pp. 184-185, June 2006. [65]J.G.Fossum, UFPDBUsersGuide(Ver.2.5) .Gainesville,FL:Univ. Florida, 2002. [66]J.G. Fossum,etal., "Floating-body/gateDRAMcell," U.S.ProvisionalPatent Application No. 61/144,289, Jan. 13, 2009

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120 BIOGRAPHICAL SKETCH ZhichaoLuwasborninHubei,China.HereceivedtheBachelorofEnigneering. degreeinelectricalengineeringfromTianjinUniversity,Tianjin,China,in2002,Masterof SciencedegreeinelectricalengineeringfromtheTsinghuaUniversity,Beijing,China,in 2005,andDoctorofPhilosophydegreefromtheUniversityofFlorida,Gainesville,FL,in 2010.FromJanuary2010toNovember2010,hewasaninternat Inter-universityMicroElectronicsCenter(IMEC), Leuven,Belgium,workingonnanoscalefloating-bodymemory cells(FBC)design.Hisresearchinterestsinvolvenanoscalecomplementarymetal-oxidesemiconductor(CMOS)devicedesignandanalysis,floatingbodymemorycellsdesignand analysis,andmodelingofnonclassicalnanoscaleCMOSdevices,andtheapplicationsin device/circuit design optimization.