Citation
Signal Processing Techniques and Dsp Hardware Structures for Dynamic Estimation and Compensation of Absolute and Relative Gain/phase Variations in Mobile Devices

Material Information

Title:
Signal Processing Techniques and Dsp Hardware Structures for Dynamic Estimation and Compensation of Absolute and Relative Gain/phase Variations in Mobile Devices
Creator:
Premakanthan, Pravinkumar
Place of Publication:
[Gainesville, Fla.]
Publisher:
University of Florida
Publication Date:
Language:
english
Physical Description:
1 online resource (197 p.)

Thesis/Dissertation Information

Degree:
Doctorate ( Ph.D.)
Degree Grantor:
University of Florida
Degree Disciplines:
Electrical and Computer Engineering
Committee Chair:
Harris, John G.
Committee Members:
McNair, Janise Y.
Taylor, Fred J.
Crisalle, Oscar D.
Graduation Date:
8/7/2010

Subjects

Subjects / Keywords:
Amplifiers ( jstor )
Calibration ( jstor )
Control loops ( jstor )
Error signals ( jstor )
Estimate reliability ( jstor )
Mobile devices ( jstor )
Propagation delay ( jstor )
Signal detection ( jstor )
Signals ( jstor )
Simulations ( jstor )
Electrical and Computer Engineering -- Dissertations, Academic -- UF
adaptive, gaincontrol, gaintracking, phaseestimation, rf, signalprocessing, transmitter
Genre:
Electronic Thesis or Dissertation
bibliography ( marcgt )
theses ( marcgt )
Electrical and Computer Engineering thesis, Ph.D.

Notes

Abstract:
We introduce system architectures and algorithms with related DSP hardware structures to dynamically estimate and compensate for relative/absolute gain variations in any analog or digital signal processing paths. In addition, the presented techniques are used to calibrate and compensate for relative signal phase shifts occurring in a mobile device. The techniques described in this thesis are implemented in a mobile device to dynamically estimate and compensate for absolute and relative signal power variations from the desired power levels. These techniques help to prolong battery life of the mobile device and to reduce signal-to-interference ratio (SIR) at the base-station. In addition the described system algorithms are implemented using efficient digital circuitry which eliminates the bulky analog components which were originally used for this purpose. The digital circuit implementation makes the mobile device less susceptible to variations in temperature, frequency of operation and manufacturing processes. The digital area of the implemented digital circuitry is found to be around 22K gates and the digital current drain is approximately 20mA. System lab measurements show that the mobile system is able to compensate better than 0.1dB absolute and relative power level accuracy and also result in phase estimation accuracy better than 1 degree. ( en )
General Note:
In the series University of Florida Digital Collections.
General Note:
Includes vita.
Bibliography:
Includes bibliographical references.
Source of Description:
Description based on online resource; title from PDF title page.
Source of Description:
This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Thesis:
Thesis (Ph.D.)--University of Florida, 2010.
Local:
Adviser: Harris, John G.
Statement of Responsibility:
by Pravinkumar Premakanthan.

Record Information

Source Institution:
University of Florida
Holding Location:
University of Florida
Rights Management:
Copyright Pravinkumar Premakanthan. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Embargo Date:
10/9/2010
Resource Identifier:
004979615 ( ALEPH )
769016416 ( OCLC )
Classification:
LD1780 2010 ( lcc )

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Full Text





Figure 1-3 shows ideal power control without any gain errors introduced during the

gain control process. However, it is very difficult to achieve such precise control

practically due to imperfections of the analog and RF circuit as a function of operating

conditions. The performance of analog and RF circuits with respect to operating

temperatures, frequency bands of operation, battery voltage causes gain and phase

errors which degrade gain control accuracy. This is discussed in detail in Chapter 2. As

shown in Figure 1-4, in present day cellular standards, the power tolerance allowance

for gain variations is around +/-3dB. For advanced protocols such as LTE (Long Term

Evolution) and 2G Evolution, the margin for gain variations is less than 0.2dB to support

different mobile standards to co-exist. These stringent power accuracy requirements

demand for precise and efficient dynamic digital gain correction techniques to yield gain

corrections better than 0.2 dB accuracy.

Another issue in present day circuits is that the gain correction is performed

instantaneously and hence leads to spectral leakage into [7],[39] bands. This in turn

causes reduction of system capacity. Figure 1-5 and Figure 1-6 shows the transmit

spectrum measured at the output of the mobile device operating at 2.5GHz band. The

communication testing equipment used to capture this measurement is Agilent N9020A

MXA signal analyzer [82]. As shown in Figure 1-5, an uncontrolled instantaneous rapid

gain change performed in the mobile device leads to spectral leakage and causes

interference to the adjacent user[1]. This degrades the SNR of the adjacent user and

hence reduces system capacity. The gain change or gain compensation applied to the

analog or the digital stages of the mobile device must be controlled in a spectrum-

friendly profile to reduce out of band spectral emissions as shown in Figure 1-6. These












Sr a
U


U


Closed loop system
adapting to multiple
power hng quest


Closed loop system
adapting to power
ramp down request


2nd power change


1st power change


M 100ps A f 28.OmV

0 33.60 %


Function Tie
Units
S Seconds


Figure 4-28. Analog closed-loop response for multiple steps with the adaptive filter
captured by Tektronix oscilloscope


IGSM180 *.we M-4;


I h |. iiI I I I I


". '.
~III~ l~r II_


rl 1 -, .i.


0 -.


Gelietalot Power Moloulallon SI|eclrlllll


Figure 4-29. Transmit power of the mobile device captured by CMU 2000.


184


Stop


Cursor
Function


Off




H Bars


Vt
V Bars





ol h

Sr n


( I-cld hImp .id.ipi- r,,







T i .i I I.
I. T II, r, i p -
lr l i ll n l~l ri' n it j_______________ T


..... . . .


C(h. 2
















0.5

a 0

E
- -0.5

-1


1

0.5
a
a 0

E
- -0.5

-1


Stability Analysis of H(z) for loop delay D = 39,45,52,58 samples at Fs



.X : 0.5
at
:X :x
aX X


-t E-
-05 --o.5 0I

'X .x ,,


1 -0.5 0 0.5 1
Real Part







. .. .. ,, '... .
4C
SI



\Jj


1

C: 0.5

a o
0)
E
- -0.5

-1


-1 -0.5 0 0.5 1
Real Part










K I) ....e. .f


-1 -0.5 0 0.5 1 -1 -0.5 0 0.5 1
Real Part Real Part


Figure 4-17. Pole-zero location with loop delay, D = 39, 45, 52 and 58 samples at
sample rate Fs.


effect of additional loop delay on convergence time and peak overshoot


specs


E0.5
a
S)

B 0.4
a
oC
S0.3


0.2


40usec


time in sec x 10"


Figure 4-18. Closed-loop step response with respect to varying plant delays.


176


x
x
x

x
, ,,,-,( ,,,,,


Ky


I









3-11 DSP Hardware structure to estimate the absolute gain change...................... 131

3-12 DSP Hardware structure to estimate the absolute gain and phase change...... 132

3-13 Simulation plots to show that RxBB(t) with frequency of 400 KHz and
OiF = 300KHz over the 8 RF gain settings ..................................................... 132

3-14 Simulation of FFT magnitude of RxBB(t) with cIF = 300KHz over the 8 RF
gain settings .............. ...... .............. ........... ........... 133

3-15 Simulated DFT magnitude of I and Q channel for K = 13, 14, 15, 16, 17 ........133

3-16 Ideal gain change AG,,, estimated gain change AG(dB) and DNLE(dB)
I AGre AG ........................................ ................ ... .. ................ 134

3-17 Ideal phase change AAr estimated phase change AA (deg) and
S err = A A A I ..................................................................... .... ..... .. 13 4

3-18 Averaged INLE error measured on three RFIC after the gain error
com sensation. .................................. ...................................... ......... 135

3-19 Absolute phase variation in the mobile device after phase compensation ........ 135

3-20 Relative phase variation in the mobile device after compensation .................... 136

3-21 Measured plots to show the 90 degrees phase compensation performed by
the D S P hard are ................. ..................................... ..... ................. 137

4-1 Power control A) Measured transmit power to show the PAR and PTN of a
LTE signal captured by Rhode and Schwartz CMU 2000 B)System
architecture of the DSP-GC algorithm implemented in a mobile device............ 167

4-2 DSP hardware implementation of the adaptive filter and 1st order integrator.... 169

4-3 System constraints in selecting the controller gains. ................................. .... 170

4-4 Sim plified closed-loop m odel ......................................................................... 170

4-5 Open loop based tuning technique................ .............................. 170

4-6 Closed-loop based tuning technique ....... ..................... ............. 171

4-7 Closed-loop system with an integral controller.............................. 171

4-8 Discrete model of closed-loop system at steady state..................................... 171

4-9 Flow chart to estimate integral gain...... ......................... 172









reduces. This means that the step response of the average has a slower response time

at lower filter factors.

An alternate strategy that can be adopted is by having a two stage filter structure

with timer enables. The first filter is enabled at time t1 with a filter factor, a and after the

filter settles, a second filter is enabled at time t2 (t > t) with a filter factor b. This

cascade architecture will also help in meeting the response time and noise trade-offs.

Once the first filter settles, the second filter will be enabled to reduce the variance at the

first filters output. The block diagram is illustrated in Figure 2-28.

The input-output equation of the second filter is represented as

y2(n)= by(n)+(1-b)y(n- 1) (2-18)

Applying z transform, the transfer function of the cascade is represented by

Y (Z) a*b (2-19)
X(z) [1-(1-a)z ][1-(1-b)z 1]

Equation 2-19 shows that the filter output is a function of the two filter factors a and b.

This structure helps in better average estimate if the input signal has relatively higher

variances. The output of the second average is shown in Figure 2-29.

2.5.5 Digital PID controller

The hardware implementation of the PID controller is shown in Figure 2-30. This

circuit is used to integrate the error signal between the reference path and the feedback

signal path and the controller output is used to adjust the digital or the analog gain stage

of the transmit path. Ife(n) is the input to the controller and Kp,KI and KD are the

proportional, integral and derivative gain, then the output of the controller, p(n) is

represented as









Figure 2-44 shows the response of the closed-loop system which tries to

compensate for the positive 6dB gain variation injected into the system. The error signal

between the reference path and the feedback signal magnitude is calculated and the

controller is updated based on the buffer rate selected. The rate of change of the error

signal, the peak overshoot and the steady state error is decided by the selected integral,

derivative and proportional gains. This controller output is either digitally applied to the

forward path signal or converted to an analog equivalent signal and applied as gain

control on to the RF amplifier stages as bias control.Figure 2-45 shows the response of

the closed-loop system for a single gain step as a function of integral gains. The

philosophy adopted in the described DSP-DGT algorithm is to fix the derivative and the

proportional gains and vary the integral gains as a function of variance of the error

signal, the desired settling time and desired steady state error. Figure 2-46 shows the

convergence of the closed-loop system to track out a positive 6dB gain variation

injected into the system. As the closed-loop system is enabled, the averaged value of

the error signal between the reference path and the feedback path is inputted into the

controller. As shown in earlier equations at steady state the controller output provides a

compensation signal in response to the sign of the error signal. In this simulation, a 6dB

gain variation is added onto the feedback path and hence this provides a negative error

signal. The negative error signal input into the controller make the controller output

provide a compensation signal which tries to bring the error back to zero at steady state.

The controller update is shown in Figure 2-44 brings back the signal power to the

desired level as shown in Figure 2-46.









LIST OF FIGURES


Figure page

1-1 Power control signaling from base-station to mobile device .............................. 28

1-2 Occupancy of mobile users in frequency domain without power control............28

1-3 Ideal gain control with no error in correction after power control.....................29

1-4 Gain errors introduced due to analog/RF circuit imperfections as a function
of operating conditions ........ .......... ................ ...... .................. 29

1-5 Measured adjacent channel interference due to abrupt power control without
signal shaping captured by Agilent N9020A MXA signal analyzer..................... 30

1-6 Lower spectral leakage due to power control with signal shaping captured by
Agilent N9020A M XA signal analyzer........................................ ...................... 30

1-7 System level overview of a m obile device................................. ...................... 31

1-8 Reduction of signal power from the mobile device captured by Rhode and
Schwartz CMU 2000 analyzer ..................................... ................ 32

1-9 Multiple power changes of the mobile device captured by Rhode and
Schwartz CMU 2000 analyzer ..................................... ................ 32

1-10 Prior art that uses fixed digital gain offsets and errors to perform digital gain
c o n tro l ...................... .. .. ......... .. .. ............................................... 3 3

1-11 Prior art that adopts pre-calibrated analog bias levels for gain control and
tra c k in g ...................... .. .. ......... .. .. .............................................. 3 3

1-12 Prior art that adopts RF feedback and coarse analog bias adjust .................. 34

1-13 Prior art that uses RF feedback and temperature compensation circuit for
b ia s a dju s t............. ......... .. .. ......... .. .. .......... .................................. 3 4

2-1 Primary sections of a mobile device transmitter ................ ............. ................ 63

2-2 Absolute RF Power variation in dB due to temperature variations averaged
over three parts ................ ............. .. ............................ ................. 63

2-3 Pout variations across frequency bands over temperature...............................64

2-4 Absolute RF power variations in dB due to frequency of operation ........ ........ 64

2-5 Pout variations across frequency bands over supply voltage ........................... 65













ideal and obtained signal magnitude


1.2

1

D 0.8
tnl
E






100 200 300 400 500 600
-o sample number
a0
8 0.8







5. mean(20*log1 O(estimated mag/ideal magnitt
m -- mean
S0.06 -e- desire
> 0.04- -e- desire

E 0.02 -




S-0.06


W 100 200 300 400 500 600
E sample number


I

Figure 2-22. Ideal and obtained signal magnitude


0.2


0.18


0.16


S0.14


. 0.12


* 0.1


0.08


700 800 900 1000


Magnitude estimate error in dB as a function of buffer hardware lengths


0 50 100 150 200 250
estimator buffer length


Figure 2-23. Magnitude error in dB as a function of buffer hardware length















0O 0
/
'~'


0 0 0 0 '%
0 ,
0


0 0



0-




00 0

0 0 0 0 0 0


-1 -0.5 0 0.5 1
Real Part
Figure 4-11. Plot of poles of the transfer function with K, = KI max


.0
a
M -I I I------------
S0.2
S0. R(t) and A(t)




0.1
) 200 400 600 800 1000 1200 1400
samples as Fs



I e(t)
22 0.1
a 0.05
-Jo~
o.5 100l 200. ... 300 100 400 500 600i... .i.. ...


Figure 4-12.


Sc~lllapeo as I


E 0.4-


a .2 ... .. .. y(.. t) .....
0


S100 200 300 400 500 600 700 800 900 1000
samples as Fs
Closed-loop system simulations with appropriate integral gains


173


100 200 300


400 500 600
I r F


1000









where, AG and AA is the estimated gain and the phase shift. Hence the estimated

gain change is calculated as the absolute value of the ratios of consecutive DFT

measurements. On observing Equation 3-26, it is clear that the result is a function of 0

and 0. The angle 0 is a random phase angle between transmit and receive VCO's. The

angle 0 is the phase angle of the injected baseband calibration signal. Based on

measurements it is found that transmit and the receive VCO's have only a frequency

error of less than 2Hz and hence does not degrade the accuracy of this algorithm. In

order to make this algorithm less susceptible to frequency and additional phase errors,

the frequency of the calibration signal is selected in such a way that there is no phase

imbalance introduced between both the quadrature paths I and Q from one iteration to

the next. Based on the above mentioned criteria the assumption of 0 and 0 being

constant is valid.

The DSP-GPE algorithm is used to estimate the relative gain and phase shifts

dynamically. The estimated gain and phase shifts are then used to correct for relative

DNL errors and phase shifts. Depending on the application, the DSP-GPE algorithm can

be used as a calibration sequence before the signal transmission. The estimated values

are be stored in ROM lookup tables and applied as correction factors during normal

transmit operations.

3.5.3 Gain and Phase Compensation Implementation and Equations

Assume that AGe and AAe are the ideal gain and phase changes between two

consecutive gain steps of the VGA according to circuit design. Let AG, AA be the actual

estimated gain and phase changes between the same consecutive steps. The DNLE is

then calculated as


113









4.3 Loop Tuning Techniques

The three primary system constraints that requires attention while designing

closed-loop system are convergence time, loop stability and gain margin. As shown in

Figure 4-3, the critical loop system parameters which influence the above mentioned

constraints are

* Feedback loop delay
* Integral gains
* Feedback gains
* Amplitude of the reference signal (depends on the power levels at the antenna).
* Operating regions of the power detector curve. (feedback path linearity).
The system specifications for which this algorithm is used are as described below.

* Peak overshoot specification of less than 3dB.
* Loop settling time of less than 40usec.
* Rise time of closed-loop response is less than 10usec.

The goal of this control loop is to reduce the average of the error signal between

the reference signal and the feedback signal. Hence an integral controller with

programmable gains is chosen for this application. However this algorithm has also

been studied with proportional, integral and derivative controllers. Sections 4.3.1 and

4.3.2 describe briefly about the classical open loop and closed-loop techniques that help

in determining the appropriate controller gains that will guarantee system stability.

4.3.1 Method I Reference Model Based Loop Tuning

This method of loop tuning is used when the open loop plant transfer function G(s)

and the closed-loop reference transfer function H(s) is known. Based on the knowledge

of H(s) and G(s) the controller transfer function Ge(s) can be estimated as described

below. Assume a system as shown in Figure 4-4. Let the input to the system is R(s),

Y(s) is the system output, G,(s) is the controller transfer function and G (s) is the


150









between the reference signal and the feedback signal goes into the controller G,(z). The

output of the controller drives the unknown plant Gp(z). The unknown plant in the

system under consideration consists of the gain amplifier and the analog components in

the transmit path of the mobile. When the closed-loop power control occurs these

components are already enabled and the transient behavior can be neglected. Thus,

considering the steady state behavior of the unknown plant, we can model this as a gain

stage. The feedback path which consists of the power detector, the digitizer, the analog

filter can be modeled as a gain stage /pand a delayD. Hence the feedback path can be

represented as ,z.

4.4.1 Effect of Loop Delay

Analysis of the loop stability with increasing loop delay is essential to decide the

operating sampling frequency of the ADC, the digital components and the appropriate

bandwidths of the analog filters in the feedback path. Assume an integral controller is

used for the sake of analysis. Hence, the transfer function of the integral controller can

be represented as

Z
G,(z) = K -- where K1 is the integral gain.
1-z

The closed-loop system equations with the integral controller can be described as

follows.

Y E(z)Kz GP
Y(z)
1-z1

E(z) = R(z) A(z) (4-24a)

A(z)= Y(z)z -D


158












avg_enable


controller clks


_______________________________________ + _


Forward path magnitude




PY(t) Undesired gain change due to PA/VGA/
baseband
Feedback path signal magnitude


Controller error signal
E(t)









Controller output
Y(t)


Error signal into the controller


Controller corrections
Until the error reaches zer


0


The PA output reaches
back to desired level


ignal reaches back to zero
\


Controller output reaches
To desired level until error becomes zero


Figure 2-10. Closed-loop dynamics when the controller compensates for an undesired negative gain change


LJLR-LIFLLL-L-












Gain correction by employing the proposed algorithm


0.26


E
a 0.18

an


time x 10

Figure 2-46. Simulation of the closed-loop circuitry adaptation until error signal
becomes zero.


S .1 __,( uflh I ulici ( 'U,,Ii ,lI
_ ., .11,, u m







N. -I nI
I




5i-05 O.)0001 1.00015 0.0,02


5e-rC', O.]nn L.n r.130 nl O.uj,21


Figure 2-47. Simulation to show the controller correction for +6dB, +5.5dB and -6.5dB
gain variation.










Let W =e N then


X(k)= 1 x(n)(e


WNx(O)+ WkN-x(1)+...Wkx(N- 2)+Wkl(N


The transfer function of the system that estimates the DFT is represented as

1
H(z) = 2
l-eJN z-'


Y(z) 1
X(z) l-eJ Nz


y(n) (n)+ y(n )e (n)+ y(n )WK
y(n) = x(n) + y(n 1)e N = x(n) + y(n 1)Wx


(3-41b)


(3-41 c)


Expanding 3-41c results in


y(n) = x(n)+ x(n -1)WK + x(n- 2)WK2 +.....x(O)WK


(3-41d)


Comparing Equations 3-41c and 3-41d it is clear that the required transform is obtained

when


X(k) = y(N)


Multiplying the numerator and denominator by the conjugate, results in


H(z)


1 ,(1
( -z1) (1
(- Wk -) 1


1 1)
Wk-z-1)


(3-41e)


Hence,


H(z)


(- ''-1 W )
(1 k 1 Z
(1 (Wk + Wk )z -1 +z-2)


Y(z)
H(z) =()
X(Z)


(1- Wkz1)
2 k 1
1- 2cos z +z
N


)"= x(n)Wk(N-n)











ss1








I
5e-05 .0001l 0.000150.0002


Figure 2-48. Simulation to show the controller output to track for +10dB, +3.5dB and -
5.5dB gain variation.







Communication testing .
Equipment to measure 'i
Mobile system *.. ... i
performance : /




SRf Ports RF cable

0 Evaluation
Z6 RF
S Board AUX interface
PA





Evaluation RF C 4 l d
Evaluation RF Computer installed
Radio With LabView tool to
Regulator IC B Mimic baseband processor
I I ____ USB cable and basestation


Figure 2-49. System interface for mobile device testing














RI Q

Clk=fs


Figure 2-12. Linear Feedback shift register for a 6 tap pseudo random signal generator


Clk=fs------ ----- ----- ----- I I

X 1 1 11 1 1 Xo111 11Xoo 1 111X 1 1 1


CIk=6*fs


Output sequence c(n)


111111011111001111000111


Figure 2-13. Timing signal to generate 6 times faster sample rate at the output











T a Ru I Irigid


. Trigger signal



Controller
Output tracking for
introduced
Disturbances
Under damped


Clhl 2.00 \ V 200m11V n 20.0ps A Chl
U-' SO. :300ps
Select Remove Gating High-L
Mefsrm Measrmnt Off Auto
forCh2 Aut


Remove
Measurement

1


2






4


f 360mV \ A
Measulren in s

.w0 Reference Indicators
Levels Off


Figure 2-52. Analog response of the controller output shows oscillations due higher
value of integral gains captured by Tektronix oscilloscope




TekPreVu I .. [


U


A Trigger
Source


Triunuer stnal


Controller
Output tracking tfior
intloii(dced
DistLiibances
(-)\ er damped


\I I_
I) Al


2IT
Type
Edge


1.00 V Ch


ChI:


2 200m11V N I 0.Ops A Chi I 320111 -ore-
1 ol :3
U-'v 3:9.(000ps
I Mode
Source Coupling Slope Level Normal
Chi Noise Rej J 520mV & Holdoff


Figure 2-53. Analog response of the controller output to shows over damped condition
due lower value of integral gains captured by Tektronix oscilloscope


Tek Run I


Tria'd


Iu--














Q(t)_comp= *smn(wt+ + _err) PA
Symbols nneRF


1s e B a nd control 0 I c. i
-/chanel Bs Band con
Q(t)=sm(wt+ 0) Filter Gej(wTXt+%)
sin( _err) RF Section

cos(6 _err) g(t) =DG[I(t) + jQ(t)]e" e"


DNLE


DSP code

Step SVGA to state 1 (G2e J2) and estimate I DFT1
DG 1 Complex single point DFT_
I -) D[DFT(G e)*A1) f- 1 1 -)ej(&'A1-0) = I \ -_-= G"(e ( w-tiw,+'()
DFT(GleI)= ,I^esliding DFT DSP .-e \..-)+
Increment the VGA gain to the next state, to (G2e ) and sng DFT DSP
estimate I DFT2
I_ DFT1(G2e12D) G e1 2-) Single point
2 /- 2 2 1 ~^ ~A sliding DFT DSP 1 r \
S. T e-[=-Q 2 _1 Q RQx(t)= Q(t*'G(e'<-"'
Estimate ratio of the magnitude of the corresponding DFT's C-l i T
Complex single point DFT_Q

Rato(2,1) I DFT(Ge2
\IDFT(Ge A1)


Ratro(2,1)= IG,
2 L2
Ratio(2,1) = AG[ej(A'], the gain and the phase shift.






Figure 3-6. Gain and phase estimation A) System block diagram of the mobile device with the DSP-GPE algorithm. B)
Implemented frequency location of the calibration signal during the algorithm


126









2-28 Cascaded structure for the fast average circuit .......................................... 82

2-29 O utput of second filter vs. tim e in sec........................................ ...................... 82

2-30 DSP structure for PID controller with programmable gains..............................83

2-31 Controller gain programming hardware............................................... 83

2-32 Digital implementation of 12 taps cross-correlation DSP hardware....... ........ 84

2-33 Cross-Correlation of calibration signal .......... ......... .. ...... ................... 85

2-34 Simulation to show the correlation estimate between the calibration signal
and the feedback signal .......... ........ ................... ...................... 85

2-35 Signal buffer of baseband signal envelope ............. ...................... 86

2-36 Detected Signal at the output of the ADC at the signal sample rate (no
dow nsam pling) .................... ............................................ .................... ...... 86

2-37 Normalized signal correlation between baseband signal envelope and
detected signal. ................................................................................... 87

2-38 Time aligned gain scaled baseband signal envelope and detected signal.......... 87

2-39 Correlation estimate of baseband signal envelope and feedback signal with
dow nsam ple ratio of N =2 .................................. ... ....... .. .............. 88

2-40 Correlation estimate of baseband signal envelope and feedback signal with
dow nsam ple ratio of N =5 ..................................... ......... .............. 88

2-41 Correlation estimate of baseband signal envelope and feedback signal with
dow nsam ple ratio of N = 10 .............................................................. .... .... .. 88

2-42 Correlation estimate of baseband signal envelope and feedback signal with
dow nsam ple ratio of N =20 ...................... .. .. ......... .................... ................ 89

2-43 Simulation to show injected 6dB gain variation and the reference signal level ... 89

2-44 Simulation to show the controller output adaptation for a positive 6dB gain
variation in m multiple steps......................... .............. .............. ............... .. 90

2-45 Simulation to show the closed-loop response with respect to different integral
gains for a positive 6dB gain variation....................................... ...................... 90

2-46 Simulation of the closed-loop circuitry adaptation until error signal becomes
zero. ............. ................................. ............................. 9 1









Apply a step response as the input and observe the system output.

Change the proportional gain iteratively until loop oscillates with a period T and
amplitude A as shown in Figure 4-6.

The smallest proportional gain that makes the output of the loop to oscillate is
called as the ultimate gain, K .

Based on the estimation of K, and the time period of oscillation T, the integral and the

derivative gains are calculated as described.Let K, =Kp _ultimate, is the smallest

proportional gain used when the loop response starts to oscillate. Let the amplitude of

the oscillation is given by A and the time period is represented byT. By characterizing

K ,A and T based on Ziegler and Nicholas approach the PID control parameters are

calculated as described below.

K, = 0.6K

Ki= 0.5T (4-18)

Kd = 0.125T

The above mentioned techniques can be used to determine a nominal loop gain

settings and further manual automation and simulations should be used to determine

the most accurate settings. In the described DSP-GC technique a combination of the

above mentioned techniques are used to estimate nominal values for the integral gains

and convergence factors analytically. The values calculated are then used as initial

estimates in system simulations based on which the final accurate value of integral

gains and convergence factors were obtained. The following section describes a novel

method to predict the controller gains for an unknown Nth order closed-loop system.


153




























ET W,= S,
W,, = W, + 2puE


12,0,u>


KI
Integral
Gain


Figure 4-2. DSP hardware implementation of the adaptive filter and 1st order integrator


169



















- 1
l'i,, rr, I_- ,-I i I' I,, l: ,,il ,- ;I- I I- II" """ ) r11-1_- D .I .I,-I lhll ... i
--- II --...........I


. L
.ci


1' 11ll


Connect.
Control

Power
vs Time


Analyzer
Level

Analyzer
Settings

Generator


mla~


I ,--1 i IJl
Level Scalei |cale S cale Menus


Figure 4-1. Power control A) Measured transmit power to show the PAR and PTN of a LTE signal captured by Rhode and
Schwartz CMU 2000 B)System architecture of the DSP-GC algorithm implemented in a mobile device


,,,,, ,,,,,,, ,,,,,, ,,,,,, ,,,,,









= DG[cos(ioFt + 0 + A) + j sin(oiFt + 0 + A)] cos(,BBt + q)

= DG[(cos(CFt + 0 + A) cos(CBt + 0)) + j(sin(oFt + 0 + A) cos(cBt + 0))]

D, [(cos(cWF + BB )t+ + 0 + A )+ + (cos(oF> oBB)t + 0 + A q)
2
+ j(sin(oF + BB)t + 0 + 0 + b) + (sin(F oBB)t + 0 + A q))

Let P = (oF + cBB)

and Q = (iF -OBB) this results in


I(t)D1G(eJ(st+ ) = D, [(cos(Pt + 0 + 2 + O) + (cos(Qt + 0 + 2 0) +
2 (3-16)
j(sin(Pt + 0 + 2 + 0) + (sin QtO + 2 0))]

Expanding the 2nd term of Equation (3-15), we get

= jQ(t)GD1(eJ(F'+t0)

= jGD1 [cos(loFt + 0) + j(sin(ojFt + 0)] sin(cBt + q)

G
SD, [j sin(Pt + 0 + )) j sin(Qt + 0 0) (cos(Qt + 0 q) + cos(Pt + 0 + 0)]
2

G D1 [cos(Pt + 0+ q) (cos(Qt +0 q)+
=2 (3-17)
j(sin(Pt + 0 + q) sin(Qt + 0 0))]

Adding (3-15) and (3-17), results in

GD [(cos(Pt + 0 + 2 + () + cos(Qt + 0 + 2 )) + cos(Pt + 0 + 0) (cos(Qt + 0 ) +
=2
j(A sin(Pt + 0 + 2 + )) + (A sin Qt + 0 + 2 )) + (sin(Pt + 0 + ) sin(Qt + )]
(3-18)

where, P = (cF +cBB) and Q = (cF -cBB)


The DSP-GPE technique uses a single baseband tone through the I channel. The

blue plot in Figure 3-7 shows the spectrum of transmit baseband signal C(t)= I(t)


110










Table 2-1. Estimation of best a and P factors for magnitude estimation


alpha*max(ll IQI)
0.952892
0.771094
0.906476
0.906476
0.771094
0.952892
0.771094
0.906476
0.906476
0.771094
0.952892


beta*min(lll, IQI)
9.16E-05
0.220419
0.115881
0.115881
0.220419
9.16E-05
0.220419
0.115881
0.115881
0.220419
9.16E-05


ideal
magnitude
0.999755
1
1
1
1
0.999755
1
1
1
1
0.999755


a=61/64,b=12/32
0.952984
0.991514
1.022357
1.022357
0.991514
0.952984
0.991514
1.022357
1.022357
0.991514
0.952984


a=15/16,b=15/32
0.937386
1.033978
1.036467
1.036467
1.033978
0.937386
1.033978
1.036467
1.036467
1.033978
0.937386


a=122/128,b=31/32
0.952991
1.009882
1.032014
1.032014
1.009882
0.952991
1.009882
1.032014
1.032014
1.009882
0.952991


a=31/32,b=12/32
0.937363
0.978873
1.007497
1.007497
0.978873
0.937363
0.978873
1.007497
1.007497
0.978873
0.937363


time
index
0
1
2
3
4
5
6
7
8
9
10









2.5.1 Digital Calibration Signal Pattern Generator............................... 47
2.5.2 Digital Sample Rate Adjust Logic...................................................... 47
2.5.3 M magnitude Estim ator .................. ................. .. .............. .......... 48
2.5.4 Fast Exponential A verager.................................................................. 51
2.5 .5 D igital P ID controller................ .................. ... ........... .. ............... 53
2.5.6 C ross-C orrelator H ardw are ............................................................... 54
2.5.6.1 Simulations with the cross-correlation DSP hardware............. 56
2.5.6.2 Correlation estimates at varying sample rates.........................58
2.6 Top Level System Simulations and Measured Lab Results................................59
2.6.1 System Sim ulations ................................................................... ........ 59
2.6.2 Mobile Testing and Lab Measurements..................... ..... ..............61
2.7 Sum m ary ............. ...... ............ .... ....... ...............62

3 DSP BASED DYNAMIC ESTIMATION AND COMPENSATION OF
DIFFERENTIAL GAIN NONLINEARITY AND RANDOM PHASE SHIFTS........... 100

3.1 Demands for Relative Gain and Phase Accuracy in Mobile Devices .......... 100
3.2 Analytical Expressions for Non Linear Distortions in an Analog RF Device.. 101
3.3 Reasons for Relative Power Level Accuracy Impairment............................ 105
3.4 Reasons for Phase Discontinuity ..................................... ......................... 107
3.5 DSP based Relative Gain/Phase Estimation Algorithm Theory (DSP-GPE). 108
3.5.1 Theory of O operation ....................... ...... ............... .. 108
3.5.2 Gain and Phase Estim ation Steps ................... ................................ 112
3.5.3 Gain and Phase Compensation Implementation and Equations........ 113
3.5.4 Derivation of Equations for Gain and Phase Estimation and
C om pensation ...................... ... .... ......... ................... ... 114
3.6 DSP Hardware Structures for Relative Gain/Phase Estimation and
Com sensation ................ ................................................. ..... 116
3.6.1 Phase Com pensation DSP Structure....................... ......................116
3.6.2 DFT Based Gain Estimation Structure........................................... 116
3.7 System Simulations and Lab Measurement Results.................................... 119
3.7.1 System Simulations of the DSP-GPE Algorithm ...............................121
3.7.2 Lab Measurement Results ...... ......... ......................................... 121
3 .8 S u m m a ry .................................................................................... 12 3

4 DYNAMIC GAIN/POWER CONTROL USING ADAPTIVE DSP TECHNIQUES ... 143

4 .1 Intro d u ctio n .................. ........................ ................... ....... 14 3
4.2 System Architecture for the DSP-GC Algorithm ............................................ 144
4.3 Loop T uning Techniques ........................................................... ................. ... 150
4.3.1 Method I Reference Model Based Loop Tuning................................ 150
4.3.2 Method II- Open Loop Tuning Based On Unknown Plant Transfer
F unctio n .......................................................... ........... ............ 152
4.3.3 Method III Loop Tuning Based on Closed-loop Cycling.................. 152
4.3.4 Method IV Implemented Loop Tuning Technique Based on
C losed-loop Stability C onstraint ......................................................... 154
4.4 Closed-loop Delay and Loop Gain Margin Analysis .................. ........... 157









3.7.1 System Simulations of the DSP-GPE Algorithm

The performance of the DSP-GPE algorithm is analyzed by system simulations.

Table 3-5 shows the estimated DFT by using the fixed point model of the DFT estimator

hardware. At each RF gain amplifier step, the absolute magnitude of I_DFT is estimated

by assuming N =512 samples. To avoid spectrum leakage, it has to be taken care that

the DFT measurement has to start at the proper time instants to capture periodic cycles

of x(n).The complex I_DFT output is tabulated in Table 3-5.

After eight periodic measurements, the DSP algorithm calculates the ratio of


successive I DFT measurements. Thus the ratios Ratio(m,n)= I DFT(Ge) is
I DFT(Gme ])

calculated by the DSP algorithm.Table 3-6 shows measurements tabulated that

correspond to ratios of consecutive eight DFT measurements. The ratio

I DFT(Ge' ")
I DFT(Gne") will lead to a gain and a phase component AG andu err
\I DFT(Gme am )

respectively. The desired gain change, AG,, and the difference DNLE= y = AGr, -AG is

calculated and applied to the baseband signal. The amount of phase change estimated

err is directly applied to the baseband signal as a pre-distorted phase to maintain

signals phase continuity specifications. The simulation results show the performance of

the algorithm with the introduced gain and phase error. Simulations performed over

worst case process variations reveal that the algorithm predicts the gain error better

than 0.1 dB and phase error better than 1 degree accuracy.

3.7.2 Lab Measurement Results

Figure 3-18 shows measured INLE curves for the 16 stage driver amplifier after

baseband gain error compensation. The DSP-GPE algorithm is performed as a part of









2.3.3 Forward Reference Path

As shown in Figure 2-6, the digital signal is tapped before the DAC and used as

the reference signal for the algorithm. The magnitude of the in-phase signal component

and the quadrature signal component signals are estimated by the fast averaging

hardware. The magnitude is then averaged by using the exponential average DSP

hardware and used as a reference signal to the proportional and integral controller. As

shown in Figure 2-6, the closed-loop feedback loop controller tracks for any change in

gain variations between the feedback and the reference signal paths.

As the ideal gain of the feedback path and the forward path is known, the gain of

the reference signal path is calibrated accordingly. A digital cross-correlation circuit is

employed to estimate the cross-correlation between the reference signal and the

feedback signal to calibrate the delay buffer in the reference signal path. This helps in

dynamically calibrating the delay between the reference and the feedback signal paths

before the gain estimation and tracking is performed. The buffer control logic also

adjusts for the sample rate differences between the forward path and feedback path

signals.

2.4 Algorithm Theory

The block diagram of the described system architecture is shown in the Figure 2-6. The

components of the algorithm are described as follows.

1. Buffer control for sample rate and block size adjustment (DSP hardware)
2. Fast exponential averaging circuit(DSP hardware)
3. Fast magnitude estimation(DSP hardware)
4. Gain controller with proportional, integral and differential control (DSP hardware)
5. Digital calibration signal pattern generation circuit. (DSP hardware)
6. Signal cross-correlation circuit. (DSP hardware)
7. Feedback path power detector (RF discrete component)
8. Analog feedback gains (analog baseband)
9. Ant-aliasing filter and ADC (analog baseband)









system. Depending on the settling time requirements of the system protocol, the integral

gains of the controller and the convergence factor of the adaptive filter are selected that

will result in the desired peak overshoot, the settling time and the steady state error. It

can be observed from Figure 4-20 that as the integral gains are increased above -20dB,

the system becomes unstable.

Figure 4-21 shows the measured transfer function of the power detector which

plots the input Pout (dBm) vs. quantized feedback signal. Based on the measured

characteristics, it is clear that the slope of the power detector is smaller at lower input

power levels and larger at higher power levels. In the presence of such non-linear

systems within the closed-loop function, appropriate loop gain programming strategies

have to be adopted to meet the desired system performance. As a strategy, in order to

compensate for sluggish response at lower power levels, a higher integral gain (less

attenuation) is used to make the loop respond faster. As the slope increases at higher

power levels, a relatively lower integral gain (higher attenuation) is used to satisfy the

desired system requirements of less than 3dB overshoot and 40usec settling time.

Hence the closed-loop operating range is sub-divided into low, high and mid power

control regions. As a result of the non-linear open loop characteristics there are three

regions over which the integral gains are chosen over the power control range of OdBm

to 24dBm transmit power level.

System simulations and lab measurements conclude that for power levels between

OdBm and 6dBm, an integral gain of -20dB is used and for the range of power levels

between 6dBm to 1 dBm an integral gain of -40dB is used. Similarly, for a range of

power levels between 12dBm to 15dBm an integral gain of -50dB is used. In addition to









2-6 System level block diagram of the DSP-DGT architecture................................ 66

2-7 Controller adopted for the closed-loop DSP-DGT algorithm .................... ........ 67

2-8 Second-order closed-loop PID controller .......................................... ........ 68

2-9 Closed-loop dynamics when the controller compensates for undesired
positive gain change ............. ......... ........ ............... ................69

2-10 Closed-loop dynamics when the controller compensates for an undesired
negative gain change .............................. ........................... ............ 70

2-11 Flow chart of the steps involved in the DSP-DGT algorithm ..............................71

2-12 Linear Feedback shift register for a 6 tap pseudo random signal generator....... 72

2-13 Timing signal to generate 6 times faster sample rate at the output ........ ........72

2-14 Output pseudo random bit stream from a 6 tap linear feedback shift register. .... 73

2-15 DSP im plem entation of sam ple rate logic ................................. ...... ............ ....74

2-16 In-phase and quadrature phase signal swings whose magnitude has to be
estimated. .............. ..... .. ........... ........ ......................... 74

2-17 Instantaneous error (linear) vs. input signal swing function as a function of
a and p factors.......................................... ...... .................. 75

2-18 Simple absolute value estimator logic ...... ................... .......................... 75

2-19 Digital DSP hardware structure for magnitude comparator............................... 76

2-20 Digital DSP hardware structure for the magnitude estimator ............................. 77

2-21 System simulations with quantized I and Q random signals and mean error in
estim action. .............. ......... ..... .................................. ......... 78

2-22 Ideal and obtained signal m agnitude......................................... ...................... 79

2-23 Magnitude error in dB as a function of buffer hardware length ................................79

2-24 DSP structure of the exponential average ............. ...................... 80

2-25 Settling times of the average as a function of filter factor............................... 80

2-26 Dynamic varying filter factor depending for noise and response time trade
offs. ................. .................................... ........................... 8 1

2-27 Magnitude response of the averager............... ....................... 81









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[41] Razavi, B, "Challenges in Portable RF Transceiver Design, IEEE Circuits and
Devices Magazine, Sep 1996, vol. 12, pp. 12-25.

[42] M.H Norris, "Transmitter Architectures, IEEE Colloquium on Design of Digital
Cellular Handsets, 1998, pp. 4.1-4.6.


192









where, D, is the digital gain, G and el" is gain and phase shift introduced by the RF VGA

for that gain step. The modulated transmit RF frequency introduced by the modulator is

denoted by e"t.

During the algorithm operation, the output of the transmit gain amplifier g(t) is

looped back into the pseudo-receiver [22] section which has an RF gain and a

demodulator stage. The RF signal g(t) is demodulated back to baseband frequency

depending on the frequency offset between the RF modulator and the demodulator.

Depending on the frequency offsets between transmit and receive VCO's the desired

baseband signal frequency can be altered. Assume eJ xt) is the transmitting frequency

and ej'(") is the demodulation frequency and the frequency difference is defined by

ej(,-t). Based on this assumption, the received demodulated baseband signal is

represented by

RxBB(t)= g(t).G(eJ("Rxt+)), where ej( 0'RY )= (ej('oTxt t+ m )

= DG[I(t) + jQ(t)]eIJeO^xtG(ej (-oXt+oJt+o))

= DG[I(t) + jQ(t)]ejlG(ej(0"t+o)

= D, [I(t)G(e I('"'Ft) + jQ(t)G(e I('t+BF )] (3-15)

Hence, the demodulated baseband signal has a frequency of olF and can be

represented as described in the Equation 3-15.

Expanding the 1st term of Equation (3-15), can be expressed as

I(t)DG(e j(""t ) = DG cos( ,t + )(ej(""t+o+

=D1G(eJ(Ost++) a)cos(),BBt + t)


109









3.5.2 Gain and Phase Estimation Steps

Based on a tonal input into I channel or Q channel of the mobile transmit signal

path, the estimation of the gain variation and phase drifts can be described in three

steps.

Step 1:

Calculate the first DFT corresponding to a complex gain and phase shift applied at the

VGA. Let this applied gain step at the VGA result in gain G1 and a phase shift of A,.

The composite gain and phase change is represented as Gle"". From Equation 3-19,

the I channel DFT can be computed as

I _DFT(Ge'))= DG eJ(+ 1)
2 L2 1 (3-23)

Step 2:

Increment the VGA gain to the next state, to G2e 2, then the corresponding I channel

DFT is computed similarly as

I DFT(G2ej2 )DG2 lej(O+2- )
2 L2 1 (3-24)

Step 3:

The ratio of the magnitude of the corresponding DFT's are calculated.

SI DFT(G2,e 2)
Ratio(2,1) = -I 2
S\I_DFT(G e'' ) (3-25)


D,91G2 II (e+ 2 2-) G2 j(,Z2-,1)
2 2 Gi (3-26)
D,1G e(0+l 21
2 L2

= AG[ej(A)


112









baseband signal and perform dynamic cross-correlation to estimate the delay between

the reference and the feedback signal paths. Hence, depending on the type of

modulation schemes used, the baseband signal can be adopted and the cross-

correlation between the forward path and the feedback path signals can estimated to

calibrate the delay dynamically.

Figure 2-35 shows a buffer of 120 samples of baseband signal envelope. The data

is simulated from a typical WCDMA channel case according to the mobile device

specifications. The sample rate is 62.4MHz and each of the buffer size is 120 samples,

which is about 1.92usec of data. As described in earlier sections the baseband analog

signal passes through the RF mixer, amplified by the PA and transmitted at the output

of the mobile device. The transmitted RF power output is fedback through the power

detector as described in earlier sections.

The detected power from the PA is fedback through the analog gain stages and

sampled with the ADC depending on the sample rate selected. Figure 2-36 shows the

detected signal at the output of the ADC. This signal can be assumed as a delayed and

scaled version of the baseband signal envelope as the feedback signal passes through

an envelope detector and gets scaled by feedback gains. Figure 2-37 shows the signal

cross-correlation between the baseband signal envelope and the detected signal. Signal

correlation is performed between the block of the baseband signal envelope and the

delayed and the scaled fedback signal. The correlation index results in peak estimate

when the signal pattern overlaps. Based on the signal correlation estimate, the delay

between these two paths is estimated.Figure 2-38 shows the gain and time aligned

version of the detected and the reference baseband signal envelope. The estimated









Hence it is critical to reduce the variance of the error signal to result in faster

convergence. The difference Ek =Dk -Ak is calculated on a sample by sample basis.

For each iteration, k the output of the filter Sk is updated. The output of the adaptive

filter Sk passes through an integral controller that accumulates the error signal to

generate a gain correction signal acc(k)as the loop output signal. The gain correction

signal is applied to the transmit path to perform the desired amount of gain change as

signaled by the baseband processor.

Based on simulations performed, it was found that the trade-off between the loop

stability, gain margin and loop settling time was reached by choosing appropriate

integral gains KI, the convergence factor /u and the number of taps of the adaptive

filter. Assume at iteration k = 0, each of the registers of the adaptive filter is initialized to

zero. Hence for k = 2 taps filter, the weight update equations can be represented as

shown in Table 4-1. Assume for tap N = 1, the first weight vector at iteration k = 0 is

represented as

wio = 0, for N = 1,k = 0.

For filter tap N = 1, iterating k, results in

w,, = W0 +/ Eo2 = pEo

w12 = w,, +/1E =/ E02 +EUE = [E2 +E ]

,13 = W12 + pE2 2= pE02 + pE12 + PE22 = [E02 +E12 +E22] (4-1 Oa)



1,n =W1n-,) +plEn,_ = p[E02 +E2 +E22 +...E,_12]

In general for n samples, in general the weights are represented as


148









technique has been implemented using digital DSP hardware and system lab

measurements have been provided to validate the performance. DSP hardware

structures employed in this algorithm are described along with system measurements.

2.2 Reasons for Signal Gain Variations in Mobile Devices

Before we introduce solutions, it is important to investigate and understand the

reasons for signal gain variations in any mobile device. The reasons for gain variations

are discussed in the following section.

2.2.1 Gain variations due to Manufacturing Processes

The performance of the baseband and RF components is a function of variations in

manufacturing process. Although the components are manufactured according to a

particular set of design specifications using defined manufacturing processes, non-

uniform results may be obtained due to uncontrolled deviations in the processes used to

fabricate the constituent semiconductor components. Typical cellular telephone designs

attempt to locate the baseband DAC, ADC and RF components in different physical

locations in the cellular telephone to avoid interference. One drawback of this design

approach is that the process variations in the manufacturing phase of the components

do not track one another. In a worst case scenario, the DAC, the ADC and RF

components have a maximum variation in the same direction which results in a

maximum total transmit gain deviation from the nominal transmit gain value.

The measurements were performed inside a temperature chamber and averaged over

three IC's. Figure 2-2 shows that the measured RF power level drops as the

temperature increases. This drop in RF output power will eventually degrade

communication link performance and ultimately lead to lower signal to noise ratio [57,

60, and 62].









3.4 Reasons for Phase Discontinuity

In systems operating at high frequencies such as cellular, WiMax the relative

phase change of the signal occurs due to

* carrier phase shifts that occur due to change in capacitive impedances during an
RF power change in multi-stage amplifiers. This is because the gain control in
the majority of present day RF amplifiers is based on altering the current through
capacitive segments.

* random signal phase changes due to the baseband analog filters stages

* random carrier phase offsets caused every time the RF VCO[69] is enabled.

* temperature compensation circuits in RF circuits such as mixer and VCO's which
cause unknown carrier phase changes.

For the sake of analysis, assume that the primary cause of the phase shifts introduced

into a mobile system is due to change in RF gain stage of the amplifier within the

system. If A, and 22 are the absolute phase changes (degrees) when the RF gain

amplifier is at step G1, and G2 respectively, then the relative phase change is defined as

AA(1,2) = / A2. This change In-phase angle will lead to unknown random phase shifts of

the RF carrier signal. Figure 3-5 shows measured results of relative phase shifts for a

discrete 16 stage gain RF amplifier. The relative phase changes between two

consecutive stages m and n are represented by AAm, n .The change in carrier phase

shift must be compensated so that the transmitted signal does not undergo relative

phase shift changes when stepping through the gain amplifier stages. The introduced

carrier phase shifts are either due to changes in capacitive impedances of the high

frequency amplifier or due to frequency dependent phase drifts introduced by analog

circuits in the transmit path.












Enable digital clocks
Set the digital baseband gain to be D,

Send Baseband signal I(t) and Q(t) with
tone frequency WBB
I(t) = cos(wt + b)

Q(t)= sin(-, t +)


Set RF upconversion Wt
frequency to be WTx e Jew
Set RF downconversion
frequency to be rand t
WRx=WTx+WIF ew

eJ = eJ Randd


Set the RF gain amplifier to G1 state (Glejl)


The transmitted signal is
g(t) = DG[I(t) + jQ(t)]eJAe""wF
I


Estimate complex DFT for real I
signal
I DFT(Ge'" )=DIGI e'(.1-)
2 2


Increment the VGA gain
to the next state, (GC2e2 )


Re-Estimate complex DFT for real I
signal
I DF7(G,"')= -q-[12 e....


Compute ratio of consecutive DFT's

Ra IDo(2,1) DFT(Ge2) G2[e(2l) i
SI _DFT(GeI') G,
Rafto(2,1) = AG[e)]

Estimate Gain DNL Error
and Phase offset error
DNLE =y= AG, -AG
err =1 A2,e A2 I




DNLE = err = A,, A I


Figure 3-8. Flowchart of the DSP-GPE algorithm for relative gain and phase change
estimation


129


Is RxBB(t)

I ')= DG[I(t)+jQl ,]. -(e (...o)








K=15 which corresponds to 146.51 KHz (oIF + CBB ), where Wi = 100KHz and

~,BB =46.51KHz. The frequency of the tone oBB has to be selected so that the DFT bin

falls exactly on an integer multiple of K.

K =146.51KHz 512= 15
S5MHz )

The following descriptions explain the basic steps involved in the gain and phase

estimation algorithm.

Step 1

By employing the DSP hardware, calculate the first I DFT with the complex gain and

phase shift applied at the VGA to be (G2e" ). The I _DFT is calculated as

I _DFT(GleJI) DG1 ie j(O+1-
22

Step 2:

Increment the VGA gain to the next state, to(G2e J2), then the corresponding I _DFT

is computed in the same way as

I DFT(G2e J2) DG2 Ie(IlJ+A2-)


Step 3: The ratio of the magnitude of the corresponding DFT's are calculated.

|I DFT(G2 A2)
Ratio(2,1) = DFT(G2e2) (3-43)
I DFT(GeJ"' )

DG2 j(eO+2- 2 )
Ratio(2,1) 2 2 G2 [ej2-1)] (3-44)
DG, 1 FgeJ(eOi ) G,
2 L2 ]

Ratio(2,1) = AG[e j(A)], is the estimated gain and the phase shift.


120









4-10 Step response of the unknown open loop system ......................... ...........172

4-11 Plot of poles of the transfer function with KI = K max ................... .... .. .............. 173

4-12 Closed-loop system simulations with appropriate integral gains..................... 173

4-13 Simplified model for loop delay and gain margin analysis............................... 174

4-14 Pole-zero location with loop delay, D = 1, 3, 7 and 9 samples at sample rate
s. ......... .... ....... ......................... .......... 174

4-15 Pole-zero location with loop delay, D = 13, 17, 19 and 21 samples at sample
ra te F s ............. ......... .. .. ......... .. .. .......... ...................................... 1 7 5

4-16 Pole-zero location with loop delay, D = 24, 26, 28 and 31 samples at sample
ra te F s ............. ......... .. .. ......... .. .. .......... ...................................... 1 7 5

4-17 Pole-zero location with loop delay, D = 39, 45, 52 and 58 samples at sample
ra te F s ............. ......... .. .. ......... .. .. .......... ...................................... 1 7 6

4-18 Closed-loop step response with respect to varying plant delays ...................176

4-19 Pole-zero location with loop delay, D =13 samples and integral gains of -36
dB, -32dB, -30dB and -26dB ......... .... ......... .. ...................... ...... .......... 177

4-20 Pole-zero location with loop delay, D =13 samples and integral gains of -22
dB, -20dB, -6dB and 9dB. ........ ......................... ............ ........ ............. .... 177

4-21 Power detector and feedback path input-output characteristics....................... 178

4-22 Loop gain margin with varying loop delay as a function of antenna power....... 179

4-23 Simulation to show the closed-loop dynamics for a positive power change...... 180

4-24 Simulation to show the closed-loop dynamics for a negative power change..... 181

4-25 Simulation to show the adaptation of the LMS algorithm with weights and
e rro r s ig n a l ...................... .. .. ......... .. .. .......... ................................ 18 2

4-26 Simulation to show the rate of change of error signal and the feedback as a
function of convergence factor ........._... ... .......... .............. ................ 183

4-27 Analog response of the closed-loop system with the adaptive filter captured
by T ektronix oscilloscope ............................... .............. ................ ......... 183

4-28 Analog closed-loop response for multiple steps with the adaptive filter
captured by Tektronix oscilloscope ............................. ...... .......... ............ 184

4-29 Transmit power of the mobile device captured by CMU 2000.......................... 184









4.3.4 Method IV Implemented Loop Tuning Technique Based on Closed-loop
Stability Constraint

This section describes a novel method by which the controller gains are estimated

based on pole placement stability constraint. Figure 4-7 shows a generic block diagram

of a closed-loop system with an integral controller. In z domain, the closed-loop

parameters involved in the analysis are represented as follows.

* The unknown open loop plant transfer function is denoted as Gp(z),
* KI is the integral gain of the controller employed,
* R(z) is the system input represented in Z domain,
* Y(z) is the system output,
* E(z) is the error between the reference signal) R(z) and the feedback
signal Y(z).
* p is the feedback gain
* Z-D is the delay through the feedback path.

The primary goal of this method is to estimate the maximum value of integral gain
K1 max above which the system become unstable. The significance of adopting this

approach is that this technique does not require prior knowledge of the open loop
system transfer function. The steady state gain and the delay can be characterized as a
lab experiment by applying a unit step input to the open loop system Gp(z) and by

monitoring the system output. At steady state, irrespective of the order of the open loop
plant transfer function Gp(z), it can be represented as Gp(z) = Gz where G,, is the

open loop steady state gain of the plant and z L is open loop delay. Hence the open
loop plant gain (G,,) and the delay (z L) can be computed based on a step input

analysis. Based on the estimated values for G,, and z the system block diagram at

steady state can be represented as shown in Figure 4-8. The next step is to derive the
expression of the closed-loop transfer function H(z). The system output is represented
as

Y(z)
H(z) R(z)
R(z)


154
























Fge- Rdtoosw f


Figure 1-8. Reduction of signal power from
Schwartz CMU 2000 analyzer













1 ,1 ,,- u


I


I:ornct
Control
.... "' "' P o r
W Tim


the mobile device captured by Rhode and













Control






..llll-l','- .;^ .



,IAfl~ ,



DApla

*IM-n


Figure 1-9. Multiple power changes of the mobile device captured by Rhode and
Schwartz CMU 2000 analyzer


I.,, lr I,,,,,


rC~LC~LC-I~LII


I


11.1 I I I



























Quest for knowledge, the learning, and the humility that accompanies it




































Figure 4-13. Simplified model for loop delay and gain margin analysis










Stability Analysis of H(z) for loop delay D = 1, 3, 7 and 9 samples at Fs


*, D=1



--o







-1 -0.5 0 0.5 1
Real Part



D=7
X X




x 2

X x



-1 -0.5 0 0.5 1
Real Part


0.5


. 0
'i
E
--0.5


-1





1


S0.5
a.
M
h o

E
--0.5


-1


X
--

x :
N- ,




-1 -0.5 0 0.5 1
Real Part






Sx
D x =9


x


:X


-1 -0.5 0 0.5 1
Real Part


Figure 4-14. Pole-zero location with loop delay, D = 1, 3, 7 and 9 samples at sample

rate Fs.





















174


1


0.5
a
m 0
0.
-Eg
E











0.5

-1
M 0.5

0)
| 0
.-.

E
--0.5


-1


















PSD of Tx BB /
-100K OO1K
Tx Baseband
Real tone through I
channel


PSD at Output of Tx LO


SWtxrf


Wtx_rf-l00k Wtx rf+l00k


Wif+100k


Wif


Figure 3-6. Continued








E(s) = R(s)- PY(s)


The controller output P(s) is represented by

P(s) = (sE(s)K ) + KpE(s) + K,IE(s) (2-7)
s

Solving for the time constants,

Y(s) = P(s)A(s)
(s + p,)(s + p2)

P(s) E(s)[(sKD)+Kp + K,]
s

Y(s)= E(s)[(sKD)+ Kp + K, ]A(s)
s (s + p)(s + P)

(s +71(s +T AGPK,
Y(s) = E(s)[(s r-)(s r2) AGpKD
s (s+ p)(s + p)


KD KD
where ,i, r K (2-8)
2

Y(s) E(s)[(s + r-)(s +r2) AGPKD
s (s+ p)(s + p)

s(s + pl)(s + p2)Y(s)
(s + rl)(S + r2)AGpKD

E(s) = R(s)- fY(s)

S (S + Sp)(s + P) + fY(s) = R(s)
(s + )(s + T,)()AGKD

(s+Tr)(s+G )AGKK
Y(s) = (rl)(s +r2)AGpKD R(s) (2-9)
Ss(s + p,)(S + P2) + f(s + rz)(s + r2)AGPKD





















2 375











low_band m-d_band high_band
35
325

25 3 5V




S 3275V 4259 43116 3912V
S25
S2
O
p 175
15
1 25

low band mid band highband
25V 4114 3989 3759
30 V 4259 4116 3912
335V 4372 4275 4044

Frequency bands of operation




Figure 2-5. Pout variations across frequency bands over supply voltage














Tx Baseband signal fbb at centered @ OHz






50

-6 -4 -2 0 2 4 6
Frequency Hz x 106
Tx modulated signal at Frf=5MHz
50 5MHz


0 5MHz-100Khz

M j k Hz+1KHz
-50
-6 -4 -2 0 2 4 6
Frequency Hz x 106
Rx demodulated signal centered at Fif=300KHz
50 3001KHz-1 00KHz

.50


-50 F' '
-6 -4 -2 0 2 4 6
Frequency Hz x 10



Figure 3-7. Frequency location of the calibration signal during the algorithm













































128









controller and the loop operation corresponding to the two cases are described below in

detail.

Case 1: Mobile Power change in the positive direction As explained in earlier sections,

when the mobile is requested to increase its transmitted power, the reference power

programmed will be greater than the actual feedback power. During the closed-loop

adaptation, this will result in a positive error signal. This positive error signal is then

accumulated by the adaptive filter and integrated by the first order integrator. The

accumulated signal is then used to perform gain control by either multiplying this loop

output to the digital gain stage or the controlling by the bias of the driver amplifier. By

accumulating positive error signal the loop response increase and hence increasing the

gain in the loop.

Case 2: Mobile Power change in the reverse direction- When the mobile is requested to

decrease its transmitted power, the reference power programmed will be lesser than the

actual feedback power. During the closed-loop adaptation, this will result in a negative

error signal. The negative error signal is then accumulated by the adaptive filter and

integrated by the first order integrator. The accumulated signal is then used to perform

gain control by either multiplying this loop output to the digital gain stage or the

controlling by the bias of the driver amplifier. By accumulating negative error signal the

loop response decreases and hence decreasing the gain in the loop.

As a second example, Figure 4-28 describes three consecutive gain adjustments

made by the mobile device to change the transmission signal power level. Figure 4-28

shows the analog bias signal increases the first two times to provide gain to the transmit

path. At the third power change request, the bias signal decreases as the base-station


165









4.3.2 Method II- Open Loop Tuning Based On Unknown Plant Transfer Function

In most of the cases, both the plant transfer function and the closed-loop transfer

function of the system are unknown. In such situations, one of the classical methods

adopted was to break the loop open and determine the step response of the open loop

plant. Figure 4-5 shows the step response of the open loop transfer function. From this

empirical result the slopeM, the time delay Td and k, the final value of the response is

calculated. This method was described by Zeigler Nicholas [76].

S0.9
Kp=
MTd (4-17a)
K, =3.33T,

and by using Cohen Coon's method [77]

Kp=1 0.9 + T
MTd 12r

T, (4-17b)

K, = 3.33Td. li
1+11T,
8r

Hence the proportional and the integral gains are calculated.

4.3.3 Method III Loop Tuning Based on Closed-loop Cycling

In certain situations, the loop cannot be broken for analysis and will be available as

a closed-loop black box where an input can be applied and the system response can be

obtained. In these cases, another closed-loop tuning loop tuning technique was

described by Zeigler and Nicholas [76]. The approach is defined as follows. Assume

that a closed-loop system is implemented using a PID controller.

Decrease the integral gains and the derivative gains.

Apply a suitable proportional gain


152









The baseband modem sends the information bits from the base band processor

into the digital path stages inside the RFIC. The digital stages have pulse shaping filters

to reduce inter-symbol interference (ISI) [23] and multi-rate filters to alter the sampling

frequency of the filters in accordance to the available clock rates and the DAC operating

rates.

As shown in Figure 2-6, assume that the base band I channel and Q channel

signals are represented by

(n)= dl* cos((obb)n) (2-1)

Q(n) dl sin((Obb)n) (2-2)

where dl is the digital gain, obb is the baseband signal frequency. The signals I(n) and

Q(n) are converted to analog signals I(t) and Q(t) by the DAC present in the transmit

path. The signals are then up converted by the RF modulator. The input to the

modulator is then up converted to RF frequency and can be expressed as

modout(t) = dl [(cos((bb )t) + j sin((bb )t + 0)]eJ" (2-3a)

where wrf is the up conversion frequency. The output of the modulator is amplified by

the PA and transmitted over the antenna. The signal transmitted over the antenna can

be represented as

PA(t) = G dl [(cos((bb)t + 0) + jsin((Cbb)t + 0)]eJ ft (2-3b)

where, G1 is the power amplifier gain. The magnitude of the power in dBm (dB with

respect to 1 mW) at the output of the PA is represented as

Pout(dBm) = 0log(Gldl[ j2'+Q2]) +30 dBm (2-4)









gain G,, is found to be 44.67 and the open loop delay is found to

beL = 18samples .Hence, the estimated system parameters are

* Steady state open loop gain, G,, = 44.67,

* Forward path delay, L = 18

* Feedback path delay, D = 10 (feedback path delay is known based on the digital
filters used).

* Programmed feedback gain 8 =0.5 (-6dB)

Substituting the values in the characteristic Equation zD+L+I -zD+L +,fSGKI results in

z29 Z28 + (0.5)(44.67)(KI) = 0 (4-23)

By employing the algorithm as illustrated in Figure. 4-9, the value of K, for

which Pax ,bs = magnitude(max p) < 1.0 is estimated. The value of KI max below which the

system becomes stable is found to be 0.0014 (-57.07dB). The 29 estimated poles

corresponding to K1 max as the controller gain are tabulated in Table 4-2. Figure 4-11

shows the plot of 29 poles which lie inside the unit circle. Figure 4-12 shows the,

reference and the feedback signal, the loop error signal and the closed-loop step

response with the predicted controller gains of K, < K1 max. Depending on the system

overshoot requirements, the integral gains can be further adjusted.

4.4 Closed-loop Delay and Loop Gain Margin Analysis

After estimating suitable controller gains K_, the effect of additional loop delay on the

stability of the closed-loop system is studied. The system architecture as described by

the DSP-GC algorithm can be simplified into a block diagram shown in Figure 4-13. The

reference signal R(z) is compared with the feedback signal A(z). The error signal E(z)


































Figure 3-12. DSP Hardware structure to estimate the absolute gain and phase change


Rx demodulated signal in 1-chanel


2 4 6 8 10 12
time in sec x 10.


Figure 3-13. Simulation plots to show that RxBB(t) with frequency of 400 KHz and
CiF = 300KHz over the 8 RF gain settings


132









Figure 4-24 shows a situation where the mobile device has been signaled to ramp

down the target power. Hence the reference signal has a ramp down profile from the

present reference value to a lower reference value. Since the feedback signal always

lags the reference signal, the error between the feedback signal and the reference

signal becomes negative and the closed-loop system tries to bring the error back to

zero at steady state. Since the error signal is averaged and accumulated the closed-

loop system provides an output which reduces the gain of the forward path and hence

reduces the output power of the mobile device. Based on simulations, it was found that

the loop takes 30-35usec to adapt for +/-7.5 dB of power change. Figure 4-25 shows the

antenna power as a function of the LMS adaptation. The plot shows that transmit power

ramp up and ramps down, the area under the error signal is minimized by the adaptive

filter on a sample by sample basis. The filter weights are cleared after the power

transition ends. Figure 4-26 show the loop dynamics of the feedback signal and the

closed-loop error signal as a function of the convergence factor. The goal of the

adaptive algorithm is to dynamically compensate for the analog gain changes

introduced on a sample by sample basis. The plot s5 in Figure 4-26 shows the

adaptation of the error signal as a function of convergence factor.

4.5.2 Lab Measurements of the DSP-GC Adaptive Algorithm

The measurement set up as explained in Chapter 2 is used to capture the output

of the controller on the Tektronix oscilloscope and the CMU2000 is used to capture the

RF power output of the mobile device. Figure 4-27 shows the analog output of the

closed-loop system captured by the Tektronix oscilloscope. The analog output is used

to control the bias of the PA or the VGA to perform gain control. Figure 4-27 shows that

the closed-loop system responds to two consecutive power change commands. The


164









changes in controller gains. As will be described in later sections, increase in loop delay

decreases the loop gain margin. However, sufficient gain margin can be maintained by

appropriately choosing the number of taps of the adaptive filter and the operating

sample rate of the closed-loop system. The components of the DSP-GC technique

hardware are

* N Tap adaptive filter [27]
* Integral controller with programmable loop gains KI
* Coefficients update block
* Multi-rate conversion logic.
* Signal multipliers.

The operation of the algorithm is described as follows. Assume that the reference

signal level is represented byDk = pwr*dk, where pwr is the signal magnitude of the

desired reference and dk is a unit step input. The error at every sample k is defined as

the difference between the desired signal level and the feedback signal level.

Ek = Dk- Ak, (4-8)

The output of the adaptive filter can be represented as

Sk = EkWk +Ek,W (4-9a)

where, EkTWk = Sk and Wk+, = W, +2/E2k, based on Least Mean Square (LMS)

Equations. Figure 4-2 shows a detailed schematic of the adaptive DSP hardware that

employs the LMS tracking technique. The error signal Ek feeds aN tap FIR filter, whose

taps are updated on a sample by sample basis. The number of taps are programmable

to N =2, 3, 4, 5, or 6 taps.

It is found that the modulation PAR of the feedback signal was as high as 7.2dB

when higher order modulation schemes such as WCDMA, CDMA and OFDM was used.











Block of Baseband signal envelope


I





B.fl5 ., ... ... .... .... -... .... ......



20 40 60 80
sample E


Figure 2-35. Signal buffer of baseband signal envelope


150 200 250 300 350 400 450
sample #


Delay to be predicted


Figure 2-36. Detected Signal at the output of the ADC at the signal sample rate (no
downsampling)


jock 01 DllIECIed Slgna310 ne corelaled









this, as was explained analytically in Chapter 2, depending on the amount of power

change, the controller gains are adjusted to maintain similar loop stability and gain

margin over the entire range of closed-loop operation.

Based on simulations and lab measurements it has been found that the loop gain

margin decreases with increasing loop delay. Figure 4-22 shows the range of values for

integral gain allowed for particular target power decreases as the loop delay increases.

It is clear from Figure 4-22 that the gain margin is around 20 dB when the feedback loop

delay 200nsec and the gain margin decreased to around 14dB when the loop delay

increases to 1.92usec. In this application the introduction of adaptive filter adds 4

samples of delay into the system. However this additional delay is tolerated based on

the fact that faster settling time is obtained when the adaptive filter is used.

4.5 System Simulation and Lab Measurement Results

System simulations were performed for the implemented DSP-GC technique with the

system models including

* RF analog circuitry
* Analog feedback path
* Additive noise
* Digital transmit path models
* Digital implementation of the system architecture.

Sections 4.5.1 and 4.5.2 describe the system simulations and lab measurement results

obtained by implementing the DSP-DGT algorithm.

4.5.1 System Simulations of the DSP-GC Method

The system simulations were performed with simulation tools Matlab and SPW.

The simulation models assumes that the modulation format was either constant

envelope such as Gaussian minimum shift keying (GMSK) or non-constant envelope


162








device bias characteristics [5], [10-13], [40]. The coefficient a, is known as the small

signal gain. For very small input signal levels, S, the coefficient a, dominates and the

higher order terms are negligible. Assume the signal S, = S, cos t is the input to a non-

linear system. The output of the non-linear system is defined by

So(i) = alS (Cos(lt) + a2S2 (Cos2 lt) + a3S3 (Cos3 lt) +........ (3-2)

The second term a2,S,(cos2 cot) is expanded as

a2S1 (cos2 t) = a2S12 [cos(O1, + )l)t +cos(o1 -O> )t]
(23-3)
= a,2S 1[1+cos2ilt] (3-3)

The cubic term a3,S,(cos3 at) is expanded as

a3S3 (cos3 ot) = a3S13 ([cos2 wtcos it])

= a3S, -cosm t + -[(cos39 t) + cost

( -o3 1 3-4
=a3S3 -cost +-cos3m>t (3-4)
(4 4
The first term in the Equation 3-4 is the fundamental and the second term is the third
harmonic term which was generated by the device nonlinearity. This component

appears at the output of the device at three times the input frequency. To analyze the
sum total distortions caused in a transceiver it is also essential to better understand the

5th order term as they determine the out of band spectrum emission requirements. More

specifically, this is responsible for the spectrum leakage at alternate channels (2


102










clk
data


Symbols RF
from Tx uDAc Modulator
Modem DigitalVG PA10 1
1010101100 line up AC RF
Pout (dBm)
Base Band Pout (dBm)
Filter

Figure 1-10. Prior art that uses fixed digital gain offsets and errors to perform digital
gain control


clk
data


Symbols
from


RF
Pout (dBm)


Base Band
Filter


Figure 1-11. Prior art that adopts
tracking


pre-calibrated analog bias levels for gain control and









TABLE OF CONTENTS
page

ACKNOW LEDGM ENTS............ ..... ........................... .................... ... ....

LIST OF TABLES .......................................................... 8

LIST OF FIGURES ............... ..... ........................ .............. .............9

LIST OF ABBREVIATIONS .......... .... .............................................. 15

A B ST R A C T ................. ................................... ........................... 16

CHAPTER

1 INTRODUCTION ............. ...... ......... ...... ........ ...... ............. 18

1.1 Motivation: Need for Power Control and Gain Tracking Inside Mobile
Device .................. .... .............. .... .......... .................. 18
1.2 Power Control Techniques in Mobile Devices ....... ... ........... ...... ........... 22
1.3 Present Day Techniques and Prior Art ................................. .... .............. ....23
1.3.1 Use of Fixed Calibrated Digital Gain Offset and Error Values ............23
1.3.2 Use of Pre-Calibrated Analog Bias Signal for Constant Envelope
M odulation..................... ................... .......................... 24
1.3.3 Use of RF Feedback and Analog Bias Control........ .............................24
1.3.4 Use of RF Feedback and Temperature Compensation Circuit
B asked G a in C ontro l .................................................. .... ......... ... .. 25
1.4 Lim stations of Prior A rt .......... ......................................... .. .... 25
1.5 Research Effort Comparisons ................ .............................. 26
1.6 Organization of Thesis .......... ................................... .. ..... ........ 26

2 DIGITAL DSP TECHNIQUES AND EFFICIENT HARDWARE TOPOLOGIES
FOR ABSOLUTE GAIN TRACKING........ ........................................... 37

2.1 Problem Statem ent ................ .... ......... .. ................ .. 37
2.2 Reasons for Signal Gain Variations in Mobile Devices................. ....... 38
2.2.1 Gain variations due to Manufacturing Processes..................................38
2.2.2 Power Gain Variations due to Change in Junction Temperature ......... 39
2.2.3 Change in Power Gain Due to Different Operating Paths Depending
on P ow er Level ............. ............... .............................. .................. 39
2.2.4 Variation in Gain Due to Different Operating Frequencies and
Supply Voltage .................... .......................... ..................40
2.3 DSP Based Dynamic Gain Tracking Algorithm (DSP-DGT).......................... 40
2.3.1 System Architecture of the DSP-DGT Algorithm.............. .......... 40
2.3.2 Feedback Path .......... ..................................... ................ 41
2.3.3 Forward Reference Path .............................. ........... ................ 42
2.4 A lgorithm T heory................. .... ................... .......................................... .. 42
2.5 DSP Hardware Structures for the DSP-DGT Algorithm ......................... 47









CHAPTER 5
CONCLUSIONS, APPLICATIONS & SCOPE FOR FUTURE DIRECTIONS

5.1 Thesis Summary

The research work describes techniques to control and compensate for absolute

and relative gain variations caused in mobile devices due to imperfections in RF and

analog circuits. It also clarifies the difference between the power control techniques

employed at the base-station and in mobile devices. Real time analyses with ongoing

cellular projects are used to describe the various steps involved in any mobile-based

gain control. Past, present and recent methods of power controls are described in

Chapter 1. A clear distinction of the functions of RFIC, base band processor and the

base-station has been made and described in detail.

Chapter 2 describes a novel DSP technique to track for absolute gain variations in

any mobile device caused by the performance degradation of analog and RF circuits as

a function of operating voltages, temperature and frequency bands. This DSP-DGT

technique employs a digital PID controller and a signal correlation circuit to track for

gain variations in the transmit signal path of a mobile device. The digital technique has

been found to use only 22K gates and the current drain is 20mA. Since this technique

is a complete digital implementation, it reduces bulky analog circuitry and complex

power amplifier bias circuitry requirements. System simulations and lab measurements

prove that the DSP-DGT algorithm compensates for absolute gain variations better than

0.1 dB accuracy independent of modulation schemes adopted.

Chapter 3 outlines a method to compensate for the relative gain and phase errors

to maintain power control accuracy requirements. The DSP-GPE technique uses DSP

circuits to estimate the relative gain error of the analog RF gain amplifier and provides









DNL gain error compensation. In addition, this technique is used to calibrate the carrier

phase changes that happen in any mobile device due to change in the capacitive load

impedances on the RF analog path. System lab measurements and simulations prove

that the implemented DSP-GPE algorithm estimates and compensates for gain errors

better than 0.1 dB accuracy and phase errors better than 1 degree accuracy. The digital

technique uses less than 10K gates and the current drain is 12mA

Chapter 4 presents the DSP-GC technique and corresponding hardware structures

to dynamically control the absolute signal power of a mobile device by using an

adaptive filter along with an integral controller. The DSP-GC technique makes the

closed-loop system robust to higher signal variances. In addition to reducing the gate

area, the DSP-GC algorithm also employs a novel control loop tuning technique based

on stability constraints. This technique is used as a systematic method to estimate the

controller gains of a closed-loop system with an unknown Nth order plant transfer

function. System stability of the implemented architecture as a function of variations in

loop delays is analyzed. System simulations and lab measurements show that the DSP-

GC technique can perform gain changes upto 90 dB dynamic range with a resolution of

0.1 dB accuracy. The convergence time of the loop is reduced to 35usec from 50usec.

The DSP-GC digital technique uses only 17K gates and the current drain is 22mA.

Table 5-1, Table 5-2 and Table 5-3 differentiates between the industrial and

academic focus involved in the DSP-DGT, DSP-GPE and the DSP-GC techniques

respectively.


188



































Figure 1-1. Power control signaling from base-station to mobile device



Signal energy
at the base-station
Without power control
in a 11 user cell


Frequency ( MHz)
Figure 1-2. Occupancy of mobile users in frequency domain without power control































S6 11 16 21 2
aget P (EdB;)

I I
0_3(,--I ------- r--,------- I I --------b,---2F-.-- ---2b--- 9----i
-3 ---- ---- --- 4--4------1 --2 ---1 ---t -u --2 --20 -2 ---2 --26----
-- -- ------ --- -- -- ----- --- ---- --- ---------

2 --------- ---------- ---------- ------------ -- ------- ----
S4 6 a p --err _gain indelay_200nse
a -a-1err aain Lax delay 208ne
421 -- ------- -------- 1--- ----- --------- -

= :::::| :::::::::: ^ : .:: :: : :: : : ::::::: : :
S-24 -i -- ----- -- t -\ -- ---- ---- .. ---- -- .- -- ---
27 ---- -- ---- ,--II--- ---


S-30 ---- ------- ---- L I -- ^- -- --. --- T" ^ ---- ------L----I .- .
-4a --- --- ------ --- --- ^- -- ---- -- T- ---. -- --- -- -- --------- r 4-- -- -- --
*' -30 -. ll .-.. .. ..... ....l.....1 .....
.54 ----------- ----------- -- -- --^ ---------


-5 ---- ----- -- ---------- -
-66. ------------------- ---------- -. .
-------- ------
-72. ---- -----'-----L J------------- ------- --- ---- L-- .


-42 -- -~-------- ------- -----------------------------
S 2------------



-60 -- '------ ------------ -: --- ----i------- L- -----~-- L--

-7
Antenna Powe.{dB m



Figure 4-21. Power detector and feedback path input-output characteristics.


























178


-"-1 --l ..-. -l- ----l -.. --l .-. -- -- [---- -- .-- --- .-- -- -- -

-- ----- ---- ---- --- -- ---- --- -- -- --- --
--i-------------i--- -------- ----------
-T---- ----- -I -- T- -- -- T 7- i----- ---- 7
S- -- -- .-- --- I -- --2 -- -J --- -



:] : : : : : :! : : : ::: : :: : : : :: : : :: i:; :: ] : : : :: ::
- -- ,


--- -- --- ---- -- --- ---- -,
'^ ^ --^- -- -ll l. .l -- l 7l --.- -. ---- .


I













avg_enable


controller clks







Forward path magnitude


Undesired gain change due to PA/VGA/
Y~(t) baseband


Feedback path signal magnitude

Error signal into the controller

Controller error signal
E(t)


Controller corrections
Until the error reaches zero
-4- ^r


C-


Error Signal


The PA output reaches
back to desired level





"eaches back to zero
N


Controller output
Y(t)


Figure 2-9. Closed-loop dynamics when the controller compensates for undesired positive gain change


LILR- LLLR___
















































2 (B3B3)


Figure 2-32. Digital implementation of 12 taps cross-correlation DSP hardware









Y(z) = E(z)K-Gz1z L (4-19a)


where the error signal E(z) and the feedback signal A(z) is represented as
E(z) = R(z)- A(z) (4-19b)

A(z)= Y(z),z (4-19c)

Combining Equation 4-19b, 4-19c results in

E(z)= R(z) z-DY(z) (4-19d)

Using equations, 4-19a, 4-19d, the closed-loop system output Y(z) is represented as

Y(z)= [R(z)-A(z)] K(Z- 'G
K(1- zl 1

Y(z) = R(z) Y(pz)z-D] K1-L-Gss

Y(z)-z-'Y(z)= [R(z)GK,z-L ]-Y[(z)Y GKz-D-L-1]

Y(z)[l- z + pGK,,z D L 1]= R(z)GsKzL1

Y(z) G,,Kz--1 (4-19e)
= H(z) =
R(z) [1- z' + PG,1KjzDL-]

In order to represent 4-19e in powers of z, we multiply the numerator and denominator

Fz(D+L+1)
by [(D+L]. This result in
z(D+L+1)

Y(z) G= [z ,KI z -L-] (D+L+1)
Y(z) Fz(DL=2
R(z) [1- z 1 +SGKIz -D-L-1 Z(D+L+1)
(4-20)
G,,K1zD
[zD+L+l ZD+L + PGPKI

Based on the z domain closed-loop stability constraint, the system H(z) as described

by Equation 4-20 is stable if the poles of the transfer function lie within the unity circle.


155









The transfer function reveals that the system has no zeros and clearly shows that it is a

low pass filter. The value of the filter factor decides the settling time of the filter and also

the amount of noise reduction. The smaller the value of a, the more noise reduction is

obtained. However, with smaller values of a, the average responds slower. Hence the

trade-off of this structure is that the more noise reduction we need, the more sluggish

the average will respond. The following plot describes the settling time of the average

to a random varying input signal whose mean is 0.195. The signal-noise (SNR)

performance of the average as a function of the filter factor a, can be described as [73]

Filter Ouput noise Variance a
S= SNR = (2-17)
Filter Ouput noise Variance 2- a

Due to the above mentioned trade-offs between settling time and SNR, a more

appropriate method of varying the filter factor has been described as follows. A

relatively large filter factor is used at the beginning of the measurement so that the

average immediately responds to the filter's input and then the filter factor is reduced

slowly to improve noise performance of the average. The filter factor can be reset to

zero at the end of every signal transmission. This is illustrated in Figure 2-26 for a

random input signal with mean of 0.195. Figure 2-26 illustrates the use of the varying

filter factor in the exponential average. A higher filter factor is used at the start of

measurement, and the value is decreased as the measurement proceeds. This results

in faster average response time at the start of the measurement and as the

measurement proceeds the average is slowed down by using a lower filter factor for

better noise reduction. The frequency response of the single stage average is

illustrated in Figure 2-27. The bandwidth of the average reduces as the filter factor
















A-LrFLiFnU I


Tx Signal 1 ) + k I



k Calibration Delay_cal_en
Gain(K)



Signal
Average
Magnitude Feedback signal Power aC
Estimation Pow
Estimation



Signal
Buffering
& Sample rate
adjust




S Delaycalen













Figure 2-7. Controller adopted for the closed-loop DSP-DGT algorithm


Simplified Plant


Feedback gain

Aliasing A
Filter


Signal
Average
Power
Estimation


System
Output









In practice an amplifier used in transceivers will operate either in the linear region or

within the 1dB compression point. Hence, Taylor series can be used for our analysis.

Since the total output signal power is a function of power of the independent harmonics,

it is important to understand the distortion metrics analytically, and it's nonlinear effects

on the desired signal power. Considering the second power term, the harmonic

distortion (HD2) can be defined as

HD2 Amplitude of second harmonic (3-6)
HD = (3-6)
Amplitude of the fundamental

From expression Equation 3-4 we can calculate

1/2 aS2 2a
HD2 I
aS, 2a1 )

Hence, it is obvious that HD2 is proportional to the input signal level. HD2 is an

important factor in distortion analysis because it generates DC components which will

degrade the signal quality unless eliminated.

Considering the third power term, the harmonic distortion component is described as

Amplitude of third harmonic
3U =- (3-7)
Amplitude of the fundamental

From expression (3-5) we can calculate

a3S13
HD=3 4 1 a312 (3-8)
aiS, 4 a )

The expression clearly shows that HD3 is proportional to square of the input signal.

Considering the 5th order term, the harmonic distortion due to the 5th order term is

defined as


104

















0
G1 G2 G3 G4 G5 G6 G7 G8 G9 G1G11G 5 G16
-10 -' -

20
S-*- low chG2g(1-16)_cold
S -30 ----------- mid_chG1g(1-16)_cold
; ---highchG3g(1-16)_cold
't -40
Sf'mid_chG1g(1-16)_room
-50 ---------- mid_chG1g(1-16)_room
S-*- high_chG3g(1-16)_room
-60 ---- mi-h 1 g1 6)ro
-- mid_chG1g(1-16)_hot
-70 ---- mid_chG1g(1-16)_hot
high_chG3g(1-16)_hot
-80

Amplifier Gain Steps

Figure 3-2. Measured amplifier bias vs. output characteristics with respect to
temperature and frequency bands of operation






0.2
--Imid_ch-mid_chl
0.15
015 -- |Imid_ch-lowch|

0.1 -- -a--|mid_ch-high_chl
Imid_ch-midchl
m 0.05
0.0 )- I|mid_ch-low_ch|

0 --|Imid_ch-high_ch|
z1 5 7 9 11 1114 mid_ch-mid_chl
---midch-mowichl
-0.1 Imid_ch-high_ch

-0.15 --max spec
I ---min spec
-0.2
Amplifier Gain Steps


Figure 3-3. Measured DNLE (dB) with respect to change is frequency bands of
operation


124









[43] Xian bin Wang, T.T.Tjhung, "Reduction of Peak-to- Average Power Ratio of
OFDM System Using a Companding Technique, IEEE Trans. on Broadcasting,
vol.45, pp 303-307, Sep. 1999.

[44] Jeroen R.Willemsen, Andre C.Linnenbank, Mark Poste, Cornelis A.Grimbergen,
"Signal Averaging of Non-Stantionary Noise, in Proc, of the First Joint
BMES/EMBS Conf, Serving Humanity, Advancing Technology, Oct. 1999.

[45] Harald Pretl, Linus Maurer, Werner Schelmbauer, Robert Weigel, Bernd
Adler,Josef Fenk, "Linearity Considerations of W-CDMA Front-Ends For UMTS,"
IEEE MTT-S Int Microwave Symp. Dig, 2000,vol. 1, pp 433-436.

[46] Abdellatif Bellaouar, "RF Transmitter Architectures for Integrated Wireless
Tranceivers, Int Conf., on Microelectronics, 1999,pp. 25-30.

[47] Allen Katz, "Linearization: Reducing Distortion in Power Amplifiers, IEEE
Microwave Magazine, 2001, vol. 2, pp. 37-49

[48] Sanggee Kang, Heonjin Hong, Hyungsoo Lee, Sungyong Hong, "The
characteristics of a Transmitter's ACLR for WCDMA." IEEE MTT-S Int
Proceedings of Microwave and Optoelectronics Conf, 2001, vol. 1, pp 43-45.

[49] Chunmig Liu, Heng Xiao, Qiang Wu, Fu Li, "Spectrum Design Of RF Amplifier for
Wireless Communication Systems, IEEE Trans. on Consumer Electronics, vol.
48, Feb. 2002.

[50] Cecil W. Thomas, Mark S. Rzeszotarski, Barry S. Isentein, "Signal Averaging by
Parallel Digital Filters, IEEE Trans. on Acoustics, Speech Processing, vol. 30,
Apr. 1982.

[51] Aristotele Hadjicristos, "Transmit Architectures and Power Control schemes For
Low Cost Highly Integrated Transceivers for GSM/EDGE Apps, IEEE 0-7803-
7761-3, 2003.

[52] Jeonghyeon Cha, Youngoo Yang, Bumjae Shin, Bumman Kim, "An adaptive Bias
Controlled Power Amplifier with a load modulated Combining Scheme for High
Efficiency and Linearity, IEEE MTT-S Int Microwave Symp. Dig, 2003, vol. 1,
pp.81-84.

[53] Yoshifumi Toda, "Adjustable Transmitter Power Control Circuit, U.S.Patent
5603,106, February, 1997.

[54] Adrian Jarrett, "Amplifier Gain Control Circuit Arrangements," U.S.Patent
4,849,712, July 18, 1989.

[55] Atusushi Miyake, "Automatic Power Controlling Transmitting Power of Modulated
Radio Frequency Signal,"U.S. Patent 5,408,197, April 18, 1995.


193









mobile system is able to compensate better than 0.1 dB absolute and relative power

level accuracy and also result in phase estimation accuracy better than 1 degree.









[83] Tektronix TDS3034B 300 MHz Digital Oscilloscope User Manual.
Author: Tektronix Incorporated.
[updated 04 April 2005]. Available from
http://www.tequipment.net/pdf/tektronix/TDS3000B_UserManual.pdf


196









1
p(n) [e(n)*Kp]+ n)n)*K, ( z-) + [e(n) *KD 1 Z-)] (2-20)


The PID controller is implemented with three adders and two flip flops clocked at

the desired sample rate. To avoid the use of multipliers, the integral, derivative and the

proportional gain stages are implemented by shift add depending on the required gain

values. The DSP hardware segment for the gain blocks are shown in the Table 2-2 and

Figure 2-31. The integral, proportional and derivative gains for the PID controller are

implemented based on shift and add logic [24]. For a gain of -6dB, the signal is shifted

right by a factor of 2 and for a gain of -8.53dB, the signal is separately shifted right by 4

and shifted right by 8 and then added together to get -8.53dB. Depending on the 4 bit

signal gain_cont<4>, the required gain values are selected and applied to the input

signal. The values of the shift and the combination of the additions can be changed to

get different desired gain values.

2.5.6 Cross-Correlator Hardware

Before the gain tracking algorithm is enabled, it is essential to calibrate the delays

between the forward and the feedback path. Calibration of the delay will help in aligning

the feedback and the reference path signals. In addition it will help to preserve loop

stability and enhance the settling time of the algorithm. As a first step, a calibration

signal is fed into the digital path and the cross-correlation between the outputs of the

forward path signals and the feedback path signals due to the calibration signal is

estimated. The time of occurrence of the maximum correlation estimate is dynamically

found by the time-delay counter and based on the time index estimate the delay is

calculated with the knowledge of the operating sample rate. This calculated delay is

then applied to the reference path delay buffer as shown in the Figure 2-7. If x(n) is the









adders and hence reduces digital gate area. The DSP hardware designed for this

purpose consists of the following four individual blocks.

Absolute value estimation. The hardware to calculate the absolute value is

implemented as described below. Assume that the signal x(n) is a 14-bit signed number

represented as <14, 0, t> (14 bits, 0 integers and 1 sign bit). The digital hardware takes

in the signed number and if the sign bit is set, then number is inverted and incremented

by 1.0, else the same signed number is sent at the output.

Bitwise compare. The DSP hardware for bitwise compare is described in Figure

2-19. The input signal which has to be compared is subtracted and the most significant

bit (MSB) is extracted and used to control a multiplexer. If the MSB is set to 1, then the

output of the multiplexer is abs(I)which the maximum of the two numbers is, else if the

MSB is zero, then the multiplexer outputs abs(Q).

Multiplication and Division By a And /. The multiplication by factors are

implemented by shift right or shift left logic. In our case, the values for a and /, we

61_ 12 61 12
selected are a =-6 and = 12. The multiplication by a = and p = 12 can be
64 32 64 32

realized by representing 61 as

61 (60+1) (5*2*2*3) (4*(4 + 1)*(2 + 1)) and
64 64 64 64

12 (4 3) (4 (2 + 1))
32 32 32

Multiplication by 4 is implemented by shifting the input signal left by 2, and multiplication

by (4+1) can be implemented by again shifting the input signal left by 2 and adding the

signal to it as shown in the Figure 2-20. Division of a number by 64 and 32 is realized by














Stability Analysis of H(z) for loop delay D = 13, 17, 19 and 21 samples at Fs


S =13



x
SX X

: x -



X .-
-K



-1 -0.5 0 0.5 1
Real Part








-x
... : ..=19.






ooX X :-"
',x x x '.-'



-1 -0.5 0 0.5 1
Real Part


1


0.5
IC
a-
. 0
E
- -0.5


-1





1


0.5


00

E
-0.5


-1


D=17

Sx x -

:x


at
x x




-1 -0.5 0 0.5 1
Real Part



,"K!X0 K,. D=21

/x x
KX K
x : x
.x W
Kx x:
aX Xa."
"' X : X X.."



-1 -0.5 0 0.5 1
Real Part


Figure 4-15. Pole-zero location with loop delay, D = 13, 17, 19 and 21 samples at

sample rate Fs.






Stability Analysis of H(z) for loop delay D = 24,26,28,31 samples at Fs


'X -. x D=24
."X X''



-1.
0.5 -. -.

KX
o ..... N ........... x
-0.5 "x e X.
'.x x,

1 D= 2 ___ ****:* *** _____
-1
-1 -0.5 0 0.5 1
Real Part


K..x' x .. D= 28


0.5 X.
.x
o .... ,x ........... ............. .
-x

-0.5 -,x K,"

Xr ,x,xx x ,,'

-1 -0.5 0 0.5 1
Real Part


i'X X" .x D=26
z" X X-,
X x;
-x K'
-X *

x x:
.x K.



-1 -0.5 0 0.5 1
Real Part



D=31


XX x
-x x.


x 3 x

; x x' '
S.x .' -


-1 -0.5 0 0.5 1
Real Part


Figure 4-16. Pole-zero location with loop delay, D = 24, 26, 28 and 31 samples at

sample rate Fs.





175


0.5

c 0

E



-1


-0.5

-1



S0.5




E
- -0.5


-1









channels away) due to a mobile user in a particular channel. The pentic term

aS,5 (cos5 cot) can be expressed as

a SS5(cos5 ot) =(cos2 Cot)(cos3 Cot)

= a5sSl5 r- cos tf + (cos3y t) [1 + cos2mYcl't]


The output So(,l) is represented by

So(n,) = aOS l (cos /t) + a2S12 (cos2 Ct) + a3S1 (coS3 Co) +........


a=a,S(cos0mt )+a2,S2 [1 + cos2oalt] +a 3 S3 -cos 't +- (cos3wot) +... (3-5)
24 4 4

From the above analysis we observe the following

* The term alSl(cosclt) is the desired term with the amplified /attenuated gain.

* The higher-order harmonics generate distortions and the coefficients are
independent of the input signal.

* The second-order terms produces DC shift and hence an undesired DC value is
added to the input signal. It is obvious from this observation that the even order
terms generate a DC component.

* The third power [3] produces the fundamental term 1i and the third harmonic
term, 31i. The phase of the ci is most important because it can produce a signal
totally out of phase of the input desired signal and can cause undesired
amplitude change of the output signal. Depending on the phase of this term it can
generate either gain compression or gain expansion of the output signal.

* Taylor series expansion of an odd function f(-s)= f(s) only has odd
components, while an expansion of even functions f(s) = f(s) generates DC
components.

* The rate at which the first harmonic grows is slower than the second and the third
harmonic.


103










LIST OF ABBREVIATIONS

ADC Analog to Digital Converter

BPSK Binary Phase Shift Keying

DSP Digital Signal Processing

DNL Differential Nonlinearity

DAC Digital to Analog Converter

DC Direct Current

EDGE Enhanced Data rates for GSM Evolution

GSM Global Systems for Mobile Communications

I In-phase

INL Integral Nonlinearity

LMS Least Mean Square

OFDM Orthogonal Frequency Division Multiplexing

PID Proportional, Integral and Derivative Controller

Q Quadrature Phase

QAM Quadrature Amplitude Modulation

QPSK Quadrature Phase Shift Keying

RF Radio Frequency

RFIC Radio Frequency Integrated Circuit

SNR Signal to Noise Ratio

SIR Signal to Interference Ratio

VCO Voltage controlled oscillator

VGA Variable Gain Amplifier

Wi-MAX Worldwide Interoperability for Microwave Access

WCDMA Wideband Code Division Multiple Access













Instantaneous error ( linear) vs Input signal swings as a function
of a and b


1.05

1.03

1.01

0.99

S0.97

0.95

0.93
-W- a=61/64,b=12/32 ---ideal magnitude
0.91 -A- a=15/16,b=15/32 --- a=122/128,b=31/32
-- a=31/32,b=12/32
0.89
0 1 2 3 4 5 6 7 8 9 10
sample points




Figure 2-17. Instantaneous error (linear) vs. input signal swing function as a function
of a and p factors








Bit Extract
MSB


_0 <14,0,u>
I abs(I)
<14,0,t> '




1.0 I



Figure 2-18. Simple absolute value estimator logic









control signal that compensates for the gain differences between the reference path and

the feedback path. A cross-correlation circuit is used to time align the reference and the

feedback path before the start of the controller operation. The introduced technique not

only helps to compensate for gain variations but also helps in shaping the power

change in a spectrum friendly way and avoids adjacent channel interference.

The system block diagram of the DSP-DGT algorithm is shown in Figure 2-6. The

digital IQ samples pass through the digital filtering stage and get converted to an analog

signal by the DAC. The differential DAC output goes to the baseband reconstruction

filters. The baseband filter outputs are converted to RF/IF frequencies depending on the

applications (Cellular, Wireless local are network (WLANS) or Audio signal paths) and

passes through an RF gain amplifier stage and transmitted through a power amplifier.

There are two signal paths for the introduced system architecture, namely the feedback

path and the feed forward path.

2.3.2 Feedback Path

The output of the RF amplifier is fedback into a power detector [45],[56],[70] which

takes in RF Power (dBm) and gives out corresponding DC voltage. The detector output

is fedback into a variable gain block with an anti-aliasing filter. The output of the filter is

quantized into digital word by an analog-digital converter (ADC). The variable feedback

gain is chosen and implemented based on the input signal dynamic range of the ADC.

Varying the feedback gain as a function of the RF power levels improves the signal-to

noise ratio of the feedback signal. The quantized digital word is then buffered and

averaged by employing a digital fast averaging circuit as will be described in section

2.5.4.









3.6 DSP Hardware Structures for Relative Gain/Phase Estimation and
Compensation

Most of the basic hardware employed in Chapter 2 can be adopted for this

algorithm. In addition, this section describes two DSP hardware structures adopted for

relative gain and phase estimation and compensation. The following section describes

the equations and the DSP implementation of the phase compensation circuit and the

gain estimation digital circuit.

3.6.1 Phase Compensation DSP Structure

Based on descriptions in earlier sections, it is understood that the relative phase

shifts estimated can be used as baseband compensation factors to correct the unknown

phase shifts introduced in a mobile system.

I(t) comp = I(t) cos(o err) Q(t) sin(q err) (3-39)


Q(t) comp = Q(t) cos(o err) + I(t) sin(o err) (3-40)

The cosine and sine of an angle are implemented with an 8X8 ROM. This has 8 bits

each and 256 entries. Prior knowledge of the maximum amount of phase compensation

that a system application will need helps in limiting the size of the ROM. For our

application, the maximum amount of phase shift required is +/-25 degrees. Adopting an

8 bit input ROM will result in accuracy of 25/256 =0.09765 degrees. Hence, 8 bit

registers will give us an output accuracy of 1/256 = 0.0039625 degrees.

3.6.2 DFT Based Gain Estimation Structure

The DFT of a signal x(n) is represented as

2;27
X(k) = x(n)(e "N)", where k = 0, 1, 2, ... N-1 (3-41a)
where, the frequency of interest is located in the kth bin.


116









F,,o = 146.51KHz will be the final baseband frequency at the receiver. The DFT index

Corresponding to this frequency is calculated by

K= toe N
F,


K =146.51KHz 512 15
S5MHz )

This DSP hardware in Figure 3-12 calculates the real and complex DFT for a real signal

stream. In our algorithm this DSP hardware is present in both I channel and the Q

channel. For our application, the I channel is employed and the output of the filter has a

real part and an imaginary part. The absolute value is then estimated to result in

I _DFT and Q _DFT

3.7 System Simulations and Lab Measurement Results

The system architecture was modeled in tools such as Matlab and Signal

Processing work station (SPW). System simulations were performed with the following

parameters. Figure 3-13 shows the time domain waveforms of demodulated I channel

at the receiver. The simulation frequencies used are oiF = 300KHz, ,BB = 100KHz,

- = 5MHz and c = 5MHz+300KHz. Hence the demodulated baseband signal

frequency is 400 KHz. Each stage results in a RF gain and a phase change (Gkek),

where k= 1,2 ...8. Figure 3-13 shows plots for k=1,2..4. Figure 3-14 shows system

simulation performed with oiF = 300KHz, OBB = 100KHz and by stepping the eight stages

of the RF gain amplifier. Each stage results in a RF gain and a phase change of

(Gke k), where k = 1, 2 ...8. Figure 3-15 shows measured DFT magnitude for

I channel signal. The measurement shows that the peak of the magnitude appears at


119









to provide gain control depending on the adopted transmit path architecture. In other

applications, the digital controller output is used to alter the digital gain of the transmit

signal path. Figure 2-54 shows the measured output of the mobile device (using FSIQ

testing equipment) whose RF power changes from a lower power level to 22dBm

employing the DSP-DGT algorithm. It is clear from Figure 2-54 that the rate of change

of signal power ramp is determined by the controller gains used. Depending on the

application and based on the peak overshoot and steady state error requirements, the

controller gains are selected. In addition of dynamic absolute gain tracking this circuit

can also be used to perform a power change as will be described in Chapter 4.

2.7 Summary

1. The DSP-DGT technique provides gain monitoring and compensation of absolute
power variations in mobile devices due to imperfections introduced due to analog
and RF circuits inside a mobile device.

2. System simulations and lab measurements show that the algorithm is provides
gain control better than 0.1 dB accuracy

3. Approximate gate count of the implementation is within the allotted 22K.

4. The described approach does not require separate reference generation circuitry
as the base band signals are used as self reference.

5. The implemented algorithm is found to be independent of modulation schemes
employed.

6. This technique however does not compensate for relative gain and phase error
introduced by RF circuits which will be dealt in Chapter 3














Average estimate vs time in sec


0.05 l 00usec desired buffer length

1 2 3 4 5 6 7 8 9 10
time in sec x 10-

feedback filter factor

I I- data
D.08 higher filter factor is desired for faster tracking
filter factor reduced to lower values to have less noise
S0.06 performance

D 0.04

0.02


0 1 2 3 4 5 6 7 8 9 10
time in sec x 10



Figure 2-26. Dynamic varying filter factor depending for noise and response time trade

offs.









Magnitude response of the Fast average


a=0.25
-25 0.1
a=0.05
a=0.01
S-10 :


-15 "


-20


-25


S-30


-35


S-40


-45
2 4 6 8 10 12 14
frequency Hz x 10



Figure 2-27. Magnitude response of the average














Ki= -35.91 dB
1 ..*",, ,-_ ,
II
X X'












KI= -29.9dB



-1
- X










x x ,-





-1 -0.5 0 0.5 1
Real Part
Real Part


D=13


ki= -31.7 dB



x : x-


X
Sx -

x : x


-1 -0.5 0 0.5 1
Real Part

Id = -26.93 dB





x
X
x x


X
",, .. x x x,,.'"


-1 -0.5 0 0.5 1
Real Part


Figure 4-19. Pole-zero location with loop delay, D =13 samples and integral gains of -

36 dB, -32dB, -30dB and -26dB.


Ki = -21.93 dB


Ki = =20 dB


x x




X X"

",,, x x "
''",xr. x


-1 -0.5 0 0.5 1
Real Part
ki = -8dB




... ..





.. .. .



-1 -0.5 0 0.5 1
Real Part


D= 13
1


0.5



E
.-0.5


-1












E -0.5



-1


X X '




x




-1 -0.5 0 0.5 1
Real Part
ki = 9.5dB





X" : X
.. z .. .


Figure 4-20. Pole-zero location with loop delay, D =13 samples and integral gains of -

22 dB, -20dB, -6dB and 9dB.









177


-1 -0.5 0 0.5
Real Part


-0.5


t1 u.,J

a 0
0
E
- -0.5


-1


K.


~ ." X
*x .|,,-x


1 1.5












Calibration
Signal generator


-LrLJnr-n-= f ZLRFLJIL
Gain control
Symbols from
Modem n bit I
1010010101 Tx
l Digital








Magnitude
estimator Dynamic
Gain adjust
Mag(IQ)=ID2+ signal
Buffer controlcor


and sample Gain pr,
rate adjust controller









DelaycalDelay_cal_en










Figure 2-6. System level block diagram of the DSP-DGT architecture
Figure 2-6. System level block diagram of the DSP-DGT architecture













Downsampled
Input data to be 0 data, sample
dowsampled _rate = Fs/N
(Input sample s
rate = Fs) 1 -



enable Control signal


sET Q -Clk2=Fs/N
R c Q N 0 Modulo N
counter output



Clkl=Fs


Downsampled clock
Clkl=Fs

v v-hen count =0, an enable is generated




Downsampled cloc
Clk2=Fs/N


Figure 2-15. DSP implementation of sample rate logic









Inphase and Quadrature phase signal swings




0.8 -
0.6





I -0.2 2-\3 4 5- 6 /- 8 9
-0.4

-0.6 -
-0.8
-1

Time index




Figure 2-16. In-phase and quadrature phase signal swings whose magnitude has to be
estimated.









whose frequency cOBB is 100 KHz. The black plot in Figure 3-7 shows the complex

baseband signal g(t) up converted to RF frequency, assumed to be 5MHz. Hence the

up converted signal frequency will fall at 5.1MHz. The red plot in Figure 3-7 shows the

down converted signal RxB(t) to a 400 KHz baseband frequency and effectively, in this

simulation, the demodulator frequency is assumed to be 300 KHz. If a DFT operation is

performed at the signal bin Q = (cilF -BB), all the terms of Equation 3-18 except the

component vectors containing Q will equate to zero. Hence, the DFT of I and Q

channel can be expressed as

I DFT =DG 1 e(+Z) e( (3-19)
2 2 2


Q DFT DIG- Aje() +j lej (3-20)
S2 2 22

If the input to the Q channel is 0, then the second term becomes zero and hence,

Equations 3-19 and 3-20 can be represented as

I D FT= 1 G e ) (3-21)
2 2


Q DFT = DG( Aje ) (3-22)
2 2

Assume the RF VGA gain stage is changed from Gain stage G to G1 which introduces

a complex phase shift from eJ"' to ejA2. The goal of the algorithm is to find the relative

phase shifts and compensate for them by predistorting the I and the Q channel signals.









2.5 DSP Hardware Structures for the DSP-DGT Algorithm

The following sections describe the DSP hardware structure adopted to implement the

algorithm.

2.5.1 Digital Calibration Signal Pattern Generator

In order to calibrate the delay between the reference path and the feedback path

signals, signal cross-correlation hardware is employed in the described algorithm. As a

part of the cross-correlation operation, a digital calibration signal is applied as the

reference input signal. This results in a corresponding feedback signal through the

transmit path. Signal cross-correlation between the reference path and the feedback

path signals is estimated based on which the group delay is estimated. Figure 2-12

shows the hardware used to generate the digital calibration signal by using a linear

feedback shift register topology.

The DSP hardware uses a 6 stage flip flop bank. The circuit consists of flip flops

with load capability as shown in Figure 2-12. An initial binary value is loaded into the flip

flop. As described in [72] for a 6 stage linear feedback shift register, the output of the 6th

and the 5th flip flop is fedback to an XOR gate. The output of the XOR gate feeds the 1st

flip flop. The output of each flip flop is tapped serially by using a multiplexer which is

controlled by a clock signal which is operating at 6 times faster than the flip flop clocks.

This results in tapping out the output as a 6 bit word serially as shown in Figure 2-14.

2.5.2 Digital Sample Rate Adjust Logic

In the described DSP-DGT algorithm, it is essential to bring the forward path signal

and the feedback path signal to the same sample rate before cross-correlation is

estimated. In our system architecture, we assume that the sample rate of the ADC

present in the feedback path higher than the forward path signal. Hence, to









has signaled the mobile device to decrease the transmit power. Figure 4-29 captured

RF power at the output of antenna using CMU equipment. The carrier frequency is

1800MHz GSM band. As shown in Figure 4-29, the transmit power of the mobile device

is increased from a lower power level to OdBm. The implemented DSP-GC algorithm not

only helps the mobile device to change the transmit power from a lower level to OdBm,

but also helps in maintaining the desired power of OdBm until the end of signal

transmission.

4.6 Summary

* The DSP-GC technique employs an adaptive filter to reduce the variance of the
error signal at the input to the controller.

* System stability and gain margin analysis is performed as a function of loop
delays. Based on the stability constraint approach, the maximum delay the loop
can handle is estimated to be 2.4usec.

* Based on the knowledge of steady state delay, the gain of the unknown plant
transfer function, the feedback loop delay a novel loop tuning technique is used
to estimate the controller gains for an Nthorder unknown plant.

* System simulations and lab measurements show that the DSP-GC algorithm
performs gain changes upto 90 dB dynamic range with a resolution of 0.1dB
power accuracy.

* Since the variance of the error signal is minimized, lab measurements prove that
the settling time improved by 15usec compared to DSP-DGT algorithm at the
slight expense of gain margin reduction.

* The DSP-GC digital technique uses only 17K digital gates and the current drain
is 22mA.


166










Table 3-8.
Ratio


Ratio(1,O)
Ratio(2,1)
Ratio(3,2)
Ratio(4,3)
Ratio(5,4)
Ratio(6,5)
Ratio(7,6)
Ratio(8,7)


142


Simulation results of phase estimate error
I DFT(G,e"l')
I DFT(GeJI) )
3.497e-01 1.428e-02i
1.956e+00 2.84i
1.444e+00 5.326e-01i
2.852e-01 1.941e-01 i
9.124- 1.996i
2.033e+01 5.1499e-01 i
1.0363e+01 5.081i
2.341e-01 1.320e-02i































Figure 2-28. Cascaded structure for the fast average circuit


Average second filter estimate vs time in sec









-*- output of the second average
S- idel average estimate






Second filter structure in the Hardware
is used if there is more varaince at the
first average output depending on the
stochastics of the input signal

This is intended to be used after the first average ends


0.5 1 1.5 2
time in sec


2.5 3 3.5 4
x10-5


Figure 2-29. Output of second filter vs. time in sec


0.16


0.14


m 0.12
E

a)
M 0.1


0.08























step I
response

0.3- Settling time


0.2-


0.1
Rise time
0
0 0.5 1 1.5 2 2.5
time (sec)
Figure 4-3. System constraints in selecting the controller gains.



FUnknown


R(s) +4 Sipife Go Y(s)






Figure 4-4. Simplified closed-loop model


T=K/M


\Time delay = time
Td
Figure 4-5. Open loop based tuning technique


170










Table 2-3. Multiplexor selection logic for the
Mux selection Xcorrout<4>


MuxA


MuxA


MuxA


MuxA


MuxB


MuxB


MuxB


MuxB


MuxC


MuxC


MuxC


MuxC


12 tap cross-correlator.
B3B2B1Bo



0000



0001


A
0010



0011



0100




0101



0110



0111



1000



1001



1010



1011


Rxy(k)


M-1
C x(n)y(n)
n=0


3)y(n)




4)y(n)


4-1
Vx(n
n=0


M-1
Vx(n
n=0

M-1
Vx(n
n=0


10)y(n)



1l)y(n)









BIOGRAPHICAL SKETCH

Pravinkumar Premakanthan was born on Feb 3, 1979 in Chennai, India. He

graduated from State Bank Officers Association (S.B.O.A) high school in Anna Nagar,

Chennai, India in 1996. He obtained his bachelor's in Electrical and Electronics

Engineering (EE) from College of Engineering, Guindy (C.E.G) Anna University,

Chennai in the year 2000. He pursued his master's degree in EE under the research

guidance of Dr. Wasfy Mikhael at the University of Central Florida, Orlando and

graduated in the year 2002. Upon completing his master's degree, he worked as

wireless system engineer with Motorola Semiconductors from 2002-2005. During these

three years, he had the opportunity to design and develop wireless ICs for cellular

phones. In 2004, while working at Motorola Semiconductors, he started to pursue his

PhD with the Computational Neuro Engineering laboratory (CNEL), University of

Florida, (UF) under the guidance of Dr. John Harris. He joined as a full-time student at

the Department of EE, UF in Aug 2005. After spending a year and half at CNEL, he re-

joined wireless team with Freescale Semiconductors and pursued active research and

development work while still continuing his doctorate studies. He is presently working as

a wireless system lead engineer with Fujitsu Microelectronics in Tempe, Arizona. He

holds five U.S. patents in the area of wireless transceivers. Upon completion of his

doctorate degree he will continue his present role as wireless system lead at Fujitsu

Micrelectronics. He lives with his wife, Manjula in Chandler, Arizona. Pravin's greatest

mentor and role model in life is his PhD advisor, Dr. John Harris.












Antenna Power (15dBm to 24dm)


29.506






-22. 4


Input to the Adaptive Filter

S I '1 11'., 11i.i 1 1. 11p 11- /i i .1 .11 Illi 111,ipil I
.1ll.lplli' U illrjh dill III!. p,.%%U t ip .111nii1 p '% tI (I.%% ii






Output of the Adaptive Filter

%' I' I -1 -i'' il 1(.ipli', I,- /I l ., ll I, ,, lptil 4,
S.Il. lll l I'illil (u11l IIl p "t1*'l ulp .111(1 p,,"t l1 (It" 11
t------.--.-^o ---

I r
-0.906 r

Weight W1







W W2

Weight W2
2.0bb


%%\\ i_'lil .I. l.i l.ilmi
\i_111 l'lll '_ l'll Il
/ III


0


Figure 4-25. Simulation to show the adaptation of the LMS
error signal


algorithm with weights and


182


I 1111i.1. u d )ilDil D,.%% s \UI .ilu (1o ICU 1(1i ll11


'









Table 3-5. Simulation results of estimated DFT of I channel
DFT Complex output
I _DFT(Ge ) 3.445e+02-5.786e+01i
I DFT(G2e12) 5.0966e+02-1.091 e+03i
I DFT(G3e j3) 1.548e+02-1.848e+03i
I DFT(G4eJA4) -3.14e+02-5.57e+02i
I DFT(Ge"j5) -3.98e+03-4.45e+03i
I DFT(G6e j6) -8.33e+04-8.8598e+04i
I DFT(G7e "7) -1.314e+06-4.947e+05i
I DFT(Gsej"8) -3.141e+05-9.84e+04i


Simulation results of


estimated ratio of DFT's
I DFT(Ge n )
I DFT(G ,e )Am
3.497e-01 1.428e-02i
1.956e+00 2.84i
1.444e+00 5.326e-01i
2.852e-01 1.941e-01 i
9.124- 1.996i
2.033e+01 5.1499e-01i
1.0363e+01 5.081i
2.341e-01 1.320e-02i


Table 3-6.
Ratio


Ratio(1,O)
Ratio(2,1)
Ratio(3,2)
Ratio(4,3)
Ratio(5,4)
Ratio(6,5)
Ratio(7,6)
Ratio(8,7)


Table 3-7.
Ratio


Ratio(1,O)
Ratio(2,1)
Ratio(3,2)
Ratio(4,3)
Ratio(5,4)
Ratio(6,5)
Ratio(7,6)
Ratio(8,7)


Simulation results showing error in estimation
I DFT(GneJn)
\I DFT(GeJ- )
3.497e-01 1.428e-02i
1.956e+00 2.84i
1.444e+00 5.326e-01i
2.852e-01 1.941e-01 i
9.124-1.996i
2.033e+01 5.1499e-01 i
1.0363e+01 5.081i
2.341e-01 1.320e-02i









[71] Gene F Franklin, J.David Powell, Michael L. Workman, "Digital Control of
Dynamic Systems," Prentice Hall; 3rd ed, Dec 29, 1997.

[72] James Palmer, "Introduction to Digital Systems," McGraw-Hill, 1993.

[73] Richard G. Lyons, "Understanding Digital Signal Processing, Prentice Hall PTR,
2nd ed, Mar 2004.

[74] Katsuyama et al, "Output Power control circuit for a Mobile Radio Apparatus,"
U.S. Patent 4870698, September 26, 1989

[75] Radio Transmitter, Masahiro Uno, Sony Corporation, Japan, US Patent
58266177, October 20, 1998.

[76] J.G. Zeigler and N.B Nicholas, "Optimum Settings for Automatic Controllers,
"Trans. of ASME- 64, pp 759-765, Dec. 1942.

[77] G.H Cohen and G.A. Coon, Taylor Instrument Companies, Theoretical
Investigations of Retarded Control, Trans. ofASME- 75, pp 827-834.

[78] Alan Edelman, H.Murakami, "Polynomial Roots from Companion Matrix Eigen
values, Internal paper, Department of Mathematics, Massachusetts Institute of
Technology, Cambridge, Jan.1994.

[79] Rohde & Schwarz CMU200 Communication Tester Application Note.
Author: Ottmar Gerlach.
[updated 03 January 2004]. Available from
http://www2.rohde-schwarz.com/file_910/1 MA64_15e.pdf

[80] Rohde & Schwarz FSQ Signal Analyzer User Manual.
Author : Rohde & Schwarz.
[updated 27 November 2009]. Available from
http://www2.rohde-
schwarz.com/file_5543/FSQ%200perating%20Manual%20English%20FW%204.
55.pdf

[81] NI LabVIEW Labview User Manual.
Author: Technical communications.
[updated 18 March 2003]. Available from
http://www.ni.com/pdf/manuals/320999e.pdf

[82] Agilent N9020A MXA Signal Analyzer Configuration Guide.
Author: James Wakeman.
[updated 30 March 2009]. Available from
http://cp.literature.agilent.com/litweb/pdf/5989-4943EN. pdf


195




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PAGE 1

1 SIGNAL PROCESSING TECHNIQUES AND DSP HARDWARE STRUCTURES FOR DYNAMIC ESTIMATI ON AND COMPENSATION OF ABSOLUTE AND RELATIVE GAIN/PHASE VARIATIONS IN MOBILE DEVICES By PRAVINKUMAR PREMAKANTHAN A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 20 10

PAGE 2

2 20 1 0 Pravinkumar Premakanthan

PAGE 3

3 Quest for knowledge, the learning, an d the humility that accompanies it

PAGE 4

4 ACKNOWLEDGMENTS I am immensely grateful to my research advisor and mentor Dr. John Harris for his encouragement and support during my PhD research. I feel extremely fortunate to work under his guidance over the past 6 years. I would like to extend my sincere thanks to my committee members Dr. Fred Taylor, Dr.Janise McNair and Dr.Oscar Crisalle. I greatly appreciate their generosity in devoting their time to serve on my research committee. I am equally grateful to my managers Dr. Mahib Rahman, and Dr. Bing Xu and Vivek Bhan for their encouragement towards my research effort. I would like to thank my wife for her selfless support and understanding. Greatest thanks to my parents for providing the path towards the quest for knowledge. Finally, I am grateful to Ms. Shannon Chillingworth for her advice and support during this research effort.

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5 TABLE OF CONTENTS ACKNOWLEDGMENTS ...................................................................................................... 4 page LIST OF TABLES ................................................................................................................ 8 LIST OF FIGURES .............................................................................................................. 9 LIST OF ABBREVIATIONS .............................................................................................. 15 ABSTRACT ........................................................................................................................ 16 CHAPTER 1 INTRODUCTION ........................................................................................................ 18 1.1 Motivation: Need for Power Control and Gain Tracking Inside Mobile Device ................................................................................................................ 18 1.2 Power Control Techniques in Mobile Devices .................................................. 22 1.3 Present Day Techniques and Prior Art ............................................................. 23 1.3.1 Use of Fixed Calibrated Digital Gain Offset and Error Values .............. 23 1.3.2 Use of Pre -Calibrated Analog Bias Signal for Constant Envelope M odulation ............................................................................................... 24 1.3.3 Use of RF Feedback and Analog Bias Control ...................................... 24 1.3.4 Use of RF Feedback and Temperature Compensation Circuit Based Gain Control ................................................................................ 25 1.4 Limitations of Prior Art ....................................................................................... 25 1.5 Research Effort Comparisons ........................................................................... 26 1.6 Organization of Thesis ....................................................................................... 26 2 DIGITAL DSP TECHNIQUES AND EFFICIENT HARDWARE TOPOLOGIES FOR ABSOLUTE GAIN TRACKING .......................................................................... 37 2.1 Problem Statement ............................................................................................ 37 2.2 Reasons for Signal Gain Variations in Mobile Devices .................................... 38 2.2.1 Gain variations due to Manufacturing Processes .................................. 38 2.2.2 Power Gain Variations due to Change in Junction Temperature.......... 39 2.2.3 Change in Power Gain Due t o Different Operating Paths Depending on Power Level ....................................................................................... 39 2.2.4 Variation in Gain Due to Different Operating Frequencies and Supply Voltage ........................................................................................ 40 2.3 DSP Based Dynamic Gain Tracking Algorithm (DSP -DGT) ............................ 40 2.3.1 System Architecture of the DSP -DGT Algorithm ................................... 40 2.3.2 Feedback Path ........................................................................................ 41 2.3.3 Forward Reference Path ........................................................................ 42 2.4 Algorithm Theory ................................................................................................ 42 2.5 DSP Hardware Structures for the DSP -DGT Algorithm ................................... 47

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6 2.5.1 Digital Calibration Signal Pattern Generator .......................................... 47 2.5.2 Digital Sample Rate Adjust Logic ........................................................... 47 2.5.3 Magnitude Estimator ............................................................................... 48 2.5.4 Fast Exponential Averager ..................................................................... 51 2.5.5 Digital PID controller ............................................................................... 53 2.5.6 Cross -Correlator Hardware .................................................................... 54 2.5.6.1 Simulations with the cross -correlation DSP hardware ............. 56 2.5.6.2 Correlation estimates at varying sample rates ......................... 58 2.6 To p Level System Simulations and Measured Lab Results ............................. 59 2.6.1 System Simulations ................................................................................ 59 2.6.2 Mobile Testing and Lab Measurements ................................................. 61 2.7 Summary ............................................................................................................ 62 3 DSP BASED DYNAMIC ESTIMATION AND COMPENSATION OF DIFFERENTIAL GAIN NONLINEARITY AND RANDOM PHASE SHIFTS ............ 100 3.1 Demands for Relative Gain and Phase Accuracy in Mobile Devices ............ 100 3.2 Analytical Expressions for Non Linear Distortions i n an Analog RF Device .. 101 3.3 Reasons for Relative Power Level Accuracy Impairment .............................. 105 3.4 Reasons for Phase Discontinuity .................................................................... 107 3.5 DSP based Relative Gain/Phase Estimation Algorithm Theory (DSP GPE). 108 3.5.1 Theory of Operation .............................................................................. 108 3.5.2 Gain and Phase Estimation Steps ....................................................... 112 3.5.3 Gain and Phase Compensation Implementation and Equations ........ 113 3.5.4 Derivation of Equations for Gain and Phase Estimation and Compensation ....................................................................................... 114 3.6 DSP Hardware Structures for Relative Gain/Phase Estimation and Compensation .................................................................................................. 116 3.6.1 Phase Compensation DSP Structure ................................................... 116 3.6.2 DFT Based Gain Estimation Structure ................................................. 116 3.7 System Simulations and Lab Measurement Results ...................................... 119 3.7.1 System Simulations of the DSP -GPE Algorithm ................................. 121 3.7.2 Lab Measurement Results ................................................................... 121 3.8 Summary .......................................................................................................... 123 4 DYNAMIC GAIN/POWER CONTROL USING ADAPTIVE DSP TECHNIQUES ... 143 4.1 Introduction ...................................................................................................... 143 4.2 System Architecture for the DSP -GC Algorithm ............................................. 144 4.3 Loop Tuning Techniques ................................................................................. 150 4.3.1 Method I Reference Model Based Loop Tuning ................................ 150 4.3.2 Method II Open Loop Tuning Based On Unknown Plant Transfer Function ................................................................................................ 152 4.3.3 Method III Loop Tuning Based on Closedloop Cycling .................... 152 4.3.4 Meth od IV Implemented Loop Tuning Technique Based on Closed -loop Stability Constraint ........................................................... 154 4.4 Closed -loop Delay and Loop Gain Margin Analysis ....................................... 157

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7 4.4.1 Effect of Loop Delay ............................................................................. 158 4.4.2 Gain Margin Analysis ............................................................................ 160 4.5 System Simulation and Lab Measurement Results ........................................ 162 4.5.1 System Simulations of the DSP -GC Method ....................................... 162 4.5.2 Lab Measurements of the DSP -GC Adaptive Algorithm ..................... 164 4.6 Summary .......................................................................................................... 166 5 CONCLUSIONS, APPLICATIONS & SCOPE FOR FUTURE DIRECTIONS ........ 187 5.1 Thesis Summary .............................................................................................. 187 5.2 Other Areas of Applications ............................................................................. 189 LIST OF REFERENCES ................................................................................................. 190 BIOGRAPHICAL SKETCH .............................................................................................. 197

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8 LIST OF TABLES Table page 1 -1 Comparison of New Techniques ............................................................................ 35 2 -1 Estimation of best and factors for magnitude estimation ............................. 96 2 -2 Signal gain implementation .................................................................................... 97 2 -3 Multiplexor selection logic for the 12 tap cross -correlator. ................................... 98 3 -1 Approximate THD requirements for a few applications ...................................... 137 3 -2 DNLE and INLE Definition ................................................................................... 138 3 -3 Measured High Frequency Amplifier gain across temperature and frequency bands of operation. ............................................................................................... 139 3 -4 Measured DNLE with mid channel as the reference for a 16 stage gain amplifier ................................................................................................................ 140 3 -5 Simulation results of estimated DFT of I channel ............................................... 141 3 -6 Simulation results of estimated ratio of DFTs ..................................................... 141 3 -7 Simulation results showing error in estimation .................................................... 141 3 -8 Simulation results of phase estimate error .......................................................... 142 4 -1 Weight update for the LMS filter .......................................................................... 185 4 -2 Esti mated Poles based on max IK ....................................................................... 185 4 -3 Feedback path delay calculation ......................................................................... 186

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9 LIST OF FIGURE S Figure page 1 -1 Power control signaling from base -station to mobile device................................. 28 1 -2 Occupancy of mobile users in frequency domain without power control ............. 28 1 -3 Ideal gain control with no error in correction after power control .......................... 29 1 -4 Gain errors introduced due to analog/RF circuit imperfections as a function of operating conditions ........................................................................................... 29 1 -5 Measured adjacent channel interference due to abrupt power control without signal shaping captured by Agilent N9020A MXA signal analyzer ....................... 30 1 -6 Lower spectral leakage due to power control with signal shaping captured by Agilent N9020A MXA signal analyzer .................................................................... 30 1 -7 System level overview o f a mobile device ............................................................. 31 1 -8 Reduction of signal power from the mobile device captured by Rhode and Schwartz CMU 2000 analyzer ............................................................................... 32 1 -9 Multiple power changes of the mobile device captured by Rhode and Schwartz CMU 2000 analyzer ............................................................................... 32 1 -10 Prior art that uses fixed digital gain offsets and errors to perform digital gain c ontrol ..................................................................................................................... 33 1 -11 Prior art that adopts pre -calibrated analog bias levels for gain control and tracking ................................................................................................................... 33 1 -12 Prior art that adopts RF feedback and coarse analog bias adjust ....................... 34 1 -13 Prior art that uses RF feedback and temperature compensation circuit for bias adjust ............................................................................................................... 34 2 -1 Primary sections of a mobile device transmitter ................................................... 63 2 -2 Absolute RF Power variation in dB due to temperature variations averaged over three parts ...................................................................................................... 63 2 -3 Pout variations across frequency bands over temperature .................................. 64 2 -4 Absolute RF power variations in dB due to frequency of operation ..................... 64 2 -5 Pout variations across frequency bands over supply voltage .............................. 65

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10 2 -6 System level block diagram of the DSP -DGT architecture ................................... 66 2 -7 Controller adopted for the closed -loop DSP -DGT algorithm ................................ 67 2 -8 Secondorder closed -loop PID controller .............................................................. 68 2 -9 Closed -loop dynamics when the controller compensates for undesired positive gain change .............................................................................................. 69 2 -10 Closed -loop dynamics when the controlle r compensates for an undesired negative gain change ............................................................................................. 70 2 -11 Flow chart of the steps involved in the DSP DGT algorithm ................................ 71 2 -12 Linear Feedback shift register for a 6 tap pseudo random signal generator ....... 72 2 -13 Timing signal to generate 6 times faster sample rate at the output ..................... 72 2 -14 Output pseudo random bit stream from a 6 tap linear feedback shift register. .... 73 2 -15 DSP implementation of sample rate logic ............................................................. 74 2 -16 In -phase and quadrature phase signal swings whose magnitude has to be estimated. ............................................................................................................... 74 2 -17 Instantaneous error (linear) vs. input signal swing funct ion as a function of and factors ...................................................................................................... 75 2 -18 Simple absolute value estimator logic ................................................................... 75 2 -19 Digital DSP hardware structure for magnitude comparator .................................. 76 2 -20 Digital DSP hardware structure for the magnitude estimator ............................... 77 2 -21 System simulations with quantized I and Q random signals and mean error in estimation. .............................................................................................................. 78 2 -22 Ideal and obtained signal magnitude ..................................................................... 79 2 -23 Magnitude er ror in dB as a function of buffer hardware length ............................ 79 2 -24 DSP structure of the exponential averager ........................................................... 80 2 -25 Settling times of the averager as a function of filter factor .................................... 80 2 -26 Dynamic varying filter factor depending for noise and response time trade offs. ......................................................................................................................... 81 2 -27 Magnitude response of the averager ..................................................................... 81

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11 2 -28 Cascaded structure for the fast average circuit .................................................... 82 2 -29 Output of second filter vs. time in sec .................................................................... 82 2 -30 DSP structure for PID controller with programmable gains .................................. 83 2 -31 Controller gain pr ogramming hardware ................................................................. 83 2 -32 Digital implementation of 12 taps cross -correlation DSP hardware ..................... 84 2 -33 Cross -Correlation of cal ibration signal .................................................................. 85 2 -34 Simulation to show the correlation estimate between the calibration signal and the feedback signal ......................................................................................... 85 2 -35 Signal buffer of baseband signal envelope ........................................................... 86 2 -36 Detected Signal at the output of the ADC at the signal sample rate (no downsampling) ....................................................................................................... 86 2 -37 Normalized signal correlation between baseband signal envelope and detected signal. ...................................................................................................... 87 2 -38 Time aligned gain scaled baseband signal envelope and detected signal .......... 87 2 -39 Correlation estimate of baseband signal envelope and feedback signal with downsample ratio of N=2 ....................................................................................... 88 2 -40 Correlation estimate of baseband signal envelope and feedback signal with downsample ratio of N=5 ....................................................................................... 88 2 -41 Correlation estimate of baseband signal envelope and feedback signal with downsample ratio of N= 10 ..................................................................................... 88 2 -42 Correlation estimate of baseband signal envelope and feedback signal with downsample ratio of N=20 ..................................................................................... 89 2 -43 Simulation to show injected 6dB gain variation and the reference signal level ... 89 2 -44 Simulation to show the controller output adaptation for a positive 6dB gain variation in multiple steps ....................................................................................... 90 2 -45 Simulation to show the closed-loop response with respect to different integral gains for a positive 6dB gain variation ................................................................... 90 2 -46 Simulation of the closed-loop circuitry adaptation until error signal becomes zero. ........................................................................................................................ 91

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12 2 -47 Simulation to show the controller correction for +6dB, +5.5dB and -6.5dB gain variation. ......................................................................................................... 91 2 -48 Simulation to show the controller output to track for +10dB, +3.5dB and 5.5dB gain variation. .............................................................................................. 92 2 -49 System interface for mobile device testing ............................................................ 92 2 -50 Analog version of the controller compensation by multiple steps to reach to the desired power as captured by Tektronix oscilloscope .................................... 93 2 -51 Analog version of the controller compensation by a single step to reach to the desired power level captured by Tektronix oscilloscope ...................................... 93 2 -52 Analog response of the controller output shows oscillations due higher value of integral gains captured by Tektronix oscilloscope ............................................ 94 2 -53 Analog response of the controller output to shows over damped condition due lower value of integral gains captured by Tektronix oscilloscope ................. 94 2 -54 Measured (FSIQ) plots of RF output at the power amplifier output as a function of controller gains ..................................................................................... 95 3 -1 System block diagram of a wireless transmitter showing gain change and phase change ....................................................................................................... 123 3 -2 Measured amplifie r bias vs. output characteristics with respect to temperature and frequency bands of operation .................................................. 124 3 -3 Measured DNLE (dB) with respect to change is frequency bands of operation 124 3 -4 Measured INLE with respect to change is frequency bands of operation .......... 125 3 -5 Absolute phase variations of an RF device due to cap acitive loads ................. 125 3 -6 Gain and phase estimation A) System block diagram of the mobile device with the DSP -GPE algorithm. B) Implemented frequency location of the calibration signal during t he algorithm ................................................................. 126 3 -7 Frequency location of the calibration signal during the algorithm ...................... 128 3 -8 Flowchart of the DSP -GPE algorithm for relative gain and phase change estimation ............................................................................................................. 129 3 -9 Baseband signal phase compensation DSP hardware structure ....................... 130 3 -10 Simulation of baseband signal phase compensation by using the DSP hardware structure ............................................................................................... 131

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13 3 -11 DSP Hardware structure to estimate the absolute gain change......................... 131 3 -12 DSP Hardware structure to estimate the absolute gain and phase change ...... 132 3 -13 Simulation plots to show that ) ( t RxBB with frequency of 400 KHz and KHzIF300 over the 8 RF gain settings .......................................................... 132 3 -14 Simulation of FFT magnitude of ) ( t RxBB with KHzIF300 over the 8 RF gain settings ......................................................................................................... 133 3 -15 Simulated DFT m agnitude of I and Q channel for K = 13, 14, 15, 16, 17 ........ 133 3 -16 Ideal gain change refG estimated gain change G (dB) and DNLE(dB) | refG G | ............................................................................................................ 134 3 -17 Ideal phase change ref estimated phase change (deg) and err =| ref | ................................................................................................ 134 3 -18 Averaged INLE error measured on three RFIC after the gain error compensation. ...................................................................................................... 135 3 -19 Absolute phase variation in the mobile device after phase compensation ........ 135 3 -20 Relative phase variation in the mobile device after compensation .................... 136 3 -21 Measured plots to show the 90 degrees phase compensation performed by the DSP hardware ................................................................................................ 137 4 -1 Power control A) Measured transmit power to show the PAR and PTN of a LTE signal captured by Rhode and Schwartz CMU 2000 B)System architecture of the DSP -GC algorithm implemented in a mobile device ............ 167 4 -2 DSP hardware implementation of the adaptive filter and 1st order integrator .... 169 4 -3 System constraints in selecting the controller gains. .......................................... 170 4 -4 Simplified closed loop model ............................................................................... 170 4 -5 Open loop based tuning technique ...................................................................... 170 4 -6 Closed -loop based tuning technique ................................................................... 171 4 -7 Closed -loop system with an integral controller .................................................... 171 4 -8 Discrete model of closed-loop system at steady state ........................................ 171 4 -9 Flow chart to estimate integral gain ..................................................................... 172

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14 4 -10 Step response of the unknown open loop system .............................................. 172 4 -11 Plot of poles of the transfer function with IK = max IK ......................................... 173 4 -12 Closed -loop system simulations with appropriate integral gains ........................ 173 4 -13 Simplified model for loop delay and gain margin analysis .................................. 174 4 -14 Pole -zero location with loop delay, D = 1, 3, 7 and 9 samples at sample rate s. ........................................................................................................................... 174 4 -15 Pole -zero location with loop delay, D = 13, 17, 19 and 21 samples at sample rate Fs. .................................................................................................................. 175 4 -16 Pol e -zero location with loop delay, D = 24, 26, 28 and 31 samples at sample rate Fs. .................................................................................................................. 175 4 -17 Pole -zero location with loop delay, D = 39, 45, 52 and 58 samples at sample rate Fs. .................................................................................................................. 176 4 -18 Closed -loop step response with respect to varying plant delays. ...................... 176 4 -19 Pole -zero location with loop delay, D =13 samples and in tegral gains of 36 dB, 32dB, -30dB and -26dB. ............................................................................... 177 4 -20 Pole -zero location with loop delay, D =13 samples and integral gains of 22 dB, 20dB, -6dB and 9dB. .................................................................................... 177 4 -21 Power detector and feedback path input output characteristics. ........................ 178 4 -22 Loop gain margin with varying loop delay as a function of antenna power ....... 179 4 -23 Simulation to show the closed-loop dynamics for a positive power change ...... 180 4 -24 Simulation to show the closed-loop dy namics for a negative power change..... 181 4 -25 Simulation to show the adaptation of the LMS algorithm with weights and error signal ............................................................................................................ 1 82 4 -26 Simulation to show the rate of change of error signal and the feedback as a function of convergence factor ............................................................................. 183 4 -27 Analog response of the closedloop system with the adaptive filter captured by Tektronix oscilloscope ..................................................................................... 183 4 -28 Analog closedloop response for multiple steps with the adaptive filter captured by Tektronix oscilloscope ..................................................................... 184 4 -29 Transmit power of the mobile device captured by CMU 2000. ........................... 184

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15 LIST OF ABBREVIATION S ADC Analog to Digital Converter BPSK Binary Phase Shift Keying DSP Digital Signal Processing DNL Differential Nonlinearity DAC Digital to Analog Converter DC Direct Current EDGE Enhanced Data rates for GSM Evolution GSM Global Systems for Mobile Communications I In -phase INL Integral Nonlinearity LMS Least Mean Square OFDM Orthogonal Frequency Divisi on Multiplexing PID Proportional, Integral and Derivative Controller Q Quadrature Phase QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RFIC Radio Frequency Integrated Circuit SNR Signal to Noise Ratio SIR Signal to Interference Ratio VCO Voltage controlled oscillator VGA Variable Gain Amplifier Wi -MAX Worldwide Interoperability for Microwave Access WCDMA Wideband Code Division Multiple Access

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16 Abstract of Dissertation Presented to the Graduate School of the Unive rsity of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy SIGNAL PROCESSING TECHNIQUES AND DSP HARDWARE STRUCTURES FOR DYNAMIC ESTIMATION AND COMPENSATION OF ABSOLUTE AND RELATIVE GAIN/PHASE VARIATI ONS IN MOBILE DEVICES. By Pravinkumar Premakanthan August 2010 Chair: John Harris Major: Electrical and Computer Engineering We introduce system architectures and algorithms with related DSP hardware structures to dynamically estimate and compensate f or relative/absolute gain variations in any analog or digital signal processing paths. In addition, the presented techniques are used to calibrate and compensate for relative signal phase shifts occurring in a mobile device. The techniques described in thi s thesis are implemented in a mobile device to dynamically estimate and compensate for absolute and relative signal power variations from the desired power levels. These techniques help to prolong battery life of the mobile device and to reduce signal -to -i nterference ratio (SIR) at the base -station In addition the described system algorithms are implemented using efficient digital circuitry which eliminates the bulky analog components which were originally used for this purpose. The digital circuit implementation makes the mobile device less susceptible to variations in temperature, frequency of operation and manufacturing processes. The digital area of the implemented digital circuitry is found to be around 22K gates and the digital current drain is approx imately 20mA. System lab measurements show that the

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17 mobile system is able to compensate better than 0.1dB absolute and relative power level accuracy and also result in phase estimation accuracy better than 1 degree.

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18 CHAPTER 1 INTRODUCTION The demand for mobile access and high data rate communications services such as video teleconferencing, real time video streaming, internet access, music download and file transfers continue s to grow rapidly for a wide variety of military as well as commercial mobile applications. It is highly essential for all the mobile st andards to coexist without any of the mobile devices degrading signal quality of the other devices In order to accomplish this present day mobile communications networks employ power control techniques wherein the base -station sends control commands to each of the mobile devices to ensure that each of the mobile users transmits only the required amount of signal power to maintain a good quality transmission and reception link. These power control tec hniques not only help prolong battery life for the mobile device, but also dramatically reduce SIR [ 23] in the system. The base -station estimates the amount of power change required by the mobile device using various power control algorithms [50] depending on the mobile standard. Similarly, each mobile user employs various techniques to respond to the commands from the base -station with the help of analog and digital signal processing circuits implemented inside the mobile device. In this thesis, we focus on techniques that are implemented in each mobile device that provide absolute/relative gain control and compensation as dictated by the base -station 1.1 Motivation: Need for Power Control and Gain Tracking Inside Mobile Device In response to dictated pow er level commands from the base-station, each mobile device must dynamically alter the absolute transmit power level and keep track of relative power level changes. This is accomplished with the help of di gital, analog and

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19 radio frequency (RF) circuitr y pr esent inside the mobile IC. The design and performance of these circuits within each mobile device determines the precision of the power control. This thesis work describes system algorithms and corresponding digital circuit implementations used inside mobile devices to dynamically estimate and compensate for any power change commands from the base -station. In addition, these circuits can be used to track the gain variations of the mobile device and to automatically compensate for gain and phase errors. Thi s helps in maintaining absolute and relative power level accuracy The described algorithms have been implemented in a mobile device and lab measurements are provided to validate the system performance. The primary reasons for dynamic gain control circuitr y inside any mobile device or in any base -station transmitter are to 1 Increase system capacity by reducing signal interferences within an operating cell. 2 Improve transmit signal quality by accurately scheduling and allocating desired power levels. 3 D ynamica lly compensate for gain variations caused by local analog/RF circuits. 4 P erform gain change s and corrections in a spectrum -friendly manner to reduce interference to neighboring users. 5 Provid e finer gain control updates. ( 0.1dB accuracy). 6 Increase co existen ce of various mobile schemes such as Worldwide Interoperability for Microwave Access (Wi -Max), Blue -tooth, Cellular, and Digital Video Broadcasting (DVB) such that all these features available in a single mobile device. 7 Maintain system gain accuracy until the next power change commands arrive from the base -station. Figure 1 1 illustrates how the base-station signals the mobile users within a cell site to either increase or decrease the transmit signal power depending on their

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20 location. Based on t he signal quality estimate, power control commands are sent to each mobile user to instruct the mobile to raise or lower its transmitted power in allotted decibel ( dB ) steps. If the received signal power at the base -station is low, then a is transmitte d to signal the mobile user to increase its mean power level. If the received signal power at the base-station is high, the base -station signals a 0 to reduce the power level of the user. To understand the gain control mechanism and the is sues faced assume a mobile system with eleven users and each assigned a separate frequency band of operation as shown in Figure 1 2. The red dotted line in Figure 1 -2 indicates the desired signal power the base -station must receive from each mobile user t o preserve signal quality irrespective of the mobile users distance from the base -station Figure 1 2 indicates that in the absence of power control from the base -station the received power levels at the base -station from certain mobile users do not meet the desired SIR. The weaker signals are completely degraded by the stronger signals and result in dropped calls. In order to solve this issue, the base -station sends power control commands to the mobile device to increase or decrease the transmit power levels depending on the location of the mobile device with respect to the base -station As an example, assume that the base -station signals a mobile user to raise its power level by 4dB. Based on this command, it is the responsibility of the circuitry insid e the mobile device to raise its power level by the desired 4dB. The amount of gain error between the ideal and the obtained power level change is called as power tolerance allowance and is a critical factor that influences relative power level accuracy.

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21 F igure 1 3 shows ideal power control without any gain errors introduced during the gain control process. However, it is very difficult to achieve such precise control practically due to imperfections of the analog and RF circuit as a function of operating conditions. The performance of analog and RF circuits with respect to operating temperatures, frequency bands of operation, battery voltage causes gain and phase errors which degrade gain control accuracy This is discussed in detail in Chapter 2. As shown in Figure 1 4, in present day cellular standards, the power tolerance a llowance for gain variations is around +/ -3dB For adv anced protocols such as LTE (Long T erm E volution) and 2G E volution, the margin for gain variations is less than 0.2dB to support d ifferent mobile standards to co exist These stringent power accuracy requirements demand for precise and efficient dynamic digital gain correction techniques to yield gain corrections better than 0.2 dB accuracy Another issue in present day circuits is t hat the gain correction is performed instantaneously and hence leads to spectral leakage into [7],[39] bands. This in turn causes reduction of system capacity. Figure 1 5 and Figure 1 6 shows the transmit spectrum measured at the output of the mobile devic e operating at 2.5GHz band. The communication testing equipment used to capture this measurement is Agilent N9020A MXA s ignal a nalyzer [82]. As shown in Figure 1 5 an uncontrolled instantaneous rapid gain change performed in the mobile device lead s to spe ctral leakage and cause s interference to the adjacent user [1] This degrade s the SNR of the adjacent user and hence reduce s system capacity. The gain change or gain compensation applied to the analog or the digital stages of the mobile device must be contr olled in a spectrum friendly profile to reduce out of band spectral emissions as shown in Figure 1 6 These

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22 issues demand for dynamic signal gain tracking and gain control algorithms which will help adjust the rate of gain correction in a spectrum -friendly manner and reduce out of band spectral emissions. 1. 2 Power Control Techniques in Mobile D evices Before we discuss various techniques employed by a mobile device to alter its power level, this section describes the various components of a mobile device an d the process by which the mobile device responds to commands from the base-station Figure 1 7 describes the primary sections of any mobile device. The device consists of a Radio Frequency IC (RFIC ) also known as the transceiver, the baseband modem proces sor which interacts with the base -station commands and is responsible for any audiovideo, data decoding and encoding and modulation algorithms. The RFIC's transmitter section receives the data bits from the modem and passes it through digital filtering st ages for pulse shaping and upsampling. The digital data is then converted into analog signals by the digital to analog converter (DAC) and then modulated into RF frequencies. The modulated signal passes through the variable gain driver amplifier (VGA) and transmitted to the base -station through the power amplifier (PA). When the signal is received from the base -station to the mobile device, the received RF signal is passed through a low -noise amplifier, and demodulated into a baseband signal. The analog si gnal is then converted to a digital signal by the analog to digital converter (ADC) [3] and passed into receive digital filter stages for further processing. The output bit stream from the filter stages is sent to the baseband processor for further decod ing. Depending on the nature of the signal (audio/video/data), the baseband processor performs the decoding algorithms and outputs the signal through the speaker or on the display.

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23 Figure 1 8 and Figure 1 9 shows measured transmit power changes captured b y communication testing equipment Rhode and Schwartz CMU 2000 [79] at the output of the mobile device. I n Figure 1 8, the mobile device is moving close to a base-station and hence the transmit power is decreased. Figure 1 9 shows a mobile responding to com mands from the base -station to increase or decrease its transmitting power level due to varying channel quality. 1. 3 Present Day Techniques and Prior Art The following approaches are adopted in present day mobile devices to dynamically provide gain change in response to commands from the base-station These approaches are either used in the mobile devices or in the base -station amplifiers to perform dynamic power control in order to increase signal quality and system capacity. Each of the approaches is ex plained below. 1.3.1 Use o f Fixed Calibrated Digital Gain Offset and Error Value s In this prior art [57] as a measure of power levels required for transmission and the signal quality requirements of the base -station pre-calibrated digital gain factors a nd offsets are applied to the digital signal paths to compensate for any gain errors in the transmit path. These calibrated values of gain and phase offsets are a function of desired power levels, operating frequency bands, battery voltage and temperature. The pre -calibrated gain and phase offsets are stored in digital memory look up tables and applied to the transmitter during signal transmission [4], [47]. This is a popularly adopted method to perform transmit power change in the mobile device or in base-station transmitters. In addition to the need for extensive calibrations, this approach places a huge demand on memory storage requirements. Also, this technique is an open loop

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24 method and cannot account for slow varying gain errors due to temperature unless separate temperature compensation circuits are used. 1.3.2 Use of Pre-Calibrated Analog Bias Signal for Constant Envelope Modulation In this prior art [65], the bias setting of the power amplifier or the driver amplifier is altered by digital control. T he digital control can be as simple as a ROM look up table or can be a ramp pattern that can be programmed with respect to operating power levels. This is a very popular technique which is still adopted for constant envelope modulation schemes such as GMSK (Gaussian Minimum shift keying). The bias voltage of the power amplifier is changed in order to effect a power change in the desired direction at the PA output. However, the final digital value needs to be calibrated as a function of desired power levels. As a limitation, this technique can only be used for constant envelope modulations schemes to satisfy linearity and efficiency tradeoffs [21 ] [ 36]. This technique is also an open loop method and cannot account for temperature based drifts in the signal power level unless temperature compensation circuits are used. 1.3.3 Use of RF Feedback and Analog Bias Control In this prior art [75] the transmitted RF power is fedback to a device called power detector which converts RF power into equivalent voltage s ignal. This fedback analog voltage signal is compared with an analog reference signal which is equivalent to the desired power level. The error between the reference signal and the feedback signal is used to alter the bias setting of the variable gain ampl ifier by using digital logic and decoder control [31], [53], [59 -64] This technique can be used for real -time gain control when the mobile device is transmitting signal power by monitoring the gain variations.

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25 Although this technique is widely used in present day mobile devices and base -station transmitters, it suffers from a few limitations It requires calibration of the bias correction factor for the VGA based on the error signals magnitude. The complexity of the analog circuits which generates the ref erence signal voltages increases with increase in the desired amount of dynamic range of gain control. 1.3.4 Use of RF Feedback and Temperature Compensation Circuit Based Gain Control In this technique [74] the RF power is looped back and sent into a receiver network which demodulates the RF signal and converts it to an equivalent analog voltage signal. The analog voltage signal is compared with an output signal generated by a temperature compensation circuit. Based on the error signal generated, a digital logic circuit is used to perform bias compensation on the driver amplifier or VGA. Thus, as a function of generated bias compensation, the transmit power of the mobile device is adjusted to account for the variation of any power change caused by circuit a nomalies. Though this circuit controls the power based on temperature changes, it cannot guarantee very fine resolution of gain control. 1. 4 Limitations of Prior Art To summarize, the limitations of the prior art techniques are as described below 1 They do not solve the spectrum leakage issue Since the gain correction is applied as a static compensation either at the digital or at the analog sections, these techniques can only provide instantaneous gain change and hence will cause spectrum splatter [4142], [48 -49], [51] as described in earlier section s. 2 There is no ability to control the rate at which the gain change is performed and hence there is no control on the amount of the time in which the power change has to be performed. 3 Local RF loop back solution does not provide infinite precision and c annot provide fine gain control accuracy due to analog circuits

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26 4 The prior art l ack compensation for any random phase variations Any random phase shift caused in the signal paths will lead to gain error and hence w ill degrade power accuracy. There is no dynamic compensation for relative phase shifts. 5 The prior art uses f ixed correction techniques Existing prior art techniques are static correction techniques and will need extensive calibration of gain and phase corr ection parameters 1. 5 Research Effort Comparisons Table 1 -1 describes the three new techniques and the compares their significance and applications 1 6 Organization of Thesis The organization of this thesis is described as follows: Chapter 2 describes th e possible causes for variations in both transmit and receive signal power levels of a mobile device. It describes DSP based a bsolute gain/power monitoring technique (DSP-DGT) using digital control loop and signal correlation circuitry to correct for gain variations introduced due to analog circuit imperfections. The DSP-DGT technique is implemented using digital signal processing hardware and system lab measurements are provided to validate the performance. The DSP -DGT technique is found to dynamically mon itor gain fluctuations in a mobile device introduced by analog circuit imperfections. Chapter 3 introduces a Discrete Fourier Transform (DFT) based DSP technique and hardware structures to compensate for the relative gain and phase errors and hence maintain relative power control accuracy (DSP -GPE). The DSP-GPE technique uses digital signal processing circuits to estimate the relative gain error (differential nonlinearity error,DNLE) caused by the analog RF gain amplifier. In addition to relative gain error compensation, this chapter also describes a method to calibrate the carrier

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27 phase changes that happen in any mobile device due to change in the capacitive load impedances on the RF analog path. The estimated relative carrier phase change is then applied as compensation when the mobile device transmits signal to the base -station This technique maintains the transmit power accurately by compensating for gain error introduced due to differential gain nonlinearity and relative phase shifts errors. System lab measurements are provided to illustrate the performance of the DSP -GPE technique. Chapter 4 describes a technique and DSP hardware structures to dynamically control the absolute signal power of any mobile device by using an adaptive DSP control along with an integral controller (DSP -G C ). The primary goal of the DSP -GC technique is to reduce the signal variances at input to the controller which are caused due to higher order modulation schemes. Reduction of signal variance makes the response of the closed l oop system more predictable and faster. A new loop tuning algorithm based on stability constraint method is defined and the controller gains are estimated for an unknown plant transfer function. The DSP -GC technique has also been implemented in a mobile device and lab measurements are provided. Chapter 5 provides the summary and conclusions of the thesis work. It also provides other areas where these techniques can be applied. In addition, it outlines the scope for further work and improvements that can be made depending on the applications.

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28 Transmit Power is increased to as the distance is large Base-station signal user to increase power level user is signaled to reduce Power level No change in user power level User is signaled to Transmit higher power Base-station signals user to reduce power level Figure 11. Power control signaling from base-station to mobile device Frequency ( MHz) Power (dBm)Signal energy at the base-station Without power control in a 11 user celluser11 user1 Figure 12. Occupancy of mobile users in frequency domain without power control

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29 Frequency ( MHz) Power (dBm)Signal energy at the base-station with power control in a 11 user celluser1 user2 user3 user11 Figure 13 Ideal gain control with no error in correction after power control Frequency ( MHz) Power (dBm)Power error tolerance upto +/-3dB Figure 14. Gain errors introduced due to analog/RF circuit imperfections as a function of operating conditions

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30 Abrupt power control without signal shaping leads to out of band spectrum leakage and leads to adjacent channel interference Mobile user at the band edge Carrier leakage Figure 15. Measured ad jacent channel interference due to abrupt power control without signal shaping captured by Agilent N9020A MXA s ignal a nalyzer Controller Power control based on signal shaping ( Reduce out of band spectrum ) Mobile user at the band edge Carrier leakage Signal image Figure 16. Lower spectral leakage due to power control with signal shaping captured by Agilent N902 0A MXA s ignal a nalyzer

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31 Figure 17. System level overview of a mobile device

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32 Upon signaling from base station, the transceiver reduces the power level transmitted. Figure 18. Reduction of signal power from the mobile device captured by Rhode and Schwartz CMU 2000 analyzer Due to varying channel quality, the base station could signal the mobile to increase or decrease the transmit signal power to maintain constant SIR F igure 19. Multiple power changes of the mobile device captured by Rhode and Schwartz CMU 2000 analyzer

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33 1010101100 VGA DAC DAC Tx Digital line up Symbols from Modem RFModulator Base Band FilterRF Pout (dBm) ROM LUT clk data temp PA ROM LUT data temp clk Figure 110. Prior art that uses fixed digital gain offsets and errors to perform digital gain control VGA DAC DAC Tx Digital line up Symbols from ModemRFModulator Base Band FilterRF Pout (dBm) ROM LUT DAC clk data tempbiasPA Figure 111. Prior art that adopts pre -calibrated analog bias levels for gain control and tracking

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34 PAVGA DAC DAC Tx Digital line up Symbols from Modem RFModulatorBase Band Filter RF Gain control RF Pout (dBm) RF Section1010101100 Detector DAC CONTROL LOGIC RC filter Summing amplifier Figure 112. Prior art that adopts RF feedback and coarse analog bias adjust PAVGA DAC DAC Tx Digital line up Symbols from Modem RFModulator Base Band Filter RF signal AmplifierRF Pout (dBm) RF Section1010101100 Receiver Bias control circuity Logic circuit Vdd 5V + Figure 113. Prior art that uses RF feedback and temperature compensation circuit for bias adjust

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35 Table 1 1. Comparison of New Techniques Significance and system comparison metrics Digital DSP Techniques and Efficient Hardware Topologies for Absolut e Gain Tracking (DSP DGT) DSP Based Dynamic Estimation and Compensation of Differential Gain Nonlinearity and Random phase shifts (DSP GPE) Dynamic Gain/Power Control Using Adaptive DSP Techniques (DSP GC) 1 Motivation Dynamically estimate and compensate for absolute gain variations and maintain average power level accuracy over time. Estimate and compensate for relative gain variations due to differential nonlinearitys and also helps to compensate for relative random phase shifts to preserve signal phas e variations Adaptive algorithm that minimizes the signal variances at the input to the controller and dynamically compensates for instantaneous gain variations and helps to perform signal power change based on desired reference power. 2 Underlying theory and principle Self generated tracking reference signal Delay alignment based on cross correlation Absolute gain tracking based on controller action Sliding DFT based signal energy and random phase shift estimation Baseband digital gain and phase compensa tion N Tap adaptive filter with programmable convergence factor for instantaneous gain tracking and reducing signal variance Integral controller for average gain tracking and control. 3 Targeted system performance metrics Mobile specifications Absolute/relative gain accuracy Adjacent channel interference ratio, in turn cell capacity requirements Gain change/settling time requirements. Cell capacity requirements Enhances battery life by performing mobile power tracking and compensation Mobile specification s Relative phase accuracy requirements. Relative gain accuracy and distortion nonlinearity requirements (between baseband processor and RFIC) Linearity requirements. (Power change vs. obtained command). Cell capacity requirements Enhances battery life by p erforming mobile power tracking and compensation Mobile specifications Absolute gain change/control requirements. Absolute power level accuracy Gain change and settling time requirements. Cell capacity requirements Enhances battery life by performing mobi le power tracking and compensation 4 Modulation schemes supported GMSK, WCDMA (QPSK, QAM, BPSK) (independent of modulation schemes) GMSK, WCDMA (QPSK, QAM, BPSK) (independent of modulation schemes) GMSK, WCDMA (QPSK, QAM, BPSK) (independent of modulation schemes) 5 Loop stability Fun ction of integral gains and the delay estimate based on cross correlation. Loop stability is not a concern. The main concern is quantization error that leads to gain errors. Function of the loop latency introduced and converg ence factor programmed along with integral gains

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36 Table 1 1. Continued Significance and system comparison metrics Digital DSP Techniques and Efficient Hardware Topologies for Absolute Gain Tracking (DSP DGT) DSP Based Dynamic Estimation and Compensation of Differential Gain Nonlinearity and Random phase shifts (DSP GPE) Dynamic Gain/Power Control Using Adaptive DSP Techniques (DSP GC) 6 System DSP hardware requirement & estimated gate count Existing external RF detector PID controller hardware DSP cros scorrelator Fast Signal Averager Fast magnitude estimator Delay buffer Sample rate adjust logic Pseudo random code generator 22K, 20mA Sliding DFT magnitude and phase estimator Baseband phase compensation DSP hardware RF loop back with existing demodulati on path <10K gates, 12mA N Tap adaptive filter Integral controller (Low pass filter) Error signal generator RF loopback with detector 17K gates,22mA 7 System lab measurements and performance Lab measurements show that the DSP DGT technique is abl e to compensate up to 0.1dB gain accuracy. Settling time of 50usec Lab measurements show that the DSP GPE technique is able to compensate up to 0.1dB of gain accuracy and phase accuracy of <1 degree. Power control accuracy of < 0.1dB accuracy is obtained Settling time decreased by 15usec to 35usec.

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37 C HAPTER 2 DIGITAL DSP TECHNIQUES AND EFFICIENT HAR DWARE TOPOLOGIES FOR ABSOLUTE GAIN TRACKING 2. 1 Problem Statement As mentioned in Chapter 1, power change commands are sent by the base -station to the mobile device to either increase or decrease its transmit power level. The base band processor present inside the mobile device decodes the command received from the base -station and provides internal gain change commands to either the digital or analog RF secti ons of the transmit path to provide the desired gain corrections. The desired gain correction can be performed by either changing the bias level of the VGA/PA or by changing the digital gains of the transmit path. There are three primary concerns associated with any gain control techniques adopted on a mobile device which requires analysis. 1 The gain changes performed by the mobile device must not be an instantaneous change to avoid spectral leakages to the neighboring user. 2 In addition to this issue, in mobile devices, there is always an error between the desired gain change and the actual gain change that occurred due to the circuit imperfections and performance variations of RF circuits as a function of temperature, frequency and battery voltages. 3 Another primary concern in any mobile device is to perform the desired power change as requested by the base -station and maintain the desired power level accuracy until the next power change is requested by the base -station For example on a WCDMA [23],[35] (wideband code division multiple access) system, a mobile user can be on a signal transmission for 45 hours continuously while moving around with respect the base -station. During these conditions, it is very critical for the mobile device to guarantee the desir ed gain accuracy and the power error allowance until a next power change command occurs. This chapter describes a DSP -based absolute gain/power monitoring and tracking technique (DSP -DGT) using digital control loop and signal correlation circuits to corre ct for gain variations introduced due to analog circuit imperfections. The DSP -DGT

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38 technique has been implemented using digital DSP hardware and system lab measurements have been provided to validate the performance. DSP hardware structures employed in thi s algorithm are described along with system measurements. 2. 2 Reasons for Signal Gain Variations in Mobile Devices Before we introduce solutions, it is important to investigate and understand the reasons for signal gain variations in any mobile device. The reasons for gain variations are discussed in the following section. 2.2.1 Gain variations due to Manufacturing P rocesses The performance of the baseband and RF components is a function of variations in manufacturing process. Although the components are manufactured according to a particular set of design specifications using defined manufacturing processes, nonuniform results may be obtained due to uncontrolled deviations in the processes used to fabricate the constituent semiconductor components. Typi cal cellular telephone designs attempt to locate the baseband DAC, ADC and RF components in different physical locations in the cellular telephone to avoid interference. One drawback of this design approach is that the process variations in the manufacturi ng phase of the components do not track one another. In a worst case scenario, the DAC, the ADC and RF components have a maximum variation in the same direction which results in a maximum total transmit gain deviation from the nominal transmit gain value. The measurements were performed inside a temperature chamber and averaged over three ICs. Figure 2 -2 shows that the m easured RF p ower level drops as the temperature increases This drop in RF output power will eventually degrade communication link perform ance and ultimately lead to lower signal to noise ratio [57, 60, and 62]

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39 2. 2.2 Power Gain V ariations due to Change i n Junction Temperature In amplifier design, the power gain of transistors used in an RF amplifier decreases with increasing junction temper ature of the transistors. Power transistors dissipate large amounts of power in the collector base junctions [26] Apart from change in ambient temperature, similar gain delta response s can also be induced by a change in the junction temperature of the power amplifier. The increase in junction temperature is usually associated with high output power operation. For example, at an output power of 28 dBm, the junction temperature of the power transistors will be increased due to higher dissipated DC power, while the junction temperature of the same power transistors will be lower at a lower output power (e.g. 16dBm). Figure 2 3 shows measured data of absolute RF power variations over low, mid and high frequency bands of operation across cold (35 degrees) roo m (+25degrees) and hot (+85 degrees) temperatures. Th e experiment reveals that as temperature increases the gain drops and the gain drop is not exactly same across frequency bands of operation. However, the gain drop due to frequency bands of operation is r elatively less as compared to gain drop due to temperature variations. The measurement results illustrated here is average of three ICs 2. 2.3 Change in Power Gain Due t o Different Operating Paths Depending o n Power Level Another reason for gain variations in multi mode amplifiers is due to the presence of parallel power paths. In the state of art of multi mode amplifier design, there exists independent parallel path to support different power levels, lower power and higher power paths. The higher power pa th may be used where the design requires an output power from about 16 to 28 dBm, and the lower power path may be used for power less

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40 than 16 dBm. One direct effect of the two (or more) power path design is that the device characteristics associated with e ach path are different since the electronic components in each path are different. For example, the active transistor sizes and DC currents in each path are different due to different power handling requirement for each path. These result in different elec trical and thermal responses between the two paths. More specifically, the two paths experience different gain variations over temperature, resulting in a gain mismatch between the two paths. 2. 2.4 Variation in Gain Due to Different Operating Frequencies and Supply Voltage Change in frequency and supply voltage of operation of any baseband or RF device will lead to change in DC operating point of the device, change in input impedances and change in the matching network. These will ultimately lead to gain v ariations due to supply voltage and frequency bands of operation. Figure 2 -4 and Figure 2 5 shows measured data that characterizes the gain drop across frequency bands of operation and battery voltage variations. 2. 3 DSP Based Dynamic Gain Tracking Algorit hm (DSP DGT) 2.3.1 System Architecture of the DSP DGT Algorithm The system algorithm described in this chapter dynamically compensates for absolute gain variations that are caused in any mobile system due to performance variations of RF and analog circuit s based on different manufacturing process, temperature and frequency bands of operation. The algorithm uses the magnitude of the digital base band signal as the reference input to the algorithm. The transmitted power is fedback and compared to the desired reference signal. An error signal is generated based on the difference between the average magnitude of the reference and the feedback signal. The error signal is used to drive a controller to generate a

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41 control signal that compensates for the gain diffe rences between the reference path and the feedback path. A cross-correlation circuit is used to time align the reference and the feedback path before the start of the controller operation. The introduced technique not only helps to compensate for gain vari ations but also helps in shaping the power change in a spectrum friendly way and avoids adjacent channel interference. The system block diagram of the DSP -DGT algorithm is shown in Figure 2 6 The digital IQ sample s pass through the digital filtering stage and get converted to an analog signal by the DAC The differential DAC output goes to the baseband reconstruction filte rs. The baseband filter outputs are converted to RF/IF frequencies depending on the applications (Cellular, Wireless local are network ( WLANS) or Audio signal paths) and passes through an RF gain amplifier stage and transmitted through a power amplifi er. There are two signal paths for the introduced system architecture, namely the feedback path and the feed forward path. 2. 3. 2 Feedback Pat h The output of the RF amplifier is fedback into a power detector [45],[56],[70] which takes in RF Power (dBm) and gives out corresponding DC voltage. The detector output is fedback i nto a variable gain block with an anti aliasing filter The output of the filter is quantized into digital word by an analog -digital converter (ADC). The variable feedback gain is chosen and implemented based on the input signal dynamic range of the ADC. Varying the feedback gain as a function of the RF power levels improves t he signal -to noise ratio of the feedback signal. The quantized digital word is then buffered and averaged by employing a digital fast averaging circ uit as will be described in section 2.5.4

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42 2. 3. 3 Forward Reference Path As shown in Figure 2 6, t he digital signal is tapped before the DAC and used as the reference signal for the alg orithm. The magnitude of the in -phase signal component and the quadrature signal component signals are estimated by the fast averaging hardware. The magnitude is then averaged b y u sing the exponential average DSP hardware and used as a reference signal to the proportional and integral controller. As shown in Figure 2 6 the closed loop feedback loop controller tracks for any change in gain variations between the feedback and the ref erence signal paths. As the ideal gain of the feedback path and the forward path is known, the gain of the reference signal path is calibrated accordingly. A digital cross-correlation circuit is employed to estimate the cross-correlation between the refer ence signal and the feedback signal to calibrate the delay buffer in the reference signal path. This helps in dynamically calibrating the delay between the reference and the feedback signal paths before the gain estimation and tracking is performed. The buffer control logic also adjusts for the sample rate differences between the forward path and feedback path signals. 2. 4 Algorithm Theory The block diagram of the described system architecture is shown in the Figure 2 -6. The components of the algorithm are described as follows. 1 Buffer control for sample r ate and block size adjustment ( DSP hardware) 2 Fast exponential averaging circuit(DSP hardware) 3 Fast magnitude estimation(DSP hardware) 4 Gain controller with proportional, integral and differential control ( DS P hardware) 5 Digital calibration signa l pattern generation circuit. ( DSP hardware) 6 Signal cross-correlation circuit. ( DSP hardware) 7 Feedback path power detector (RF discrete component) 8 Analog feedback gains ( analog baseband) 9 Ant aliasing filter and ADC ( analog baseband)

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43 The baseband modem sends the information bits from the base band processor into the digital path stages inside the RFIC The digital stages have pulse shaping filters to reduce inter -symbol interference (ISI) [23] and multi -rate filters to al ter the sampling frequency of the filters in accordance to the available clock rates and the DAC operating rates. As shown in Figure 2 6, assume that the base band I channel and Q channel signals are represented by ) ) cos(( 1 ) ( n d n Ibb (2 1) ) ) sin(( 1 ) ( n d n Qbb (2 2) where 1 d is the digital gain, bb is the baseband signal frequency. The signals ) ( n I and ) ( n Q are converted to analog sign als ) ( t I and ) ( t Q by the DAC present in the transmit path. The signals are then up converted by the RF modulator. The input to the modulator is then up converted to RF frequency and can be expressed as rft j bb bbe t j t d )] ) sin(( ) ) [(cos(( 1 modout(t) (2 -3a) where wrf is the up conversion frequency. The output of the modulator is amplified by the PA and transmitted over the antenna. The signal transmitted over the antenna can be represented as rft j bb bbe t j t d G )] ) sin(( ) ) [(cos(( 1 1 PA(t) (2 3b) where, 1 G is the power amplifier gain. The magnitude of the power in dBm (dB with respect to 1mW) at the output of the PA is represented as dBm Q I d G dBm Pout 30 ]) [ 1 1 log( 10 ) (2 2 (2 -4)

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44 The output of the power amplifier is converted into an equivalent DC voltage s ignal by using an RF power detector which converts RF power (dBm) into average DC voltage. The power detector outputs linear DC voltage for RF input power in dBm. The output of the detector in volts is approximated to be the envelope of the signal power an d denoted as ]) ([ ) (2 2Q I abs t v (2 -5) where, is the feedback path gain. Controller theory, Flow chart of the algorithm The algorithm employs a PID controller to dynamically track for any absolute gain variations in any closed loop feedback system. L iteratur e about any PID controller can be found in [ 71 ]. In our applications, we exploit the benefits of this controller to dynamically track gain variations. A secondorder closed-loop PID controller is shown in Figure 2 8 T he plant transfer function for a second order system is is given by ) )( ( ) (2 1p s p s G s Dp (2 6a) where 1p and 2p are syste m poles Replacing j s in Equation 2 -6(a) results in ) )( ( ) (2 1p j p j G s Dp (2 -6b) The reference signal input to the system is defined by )( s R and the system output is represented by ) ( s Y and is the feedback gain. The proportional, derivative and the integral gains are represented by pK DK andIK. The error signal between )( s R and the feedback signal ) ( s Y is represented by ) ( s E Hence,

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45 ) s ( Y ) s ( R) s ( E The controller output ) (s P is represented by ) ( 1 ) ( ) ) ( ( ) ( s E K s s KpE K ssE sPI D (2 7) Solving for the time constants, ) )( ( ) ( ) ( ) (2 1p s p s G s A s P s Yp ] 1 ) )[( ( ) (I DK s Kp sK s E s P ) )( ( ) ( ] 1 ) )[( ( ) (2 1p s p s G s A K s Kp sK s E s Yp I D ) )( ( ] ) )( ( )[ ( ) (2 1 2 1p s p s K AG s s s s E s YD p 2 4 ,2 2 1 D I D p D pK K K K K K where (2 8) ) )( ( ] ) )( ( )[ ( ) (2 1 2 1p s p s K AG s s s s E s YD p D pK AG s s s Y p s p s s s E ) )( ( ) ( ) )( ( ) (2 1 2 1 ) ( ) ( ) ( s Y s R s E ) ( ) ( ) )( ( ) )( (2 1 2 1s R s Y K AG s s p s p s sD p ) ( ) )( ( ) )( ( ) )( ( ) (2 1 2 1 2 1s R K AG s s p s p s s K AG s s s YD p D p (2 -9)

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46 Assume that the input ) ( t R is a unit step, and can be represented as ) () ( t Ru t R s R s R ) ( (2 10) s R K AG s s p s p s s K AG s s s YD p D p) )( ( ) )( ( ) )( ( ) (2 1 2 1 2 1 At steady state the final value s R K AG s s p s p s s K AG s ss s s sY t t yD p D p) )( ( ) )( ( ) )( (0 | ) ( 0 | ) (2 1 2 1 2 1 D p D pK AG R K AG s s sY ) )( ( ) )( ( 0 | ) (2 1 2 1 R s s sY t Ysss 0| ) ( ) ( (2 11) Equation 2 11 shows that the steady state value of ) ( t y is equal to the ratio of the amplitude of the input and the feedback gains. When the system reaches s teady state, the error signal ) ( t e = 0 and the feedback signal ) ( ) ( s R s Y In the presence of external disturbances in gain g Gp due to temperature and operating conditions, the controller tries to track for any additional gain variations g as described in t he above Equations The system simulation with a simple controller proves the theory of operation. The rise time, the maximum peak overshoot and the settling time depend on the controller gains selected and the application. A detailed illustration of the c ontroller operation and corresponding loop dynamics for a positive and a negative gain change is shown in Figure 2 9 and 210 respectively. The flowchart of the DSP DGT technique is described in Figure 2 11.

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47 2.5 DSP Hardware Structures for the DSP DGT Algo rithm The following sections describe the DSP hardware structure adopted to implement the algorithm. 2. 5.1 Digital Calibration Signal Pattern Generator In order to calibrate the delay between the reference path and the feedback path signals, signal cross-correlation hardware is employed in the described algorithm As a part of the cross-correlation operation, a digital calibration signal is applied as the reference input signal. This results in a corresponding feedback signal through the transmit path. Si gnal cross-correlation between the reference path and the feedback path signals is estimated based on which the group delay is estimated. Figure 2 12 shows the hardware used to generate the digital calibration signal by using a linear fe edback shift regist er topology. T he DSP hardware uses a 6 stage flip flop bank. The circuit consists of flip flops with load capability as shown in Figure 2 -12. An initial binary value is loaded into the flip flop. As described in [72] for a 6 stage linear feedback shift register, the output of the 6th and the 5th flip flop is fe dback to an XOR gate. The output of the XOR gate feeds the 1st flip flop. The output of each flip flop is tapped serially by using a multiplexer which is controlled by a clock signal which is operating at 6 times faster than the flip flop clocks. This results in tapping out the output as a 6 b it word serially as shown in Figure 2 14 2. 5.2 Digital Sample Rate Adjust Logic In the described DSP -DGT algorithm, it is essential to bring the forward path sig nal and the feedback path signal to the same sample rate before cross-correlation is estimated. In our system architecture, we assume that the sample rate of the ADC present in the feedback path higher than the forward path signal. Hence, to

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48 downsample the forward path signal downsample hardware is required. The DSP hardware with programmable downsample factor is shown in Figure 2 -15. The circuit adopted consists of a modulo N counter, (where N is the downsample ratio), a multiplexe r, a flip -flop and a couple of comparators. As shown in Figure 2 -15, w hen the output of the counter reaches 0, a control signal is generated and used to control the multiplexer which pipes in the input data into the flip flop, when the control signal is 0, and th en the current data sample is held. This repeats the data at the output of the flop and h ence performs downsample operation by losing every N sample s. 2.5.3 Magnitude Estimator The signal magnitude of the forward reference path is estimated by the fast magnitude estimator cir cuit [73]. This is a linear approximation to the vector magnitude problem that requires determining which of the orthogonal vector, I or Q, has greater absolute value. If the maximum absolute value of I or Q is designated by Max and the minimum v alue of either I or Q is designated as Min, an approximation of | ) ( Q I Mag | is expressed as Min Max Q I Mag | ) ( | (2 12) There are several pairs for and constants that provide varying degrees of vector magnitude approximation accuracy to within 0.1dB [73]. If I and Q are the in -phase and quadrat ur e phase signals, then the magnitude of the I and Q is represented by ) | |, min(| ) | |, max(| ) (2 2Q I Q I Q I Q I Magest (2 -13) The DSP implementation of the fast magnitude estimator is shown in Figure 2 20. The adopted hardware structure is a combinational logic and designed without any multiplier to make the area smaller. The adopted structure includes shift registers and

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49 adders and hence reduces digital gate area. The DSP hardware designed for this purpose consists of the following four individual blocks. Absolute value estimation The hardware to calculate the absolute value is implemented as described below. Assume that the signal ) (n x is a 14 -bit signed number represented as <14, 0, t> (14 bits 0 integers and 1 sign bit). The digital hardware takes in the signed number and if the sign bit is set, then number is inverted and incremented by 1.0 else the same signed number is sent at the output. Bitwise compare. The DSP hardware for bitwise compare is described in Figure 2 -19. The input signal which has to be compared is subtracted and the most significant bit ( MSB) is extracted and used to control a multiplexer. If the MSB is set to 1, then the output of the multiplexer is ) ( I abs which the maximum of the two numbers is, else if the MSB is zero, then the multiplexer outputs ) ( Q abs Multiplication and Division By And The multiplication by factors are implemented by shift right or shift left logic. In our case, the values for and we selected are 64 61 = and 32 12 The multiplication by 64 61 and 32 12 can be realized by representing 61 as 64 )) 1 2 ( ) 1 4 ( 4 ( 64 ) 3 2 2 5 ( 64 ) 1 60 ( 64 61 and 32 )) 1 2 ( 4 ( 32 ) 3 4 ( 32 12 Multiplication by 4 is implemented by shifting the input signal left by 2, and multiplication by (4+1) can be implemented by again shifting the input signal left by 2 and adding the signal to it as shown in the Figure 2 -20 Divi sion of a number by 64 and 32 is realized by

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50 shifting the input signal right 6 and 5 respectively. Let I and Q be uniformly distributed random signal s with mean 0 and variance of 0.335. The magnitude of I and Q is estimated by the abo ve hardware. ) | |, min(| 32 12 ) | |, max(| 64 61 ) (2 2Q I Q I Q I Q I Magest (2 -14) Figure 2 21 shows the ideal signal magnitude and the estimated signal magnitude. If the ideal magnitude is defined by idealQ I Mag | ) ( | and the estimated signal magnitude is defined by| ) ( |estQ I Mag, then the Magnitude error is calculated by 2 2) | ) ( (| | ) ( | | ) ( | _ideal est idealQ I Mag Q I Mag Q I Mag error Mag (2 15) The plot of error Mag is shown in the Figure 2 21 for 1000 samples of I and Q random vector. The DSP -DGT algorithm requires block based magnitude estimation r ather than instantaneous magnitude. Depending on the size of the input buffer, the magnitude estimator calculates the signal magnitude and updates the register at every block rate. Figure 2 -22 shows the magnitude of quantized I and Q samples of 12 bits each. Also, shown in Figure 2 22 is the estimated block magnitude for every 200 sample buffer length. The block based magnitude estimat ion error is found to be within the system specification of 0.08dB The simulations show the magnitude error in dB for 5 consecutive buffers of 200 samples of I and Q signals is within the desired specifications.The simulation shows that the magnitude error reduces with increase in buffer sizes. Hence, the selection of the buffer sizes based on the signal variances is an important aspect of this system topology. Simulations show that as the buffer size increases, the error in magnitude estimation decreases. Hence depending on the loop

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51 operating sample rate and the rate of adaptation, an appropriate buffer size can be chosen 2.5.4 Fast Exponential Averager The fast average DSP hardware employs an exponential averaging technique. The hardware is used to estimate the magnitude of the digital I channel and Q channel signals. Although other t ypes of signal averaging techniques exists [ 37],[44],[50] the primary reasons for adopting this structure to perform fast average are 1) Capability to vary the amount of noise reduction and the response time by changing the value of the filter factor. 2) Easy to implement with one or two flip flops, shift registers and an adder. The system block diagram of the adopted exponential averager is shown Figure 2 24. The input ) ( n x is scaled by a factor a known as the filt er factor. The multiplied input is added to the delayed version of output scaled by ) 1 ( a as expressed in Equation 2 17. By adopting this structure depending on the variance of the input signal, the final average estimate is either made dependent on the last averaged sample or on the new input sample by selecting proper values of a. Assuming that the value of a must be within 0 and 1, if the value chosen for a is close to 0, then the output averag e estimate is more dependent on the past average estimate else it is more dependent on the new input sample. ) 1 ( ) 1 ( ) ( ) ( n y a n ax n y (2 -17) To estimate the transfer function, we take z transform. 1 1) 1 ( 1 ) ( ) ( ) ( ] ) 1 ( 1 )[ ( z a a z X z Y z aX z a z Y (2 16)

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52 The transfer function reveals that the system has no zeros and clearly shows that it is a low pass filter. The value of the filter factor decides the settling time of t he filter and also the amount of noise reduction. The smaller the value of a, the more noise reduction is obtained. However, with smaller values of a the averager responds slower. Hence the trade off of this structure is that the more noise reduction we need, the more sluggish the averager will respond. The following plot describes the settling time of the averager to a random varying input signal whose mean is 0.195. The signal noise (SNR) performance of the averager as a function of the filter factor a, can be described as [73] a a SNR Variance noise Ouput Filter Variance noise Ouput Filter 2 (2 -17) Due to the above mentioned trade offs between settling time and SNR a more appropriate method of varying the filter factor has been described as follows A relatively large filter factor is use d at the beginning of the measurement so that the averager immediately responds to the filter s input and then the filter factor is reduced slowly to improve noise performance of the averager. The filter factor can be reset to zero at the end of every signal transmission. This is illustrated in Figure 2 -26 for a random input signal with mean of 0.195. Figure 2 -26 illustrates the use of the varying filter factor in the exponential averager. A higher filter factor is used at the start of measurement, and the value is decreased as the measurement proceeds. This results in faster averager response time at the start of the measurement and as the measurement proceeds the averager is slowed down by using a lower filter factor for better noise reduction. The freque ncy response of the single stage averager is illustrated in Figure 2 -27. The bandwidth of the averager reduces as the filter factor

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53 reduces. This means that the step response of the averager has a slower response time at lower filter factors An alternate strategy that can be adopted is by having a two stage filter structure with timer enables. The first filter is enabled at time 1t with a filter factor, a and after the filter settles, a second filter is enabled at time ) (1 2 2t t t with a filter factor b This cascade architecture will also help in meeting the response time and noise tradeoffs. Once the first filter settles, the second filter will be enabled to reduce the variance at the first filters output. The block diagram is illustrated in Figure 2 28. The input output e quation of the second filter is represented as ) 1 ( ) 1 ( ) ( ) (2 2 n y b n by n y (2 -18) Applying z transform, the transfer function of the cascade is represented by ] ) 1 ( 1 ][ ) 1 ( 1 [ ) ( ) (1 1 2 z b z a b a z X z Y (2 19) Equation 2 19 shows that the filter output is a function of the two filter factors a and b This structure helps in better average estimate if the i nput signal has relatively higher variances. The output of the second averager is shown in Figure 2 29 2. 5.5 Digital PID controller The hardware implementation of the PID controller is shown in Figure 2 -30 This circuit is used to integrate the error sign al between the reference path and the feedback signal path and the controller output is used to adjust the digital or the analog gain stage of the transmit path. If ) ( n e is the input to the controller and IK Kp and DK are the proportional, integral and derivative gain, then the output of the controller, ) ( n p is represented as

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54 ) 1 ( ) ( ) 1 ( ) ( ] ) ( [ ) (1 1 1 z K n e z z K n e Kp n e n pD I (2 20) The PID controller is implemented with three adders and two flip flops clocked at the desired sample rate. To avoid the use of multipliers, the integral, derivative and the proportional gain stages are implemented by shift add depending on the required gain values. The DSP hardware segment for the gain block s are shown in the T able 2 -2 and Figure 2 31. The integral, proportional and derivative gains for the PID controller are implemented based on shift and add logic [24]. For a gain of -6dB, the signal is shifted right by a factor of 2 and for a gain of 8.53dB, the signal is separately shifted right by 4 and shifted right by 8 and then added together to get 8.53dB. Depending on the 4 bit signal gain_cont<4>, the required gain values are selected and applied to the input signal. The values of the shift and t he combination of the additions can be changed to get different desired gain values. 2 .5.6 Cross -Correlator Hardware Before the gain tracking algorithm is enabled it is essential to calibrate the delays between the forward and the feedback path. Calibrat ion of the delay will help in aligning the f eedback and the reference path signals In addition it will help to preserve loop stability and enhance the settling time of the algorithm. As a first step, a calibration signal is fed into the digital path and t he cross-correlation between the outputs of the forward path signals and the feedback path signals due to the calibration signal is estimated. The time of occurrence of the maximum correlation estimate is dynamically found by the time -delay counter and bas ed on the time index estimate the delay is calculated with the knowledge of the operating sample rate This calculated delay is then applied to the reference path delay buffer as shown in the Figure 2 7 If ) ( n x is the

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55 calibration signal at the forward path and ) ( n y is the feedback signal, the crosscorrelation ) (k Rxy is given by 1 0) ( )( 1 ) (M nn y k n x M k Rxy where 1 ..1 0 M k (2 -21) To calibrate the delay buffer, a known calibration signal can be used before the actual gain tracking algorithm. The hardware to generate the calibration signal was described in section 2.5.12 and shown in the Figure 2 13. Also, as an alternate strategy, depending on the type of modulation employed, the actual tr ansmitted signal can be used to dynamically calibrate the delay buffer by finding the cross-correlation between the forward path and the feedback signals. The implemented digital DSP hardware structure for the k = 12 sample lag correlat or is shown in Figure 2 -32 The digital circuit consists of delay logic, multipliers, adders and multiplexers. The input signal ) ( n x from the reference path passes through a bank of delay registers clocked at the sampling frequency Fs The reference path signals ) ( n x ) 1 ( n x ) ( k n x are then simultaneously multiplied by the feedback signal ) ( n y which will be delayed and the scaled version of the ref erence path signal. The outputs of the respective multipliers are denoted as ) ( ) ( n y k n x corresponding to the respective signal lag k Each of the m ultiplier outputs is accumulated over M sample to res ult in the signal 1 0) ( ) ( ) (M nn y k nx k Rxy Th e output is then scaled by M 1 which is implemented by a shift right block The final output values of each of the signal lags are latched into flops and stored. The latched values are then used by the

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56 software code and the correlation index corresponding to the maximum value is estimated. Thus, the maximum correlation index max k can be estimated as follows ) ) ( ) ( max( )) ( max(1 0 max M nn y k n x k Rxy k (2 -22) The estimated delay index sF kmax is the calibrated feedback path delay at the instant of maximum correlation as shown in the simulations. The detailed DSP hardware structure adopted for a 12 tap cross -correlator [17 -19],[25] is shown in Figure 2 32. The corresponding multiplexer logic is shown in Table 2 3. The assumption of this correlation approach is to use either a calibration signal generated from the random signal generator hardware or to use the actual transmit signal by itself. These two approaches are simu lated and the results are presented in the following sections 2.5.6.1 Simulations with the cross -correlation DSP h ardware Figure 2 33 shows the calibration signal (blue) and the feedback signal (in red). The calibration signal in the reference path is del ayed at every clock cycle and the correlation estimate is calculated. The size of the correlator is decided based on the maximum expected lag based on system simulation and the application. The delay tracking counter keep track of the time at which the ma ximum correlation estimate occurs and based on the sampling frequency, the delay estimate is calculated corresponding to the maximum estimate. This delay estimate is then applied to the delay buffer to align the forward and feedback paths. Figure 2 -34 show s the correlation estimate at the output of correlator based on system simulations. Apart from using the calibration signal to detect the delay between the forward path and the feedback paths, we can exploit the correlation properties of the

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57 baseband signa l and perform dynamic cross-correlation to estimate the delay between the reference and the feedback signal paths Hence, d epending on the type of modulation schemes used, the baseband signal can be adopted and the crosscorrelation between the forward pat h and the feedback path signals can estimated to calibrate the delay dynamically. Figure 2 35 shows a buffer of 120 samples of baseband signal envelope. The data is simulated from a typical WCDMA channel case according to the mobile device specifications. The sample rate is 62.4MHz and each of the buffer size is 120 samples, which is about 1.92usec of data. As described in earlier sections the baseband analog signal passes through the RF mixer, amplified by the PA and transmitted at the output of the mobile device The transmitted RF power output is fed back through the power detector as described in earlier sections. The detected power from the PA is fedback through the analog gain stages and sampled with the ADC depending on the sample rate selected Figur e 2 36 shows the detected signal at the output of the ADC This signal can be assumed as a delayed and scaled version of the baseband signal envelope as the feedback signal passes through an envelope detector and gets scaled by feedback gains. Figure 2 -37 shows the signal cross-correlation between the baseband signal envelope and the detected signal. Signal correlation is performed between the block of the baseband signal envelope and the delayed and the scaled fedback signal The correlation index results in peak estimate when the signal pattern overlaps. Based on the signal correlation estimate, the delay between these two paths is estimated. Figure 2 38 shows the gain and time aligned version of the detected and the reference baseband signal envelope. The estimated

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58 time delay can be employed in any of the conventional system architecture or integrator based closed -loop power control architecture. The red curve in Figure 2 38 is the baseband signal envelope and the blue curve is the gain scaled and time aligned detected signal after delay and gain estimation. This shows accurate prediction of the delay and gains based on the signal correlation algorithm. 2.5.6.2 Correlation e s timates at varying s ample r ates Depending on the operating rates of the ADC, the de tected signal has to be downsampled before performing sign al correlation. The difference in the operating sample rates between the reference path and the feedback path will alter the correlation estimate. Hence for desired correlation accuracy there will b e a limitation place d on the downsample limit. The digital logic circuit described in section 2.5.2 shows how the reference signal is downsampled. Hence the sample rates of either the forward path signal or the feedback path signal will be adjusted befor e estimating the correlation. Figure 2 39 2 42 illustrate s the performance of the correlation circuit at different downsample rations of 2, 5, 10, 15 and 20. If ) ( n x is the forward path signal at sample rate Fs and ) ( n y is the feedback path signal at sample rate Fs N 1 then the factor N is the oversampling/ downsampling factor. In these situations, the sample rates of the signals are adjusted to be the same before the correlation is estimated. If Nn x ) ( denote s the signal ) ( n x downsampled by N and ) ( n y is the feedback signal, then the correlation estimate between the downsampled ) ( n x and ) ( n y is represented as 1 0) ( ) ( 1 ) (M n Nn y k n x M k y Rx where 1 .. 1 0 M k (2 23)

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59 Simulations reveal that we can derive normalized cross-correlation estimate even with sample rate differences of 1/20 between the baseband signal envelope and the feedback signal. Based on the signal correlation estimate, the peak of the signal and hence the delay between the baseband and the feedback signal can be calculated. 2.6 Top Level System Simulations and Measured Lab Results 2.6.1 System Simulations System simulations for the DSP -DGT algorithm have been performed in Matlab and fixed point digital tools known as Signal Processing Workstation (SPW). The detailed system parameters and simulation conditions are as follows 1 Baseband analog system models such as baseband filters, DAC with quantization and noise models [20],[21]. 2 Digital fixed point filter models for the pulse shaping and multi -rate digital filter stages. 3 Phase noise models for the voltage controlled oscillators 4 Power amplifier and RF discrete driver amplifier model with nonli near ties such as 1dB compression point, third and second intercept products. 5 Measured data of power detectors, PA and driver amplifier including slope variations based on temperature and frequency of operation. 6 Phase and gain variation response for the an alog RF circuitry. 7 Digital fixed point models for the described DSP hardware. 8 Different modulation formats as input signals such as GSM, WCDMA, EDGE [36] and OFDM [15] Figure 2 43 shows the magnitude of the reference path signal ) ( n x in blue and the magnitude of the feedback signal ) ( n y with injected gain variation of +6dB. The mean of the reference signal is shown in black. As shown in Figure 2 -46, the closed loop system can track for gain variations and compensate fo r the positive gain variation.

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60 Figure 2 44 shows the response of the closed loop system which tries to compensate for the positive 6dB gain variation injected into the system. The error signal between the reference path and the feedback signal magnitude i s calculated and the controller is updated based on the buffer rate selected. The rate of change of the error signal, the peak overshoot and the steady state error is decided by the selected integral, derivative and proportional gains. This controller output is either digitally applied to the forward path signal or converted to an analog equivalent signal and applied as gain control on to the RF amplifier stages as bias control. Figure 2 45 shows the response of the closed -loop system for a single gain step as a function of integral gains. The philosophy adopted in the described DSP -DGT algorithm is to fix the derivative and the proportional gains and vary the integral gains as a function of variance of the error signal, the desired settling time and desired steady state error. Figure 2 -46 shows the convergence of the closed loop system to track out a positive 6dB gain variation injected into the system. As the closed -loop system is enabled, the averaged value of the error signal between the reference path and the feedback path is inputted into the controller. As shown in earlier equations at steady state the controller output provides a compensation signal in response to the sign of the error signal. In this simulation, a 6dB gain variation is added onto the f eedback path and hence this provides a negative error signal. The negative error signal input into the controller make the controller output provide a compensation signal which tries to bring the error back to zero at steady state. The controller update is shown in Figure 2 -44 brings back the signal power to the desired level as shown in Figure 2 46.

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61 2.6.2 Mobile Testing and Lab M easurements In order to measure the transmit power at the output of the RF IC, the mobile IC is mounted on a 7 layer evaluation radio board. The transmit RF ports are connected to communication testing equipments to measure the signal power. In order to measure the digital signal, a signal oscilloscope is used. Digital test ports which are present on the mobile are connected to the digital oscilloscope and the internal reference signals are used as trigger to perform single shot capture. National Instruments LabView [81] is the software tool which was used to send commands to the RF IC that will mimic the baseband processor and the base -station controller. This software is installed to the computer and the evaluation board was connected to the computer using a Universal Serial Bus ( USB) interface. Figure 2 -49 describes the interface between the mobile IC, the external PA, the comput er and the testing equipments The digital controller outputs are converted to analog signal by either an internal or an external DAC and the applied as bias voltages for the PA. The analog signals are captured by an analog oscilloscope and the RF power is monitored by using c ommunication testing equipments. The make and the model numbers of communication testing and measurement equipments used in this work are: Rhode and Schwartz (R&S) CMU200 Universal Radio Communication Tester [79] Rhode and Schwartz (R& S) FSQ Signal Analyzer [80] Tektronix TDS3034B Oscilloscope [ 83]. Agilent N9020A MXA signal analyzer [82]. Figure s 2 50 to Figure 2 -53 captures the measured analog signal at the output of the loop controller. This signal is applied as a bias control signal either to the PA or the VGA

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62 to provide gain control depending on the adopted transmit path architecture. In other applications, the digital controller output is used to alter the digital gain of the transmit signal path. Figure 2 54 shows the measured out put of the mobile device (using FSIQ testing equipment) whose RF power changes from a lower power level to 22dBm employing the DSP -DGT algorithm. It is clear from Figure 2 54 that the rate of change of signal power ramp is determined by the controller gains used. Depending on the application and based on the peak overshoot and steady state error requirements, the controller gains are selected. In addition of dynamic absolute gain tracking this circuit can also be used to perform a power change as will be de scribed in Chapter 4. 2.7 Summary 1 The DSP -DGT technique provides gain monitoring and compensation of absolute power variations in mobile devices due to imperfections introduced due to analog and RF circuits inside a mobile device. 2 System simulations and l ab measurements show that the algorithm is provides gain control better than 0.1dB accuracy 3 Approximate gate count of the implementation is within the allotted 22K. 4 The described approach does not require separate reference generation circuitry as the ba se band signals are used as self reference. 5 The implemented algorithm is found to be independent of modulation schemes employed. 6 This technique however does not compensate for relative gain and phase error introduced by RF circuits which will be dealt in C hapter 3

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63 PAVGA DAC Filter DAC Tx Digital line up Symbols from Modem Base-Band Gain controlRFModulator RF Gain control I channel Q channel RF Pout (dBm)RF Section 1010101100 ) cos( ) ( t t IBB ) sin( ) ( t t QBB 1D ) (k j ke G Baseband section Digital Section Figure 2 1 Primary sections of a mobile device transmitter Absolute RF Power variation ( dBm) due to temperature variations ( Average of 3 IC's) 3.3 3.5 3.7 3.9 4.1 4.3 4.5 plus 25 deg(meas1) plus 25 deg(meas2) plus 25 deg(meas3) plus 25 deg(meas3) plus 45 deg(meas1) plus 45 deg(meas2) plus 45 deg(meas3) plus 85 deg(meas1) plus 85 deg(meas2) plus 85 deg(meas3) Temperature Sweep in temp chamber ( room temp to plus 85 degrees) RF Power (dBm) absolute ~ 0.8dB gain variation across temperature Temperature sweep (25degress to 85 degrees) RF power (dBm) Figure 22. Absolute RF Power v ariation in dB due to temperature variations averaged over three parts

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64 1 1.5 2 2.5 3 3.5 4 4.5 5 Frequency Bands of operation RF Power (dBm) absolute variation min_30deg room_temp plus_85deg min_30deg 3.993 4.77 4.561 room_temp 4.259 4.116 3.912 plus_85deg 2.987 3.218 2.985 low_band mid_band high_band Frequency bands of operation RF Power (dBm) Figure 23. Pout variations across frequency bands over temperature Absolute RF Power variations ( dBm) due to frequency of operation ( average of 3 IC's) 3.8 3.85 3.9 3.95 4 4.05 4.1 4.15 4.2 4.25 4.3 low band (channel 1) low band (channel 2) low band (channel 3) low band (channel 4) mid band (channel 1) mid band (channel 2) mid band (channel 3) mid band (channel 1) high band(channel 2) high band(channel 3) Power level (dBm) Frequency bands of operation Figure 24. Absolute RF power variations in dB due to frequency of operation

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65 Pout Variations across frequency bands over supply voltage average of 3 parts 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 Frequency Bands of operation RF Power (dBm) absolute variation 2.5V 3.0V 3.5V 2.5V 4.114 3.989 3.759 3.0V 4.259 4.116 3.912 3.5V 4.372 4.275 4.044 low_band mid_band high_band Power level (dBm) Frequency bands of operation Figure 25. Pout variations across frequency bands over supply voltage

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66 GejwRFt RF Mixer PA VGA Filter DAC Filter DAC _gain ADC Tx Digital line up Filter Symbols from Modem 10101010101 RF Gain control amplifier Power Detector Buffer control and sample rate adjust Signal Average Power Estimation Correlation Estimate Time index corresponding to maximum estimate 0 1 Delay_cal_en Delay buffer 0 Fast Magnitude estimator Signal Average Power Estimation Delay_cal_en ) S ( R ) S ( Y Gain controller Calibration Signal generator Digital to Analog convertern bit I n bit QRF dBm to DC Voltagedetection Dynamic Gain adjust signal y(n) Rxy(k) K(max)0 0Gain control Forward path Feedback path1 1 2 2) ( Q I Q I Mag MQ I Mag2| ) ( | I Q Figure 26. Sys tem level block diagram of the DSP -DGT architecture

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67 ) p S )( p S ( Gp 2 1 pk Ik Ik 1/S S + + + + -Calibration signal ) S ( A ) s ( Y ) S ( Y DAC ADC Magnitude Estimation Signal Buffering & Sample rate adjust Signal Average Power Estimation Correlation Estimate Time index corresponding to maximum estimate Tx Signal 0 1 Delay_cal_en Aliasing FIlter Delay buffer ) S ( R Signal Average Power Estimation Delay_cal_en 0 1 Calibration Gain(K) Feedback signal System Output Controller Feedback gain Simplified Plant Model 0 Figure 27. Controller adopted for the closed loop DSP-DGT algorithm

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68 ) p S )( p S ( Gp 2 1 pk Dk Ik s s 1 + + + ) s ( R Reference Signal+ ) s ( A ) s ( Y ) s ( Y ) s ( E ) s ( P Figure 28 Second order closed loop PID controller

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69 avg_enable controller_clksForward path magnitude ) (t Y Feedback path signal magnitude Controller error signal E(t) Controller output Y(t) ) ( t R Undesired gain change due to PA/VGA/ baseband Controller corrections Until the error reaches zero Error signal into the controller Error signal reaches back to zero The PA output reaches back to desired level Figure 29. Closed -loop dynamics when the controller compensates for undesired positive gain change

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70 avg_enable controller_clksForward path magnitude ) ( t Y Feedback path signal magnitude Controller error signal E(t) Controller output Y(t) ) ( t R Undesired gain change due to PA/VGA/ baseband Controller corrections Until the error reaches zero Error signal into the controller Error signal reaches back to zero The PA output reaches back to desired level Controller output reaches To desired level until error becomes zero Figure 210. Closed-loop dynamics when the controller compensates for an undesired n egative gain change

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71 Enable digital clocks Set the digital baseband gain to be D1 1) Enable cal_enable signal This forces the calibration signal into the I channel and the Q channel This cuts off any signal into the reference path. 2) Enable Power detector 3) Enable ADC 4) Enable Cross correlator hardware 5) Enable magnitude estimator Enable calibration generator and send signal into I channel and the Q channel Set RF upconversion frequency to be WTx 1) Disable cal_enable signal 2) Start Transmission of data bits into I and Q channels, depending on modulation 3) Disable cross correlator path 4) Enable signal averager DSP hardware 5) Enable Controller after programming nominal loop gains Estimate Cross Correlation between reference path x(n) and feedback path signals y(n) 1 0) ( ) ( 1 ) (M nn y k n x M k Rxy Detect peak of correlation and apply the delay in the reference path to align feedback and reference path signals Control timing accurately for average enables and loop update rate. 1) Loop can update every sample 2) Loop can update every M samples Loop adapts and Additional disturbances are tracked and hence gain dynamic gain compensation is performed as loop error signal goes to zero Figure 211. Flow chart of the steps involved in the DSP -DGT algorithm

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72 Q QSET CLRS R Q QSET CLRS R MUX MUX MUX Q QSET CLRS R Q QSET CLRS R MUX MUX Q QSET CLRS R Q QSET CLRS R MUX load1 0 0 0 0 0 0 1 1 1 1 1 MUX 6 times faster clk Based on mod 5 counter logic 0 1 2 3 4 5Output sequence c(n)1 1 1 1 1 1 x5 x6 s(n) Clk=fs Clk=6*fs 0 5 Figure 212. Linear Feedback shift register for a 6 tap pseudo random signal generator 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 1 1 1Clk=fs Clk=6*fs Output sequence c(n)1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 1 1 1 Figure 2 13. Timing signal to generate 6 times faster sample rate at the output

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73 111111 011111 001111 000111 000011 000001 100000 010000 001000 000100 000010 100001 110000 011000 001100 000110 101000 111101 xor Size =2^6 =63 unique sample word Figure 214 Output pseudo random bit stream from a 6 tap linear feedback shift register.

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74 MUX Q QSET CLRS R 1.0 Q QSET CLRS R =N enable = 0 1 0 Modulo N counter output Control signal Clk1=Fs Clk2=Fs/NInput data to be dowsampled ( Input sample rate = Fs) Downsampled data, sample rate = Fs/N Downsampled clock Clk2=Fs/N When count = 0, an enable is generated Downsampled clock Clk1=Fs Figure 215. DSP implementation of sample rate logic Inphase and Quadrature phase signal swings -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 7 8 9 10 Time index Amplitude I Q Figure 216. Inphase and quadrature phase signal swings whose magnitude has to be estimated.

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75 Instantaneoius error ( linear) vs Input signal swings as a function of a and b 0.89 0.91 0.93 0.95 0.97 0.99 1.01 1.03 1.05 0 1 2 3 4 5 6 7 8 9 10 sample points Linear Error a=61/64,b=12/32 ideal magnitude a=15/16,b=15/32 a=122/128,b=31/32 a=31/32,b=12/32 Figure 2-17. Instantaneous error (linear) vs. input signal swing function as a function of and factors 1.0 MUXI <14,0,t> Bit Extract MSB 1 0<14,0,u> abs(I) Figure 218. Simple absolute value estimator logic

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76 MUX Bit Extract MSB + abs(I) <14,0,u> abs(Q) <14,0,u> 1 0 <15,0,t> Max(I,Q) Figure 219. Digital DSP hardware structure for m agnitude comparator

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77 1.0 MUXI <14,0,t> Bit Extract MSB 1 0<14,0,u> abs(I) 1.0 MUXQ <14,0,t> Bit Extract MSB 1 0<14,0,u> abs(Q) Bitwise Compare I>Q MUX MUX 1 0 1 0Max(|I|,|Q|) Min(|I|,|Q|) Left shift By 2 Left shift by 1 Left shift by 2 x4 x3 x5 right shift by 6 x3 x4 /32 /64 Magnitude estimate Left shift by 2 Left shift by 1 right shift by 5 Figure 220 Digital DSP hard ware structure for the magnitude estimator

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78 Figure 2-2 1 System simulations with quantized I and Q random signals and mean error in estimation.

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79 Figure 2-22. Ideal and obtained signal magnitude Figure 223. Magnitude error in dB as a function of buffer hardware length

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80 + + Z-1 x(n) a 1-a y(n) Coeffecient generator Time enables Figure 224. DSP structure of the exponential averager Figure 225. Settling times of the averager as a function of filter factor

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81 Figure 226. Dynamic varying filter factor depending for n oise and response time trade offs. Figure 227. Magnitude response of the averager

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82 + + Z-1 b 1-b y2(n) + + Z-1 x(n) a 1-a y(n) Coeffecient generator Clock enable for the 1st stage Clock enable for the 2nd stage y(n) MUX Cascade_enable1 0 Figure 2 28 Cascaded structure for the fast average circuit Figure 229. Output of second filter vs. time in sec

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83 Q QSET CLRS R Q QSET CLRS R Kp Ki Kd + + + + + clk e(n) + + ) ( 1 ) ( ) ) ( ( ) ( s E K s s KpE K s E s s PI D p(n) Figure 230. DSP structure for PID cont roller with programmable gains right shift by 1 right shift by 2 right shift by 3 right shift by 4 right shift by 5 right shift by 6 right shift by 7 right shift by 8 MUX-A MUX-B MUX-C MUX-D MUX=E BIT SPLIT2 (B1B0) 2 (B3B2) x(n) Gain_cont<4> G*x(n) Figure 231. Controller gain programming hardware

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84 y(n) Q QSET CLRS R Q QSET CLRS R Q QSET CLRS R Q QSET CLRS R Q QSET CLRS R Q QSET CLRS R MUX-A MUX-B MUX-C MUX-Dx(n) BIT SPLIT 4 2 (B1B0) 2 (B3B3) Xcorr_out<4> clk Rxy(k) x(n) x(n-1) x(n-2) x(n-3) x(n-4) x(n-5) x(n-11) x(n-10) x(n-6) x(n-9)0 1 2 3 0 1 2 3 3 2 1 0 Q QSET CLRS R Q QSET CLRS R Q QSET CLRS R Q QSET CLRS R Q QSET CLRS R Q QSET CLRS R x(n-7) x(n-8) x(n-12)0 1 2 3 Figure 232. Digital implementation of 12 taps cross -correlation DSP hardware

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85 Figure 233. Cross -Correlati on of c alibration signal Figure 234. Simulation to show the c orrelation estimate between the calibration signal and the feedback signal

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86 Figure 2-35. Signal buffer of baseband signal envelope Figure 236. Detected Signal at the output of t he ADC at the signal sample rate (no downsampling)

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87 Figure 2-37. Normalized signal c orrelation between baseband signal envelope and detected signal. Figure 238. Time aligned gain scaled baseband signal envelope and d etected signal

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88 Figure 239. Correlation estimate of b aseband signal envelope and feedback signal with downsample ratio of N=2 Figure 240. Correlation estimate of b aseband signal envelope and feedback signal with downsample ratio of N=5 Figure 241. Correlation estimate of b aseband signal envelope and feedback signal with downsample ratio of N=10

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89 Figure 242. Correlation estimate of b aseband signal envelope and feedback signal with downsample ratio of N=20 Figure 243. Simulation to show injected 6dB gain variation and the reference signal level

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90 Figure 244. Simulation to show the controller output adaptation for a positive 6dB gain variation in multiple steps Figure 245. Simulation to show the closed loop response with respect to different integral gains fo r a positive 6dB gain variation

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91 Figure 246. Simulation of the closed loop circuitry adaptation until error signal becomes zero. 6dB Gain adjust 5.5dB Gain adjust 6.5dB Gain adjust Controller output simulations for +6,+5.5 and 5.5 dB gain adjust Controller Output signal Figure 247. Simulation to show the controller correction for +6dB, +5.5dB and 6.5dB gain var iation.

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92 Figure 248. Simulation to show the controller output to track for +10dB, +3.5dB and 5.5dB gain variation. Figure 249 System interface for mobile device testing

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93 Controller Output tracking for introduced disturbances Trigger signal A lower integral gain is used Figure 250. Analog version of the controller compensation by multiple steps to reach to the desired power as captured by Tektronix oscilloscope Trigger signal Controller output Ramps down to compensate for positive disturbance Figure 251. Analog version of the controller compensation by a single step to reach to the desired power level captured by Tektronix oscilloscope

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94 Controller Output tracking for introduced D isturbances Under damped Trigger signal Figure 252. Analog response of the controller output shows oscillations due higher value of integral gains captured by Tektronix oscilloscope AOC DAC Controller Output tracking for introduced D isturbances Over damped Trigger signal Figure 253. Analog res ponse of the controller output to shows over damped condition due lower value of integral gains captured by Tektronix oscilloscope

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95 Figure 254. Measured (FSIQ) plots of RF output at the power amplifier output as a function of controller gains

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96 Table 2 1. Estimation of best and factors for magnitude estimation time index alpha*max(|I|,|Q|) beta*min(|I|,|Q|) ideal magnitude a=61/64,b=12/32 a=15/16,b=15/32 a=122/128,b=31/32 a=31/32,b=12/32 0 0.952892 9.16E 05 0.999755 0.952984 0.937386 0.952991 0.937363 1 0.771094 0.220419 1 0.991514 1.033978 1.009882 0.978873 2 0.906476 0.115881 1 1.022357 1.036467 1.032014 1.007497 3 0.906476 0.115881 1 1.022357 1.036467 1.032014 1.007497 4 0.771094 0.220419 1 0.99151 4 1.033978 1.009882 0.978873 5 0.952892 9.16E 05 0.999755 0.952984 0.937386 0.952991 0.937363 6 0.771094 0.220419 1 0.991514 1.033978 1.009882 0.978873 7 0.906476 0.115881 1 1.022357 1.036467 1.032014 1.007497 8 0.906476 0.115881 1 1.022357 1.036467 1. 032014 1.007497 9 0.771094 0.220419 1 0.991514 1.033978 1.009882 0.978873 10 0.952892 9.16E 05 0.999755 0.952984 0.937386 0.952991 0.937363

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97 Table 2 2. Signal gain implementation shift right factor linear gain dB gain Gain_cont<4> 0 1 2 3M M M M 1 1 0 0 2 0.5 6.0206 1 (1/2+1/4) 0.75 2.49877 2 4 0.25 12.0412 3 (1/4+1/8) 0.375 8.51937 4 8 0.125 18.0618 5 (1/8+1/16) 0.1875 14.54 6 16 0.0625 24.0824 7 (1/16+1/32) 0.09375 20.5606 8 32 0.03125 30.103 9 (1/32+1/64) 0.046875 26.58 12 10 64 0.015625 36.1236 11 (1/64+1/128) 0.0234375 32.6018 12 128 0.0078125 42.1442 13 (1/128+1/256) 0.01171875 38.6224 14 256 0.00390625 48.1648 15

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98 Table 2 3 Multiplexor selection logic for the 12 tap cross -correlator. Mux selection Xcorr_ out<4> 0 1 2 3B B B B ) ( k Rxy MuxA 0 0000 1 0) ( ) (M nn y n x MuxA 1 0001 1 0) ( ) 1 (M nn y n x MuxA 2 0010 1 0) ( ) 2 (M nn y n x MuxA 3 0011 1 0) ( ) 3 (M nn y n x MuxB 4 0100 1 0) ( ) 4 (M nn y n x MuxB 5 0101 1 0) ( ) 5 (M nn y n x MuxB 6 0110 1 0) ( ) 6 (M nn y n x MuxB 7 0111 1 0) ( ) 7 (M nn y n x MuxC 8 1000 1 0) ( ) 8 (M nn y n x MuxC 9 1001 1 0) ( ) 9 (M nn y n x MuxC 10 1010 1 0) ( ) 10 (M nn y n x MuxC 11 1011 1 0) ( ) 11 (M nn y n x

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99 Table 2 3 Continued Mux selection Xcorr_out<4> 0 1 2 3B B B B ) ( k Rxy MuxD 12 1100 1 0) ( ) 12 (M nn y n x NA 13 1101 NA NA 14 1110 NA NA 15 1111 NA .

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100 CHAPTER 3 DSP BASED DYNAMIC ESTIMATION AND COMPENSATION OF DIFFERENTIA L GAIN NONLI NEARITY AND RANDOM P HASE SHIFTS 3.1 Demands for Relative Gain and Phase Accuracy in Mobile Devices Wireless communication devices employ multistage gain amplifiers and RF driver amplifiers to perform output power control in transmitters Most of the wirel ess communication standards impose stringent requirement s on the relative power accuracy and phase continuity specifications to enhance system capacity and signal quality. More specifically, wireless transmitters which adopt advanced communic ations standar ds such as CDMA 2000, WCDMA, LTE [3134] require the output power accuracy specifications to be better than 0.2dB. This implies that when a transmit power change happens in a mobile system the final value of the desired power level must be within +/ 0.2dB accuracy. In addition, it also requires the phase continuity specification to be within +/ 3 degrees between adjacent transmissions. This implies that the phase variation of the signal carrier between consecutive RF step changes must be within +/ 3 degrees These standard requirements [28 30] pose great challenges for any wireless device design and manufacturing. The relative power accuracy specifications help to maintain system capacity, and avoid signal interference from nearby users, while the carrier ph ase discontinuity specifications help to preserve signal quality and easier demodulation at the base-station receivers. The technique presented in this Chapter uses DSP circuits to estimate the relative gain error (Differential Nonlinear Error, DNLE) of th e analog RF gain amplifier and compensate for the accumulated nonlinearities introduced. In addition, this Chapter also introduces a method to calibrate the carrier phase changes in which happens in a mobile device due to change in the capacitive

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101 load impedances on the RF analog path. Along with the system architecture, this chapt er also describes the corresponding DSP hardware implementation topologies system simulation s and measurement r esults.Figure 31 shows the block diagram of a wireless transmitter and the nodes at which the nonlinear impairments get added into the system which will degrade system performances. The phase changes associated in any high frequency wireless system can be either due to the phase shifts introduced by the RF modulators or due to phase response variations of the analog filters in the signal path. The phase variations are also a result of change in capacitive loads [16] during different stages of operation of any RF device. The presented technique is found to estimate and com pensate for gain errors better than 0.1 dB accuracy and phase errors less than 1 degree accuracy. 3.2 Analytical Expressions for Non Linear Distortions in an Analog RF Device Before we try to find a solution to compensate for gain and phase nonlinearities that originate in a RF analog circuit, it is important to understand the origin of nonlinear distortions and the distortion metrics to address the problems which are introduced into the system. Assume an RF amplifier used either in a mobile device or at th e basestation that operates in a weakly nonlinear range. The input and output of any memoryless nonlinear system can be system can be described by the following power series. .........4 3 3 3 2 2 1 i i i i oS a S a S a S a S (3 -1) where oS is the output of the system, iS is the input to the system and the coefficients ka are the thkorder coefficients depending on the degree of system nonlinearity. These coefficients are independent of the input signal level but primarily a function of the

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102 device bias characteristics [5], [1013], [40]. The coefficient 1a is known as the small signal gain. For very small input signal levels, iS the coefficient 1a dominates and the higher order terms are negligible. Assume the signal t S Sicos1 is the input to a nonlinear system. The output of the non-linear system is defined by ........ ) ( ) ( ) (1 3 3 1 3 1 2 2 1 2 1 1 1 ) ( t Cos S a t Cos S a t Cos S a Snl o (3 -2) The second term ) (cos1 2 2 1 2t S a is expanded as ) (cos1 2 2 1 2t S a = 2 1 2S a ] ) ) [cos( 2 11 1 1t t 1cos( = ] 2 cos1 [ 2 11 2 1 2t Sa (3 -3) The cubic term ) (cos1 3 3 1 3t S a is expanded as ) (cos1 3 3 1 3t S a = ] cos [cos1 1 2 3 1 3t t S a = t t t S a1 1 1 3 1 3cos ) 3 [(cos 4 1 cos 2 1 = t t S a1 1 3 1 33 cos 4 1 cos 4 3 (3 4) The first term in the Equation 3-4 is the fundamental and the second term is the third harmonic term which was generated by the devi ce nonlinearity. This component appears at the output of the device at three times the input frequency. To analyze the sum total distortions caused in a transceiver it is also essential to better understand the 5th order term as they determine the out of b and spectrum emission requirements. More specifically, this is responsible for the spectrum leakage at alternate channels (2

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103 channels away) due to a mobile user in a particular channel. The pentic term ) (cos1 5 5 1 5t S a can be expressed as ) (cos1 5 5 1 5t S a =t1 2(cos) t1 3(cos ) = ] 2 cos 1 [ 2 1 ) 3 (cos 4 1 cos 4 31 1 1 5 1 5t t t S a The output ) ( nl oS is represented by ........ ) (cos ) (cos ) (cos1 3 3 1 3 1 2 2 1 2 1 1 1 ) ( t S a t S a t S a Snl o = ) (cos1 1 1t S a + ] 2 cos 1 [ 2 11 2 1 2t Sa + ) 3 (cos 4 1 cos 4 31 1 3 1 3t t S a + (3 5) From the above analysis we observe the following The term ) (cos1 1 1t S a is the desired term with the amplified /attenuated gain. The higher order harmonics generate distortions and the coefficients are independent of the input signal. The secondorder terms produces DC shift and hence an undesired DC value is added to the input signal. It is obvious from this observation that the even order terms generate a DC comp onent. The third power [3] produces the fundamental term 1 and the third harmonic term, 13 The phase of the 1 is most important because it can produce a signal totally out of phase of the input desired signal and can cause undesired amplitude change of the output signal. Depending on the phase of this term it can generate either gain compression or gain expansion of the output signal. Taylor series expansion of an odd function ) ( ) ( s f s f only has odd components, while an expansion of even functions ) ( ) ( s f s f generates DC components. The rate at which the first harmonic grows is slower than the second and the third harmonic.

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104 In practice an amplifier used in transceivers will operate either in the linear region or within the 1dB compression point. Hence, Taylor series can be used for our analysis. Since the total output signal power is a function of power of the independent harmonics, it is important to understand the dist ortion metrics analytically, and its nonlinear effects on the desired signal power. Considering the second power term, the harmonic distortion ( 2HD ) can be defined as l fundamenta the of Amplitude harmonic second of Amplitude 2HD (3 -6) From expression Equation 3-4 we can calculate 1 1 2 1 2S a S HD2a 1/2 = 1 12 1 S a a 2 Hence, it is obvious that 2HD is proportional to the input signal level. 2HD is an important factor in distortion an alysis because it generates DC components which will degrade the signal quality unless eliminated. Considering the third power term, the harmonic distortion component is described as l fundamenta the of Amplitude harmonic third of Amplitude 3HD (3 7) From expression (3 5) we can calculate 1 1 3 1 3 34 S a S a HD = 2 1 14 1 S a a 3 (3 -8) The expression clearly shows that 3HD is proportional to square of the input signal. C onsidering the 5th order term, the harmonic distortion due to the 5th order term is de fined as

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105 l fundamenta the of Amplitude harmonic fifth of Amplitude 5HD (3 -9) From expression (36) we can calculate the total harmonic distortion ( THD ) as ..2 4 2 3 2 2 HD HD HD THD l fundamenta the in Power distortion the in Power (3 10) The total harmonic distortion is equal to the square root of sum of square of independent harmonic distortions. Approximate THD requirements for certain applications are denoted in Table 3-1. The presence of these nonlinearities will cause relative gain and phase errors when changing power levels in a mobile device. These will dictate the need to perform gain and phase shift compensation to maintain relative power accuracy specifications and to perform accurate power control. 3.3 Reasons for Relative Power Level Accuracy Impairment One of the primary impairments of the relative power level accuracy specifications is the DNLE associated with the h igh frequency RF and analog components [6],[8] In any high frequency amplifiers, if 1 1 gG and 2 1 gG are the g ains in dB of two successive stages of an amplifier and if 1 2 gG and 2 2 gG are the gains in dB of the same amplifier at different operating conditions (frequency bands of operation, voltage and temperature), then DNLE bet ween the two gains stages is expressed as | ) ( ) ( | ) )( (2 2 1 2 2 1 1 1 2 1 g g g gG G G G dB g g DNLE (3 11) | ) ( ) ( | ) )( (2 2 1 1 gl gk gl gk l kG G G G dB g g DNLE (3 12) These non linear terms get accumulated and leads to integral gain error which are re presented by integrated nonlinearity (INL). The INL for a thn stage gain amplifier can be expressed as

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106 ) ( .... ) ( ) ( ) )( 1 (1 3 2 2 1 n ng g DNLE g g DNLE g g DNLE dB n INLE or n ng g DNLE dB n INLE ) ( ) )( 1 (1 (3 13) where n is the desired stage up to which the nonlinearity is measured. The INL leads to gain errors and degrades the relative power level accuracy unless compensated. Figure 32 shows measured gain changes of a 16 step RF amplifier with respect to low, mid and high frequency bands of operation and at room(25 degree), hot(85 degree) and cold( 30 degree) temperatures. The DNLE for a 16 stage amplifier is calculated based on the measured data as described in Equation 3-13. Figure 33 shows measured DNL E in dB for a 16 stage high frequency gain amplifier. The calculated DNLE are based on mid channel and room temperature as the reference. Any error from this ideal reference is attributed as DNLE. The red line in Figure 3-3 is the desired specification for the selected mobile application. In addition, any gain variations due to temperature and supply voltage changes will add to the DNLE and will degrade the system power accuracy unless compensated. Tables 3 -3 and 34 shows measured power level and the co rresponding DNLE in dB for successive gain steps for a 16 stage high frequency amplifier. F igure 3 -4 shows measured INLE curves for a 16 stage driver amplifier as a function of different frequency bands of operation. As show n in Figure 3 -3 the DNLE associated with each step change is accumulated when the mobile device performs a power change. The a ccumulated INL errors lead to integral gain errors and create relative power offsets at the output of the power amplifier.

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107 3.4 Reasons for Phase Discontinuity In systems operating at high frequencies such as cellular, WiMax the relative phase change of the signal occurs due to carrier phase shifts that occur due to change in capacitive impedances during an RF power change in multi -stage amplifiers. This is becaus e the gain control in the majority of present day RF amplifiers is based on altering the current through capacitive segments. random signal phase changes due to the baseband analog filters stages random carrier phase offsets caused every time the RF VCO[69] is enabled. temperature compensation circuits in RF circuits such as mixer and VCOs which cause unknown carrier phase changes. For the sake of analysis, assume that the primary cause of the phase shift s introduced into a mobile system is due to ch ange i n RF gain stage of the amplifier within the system. If 1 and 2 are the absolute phase changes (degrees) when the RF gain amplifier is at step 1G and 2G respectively, then the relative phase change is defined as 2 1 ) 2 1 ( This change In phase angle will lead to unknown random phase shifts of the RF carrier signal. Figure 3-5 shows measured results of relative phase shifts for a discrete 16 stage gain RF ampli fier. The relative phase changes between two consecutive stages m and n are represented by ) ( n m The change in carrier phase shift must be compensated so that the transmitted signal does not und ergo relative phase shift changes when stepping through the gain amplifier stages. The introduced carrier phase shifts are either due to changes in capacitive impedances of the high frequency amplifier or due to frequency dependent phase drifts introduced by analog circuits in the transmit path.

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108 3.5 DSP based Relative Gain/Phase Estimation Algorithm Theory (DSP -GPE) The goal of DSP -GE algorithm is to estimate the relative gain change s and random signal phase shifts introduced by the RF and analog components of the mobile system. The estimated gain and phase values are then used to compensate for the gain errors by providing digital gain and phase correction at the baseband signal processing path of the mobile device. This helps in reducing the relative gain error and maintaining the phase information of the signal. The primary idea of the introduced technique is to estimate successive gain and phase variations by employing DFT based detection of relative change in signal energy and phase information. 3.5.1 Th eory of Operation As explained in chapter 2, Figure 36a describes system architecture of any quadrature signal based mobile transmit path. The theory behind the algorithm can be described by assuming tone inputs as the in-phase ) ( t I and quadrature phase signal ) ( t Q Based on this assumption, the complex baseband signal is represented as ) ( ) ( ) ( t jQ t I t C where ) cos( ) ( t t IBB and ) sin( ) ( t t QBB Where, BB is the digit al baseband frequency of the tone and is the phase angle of the baseband signal vector. The complex signal is generated at the baseband and passes through the DAC and modulated by the RF mixer and transmitted through an RF gain ampli fier.The transmitted signal can be represented as t jRFe e t jQ t I GD t g )] ( ) ( [ ) (1 (3 -14)

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109 where, 1D is the digital gain, G and je is gain and phase shift introduced by the RF VGA for that gain step. The modulated transmit RF frequency introduced by the modulator is denoted by tRFe During the algorithm operation, the output of the transmit gain amplifier ) (t g i s looped b ack into the pseudo-receiver [22] section which has an RF gain and a demodulator stage. T he RF signal ) ( t g is demodulated back to baseband frequency depending on the frequency offset between the RF modulator and the demodulator. Dependin g on the frequency offsets between transmit and receive VCOs the desired baseband signal frequency can be altered. Assume ) ( t jTXe is the transmitting frequency and ) ( t jRXe is the demodulation frequency and the frequency diff erence is defined by ) ( t jIFe Based on this assumption, the received demodulated baseband signal is represented by ) ( ). ( ) () ( t j BBRXe G t g t Rx where ) ( t jRXe = ) () ( t t jIF TXe ) ( )] ( ) ( [) ( 1 t t j t jIF TX TXe G e e t jQ t I G D ) ( )] ( ) ( [( 1 t j jIFe G e t jQ t I G D )] ( ) ( ) ( ) ( [( ( 1 t j t jIF IFe G t jQ e G t I D (3 -15) Hence the demodulated baseband signal has a frequency of IF and can be represented as described in the Equation 3-15 Expanding the 1st t erm of Equat ion (3 -15), can be expressed as ) ( ) (( 1 t jIFe G D t I = ) )( cos(( 1 t j BBIFe t G D = ) cos( ) (( 1 t e G DBB t jIF

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110 = ) cos( )] sin( ) [cos(1 t t j t G DBB IF IF = ))] cos( ) (sin( )) cos( ) [(cos(1 t t j t t G DBB IF BB IF = )) ) (sin( ) ) (sin( ) ) (cos( ) ) [(cos( 21 t t j t t G DBB IF BB IF BB IF BB IF L et P = ) (BB IF and Q = ) (BB IF this results in ))] (sin ) (sin( ) (cos( ) [(cos( 2 ) ( ) (1 ( 1 Qt Pt j Qt Pt G D e G D t It jIF (3 16) Expanding the 2nd term of Equation (315), we get = ) ( ) (( 1 t jIFe GD t jQ = ) sin( )] (sin( ) [cos(1 t t j t jGDBB IF IF = )] cos( ) (cos( ) sin( ) sin( [ 21 Pt Qt Qt j Pt j D G = ))] sin( ) (sin( ) (cos( ) [cos( 21 Qt Pt j Qt Pt D G (3 -17) Adding (3-15) and (3-17), results in = )] sin( ) (sin( ) sin ( ) sin( ( ) (cos( ) cos( ) cos( ) [(cos( 21 Qt Pt Qt A Pt A j Qt Pt Qt Pt D G (3 -18) where, P = ) (BB IF and Q = ) (BB IF The DSP -GPE technique uses a single baseband tone through the I channel. The blue plot in Figure 3-7 shows the spectrum of tra nsmit baseband signal ) ( ) ( t I t C

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111 whose frequency BB is 100 KHz. The black plot in Figure 3-7 shows the complex baseband signal ) (t g up converted to RF frequency, assumed to be 5MHz. Hence the up convert ed signal frequency will fall at 5.1MHz. The red plot in Figure 3 -7 shows the down converted signal ) ( t RxBB to a 400 KHz baseband frequency and effectively, in this simulation, the demodulator frequency is assumed to be 300 KHz. If a DFT operation is performed at the signal bin Q = ) (BB IF all the terms of Equation 3 -18 except the component vectors containing Q will equate to zero. Hence, the DFT of I and Q c hannel can be expressed as ) ( ) ( 12 12 1 2 j je e G D DFT I (3 -19) ) ( ) ( 12 1 2 2 j je j je A G D DFT Q (3 20) If the input to the Q channel is 0, then the second term becomes zero and hence, Equations 319 and 3-20 can be represented as ) ( 12 1 2 je G D DFT I (3 -21) ) ( 12 2 jje A G D DFT Q (3 -22) Assume the RF VGA gain stage is changed from Gain stage 1G to 1G which introduces a complex phase shift from 1je to 2je The goal of the algorithm is to find the relative phase shifts and compensate for them by predistorting the I and the Q channel signals.

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112 3.5.2 Gain and Phase Estimat ion Steps Based on a tonal input into I channel or Q channel of the mobile transmit signal path, the estimation of the gain variation and phase drifts can be described in three steps. Step 1: Calculate the first DFT corresponding to a complex gain and phase shift applied at the VGA. Let this applied gain step at the VGA result in gain 1G and a phase shift of 1 The composite gain and phase change is represented as 1 1je G From Equation 319, the I channel DFT can be computed as ) 1 ( 1 1 1 12 1 2) ( j je G D e G DFT I (3 -23) Step 2: Increment the VGA gain to the next state, to 2 2je G then the corresp onding I channel DFT is computed similarly as ) ( j je G D ) e G ( DFT I 2 2 1 2 22 1 2 (3 -24) Step 3: The ratio of the magnitude of the corresponding DFTs are calculated. | ) e G ( DFT I \ | | ) e G ( DFT I | ) ( Ratioj j 1 1 2 21 2 (3 -25) ) 1 ( 1 1 ) 2 ( 2 12 1 2 2 1 2 j je G D e G D ) ( je G G1 2 1 2 (3 26) ) ( je G

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113 where G and is the estimated gain and the phase shift. Hence the estimated gain change is calculated a s the absolute value of the ratios of consecutive DFT measurements. On observing Equation 3-26 it is clear that the result is a function of and The angle is a random phase angle between transmit and receive VCOs. The angle i s the phase angle of the injected baseband calibration signal. Based on measurements it is found that transmit and the receive VCOs have only a frequency error of less than 2Hz and hence does not degrade the accuracy of this algorithm. In order to make this algorithm less susceptible to frequency and additional phase errors, the frequency of the calibration signal is selected in such a way that there is no phase imbalance introduced between both the quadrature paths I and Q from one iteration to the next Based on the above mentioned criteria the assumption of and being constant is valid. Th e DSP -GPE algorithm is used to estimate the relative gain and phase shifts dynamically. The estimated gain and phase shifts are then used to correct for relative DNL errors and phase shifts. Depending on the application, the DSP GPE algorithm can be used as a calibration sequence before the signal transmission. The estimated values are be stored in ROM lookup tables and applied as correction factors during normal tra nsmit operations. 3.5.3 Gain and Phase Compensation Implementation and Equations Assume that ref G and ref are the ideal gain and phase changes between two consecutive gain steps of the VGA according to circuit design. Let G be the actual estimated gain and phase changes between the same consecutive steps. The DNLE is then calculated as

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114 || GG DNLEref (3 -27) and the phase error is calcu lated as | | ) rees (deg err _ref (3 -28) The phase error is then applied as correction to the digital baseband signal to compensate for the amount of phase change to meet the phase discontinuity of the signal transmitted. The gain er ror is then applied to the baseband signal to meet relative power level accuracy specifications. 3.5.4 Derivation of Equations for Gain and Phase Estimation and Compensation The complex signal at the input of the modulator is given by the Equation )] sin( ) [cos(1 t jt DBB BB (3 29) where 1D is the digital gain at the baseband and is the phase angle of I and the Q channel signals. The DNLE (dB) is represented by a linear value of The phase of ) t ( I and ) t ( Q has to be compensated by the estimated phase error term err Hence the gain and phase compensated signal can be represented as ) cos( ) ( err t comp t IBB (3 30) ) sin( ) ( err t comp t QBB (3 -31) To realize this in hardware, we need to find a way mathematically to convert ) t ( I and ) t ( Q to comp ) t ( I and comp ) t ( Q Multiply ) t ( I by ) err cos( and ) t ( Q by ) err sin( ) cos( ) ( errt I = ) cos( ) cos( err tBB (3 32) ) sin( ) ( err t Q = ) sin( ) sin( err tBB (3 -33) Initially, on expanding ) cos( ) ( errt I results in

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115 ) sin( 2 1 ) cos( 2 1) cos( ) ( err t errt err t IBB BB = ) cos( 2 1 ) cos( 2 1 err t err tBB BB (3 34) But, we know that ) cos( ) ( err t comp t IBB disregarding the gain DNL term for n ow. Adding the required terms results in comp ) t ( I = ) cos( err tBB = ) cos( 2 1 ) cos( 2 1 ) cos( 2 1 ) cos( 2 1 err t err t err t err tBB BB BB BB = ) cos(err tBB Substituting in Equation 334 results in = ) sin( ) ( ) cos( 2 1 ) cos( 2 1 err t Q err t err tBB BB = ) cos( ) sin( ) ( ) cos( ) ( err t err t Q err t IBB (3 -35) On similar lines, we can prove that ) sin( ) sin( ) ( ) cos( ) ( err t err t I err t QBB (3 -36) Hence, to compensate the signal by err the following implementation can be adopted. ) sin( ) ( ) cos( ) ( ) ( err t Q err t I comp t I (3 -37) ) sin( ) ( ) cos( ) (_ ) ( err t I err t Q comp t Q (3 38) The brief overview of the algorithm is described in by the flow chart in Figure 3 -8.

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116 3. 6 DSP Hardware Structures for Relative Gain/Phase Estimation and Compensation Most of the basic hardware employed in Chapter 2 can be adopted for this algorithm. In addition, this section describes two DSP hardware structures adopted for relative gain and phase estimation and compensation. The following section describes the equations and the DSP implementation of the phase compensation circuit and the gain estimation digital circuit. 3.6.1 Phase Compensation DSP Structure Based on descriptions in earlier sections it is understood that the relative phase shifts estimated can be used as baseband compensation factors to correct the unknown phase shifts introd uced in a mobile system. ) sin( ) ( ) cos( ) ( ) ( err t Q err t I comp t I (3 39) ) sin( ) ( ) cos( ) (_ ) ( err t I err t Q comp t Q (3 -40) The cosine and sine of an angle are implemented with an 8X8 ROM. This has 8 bits each and 256 entries. Prior knowledge of the maximum amount of phase compensation that a system application will need help s in limiting the size of the ROM. For our application, the maximum amount of phase shift required is +/ -25 degrees. Adopting an 8 bit input ROM will result in accuracy of 25/256 =0.09765 degrees. Hence, 8 bi t registers will give us an output accuracy of 1/256 = 0.0039625 degrees. 3.6.2 DFT Based Gain Estimation Structure The DFT of a signal ) ( n x is represented as n N n N k je n x k X ) )( ( ) (1 0 2 where k = 0, 1, 2, N -1 (341a) where, the frequency of interest is located in the th k bin.

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117 Let N k j ke W2 then ) 1 ( ) 2 ( ... ) 1 ( ) 0 ( ) ( ) )( ( ) (1 2 1 ) ( 1 0 1 0 2 N x W N x W x W x W W n x e n x k Xk k N k N k n N k N n n N n N k j The transfer function of the system that estimates the DFT is represented as 1 21 1 ) ( z e z HN k j 1 21 1 ) ( ) ( z e z X z YN k j (3 -41b) K N k jW n y n x e n y n x n y ) 1 ( ) ( ) 1 ( ) ( ) (2 (3 41c) Expanding 3 41c results in n K K KW x W n x Wn x n x n y ) 0 ( ..... ) 2 ( ) 1 ( ) ( ) (2 (3 41d) Comparing Equations 3 41c and 3-41d it is clear that the required transform is obtained when ) ( ) ( N y k X Multiplying the numerator and denominator by the conjugate, results in ) 1 ( ) 1 ( ) 1 ( 1 ) (1 1 1 1 1 z W z W z W z Hk k k (3 -41e) Hence, ) ) (1 ( ) 1 ( ) (2 1 1 1 1 z z W W z W z Hk kk 2 1 1 12 cos 2 1 ) 1 ( ) ( ) ( ) ( z z N k z W z X z Y z Hk

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118 where ) (1 k kW W = ) 2 cos( 22 2N k e eN k j N k j Based on this, the DFT ) 1 ( ) ( ) (1 N y W N y k Xk ) 2 sin( ) 1 ( ) 2 cos( ) 1 ( ) ( N k N jYN k N Y N Y DFT (3 -41f) where, ) ( ) ( N y k X at the final iteration N which is the DFT length. ) 1 ( ) ( ) (1 N y W N y k Xk (3 -41g) Taking the square of the Equation 3 41g, we obtain ) ( ) ( | ) ( |* 2k X k X k X ) 1 ( ) ( ) ( ) 1 ( ) ( ) (1 1 N y W N y k X N y W N y k Xk k )] 1 ( ) ( )][ 1 ( ) ( [ | ) ( |1 1 2 N y W N y N y W N y k Xk k ) 1 ( ) ( ) ( ) 1 ( ) ( | ) ( |1 1 2 2 2 N Y N y W W N y N y k Xk k ) 1 ( ) ( ) 2 cos( 2 ) 1 ( ) ( | ) ( |2 2 2 N Y N y N k N y N y k X (3 42) Equation 342 can be used as the single point power spectral densi ty estimator. Depending on the value of k the frequency bin of interest, the value of the DFT is estimated. The DSP hardware structure adopted to estimate the single point magnitude of DFT is shown in Figure 3 -11. The DSP hardware th at estimates the gain and phase estimate of the signal is shown in Figure 3-12. Assume that the number of samples of the DFT is 512 N and the sampling frequency of the DSP hardware is Fs = 5MHz and KHz Ftone51 146 In our algorithm,

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119 KHz Ftone51 146 will be the final baseband frequency at the receiver. The DFT index K corresponding to this frequency is calculated by N F F Ks tone 15 512 5 51 146 MHz KHz K This DSP hardware in Figure 3-12 calculates the real and complex DFT for a real signal stream. In our algorithm this DSP hardware is present in both I channel and the Q channel. For our application, the I channel is employed and the output of the filter has a real part and an imaginary part. The absolute value is then estimated to result in DFT I and DFT Q 3. 7 System Simulat ions and Lab Measurement Results The system architecture was modeled in tools such as Matlab and Signal Processing work station (SPW). System simulations were performed with the following parameters. Figure 313 shows the time domain waveforms of demodulat ed I channel at the receiver. The simulation frequencies used are KHzIF300 KHzBB100 MHzTX5 and KHz MHzRX300 5 Hence the demodulated baseband signal frequency is 400 KHz. Each stage results in a RF gain and a phase change ) (k j ke G where k = 1,2 Figure 313 shows plots for k =1,2..4. Figure 3-14 shows system simulation performed with KHzIF300 KHzBB100 and by stepping the eight stages of the RF gain amplifier. Each stage results in a RF gain and a phase change of ) (kj ke G where k = 1, 2 8. Figure 3-15 shows measured DFT magnitude for I channel signal. The measurement shows that the peak of the magnitude appears at

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120 K =15 which corresponds to 146.51 KHz ( BB IF ), where KHzIF100 and KHzBB51 46 The frequency of the tone BB has to be selected so that the DFT bin falls exactly on an integer multiple of K 15 512 5 51 146 MHz KHz K The following descriptions explain the basic steps involved in the gain and phase estimation algorithm. Step 1 By employing the DSP hardware, calculate the first DFT I with the complex gain and phase shift applied at the VGA to be ) e G (j 1 2. The DFT I is calculated as ) 1 ( 1 1 1 12 1 2 ) ( j je G D e G DFT I Step 2: Increment the VGA gain to the next state, to ) e G (j 2 2 then the corresponding DFT I is computed in the same way as ) ( j je G D ) e G ( DFT I 2 2 1 2 22 1 2 Step 3: The ratio of the magnitude of the corresponding DFTs are calculated. | ) e G ( DFT I \ | | ) e G ( DFT I| ) ( Ratioj j 1 1 2 21 2 (3 43) ) ( j ) ( je G D e G D ) ( Ratio 1 1 1 2 2 12 1 2 2 1 2 1 2 ) ( je G G1 2 1 2 (3 -44) ) () 1 2 ( je G Ratio is the estimated gain and the phase shift.

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121 3.7.1 System Simulations of the DSP -GPE Algorithm The performance of the DSP -GPE algorithm is analyzed by system simulations. Table 3 5 shows the estimated DFT by using the fixed point model of the DFT estimator hardware. At each RF gain amplifier step, the absolute magnitude of I_DFT is estimated by assuming N =512 samples. To avoid spectrum leakage, it has to be taken car e that the DFT measurement has to start at the proper time instants to capture periodic cycles of ) ( n x .The complex I_DFT output is tabulated in Table 35. After eight periodic measurements, the DSP algorithm calculates the ratio of successive I_DFT measurements. Thus the ratios ) ( n m Ratio = | ) e G ( DFT I \ | | ) e G ( DFT I |m j m n j n is calculated by the DSP algorithm.Table 3-6 shows measurements tabulated that correspond to ratios of consecutive eight DFT measurements. The ratio | ) e G ( DFT I \ | | ) e G ( DFT I |m j m n j n will lead to a gain and a phase component G and err respectively. The desired gain change, refG and the difference | | G G DNLEref is calculated and applied to the baseband signal. The amount of phase change estimated err is directly applied to the baseband signal as a pre distorted phase to maintain signals phase continuity specifications. The simulation results show the performance of the algorithm with the introduced gain and phase error. Simulations performed over worst ca se process variations reveal that the algorithm predicts the gain error better than 0.1dB and phase error better than 1 degree accuracy. 3.7.2 Lab Measurement Results Figure 3 18 shows measured INLE curves for the 16 stage driver amplifier after baseband gain error compensation. The DSP-GPE algorithm is performed as a part of

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122 the mobile radio calibration for a single RFIC for a mid frequency band of operation assuming room temperatures The estimated DNLE values are stored in ROM look up tables based on fr equency of operation and are applied to the baseband signal during normal transmission. The measurement shown in Figure 3 -18 is average INLE over three different RFIC The technique compensates for relative gain errors caused due to differential nonlinearit ies in a high frequency amplifier Figure 319 shows the estimated phase change in degrees across different sections of the high frequency amplifier by calibrating using a tonal input at the I and the Q channel a s described earlier. The algorithm is run only at room temperature (+25 degrees) and at mid frequency conditions. The phase estimation is then stored in the ROM look up tables after the calibration is performed. The estimated phase values are applied as b aseband compensation as described in earlier sections. Figure 3 20 shows measured relative phase change in degrees across different sections of the high frequency amplifier after the estimated phase compensation is applied at the baseband signal path. The algorithm is able to estimate the relative phase change effectively and the applied phase correction helps to preserve system phase discontinuity specifications. System lab measurements and simulations prove that the described technique can estimate DNLE better than 0.1dB accuracy and a phase shift less than 0.5 degrees and hence, reducing relative gain and phase error to within 0.1dB and 1 degree accuracy. Figure 3 -21 shows lab measurements with a sinusoidal input into the mobile system and a phase angle c ompensation of +/ -90 degrees applied on I and Q channels. In order to improve the range of correction angle and reduce area, DSP -software is used to implement fixed

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123 point level algorithms. The above mentioned measurements and system simulations prove the functionality and system performance of the DSP -GPE system algorithm. 3.8 Summary The DSP -GPE algorithm is implemented in a mobile device for the gain and phase estimation. System lab measurements and simulations prove that the DSP -GPE technique can estimate DNLE better than 0.1dB accuracy and phase shifts better than 0.5 degrees accuracy. This helps to maintain relative gain and phase errors to be within 0.1dB and 1 degree accuracy respectively. The approximate gate count is less than 10K as the DSP hardware includes the DFT filter and the gain and phase compensation circuits. The DSP -GPE algorithm is either used a pre-calibration technique to initially estimate the gain and phase error or used dynamically by interleaving periodic tone signals as a part of the baseband signals to be transmitted. The obtained gain and phase error estimates are stored in a ROM table and then applied during normal signal transmission. ej(w TX t+ph PAVGA DAC Filter DAC Tx Digital line up Symbols from Modem Base-Band Gain controlRFModulator RF Gain control I channel Q channel RF Pout (dBm) RF Section 1010101100 t w jTXe e t jQ t I G D t g)] ( ) ( [ ) (1 ) cos( ) ( t w t IBB ) sin( ) ( t w t QBB 1D ) (k j ke G Phase response with Respect to frequency DNL error determined by number of bits Figure 31. Sys tem block diagram of a wireless transmitter showing gain change and phase change

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124 -80 -70 -60 -50 -40 -30 -20 -10 0 10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 Amplifier Gain Steps Gain (dB) low_chG2g(1-16)_cold mid_chG1g(1-16)_cold high_chG3g(1-16)_cold mid_chG1g(1-16)_room mid_chG1g(1-16)_room high_chG3g(1-16)_room mid_chG1g(1-16)_hot mid_chG1g(1-16)_hot high_chG3g(1-16)_hot Figure 32. Measured amplifier bias vs. output characteristics with respect to temperature and frequency bands of operation -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Amplifier Gain Steps DNLE (dB) |mid_ch-mid_ch| |mid_ch-low_ch| |mid_ch-high_ch| |mid_ch-mid_ch| |mid_ch-low_ch| |mid_ch-high_ch| |mid_ch-mid_ch| |mid_ch-low_ch| |mid_ch-high_ch| max spec min spec Figure 33. Measured DNLE (dB) with respect to change is frequency bands of operation

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125 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Amplifier Gain stages (16) integrated non-linearity ( INL) dB |mid_ch-low_ch| |mid_ch-high_ch| |mid_ch-high_ch| |mid_ch-low_ch| |mid_ch-high_ch| |mid_ch-mid_ch| |mid_ch-low_ch| |mid_ch-high_ch| upper INL spec (dB) lower INL spec (dB) Figure 34. Measured INLE with respect to change is frequency bands of operation -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 Amplifier Gain Steps phase change (degrees) mid_ch low_ch high_ch max spec min spec Figure 3 5. Absolute phase variations of an RF device due to capacitive loads

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126 _gain ADC ADC Single point sliding DFT DSP Single point sliding DFT DSP Filter Filter Gej(wTXt+ PA VGA Filter DAC Filter DAC Tx Digital line up Symbols from Modem Base-Band Gain controlRFModulatorBase Band Filter RF Gain control I channel Q channel RF Pout (dBm) RF Section Relative Phase shift compensation 1010101100 ) sin( err ) cos( err DNLE II t w jIFe G t Q t Rx Q ) ( ) ( ) ( _( ) cos( ) ( err t w comp t IBB ) sin( ) ( err t w comp t QBB t w jTXe e t jQ t I G D t g)] ( ) ( [ ) (1 ) cos( ) ( t w t IBB ) sin( ) ( t w t QBB I t w jIFe G t I D t Rx I ) ( ) ( [ ) ( _( 1 ) ('t w jRXe G ) ( ') ( t w t w jIF TXe G ) ( ) ( 12 1 2 1 2 j je e G D I DFT ) ( ) ( 12 1 2 2 j je j e j A G D Q DFT Complex single point DFT_I Complex single point DFT_Q code DSP Step SVGA to state 1 ) e G (j 2 2 and estimate I_DFT1 ) 1 ( 1 1 1 12 1 2 ) ( j je G D e G DFT I Increment the VGA gain to the next state, to ) e G (j 2 2 and estimate I_DFT2 ) ( j je G D ) e G ( DFT I 2 2 1 2 22 1 2 Estimate ratio of the magnitude of the corresponding DF Ts | ) e G ( DFT I \ | | ) e G ( DFT I | ) ( Ratioj j 1 1 2 21 2 ) ( j ) ( je G D e G D ) ( Ratio 1 1 1 2 2 12 1 2 2 1 2 1 2 ) ( je G G1 2 1 2 ) () 1 2 ( je G Ratio the gain and the phase shift. Figure 3 6. Gai n and phase estimation A) System block diagram of the mobile device with the DSP -GPE algorithm. B) Implemented frequency location of the calibration signal during the algorithm

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127 100K-100K DC Wtx_rf+100k Wtx_rf-100k Wtx_rf Wif Tx Baseband Real tone through I channel PSD at Output of Tx LO PSD at Rx base band After demodulation by Wrx_rf PSD of Tx BB Wif+100k Wif-100k Figure 36 Continued

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128 Figure 37. Frequency location of the calibration signal during the algorithm

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129 ) (1 1je G Set the RF gain amplifier to G1 state ) cos( ) ( t w t IBB ) sin( ) ( t w t QBB Send Baseband signal I(t) and Q(t) with tone frequency WBBEnable digital clocks Set the digital baseband gain to be D1 t w jRFe e t jQ t I G D t g)] ( ) ( [ ) (1 The transmitted signal is Set RF upconversion frequency to be WTx t w jTXe e Set RF downconversion frequency to be WRx=WTx+WIF t w jrandRXe e jrand j je e e Increment the VGA gain to the next state, ) (2 2je G The demodulated received signal Is RxBB(t) ) ( )] ( ) ( [ ) (( 1 t w j j BBIFe G e t jQ t I G D t Rx ) 1 ( 1 1 1 12 1 2 ) ( j je G D e G DFT I Estimate complex DFT for real I signal ) 2 ( 2 1 2 22 1 2 ) ( j je G D e G DFT I Re-Estimate complex DFT for real I signal | ) ( | | ) ( | ) 1 2 (1 1 2 2 j je G DFT I e G DFT I Ratio Compute ratio of consecutive DFTs ) 1 2 ( 1 2 je G G ) () 1 2 ( je G Ratio DNLE | | referr | | G G DNLEref | | referr Estimate Gain DNL Error and Phase offset error Figure 38. Flowchart of the DSP -GPE algorithm for relative gain and phase change estimation

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130 I(t) Q(t) 6X12 ROM Q QSET CLRD MUX + Software Mapping Phi(radians) + + 1.5709 radians (Phi+ 90) deg <6, 6,u > <12, 0,t > Q QSET CLRD Cos_sin_sel 0 1 Negate -sin(phi) Sin(phi) Cos(phi) DSP code Hardware clk ) ( err I(t) _comp Q(t) _comp Figure 39. Baseband signal phase compensation DSP hardware structure

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131 Figure 310. Simulation of baseband signal phase compensation by using the DSP hardware structure Q QSET CLRS R Q QSET CLRS R CosX ROM8X8ROM left shift by 12*Cos(2*pi*k/N) (2*pi*k/N) Cos(2*pi*k/N) N samples of x(n) + + + Y(N-1) YN) ) 1 ( ). ( ) 2 cos( 2 ) 1 ( ) ( | ) ( |2 2 2 N Y N y N k N y N y k X DSP Code |X(K)|2 Figure 311. DSP Hardware structure to estimate the absolute gain change

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132 Q QSET CLRS R Q QSET CLRS R Q QSET CLRS R Q QSET CLRS R CosX ROM sinX ROM left shift by 12*Cos(2*pi* k/N) (2 *pi* k/N ) Cos(2* pi*k/N ) sin(2*pi*k/N) Abs Y(N) Y( N-1 ) Cos( 2*pi*k/N)*Y(N-1) Y(N) -Cos(2* pi*k/ N)*Y(N -1) Real Part N samples of x(n) Pulse generated after N iterations + + + + Y(N-1)*sin(2*pi*k /N) Imag Part sin(2*pi*k/N) DFT X(k) Figure 312. DSP Hardware structure to estimate the absolute gain and phase change Figure 313. Simulation plots to show that ) ( t RxBB with frequency of 400 KHz and KHzIF300 over the 8 RF gain settings

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133 Figure 314. Simulation of FFT magnitude of ) ( t RxBB with KHzIF300 over the 8 RF gain settings Figure 315. Simulated DFT magnitude of I and Q channel for K = 13, 14, 15, 16, 17

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134 Figure 316. Ideal gain change refG estimated gain change G (dB) and DNLE(dB) | refG G | Figure 317. Ideal phase change ref estim ated phase change (deg) and err =| ref |

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135 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Amplifier Gain stages integrated non-linearity ( INL) dB |mid_ch-low_ch| |mid_ch-high_ch| |mid_ch-high_ch| |mid_ch-low_ch| |mid_ch-high_ch| |mid_ch-mid_ch| |mid_ch-low_ch| |mid_ch-high_ch| upper INL spec (dB) lower INL spec (dB) Figure 318. Averaged INLE error measured on three RFIC after the gain error compensation. -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 Amplifier Gain Steps phase change (degrees) mid_ch low_ch high_ch Estimated Phase angle Figure 319. Absolute phase variation in the mobile device after phase compensation

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136 -1.5 -1 -0.5 0 0.5 1 1.5 Amplifier Gain Steps phase change (degrees) mid_ch low_ch high_ch max spec min spec Figure 320. Relative phase vari ation in the mobile device after compensation

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137 <=> 90 offset Figure 321. Measured plots to show the 90 degrees phase compensation performed by the DSP hardware Table 3 1. Approximate THD requirements for a few applications Applications T HD % Telephone < 10 % High Quality Audio < 1% Video < 5% Analog Repeaters <0.001% RF Amplifiers <0.1%

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138 Table 3 2. DNLE and INLE Definition Amplifier gain stages (3 bits decoder) Gain in dB Operating condition 1 Gain in dB operating condition 2 DNLE (dB) ) (l kg g DNLE INLE (dB) ) ,1 ( n INLE 1 1 1 gG 1 2 gG 2 2 1 gG 2 2 gG ) (2 1g g DNLE ) 2, 1 ( INLE 3 3 1 gG 3 2 gG ) (3 2g g DNLE ) 3, 1 ( INLE 4 4 1 gG 4 2 gG ) (4 3g g DNLE ) 4 1 ( INLE 5 5 1 gG 5 2 gG ) (5 4g g DNLE ) 5 1 ( INLE 6 6 1 gG 6 2 gG ) (6 5g g DNLE ) 6 1 ( INLE 7 7 1 gG 7 2 gG ) (7 6g g DNLE ) 7 1 ( INLE 8 8 1 gG 8 2 gG ) (8 7g g DNLE ) 8 1 ( INLE

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139 Table 3 3. Measured High Frequency Amplifier gain across temperature and frequency bands of operation. 30 degrees (low,mid,high) channels +25 degrees ( low,mid,high) channels +85 degrees ( lo w,mid,high) channels Conditions Gain Stage low_chG2g(116)_cold mid_chG1g(1 16)_cold high_chG3g(116)_cold low_chG2g(116)_room mid_chG1g(1 16)_room high_chG3g(116)_room low_chG2g(116)_hot mid_chG1g(1 16)_hot high_chG3g(116)_hot G1 64.5208 64.74 64.7999 65.543 65.774 65.8389 67.0378 67.268 67.3639 G2 56.6248 56.845 56.9019 57.758 57.997 58.0629 59.3578 59.604 59.7129 G3 51.2648 51.472 51.5069 52.453 52.678 52.7459 54.1348 54.362 54.4719 G4 45.4898 45.678 45.7199 46 .705 46.92 46.9679 48.4048 48.622 48.7279 G5 39.6318 39.829 39.8439 40.871 41.084 41.1369 42.5918 42.811 42.9099 G6 33.6358 33.831 33.8569 34.859 35.082 35.1309 36.5798 36.81 36.8939 G7 27.342 27.458 27.6 28.593 28.746 28.91 1 30.235 30.429 30.615 G8 20.641 20.755 20.88 21.821 21.97 22.133 23.39 23.56 23.758 G9 14.685 14.795 14.939 15.867 16.019 16.185 17.447 17.62 17.804 G10 12.152 12.269 12.421 13.493 13.658 13.841 15.223 15.406 15.615 G11 9.548 9.676 9.843 10.889 11.056 11.231 12.632 12.818 13.016 G12 7.421 7.544 7.704 8.771 8.931 9.108 10.505 10.697 10.892 G13 5.471 5.606 5.763 6.825 6.991 7.163 8.562 8.767 8.955 G14 2.983 3.132 3.276 4.461 4.638 4.828 6 .317 6.532 6.739 G15 0.436 0.593 0.772 2.019 2.205 2.402 3.96 4.193 4.395 G16 1.787 1.619 1.442 0.214 0.004 0.196 1.74 2.002 2.2

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140 Table 3 4 Measured DNLE with mid channel as the reference for a 16 stage gain amplifier Gain steps |mid _ch mid_ch| |mid_ch low_ch| |mid_ch high_ch| |mid_ch mid_ch| |mid_ch low_ch| |mid_ch high_ch| |mid_ch mid_ch| |mid_ch low_ch| |mid_ch high_ch| 1 0 0.008 0.001 0.118 0.119 0.121 0.113 0.097 0.126 2 0 0.014 0.002 0.054 0.041 0.076 0.077 0.096 0.078 3 0 0.01 0.02 0.036 0.017 0.029 0.018 0.028 0.014 4 0 0.002 0.005 0.013 0.022 0.04 0.025 0.023 0.018 5 0 0.01 0.004 0.004 0.006 0.015 0.001 0.01 0.014 6 0 0.0698 0.1157 0.037 0.0418 0.0787 0.045 0.0092 0.0567 7 0 0.004 0.002 0.073 0.075 0.056 0.093 0.069 0.081 8 0 0.003 0.003 0.009 0.005 0.01 0.011 0.008 0.003 9 0 0.013 0.017 0.165 0.172 0.157 0.147 0.137 0.172 10 0 0.002 0.008 0.009 0.002 0.024 0.014 0.011 0.003 11 0 0.007 0.002 0.007 0.002 0.014 0.004 0.002 0.001 12 0 0.006 0.005 0.002 0.01 0.001 0.01 0.003 0.003 13 0 0.011 0.018 0.121 0.135 0.134 0.118 0.108 0.137 14 0 0.009 0.007 0.106 0.114 0.071 0.094 0.076 0.089 15 0 0.032 0.005 0.011 0.022 0.013 0.01 0.019 0.006 max DNLE 0 0.0698 0.115 7 0.073 0.075 0.0787 0.147 0.137 0.172 min DNLE 0 0.032 0.02 0.165 0.172 0.157 0.093 0.069 0.081 DNLE 0 0.0698 0.1157 0.165 0.172 0.157 0.147 0.137 0.172 spec 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1

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141 Table 3 5. Simulation results of estimated DFT of I c hannel DFT Complex output ) ( _1 1je G DFT I 3.445e+02 5.786e+01i ) e G ( DFT Ij 2 2 5.0966e+02 1.091e+03i ) e G ( DFT Ij 3 3 1.548e+02 -1.848e+03i ) e G ( DFT Ij 4 4 -3.14e+02 5.57e+02i ) e G ( DFT Ij 5 5 3.98e+03 4.45e+03i ) e G ( DFT Ij 6 6 8.33e+04 8.8598e+04i ) e G ( DFT Ij 7 7 1.314e+06 4.947e+05i ) e G ( DFT Ij 8 8 3.141e+05 9.84e+04i Table 3 6. Simulation results of estimated ratio of DFTs Ratio | ) e G ( DFT I \ | | ) e G ( DFT I |m j m n j n ) ( Ratio 0 1 3.497e 01 1.428e 02i ) ( Ratio 1 2 1.956e+00 2.84i ) ( Ratio 2 3 1.444e+00 5.326e01i ) ( Ratio 3 4 2.852e 01 1.941e 01i ) ( Ratio 4 5 9.124 1.996i ) ( Ratio 5 6 2.033e+01 5.1499e 01i ) ( Ratio 6 7 1.0363e+01 5.081i ) ( Ratio 7 8 2.341e 01 1.320e 02i Table 3 7. Simulation results showing error in estimation Ratio | ) e G ( DFT I \ | | ) e G ( DFT I |m j m n j n ) ( Ratio 0 1 3.497e 01 1.428e 02i ) ( Ratio 1 2 1.95 6e+00 2.84i ) ( Ratio 2 3 1.444e+00 5.326e 01i ) ( Ratio 3 4 2.852e 01 1.941e 01i ) ( Ratio 4 5 9.124 1.996i ) ( Ratio 5 6 2.033e+01 5.1499e 01i ) ( Ratio 6 7 1.0363e+01 5.081i ) ( Ratio 7 8 2.341e 01 1.320e 02i

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142 Table 3 8. Simulation results of phase estimate error Ratio | ) e G ( DFT I \ || ) e G ( DFT I |m j m n j n ) ,( Ratio 0 1 3.497e 01 1.428e 02i ) ,( Ratio 1 2 1.956e+00 2.84i ) ,( Ratio 2 3 1.444e+00 5.326e 01i ) ( Ratio 3 4 2.852e 01 1.941e 01i ) ( Ratio 4 5 9.124 1.996i ) ( Ratio 5 6 2.033e+01 5.1499e 01i ) ( Ratio 6 7 1.0363e+01 5.081i ) ( Ratio 7 8 2.341e 01 1.320e 02i

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143 CHAPTER 4 DYNAMIC G AIN/POWER CONTROL US ING ADAPTIVE DSP TEC HNIQUES 4.1 Introduction As a continuation of system architectures presented in Chapter 2 and Chapter 3, this C hapter describes a DSP technique that alters the transmit signal power of a mobile device depending on th e request from the base -station To recall, Chapter 2 describes a technique t o dynamically track for gain variations caused due to analog and RF circuit imperfections at different operating conditions. Chapter 3 presents a technique to compensate for gain errors caused due to differential nonlinearities and relative phase shifts in the RF components of the mobile device and hence preserving the relative power level accuracy for any mobile device. This chapter describes a Dynamic Gain Control technique (DSP -GC) along with corresponding hardware implementation details to dynamically control the absolute signal power of any mobile device. The primary motivation of this technique is to make the system converge faster by making the closed loop system resilient t o large signal variances which are introduced due to higher order modulation schemes. Another motivation for this approach is to adopt possible DSP structures to reduce gate area. As a function of increasing data rates, adoption of higher order modulation schemes and rapid changes in channel conditions from voice to data and video, the variance of the signal transmitted increases drastically. This result in both higher peak to average ratio (PAR) [43] ,[46] and peak to null (PTN) ratio at the output of the mobile device as shown in Figure 41a. As an example in WCDMA modulation scheme, a mobile device transmitting voice information has a PAR of 3.2dB while the PAR of the transmit signal increases to 4.2dB when data is being transmitted. As mentioned in

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144 Chapt er 2 in systems employing closed-loop controller [52-55],[65 -68], to track for average level of gain variations, the loop dynamics will be dramatically influenced by the transmit signal variance. This is because when an RF feed back is applied, the error s ignal between the reference signal and the feedback signal will have the corresponding large variances which will affect loop stability. To preserve both the closedloop stability and to meet the settling time requirements during these higher signal variance conditions, there is a need for minimizing the signal variance at the input to the controller. This will make the loop less responsive to abrupt signal shifts and hence provide more predictable gain control. The described DSP -GC sy stem architecture make s use of an adapti ve filter to reduce the signal variance of the error signal between the reference and the feedback path. The output of the adaptive filter is then fed into an integral controller with programmable gains to accumulate the error signal and provide the controller output. This approach reduces abrupt signal fluctuations at the input to the controller and makes the loop more predictable. The integral controller is used to perform average gain tracking while the adaptive filter is used to perfor m instantaneous sample filtering. 4.2 System Architecture for the DSP -GC Algorithm The system architecture [14] of the DSP -GC algorithm to perform absolute gain and power change is shown in Figure 4 1b. As described in earlier chapters, a wireless transmi tter is used as an application on which the DSP -GC algorithm is implemented. As shown in Figure 41b, assume that the base band I channel and Q channel signals are represented by ) ) cos(( 1 ) ( n d n Ibb (4 1)

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145 ) ) sin(( 1 ) ( n d n Qbb (4 2) Where 1 d is the digital gain, bb is the baseband signal frequency. The signals ) (n I and ) (n Q are converted to analog signals ) (t I and ) (t Q by the DAC present in the transmit path. The signals are then up converted by the RF modulator. The complex signal at the input to the RF modulator is represented as )] ) sin(( ) ) [(cos(( 1 t j t dbb bb modin(t) (4 -3) The input to the modulator is then up converted to RF frequenc y and can be expressed as rft j bb bbe t j t d )] ) sin(( ) ) [(cos(( 1 modout(t) (4 -4) where wrf is the up conversion frequency. The output of the modulator is amplified by the PA and transmitted over the antenna. The signal transmitted over the antenna can be represe nted as rft j bb bbe t j t d G )] ) sin(( ) ) [(cos(( 1 1 PA(t) (4 5) where, 1 G is the power amplifier gain. The magnitude of the power in dBm (dB with respect to 1mW) at the output of the PA is represented as dBm Q I d G dBm Pout 30 ]) [ 1 1 log( 10 ) (2 2 (4 -6) The output of the power amplifier is converted into an equivalent DC voltage signal by using an RF power detector which converts RF power (dBm) into average DC voltage. The power detector outputs linear DC voltage for RF input power in dBm. The input vs. output transfer function is shown in Figure 4-15. The detector chosen in this technique

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146 is an envelope detector and hence the output of the detector in volts is approximated to be the envelope of the signal power and denoted as ]) ([ ) (2 2Q I abs t v (4 -7) wh ere, is the feedback path gain. The analog signal gets digitized by the ADC present in the feedback path. The RF signal is fedback through a power detector and converted into a digital equivalent signal kA The d igital signal kA is compared to a reference signal k kd pwr D where pwr corresponds to the amplitude of the reference signal in accordance to the desired power level at the antenna and kd is the adopted reference signal. Th e reference signal kd is either a step input or a normalized raised cosine ramp signal whose final value is dictated by pwr When pwr is changed the steady state value of the loop output is changed as described by Equations 211. The error signal between the refer ence signal and the feedback signal, denoted by kE = k kA D is fed into a N tap adaptive filter whose output is fed into an integral controller. The adaptive filter acts as a sample based moving average filter that reduces the large signal va riances of the error signal which are introduced due to higher order modulation schemes. As the variance of the signal is filtered out dynamically, before entering into the integral controller, this technique is found to yield faster convergence and more p redictable closed-loop performance. A price that is paid for is reduction in gain margin as the loop delay increases when an adaptive filter is used. The gain margin for the system under consideration is defined as the difference between the maximum and m inimum controller gains that can be used to maintain closedloop stability. The goal is to have a large gain margin as that will make the closed-loop system less sensitive to

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147 changes in controller gains. As will be described in later sections, increase in loop delay decreases the loop gain margin. However, sufficient gain margin can be maintained by appropriately choosing the number of taps of the adaptive filter and the operating sample rate of the closedloop system. The components of the DSP GC technique hardware are N Tap adaptive filter [27] Integral controller with programmable loop gains IK Coefficients update block Multi rate conversion logic. Signal multipliers The operation of the algorithm is described as follows. Assume that the reference signal level is represented by k kd pwr D where pwr is the signal magnitude of the desired reference and k d is a unit step input. The error at every sample k is defined as the difference between the desired signal level and the feedback signal level. k k kA D E (4 -8) The output of the adaptive filter can be represented as W E W E Sk k k k 1 (4 9a) where, k k T kS W E and k k kE W W2 12 based on Least Mean Square (LMS) Equations. Figure 42 show s a detailed schematic of the adaptive DSP hardware that employs the LMS tracking technique. The error signal kE feeds a N tap FIR filter, whose taps are updated on a sample by sample basis. The number of taps are programmable to N =2, 3, 4, 5, or 6 taps. It is found that the modulation PAR of the feedback signal was as high as 7.2dB when higher order modulation schemes such as WCDMA, CDMA and OFDM was used.

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148 Hence it is critical to reduce the variance of the error sig nal to result in faster convergence. The difference k k kA D E is calculated on a sample by sample basis. For each iteration, k the output of the filter kS is updated. The output of the adaptive filte r kS passes through an integral controller that accumulates the error signal to generate a gain correction signal ) k ( acc as the loop output signal. The gain correction signal is applied to the transmit path to perform t he desired amount of gain change as signaled by the baseband processor. Based on simulations performed, it was found that the tradeoff between the loop stability, gain margin and loop settling time was reached by choosing appropriate integral gains IK the convergence factor and the number of taps of the adaptive filter. Assume at iteration 0 k each of the registers of the adaptive filter is initialized to zero. Hence for 2 k taps filter, the weight update equations can be represented as shown in Table 4 1 Assume for tap 1 N the first weight vector at iteration 0 k is represented as 01ow, for 0 1 k N For filter tap 1 N iterating k results in ] ... [ ... ] [ ] [2 1 2 2 2 1 2 0 2 1 ) 1 ( 1 1 2 2 2 1 20 2 2 2 1 2 0 2 2 12 13 2 1 2 0 2 1 2 0 2 1 11 12 2 0 2 0 10 11 n n n nE E E E E w w E E EE E E E w w E E E E E w w E E w w (4 10a) In general for n samples, in general the weights are represented as

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149 1 0 2 1 n k k nE w (4 10b) The output of the adaptive filter kS for a 2 tap filter ( 2 N ) can be represented as ]1 ) 2 ( ) 1 ( k T k k T k kE w E w S (4 -10c) Iterating k in Equation 410c results in 0 k 1 20 0 10 0 E w E w ST T 1 k 0 21 1 11 1E w E w ST T 2 k 1 22 2 12 2E w E w ST T ] [1 ) 2 ( ) 1 ( n T n n T n nE w E w S Substituting Equation 4-10b in 4-10c results in 1 1 0 2 1 1 0 2 1 0 2 n n n k k n n k k n n k k nE E E E E E E S (4 11) Equati on 411 shows that the input to accumulator at every iteration is weighted average of past samples of error signal and thus reducing the variance of the error signal. The output of the adaptive filter nS is multiplied by the integral g ain I K before it reaches the accumulator. Hence, the input to the accumulator at iteration n is represented as ) ( n in acc which can be defined as 1 1 0 2) ( ) ( _n n n k k I n IE E E K n in acc S K n in acc (4 -12) Equation 412 shows that the effect of convergence factor on the output of the integrator is same as the integral gains. It was found that higher the integral gains and the convergence factor, faster is the rate of convergence but lower is the loop stability.

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150 4.3 Loop Tuning T echniques The three primary system constraints that requires attention while designing closed loop system are convergence time, loop stability and gain margin. As shown in Figure 43, the critical loop system parameters which influence the above mentioned constraints are Feedback loop delay Integral gains Feedback gains Amplitude of the reference signal (depends on the power levels at the antenna). Operating regions of the power detector curve. (feedback path linearity). The system specifications for whic h this algorithm is used are as described below. Peak overshoot specification of less than 3dB. Loop settling time of less than 40usec. Rise time of closed -loop response is less than 10usec. The goal of this control loop is to reduce the average of the error signal between the reference signal and the feedback signal. Hence an integral controller with programmable gains is chosen for this application. However this algorithm has also been studied with proportional, integral and derivative controllers. Sec tions 4.3.1 and 4.3.2 describe briefly about the classical open loop and closedloop techniques that help in determining the appropriate controller gains that will guarantee system stability. 4.3.1 Method I Reference Model Based Loop Tuning This method of loop tuning is used when the open loop plant transfer function ) ( s G and the closed-loop reference transfer function ) ( s H is known. Based on the knowledge of ) ( s H and ) ( s G the controller transfer function ) ( s Gc can be estimated as described below. Assume a system as shown in Figure 44. Let the input to the system is )( s R ) ( s Y is the system output, ) ( s Gc is the controller transfer function and )( s G is the

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151 known plant transfer function. The goal is to estimate the controller gains which is a part of ) ( s Gc The closed loop transfer function is represented by c cGG GG s H 1 ) ( and hence c cGG GG s R s Y s H 1 ) ( ) ( ) ( (4 -14) Assume that the known open loop plant transfer function is a second order system and can be represented as ) 1 )( 1 ( ) (2 1S T S T k s G and the closed-loop reference model transfer function is represented by ) 1 ( 1 ) ( ) ( ) ( S T s R s Y s Hc (4 -15) Equating (4 -14) and (4 -15), we ge t c c cGG GG S T 1 ) 1 ( 1 ) 1 ( 1 S T GG GGc c c ) ( 1 ) ( s G sT s Gc c K sT T T s T T s s Gc c 2 1 2 2 1) ( 1 ) ( ) ( ) ( ) ( 1 1 ) (2 1 2 1 2 1 2 1T T s T T s T T K T T s Gc c (4 -16) Hence by knowing the desired system open loop transfer function, 2 1, T T we can estimate the value for in tegral, derivative and proportional gains. This is simple method to estimate the controller parameters when the open loop and desired closedloop response is known.

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152 4.3.2 Method IIOpen Loop Tuning Based On Unknown Plant Transfer Function In most of the c ases, both the plant transfer function and the closedloop transfer function of the system are unknown. In such situations, one of the classical methods adopted was to break the loop open and determine the step response of the open loop plant. Figure 45 s hows the step response of the open loop transfer function. From this empirical result the slope M the time delay dT and k the final value of the response is calculated. This method was described by Zeigler Nicholas [76]. d i dT K MT Kp 33 3 9 0 (4 -17a) and by using Cohen Coons method [77] 8 11 1 11 1 33 3 12 9 0 1d d d i d dT T T K T MT Kp (4 -17b) Hence the proportional and the integral gains are calculated. 4.3.3 Method III Loop Tuning Based on Closed-loop Cycling In certain situations, the loop cannot be brok en for analysis and will be available as a closedloop black box where an input can be applied and the system response can be obtained. In these cases, another closed -loop tuning loop tuning technique was described by Zeigler and Nicholas [76]. The approac h is defined as follows. Assume that a closed-loop system is implemented using a PID controller. Decrease the integral gains and the derivative gains. Apply a suitable proportional gain

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153 Apply a step response as the input and observe the system output. Ch ange the proportional gain iteratively until loop oscillates with a period T and amplitude A as shown in Figure 4-6. The smallest proportional gain that makes the output of the loop to oscillate is called as the ultimate gain, uK Based on the estimation of uK and the time period of oscillation T, the integral and the derivative gains are calculated as described.Let ultimate Kp Ku_ is the smallest proportional gain used when the loop response starts to oscillate. Let the amplitude of the oscillation is given by A and the time period is represented by T By characterizing A Ku, and T based on Ziegler and Nicholas approach the PID control parameters are calculated as described below. T Kd T Ki K Ku p125 0 5 0 6 0 (4 -18) The above mentioned techni ques can be used to determine a nominal loop gain settings and further manual automation and simulations should be used to determine the most accurate settings. In the described DSP -GC technique a combination of the above mentioned techniques are used to estimate nominal values for the integral gains and convergence factors analytically. The values calculated are then used as initial estimates in system simulations based on which the final accurate value of integral gains and convergence factors were obtain ed. The following section describes a novel method to predict the controller gains for an unknown thN order closed loop system.

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154 4.3.4 Method IV Implemented Loop Tuning Technique Based on Closed-loop Stability Constraint This section d escribes a novel method by which the controller gains are estimated based on pole placement stability constraint. Figure 47 shows a generic block diagram of a closed loop system with an integral controller. In z domain, the closed-loop parameters involved in the analysis are represented as follows. The unknown open loop plant transfer function is denoted as ) ( z Gp I K is the integral gain of the controller employed, ) ( z R is the system input represented in Z domain, ) ( z Y is the system output, ) ( z E is the error between the reference signal ) ) ( z R and the feedback signal ) ( z Y is the feedback gain DZ is the delay through the feedback path. The primary goal of this method is to estimate the maximum value of integral gain max IK above which the system become unstable. The significance of adopting this approach is that this technique does not require prior knowledge of the open loop system transfer function. The s teady state gain and the delay can be characterized as a lab experiment by applying a unit step input to the open loop system ) ( z Gp and by monitoring the system output. At steady state, irrespective of the order of the open loop plant transfer function ) ( z Gp it ca n be represented as L ssz G z Gp ) ( where ssGis the open loop steady state gain of the plant and Lz is open loop delay. Hence the open loop plant gain (ssG) and the delay ( Lz ) can be computed based on a step input analysis. Based on the estimated values for ssG and Lz the system block diagram at steady state can be represented as shown in Figure 48 The next step is to derive the expression of the closed -loop transfer function ) ( z H The system output is represented as ) ( ) ( ) ( z R z Y z H

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155 1 11 ) ( ) ( z z G z K z E z YL ss I (4 19a) where the error signal ) (z E and the feedback signal ) (z A is represented as ) () ( )( z A z R z E (4 19b) Dz z Y z A) ( ) ( (4 -19c) Combining Equation 419b, 4-19c results in ) ( ) ( ) ( z Y z z R z ED (4 19d) Using equations, 419a, 4-19d, the closed -loop system output ) ( z Y is represented as 1 1 1 1 1 1 1) ( ) ( ) ( ) ( 1 ) ( ) ( ) ( ) 1 ( ) ( ) ( ) ( L D I ss L I ss ss L I D ss L Iz K G z Y z K G z R z Y z z Y z G z K z z Y z R z Y z G z K z A z R z Y ] 1 [ ) ( ) ( ) ( ) ( ] 1 )[ (1 1 1 1 1 1 L D I ss L I ss L I ss L D I ssz K G z z K G z H z R z Y z K G z R z K G z z Y (4 19e) In order to represent 419e in powers of z, we multiply the numerator and denominator by ) 1 ( ) 1 ( L D L Dz z This result in ] [ ] 1 [ ) ( ) () (1 ) 1 ( ) 1 ( 1 1 1 I p L D L D D I ss LD L D L D I p L I ssK G z z z K G z z zK G z z K G z H z R z Y (4 20) Based on the z domain closed-loop stability constraint, the system ) ( z H as described by Equation 4 -20 is stable if the poles of the transfer function lie within the unity circle.

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156 Based on this constraint, the absolute value of the roots of the denominator of ) (z H should be less than 1. If this condition is true, then the system will have bounded output ) (n y for an input ) (n x .The poles of the transfer function are estimated by equating the roots of the denominator part of Equation 420 to zero. Equating the denominator to be equal to 0 results in 01 I ss L D L DK G z z (4 -21) The values for D Gss, and L are substituted based on open loop system characterization. In order to solve Equation 421 for th e max_ IK a random initial estimate of IK is assumed. The roots of the Equation 4 -21 are found by known numerical methods [78]. These calculated roots represent the poles ) 1 .... 0 ( L D k pk of the system function ) ( z H Once the poles are estimated, the magnitude of the maximum pole ) (maxmax_ k absp magnitude P is calculated. If absPmax_ is > 1.0, then the integral gain IK is decreased and the process is repeated. If absPmax_ <1.0, then the corresponding integral gain IK is denoted as the maximum value of integral gain max IK above which the system becomes unstable. The DSP algorithm than can be implemented in the radio software is described in Figure 49 As an example, assume that th e plant transfer function is ) 9234 0 891 0 )( 02 0 234 0 9235 0 )( 9235 0 )( 892 0 )( 2 0 ( ) 4912 0 )( 4523 0 )( 1212 0 )( 8782 0 ( 23 250 ) (2 2 3 s s s s s s s s s s s s s Gp (4 -22) As a first step, the steady state gain and the delay of the unknown transfer function is found by a step input to the open loop system. The step response of the open loop system ) ( s Gp is shown in F igure 4 -10. Based on this measurement, the steady state

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157 gain ss G is found to be 44.67 and the open loop delay is found to be samples L18 Hence, the estimated system parameters are Steady state open loop gain, ss G = 44.67, Forward path delay, L = 18 Feedback path delay, D = 10 (feedback path delay is known based on the digital filters used). Programmed feedback gain =0.5 ( -6dB) Substituting the values in the characteristic Equation I ss L D L DK G z z 1 results in 0 ) )( 67 44 )( 5 0 (28 29 IK z z (4 23) By employing the algorithm as illustrated in Figure. 49, the value of IK for which 0 1 ) (maxmax_ k absp magnitude P is estimated. The value of max IK below which the system becomes stable is found to be 0.0014 ( 57.07dB). The 29 estimated poles corresponding to max IK as the controller gain are tabulated in Table 4-2 Figure 4-11 shows the plot of 29 poles which lie inside the unit circle. Figure 412 s hows the, reference and the feedback signal, the loop error signal and the closed-loop step response with the predicted controller gains of max I IK K Depending on the system overshoot requirements, the integral gains can be further adjusted. 4.4 Closed -loop Delay and Loop Gain Margin Analysis After estimating suitable controller gains IK the effect of additional loop delay on the stability of the closedloop system is studied. The system architecture as described by the DSP -GC algorithm can b e simplified into a block diagram shown in Figure 413. The reference signal ) ( z R is compared with the feedback signal ) ( z A The error signal ) ( z E

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158 between the reference signal and the feedback signal goes into the controller ) ( z Gc The output of the controller drives the unknown plant ) ( z Gp The unknown plant in the system under consideration consists of the gain amplifier and the analog components in the transmit path of the mobile. When the closedloop power control occurs these components are already enabled and the transient behavior can be neglected. Thus, considering the steady state behavior of the unknown plant, we can model this as a gain stage. The feedback path which consists of the power detector, the digitizer, the analog filter can be modeled as a gain stage and a delay D Hence the feedback path can be represented asDz. 4.4.1 Effect of Loop D elay Analysis of the loop stability with increasing loop delay is essential to decide the operating sampling frequency of the ADC, the digital components and the appropriate bandwidths of the analog filters in the feedback path. Assume an integral control ler is used for the sake of analysis. Hence, the transfer function of the integral controller can be represented as 1 11 ) ( z z K z GI c where IK is the integral gain. The closed-loop system equations with the integral controller can be described as fo llows. D p Iz z Y z A z A z R z E z G z K z E z Y ) ( ) ( ) ( ) ( ) ( 1 ) ( ) (1 1 (4 -24a)

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159 Hence, 24b) (4 1 1 1 1 11) () ( ) ( ) 1 ( ) ( ) ( ) ( z z K G z G Kz Hz R z Y z G z K z A z R z YD I p p I p I It is evident from Equation 4 24b that the closed-loop stability is a function of the feedback loop delay, D the integral gain I K and the feedback gain The loop delay depends both on the operating digital sample rate sample rate Fs and on the delay introduced by the anal og components along the path. Typical loop delay calculations for the implemented architecture are shown in Table 4 -3. It is essential to estimate the minimum value of minD D above which the system will reach the verge of instability. The loop stability with increasing loop delays is analyzed by estimating the poles of the transfer function as described in Equation 424b. Figures 414, 4 -15 4-16 and 4-17 shows the pole zero plot for the closed-loop transfer function with the feedback loop delay D = 1, 3, 7, 9, 13, 17, 19, 21, 24, 26, 28, 31, 39, 45, 52 and 58 samples at the chosen sample rate Fs for the transfer function represented by 1 1 11 ) ( ) ( ) ( z z K G z G K z H z R z YD I p p I where ) 16 .0 ( 16 ) 9 ( 20 ), 046 0 ( 26 dB and dB Gp dBKI .As shown in Figure 4 -14, 4-15, 416 and 4-17 it is clear that for a fixed integral gain, the system stability decreases with increasing loop delay because the magnitude of the poles increases starts moving away from the center of the unit circle. The calculated delay through the loop is around 750nsec b ased on calculations as shown in Table 4 -3. Extensive simulations have been performed to guarantee the loop stability in the presence of additional delays. Figure 4-

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160 18 shows the steps response of the closed-loop system with increasing loop delay. As we can observe that the delay increases the loop stability decreases. Based on system simulations and empirical analysis it has been found that the loop can handle up to a maximum delay of 2.5usec to meet the 40usec settling time and the 3dB overshoot specificat ions. The adaptive filter implemented was used to reduce the signal variance and the integral controller was used to perform average gain tracking. As the goal of this loop was to perform average power tracking an appropriately tuned integral controller wa s efficient enough to result in the desired system metrics. This also reduced both the tuning process and the implementation complexity. 4.4.2 Gain Margin Analysis Once a nominal value of loop delay D which will guarantee loop stabili ty is known, for that particular value of loop delay, there exists a maximum and a minimum value of integral gain over which the system is stable. Figure 4-19 and Figure 4-20 shows the pole zero plot for a system with a loop delay of D = 13 samples and as a function of varying integral gains. It is clear from Figure 419 and Figure 4-20 that as the integral gains are increased, the closedloop stability decreases. Based on this observation it can be concluded that system becomes over damped and sluggish when the programmed integral gain is below a certain value (err_gain_min) and the loop becomes unstable and oscillates when the programmed gain is greater than a certain value (err_gain_max). As defined earlier section, the range of value s of integral gains between the err_gain_min and err_gain_max for which the system is stable is known as the gain margin. The integral gains IK and the convergence factor employed in the tracking algorithm determine the rate of converg ence and the stability of the closedloop

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161 system. Depending on the settling time requirements of the system protocol, the integral gains of the controller and the convergence factor of the adaptive filter are selected that will result in the desired peak o vershoot, the settling time and the steady state error. It can be observed from Figure 420 that as the integral gains are increased above -20dB, the system becomes unstable. Figure 421 shows the measured transfer function of the power detector which plot s the input Pout (dBm) vs. quantized feedback signal. Based on the measured characteristics, it is clear that the slope of the power detector is smaller at lower input power levels and larger at higher power levels. In the presence of such nonlinear syste ms within the closed-loop function, appropriate loop gain programming strategies have to be adopted to meet the desired system performance. As a strategy, in order to compensate for sluggish response at lower power levels, a higher integral gain (less attenuation) is used to make the loop respond faster. As the slope increases at higher power levels, a relatively lower integral gain (higher attenuation) is used to satisfy the desired system requirements of less than 3dB overshoot and 40usec settling time. H ence the closed -loop operating range is sub-divided into low, high and mid power control regions. As a result of the nonlinear open loop characteristics there are three regions over which the integral gains are chosen over the power control range of 0dBm to 24dBm transmit power level. System simulations and lab measurements conclude that for power levels between 0dBm and 6dBm, an integral gain of 20dB is used and for the range of power levels between 6dBm to 11dBm an integral gain of -40dB is used. Simil arly, for a range of power levels between 12dBm to 15dBm an integral gain of -50dB is used. In addition to

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162 this, as was explained analytically in Chapter 2, depending on the amount of power change, the controller gains are adjusted to maintain similar loop stability and gain margin over the entire range of closedloop operation. Based on simulations and lab measurements it has been found that the loop gain margin decreases with increasing loop delay. Figure 4-22 shows the range of values for integral gain allowed for particular target power decreases as the loop delay increases. It is clear from Figure 4-22 that the gain margin is around 20 dB when the feedback loop delay 200nsec and the gain margin decreased to around 14dB when the loop delay increases to 1.92usec. In this application the introduction of adaptive filter adds 4 samples of delay into the system. However this additional delay is tolerated based on the fact that faster settling time is obtained when the adaptive filter is used. 4.5 System Simu lation and Lab Measurement Results System simulations were performed for the implemented DSP -GC technique with the system models including RF analog circuitry Analog feedback path Additive noise Digital transmit path models Digital implementation of the s ystem architecture Sections 4.5.1 and 4.5.2 describe the system simulations and lab measurement results obtained by implementing the DSP -DGT algorithm. 4.5.1 System Simulations of the DSP -GC Method The system simulations were performed with simulation tools Matlab and SPW. The simulation models assumes that the modulation format was either constant envelope such as Gaussian minimum shift keying (GMSK) or non -constant envelope

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163 schemes such as codedivisionmultiple access. (CDMA). The reference signal is a ssumed to be a digital ramp signal stored in a look up table ROM implementation. In these system simulations a raised cosine signal is used as a reference signal kd The desired target power k kd pwr D corresponding to the required mobile output power level is known based on prior calibration. The DAC is assumed to operate at 62.4MHz. The simulations were performed with the fixed point digital circuits, the RF and analog system models in the presence of noise and nonlinear impairments. Various signal sources employing modulation schemes such as Binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), Gaussian minimum shift keying (GMSK) were used to simulate the implemented algorithm. By employing various modulation schemes with various PAR [23] the closed -loop dynamics such as the loop stability and steady state error is analyzed. Figure 423 shows the reference signal kD which is a ramp signal multiplied by the desired power value, pwr The corresponding feedback signal kA is shown to track the reference signal kD The error signal kE which is the difference between the reference signal and the feedback signal kE = k kA D is found to settle to zero depending on the integral gains and the convergence factor programmed in the loop. The integral controller accumulates the output of the adaptive filter as described by ) ( k acc This signal is then converte d to analog signal and either used to perform gain tracking on the digital baseband signal or can be used to control the bias voltage on the variable gain amplifier [9],[38]. Figure 4-23 illustrates that the error signal is positive because the reference s ignal is greater than the feedback signal. This denotes that more gain has to be added to the loop to increase the transmit power of the mobile device, thus resulting in power change in the positive direction.

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164 Figure 424 shows a situation where the mobi le device has been signaled to ramp down the target power. Hence the reference signal has a ramp down profile from the present reference value to a lower reference value. Since the feedback signal always lags the reference signal, the error between the feedback signal and the reference signal becomes negative and the closed-loop system tries to bring the error back to zero at steady state. Since the error signal is averaged and accumulated the closed loop system provides an output which reduces the gain of the forward path and hence reduces the output power of the mobile device. Based on simulations, it was found that the loop takes 30-35usec to adapt for +/ 7.5 dB of power change. Figure 4 25 shows the antenna power as a function of the LMS adaptation. The plot shows that transmit power ramp up and ramps down, the area under the error signal is minimized by the adaptive filter on a sample by sample basis. The filter weights are cleared after the power transition ends. Figure 4-26 show the loop dynamics of the feedback signal and the closed loop error signal as a function of the convergence factor. The goal of the adaptive algorithm is to dynamically compensate for the analog gain changes introduced on a sample by sample basis. The plot s5 in Figure 4-26 shows the adaptation of the error signal as a function of convergence factor. 4.5.2 Lab Measurements of the DSP -GC Adaptive Algorithm The measurement set up as explained in Chapter 2 is used to capture the output of the controller on the Tektronix oscilloscop e and the CMU2000 is used to capture the RF power output of the mobile device. Figure 4 -27 shows the analog output of the closed loop system captured by the Tektronix oscilloscop e The analog output is used to control the bias of the PA or the VGA to perfo rm gain control. Figure 427 shows that the closed-loop system responds to two consecutive power change commands. The

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165 controller and the loop operation corresponding to the two cases are described below in detail. Case 1: Mobile Power change in the positiv e direction As explained in earlier sections, when the mobile is requested to increase its transmitted power, the reference power programmed will be greater than the actual feedback power. During the closed-loop adaptation, this will result in a positive error signal. This positive error signal is then accumulated by the adaptive filter and integrated by the first order integrator. The accumulated signal is then used to perform gain control by either multiplying this loop output to the digital gain stage or the controlling by the bias of the driver amplifier. By accumulating positive error signal the loop response increase and hence increasing the gain in the loop. Case 2: Mobile Power change in the reverse directionWhen the mobile is requested to decrea se its transmitted power, the reference power programmed will be lesser than the actual feedback power. During the closedloop adaptation, this will result in a negative error signal. The negative error signal is then accumulated by the adaptive filter and integrated by the first order integrator. The accumulated signal is then used to perform gain control by either multiplying this loop output to the digital gain stage or the controlling by the bias of the driver amplifier. By accumulating negative error s ignal the loop response decreases and hence decreasing the gain in the loop. As a second example, Figure 4 -28 describes three consecutive gain adjustments made by the mobile device to change the transmission signal power level. Figure 428 shows the analo g bias signal increases the first two times to provide gain to the transmit path. At the third power change request, the bias signal decreases as the base -station

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166 has signaled the mobile device to decrease the transmit power. Figure 429 captured RF power at the output of antenna using CMU equipment. The carrier frequency is 1800MHz GSM band. As shown in Figure 429, the transmit power of the mobile device is increased from a lower power level to 0dBm. The implemented DSP -GC algorithm not only helps the mobile device to change the transmit power from a lower level to 0dBm, but also helps in maintaining the desired power of 0dBm until the end of signal transmission. 4.6 Summary The DSP -GC technique employs an adaptive filter to reduce the variance of the e rror signal at the input to the controller. System stability and gain margin analysis is performed as a function of loop delays. Based on the stability constraint approach, the maximum delay the loop can handle is estimated to be 2.4usec. Based on the kn owledge of steady state delay, the gain of the unknown plant transfer function, the feedback loop delay a novel loop tuning technique is used to estimate the controller gains for an thN order unknown plant. System simulations and lab mea surements show that the DSP -GC algorithm performs gain changes upto 90 dB dynamic range with a resolution of 0.1dB power accuracy. Since the variance of the error signal is minimized, lab measurements prove that the settling time improved by 15usec compared to DSP -DGT algorithm at the slight expense of gain margin reduction. The DSP -GC digital technique uses only 17K digital gates and the current drain is 22mA.

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167 Average Power Peak Null Figure 41. Power control A) Measured transmit power to show the PAR and PTN of a LTE signal captured by Rhode and Schwartz CMU 2000 B)S ystem architecture of the DSP -GC algorithm implemented in a mobile device

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168 GejwRFt RF Mixer PA VGA Filter DAC Filter DAC _gain ADC Tx Digital line up Filter Symbols from Modem 10101010101 RF Gain control amplifier Power Detector Digital to Analog convertern bit I n bit QRF dBm to DC Voltagedetection Gain control + Reference Signal ( ROM)N-Tap FIR Filter Integral Controller LMS Coeffecient calculation DkAkEkSkacckpwr bypass GIntegral gain Number_taps Figure. 4 -1 Continued

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169 DkAk+ Ek lms_clr 0 1 0<11,0,t> Upsample by 4 Sample and hold by 4 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 MUX Downsample by 4 MUX Ek-1Ek-2Ek-3Ek-4Ek-5Ek-6W1W2W3W4W5W6W7E2 k2E2 k<19,1,u> <20,1,u>2<10,0,u> kE W W S W Ek k k k k T 2 12 Sk Z-1 <20,0,t>KI Integral Gainacc(k)<10,0, u> <10,0,u> <12,0,u> clk lms_sel 1 0 Z-1 MUX clr Ek2E2 kWk 1 0 0 Figure 42. DSP hardware implementation of the adaptive filter and 1st o rder integrator

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170 Rise time Settling time Peak Overshoot I st undershoot Figure 43. System constraints in selecting the controller gains. Gc(s) G(s) R(s) Y(s) + Unknown Figure 44. Simplified closed-loop model Slope = M Time delay = Td kStep responsetime Figure 45. Open loop based tuning technique

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171 kClosed loop response to a step input A T Figure 46. Closed -loop based tuning techniq ue Z-1 Gp(z) Z-D R(z) Y(z) E(z) KI+ + + Gc(z) A(z) Figure 47. Closed -loop system with an integral controller Z-D R(z) Y(z) E(z) + Gc(z) 1 11 z z KI L ssz G* Figure 48. Discrete model of closed-loop system at steady state

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172 Set values for D, L and Gss Set initial value of KI Form Equation 01 I ss L D L DK G z z Is Pmax_abs>1. 0 Find the (D+L+1) roots, Pk Decrease Ki Output Ki max IK ) (maxmax_ k absp magnitude P Y N Figure 49. Flow chart to estimate integral gain Figure 4 10. Step response of the unknown open loop system

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173 Figure 411. Plot of poles of the transfer function with IK = max IK Figure 412. Closed-loop system simulations with appropriate integral gains

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174 Z-1 Gp(z) Z-D R(z) Y(z) E(z) KI+ + + Gc(z) Figure 413. Simplifie d model for loop delay and gain margin analysis Figure 414. Polezero location with loop delay, D = 1, 3, 7 and 9 samples at sample rate Fs.

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175 Figure 415. Polezero location with loop delay, D = 13, 17, 19 and 21 samples at sample rate Fs. Figure 416. Polezero location with loop delay, D = 24, 26, 28 and 31 samples at sample rate Fs.

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176 Figure 417. Polezero location with loop delay, D = 39, 45, 52 and 58 samples at sample rate Fs. Figure 418. Closed-loop step response with respect to varying plant delays.

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177 Figure 419. Polezero location with loop delay, D =13 samples and integral gains of 36 dB, -32dB, 30dB and 26dB. Figure 420. Polezero location with loop delay, D =13 samples and integral gains of 22 dB, -20dB, 6 dB and 9dB.

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178 Figure 421. Power detector and feedback path input output characteristics.

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179 -6 -16 -41 -48 -36 -50 -63 -70 -4 -15 -38 -42 -25 -35 -50 -58 -75 -72 -69 -66 -63 -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 Antenna Power (dBm) Integral gains (dB) err_gain_min_delay_200nsec err_gain_max_delay_200nsec err_gain_min_1.92usec err_gain_max_1.92usec Figure 422. Loop gain margin with varying loop delay as a function of antenna power

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180 Ideal integral _gain= 19dB Programmed integral _gain= 26 dB Reference signal ( Dk) Control loop voltage A k E k acc k Figure 423. Simulation to show the clo sedloop dynamics for a positive power change

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181 Convergence Factor:0.1, Taps:2 Meeting the desired settling time D k A k E k Reference signal Loop output signal acc(k) Figure 424. Simulation to show the closed loop dynamics for a negative power change

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182 Simulated Ouput power of Mobile device (dBm) Error signal adaptive to zero at the input of adaptive filt er during power up and power down Error signal adaptive to zero at the output of adaptive filter during power up and power down Weights adaptation And getting reset to zero Weights adaptation And getting reset to zero Figure 425. Simulation to show the a daptation of the LMS algorithm with weigh ts and error signal

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183 0. 08 0. 20 0. 25 0. 0 8 0. 20 0. 25 Convergence factor Convergence factor A k E k Figure 426. Simulation to show the rate of change of error signal and the feedback as a function of convergence factor Analog version of closed loop output acc (k) +ve Gain controlled performed when the error signal positive as the accumulator integrates the error signal. Helps mobile device to raise its power signal ve Gain controlled performed when the error signal positive as the accumulator integrates the error signal. Helps mobile device to decrease its power signal Signal gain change 1 Signal gain change 2 Figure 427. Analog response of the closed-loop system with the adaptive filte r captured by Tektronix oscilloscope

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184 1 st power change 2 nd power change Closed loop system adapting to multiple power change request Closed loop system adapting to power ramp down request Figure 428. Analog closed-loop response for multiple steps with the adaptive filter captured by Tektronix oscilloscope Closed loop adapt s to desired average power level with adaptive filter Figure 429. Transmit power of the mobile device captured by CMU 2000.

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185 Table 4 1. Weight update for the LMS filter Iteration ( k ) Filter Tap kw1 ( 1 N ) Filter Tap kw2 ( 2 N ) 0 k 0 1 o w 02ow 1 k 2 0 10 11E w w 2 0 20 21E w w 2 k 2 1 11 12E w w 2 1 21 22E w w 3 k 2 2 12 13E w w 2 2 22 23E w w 4 k 2 3 13 14E w w 2 3 23 24E w w .. n k 2 ) 1 ( ) 1 ( 1 1 n n nE w w 2 ) 1 () 1 ( 2 2 n n nE w w Table 4 2. Estimated Poles based on max IK k Poles kp ) (maxmax_ k absp magnitude P 1 0.9851 + 0.0438i 0.9861 2 0 .9851 0.0438i 0.9861 3 0.8939 + 0.2434i 0.9264 4 0.8939 0.2434i 0.9264 5 0.8011 + 0.4266i 0.9076 6 0.8011 0.4266i 0.9076 7 0.6790 + 0.5852i 0.8964 8 0.6790 0.5852i 0.8964 9 0.5291 + 0.7138i 0.8885 10 0.5291 0.7138i 0.8885 11 0.3572 + 0.8070i 0.8826 12 0.3572 0.8070i 0.8826 13 0.1707 + 0.8612i 0.8779 14 0.1707 0.8612i 0.8779 15 0.0221 + 0.8740i 0.8742 16 0.0221 0.8740i 0.8742 17 0.2123 + 0.8450i 0.8713 18 0.2123 0.8450i 0.8713 19 0.3912 + 0.7759i 0.869 20 0.3912 0.7759i 0.869 21 0.8641 0.8641 22 0.8433 + 0.1892i 0.8643 23 0.8433 0.1892i 0.8643 24 0.7819 + 0.3695i 0.8649 25 0.7819 0.3695i 0.8649 26 0.6828 + 0.5324i 0.8658 27 0.6828 0.5324 i 0.8658 28 0.5505 + 0.6700i 0.8672 29 0.5505 0.6700i 0.8672

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186 Table 4 3. Feedback path delay calculation Delay component Description Delay Anti aliasing filter after (AAF) ADC 1 Pole RC F3dB = 1.3 MHz ns f delaydB122 2 13 ADC + Digital filter stages after ADC Through simulations and implementation structures 300nsec DAC reconstruction filter response time that controls the VGA output change F3dB = 1.3 MHz Second order butter worth filter ns f delaydB230 2 414 13 AAF Bandwidth variation due to Process/temperature 100nsec PA and power detector Enabled long before and hence not significant delay contributor 0 Total possible delay 752nsec

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187 CHAPTER 5 CONCLUSIONS, APPLICA TIONS & SCOPE FOR FU TURE DIRECTIONS 5.1 Thesis Summary The resear ch work describes techniques to control and compensate for absolute and relative gain variations caused in mobile devices due to imperfections in RF and analog circuits. It also clarifies the difference between the power control techniques employed at the base -station and in mobile devices. R eal time analys e s with ongoing cellular projects are used to describe the various steps involved in any mobile based gain control Past, present and recent methods of power controls are described in Chapter 1. A clear d istinction of the functions of RFIC, base band processor and the base-station has been made and described in detail. Chapter 2 describes a novel DSP technique to track for absolute gain variations in any mobile device caused by the performance degradation of analog and RF circuits as a function of operating voltages, temperature and frequency bands. This DSP DGT technique employs a digital PID controller and a signal correlation circuit to track for gain variations in the transmit signal path of a mobile d evice. The digital techni que has been found to use only 22K gates and the current drain is 20mA Since this technique is a complete digital implementation, it reduces bulky analog circuitry and complex power amplifier bias circuitry requirements. System s imulations and lab measurements prove that the DSP -DGT algorithm compensates for absolute gain variations better than 0.1dB accuracy independent of modulation schemes adopted. Chapter 3 outlines a method to compensate for the relative gain and phase errors to maintain power control accuracy requirements. The DSP -GPE technique uses DSP circuits to estimate the relative gain error o f the analog RF gain amplifier and provides

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188 DNL gain error compensat ion In addition, this technique is used to calibrate the car rier phase changes that happen in any mobile device due to change in the capacitive load impedances on the RF analog path. System lab measurements and simulations prove that t he implemented DSP -GPE algorithm estimates and compensate s for gain errors better than 0.1dB accuracy and phase errors better than 1 degree accuracy. The digital techni que uses less than 10K gates and the current drain is 12mA Chapter 4 presents the DSP -GC technique and corresponding hardware structures to dynamically control the absol ute signal power of a mobile device by using an adaptive filter along w ith an integral controller. The DSP -GC technique makes the closed loop system robust to higher signal variances. In addition to reducing the gate area, the DSP -GC algorithm also employs a novel control loop tuning technique based on stability constraints. This technique is used as a systematic method to estimate the controller gains of a closed -loop system with an unknown thN order plant transfer function. System stability of the implemented architecture as a function of variations in loop delays is analyzed. System simulations and lab measurements show that the DSPGC technique can perform gain changes upto 90 dB dynamic range with a resolution of 0.1dB accuracy. The convergence time of the loop is reduced to 35usec from 50usec. The DSP-GC digital techni que uses only 17 K gates and the current drain is 22mA. Table 5 1, Table 5 -2 and Table 5 -3 differentiates between the industrial and academic focus involved in the DSP -DGT, DSP -GPE and the DSP -GC techniques respectively .

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189 5.2 Other Areas of Applications The algorithms and system implementation presented and implemented can be employed in base-station transmitters along with the existing power control techniques. The DSP h ardware implementations on base -station receivers and transmitters can be further analyzed. Suitable techniques can be used to track the random carrier phase shifts offsets introduced by the voltage control oscillators in mobile devices. The DSP DGT and GP E gain tracking techniques can be employed to any power regulation circuit where precise signal tracking accuracy is desired. The correlation DSP -DGT algorithm can be used in RF applications such as power amplifier droop compensation, signal power correcti on during gain compression and saturation of RF amplifiers. The DSP -GC technique can also be applied to adaptively control the tune line voltage of any voltage control oscillators used in mobile devices.

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190 LIST OF REFERENCES [ 1 ] L.Sundstrom, Fast and Accurate ACLR Estimation Method in Proc IEEE Radio and Wireless Conf., 2004, pp. 183186. [ 2 ] Oscar Pedro B.Torrecampo, Correlation of two tone 3rd order Intermodulation Distortion Ratio and EDGE Adjacent Channel Power Ratio at 900 MHz, in Proc Int Conf on Elec tronic Material & Packaging, Conf., 2006 pp. 1 -5. [ 3 ] David Jarman, A Brief Introduction to Sigma Delta Conversion, Intersil C orporation, App Note AN9504 May 1995. [ 4 ] Rahul Gupta, Saad Ahmad, Reinhold Ludwig, and John McNeill, Adaptive Digital Baseband P redistortion for RF Power Amplifier Linearization, High Frequency Electronics, Summit Technical Media LLC 2006, pp1625. [ 5 ] Noureddine Boulejfen, Afef Harguem, and Fadhel M .Ghannouchi, New ClosedForm Expressions for the Prediction of Multitone Inte rmodulation Distortion in Fifth -Order Nonlinear RF Circuits/Systems, IEEE Trans. on Microwave Theory and Techniques pp 121 132. Jan. 2004. [ 6 ] S.Mann, M.Beach, P.Warr and J.McGeehan, Increasing the Talk -Time of Mobile Radios With Efficient Linear Transmit ter Architectures, Electronics & Communication Engineering Journal vol. 13, pp.65 76, Apr. 2001. [ 7 ] Oleksandr Gorbachov, Yu Cheng, and Jason S.W.Chen, Noise and ACPR Correlation in CDMA Power Amplifiers, R F Amplifiers May 2001. [ 8 ] Mueller et al, Multi -band Handset Architecture U S. Patent 7383024 B2, June 3, 2008. [ 9 ] Jin -Su Ko, Hyun -Seok Kim, Sung-Gi Yang, Bonkee Kim and ByeongHa Park, Bias Control Technique For CDMA Driver Amplifier to Decrease Current, IEEE MTT-S Int. Microwave Symp. Dig. 2001, vol. 3,pp 2219 -2222. [ 10 ] Wang Xinwei, Hiroshi Nakamura, Rajinder Singh, ACPR, IM3 and their Correlation for a PCS CDMA Power Amplifier ARFTG Conf., Dig vol. 32, pp 9196 Dec. 1997 [ 11 ] Chunmig Liu, Heng Xiao, Qiang Wu, Fu li, Linear RF Power Amplifier Design for Wireless Signals: A Spectrum Analysis Approach, in Proc IEEE Int Conf., on Acoustic Speech and Signal Processing, vol. 4, pp.56871 Apr. 2003 [ 12 ] W.J Warren and W.R.Hewlett, An Analysis of the Intermodulation Method of Distortion Measurement, in Proc of the IRE vol. 36 pp 457466,Apr. 1948

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193 [ 43 ] Xian bin Wang, T.T.Tjhung, Reduction of Peak to Average Power Ratio of OFDM System Using a Companding Technique, IEEE Trans. on Broadcasting, vol. 45, pp 303 307 Sep. 1999. [ 44 ] Jeroen R.Willemsen, Andre C.Li nnenbank, Mark Poste, Cornelis A.Grimbergen, Signal Averaging of Non -Stantionary Noise, in Proc of the First Joint BMES/EMBS Conf., Serving Humanity Advancing Technology, Oct 1999. [ 45 ] Harald Pretl, Linus Maurer, Werner Schelmbauer, Robert Weigel, Bernd Adler,Josef Fenk, Linearity Considerations of W -CDMA Front Ends For UMTS, IEEE MTT -S Int Microwave Symp. Dig 2000, vol. 1, pp 433 436. [ 46 ] Abdellatif Bellaouar, RF Transmitter Architectures for Integrated Wireless Tranceivers Int Conf., on Microelectroni cs, 1999,pp. 2530. [ 47 ] Allen Katz, Linearization: Reducing Distortion in Power Amplifiers, IEEE Microwave Magazine, 2001 vol. 2, pp. 374 9 [ 48 ] Sanggee Kang, Heonjin Hong, Hyungsoo Lee, Sungyong Hong, The characteristics of a Transmitters ACLR for WCDMA. I EEE MTT -S Int Proceedings of Microwave and Optoelectronics Conf., 2001, vol. 1, pp 43 45. [ 49 ] Chunmig Liu, Heng Xiao, Qiang Wu, Fu Li, Spectrum Design Of RF Amplifier for Wireless Communication Systems, IEEE Trans. on Consumer Electronics vol. 48, Feb 20 02. [ 50 ] Cecil W. Thomas, Mark S. Rzeszotarski, Barry S. Isentein, Signal Averaging by Parallel Digital Filters, IEEE Trans. on Acoustics, Speech Processing, vol. 30, Apr 1982. [ 51 ] Aristotele Hadjicristos, Transmit Architectures and Power Control schemes For L ow Cost Highly Integrated Transceivers for GSM/EDGE App s, IEEE 0 780377613, 2003. [ 52 ] Jeonghyeon Cha, Youngoo Yang, Bumjae Shin, Bumman Kim, An adaptive Bias Controlled Power Amplifier with a load modulated Combining Scheme for High Efficiency and Linearity IEEE MTT S Int Microwave Symp. Dig 2003, vol. 1, pp.81 -84. [ 53 ] Yoshifumi Toda, Adjustable Transmitter Power Control Circuit, U.S.Patent 5603,106, February, 1997. [ 54 ] Adrian Jarrett, Amplifier Gain Control Circuit Arrangements, U.S.Patent 4,849, 7 12, July 18, 1989. [ 55 ] Atusushi Miyake, Automatic Power Controlling Transmitting Power of Modulated Radio Frequency Signal,U.S. Patent 5,408,197, April 18, 1995.

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196 [83] Tektronix TDS3034B 300 MHz Digital Oscilloscope User Manual. Author : Tektronix Incorporated. [updated 04 April 2005] Available from http://www.tequipment.net/pdf/tektronix/TDS3000B_UserManual.pdf

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197 BIOGRAPHICAL SKETCH Pravinkumar Premakanthan was born on Feb 3, 1979 in Chennai, India. He graduated from State Bank Officers Association (S.B.O.A) high school in Anna N agar, Chennai, India in 1996. He obtained his b achelor s in Electrical and Electronics Engineering (EE) from College of Engineering, Guindy (C.E.G) Anna University, Chennai in the year 2000. He pursued his m aster s degree in EE under the research guidance of Dr. Wasfy Mikhael at the University of Central Florida, Orlando and graduated in the year 2002. Upon completing his m aster s degree, h e worked as wireless system engineer with Motorola Semiconductors from 20022005. During these three years, he had the opport unity to design and develop wireless ICs for cellular phones. In 2004, while working at Motorola Semiconductors, he started to pursue his PhD with the Computational Neuro Engineering laboratory (CNEL), University of Florida, (UF) under the guidance of Dr. John Harris. He joined as a full -time student at the Department of EE, UF in Aug 2005. After spending a year and half at CNEL, he re joined wireless team with Freescale Semiconductors and pursued active research and development work while still continuing his doctorate studies. He is presently working as a wireless system lead engineer with Fujitsu Microelectronics in Tempe, Arizona. He holds five U.S patents in the area of wireless transceivers. Upon completion of his doctorate degree he will continue his present role as wireless system lead at Fujitsu Micrelectronics. He lives with his wife, Manjula in Chandler, Arizona. Pravins greatest mentor and role model in life is his PhD advisor, Dr. John Harris.