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- Permanent Link:
- https://ufdc.ufl.edu/UFE0041400/00001
## Material Information- Title:
- Embedded S-Parameter Measurement
- Creator:
- Lee, Ming
- Place of Publication:
- [Gainesville, Fla.]
- Publisher:
- University of Florida
- Publication Date:
- 2010
- Language:
- english
- Physical Description:
- 1 online resource (195 p.)
## Thesis/Dissertation Information- Degree:
- Doctorate ( Ph.D.)
- Degree Grantor:
- University of Florida
- Degree Disciplines:
- Electrical and Computer Engineering
- Committee Chair:
- Eisenstadt, William R.
- Committee Members:
- Fox, Robert M.
Harris, John G. Crisalle, Oscar D. - Graduation Date:
- 4/29/2010
## Subjects- Subjects / Keywords:
- Bandwidth ( jstor )
Calibration ( jstor ) Electric potential ( jstor ) Error rates ( jstor ) Gold standard ( jstor ) Reflectance ( jstor ) Reflectometers ( jstor ) Signal detection ( jstor ) Signals ( jstor ) Simulations ( jstor ) Electrical and Computer Engineering -- Dissertations, Academic -- UF analyzer, embedded, measurement, microwave, millimeterwave, network, onchip, parameter, reflectometer, rf, scattering, spr, testing, vector, vna - Genre:
- Electronic Thesis or Dissertation
born-digital ( sobekcm ) Electrical and Computer Engineering thesis, Ph.D.
## Notes- Abstract:
- This dissertation focuses mainly on research concerning embedded S-parameter measurement system implementation. The most severe challenge is to exploit a small area on a chip to realize functionality of complicated measuring systems such as commercial vector network analyzers (VNAs). To make this possible, many existing circuits within a VNA need to be simplified or rethought, and fabrication variation must be stringent. Fortunately, with the explosive performance advances of semiconductor technology, it now becomes more practicable to build on-chip S-parameter measurement systems. Two different strategies are explored in this research work. The first approach is to build on-chip RF signal manipulating networks by simplifying the front-end structure of a VNA. Two systems, denoted as S11 and S21 detection networks, are developed. More specifically, two lumped passive integrated circuits, including directional couplers and dividers, are used to construct detection systems operational at approximately 10 GHz. Working differently than a traditional RF signal flow manipulation in a VNA, the networks enable S-parameter measurements by directly reading the outputs from cascaded amplitude and phase detectors, without the need of traditional back-end data processing typical of VNA designs. To solve the issue of anticipated process variation and to extend the usable bandwidth, three calibration methods are presented for the S11 detection network and one calibration method is developed for the S21 detection network. The second strategy is to use a totally different structure, the six-port reflectometer (SPR), to accomplish embedded S-parameter measurements. Two SPR designs with central frequencies targeted at 20 GHz and 40 GHz are developed. A bipolar junction transistor (BJT) amplitude detector and its closed-form detection theory are introduced, along with two dividers and two phase shifters. The BJT amplitude detector, capable of performing both single-ended and differential detection, can work up to 80 GHz. The resistive divider and lumped phase shifter are applied to the 20-GHz SPR. The lossless divider and transmission-line phase shifter are applied to the 40-GHz SPR to deal with the more rigorous measuring conditions at higher frequencies. To determine the best detector characterization models for SPRs, a new figure-of-merit and its calculation algorithm are also presented. ( en )
- General Note:
- In the series University of Florida Digital Collections.
- General Note:
- Includes vita.
- Bibliography:
- Includes bibliographical references.
- Source of Description:
- Description based on online resource; title from PDF title page.
- Source of Description:
- This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
- Thesis:
- Thesis (Ph.D.)--University of Florida, 2010.
- Local:
- Adviser: Eisenstadt, William R.
- Electronic Access:
- RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2011-04-30
- Statement of Responsibility:
- by Ming Lee.
## Record Information- Source Institution:
- University of Florida
- Holding Location:
- University of Florida
- Rights Management:
- Copyright Lee, Ming. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
- Embargo Date:
- 4/30/2011
- Resource Identifier:
- 700510606 ( OCLC )
- Classification:
- LD1780 2010 ( lcc )
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PAGE 1 1 EMBEDDED S -PARAMETER MEASUREMENT By MING CHE LEE A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2010 PAGE 2 2 2010 Ming Che Lee PAGE 3 3 To my parents for their support, encouragement, and constant love PAGE 4 4 ACKNOWLEDGMENTS I would like to express my deep gratitude and appreciation to my advisor, Profess or William R. Eisenstadt, for his patient, constant encouragement and devotion. Under his supervision, I had opportunities to work in microelectronics, which eventually became a joy for me. I also would like to thank Professor Robert M. Fox, Professor John G. Harris and Professor Oscar D. Crisalle for their interests in this work and serving on my Ph.D. supervisory committee. I would like to thank all the former and current colleagues in the Mixed -Signal/RFIC Embedded Test research group for their helpful discussions, advice, and friendship. Some names are listed here: Moishe Groger Devin Morris Said Rami, Byul H ur, Wako Tuni, Sha di Harb and Hyunho Baek Much appreciation goes to National Nano Device Laboratories, Hsinchu, Taiwan, for supporting essential test equipment. Finally, I am grateful to my parents, to whom this work is dedicated. PAGE 5 5 TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................................... 4 LIST OF TABLES ................................................................................................................................ 9 LIST OF FIGURES ............................................................................................................................ 10 ABSTRACT ........................................................................................................................................ 17 CHAPTER 1 INTRODUCTION ....................................................................................................................... 19 1.1 S Parameters and the Traditional Way of Measurement .................................................... 19 1.2 The Idea of Embedded S -Parameter Measurement ............................................................ 20 1.3 The Challenges of Embedded S -Parameter Measurement ................................................. 21 1.4 The Opportunities for Embedded S -Parameter Measurement ........................................... 22 1.5 Research Goal ....................................................................................................................... 26 1.6 Outline of the Dissertation .................................................................................................... 28 2 LUMPED PASSIVE CIRCUITS FOR EMBEDDED TESTING OF RF SoCs ..................... 30 2.1 Overview ............................................................................................................................... 30 2.2 Lumped Passive Integrated Directional Coupler ................................................................ 30 2.3 Lumped Passive Integrated Divider ..................................................................................... 31 2.4 Simulation Results ................................................................................................................ 32 2.5 Fabrication Results ................................................................................................................ 33 2.6 Conclusion ............................................................................................................................. 34 3 ONCHIP S -PARAMETER DETECTION NETWORKS ....................................................... 36 3.1 Overview ............................................................................................................................... 36 3.2 Embedded S11 Detection Network ....................................................................................... 36 3.3 Embedded S21 Detection Network ....................................................................................... 39 3.4 Simulation Results ................................................................................................................ 42 3.5 Experimental Results ............................................................................................................ 44 3.6 Conclusion ............................................................................................................................. 50 4 CALIBRATION FOR ON CHIP S -PARAMETER DETECTION NETWORKS ................ 54 4.1 Overview ............................................................................................................................... 54 4.2 Calibration Methods for Embedde d S11 Detection Network .............................................. 55 4.2.1 Type I Calibration Method ........................................................................................ 55 4.2.2 Type II Calibration Method ....................................................................................... 58 4.2.3 Type III Calibration Method ...................................................................................... 65 PAGE 6 6 4.3 Calibration Method for Embedded S21 Detection Network ............................................... 66 4.4 Conclusion ............................................................................................................................. 72 5 AMPLITUDE DETECTOR ....................................................................................................... 75 5.1 Overview ............................................................................................................................... 75 5. 2 Main Circuit Structure and Detection Theory ..................................................................... 76 5.2.1 Single -ended Detection Theory ................................................................................. 77 5.2.2 Differential Detection Theory ................................................................................... 82 5.3 Simulation Results ................................................................................................................ 83 5.3.1 Single -ended Amplitude Detector ............................................................................. 83 5.3.2 Differential Amplitude Detector ................................................................................ 84 5.3.3 Matched Single -Ended Amplitude Detector ............................................................. 86 5.4 Experimental Results ............................................................................................................ 88 5.5 Conclusion ............................................................................................................................. 95 6 SIX PORT REFLECTOMETER ............................................................................................... 96 6.1 Overview ............................................................................................................................... 96 6.2 Theory of Six-Port Reflectometer ........................................................................................ 96 6.3 Calibration Procedure ........................................................................................................... 99 6.4 S ystem Design of SixPort Reflectometer ......................................................................... 100 6.4.1 SPR Targeted at 20 GHz .......................................................................................... 102 6.4.2 SPR Targeted at 40 GHz .......................................................................................... 103 6.5 Simulation Results .............................................................................................................. 104 6.5.1 SPR Targeted at 20 GHz .......................................................................................... 105 6.5.2 SPR Targeted at 4 0 GHz .......................................................................................... 106 6.6 Experimental Results .......................................................................................................... 107 6.6.1 SPR Targeted at 20 GHz .......................................................................................... 107 6.6.2 SPR Targeted at 40 GHz .......................................................................................... 112 6.6.2.1 Measurement Results at 30 GHz .................................................................. 114 6.6.2.2 Measurement Results at 40 GHz .................................................................. 117 6.6.2.3 Measurement Results at 50 GHz .................................................................. 119 6.7 Conclusion ........................................................................................................................... 123 7 OPTI MIZATION FOR DETECTOR CHARACTERIZATION IN SIX -PORT REFLECTOMETER ................................................................................................................. 124 7.1 Overview ............................................................................................................................. 124 7.2 Characterization Models ..................................................................................................... 127 7.2.1 Bergeault Model ....................................................................................................... 127 7.2.2 Demers Model .......................................................................................................... 128 7.3 Encountered Problems ........................................................................................................ 128 7.3.1 The Determination of Model Type .......................................................................... 131 7.3.2 The Determination of Model Order ........................................................................ 131 7.3.3 The Determination of Intrinsic Parameter .............................................................. 131 7.4 Two Types of Linearity ...................................................................................................... 132 PAGE 7 7 7.4.1 MPPP Linearity ........................................................................................................ 132 7.4.2 RMSPP Linearity ..................................................................................................... 133 7.4.3 Relationship between MPPP Linearity and RMSPP Linearity ............................. 134 7.4.4 Potential Problem of MPPP Linearity ..................................................................... 135 7.5 Optimization Algorithm ..................................................................................................... 138 7.5.1 Figure -of -Mer it for Simulation ................................................................................ 138 7.5.2 Figure -of -Merit for Measurement ........................................................................... 139 7.6 Simulation Results .............................................................................................................. 141 7.6.1 Success of the Determination of Model Type ........................................................ 141 7.6.2 Success of the Determination of Model Order ....................................................... 143 7.6.3 Success of the Determination of Intrinsic Parameter ............................................. 144 7.7 Another Method of Verification ........................................................................................ 145 7.8 Conclusion ........................................................................................................................... 146 8 SUMMARY AND SUGGESTIONS FOR FUTURE WORK ............................................... 148 8.1 Summary.............................................................................................................................. 148 8.2 Suggestions for Future Work ............................................................................................. 150 APPENDIX A MORE DETAILED DISCUSSIONS OF THE DESIGN CONCEPTS IN CHAPTER 3 .... 153 A.1 Discussions of the Embedded S11 Detection Network .................................................... 153 A.2 Discussions of the Embedded S21 Detection Network .................................................... 155 A.2.1 First Order Non ideality Analysis of the Embedded S21 Detection Network ..... 155 A.2.2 Design Clarification for the Embedded S21 Detection Network .......................... 157 A.3 Ana lysis of the Intentional Open in the Embedded S11 Detection Network .................. 160 B MORE MEASUREMENT DATA ANALYSIS IN CHAPTER 3 ........................................ 162 B.1 Mo re Measurement Data Analysis of Embedded S11 Detection Network ..................... 162 B.2 More Measurement Data Analysis of Embedded S21 Detection Network ..................... 167 C THE VARIABLE FORMATION IN CHAPTER 4 ............................................................... 172 C.1 The Formation of Variables a, b, c, d from Type I Calibration Method......................... 172 C.2 The Formation of Variables a, b, c, d from Type II Calibration Method ....................... 173 C.3 The Formation of Variables l, m, n, o, p, q from Type II Calibration Method .............. 177 C.4 The Formation of Variables a, b, c for S21 Detection Network Calibration ................... 180 D THE EXAMPLE GOLDEN DUTS IN CHAPTER 4 ............................................................. 182 D.1 The Golden DUTs for Embedded S11 Detection Network .............................................. 182 D.2 The Golden DUTs for Embedded S21 Detection Network .............................................. 182 PAGE 8 8 E SENSITIVITY ANALYSIS OF THE CALIBRATION METHODS IN CHAPTER 4 ...... 184 E.1 Sensitivity Analysis of Calibrations for Embedded S11 Detection Network .................. 184 E.1.1 Type II Calibration Method..................................................................................... 184 E.1.2 Type III Calibration Method ................................................................................... 186 E.2 Sensiti vity Analysis of Calibration for Embedded S21 Detection Network .................... 188 LIST OF REFERENCES ................................................................................................................. 192 BIOGRAPHICAL SKETCH ........................................................................................................... 195 PAGE 9 9 LIST OF TABLES Table page 3 1 Average and variance of the S11 detection network measurement results .......................... 48 3 2 Average and variance of the S21 detection network measurement results .......................... 52 4 1 Three Types of calibration method for the embedded S11 detection network .................... 74 4 2 The normal and over determined results of the calibration method for the embedded S21 detection network ............................................................................................................. 74 6 1 Specifications of loads and measurement re sults of the 20GHz SPR at 20 GHz ........... 112 6 2 Specifications of loads and measurement results of the 40GHz SPR at 30 GHz ........... 116 6 3 Sp ecifications of loads and measurement results of the 40GHz SPR at 40 GHz ........... 119 6 4 Specifications of loads and measurement results of the 40GHz SPR at 50 GHz ........... 122 6 5 The maximum measurement error for each test condition ................................................ 123 7 1 Reflection coefficients of the eight loads serving as calibration standards ...................... 130 7 2 Maximums and minimums of power ratios with varying input voltages for each load .. 130 7 3 Different multiples between the real and measure d power ratios ..................................... 130 E 1 Sensitivity analysis results of Type II calibration method for S11 detection network ..... 186 E 2 Sensitivity analysis results of Type III calibration method for S11 detection network .... 188 E 3 Sensitivity analysis results of the calibration method for S21 detection network ............. 191 PAGE 10 10 LIST OF FIGURES Figure page 1 1 Internal schematic of HP 8516A. .......................................................................................... 20 2 1 Schematic and design values of the lu mped passive integrated directional coupler. ........ 31 2 2 Simplified signal flow graph of the lumped passive integrated directional coupler. ......... 31 2 3 Schematic and design values of the lumped passive integrated divider. ............................ 32 2 4 Simplified signal flow graph of the lumped passive integrated divider. ............................ 32 2 5 Simulation results of the lumped passive integrated directional coupler. .......................... 33 2 6 Simulation results of the lumped passive integrated divider. .............................................. 34 2 7 Die micrographs of directional coupler and divider. A) Die micrograph (345m x 405m) of the lumped passive integrated directional coupler, B) Die micrograph (270m x 300m) of the lumped passive integrated divider. ............................................. 34 3 1 System -level architecture of the proposed on-chip S11 detection network. ........................ 37 3 2 Schematic and design values of the DUT1. .......................................................................... 37 3 3 Signal propagation within the embedded S11 detection network. ....................................... 39 3 4 System -level architecture of th e proposed on-chip S21 detection network. ........................ 40 3 5 Schematic and design values of the DUT2. .......................................................................... 40 3 6 Signal propagation within the e mbedded S21 detection network. ....................................... 42 3 7 Simulation results of the embedded S11 detection network. ................................................ 43 3 8 Simulation results of the embedded S21 detection network. ................................................ 44 3 9 Die micrograph of the embedded S11 detection network. .................................................... 45 3 10 Measurement results of the embedded S11 detection network. ........................................... 46 3 11 Enlarged picture of Figure 3 10. ........................................................................................... 47 3 12 Error percentage of the measurement results of the S11 detection network. ....................... 47 3 13 Error difference of the measurement results of the S11 detection network. ........................ 47 3 14 Die microg raph of the embedded S21 detection network. .................................................... 48 PAGE 11 11 3 15 Measurement results of the embedded S21 detection network. ........................................... 49 3 16 Enlarged picture of Figure 3 15. ........................................................................................... 51 3 17 Error percentage of the measurement results of the S21 detection network. ....................... 51 3 18 Error differen ce of the measurement results of the S21 detection network. ........................ 51 4 1 Type I flow graph of the embedded S11 detection network. ................................................ 56 4 2 Comparisons between the real S11_DUT1 and the calibrated S11_DUT1 by the Type I calibration method. ................................................................................................................. 57 4 3 Error percentage of the Type I calibration result. ................................................................ 58 4 4 Type II flow graph of the embedded S11 detection network. .............................................. 6 0 4 5 Derived value of r50 by Equation 4 2. .................................................................................. 61 4 6 Comparisons between the real S11_DUT1 and the calibrated S11_DUT1 by Type II calibration method. ................................................................................................................. 61 4 7 Derived S11 values and ideal S11 values of DUT3, DUT4, and DUT5. .............................. 62 4 8 Calibration result of DUT3, DUT4, and DUT5 by Type II calibration method. ............... 63 4 9 Comparisons between the real S11_DUT1 and the calibrated S11_DUT1 by Type II calibration method. ................................................................................................................. 64 4 10 Error percentage of the Type II calibration result. ............................................................... 64 4 11 Comp arisons between the real S11_DUT1 and the calibrated S11_DUT1 by Type III calibration method. ................................................................................................................. 66 4 12 Error percentage of the Type III calibration result. .............................................................. 66 4 13 Flow graph of the embedded S21 detection network. ........................................................... 67 4 14 Comparisons between the real S21_DUT2 and the calibrated S21_DUT2 after calibrating the embedded S21 detection network by five golden DUTs. ............................................... 71 4 15 Error percentage of the calibration result by five golden DUTs. ........................................ 71 4 16 Compari sons between the real S21_DUT2 and the calibrated S21_DUT2 after calibrating the embedded S21 detection network by ten golden DUTs. ................................................. 72 4 17 Error percentage of the calibration result by ten go lden DUTs. ......................................... 73 5 1 The main structure of the proposed amplitude detector. ..................................................... 76 PAGE 12 12 5 2 Using the detector as a differential amplitude d etector. ...................................................... 76 5 3 Using the detector as a single -ended amplitude detector. .................................................... 77 5 4 The Lamberts W function when x ranges from 0 to 10. ..................................................... 81 5 5 The values of S11 looking into the input port of the single -ended detector with respect to different VBIAS values. A) Magnitude, B) Phase. ............................................................. 83 5 6 Input -output relation of the single -ended amplitude detector. ............................................ 84 5 7 The values of S11 looking into the two input ports of the differential detector with respect to different values of r1. A) Magnitude of port 1, B) Phase of port 1, C) Magnitude of port 2, D) Phase of port 2. .............................................................................. 85 5 8 Input -output relation of the differential amplitude detector. ............................................... 86 5 9 Matched single ended amplitude detector. ........................................................................... 86 5 10 The magnitude of S11 looking into the two input ports of the matched single -ende d amplitude detector with respect to different values of VBIAS. ............................................. 87 5 11 Input -output relation of the matched single -ended amplitude detector. ............................. 88 5 12 The die micrograph of the stand alone matched single -ended amplitude detector. ........... 88 5 1 3 Measurement results of the matched single-ended amplitude detector at 21 GHz. ........... 89 5 14 Measurement results of the matched single-ended amplitude detector at 40 GHz. ........... 90 5 15 Measurement results of the matched sing le -ended amplitude detector at 50 GHz. ........... 91 5 16 Measurement results of the matched single-ended amplitude detector at 60 GHz. ........... 91 5 17 Measurement results of the matched single-ended amplitude detector at 67 GHz. ........... 92 5 18 Calibrated measurement results of the amplitude detector at 21 GHz. ............................... 92 5 19 Calibrated measurement results of the amplitude detector at 40 GHz. ............................... 93 5 20 Calibrated measurement results of the amplitude detector at 50 GHz. ............................... 93 5 21 Calibrated measurement results of the amplitude detector at 60 GHz. ............................... 94 5 22 Calibrated measurement results of the amplitude detec tor at 67 GHz. ............................... 94 5 23 Superimposition of calibrated measurement results at different frequencies. .................... 95 6 1 Block diagram of a six port reflectometer. ........................................................................... 96 PAGE 13 13 6 2 .................................................. 99 6 3 Complete set of calibration procedures for SPR. ................................................................. 99 6 4 System design of the on-chip SPR. ..................................................................................... 101 6 5 A) Schematic of the resistive power divider, B) Schematic of the phase shifter. ............ 102 6 6 Layou t of the lossless power divider. .................................................................................. 104 6 7 S parameter simulation results of the resistive divider. A) magnitude, B) phase. ........... 105 6 8 S parameter simulation results of the lumped phase shifter. A) magnitude, B) phase. ... 105 6 9 Simulated S21 of the 20GHz SPR. A) magnitude, B) phase. ............................................ 106 6 10 S parameter simulation results of the micro -strip divider. A) magnitude, B) phase. ...... 106 6 11 S parameter simulation results of the transmission -line phase shifte r. A) magnitude, B) phase. ............................................................................................................................... 107 6 12 Simulated S21 of the 40GHz SPR. A) magnitude, B) phase. ............................................ 107 6 13 Die micrograph of the 20G Hz SPR. .................................................................................. 108 6 14 Measured S21 of the 20GHz SPR. ...................................................................................... 109 6 15 Test set up for the 20 GHz SPR. ......................................................................................... 109 6 16 Lateral and vertical views of the probe station set up. ...................................................... 110 6 17 Output of the embedded detectors for the first 5 loads at 20 GHz. ................................... 110 6 18 Output of the embedded detectors for load 6 to load 11 at 20 GHz. ................................ 111 6 19 ................................... 112 6 20 Die micrograph of the 40GHz SPR. .................................................................................. 113 6 21 Measured S21 of t he 40GHz SPR. ...................................................................................... 113 6 22 Output of the embedded detectors for the first 6 loads at 30 GHz. ................................... 115 6 23 Output of the embedded detect ors for load 7 to load 15 at 30 GHz. ................................ 115 6 24 Comparis ................................... 116 6 25 Output of the embedded detectors for the first 6 loads at 40 GHz. ................................... 118 6 26 Output of the embedded detectors for load 7 to load 15 at 40 GHz. ................................ 118 PAGE 14 14 6 27 ................................... 119 6 28 Output of the embedded detectors for the first 6 loads at 50 GHz. ................................... 120 6 29 Output of the embedded detectors for load 7 to load 15 at 50 GHz. ................................ 121 6 30 ................................... 122 7 1 Typical detector characterization flow of SPR. .................................................................. 125 7 2 Transf er function of diode -connected BJT amplitude detectors. ...................................... 129 7 3 Measured power ratios are level as input signal changes its amplitude. .......................... 129 7 4 An SPR diagram with input power source and embedded detectors. ............................... 133 7 5 The requirement of MPPP linearity. ................................................................................... 133 7 6 Illustration of the potential problem of MPPP linearity. ................................................... 136 7 7 RMSPP linearity detects the ill-conditioned characterization result. ............................... 137 7 8 Figures -of -merit for the three models M1, M2, and M3. A) full range Total error, B) zoomedin Total error, C) full range CV total and D) zoomed in CV total. .................... 141 7 9 Another way to visualize Figure 7 8. .................................................................................. 142 7 10 The relationship between Total error and CV total. A) full range, B) zoomed in. .......... 143 7 11 Total error helps decide the optimal order for a specific model. A) no input voltage interpolation, B) with input voltage interpolation. ............................................................. 144 7 12 Determination of the optimal values for q. A) Total error, B) CV total. .......................... 145 7 13 The relationship between Total error and CV total2. A) full -range, B) zoomed in. ....... 146 8 1 The integration of cascaded detectors for the S11 detection network. ............................... 150 8 2 The integration of cascaded detectors for the S21 detection network. ............................... 151 8 3 The structure of a dual SPR system. ................................................................................... 151 A 1 Modified signal propagation within the embedded S11 detection network. ..................... 153 A 2 The magnitude of the parameter A in Equation A 4. ......................................................... 155 A 3 Modified signal propagation within the embedded S21 detection network. ..................... 156 A 4 The magnitude of the S23 of the divider. ............................................................................. 157 PAGE 15 15 A 5 Original system level architecture of the S21 detection network. ...................................... 158 A 6 Simulation result of the network in Figure A 5. ................................................................ 159 A 7 Error percentage of the S21_DUT2_DERIVED in Figure A 6. .................................................... 159 A 8 Error percentage of the S21_DUT2_DERIVED in Figure 3 8. ..................................................... 159 A 9 The layout surroundings of the intentional open. ............................................................... 160 A 10 The parasitic capacitance at the open node reported by Raphael. ..................................... 161 B1 The over -simplified DC model of the S11 detection network. ........................................... 163 B2 The simplified DC model of the S11 detection network. .................................................... 164 B3 The resistance seen by port 2 in Figure B 2. ...................................................................... 165 B4 T he resistance seen by port 3 in Figure B 2. ...................................................................... 165 B5 The slope of the difference of slope for the five resistors. ................................................ 166 B6 The mag nitude comparison between the simulated and measured S21 and S31. ............... 167 B7 The simplified DC model of the S21 detection network. .................................................... 168 B8 The resistance seen by port 1 when measuring port 1 and port 2. .................................... 169 B9 The resistance seen by port 1 when measuring port 1 and port 3. .................................... 169 B10 The phase comparison between the simulated and measured S21 and S31. ....................... 171 D 1 The schematic of the example golden DUTs for S11 detection network. ......................... 182 D 2 The schematic of the first group example golden DUTs for S21 detection network. ....... 183 D 3 The schematic of the second -group example golden DUTs for S21 detection network. .. 183 E 1 Sensitivity analysis results of Type II calibration method with 1% deviation. ................ 185 E 2 Sensiti vity analysis results of Type II calibration method with 2% deviation. ................ 185 E 3 Sensitivity analysis results of Type II calibration method with 3% deviation. ................ 186 E 4 Sensitivity analysis results of Type III calibration method with 1% deviation. ............... 187 E 5 Sensitivity analysis results of Type III calibration method with 2% deviation. ............... 188 E 6 Sensitivity analysis results of Type III calibration method with 3% deviation. ............... 188 PAGE 16 16 E 7 Sensitivity analysis r esults of the calibration method for S21 detection network with 1% deviation. ........................................................................................................................ 190 E 8 Sensitivity analysis results of the calibration method for S21 detection network with 2% deviation. ........................................................................................................................ 190 E 9 Sensitivity analysis results of the calibration method for S21 detection network with 3% deviation. ........................................................................................................................ 191 PAGE 17 17 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy EMBEDDED S -PARAMETER MEASUREMENT By Ming -Che Lee May 2010 Chair: William R. Eisenstadt Major: Electrical and Computer E ngineering This dissertation focuses mainly on research concerning embedded S -parameter measurement system implementation T he most severe challenge is to exploit a small area on a chip to realize functionality of complicated measuring systems such as com mercial vector network analyzers (VNAs) To make this possible many existing circuits within a VNA need to be simplified or rethought and fabrication variation must be stringent Fortunately, with the explosive performance advances of semiconductor technology, it now becomes more practicable to build on -chip S -parameter measurement systems. Two different strategies are explored in this research work. The first approach is to build on -chip RF signal manipulating networks by simplifying the front -end stru cture of a VNA. Two systems, denoted as S11 and S21 detection networks are developed More specifically two lumped passive integrated circuits, including directional coupler s and divider s are used to construct detection systems operational at approximat ely 10 GHz. W orking different ly than a traditional RF signal flow manipulation in a VNA the networks enable S parameter measurement s by directly reading the outputs from cascaded amplitude and phase detectors without the need of traditional back -end data processing typical of VNA designs To solve the issue of anticipated process variation and to extend the usable bandwidth, three calibration PAGE 18 18 methods are presented for the S11 detection network and one calibration method is developed for the S21 detection network. The second strategy is to use a totally different structure, the six -port reflectometer (SPR), to accomplish embedded S -parameter measurement s Two SPR designs with central frequencies targeted at 20 GHz and 40 GHz are developed. A bipolar juncti on transistor ( BJT ) amplitude detector and its closed -form detection theory are introduced along with two dividers and two phase shifters. The BJT amplitude detector, capable of performing both single -ended and differential detection, can work up to 80 GHz. The resistive divider and lumped phase shifter are applied to the 20GHz SPR The lossless divider and transmission -line phase shifter are applied to the 40 GHz SPR to deal with the more rigorous measuring conditions at higher frequencies. To determine the best detector characterization models for SPRs, a new figure -of -merit and its calculation algorithm are also presented PAGE 19 19 CHAPTER 1 INTRODUCTION 1.1 S -Parameters and the Traditional Way of Measurement Due to the difficulty of achieving perfect open and short circuit conditions at high frequencies, scattering parameters (S -parameters) became the mainstream parameter that is used to characterize the performance of circuits, chips, or systems in RF/microwave/millimeter -wave scenarios. As the RF era is ubi quitous nowadays, scattering parameters play an essential role in the modeling and verification of a variety of devices, chips, packages, and transmission lines. S parameters are defined through the ratios of the forward and backward propagating waves, whi ch generally contain the magnitude and phase information. Therefore, unlike the measurement of analog/mixed -signal/digital integrated circuits where only real -valued voltages and/or currents are measured, S -parameters are measured through complex values in order to fully describe both the magnitude and phase of the system. Based on this, it can be imagined that the design of an S -parameter measuring instrument is more difficult and complicated than that of some measuring devices that obtain only real valued readings for analog/mixed -signal/digital integrated circuits at relatively low frequencies. The traditional way to measure S -parameters is through a vector network analyzer (VNA). A commercial VNA is basically a machine that has a complicated system both in hardware and software within its microprocessor system. The hardware part needs to properly tune and guide the input RF signal and correctly down -convert and sense the output signal at baseband. The software part needs to be able to correctly analyze al l the nonidealities within the hardware part, compensate the nonidealities to the utmost, calculate and display the final measurement results, and interface with microwave CAD software. The RF measurement concept can be better PAGE 20 20 comprehended through Figure 1-1, where the intern al schematic of the HP 8516A VNA RF front end [1][2] is shown. Figure 1-1. Internal schematic of HP 8516A. 1.2 The Idea of Embedded S-Parameter Measurement Just like the testing cost of analog/mixed-signal integrated circuits is much higher than that of the digital ones, measuring S-parameters for RF integrated circuits wi th VNAs is much more expensive than testing the analog/mixed-signal ones with automatic test equipment (ATE). This high cost of testing RF integrat ed circuits by measuring their S-parameters with VNAs sharply reduces the profit of microwave IC products especially when the trend of Systems-on-a-Chip is so prevalent today. Therefore, although academi cally feasible for measuring S-parameters, VNAs are considered insufficient by industry for characterizing pr oduction chips due to the high PAGE 21 21 increment of testing cost on top of manufacturing cost. With a vision that minimal additional cost is required to test a RFIC after being fabricated, the id ea of embedded S -parameter measurement emerges in the hope of replacing the expensive VNAs. Another reason that the idea of embedded S -parameter measurement becomes so attractive is because it can increase the portion of a chip being measured. As the fabri cation technology of semiconductor advances so rapidly nowadays, chip complexity is also increasing at an explosive rate For a complicated product undergoing the design cycle, such high complexity makes it difficult to test the internal nodes within the s ystem. Hence, the product may become unrepairable and unprofitable by having too little information and not knowing how to redesign to improve performance Similar to the scan chain concept in memory testing, by having the embedded S -parameter measurement circuitry, the measurable nodes inside of the RF integrated circuits are increased. T he diagnosis time will be reduced, which will in return reduce the time to the market and increase the profit. The new technologies such as 3D IC will require methods of o n -chip verification for RF circuit since RF nodes may be buried deep inside a chip stack. Verification of RF performance is also a key use of onchip S -parameters. 1.3 The Challenges of Embedded S -Parameter Measurement Although the idea of embedded S -param eter measurement sound s like a potential way to reducing the cost of production ICs, there exist several challenges that may hinder the progress in the realization of this idea. One issue is that the embedded S -parameter measuring circuitry is much more co mplicated than the circuitry used for digital, analog, or mi xed -signal ICs as explained in S ection 1.1. Due to the innate higher complexity of embedded S parameter measurement circuitry, if the design is not compact enough, the extra expense cost by the ad ditional chip area that is occupied by the embedded measuring circuitry is likely to overweigh PAGE 22 22 the sav ings in test cost and thus nulli fy the original purpose of implementing embedded S parameter measurement systems. Another potential issue of having embedded S -parameter measurement is the issue of signal disturbance. For a RF system, there exist some high-frequency nodes that are very sensitive to noise or unwanted signal coupling and would perform better when not loaded by extra circuitry When these sens itive nodes are connected to the embedded S -parameter measuring circuitry, it is necessary to make sure that the loading impact caused by adding the embedded circuitry is reduced to the minimum so that the device under -test (DUT) does not deviate too much form the original design specification s When the impact is not negligible, some compensation needs to be made, which will require more power in the design and add to the part cost through additional chip area. One last major difficulty in realizing embedd ed S -parameter measurement s comes from the limitation s of semiconductor fabrication technology. Because the semiconductor fabrication process es have different features the available types of devices and their corresponding electronic characteristics and f abrication variations are also different. This causes the problem that particular embedded S -parameter measurement circuit may become impossible to implement when chips are fabricated in certain types of semiconductor fabrication technologies. For example, a quality diode can be implemented in a process that supports quality bipolar transistors, but it cannot be fabricated in a pure CMOS technology. Therefore, this issue of technology dependence makes it difficult for a particular embedded S -parameter measu rement circuit to be a general solution that is applicable to every production RF integrated circuit 1.4 The Opportunities for Embedded S-Parameter Measurement In spite of the challenges of embedded S -parameter measurement s mentioned in Section 1.3 the a dvantages of the technique still remain in peoples minds and various research is being PAGE 23 23 conducted. In view of the rapid increase in the RFIC complexity and the increasing operating frequencies, more and more nodes within a n RF SOC cannot be measured through the conventional method of using VNAs. To measure such a complex system, the idea of embedded S parameter measurement becomes desirable Fortunately, some challenges start to melt away and some opportunities for embedded S parameter measurement start to unfold as the semiconductor technology advances. First of all, some compact systems for S parame ter measurement are proposed [3][ 4]. These new structures are simpler circuit -wise and easier to be made on -chip. Due to the simplification of measuring structu re and the circuit compliance to the scaling down prediction of the Moores law, the area overhead caused by the embedded measuring circuitry can be greatly reduced. For on -chip lumped passive devices, the area can be even more greatly reduced when the mea suring frequencies go higher [5][ 6]. Furthermore, as the cost of semiconductor area today less expensive than the cost of using VNAs, engineers will be less concerned about the extra area caused by the extra embedded measuring circuitry. In order to minimi ze the possible disturbance to sensitive high -frequency nodes caused by the addition of embedded measuring circuitry, some helpful design strategies can be adopted. For an embedded measuring circuit with a shunt connection that minimizes stimulus to the or iginal design, the impedance looking into the embedded measuring circuit is normally designed to be very high so that the reflection coefficient looking into it is as close to unity as possible. For a series embedded measuring circuit that does cause any r eflected wave into the original design, the impedance looking into the embedded measuring circuit is normally made as close to the characteristic impedance as possible. In addition to these two techniques, researchers have spent effort o n the invention of various on -chip RF switches [ 7]. Hopefully, the perturbation in PAGE 24 24 performance caused by the embedded S -parameter measurement systems can continue to be reduced. For the issue of limitation in semiconductor fabrication technology, the situation is also having a favorable turn. As the fabrication technology progresses, a variety of techniques have been invented to reduce process variations. This way, many non -ideal electronic characteristics of devices can be suppressed and hence the result of embedded S -parame ter measurement can be more precise and the calibration procedure can be simpler. Moreover, much research has been performed in order to build measuring circuits with modern technologies. For example, it is possible to replace the traditional amplitude det ectors made by diodes or bipolar transistors with det ectors made by MOSFETs [ 8]. An embedded S -parameter measurement system originally composed of the amplitude detectors made by diodes can only be applied to processes that support diodes or quality bipola r transistors. However, after the detectors within the system are replaced with those made by MOSFETs, the system becomes applicable to the general CMOS technologies. As this kind of improvement proceeds, the embedded S parameter measurement becomes less r estricted to particular semiconductor technologies. The reuse concept similar to that for digital design becomes viable also in RF embedded measurement s and will further foster the popularity of embedded S -parameter measurement in production RFICs. There are still many other advantages that make the idea of embedded S parameter measurement more favorable. Although they cannot be detailed one by one due to the limitation of space, at least three other major advantages can be introduced. The first is that ci rcuits can be measured without the addition of package effect s by utilizing embedded S -parameter measurement. Because the package is easily overlooked, and usually an afterthought to designing the die, it is often found that a high -performance die in an in ferior package results in a mediocre - PAGE 25 25 performing component when measuring externally with a VNA. Also, the drive to keep package cost low results in inferior microwave package housing high performance silicon. However, by measuring circuits on chip or on wa fer without the noise and parasitic loading of package, the chance of this kind of tradeoff can be reduced and the component can be better characterized. The second major advantage is that the need of test fixtures can be reduced. Because many RF packages cannot be directly probed, there needs to be test fixtures playing the bridge role between the package and the cables. Although test fixtures are cheaper than wafer probe stations and offer more flexibil ity to the RF port location, they add parasitics, suc h as ground loops and RF reflections at the interfaces, to the characterization scheme. Besides, since the calibration plane is not usually at the packages pads, accurate de -embedding becomes essential. Fortunately, having embedded S -parameter measurement helps avoid these cumbersome procedures. The third major advantage is that there is less chance to have an erroneous measurement. The typical RF measurement system is composed of a VNA, RF cables, bias cables, and an interface to the DUT. The interface is either RF on -wafer probes or a test fixture. With such a large set of test equipment exposed to the outside world, it is very possible to make errors during the measuring process because the quality of the test systems RF performance depends on the quali ty of the VNA, the reliability of the RF cable and fixture connections, and the calibration quality. That is, attempts at RF measurement fail when parts of the test system are corrupted by errors. An embedded S -parameter measurement system that is fabricat ed in a decent fabrication technology with little process variation, on the other hand, after it has been well designed and tested, can provide data with much higher reliability due to its hidden and fixed measuring PAGE 26 26 structure. Hence, in the aspect of reduc ing measuring errors, the idea of embedded S -parameter measurement is also favorable to production RFICs. 1. 5 Research Goal As mentioned in S ection 1.1, S -parameters are measured through complex numbers, by which both the magnitude and the phase of the rat ios of RF waves can be fully specified. Since various amplitude and phase detectors are found in the literature [9][10][11][12] that are able to directly process high -frequency signals without the need of down-conversion, this dissertation explores circuit s in which all the RF signal s are processed directly and the traditional down conversion circuitry can be disused. Although high-frequency amplitude and phase detectors are suitable for building up embedded S -parameter measurement systems, they cannot meas ure the S parameters by working alone. Instead, some indispensable networks are necessary to properly manipulate RF wave flows and create suitable signals for the detectors to sense. Thanks to the advances of semiconductor fabrication technology and the increase on the measuring frequency, more and more essential passive components for RF measurement, such as power dividers, start being realizable in their lumped form [ 13] which occupies much less area than their distributed counterpart In view of the emer gence of these factors, the first aspect of t his research tries to explore and construct networks that can properly manipulate RF signal flows so that amplitude and phase detectors can be directly cascaded in the future to sense the processed signals and t hus achieve the goal of measuring S parameters. The manipulating RF networks are composed of simple lumped integrated circ uits that are easy to fabricate with reasonable chip areas. Containing only some passive elements, such as capacitors and resistors, t he proposed simple -structured networks overcome the issue of technology dependence mentioned in S ection 1.3 and can be a general solution for most of the available semiconductor fabrication technologies today. PAGE 27 27 As mentioned in S ection 1.4, new compact syste ms for measuring S -parameters are continually being proposed. Among all the proposed systems, the six -port reflectometer [3][4] is one of the most popular. Based on a sound mathematical theory, the six-port reflectometer is able to measure complex -valued S -parameters by having only one type of detector, the amplitude detector, inside the system. That is, phase detectors are no longer necessary. This disuse of phase detectors not only simplifies the system structure, but it also means that the S parameter me asurement system is less restricted in technology selection mentioned earlier. This approach may serve as a general solution. By building a simple signal manipulating network as the core and by properly spreading the amplitude detectors in different locati ons, the S parameters can be determined through a set of complicated mathematical operations on the analog voltage readings by the microwave amplitude detectors. Because the six -port reflectometer has a robust ma thematical theory background [ 14], it is les s vulnerable to the drift of system performance due to process variation. Since the difficulties in mathematical calculations can be alleviated by todays high performance computers, the two major advantages predominate and make the sixport reflectometer engagingly good. That is, the invulnerability to system performance drift makes sure that no chip gets discarded because of the malfunction of the embedded measuring circuitry, and the disuse of phase detectors widens the applicability of six -port reflecto meter for different technologies. Considering these two major advantages stated above, the second direction that this research tries to investigate is to construct some six -port reflectometers that are of modern design structures and can perform the measur ement of S -parameters. In addition to hardware implementation s in view of the importance of this detector characterization step to the SPR operation this research also reexamine s with care the existing characterization algorithms and PAGE 28 28 proposes a new algor ithm that helps determine the best characterization model when given a set of SPR specifications 1. 6 Outline of the Dissertation This dissertation is organized in eight chapters. The first chapter introduces the background for th e embedded S -parameter mea surement the challenges and opportunities of such an idea, the go al of research, and the outline of this research work In C hapter 2, a lumped passive integrated directional coupler and a lumped passive integrated divider are pr esent ed. In C hapter 3, two network s the embedded S11 and the embedded S21 detection network s are develop ed by using the lumped integrated devices pr esent ed in Chapter 2 In C hapter 4, to discern between malfunctions from the networks and DUTs and to expand the usable bandwidth, a variety of calibration methods for the network s in Chapter 3 are present ed. Three different calibration methods, accommodating different conditions and providing with different precision levels, are developed for the embedded S11 detection network One cal ibration method is developed for the embedded S21 detection network In C hapter 5, one simple amplitude detector whose core is a diode -connected NPN bipolar transistor, is present ed. The detector has two major advantages. The first is its simple structure and the second is its variable measuring configurations. Both advantages make the develop ed amplitude detector a good candidate for on-chip S -parameter measurement. Chap ter 6 introduces the six -port reflectometer. The operation theory a nd the calibration theory of six -port reflectometer are well discussed. Two six -port reflectometer systems are present ed One has a central operating frequency of about 20 GHz and the other has a central operating frequency of about 40 GHz. PAGE 29 29 Chapter 7 pr esents the concept of Type II linearity for the detector characterization in six port reflectometer. The difference between Type II and Type I linearity is well discussed. By exploiting the concept of Type II linearity, a new algorithm that can help dynamically determine th e op timal model for the detector characterization in six -port reflectometer is pr esente d Chapter 8 summarizes the dissertation and presents some suggestions for future work. PAGE 30 30 CHAPTER 2 LUMPED PASSIVE CIRCU ITS FOR EMBEDDED TES TING OF RF SOCS 2 .1 Overview Similar to the great need for precision passive components inside of a VNA, there is also an essential demand for their existence in an embedded RF SOC testing system The passive component s are of such great importance because they can manipul ate the RF signal flows in many ways, such as power splitting or signal coupling, and this manipulation is necessary for every kind of RF test system. Thanks to the rapid advance of the semiconductor fabrication technology nowadays it becomes more promisi ng to fabricate low loss on -chip inductors and capacitors and precise on -chip resistors, which are suitable to construct ma n y lumped element passive integrated circuits To show the practicability of the integration of lumped passive device s and to prepa re for the implement ation of the two embedded S -parameter detection networks proposed in Chapter 3 the designs of one lumped passive integrated directional coupler and one lumped passive integrated divider are presented in this chapter 2.2 Lumped Passive Integrated Directional Coupler The lumped integrated directional coupler (D RC) is designed via a transform ation from the coupled line directional coupler [15][16][17 ]. The equations for deriving the values of the capacitors and inductors are well describe d in [13] Composed of five MIM capacitors and six spiral inductors, the lumped passive integrated directional coupler is designed in a 0.18 m IBM 7RF technology and the schematic is shown in Figure 2 1. As a four -port network, the DRC couples, transmits, and isolates the input signal according to the port position of the input. For example, v iewing port 1 as the input port makes port 2, port 3 and port 4 the coupling, transmitting, and isolation ports respectively. Figure 2 2 shows the PAGE 31 31 simplified signal flow graph of the DRC when the four ports are assumed to be correctly terminated. According to the design specifications, a certain portion of the input signal from port 1 will be coupled to port 2 (i.e. S21), a certain portion will be transmitted to port 3 (i.e. S31), and there should be ideally no signa l received at port 4 (i.e. S41 = 0). With this unique coupling ability, a DRC can distinguish between the fo rward and the backward propagating waves and proves to be very useful for building up embedded S-parameter measurement systems. Figure 2-1. Schematic and design values of the lumped passive integrat ed directional coupler. Figure 2-2. Simplified signal flow graph of the lumped passive integrat ed directional coupler. 2.3 Lumped Passive Integrated Divider Similar to the lumped passive integrated DRC, the lumped passive integrated divider (DIV) [13] can also be construc ted by using some passive com ponents. Composed of four MIM capacitors, two spiral inductors, and one K1 BE OL resistor, the lumped passive integrated divider is designed in a 0.18-m IBM 7RF technology and the schematic is shown in Figure 2-3. PAGE 32 32 Figure 2-3. Schematic and design values of the lumped passive integrated divider. As a three-port network, the divider serves main ly as a signal splitter. Figure 2-4 shows the simplified signal flow graph of the DIV when the three ports are assumed to be correctly terminated. If a RF signal is input from port 1, the divider divides the input signal into two signals with equal magnitude and identical phase and outputs them to port 2 and port 3 (i.e. S21 = S31). With this unique ability of signal splitting, it becomes feasib le to generate two or more identical RF half power signals from one given RF signal source. Since th is signal duplication is another essential requirement in most of the Sparameter measurement systems in that it allows the realization of comparing a modi fied RF signal due to some diffe rence in path to the reference RF signal and hence obtaining the char acteristics of that path, the divider is also very useful in the construction of embedded S-pa rameter measurement systems. Figure 2-4. Simplified signal fl ow graph of the lumped passive integrated divider. 2.4 Simulation Results Targeted at the frequency of 10 GHz, the 10 dB lumped integrated directional coupler has its simulation results shown in Figure 2-5, where th e port 1 is now regarded as the input port. It PAGE 33 33 can be s een that most of the input signal launched from port 1 enters into port 3, and a portion of about 10 dB is coupled to port 2 as it is designed for at 10 GHz In addition, the signal reaching port 4 can be seen to be about 34 dB instead of ideally being i nfinitely small Figure 2 6 shows the simulation results of the lumped passive integrated divider designed in Figure 2 3. As can be seen, the S -parameters S21 and S31 equal each other both in magnitude and in phase for the whole frequency range. Figure 2 5 Simulation result s of the lumped passive integrated directional coupler. 2.5 Fabrication Results Due to the limited design wafer area and in the hopes of demonstrating the more powerful functions of the lumped passive integrated DRC and DIV, no standalone DRC and DIV is fabricated. Instead, they are fabricated as parts of the embedded S11 and S21 detection networks presented in Chapter 3 Figure 2 7 shows the die micrograph of the fabricated DRC and DIV. In Figure 2 7(A), it can be seen that the six s piral inductors are placed symmetrically and the four MIM capacitors are also placed symmetrically at the four corners, and one MIM capacitor is placed in the center. The size of the DRC is about 345 m by width and 405 m by length. In PAGE 34 34 Figure 2 7(B), it c an be seen that that the two spiral inductors are placed symmetrically and the four MIM capacitors are also placed symmetrically at the four corners. The size of the divider is about 270 m by width and 300 m by length. Figure 2 6 Simulation result s o f the lumped passive integrated divider. A B Figure 2 7 Die micrographs of directional coupler and divider. A) Die micrograph (345m x 405m) of the lumped passive integrated directional coupler, B) Die micrograph (270m x 300m) of the lumped passive integrated divider. 2.6 Conclusion The designs of the lumped passive integrated DRC and DIV in 0.18m IBM 7RF process are presented in this chapter T he sim ulation result s show the practicability of integrating lumped passive circuits on chips. This success of constructing lumped passive integrated circuits opens PAGE 35 35 the doors to the realization of the embedded S parameter detection networks pr esent ed in Chapter 3 In stead of being fabricated alone, the pr esent ed directional coupler and di vider are fabricated as parts of the embedded S11 and the embedded S21 detection networks introduced later on. The size of the fabricated directional coupler is about 345 m by width and 405 m by l ength and the size of the fabricat ed divider is about 270 m by width and 300 m by length. PAGE 36 36 CHAPTER 3 ONCHIP S -PARAMETER DETECTION NETWORKS 3 .1 Overview As mentioned in C hapter 1, in order to reduce the excessive cost in production chip testing with vector network analyzers (VNA s ), it may become important t o build example embedded S parameter measurement systems Therefore, b ased upon the success of constructing lumped passive circuits on chip and according to the special functions of the directional coupler and divider discussed in the preceding chapter t wo types of on-chip detection network s enablin g the measurement of S11 and S21 of a device under test (DUT) using power and phase detectors, are present ed in this chapter. The embedded S11 detection network is composed of one divider (DIV) and two directi onal couplers (D RC). The embedded S21 detection network is composed of three dividers. These two simple -structured networks prove to be successful and provide for a minimal extra increase o f the chip manufacture cost for on -chip VNA capability 3 .2 Embedde d S11 Detection Network The system level architecture of the proposed on chip S11 detection network [18 ] is shown in Figure 3 1, where port 1 is the input port and port 2 and port 3 are the output ports In addition to the specification s of the system -lev el ports, port definitions inside of each component are also given through the circled numbers in Figure 3 1. A mplitude and phase detectors can be cascaded and connected to the system output ports to inc rease the level of integration. Constructed in such a simple structure containing only two directional couplers, one divider, and one DUT, the proposed system is able to report the S11 of the DUT (S11_DUT1). This S11 is measured when back end circuits divide the S31 of the system (S31_SYS), i.e. the signal f rom port 1 to port 3, by the S21 of the system (S21_SYS), i.e. the signal from port 1 to port 2. Figure 3 2 shows the schematic and design values of the DUT1 used in Figure 31. PAGE 37 37 Port 1 D R C DUT1 50 DIV 1 2 3 1 2 3 4 Port 2 D R C 1 2 3 4 Port 3 50 1 Figure 3 1. System level architecture of the pr oposed on-chip S11 detection network Port 1 L = 2 nH C = 409 fF R = 50 C Figure 3 2. Schematic and design values of the DUT1. By defining S31_SYS over S21_SYS as S11_DUT1_DERIVED, Equation 3 1 shows that th is newly defined term will equal the S11 of the DUT 1 u nder such system arrangement at the targeted frequency 1 11 1 11 21 31 DUT DERIVED DUT SYS SYSS S S S (3 1) In fact, t he accuracy of the equality between S11_DUT1_DERIVED and S11_DUT1 in Equation 3 1 is based upon five assumptions that are described as follows 1 Coupling b etween port 2 and port 3 of DIV is negligible This assumption requires that there is no coupling in effect between the port 2 and port 3 of the divider. That is, S23_DIV and S32_DIV should ideally be infinitely small. The reason for this assumption is for occasions when the characteristic impedance looking into the port 1 of the D RC no longer equals 50 In this situation, there w ill be a reflection at the port 1 of the D RC, PAGE 38 38 and this reflected signal will then spoil the signal integrity of the two intentionally -separated branches if the S23_DIV and S32_DIV are not negligibly small. 2 High order reflections are negligible Because the validity of the proposed system is based upon the first order approximation of the RF signal flow graph, unwanted high -order r eflections may also damage the performance of the system. By developing a system in which high -order reflections will be dissipated to a negligible level, the efficacy of Equation 3 1 can be guaranteed. 3 Signal leakage through pairs of ports having high iso lation in the D RC is negligible As introduced in S ection 2.2, viewing port 1 of the D RC as the input port makes the DRC port 4 an isolation port, where ideally no signal flows o ut However, this kind of isolation is not perfect in reality and some signal may leak through pairs of ports that have high isolation To validate Equation 3 1 and thus make the system work, it is necessary to have the power of such signal leakage through isolated paths be negligibly small when compared to the signal of interest. 4 The intentional open has a reflection coefficient of unity It can be noted that the port 3 of the upper D R C in Figure 3 1 is intentionally left as open. Although ideally an open has a reflection coefficient of unity, the actual reflection coefficient of this intentional open is influenced by the surrounding environment in its neighborhood and may not exactly be unity To validate Equation 3 1 this assumption requires that the neighborhood of this intentional open be clear ed of parasitic element s to an ex tent that this open has a reflection coefficient of unity. 5 The two 50 and are truly 50 It can be seen in Figure 3 1 that there are two 50each D RC. These two resistors are used to terminate any further reflections into port 2 of each PAGE 39 39 DRC. Although they are particularly chosen to ha ve resistance of 50 in IC design librarys pcells, there might be some process variation duri ng fabrication. Besides, th ese two resistors have some coupling relationship with the substrate and this relation is defined in their simulation models. Because all these possibili ties of variation alter the origin ally-designed resistance value and hence spoil the property of th e two resistors as matched terminators, for this sample analysis to work, it is necessary to assume that these two resistors are fabricated with negligible process variation and that their coupling to the substrate is negligible. With these five assumptions stated above, the measurement concept, expressed by Equation 3-1, is easy to understand through a syst em diagram. Figure 3-3 shows the propagation condition of a unity signal, input from port 1, within the proposed dete ction network. For the simplicity of observation, every S-parameter is appended with an additional subscript attribute so as to indicate which sub-circu it it belongs to. By the help of the above five assumptions and Figure 3-3, it can be realized that around the ta rgeted frequency the signals reaching port 2 and port 3 differ only by the response of S11_DUT1. More detailed and insight ful discussions of the design concept and related simulation results are given in Appendix A.1. Figure 3-3. Signal propagation within the embedded S11 detection network. 3.3 Embedded S21 Detection Network The system-level architectur e of the proposed on-chip S21 detection network is shown in Figure 3-4, where port 1 is the input port, and port 2 and port 3 ar e the output ports. In addition PAGE 40 40 to the specification of the system level ports, port definitions inside of each component are also given through the circled numbers The original system can be made even simpler by having only the divider on the left and the DUT2. The addition of the two dividers on the right serv es as the connector when further integration of amplitude and phase detectors is implemented The port 3 of each of the dividers on the right is now left as open in order to observe how well the system deals with unmatched conditions and it will see an in put impedance of about 50 when further connected to a n amplitude or phase detector. Constructed in such a simple structure containing only three divider s and one DUT, the proposed system is able to report the S21 of the DUT (S21_DUT 2) when back end circuits divide the S31 of the system (S31_SYS), i.e. the signal from port 1 to port 3, by the S21 of the system (S21_SYS), i.e. the signal from port 1 to port 2. Figure 3 5 shows the schematic and design values of the DUT2 used in Figure 3 4. Port 1 DIV 1 2 3 Port 2 DUT2 DIV 1 2 3 Port 3 DIV 1 2 3 1 2 Figure 3 4 System level architecture of the proposed on-chip S21 detection network Port 1 L = 786 pH C = 249 fF C Port 2 Figure 3 5. Schematic and design values of the DUT2. PAGE 41 41 By defining S31_SYS over S21_SYS as S21_DUT 2_DERIVED, Equation 3 2 claims that this newly defined term will equal the S21 of the DUT 2 under such system arrangement. 2 21 2 21 21 31 DUT DERIVED DUT SYS SYSS S S S (3 2) Similar to Equation 3 1 in Section 3.2, the accuracy of the equality between S21_DUT2_DERIVED and S21_DUT 2 in Equation 3 2 is based upon some assumptions simpler due to the simpler system structure, as follows 1 Coupling between port 2 and port 3 of DIV is negligible In order not to spoil the signal integrity among the two deliberately -separated branches, the coupling between port 2 and port 3 of DIV shoul d be negligible. That is, S23_DIV and S32_DIV should be negligible. 2 High order reflections are negligible Similar to the reason given in Section 3.2, high order reflections should be assumed to be negligible in order to claim Equation 3 2 valid. With these two assumptions stated a bove, the measurement concep t expressed by Equation 3 2 is easy to understand through a system diagram. Figure 3 6 shows the propagation condition of a unity signal, input from port 1, within the proposed detection network For t he simplicity of observation, every S -parameter is appended with an additional attribute indicating the sub-circuit it belongs to. By the help of the above two assumptions and Figure 3 6 it is easy to realize that the signals reaching port 2 and port 3 di ffer only by the response of S21_DUT 2. More detailed and insightful discussions of the design concept and related simulation results are given in Appendix A.2 PAGE 42 42 Figure 3-6. Signal propagation within the embedded S21 detection network. 3.4 Simulation Results Figure 3-7 shows the simulation results of the proposed embedded S11 detection network. The S11_DUT1 curve is obtained by running a direct simulation on the DUT1 using a CAD tool. The S11_DUT1_DERIVED curve, on the other hand, is acquire d by simulating the whole system in Figure 3-1, and then by a pplying the resultant S21_SYS and S31_SYS to Equation 3-1. As can be seen in Figure 3-7, the actual and calculated S11_DUT1 have an intersection at around 10.25 GHz. This shows that the equality in Equation 3-1 holds around the targeted design frequency, where the five assumptions given in Section 3.2 are satis fied. Upon leaving the design frequency, however, unwanted signal coupling starts showing up and invalidates the equality in Equation 3-1, resulting in deviations between the S11_DUT1 device simulation and the S11_DUT1_DERIVED system simulation. For the purpose of evaluating the fitness betw een a derived S-paramete r and its ideal value with simplicity, Equation 3-3 is often used in th is dissertation whenever it is required to use a scalar value to represent the erro r between two S-parameters, where SA represents the derived value and SB stands for the ideal value. B BAS SS error (3-3) PAGE 43 43 Figure 3 7 Simulation res ult s of the embedded S11 detection network By using Equation 3 3 and b y defining the frequency range where there is less than 3% error between S11_DUT1 and S11_DUT1_DERIVED as the valid measurement bandwidth, it can be found that the proposed embedded S11 detection network has a bandwidth of about 200 MHz which ranges from 10.154 GHz to 10.355 GHz and is marked by the red rectangle in Figure 3 7 Figure 3 8 shows the simulation result s of the proposed embedded S21 detection network The S21_DUT2 curve is obtained by running direct simulation on the DUT2 using a CAD tool The S21_DUT2_DERIVED curve, on the other hand, is acquired by simulating the whole system in Figure 3 4 and then by applying the resultant S21_SYS and S31_SYS to Equation 3 2 As can be s een in Figure 3 8 the actual and calculated S21_DUT 2 have an intersection at around 11.25 GHz. This shows that the equality in Equation 3 2 holds around the targeted design frequency, where the two assumptions given in S ection 3.3 are satisfied. Upon leav ing the design frequency, again unwanted signal coupling start s showing up and invalidate s the equality in Equation 3 2 resulting in deviations between the S21_DUT 2 device simulation and the S2 1_DUT 2_DERIVED system simulation. PAGE 44 44 Figure 3 8 Simulation r esult s of the embedded S21 detection network By using Equation 3 3 and by defining the frequency range where there is less than 3% error between S21_DUT 2 and S21_DUT 2_DERIVED as the bandwidth, it can be found that the proposed embedded S21 detection netwo rk has a bandwidth of about 400 MHz which ranges from 11.017 GHz to 11.417 GHz and is marked by the red rectangle in Figure 3 8 3.5 Experimental Results Constructed by two lumped passive integrated DRC s and one DIV proposed in Chapter 2 the embedded S11 detection network is fabricated in the 0.18m IBM 7RF technology and its die micrograph is shown in Figure 3 9 Including the pads, t he chip size is about 1.6 mm by width and 1.4 mm by length. Figure 3 10 shows the measurement results of the embedded S11 detection network. The curve device sim and the curve system sim represent the two curves S11_DUT1 and S11_DUT1_DERIVED in Figure 3 7, respectively. The curves system meas represents the derived S11_DUT1 from the measurement results. That is, by tak ing the measurement of S21 and S31 of the chip in Figure 3 9 and applying the measured data to Equation 3 1. PAGE 45 45 Figure 3 9 Die micrograph of the embedded S11 detection network From Figure 3 10, it can be seen that for the magnitude part, the curve of derived S11_DUT1 from measurement (i.e. system meas) has a similar trend as the curve of derived S11_DUT1 from simulation (i.e. system sim) that intersects the curve of device sim at around 10.863 GHz where there exists an error of about 22 degrees f or the phase part That is, the intersect ion point is shifted from 10.25 GHz in Figure 3 7 to 10.863 GHz in Figure 3 10 with an error of 22 degrees in phase It is analyzed that the frequency shift and error in phase are potentially caused by the process variation on DUT1 and the detailed analysis and reasoning is given in Appendix B.1 In spite of the frequency shift and the phase error, the design concept is successfully demonstrated and verified. To remove the effect of the possible process variation on the detection network some more comprehensive calib ration methods are proposed in C hapter 4 Figure 3 11 shows the enlarged region marked by the red rectangle in Figure 3 10. As can be seen, for the magnitude part, the curve system meas intersects with the curve device sim at a higher frequency than the curve system sim. By assuming that the fabricated DUT1 has no process variation (i.e. the fabricated DUT1 has the same S11_DUT 1 as that from device simulation), Figure 3 12 shows the error percentage of magnitude and phase between the two curves device PAGE 46 46 sim and system meas for the region marked by the red rectangle in Figure 3 11. When neglecting the phase error part, the 3% error bandwidth from the measurement can be found to be 150 MHz, ranging fr om 10.789 GHz to 10.943 GHz. Figure 3 10. Measurement results of the embedded S11 detection network. Figure 3 13 shows the error difference of magnitude and phase between the two curves device sim and system meas for the region marked by the red rec tangle in Figure 3 11. As can be seen, from 10.789 GHz to 10.943 GHz, the magnitude error ranges from 0.027 to 0.0 27 and the phase error ranges from 22.57 to 21.57 degrees. For the measurement of the S11 detection network, there are a total of 8 chips bei ng measured and all the measurement results are consistent with each other. To show the excellent congruency among the measured data of the 8 chips, the average and variance of the magnitude and phase of the derived S11 at around the targeted frequencies a re given in Table 3 1, where the variance values can be seen to be very small. PAGE 47 47 Figure 3 11. Enlarged picture of Figure 3 10. Figure 3 12. Error percentage of the measurement results of the S11 detection network. Figure 3 13. Error difference of t he measurement results of the S11 detection network. PAGE 48 48 Table 3 1. Average and variance of the S11 detection network measurement results Frequency (GHz) Magnitude of S 11 Phase of S 11 (degree) Mean Variance Mean Variance 10.8 0.958261 0.000187 73.587971 0 .680154 10.85 0.938658 0.000166 74.193411 0.676334 10.9 0.921294 0.000139 74.889299 0.721519 10.95 0.903408 0.000123 75.584564 0.713267 Constructed by the three lumped passive integrated DIV s proposed in Chapter 2 the embedded S21 detection networ k is fabricated in the 0.18m IBM 7RF technology and its die micrograph is shown in Figure 3 14. Including the pads, the chip size is about 1.2 mm by width and 1.2 mm by length. Figure 3 14. Die micrograph of the embedded S21 detection network. Figure 3 15 shows the measurement results of the embedded S21 detection network. The curve device sim and the curve system sim represent the two curves S21_DUT2 and S21_DUT2_DERIVED in Figure 3 8, respectively. The curve system meas represent s the derived S21_DUT2 from the measurement results. That is, by taking the measurements of S21 and S31 of the chip in Figure 3 14 and applying the measured data to Equation 3 2 PAGE 49 49 From Figure 3 15, it can be seen that for the magnitude part, the curve of derived S21_DUT2 from measurement (i.e. system meas ) ha s a similar trend as the curve of derived S21_DUT2 from simulation (i.e. system sim ) that intersect s the curve of device sim at around 11.05 GHz where there exists an error of about 20 degrees for the phase par t That is the intersection point is shifted from 1 1.2 5 GHz in Figure 3 8 to 11.05 GHz with an error of 2 0 degrees in phase. The frequency shift which may come from process variation or some real -world parasitics in the circuit is much less than that of the S11 detection network and thus can be neglected For the phase error part, i t is analyzed that the potential cause is the process variation on both the path from port 1 to port 3 in Figure 3 4 and the inductor inside DUT2. T he detailed analysis and re asoning is given in Appendix B.2 In spite of the error in phase, the design concept is successfully demonstrated and verified. To remove the effect of process variation on the detection network some more elaborate calibration methods are proposed in Chapter 4 Figure 3 15. Measurement results of the embedded S21 detection network. PAGE 50 50 Figure 3 16 shows the enlarged region marked by the red rectangle in Figure 3 15. As can be seen, for the magnitude part, the curve system meas intersects with the curve d evice sim at a lower frequency than the curve system sim. By assuming that the fabricated DUT2 has no process variation (i.e. the device simulation of S21_DUT2 remains the same), Figure 3 17 shows the error percentage of magnitude and phase between the two curves device sim and system meas for the region marked by the red rectangle in Figure 3 16. When neglecting the phase error part caused by the process variation the 3% error bandwidth from the measurement can be found to be 560 MHz ranging from 10.764 GHz to 11.331 GHz Figure 3 18 shows the error difference of magnitude and phase between the two curves device sim and system meas for the region marked by the red rectangle in Figure 3 16. As can be seen, from 10.764 GHz to 11.331 GHz, the magn itude error ranges from 0.03 to 0.03 and the phase error ranges from 20 to 25 degrees. For the measurement of the S2 1 detection network, there are a total of 8 chips being measured and all the measurement results are consistent with each other. To show the excellent congruency among the measured data of the 8 chips, the average and variance of the magnitude and phase of the derived S21 at around the targeted frequencies are given in Table 3 2, where the variance values can be seen to be very small. 3.6 C onclusion Fabricated in the 0.18 m IBM 7RF technology, the three port embedded S11 and S21 detection networks have a targeted operating frequency of about 10 GHz when all the devices within are correctly tuned. The simulation results of the embedded S11 a nd S21 detection networks show the expected responses expressed by Equations 3 1 and 3 2 around the targeted frequency, but inaccuracy occurs away from this frequency. PAGE 51 51 Figure 3 16. Enlarged picture of Figure 3 15. Figure 3 17. Error percentage of the measurement results of the S21 detection network. Figure 3 18. Error difference of the measurement results of the S21 detection network. PAGE 52 52 Table 3 2. Average and variance of the S21 detection network measurement results Frequency (GHz) Magnitude of S 2 1 Phase of S 2 1 (degree) Mean Variance Mean Variance 10.95 0.907098 0.000016 119.539802 0.594578 11 0.905301 0.000013 120.025170 0.628977 11.05 0.913969 0.000015 120.783017 0.655643 11.1 0.909182 0.000016 121.873961 0.674856 11.15 0.909432 0.000014 123.613379 0.736022 Some discrepancy exists between the measurement and the simulation results for the embedded S11 detection network due to some process variation s in DUT1, and the detailed analysis is given in Appendix B.1 However, from the comparis ons between the three curves device sim, system sim, and system meas in Figure 3 10, one can easily tell that the design concept is correct. Although designed for a targeted operating frequency of about 1 0 GHz, the design concept is applicable for ot her ta rget ed frequencies in the future. More insightful discussion of design criteria and precautions are given in Appendix A.1. The measurement results of the embedded S21 detection network are more consistent with the simulation results because of its si mpler system structure. The phase error in Figure 3 16 is mainly caused by process variation that creates additional signal delay between port 1 and port 3 of the chip and the detailed analysis is given in Appendix B.2 Although designed for a targeted op erating frequency of about 10 GHz, the design concept is applicable for other targeted frequencies in the future. More insightful discussion of design criteria and precautions are given in Appendix A.2. From experiment s it is realized that when trying to derive the phase information of the DUT, both detection networks are sensitive to signal path difference between port 1 to port 2 and port 1 to port 3, which should ideally be equal if subtracting the DUT. Therefore, when drawing the layout, it is worth th e designers attention to make sure that the interface paths of the DUT PAGE 53 53 are all taken into account and that necessary compensations are made to keep the two paths equal. The chip area can be further reduced by drawing a more compact layout especially when the measuring frequency goes higher. In addition, the proposed S11 and S21 detection networks can work well with ad -hoc production testing simply by placing a g olden DUT inside the detection networks and sav ing its measured characteristics For situations where broad -band measurements are needed, calibration procedures become essential. In addition, when a discrepancy occurs in measurement result s it is necessary to discern which part, the DUT or the measuring system, causes such error s To address these t wo issues, several calibration methods are proposed and evaluated in Chapter 4 PAGE 54 54 CHAPTER 4 CALIBRATION FOR ONCHIP S -PARAMETER DETECTION NETWORKS 4.1 Overview From Chapter 3 it is known that the proposed S11 and S21 detection networks have a d esirable system response around the targeted frequency when all their constitutive subcircuit s are properly tuned. Away from the targeted operating frequency, deviations begin to take place and the network s may not continue to work unless they are used in a comparison mode with a golden standard for an ad hoc production testing. According to the simulation result s in the preceding chapter with a 3% error bandwidth definition, the bandwidth of the S11 detection network is about 200 MHz and that of the S21 d etection network is about 400 MHz. To extend the working bandwidth, calibration become s necessary and effective Another important issue that calibration can address is to help determine the location of the problematic site in the face of a failure measure ment. That is, w hen the proposed networks are used to measure production chips, if the yield is noticeably lower than expected, then it sure is a good idea to examine whether the measuring network itself is working properly. Calibrations can take care of s uch a task by equivalently removing all the non idealities from the measuring networks With all the non idealities of the detection networks removed, any residual measurement error should be counted as the fault of the tested DUT. In this chapter, three t ypes of calibration methods [18] are proposed to extend the working bandwidth of the S11 detection network From the simplest to the most complicated, each method deals with different combinations of the violations of the five assumptions given in S ection 3.2 and provid es the users with different levels of precision at different costs Due to the simpler system structure o ne type of calibration method is proposed to extend the working bandwidth of the S21 detection network by deal ing with violations of two of the assumptions given in S ection PAGE 55 55 3.3 In addition to verification through the flow graph analysis, t he e ffects of the calibration methods are all reconfirmed through simulation. 4.2 Calibration Methods for Embedded S11 Detection Network It is ment ioned in Chapter 3 that the valid ity of the equality in Equation 3 1 relies on whether the five assumptions given in S ection 3.2 are satisfied Although any unsatisfied assumption among the five can nullify the equality in Equation 3 1 the intensity of influen ce differs from one to another. Therefore, for situations where there is no need to have such a wide bandwidth or high precision, some assumption violations with slight impact can just be neglected and the number of calibration standards can be reduced cor respondingly. Dealing with different combinations of assumption violations and presenting different calibration results, three types of calibration methods that have different calibration standard requirem e nts are introduced as follows to expand the usable bandwidth of the embedded S11 detection network Abstracts of the five assumptions given in S ection 3.2 are repea ted here for convenience. 1 Coupling between port 2 and port 3 of DIV is negligible 2 High order reflections are negligible 3 Signal leakage through pairs of ports having high isolation in the DRC is negligible 4 The intentional open has a reflection coefficient of unity 5 The two 50 4.2.1 Type I Calibration Method Knowing that both the directional coupler and divider are tuned devices and seeing the large discrepancy between the S11_DUT1 and S11_DUT1_DERIVED curves in Figure 3 7 it can be recognized that the assumptions 1 through 3 given in S ection 3.2 are no longer qualified to describe the system behavior for frequencies outside the targeted range. By discarding the assumptions 1 to 3 and keeping the assumption s 4 and 5, the simple RF signal propagation PAGE 56 56 condition demonstrated in Figure 3-3 needs to be modified to the more complex flow graph shown in Figure 4-1. By making the flow graph analysis of the network shown in Figure 4-1, when all the S-parameters of the directional couplers and divi der are taken into account, it is found that the S11_DUT1_DERIVED reported by the network needs to be m odified from Equation 3-1 to Equation 4-1. S11_DIVa1 b1 S21_DIV S21_DIV S12_DIV S31_DRCS11_DRCS22_DIV 1S33_DRC S13_DRC S41_DRCS43_DRC S31_DRCS11_DRC S33_DRC S13_DRC S41_DRCS43_DRC S22_DIVS11_DUT1S32_DIV S12_DIV S23_DIV Port 1 Port 2 Port 3 Figure 4-1. Type I flow graph of the embedded S11 detection network. dSc bSa SDUT DUT DERIVED DUT 1_11 1_11 _1_11 (4-1) The variables a, b c and d are four complex numbers formed by different combinations of the individual components S-parameters with in the network. Through flow-graph analysis, the formation of these four coefficients can be obt ained. The detailed formation of each variable is given in Appendix C.1. Suppose all the S-parameters of each constitutive component within the PAGE 57 57 network are known, the values of the variables a b c and d in Equation 4 1 can be calculated After the values of these four coefficients are at hand, according to Equation 41 the calibration process can be accompl ished by deriving the S11_DUT1 through some simple mathematical operations on S11_DUT1_DERIVED. Figure 4 2 shows the comparisons between the calibrated S11_DUT1 and the real S11_DUT1. After calibration, it can be seen that the original discrepancy between S11_DUT1 and S11_DUT1_DERIVED in Figure 3 7 outside the targeted frequency band is greatly reduced. Figure 4 2 Comparisons between the real S11_DUT1 and the calibrated S11_DUT1 by the Type I calibration method. By applying Equation 3 3 and by using a 3 % -error bandwidth definition, the bandwidth of the embedded S11 detection network is now extended to the range from DC to 12.452 G Hz which is 62.26 times wider than the original bandwidth Figure 4 3 shows the error percentage of the calibrated S11_DUT1 s hown in Figure 4 2 It can be seen that the error percentage has a tendency to increase along with the frequency. Having an overall satisfactory calibration result, the proposed Type I calibration method requires the knowledge of the S -parameters of both t he directional couplers and the divider within the network and deals with violations of the first three PAGE 58 58 assumptions given in S ection 3.2. In S ubsection 4.2.2 t he cause of the residual large error at higher frequencies after calibration will be discussed i n more detail, and the solutions to compensating this problem will be presented Figure 4 3 Error percentage of the Type I calibration result. 4.2.2 Type II Calibration Method Although the discrepancy between S11_DUT1 and Calibrated S11_DUT1 is greatl y reduced for all frequencies in Figure 4 2 a certain amount of error that is not negligible still exists at high frequencies. Since Type I calibration deals with violations of the first three assumptions given in S ection 3.2, the cause of this high-frequ ency error may result f ro m the violation of the assumption 4 or 5 or both. Because circuit simulat ions of the system indicate the assumption 4 of S ection 3.2 as true, this high -frequency error comes from the failure in satisfying the assumption 5. As menti oned in S ection 3.2, in addition to the possibility of having some process variation during fabrication, the PAGE 59 59 two 50 also have some coupling issues with the substrate resistance in their schematic models. The problem herein appears in two aspect s. For one thing, the substrate resistance itself is difficult to precisely define in simulation. This will cause a potential uncertainty in the resistance of the resistors after their being fabricated. In addition when devices with different substrate re sistance are integrated, the effective substrate resistance seen by these two resistors changes from the value that they have when they stand alone. Both of these two aspects will alter the reflection coefficient looking into the se two 50 resistors from port 2 of each D R C, and will spoil the originally matched termination. It is this change of reflection coefficient that creates the error at high frequencies. When the assumption 5 in S ection 3.2 is not satisfied the flow graph in Figure 4 1 needs to be modified to Figure 4 4 which is even more complicated than before By redoing the flow graph analysis, it is found that the S11_DUT1_DERIVED reported by the network is of the same form as Equation 4 1 except there is an addition of r50 the ref lection coefficient looking into the two 50RC in Figure 3 1, to the original a b c d variables. The new formation of a b c d variables is given in Appendix C .2. Because r50 deals with the complicated substrate coupli ng issue, assuming its value given is not practical. However, being added into the a b c d in Equation 4 1 r50 can be factored out as in Equation 4 2 where complex numbers l m n o p q are formed by different combinations of the S11_DUT1 and the S parameters of each constitutive component. The formation of variables l m n o p q is given in A ppendix C.3 q r p r o n r m r l SDERIVED DUT 50 ) 50 ( 50 ) 50 (2 2 1 11 (4 2) PAGE 60 60 S11_DIVa1 b1 S21_DIV S21_DIV S12_DIV S31_DRCS11_DRCS22_DIV 1S33_DRC S13_DRC S41_DRCS23_DRC S31_DRCS11_DRC S33_DRC S13_DRCS41_DRCS33_DIVS11_DUT1S32_DIV S12_DIV S23_DIV Port 1 Port 2 Port 3 S21_DRC r50 S22_DRC S12_DRC S32_DRC S42_DRC S43_DRC S21_DRCS12_DRC r50 S22_DRC S32_DRC S42_DRCS23_DRC S43_DRC Figure 4-4. Type II flow graph of the embedded S11 detection network. By having a golden DUT, whose S11 is known, and by knowing the S-parameters of each constitutive component, r50 can be solved through Equation 4-2. After r50 is solved, it can be applied back to Equation 4-1 to calculate the new values of a, b c and d After the new values of these four coefficients are at hand, according to Equation 4-1, the calibration process can be accomplished by deriving the S11_DUT1 through some simple mathematical operations on S11_DUT1_DERIVED. Figure 4-5 shows the derived r50 through Equation 4-2 when the S11_DUT1 is assumed to be known. It can be seen that the reflec tion coefficient looking into the two 50resistors does not remain close to zero as an ideal matched case. In stead, the magnitude of the reflection coefficient has a tendency to increase along with the frequency, a trend that is consistent with what is observed through Figure 4-2 and Figure 4-3. PAGE 61 61 Figure 4 5 Derived value of r50 by Equation 4 2 By applying the derived r50 in Figure 4 5 to Equation 4 1 the calibrated S11_DUT1 can be derived. Figure 4 6 shows the comparisons between the real S11_DUT1 and the calibrated S11_DUT1 by per forming the Type II calibration. It can be seen that the calibration result is better than that of the Type I calibration and the error at high frequencies is removed Figure 4 6 Comparisons between the real S11_DUT1 and the calibrated S11_DUT1 by Type II calibration method. PAGE 62 62 To show that the derived r50 is not only applicable to calibrating the S11_DUT1_DERIVED, three other different DUT s are created and simulated (not measured) Compared with the corresponding derived values, their ideal S11 values are shown in Fi gure 4 7 Figure 4 7 D erived S11 values and ideal S11 values of DUT3, DUT4, and DUT5 By using the r50 in Figure 4 5 the calibrated S11 of these three DUTs can then be acquired by the Type II calibration metho d in the same manner. Figure 4 8 shows the calibration result, where the calibrated and real S11 values of the three additional DUTs are compared. For each DUT, it can be seen that there is great agreement between the calibrated and real S11 values. For situations where the constitutive components S -parameters are not available, it becomes necessary to find another way to execute the Type II calibration. Since the S11_D UT1_DERIVED reported by the network is of the same form as Equation 4 -1 even when the two 50ideal, a solution should exist if there is a way to derive the S11_DUT1 from the one known, S11_DUT1_DERIVED, and the four unknowns, a b c d according to Equation 4 1 PAGE 63 63 Figure 4 8 Calibration result of DUT3, DUT4, and DUT5 by Type II calibration method. By dividing both the numerat or and denominator of Equation 4 1 by a and by redefining the terms b/a c/a and d/a as A B and C E qua tion 4 1 can be rewritten as Equation 4 3 where besides the S11_DUT1 there are three unknowns, A B, and C The significance expressed by Equation 4 3 is that once the systemic coefficients A B and C are known, the calibration process is accomplished an d the S11 of any DUT can thereafter be correctly measure d C S B A S SDUT DUT DERIVED DUT 1 11 1 11 1 11 (4 3) Based upon the theor y of linear algebra, three linearly independent equations are required to solve three unknowns in a linear system. Therefore, b y having three different golden DUTs, whose S11 values are known as three calibration standards measured by the proposed S11 detection network the values of A B, and C in Equation 4 3 can be acquired. With the derived values of A B, and C at hand, the S11 detection network becomes fully calibrated and can thereafter measure the S11 of any DUT with great precision. Figure 4 9 shows the success of calibrating the network with DUT3 DUT 4 and DUT 5 and hence correctly measuring DUT 1 It PAGE 64 64 can be seen that the result is as good as that shown in Figure 4 6 By applying Equation 3 3 Figure 4 10 shows the error percentage of the calibrated S11_DUT1 shown in Figure 4 9 The peak error percentage is about 0.12%. By adopt ing the 3%-error bandwidth definition, the usable bandwidt h of the S11 detection network is now extended to the whole 15 GHz range which is even wider than the improved bandwidth by Type I calibration method shown in Figure 4 3 Figure 4 9 Comparisons between the real S11_DUT1 and the calibrated S11_DUT1 by Type II calibration method Figure 4 10. Error percentage of the Type II calibration result. PAGE 65 65 4.2.3 Type III Calibration Method Type III calibration method is proposed for situations where S -parameters of constitutive components are not available, or whe re three golden DUTs are considered too costly when integrated as separate ICs Requiring only two golden DUTs as calibration standards, this method provides with an intermediate precision level Referring to the system structure in Figure 3 1, Type III ca libration method assumes that the signal received at port 2 is Equation 4 4 and that at port 3 is Equation 4 5 where O represents the non -ideal open seen by port 3 of the upper D RC, H represents the effective system transfer function, and L represents the constant leakage of the system. All these three systemic parameters are assumed to be unknown. L H O SSYS 21 (4 4) L H S SDUT SYS 1_ 11 31 (4 5) By applying Equations 4 4 and 4 5 into Equation 3 1 and by defining H/(O H+L) and L/( O H+L) as K and Q S11_DUT1_DERIVED can be expressed as Equation 4 6 Now that there are only two unknowns K and Q that need to be derived, two golden DUTs being measured by the system as calibration standards are adequate to fully calibrate the S11 detect ion network Q K S SDUT DERIVED DUT 1 11 1 11 (4 6) Figure 4 11 shows how S11_DUT 1 can be correctly measured after calibrating the system with DUT 3 and DUT 4 using Type III calibration method Except for some slight error around certain frequencies, the calibr ation result is satisfactory in general. By applying Equation 3 3 Figure 4 12 shows the error percentage of the calibrated S11_DUT1 shown in Figure 4 11. The maximal error percentage is about 1.6%. In spite of the larger peak error percentage compared to Type II calibration method in Figure 4 10, the usable bandwidth of the S11 detection network still covers the whole 15 GHz range when adopt ing the 3%-error bandwidth definition PAGE 66 66 Figure 4 11. Comparisons between the real S11_DUT1 and the calibrated S11_D UT1 by Type I II calibration method Figure 4 12. Error percentage of the Type III calibration result. 4.3 Calibration Method for Embedded S21 Detection Network Similar to the embedded S11 detection network the validity of the equality in Equation 3 2 relies on whether the two assumptions given in S ection 3. 3 are satisfied. When frequency is around the designed operating range, all the devices within the system are properly tuned and PAGE 67 67 both the two assumptions are satisfi ed, resulting in the establishmen t of the equality in Equation 3-2. However, upon leaving the designed operating frequency, devices within the system start coupling unwanted signals and br eak the satisfaction of the two assumptions, resulting in the collapse of the equality in Equation 3-2. Abstra cts of the two assumptions given in Section 3.3 are repeated here for convenience. 1. Coupling between port 2 and port 3 of DIV is negligible 2. High-order reflections are negligible Due to its simpler system structure and fewe r assumptions compared to that of the S11 detection network, only one type of calibration method, capable of dealing with violations of both the two assumptions given in Section 3.3, is proposed for the embedded S21 detection network. When the assumption 1 and 2 in Section 3.3 become unsatisfied, the simple RF signal propagation condition given in Figur e 3-6 needs to be modified to the more complicated flow graph shown in Figure 4-13. S23_DIV S32_DIV S23_DIV Figure 4-13. Flow graph of the embedded S21 detection network. PAGE 68 68 By analyzing the flow graph in Figure 4 13, with S -parameters of each component within taken into account, it is found that the S2 1_DUT 2_DERIVED reported by the system is now of the form expressed by Equation 4 7 cS S b S a SDUT DUT DUT DERIVED DUT 2 12 2 21 2 21 2 21 (4 7) The variable s a b and c are three complex numbers The variables a and b are formed by different combinations of the constitutive component s S -parameters within the system. The variable c is formed by combinations of the S11 and S22 of the DUT 2 as wel l as the const itutive component s S -parameters within the system. That is, instead of relying merely on the specification of the S21 detection network like a and b the variable c depends also on the S11 and S22 of the DUT 2 measured by the network an entanglement that adds a bit more complication to the calibration procedure The general formation of c is described in Equation 4 8 where l m n and o are complex numbers that are decided only by the network specification. o S n S m S S l cDUT DUT DUT DUT 2 22 2 11 2 22 2 11 (4 8) Through flow g raph analy sis, the formation of these three coefficients a b and c can be obtained, and the ir detailed formations are given in A ppendix C .4 Suppose all the S -parameters of each constitutive component within the system are known, and assume the S11 and S22 of the DUT 2 are also known, the values of the variables a b and c in Equation 4 -7 can be calculated. For a reciprocal DUT 2 whose S21 equals S12, Equation 4 7 can be simplified as Equation 4 9 By knowing the values of a b and c according to Equatio n 4 9 the calibration process can be accomplished by deriving the S21_DUT 2 through some simple mathematical operations on S21_DUT 2_DERIVED. c S b S a SDUT DUT DERIVED DUT 2 2 21 2 21 2 21) ( (4 9 ) PAGE 69 69 For a non-symmetrical DUT 2 on the other hand, it requires that the S21 detecti on network measure the DUT 2 in two directions in order to correctly derive the S2 1_DUT 2. By measuring the DUT 2 in two directions, Equation 4 7 can be rearranged as Equations 4 10 and 4 11, where Equation 4 10 is from the original m easuring configuration and Equation 4 -11 is by measuring the DUT 2 in reverse orientation As expressed by Equation 4 8 t he coefficients c1 and c2 can be known by knowing all the S -parameters of each constitutive compo nent within the system as well as the S11 and S22 of the DUT 2 W ith the help of Equations 4 10 and 4 -11, the two unknowns, S21_DUT 2 and S12_DUT 2, can be derived through some simple mathematical operations on S21_DUT 2_DERIVED and S12 _DUT 2_DERIVED. 12 12 2 21 2 21 2 21c S S b Sa SDUT DUT DUT DERIVED DUT (4 10) 22 21 2 12 2 12 2 12c S S b S a SDUT DUT DUT DERIVED DUT (4 11) For situations where the constitutive components S -parameters are not available, there should be a substitute way to perform the above calibration Since it is demonstrated that the proposed embedded S21 detection network can also be properly calibrated when measuring a non -symmetrical DUT 2 the following derivation of the substitute calibration method will assume that the DUT 2 is symmetrical for the simplicity of explanation By replacing the c with Equation 4 8 Equation 4 9 can be rewritten as Equation 4 12, where a b l m n o are systemic parameters and are not affect ed by the DUT 2 By dividing both the numerato r and denominator of Equation 4 12 by a and by defining b/a l/a m/a, n/a o/a as A B, C D E Equation 4 12 can be readjusted as Equat ion 4 13, where besides the S21_DUT 2, there are five unknowns, A B, C D E PAGE 70 70 o S n S m S S l S b S a SDUT DUT DUT DUT DUT DUT DERIVED DUT 2 22 2 11 2 22 2 11 2 2 21 2 21 2 21) ( (4 12) E S D S C S S B S AS SDUT DUT DUT DUT DUT DUTDERIVED DUT 2 22 2 11 2 22 2 11 2 2 21 2 21 2 21) ( (4 13) The significance expressed by Equation 4 1 3 is that once the systemic coefficients A B, C D E ar e known, the c alibration of the network can be accomplished and the S21 of any DUT can th ereafter be correctly measured. Based upon the theor y of linear algebra, t o solve five unknowns, there need to be five linearly independent equations. Therefore, by having five diff erent reciprocal golden DUTs, whose values of S11, S22, and S21 are known, as five calibration standards measured by the S2 1 detection network the values of A B, C D and E in Equation 4 1 3 can be acquired Then the S21 detection network becomes fully c alibrated and can thereafter measure the S21 of any symmetrical DUT with great precision. Figure 4 14 shows the success of calibrating the system with five golden DUTs and hence correctly measuring the S21 of the DUT 2 By applying Equation 3 3 Figure 4 1 5 shows the error percentage of the calibrated S21_DUT 2 shown in Figure 4 1 4 The maximal error percentage is about 4 %. By us ing the 3% -error bandwidth definition the bandwidth of the S21 detection network is now extended to about 13.651 GHz, which is 34. 13 times wider than the original bandwidth in Figure 3 8 Unlike the calibration result of the S11 detection network in S ection 4.2 the 3%error bandwidth of the S21 detection network does not cover the whole 15GHz range. This is because solving more var iables demands a larger matrix, and doing the inverse operation on a larger matrix tends to be more sensitive to the noise, caused by the truncation when the circuit PAGE 71 71 simulator outputs its internal data to the external world. To solve this problem and hence broaden the bandwidth, it is practicable to use more golden DUTs to calibrate the system. In this way, the matrix solutions can be more invulnerable to the unwanted numerical noise due to the property of an over -determined system. Figure 4 14. Comparis ons between the real S21_DUT2 and t he calibrat ed S21_DUT2 after calibrating the embedded S21 detection network by five golden DUTs Figure 4 15. Error percentage of the calibration result by five golden DUTs PAGE 72 72 Figure 4 16 shows the simulated success of c alibrating the system with ten golden DUTs, and hence correctly measuring the S21 of DUT2. At higher frequencies, it can be noticed that the blue and red curves match each other better tha n they do in Figure 4 14. By applying Equation 3 3, Figure 4 17 show s the error percentage of the calibrated S21_DUT 2 shown in Figure 4 16. The maximal error percentage is reduced to about 0.8 65% much less than t he 4% in Figure 4 15. By using the 3%-error bandwidth definition, the bandwidth of the S21 detection network is now extended to 15 GHz Figure 4 16. Comparisons between the real S21_DUT2 and the calibrated S21_DUT2 after calibrating the embedded S21 detection network by ten golden DUTs 4.4 Conclusion In order to extend the effective operating bandwidth of the e mbedded S11 detection network proposed in S ection 3.2 and the embedded S21 detection network proposed in S ection 3.3, this chapter presents several kinds of calibration methods through different assumptions and their corresponding flow -graph analysis. In a ddition to the flow graph analysis, the effects of the PAGE 73 73 proposed calibration methods are all reconfirmed through simulation. The calibration results are satisfying due to the much wider operating bandwidth compared to cases without calibration. Figure 4 1 7 Error percentage of the calibration result by ten golden DUTs. For the embedded S11 detection network three types of calibration methods are proposed. The abstracts of each method are summarized in Table 4 1. When no golden DUT is available as calibra tion standard, Type I calibration method can be appli ed if all the S parameters of each constitutive component within the S11 detection network are known or by using the simulation values if the actual values are not available The best situation will all ow a 3% -error bandwidth of about 12.452 GHz. If two golden DUTs are available as calibration standard, Type III calibration method can be applied and will provide with a 3% -error bandwidth of 15 GHz and a peak error percentage of 1.6% as the best achievabl e result. If three golden DUTs are available as calibration standard, Type II calibration method can be applied and will provide with a 3% -error bandwidth of 15 GHz and a peak error percentage of 0.12% in the best condition For the embedded S21 detection network, one type of calibration method is proposed. It is found that with a larger number of unknowns to be solved, the calibration results tend to possess PAGE 74 74 vulnerability to data -retrieving error from the simulator. To mend this problem, adding more golden DUTs as calibration standards proves to be a good solution. Table 4 -2 summarizes the result of the calibration method for the S21 detection network by using different numbers of golden DUTs as the calibration standard. If five golden DUTs are available as calibration standard, the best achievable 3% -error bandwidth is about 13.651 GHz. If ten golden DUTs are available, the best achievable 3% -error bandwidth can cover the whole 15 GHz range. Table 4 1. Three Types of calibration method for the embedded S11 detection network Type I Type II Type III Re quired knowledge S parameters of each constitutive component { S parameters of each constitutive component and one golden DUT} or { Three golden DUTs} Two golden DUTs Precision of calibration result lowes t highest medium Best a chievable BW 12.452 GHz 15 GHz 15 GHz Peak error percentage 4.2% 0.12% 1.6% Table 4 2. The normal and over -determined results of the calibration method for the embedded S21 detection network Normal condition Over determined con dition Required knowledge Five golden DUTs Ten golden DUTs Precision of calibration result lower h igher Best achievable BW 13.651 GHz 15 GHz Peak error percentage 4% 0.865% The schematics of all the golden DUTs used in this chapter are given in Appendix D The sensitivity analysis of all the proposed calibration meth ods are also given in Appendix E PAGE 75 75 CHAPTER 5 AMPLITUDE DETECTOR 5 .1 Overview Being able to report an output DC voltage according to the amplitude of the input AC signal, amplitude detec tors not only enable the observ ation of the internal nodes within RF systems for the purpose of diagnosis but they also play an essential role in a variety of S parameter measurement systems, such as embedded S11 and S21 detection networks pr esented in Ch apter 3 six -port reflectometer s (SPR), and commercia l vector network analyzers (VNA ). With the rapid advance of the semiconductor fabrication technology transistors nowadays can operate at much higher frequencies than in the past. T his trend increases th e usable bandwidth of amplitude detectors, composed of one or more transistors, and furthers their importance by gradually realizing the vision of direct measurement of high -frequency microwave and millimeter -wave signals without the need of conventional down conversions. To prepare for the construction of the six -port reflectometer introduce d in C hapter 6 this chapter presents an easily adjust able amplitude detector that is suitable for a variety of measuring configurations one of which is fabricated as a stand alone piece of work. The amplitude detectors are designed and fabricated in the 0.13 m IBM BiCMOS 8HP technology that provides T. Referring to the design in [ 4 ], which is suitable for the use of the SPR structure [ 4 ], the pr esent ed amplitude detector [19 ] replaces the diode with a diode -connected NPN bipolar transistor which become s the only active component in the circuit. The simulation result s show that the presented amplitude detector can operate up to 8 0 GHz Due to the limitation s of test equipment, t he measurement results verify that it can operate up to 67 GHz. PAGE 76 7 6 5 .2 Main Cir cuit Structure a nd Detection Theory Figure 5 1 shows the main circuit structure of the developed amplitude detector The amplitude detector is capable of performing differential signal detection in essence by connecting the port 1 and port 2 to two differe nt signal source s as shown in Figure 5 2. In addition, it also can be readily modifie d for using in single ended signal detection by simply connecting the port 2 to ground as shown in Figure 5 3 VBIAS Vout CF=2pF Cin Cin=114fF RB RB=10k RF=60k Port 1 Port 2 Figure 5 1. The main structur e of the proposed amplitude detector. VBIAS Vin1 Vin2 Vout CF=2pF Cin Cin=114fF RB RB=10k RF=60k Figure 5 2. Using the detector as a differential amplitude detector PAGE 77 77 VBIAS Vin1 Vout CF=2pF Cin Cin=114fF RB RB=10k RF=60k Figure 5 3. Using the detector as a single -ended amplitude detector. Generally, the RF signals propagating in S -parameter measurement systems are restricted to sinusoidal signals only. Therefore, the following analysis of the detectors detection theory is given based on sinusoidal signals only. In Figure 5 1, there are two signal paths ins ide the circuit. One is the RF path, which is formed by the diode -connected bipolar and the two capacitors, Cin. The other is the DC path, which is formed by the two resistors RB, one resistor RF, and the diode -connected bipolar. The two capacitors Cin are used to couple the RF signal into the detector. The two resistors RB and the resistor RF are used to properly bias the transistor, and the two resistors RB also have the function of achieving sufficient isolation between RF lines and bias lines. The outpu t stage, formed by the resistor RF and capacitor CF, serves as a low -pass filter and thus enables the detector to output a DC voltage. 5.2.1 Single -ended Detection Theory When there is no input RF signal in Figure 5 3, the two capacitors Cin act like an op en and there is only DC current within the circuit. T he DC current can be described as Equation 5 1 where VDQ is the DC voltage across the diode -connected transistor IS is the saturation current, and VT is the thermal voltage When a n RF signal is couple d through the capacitor Cin into the PAGE 78 78 detector in Figure 5 3, it will create a n AC voltage signal on the transistor s collector node If Cin is sufficiently large, the input RF signal will be almost completely coupled to the transistors collector node Bec ause the capacitor Cin on the other side of the transistor will draw the transistors emitter node to an AC ground by acting as an AC short, the AC voltage across the diode -connected transistor then would be the RF signal itself. By assuming that the new D C voltage across the transistor is now V DQ and by modify ing the analysis result from [ 9 ], the current flowing through the transistor can be expressed as Equation 5 2 where Vac is the peak amplitude of AC input signal, Veff is Vac/VT, and In( Veff) is the modified Bessel function of order n [ 20]. F B DQ BIAS V V S DC D DR R V V e I I IT DQ 2 ) 1( | (5 1) } 1 ] cos ) ( 2 cos ) ( 2 ) ( [ { ) 1 () 1 (2 1 0 ) cos( ) cos( t V I t V I V I e I e e I eI Ieff eff eff V V S V t VV V S V t V V S DT DQ T ac T DQ T ac DQ (5 2) According to the analysis in [ 9 ], for large values of Veff, I0( Veff) has the asymptoti c behavior as in Equation 5 3 and for smaller values of Vef f, I0( Veff) has the square law behavior as in Equation 5 4 Both Equation 5 3 and Equation 5 4 indicate that I0( Veff) increases as Vac increases. eff V effV e V Ieff2 ) (0 (5 3 ) 4 1 ) (2 0 eff effV V I (5 4 ) Since I0( Veff) is a function of Ve ff and is independent of the frequency, t he significan t fact expressed by Equation 5 2 is that the DC current of the transistor is not only determined by the PAGE 79 79 DC voltage across it, but it is also influenced by the peak amplitude of the input AC signal. F rom Equation 5 2 the DC current of the transistor can be rewritten as Equation 5 5 Because the new DC voltage acro ss the transistor and the new DC current flowing through it also need to satisfy the DC loop formed by the two resistors RB, the resistor RF, a nd the diode -connected transistor, Equation 5 5 can be modified into Equation 5 6 By comparing Equation 5 -1 with Equation 5 6 it can be deduced that V DQ must be smaller than VDQ due to the additional term I0( Veff), which is larger than unity. Besides, t he larger the peak amplitude of the input AC signal is, the smaller V DQ will be. Due to this decrease of the DC voltage across the transistor and the increase of the DC current in the DC path the DC voltage on the collector node of the bipolar will decre ase and that on the emitter node will increase. The ratio between the amount of DC voltage drop and increase on the collector and emitter node of the transistor is described by Equation 5 7, where v1 and v2 represent the absolute value change of the DC vol tage on the collector and emitter node and need to satisfy Equation 5 8 ] 1 ) ( [ |0 eff V V S DC DV I e I IT DQ (5 5) F BDQ BIAS eff V V S DC DR RV V V I e I IT DQ 2 ] 1 ) ([ |0 (5 6) B F BR R R v v 1 2 (5 7) DQ DQV V v v 2 1 (5 8) As implied by Equation 5 7, to hav e a decent output voltage range means that RF should be several times larger than RB. After the input RF signal causes a DC voltage increase on the emitter node of the bipolar transistor, the low -pass filter, formed by RF and CF, will further PAGE 80 80 stabilize the signal and provide with a nearly DC voltage Vout at the output port By assuming that the DC voltage increase on the emitter node is v2, the corresponding DC voltage increase on the output port can be easily de fined by Equation 5 9 Consistent with Equati on 5 7, Equation 5 9 also implies that having a decent output voltage range require s that RF be several times larger than RB. F B F outR R R v v 2 (5 9) According to Equation 5 1, if the saturation current, the thermal voltage, the DC bias volta ge, and the resistors RB and RF are decided, the value of VDQ can be determined through the equality. The resultant VDQ can be expressed as Equation 5 10, where lambertw represents the Lamberts W function [ 21][22 ]. Similarly, according to Equation 5 6, th e value of V DQ can be determined through the equality after all the other design parameters are decided and the resultant V DQ can be expressed as Equation 5 11. By letting Equation 5 10 subtract Equation 5 11, the value of Equation 5 8 can be derived as shown in Equation 5 12. By substituting Equation 5 12 into Equation 5 8 and by using Equation 5 7 and Equation 5 9 the DC voltage increase on the output port corresponding to a certain input RF signal can be specifically quantified in a closed form by Equ ation 5 13. BIAS F B S V V R R I T F B S T DQV R R I e V R R I lambertw V VT BIAS F B S ) 2 ( ) 2 () 2 ( (5 10) BIAS F B S V V R R I T F B eff S T DQV R R I e V R R V I I lambertw V VT BIAS F B S ) 2 ( ) 2 ) ( ( ') 2 ( 0 (5 11) PAGE 81 81 )] 2 ( ) 2 ) ( ( [ ') 2 ( ) 2 ( 0T BIAS F B S T BIAS F B SV V R R I T F B S V V R R I T F B eff S T DQ DQe V R R I lambertw e V R R V I I lambertw V V V (5 12) )] 2( ) 2 ) ( ( [ 2) 2 ( ) 2 ( 0T BIAS F B S T BIAS F B SV V R R I T F B S VV R R I T F B eff S T F B F oute V R R I lambertw e V R R V I I lambertw VR R R v (5 13) The definition of the Lamberts W function can be explained through Equation 5 1 4 and Equation 5 1 5 If two v ariables, w and x have the relation in Equation 5 1 4 then w can be solved and expressed as the Lamberts W function of x in Equation 5 1 5 Based on the Lagrange inversion theorem [23], the equivalent series expansion of the Lamberts W function is also g iven in Equation 5 1 5 Figure 5 4 shows the values of the Lamberts W function when x is a real number ranging from 0 to 10. x e ww (5 14) n n nx n n x lambertw w 1 1! ) ( ) ( (5 15) Figure 5 4. The Lamberts W function when x ranges from 0 to 10. PAGE 82 82 5.2.2 Differential Detection Theory For the differential amplitude detection configuration in Figure 5 2, one RF signal Vin1 is coupled through the capacitor Cin to the transistors collector node and the other RF signal Vin 2 is coupled throu gh the capacitor Cin to the transistors emitter node. By a ssuming that the Vin1 and Vin 2 are the same in frequency but different in amplitude and phase as is shown in Equation 5 1 6 and Equation 5 1 7 the ir difference will have the form in Equation 5 1 8 w here Vdiff is still a sinusoidal signal with the same frequency except th e newly formed amplitude C which the differential amplitude detector in Figure 5 2 is able to sense. ) cos(1 i int A V (5 16) ) cos(2 j int B V (5 17) ) ) cos( 2 cos cos ( cos ) cos( ) cos( ) cos( 22 2 1 2 2 2 1 j i j i j i in in diffAB B A B A where t C t AB B A V V V (5 1 8 ) If Cin is sufficiently large, the input RF signal, Vin1, will be almost completely coupled to the transistors collector node which will force the AC voltage on the transistors collector node to be Vin1. Similarly, the input RF signal, Vin 2, will be almost completely coupled to the transistors emitter node and hence force the AC voltage on the transistor s emitter node to be Vin 2. In this way the total AC voltage across the transistor will be exactly the difference between Vin1 and Vin 2. By replacing the AC voltage across the transistor with Vdiff in Equation 5 1 8 Equation 5 2 can be modified as Equation 5 1 9 and the new DC current can be found to be the same as Equation 5 6 except the definition of Veff is changed to C/VT. Therefore, an increase o n PAGE 83 83 amplitude C will result in a corresponding increase on the output voltage Vout at the output port as the single -ended detection case. T eff eff eff eff V V S V t C V V S V t C V S DV C V where t V I t V I V I e I e e I e I IT DQ T T DQ T DQ } 1 ] ) cos( ) ( 2 ) cos( ) ( 2 ) ( [ { ) 1 ( ) 1 (2 1 0 ) cos( ) cos( (5 19) 5.3 Simulation Results 5.3.1 Single -ended Amplitude Detector W ith the measuring configuration of Figure 5 3, Figure 5 5 shows the S11 looking into the input port of the single -ended detector w hen VBIAS varies from 0 volt to 1 volt. As will be required by the SPR in C hapter 6 the S11 of the input port of the single -e nded detector needs to be close to unity in order to reduce the disturbance added to the SPR core. This requirement as can be seen in Figure 5 5 is satisfied for the proposed single -ended detector. The S11 values, very insensitive to the variation of VBI AS, are all very close to unity. Figure 5 5 The values of S11 looking into the input port of the single ended detector with respect to different VBIAS values. A) Magnitude, B) Phase. Figure 5 6 shows the relation between the input AC magnitude and t he output DC magnitude at different frequencies for the measuring configuration in Figure 53, where the RF and the VBIAS is set to 740 mv As A B PAGE 84 84 can be seen in Figure 5 6 although there is a little decrease on the output voltage range when the measuring frequency increases, the detector can work decently up to 80 GHz. Figure 5 6 Input -output relation of the single ended amplitude detector 5.3.2 Differential Amplitude Detector With the mea suring configuration of Figure 52, Figure 5 7 shows the S11 looking into the two input ports of the differential detector when VBIAS equals 705mv with r1 varying fr As will be required by the SPR in Chapter 6 the S11 looking into each input port of the differential detector also needs to be close to unity. This requiremen t as can be seen in Figure 5 7 is satisfied for the proposed differential detector. The S11 values, very insensitive to how the other input port is connected to ground, are all very close to unity. Figure 5 8 shows the relation between the input AC magni tude and the output DC magnitude at different frequencies for the measuring configuration in Figure 52, where each RF signal source is assumed to have an output resistance of 50 BIAS is set to 740 mv. T he two RF signal sources are simulated to generate signals with 180 phase difference. As can be PAGE 85 85 seen, although there is a little decrease on the output voltage range when the measuring frequency increases, the detector can work decently up to 80 GHz. When compared to Figure 5 6 it can be noted that the output magnitude is doubled with the same input magnitude, a phenomenon that reconfirm s the differential detection mechanism Figu re 5 7 The values of S11 looking into the two input ports of the differential detector with respect to different values of r1. A) Magnitude of port 1, B) Phase of port 1, C) Magnitude of port 2, D) Phase of port 2 A B C D PAGE 86 86 Figure 5 8 Input -output relation of the differential amplitud e detector. 5.3.3 Matched Single -Ended Amplitude Detector For the construction of the SPR targeted at 20 GHz and 40 GHz in Chapter 6 there also needs to be o ne single -ended amplitude detector with matched input ports By simply adding one 50resistor RM in between the port 1 and port 2 in Figure 5 1, the single -ended amplitude detector can be modified into one that has a matched input stage and the resultant schematic is shown in Figure 5 9 VBIAS Vout CF=2pF Cin Cin=114fF RB RB=10k RF=60k Port 1 Port 2 RM=50 Figure 5 9 Matched single -ended amplitude detector. PAGE 87 87 Figure 5 10 shows the S11 looking into the two input ports of the detector with different values of VBIAS. As can be seen, t he matched input port requirement is satisfied with the matched detector schematic in Figure 5 9 The S11 value s looking into port 1 and port 2 differentially, when VBIAS varies from 0 volt to 1.25 volt, are all below 30 dB from DC to 60 GHz. Figure 5 11 shows the relation between the input AC magnitude and the output DC magnitude at different frequencies for the schematic in Figure 5 9 where the port 1 is connected to a RF signal source the port 2 is connected to the ground, and the VBIAS is set to 740 mv. As can be seen, although there is a little decrease on the output voltage range when the measuring frequency increases, the detector can work decent ly up to 80 GHz. When compared to Figure 5 6 it can be noted that the output magnitude is only a half with the same input magnitude This is mainly due to the voltage division on the 50 signal generator and the newly added re sistor RM in Figure 5 9 Figure 5 10. The magnitude of S11 looking into the two input ports of the matched single -ended amplitude detector with respect to different values of VBIAS. PAGE 88 88 Figure 5 11. Input -output relation of the matched single -ended ampli tude detector. 5.4 Experimental Results Among all the different measuring configurations presented in S ection 5.3, o nly the matched single -ended detector in S ubsection 5 .3.3 is fabricated as a stand alone piece of work. The other s are fabricated as parts o f the SPR systems pr esente d in Chapter 6 Figure 5 1 2 shows the die micrograph of the standalone matched single -ended amplitude detector. Excluding the pads, the chip area of the detector is about 100 m by width and 90 m by length. Figure 5 1 2 The d ie micrograph of the standalone matched single ended amplitude detector. PAGE 89 89 Figure 5 1 3 shows the measurement results of the matched single -ended detector in Figure 5 9 at the frequency of 21 GHz when the VBIAS is set to 0.78 volt. By doing the parasitic an alysis and feeding the derived parasitic values to the simulator, Figure 5 1 3 also shows the comparison between the measurement results and the simulation results. As can be seen, the two curves are well matched. The biggest value of the input signal ampli tude that the detector can tolerate is found to be about 3.55 volt. Above this value, the simulator reports warnings of base -emitter breakdown and the measurement results cannot match the simulation results very well. Figure 5 1 3 Measurement results o f the matched single -ended amplitude detector at 21 GHz. By doing the parasitic analysis and feeding the derived parasitic values to the simulator, the comparisons between the measurement and simulation results of the matched single -ended detector in Figur e 5 9 at the frequencies of 40 GHz, 50GHz, 60GHz, and 67 GHz are also shown in Figure 5 1 4 Figure 5 1 5 Figure 5 1 6 and Figure 5 1 7 respectively. By comparing from Figure 5 13 to Figure 517, it can be noted that the range of the input AC magnitude is r educing as the measuring frequency goes higher. This tendency is because of PAGE 90 90 the limitations in the RF signal generator. Besides, when given the same input AC magnitude, the output DC magnitude at a higher measuring frequency can be noted to be smaller due to the more severe loss on the input signal transmission path. These seemingly frequency -dependent detector responses can be removed by subtracting the loss on the input signal transmission path, including the loss in the cable and the RF probe, from the m easurement data. After taking away the signal loss effect existing in Figure 5 13 to Figure 5 17, the subtraction results, compared with their corresponding simulation results, are shown in Figure 5 18 to Figure 5 22. By superimposing the calibrated measur ement results from Figure 5 18 to Figure 5 22, Figure 5 23 shows that the measure d data of the amplitude detector at different frequencies become mutually consistent and reconfirms the simulation results in S ection 5.3 that the amplitude detector itself is not to first order frequency dependent when the signal generator possesses a 50 Figure 5 1 4 Measurement results of the matched single -ended amplitude detector at 40 GHz. PAGE 91 91 Figure 5 1 5 Measurement results of the matched single -ended amplitude detector at 5 0 GHz. Figure 5 1 6 Measurement results of the matched single -ended amplitude detector at 60 GHz. PAGE 92 92 Figure 5 1 7 Measurement results of the matched single -ended amplitude detector at 67 GHz. Figure 5 18. Calibrated measu rement results of the amplitude detector at 21 GHz PAGE 93 93 Figure 5 19. Calibrated measurement results of the amplitude detector at 40 GHz Figure 5 20. Calibrated measurement results of the amplitude detector at 50 GHz PAGE 94 94 Figure 5 21. Calibrated measureme nt results of the amplitude detector at 60 GHz Figure 5 22. Calibrated measurement results of the amplitude detector at 67 GHz PAGE 95 95 Figure 5 23. S uperimposition of calibrated measurement results at different frequencies 5.5 Conclusion An easil y adjusta ble amplitude detector, designed and fabricated in the 0.13m IBM BiCMOS 8HP technology is pr esent ed in this chapter. The core of the developed amplitude detector is just a diode -connected NPN bipolar transistor. Due to its simple circuitry structure and variable measuring configurations, the design ed detector proves to be a good candidate for the embedded amplitude detectors inside of the SPR system s pr esented in Chapter 6 T he simulation results show that the detector can work up to 80 GHz Due to the l imitation s of test equipment, the measurement results verify that the detector can work up to 67 GHz By doing the parasitic analysis and feeding the derived parasitic values to the simulator, it is found that the measurement and the simulation results are agreeable to each other. PAGE 96 96 CHAPTER 6 SIX-PORT REFLECTOMETER 6.1 Overview Six-port reflectometer (SPR) [3][4] is a passi ve linear device which measures the complex reflection coefficients of a device under test (DUT) by usi ng four voltage readings followed by a sequence of mathematical analyses and operations on the measured data. As the structure of an SPR is usually much simpler than that of a traditional VNA, and because having a set of sound calibration procedures makes an SPR more i nvulnerable to process variation, it is a good candidate for the on-chip implementation of microwave/millimeter-wave embedded S-parameter measurement. 6.2 Theory of Six-Port Reflectometer Normally, an SPR has a system structure as encompassed by the dotted lines in Figure 6-1, where the left-hand port is connected to an RF signal source, the right-hand port is connected to the DUT, and the other four ports are connected to four embedded amplitude detectors. The core is a network that manipulates RF signal flows ac cording to the design spec ifications, and the four detectors are placed in proper places to sense th e RF signal amplitudes at specific locations and phase delays. Figure 6-1. Block diagram of a six-port reflectometer. PAGE 97 97 By defining the normalized propagation waves that is into and out of the DUT as b2 and a2 in Figure 6 1, the theory of SPR [14][24 ] assumes that Equations 6 1 to 6 4 are satisfied, where P3, P4, P5, and P6 are power levels measured by the four amplitude detectors DET1, DET2, DET3, and DET4, and the complex numbers A~H are the systemic design specification s of the SPR. 2 2 2 3Bb Aa P (6 1) 2 2 2 4Db Ca P (6 2) 2 2 2 5Fb Ea P (6 3) 2 2 2 6Hb GaP (6 4) It is s hown in li terature that one solution to Equations 6 1~ 6 4 can be expressed as Equations 6 5 and 6 6, where Ci, Sii ar e real and functions of A~H [25][26]. 6 3 2 2 i i iP b (6 5) 6 3 6 3) (i ii i i i iP P jS C (6 6) A more insightful way to understand how a n SPR works can be described as follows. For the simplicity of explanation and adopted by many modern designs of SPR, the systemic design parameter A in Equation 6 1 is assumed zero, an assumption representing that the power level s ensed by DET3 has no relation with the reflected wave from the DUT. This way, Equation 6 1 can be modified as Equation 6 7 In order to explicitly display the measurand of interest, Equations 6 2~6 4 can be rearranged as Equations 6 8~ 6 10, where q4, q5, and q6 are newly defined thr ough C~H. PAGE 98 98 2 2 2 2 2 3b B Bb P (6 7) 2 4 2 2 2 2 2 2 2 4q b C C D b C P (6 8) 2 5 2 2 2 2 2 2 2 5q b E E F b E P (6 9) 2 6 2 2 2 2 2 2 2 6q b G G H b G P (6 10) By letting Equations 6 8~6 10 divided by Equation (6 7), the term |b2|2 within Equations 6 8~6 10 can be e liminated and Equations 6 11~ 6 13 can be obtained. 3 4 2 2 4P P C B q (6 11) 3 5 2 2 5P P E B q (6 12) 3 6 2 2 6P P G B q (6 13) By further inspecting Equations 6 11~ 6 13, it can be seen that each equation stands for a circle, whose center is at the qi point (i.e. q4, q5, and q6) and locus determined by different values of plane. Besides, by taking Equation 6 11 for example, the radius of the circle is also determined by |B/C|2 from the systemic design parameters as well as P4/P3 from the measurement results by DET3 and DET4. With a set of well -designed systemic p arameters A~H, thus three well -positioned qi he three circles specified by Equations 6 11~613. The derivation concep t is e xpressed graphically in Figure 6 2, where a passive DUT is assumed. Acco rding to the conclusion from [3][ 14], the PAGE 99 99 optimal settings for the q points are to let |q4|=|q5|=|q6|, and to make the arguments differ by Besides, the magnitude is best to be set in between 0.5 and 1.5. Figure 6-2. Determination of from the intersection of three circles. 6.3 Calibration Procedure After an SPR is fabricated, it needs to be cal ibrated first before it can be used for any measurement. Although many calibration methods [14] have been proposed, the six-port-to-fourport reduction technique proposed by Engen [27] wins more favor than the others. Accompanied by three other calibration procedures, Figure 6-3 shows the complete set of calibration procedures for an SPR. Figure 6-3. Complete set of calibration procedures for SPR. The detector characterization [28][29][30][31], also called detector linearization, is for inferring the power values observed at the detectors input ports from their output DC voltages. PAGE 100 100 Since the primary outputs of a n SP R are the four DC voltage readings reported by the four embedded amplitude detectors, and because the theory of SPRs operates on power levels, this output -voltage -to -input -power transformation step is essential and allows the proceeding of the following ca libration procedures as well as the measurement. Not surprisingly, this step of power characterization can be seen as the most important one among the four calibration procedures because any error occurring at this stage will cause a misleading interpretat ion of the power values, and is likely to be continually propagated to the last step and ultimately be reflected as a measurement failure with an originally well -designed system. Therefore, the quality of the characterization of the embedded amplitude dete ctors inside a n SPR system is directly affecting the quality of the SPR measurement result and needs to be monitored with care. More details and new techniques of detector characterization will be presented in Chapter 7 Although Engens sixport -to -four -p ort reduction technique provides with an optimization equation that often permits to improve the accuracy of measurements made with the SPR significantly, the equation is of the third order and hence is likely to find a wrong answer if a set of good initia l estimates are not given. Due to this reason, there needs to be an initial estimation procedure [ 27][32][33][34] before the six -port -to -four -port reduction technique. In addition, because Engens six -port to -four port reduction technique is operated on th e W -plane instead of -plane, a final step is required to transform the data from the W -plane back to the -plane. 6.4 System Design of Six Port Reflectometer Various system structures of SPR have been proposed in literature. Among th em, the o ne proposed by [ 4] has the most compact on-chip implementation and thus the least area overhead. Therefore, it is used for the research of SPR in this dissertation. Constructed mainly by one power divider, one phase shifter, and four amplitude detectors, t he system design of the on-chip PAGE 101 101 SPR is shown Figure 6 4. The system uses the power divider to equally split the input RF signal into two branches, where one is co nnected to DET3 and satisfies Equation 6 7 and the other is connected to the phase shifter, which, together with DET4~DET6, are designed to satisfy Equations 6 8~ 6 10 according to the system specification s Phase Shifter DUT DET3 DET4 DET5 DET6 Power Divider Pin < Port 1 > < Port 3 > < Port 2 > + + + Figure 6 4. System design of the on-chip SPR. By assuming that the power divider and the phase shifter are perfe ctly matched and the input impedance of the amplitude detectors is infinite, the systemic parameters A~H in Equations 6 1 ~6 4 can be rewritten in Equations 6 14~ 6 17 as functions of the phase shift caused by t he phase shifter. By applying Equations 6 15~617 to Equations 6 8~ 6 10, the qi points can be found to be Equations 6 18~6 20. je B A 0 (6 14) 1 1 j je D e C (6 15) j je F e E (6 16) 1 1 H G (6 17) je q 4 (6 18) 2 5 je q (6 19) PAGE 102 102 16 q (6 20) From Equations 6 18~ 6 20, it can be found that the magnitude of the qi points is one and their phases are 2 180 and 180 respectively. Therefore, the optimum value for is 60 so that the arguments of the three qi points can differ by 120. 6.4.1 SPR Targeted at 20 GHz Figure 6 5(A) shows the schematic of the resistive power divider. Similar to a Wheatstone bridge, the resistive divider has the advantage of a wider bandwidth at the cost of larger attenuation of 6 dB. It can be shown that if 2 0Z R Rc a is satisfied, the S -p arameter matrix of the divider with respect to Z0 can be expressed as Equation 6 21. By having 500Z R Rc a all ports are matched and port 2 and 3 are isolated from each other. The phase shifter can be implemented by a simple low -pass circuit c onsisting of two series inductors and one capacitor shunted to the ground. Figure 6 5(B) shows the schematic of the phase shifter. The ampl itude detectors proposed in Chapter 5 can be readily used in the SPR. Among the four detectors, DET4 is differential detector and DET3, DET5, and DET6 are single -ended detectors. In addition, all the detectors need to have high input impedance in order to reduce the disturbance to the RF signal flows in the SPR core except DET3, where a matched input stage is required. A < Port 1 > + < Port 2 > + < Port 3 > + Ra Z0 Rc B L L C Figure 6 5. A) Schematic of the resistive power divider, B) Schematic of the phase shifter. PAGE 103 103 0 0 1 1 0 0 1 11 1 1 1 00 0 0 0Z R Z R Z R Z R Sc a c a (6 21) 6.4.2 SPR Targeted at 40 GHz According to the experiment results o f the SPR targeted at 20 GHz, the signal sensed by DET6 in Figure 6 4 is much weaker than those by the other detectors due to the signal loss through the substrate and wire lines. Hence, it can be reasonably projected that the SPR will be hardly able to work at 40 GHz if its design remains unchanged. To conquer the severe loss issue at higher frequencies, three main modifications are made. First, the resistive power divider in Figure 6 5( A ) is replaced by a lossless micro -strip divider. By this modification, the signal sensed by DET6 can be increased by about 3 dB. The layout of the divider is shown in Figure 6 6. The size of the lossless divider is about 400 m by width and 460 m by length. Compared to the size of the resistive divider 40 m by width and 50 m by length, in the 20-GHz SPR, this abrupt area increase is a price that must be paid in order to accurately measure S -parameters at such high frequencies. T he lumped divider presented in C hapter 2 is not a good candidate either, because it still poss esses a 4 dB loss. Besides, the design values of its constitutive lumped devices keep on decreasing when the frequencies go higher, a trend that prohibits the divider manufacture and makes the divider more and more vulnerable to other parasitics should it b e manufactured PAGE 104 104 The second modification is to substitute the phase shifter in Figure 6 5(B) with a transmission -line phase shifter. The size of the transmissionline phase shifter is about 580 m by width and 20 m by length. This change is necessary becau se the design values of the lumped devices in the phase shifter in Figure 6 5(B) also decrease when the frequencies go high. At 40 GHz, the design values of the lumped devices become so small that it is not possible to fabricate Besides, other parasitics can easily kill the performan ce of the phase shifter were it to be fabricated. Figure 6 6. Layout of the lossless power divider. The third circuit modification is on the amplitude detectors. As discussed in C hapter 5, the output range of an amplitude de tector can be increased by increasing the ratio of RF t o RB. That is in addition to intensify ing the signal that is to be sensed by DET6, the other way of improving the sensitivity of the SPR system is to increase the output range of the detectors. Hence, the design value of RF in C hapter 5 is changed to 120k 6.5 Simulation Results Two versions of SPR systems are designed and fabricated in the 0.13m IBM BiCMOS 8HP technology that supports high quality bipolar transistors. The first version is to operate at 20 GHz and the secon d is to operate at 40 GHz. Their simulation results are as follows. PAGE 105 105 6.5.1 SPR Targeted at 20 GHz Figure 6 7 shows the S -parameter simulation results of the resistive power divider shown in Figure 6 5(A) As expected, an equal power splitting is achieved wi th an attenuation of 6dB for each output port Figure 6 8 shows the S -parameter simulation results of the phase shift er in Figure 6 5(B) As is discussed in S ection 6 .4, for the optimal system configuration, the phase shift is designe d to be about 60 around the targeted frequency. Figure 6 7 S -parameter simulation results of the resistive divider. A) magnitude, B) phase. Figure 6 8 S -parameter simulation results of the lumped phase shifter. A) magnitud e, B) phase. By defining the port connected to the RF signal source as port 1 and the port connected to the DUT as port 2, Figure 6 9 shows the simulated S21 of the SPR targeted at 20 GHz As can be seen, after the pads and amplitude detectors are integrat ed, the magnitude of the S21 of the whole SPR chip becomes 0.47 and the phase becomes 75 degree s A B A B PAGE 106 106 Figure 6 9 Simulated S21 of the 20 GHz SPR. A) magnitude, B) phase. 6.5.2 SPR Targeted at 40 GHz Figure 6 10 shows the S -parameter simulation results of the lossless micro -strip divider shown in Figure 6 6 As expected, an equal power splitting is achieved for each output port. Instead of being exactly 3 dB, the attenuation can be seen to be about 3.62 dB at 40 GHz, which indicates that the new divide r still suffers some slight loss. However, the loss problem is greatly alleviat ed compared to the 6.02 dB shown in Figure 6 7. Figure 6 11 shows the S -parameter simulation results of the transmission line pha se shifter. As is discussed in S ection 6.4, for the optimal SPR system configuration, the phase shift is designed to be about 60 around the targeted frequency. Figure 6 10. S -parameter simulation results of the micro -strip divider. A) magnitude, B) phase A B A B PAGE 107 107 Figure 6 11. S -parameter simulation results of the transmission line phase shifter. A) magnitude B) phase By defining the port connected to the RF signal source as port 1 and the port connected to the DUT as port 2, Figure 6 12 shows the simula ted S21 of the SPR targeted at 40 GHz As can be seen, after the pads and amplitude detectors are integrated, the magnitude of the S21 of the whole SPR chip becomes 0. 59 and the phase becomes 183 degrees Figure 6 12. Simulated S21 of the 40 GHz SPR A) magnitude, B) phase. 6.6 Experimental Results 6.6.1 SPR Targeted at 20 GHz Fabricated in the 0.13 m IBM BiCMOS 8HP technology, Figure 6 13 shows the die micrograph of the SPR targeted at 20 GHz The whole chip size is 1.25 mm by width and 1 mm by le ngth. This large chip area mainly results from the limitation of the number of pads and other A B A B PAGE 108 108 test pieces. Excluding all the pads and other auxiliary test circuitr y, the chip area of the SPR is about 0.104 m m2. Figure 6 14 shows the measured S21 of the 20GHz SPR in Figure 6 13 from 100 MHz to 30 GHz. Compared to Figure 6 9 the measured S21 at 20 GHz ha s some deviation from its simulation estimate However, as mentioned in S ection 1.5, because a n SPR has a set of firm calibration algorithms, it is more inv ulnerable to the drift of system performance due to process variation and parasitics A s long as the embedded detectors inside the SPR can work properly, it is still possible to derive the non -ideal system parameters through a sequence of calibration proce dures and hence correctly measure the reflection coefficients of the DUTs. Figure 6 13. Die micrograph of the 20GHz SPR. To verify the functionality of this 20 GHz SPR, the calibration procedures presented in S ection 6.3 are performed in turn and a mea surement set up is constructed as in Figure 6 15. The SPR chip is fixed on a probe station. The two RF probes and one DC probe are used as the interface of the tested chip and the external testing equipment. Four piece s of external testing equipment are ne eded, where t he signal generator feeds sinusoidal RF signals into the SPR t he programmable tuner create s DUTs with differen t reflection coeffi cients, t he power supply biases the embedded amplitude detectors, and t he voltage meter reads the output of the a mplitude detectors. The lateral and vertical views of the probe station set up are shown in Figure 6 16. PAGE 109 109 Figure 6 1 4 Measured S21 of the 20 GHz SPR. SPR chip Signal Generator Programmable Tuner RF Probe RF Probe DC Probe 5 Voltage Meter 4 Power Supply Figure 6 15. Test set up for the 20 GHz SPR. For the test at 20 GHz, t he programmable tuner is used to generate 11 DUTs that help verify the functionality of the SPR. Among all the generated loads load 1 to load 5 are first used to perform the calibration procedures given in S ection 6.3, and then the SPR functionality can be examined through comparing the reflection coefficients measured by the SPR to those by the VNA for the total 11 loads Figure 6 17 shows the output of the embedded amplitude detectors when the SPR is connected to the first 5 loads and the RF signal amplitu de sweeps from 0 volt to 1.04 volt with a n 8 0mv interval. PAGE 110 110 Figure 6 16. Lateral and vertical views of the probe station set up. Figure 6 17. Output of the embedded detectors for the first 5 loads at 20 GHz PAGE 111 111 After calibrating the SPR with the first 5 loads, the magnitude of the RF signal generated by the signal source is set at 640 mv when the SPR measures the load 6 to load 11. T he value of the DC output voltage of each embedded amplitude detector is shown in Figure 6 18. Figure 6 18. Output of the embedded detectors for load 6 to load 11 at 20 GHz By adopting the calibration algorithms suggested by [ 27], [29], [30], and [ 33], the voltage measurement results in Figure 6 17 and Figure 6 18 can be transformed into reflection coefficient measurement r esults. The specification s and measurement results of the 11 loads generated by the programmable tuner for the frequency of 20 GHz are listed in Table 6 1, where t he Tuner Position is the position command given to the tuner in order to create such load, the Reflection Coefficient (VNA) is the reflection coefficient of the load that is measured by the commercial VNA, and the Reflection Coefficient (SPR) is the reflection coefficient of the load that is measured by the 20GHz SPR chip. As can be seen, the two counterparts match each other very well, proving the performance of the SPR of measuring the reflection coefficients at 20 GHz. The comparison is also presented graphically through Figure 6 19, where the circles and stars can be seen to be in great proximity to each other. PAGE 112 112 Table 6 1. Specification s of loads and measurement results of the 20 GHz SPR at 20 GHz Load N umber Tuner Position Reflection Coefficient (VNA) Reflection Coefficient (SPR) Pos1 Pos2 Magnitude Phase (deg) Magnitude Phase (deg) 1 835 2685 0.51261 4.1517 0.51282 4.5807 2 35 2440 0.50261 86.339 0.49840 84.0508 3 2000 2550 0.49638 112.89 0.49881 112.207 2 4 685 2505 0.50046 46.359 0.50203 48.2765 5 1800 2620 0.50004 130.64 0.50083 132.1678 6 735 2545 0.50814 39.25 0 0.49939 41.8899 7 585 2465 0.50423 55.094 0.54478 58.8780 8 280 2054 0.35310 73.247 0.37031 69.0118 9 35 2685 0.73969 71.850 0.74150 69.2505 10 2000 2685 0.70062 100.52 0.66060 100.6245 11 180 2600 0.64998 73.700 0.66181 72.3899 Figure 6 19. Comparison of the measured by the VNA and SPR at 20 GHz 6.6.2 SPR Targeted at 40 GHz Fabricated in the 0.13 m IBM BiCMOS 8HP technology, Figure 6 20 shows the die micrograph of the SPR targeted at 40 GHz. The whole chip size is 1. 5 mm by width and 1 mm by length. This large chip area mainly results from the limitation of the number of pads and other test pieces. Excluding all the pads and other auxiliary test circuitry, the chip area of the SPR is about 0.244 mm2. PAGE 113 113 Figure 6 20. Die micrograph of the 40GHz SPR. Figure 6 21 show s the measured S21 of the 40GHz SPR in Figure 6 20 from 30 GHz to 67 GHz Compared to Figure 6 12, the measured S21 at 4 0 GHz have some deviation from its simulation estimate. However, because a n SPR has a set of firm calibration algorithms, it is still p ossible to derive the deviated system parameters and hence correctly measure the reflection coefficients of the DUTs a s long as the embedded detectors inside the SPR can work properly Figure 6 21. Measured S21 of the 40 GHz SPR. To verify the functiona lity of the SPR targeted at 40 GHz the same calibration procedures and test set up as those described in S ubsection 6.6.1 are applied. The 40 GHz SPR are measured PAGE 114 114 at the frequencies of 30 GHz, 40 GHz, and 50 GHz in turn in order to demonstrate its capabil ity of measuring over a wide range. The measurement results of each frequency are described as follows. 6.6.2 .1 Measurement Results at 3 0 GHz For the test at 30 GHz, the programmable tuner is used to generate 15 DUTs that help verify the functionality of t he SPR Among all the generated loads, load 1 to load 6 are first used to perform the calibration procedures given in S ection 6.3, and then the SPR functionality can be examined through comparing the reflection coefficients measured by the SPR to those by the VNA for the total 1 5 loads. Figure 6 22 shows the output of the embedded amplitude detectors when the SPR is connected to the first 6 loads and the RF signal amplitude sweeps from 0 volt to 1.04 volt with an 80mv interval. After calibrating the SPR with the first 6 loads, the magnitude of the RF signal generated by the signal source is set at 640 mv when the SPR measures the load 7 to load 15. The values of the DC output voltage of each embedded amplitude detector is shown in Figure 6 23. By adopting th e calibr ation algorithms suggested by [ 27], [29], [ 30], and [ 33], the voltage measurement results in Figure 6 22 and Figure 6 23 can be transformed into reflection coefficient measurement results. The specifications and measurement results of the 15 loads generated by the programmable tuner for the frequency of 30 GHz are listed in Table 62. The meaning of each column is the same as that in Table 6 1. As can be seen, the two counterparts, Reflection Coefficient (VNA) and Reflection Coefficient (SPR), m atch each other very well, proving the performance of the 40GHz SPR when measuring the reflection coefficients at 30 GHz. The comparison is also PAGE 115 115 presented graphically through Figure 6 24, where the circles and stars can be seen to be in great proximity to each other. Figure 6 22. Output of the embedded detectors for the first 6 loads at 30 GHz Figure 6 23. Output of the embedded detectors for load 7 to load 15 at 30 GHz PAGE 116 116 Table 6 2. Specifications of loads and measurement results of the 40 GHz SPR at 30 GHz Load Number Tuner Position Reflection Coefficient (VNA) Reflection Coefficient (SPR) Pos1 Pos2 Magnitude Phase (deg) Magnitude Phase (deg) 1 1080 2685 0.62931 6.0758 0.6426 3 8.0136 2 735 2685 0.63186 80.681 0.62571 79.5559 3 585 2685 0.6289 5 109.73 0.62146 108.2874 4 321 2685 0.59118 157.48 0.60870 160.6068 5 180 2685 0.61578 168.01 0.6074 169.5503 6 35 2685 0.61087 133.15 0.60574 133.9897 7 900 2685 0.63705 46.747 0.63267 44.5856 8 450 2685 0.60465 132.53 0.58883 134.2334 9 735 25 45 0.48859 96.581 0.48520 95.3777 10 586 2124 0.1453 120.99 0.13969 116.7309 11 280 2054 0.065044 148.71 0.05652 141.6378 12 160 1892 0.047606 107.72 0.04691 94.4547 13 198 2388 0.24639 146.93 0.23791 146.6249 14 450 2489 0.40343 153.89 0.39131 153. 1244 15 463 2373 0.28876 152.02 0.27779 151.0140 Figure 6 24. Comparison of PAGE 117 117 6.6.2. 2 Measurement Results at 4 0 GHz For the test at 40 GHz, the programmable tuner is used to generate 15 DUTs that help verify the functionality of the SPR. Among a ll the generated loads, load 1 to load 6 ar e first used to perform the detector characterization given in Figure 6 3 and then load 1, 2, 5, 6, 7, 8 are used to execute the remaining three calibration procedures in Figure 6 3. After this, the SPR functionality can be examined through comparing the reflection coefficients measured by the SPR to those by the VNA for the total 15 loads. Figure 62 5 shows the output of the embedded amplitude detectors when the SPR is connected to the first 6 loads and the RF signal amplitude sweeps from 0 volt to 1.04 volt with an 80mv interval. After characterizing the embedded amplitude detectors with the first 6 loads, the magnitude of the RF signal generated by the signal source is set at 640 mv when the SPR measures the load 7 to load 15. The value of the DC output voltage of each embedded amplitude detector is shown in Figure 6 26. By adopting the calibration algorithms suggested by [ 27], [29], [ 30], and [ 33], the voltage measurement results in Figure 6 25 and Figure 6 26 can be transformed into reflection coefficie nt measurement results. The specifications and measurement results of the 15 loads generated by the programmable tuner for the frequency of 40 GHz are listed in Table 63. The meaning of each column is the same as that in Table 6 1. As can be seen, the two counterparts, Reflection Coefficient (VNA) and Reflection Coefficient (SPR), match each other very well, proving the performance of the 40GHz SPR when measuring the reflection coefficients at 40 GHz. The comparison is also presented graphically throu gh Figure 6 27, where the circles and stars can be seen to be in great proximity to each other. PAGE 118 118 Figure 6 25. Output of the embedded detectors for the first 6 loads at 40 GHz. Figure 6 26. Output of the embedded detectors for load 7 to load 15 at 40 GHz PAGE 119 119 Table 6 3. Specifications of loads and measurement results of the 40 GHz SPR at 4 0 GHz Load Number Tuner Position Reflection Coefficient (VNA) Reflection Coefficient (SPR) Pos1 Pos2 Magnitude Phase (deg) Magnitude Phase (deg) 1 1080 2545 0.4902 4 82.007 0.49432 82.6885 2 900 2660 0.50872 45.745 0.50435 45.9217 3 735 2680 0.43519 8.2613 0.43123 9.4687 4 585 2680 0.44539 85.209 0.45191 84.4815 5 450 2640 0.50856 153.18 0.50173 153.3233 6 321 2555 0.49102 163.75 0.49667 163.4261 7 180 25 35 0.51024 133.47 0.51931 133.7449 8 35 2535 0.50994 106.95 0.5167 108.0575 9 735 2545 0.30154 22.989 0.30214 24.7276 10 585 2545 0.31684 104.64 0.31786 103.8112 11 268 1931 0.17069 122.5 0.1732 123.5477 12 650 2208 0.030413 173.25 0.031581 17 3.1591 13 1080 2680 0.59329 88.694 0.59681 89.619 14 180 2680 0.61981 139.66 0.63782 141.0983 15 321 2680 0.59445 174.14 0.60136 172.5347 Figure 6 27. Comparison of the me 0 GHz. 6.6.2.3 Measurement Results at 50 GHz For the test at 50 GHz, the programmable tuner is used to generate 15 DUTs that help verify the functionality of the SPR. Among all the generated loads, load 1 to load 6 are first used PAGE 120 120 to perform the detector characterization given in Figure 6 3, an d then, together with load 8, are used to execute the remaining three calibration procedures in Figure 6 3. After this, the SPR functionality can be examined through comparing the reflection coefficients measured by the SPR to those by the VNA for the tota l 15 loads. Figure 628 shows the output of the embedded amplitude detectors when the SPR is connected to the first 6 loads and the RF signal amplitude sweeps from 0 volt to 1.04 volt with an 80mv interval. After characterizing the embedded amplitude detectors with the first 6 loads, the magnitude of the RF signal generated by the signal source is set at 640 mv when the SPR measures t he load 7 to load 15. The value of the DC output voltage of each embedded amplitude detector is shown in Figure 6 29. Figur e 6 28. Output of the embedded detectors for the first 6 loads at 50 GHz. PAGE 121 121 Figure 6 29. Output of the embedded detectors for load 7 to load 15 at 50 GHz. By adopting the calibr ation algorithms suggested by [ 27], [29], [ 30], and [ 33], the voltage measure ment results in Figure 6 28 and Figure 6 29 can be transformed into reflection coefficient measurement results. The specifications and measurement results of the 15 loads generated by the programmable tuner for the frequency of 50 GHz are listed in Table 64. The meaning of each column is the same as that in Table 6 1. As can be seen, the two counterparts, Reflection Coefficient (VNA) and Reflection Coefficient (SPR), match each other very well, proving the performance of the SPR of measuring the reflec tion coefficients at 50 GHz. The comparison is also presented graphically through Figure 6 30, where the circles and stars can be seen to be in great proximity to each other. According to the measurement data given in Table 6 1 to Table 6 4, the maximum ab solute difference between the reflection coefficients measured by the commercial VNA and those measured by the two SPR chips can be calculated. For each test condition, Table 6 5 gives a PAGE 122 122 summary of the maximum absolute difference between the measured refle ction coefficients and the load number where the maximum difference takes place. Table 6 4. Specifications of loads and measurement results of the 40 GHz SPR at 50 GHz Load Number Tuner Position Reflection Coefficient (VNA) Reflection Coefficient (SPR) Pos1 Pos2 Magnitude Phase (deg) Magnitude Phase (deg) 1 1080 2685 0.39518 104.88 0.40276 101.0865 2 900 2560 0.40243 39.485 0.39191 38.3536 3 735 2480 0.40692 7.7267 0.42849 7.2733 4 585 2490 0.40871 51.732 0.39536 54.5365 5 450 2570 0.40582 102.7 5 0.41038 101.4599 6 321 2685 0.40378 164.87 0.40322 164.5889 7 180 2685 0.37728 124.54 0.40346 128.4482 8 35 2625 0.40817 65.05 0.4022 70.4129 9 1080 2545 0.29872 100.81 0.31286 107.4347 10 900 2660 0.47132 40.938 0.45083 45.3927 11 735 2680 0.55726 4.608 0.5288 3.6457 12 585 2680 0.58003 51.136 0.55183 52.9761 13 450 2640 0.47545 104.64 0.468 106.264 14 321 2555 0.29876 164.59 0.29572 167.2956 15 180 2535 0.27165 120.25 0.29973 124.7056 Figure 6 the VNA and SPR at 50 GHz PAGE 123 123 Table 6 5. The maximum measurement error for each test condition Test Case Max error Load SPR VNA | 20 GHz SPR working at 20 GHz Load 7 0.05 40 GHz SPR working at 30 GHz Load 4 0.04 40 GHz SPR working at 40 GHz Load 14 0.02 40 GHz SPR working at 50 GHz Load 10 0.04 6.7 Conclusion In this chapter, the theory and calibration procedures of SPR s are introduced. Two SPR systems, designed and fabricated in the 0.13 m IBM BiCMOS 8HP technology, are presented. The two SPR systems are both of modern design structure and their targeted frequency are at 20 GHz and 40 GHz respectively The measurement results show that the 20 GHz SPR functions well at 20 GHz To show that a n SPR is invulnerable to process variation and can work over a wide band, the SPR targeted at 40 GHz is measured at 30 GHz, 40 GHz, and 50 GHz. The measurement results show that the 40 GHz SPR can work well at all these frequencies. In addition, in view of the significant role that the detector c haracteriza tion step in Figure 6 3 plays in the measuring of a n SPR, more details and improvements of it are discussed in Chapter 7 PAGE 124 124 CHAPTER 7 OPTIMIZATION FOR DETECTOR CHARACTERIZATION IN SIX -PORT REFLECTOMETER 7.1 Overview The first step among the four -step cal ibration procedure s of a n SPR is to transfer the output voltage values reported by the embedded amplitude detectors into the incident power values observed at the ir input ports. This kind of transformation, from the voltage domain to the power domain, char acterizes the detectors and enables the following SPR calibration and operations because the theory of a n SPR is to operate on known power levels. Not surprisingly, this step of characterization (some papers call this linearization) can be seen as the most important one among the four calibration steps because any erroneous mapping between the output voltage values and the incident power levels of the embedded detectors will be directly reflect ed as a misleading measurement failure of an originally well -des igned test system Therefore, the quality of the characterization for the embedded amplitude detectors inside a n SPR system directly affects the quality of the SPR measurement result and needs to be optimized. Figure 7 1 shows a typical detector characteri zation flow of an SPR. The first step is to connect the SPR to a load and change the intensity of the input RF signal connected to the SPR. In the meantime, the outputs of the four embedded amplitude detectors within the SPR should be recorded. T he detecto rs responses against different input RF signal intensities are logged when the SPR is connected to a first load Then, the SPR is connected to a different load and the same voltage recording procedure is performed for the second load. This procedure conti nues so that all the prepared loads are measured by the SPR and all the detectors outputs are stored. By performing linear regression technique on all the saved responses of the four detectors, the model coefficients of each detector can be derived. PAGE 125 125 After each detectors characterization model is obtained, the characterization flow enters into its verification stage, wher e the quality of each detectors model should be determined. To do this, those previously recorded outputs from the detector s are used, with the help of the derived characterization models, to calculate the incident power at the input port of each embedded amplitude detector. The conventional method is to utili ze one special property of an SPR that when it is connected to a specific load, the ratios of the incident power at the input ports of two detectors should remain constant while th e input RF signal intensity varies. Therefore, for an SPR system with four embedded amplitude detectors as is shown in Figure 6-1, the conventional method [30][31] is to ve rify that the three power ratios, P4/P3, P5/P3, and P6/P3 in Equations 6-11 to 6-13, are unchanging when the input signal source Pin changes its intensity. This indicates a good power cal ibration for the SPR system. Figure 7-1. Typical detector ch aracterization flow of SPR. Although used for decades, the conventional method mentioned above was discovered by this research to be insufficient and leads to inaccuracy in measurement. In this chapter, a counterexample that shows characterization error will first be introduced. This is followed by PAGE 126 126 some detailed discussion and proof demonstrating that the original checking criteria are inadequate and that a more comprehensive method presented here surpasses the original one In addition, possibly due to using the wrong criteria to verify there is no mention in literature about how to determine the optimal characterization model set, including the optimal model type, the optimal model order, and the optimal intrinsic para meter s within a model when executing the in -situ detector characterization process Instead, engineers tend to rely merely on their empirical choices and try to manage accuracy by using some pass a ble model combinations. By learning that the newly presente d method is more robust fundamentally and by exploi ting this discovery, two figures -of -merit, CV total and Total error, are developed to quantify the suitability of a set of model combinations for given SPR test condition s The CV total is used as a golden indicator that helps validate the functionality of Total error, which is applicable for real measurement s Because the choice of the optimal detector characterization model combination for a particular test condition depends cooperatively on many differen t factors, including the structure of SPR, the type of embedded amplitude detectors, the loads used as calibration standard s and the input RF signal intensities used to stimulate the system it is unlikely that an engineer can know his optimal model set w ithout consum ing too much time on detailed matters, such as what kind of model is best for his detector type or what are the impacts of several influencing factors discussed above The two new figures -of -m erit presented in this chapter grant engineers the ability to find the optimal solution according to their test conditions without the penalty of striving to know the detailed minutia. By simply applying the calculation algorithm of Total error developed in this PAGE 127 127 chapter the best detector characterization model set for a given test co ndition can be easily derived and recognized from a group of potential candidates 7.2 Characterization Models There are several characterization models in the literature for amplitude detectors. Among them, two models f rom [30] and [31 ] are suitable for the in -situ detector characterization of SPR systems and thus receive the most attention of SPR designers. 7.2.1 Bergeault Model For a detector connect ed at port i of a n SPR, t he Bergeault model equations [30] transferring the d etector s output voltage to its incident power are shown in Equations 7 1 7 2 and 7 3 where Pi is the incident power, Ki is a proportion constant between the real and measured power and needs not to be known, b1 to bn are coefficients to be derived, n i s the order of the model, V is the detectors output voltage, Vo is the detectors output voltage when there is no incident power, and q is a scale factor whose best value is around the region recommended in [35]. 6 5 4 3 ,) ( i v K Pvi fi i i i (7 1) n nv b v b v f 11 ) ( (7 2) ) (oV V q v (7 3) Because the operation algorithm of SPR s works only on power ratios the Ki in Equation 7 1 is kept as an unknown in practice and the calculated incident power for the use of SPR instea d of being Pi i n Equation 7 1 is usually replaced by Pi,meas as described in Equation 7 4 6 5 4 3 ,) ( i v K P Pvi fi i i i meas i (7 4) PAGE 128 128 7.2.2 Demers Model Demers [31] proposed the idea of applying the detector model by Zhaowu [36] to the in situ detector character ization in SPR systems For a detector connected at port k of a n SPR, the model equations are shown in Equations 7 5 7 6, and 7 7 where Pk is the incident power, Ck is a proportion constant between the real and measured power and needs not to be known, Vk is the detectors output voltage ak1 to akN are coefficients to be derived, N is the order of the model, and q is a scale f actor such that xk has a maximum value of about 0.5. kS k k kV C P 10 (7 5) i k N i ki kx a S 1 (7 6) ) 1 ln( q V xk k (7 7) kS k k k meas kV C P P 10, (7 8) Similar to the Bergeault M odel, the Ck in Equation 7 5 is left as unknown in practice, and the calculated incident power for the use of SPR, instead of being Pk in Equation 7 5 is usually replaced by Pk,meas as described in Equation 7 8 7.3 Encountered Problems In experi ment s of this research some problems are encounter ed when performing the detector characterization process. An example can be found by applying Demers Model to t he SPR structure proposed by [ 4]. The SPR under test is equipped with four diode -connected BJT amplitude detectors designed in 0.13 m IBM 8HP technology. The transfer function of the embedded detectors is also shown in Figure 7 2 The test condition is desi gned to use eight loads, whose reflection coefficients are shown in Table 7 1 as calibration standards, and to have thir teen sinusoidal signal amplitude s ranging PAGE 129 129 uniformly from 0.2 volt to 1.4 volt, as the input stimulus When the order of the applied De mers Model is set to 10, Figure 7 3 shows that the three power ratios ( P4 ,meas/ P3 ,meas P5,meas/ P3,meas and P6,meas/ P3,meas), traditionally used to examine the quality of characterization are very level with varying input signal amplitudes The maximums an d minimums of power ratios for each load are also listed in Table 7 2. Figure 7 2 Transfer function of diode connected BJT amplitude detectors Figure 7 3 Measured power ratios are level as input signal changes its amplitude PAGE 130 130 Table 7 1. Reflection coefficients of the eight loads serving as calibration standards Load 1 Load 2 Load 3 Load 4 Load 5 Load 6 Load 7 Load 8 Magnitude 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.75 Phase (degree) 0 45 90 135 180 135 90 45 Table 7 2. Maximums and minimums o f power ratios with varying input voltages for each load Load 1 Load 2 Load 3 Load 4 Load 5 Load 6 Load 7 Load 8 P 4/ P 3 MAX 1.11999 1.01863 1.06041 1.13889 1.17484 1.19052 1.18704 1.16523 min 1.11519 1.01217 1.05433 1.13481 1.17265 1.18782 1.18368 1.16 307 P 5/ P 3 MAX 1.11999 1.16523 1.18704 1.19052 1.17484 1.13889 1.06041 1.01863 min 1.11519 1.16307 1.18368 1.18782 1.17265 1.13481 1.05433 1.01217 P 6/ P 3 MAX 1.22098 1.21184 1.18268 1.1214 1.01487 1.1214 1.18268 1.21184 min 1.21868 1.20961 1.17983 1.11 725 1.00381 1.11725 1.17983 1.20961 A ccording to the criteria given in [ 30][31], these level power ratios with varying input signal intensities represent that the derived model (a set of coefficients) is good for serving the power translation function. H owever, if we focus our attention on a certain input level, say 1.4 volt, and divide the real power ratios by the measured ones for each load, different multiples can be found for different loads as shown in Table 7 3 For example, the ratios between the r eal and measured P4/ P3 is as small as 0.1118 for Load 2 but as large as 2.5295 for Load 6. This incongruence violates the assumption that the re is a constant proportion between the measured and the real power as is regulated in Equations 7 4 and 7 8 and wi ll cause errors on the subsequent SPR operations Table 7 3 Different multiples between the real and measured power ratios Load 1 Load 2 Load 3 Load 4 Load 5 Load 6 Load 7 real( P 4 / P 3 )/meas( P 4 / P 3 ) 0.7282 0.1118 0.2494 1.0331 1.9686 2.5295 2.4175 real( P 5 / P 3 )/meas( P 5 / P 3 ) 0.7282 1.6768 2.4175 2.5295 1.9686 1.0331 0.2494 real( P 6 / P 3 )/meas( P 6 / P 3 ) 2.5112 2.1670 1.3228 0.4483 0.0618 0.4483 1.3228 Load 8 real( P 4 / P 3 )/meas( P 4 / P 3 ) 1.6768 real( P 5 / P 3 )/meas( P 5 / P 3 ) 0.1118 real( P 6 / P 3 )/me as( P 6 / P 3 ) 2.1670 PAGE 131 131 7.3.1 The Determination of Model Type From the description of the encountered problems above, it should be realized that checking the quality of detector characterization by the criteria given in existing literature is not only ins ufficient but may also lead to some potentially ill -conditioned model s and hence damage the SPR measurement result afterwards Intuitively, for a certain type of SPR system there exists a type of model that best characterizes the amplitude detectors with in the system. This suitability can be affected by the structure of the SPR, the type of the amplitude detectors, the calibration loads, and even the stimulus power range. Therefore, when doing the experiment s it becomes an important issue to be able to d ecide the best characterization model among several different candidates in real time This issue can be addressed by the pr esented optimization algorithm described in S ection 7.5. 7.3.2 The Determination of Model Order After the best characterization model is chosen, the next question goes to the order of the model. With the order set too low, the model will tend to predict power graphs more like straight lines and may not be able to e mulate the real power curves properly However, there will also be impre cision due to too much damping if the order of the characterization model is set too high. Therefore, deciding the proper order for the chosen model becomes another important issue and may directly influence the precision of the subsequent SPR measurement. This issue can also be dealt with by the proposed optimization algorithm introduc ed in S ection 7.5. 7.3. 3 The Determination of Intrinsic Parameter As can be seen in Equations 7 3 and 7 7 f or both the Bergeault Model and the Demers Model there is an addi tional parameter q that needs to be determined. Although some suggested estimate s are given in [ 31] and [35], the actual best value still varies with different cases. Therefore, how to find the optimal value for q becomes the third essential question. For tunately, PAGE 132 132 the optimization algorithm pr esented in S ection 7.5 can also provide with an answer to this question 7.4 Two Types of Linearity To better comprehend the developed optimization algorithm in S ection 7.5, it is better to understand the linearity is sue s encountered in SPR detector characterization first. Two types of linearity can be defined when doing an embedded amplitude detector characterization for a n SPR system. The conventional way of checking the flatness of the power ratios with varying input signal levels as demonstrated in Figure 7 3 is defined by this dissertation as the measured power -from -port to -port (MPPP) linearity W hereas the real -to -measured -single -port -power (RMSP P ) linearity whose importance is the first time emphasized by thi s dissertation in history, is defined according to the very basic assumption that the proportion between the measured and the real incident power for each embedded detector should remain constant at all time s B y this research work it is discovered that t he conventional MPPP linearity criteria are not only insufficient in recognizing the optimal solution, but it sometimes may even lead to illconditioned characterization traps. To show that RMSP P linearity has a more stringent constraint which can be expl oited to find the optimal model set, t he definition s of the MPPP and RMSP P linearity and their relation ship are discussed in more detail in the following subsections 7. 4 .1 MPPP Linearity MPPP linearity is widely used as the checkpoint to verify the qualit y of the detector characterization in existing SPR papers. Figure 7 4 is a n SPR diagram with the specification of the input sinusoidal power source and the embedded detectors DET3 and DET4 where DET3 represents the reference detector within a n SPR The cr iteria that MPPP linearity requests are to have the power ratios as flat as possible with varying input power levels. Take Figure 7 5 for example if the measured power by DET3 is P3,meas and P 3,meas when the input power is Pin 1 and PAGE 133 133 Pin2, and that by DET4 is P4,meas and P4,meas correspondingly, MPPP linearity requires that the relation given in Equation 7-9 hold. Figure 7-4. An SPR diagram with input power source and embedded detectors. Figure 7-5. The requirement of MPPP linearity. meas meas meas measP P P P,3 ,4 ,3 ,4' (7-9) 7.4.2 RMSPP Linearity RMSPP linearity comes from the very basic as sumption of the detect or characterization and requires that the proportion fact or between the real and the meas ured power be constant at all times, as is stated by Equations 7-4 and 7-8. That is, even with varying input power levels or different measured loads, the proportion factor should remain constant for each characterized detector within an SPR system. Although not us ed in existing literature as the checkpoint, RMSPP linearity possesses great importance in that it is possible for a model to pass the MPPP linearity requirement but violate the RMSPP linear ity requirement as is shown in the example PAGE 134 134 given in Table 7 3 This violation, unfortunately, can cause detrimental imprecision on the S parameter measurement using a n SPR afterwards 7.4.3 Relation ship between MPPP Linearity and RMSP P Linearity It can be proved that RMSP P linearity is the sufficient condition for MPPP linearity but not vice versa. This means that RMSP P linearity is a stronger condition than MPPP linearity and rationalizes the example shown in Table 7 3, where the requirement of MPPP linearity is satisfied but th at of RMSP P linearity is not. Accor ding to Figure 7 4 and Figure 7 5 the proportion factors between the measured and the real power for DET4 and DET3 when Pin equals Pin1 and Pin2 can be defined as t4 t4 t3 and t3. By defining the real incident power at DET4 when Pin equals Pin1 and Pi n2 as P4 and P 4, and by defining the real incident power at DET3 when Pin equals Pin1 and Pin2 as P3 and P 3, the four defined proportion factors will have the relations shown in Equations 7 10, 711, 7 12, and 7 13. 4 44 P P tmeas (7 10) 4 4' 4 P P tmeas (7 11) 3 33 P P tmeas (7 12) 3 3' 3 P P tmeas (7 13) If MPPP linearity is satisfied, Equation 7 14 needs to be true. Since Equation 7 15 is true for any SPR, the relation in Equation 7 16 can be derived. 3 4 3 4 3 4 3 4' 3 4 3 4 P t P t P P P t P t P Pmeas meas meas meas (7 14) PAGE 135 135 3 4 3 4' P P P P (7 15) 3 4 3 4 t t t t (7 16) The significance expressed by Equation 7 16 is that t3 can be unequal to t3 and t4 can be unequal to t4 as long as thei r ratios are the same Obvious ly, this loose constraint does not satisfy the requirement of RMSP P linearity where the proportion factor between the real and the measured power should be constant at any time Contrarily, by assuming that t3 equals t3 and t4 equals t4 as is requested by RMSP P linearity definition it is easy to see that the flatness in Figure 7 5 required by MPPP linearity, can be guaranteed according to Equations 7 14 and 7 15. From the above analyses it can be concluded that the require ment of RMSP P linearity encompasses that of MPPP linearity. Hence, using RMSP P linearity as the criteria in characterizing detectors is more promising in directing to the optimal solution. 7.4.4 Potential Problem of MPPP Linearity In spite of the proof given in S ubsection 7.4.3, it is still easy to have the misconception that failing to meet RMSP P linearity requirement is trivial since SPRs operate only according to power ratios. However, such an idea is fals e and Figure 7 6 explains the reason. Figure 7 6 shows the characterized relations between the real incident power P3 and P4 at DET3 and DET4 and their corresponding measured values P3,meas and P4,meas by using the load r1 Instead of being straight lines, the characterized relations can be seen to be se gmented, which is a serious problem to any SPR. However, if r1 causes only the characterized power region across region I and II, as specified in Figure 7 6 the power ratio P4,meas/ P3,meas within such region can be constant with varying input power level s and the potential problem can be PAGE 136 136 overlooked. This can be proved by defining the ratio between P3 and P4 as k1 with the load r1 With this definition, the measured power ratio P4,meas/P3,meas at different input power levels {P(4,1);P(3,1)} and {P(4,2);P(3,2)} can be described as in Equations 7-17 and 7-18. Figure 7-6. Illustration of the pot ential problem of MPPP linearity. )1,3( )1,4( )1,3()1,4( )1,4()1,4( )1,3()1,3( )1,4()1,4( ),1,3( ),1,4(1 1 tk t tPk tP tP tP P Pmeas meas (7-17) )2,3( )2,4()1,3( )2,4( )2,4()1,4( )2,3( )2,4( )1,3( )2,4( )2,4()1,4( )2,3( )2,3()1,3( )2,4( )2,4()1,4( ),2,3( ),2,4()2(2 )2(2 1 1 )211(21 )2(2 )1(1 )2(2 txPtx txPtx k txkPktxk txPtx txPtx txPtx P Pmeas meas (7-18) If the relation in Equation 7-19 holds, where m represents a constant, it can be found that Equation 7-17 equals Equation 7-18. In this way, the segmented characterized relations in Figure PAGE 137 137 7-6 can meet the requirement of MPPP linearity and be mistakenly considered a good characterization result. m t t t t )1,4( )2,4( )1,3( )2,3( (7-19) By adding another load r2 into the characteriza tion standard set where r2 causes a characterized power region, across region II and III as specified in Figure 7-6, MPPP linearity requirement becomes not satisfied as stated in Equation 7-20 unle ss the ratio between P3 and P4 still equals k1 with the load r2 and both t(4,3)/t(4,2) and t(3,3)/t(3,2) equal m meas meas meas measP P P P),4,3( ),4,4( ),3,3( ),3,4( (7-20) Therefore, the originally good model becomes bad when adding one more load to the original calibration stan dard set. The significant fact illu strated here is that expecting a good characterization quality by checking the MPPP linearity criteria over so me limited number of loads is hazardous. On the contrary, RMSPP linearity, having a more rigid requirement, can help detect the foregoing ill-conditioned characterization. The de tection mechanism can be explained by Figure 7-7, where the dotted line represents the proble m illustrated in Figure 7-6 and the solid line represents the good-conditioned characterizati on that meets RMSPP linearity requirement. Figure 7-7. RMSPP linearity detects the i ll-conditioned charac terization result. PAGE 138 138 Since RMSP P linearity requires that the proportion factor between th e measured and the real power be constant at all time s the ill condition can be detected because of Equation 7 21 and the good condition can pass because of Equation 7 22. Unlike MPPP linearity requirement, RMSP P linearity requirement can promise to filte r out all the ill conditioned characterization results and retain only good-conditioned cases ) 2 3 ( ), 2 3 ( ) 1 3 ( ), 1 3 (2 tan 1 tan P P P Pmeas meas (7 21) ) 2 3 ( ), 2 3 ( ) 1 3 ( ), 1 3 (' 1 tan P P P Pmeas meas (7 22) 7. 5 Optimization Algorithm It is know n from S ection 7.4 that RMSP P linearity is more r obust in examining the quality of detector characterization results. Following thi s train of thought, two figures -of -merit that can help evaluate the appropriateness of the characterization models are proposed in this section by exploit ing the advantage of RMSP P linearity. The first pr esented figure -of -merit, called CV total is for situation where the real incident power at the emb edded detectors input ports is known as if in the simulation mode The second pr esented figure of -merit, called Total error, i s for situation wher e the real incident power at the emb edded detectors input ports is unknown as if in the measurement mode. The former is used to validate the latter, which is applicable to real world measurement. 7.5.1 Figure -of -Merit for Simulation In order to evaluate and hence validate the pr esented figure -of -merit that is applicable to real -world measurement, it is necessary to have another figure -of -merit serving as a golden standard. To have this it is helpful to realize that the real incident po wer at the input port of each embedded detector is known in simulation mode Hence the figure -of -merit serving as a golden PAGE 139 139 standard, also regarded as the RMSP P linearity error quantification in simulation mode can be defined through the coefficient of variation (CV) of the ratios between the real and the measured power The actual calculation procedure is given in Equation 7 23, where the function fcv means taking the coefficient of variation of the terms enclosed by the parentheses With different input power levels and calibration loads, many measured power values are available by each detector when the characterization is over. For each detector, if we divide the real incident power by its corresponding measured power and get many ratios, the ideal case is that they should be all the same and their coefficient of variation should be zero. Therefore, by summing up the four CVs contributed by the four detectors, the figure -of -merit CV total based on the very de finition of RMSP P linearity, can be presented as in Equation 7 23, where greater values stand for worse characterization results. ) (6 3DET of ratios power f total CVCV DET DET DET (7 23) 7.5.2 Figure -of -Merit for Measurement Although error of the RMSP P linearity can be quantified intuitively by the consistence level of th e ratios between the real and the measured power for each detector as shown in Equation 7 23, the real incident power in experiment, unfortunately, is inaccessible. To solve this problem and present a figure -of -merit accommodating the real -world measuremen t Equation 7 22 is first rewritten into a more general form as in Equation 7 24, and then rearranged as in Equation 7 25, where Pmeas and P represent the measured and real incident power at a certain detector, and the primed variables indicate the corresponding values when there is a new value of the input power to the SPR P P P Pmeas meas (7 24) PAGE 140 140 P P P Pmeas meas' (7 25) Although P and P are unknown in measurement, for each calibration load, they are in the same proportion to the SPRs input power, a fact that means they are both proportional to the square of the SPRs input voltage and that their ratio can be known Therefore, two parameters A and B, ideally equal, can be defined as in Equations 7 26 and 727, where vin rep resents the input voltage to the SPR. A P Pmeas meas (7 26) B v v P Pin in 2 2) ( ) ( (7 27) Since A and B should be ideally equal, the severity of RMSP P linearity inaccuracy can thereafter be quantified as in Equation 7 28. B B A error 100 ) ( (7 28) For each calibration load and for each detector having N levels of input means at least N -1 terms by considering only the consecutive levels, of error as in Equation 7 -28 can be derived. Among th ese N -1 terms of error, the maximal one is selected as the representative for that combination of calibration load and detector. To have a thorough inspection, the figure -of -merit for measurement use, also regarded as the RMSP P linearity error quantification in measurement mode, can finally be defined as the summation of all the representatives coming from every combination o f calibration load and detector T he formula is shown in Equation 7 29, where M is the number of loads used to perform detector characterization )(6 3 1DET of error Max error TotalDET DET DET rM r load (7 29) PAGE 141 141 7.6 Simulation Results In this section, t he two figures of -merit pr esented in S ection 7.5 are demonstrated to evaluate different combinations of characterization models, model orders, and intrinsic coefficients. With the same test envir onment given in S ection 7.3, CV total and Total error show their ability to select the best solution from all the possibilities. T he nearly complete association relation between these two factors also validates the application of Total error in real measur ement. 7.6.1 Success of the Determination of Model Type Three models are analyzed under the same test environment given in S ection 7.3 through the help of the two developed figures -of -merit CV total and Total error. T he simulation result s reported by the t wo figures -of -merit with respect to different order s for each model are compared in Figure 7 8 where (B) and (D ) are the zoom ed in representation of ( A ) and (C) Figu re 7 8 Figures -of -merit for the three models M1, M2, and M3 A) full -range Total error B) zoom ed in Total error C) full range CV total and D) zoom ed in CV total A B C D PAGE 142 142 In Figure 7 8 M1 represents the Bergeault Model with q equal to unity M2 represents the Demers Model with Vk equal to the detectors output as is defined in [ 31], and M3 represents the modified Demers Model with Vk equal to the detectors output minus the output when no power is input to the SPR. Under the same test condition as is given in S ection 7.3, M1 is found to be the optimal because both the minimums of CV total and Total error happen in this model at the order of six. Another way to visualize Figure 7 8 is shown in Figure 7 9 where the two fig ures -of -merit are compared for each model with respect to different model orders Again, it can be clearly seen that M1 with a n order of six is the optimal solution. From Figure 7 9 it can also be seen that CV total and Total error have very similar trends for all the three models. Figure 7 9 Anothe r way to visualize Figure 7 8 By plotting these two figures -of -merit for t he three models as x axis and y axis data respectively, they can be found to be very positively correlated as is shown in Figure 7 10, where PAGE 143 143 (B) is the zoom ed in graph of ( A ). This very close relation ship proves the validity of applying Total error to real -world measurement. Figure 7 10. The relation ship between Total error and CV total. A) full range, B) zoom ed -in. In addition, it can be seen that the encountered problem described in S ection 7.3, which is represented by M2 here, should be totally excluded from candidacy regardless of what value the model order is due to its enormous CV total and Total error. Hence, through t he examination of the two developed figures -of -merit, it can be guaran t e ed that mistakenly using some seemingly good models is com pletely avoidable 7.6 .2 Success of the Determination of Model Order In S ubsection 7.6.1, it is fore c asted that there exists an optimal order for each model. For example, model M3 in Figure 7 9 has an optimal order of ten Although it is already known tha t the optimal model order can be easily derived through the calculation of Equation 729 during measuring, there is an additional issue worth mentioning. One example of using the Bergeault Model with q equal t o 0.5492 is shown in Figure 711(A) where the same stimulus input voltage levels as in S ection 7. 3 are given Although the Total error for the order from 13 to 15 seems to be smaller it is misleading to think that they A B PAGE 144 144 are better choices than 5 because starting from the order of 12 a rank deficiency representing damping imprecision begins to take place. To prove that higher orders are not the best solution, 100 points of voltages are uniformly interpolated into each of the original input voltage intervals and the new Total error is recalculated by u sing the old model coefficients. Th e result is shown in Figure 7 11(B), where originally an invisible damping problem of higher orders is revealed and the optimal order is confirmed to be 5 instead of 13 to 15. From this experiment, it is realized that one cannot merely depend on what Total error reports. That is, when ever a rank deficiency warning starts to show up the consideration of using that order or higher ones should be abandoned. Figure 7 11. Total error helps decide the optimal order for a specific model A) no input voltage interpolation, B) with input voltage interpolation. 7.6.3 Success of the Determination of Intrinsic Parameter To demonstrate that the prese nted optimization algorithm in S ection 7.5 can help determine the optimal value f or the intrinsic parameter within a model, the Bergeault Model is used here as an example. Although a rough estimate for assigning q inside the model equation is A B PAGE 145 145 recommended in [ 35], the exact optimal value still varies with cases partly because of the dif ference in circuit topology and test conditions and partly because of the omission of the parameter from [35] to [ 30]. Adopting the recommendation given by [ 35] and applying it to the test condition described in S ection 7.3, a starting value for q can be decided to be 0.69. Starting from this initial guessing point, the optimal value for q obtained by searching in opposite directions, can then be acquired through Equations 7 23 and 7 29. Figure 7 12 shows the simulation result, where both CV total and To tal error indicate that the optimal q should be equal to 0.5492 at the order of 5. Figure 7 12. Determination of the optimal values for q A) Total error B) CV total. 7.7 Another Method of Verification One other way to verify Equation 7 29 is to si mulate the SPR working in its normal operation mode, where a fixed level of power is input and a group of loads are measured. By fixing the input sinusoidal signal amplitude to the SPR at 0.8 volt and by lett ing the SPR measure 80 loads, whose reflection c oefficients magnitudes range uniformly from 0.2 to 0.8 with an angle interval of 22.5 degrees, there can be 80 values of real incident power and 80 values of the A B PAGE 146 146 corresponding measured power for each detector. By taking the CV of the ratios of the real to measured power for ea ch detector and by adding them up, another factor can be defined, called CV total2 By plotting the v alues of CV total2 for the four models ( M1 M2 M3 are from S ubsection 7.6.1 and M4 is the one with optimal q from S ubsection 7.6.3) wi th orders from 3 to 11 as y axis data, and by plotting the corresponding values of Total error as x axis data Figure 7 13 shows that CV total2 and Total error, s imilar to the relationship between CV total and Total error in S ubsection 7.6.1, are again ver y positively correlated, which fortifies the validity of applying Total error to real -world measurement. Besides, Figure 7 13 also shows that M4 is still regarded as the optimal by CV total2 as by CV total and Total error previously. Figure 7 13. The relation ship between Total error and CV total2. A) full range, B) zoom ed in. 7.8 Conclusion Two types of the most commonly used detector characterization models are introduced in this chapter. In addition, the encountered problems of doing the detector characterization are described. To solve these problems, two types of linearity are introduced and their properties analyzed. With the conclusion that RMSP P linearity is more robust, the optimization algorithm is presented by exploiting the advantage of the RMSP P linearity. Two figures -of -merit are defined A B PAGE 147 147 in the optimization algorithm, where CV total is used to validate Total error, which is applicable to real measurement. From the demonstrations, it is shown that Total error can help solve all the previousl y mentioned problems by correctly determining the optimal type of model, the optimal order for that model and the optimal intrinsic coefficient q within the model Another way to verify the effect of Total error is also given, where the SPR is working und er its normal operation mode measuring a group of loads. For the four models in S ection 7.7 with orders ranging from 3 to 11, it is found that Total error and CV total have a correlation coefficient of 0.999907, and Total error and CV total 2 have a correla tion coefficient of 0.999769. These almost unity correlation coefficients substantiate the function of Total error when it is applied to real measurement. Although the most suitable detector characterization set differs from case to case and may be affecte d by many factors the figure -of -merit defined in Equation 7 29 is able to select the optimal one among a group of options under a given test condition. Therefore, neither spending so much time fathoming the fitness between a n SPR and certain mathematical models nor depending merely on experience and trying to manage by some passable model is necessary. The ease and proof of Equation 7 29 provide with the practicability and reliability in finding the optimal characterization solution for embedded detectors in any SPRs. PAGE 148 148 CHAPTER 8 SUMMARY AND SUGGESTI ONS FOR FUTURE WORK 8.1 Summary This dissertation focuses on the implementation of embedded S -parameter measurement systems. Two different strategies are explored in this research work. Based on the success in implementing on -chip lumped devices with reasonable sizes S11 and S21 detection networks are developed to process RF signals so that back -end detectors can measure the S11 and S21 of a DUT by directly sensing the processed signals Although a bit of d iscrepancy exists between the measurement and simulation results due to the possible process variation on the embedded DUTs, the measurement results still substantiate the design concept and manifest the importance of an even layout on the paths from port 1 to port 2 and from port 1 to port 3 T he simple structures of the S11 and S21 detection networks guarantee their easy usage in the future when amplitude and phase detectors are integrated. Based on the assumption that process variation is negligible no complicated calibration procedures are necessary and S parameters can be derived directly by reading the output of the detectors. However, f rom the calculation equation s of the lump devices design values provided in [ 13], it is estimated by this disserta tion that the presented detection networks can best operate from 5 GHz to 15 GHz. Below 5 GHz, the sizes of the lumped devices become formidably large and the gargantuan area overhead makes the networks unattractive Above 15 GHz, the sizes of the lumped d evice s become t oo small to be fabricate d. Even were they manufactured, the networks will become so susceptible to other parasitics that calibration becomes unavoidable To discern the problematic site in case measurement errors occur and to prepare for broadband applications, calibration methods for the detection networks are presented in C hapter 4 where the calibration standards are required to possess certain level of absolute precision, PAGE 149 149 which at higher frequencies are more difficult to realize than the sliding short, need ed to calibrate SPRs and required only to possess relative precision level Therefore, this dissertation suggests that the maximal application frequency of the S11 and S21 detection networks be set at 1 5 GHz. To accommodate embedded S pa rameter measurement at higher frequencies, SPR is investigated as the second theme of this research work. To prepare for its construction, the only active component within the SPR, the amplitude detector, wa s designed and fabricated. The simulation results show that the amplitude detector can operate up to 80 GHz and the measurement results verify its functionality up to 67 GHz due to the test equipment limitation s Also, the diode -connected NPN bipolar amplitude detector is analyzed in a closed-form. To be able to operate at higher frequencies SPRs posses s several favorable advantages. Requiring only amplitude detectors helps SPRs avoid the use of phase detectors, wh ich are infamous for their signal magnitude dependent response issues In addition, being a n over determined system and having a set of solid calibration algorithms enables a n SPR to resist errors from process variations and parasitics. In view of these advantages, two SPR systems, targeted at 20 GHz and 40 GHz, were designed and fabricated. The 20-GHz SPR is verified through measurement at 20 GHz and the 40GHz SPR is measured at 30 GHz, 40 GHz, and 50 GHz. All the measurement results prove the functionality of the two SPRs and confirm that a n SPR can work over a wide band. To improve the measur ement p recision of a n SPR, a new figure of -merit, which helps determine the optimal model set for detector characterization of SPR, and its calculation algorithm is also presented. However, since the calibration and measurement procedures of a n SPR are com paratively complicated and tedious, it is recommended not to be used for low -frequency applications Unless the used semiconductor technology has a very poor yield o nly when the measuring PAGE 150 150 frequencies are high enough ( approximately above 15 GHz), would it be meaningful to use SPRs to perform on -chip S parameter measurement s Otherwise, it would be like sailing a cruise ship to cross a stream. 8.2 Suggestion s for Future Work The ultimate objective of our research is to realize embedded S -parameter measureme nt systems on chip. Based upon the foundation that this dissertation has built up four suggestions for future work are given in the hope of providing interested researchers with some helpful guidance and reaching the ultimate RF BIST goal sooner. The suggestions are as follows. 1 The integration of amplitude and phase detectors Since the functionality of the S11 and S21 detection networks has been fully verified, detectors can be integrated into the networks to make the S parameter measuring systems more com plete. For the S11 detection network, i f both the magnitude and phase information of the S11 of a DUT is of interest, the network in Figure 3 1 can be modified to that in Figure 8 1 where two additional dividers are used to generate two pairs of identical RF half power signals. With this integration when an RF signal is input into port 1, the amplitude of S11 can be known by dividing the output from port 4 to that from port 2, and the phase can be derived by the output from port 3. Port 1 D R C DUT1 50 DIV 1 2 3 1 2 3 4 D R C 1 2 3 4 50 1 Amplitude DET Port 2 Amplitude DET Port 4 DIV 1 2 3 DIV 1 2 3 Phase DET Port 3 Figure 8 1. The integration of cascaded detectors for the S11 detection network. PAGE 151 151 Similarly, if both the magnitude and phase information of the S21 of a DUT is desir ed the S21 detection network in Figure 34 can be modified in to that in Figure 8 2, where the RF signal is input from port 1, the amplitude of S21 can be known by dividing the output from port 4 to that from port 2, and the phase can be derived by the output from port 3. Port 1 DIV 1 2 3 DUT2 DIV 1 2 3 DIV 1 2 3 1 2 Amplitude DET Port 2 Amplitude DET Port 4 Phase DET Port 3 Figure 8 2. The integration of casca ded detectors for the S21 detection network. 2 The exploration of dual SPRs Based upon the great success of measuring S11 at up to 50 GHz by using single SPR it should be a good idea starting the exploration of the dual SPR s which requires two copies of SPRs and enable s the full 2 port S -parameter measurement Enclosed by the dotted lines, t he structure of a dual SPR system is shown in Figure 83, where two SPRs are placed at each side of the DUT. SPR Pin1 DUT SPR Pin2 Dual SPRs Figure 8 3. The structure of a dual SPR system. 3 The construction of on-chip RF signal s ource PAGE 152 152 There are several advantages of creating on -chip RF signal sources. Due to the paragraph limitation, just some major ones are stated here First, having an on-chip RF signal generator makes o ne on -chip S parameter measurement system more self -contained. Second, it can prevent serious signal loss through cables, connectors, and probes occurring when external RF signal source s are applied. Besides, being located on the same chip it becomes easi er and more accurate in estimating the real signals reaching the DUTs. Last of all, the test capability wont be limited by external test equipment. 4 The improvement in SPR calibration algorithms Although the existing calibration algorithms for SPR are very solid and comprehensive, the required procedures are a bit too tedious and the concepts are a bit too formidable. By ruminat ing about the meaning of its calibration, one can see that it is nothing more than a mapping problem. That is, finding a way that c an map correctly the voltage readings in to S parameter readings. In view of this idea this dissertation suggests that effort be spent on the investigation of SPR calibration algorithms in order to improve and simplify or even replace the present ones and make the use of SPR more accessible PAGE 153 153 APPENDIX A MORE DETAILED DISCUSSIONS OF THE DESIGN CONCEPTS IN CHAPTER 3 A.1 Discussions of the Embedded S11 Detection Network To have the embedded S11 detection network in Figure 3-1 work properly according to Equation 3-1 around the targeted frequency, the five assumptions given in Section 3.2 need to be satisfied. However, they are not so complete as to help comprehend the network design concept and understand its limitation. Hence, some more fundamental and detailed discussions are given here in the hope of providing with more insight and clarity. If considering the first-order non-ideality wi thin the detection network, the simple RF signal propagation condition shown in Figure 3-3 n eeds to be modified to Figure A-1, where the solid arrows represent the original signals reaching port 2 and port 3 and the dotted arrows represent the extra signa l coupling due to the first-order nonidealities of the system. According to Figure A-1, the signals reaching port 2 and port 3 of the system can therefore be redefined as Equations A-1 and A-2. In Equations A-1 and A-2, the first term is the original desired term that allows the network to determine the S11 of the DUT1, and the second term is the unwanted term that occurs due to first-order non-ideality of the system and can hinder the network from measuring S11_DUT1 correctly. Figure A-1. Modified signal propagation within the embedded S11 detection network. DRC DIV DRC DRC DIV SYSSSSSSion Approximat OrderstS_41 _21 _43 _31 _21 _21) 1( (A-1) PAGE 154 154 DRC DIV DRC DRC DUT DIV SYSS S S S S S ion Approximat Order st S_ 41 21 43 31 1 11 21 31) 1 ( (A 2) According to Equations A 1 and A 2 the S11_DUT1_DERIVED given in Equation 31 can be modified to Equation A 3 to evaluate the influence caused by the first -order non ideality of the system. To gain more insight Equation A 3 can be rearranged to Equation A 4 by dividing both the numerator and denominator by S21_DIVS41_DRC. N eglecting the trivial point that S11_DUT1_DERIVED will equal S11_DUT1 when S11_DUT1 equals unity, the significance expressed by Equation A 4 is that the proxi mity between S11_DUT1_DERIVED and S11_DUT1 can be gained by making the denominator (i.e. DRC DRC DRCS S S_ 41 43 31 +1 ) sufficiently large or, equivalently, making the newly -defined term A sufficiently large. DRC DIV DRC DRC DIV DRC DIV DRC DRC DUT DIV SYS SYS DERIVED DUTS S S S S S S S S S S S S S_ 41 21 43 31 21 41 21 43 31 1 11 21 21 31 1 11 (A 3) DRC DRC DRC DUT DUT DRC DRC DRC DUT DUT DRC DRC DRC DUT DRC DRC DRC DUT DRC DRC DRC DRC DRC DRC DUT DERIVED DUTS S S A where A S S S S S S S S S S S S S S S S S S S S S S S_ 41 43 31 1 11 1 11 41 43 31 1 11 1 11 41 43 31 1 11 41 43 31 1 11 41 43 31 41 43 31 1 11 1 11, 1 1 1 1 1 1 ) 1 ( 1 1 (A 4) From the first -order non ideality analysis above it can be known that al though any unsatisfied assumption among the five given in S ection 3. 2 can spoil the equality in Equation 3 1, the bottleneck of the whole network design is limited by the directional coupler, and the most important specification parameter of design interest is the parameter A defined in Equation A 4. PAGE 155 155 Figure A 2 shows the magnitude of the parameter A for the embedded S11 detection network presented in C hapter 3. As can be s een, the best operating frequency of this system to the first order approximation should be at 10.58 GHz, which is very close to the intersect ed frequency 10.25 GHz, between S11_DUT1 and S11_DUT1_DERIVED presented in Figure 3 7 Figure A 2 The magnitu de of the parameter A in Equation A 4 A.2 Discussions of the Embedded S21 Detection Network A.2.1 First -Order Non -ideality A nalysis of the Embedded S21 Detection Network To have the embedded S21 detection network in Figure 3 4 work properly according to E quation 3 2 around the targeted frequency, the two assumptions given in S ection 3.3 need to be satisfied. However they are not so insightful to help comprehend the network design concept and its limitation. Hence, some more fundamental and detailed discus sions are given here in the hope of providing with more insight and clarity. If considering the first -order non ideality within the detection network, the simple RF signal propagation condition shown in Figure 3 6 needs to be modified to Figure A 3, where the solid arrows represent the original signals reaching port 2 and port 3 and the dotted arrows represent the extra signal coupling due to the first-order nonidealities of the system. According to Figure A 3, the signals reaching port 2 and port 3 of the system can therefore be redefined as PAGE 156 156 Equations A-5 and A-6. In Equations A-5 and A-6, the first term is the original desired term that allows the network to determine the S21 of the DUT2, and the second term is the unwanted term that occurs due to first-order non-ideality of the system and can hinder the network from measuring S21_DUT2 correctly. Figure A-3. Modified signal propagation within the embedded S21 detection network. ) 1( ) 1(1_23 _21 _21 _21 DIV DIV DIV SYSS SSion Approximat OrderstS (A-5) ) 1( ) 1(2_23 _21 _21 _21 _31 DIV DUT DIV DIV SYSS SSSion Approximat OrderstS (A-6) By observing Equations A-5 and A-6, it can be noted that the interference effect caused by the first-order non-ideality of the system can be suppressed to the utmost when the S23_DIV is reduced to the minimum. From the first-order no n-ideality analysis a bove, it can be concluded that although any unsatisfied assumption among the two given in Sect ion 3.3 can spoil the equality in Equation 3-2, the bottleneck and the mo st important specifica tion parameter of design interest for the S21 detection network is the S23 of the divider. Figure A-4 shows the magnitude of the S23 of the divider. As can be seen, the best operating frequency of this system to the firstorder approximation should be at 9.15 GHz, which PAGE 157 157 is very close to the real intersection frequency of S21_DUT2 and S21_DUT2_DERIVED presented by Figure A 7 in Sub section A.2.2 Figure A 4. The magnitude of the S23 of the divider A.2. 2 Design Clarification for the Embedded S21 Detection Network As mentioned in S ection 3.3, the port 3 of eac h of the dividers on the right in Figure 3 4 is left as open in order to observe the worst -case response of the S21 detection network with totally unmatched loads. By doing so, a considerable amount of signal will be reflected back into the network and hen ce damage the system performance This unwanted signal coupling explains why the intersection frequency of the S21_DUT2 and S21_DUT2_DERIVED curves is shifted far away from its first order approximated 9 .15 GHz in Figure A 4 to 11.25 GHz in Figure 3 8. In this sub section, more details will be explored to discuss this discrepancy between the design expectation and the design result. Originally, with no intention to observe the worst -case response of the system, the proposed embedded S21 detection network in Figure 3 4 should have the system level architecture shown in Figure A 5 where all the output ports are well -matched. With this system level architecture, the simulation result demonstrated in Figure 3 8 will become that shown in PAGE 158 158 Figure A 6. As can be seen in Figure A 6, the network has a wid er 3% -error bandwidth, enclosed by the solid red rectangle, from 7.608 GHz to 10.056 GHz. Figure A7 shows the error percentage of the S21_DUT2_DERIVED shown in Figure A 6. As can be seen, the minimal error frequency f alls at about 9 GHz, which is very close to the first -order approximation estimated in Figure A 4. Compared to Figure A 7, Figure A 8 shows the error percentage of the S21_DUT2_DERIVED shown in Figure 3 8. As can be seen, the error percentage is increased and the curve shape is also twisted. The resultant 6%-error bandwidth enclosed by the dotted pink rectangle is from 8.63 GHz to 11.627 GHz and the 3% -error bandwidth, enclosed by the solid blue rectangle, is from 11.017 GHz (lb) to 11.417 GHz (ub) which is the bandwidth provided in Section 3. 4. Port 1 50 DIV 1 2 3 Port 2 DUT2 DIV 1 2 3 50 Port 3 DIV 1 2 3 1 2 Figure A 5. Original system -level architecture of the S21 detection network. PAGE 159 159 Figure A 6. Simulation result of the network in Figure A 5 Figure A 7. E rror percentage of the S21_DUT2_DERIVED in Figure A 6 Figure A 8. Error percentage of the S21_DUT2_DERIVED in Figure 3 8 From the above analysis, two conclusions can be made. First, the first -order non ideality approximation analysis given in Appendix A 2.1 for the embedded S21 detection network is PAGE 160 160 correct S econd the reason why the 3%error bandwidth presented in Figure 3 8 is deviated a bit from the first -order estimation presented in Figure A 4 is because the port 3 of the two dividers on the right in Figure A 5 are deliber ately left as open. Since the loads connected to the two dividers in real practice will be made as matched as possible and never be open it can be expected that the effect caused by mismatched loads will fall in between what is estimated by Figure A 7 and Figure A 8 f or f uture version of implementation. The more the loads are matched, the closer the result will be to the estimation given by Figure A 7, and the wider the resultant 3% error bandwidth will be A.3 Analysis of the Intentional O pen in the Embedded S11 Detection Network For the S11 detection network system -level architecture presented In Figure 3 1, the port 3 of the upper DRC is left intentionally as open. Although effort has been spent on perfecting this open when drawing the layout, some inevi table parasitic capacitance still exists in the real -world layout geometry. To gain more detailed information of this theoretically ideal open, the post layout simulation is performed. Figure A 9 shows the layout surroundings of the intentional open, where several ground nodes can be seen to be around the open node at certain distance. Figure A 9. The layout surroundings of the intentional open PAGE 161 161 To estimate the parasitic capacitance on the node of the intentional open according to the actual physical des ign, a 3D field solver (Raphael) is used By taking a large surrounding area around the open node into account, t he simulation result is believed to be more pessimistic than the real situation. According to Raphael, the parasitic capacitance of the open is about 22 fF which is also shown in Figure A 10. By r eferring to Figure 2 1 and Figure 31, it can be known that this non ideal parasitic capacitance will perturb the original design of the capacitor C1 in the directional coupler. Since the design value o f C1 in this dissertation is 229 fF as is shown in Figure 2 1 it is concluded that the non -ideal open can at worst contribute an error of about 9.68% on the design value of the capacitor C1 in the directional coupler. Figure A 10. The parasitic capaci tance at the open node reported by Raphael PAGE 162 162 APPENDIX B MORE MEASUREMENT DAT A ANALYSIS IN CHAPTER 3 B.1 More Measurement Data Analysis of Embedded S11 Detection Network It is mentioned in S ection 3.5 that some discrepancy exists between the measuremen t and simulation results of the S11 detection network. Because the DUT1 is enclosed in the measuring system and there is no measurable DUT1 that stands alone, it becomes real difficult to interpret the measurement data and judge the site, the DUT1 or the detection network, that creates error However, by exploiting the measured data, there are still some ways that can help investigate and indentify the dominant problematic site that potentially cause s the measurement error. The analysis and reasoning for th e measurement data of the S11 detection network are given in this section. Since directly analyzing the impact of each component in the network shown in Figure 3 1 is too complicated and formidable to give any practical insight, it is necessary to circumve nt the complica tions by using a rather simplified model. To do this an effective technique is to examine the network at a DC or nearly DC frequency point. This is practical and convenient because the nearly DC data can easily be retrieved by tak ing the S -parameter s measured at the lowest frequency. Since the lowest frequency taken for the S11 detection network in this research is at 50 MHz, the following analysis is mainly one that approximates the nearly DC 50 MHz as DC When the network operates at a nea rly DC frequency, the capacitors can be approximated as open and the inductors as short. In this way, the S11 detection network can be si mplified to that in Figure B 1, where RDRC represents the 50 1 and RDUT1 represents the 50istor in Figure 3 2. There is however, not too much useful information for this simplified network to give due to its over simplification. W hen the network is measured by a PAGE 163 163 VNA in a 3 port measuring configuration, the impedance seen by port 2, which can be retrieved by S22 of the 3 port S -parameter measurement, will be like Equation B 1 and that seen by port 3, which can be retrieved by S33 of the 3 port S -parameter measurement, will be like Equation B 2 where there is no difference in between and thus can not provide with any useful information. Port 1 Port 2 Port 3 RDRC RDRC RDUT1 Figure B 1 The over -simplified DC model of the S11 detection network 25 || 5 0 || || || || ||1 0 1 0 2 DRC DUT DUT DRC DRC portR R Z R R Z R Z (B1) 25 || 5 0 || || || || ||1 0 0 1 3 DRC DUT DRC DRC DUT portR R Z R Z R R Z (B2) As a matter of fact, even the different simulat ed values of S22 and S33 by CAD tools can prove that the network in Figure B 1 is over -simplified At 50 MHz, t he simulated S22 and S33 values are about 0.5145 and 0. This means that the resistance observed by port 2 is different from that by port 3 and invalidates the model in Figure B 1. To make the simplified network more realistic and closer to the real -world situation, the resistance of the inductors needs to be taken into consideration. To do this, it is assumed that the inductor L2 of the DRC in Figure 2 1 has a resistance of R 1 the two inductors L1 in series in Figure 2 1 has a resistanc e of R2 the 50 1 has a resistance of R 3 the inductor L1 in Figure 2 3 has a resistance of R 4 and the resistance looking into DUT1 is R 5 (including the inductor L and resistor R in Figure 32). Because the resistance of an inductor PAGE 164 164 should be comparatively small compared to the resistor R1 3, it can simply be neglected when there is another path of much less resistance connect ing its both ends. By having the above assumptions, the network in Figure B 1 can be modified to that in Figure B 2. Port 1 R4 R4 Port 2 Port 3 R2 R5 R1 R1 R2 R3 R2 R2 R1 R1 R3 Figure B 2. The simplified DC model of the S11 detection network. From Figure B 2, it can be noted that there is a certain lev el of symmetry in this network because the resistance seen by port 2 is identic al to that seen by port 3 if R5 did not exist With this observation it can be intuitively reason ed that when all the resistors are having the same amount of variation, the variation on R5 would have the biggest effect on changing the difference of the re sistance values observed by port 2 and port 3. That is, if there is any variation on the difference of the resistance values observed by port 2 and port 3, R5 is the most potential one that cause s such change. To prove that this intuition is correct, the r esistance seen by port 2 and port 3 are analyzed. Figure B 3 and Figure B 4 show the resistance seen by port 2 and port 3 when performing the 3 port S parameter measurement using a VNA. As can be seen, the resistance seen by port 2 and port 3 (Zx and Zy) a re functions of R1 to R5. To evaluate the compact each resistor has toward the difference between Zx and Zy, some mathematical operations are performed and the procedures are described as follows. PAGE 165 165 Figure B-3. The resistance seen by port 2 in Figure B-2. Figure B-4. The resistance seen by port 3 in Figure B-2. Take R1 for example, the Zx and Zy are first differentiated with respect to R1 as shown in Equations B-3 and B-4. Then one function is subtracted from another and the absolute value of the subtraction is calculated as expressed by Equa tion B-5. The last step is to calculate the slope of the new function among consecutive data points as expressed by Equation B-6. )5,4,3,2,1(1 1 RRRRRfZ Rx (B-3) )5,4,3,2,1(2 1 RRRRRfZ Ry (B-4) 213 fff (B-5) )3(4 fslopef (B-6) The meaning of the above pr ocedures is that if Zx and Zy have the same trend of variation with respect to the variation on R1, then the resultant difference between the new values of Zx PAGE 166 166 and Zy would not have too much change. On the contrary, if Zx and Zy have different trend of variation with respect to the variation on R1, then the resultant difference between the new values of Zx and Zy would be different from its original value. According to simulation, the resistance values of R1 to R5 at 50 MHz are 4.3 8 By applying the procedures expressed from Equations B3 to B 6 to all the five resistors R1 to R5 in Figure B 2 and by using the above simulated resistance as the nominal values the comparison results are plotted in Figure B 5, where the curve representing R5 is the most sloping indicating that R5 should be responsible if there is any change of the difference between Zx and Zy. Hence, the reasoning by intuition is proved to be correct. Figure B 5. The s lope of the difference of slope for the five resistors According to the 3 -port S parameter measurement results of the S11 detection network, the S22 and S33 at 50 MHz are about 0.2463 and 0.3393, respectively. This means that the measured values of Zx a nd Zy more than three times larger compared PAGE 167 167 Therefore, it is reasonable to consider the variation on R5 the top suspect that cause s the deviation between the measurement and simulation results Because R5 stands for the effective resistance of the inductor L in series with the resistor R in Figure 3 2, it can therefore be concluded that the process variation on DUT1 is the most poten tial one that brings about the difference between the simulation and measurement results for the S11 detection network in S ection 3.5. Another way to double -check the problematic site in the network is to compare the simulated S21 and S31 with their measur ed counterpart. Figure B 6 shows the comparisons between the simulated and measured magnitude s of S21 and S31. As can be seen, except for some minor loss problem, larger discrepancy exists between the curve of the simulated and measured S31. Since the layo ut structures from port 1 to port 2 and port 3 are identical except the DUT1 part, the inference is reconfirmed that the potential problematic site happens on the DUT1. Figure B 6. The magnitude comparison between the simulated and measured S21 and S31. B.2 More Measurement Data Analysis of Embedded S2 1 Detection Network Like the DC analysis technique demonstrated in Section B.1 some similar DC analysis can also be applied to the S21 detection network in order to gain more information about the potentia l PAGE 168 168 reasons that cause the phase inaccuracy between the simulation and me asurement results described in S ection 3.5. To do this, it is assumed that the inductor L1 in Figure 2 3 has a resistance of RDIV, the resistor R1 in Figure 2 3 has a resistance of R118, and the inductor L in Figure 3 5 has a resistance of RDUT2. By having the above assumptions, the S21 detection network in Figure 3 4 can be simplified to the DC model shown in Figure B 7. Port 1 Port 2 Port 3 RDIV RDIV RDUT2 RDIV RDIV RDIV RDIV R118 R118 R118 Figure B 7. The simplified DC model of the S21 detection network. By taking the two-port S parameter measurement at port 1 and port 2 in Figure B 7 the resistance seen by port 1 which can be retrieved by S11 of the 2 -port S -parameter measurement, should be the Zx shown in Figure B 8 Simi larly, By taking the two -port S -parameter measurement at port 1 and port 3 in Figure B 7, the resistance seen by port 1, which can be retrieved by S11 of the 2 -port S -parameter measurement, should be the Zy shown in Figure B 9. By comparing Figure B 8 and Figure B 9, it can be noted that Zx and Zy differ only by the resistor RDUT2. Hence, it is practicable to verify the resistance of the fabricated RDUT2 through measurement. By performing the two port S -parameter measurement at port 1 and port 2, the S11 is found to be 0.121. By performing the two-port S -parameter measurement at port 1 and port 3, the S11 is found to be 0.1521. These two measured S11 values correspond to a Zx y of DUT2 after fabrica PAGE 169 169 resistance of RDUT2 is only 2.21 which shows that there is an increment of 1.96 on the path between port 1 and port 3 afte r the chip is manufactured. RDIV RDIVRDIVRDIVR118R11850 Zx Figure B-8. The resistance seen by port 1 when measuring port 1 and port 2. Figure B-9. The resistance seen by port 1 when measuring port 1 and port 3. This discovery is consistent with the meas urement results shown in Figure 3-16, where the magnitude part is fine but the phase part is deviated about -21.6 degrees from the simulation results at 11.05 GHz. Because the curve system meas is obtained by applying the measured S21 and S31 to Equation 3-2, this negative phase deviation indicates that there is an increase of signal path from port 1 to port 3, which rec onfirms the derived ex tra resistance of 1.96 According to analysis, it is not the inductor L in Figure 3-5 that sole ly contributes all the extra 1.96 which if true will cause a correspondi ng phase shift of about -33.61 degrees in Figure 3-16. Therefore, it can be inferred that part of the extra re sistance is caused by variations PAGE 170 170 on the inductor L in Figure 3 5 and part of the extra resistance is caused by variations on the interface paths connecting the DUT2 and the detection network. Based on the information that the width of the paths are made 6.48 m using the metal layer MT, having it is simulated that a wire of a length of 64.8 m (ten times the width) causes a phase shift of about 1.86225 degrees at 11.05 GHz Besides, is simulated to c ause a phase shift of about -37.990 9 degrees at such frequency With all this information, the portions contributed by the two factors can be known through solving Equations B 7 and B 8 when assuming that the resistance contributed by variations on the inductor is x variation on interface path s is y 9588 1 y x (B7) 6. 21 089 0 10 86225 1214 2 9909 37 y x (B8) From solving Equations B 7 and B 8 above, the x and y are found to be 1.16157 and 0.79723, respectively. That is, about 60% of the extra resistance is cont ributed by variations on the inductor in DUT2, and 40% of the extra resistance is contributed by variations on the interface paths. In addition, among the 21.6 degrees of phase deviation, it can also be calculated that about 19.93 degrees are caused by v ariations on the inductor in DUT2 and 1.67 degrees are caused by variations on the interface paths. Another way to double -check the validity of the above inference is to perf or m the 3 -port S parameter simulation on the S21 detection network and compare th e simulated S21 and S31 with their measured counterpart. Figure B 10 shows the comparisons between the simulated and measured phase s of S21 and S31. As can be seen, although both lag their corresponding simulation values at 11.05 GHz the measured S21 lags the simulat ed S21 only by about 80.6 while the measured S31 lags the simulat ed S31 by about 102.2, a longer lag that causes the phase difference PAGE 171 171 of about 21.6 in Figure 3 18. Based on the above analysis and reasoning and based on the fact that the lay out structures from port 1 to port 2 and port 3 are identical except the DUT 2 and its interface paths it is reasonable to identify the DUT 2 and its interface paths as the most potential problematic sites that caus e the measurement deviation in S ection 3.5. Figure B 10. The phase comparison between the simulated and measured S21 and S31. PAGE 172 172 APPENDIX C THE VARIABLE FORMATI ON IN CHAPTER 4 C .1 The Formation of Variables a, b, c, d from Type I Calibration Method The formation of the four complex vari ables a b c and d in Equation 4 1 can be obtained through flow graph analysis and the results are as follows. PAGE 173 173 C .2 The Formation of Variables a, b, c, d from Type II Calibration Method The new formation of the four complex variables a b c a nd d in Sub section 4.2.2 can be obtained through flow graph analysis and the results are as follows. PAGE 174 174 PAGE 175 175 PAGE 176 176 PAGE 177 177 C .3 The Formation of Variables l, m, n, o, p, q from Type II Calibration Method As described in Sub section 4.2.2, the reflection coefficient looking into the two 50resistors from port 2 of each DRC in Figure 3 1 can be factored out as in Equation 4 2 That is, the formation of the complex variables l m n o p and q can be obtained by analyzing the contents of a b c and d in Appendix C .2 and the results are as follows. PAGE 178 178 PAGE 179 179 PAGE 180 180 C .4 The Formation of Variables a, b, c for S21 Detection Network Calibration The formation of the four complex variables a b and c in Equation 4 7 can b e obtained through the flow graph analysis and the results are as follows. PAGE 181 181 As described in S ection 4.3, the formation of the complex variables l m n and o in Equation 4 8 can be obtained by analyzing the contents of the coefficient c given above, and the results are as follows. PAGE 182 182 APPENDIX D THE EXAMPLE GOLDEN D UTS IN CHAPTER 4 D .1 The Golden DUTs for Embedded S11 Detection Network In Sub section 4.2.2 three DUTs, DUT3, DUT4, and DUT5, are used to demonstrate that the derived r50 is also effective for DUTs other than DUT1 and that Type II calibration method can also be performed through having these as three golden standards. DUT3 and DUT4 are also used to demonstrate Type III calibration method in Sub section 4.2.3. The schematic of these example golden standards are shown in Figure D 1 where standards 1 to 3 represent DUT3 to DUT5 However, as explained in Sub section 4 .2.2 and Subsection 4.2.3 the choices of the golden standards are not necessarily limited to these three DUTs as lo ng as the standards S11 values are linearly independent Port 1 L = 1 823nH C = 409 fF Standard 1 R = 50 C = 339 fF Port 1 L = 1 281nH C = 409 fF Standard 2 R = 50 C = 339 fF Port 1 L = 786pH C = 409 fF Standard 3 R = 50 C = 339 fF Figure D 1. The schematic of the example golden DUT s for S11 detection network. D .2 The Golden DUTs for Embedded S21 Detection Network In S ection 4. 3 five DUTs are fi rst used as calibration standards to demonstrate the calibration method proposed for the embedded S21 detection network and cause the calibration results shown in Figure 4 14. Later, five more DUTs are added as the calibration standards to increase the pre cision of the calibration and cause the calibration results shown in Figure 4 16. The schematics of these ten example golden standards are shown in Figure D 2 and Figure D 3 where standards 1 to 5 are the first group being applied and standards 6 to 10 ar e the second PAGE 183 183 group being added as the auxiliary. Again as explained in S ection 4.3 as long as the standards S21 values are linearly independent, the choices are not necessarily limited to these ten DUTs. Port 1 L = 306pH C = 249 fF Port 2 Standard 1 Port 1 L = 534pH C = 249 fF Port 2 Standard 2 Port 1 L = 1 036nH C = 249 fF C Port 2 Standard 3 Port 1 L = 1 281nH C = 249 fF Port 2 Standard 4 Port 1 L = 1 493nH C = 249 fF Port 2 Standard 5 Figure D 2. The sc hematic of the first group example golden DUTs for S21 detection network. Port 1 L = 306pH C = 249 fF Port 2 Standard 6 R = 3 R = 500 C = 125 fF Port 1 L = 534pH C = 230 fF Port 2 Standard 7 R = 5 2 R = 450 C = 145 fF Port 1 L = 1 036nH C = 210 fF Port 2 R = 10. 2 R = 400 C = 165 fF Port 1 L = 1 281nH C = 190 fF Port 2 Standard 9 R = 12. 6 R = 350 C = 185 fF Port 1 L = 1 493nH C = 170 fF Port 2 R = 14. 6 R = 300 C = 205 fF Standard 8 Standard 10 Figure D 3. The schematic of the second group example golden DUTs for S21 detection network. PAGE 184 184 APPENDIX E SENSITIVITY ANALYSIS OF THE CALIBRATION METHODS IN CHAPTER 4 E. 1 Sensitivity Analysis of Calibrations for Embedded S11 Detection Network When demonstrating t he Type II and Type III calibration methods in C hapter 4 for the embedded S11 detection network, it is assumed that the exact S11 values of the go lden DUTs, used as calibration standards, are known. However, since these standards might also have some variation after being fabricated assuming that their S11 values are exact ly as designed is not practical. Hence, in order to know how the performance of the calibration methods degrade in the face of deviated golden DUTs, the sensitivity issue of the Type I I and Type I II calibration methods is studied in this section assuming that there is 1%, 2%, and 3 % deviation between the designed and fabricated S11 values of the golden standards. E.1.1 Type II Calibration Method As presented in S ubsection 4.2.2, Type II calibration method requires three golden DUTs and utilizes Equation 4 3 to perform the calibration where the S11 values of the golden DUTs are used Hence, there is one variable, the S11, for each golden DUT Since three golden DUTs are required, there are three variables for the whole calibration set. By adopting the concept of design of experiments, each variable is given three possibilities of val ue assignment, which are low, nominal, and high deviations F or example, for a 1% -deviation analysis, each variable should take turns to be assigned deviations of 1%, 0%, and 1%. Therefore, the whole set of analysis should contain 27 kinds of deviation co mbinations, including the combination where the three variables are all assigned with nominal values. By using Equation 3 3 to calculate the error between two S parameters, Figure E 1 shows the worst case of 1% deviation analysis. The result s show that the case with the maximal error percentage happens in the same combination as that with the minimal bandwidth. As can be PAGE 185 185 seen, with 1% deviation allowance on the golden standards, the bandwidth still covers the wh ole 15GHz range. The detailed analysis result s are summarized in Table E 1. Figure E 1. Sensitivity analysis result s of Type II calibration method with 1% deviation Figure E 2 shows the worst case of 2%-deviation analysis. The results show that the case with the maximal error percentage happens i n the same combination as that with the minimal bandwidth. As can be seen, with 2% deviation allowance on the golden standards, the bandwidth no longer covers the whole 15 GHz range and the maximal error percentage can be as high as 5.76%. The detailed ana lysis results are summarized in Table E 1. Figure E 2. Sensitivity analysis result s of Type II calibration method with 2% deviation Figure E 3 shows the worst case s of 3 % -deviation analysis. The results show that the case with the maximal error percent age and the case with the minimal bandwidth happen in different PAGE 186 186 combinations. As can be seen, with 3% devi ation allowance on the golden standards, the bandwidth becomes even narrower than before a nd the maximal error percentage can be as high as 9.49%. The detailed analysis resu lts are summarized in Table E-1. Figure E-3. Sensitivity analysis results of T ype II calibration method with 3% deviation. Table E-1. Sensitivity analysis result s of Type II calibration method for S11 detection network Standards dev. Max error Dev. Comb ination min BW Dev. Combination 1% 2.6404% DUT1 S11 + 1% DUT2 S11 1% DUT3 S11 + 1% 15 GHz DUT1 S11 + 1% DUT2 S11 1% DUT3 S11 + 1% 2% 5.7584% DUT1 S11 + 2% DUT2 S11 2% DUT3 S11 + 2% 7.4627 GHz DUT1 S11 + 2% DUT2 S11 2% DUT3 S11 + 2% 3% 9.4925% DUT1 S11 + 3% DUT2 S11 3% DUT3 S11 + 3% 1.1194 GHz DUT1 S11 3% DUT2 S11 + 3% DUT3 S11 3% E.1.2 Type III Calibration Method As presented in Subsection 4.2.3, Type III calibration method requires two golden DUTs and utilizes Equation 4-6 to pe rform the calibration, where the S11 values of the golden DUTs are used. Hence, there is one variable, the S11, for each golden DUT. Since two golden DUTs are required, there are two variables for the whole calibration set. By using the same assignment rules given in Subsection E.1.1, the whole set of analysis should contain 9 kinds of deviation PAGE 187 187 combinations, including the combination where the two variables are all assigned with nominal values. Figure E 4 shows the worst case of 1%-deviation analysis. The results show that the case with the maximal error percentage happens in the same combination as that with the minimal bandwidth. As can be seen, with 1% deviation allowance on the golden standards, the bandwidth still covers the whole 15 GHz range. The detailed analysis results are summarized in Table E 2 Figure E 4. Sensitivity analysis result s of Type III calibration method with 1% deviation Figure E 5 shows the worst cases of 2%-deviation analysis. The results show that the case with the maximal error percentage and the case with the minimal bandwidth happen in different combinations. As can be seen, with 2% deviation allowance on the golden standards, the bandwidth no longer covers the whole 15 GHz range and the maximal error percenta ge can be as high as 3.98%. The detailed analysis results are summarized in Table E 2. Figure E 6 shows the worst cases of 3%-deviation analysis. The results show that the case with the maximal error percentage happens in the same combination as that with the minimal bandwidth. As can be seen, with 3% deviation allowance on the golden standards, the bandwidth becomes even narrower than before and the maximal error percentage can be as high as 5.17%. The detailed analysis results are summarized in Table E 2. PAGE 188 188 Figure E 5. Sensitivity analysis result s of Type III calibration method with 2% deviation Figure E 6. Sensitivity analysis result s of Type III calibration method with 3% deviation Table E 2. Sensitivity analysis results of Type III calibration me thod for S11 detection network Standards dev. Max error Dev. Combination min BW Dev. Combination 1% 2. 7971 % DUT1 S 11 1% DUT2 S11 + 1% 15 GHz DUT1 S 11 + 1% DUT2 S11 1% 2% 3.9814 % DUT1 S 11 2% DUT2 S11 + 2% 12.8358 GHz DUT1 S 11 + 2% DUT2 S11 2% 3% 5.1662 % DUT1 S 11 3% DUT2 S11 + 3% 1.9403 GHz DUT1 S 11 3% DUT2 S11 + 3% E.2 Sensitivity Analysis of Calibration for Embedded S21 Detection Network When demonstrating the calibration method in C hapter 4 for the embedded S21 detection network, it is as sumed that the exact values of the S21, S11, and S22 of the golden DUTs, used as PAGE 189 189 calibration standards, are known. However, since these standards might also have some variation after being fabricated, assuming their S -parameter values unchanged is not prac tical. Hence, s imilar sensitivity analysis as that given in Appendix E.1 is performed in this section for the calibration method of the S21 detection network As presented in S ection 4.3, the calibration method for the S21 detection network requires at lea st five golden DUTs and utilizes Equation 4 1 3 to perform the calibration, where the values of S21, S11, and S22 of the golden DUTs are used. According to analysis the calibration method for the S21 detection network is found to be more sensitive to the s tandard s deviation than those for the S11 detection network. In addition, it is discovered that t he square term of S21_DUT2 in Equation 4 13 dominates the sensitivity of the whole calibration. This discovery stands to reason because any deviation in S21_D UT2 will get magnified through the second-order term which does not exist in the calibration equations for the S11 det ection network in Equations 4 3 and 4 6 To alleviate such a high sensitivity caused by deviation in the square term of S21_DUT2 in Equat ion 4 13, it may be a good idea to require that the golden DUTs have the minimal deviation in their S21 values when their b e ing manufactured. By assuming that the deviation in S21 for each golden DUT is zero the analysis results show that the sensitivity can be alleviated by approximately ten times. Since for a local area on a chip, the deviation of devices parameters due to process variation should have similar trend s it is reasonable to assume that the deviations in S21 of each golden DUT are the same. Similarly, the deviations in S11 and S22 of each golden DUT are assumed to be the same. By these assumption s there remain only 3 variables for the whole calibration set and the sensitivity can be greatly reduced By adopting the concept of design of expe riments, where each variable is given assignments of low, nominal, and high deviations, the PAGE 190 190 whole set of analysis should contain 27 kinds of deviation combinations, including the combination where the three variables are all assigned with nominal values. By using Equation 3 3 to calculate the error between two S parameters, Figure E 7 Figure E 8 and Figure E 9 show the worst case of 1% -deviation, 2% deviation, and 3%-deviation analysis, respectively. As can be seen, the maximal error percentage increases and the minimal bandwidth decreases as the deviation in the S -parameters of DUTs increases. The detailed analysis results are summarized in Table E 3 Figure E 7 Sensitivity analysis result s of the calibration method for S21 detection network with 1 % d eviation Figure E 8 Sensitivity analysis result s of the calibration method for S21 detection network with 2 % deviation PAGE 191 191 Figure E 9 Sensitivity analysis result s of the calibration method for S21 detection network with 3 % deviation Table E 3 Sens itivity analysis results of the calibration method for S2 1 detection network Standards dev. Max error Dev. Combination min BW Dev. Combination 1% 4.7083 % S 21 1% 11.9403 GHz S 21 1% S 1 1 1% S 1 1 1% S 22 1% S 22 1% 2% 5.6923 % S 2 1 2 % 10.597 GHz S 2 1 2 % S 1 1 2 % S 1 1 2 % S 22 2 % S 22 2 % 3% 6.8265 % S 2 1 3 % 0.8955 GHz S 2 1 3 % S 1 1 3 % S 1 1 0% S 22 3 % S 22 3 % PAGE 192 192 LIST OF REFERENCES [1] HP 8510C+24D, Student guide for basic network measurements using the hp 8510 network analyzer system, July 1991. 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Binchun, Linearization of diode detector characteristics, IEEE M77 -S Dig., pp. 265 267, June 1987. PAGE 195 195 BIOGRAPHICAL SKETCH Ming-Che Lee was born in Taipei, Taiwan, in August 1978. He received his Bachelor of Science and Master of Science in electrical en gineering from National Tsing Hua University, Hsinchu, Taiwan in 2000 and 2002, respectivel y. In August 2005, he joined the MixedSignal/RFIC Embedded Test Research Group and be gan working on the doctorate degree in the Department of Electrical and Comp uter Engineering at the Univers ity of Florida, Gainesville, Florida. He received his Ph.D. from the University of Florida in May 2010. For his Ph.D. dissertation research, he mainly focused on the implementation of embedded S-parameter measurement. |