1 CARBON NANOTUBE SYNTHESIS ON CMOS SUBSTRATE VIA LOCALIZED RESISTIVE HEATING By Y ING Z HOU A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE UNIVERSITY OF FLORIDA 2009
2 2009 Y ing Zhou
3 To my parents and my dear loving husband who have always given me the greatest l ove, encouragement, and support
4 ACKNOWLEDGMENTS First I have to thank my advisor, Dr. Huikai Xie, for his academic guidance, support and encouragement. I s tarted working for Dr. Xie when I came to UF in the f all of 2007. From the first weekly research report to the first group presentation, from the layout to the fabrication, from the first conference abstract to the first journal manuscript, Dr. Xie taught me a lot and I enjoyed working on the project. I would also like to thank my other two committee members, Dr. Ant Ural and Dr. Jing Guo for their help and guidance, and my project partner Jason Lee Johnson. Jason and I have been working together for two years, and he did a lot for this project. I owe a lot of gratitude to our BML lab members, especially Kemiao Jia, Lei Wu and Sagnik Pal Kemiao and Lei train ed me to do the fabrication when I came to UF. At that time, I had little hand on experience. Sagnik and I discussed the micro heater reliability issues together and I appreciate the time that he gave for discussion. I would like to thank Sarah Maley from A ir Force for taking the thermal imaging. The data obtained from those images are very helpful for temperature distribution investigation. I would also like to thank NanoHoldings LLC for supporting this project and MOSIS Educational Program for offering us a free CMOS foundry service.
5 TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................................... 4 LIST OF TABLES ................................................................................................................................ 7 LIS T OF FIGURES .............................................................................................................................. 8 ABSTRACT ........................................................................................................................................ 10 CHAPTER 1 INTRODUCTION ....................................................................................................................... 12 1.1 Carbon Nanotubes ................................................................................................................. 13 1.2 CNT Based Devices ............................................................................................................. 16 1.3 CMOS -CNT Hybrid Devices ............................................................................................... 20 1.4 Thesis Outline ....................................................................................................................... 22 2 FROM MATERIAL TO INTEGRATED MICROSYSTEMS: CARBON NANOTUBES SYNTHESIS AND ASSEMBLY .................................................................... 23 2.1 Carbon Nanotubes Synthesis ................................................................................................ 23 2.2 CMOS -CNT Integration Challenges and Discussion ......................................................... 25 2.3 Synthesis Based on Localized Heating ................................................................................ 28 2.4 Summary................................................................................................................................ 30 3 THE INTEGRATION OF CNTS ON MOCK-CMOS SUBSTRATE USING LOCALIZED RESISTIVE HEATING ..................................................................................... 32 3.1 Microheaters Design ............................................................................................................. 32 3.2 Device Fabrication ................................................................................................................ 34 3.3 Microheater Characterization ............................................................................................... 37 3.3.1 Maximum Temperature Estimation .......................................................................... 37 3.3.2 Heating Experiment .................................................................................................... 39 3.3.3 Hi gh Temperature Reliability .................................................................................... 40 3.3.4 Local Temperature Distribution ................................................................................ 43 3.4 Room Temperature Carbon Nanotube Synthesis ................................................................ 45 3.5 Characterization of Carbon Nanotubes ................................................................................ 47 3.6 Summary................................................................................................................................ 52 4 THE INTEGRA TION OF CARBON NANOTUBES ON CMOS SUBSTRATE ................. 53 4.1 Integration Principles and Device Design ........................................................................... 54 4.2 Device Fabrication and Charact erization ............................................................................ 60 4.3 On-chip Synthesis of Carbon Nanotubes ............................................................................ 67
6 4.4 Characterization of Carbon Nanotubes and Circuit Evaluations ....................................... 68 4.5 Summary................................................................................................................................ 72 5 FUTURE WORK ........................................................................................................................ 74 LIST OF REFERENCES ................................................................................................................... 76 BIOGRAPHICAL SKETCH ............................................................................................................. 87
7 LIST OF TABLES Table page 2 1 MOSIS AMI C5 Technology ................................................................................................ 60
8 LIST OF FIGURES Figure page 1 1 Schematic structure of single -walled carbon nanotube and multi -walled carbon nanotube with typical dimensions of length, width, and layer spacing in MWNTs. ......... 13 1 2 Honeycomb structure of a planar graphene sheet ................................................................ 14 1 3 The interplay of electrical, mechanical an d optical properties of carbon nanotubes and possible corresponding CNT based transducers. .......................................................... 17 1 4 The structure of NRAM at on and off states. ....................................................................... 21 2 1 Circuit schematic of the decoder consisting of NMOS and single -walled carbon nanotubes ................................................................................................................................ 26 2 2 Process flow to integrate MWNT interconnects on CMOS substrate. SEM image of one MWNT interconnect (wire and via). .............................................................................. 27 2 3 SEM images of vertically aligned CNFs grown by PECVD deposition at 500C, 270C, and 120C.. ................................................................................................................ 28 2 4 Fabrication process and localized heating concept. ............................................................. 29 2 5 Schematic of the cross -sectional layout of the chip.. ........................................................... 30 3 1 Structural demonstration of mock CMOS platinum microheater ....................................... 33 3 2 Cross -sectional view of the proposed process flow. PECVD SiO2 deposition. Pt sputtering and lift-off to form heater an d pads ..................................................................... 35 3 3 SEM pictures of fabricated microheaters .............................................................................. 36 3 4 I-V characterization of microheater. Temperature estimated based on resistance change. .................................................................................................................................... 38 3 5 Microscopic images under applied voltages of 2.28 V, 2.62 V, and 3.00 V, respectively. ............................................................................................................................ 40 3 6 Embedde d straight line Pt microheater I -V characteristics ............................................... 41 3 7 The formation and growth of holes in the 100 -nm Pt/10 nm Ti thin film. After 0 hour at 900C. After 2 hours at 900C. After 6 hours at 900C. After 9 hours at 900C. ........ 43 3 8 Thermal imaging of Design 1 Design 2 and Design3 ....................................................... 44 3 9 Dense film of CNTs over micr o -hotplate surface (Design 1) ............................................. 45
9 3 10 Localized synthesis of CNTs suspended across the trench, showing good CNT alignment ................................................................................................................................ 46 3 1 1 I-V characteristics of SWNTs contacted by Pt electrode. It was measured on the same device shown in Fig. 3 10c .......................................................................................... 48 3 12 Demonstration of the types of nanotube nanoto -micro contacts ....................................... 49 3 13 I-V characteristics of CNTs contacted by Pt electrode ........................................................ 50 3 14 Response curve to oxygen vs. time ....................................................................................... 51 3 15 Measured resistance vs. temperature relationship. ............................................................... 51 4 1 The 3 D schematic showing the concept of the CMOS integrated CNTs .......................... 55 4 2 A typical heater design with stripe -shaped resistor .............................................................. 57 4 3 Schematic layouts showing 10 20 with multiple tips as landing walls, and a microheater with opposing sharp tips ............ 58 4 4 Schematic layouts of the chip, including test circuits and 13 embedded microheaters ..... 59 4 5 Mastless post CMOS MEMS fabrication process flow: CMOS chip from foundry. SiO2 dry etch. Al etch. ........................................................................................................... 61 4 6 The CMOS chip photograph (1.5 1.5 mm2) after foundry process ................................. 63 4 7 I-V characterization 20 ........................................................... 66 4 8 Localized synthesis of carbon nanotubes grown from the 3 3 and the 6 6 to the polysilicon tip/wall ................................................................................................................. 68 4 9 I-V characteristics of the as -grown CNTs. The I -V curve is measured between two polysilicon microstructures contacting the CNTs. ............................................................... 69 4 10 DC electrical characteristics of single transistors before and after CNT growth ............... 69 4 11 SEM images showing the catalyst layers on silicon dioxide surface pl atinum microheater surface, and polysilicon microheater surface .................................................. 71
10 Abstract of Thesis Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for t he Degree of Master of Science CARBON NANOTUBE SYNTHESIS ON CMOS SUBSTRATE VIA LOCALIZED RESISTIVE HEATING By Ying Zhou August 2009 Chair: Huikai Xie Major: Electrical and Computer Engineering Since their discovery, the unique properties of c arbon nano tubes (CNTs) have drawn great attention, and a lot of applications have been demonstrated, such as CNT based transistors, circuitry interconnection and different types of sensors. Although CNTs exhibit extraordinary performance, fabricating CNTs with preci se control at a very large scale integration to constitute a complete component library is still very difficult. Therefore, substantial efforts have been made to develop CMOS CNT hybrid devices that can take the advantages of both the maturity of the CMOS technology and the unique properties of CNTs. To fabricate such hybrid devices, the CMOS CNT integration faces several challenges due to the incompatibility between the CNT growth process and the post CMOS processing. Among several proposed methods, synthesis based on localized heating is one of the most promising solutions, which satisfies both the high temperature requirement for CNT growth and the low temperature limitation of post CMOS processing. The growth is performed in a room -temperature chamber, and t he resistive heating of the microheater provides the local high temperature to activate the growth just on the microstructure. This localized heating approach solves the temperature incompatibility and eliminates the postgrowth assembly steps. But a simple and reliable fabrication process has not been developed for CMOS CNT integration.
11 The novel monolithic CMOS CNT integration approach proposed in this work incorporates the localized heating concept and maskless post CMOS MEMS fabrication process to solve the remaining problems It uses the gate polysilicon to form the heaters for localized heating and use the maskless post CMOS fabrication to form micro cavities for thermal isolation. The polysilicon microheaters are fabricated with the gates of the transistors in the foundry processes, so they can be simultaneously interconnected to each other without any need of post growth clamping or connection steps. To accomplish this monolithic integration, mock CMOS substrates are first investigated for the pr ocess development and basic conceptual verification. Three types of platinum microheaters have been designed, fabricated and characterized, demonstrating an ideal temperature distribution profile. CNTs have been locally synthesized on Pt microheaters and t hey show excellent alignment and reliable ohmic contacts with Pt electrodes Then, CMOS chip s with testing circuits and embedded polysilicon microheaters ha ve been designed and fabricated through MOSIS foundry processes followed by the microheater release using the proposed maskless post CMOS fabrication process. Room temperature localized synthesis of CNTs on CMOS substrates has been realized, and the electrical characteristics of the neighboring CMOS transistors have been proven unchanged after the CNT s ynthesis, indicating a successful monolithic CMOS -CNT integration.
12 CHAPTER 1 INTRODUCTION Carbon Nanotubes (CNTs) have drawn great interest for their unique thermal, mechanical, electrical, chemical and optical properties in recent years Since their discovery in 1991 by Iijima , various CNT based applications have been demonstrated, ranging from composite materials, molecular electronics, nano -prob es and sensors, biomedical sensing to energy storage and many other s T he demand for carbon nanotubes is increas ing rapidly. A decade ago, carbon nanotubes were very expensive and sold in small quantities for research purpose. However, the massive product ion has driven price down substantially to below $100 per kilogram for multi -walled carbon nanotubes , making them attractive for various comm ercial applications such as CNT composite materials that can be added in polymers to improve their performance. After a moderate annual growth rate of 40% till 2004 2005, the global CNTs market is expected to soar, exceed ing $1.9 billion by 2010 [3, 4] Electronics, a utomotive and a erospace/ d efen s e industries are three major end use rs. Among them, electronics devices are forecasted to be the largest end use sector in terms of dollar value, and composite materials in automotive industr y to be the largest sector in terms of volumes in the next few years . Among intensive explorations on CNTs, this thesis is focuse d on the development of a simple and reliable method of integrating CNTs with commercial foundry CMOS circuits The goal of this chapter is to give readers an introduction. First a brief description of CNT structure will be given. Second, special properties of CNTs and the corresponding applications will be discussed. Then, the emerging CMOS CNT hybrid integration efforts wil l be presented. Finally, a thesis outline describing the content of each chapter wi ll be given.
13 1.1 Carbon Nanotubes Carbon nanotubes can be considered as the result of rolling up honeycomb graphe n e sheets into hollow carbon cylinders As shown in F ig 1 1 , t here are two basic types: single -walled carbon nanotubes (SWNTs) which consist of a single graphen e sheet, and m ulti -walled carbon nanotubes (MWNTs), which are composed of several such sheets with one cylinder inside another Figure 1 1 Schematic structur e of A) SWNT and B) MWNT with typical dimensions of length, width, and layer spacing in MWNT s . The nanotube properties are extremely structure -sensitive, strongly dependent on the nanotube diameter and chirality. By unwrapping a nanotube along its axis the chirality can be determined from the planar graphene sheet as shown in Fig. 1 2 A . The two dashed tube axes coincide with each other. One carbon bonding site on the left tube axis is chosen as the origin point (0, 0) an d the point C on the right tube axis corresponds to the same point on the nanotube. The sheet is rolled until these two points coincide to form a SWNT. The chiral vector C is formed by connecting the origin point (0, 0) to the poi nt C, and it is specified by a pair of integers (n, m) that relate C to two unit vectors 1a and 2a ( C = n 1a + m 2a ) . The unit vectors 1a and 2a are expressed as: A ) B )
14 Figure 1 2 A ) Honeycomb structure of a planar graphe n e sheet A carbon nanotube indicated by indices (11, 7) is formed by rolling up a single graphe n e sheet along the wrapping vector C such that the origin (0, 0) coincides with point C . Some SWNTs with different chiralities: B) armchair structure C) zigza g struct ure and D) chiral structure . 3 (,), 22 a a 1a 3 (,) 22 a a 2a (1 1) in which a is the lattice constant of graphene sheet n and m are the nanotube indices obtained along vectors 1a and 2a, respectively. As shown in Fig. 1 2 A the point (11,0) is in the direction of 1a and its length is 11 times of the lattice constant so n equals to 11 and m equals to 0. A ) B ) C ) D )
15 Similarly, we can obtain the value of other vectors such as (0,7) and (11,7). The chiral vector C is equivalent to the circumference of the nanotubes circular cross section. Thus the diameter of such tubes can be calculated as: 22 anmnm d (1 2 ) The typical diameter for single -walled carbon nanotube s is 1 1.5 nm . In contrast m ulti walled nanotubes have different number s of walls and different separation distance s between the graphene layers so their diameters vary typically from 5 nm to hundreds of nanometers  The chiral angle as shown in Fig. 1 2 A is defined as: 1 22 12 2 Ca nm cos Ca nmnm (1 3 ) If n and m are equal (Fig. 1 2 B), the nanotube is called armchair with a chiral angle of 3 0. If m equals zero (Fig. 1 2 C), t he tube is called zigzag with a chiral angle of 0. All other nanotubes having a configuration with 0 < | | < 30 are of chiral type (Fig. 1 2 D ) [7, 8] The electronic properties of a nanotube depend on its atomic structure. It is theoretically predicted that the armchair nanotubes are met allic with the bands cross ing the Fermi level  For all other tubes, they can either be metallic or semiconducting I f n m = 3N (where N is an integer), such nanotubes are expected to be metallic. Otherw ise, if ( n m ) is not a multiple of 3 such nanotubes are semiconducting with an energy gap of the order of approximately 0.5 eV . For semiconducting nanotubes with the same chirality t h e energy band gap is only dependent on the tube diameter, with an inversely proportional relation as: 02cc gapa E d (1 4 ) in which 0 is the C -C tight -binding overlap energy, cca is the nearest neighbor C C distance (0.142 nm) and d is the diameter . T he theoretical analysis discussed so far regarding the
16 chiral angle and the energy band gap is only applicable to SWNTs. The analysis is more complicated f or MWNTs due to th e different number of walls and different structure s of each layer. As we can see from the above discussion, the electr ical properties of nanotubes are strong ly dependent on the nanotube diameter and chirality. The v ariegated atomic structures bring perhap s the most extreme diversity and richness among nanomaterials. T he interplay of electrical, mechanical, and chemical properties of nanotubes further promises a wide range of applications. V arious CNT -based devices will be discussed in the next section 1. 2 CNT -Based Devices Compared to SWNTs MWNTs are generally easier to produce at large scale and thus less expensive R evenues generated from MWNTs were dominant for l ast few years, with an est imated market of $290 million in 2006 . S ince MWNTs are usual l y used as composite materials for their high thermal conductivity and to add mechanical s trength and electrical conductivity to polymer s in products such as vehicle chassis and sports goods , t heir wide variations in length, width and number of walls are not concerns at present. However, more advanced uses of CNTs as functional devices demand SWNTs with specific types This is an area that is growing rapidly and provides the stage for nanotubes to show their fascinating unique talents C. Hierold et al. summarized possible CNT based electrical, mechanical and optical transducers and their applications in the matrix as shown in Fig. 1 3  D ifferent inpu t s such as electrical, mechanical and optical signals are listed in the first column of the matrix and different output signals are listed in the upper row Each crisscrossed cell indicates the corresponding transduction principle converting signal in one domain to another.
17 Figure 1 3 The interplay of electrical, mechanical and optical properties of carbon nanotubes and possible corresponding CNT based t ransducers  The upper lef t cell (electrical -electrical) represents the nano electronic device category, and carbon nanotube field effect transistors (CNFETs) are the key focus of ongoing studies. Due to the fundamental scaling limits of traditional silicon -based integrated circuit s [13, 14] molecular electronics as one of the new miniaturization strategies has drawn great attention. The remarkable electrical properti es of carbon nanotubes, such as a large current density exceeding 109 A/cm2  and a high-mobility of 9000 cm2/Vs  make them ideal candidates for novel molecular nanoelectronics, which has been intensively explored in recent years Carbon nanotube field effect transistors were first demonstrated using a back -gate configuration with one semiconducting SWNT connected to two metal electrodes and Si substrate as a back -gate [17, 18] The as -prepared semiconducting SWNT s with metal electrodes always exhibit p type field effect transistor (FET) behavior s at room temperature : n egative gate voltages lead to an on state of the CNFETs as a result of an a ccumulation of holes and an increasing conductance,
18 whereas positive gate voltages deplete the holes and lower the conductance leading to an insulating off state Under the electrostatic gating the electrical conductance can var y by more than 5 orders of magnitude  This hole doping characteristic has been reported by many groups [17 19] and its mechanism was found to be attributed to the c harge transfer between SWNTs and adsorbed oxygen molecules [20 23] known as chemical gating effect After removing the oxygen, the e xtrinsically induced p type FET behavior vanishes and t he nanotubes approaches an intrinsic semiconducting behavior  The complementary n type CNFETs can be realized via c hemical doping methods, such as charge transfer doping with alkali metals and SWNT sidewall functionalization with polymers [24 27] Following the successful demonstrati on of basic individual CN FET components, several r esearch groups stepped towards the integration of such nanotube FETs onto the same chip to form logic circuits ranging from inverters, NAND and NOR gates to ac ring oscillators [28, 29] Semiconducting CNFETs promise very fast (THz) transistors  and metallic CNTs with excellent electrical conductivity may enable the realization of electronic systems where both active components and interconnection use the same material. However, so far large scale integration with predictable performance and precise control has not been realized yet, primarily due to the la ck of reliable ways to directly produce large amounts of CNTs with identical desired type. The upper center and center left cells cover the conversion between electrical signal and mechanical deformation, and its potential applications as electromechanical transducers. Tombler et al.  studied the effects of mechanical deformations on the electrical properties of carbon nantubes by the AFM tip pushing experiment and demonstrated that i ncreased bending leads to decreased conductance by more than two orders of magnitude Cao et a l.  reported piezoresistive gauge factor s 00(/)/(/) RRll as much as 600 to 1000 under axial strains,
19 compared to 200 of commonly used p -doped silicon  effects resulting from the increased curvature produced by highangle bending are proposed to be the cause of the conductance decrease  Based on the remarkable and reversible electrical response to a mechanical load, a variety of different ele ctromechanical sensors have been demonstrated, some of which are listed in the center left cell. Electromechanical actuation devices (upper center) operate in the opposite way : it utilizes the mechanical responses of carbon nanotubes to electrical signal s based on electrostatic  and piezo electric effect [36, 37] Applications include nano relays, nano tweezers and CNT based mechanical memory cells etc. [38 40] P hotoelectronic transducers are based on photo n emission and absorption. Illuminated nanotube p -n junctions under bias can convert incident photon energy into electric al energy. Curr ent -voltage characteristics and power efficiency are functions of photon energy and the energy conversion rate increases with decrease of nanotube diameter s [41, 42] Another important category which is not listed in Fig. 1 3 is the CN T -based chemical/bio sensors. Although CNTs are highly stable and chemically inert the electrical properties of semiconducting SWNT s (S SWNT) are found to be extremely sensitive to charge transfer between SWNTs and molecules adsorbed via non-covalent forces [8, 20] This serves as the basis for chemical sensors. Owing to their unique structure (nanometer range diameters and all on -surface atoms), nanotubes are suitable for miniaturization and chem ical coating for high selectivity. Such sensors exhibit faster response, smaller size, substantially higher sensitivity and no need to heat, but slow er recovery time to gases, c ompared to existing metal -oxide -based gas sensors It has been reported that t he electrical resistances of S -SWNTs changed dramatically by several orders of magnitude when exposed to 200 ppm NO2 and 1% NH3 . The sensing mechanism is s imilar to the way that the conductance of silicon-based transistors being
20 modulated by doping n or p -type impurities ( such as boron and phosphorus). NO2 is a strong oxidizer with an unpaired electron, and can be regarded as p -type impurity. When expos ed electron -withdrawing NO2 molecules increase the hole carriers in the as -grown p type SWNT s leading to the modulation of the Fermi level in the semiconducting t ubes towards valence band, and thus a higher conductivity is induced  In the opposite way, NH3 has a lone electron pair to donate and will shift the Fermi level away from the valence band, resulting in hole depletion and reduced conductance The S -SWNT based chemical sens ors is applicable to other molecul e s with el ectron -donating or withdrawing capabilities, such as oxygen and polymers [21, 24, 43] Surface modification and functionalization, along with other methods, allow nanotubes to inter act with specific biochemical species and can be used for biomedical applications such as protein -nanotube sensors, DNA detection sensors and active biomarkers [44 46] 1.3 CMOS -CNT Hybrid Devices Although CNTs have been explored for variou s applications and exhibit extraordinary performance as discusse d in the previous section, fabricating CNTs with precise position chirality and performance control at a very large scale integration (VLSI) to constitute the necessary library of components (transistors, diodes, resistors, capacitor, etc.) on a single substrate has not been realized Meanwhile, owing to the maturity of the standard silicon technology and the unique properties of CNTs, substantial eff or ts have been made on the develop ment of CMOS CNT hybrid integration technology that take s the advantages of both CMOS and CNTs. For nanoelectronics applications high-performance carbon nanotube field effect transistors can be integrated with conventional CMOS circuits that can provide power reg ulation, load capacitors, and other peripheral devices. The CNT memory device is one of the numer ous examples Since t he further scaling of silicon based memories is expected to approach the limits
21 in the near future as the capacitor charge and writing/era sing voltages cannot be scaled down  a highly scalable hybrid CMOS -molecular non -volatile memor y has been widely explored where CNT based memories are connected to the readout CMOS logic circuitry [48, 49] A nanotube random access memory (NRAM) used in  is shown in Fig. 1 4 It is a non -volatile, high -density, high-speed and low -power nanomemory developed by the company Nantero and it is claimed to be a universal me mory chip that can replace DRAM, SRAM, flash memory, and ultimately hard disk storage [49, 50] Figure 1 4 The structure of NRAM at A) on and B ) off states  For sensing applications, research groups have investigated the use of CMOS VLSI as advanced system control and powerful signal processing for CNT sensor output to achieve so -called smart sensors. Such CMOS interface architectures for resistive sensors can be used to regulate the sensing temperature  widen the dynamic range  imp rove the measurement accuracy  and provide multiple readout channels to realize electronically addressable nanotube chemical sensor arrays  V a rious sensors based on such CMOS -CNT hybrid systems ha ve been demonstrated [56 58] Other attempts have been made to use MWNTs as CMOS interconnect for high frequency applications  apply CNT -based nano -electromechanical switch es for leakage reduction in CMOS logic and memory circuits  to name a few. B ) Interconnects CNT ribbons Electrode A )
22 1. 4 Thesis Outline As discussed in Sections 1.3, the integration of carbon nanotubes with microelectronics can make use of advantages of both. However, owing to the immature nanofabrication techniqu es, most of the CMOS CNT systems have been realized either by a two -chip solution or complicated CNT manipulations. Integration challenges, such as temperature incompatibility, will be discussed in detail in Chapter 2. The objective of this thesis is to de velop a simple and scalable monolithic CMOS CNT integration technique and our solution will be presented in Chapter 3 and 4. Here we just give an outline of this thesis. There are five chapters in this thesis. The first chapter gives an introduction and motivation of this project. Chapter 2 first presents the CNT growth mechanism and the synthesis methods. Then, the monolithic CMOS -CNT integration technique using localized resistive heating, as well as other integration methods, will be discussed and comp ared in detail. In Chapter 3, three microheater designs will be presented and analyzed by thermal imaging L ocalized synthesis of CNTs on this mock CMOS substrate will be presented to demonstrate the concept of resistive heating integration Chapter 4 will focus on the monolithic CMOS CNT integration. First, the device design including test circuits and embedded microheaters within a single chip, and some design concerns will be presented and discussed Then, a novel maskless post -CMOS surface micromachini ng processing will be introduced, followed by the on-chip synthesis and after -growth CNT characterization and circuit evaluations. Chapter 5 will discuss the future work on this research topic.
23 CHAPTER 2 F ROM MATERIAL TO INTEGRAT ED MICROSYSTEMS: CAR BON NANOTUBES SYNTHESIS AND ASSEMB LY Carbon nanotubes are the basic building blocks. This chapter will discuss the CNT growth mechanism and the synthesis methods first Then, in order for CMOS -CNT hybrid devices to be effi ciently and reliably functional a robust CMOS CNT integration process that is simple and compatible with the mainstream foundry CMOS processes is of vital importance. Several integration methods have been developed and will be discussed in this chapter and the room -temperature localized synt hesis using J oule heating is of particular interest. 2.1 Carbon Nanotubes Synthesis The mechanism of carbon nanotube formation is not completely understood Although great efforts have been made to investigate the growth mechanism, it is still shrouded in controversy. Based on transmission electron microscope (TEM) observation, Yasuda et al. proposed that CNT growt h starts with rapid formation of rodlike carbons, followed by slow graphitization of wall s and formation of hollow structure s inside the rods . There are three main methods for carbon nanotubes synthesis : a rc -discharge [62 64] laser ablation [65 67] and ch emical vapor deposition (CVD) [68 71] The first two methods involve evaporation of solid-state carbon precursor s and condensation of carbon atoms to form nanotubes The high temperature invol ved (thous ands of degrees Celsius) ensures perfect annealing of defects, and hence these two methods produce high quality nanotubes However, they tend to pro duce a mixture of nanotubes and other byproducts such as catalytic metals, so the nanotubes must be selectiv ely separat ed from the byproducts This requires quite challeng ing post growth purification and manipulation. In contrast, the CVD method employs a hydrocarbon gas as the carbon source and involves heating metal catalyst s in a tube furnace to synthesi ze n anotubes. It is commonly accepted that
24 the synthesis process starts with hydrocarbon molecules adsorbed on the catalyst surface. T hen the carbon is decomposed from the hydrocarbon and diffu ses into the catalytic particles. Once the superaturation is reached, carbon s start to precipitate onto the particle s to form carbon tubes After that, nanotube s can grow by adding carbons at the top of the tube s if the particle s are weakly a dhered to the substrate surface. Nanotubes can also grow from the bottom if the p article s are strongly adhered  The former is called the tip growth model and the later is called the base-growth model. Compared to the arc -dis charge and laser ablation methods, CVD uses much lower synthesis temperature but it is still too high to directly grow on CMOS substrates In addition, CVD growth provides an opportunity to directly manufacture substantial quantities of individual carbon nanotubes. The diameter and location of the grown CNTs can be controlled via catalyst size  and catalyst patterning  while the orientation can be guided by an external electric field  Suitable catalysts that have been reported include Fe, Co, Mo, and Ni  Besides the CNT synthesis, electrical contacts need to be created for functional CNT based devices. It is reporte d that Molybdenum (Mo) electrodes form good ohmic contacts with nanotubes and show excellent conductivity after growth, with resistance ranging from 20 1 per tube  The electrical properties can be measured without any post -growth metallization processing. The low resistance, however, tends to incre ase over time, which might be due to the slight oxidation of the Mo in air. Other than that, e lectron -beam lithography is generally used to place post -growth electrodes. Several metals such as gold, titanium, tantalum and tungsten, have been investigated as possible electrode materials and palladium top -contacts are believed to be most promising 
25 2.2 C MOS -C NT Integration Challenges and Discussion As mentioned in Chapt er 1, a complete system with carbon nanotube s and microelectronic circuitry integrated on a single chip is needed to fully utilize the potential of nanotube s for emerging nanotechnology applications. This monolithic integration requires not only high -qu ality nanotube s but also a robust fabrication process that is simple reliable and compatible with standard CMOS foundry processes. Such CMOS -compatible integration process up t o now remains a challenge, primarily due to the material and temperature limita tions of CMOS technology [79, 80] As discussed in Section 2.1, thermal chemical vapor deposition has been widely use d to synthesize nanotubes. Research groups ha ve been working on growing CNTs directly on CMOS substrate using thermal CVD method. For example, Tseng et al. demonstrated for the first time, a process that monolithically integrates SW NTs with n -channel meta l oxide semiconductor (NMOS ) FET in a CVD furnace at 875C  However, the high synthesis temperature (typically 8 001000C for SWNT growth  ) would melt aluminum metallization layers and deteriorate the on -chip transistors. Ghavanini et al. have a ssessed the deterioration level of CMOS transistor s when subjected to CVD synth e sis techniques, and reported that one PMOS transistor lost its function after the thermal CVD treatment (610C, 22 min)  As a result, integrated circuits demonstrated by Tseng et al. using thermal CVD method, as shown in Fig. 2 1, can only consist of NMOS and use n+ polysilison and molybdenum as interconnect, which make it incompatible with CMOS VLSI foundry processes. To address thi s problem, one possible solution is to grow nanotubes at high temperature first and then transfer them to the desired positions on another substrate at low temperature. However, handling, maneuvering, and integrating these nanostructures with CMOS chips/wa fers
26 Figure 2 1. A ) Circuit schematic of the decoder consisting of NMOS and single -walled carbon nanotube s B ) Schematic of the cross -section of the decoder chip interconnected by phosphorus doped n+ polysiscon and molybdenu m  to form a complete system are very difficult. In the early stage, an atomic force microscope (AFM) tip was used to manipulat e and position the nanotubes into a predete rmined location under the guide of scanning electron microscope ( SEM ) imaging [83, 84] Although this nanorobotic manipulation realized precise control over both the type and location of CNTs, its low throughput becomes the bottleneck for large scale assembly. Oth er post -g r owth CNT assembly methods that have been demonstrated so far include surface functionalization  liquid -crystalline processing  dielectrophoresis (DEP) [87 90] and large scale transfer of aligned nanotu b es grown on quartz [91, 92] Among these methods, CMOS -CNT integration based on DEP assisted assembly technique has been reported, and a 1 GHz integrated circuit with CNT interconnects and silicon CMOS transistors has been demonstrated by Close et al.  The fabrication process flow and the assembled MWNT interconnect are shown in Fig. 2 2. The DEP process provides the capability of precisely positioning the n anotubes in a noncontact manner, which minimizes the parasitic capacitances and allows the circuits to operate above 1 GHz. However, to immobilize the DEP trapped CNTs in place and to improve the contact resistances between CNTs and the electrodes, metal c lamps have to be selectively A ) B )
27 deposited at both ends of the CNTs (Fig. 2 2 A step 3) The p rocess complexity and low yield (~ 8%, due to the MWNT DEP assembly limitation) are still the major concerns. Figure 2 2 A ) Process f low to integrate MWNT interconnects on CMOS substrate. B) SEM image of one M WNT interconnect (wire and via)  Alternatively, some other attempts have been made to develop low temperature growth using various CVD methods [93 95] Hofmann et al. reported vertically aligned carbon nanotubes g rown at temperature as low as 120C by plasma -enhanced chemical vapor deposition (PECVD )  However, the decrease in growth temperature jeopardize s both the quality and yield of the CNTs as evident from their p ublished results (shown in Fig. 2 3). The synthesized produc ts are actually defect -rich, less crystalline, bamboolike structured carbon nanofibers rather than MWNTs or SWNTs. A ) B )
28 Figure 2 3 SEM images of vertically aligned CNFs grown by PECVD deposit ion at A) 500C, B) 270C, and C) 120C [scale bars: A) and B ) 1 ) 500 nm]  2.3 Synthesis Based on Localized Heating To accommodate both the high temperature requirement (800 1000C) for highquality SWNT synthesis and the temperature li mitation of CMOS processing (< 450C), synthesis based on localized heating has drawn great interest. Englander et al. demonstrated, for the first time, the localized synthesis of silicon nanowires and carbon nanotubes based on microheater resistive heatin g  The fabrication processes and concepts are shown in Fig 2 4. Operated inside a room temperature chamber, the suspended microelectromechanical systems (MEMS) structures serve as microresistive heaters to provide high temperature at predefined reg ions for optimal nanotube growth, leaving the rest chip area at low temperature. Using the localized heating concept, direct integration of nanotubes at specific area can be potentially achieved in a CMOS compatible manner, and there is no need for additional assembly steps. Attracted by this promising technique, several research groups have followed up, and localized CNT growth on various MEMS structures has been demonstrated [97 99] However, the devices typically have large sizes and their fabrication processes are not fully compatible with the standard foundry CMOS processes. Although this concept has solved the temperature incompatibility problem between CNT synthesis and circuit protection, the fabrication processes of microheater structu res B) C ) A )
29 still have to be well designed to fit into standard CMOS foundry processes and the materials of microheaters have to be selected to meet the CMOS compatible criterion. Figure 2 4 Fabrication process and localized heat ing concept  The progress towards complete CMOS -CNT system has been made. On -chip growth using CMOS micro hotplates was later demonstrated by Haque et al.  As shown in Fig. 2 5, tungsten was used to fabricate both the micro -hotplates (as the thermal source) and interdigitated electrodes for nanotubes contacts MWNTs have been successfully synthesized on the membrane, and simultaneously connected to cir cuits through tungsten metallization. Although tungsten can survive the high temperature growth process, and has high connectivity and conductivity, Franklin et al. reported that no SWMTs were found to grow from catalyst particles on the tungsten electrode s, presumabl y due to the high catalytic activity of tungsten towards hydrocarbons  Further, although the monolithic integration has been achieved, the utili zation of tungsten, a refractory metal as interconnect metal is limited in foundry CMOS especially for mixed -signal CMOS processes. Tungsten is obviously not a good candidate as interconnect metal compared with aluminum and copper. Other than the materia l, this approach is limited to
30 SOI CMOS substrates, requires a complex backside bulk micromachining process, and it has low integration density. Figure 2 5 A ) Schematic of the cross -sectional layout of the chip. B) Optical image of the device top -view, showing the tungsten interdigitated electrodes on top of the membranes,  2. 4 Summary From the reviews in Chapter 1, we know that a monolithic CMOS -CNT integration is desirable to fully utilize the potential of nanotube s for emerging nanotechnology applications. However, based on the above discussion of the existing approaches, we have the understanding that although each method has its own merits, there is still a lack of integration technique that can meet all the requirements and realize complete compatibility with CMOS processes. To solve the problem, a simple and scalable monolithic CMOS -CNT integration technique using a novel maskless post -CMOS surface micromachining processing is proposed in this thesis. The approach is fully compatible with commercial foundry CMOS processes, and has no specific requirements on the type of me tallization layers and substrates. Since CMOS fabrication is costly and time -consuming even through the MPW service of MOSIS, mock CMOS substrates will be used for the process development and basic conceptual verification. Thus, in Chapter 3, a maskless p ost -CMOS MEMS process using inexpensive A ) B )
31 mock CMOS substrates will be developed to demonstrate the localized growth of SWNTs using platinum microheaters. Then Chapter 4 will present the demonstration of a novel room -temperature on -chip synthesis of carbon n antobues via localized resistive heating and maskless post -CMOS surface micromachining processing
32 CHAPTER 3 THE INTEGRATION OF C NTS ON MOCK-CMOS SUBSTRATE USING LOCALIZED RESISTIVE HEATING As discussed at the end of the previous c hapter, mock -CMOS substrates will be used to demonstrate the localized heating and CNT growth in a room -temperature chamber. Room temperature CNT growth on real CMOS substrates will be presented in Chapter 4 3.1 Microheaters Design Several different mater ials have been investigated as the electrode material for CVD growth of CNTs in the literature Metals with relatively low melting temperature, such as gold, become discontinuous as balling up during the high temperature growth process, while some other ca ndidates, such as Ti and Ta, tend to react with hydrogen and form volatile metal hydride at high temperature  In our experiment, platinum (Pt) ha s been chos en as the micro heater material due to its compatibility with C NT growth. Pt is a refractory metal with very high melting temperature. And i t has been widely used as contact electrodes in traditional CVD CNT synthesis procedures and demonstrated good contac t s with C NTs with resistance ranging from 10 . The local temperature distribution and the maximum temperature are the key parameters of the microheater structures. Since SWNT growth requires temperature as high as 800C, the resistivity of the heater, thermal isolation, thermal stresses and structural stiffness must be taken into consideration when design ing the microheaters A 3D model of the mockCMOS microheater is shown in Fig 3 1 A Suspended microstructures are created over a micro -cavity for good thermal isolation P latinum resistors are integrated as the heating source, and the local electrical field (E -field) and growth temperature can be controll ed by the micro heater geometry and power supply Three types of microheaters have bee n designed. The first microheater design (Fig. 3 1 B) i s a micro -hotplate with a meander Pt microheater embedded. The hotplate is
33 supported by two anchored short beams. This design has a large growth area with relatively uniform temperature distribution a nd the potential as gas sensors. CNT s are expected to grow on the hotplate surface. The second design (Fig. 3 1 C ) ha s a serpentine shape This design introduces trenches between the micriheater (the red part) and the silicon dioxide secondary wall (the bl ue lines) for suspended C NT growth. With the secondary wall grounded, this configuration is also designed to study the local E -field distribution and the impact of the E -field on the CNT alignment. The third design (Fig. 3 1 D ) is further simplified into o ne straight lin e microheater for studying temperature and C NT density distribution along the microheater. Th e distribution information will facilitate the further microheater scaling With a hot spot heater the m inimization of heating elements offers more accurate local control of E -field, temperature and growth rate Thus, the position, quantity, length direction, and properties of C NTs can be better controlled. Moreover smaller heating elements require less power, and lead to a higher CMOS CNT integrat ion density. Figure 3 1 A ) Structural demonstration of mock-CMOS platinum microheater. B) Large hotplate with a meander Pt microheater embedded C) Serpentine microheater design. D ) Straight line microheater design. B) C ) D ) A )
34 3.2 Device Fabrication Based on the above microheater design s a process flow is proposed to fabricate the devices Fig 3 2 shows the cross sectional view of the process flow. The fabrication pro cess starts from the deposition of a 2 (Fig. 3 2 A ). A Cr/ Pt /Cr heater film is then sputtered and patterned using a lift -off process in which 200 nm thick Pt is the heater and 30 nm thick Cr is the adhesive layer for Pt (Fig. 3 2 B, Cr layer not shown). Next, a top SiO2 layer is deposited and patterned Depending on the mask design, the top SiO2 layer can be left there to form an oxide/Pt/oxide sandwich structure (Fig. 3 2 C), or the SiO2 over the microheater can be etched away to form a Pt/oxide bimorph structure (Fig. 3 2 C ) in which c ase direct cont act between Pt electrodes and C NTs will be formed during the synthesis process Then, using the patterned SiO2 layer (Fig. 3 2 D ) or the Pt heater itself (Fig. 3 2 D ) as the etching mask an anisotropic deepreactive ion etching (DRIE) of s ilicon is performed to create trenches around the heater Finally, isotropic silicon dry etching is performed to undercut the silicon underneath to release the microheater hotplates (or bridges) suspended over the cavity (Fig. 3 2 E and E ). The localized heating is realized by using DRIE silicon dry etching process to form a cavity to obtain a good thermal isolation. In the next c hapter, we will see that the process proposed for mock CMOS microheater fabrication is fully transferable for releasing microhea ter s integrated in CMOS substrates Three types of microheaters that were introduced in Section 3.1 have been fabricated and characterized. Fig. 3 3 shows the SEM pictures of fabricated microheaters. The first design (Fig. 3 3 A ) is an 87 2 micro -ho tplate with a symmetric meander Pt heater emb edded. The second one (Fig. 3 3 B ) is the s erpentine microheater design The dark region is the etch through openings that are patterned du ring the step shown in Fig. 3 2 C It is corresponding to
35 Figure 3 2 Cross -sectional view of the proposed process flow A ) PECVD SiO2 d eposition. B ) Pt sputtering and lift-off to form heater and pads. C) and C ) Top PECVD SiO2 d eposition and patterning. D) and D) Anisotropic Si dry etch. E) and E ) Isotropic Si dry etch and heater release. the trench as shown in Fig. 3 3 D. The white region surrounding the center Pt heater in the SEM picture is bare silicon oxide with no silicon under neath as shown in Fig. 3 3 D Therefore, the white reg ion outlines the size of micro -cavity below the microheater Its bright color is an artifact due to the charging effect of the sample during SEM imaging. Due to its serpentine shape, some bare silicon oxide was left between etch openings as the extra mecha nical supports. This is found to be necessary. A test structure with similar serpentine shape but no extra mechanical supports sagged down obviously after the release. Although it still can function as a microheater, one could imagine the mismatch in thermal coefficient of expansion between CNT and Pt heaters and the freedom of microstructure deformation might increase the probability of detach ment of the A ) B ) D ) D ) C ) C ) E ) E ) Pt Silicon SiO 2
36 CNT s from the devices. The third d esign (Fig. 3 3 C) is a straight line Pt microheater. It is 5 The top SiO2 layer is etched during the step shown in Fig. 3 2 C, and thus the Pt is exposed to facilitate the electrical contact with CNT s. The exposed Pt is 80 long, defined as the effective length of the microheater L1. Simi larly, the white bare silicon region represents the cavity boundary, and the effective length is labeled as L2. In this design two extra parallel Pt lines are placed on the left and right of the heater as labeled as A and C, respectively They are used as the second wall s for CNT landing during the growth, and as the second electrode s for extracting electrical signals after CNT growth for applying electrical voltage to generate heating Another pair of electrodes is designed to apply proper E -field if necessary (as shown in Fi g. 3 3, labeled as E -field electrode). Figure 3 3 SEM picture s of fabricated microheaters. A ) Design 1: Pt heater embedded in a micro -hotplate, B ) Design 2: Pt heater in a curved shape, and C ) Design 3: Pt heater with two straight lines in parallel, labeled as A, B and C, respectively. L1 and L2 represent respectively D ) Cross sectional view of the device ( line MM in part B). D ) Bare Si Trench A ) Pad Pad C ) L1 A L2 B C Pad Pad E field electrode E field electrode B ) M M Pad Pad E field electrode E field electrode Extra supports
37 3.3 Microheater Characterization After device fab rication, the microheaters ar e characterized before performi ng growth experiments. The characterization is design ed to measure the following properties. First, f or the purpose of successful SWNT synthesis, the maximum temperature that can be reached by resistive heating and the reliability of the microheaters under such high temperature conditions are two key factors. Then, f or the purpose of integrating SWNTs on CMOS chips, the local temperature distribution is a major concern, i.e. a sharp temperature gradient is desired so that temperature can decrease rapidly fr om the heater center toward the substrate. 3.3.1 Maximum Temperature Estimation The mechanical robustness at high temperature was first tested by baking m icroheaters in oven at 900C for 20 minutes. Both t he oxide/Pt/oxide and Pt/oxide bimorph structure we re expected to undergo str ain incompatibility primarily due to the thermal expansion mismatch of different materials. A lthough slight sag was ob served, all the microheaters were survived the high temperature treatments with no rupture occurred. Then, t he working temperature of microheaters w as evaluated using micro -hotplate design. It is reported that platinum has the optimum thermo resistive characteristics and Pt resistance thermometers have served as the international standard for te mperature measur ements between 259.34 C and 630.75 C  In a linear approximation, the relation between resistance and temperature is given as follows : 0(1)TRRT (3 1) in which 0R is the initial resistanc e, TR is the resistance dependent on temperature is the temperature coefficient of resistance (TCR) and T is the temperature increment The de facto industrial standard value of TC R is 0.00385 / C, but thin film platinum exhibits a coefficient that
38 tends to decr ease with the t hickness. The value of TCR used for our 200 nm thick Pt microheater is about 0.00373/ C, which i s obtained from Clayton s report  The microhea ter was electrically connected using silver epoxy and then characterized. The experimental current voltage relation was plotted in Fig 3 4 A The resistance under each power supply can be calculated, and the corresponding temperature can be estimated base d on the change of the Pt heater resistance and the TCR of Pt. The resistance of the micro -hotplate was about 46 at room temperature. It increased to 212.5 w hen the applied current was increased to 14 mA T herefore, the maximum temperatur e wa s estimated to be above 900 C based on equation 3 1 (Fig. 3 4 B). Figure 3 4 A ) I -V characteri zation of microheater. B ) Te m perature estimated based on resistance change. For the temperature obtained by this method, it should be noted that the calculated temperature is only an approximation and subject to following simplifications. First, the re sistance measurement is simplified. The resistance measured is actually the sum of the contact resistance and the heater s resistance: Totalcontactresistor RRR Further, the overall heater s resistance resistorR should consider both th e 200 nm Pt layer and the 30 nm Cr adhesive layers. At 20 C trical resistivity of Pt is 105 [102, 103] Second, under J oule heating, the microheater actually exhibits complex 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 2 4 6 8 10 12 14 Current (mA)Voltage (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 200 400 600 800 1000 Temperature (C)Voltage(V) A ) B )
39 temperature distribution along the heater rather than one uniform temperature. Thus the calculated temperature is an approximation of the average As a result of these simplifications, what we obtained is a rough range that indicates high enough temperatu re for growth rather than a specific temperature. T hermal characterization accurate to degree centigrade is desirable but not the primary objective of this thesis 3.3.2 Heating Experiment During the I -V characterization presented above, red glowing of the microheater s und er different voltages wa s clearly observed under an optical microscope, as shown in Fig 3 5. This red glowing can be switched between on and off instantaneously by controlling the power supply, indicating much shorter response time com pared to traditional CVD processes. The localized microheating combined with this fast response greatly reduces the total power consumption and thermal budget of post CMOS processing. In addition, we need an indicat or to determine when the microheater has reached the required high temperature so that we can stop increasing the power supply and start the CNT synthesis process. Due to different structure designs and/or fabrication variation s between devices, individual microheater s require different electrical powers to reach the same temperature. Thus neither current nor voltage is a good indicative parameter unless each microheater is characterized under the growth condition and the temperature-power relation is established for each device before the real g rowth. Instead, the incandescence, the emission of visible light from a hot body due to its temperature, of platinum microheaters observed as red glowing indicates that the heater reaches the required high temperature. Indeed, we start flowing in synthesis gas es once the red glowing is observed in our practice.
40 Figure 3 5 Microscopic im ages under applied voltages of A ) 2.28 V, B) 2.62 V, and C ) 3.0 0 V, respectively. 3.3.3 High Temperature Reliability After assessing th e maximum temperature, the reliability of the microheaters at high temperature was then evaluated. Although bulk platinum has a high melting point (1768C  ) and i t is extraordinarily stable at high temperatures, the degr adation of platinum thin film at high temperature has been reported by several groups  As shown in Fig. 3 6 A we observed a kink point in the curve at higher voltage and a negative slope between 1.2 V to 1.4 V before the microheater was broken. To study the negative slope region, another newly released platinum thin film microheater with the same design was tested. T he voltage wa s gradually increased from 0 to 1.5 V and then swept back to 0 V. T he sweepings were repeated from 0 to 1.5 V and from 0 to 1.8 V. As shown in Fig. 3 6 B the negative slope only occurre d during the first 0 1.5 V voltage sweeping. A fter that, the electrical characteristics changed and became repeatable as a result of a permanent change in the platinum resistance. Briand et al. reported that the resistivity of the Pt/ Ta thin film increas ed after a heat treatment of 95 minutes at 830C, as a function of the film thickness (Fig. 3-6 D )  Re -plotting the electrical characteristics we obtained (Fig. 3 6 B) as Resistance Vs. Power in Fig. 3 6 C, we found that the resistance increased from 134 185 sweeping. This resistance increase is explained as the result of self -heating treatment t hrough C ) B ) A )
41 resistive J oule heating with points A and B corresponding to points A and B in Briands paper, respectively There might be a cr itical point that is associate d with this high temperature degradation This critical temperature might be different for Pt thin films with different configurations such as thickness, structure, type of adhesion layer, etc. Firebaugh et al. reported that the resistance of their 100nm Pt/10-nm Ti film was well behaved up to ~900C beyond Figure 3 6 A ) Embedded s traight line platinum microheater I -V characteristics. Negative slope was observed between 1.2 V to 1.4 V. B ) Heater characteris tics under repeated sweepings. C ) Microheater resistance under repeated sweepings. Inset: resistance characterization of the 100 -nm Pt/10 nm Ti film, reported in literature  C) Sheet resistance for 205 -nm Pt/15 nm Ta and 145nm Pt/15-nm Ta thin fil m, (1) before and (2) after 830 C heat treatment, as reported in literature  0.0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 Current (mA)Voltage (V) 0.0 0.5 1.0 1.5 2.0 0 2 4 6 0 1.5V 1.5 0V 0 1.5V 0 1.8V Current (mA)Voltage (V) B ) A ) C ) A B 0 2 4 6 8 100 150 200 250 300 Resistance (Ohm)Power (mW) 0 1.5V 1.5 0V A B D )
42 which holes started to form in the film and resistance increased rapidly  (Fig. 3 6, inset). For our de vice, the critical temperature wa s believed to be reached at the center of the microheater when the power supply was increased to around 6 mW, and the rest part of the microheater later underwent the similar temperature treatment when the input power was continuously increased to about 8 mW. Several factors attribute to the degradation of platinum thin film, including interdiffusion and reaction between the Pt lay er and the adhesive layer, stress, and pl atinum silicide formation  but the agglomeration of cont inuous thin films into islands of material is believed to be the dominant mechanism  A gglomeration involves the nucl eation and growth of holes in the film, and it is driven by the high surface to -volume ratio of the thin films The surface diffusivity is dependent on the temperature, and the diffusion of metal atoms on surface tends to reduce the surface to -volume ratio th rough capillarity  The size s for the initial hole s must be larger than the thickness dependent thermodynamic critical radius, and the holes will then grow under the surface -diffusion -driven capillarity  As reported by Firebaugh et al.  holes started to form in the platinum thin film at around 900 C, and gradually increased in size with time, resulting in the discontinuity (Fig. 3 7). Note that the hole growth rate is slow and the film life time i s sufficient long, compared with the tim e required for CNT growth. To avoid agglomeration, thin film thickness greater than 1 recommen ded  For our 20 0 -nm platinum microheater s we noticed that although the film is not sufficiently thick, all the microheaters are capable of withstand ing a sufficient amount of time required for CNT growth process.
43 Figure 3 7 The formation and growth of holes in the 100-nm Pt/10 -nm Ti thi n film. A ) After 0 hour at 900C. B) After 2 hour s at 900 C. C) After 6 hour s at 900C. D ) After 9 hour s at 900C. R eported in literature  3.3.4 Local Temperature Distribution Other than the maximum temperature and the heater reliability, the local temperature distribution i s also of vital importance It wa s investig ated using a QFI InfraScope. The thermal image of the straight line microheater is shown in Fig 3 8 A Since the maximum working temperature of this infrared imager is 400 C, only 0.6 V wa s applied to the microheater. Fig. 3 8 D and Fig. 3 8 E show t he te mperature distributions along and tra nsverse to the platinum heater line, respectively. It is clearly shown that t he temperature is near uniform at the region 30 m from the microheater center This offer s the optimal region for CNT growth. Meanwhile, wi th the temperature as high as 400 C around the heater center th e temperature outside the micro -cavity drops quickly to about 100 C. N ote that the InfraScope stage wa s heated to 60 C to facilitate accurate temperature measurement for this image Therefore the temperature distribution is compatible with the post -CMOS processing even when the supply power must be increased to provide the desired growth temperature of ~900 C. A ccurately choosing the B) A ) D ) C )
44 spacing between CMOS circuits and microheaters this local ized micr oheating method can integrate CNTs at a close proximity of the CMOS devices on the same chip. For design1 and design 2 the corners of the microheaters have slightly higher temperature due to the current crowding effect, as evident from their the rmal images (as shown in Fig. 3 8 A and Fig. 3 8 B). Figure 3 8 Thermal imaging. A ) Thermal image of Design 1 by applying 0.93 V dc voltage B ) Thermal image of Design 2 by apply ing 1.2 V dc voltage C) Thermal image of D esign 3 by applying 0.6Vdc voltage D ) and E ) Corresponding t emperature distribution alon g and transverse to the micro heater, indicating good thermal isolation. (T he substrate temperature is 60 C). C ) ( e ) ( d ) -60 -40 -20 0 20 40 60 100 200 300 400 Temperature(C)Disstance(um) Distance ( m) 60 40 20 0 20 40 60 E ffective length of heater: L 1 L ength of cavity: L2 Temperature ( C) 400 300 200 100 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24 100 200 300 400 Y Axis TitleX Axis Title Distance ( m) Temperature ( C) 400 300 200 100 28 24 20 16 12 8 4 0 4 8 12 16 20 24 Width of heater D ) E ) B ) Temperature (C) 52.9 1 52.1 2 51.3 350.5 A ) 0 133.6 267.2 400.8 Temperature (C)
45 3. 4 Room Temperature Carbon Nanotube Synthesis After devi ce fabrication and c haracterization, the samples were coated with a lumina -supported iron catalyst by drop -drying. Two contact pads were conn ected to a voltage -cont rolled power supply by clamps. A nd t hen t he sample wa s placed into a quartz tube. After 5 min utes argon purg ing the microheater wa s heated up t o the state that red glowing could be observed. For example, Design 2 needs a supply voltage of 33.5 V. Then, a mix of 1000sccm CH4, 20-sccm C2H4 and 500-sccm H2 wa s fl owed into the quartz tube for C NT g rowth. After a 15 minutes growth, SWNTs and MWNTs with diameters ranging from 1 10 nm were successfully synthesized on all the three types of suspended microstructures. Fig 3 9 shows a dense film of C NTs grown on the micro-hotplate surface Some in terest ing coiled nanostructure s as shown in the insets in Fig. 3 9, are observed on many samples. The orientations of these CNT s are random since there is no guiding electrical field. Figure 3 9 Dense film of CNTs over micro hot plate surface (Design 1). Insets: coiled nanostructures observed in the growth. On the other hand, for the other two designs with trenches and secondary landing walls, the suppl ied voltage simultaneously introduces an E n the microheater and a nearby ground electrode/oxide wall. As a result, most of the suspended CNTs gro w n on these two types of microheaters exhibit a significant alignment along the E -field 100 nm 100 nm C oiled Ntt 100 nm
46 perpendicular to the cold wall, as shown in Fig 3 10. As demonst rated in our experiments with proper designed microheaters and trench width s the desired temperature profile and E -field distribution can be obtained by the same power supply. The extra pair of back up electrodes designed to enhance E -field was not used, and thus can be removed to simplif y the design in the future. Although the microheater corners have higher temperature and denser E -field, comparing the SEM images (shown in Fig. 3 10 A and Fig. 3 10 B) reveal s that there is no significant difference betw een the growth around the corner s and the rest of the microheater When the microheater i s further simplified into one straight line (Design 3) we f in d that the alignment i s further improved as shown in Fig. 3 10 C and the CNT growth i s uniform along the length of the Figure 3 10. L ocalized synthesis of CNTs suspended across the trench showing good CNT alignment. A ) and B ) Zoom -in SEM of CNTs grown on Design 2 C) Zoom in SEM of CNTs grown on Design 3 (from second batch, w ith no Cr on top) Insets: SEMs of overall microheaters. 1 m Cold wall of SiO 2 B ) 1 m Cold wall of SiO2 100 nm Cold wall of P arallel P t Highly aligned SWNTs C ) A ) E field electrode E field electrode E field electrode E field electrode
47 entire microheater except on the small regions next to the anchors. These results are in good agreement with the measured temperature distribution. Hence, the microheater geometry with either a relat ively larger hotplate or a small hot -spot can be customized to control the temperature distribution for regulating the CNT growth for various applications. 3.5 Characterization of Carbon Nanotubes In the third design, there are three parallel Pt lines ( as shown in Fig. 3 11 inset, labeled as A, B and C, the one in the center is the microheater) The top SiO2 coverage has been etched away for facilitating direct electrical contact between CNT s and the Pt lines. The Pt lines are initially separated from each other. Once two of the Pt lines are connected by CNTs, the resistance between them can be measured to characterize the electrical properties of the synthesized CNTs. However, a lthough tens or hundreds of CNTs are observed connecting the Pt lines, the measurement shows infinite resistance which indicates very poor electrical contact s After some investigation of the involved materials including palladium molybdenum platinum and chromium it turns out that the adhesive chromium layer is easily pass ivated by oxygen, forming a thin oxide surface layer thereby increasing the contact resistance to unusable levels. In the s econd batch the same process flow was followed but the top Cr layer was removed. The microheater consists of a structure of 200-nm Pt/30 nm Cr/0.5 2. The SEM image shows the similar growth result in term of the growth density, nanotube diameters etc., but the I -V characterization shows that the contact resistance has been reduced significantly: from infinite to the indicating good oh mic contacts between the Pt and CNTs The characterization bet ween pads A and B, A and C B and C are measured on the same sample shown in Fig. 3 10 C (A, B and C are as labeled in Fig 3 11 inset). The measured resistances are shown in Fig. 3 11. The resi stance RB C between the pads C and B B A between the pads A and B
48 due to the denser and shorter CNT connection. Since CNT s cannot grow from the cold Pt landing walls there is no direct connection betwe en lines C and A The measured resistance RA C between the pads C and A is about -connected resistors RB C and RB A. Thus, we demonstrated that, by selecting a proper material as the electrode s suspended SWNT devi ces can be fabricated using this approach, and t he electrical properties can be measured without any post -growth metallization processing. Figure 3 11. I -V characteristics of SWNTs contacted by Pt electrode. It was measured on the same device shown in Fig. 3 10 C Inset: a SEM image of the overall microheater. As mentioned in Section 2.1, CNT s growth can follow two growth mechanisms: tip growth and base -growth. Thus two types of contacts can be consequently formed when CNT s reach the secondary Pt lines. Jiang et al. proposed that in the tip growth model, once the hot catalyst particles reach the cold secondary structure, the growth process stops immediately due to the temperature drop (Fig. 3 12 A left) ; in the base growth mod el, since the catalyst particles stay at the high temperature microheater surface, the growth process will continue after the CNT landing and result in a line contact on the secondary electrode ( Fig 3 12 A right)  The line -1.0 -0.5 0.0 0.5 1.0 -80 -40 0 40 80 Current (uA)Voltage (V) Resistance between pad A and C Resistance between pad B and C Resistance between pad A and B A B C
49 contact was clearly observe d from our growth results (Fig. 3 12 C), but the tip contacts were unclear since the secondary electrode surface was covered by th e catalyst layer (Fig. 3 12 B ). Franklin et al. also reported that it was the overlapping of the CNT with the Mo electrode surface that forms the electrical contact  H owever, so far there have been no conclusive experimental result s on which growth model would result in better contact s Our fore -mentioned good ohmic contacts and low resistances are the results of numerous parallel CNT s, probably including bot h tip contact s and line contact s Future investigation may try to grow one single CNT on each device in the batch mode, and establish the relation of grow model and contact resistance. Figure 3 12. A ) Demonstration of the t ypes of nanotube nanoto -micro contacts. The left one shows the tip -growth mechanism, and right one is the base -growth mechanism [11 1] B) An SEM image of the possible tip contact s C) An SEM image of the possible line contact. 100 nm B ) Secondary Pt wall 100 nm Secondary Pt wall C ) A ) Tip growth Base growth
50 Recall in the cases w h ere suspended CNTs were directly synthesiz ed between two Mo electrode s without any post growth metal clamp s the resistance tend ed to in crease over time which was attributed to the slight oxidation of the Mo in air  I-V characterization of C NTs was performed right after the synthesis (Fig. 3 11) an d the characterization was done once again one year later for the same device The two measured resistances were shown in Fig 3 13. The resistance under 1.0 volt was almost the same, but some nonlinearity under low input power was occurred. It might be due to the change of the contact condition ( the oxidiz ation of the catalyst/Pt electrode surface), or due to the property change of the CNT s themselves (absorption of the gas molecular and mechanical deformation). Figure 3 1 3 I -V characteristics of C NTs contacted by Pt electrode. One measurement was obtained right after growth, and the other measurement was performed one year later. Following the resistance characterization, the sensing abili ties of the suspended nanotube de vice were investigated as gas and t hermal sensors. As a gas sensor, t he resistance tend ed t o de crease when exposed to oxygen and in crease during pure nitrogen purging. However, n o -1.0 -0.5 0.0 0.5 1.0 -80 -40 0 40 80 I (uA)Voltage (V) R obtained one year later R obtained after growth
51 significant changes can be identified as the outputs seem to be dominated by the noises as shown in Fig. 3 14. Figure 3 14. Response curve to oxygen vs. time. Bias voltage is 1 V. A ) 1 -200s: 1000sccm N2. 2002000s: 500sccm N2 and 500-sccm O2. B ) 0 400s: 1000-sccm N2. 400-4000s: 200sccm N2 and 800-sccm O2. Figure 3 1 5 Measured resistance vs. temperature relationship. As a thermal sensor, we repeatedly observed that the resistance of CNTs decreased with temperature, which coincides with the literature  (i.e. negative TCR). Fig. 3 15 shows the 0 500 1000 1500 2000 25 26 27 28 I (uA)Time (s) 0 1000 2000 3000 4000 23.5 24.0 24.5 25.0 25.5 26.0 26.5 I (uA)Time (s) B ) A ) 40 50 60 70 80 90 42 43 44 45 46 47 Resistance (Kohm)Temperature ( C)
52 measured temperatureresistance relationship. The temperature coefficient of resistance i s about 0.15 % per degree Celsius. The value of TCR reported in the literatures range s from 0.1 % to 0.66% per degree Celsius [56, 114116] mainly depending on the type of CNTs and the fabrication process. 3. 6 Summary In t his chapter room temperature localized CVD synthesis of CNTs based on three microheaters designs has been successfully demonstrated. Three types of pl atinum microheaters have been designed, fabricated and tested which successfully demonstrated the targeted mechanical robustness and temperature profile. Local temperature distribution has been investigated using a high -resolution thermal imag er and later confirmed by the CNT growth density distribution The synthesized CNT s showed excellent alignment and good ohmic contacts with platinum electrodes. The suspended CNT device has been demonstrated as a thermal sensor, with the TCR value in accordance with o ther literature reports. Future work of this part of the project will focus mainly on investigating the growth mechanism and the contact resistance, improving its sensing abilities, and exploring other applications.
53 CHAPTER 4 THE INTEGRATION OF C ARBON NA NOTUBES ON CMOS SUBS TRATE In the previous chapter, localized CNT synthesis on mock CMOS substrates has been demonstrated We have proved that, based on the voltage controlled localized heating, suspended on -chip microheaters can provide both uniform high t emperature for high-quality CNT growth and good thermal isolation for CMOS compatibility requirement. Repeatable and well aligned CNT growth c an be realized, and the simple straig h t line microheater is promising for further scaling down to a hot -spot. Howe ver, a number of vital questions have yet to be settled. First, platinum is still incompatible with other standard CMOS materials and thus unlikely to be used in a post CMOS process in a commercial CMOS foundry. Second, the process flow proposed in Section 3.2 requires two lithograph y steps for patterning microheater s and release openings which is still too complicated for postCMOS processes. Third, the integration presented in the previous chapter did no t involve the interconnect ion of CNT s with CMOS cir cuits in the monolithic integration. To address these issues, we propose a simple and scalable CMOS CNT integration approach in this chapter. CNTs are selectively synthesized on polysilicon microheaters embedded aside the CMOS circuits using localized hea ting and maskless post -CMOS surface micromachining techniques There is no need of any photo-masks, shadow masks or metal deposition to achiev e the localized synthesis and the CNT -polysilicon electrical contact. Successful monolithic CMOS CNT integration ha s been demonstrated A nd it i s verified that the electrical characteristics of the neighboring NMOS and PMOS transistors are unchanged after CNT growth.
54 4.1 Integration Principles and Device Design As illustrated in Fig 4 1, the basic idea of the monolit hic integration approach is to use maskless post -CMOS MEMS processing to form micro cavities for thermal isolation and use the gate polysilicon to form the heaters for localized heating as well as the nanotube to CMOS interconnect. The microheaters, made o f the gate polysilicon, are deposited and patterned along with the gates of the transistors in the standard CMOS foundry processes Except the shape and dimensions, the polysilicon microheaters are equivalent to the transistor gate, and thus they share exa ct ly the same subsequent process es, i.e. the vias interconnects passivation layers and I/O pads One of the top metal layers (i.e. the metal 3 layer as shown in Fig. 4 1 B) is also patterned during the CMOS fabrication It is used as etching mask in the following post -CMOS microfabrication process for creating the micro -cavities. Finally, the polysilicon microheaters are exposed and suspended in a micro-cavity on a CMOS substrate, while the circuits are covered under the metallization and passivation laye rs as illustrated in Fig. 4 1 B. Unlike the traditional thermal CVD synthesis that heat s up the whole chamber to above 800 C, the device with embedded microheaters works like a miniaturized CVD array : the CVD chamber is kept at room temperature all the ti me, with only the microheaters activated to provide the local high temperature for CNT growth (Fig. 4 1 A the red part represents the hot microheater ). The top view of a microheater design is shown in Fig. 4 1 C The configuration is similar to the platin um microheaters. There are two polysilicon bridges: one as the microheater for generating high temperature to initiate CNT growth and the other for CNT landing. With the cold wall grounded, an E -field perpendicular to the surface of the two bridges will be induced during CNT growth. Activated by localized heating, the nanotube s will start to grow from the hotspot ( i.e. the center of the microheater ) and will eventually reach the secondary cold bridge under the influence of local E -field. Since both the micr oheater bridge and the landing bridge are made of gate
55 polysilicon layer and they have been interconnected with the metal layers in CMOS foundry process, the as -grown CNT s can be electrically connected to CMOS circuit ry on the same chip without any post -gr owth clamping or connection steps. Figure 4 1 A ) The 3 D schematic showing the concept of the CMOS integrated CNTs. The CVD chamber is kept at room temperature all the time. The red part represents the hot microheater that has been activated for high temperature nanotube synthesis. B) Cross -sectional view of the device. C ) The schematic 3 D microheater showing the local synthesis from the hotspot and self assembly on the cold landing wall under the local electric field. As discusse d in Section 3.1, the microheater design is of vital importance. T he gate polysilicon layer is thin and its thickness is determined by the foundry CMOS processes. For the AMI 0.5  used in this work, the polysilicon the serpentine design showed no meaningful advantages of the corner effect but required extra E Hotspot for growth Cold wall for landing CNTs I V C ) A ) CMOS chip Al Oxid P+ P+ N N+ P N+ Gate B )
56 mechanical supports in the previous mock CMOS synthesis experiments, a line shape microheater is ad opted for its superior mechanical robustness and simpl e design A typical heater design is shown in Fig. 4 2 A which is basically a polysilicon resistor. Since t he temperature ha s to reach at least as high as 800C for SWNT growth and to drop quickly to a void deteriorat ing the surrounding CMOS circuits, the thermal isolation thermal stresses and structural stiffness must be well balanced during microheater design. As we all know, short resistors tend to dissipate heat faster so that reaching high temperat ure requires more power (because the center of the resistor is close r to the anchors), while long resistors tends to have mechanical stiffness issues. In addition, the current density limitation of the polysilicon resistors and the limitation of the releas e process do not allow us to design microheaters with too narrow width. As a result of considering all these factors, t he heating unit first investig ated is a 3 polysilicon resistor Electrothermal modeling in a multi -physics finite element method tool, COMSOL  ha s been used to simulate and optimize the microheater design. The simulation result s are shown in Fig. 4 2 B and Fig. 4 2 C where a typical polysilicon sheet resistance of 30 other material properties are chosen according to the employed foundry process  (see Table 4 1) For the simulation, the convection and radiation heat ing losses are neglected as the heating area is small. The substrate bottom surface is assumed to stay at room temp erature. Fig. 4 2 B shows the temperature distribution when a 2.5 V activ ation voltage is applied to the heater. It shows a good agreement with the post -growth surface pattern (Fig. 4 2, inset SEM image) which is believed to reflect the temperature distri bution during the growth. Fig. 4 2 C plots the temperature distribution along the micro heater. It shows an ideal condition for CMOS CNT
57 integration: a very small, localized h igh temperature region for CNT growth and a sharp temperature decrease toward the substrate. Figure 4 2 A ) A typical heater design with stripe -shaped resistor. B) Simulated temperature distribution along the surface of the microheater at an applied voltage of 2.5V through the pads. The area of polysilic on microheater is is chosen according to the CMOS foundry process. Inset: an SEM image of a microheater after CNT growth. C ) The line plot of the temperature along the heater (line AA in part B). Based on this 3 2 heating unit, a series of heater design variation s have been investigated. First, to exploit the geometry limitations (mainly the mechanical robustness and electrothermal properties) six line -shape microheaters are designed with dimension variations. Th e width ranges fro two types of the secondary wall are des igned: one is a bridge parallel to the microheater for A ) Polysilicon heater 20 0 20 40 40 Temperature ( C ) 600 0 400 800 1000 C ) A A 200 B ) 900 300 100 Boundary: Temperature 500 700 A A
58 uniform E -field formation (Fig. 4 3 A ) and the other is a sharp tip (or multiple tips) to f orm a converged E -field (Fig. 4 3 B ) The gap between the two polysilicon microstructures is typically 3 6 CNT landing. Third, opposing sharp tips (Fig. 4 3 C) are also designed to facilita te the CNT bridge formation since CNT s tend to attach to the nearest support boundary  Finally, instead of grounding the secondary wall, some designs have five configurable inputs. As illustrated in Fig. 43 A four pads c an input different voltages to tune the electric field, and the fifth input (not shown) i s connect to the substrate as a global back gate for studying the electrical gating effect Figure 4 3 S chematic layout s showing A ) a 10 m microheater with a paralleled bridge as the secondary wall and four configurable input pads B) a 6 2 microheater with multiple tips as landing walls, and C) a microheater with opposing sharp tips The final CMOS chip includes test c ircuits and 13 embedded microheaters. The sch ematic layout is shown in Fig. 4 4. Microheaters are placed around the center and they are independent from each other. Four test circuits are placed close to the microheater with spacing s ranging from 36 60 The spacing is chosen based on the temperature distribution investigation shown in Fig. 3 8. The sizes of the NMOS and PMOS transistors which are the subject of our investigation are Wn/Ln = 3.6 p/Lp = 7.2 The big square with green color in Fig. 4 4 B is the metal 3 layer. It is patterned as etching mask that covers all the circuit area beneath but has 13 etching openings, with one opening for each B ) A ) C ) heate r Pad 1 : 7 V Pad 2 : 4 V Pad 3 : 3 V Pad 4 : 0 V
59 individual microheater. The etching opening as shown in Fig. 4 4 C determines the size of the micro -cavity The micro -cavities will be formed when the top silicon dioxide and bottom silicon are all etch ed away during the post CMOS MEMS processes, leaving only the suspended microheaters, as shown in Fig. 4 1 A and Fig. 4 1 B However, there is a selective etching issue. In the cases where the microheaters are made of platinum, specific etch chemistry can be used to etch away silicon dioxide or silicon completely with little etching to platinum. Thus, etching protection for the heaters is not necessary, and the platinum microheaters themselves can be used as masks once the heaters shapes have been patterned. When switching the heater material to polysilicon, this is no longer the case. Both the dioxide etchant (dry etch ) and silicon etchant will etch polysilicon. Recall that and etching protection is essential In our design, the metal 1 layer a bove the microheater is pattern ed with the same shape as the microheater but with a slight ly greater wid th as shown in Fig. 4 4 D This patterned metal 1 layer will protect the microheaters during the first few steps Figure 4 4 A) and B ) Schematic layouts of the chip, including test circuits and 13 embedded microheaters. The spacing s between the microheaters and circuits vary from 36 60 C) and D ) Close up views of a microheater with metal 3 as etching opening mask and metal 1 as etching protection. B ) A ) C ) D )
60 when the etchants can react with polysilicon, and then it will be removed using polysilicon-safe etching recipes. Details wi ll be presented in the device fabrication section. 4.2 Device Fabrication and Characterization After the layout design the CMOS chips ar e fabricated through MOSIS using the commercial AMI 0.5 -metal CMOS process  The gate oxide thickness is 13.5 nm. The estimated lay er thicknesses and other parameters are listed in Table 4 1. Several parameters have been used in the modeling in Section 4.1. In addition, the thickness of each layer is used to estimate the etching time in the post-CMOS fabrication processes; the current density limits have been taken into consideration when designing the metallization. Table 2 1 MOSIS AMI C5 Technology Structure Min Typ Max Units N+ Poly Sheet Res 23 30 37 Ohms/sq CMP M3 Thickness 7000 7700 8400 CMP M3 to M2 Dielectric 10000 1100 0 12000 CMP M2 Thickness 5000 5700 6400 CMP M2 to M1 Dielectric 10000 11000 12000 CMP M1 Thickness 5700 6400 7100 Poly Thickness 3000 3500 4000 Field Ox Under Poly 3500 4000 4500 Via allowed current density 1.6 (85 C); 0.6 (125 C) mA/cnt Metal allowed current density per width 2.2 (85 C); 0.85 (125 C) Fig. 4 5 A shows the schematic cross -sectional view of the CMOS chip after the foundry process es but before any post -CMOS MEMS fabrication. The metal 1 and metal 3 layers have been patterned as descri bed in the previous section. The corresponding optical microscope image is shown in Fig. 4 6 A The total chip area is 1.5 1.5 mm2. Due to this small size, individual chips ar e mounted on top of a four inch carrier wafer for easy handling and processing. The
61 center big golden square is the metal 3 lay er. In addition to the 13 etching openings to expose the microheaters, there are 6 extra opening windows in the center. These are dummy structures for etching rate control. There are 32 outer pads for microheaters and 16 inner pads for circuits. The se pads as well as the area uncovered by the metal 3, need to be covered with photoresist for protection before any release processes. Figure 4 5 Mastless post -CMOS MEMS fabrication process flow: A) CMOS chip from foundry. B ) Si O2 d ry etch. C) Al etch. D) Anisotropic Si dry etch. E ) Isotropic Si dry etch and heater release. F ) SiO2 wet etch. The maskless post -CMOS MEMS fabrication process flow that used to release the polysilicon microheaters is shown in Fig. 4 5. It starts with the reactive ion etching (RIE) of silicon dioxide (Fig. 4 5 B). The metal 3 layer of the CMOS substrate is used as etching mask to protect the CMOS circuit area, and it also defines the cavity opening size. Within the cavity, the anisotropic etching, which uses a mixture of CHF3 and O2 as the etch chemistry, is mainly in the Poly Si Silicon SiO 2 C ) E ) Micro cavity F ) Poly Si heater Poly Si gate B ) Al A ) P+ P+ N+ N N+ P D )
62 vertical direction. As a result, when the reactive ions etch down and reach the metal 1 layer, three steep trenches are formed but the oxide under the metal 1 is almost un -attacke d, i.e. the polysilicon microheaters are entirely wrapped in a thin dioxide layer. Next, the exposed alum inum is etched by RIE (Fig. 4 5 C ), using BCl3, Cl2 and Ar. At this point, the photoresist should be removed since the pad protection is no longer nee ded in the following steps and removing it after the release step may damage the suspended microstructures. Then an anisotropic deep-reactive ion etching (DRIE) of silicon is performed (Fig. 4 5 D ) using SF6 and C4F8 as the etching and passivation gas es r espectively, to create a roughly 6 -deep trench around the heater. Next, an isotropic DRIE silicon etching using only SF6 is performed to undercut the silicon u nder the microheaters (Fig. 4 5 E ), resulting in suspended microheaters in micro -cavities. In these two steps of silicon etching, polysilicon will be quickly etched away if exposed. The silicon dioxide will also be etched but at a much slower rate. As mentioned in Section 4.1, the metal 1 is designed slightly wider than the polysilicon microheaters The width difference determines the thickness of the sidewall protective dioxide. The oxide sidewall must withstand the etching during the two silicon etching steps so that the polysilicon microheaters will remain unattacked. The final step is to etch aw ay the thin dioxide protective layer surrounding the microheaters using a 6:1 buffered oxide etchant (BOE) at room temperature for approximately five minutes to expose the polysilicon for electrical contact with CNT s (Fig. 4 5 F ). This BOE wet etch has a v ery high etching selectivity between silicon and silicon dioxide. Overall, since all the required etching masks have been patterned in the foundry processes, the post CMOS MEMS fabrication is simple and easy to control, requiring only RIE, DRIE and BOE etc hing.
63 Optical microscope images of the CMOS chip before and after the post CMOS processing are shown in Fig. 4 6 A and Fig. 4 6 B respectively. A c lose d up optical image of one microheater is shown in Fig. 4 6 C. The nearby circuit, although visible, is protected under silicon dioxide layer. Only the microheater and cold wall within the micro -cavity are exposed. To satisfy the spacing, the microstructures are rearranged such that the microheater is closest to the circuits and the secondary wall is on the opposite side. The p olysilicon heater is connected to Figure 4 6 A ) The CMOS chip photograph (1.5 1.5 mm2) after foundry process. B) The CMOS chip photograph after post CMOS process (before final DRIE step). C) Close up o ptical image of one microheater and nearby circuit. CMOS circuit area, although visible, is protected under silicon dioxide layer. Only the microheater and cold wall within the micro -cavity are exposed to synthesis gases. Polysilicon heater and metal wire ar e connected by vias. D) and E ) Close up SEM images of two microheaters. B ) CMOS circuits Micro cavity Poly Si layer Metal layer C ) Vias E ) D ) Microheaters A ) CMOS chip from fo undry 1.5 mm 1.5 mm
64 the metal interconnect by a number of via s The quantity of the vias is determined by two factors: the current that is required for Joule heating and the maximum current that one single via can withstand (see Table 4 1). SEM images of two microheaters are shown in Fig. 4 6 D and Fig. 4 6 E with the resistances of 97 released microstructures are mechanically robust. All the 13 microheaters, including the sharptip design and the 40 long design, survived the post CMOS processes. Five chips have been fabricated with a yield of 100%, indicating the robustness of the maskless post CMOS MEMS processes. Similar to the mock CMOS samples, polysilicon microheaters were also characterized before the CNT growth experiments. The measured current -voltage relation was plotted in Fig 4 7 A However, extracting the temperature dependent resistivity from the I -V characterization and then using the resistivity to estimate the temperature become s difficult due to the following reasons. First, grain bou ndaries in polysilicon exhibit charge carrier trapping and contribute to the temperature dependent behavior  Second, dopant concentrations have a significant impact on the temperature dependent resistivity within polysilicon. For low to moderate dopant levels (18 cm3) increased temperature offers higher therma l energy that excites more dopant electrons to the conduction band  resultin g in a negative TCR. Such temperature dependent behavior is undesirable since it will cause eletrothermal instability at high temperature. For heavily doped polysilicon ( 1019 cm3), if neglecting the grain boundary effects, the temperature dependent res istivity can be defined as: 1 ()ehpe (4 1) in which is the resistivity, p is the free electron concentration e is the magnitude of an electron charge, and e and h are the electron and hole mobility, respectively  Since the majority of
65 the dopant electrons in heavily -doped silicon are already in the conduction band, the free electron s that are thermal ly activated from the donor no longer domina te the resistivity. Instead, the temperature dependent behavior is dominated by the carrier mobilities at high doping levels, resulting in a positive TCR and a linearly increas ed resistance with in the temperature range from 300 to 800K. Lattice and impurity scattering mobility, L and I respectively, are found to have significant contributions to the charge carrier mobility at high temperature  The mobility terms can be expressed i n the following form s : a L b IT T 2.71.5 1.52 a b (4 2) and the temperature dependent resistivity can be expressed by a general equation: 312 T (4 3) in which the parameters 1, 2 and 3 have to be extracted empirically. For our microheaters, b ased on the polysilicon sheet resistance and the thickness, the resistivity is estimated to be 1.05105 ohm m and the impurity doping level is estimated to be above 1019 cm3 using the equation 4 1. Although high doping level requirement has been satisfied and a positive TCR has been confirmed from the resistance calculation (as plotted in Fig. 4 7 B) the electrical characteristics of the microheaters were found to be unstable at t emperature beyond the polysilicon recrystallization temperature Tcr (at roughly 870 K  ), and the linear increase in resistance no longer exists. Mastrangelo et al. reported that the resistance of a heavily doped polysilicon filament decreases when the bias beyond a kink point (Fig. 4 7 inset, point P )  For the microheater we investigated, the kink point P happens around at a bias voltage of 2 V (see
66 Fig. 4 7 A and Fig. 4 7 B ). Possible mechanisms reported include current -induced resistance decrease [125, 126] filamentation  and the polysilicon thermal breakdown [128, 129] Figure 4 7 A ) I -V characterization of 20 microheater. B) Resistance extracted from the I -V characterization C) F ) Microscopic images of a microheater : C ) before applyin g po wer, D ) starting to glow at 2.2 0 V, E ) showing bright glowing at 2.38 V, and F ) burnt after applying 2.47 V. Inset: filament I -V characteristics showing the kink point  Continuing to increase the bias voltage, a red glowing was first observed in the dark at 2.2 0 V (Fig. 4 7 D ), and it quickly became much brighter at 2.38 V. The heater was burnt in the center under a bias voltage of 2.47 V, as evident from the comparison between Fig. 4 7 C and Fig. 4 7 F As previously discussed, the extraction of temperature above the polysilicon recrystallization temperature is quite difficult due to its unstable electrical characte ristics. Again, the incandescence of the microheater becomes a good indicat ion of high temperature. Ehmann et al carefully calibrated a microheater, which is also made of n -doped CMOS gate polysilicon, and estimated that the average heater temperature was about 1200 K when 0.0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 Current (mA)Voltage (V) 0.0 0.5 1.0 1.5 2.0 2.5 120 140 160 180 200 220 240 Resistance (Ohm)Voltage (V) C ) D ) A ) B ) P P E ) F )
67 incandescence was observed in the dark  In addition, Englander et al. who first locally synthesized CNTs on suspended polysilicon MEMS structures, reported that based on their growth results, the barely glowing condition offered ri ght temperature (850C to 1000C) for maximum growth ( prior -glowing wa s too cold while bright glowing wa s too hot)  Therefore, the microheaters we designed and fabricated are capable of providing the high temperature required for CNT growth, and it can withstand a sufficient amount of time under barely glowing state. The local temperature distribution is not characterized. Instead, the performance of test circuits and individual transistors are recorded, and will be compared with the ir performance after CNT growth to assess the effec tiveness of the thermal isolation. 4.3 On -chip Synthesis of Carbon Nanotubes After the microheater release, the CMOS chip s wer e carefully taken off from the carrier wafer and then wire bonded to a DIP package Next, the chips wer e coated with alumina -supp orted iron catalyst by drop -drying on the surface  The whole package wa s then placed into a quartz chamber. The on -chip microheater s wer e turned on by applying appropriate voltage s such that bare growing wa s observed. The supplied voltage also introduce d a loc al E -field of about 0.1 ~ 1.0 simultaneously The CNT growth was carried out using 1000sccm CH4, 15-sccm C2H4 and 500-sccm H2 for 15 minutes, while t he chamber remain ed at room temperature all the time. After a 15 minutes growth, CNTs were succe ssfully synthesized Two SEM images with locally synthesized CNT s are shown in Fig. 4 8 The individual suspended CNT s in Fig. 4 8 A ar e grown from the 3 3 icroheater as shown in Fig. 4 6 E and land on the near polysilicon tip. In the configuration with a parallel bridge as the secondary landing wall, the growth exhibits less convergence due to the less converged E -field S imilar growth occurred on 11 out of 13 microheaters. The 1.2 1.2
68 tips were broken during the growth. The reason might be the presence of super local heating that causes the failure at grain boundaries. Figure 4 8 Localized synthesis of carbon nanotubes grown from A ) the 3 3 microheater and B) the 6 6 suspended across the trench and connecting to the polysilicon tip/wall Insets: SEM images of the overall microheater. 4.4 Characterization of Carbon Nanotubes and Circuit Evaluations After the growth, the as grown CNT s wer e characterized by measuring t he resistance between two polysilicon microstructures (the microheater and the landing wall) at room temperature and at atmosphere. The I -V characteri stic is shown in Fig. 4 9. The typical resistances of in -situ grown CNT s ar e i n the range of This large resistance is primarily attributed to the contact resistance between the polysilicon and the CNT s. Recall that the final step of the post -CMOS fabrication is meant to completely remove the silicon dioxide and thus fully expose the pl oysilicon surface. However, this step ha s been done long before the growth process due to the subsequent steps such as wire -bonding, package, and catalyst deposition. A thin layer of native oxide is expected to naturally grow on the polysilicon electrode surface with a typical thickness of about 2 nm  Other factors such as defects along the CNT s m ight also contribute to the large resistance. Catalyst layer A ) B )
69 Figure 4 9 I -V characteristics of the as -grown CNTs. The I -V curve is measured between two polysilicon microstructures contacting the CNT s. Figure 4 10. DC electrical characteristics of single tra nsistors before and after CNT growth. A ) Drain current (Ids) versus grain voltage (Vds) for NMOS transistors under seven different gate voltages. B ) Drain current (Ids) versus grain voltage (Vds) for PMOS transistors under seven different gate voltages. After the successful on -chip synthesis of CNTs, the impact of the localized heating on the nearby circuits was assessed. As mentioned in Section 4.1, the spacing ranges from 36 60 after synthesis. Then, more accura te electrical characteristics wer e measured at the transistor Ids (A) 0 1 2 3 4 5 Vds (V) 0 0.5 1 1.5 10 3 Before After Ids (A) 5 4 3 2 1 0 Vds (V) 1.5 1 0.5 0 10 3 Before After A ) B ) Current (nA) 0 0.25 0 0.25 0.5 Voltage 50 25 25 50 Voltage (V) 0.5
70 level. Fig. 4 10 shows the DC electrical characteristics of individual NMOS and PMOS transistors before and after the CNT growth. The tests were performed at room temperature using a Keithley 4200 semiconductor characterization system. The drain current versus drain-source voltage (Ids -Vds) plots show no signifi cant change after the synthesis, demonstrating the CMOS compatibility of this integration approach. It should be noted that after a short period (approximate ly became infinite. stayed almost the same after one year. These two synthesis experiments used the same catalyst recipe and same growth procedure The differences come from the electrode material which result s in two types of c ontacts: one is polysilicon/CNTs versus Pt/CNTs, and the other is polysilicon/catalyst versus Pt/catalyst. There might be two reasons that cause the failure. First, it might be the result of the continuous oxidation of the polysilicon in air. Another possible reason might be due to the weaker adhesion of the CNT s and catalyst particles to the polysilicon In our practice, the nanometer -scale iron catalyst particles are separa ted by and supported on alumina a thin non -conductive layer As shown in Fig. 4 1 1 the catalyst on the top of the silicon dioxide surface consists of discrete particles with heate r outline clearly visible (Fig. 4 1 1 A ); the catalyst on the top of the pl atinum surface has a fluffy appearance, with the underneath platinum electrode partially exposed (Fig. 41 1 B). However, the catalyst layer appears much thicker on CMOS c hips, as evident from Fig. 4 11 C F The catalyst layer extends over trenches (Fig. 411 C). A thick catalyst layer on one of the heaters even cracks and peels off (Fig. 411 D ). Some designed shapes ( e.g. the multi tip landing wall) that have successfully survived the post CMOS fabrication (Fig. 4 11 E ) are unable to be preserved after ca talyst deposition (Fig. 4 11 F ). The mock CMOS devices have
71 Figure 4 1 1 SEM images s howing the catalyst layers on A ) silicon dioxide surface B ) plat inum microheater surface, and C ) pol ysilicon microheater surface. D ) An SEM image of one polysilicon microheater with thi ck catalyst layer peeled off. E) and F ) SEM images of one polysilicon microheater before and after catalyst deposition. Multi -figure structure was completely c overed by the catalyst layer. G) and H ) Schemat ic cross -sectional views of mock CMOS platinum heater and polysilicon heater embedded in CMOS chips. Catalyst layer 100 nm B ) 10 m D ) 1 m C ) 10 m 2 0 m E ) 10 m F ) A ) 1 m H ) G )
72 on -surface platinum microheaters (Fig. 4 11 G ), while the CMOS chips have polysilicon microheaters hidden insid e the micro -cavities (Fig. 4 11 H ). The top ographic profiles, the surface condition of different materials, and the further miniaturized feature size might all contribute to the thicker catalyst layer, which in return might block the nanotube/polysilicon contacts or result in weak adherence when CN T s reach the secondary electrode. To improve the chemical stability and mechanical robustness, several possible solutions are recommended for the future work. First, instead of using aluminum -supported iron catalyst particles and drop -d rying method, thin film metal catalysts can be deposited using various techniques such as evaporation, sputtering or molecular beam epitaxy technique  These thin films will ball up and break up into particles dur ing the growth as long as the film thickness does not exceed the critical thickness  In this way, the structure shape can be preserved, and the thickness of the catalyst layer can be controlled. Second, contact activation through electrical breakdown in the inert gas environment has been proved to be effective for healing the 2 nm native oxide  which should be employed for our future contact resistance investigations. Third, polymer deposition after the CNT growth has been reported to be capable of stabilizing the nanotube/electrode contact resistances  This coating might be helpful for preventing the polysilicon from oxidation over time. 4.5 Summary This chapter first presented the concept of the C MOS integrated CNTs and discussed the integration principles in Section 4.1. FEM modeling of the 3 3 done to estimate the working temperature. Based on the simulation result, various designs of microheaters were presented and discussed. Then a 1.5 1.5 mm2 chip layout, including test circuits and 13 embedded microheaters, was revealed. In Section 4.2, a novel maskless post CMOS MEMS fabrication process flow was discussed in detail. The temperature dependent
73 resistivity and the electrical characteristics of the polysilicon microheaters were theoretically discussed. The released microheater was tested and compared with the results reported in the literature. Then on-chip CNT synthesis process was presented in Section 4.3. Both th e CNT s and the transistors were characterized and evaluated in Section 4.4. Observed catalyst and contact resistance problems were discussed, followed by some recommendations for future work. This monolithic CMOS CNT integration approach is fully compatible with commercial foundry processes, and requires no photolithography or metal deposition steps. It has been demonstrated that CNT s can be synthesized on specific positions determined by local temperature and E -field distribution, without deteriorating th e neighboring CMOS circuits. This simple, scalable and low -cost integration approach opens up the possibility of integrating CNTs with commercial foundry CMOS circuit ry for emerging hybrid nanoelectronics applications.
74 CHAPTER 5 FUTURE WORK As mentioned i n Section 4.5, the monolithic CMOS CNT integration approach proposed in this thesis is promising for making various nano devices and integrated micro/nano -systems. However, the research work done so far serves primarily as a foundation and a preliminary st age of exploration to demonstrate the possibility. To realize the large scale manufacture of the functional CMOS CNT hybrid device s with high yield and high performance the most important fut ure work that needs to be done are the CNT synthesis control and contact improvement. First, synthesis process could be better controlled. I n future designs, thin film metal catalysts should be investigated, and compared with drop drying method to find out the best recipe. A 15 minutes growth process was used in our pr evious attempts. In future experiments, electrical parameters, such as the resistance between the microheater and the secondary electrode, could be in situ monitored to indicate the accomplishment of the CNT assembly process The resistance will change fro m infinite to the resistance of the first bridging nanotube and decrease continuously once more nanotubes are electrically connected to the secondary electrode. Thus, the quantity of the assembled nanotubes could be counted and controlled. It will be very helpful for individual nanotube characterization. In our previous growth experiments, there were numerous parallel nanotubes, so the test results were the outcomes of a mixture. With one single nanotube on each device, the properties of individual nanotub e could be better characterized under electrical gating and the relation of grow model and contact resistance could be further investigated. Second, several post -growth treatments could be investigated in the future work. C ontact activation through electr ical breakdown could be employed to heal the native oxide on the surface of the polysilicon microheaters. Experiments should be done to find out the dominant
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87 BIOGRAPHICAL SKETCH Ying Zhou became interested in scientific research in high school a nd won the first prize in the Chinese National Chemistry Olympic Contest for High School Students After graduating high school she enrolled at Fudan University in the fall of 2003. As an undergraduate at Fudan University, she participated in various proje cts including nanoparticle -based electrochemical DNA sensor research. In the fall of 2007, she received her B.S. in Microelectronics from Fudan University, and then enrolled at the University of Florida and joined the Interdisciplinary Microsystems Group ( IMG) in the Department of Electrical and Computer Engineering. Her M.S. thesis research involved the design, modeling, and fabrication of onchip microheaters, as well as the synthesis and characterization of C MOS integrated carbon nanotubes. She entered a joint master program in June 2008, and will receive her M.S. in E lectrical Engineering in August 2009 and M.S. in Management in the fall of 2009. After graduation, she will continue her education with the pursuit of the Ph.D. in b usiness with a concentrat ion in a ccounting at UF.