Citation
Decoding-Aware Compression Techniques for Reconfigurable Systems

Material Information

Title:
Decoding-Aware Compression Techniques for Reconfigurable Systems
Creator:
Murthy, Chetan
Place of Publication:
[Gainesville, Fla.]
Publisher:
University of Florida
Publication Date:
Language:
english
Physical Description:
1 electronic resource ; 65 pages

Thesis/Dissertation Information

Degree:
Master's ( M.S.)
Degree Grantor:
University of Florida
Degree Disciplines:
Computer Engineering
Computer and Information Science and Engineering
Committee Chair:
Mishra, Prabhat
Committee Members:
Xia, Ye
Entezari, Alireza
Graduation Date:
12/19/2008

Subjects

Subjects / Keywords:
Algorithms ( jstor )
Bytes ( jstor )
Compression ratio ( jstor )
Computer memory ( jstor )
Decryption ( jstor )
Engines ( jstor )
Maps ( jstor )
Mathematical vectors ( jstor )
Pressure reduction ( jstor )
Vertices ( jstor )
Computer and Information Science and Engineering -- Dissertations, Academic -- UF
aware, bitmask, chetan, compression, control, decode, decoding, decompression, dictionary, fpga, huffman, lzss, mishra, murthy, nisc, parallel, parameter, prabhat, reconfigurable, rle, word
Genre:
Electronic Thesis or Dissertation
Computer Engineering thesis, M.S

Notes

Abstract:
In recent years FPGAs are widely used in reconfigurable systems. Field programmable gate arrays (FPGAs) are configured using bitstreams often loaded from memory. Configuration data is reaching megabytes because of multiple versions of an IP core are configured on a single FPGA and sometimes because of the multiple IP cores. Limited configuration memory restricts the number of IP core bitstreams that can be stored. Moreover slower memory and limited communication bandwidth limit how frequently IP cores can be configured. One promising direction is to compress these bitstreams. Most of the compression techniques exploit redundancies to compress multiple bitstreams but are not suitable for realtime decompression. Other techniques focus on accelerating decompression but compromises compression efficiency. It is a major challenge to design a compression technique which efficiently reduces bitstream size, meanwhile keeping decompression overhead minimal. Our study proposes a novel bitstream compression technique efficiently combining bitmask and run length encoding for better compression ratio and smart rearrangement of compressed bits for fast decoding. Our study's main contributions are i) decoding aware dictionary selection to increase dictionary coverage, ii) run length encoding of repetitive patterns to reduce compressed size, iii) efficient encoding scheme for storing least frequently changing bits and, iv) smart rearrangement of compressed bits into fixed length words that can significantly decrease the decompression overhead. Hard to compress benchmarks are chosen which are widely used IP cores from image processing and encryption domain to show the usefulness of this technique. The proposed technique outperforms the compression ratio of existing techniques by 5 to 15% and decompression hardware is capable of operating at 200 MHz, the best known operating speed for FPGA based decompressor. Our study also analyzes the application of an enhanced version of proposed bitstream compression technique to compress no instruction set computer (NISC) control words. Results show an improvement in compression ratio by 15 to 20% without adding any decompression overhead.
Statement of Responsibility:
by Cheatan Murthy

Record Information

Source Institution:
UFRGP
Rights Management:
Copyright Chetan Murthy. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Embargo Date:
12/31/2010
Resource Identifier:
695699118 ( OCLC )

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