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Signal-Strength Indicators and High-Speed Samplers for Embedded Test of Mixed-Signal Integrated Circuits

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Title:
Signal-Strength Indicators and High-Speed Samplers for Embedded Test of Mixed-Signal Integrated Circuits
Creator:
Puligundla, Sudeep
Place of Publication:
[Gainesville, Fla.]
Publisher:
University of Florida
Publication Date:
Language:
english
Physical Description:
1 online resource (131 p.)

Thesis/Dissertation Information

Degree:
Doctorate ( Ph.D.)
Degree Grantor:
University of Florida
Degree Disciplines:
Electrical and Computer Engineering
Committee Chair:
Eisenstadt, William R.
Committee Members:
Bashirullah, Rizwan
Harris, John G.
Welt, Bruce A.

Subjects

Subjects / Keywords:
Amplifiers ( jstor )
Architectural design ( jstor )
Delay circuits ( jstor )
Delay lines ( jstor )
Electric potential ( jstor )
Noise spectra ( jstor )
Propagation delay ( jstor )
Signals ( jstor )
Transistors ( jstor )
Vibration ( jstor )
Electrical and Computer Engineering -- Dissertations, Academic -- UF
amplifiers, architecture, built, delay, embedded, high, in, indicators, limiting, line, logarithmic, samplers, signal, snapshot, speed, strength, test, vernier
Genre:
Electronic Thesis or Dissertation
bibliography ( marcgt )
theses ( marcgt )
government publication (state, provincial, terriorial, dependent) ( marcgt )
Electrical and Computer Engineering thesis, Ph.D.

Notes

Abstract:
Over the past decade, advancements in areas of semiconductor device physics, IC manufacturing and integration technologies on silicon have considerably increased the operating frequencies (ft) of transistors in the deep sub-micron regime. This enabled design engineers to design circuits that operate at high frequencies and use high-speed clock signals, both leading to increased signal-integrity problems for test engineers responsible for testing and validating integrated circuits. While the design community is able to push the design envelope far into the future, production IC test equipment has not kept pace with test requirements of high-speed, integrated wireless and wired communications designs. This explosive improvement of design performance has made testing of high-speed analog/mixed-signal circuits very challenging, particularly under the constraints of high quality and low price. In order to perform effective signal analysis and tests on such high frequency on-chip signals, one should be able to export those signals off-chip. However, exporting high-frequency on-chip signals off-chip without degrading the signal quality of the signals is not easy. A less attractive solution to this problem is to replace low cost testers with very expensive Automatic Test Equipment (ATE) systems and measurement equipment such as pico-probes and E-beam probes. The electronics industry is ready to welcome any solution that can substantially reduce the cost and time involved in testing its integrated circuits. Embedded test or Built-in-Test is a potential solution to face the challenges posed to the test community in the high-frequency domain. This method helps to keep up with the pace of the growing complexity of tests. Embedded test reduces the time to production without increasing the test cost and enables the use of low-cost testers, already on the factory floor, efficiently. However, there is some increase in chip die area and production chip cost. The fundamental idea in this solution is to move some of the external high-speed and high-bandwidth test functions on to the chip. This move, however, is not that simple, and still is in the development stage. This work involved development of some efficient test circuitry that could reside along with the Device-Under-Test (DUT) on the same die. These embedded test circuits help in extracting useful information from high-frequency on-chip signals and converting them to low-frequency (base-band) signals for easy transfer of information off-chip for post processing on an external, low cost, low frequency ATE. On-chip signal shape capturing circuits using high-speed samplers and on-chip signal strength measurement circuits were developed that can be used in embedded test of mixed-signal integrated circuits. ( en )
General Note:
In the series University of Florida Digital Collections.
General Note:
Includes vita.
Bibliography:
Includes bibliographical references.
General Note:
Description based on online resource; title from PDF title page.
General Note:
This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Thesis:
Thesis (Ph.D.)--University of Florida, 2007.
General Note:
Adviser: Eisenstadt, William R.
General Note:
RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2016-05-31
Statement of Responsibility:
by Sudeep Puligundla.

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Source Institution:
UFRGP
Rights Management:
Copyright Sudeep Puligundla. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Embargo Date:
12/31/2016
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4.3.1 The Sub-Sampling Technique


Exporting on-chip high-speed signals off-chip without degrading the signal quality poses



an interesting challenge in today's design environments. Measuring high-speed waveforms is




HighSpeedlO OLLVDL schematic : Jul 22 23:24:20 2007
Transient Response
800m : /Vot
600m







1.10
700m -
400m







1.50 : /c k2





--o-~










Transn Repon

1.30 1 /ci2







700m









300 n /


100rn .



105.870n 105,890n 105910n 105.930n 105,950n






Figure 4-11. Simulations of DLL based VDL. A) Vctrl, CLK1, and CLK2 signals. B) Time
separation between CLK1 and CLK2
10570r 1~r~ 059~ 159~r~ 0590,
tlh (l




Fiue41.Smlton fDLbsdVL A crCKadCL2sgas )Tm











Samples from
Sth sampler


ITTT l T iT





f- om E-J s_


raoml st
sampler


I


Figure A-3. Sampling instants with same 't' between samplers and irregular 't' between
samplers.

Therefore, we can write (A-1) as,


1 1 p -1


1 1 (+l-)p k f


km2ff 2p-1 2-k2 tt -k 2ff
e- KK+)Ye- Kt]e-
m=p

-re K 0-


np-I1
e
m=(n-l)p


1 1 "- o-k ,(,+)p-1
t LK K ..t p
=t e e
k=- i=u0 m=-p


jkm 2(i) ) j
-kt


(A-2)


For the case of sinusoidal input, X (co)=27i6(c-co)) the above equation can be written as


n-1 \ o+k 2, t t(+l)p-1
t
k=-c 1=0 m= 1p


k=-., 1=0 m=2p


Jk(m-t )2 O 2 )
e 2 CO mo -
(',N\/2N

]]29rw co Ky-)),


*^\nLa ,,-{


That is the digital spectrum is represented by the following equation.


e ( m ] -k j)
Kt









N stages in its voltage controlled delay line and DLL 2 has M stages in its voltage controlled

delay line. When the DLLs are in locked state, the delay from each stage in DLL 1 is equal to

T/N and delay from each stage in DLL 2 is equal to T/M.



DLL 1 (VCDL= N Stages)




Ref. Clk CLK1 (Event triggering Clock)
Multiiplexer
CLK2 (Sampling Clock)




DLL 2 (VCDL = M Stages)



Figure 4-10. Delay locked loop based Vernier delay line

Therefore, the time delay between the event-triggering clock and sampling clock is given

by (T/N-T/M). Simulations have been performed on such a Vernier delay line with DLL 1

having 14 stages and DLL 2 having 16 stages. Simulation results for an input clock signal of

frequency 625MHz show a minimum separation of 14.3ps as shown in Figure 4-11. Figure 4-

11(A) shows the control voltage of the DLL and the CLK1 and CLK2. Figure 4-1 1(B) zooms the

time difference between them.

4.3 High-Speed Samplers

The following subsection briefly reviews the sub-sampling technique commonly used in

sampling oscilloscopes and testing sampling switches. Designs of high-speed samplers to

reliably sample signals that extend beyond supply are discussed following this subsection.









Figure 4-24 shows the layout of the entire chip. A stand-alone sampler is used for

calibration purposes. Measurement results from this stand-alone sampler are explained here.

Measurements have been recorded for an input sinusoidal signal of frequency 155MHz and a

sampling clock frequency of 150MHz. Therefore, the output signal from the sampling switches

should be a 5MHz signal corresponding to the beat frequency of the input signal and the

sampling clock (Figure 4-25).


Samplers Up & o/p pads


Samplers





SV I &VS

I0 VSS & VSS


Core VDD & VSS


Drive
a10 S &DrlvS
I0 VSS & V'SS


Figure 4-24. Layout of the chip (IBM7WL 0.18um process)

Ph mc fkl flaw MNM -b Vtai Hita


Figure 4-25. Output sub-sampled signal (frequency = 5MHz)


6 M









speed tests on the ICs adds enormously to the overall test cost involved and leads to the case

where test cost exceeds manufacturing cost. In brief, it is vital to perform low cost but at-speed

chip/package/board observation of high-speed circuit's performance prior to IC prototyping.

1.2.4 Time Involved in IC Test

Time to market is a pressing issue because profit margins for a new product are highest

shortly after it has been released to the market. Margins begin to shrink as competitors introduce

similar products at lower prices. The lack of a complete, cost-effective test methodology is often

a bottleneck preventing the release of a new product for profitable volume production. In the

case of I/O verification experiments which are limited and under extreme time pressure,

unexpected loading parasitics, mismatches and coupling in the packages and boards add weeks

or months and can make a new digital IC miss its profitable market window. Mainframe ATE

systems are designed to minimize test time and maximize overall product throughput. Figure 1-6

shows the relationships between test cost and test time; the information source is from IBM test

development group [IBM02]. The comparison is made between a $2M tester and a $100K tester.

The plots show that the test cost/part is entirely a function of time. Total test time includes tester

capability/speed (electrical test time), handler/tester/controller communications time, handler

capability and index time of handler. One second of test time can cost three to ten cents. This

may not seem expensive at first glance, but when test costs are multiplied by millions of devices

a year the numbers add up quickly. For example from the available data in Figure 1-6, a four-

second test program costing approximately sixteen cents per part on a $2M tester and nine cents

per part on a $100K tester times one million devices per quarter costs a company $640,000 and

$360,000 respectively per year in bottom-line profit.

As a result, the test community is not able to keep pace with the test requirements of high-

speed, integrated wireless and wired communication designs. It is time to look for innovative










5.6 Application in Substrate Noise Measurement

Logarithmic amplifiers can be used in the measurement of substrate noise. As shown in

Figure 5-18, a broadband embedded measurement technique has been proposed to measure and

characterize substrate noise in RF/microwave ICs [He06]. Substrate noise is introduced by

injecting well-defined signal from an external signal source into the substrate. An external LO

signal is supplied to the on-chip mixer at a frequency slightly offset from the injected signal

frequency. The detected signal is down-converted to baseband and fed to logarithmic amplifier.

The logarithmic amplifier works as a signal strength indicator and tells the received signal level.

By varying input signal frequency and LO signal frequency correspondingly, substrate noise

coupling over very wide frequency range can be investigated using low-frequency test

equipment. Comparing to a linear AGC-based measurement method, the advantage of such

technique is that it can detect broadband signals and compress a much wider input dynamic

range into a small range at the output.

External External
Signal Source LO


Sub Contact Sub Contact Low-frequency

(Source) (Detector)
output
Down Conversion Log Amp
Mixer

Substrate Noise Coupling


Figure 5-18. Down conversion based substrate noise measurement.

In summary, this chapter presented an important on-chip test circuit that can be embedded

along with the device under test. The signal strength detector circuit described here is fabricated

in a 0.18 um process and occupies very small area. This circuit can be used as a part of a data

analyzing circuit.













Input signal
Period = T




Sampling clock
Period = T+-t




Sub-sampled output
Period = P rT )
(LJT-k'


: i



V : V : V. V




0 ElE Ei
:1
i _
_=_=U:_=


Off-chip reconstruction using software


Figure 4-12. Sub-sampling technique in time-domain

4.3.2 Master-Slave Type Sampling Switches

Figure 4-13 shows the master-slave type sample-and-hold switches commonly used in sub-

sampling oscilloscopes [HAMWMH98]. Dummy transistors are inserted to reduce the channel

charge injection and clock feed-through. Assuming that exactly half of the channel charge is

injected onto the hold capacitor at the output of the sampling switch when it is turned off, the

dummy transistor is designed to be half the size of the sampling transistor [RazO1]. A separate

non-overlapping clock generator is used to generate the clock phases phil, phi2 and their

complementary signals. It is essential to have non-overlapping clocks in order to guarantee

charge is not inadvertently lost.

















































U.J
-120 -100 -80 -60 -40 -20 0
Input Power (dBm)


Figure 5-17. Measurement results. A) Measured RSSI output. B) Output error curve.


1 .5



1



0.5



0





0
1 -0.5







-1.5



-2



-2.5
-12


0


-100 -80 -60 -40
Input Power (dBm)


-20 0


Figure 5-17. Continued.


Measurement
Simulation

.. ...................... ........................: .. ....-





- .



............. ............ ........... ......... ............... ...



. ............. ........... ............. .... ............... ....................



-,.. -,. i . .



-. . . .-.. . . . .. .. .. .. .


I"l









4.3.3 Low-Voltage Bootstrapped Switches

Problems with the conventional sample-and-hold switches discussed previously can be

eliminated with the use of bootstrapped switches [Ste99, AG99, DK01]. Figure 4-15 describes



O > IYADtJfY l
Ron,p Ron,n





Ron,n Ron,p

on,TG







Figure 4-14. Resistance variation ofNMOS, PMOS, and a TG. A) Vdd > |Vtnl + |Vtpl. B) Vdd <
|Vtnl + |Vtpl.

the bootstrapping concept that helps in keeping the gate-to-source voltage of the sampling switch

constant when the switch is conducting. The on-resistance of the switch is given by,

Ro, = 1 (4-1)
/U*Co* -(Vgs- Vh)


If the variation in threshold voltage due to bulk effect is neglected then Ron of a

bootstrapped switch is nearly constant. The operation of a bootstrapped switch is described here.

During the off state (phibar), the sampling switch is cut off by connecting its gate to ground

while the capacitor (Cb) is pre-charged to approximately Vdd in this off state. During the on state

(phi), the signal to be measured is applied to the sampling switch and the gate voltage is boosted









Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

SIGNAL-STRENGTH INDICATORS AND HIGH-SPEED SAMPLERS FOR EMBEDDED
TEST OF MIXED-SIGNAL INTEGRATED CIRCUITS

By

Sudeep Puligundla

December 2007

Chair: William R. Eisenstadt
Major: Electrical and Computer Engineering

Over the past decade, advancements in areas of semiconductor device physics, IC

manufacturing and integration technologies on silicon have considerably increased the operating

frequencies (ft) of transistors in the deep sub-micron regime. This enabled design engineers to

design circuits that operate at high frequencies and use high-speed clock signals, both leading to

increased signal-integrity problems for test engineers responsible for testing and validating

integrated circuits. While the design community is able to push the design envelope far into the

future, production IC test equipment has not kept pace with test requirements of high-speed,

integrated wireless and wired communications designs. This explosive improvement of design

performance has made testing of high-speed analog/mixed-signal circuits very challenging,

particularly under the constraints of high quality and low price. In order to perform effective

signal analysis and tests on such high frequency on-chip signals, one should be able to export

those signals off-chip. However, exporting high-frequency on-chip signals off-chip without

degrading the signal quality of the signals is not easy. A less attractive solution to this problem is

to replace low cost testers with very expensive Automatic Test Equipment (ATE) systems and

measurement equipment such as pico-probes and E-beam probes. The electronics industry is









1.2.3 Increased Speeds of Operation

MOS transistors in the deep sub-micron regime have unity gain frequencies in the range of

one hundred gigahertz, indicating a capability for creating signals with high bandwidth internally

on a chip. Also, penetration of high-speed interfaces (Gigabit-per-second I/O) into new designs

is increasing dramatically. The trend toward faster high-speed serial interfaces and an increased

port count will continuously drive the need for efficient methods of high-speed analog/digital

testing. Figure 1-5 shows the current microprocessor's clock frequency trend [Rus04].

10000










LU 100
SentPeniumium


3 ..



1987 1989 1991 1993 1995 1997 1999 2001 2003


Figure 1-5. CPU clock frequency trend Moore's law.

Current test methodologies are challenged by the number of high clock speed nodes in the

circuits. Testing is usually done at less than the circuit's targeted operating speed but a circuit

that passed a low-speed test may fail when operated at full speed. With the advent of SoCs, this

problem is greater than before. High-speed domain testing can be done by resorting to the use of

very expensive high-frequency testers that include specialized membrane probes, picoprobes and

E-beam probers. The usage and in-lab maintenance of this expensive equipment to perform at-










regulators etc that keep the voltage transients within the acceptable range in order to deliver as

much performance as possible while maintaining reliable operation.

Figure 3-1 shows the fluctuations in the power supply of a microprocessor due to large

di/dt and IR events [MTRA04]. The fluctuations are a result of the interaction of the parasitics

with changes in current demand. Clearly, the demands are highest at the clock events.


+ di/dt
+ dildt reliability
event limiter

vcc
nomiin
setting

performance i
limiter .di/dt
event

Low Frequency
Ultra-High Frequency Mid Frequency -1-100 kHz
(not show y High Frequency -1-10 Mhz Source:
o10-100 GHz -100-1000 MHz Source: Motherboard/
Source: Source: Package/Socket/ Voltage Regulator
Die L, C Die/Package L, C Motherboard L, C L, C

Localized Droops Droops observed across the die -
may impact local circuit paths will impact all circuit paths

Figure 3-1. Microprocessor power supply line fluctuations.

Preserving the shape of an on-chip waveform and exporting it off-chip without degrading

signal quality is not easy. An architecture capable of taking snapshots of signals for a certain

length of time following a triggering event is demonstrated in this chapter. Timing issues such as

clock skew, clock jitter and their effects on this architecture are also discussed in detail here.

While this chapter deals with the system analysis, performance, measurement results of the

complete architecture of a device-under-test (on-die interconnect), the next chapter deals with the

circuit design details of individual blocks in the architecture and their stand-alone performances

and measurement details for system characterization.










power plan r

P signal tract
....L


'mriutiplsxeri
* demuliplexurs
muignalgun.
- samples
C teden d
^C 'i ,,ili


-power plane

,tigial Iracas
3/---


Built.off Tt Load Board


Figure 2-1. Load boards for IC test. A) For conventional ATE test. B) For silicon
verification/design deugging, built-off test (BoT). C) For general built-in test (BiT)


Load Board









Also, compared to the earlier architecture, this modified version requires fewer parallel samplers

to capture the same number of signal sample points. The delay line is used to provide two clock

Clock

-*L


Figure 3-2. System Architecture

signals (CLK1, CLK2). The condition on the select signals for the decoder/multiplexer in the

delay line determines the delay between the clock edges of the two signals as shown in Figure 3-

3. The minimum delay between CLK1 and CLK2 is the effective resolution (td) between signal

samples.











phil phil bar phi2 phi2bar
Vin _L


C1 C2 Vout


Cout
Vbias i




Figure 4-13. Master-Slave type Sample-and-Hold circuit

However, the problem with this type of sample-and-hold circuit is that the sampling

transistor's conductance is not constant over the entire supply range. Figure 4-14(A) shows the

variation of the resistance of NMOS and PMOS transistors with supply voltage. Figure 4-14(A)

also shows the resistance variation of a transmission gate. Though transmission gates appear to

have constant resistance for a certain signal range and can potentially replace the MOS

transistors in the switch circuits, they have a non-conducting region in low-Vdd technologies.

The threshold voltages of the devices have not scaled down at the same rate as the supply voltage

because low threshold voltage devices are susceptible to more leakage problems. In technologies

where Vdd is less than the sum of the threshold voltages, a transmission gate has a region of non-

conductance as shown in Figure 4-14(B).

For accurate measurements, switches with constant impedance over the entire signal range

and that can be operated in low-Vdd technologies are needed. The second-generation sampling

switches designed here use TI 65nm technology with a 1.2V power supply. For the reasons

described above, alternate design techniques had to be used for reliable signal measurements.









CHAPTER 4
DELAY GENERATORS AND HIGH-SPEED SAMPLERS

4.1 Introduction

This chapter details the circuit design issues of the sub-blocks used in the architectures

proposed in Chapter 3 for capturing snapshots of events on the die. The discussion here mainly

deals with the design of on-chip samplers, delay generators between parallel samplers, the design

of a Vernier delay line for precise skew generation between the event triggering clock for the

device-under-test and the sampling clock used in the architectures. The prototype demonstrated

in the previous chapter used the AMI 0.5um process technology with a power supply voltage of

5V. As previously discussed, jitter and clock skew in the sampling clock signal gives rise to a

proportional amount of noise in the output spectrum. Gaussian random jitter increases the noise

floor and constant clock skews inject noise spectral powers in the output spectrum along with the

signal power thus reducing the overall signal to noise ratio of the snapshot architecture. These

jitter and clock skew tolerances of the architecture become very stringent and important in deep

sub-micron processes. Therefore, the design of these circuits in state-of-the-art processes

involves the implementation of more robust design techniques.

While measurements are made on the delay elements in AMI 0.5um process designed for

the prototype, circuit design and simulation results of a delay-locked loop based Vernier delay

line and delay chain are presented for a TI 65nm process with a 1.2V power supply. Also,

master-slave type samplers are built and measured in AMI 0.5um process. These circuits are

used as sampling switches in oscilloscope architectures. However, unless an elaborate calibration

method is used, conventional transistor sampling switches cannot be used in testing circuits in

today's low Vdd designs because such switches do not offer constant conductance in the entire

signal range. Also, in low Vdd processes, such switches do not conduct for certain voltages in









Table 3-1 compares various on-chip measurement circuits to capture on-chip signal details

in the available literature with this architecture.

Table 3-1. Comparison of On-chip measurement circuits
This Work
Reference [HAMWMH98] [TMNO2] Prototye
Prototype Simulations
Process 0.25um 0.13um 0.5um 65nm
Sa g Real time Real time
Tehniqe Sub-sampling Sub-sampling or Sub- or Sub-
Technique
sampling sampling
Design
Design Simple Complex Simple Moderate
Complexity
Sampling Rate 35GHz 100GHz 4GHz 70GHz
Target High-Speed Substrate High- High-Speed
Measurement signals noise Speed Signals
signals
Beyond Full Beyond
Input Range Full Swing Beyond Full Beyond
Supply Swing Supply


In summary, the architectures discussed in this chapter can be used as on-chip

measurement circuits. They have been verified behaviorally in MATLAB and the system

performance is demonstrated for a device-under-test (8mm long interconnect). The degradation

of a signal transmitted along the DUT is reproduced by the architecture and compared with the

measurement from a real time oscilloscope. The next chapter presents the circuit designs and

measurement results of individual blocks in the architecture. The characterization of timing

information of these sub-blocks is essential for reconstructing the signal from the input signal

samples obtained by the snapshot architecture.









In Chapter 2, the differences between Digital BIST and analog/mixed-signal BIST are

discussed before introducing the current approaches in Analog/Mixed-Signal (AMS) embedded

test and the concept of alternate test using feature-extracting circuits. The importance of area

efficient signal feature extracting circuits that enable alternate test in the BIT is explained. These

feature extractors reside on the same die as the device under test (DUT). Motivation and

contributions of this research work to the areas of integrated circuit testing is described in this

chapter. On-chip signal waveform shape capturing circuits and on-die signal strength detectors

are developed as a part of this work. The scope of this research and its goals are discussed.

Chapter 3 describes novel architectures proposed for capturing on-chip events following a

triggering event. Complete analysis involving timing issues and the effects of timing errors on

the performance of specific architectures is described. Mathematical observations and system

analysis are verified by modeling and simulating the architectures in MATLAB. Prototypes of

the circuit are designed using AMI 0.6um process and this chapter describes the measurement

results of the performance of the circuit in capturing an event on the DUT (on-chip interconnect).

Design of delay generators and reliable high-speed samplers that can be used in the

architectures presented in Chapter 3 are discussed in detail in Chapter 4. While the prototypes of

the snapshot architecture are fabricated using AMI 0.6um process, design techniques for the

circuit in state-of-the-art processes such as 0. 18um technology and 65nm technology are also

discussed in this chapter. Improved switches using bootstrapping technique are introduced in this

chapter for sampling signals that extend beyond supply range (overshoots and undershoots). As

an application, the use of such switches in observing on-die signals in high-speed I/O circuits is

presented.









[RazO1] B. Razavi. Design of Analog CMOS Integrated Circuits. McGraw-Hill,
New York, 2001.

[Rus04] S. Rusu. Trends and Challenges in High-Performance Microprocessor
Design. Electronic Design Processes, Monterey, CA, April, 2004.

[SAW90] M. Shinagawa, Y. Akazawa, and T. Wakimoto. Jitter Analysis of High-
Speed Sampling Systems. IEEE Journal of Solid-State Circuits, vol. 25,
no. 1, pp. 220-224, February, 1990.

[Ste99] J. Steensgaard. Bootstrapped low-voltage analog switches. Proceedings of
IEEE International Symp. On Circuits and Systems, vol. 2, pp 29-32,
1999.

[SZ03] K. L. Shepard and Y. Zheng. On-chip oscilloscopes for noninvasive time-
domain measurement of waveforms in digital integrated circuits. IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11,
issue 3, pp. 336-344, June 2003.

[TMN02] M. Takamiya, M. Mizuno, and K. Nakamura. An On-Chip 100GHz
Sampling Rate 8-channel Sampling oscilloscope with embedded sampling
clock generator. ISSCC, Session 11, TD: RF/High-Speed Technologies,
2002.

[VB04] B. Vrignon and S. Bendhia. On-chip Sampling sensors for high frequency
signals measurement: evolution and improvements. Proceedings of the
fifth IEEE International Caracas Conference on devices, circuits and
systems, Dominican Republic, November, 2004.

[VC98] P. Variyam and A. Chatterjee. Enhancing test effectiveness for analog
circuits using synthesized measurements. 16th IEEE Proceedings VLSI
Test Symposium, pp. 132-137, April 1998.

[VCOO] P. Variyam and A. Chatterjee. Specification Driven Test Generation for
Analog Circuits. IEEE Transactions on Computer Aided Design of
Integrated Circuits and Systems, vol. 19, no, 10, pp. 1189-1201, October
2000.

[VCC02] P. Variyam, S. Cherubal, and A. Chatterjee. Prediction of analog
performance parameters using fast transient testing. IEEE Transactions on
Computer Aided Design ofIntegrated Circuits and Systems, vol. 21, no. 3,
pp. 349-361, March 2002.

[Vin98] B. Vinnakota. Analog and Mixed-Signal Test. Prentice Hall PTR, Upper
Saddle River, New Jersey, 1998.








X t( 1 octo 2e +e m ot e npm ... ott l t e- k_ np m 2 -27r
X eoet(cL)C-CO... k t
k=-m m=0 mp m=(nl)p


(A-3)









CHAPTER 6
SUMMARY AND FUTURE WORK

6.1 Summary

Important contributions of this work to the field of analog/mixed-signal test are

summarized in this chapter. The goal of this research was to develop measurement circuits that

can be embedded on the chip for both built-in and built-off test strategies. Information extracted

from signals in the circuit-under-test by these measurement circuits can be analyzed to evaluate

the circuit's performance and reliability.

Existing approaches for analog/mixed-signal test such as direct measurement of circuit

specification and indirect measurement based on alternate test are described in Chapter 2.

Architecture for capturing on-die events is proposed in Chapter 3 and is completely analyzed. By

using a Vernier delay line for fine spacing between the sample points, it is observed that noise

spectral lines, due to non-uniform sampling, can be reduced. Mathematical derivation of this

observation is included in the appendix. Measurement results of the architecture are described by

measuring a part of the clock signal at the end of a long 8mm interconnect. The parasitics of the

interconnect cause overshoots and undershoots on the signal and the shape of such a signal is

reconstructed off-chip by the samples from the parallel samplers. The prototype system is built in

AMI 0.5um process with a power supply of 5V. Circuit design suggestions are made for

advanced processes such as a 65nm process with a power supply of 1.2V. In these advanced

processes, jitter and skew tolerances are very important for they have adverse effects on the

signal to noise ratio of the reconstructed signal. An improved switch based on bootstrapping

technique is designed to sample signals that extend beyond the supply.

Finally, on-chip measurement techniques are discussed in Chapter 5. A signal strength

detector with an input dynamic range of more than 75dB based on successive detection










Vernier Delay Line to generate delays CLK1
between CLK1 and CLK2
Clock
CLK1: Event triggering Clock Signal CLK2
CLK2: Sampling Clock Signal

.1 -- --- M
CLK2

control inputs to select delay between cdk and dk2
2 cases of different delays between ck1 and clk2










DUT



03











I


Figure 3-5. Modified system architecture

parallel samplers. The occurrence of such deviations in the sampling instants gives rise to a time-

distorted output signal. Clock skew and clock jitter are two different terms that describe different

effects on the architecture's performance. While clock skew is defined as a constant timing offset

in the sampling edge of the clock from the ideal sampling edge, clock jitter is a random


















-10

-20

-30

-40

S-50

-60

-70

-80

-90


-10

-20

-30

S-40

I -50
eo
-60

-70

-80

-90

-100


01 02 03 0.4 0.5 0.6 07 08 09
a

-i














0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Normaized frequency


. .. ; ;.. .. . .. .







... .. . .... ... . ..









... .. ........... ....... .... ..... i
.1h. ;,A ... Al 11 l I .: I I I11 .. k, I


Normaizea Trequency


Figure 3-7. MATLAB simulations forjitter. A) Jitter-free sampling. B) Sampling with jitter


architecture using a Vernier delay line. A mathematical expression is derived to prove this effect



of the Vernier delay line on the system's performance. The mathematical observations are then



verified with modeling and simulating the architecture including clock skew and jitter effects in



MATLAB. As sinusoidal signals play an important role in signal analysis, the following analysis



is discussed for a sinusoidal input signal V,,(t)= A sin(2fot).


.I .. .. .I .J I..
. ... .

. i. ... .



. .,. ... ,


.. . .













'" ''" '"."" '''" '""."'"









for a buffer design that provides the measurement circuit with the signal without having the

circuit load the node that is probed. If the signals to be sampled have rail-to-rail swings, then

techniques such as voltage division, or higher supply for the buffer circuit can be explored.

Reducing system jitter and increasing output SNR: In Chapter 3, effects of timing

errors are discussed on the measurement circuit's output signal-to-noise ratio. In a deep sub-

micron manufacturing processes, tolerances of jitter and clock skew errors are very limited. In

such tight constraints, delay-locked loop and Vernier delay lines based on DLLs can produce

delays and clock signals with reduced jitter and skews. A delay-locked loop based Vernier delay

line has been simulated in 65nm process with a 1.2V power supply.

Reducing silicon area, most important test metric in embedded test: The prototype

demonstrated in this work uses 10 parallel samplers, and voltages on each channel are exported

off-chip via a bond pad. Bond pads occupy a lot of silicon area. This problem can be addressed

by multiplexing the outputs via n: 1 analog multiplexer. The voltages from the channels can be

converted to corresponding currents using a single gm device in each channel and the currents

can be multiplexed via analog current mirrors to a single bond pad. This reduces the silicon area

required by the system by a huge factor.

All the above discussions regarding future work are shown in Figure 6-1. Exploring and

addressing these issues in this may allow this to be an inexpensive solution to measuring on-chip

signals.









Design-for-test (DfT) is a major topic of interest in the testing field. Any circuit design that

results in a more easily or thoroughly testable product can be categorized as DfT. There are

many types of DfT. Some DfT concepts are based on built-in circuits that allow easier or more

complete testing. The choice of DfT approach depends very much on the specifics of the device

under test (DUT) and the demands placed on it by its system-level application. Built in self-test

(BIST) or embedded test circuits allow the device-under-test (DUT) to self-evaluate quality

without elaborate automated test equipment (ATE) support. With BIST, low cost testers can be

used to perform high-speed IC testing. The limited tester resources required by BIST and the

ability to perform parallel testing of multiple circuits on the DUT are key advantages of BIST-

based testing methodologies. The fundamental approach in embedded test or BIST is to move

very high-speed test functions on-chip, thus reducing the requirement of and the cost of the

external test. This move, however, is not straightforward, and still in the development stage.

Analog BIST technology has lagged behind digital BIST because of difficulties in guaranteeing

accurate signals generated and measured on-chip. However, analog embedded test techniques

will improve the circuit controllability and circuit observability.

1.4 Organization of the Dissertation

This section describes the organization of the dissertation. The work presented here

concentrates on the solutions to issues arising from the need for developing efficient test methods

for high-speed digital/analog integrated circuits.

The current chapter (Chapter 1) introduces the reader to the background of testing

integrated circuits using ATE systems, and cost involved in such solutions. This is followed by

the challenges that the test community is facing in the sub-micron regime. Built-in-test (BIT) or

embedded test is briefly introduced and discussed as a potential solution for such challenges.









clock signal degradation after transmission through this long interconnect is reproduced by the

snapshot architecture. The loading of the measurement circuit at the end of the interconnect was

not a problem as the input capacitance of the circuit was a lot lower than the capacitance of the

8mm long interconnect. The samples obtained from the parallel architecture are interlaced based

on the timing information obtained by characterizing each sub-block used in the architecture.

These characterization results are shown in the next chapter when the design of each sub block is

considered individually. After interlacing the samples, the shape of the signal reproduced from

the measurement circuit is then compared with the shape displayed on a real-time oscilloscope

using a high-impedance probing method.





On-Cdp Snapshot
A tailecture '



DUT Interconnect (Length L)
--------- Comp
-------------------------------------------i






Expensive RT Scope

DUT Interconnect (Length L)

Figure 3-18. Strategy of waveform comparison (DUT 8mm long interconenct)

Figure 3-19 (A) shows the clock signal at the end of the DUT captured on a real-time

oscilloscope with a high-impedance probe. The part of the signal of interest here is enlarged in

Figure 3-19 (B). The length of the signal of interest here is approximately 15ns, which was

compared to the signal obtained from the measurement circuit.











each set having p=2m samples that are off from their ideal sampling instants by the same amount.


Here, 'm' is the number of control bits to the delay line.


samples from
5th sampler








from 1 st
sampler
-t


1 samples from
4 t4th sampler


A; \ I It


from 1 st
sampler


-s -^


Figure 3-12. Same 't' between samplers ideal case and irregular 't' between samplers

Considering this effect of the Vernier delay line in Equation 3-5, we can derive the


following for a sinusoidal input whose spectrum is given by X (co)=276(co-c 0). For complete


derivation of (3-7), refer to appendix a.


p1 p1 -Jk2i m 2p-1 -Jk 2m "np-1 -jk 2 m 2
X,()= Y + e-+O d Ye0 +e- d np + .. 0- e np 2 _
d k=- m=0 m=p m=(n-l)p Ktd



(3-7)


where ti, i = 0,1,2,..,(n-1) are the offsets for each one of the 'n' sets of samples.









Constraints for different voltages in an MOS transistor [AG99]:

Oxide breakdown: Vox < Ebd tox

Gate-Induced drain leakage: Vgd < Egidi tox +1.2V VFB

Vds < Vdsat(L) + Ec (12 + ILDD)
Hot electron effects:
12 = 0.2toLX/2

NsubL3
Punch-through mechanism: Vds < Vp oc
Xj + 3to

where, tox is thickness of gate oxide, Ebd is typically 5mV/cm, Egidl is the electric field in

the oxide that induces GIDL currents, VFB is transistor's flat-band voltage, Xj is the drain/source

junction depth, ILDD is the effective length of the lightly doped drain.

4.3.3 Improved Bootstrapped Switch

Figure 4-16 shows the conventional bootstrap switch. Transistor N1 performs the actual

sampling and the rest of the circuit is used to boost the gate voltage of N1 to keep its gate to

source voltage constant and to keep the relative terminal voltages of the transistors small enough

for reliable operation. However, the circuit described in Figure 4-16 cannot be used for sampling

input voltages larger than the supply voltage. During the on state (phi) input voltage is applied to

the drain of the PMOS transistor P2. If this input voltage is larger than the bulk potential of P2

(equal to Vdd in this design) it can forward bias the p-n diode at the junction between the

source/drain and the well of the transistor P2 [AASM05]. Such a forward bias could damage the

circuit permanently. This problem can be avoided by exploiting the ability to connect the well

potential of a PMOS to any appropriate voltage in an n-well process. A voltage larger than Vdd

has to be generated on the chip to which the bulk of this PMOS (P2) can be connected.

A charge pump circuit shown in Figure 4-17 can be used to achieve this requirement. The

operation of this circuit can be explained as follows. When phibar changes from low to high













is due to random Gaussian jitter. Reduction in the number of noise spectral lines can be seen by


the architecture using ideal Vernier delay line.


Case i: Simulation of architecture without VDL. Observation: Total number of spectral


lines [0,fs/2] = 8; 1 signal and 7 noise


Case ii: Simulation of modified version; n = 4, p = 2. Observation: number of spectral


lines [0,fs/2] = 7; 1 signal and 6 noise; (p-1) = 1 less from Case i.


Case iii: Simulation of modified version; n = 2, p = 4. Observation: number of spectral


lines [0,fs/2] = 5; 1 signal and 4 noise; (p-) = 3 less from Case i.



-10 ............ ............... ........... .. .............

-20 . .. .

-30
-40 . .
-5 0 .. .. ... .. .... .. .. .. ... .


-60 . .. . .
-40 ...



-90

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Normalized frequency



Figure 3-14. Spectrum of output signal


0


-20 . .

-30

-40 .

o -50 .. ... ... ... ....... .
S-60 .

-7 0 . .... .. ... .. : .. ....



-90
-100
0 01 02 0.3 04 05 0.6 0.7 08 0.9 1
Normalized frequency



Figure 3-15. Spectrum of output signal (n=4, p=2)









td = minimum delay between CLK1 and CLK2;

m = number of select bits to the decoder/multiplexer in the VDL.

Figure 3-4 compares the sampling instants of different samples of the signal between the

two architectures. A large number of samples is obtained from the modified architecture for

different select conditions on the Vernier delay line. However, the input signal has to be made

repetitive.

t





01 02 03 04


td t

B



L,_ LI L__ LI__

samples from 01 for
different select conditions \
samples from 02 for
different select conditions

Figure 3-4. Comparison of sampling instants. A) First architecture. B) Modified architecture.

Another important advantage of the modified architecture is it has less noise due to timing

errors in the sampling instants if the Vernier delay line generates exact integral multiples of

minimum delay (td) for different select conditions. This is explained later in the discussion about

clock skew.

3.3 Errors in Timing Instants of the Samplers

This section discusses the effects on the output signal from the snapshot architecture due to

errors/offsets in actual timing instants from ideal instants (i.e., clock skew, clock jitter) for the









connected loads is shown in Figure 5-7(a). Assuming a perfectly balanced source-coupled pair,

the small-signal differential gain of this topology can be derived using the half-circuit concept as

gm (WI L),
A-= g" (5-9)
gm,3 (WIL)3

Clearly, the gain is a function of the aspect ratios (device dimensions) of the transistors and

first-order independent from process parameters. However, in deriving Equation 5-9, the body

effect of the load devices is neglected. It is important to note that neglecting gmb of the input

transistors (Ml and M2) from this analysis has no effect on the small-signal gain because the

voltage across the tail current source is constant for a pure differential input and there is no

small-signal change in the voltage from the source to the body of these input transistors. Where

as, the load devices do suffer body effect and causes the small-signal gain of the circuit to

depend not only on gm but also gmb of the NMOS loads. Using a PMOS load would eliminate this

body effect but then the gain would depend on the ratio of mobility, a process parameter of both

NMOS input transistor and PMOS load device. When using a logarithmic amplifier as a detector

of signal strengths in the embedded test of wireless circuits, it is essential that the gain of each

gain cell is independent of process variations and variations in the temperature. This ensures high

accuracy in the detection of the signal strength. This problem is eliminated in the topology

shown in Figure 5-7(b). Though the NMOS loads in this circuit do not suffer body effect, the

gain of such circuit depends on the accuracy of the current mirrors. Other drawbacks include

more area, extra power consumption and degraded frequency response.

A triple-well NMOS transistor used as a load device in a differential pair can eliminate the

body effect and the need for a current mirror. The small-signal gain of such a differential pair is

then a function of device sizes only. Another important advantage of this topology is by using

mainly NMOS devices the temperature dependency cancels out in a first order approximation.









In the architecture discussed in Chapter 3 for taking snapshots of events on a die following

a triggering event, two clocks need to be generated: an event triggering clock and a sampling

clock that propagates across the parallel samplers. The time delay between the transition edges of

these two samplers can be generated by a Vernier delay line [DSHOO]. This time delay is related

to the resolution of the information captured by the architecture. As shown in the Figure 4-4, a

decoder/multiplexer can be used to adjust this time delay in multiples of the minimum delay

equal to (tpl-tp2).

tpl


tp2 (a)
CLK1 = Event Triggering Clock Signal (a)
CLK2 = Sampling Clock Signal


(b) (c)
Figure 4-4. Vernier delay line. A) System. B) Current starved inverters in the top delay chain
(buffer delay = tpl). C) NOR gate based inverters in the bottom delay chain (tp2)









2.2 Digital BIST versus Analog BIST

For quite some time, built-in-self-test techniques have been integrated into digital circuit

designs so they can be tested. In digital IC test, the terms functionality and performance of a

circuit have been clearly distinguished in their definitions, which unfortunately is not the case

with analog/mixed-signal test [Vin98]. Validating the truth table specified by the designer is

enough to determine if a digital circuit meets the required functionality. Mapping between a set

of output vectors and a set of input vectors is represented in a truth table. The performance

specification is defined mostly by the speed of the digital circuit. In most cases, it is specified by

the delay an analog quantity of the circuit. On the other hand, in AMS test the circuit properties

and its behavior is so different from the digital circuits behavior that it blurs the lines between

the definitions of the terms functionality and performance. These terms are closely knitted in the

testing of analog circuits. Unlike digital circuits where separate fault models and algorithms can

be developed for functionality and performance, it is not only difficult but at times it is also

impossible to develop such models for AMS circuits. In circuits such as data converters,

structural fault models have been shown to adequately model faults that affect the I/O

relationship [Vin98]. However, circuit structure alone does not determine performance. Altering

device sizes while preserving topology can substantially alter performance. Thus, it is harder to

establish a quantitative relationship between a structural fault model and circuit performance.

Digital BIST is far more advanced than analog/mixed-signal BIST. The primary reason is the

absence of a widely accepted common methodology for analog and mixed-signal circuit test.

Stuck-at fault models and validation of the formulated truth tables have been the primary

methodology for digital integrated circuits. Researchers in analog test have been strongly

influenced by the success this methodology and have started to create similar techniques that can

be applied to analog integrated circuits. However, there is a substantial difference in the way









CHAPTER 3
CAPTURING ON-CHIP SIGNAL WAVEFORM SHAPE

3.1 Introduction

Current test methodologies are challenged in testing circuits that are operated with high

clock speeds. It should be noted that there is no guarantee that a signal at a node in the circuit

operated in the test mode is exactly the same as it is when the chip is operated at full speed. For

example, supply noise is not periodic on a chip during its normal operation. Autocorrelation of

the supply noise can be used to measure the noise spectrum by treating supply noise as a random

process [ASH05]. However, an ideal solution is to measure a full time-domain waveform during

the chip's at-speed operation. While realizing such a system is difficult, a novel architecture is

proposed in this chapter that will enable sampling a signal in real time for a certain period of

time following a triggering event. The sampled values are stored and can be exported off chip

easily. Real-time behavior of the signal on a Vdd line in a complex digital circuit contains

information about the variations in the current demands of a circuit from the power supply

during a clock event triggering the digital gates in the circuit. The L(di/dt) noise details of the

line can be extracted from this waveform. This noise is seen as voltage transients such as ringing,

overshoots and undershoots on the signal. Effects of parasitics are more pronounced for signals

with high frequency content. Amplitudes of these unwanted voltage transients on the supply line

are highest during and immediately after the clock transition as the frequency content in the

signal at the transitions is very high. The effects of the parasitics die down gradually when the

clock signal is stabilized. In today's microprocessor where the number of transistors is in the

order of billions, the noise generated can be catastrophic for the functionality of the circuit. This

problem should be properly addressed by techniques such as sufficient bypass capacitors, voltage










in terms of and the negative feedback in the loop still helps to suppress the offsets even when

the last stage is clipping.

Signal Path


Case 1: Zero offset. No duty cycle
degradation in the output


Signal Path


C2
ICase 2: Non-zero offset. Duty cycle
degradation in the output


T

nParameters in a non-50% duty-cycle waveform




Figure 5-13. Duty cycle degradation with non-zero input referred offset.

5.5 Results

In this work, the logarithmic amplifier or the limiting amplifier based signal strength

detector discussed in the above sections has been designed, simulated and fabricated in a 0.18um







































10 10 10. 109 101-
10 .

















-2









O -. .: : :




-20 : i : : i : : :
6 7 10















10 10 10 10 10
Frequency (Hz) A



















Figure 5-14. Frequency response curves. A) From single stage. B) From nine stages
0112
60


40









-20


-40 1"
10 10 10 10 10






Frequency (Hz) B



























112
j i :








































112









1.8V power supply. It can be observed that it conforms to the log curve with an error of +0.2dB


over the input dynamic range of 75dB.


'Chip under test


Multimeter


Figure 5-16. Measurements specifics of a logarithmic amplifier. A) Setup. B) Chip
microphotograph


Figure 5-16. Continued.










Let Vi=V+-V-. The simulated DC transfer characteristic or the input-output characteristics

of the CMOS full-wave rectifier with unbalanced source-coupled pairs is shown in Figure 5-11.

The three plots in the figure are the output current from the rectifier (AI = (ID1+ID4) (ID2+ID3)),

the sum of currents in the larger transistors Ml, M4 (xK currents), and the sum of currents in the

smaller transistors M2, M3 (xl currents) plotted against the input voltage Vi. When the input

voltage is small, most of the current flows through the larger transistors Ml and M4. However,

as the input voltage increases, the smaller transistors M2 and M3 start carrying significant

currents and the currents through the larger transistors start to decrease. Therefore, the total

current is shared between the different sized transistors and the effective output current from the

rectifier depends on the input voltage Vi.

-4
x 10
3.5 ,
-- deltal

Assuming matched.. .......devices and a sq e current... equation for the transiss in




















or saturation region, the differential output current of the rectifier A (D1D4) -D2-D3)
1 .5 . .








-0.4 -0.2 0 0.2 0.4 0.6
W2 (V)


Figure 5-11. Various currents in the rectifier (Simulated DC transfer curve)

Assuming matched devices and a square law current equation for the transistors in active

or saturation region, the differential output current of the rectifier AI = (ID1+ID4) (ID2+ID3) can









5.3 Mathematics of Logarithmic Amplifiers

Two key parameters that need to be decided before designing a log amplifier are the

number of stages (N) in the successive detection architecture and the log-error of the

architecture. The piece-wise linear approximation to a log curve is shown in Figure 5-4. Log-

error analysis gives a measure to the degree the piece-wise linear approximation of the

architecture conforms to the ideal log curve. Factors and analysis involved in deciding the

number of stages and a complete mathematical derivation of log amplifiers is described in this

section.









logx








Figure 5-4. Piece-wise linear approximation to a log curve

5.3.1 Operation Analysis Including Error Analysis of Log Amplifiers

Consider a limiting amplifier with N identical gain cells (Figure 5-3). Let each gain cell be

characterized by a gain A and a 3-dB frequency And, let the output of the mth stage be just

limiting and subsequent stages outputs clipped. Let VL be the limiting voltage of the gain cells.

The output of the mth stage = VL (limiting voltage). Therefore, the input of the mth stage is


equal to = A-V, where Vn is the input voltage to the first stage. Thus,
A












order for this system to be fabricated in a state of the art CMOS process, more robust design


techniques have to be employed for better performance. Such circuit design suggestions are also


made in this chapter. The next chapter presents another important on-chip test circuit, a signal


strength measurement circuit that can be used as a signal feature extractor in embedded test.


9
C5



-0.5 0 0.5 1 10.5 2.5
*Q_


x 10
o5




-0.5 0 0.5 1 1.5 2 2.5
Time () 1-8
0x 10
0-







time (s) -7



1 5
a








0,5















-1 0 1 2 3 4 5 6 7 8
time (s) xl05
2B












Figure 4-27. Measurement results. A) From conventional sampling switches. B) Switching at the
I/0 drivers.









[Vog05] C. Vogel. The Impact of Combined Channel Mismatch Effects in Time-
Interleaved ADCs. IEEE Transactions on Instrumentation and
Measurement, vol. 54, no. 1, February, 2005.

[Voo00] R. Voorakaranam. Test generation for accurate prediction of analog
specifications. 16th IEEE Proceedings VLSI Test Symposium, pp. 137-142,
May 2000.

[WW88] K. D. Wagner and T. W. Williams. Design for Testability of Mixed-Signal
Integrated Circuits. International Test Conference, pp. 823-828,
September 1988.

[YEF04] Q. Yin, W. R. Eisenstadt, and R. M. Fox. A Translinear based RF RMS
Detector for Embedded Test. Proceedings of the 2004 International
Symposium on Circuits and Systems, vol. 1, pp. 1245-1248, 2004.

[ZEF04] T. Zhang, W. R. Eisenstadt, and R. M. Fox. A Novel 5GHz RF Power
Detector. Proceedings of the 2004 International Symposium on Circuits
and Systems, vol. 1, pp. 1897-1900, 2004.













-*-Bandwidth
S-M- Gain

10



-5
10 -II I
0 2 4 6 8 10 12
Number of Gain Cells (N)
25
10
2,




S2 4 6 8 10 12
^ 10

0

1 15
10 -I I
0 2 4 6 8 10 12
Number of Gain Cells (N)


Figure 5-6. Gain, bandwidth and total power consumption versus number of stages

of each gain stage and the DC offset cancellation circuit. Since the limiting amplifier has a large

gain, a DC offset cancellation is required to suppress any offsets due to device mismatches,

which may otherwise cause the amplifier to saturate and smear off any small input signal coming

from the RF front-end. This section describes the circuit design techniques used in the design of


the log amplifier.

5.4.1 Limiting Amplifier Design

Each gain stage in the limiting amplifier chain can be a conventional simple differential


pair with a diode load. A differential pair has been chosen in this design because of its two

important advantages. First, it is primarily sensitive to the difference between two input voltages,

allowing a high degree of rejection of signals common to both inputs. Second, cascades of

differential pairs can be directly connected to one another without interstate coupling capacitors,

which is essential for the limiting amplifier chain. A NMOS differential pair with NMOS diode-









spectrum along with the signal power, thus reducing the overall signal to noise ratio of the

snapshot architecture. These jitter and clock skew tolerances of the architecture become very

Input Coc = 1MHz Input Clck = 10MHz



^ ,_C ~--------------
........... ... ... .
J .. ... .. .. ...... .. .........; ..... .:........... .. ......... .- .- .. ... ..... .



TI










stringent and important in deep sub-micron processes. Therefore, the design of these circuits in

the state-of-the-art process involves the implementation of more robust design techniques.

Besides the timing errors in the parallel samplers, the timing errors from the Vernier delay line

propagate into the parallel sampling system. We have already seen from the mathematical

derivation that the number of noise spectral lines in the output signal spectrum can be reduced if

the delay line generates precise integral multiples of minimum delay (tpi-tp2) between the event

triggering clock (CLK1) and the sampling clock (CLK2) for different conditions on the select

signals to the multiplexer. Therefore, it is necessary to be able to generate the clock signals that

are stable against temperature and process variations.

Multiple phases of clocks with low jitter can be generated by using a delay locked loop

(DLL). DLL design takes a considerably long design time. For this work, the most commonly

used and previously reported [MH93, Man96] DLL circuit is designed in a 65nm process. This









circuits on-wafer, before the ICs were diced and packaged. In order to make such wafer-level

testing possible, measurement systems have evolved from the old rack-and-stack systems to

extremely complex, million dollar systems with high throughput. Today's advanced

manufacturing process integrating more system functionality in less silicon area is very common.

This integration resulted in having analog, digital, RF and microwave circuits on the same die

(SoC, System-on-a-Chip) instead of having them as discrete circuits in a system: This led to

difficulties and expense in testing the analog, digital, RF and microwave circuits.

1.2.1 Cost Involved in IC Test

The key challenge in the way ICs are tested today is the cost involved in the test. The cost

of testing an IC has not been scaling at the same rate as the cost of manufacturing the IC.

Packaged dice are mostly tested in a two-fold manner: wafer-level testing and post-packaging

testing while known-good-die, KGD are used in flip chip applications. Wafer-level testing helps

to eliminate catastrophically defective dice before packaging. The dice that pass this wafer-level

testing are again tested thoroughly for defects after they are packaged. Today, high-speed testers

above 1-2 GHz are prohibitively expensive for low cost IC production parts. As an example, the

Teradyne Catalyst tester can test up to 3 GHz but costs more than millionn dollars. This has

made the testing of high-speed analog/mixed-signal circuits very challenging, particularly under

the constraints of high quality and low price. In the past, despite the high production cost, high

market prices of the products could still provide adequate profits. However, with increasing

competition in the electronics industry such as in the markets of cellular phones, portable music

players, portable computers, gaming consoles, profit margins are decreasing. Before, design and

manufacturing were the major components of the total cost, thus drawing little attention to

testing. But with recent improvements in manufacturing and fabrication of circuits, the

manufacturing cost has dramatically reduced thus making the cost to test the circuit a major









distribution of the sampling edge around the actual sampling edge of the clock (Figure 3-6).

Therefore, clock skew is deterministic and clock jitter is random. While clock jitter error in

sampling instant gives rise to an increased noise floor, constant clock skew error gives rise to

unwanted spectral lines in the output spectrum. However, both effects add noise in the spectrum

and degrade signal to noise ratio of the output signal.

ideal actual
samtintg sampling
instant instant











S Itte



Figure 3-6. Clock skew and clockjitter

3.3.1 Effects of Random Clock Jitter

Consider an input sinusoidal signal V (t)= A, sin(27ft). When this signal is sampled by a

jitter-free clock of frequency f, (period = TJ, then the output time discrete samples are given by

[n] = A sin(27nT,). (3-1)

Now, assuming a random variable forjitter (Q) that follows a Gaussian distribution

N(0,aU,), the actual sampling instant occurs at t = nT^ + t. and the actual output time discrete

samples are given by VJ[nl = A. sin(2#J(n7: + t)).
~~~~~~ITherefore, [n = As(2Icos(2 Acos(2n s(2,),
I II I
I II I
I II I
I II I






Figure 3-6. Clock skew and clock jitter

3.3.1 Effects of Random Clock Jitter

Consider an input sinusoidal signal VK(t)= Ao sin(2nfot). When this signal is sampled by a

jitter-free clock of frequency fJ (period = T,), then the output time discrete samples are given by

Vo,0[n] = A sin(2 fonTI,). (3-1)

Now, assuming a random variable for jitter (ti) that follows a Gaussian distribution

N(0,o- ), the actual sampling instant occurs at t = n + t and the actual output time discrete

samples are given by Vo,,[n]= Aosin(2nfo(nT,+ t)).

Therefore, Vot[n] = Ao sin(2 fnT,) cos(2nfot,) + Ao cos(2 nfnT,) sin(2 ,fot ),













pass/fail


Figure 2-3. Test setup and contributions of this work

2.5 Capturing Signal's Waveform Shape

Increasing unity gain frequencies of today's transistors enable circuit designers to design

very high-speed on-chip circuitry [LS93]. To understand various signal integrity problems such

as crosstalk, supply noise and ground bounce in these high-speed systems it is essential for a test

engineer responsible for validating and testing the functionality of the chip to be able to look at

the high-speed real-time behavior of on-chip signals. For example, real-time behavior of the

signal on a Vdd line in a complex digital circuit contains information about the amount of current

drawn from the power supply at a clock event triggering the digital gates in the circuit. The

L(di/dt) noise details of the line can be extracted from this waveform. Similarly, shapes of clock

signals at the start and at the end of a long on-chip interconnect can be studied to determine the

delays in this interconnect, and degradation of rise/fall times caused by this interconnect.


on-chip waveform IV
shape generation on-cp
on-chip signal
S Chapter 3 strength measurement
Sn Architechapter 5
Ste Signal Strength Detector
Chapter 4 -dlienf
High-Spebd Samplers
_____________ dc-like info.










Figure 4-19 shows the transient plot of Vgs of the main transistor (N1) in the improved

switch. From the figure, it can be seen that when the switch is on (phi) Vgs is nearly constant

irrespective of input signal. Figure 4-20 shows the transient plot of the bulk voltage of the PMOS

transistor (P2). The bulk voltage of this PMOS switches between Vdd and 2Vdd depending on

whether the switch is off and on, respectively. Simulation results showing the complete switch

behavior are shown in Figure 4-21. The plot shows the clock signal (phi), boosted gate voltage of

N1, input sinusoidal signal and the output signal. The switch transistor N1 together with the load

capacitance will form an RC circuit. The sampler's front end RC bandwidth of N1 and load

capacitance is 6 Ghz.


Clock (phi) and Vgs of the main transistor switch (N1)


> 1

.CS
6 0.5
0


time (s) -8
10


1.5


5 0.5

0

0 -0.5

> -1


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
time (s) -x

Figure 4-19. Clock (phi) and Vg of the main switch transistor (N10
Figure 4-19. Clock (phi) and Vgs of the main switch transistor (N1)










the reference time. Finally, when all the samplers are interlaced, the output signal is as shown in

the Figure 3-10. The digital spectrum of such a non-uniformly sampled signal has been derived

in [Jen88], and is given by



t kpr m=K0 Ktj

where, (3-5)
r mt-t
t



For the case of sinusoidal input, X (o)=27r6(o-co) the above equation can be written as


Xo,, () =1 (A(k))2 co k -

where, (3-6)

A(k) =y e- iJco}rt j K

K\I\

A 0-


/ I I I \
/ I \___


0 t, t2t% t4 -----

\ I






Figure 3-10. Output signal of a non-uniformly sampled signal

Here, A (k) is periodic on k with period K, hence the spectrum Xout(co) is periodic on co

with period equal to os (sampling frequency). Clearly, one period of the spectrum has noise













. 0 ..... .. .. .... ... .i ........... .....
-20I ....
-30
-4 0 ... .. ... .. .. .. .. ... ... ... .. ... ... .. .. .. ...


-60 ... .. .. .. .. .. .. .. ...

-70 .. .......
-60. .


0 1 0.2 0.3 04 0.5 0.6 07 0.8 0.9 1
Normalized frequency


Figure 3-16. Spectrum of output signal (n=2, p=4)

3.5 Measurement Results

This section describes about the measurement results from the prototype of the snapshot


architecture designed in AMI 0.5um process with a 5V power supply. Full system occupies an


area of 0.329 mm2 excluding bond pads and ESD devices. Figure 3-17 shows the boards and the


measurement apparatus.



















Figure 3-17. Measurement board and setup

The goal of this architecture is to be able to reproduce the shape of an on-chip signal


waveform off-chip. Figure 4-18 shows the measurement strategy. In the layout, a 8mm long


interconnect in this 3-metal layer process is considered as the device-under-test (DUT). The



62


























To my wonderful parents and my also wonderful brother













and cannot track the input signal. In this case, the supply voltage is 5V. The parallel line in the


figure shows the maximum voltage from the samplers. On the other hand, for signals that are


below Vdd, the reproduced signal is a close match to the input signal (Figure 3-22 (B)). This


inability of the samplers to sample reliably the voltages that extend beyond supply voltage is


addressed in the next chapter and an improved switch based on bootstrapping techniques is


proposed. The results from the switch are discussed there.


Waveform Comparison


6.00


5.00 ---- -









2.00


1C00


0.00 -
0.00 10.00 210,00 30.00 40.00 SO.00 60.00 70.00
thm (n)


Waveform Comparison


5.00 -

4.50 -

4.00 -- -



1.50







1.00
1 .50 --- --- --- -- --- --- --




0.50

0.0 ---- -


- Ext. sine signal
* Snapshot architecture


0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00
t0ne (s) B



Figure 3-22. System performance. A) For signals beyond Vdd (=5V). B) For signals below Vdd


--Ext. sine signal
* Snapshot Architectur









the signal range. These problems with the conventional sampling switches can be eliminated by

using bootstrapping techniques. An improved bootstrap switch that can reliably sample signals

beyond the supply voltage is designed in IBM7WL 0. 18um process with a 1.8V power supply

and TI 65nm process with a 1.2V power supply. This chapter also reviews the sub-sampling

technique commonly used in on-die oscilloscopes and used to validate the performance of switch

circuits.

4.2 Delay Generators and Vernier Delay Line

A simple delay element is a buffer consisting of two CMOS inverters as shown in the

Figure 4-1. However, this delay element does not provide any controllability on the delay of the

circuit after fabrication.

Vdd








in out









Figure 4-1. Simple delay cell

The current starved inverter style delay element shown in Figure 4-2 on the other hand

provides the user with the capability to adjust the delay of the circuit [LCMK94]. This is most

essential in achieving desired timing between two nodes in a circuit.









L(di/dt)


._FLL


Figure 2-5. L(di/dt) noise generation in circuits


sampler


sampler J

VDD, GND Bounce Characterization

Figure 2-6. Application of samplers to characterize supply and ground bounce


sampler J


Crosstalk Characterization

Figure 2-7. Application of samplers to characterize crosstalk effects











(5-5)


ft =f 2-1

Normalizing each gain cell's parameters with the total gain and 3-dB frequency, we get

A A tot _N
Normalized gain of single stage = A no,,, AtoNN (5-6)
Atot Atot

f 1
Normalized 3-dB frequency of single stage = fnom (5-7)


Total power consumption (Pt) can be calculated using single stage gain-bandwidth product

[HCWOO] and is given by P, ocN*(GBW)2. Implies,


N*Kttt1. 21N (5-8)


The plots showing the normalized values of gain and bandwidth versus number of gain

cells is shown in Figure 5-6. Also shown in the figure is the total power consumption of the

limiting amplifier versus number of stages. For a total gain of 90dB, from Figure 5-6, the

optimum value for the number of gain cells in the limiting amplifier is 7 or 9. However, when the

number of stages is 7, from Figure 5-5, the maximum error in dB slightly exceeds l+dB. Hence,

in this design, nine stages have been chosen with a slight penalty of area. The total gain of the

limiter is 90dB and the total bandwidth is approximately 100Mhz. Simulation results of this

circuit are shown in the later sections of this chapter.

5.4 Circuit Design

There are three main circuit components in a logarithmic amplifier. They are the gain stage

that is used in the limiting amplifier chain, the full-wave rectifier used as a detector at the outputs









ACKNOWLEDGMENTS

I would like to take this opportunity to thank the many people who have directly or

indirectly encouraged me and made this dissertation possible.

Foremost, I express my sincere appreciation to my PhD advisor, Professor William R.

Eisenstadt, for his continuous support and guidance throughout my journey as a graduate student

at the University of Florida. Without his many years of experience in the areas of circuit design

and test and his invaluable ability to see right through the problems to the solutions, my

exploration in the research would not have been successful. I would also like to thank Professors

John G. Harris, Rizwan Bashirullah, and Bruce A. Welt for their advice on this work and their

willing service on my committee. I am grateful to Dr. Rizwan Bashirullah and his students who

have allowed me access to the test equipment whenever needed.

I also would like to thank Professor Robert M. Fox; I cannot express in words the

importance of his involvement in my graduate career. I appreciate his interest in my work and his

valuable suggestions and comments from the idea proposal to its realization.

I thank the University of Florida and in particular the department of ECE for awarding me

the prestigious Graduate Alumni Fellowship.

Special thanks go to my colleagues at the University of Florida Jongshick Ahn, Kooho

Jung, Ming He, Qizhang Yin, Tao Zhang, Xiaoqing Zhou, Andy Wang, Said Rami, Devin

Morris, and Moishe Groger for their helpful discussions, advice, and friendship. My sincere

thanks also go to my friends from Clemson University and my undergraduate school, Andhra

University, who have in every way been available as a resource be it emotionally, socially, or

scholarly.

Special thanks also go to my parents, my brother, and all of my family members who

believed in me and thought it was a great idea when I said I wanted to pursue a PhD. Above all, I









ready to welcome any solution that can substantially reduce the cost and time involved in testing

its integrated circuits.

Embedded test or Built-in-Test is a potential solution to face the challenges posed to the

test community in the high-frequency domain. This method helps to keep up with the pace of the

growing complexity of tests. Embedded test reduces the time to production without increasing

the test cost and enables the use of low-cost testers, already on the factory floor, efficiently.

However, there is some increase in chip die area and production chip cost. The fundamental idea

in this solution is to move some of the external high-speed and high-bandwidth test functions on

to the chip. This move, however, is not that simple, and still is in the development stage.

This work involved development of some efficient test circuitry that could reside along

with the Device-Under-Test (DUT) on the same die. These embedded test circuits help in

extracting useful information from high-frequency on-chip signals and converting them to low-

frequency (base-band) signals for easy transfer of information off-chip for post processing on an

external, low cost, low frequency ATE. On-chip signal shape capturing circuits using high-speed

samplers and on-chip signal strength measurement circuits were developed that can be used in

embedded test of mixed-signal integrated circuits.









APPENDIX
SPECTRUM OF OUTPUT SIGNAL FROM THE SNAPSHOT ARCHITECTURE

If the delays of the buffers are not matched between the parallel samplers, the output signal

is a result of what is called the non-uniform sampling. In such a case, assuming a constant skew

for each buffer but different from other buffers, we can assume the following for the sampling

instants of the samplers. Unlike uniform sampling (Figure A-1), where the final interlaced

samples are at times t, 2t, 3t ... with respect to the reference time, we can assume the samples in

this case to be at times to, tl, t2, ... with respect to the reference time (Figure A-2). The digital

spectrum of such a non-uniformly sampled signal has been derived in [Jen88], and is given by

1 1 K -Io -k( lrt 2; km 2; 2 r

t K Kt0

where, (A-l)
mt tm
rm i
t



\


/ \

/ \


I \

0 t 2t 3t 4t \





Figure A-. Uniform sampling
\ /
\ /
\ /
\ /
\ /





Figure A-i. Uniform sampling








circuit the source/drain to well potential of P2 can reach a voltage as high as 2Vdd depending on
the input signal of the switch. However, the reverse breakdown voltage of this p/n junction in
modern technologies is much larger than the supply voltage [FSR06].
Vdd
T_1


-LC1


phibar


-L C2


Figure 4-17. Charge-pump circuit


phibar


Figure 4-18. Improved bootstrap switch









5-11 Various currents in the rectifier (Simulated DC transfer curve).................................... 106

5-12 DC offset cancellation techniques. ...........................................................................108

5-13 Duty cycle degradation with non-zero input referred offset ........................................110

5-14 Frequency response curves. ................................................................... ...................112

5-15 Simulation results of the logarithmic amplifier. ........................................ ...............113

5-16 Measurements specifics of a logarithmic amplifier. ................................................. 114

5-17 M easurem ent results. ......................... ...... ..................... .... ............... 115

5-18 Down conversion based substrate noise measurement.............................116

6-1 Addressing loading, jitter and silicon area...............................................120

A-i Uniform sam pling ............................. .... ................... .......... .............. 121

A -2 N on-uniform sam pling ............................................................................ ................... 122

A-3 Sampling instants with same 't' between samplers and irregular 't' between
sam plers ........................................................................................ 123





























12









Exact logarithmic response can be obtained by using the logarithmic I-V characteristics of

an inverting operational amplifier with a diode or a transconductance feedback (Figure 5-2).







Vin Vin
Rs Vout Rs Vout
+ +




Figure 5-2. Transconductance feedback logarithmic amplifiers. A) Diode. B) Transistor

out kT Vin
I= e / .I; (Or) Vourt= (5-1)
q RKs Is

However, these structures have strong temperature dependence as shown in Equation 5-1

and need elaborate compensation techniques. Also, since these techniques rely on the logarithmic

characteristic of a physical electronic device in their feedback loops, they become less practical

at higher frequencies where the device response is degraded [Gre92]. A more powerful

logarithmic technique is the approximation of a logarithmic function by the summation of

straight-line segments. This method relies on the circuit architecture known as the successive

detection architecture (Figure 5-3) to produce a pseudo-logarithmic transfer function rather than

a particular device's V-I characteristics. The transfer function is called pseudo-logarithmic for

the reason that it is an approximation to an ideal logarithmic curve. The degree of this

approximation to the ideal logarithmic curve depends on certain design parameters, which will

be discussed later in the chapter.









LIST OF REFERENCES


[AASM05]


[AG99]


[ASHO5]


[ATRCAO6]


[Awa98]


[Bak05]


[Bog04]


[Boh03]


[BR01]


[BRD96]


[CAHK04]



[CBS01]


D. Aksin, M. A. Al-Shyoukh, and F. Maloberti. A Bootstrapped Switch
for Precise Sampling of Inputs with Signal Range beyond Supply Voltage.
IEEE 2005 Custom Integrated Circuits Conference, 2005.

A. M. Abo and P. R. Gray. A 1.5V, 10-bit, 14.3MS/s CMOS pipeline
analog-to-digital converter. IEEE Journal of Solid-State Circuits, vol. 34,
no. 5, pp. 599-606, May 1999.

E. Alon, V. Stojanovic, and M. A. Horowitz. Circuits and Techniques for
High-Resolution Measurement of On-Chip Power Supply Noise. IEEE
Journal of Solid-State Circuits, vol. 40, no. 4, April 2005.

S. S. Akbay, J. L. Torres, J. M. Rumer, A. Chatterjee, and J. Amtsfield.
Alternate Test of RF Front Ends with IP Constraints: Frequency Domain
Test Generation and Validation. IEEE International Test Conference, pp.
1-10, October, 2006.

S. S. Awad. Analysis of Accumulated Timing Jitter in the Time domain.
IEEE Transactions on Instrumentation and Measurement, vol. 47, no. 1,
pp. 69-74, February, 1998.

R. J. Baker. CMOS Circuit Design, Layout and Simulation. IEEE Press,
Wiley Interscience, 2005.

E. Bogatin. Signal Integrity-Simplified. Prentice Hall, Upper Saddle
River, New Jersey, 2004.

M. Bohr. High-Performance Logic Technology and Reliability
Challenges. IEEE International Reliability Physics Symposium, 2003.

M. Burns and G. W. Roberts. An Introduction to Mixed-Signal IC Test
and Measurement. Oxford University Press, New York, 2001.

K. Baker, A. M. Richardson, and A. P. Dorey. Mixed-Signal Test-
Techniques, Applications and Demands. IEE Proceedings Circuits
Devices Systems, vol. 143, no. 6, December, 1996.

A. Chatterjee, S. S. Akbay, A. Halder, and D. Keezer. Low-Cost Test of
Embedded RF/Analog/Mixed-Signal Circuits in SoPs. IEEE Transactions
on Advanced Packaging, vol. 27, no, 2, pp. 352-363, May 2004.

F. Caignet, S. Bendhia, and E. Sicard. The challenge of signal integrity in
deep submicrometer CMOS technology. Proceedings of the IEEE, vol. 89,
no, 4, pp. 556-573, April 2001.









would like to thank God for being with me in every walk of life and for the blessings that have

been the major source of strength throughout my life.









Again, the spectrum Xout(co) in Equation 3-7 is periodic on co with period equal to os

(sampling frequency). Clearly, one period of the spectrum has noise spectral lines at frequencies

k
equal to + -f,k = 1,2,3.... These noise spectral lines are due to the clock skews in the buffers
K

between the samplers and degrade the signal to noise ratio (SNR) as input frequency increases.

(<>_+l -1 -J k2 m
Additionally, the summation terms e-Jio t enp in Equation 3-7 become zero
m=- p

when k is an integral multiple ofn. This implies that in this architecture, noise spectral lines due

to clock skew effects at these values of k become zero (Figure 3-13). Therefore, the snapshot

architecture with Vernier delay line has (p-1) less noise spectral lines and increased SNR in the

reconstructed signal when compared to case ii.

fin

Signal
Power
(Noise due to skew)
A






0 freq. f/2

Figure 3-13. Reduction of noise spectral lines with an ideal VDL in the architecture

3.4 Modeling and Simulating in MATLAB

Modeling and simulating the architectures in MATLAB has been done to verify the

observations and mathematical derivations described earlier. The effects of clock jitter and clock

skew are included in the timing instants generator in the model. In this model 8 parallel samplers

are considered. Input signal frequency is 25Hz and sampling frequency is 100Hz. The noise floor













Table 4-2 shows the measured separation between the two clock edges for different control


signals in the multiplexer. Figure 4-6 shows the measurements from a real-time oscilloscope.


Table 4-2. Measurements of Vernier delay line (average time separation = 397ps)

Measured
AO Al separation between
clkl and clk2 edges

0 0 375ps
0 Vdd 770ps

Vdd 0 1193ps
Vdd Vdd 1591ps


AO =O,A1= 0


AO = Al Vdd


S... I .. .
7 0 J, 77
--I "- I -------- ,-._-...- ------ .
----------- -------- --,- --.,--------- ------ -- --- .--- ------, ------ --------
.I
11----------------- --------------------------------------

II I
___ ............ ..___.______--. ........ .._ L. I.-- -





I -

SI I I
- ,- -,- --. ...... r .. .. ..i- ----
1 I SM IIIaCM5 _
B-1





,Ii) 7 ,I u ",_______ ,__ __ ,I i


Ii .

---------- ----------- --r- ------------------
------ ---- I --I----



I i i


--------- -------------------- -----------




AO---- -- --- -Al = --0



AO =Vdd, A1 =0


I I__


-- M i ili i*- d lffT -f :


-rC~Ck~~--- ---- L-..--J----

-------r--. ----i------,-----,
I I i ,

I I i

I I I ,


A-


/ I




-------------------------
---- -----------------


--[----------------------
r.


AO Vdd, Al = Vdd


Figure 4-6. Average time separation increments of 397ps between clock and clock2


i-I'


~____,__










section shows the simulation results of a delay locked loop based Vernier delay line. The basic

blocks of a DLL are shown in Figure 4-9.






PFO --B as Gen.
u Pump
OCk nut FL_ I Dow




V ohtlageCon~oIlad Deay Lire
- -





Figure 4-9. Delay locked loop

The phase of the reference clock is compared to the phase of the output clock from the

voltage-controlled delay line. Any phase error between the two clock signals is detected in the

phase-frequency detector (PFD) and generates an appropriate voltage on the loop filter via a

charge pump circuit. This voltage on the loop filter adjusts the delay in each stage of the voltage

controlled delay line until the phase error between the reference clock and output clock is zero.

The negative feedback in the loop reduces the phase error gradually to zero. When the phase of

the output clock from delay line is aligned with the phase of the reference clock, the DLL has

achieved its locked state. At this point, the different outputs of the voltage controlled delay lines

have stable clock signals with equal phase shifts between them. For a reference clock period

equal to T, the delay in each stage of the VCDL in an N-stage delay line is given by T/N in the

locked state.

In order to generate two clock signals, two delay locked loops can be used as shown in

Figure 4-10. The number of stages in each delay locked loop is different. Assume that DLL 1 has








by the capacitor (Cb) to approximately (Vdd + Vin). This implies, Vgs = Vg-Vs = (Vdd + Vin) Vin

=Vdd

Vdd

phibar

phi phibar


Cb
phi
Vout
phibar Vin Cout


I I

Figure 4-15. Conceptual diagram for bootstrapping technique

Certain node voltages in the bootstrapped switch exceed the supply voltage. Care should

be taken while designing such switches so that the device reliability rules are not violated

[AG99]. The limitations on the terminal voltages set by the device breakdown mechanisms in an

MOS transistor are briefly described here.

Oxide breakdown sets a limit on the Vgs and Vgd that can be applied to a transistor for

reliable operation. Hot electron effects limit the Vgs and Vds that can be applied. Gate-induced

drain leakage currents also limit the voltage that can be applied across the gate oxide. Finally,

punch-through determines the Vds that can be applied when the device is off. A more detailed

discussion of the breakdown mechanisms can be found in [AG99, MH90, Hu94]. For reliable

operation, the terminal voltages in a MOS transistor with respect to each other should not exceed

the Vdd provided by the technology [(Vgs, Vgd, Vds) < Vdd]. The absolute terminal voltages,

however, can be larger than Vdd.

















0 t 2t 3t 4t \ /
\ I
\ I
I
\ /

\../



Figure 3-9. Output signal from uniformly sampled signal

1
This corresponds to uniform sampling of the input signal at a sampling rate equal to or
t

sampling period equal to t. The spectrum of such an output signal is given by the well-known

spectrum representation [PL76],


S)=o)-k ))

where, (3-4)
X(o)) = 2lr(o o))

It is seen that Xout (co) is periodic in o with period 27T. Spectral lines in the output spectrum

are at o=oo. There are no other noise spectral lines as the signal is uniformly sampled with zero

skew between samplers.

Case ii: If the delays of the buffers are not matched, the output signal is a result of what is

called the non-uniform sampling. In the presence of constant skew for each buffer but different

from other buffers, we can assume the following for the sampling instants of the samplers.

Unlike case i, where the final interlaced samples are at times t, 2t, 3t ... with respect to the

reference time, we can assume the samples in this case to be at times to, ti, t2, ... with respect to









2.5.2 On-Chip Techniques

On-chip techniques to measure the shape or analog properties of signals rely on sampling

techniques. The challenge here is to capture the details of a fast changing signal. A sub-sampling

technique is most commonly used to sample an on-chip signal that is periodic or a signal that is

made repetitive by having the IC operate in test mode rather than in its normal operation mode.

The shape of the signal is reconstructed off-chip. In this type of sampling, high-frequency

information of the signal is converted to low frequency that can be easily transported off-chip

without degradation. Sampling techniques offer a less invasive time domain measurement of

waveforms.

The idea is to deploy on-chip samplers at various places of interest on the chip to sample

the node information. The information captured by these can be used not only to analyze various

signal integrity issues in a high-speed system but also to generate models for validation and

simulations to emulate the electrical behavior of on-chip circuit elements. Some of the causes for

unwanted effects of parasitics such as delay, crosstalk, supply and ground bounce, and the

application of samplers to characterize them are briefly discussed here.

Interconnect delay measurement: Transmission line is the term that is commonly used

for today's interconnects. An interconnect can be considered as a lumped element or a

distributed RLGC model depending on its physical length's relation to the wavelength

(frequency) of the signal that it is carrying. As a rule of thumb, if the physical length of an

interconnect is larger than one-tenth of the wavelength of the signal in the line it should be

considered as a distributed line. When interconnect response is treated through distributed RLGC

models, the voltage along the length of interconnect is not constant but is position and time

dependent. The signal takes a finite time to travel across this interconnect and gets distorted

because of the line's lossy circuit elements (R, G) in the model. Therefore, the signal is delayed




















0 t1 t2t3 t4 -
\ /
\ I
\ /






Figure A-2. Non-uniform sampling

Here, the total number of samples is K. Architecturally if changes are made such that these

K samples can be divided into 'n' sets with 'p' samples in each set (Figure A-3) and that all the

samples in each set are off from their ideal sample instants by the same amount, we can derive

the following. This change in the architecture can be brought by the addition of a Vernier delay

line that is discussed in detail earlier. The goal here in this appendix is to derive the equation to

represent the spectrum of the signal that is obtained from the samples satisfying the condition K

=np.

The sample sets are,

(0,,23,..,p-1)0,(p,p+ 1,...,2p-1)1,(2p,2p+1,...,3p-1)2,...,((n 1)p,(n -)p+ 1,...,p- 1)1

For this condition in (A-l), we have,

ro = r =...= rp- = to

rp = rp+1 =. = 2p-1 =


(n-l)p = (n-l)p+l = = p-l = tn-1


















C1 C2


phibar
IL


phibar phi
N1

Vout
phibar _




Figure 4-16. Conventional bootstrap switch

(0-Vdd), node A changes from 0-Vdd. This turns on the transistor whose gate is connected to

node A pulling node B to approximately (Vdd-Vt). When phibar changes from high to low

(Vdd4O) and phi from low to high (0-Vdd), node B is boosted from (Vdd-Vt) to (2Vdd-Vt).

This in turn pulls node A to Vdd. In the next iteration, node A boosted to 2Vdd and node B is

pulled to Vdd. From here on, nodes A and B switch between Vdd and 2Vdd.

The improved Bootstrapped circuit is shown in Figure 4-18. A separate charge pump is

used to generate a voltage 2Vdd when the main switch is on. In this circuit, the bulk of PMOS

transistor P2 switches between 2Vdd and Vdd when the sampling switch is on and off

respectively. This avoids the forward biasing of the p-n diode for input voltages larger than

supply and the switch can be used reliably for sampling signals beyond Vdd. The inset in this

figure shows how this switch will be represented in the rest of this chapter. A separate non-

overlapping clock generator generates the clock signals phi and phibar in the circuit. In this


=









methods to circumvent these challenges, methods that offer the possibility of low cost test

methodologies, at-speed testing techniques and quicker time to market that help to maximize the

profit margins. Only then can the test techniques catch up to the pace of the design techniques.

Test Cost vs Test Time &2M Teste rest Cost vs Test Tie $100 K Tester
o O

S o- r
1 2ei Sltn-o- I Cllne
15
o 10 __mmm




Toa0121 lt Time [seconds) Toa Test Time (seconds)
[ TOster Captal [ Handler Caplta Z Test House, Maintenance, Operator I TestDeIlopnent NRE


Figure 1-6. Cost contributors to testing a part for various test times.

1.3 Potential Solution to the Challenges

For speeds beyond a gigahertz, built-in-test (BIT) of high-speed systems is a very

attractive solution. Built-In-Test involves designing and integrating test hardware on-chip,

supporting the test hardware with design-for-testability features and designing in standard

communication protocols that allow an external tester to control the test procedure with low

bandwidth access and hence, lower cost external testers. In the past, design engineers were

sometimes reluctant to add testability features to a device, since BIT added design cycle time, die

area, and/or power consumption. Fortunately, the attitude has changed in recent years from

reluctance to acceptance as design engineers have seen the competitive advantages of BIT. Now

some companies see BIT as a major technological differentiator that can reduce production costs,

enhance quality control, and even provide customers with value-added testability features for use

in their system-level products.











[HCWOO] P. Huang, Y. Chen, and C. Wang. A 2-V 10.7MHz CMOS Limiting
Amplifier/RSSI. IEEE Journal of Solid-State Circuits, vol. 35, no, 10, pp.
1474-1480, 2000

[He06] M. He. Embedded Substrate Noise Measurement for Mixed-
Signal/RF/Microwave ICs. Ph.D. Dissertation, University of Florida,
2006.

[HR03] M. M. Hafed and G. W. Roberts. Techniques for High-Frequency
Integrated Test and Measurement. IEEE Transactions on Instrumentation
and Measurement, vol. 52, pp. 1780-1786, Dec. 2003.

[Hu94] C. Hu. Ultra large scale integration device scaling and reliability. Journal
of Vac. Sco. Tech. B, vol. 12, no. 6, pp. 3237-3241, November, 1994.

[Hug86] R. S. Hughes. Logarithmic Amplification with Application to Radar and
E.W. Artech House, Dedham, MA, 1986.

[IBM02] IBM RF & Analog Test Development. Lowering Test Costs for RF ICs.
IBM Technical Note, Dec. 2002.

[ITR01] The International Technology Roadmap for Semiconductors 2001, pp. 10-
11,2001.

[ITR03] The International Technology Roadmap for Semiconductors 2003, pp. 27-
30, 2003.

[Jen88] Y. C. Jenq. Digital Spectra of Non uniformly Sampled Signals:
Fundamentals and High-Speed Waveform Digitizers. IEEE Transactions
on Instrumentation and Measurement, vol. 37, no. 2, pp. 245-251, June,
1988.

[Jin87] R. P. Jindal. Gigahertz-band high-gain low-noise AGC amplifiers in fine-
line NMOS. IEEE Journal of Solid-State Circuits, vol. 22, no. 4, pp. 512-
521, August 1987.

[Kim92] K. Kimura. Some circuit design techniques for bipolar and MOS pseudo-
logarithmic rectifiers operable on low supply voltage. IEEE Circuits and
Systems I: Fundamental Theory and Applications, vol. 39, no. 9, pp. 771-
777, September 1992.

[Kim93] K. Kimura. A CMOS Logarithmic IF Amplifier with unbalanced source-
coupled pairs. IEEE Journal of Solid-State Circuits, vol. 28, no. 1, pp. 78-
83, January 1993.









component of the total cost. Unless fundamental changes are made to the way testing is done in

the high-frequency regime, it might cost more to test complicated and high performance chips

than to manufacture them in the future. Figure 1-2 shows the cost of silicon manufacturing

versus the cost of testing, normalized per transistor as projected by 2001 technology roadmap for

semiconductors [ITR01]. The top curve shows the manufacturing capital per transistor and the

bottom curve shows the test capital per transistor.

1980 1985 1990 1995 2000 2005 2010 2015

-SIA Silicon manufactumg
S 0.1 mSIA Test euipentdepreciain

0.01


L 0.001


0.00001
0 .0 01 ,

o
0 --
0.000001

Figure 1-2. Moore's law for test: fabrication vs. test costs.

It is clearly seen that there is a consistent reduction in chip fabrication cost per transistor

that in turn drives the continued expansion and evolution of the semiconductor business. It is also

observed from the graph that the capital expenses for IC test have been essentially flat per

transistor and is projected to reach the projected manufacturing costs per transistor by year 2012.

This challenge posed by the cost involved in the testing of ICs should properly be addressed

today to avoid any unexpected surprises to the electronics industry tomorrow.











DUT Detail


. multipletxers I denmlmiplxemrs
. signal gnelors
isaplerpas, conveprs
Prmsponse compressors
> test-aes.etc...




power planes

signll Irces


BuWt4n Test Load Board


Figure 2-1. Continued.




Table 2-1. Comparison of built-off test and built-in test


Built-off Test


Built-In Test


Area Importance


Less to Moderate


Controllability/Observability Moderate


Signal Degradation


Moderate to High


Applications


Silicon verification and
Design debugging


Suitable for all high-speed
applications


Tester Electronics in the end-
productNo
product


High

High

Less


Yes


~









Shown in the Figure 2-1 are the various load boards that are used in testing [CAHK04].

Figure 2-1(A) is the load board in the conventional ATE measurement setup. It does not have

either built-off test or built-in test features. Tester electronics reside completely in the ATE. This

is suitable for low frequency testing. Figure 2-1(B) shows the load board that is commonly used

for silicon verification or design debugging. These DUTs end up as products without any

integrated tester capabilities. Area metric or area overhead is not given a high importance in

these built-off test strategies. Some of the test metrics are compared between BoT and BiT in

Table 2-1. Figure 2-1(C) shows the true built-in-test strategies where all the high-speed tester

electronics reside along with the device under test. These DUTs have integrated tester

capabilities even after production.

2.3.1 Direct Measurement of Circuit Specifications

In direct measurement of circuit specifications, appropriate test stimuli are applied and the

corresponding test response is measured to validate a circuit specification. Each circuit

specification needs appropriate tester resources. Some examples are multitone signal generators

for measuring distortion, gain for codec, and so on [CAHK04]. This approach is in complete

agreement with the traditional production test approach for analog and mixed signal circuits that

uses similar test stimuli and configuration with respect to which the specification is defined and

documented by the systems engineer.

For direct measurement techniques, tests are performed sequentially one by one. Relays are

used to switch between different test sets and equipment for test when the specifications needed

to test on a circuit are incompatible in environment. Several BIST techniques in the available

literature have shown the application of this approach. For instance, different implementations of

on-chip signal generators and test response data acquisition circuits are reported [CEF03,

YEF04, ZEF04]. Signal source in [CEF03] demonstrated the capabilities of generating pure









BIOGRAPHICAL SKETCH

Sudeep Puligundla was born in Andhra Pradesh, India. He received his Bachelor of

Engineering degree in electronics and communications engineering from Andhra University,

India in 2001 and his M.S. degree in electrical engineering from Clemson University, South

Carolina in 2002. He was awarded Graduate Alumni Fellowship by the University of Florida in

Gainesville, Florida where he received a Ph.D. degree in electrical engineering in 2007.

During the summer and the fall of 2006, he worked as a Graduate Technical Intern at Intel

Corporation, Hillsboro, Oregon and during the summer of 2002, he worked as an Engineering

Intern at Raritan Computer Inc., New Jersey.

His research interests are in the areas of analog/mixed-signal/RFIC design, circuit

validation, and embedded IC design for test.









[CEF03] S. Choi, W. R. Eisenstadt, and R. M. Fox. Design of programmable
embedded IF source for design self test. Proceedings of the 2003
International Symposium on Circuits and Systems, vol. 5, pp. 241-244,
May 2003.

[CP96] R. Chandramouli and S. Pateras. Testing Systems on a Chip. IEEE
Spectrum, November. 1996.

[DK01] M. Dessouky and A. Kaiser. Very Low-voltage digital-audio AS
Modulator with 88-dB dynamic range using local switch bootstrapping.
IEEE Journal of Solid-State Circuits, vol. 36, no. 3, March 2001.

[DSHOO] P. Dudek, S. Szczepanski, and J. V. Hatfield. A High-Resolution CMOS
Time-to-Digital Converter Utilizing a Vernier Delay Line. IEEE
Transactions on Solid-State Circuits, vol. 35, no. 2, February 2000.

[EE93] Y. Eo and W. R. Eisenstadt. High-Speed VLSI Interconnect Modeling
Based on S-Parameter Measurements. IEEE Trans. Comp. Hybrids Manuf
Technol., vol. 16, pp. 555-562, August, 1993.

[EFYYZ04] W. R. Eisenstadt, R. M. Fox, Q. Yin, J. S. Yoon, and T. Zhang. On-Chip
Microwave Test Circuits for Production IC Measurements. 64- ARFTG
conference, December 2004.

[FSR06] C. J. B. Fayomi, M. Sawan, and G. W. Roberts. Low-voltage Analog
Switch in deep submicron CMOS: design technique and experimental
measurements. IEICE Trans. Fundamentals, vol. E89, no. 4, April, 2006.

[Gre92] J. C. Greer. Error Analysis for Pseudo-Logarithmic Amplification. Meas.
Sci. Technol. 3, 1992.

[GM93] P. R. Gray and R. G. Meyer. Analysis and Design of Analog Integrated
Circuits. Wiley, New York, 1993.

[GVC98] A. V. Gomes, R. Voorakaranam, and A. Chatterjee. Modular fault
simulation of mixed signal circuits with fault ranking by severity. IEEE
International Symposium on Defect and Fault Tolerance in VLSI Systems,
pp. 341-348, November 1998.

[HAMWMH98] R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori, and M. A. Horowitz.
Applications of on-chip samplers for test and measurement of integrated
circuits. Symposium on VLSI Circuits, Digest of Technical Papers, pp.
138-139, June 1998.

[HBC03] A. Halder, S. Bhattacharya, and A. Chatterjee. Automatic multitone
alternate test generation for RF circuits using behavioral models.
Proceedings International Test Conference, vol. 1, pp. 665-673,
September 2003.









Skew-less clock signals are important for the master-slave type sampling switches in the

samplers. This is important so that the charge is not inadvertently lost. The trick to obtain skew-

less design is described here. Figure 4-7 shows the circuit consisting of CMOS inverters.

A B C
phi

CLK

1 2
N N_ phibar



Figure 4-7. Skew-less clock generator

To provide skew-less clock generation, it is important that devices are sized such that the

sum of pull-up delays in path 1 is equal to the sum of pull-up delays in path 2. Similarly, pull-

down delays in path 1 must be equal to pull-down delays in path 2. Such a design is made in

AMI 0.5um process for use in the architecture. Table 4-3 shows the measured crossover points

for clock and inverted clock for an input full swing clock signals of frequencies 1MHz and

10MHz.

Table 4-3. Measured crossover voltage values
Measured cross-over
Input clock frequency e o e Ideal cross-over voltage
voltage
1MHz 2.43V 2.5V
10MHz 2.33V 2.5V

4.2.2 Delay Locked Loop Based Vernier Delay Line in 65nm

As discussed in Chapter 3, jitter and clock skew causes non-uniform sampling of the input

signal. This results in a proportional amount of noise in the output spectrum. Gaussian random

jitter increases the noise floor and constant clock skews inject noise spectral powers in the output









3.2 Proposed System Architecture

In order to be able to capture enough details describing the signal at a node on the chip, the

signal needs to be sampled in real-time at very high-speed. High resolution in the sample points

is important for an effective characterization of the signal. Sampling at high-speeds requires a

very high-speed clock. The architecture shown here in Figure 3-2, however, does not require a

high-speed clock to provide samples of the signal with high resolution. The signals of interest

here are triggered in the device-under-test by the clock signal and are sampled by a number of

parallel samplers each using the same low frequency clock (Period = T). Notice that the sampling

instants of two consecutive parallel samplers are separated by a certain delay, t to achieve the

resolution in the sample points. This way each sampler captures new information about the

signal. In essence, the sampling of the input signal is performed in real time unlike a sub-

sampling technique where each sample of the input periodic signal is taken in a different period.

The parallel outputs are then extracted and the samples are interlaced with the timing information

of the delay between the parallel samplers to reproduce the original signal. In this case,

1
effective sampling rate = ;


length of the snapshot = (K 1)t;

K = number of parallel samplers;

t = delay between sampling instants of two consecutive parallel samplers.

Increasing the number of input samples can increase the signal to noise ratio of the

reconstructed signal. Figure 3-5 shows a modified version of this architecture that takes more

samples of the signal. By making the input signal repetitive and using a Vernier delay line

(VDL) a fine adjustment of the resolution or time spacing between the samples can be achieved.










1.2.2 Increased Integration of System Functionality

Semiconductor transistors are becoming so cheap and commonly available that whole

industries now live on continuously integrating more and more functions into smaller and

smaller packages, hence creating system-on-chips. The trend toward more system functionality

on a single die (SOC) or in a single package (SIP) will increasingly blur the lines between

traditional digital, analog, RF/microwave and mixed signal devices. This trend will drive test

equipment toward a single platform solution that can test any application. Being able to rapidly

test, diagnose and verify complex new chips and products using such chips is crucial for the

continued success of our economy. This growth is expected to continue full force at least for the

next decade, while making possible the production of billion transistor chips. Figure 1-3 shows

the drastic increase in the number of transistors integrated on a microprocessor over the past

three decades [Rus04].


1.E+D9
ir 9MBo
Itaniumn2 6MB
1.3MB M
1.E+D8 Pentiun?4
PeniuPentium
PentiumP4
Pentium III
o Itanium
+ : Pentium I
-' 1.E+D7

486
1.E+06 -
386
286
1.E+05
1980 1990 2000 2010


Figure 1-3. CPU transistor count trend Moore's law.

According to Moore's law, the number of transistors on a chip doubles every 18 months.

For the discussion here, this trend can be understood in a different way. The functionality that is

achieved on a certain area of silicon is doubled every 18 months. If this trend is followed by the









architecture has been reported. Diode connected triple-well NMOS transistors are load devices in

each gain cell of the cascade of limiting amplifiers to make the gain a function of device sizes

only. The fabricated chip occupies an area of 0.96mm2 in 0.18um CMOS process with a 1.8V

power supply.

6.2 Suggested Future Work

The goal of this research is to develop on-chip measurement circuits that can exhaustively

characterize the increasing signal integrity problems in integrated circuits. It has been shown that

parallel sampling can be applied to measure on-chip signals without sampling the signal at very

high sampling rates. However, this architecture is in its development stage and many areas

remain to be studied so that it evolves into a complete system that can be integrated as an

embedded test circuit. Some simple design changes should allow this architecture to be deployed

to measure any critical signals. Most important issues that need to be addresses in future

evolutions are

Non-destructive probing
Reducing system jitter and skew errors, increasing output SNR
Reducing silicon area, most important test metric in embedded test

Non-destructive probing: Power and ground lines on a chip are designed to drive huge

loads and so this measurement circuit would not really load these nodes when signals on them

need to be measured. Similarly, measuring signals at the outputs of the clock buffers in a high-

speed digital circuit would not be a problem. These clock signals are routed to a number of

sequential logic circuits on the chip, and the buffers are designed to drive large capacitive loads

in the circuit. However, when measuring critical nodes that are not designed to drive large

capacitances, this on-chip signal shape capturing circuit should not load the node that is being

probed. Non-invasive or non-destructive probing is very important. In such cases, there is a need









sinusoidal signal thus enabling the self-testing of analog/RF blocks within the package. The

application of on-chip samplers using sub-sampling technique has been demonstrated in [LS93,

SZ03]. All these circuits demonstrate the feasibility of in-situ characterization and testing of

performance of high-speed analog/RF circuits. Direct measurement techniques have certain

drawbacks. As the tests are performed sequentially with circuit specification specific hardware

resources, these techniques lack the ability to simultaneous measurement of multiple

specifications. In the case of evaluating multiple specifications this methodology results in large

area overhead and longer test times.

2.3.2 Alternate Test for Circuits

Integration of more functionality and performance into a single device increases the

number of specifications that need to be tested. Like discussed in direct measurement of circuit

specifications, sequential testing of today's circuits would result longer test times. Also, each test

would require different equipment or different load board resources. This results in increased test

cost. The concept of alternate test was proposed [CAHK04, ATRCA06, VC98] to address these

issues and reduce the cost and time involved in testing analog/RF ICs. In this methodology, a

complete suite of sequential specification tests is replaced with a single test, consisting of a

carefully crafted test stimulus applied to the device-under-test. After finding the suitable

transient test stimulus, this approach relies on the fact that if the response of a circuit-under-test

to an alternate test stimulus is sensitive to all process variations that also affect its test

specifications, then it is possible to predict all its test specifications from the test response

without having to measure the specifications explicitly.

Figure 2-2 shows the variations in process or circuit parameters and their effect on circuit

specification and test [CAHK04]. Consider a vector P defined as the process parameter space

consisting of p process parameters, a vector S defined as the specification space consisting of s









various inputs, usually known as stimuli generated in the ATE to the device-under-test (DUT)

and observing the response of the DUT. This response is compared to a predetermined response

in the ATE based on the specifications documented by the systems engineer to determine if the

design is good (pass) or bad (fail).


ATE I > Result (Pass/Fail)
ATE



Test Stimuli DUT Response



DUT


Figure 1-1. Conventional IC testing using ATE.

This conventional IC testing works well for simple integrated circuits operating at low

frequencies. However, this method does not appear to be an attractive solution for today's

complex multi-functional high frequency circuits due to the challenges and difficulties in ATE

based testing described in the next sections.

1.2 Challenges in High-Speed IC Test

In the past, the simple ATE testing approach described in the above section has been used

as a functional verification test for integrated circuits that operate at low frequencies. Extending

this approach to a more robust testing of today's complex circuits operating at higher clock

frequencies than before is not straightforward. Earlier, high-speed IC designers could only

speculate as to why a particular design worked. The true electrical performance of these tiny

circuits was impossible to measure at wafer level. With the advancements in high-performance,

high frequency, on-wafer probes and probe stations, design engineers could test and characterize



























Figure 5-1. Typical front-end of a wireless receiver

logarithmic amplifying function in circuits is described in the error analysis of log amplifiers.

Next, circuit design of limiting amplifiers, rectifiers and dc offset cancellation circuits is

discussed. Finally, the layout of the chip, results from the simulation and measurements are

presented to verify the functionality of the overall circuit. This chapter is concluded with a case

study of an application of logarithmic amplifier based signal strength detectors in substrate noise

measurement.

5.2 Logarithmic Amplifiers

Logarithmic amplifier is an indispensable tool in many measurement circuits where a

precise knowledge of the signal amplitude is necessary. This magnitude control of the signals

can be achieved by using an automatic gain control (AGC) circuit but an AGC system has a

limited useful instantaneous input dynamic range before saturation occurs. A logarithmic

amplifier helps in compressing and mapping a wide dynamic range at the input to a small range

at the output. Logarithmic amplifiers are able to replace AGC circuits, as an input dynamic range

in excess of 80dB is not uncommon with log amps [Hug86].









and attenuated at the other end of this interconnect. Deployment of the samplers at the beginning

and at the end of such a long interconnect will help in capturing the waveforms at these nodes

from which the delay can be measured (Figure 2-4).

sampler sampler








Interconnect delay measurement

Figure 2-4. Application of samplers to measure interconnect delay

Supply and ground bounce characterization: Simultaneous switching of gates in an IC

at clock events causes the circuit to draw a huge amount of current from the power supply

generating current spikes. Power supply lines are resistive and inductive in nature and so these

current spikes cause the voltage on a power line to bounce from its ideal Vdd or ground levels.

This noise is commonly referred to as the L(di/dt) noise in digital circuits (Figure 2-5).

Application of samplers to measure this noise from the shape of waveform is shown in Figure 2-

6.

Crosstalk characterization: Crosstalk happens when a signal transition on one

interconnect effects the signal on the nearby interconnects. The former is called the aggressor

and the later is called the victim. The coupling of energy between the aggressor and the victim as

a result of mutual capacitance (electric field) and mutual inductance (magnetic field) provides a

path for unwanted noise from one net to the other.









LIST OF TABLES


Table page

2-1 Comparison of built-off test and built-in test............... ............ ............... .... ........... 34

2-2 Comparison between off-chip m ethods ........................................ ......................... 40

3-1 Comparison of On-chip measurement circuits ...................................... ............... 67

4-1 Separation between CLK1 and CLK2 edges for select signals ......................................72

4-2 Measurements of Vernier delay line (average time separation = 397ps)...........................73

4-3 M measured crossover voltage values .............................................................................74









S-parameter measurements: At high frequencies, Eo and Eisenstadt [EE93] described a

technique to determine the characteristic impedance of a transmission line including the

conductance effect of the line and capacitance variation due to varying permittivity. The s-

parameters of the line under test are measured by a probe-tip calibration with those of an ideal

transmission line. This technique which has been improved upon is widely used as the preferred

way to obtain high frequency characterization of interconnects by giving the interconnect s-

parameters.

Time-domain reflectometry: A time-domain reflectometer is similar to VNA but operates

in the time domain. It emits a fast rise-time step signal, and measures the reflected transient

amplitude. Again, using the reflected voltage, the impedance of the line under test can be

extracted. In the time domain, the impedance measured represents the instantaneous impedance.

Although this method effectively characterizes the package and PCB trace impedance, the

crosstalk effects between on-chip interconnects cannot be characterized precisely. Comparison

between various off-chip methods is shown in Table 2-2 [VB04].

Table 2-2. Comparison between off-chip methods

Probing S-parameter Time-domain
E-beam probing
techniques techniques reflectometry

Bandwidth <1-2GHz 10GHz 70GHz 15GHz

Cost High Very High Very High High
Measurements Dynamic Dynamic Impedance Dynamic


invasive, requires calibration
invasive, .
loading effects availability of needed,
Drawbacks i signal on top- conversion of specific test
f the probe- level metal, msmts. to time- patterns
tips expensive domain
very expensive domain









CHAPTER 1
INTRODUCTION

1.1 Background of ATE Based Testing

Delighting customers by relentlessly delivering efficient products before competitors can

deliver is the business plan of today's successful semiconductor companies. This has been the

driving force and also the reason behind the success of such companies. Not only delivering the

product on time is important but also equally important is making sure that the delivered product

is a reliable and a fully functional product that meets the customer's requirements.

While the job of a systems engineer is defining and documenting the customer's

requirements, a circuit design engineer is responsible for designing and developing the integrated

circuit that meets the specifications. Unfortunately, after the design process not all manufactured

designs meet the specifications. Such failures may be caused by design flaws or process errors. A

test engineer is responsible for identifying design flaws in the design before the product is

fabricated and shipped to the customer. In addition, the test engineer identifies badly

manufactured parts after a design is verified as good. The test engineer's role is to generate

hardware and software that will be used to guarantee the performance of each device after it is

fabricated [BR01]. Some of such hardware and software could go into what is called the

automatic test equipment (ATE) or in the future reside on the same silicon as the device-under-

test (DUT) commonly known as embedded test or built-in-test. Automatic Test Equipment ATE

is any automatic device that is used in the IC manufacturing industry to test electronic

components ranging from simple components such as resistors, capacitors, and inductors to a

more complex printed circuit boards and ICs after they are fabricated. While computer

simulation tools are used as pre-silicon validation tools, ATEs are used for post-silicon validation

for the circuit designs. A typical test using an ATE is shown in Figure 1-1. It involves applying









Table 4-1. Separation between CLK1 and CLK2 edges for select signals
AO Al Separation between
clkl and clk2 edges
0 0 (tpl-tp2)
0 Vdd 2(tpi-tp2)
Vdd 0 3(tpl-tp2)
Vdd Vdd 4(tpi-tp2)


4.2.1 Measurement Results

Vernier delay line discussed in the previous section has been designed in AMI 0.5um

process with a 5V supply for the snapshot architecture discussed in the previous chapter. The

timing delay information of each block used in the architecture is very important for accurate

interlacing of the samples obtained from the parallel samplers. Different sub-blocks of the

architecture are designed and laid out as stand-alone circuits for evaluating the performance in

the overall system design. The layout in Figure 4-5 is repeated from previous chapter here. It

highlights the stand-alone circuits used for the characterization of the system. The following

measurements are performed for an input full-swing (0-Vdd) clock signal of frequency 10 MHz.







1. Full systeba
2. DUT
3. Vernier delay line
4. Paralel delay chain
5. Skewless clock generator






Figure 4-5. Layout of sub-blocks in the system









However, preserving the shape of an on-chip waveform and exporting it off-chip without

degrading signal quality poses an interesting challenge.

Capturing techniques of an on-chip signal's waveform shape can be broadly classified into

two types, (1) off-chip techniques (2) on-chip techniques.

2.5.1 Off-Chip Techniques

Off-chip techniques are usually invasive where as on-chip techniques give less invasive

time-domain information of waveforms.

Some of the common off-chip techniques for characterizing on-chip signal integrity

[CBS01] are

Low frequency probing methods
E-beam probing
S-parameter measurements
Time-domain reflectometry

Probing methods: This method uses high-impedance probe tips to probe a required signal

node on silicon directly. This eliminates the signal transmission through the package leads and

board traces, which adds a lot of capacitive and inductive parasitics. However, in order to be

probed on the silicon, the signal needs to be probed via a metal area where the probe tip is

landed. This metal adds capacitance and can effect the measurement. The loading of the probes

also effects the measurement. Effective calibration techniques need to be employed to cancel

such effects. These drawbacks confine the measurement to few gigahertz ranges.

E-beam probing: Measurements using E-beam probing are completely non-invasive as it

is a contact less measurement. There are no loading effects of the measurement equipment

involved. However, the disadvantages are it requires a very expensive measurement setup and

requires top-level metal to carry the signal to be measured.









4 DELAY GENERATORS AND HIGH-SPEED SAMPLERS ..............................................68

4 .1 In tro du ctio n .................. .............................................................................................. 6 8
4.2 Delay Generators and Vernier Delay Line ............................................ ............... 69
4 .2 .1 M easurem ent R esults................................... ................................... ..................72
4.2.2 Delay Locked Loop Based Vernier Delay Line in 65nm ............. ...............74
4.3 High-Speed Sam plers .................................. .. .. .. ...... .. ............77
4.3.1 The Sub-Sam pling Technique ........................................ .......................... 78
4.3.2 Master-Slave Type Sampling Switches..... .................... ............80
4.3.3 Low-Voltage Bootstrapped Switches...... ..................... ...............82
4.3.3 Im proved B ootstrapped Sw itch ........................................ ......................... 84
4 .3.4 M easurem ent R esults...................................................................... ..................89

5 LOG AMPLIFIER: LIMITING AMPLIFIER BASED SIGNAL-STRENGTH
IN D IC A T O R ................................................................................93

5 .1 In tro d u ctio n ................................................................................................................. 9 3
5.2 L ogarithm ic A m plifi ers .......................................................................... ....................94
5.3 Mathematics of Logarithmic Amplifiers ..................................................................97
5.3.1 Operation Analysis Including Error Analysis of Log Amplifiers ..........................97
5.4 Circuit D design .................. ................................................. ............ ...... 100
5.4.1 L im iting A m plifi er D esign ....................................................................... ..... 101
5.4.2 R ectifier D design ............................................................. ......... 103
5.4.3 DC Offset Cancellation Techniques ...................................... ...............107
5 .5 R e su lts ......................................................... .................. ................ 1 1 0
5.5.1 Sim ulation R results .................. .................... ...... ............... .............. .. 111
5.5.2 M easurem ent Results ........................................................ ................... 111
5.6 Application in Substrate Noise Measurement .............. ......................................116

6 SUM M ARY AND FUTURE W ORK ...............................................................................117

6 .1 S u m m a ry ................................................................................................................... 1 1 7
6.2 Suggested F future W ork ..................................................................... ....................... 118

APPENDIX SPECTRUM OF OUTPUT SIGNAL FROM THE SNAPSHOT
A R C H IT E C T U R E ................................................................. .................... 12 1

L IST O F R E F E R E N C E S ..................................................................................... ..................125

B IO G R A PH IC A L SK E T C H ......................................................................... ........................ 131















0.8


0.7


0.6


0.5


A_ 0.4


0.3






0.1
-1








0.8

0.6

0.4

0.2

0
0

- -0.2
C-


-20 0 2


-1 1 i I i i "
-100 -80 -60 -40 -20 0 20
Input Power (dBm)


Figure 5-15. Simulation results of the logarithmic amplifier. A) Output voltage versus input

power. B) Error curve.


produce a DC-like measurement proportional to the logarithm of the amplitude of the input RF


signal. Measurement results are shown in Figure 5-17, which show the signal strength indicator


outputs and the log conformance of the logarithmic amplifier chips. The measurements have


characterized an input dynamic range of more than 75dB for a 100MHz sinusoidal signal with a


SNMOS Loads
Triple-well Loads



......... i... ...... i. I .

.............. ... .. .. .. ... ... ......... .... .... ....
-I





. ............... .............. ......... .. .. .


.. ......... ...... .. .. ...... .. ........ .. .. .. .. ..
- .. ..

-.... : ......:.~ ....

-


-80 -60 -40
Input Power (dBm)









made possible by the use of sub-sampling technique [LS93, HAMWMH98, TMN02, CBS01].

This technique relies on the concept that any periodic signal can be reconstructed from samples

of the signal sampled once in every period, but at different time instants with respect to previous

periods. Figure 4-12 shows time domain description of the sub-sampling technique.

If the signal to be measured is periodic with period Tthen let the period of the sampling

clock be (T + At) where At is a small fraction of T. Thus, every sample of the signal sampled by

the clock in the next period is delayed so that each sample has new information about the

original signal. If n cycles of sampling clock are required to sample the information contained in

one period of the input signal, then the time period of the resulting sampled signal is, n(T + At),

where n -


Therefore, the period of the sampled signal (T +At).


This implies that the frequency of the sampled signal = 1 At which is
(T+At) T(T+ At)
AT+ t)


exactly the beat frequency of the input signal and the sampling clock = Therefore,
T T+At)

fout input fsamplingclock

The sub-sampling technique provides a magnification in the time domain and a reduction

in frequency of the output signal. This helps to export information stored in the samples easily

off-chip with a low cost test equipment without degrading the signal quality. Low frequency

circuits or software can be used for analyzing the information of the signal from the stored

samples.









4.3.4 Measurement Results

In this work, different switch circuits have been designed using IBM7WL 180nm

technology with 1.8V power supply. Figure 4-22 shows the boards with the circuits. The chips

on the boards also contain high-speed I/O drivers designed to create test signals for the

characterization of the package. Switching of these drivers generates ground bounce and power

supply fluctuations. Samplers are deployed at various places on the chip to measure these critical

signals. These samplers not only help measuring signals but also help in debugging a packaged

chip for functionality where the internal nodes are inaccessible for probing. Figure 4-23 shows

the chip microphotograph.


Figure 4-22. Board with the conventional sample-and-hold circuit


Figure 4-23. Chip microphotograph









CHAPTER 5
LOG AMPLIFIER: LIMITING AMPLIFIER BASED SIGNAL-STRENGTH INDICATOR

Logarithmic amplifiers can be used in determining on-chip signal amplitudes because of

their capability of handling a larger dynamic range while consuming less power with simple

circuitry. As discussed in Chapter 2 a built-in-test problem can be broken down into two aspects.

First, the DUT must be stimulated with the help of high-speed test stimulus generators developed

on-chip and second, the DUT response should be analyzed with the help of high-speed on-chip

acquisition circuits. Signal strength detectors discussed in this chapter can be used as an

analyzing circuit. This chapter talks about the design of limiting amplifier based signal-strength

indicators and their usefulness in embedded test of circuits.

5.1 Introduction

Detectors play an important role in the embedded test of circuits. Accurate measurement of

signal strengths at various places on a wireless chip is almost indispensable. In addition, in

mobile communication systems, knowledge of the strength of the received signal by the receiver

is essential to monitor and control the signal levels transmitted by the base station. Constant

monitoring of the transmitted and received signal strengths can help in dynamic adjustments of

the power transmitted by the base station that reduces the power consumption. A logarithmic

amplifier is a limiting amplifier based signal-strength indicator and is widely used in cellular

phones that require an on-chip circuit to measure the received signal strength. A typical front-end

circuitry in a wireless receiver and a typical application of logarithmic amplifiers is shown in

Figure 5-1 [HCWOO].

Organization of this chapter is as follows. First, a brief overview of logarithmic amplifier

techniques is discussed followed by a complete mathematical analysis of logarithmic amplifiers,

which describes the operation of the circuit quantitatively. Error involved in realizing a









If random jitter variable t, is assumed to be much less than T7, then

V,[n] = A. sin(2fonT) + Ao,2aft, cos(2fonT). (3-2)

In Equation 3-2 the jitter term is separated from the signal term. Therefore, from Equations

3-1 and 3-2, voltage error due to jitter is given by,

V,[n]= A,2o7ft, cos(2nfonT,)

v, [n] = P)t -nT,


This implies that timing error due to jitter would cause large sample error at fast transitions

of the input signal. The noise power value due to jitter is given by,

P = V2 Jmis[n] rAo2nfoJ2
P= []= 2 j (3-3)
22 2
=2 2fo2 Ao0 o

This noise power due to jitter is seen as the noise floor in the output spectrum. The

architecture in this discussion has been modeled behaviorally in MATLAB and the simulation

results of the output spectrum without and with jitter (MATLAB function:

normrnd(mean, variance,rows, columns)) are shown in Figure 3-7. Noise floor seen here is the

effect of random Gaussian jitter in the clock signal for the samplers. Here in the simulation, 8

parallel samplers are considered and for now clock skew in the delays between parallel samplers

is assumed to be zero. Hence there are spectral lines only at the input signal frequency. Input

signal frequency is 25Hz and sampling frequency is 100Hz.

3.3.2 Effects of Deterministic Clock Skew

Presence of clock skew, a constant offset in the sampling instant from its ideal sampling

instant, causes unwanted noise represented as spectral lines in the spectrum of the output

sampled signal. The following discussion analyses the architecture with and without a Vernier

delay line. The number of noise spectral lines in the output spectrum is less for the modified









in the input transistors of the differential pair helps in steering and sharing the current between

the larger and smaller transistors depending on the input voltage.

Vdd










(+) (+)


Vbias




Figure 5-9. CMOS multiplier based on Gilbert cell.


Figure 5-10. CMOS full-wave rectifier with unbalanced source-coupled pairs









can be replaced by measurements R as all process variations that affect the performance of the

DUT can be detected by the measurements R. In this case, it follows that there exists a mapping

f: R-4S that can be used to compute the valued of all the DUT's specifications S from the

transient or AC response measurements R.

First, the goal is to find a deterministic or pseudo-random test stimulus input such that the

response R of the circuit under test to the applied stimulus is sensitive to all process variations in

P that also affect its specification space S. So, initially conventional tests are run on the DUTs

from various fabrication runs in order to determine the nonlinear mapping functions between the

spaces. Several papers in the literature reported the successful application of alternate test

approach to circuits such as op-amps, filter circuits, and high-frequency RF modules while

mentioning that response acquisition circuits in alternate testing of analog/RF modules is

difficult and still in the development stage.

2.4 Motivation and Contributions of this Work

The key to success in any of the above-discussed methodologies in analog/mixed-signal

embedded test lies in creating (Figure 2-3),

On-chip high quality test signal generators or stimuli generators, and
On-chip test response data acquisition circuits.

Data acquisition circuits also called as feature extractors [CAHK04] are used in both direct

measurement of circuit specifications and deriving the nonlinear mapping functions between

various parameter spaces in the alternate test. This research work addresses two important kinds

of these circuits,

Capturing a snapshot of on-chip signal's waveform shape
Measuring on-chip signal strength










mlogA = log

Sog (5-2)
-> m =--
logA

When the circuit sums the outputs of the gain cells, the output of the summer is,

S+A +2 +A + A3 + ......+Am-, +(N-(m-1))Vi
=(+ A + A2 + A3 +......+Am -, +(N (m-1))VL
if,A >>1
Am
A V, + (N- (m -1))VL
A-l

Slog V
V 7V
+ N+1 L





=-N+1+-+ V
A logA




V 1 lo gV
SlogV + (5-3)
logA A- logA

Equation 5-3 represents the equation of a straight line, y = mx + c, with a linear


relationship between the output and the log of the input. The slope m = and intercept c


( 1 logV 1
= N+1- Once the limiting voltage (VL) and the small-signal voltage gain (A)
are known, the signal strength of any input signal can be predicted using Equation 5-3.
are known, the signal strength of any input signal can be predicted using Equation 5-3.




Full Text

PAGE 1

1 SIGNAL-STRENGTH INDICATO RS AND HIGH-SPEED SAMPLERS FOR EMBEDDED TEST OF MIXED-SIGNAL INTEGRATED CIRCUITS By SUDEEP PULIGUNDLA A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2007

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2 2007 Sudeep Puligundla

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3 To my wonderful parents and my also wonderful brother

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4 ACKNOWLEDGMENTS I would like to take this oppor tunity to thank the many pe ople who have directly or indirectly encouraged me and ma de this dissertation possible. Foremost, I express my sincere appreciation to my PhD advisor, Professor William R. Eisenstadt, for his continuous support and guidance throughout my journey as a graduate student at the University of Florida. Without his many y ears of experience in the areas of circuit design and test and his invaluable ab ility to see right through the pr oblems to the solutions, my exploration in the research would not have been successful. I would also li ke to thank Professors John G. Harris, Rizwan Bashirul lah, and Bruce A. Welt for their advice on this work and their willing service on my committee. I am grateful to Dr. Rizwan Bashirullah and his students who have allowed me access to the te st equipment whenever needed. I also would like to thank Pr ofessor Robert M. Fox; I cannot express in words the importance of his involvement in my graduate career I appreciate his interest in my work and his valuable suggestions and comments from the idea proposal to its realization. I thank the University of Florida and in par ticular the department of ECE for awarding me the prestigious Graduate Alumni Fellowship. Special thanks go to my colleagues at the University of Florida Jongshick Ahn, Kooho Jung, Ming He, Qizhang Yin, Tao Zhang, Xi aoqing Zhou, Andy Wang, Said Rami, Devin Morris, and Moishe Groger for their helpful discussions, advice, and friendship. My sincere thanks also go to my friends from Clemson University and my undergraduate school, Andhra University, who have in every way been availabl e as a resource be it em otionally, socially, or scholarly. Special thanks also go to my parents, my brother, and a ll of my family members who believed in me and thought it was a great idea when I said I wanted to pursue a PhD. Above all, I

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5 would like to thank God for being with me in ever y walk of life and for the blessings that have been the major source of st rength throughout my life.

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6 TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................4 LIST OF TABLES................................................................................................................. ..........8 LIST OF FIGURES................................................................................................................ .........9 ABSTRACT....................................................................................................................... ............13 CHAPTER 1 INTRODUCTION..................................................................................................................15 1.1 Background of ATE Based Testing..................................................................................15 1.2 Challenges in High-Speed IC Test...................................................................................16 1.2.1 Cost Involved in IC Test.........................................................................................17 1.2.2 Increased Integration of System Functionality.......................................................19 1.2.3 Increased Speeds of Operation...............................................................................21 1.2.4 Time Involved in IC Test.......................................................................................22 1.3 Potential Solution to the Challenges.................................................................................23 1.4 Organization of the Dissertation.......................................................................................24 2 EMBEDDED TEST FOR ANALOG/MIXED-SIGNAL IC..................................................28 2.1 Introduction............................................................................................................... ........28 2.2 Digital BIST versus Analog BIST....................................................................................29 2.3 Approaches in Analog/Mixed-Signal/RF Test.................................................................31 2.3.1 Direct Measurement of Circuit Specifications.......................................................32 2.3.2 Alternate Test for Circuits......................................................................................35 2.4 Motivation and Contributions of this Work......................................................................37 2.5 Capturing Signals Waveform Shape...............................................................................38 2.5.1 Off-Chip Techniques..............................................................................................39 2.5.2 On-Chip Techniques...............................................................................................41 2.6 Measuring On-Chip Signal Strength................................................................................44 3 CAPTURING ON-CHIP SIGNAL WAVEFORM SHAPE...................................................45 3.1 Introduction............................................................................................................... ........45 3.2 Proposed System Architecture..........................................................................................47 3.3 Errors in Timing Instants of the Samplers........................................................................50 3.3.1 Effects of Random Clock Jitter..............................................................................52 3.3.2 Effects of Deterministic Clock Skew.....................................................................53 3.4 Modeling and Simulating in MATLAB...........................................................................60 3.5 Measurement Results........................................................................................................62

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7 4 DELAY GENERATORS AND HIGH-SPEED SAMPLERS...............................................68 4.1 Introduction............................................................................................................... ........68 4.2 Delay Generators and Vernier Delay Line.......................................................................69 4.2.1 Measurement Results..............................................................................................72 4.2.2 Delay Locked Loop Based Vernier Delay Line in 65nm.......................................74 4.3 High-Speed Samplers.......................................................................................................77 4.3.1 The Sub-Sampling Technique................................................................................78 4.3.2 Master-Slave Type Sampling Switches..................................................................80 4.3.3 Low-Voltage Bootstrapped Switches.....................................................................82 4.3.3 Improved Bootstrapped Switch..............................................................................84 4.3.4 Measurement Results..............................................................................................89 5 LOG AMPLIFIER: LIMITING AMPL IFIER BASED SIGNAL-STRENGTH INDICATOR...................................................................................................................... ....93 5.1 Introduction............................................................................................................... ........93 5.2 Logarithmic Amplifiers....................................................................................................94 5.3 Mathematics of Logarithmic Amplifiers..........................................................................97 5.3.1 Operation Analysis Including E rror Analysis of Log Amplifiers..........................97 5.4 Circuit Design............................................................................................................. ....100 5.4.1 Limiting Amplifier Design...................................................................................101 5.4.2 Rectifier Design....................................................................................................103 5.4.3 DC Offset Cancellation Techniques.....................................................................107 5.5 Results.................................................................................................................... .........110 5.5.1 Simulation Results................................................................................................111 5.5.2 Measurement Results............................................................................................111 5.6 Application in Substrate Noise Measurement................................................................116 6 SUMMARY AND FUTURE WORK..................................................................................117 6.1 Summary.................................................................................................................... .....117 6.2 Suggested Future Work..................................................................................................118 APPENDIX SPECTRUM OF OUTPUT SIG NAL FROM THE SNAPSHOT ARCHITECTURE.............................................................................................. 121 LIST OF REFERENCES.............................................................................................................125 BIOGRAPHICAL SKETCH.......................................................................................................131

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8 LIST OF TABLES Table page 2-1 Comparison of built-off test and built-in test.....................................................................34 2-2 Comparison between off-chip methods.............................................................................40 3-1 Comparison of On-chip measurement circuits..................................................................67 4-1 Separation between CLK1 and CLK2 edges for select signals.........................................72 4-2 Measurements of Vernier delay line (average time separation = 397ps)...........................73 4-3 Measured crossover voltage values...................................................................................74

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9 LIST OF FIGURES Figure page 1-1 Conventional IC testing using ATE...................................................................................16 1-2 Moores law for test: fa brication vs. test costs..................................................................18 1-3 CPU transistor count trend Moores law........................................................................19 1-4 Feature size trend in IC manufacturing..............................................................................20 1-5 CPU clock frequency trend Moores law........................................................................21 1-6 Cost contributors to testi ng a part for various test times...................................................23 1-7 Organization of dissertation.............................................................................................. .27 2-1 Load boards for IC test. ................................................................................................. ...33 2-2 Alternate test with re sponse feature extraction..................................................................36 2-3 Test setup and cont ributions of this work..........................................................................38 2-4 Application of samplers to measure interconnect delay....................................................42 2-5 L(di/dt) noise generation in circuits...................................................................................43 2-6 Application of samplers to characterize supply and ground bounce.................................43 2-7 Application of samplers to characterize crosstalk effects..................................................43 3-1 Microprocessor power supply line fluctuations.................................................................46 3-2 System Architecture....................................................................................................... ....48 3-3 Vernier delay line (VDL).................................................................................................. .49 3-4 Comparison of sampling instants. .....................................................................................50 3-5 Modified system architecture.............................................................................................51 3-6 Clock skew and clock jitter............................................................................................... .52 3-7 MATLAB simulations for jitter.........................................................................................54 3-8 Parallel samplers with buffers............................................................................................55 3-9 Output signal from uniformly sampled signal...................................................................56

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10 3-10 Output signal of a non-uniformly sampled signal..............................................................57 3-11 Spectrum of a non-uni formly sampled signal....................................................................58 3-12 Same t between samplers ideal case and irregular t between samplers.....................59 3-13 Reduction of noise spectral lines w ith an ideal VDL in the architecture...........................60 3-14 Spectrum of output signal................................................................................................ ..61 3-15 Spectrum of output signal (n=4, p=2)................................................................................61 3-16 Spectrum of output signal (n=2, p=4)................................................................................62 3-17 Measurement board and setup...........................................................................................62 3-18 Strategy of waveform comparis on (DUT 8mm long interconenct)................................63 3-19 Clock signal at the end of DUT. .......................................................................................64 3-20 Signal reproduced by the snapshot architecture.................................................................64 3-21 Waveform comparison between measurement circuit and oscilloscope...........................65 3-22 System perform ance....................................................................................................... ....66 4-1 Simple delay cell......................................................................................................... .......69 4-2 Current starved delay cell................................................................................................ ..70 4-3 Delay versus control voltage (AMI 0.5um process Vdd = 5V)......................................70 4-4 Vernier delay line........................................................................................................ .......71 4-5 Layout of sub-blocks in the system...................................................................................72 4-6 Average time separation increments of 397ps between clock1 and clock2.......................73 4-7 Skew-less clock generator................................................................................................. .74 4-8 Measurements of a skew-less clock generator on a real-time oscilloscope.......................75 4-9 Delay locked loop......................................................................................................... .....76 4-10 Delay locked loop based Vernier delay line......................................................................77 4-11 Simulations of DLL based VDL........................................................................................78 4-12 Sub-sampling technique in time-domain...........................................................................80

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11 4-13 Master-Slave type Sample-and-Hold circuitt.....................................................................81 4-14 Resistance variation of NMOS, PMOS, and a TG. ...........................................................82 4-15 Conceptual diagram fo r bootstrapping technique..............................................................83 4-16 Conventional bootstrap switch...........................................................................................85 4-17 Charge-pump circuit...................................................................................................... ....86 4-18 Improved bootstrap switch................................................................................................ .86 4-19 Clock (phi) and Vgs of the main switch transistor (N1).....................................................87 4-20 Clock (phi) and the bulk voltage of the PMOS transistor (P2)..........................................88 4-21 Simulated proposed bootstrap switch behavior (Clock (phi ), gate voltage (Vg) of N1, input and output signals)....................................................................................................88 4-22 Board with the conventional sample-and-hold circuit.......................................................89 4-23 Chip microphotograph..................................................................................................... ..89 4-24 Layout of the chip (IBM7WL 0.18um process).................................................................90 4-25 Output sub-sampled signal (frequency = 5MHz)..............................................................90 4-26 Frequency spectrum of the output signal...........................................................................91 4-27 Measurement results. .................................................................................................... ....92 5-1 Typical front-end of a wireless receiver............................................................................94 5-2 Transconductance feedback logarithmic amplifiers. ........................................................95 5-3 Successive detection architect ure of logarithmic amplifiers.............................................96 5-4 Piece-wise linear appr oximation to a log curve.................................................................97 5-5 Maximum error (dB) versus number of gain cells (N)......................................................99 5-6 Gain, bandwidth and total power consumption versus number of stages........................101 5-7 CMOS limiting amplifiers...............................................................................................103 5-8 Amplifier circuit. ....................................................................................................... ......104 5-9 CMOS multiplier based on Gilbert cell...........................................................................105 5-10 CMOS full-wave rectifier with unbalanced source-coupled pairs...................................105

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12 5-11 Various currents in the rectifie r (Simulated DC transfer curve)......................................106 5-12 DC offset cancellation techniques. .................................................................................108 5-13 Duty cycle degradation with non-zero input referred offset............................................110 5-14 Frequency response curves. ............................................................................................112 5-15 Simulation results of th e logarithmic amplifier. .............................................................113 5-16 Measurements specifics of a logarithmic amplifier.........................................................114 5-17 Measurement results. .................................................................................................... ..115 5-18 Down conversion based s ubstrate noise measurement....................................................116 6-1 Addressing loading, j itter and silicon area.......................................................................120 A-1 Uniform sampling.......................................................................................................... ..121 A-2 Non-uniform sampling.....................................................................................................122 A-3 Sampling instants with same t be tween samplers and ir regular t between samplers....................................................................................................................... ....123

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13 Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy SIGNAL-STRENGTH INDICATO RS AND HIGH-SPEED SAMPLERS FOR EMBEDDED TEST OF MIXED-SIGNAL INTEGRATED CIRCUITS By Sudeep Puligundla December 2007 Chair: William R. Eisenstadt Major: Electrical and Computer Engineering Over the past decade, advancements in areas of semiconductor device physics, IC manufacturing and integration t echnologies on silicon have consid erably increased the operating frequencies (ft) of transistors in the deep sub-micron regime. This enabled design engineers to design circuits that operate at high frequencies and use high-speed clock signals, both leading to increased signal-integrity problems for test e ngineers responsible for testing and validating integrated circuits. While the de sign community is able to push th e design envelope far into the future, production IC test equipment has not ke pt pace with test requirements of high-speed, integrated wireless and wired communications de signs. This explosive improvement of design performance has made testing of high-speed an alog/mixed-signal circui ts very challenging, particularly under the constraints of high quality and low price. In order to perform effective signal analysis and tests on such high frequency on-chip signals one should be able to export those signals off-chip. However, exporting hi gh-frequency on-chip signals off-chip without degrading the signal quality of the signals is not easy. A less attractive solution to this problem is to replace low cost testers with very expensiv e Automatic Test Equipment (ATE) systems and measurement equipment such as pico-probes and E-beam probes. The electronics industry is

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14 ready to welcome any solution that can substantially reduce the cost and time involved in testing its integrated circuits. Embedded test or Built-in-Test is a potentia l solution to face the challenges posed to the test community in the high-freque ncy domain. This method helps to keep up with the pace of the growing complexity of tests. Embedded test reduces the time to produc tion without increasing the test cost and enables the us e of low-cost testers, already on the factory floor, efficiently. However, there is some increase in chip die ar ea and production chip cost The fundamental idea in this solution is to move some of the extern al high-speed and high-band width test functions on to the chip. This move, however, is not that si mple, and still is in the development stage. This work involved development of some effi cient test circuitry th at could reside along with the Device-Under-Test (DUT) on the same die. These embedded test circuits help in extracting useful information from high-frequenc y on-chip signals and converting them to lowfrequency (base-band) signals for easy transfer of information off-chip for post processing on an external, low cost, low frequency ATE. On-chip signal shape capturing circ uits using high-speed samplers and on-chip signal strength measurement ci rcuits were developed that can be used in embedded test of mixed-signa l integrated circuits.

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15 CHAPTER 1 INTRODUCTION 1.1 Background of ATE Based Testing Delighting customers by relentlessly delivering efficient products before competitors can deliver is the business plan of todays successf ul semiconductor companies. This has been the driving force and also the reason behind the succ ess of such companies. Not only delivering the product on time is important but also equally impo rtant is making sure th at the delivered product is a reliable and a fully f unctional product that meets the customers requirements. While the job of a systems engineer is defining and documenting the customers requirements, a circuit design engi neer is responsible for designi ng and developing the integrated circuit that meets the specifications. Unfortunate ly, after the design proc ess not all manufactured designs meet the specifications. Such failures ma y be caused by design flaws or process errors. A test engineer is responsible for identifying design flaws in th e design before the product is fabricated and shipped to the customer. In addition, the test engi neer identifies badly manufactured parts after a design is verified as good. The test e ngineers role is to generate hardware and software that will be used to gua rantee the performance of each device after it is fabricated [BR01]. Some of such hardware a nd software could go into what is called the automatic test equipment (ATE) or in the future reside on the same silicon as the device-undertest (DUT) commonly known as em bedded test or built-in-test. Automatic Test Equipment ATE is any automatic device that is used in th e IC manufacturing industr y to test electronic components ranging from simple components such as resistors, capacitors, and inductors to a more complex printed circuit boards and ICs after they are fabricated. While computer simulation tools are used as pre-silicon validation tools, ATEs are used fo r post-silicon validation for the circuit designs. A typical test using an ATE is shown in Figure 1-1. It involves applying

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16 various inputs, usually known as stimuli genera ted in the ATE to the device-under-test (DUT) and observing the response of the DUT. This res ponse is compared to a predetermined response in the ATE based on the specifications documented by the systems engineer to determine if the design is good (pass) or bad (fail). Figure 1-1. Conventional IC testing using ATE. This conventional IC testing wo rks well for simple integrated circuits oper ating at low frequencies. However, this method does not appe ar to be an attractive solution for todays complex multi-functional high frequency circuits due to the challenges and difficulties in ATE based testing described in the next sections. 1.2 Challenges in High-Speed IC Test In the past, the simple ATE testing approach described in the above section has been used as a functional verification test for integrated ci rcuits that operate at low frequencies. Extending this approach to a more robust testing of toda ys complex circuits operating at higher clock frequencies than before is not straightforwar d. Earlier, high-speed IC designers could only speculate as to why a particular design worke d. The true electrical pe rformance of these tiny circuits was impossible to measure at wafer leve l. With the advancements in high-performance, high frequency, on-wafer probes and probe stations, design engineer s could test and characterize

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17 circuits on-wafer, before the IC s were diced and packaged. In order to make such wafer-level testing possible, measurement systems have evol ved from the old rack-and-stack systems to extremely complex, million dollar systems with high throughput. Todays advanced manufacturing process integrating more system functionality in le ss silicon area is very common. This integration resulted in ha ving analog, digital, RF and microwave circuits on the same die (SoC, System-on-a-Chip) instead of having them as discrete circuits in a system: This led to difficulties and expense in testing the anal og, digital, RF and microwave circuits. 1.2.1 Cost Involved in IC Test The key challenge in the way ICs are tested toda y is the cost involved in the test. The cost of testing an IC has not been scaling at the same rate as th e cost of manufacturing the IC. Packaged dice are mostly tested in a two-fold manner: wafer-level testing and post-packaging testing while known-good-die, KGD are used in flip chip applications. Wafe r-level testing helps to eliminate catastrophically defective dice before packaging. The dice that pass this wafer-level testing are again tested thoroughl y for defects after they are p ackaged. Today, high-speed testers above 1~2 GHz are prohibitively expensive for low cost IC production parts. As an example, the Teradyne Catalyst tester can test up to 3 GHz but costs more than $1million dollars. This has made the testing of high-speed analog/mixed-signa l circuits very challe nging, particularly under the constraints of high quality and low price. In the past, despite the high production cost, high market prices of the products could still provide adequate profits. However, with increasing competition in the electronics industry such as in the markets of cellular phones, portable music players, portable computers, gaming consoles, profit margins are decreasing. Before, design and manufacturing were the major co mponents of the total cost, thus drawing little attention to testing. But with recent improvements in ma nufacturing and fabrica tion of circuits, the manufacturing cost has dramatical ly reduced thus making the cost to test the circuit a major

PAGE 18

18 component of the total cost. Unless fundamental ch anges are made to the way testing is done in the high-frequency regime, it might cost more to test complicated and high performance chips than to manufacture them in the future. Figure 1-2 shows the cost of silicon manufacturing versus the cost of testing, nor malized per transistor as proj ected by 2001 technology roadmap for semiconductors [ITR01]. The top curve shows the manufacturing capital pe r transistor and the bottom curve shows the test capital per transistor. Figure 1-2. Moores law for test : fabrication vs. test costs. It is clearly seen that there is a consistent reduction in chip fabrication cost per transistor that in turn drives the continue d expansion and evolution of the se miconductor business. It is also observed from the graph that the capital expenses for IC test have been essentially flat per transistor and is projected to reach the projecte d manufacturing costs per transistor by year 2012. This challenge posed by the cost involved in th e testing of ICs should properly be addressed today to avoid any unexpected surprises to the electronics industry tomorrow.

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19 1.2.2 Increased Integration of System Functionality Semiconductor transistors are becoming so cheap and commonly available that whole industries now live on continuously integrating more and more functions into smaller and smaller packages, hence creating system-on-chips. The trend toward more system functionality on a single die (SOC) or in a single package (SIP) will increasingly blur the lines between traditional digital, analog, RF/microwave and mixed signal devices. This trend will drive test equipment toward a single platform solution that can test any application. Being able to rapidly test, diagnose and verify complex new chips and products using such chips is crucial for the continued success of our economy. This growth is e xpected to continue full force at least for the next decade, while making possible the production of billion transistor chips. Figure 1-3 shows the drastic increase in the number of transistor s integrated on a microprocessor over the past three decades [Rus04]. Figure 1-3. CPU transistor count trend Moores law. According to Moores law, the number of transistors on a chip doubles every 18 months. For the discussion here, this trend can be underst ood in a different way. The functionality that is achieved on a certain area of silicon is doubled ev ery 18 months. If this trend is followed by the

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20 industry, which is expected to be the case for at least the next decade, everything that performs signal processing and data processing on the prin ted circuit board may be moved on to the same chip. For a test engineer, unlike in the past, in stead of testing limited functionality on a discrete integrated circuit, the challeng e is to perform more robust te sts that validate the full multifunctionality of the chip. More and more SoCs are being able to be realized by the unprecedented reduction in the feature size. As shown in Fi gure 1-4, a new technology is introduced every two years [Boh03]. Figure 1-4. Feature size tr end in IC manufacturing. Another challenge with this d ecreasing feature size c oupled with complex integration is the inaccessibility of test points on the wafer in testin g ICs. This makes certain characteristics of the DUTs immeasurable using existing testing met hods. At the same time, as the density and complexity of circuits increases, the number if input/output pins increas es much more slowly, thus the need for added testing pads and increas ed placement precision of testing probes is more and more demanding and expensive.

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21 1.2.3 Increased Speeds of Operation MOS transistors in the deep sub-micron regime have unity gain frequencies in the range of one hundred gigahertz, indicating a capability for creating signals with high bandwidth internally on a chip. Also, penetration of high-speed interf aces (Gigabit-per-second I/O) into new designs is increasing dramatically. The trend toward fast er high-speed serial interfaces and an increased port count will continuously drive the need for ef ficient methods of high-speed analog/digital testing. Figure 1-5 shows the current micr oprocessors clock frequency trend [Rus04]. Figure 1-5. CPU clock freque ncy trend Moores law. Current test methodologies are challenged by the number of high clock speed nodes in the circuits. Testing is usually done at less than th e circuits targeted opera ting speed but a circuit that passed a low-speed test may fail when operate d at full speed. With the advent of SoCs, this problem is greater than before. High-speed domain testing can be done by resorting to the use of very expensive high-frequency testers that incl ude specialized membrane probes, picoprobes and E-beam probers. The usage and in-lab maintenan ce of this expensive equipment to perform at-

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22 speed tests on the ICs adds enormously to the overall test cost involve d and leads to the case where test cost exceeds manufacturing cost. In brie f, it is vital to perfor m low cost but at-speed chip/package/board observation of high-speed ci rcuits performance prior to IC prototyping. 1.2.4 Time Involved in IC Test Time to market is a pressing issue because profit margins for a new product are highest shortly after it has been released to the market Margins begin to shrink as competitors introduce similar products at lower prices. The lack of a complete, cost-effective test methodology is often a bottleneck preventing the release of a new product for profitable volume production. In the case of I/O verification expe riments which are limited and under extreme time pressure, unexpected loading parasitics, mismatches and coupling in the packages and boards add weeks or months and can make a new digital IC mi ss its profitable market window. Mainframe ATE systems are designed to minimize test time and maximize overall product throughput. Figure 1-6 shows the relationships between te st cost and test time; the info rmation source is from IBM test development group [IBM02]. The comparison is made between a $2M tester and a $100K tester. The plots show that the test cost/part is entirely a function of time. Total test time includes tester capability/speed (electrical test time), handler /tester/controller communications time, handler capability and index time of handler. One second of test time can cost three to ten cents. This may not seem expensive at first glance, but when test costs are multiplied by millions of devices a year the numbers add up quickly. For example fr om the available data in Figure 1-6, a foursecond test program costing approxi mately sixteen cents per part on a $2M tester and nine cents per part on a $100K tester times one million devices per quarter costs a company $640,000 and $360,000 respectively per year in bottom-line profit. As a result, the test community is not able to keep pace with the test requirements of highspeed, integrated wireless and wired communica tion designs. It is time to look for innovative

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23 methods to circumvent these challenges, methods that offer the possibility of low cost test methodologies, at-speed testing tech niques and quicker time to market that help to maximize the profit margins. Only then can the test technique s catch up to the pace of the design techniques. Figure 1-6. Cost contributors to te sting a part for va rious test times. 1.3 Potential Solution to the Challenges For speeds beyond a gigahertz, built-in-test (BIT) of high-speed systems is a very attractive solution. Built-In-Test involves desi gning and integrating te st hardware on-chip, supporting the test hardware with design-for-te stability features and designing in standard communication protocols that allow an external tester to contro l the test procedure with low bandwidth access and hence, lower cost external testers. In the past, design engineers were sometimes reluctant to add testab ility features to a device, sin ce BIT added design cycle time, die area, and/or power consumption. Fortunately, th e attitude has changed in recent years from reluctance to acceptance as design engineers have seen the competitive advantages of BIT. Now some companies see BIT as a major technological differentiator that can reduce production costs, enhance quality control, and even provide customer s with value-added testability features for use in their system-level products.

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24 Design-for-test (DfT) is a major topic of interest in the testing field. Any circuit design that results in a more easily or t horoughly testable product can be categorized as DfT. There are many types of DfT. Some DfT concepts are based on built-in circuits that allow easier or more complete testing. The choice of DfT approach depends very much on the specifics of the device under test (DUT) and the demands placed on it by its system-level applica tion. Built in self-test (BIST) or embedded test circuits allow the de vice-under-test (DUT) to self-evaluate quality without elaborate automated test equipment (ATE ) support. With BIST, low cost testers can be used to perform high-speed IC testing. The lim ited tester resources required by BIST and the ability to perform parallel testing of multiple ci rcuits on the DUT are key advantages of BISTbased testing methodologies. The fundamental appr oach in embedded test or BIST is to move very high-speed test functions on-chip, thus re ducing the requirement of and the cost of the external test. This move, however, is not straig htforward, and still in the development stage. Analog BIST technology has lagged behind digital BIST because of difficulties in guaranteeing accurate signals generated and measured on-chip. However, analog embedded test techniques will improve the circuit controllability and circuit observability. 1.4 Organization of the Dissertation This section describes the or ganization of the dissertation. The work presented here concentrates on the solutions to issues arising from the need for developing efficient test methods for high-speed digital/anal og integrated circuits. The current chapter (Chapter 1) introduces the reader to the background of testing integrated circuits using ATE syst ems, and cost involved in such solutions. This is followed by the challenges that the test community is facing in the sub-micron regime. Built-in-test (BIT) or embedded test is briefly introduced and discussed as a potential solution for such challenges.

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25 In Chapter 2, the differences between Dig ital BIST and analog/mixed-signal BIST are discussed before introducing the current approa ches in Analog/Mixed-Signal (AMS) embedded test and the concept of alternat e test using feature-extracting circuits. The importance of area efficient signal feature extracting circuits that enable alternate test in the BIT is explained. These feature extractors reside on the same die as the device under test (DUT). Motivation and contributions of this research work to the areas of integrated circuit testing is described in this chapter. On-chip signal waveform shape capturi ng circuits and on-die si gnal strength detectors are developed as a part of this work. The scope of this research and its goals are discussed. Chapter 3 describes novel archite ctures proposed for capturing on-chip events following a triggering event. Complete analysis involving ti ming issues and the effects of timing errors on the performance of specific ar chitectures is described. Mathem atical observations and system analysis are verified by modeli ng and simulating the architectu res in MATLAB. Prototypes of the circuit are designed using AMI 0.6um proces s and this chapter describes the measurement results of the performance of th e circuit in capturing an event on the DUT (on-chip interconnect). Design of delay generators and reliable high-speed samplers that can be used in the architectures presented in Chapter 3 are discusse d in detail in Chapter 4. While the prototypes of the snapshot architecture are fabricated usi ng AMI 0.6um process, design techniques for the circuit in state-of-the-art processes such as 0.18um technol ogy and 65nm technology are also discussed in this chapte r. Improved switches usin g bootstrapping technique are introduced in this chapter for sampling signals that extend beyond supply range (overshoots and undershoots). As an application, the use of such switches in obser ving on-die signals in highspeed I/O circuits is presented.

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26 Detectors play an important role in the embedde d test of circuits. A ccurate measurement of signal strength at various places is almost indispensable. Chapter 5 describes in detail about the theoretical analysis of signal strength indicators. Complete mathematical analysis of the operation followed by error analysis involved in the powerful successive detection architecture of logarithmic amplifiers (alternatively called as RSSI) is also provided. The circuit design details and the measurement results of a cascad ed limiting amplifier based log amplifier using triple-well NMOS devices as lo ads are presented. As an applic ation, the use of such signal strength indicators in substrate noise measurement is discussed. Finally, Chapter 6 summarizes the dissertati on and concludes by discussing about the future work involved in the design of proposed signal feature extractors.

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27 Figure 1-7. Organiza tion of dissertation.

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28 CHAPTER 2 EMBEDDED TEST FOR ANALOG/MIXED-SIGNAL IC 2.1 Introduction Challenges and costs posed by the conventional ATE methods discussed in Chapter 1 have been driving researchers to create new solutions for testing todays ICs. Embedded test proves to be an attractive solution. This approach involves embedding various power and area efficient test circuits on the same silicon as the device-under-tes t. During the test mode of the IC, these test circuits help to diagnose the performance and functionality of the DUT. With a typical ATE, high frequency test signals need to be transp orted across the board-pa ckage-chip interface for test stimulus excitation or signal measurement. The variations in the load board signal loss, package-load board crosstalk, frequency limitations of the encapsulating package, mechanical placement in the connections to IC packages and lower speed external I/O channels can create large uncertainties in the amount of power delivered in the test si gnals to the DUT from the ATE. This could lead to either reje cting good ICs or accepting bad IC s during the manufacturing test. These issues motivate development of new designs for test paradigms for high-speed BIST. An alternative to this ATE approach is to limit the high frequency communication to on-chip and eliminate high frequency signals between DUT and the external tester. The next section in this chapter presents digital BIST versus analog BIST with an emphasis on answering the question, Why is it diffi cult to port digital test methods to high frequency analog/mixed-signal test? Existing appro aches such as direct measurement of circuit specifications and alternate test strategies fo r RF/analog/mixed-signal embedded test are also presented in this chapter. Finally, the motivati on behind and a brief introdu ction to the circuits developed in this work are presented.

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29 2.2 Digital BIST versus Analog BIST For quite some time, built-in-self-test techniques have been integrated into digital circuit designs so they can be tested. In digital IC te st, the terms functionality and performance of a circuit have been clearly disti nguished in their definitions, whic h unfortunately is not the case with analog/mixed-signal test [Vin98]. Validatin g the truth table specified by the designer is enough to determine if a digital circuit meets the required functionalit y. Mapping between a set of output vectors and a set of i nput vectors is represented in a truth table. The performance specification is defined mostly by th e speed of the digital circuit. In most cases, it is specified by the delay an analog quantity of the circuit. On the other hand, in AMS test the circuit properties and its behavior is so different from the digital circuits behavior that it blurs the lines between the definitions of the terms func tionality and performance. These te rms are closely knitted in the testing of analog circuits. Unlike digital circuits where separate fault models and algorithms can be developed for functionality and performance, it is not only difficult but at times it is also impossible to develop such models for AMS circ uits. In circuits such as data converters, structural fault models have been shown to adequately model faults that affect the I/O relationship [Vin98]. However, ci rcuit structure alone does not de termine performance. Altering device sizes while preserving topolog y can substantially a lter performance. Thus, it is harder to establish a quantitative relationship between a st ructural fault model a nd circuit performance. Digital BIST is far more advanced than anal og/mixed-signal BIST. The primary reason is the absence of a widely accepted common methodolo gy for analog and mixed-signal circuit test. Stuck-at fault models and validation of the fo rmulated truth tables have been the primary methodology for digital integrated circuits. Rese archers in analog test have been strongly influenced by the success this methodology and have started to create simila r techniques that can be applied to analog integrated circuits. Howeve r, there is a substantial difference in the way

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30 analog ICs need to be tested when compared to digital ICs. Two significa nt factors that can be attributed to this difference are presented. First, every analog/mixed-signal circuit has a unique set of sp ecifications. For example, the set of performance specifications for a data converter is different from the set of specifications for an operational amplifier. Correspondingly, design procedures and design techniques for analog circuits tend to be circuit-specific. No ge neral design techniques a pplicable to all analog circuits exist. A complex analog circuit comprisi ng of sub-blocks would need a complex set of tests written for each sub block so that the specifica tions of the circuit are validated exhaustively. Second, an analog signal at a node in a circuit can possess infi nite number of values where as in digital circu its the set of allowed values at a node is clearly defined. It is very easy to develop a test or an algorithm or a model to de termine a fault at a node whose value is specific when compared to developing a test to determ ine a fault whose value is not uniquely defined. Though analog signals can theoretically have any value within a ra nge specified by the technology, any particular node in a circuit is allowed to vary around a nominal value defined by the specifications. This variati on around the nominal value is calle d tolerance of the node. For a node, any value outside its tolerance can be c onsidered as faulty. The accuracy with which signals are generated and measur ed on-chip is one of the r easons why analog BIST technology has lagged behind digital BIST technology. Also, digital circuits can be separated into sub circuits using a divide-and-conquer approach. The properties of these sub circuits are less dependent on each other. As a result, testing of blocks individually can almost guarantee a fully operational complete system. However, the interdependence amon g individual circuits that ma ke a whole analog/mixed-signal system is very complex. Analog circuits have cr osstalk problems and other interactions between

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31 circuits. The divide-and-conquer approach is ne cessary for characterization, but it may not be sufficient to guarantee the system-level specif ications. These are some of the differences between digital and analog/mixedsignal circuits that have made it difficult to use the same successful digital DfT techniques in analog circuits. Having said that, the next section details about the different existing approaches in analog/mixed-signal/RF circuits in SiPs. 2.3 Approaches in Analog/Mixed-Signal/RF Test In BIT applications, an important test quality metric is the area overhead, the percentage of extra area introduced by tester rela ted electronics. Embedde d test only is justified if the area is relatively small. This is a factor in deciding whet her certain test structur es should be migrated on to the actual die area or to th e proximity of the DUT on the load board [CAHK04]. In either case, the goal is to improve the test-access spee d, minimize signal degradation and increase controllability and observa bility of the signals internal to th e DUT. The circuit can have the test support functions implemented within the device. This enables to apply test throughout the life span of the product as a post-manufacturing test. A lternatively, the circuit under test can be seen as an end product without having dedicated test circ uitry internal to the de vice. In this case, the test support circuits known as verification structures are bu ilt around the device. This is commonly known as BoT (Built-off test). This is the common technique used for silicon verification and design debugging. Th ese verification structures for high-speed designs are built around the prototype devices to ensure the corre ctness of the design and the viability of the process. If necessary, the desi gn is altered, new prototypes are built and new sets of tests are applied until an optimum design is obtained. Af ter validating on-chip signal (e.g. microprocessor signal) performance at key inaccessible nodes, thes e verification structures are removed and the devices are produced without built -in verification structures.

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32 Shown in the Figure 2-1 are the various load boards that are used in testing [CAHK04]. Figure 2-1(A) is the load board in the conve ntional ATE measurement setup. It does not have either built-off test or built-in test features. Tester electronics reside completely in the ATE. This is suitable for low frequency te sting. Figure 2-1(B) shows the load board that is commonly used for silicon verification or design debugging. These DUTs end up as products without any integrated tester capabilities. Area metric or area overhead is not gi ven a high importance in these built-off test strategies. Some of the test metrics are compared between BoT and BiT in Table 2-1. Figure 2-1(C) shows the true built-in-te st strategies where all the high-speed tester electronics reside along with the device under test. These DUTs have integrated tester capabilities even after production. 2.3.1 Direct Measurement of Circuit Specifications In direct measurement of circui t specifications, appropriate te st stimuli are applied and the corresponding test response is measured to validate a circuit specification. Each circuit specification needs appropriate tester resources. Some examples are multitone signal generators for measuring distortion, gain for codec, and so on [CAHK04]. This approach is in complete agreement with the traditional production test appr oach for analog and mixed signal circuits that uses similar test stimuli and conf iguration with respect to which the specification is defined and documented by the systems engineer. For direct measurement techniques, tests are performed sequentially one by one. Relays are used to switch between different test sets and equipment for test when the specifications needed to test on a circuit are incompatible in environment. Several BIST techniques in the available literature have shown the applicat ion of this approach. For instan ce, different implementations of on-chip signal generators and test response data acquisition circu its are reported [CEF03, YEF04, ZEF04]. Signal source in [CEF03] demons trated the capabilities of generating pure

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33 A B Figure 2-1. Load boards for IC test. A) For conventional ATE test. B) For silicon verification/design deugging, built -off test (BoT). C) For ge neral built-in test (BiT)

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34 C Figure 2-1. Continued. Table 2-1. Comparison of builtoff test and built-in test Built-off Test Built-In Test Area Importance Less to Moderate High Controllability/Observability Moderate High Signal Degradation Moderate to High Less Applications Silicon verification and Design debugging Suitable for all high-speed applications Tester Electronics in the endproduct No Yes

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35 sinusoidal signal thus enabling th e self-testing of analog/RF bloc ks within the package. The application of on-chip samplers using sub-samp ling technique has been demonstrated in [LS93, SZ03]. All these circuits demonstr ate the feasibility of in-situ characterization and testing of performance of high-speed analog/RF circuits. Direct measurement techniques have certain drawbacks. As the tests are perf ormed sequentially with circuit specification specific hardware resources, these techniques lack the abili ty to simultaneous measurement of multiple specifications. In the case of evaluating multiple specifications this methodology results in large area overhead and longer test times. 2.3.2 Alternate Test for Circuits Integration of more functiona lity and performance into a single device increases the number of specifications that need to be tested. Like discussed in direct measurement of circuit specifications, sequential testing of todays circuits would result l onger test times. Also, each test would require different equipment or different load board resources. This results in increased test cost. The concept of alternate test was pr oposed [CAHK04, ATRCA06, VC 98] to address these issues and reduce the cost and time involved in testing analog/RF ICs. In this methodology, a complete suite of sequential specification tests is replaced with a single test, consisting of a carefully crafted test stimulus applied to the device-under-test. After finding the suitable transient test stimulus, this appr oach relies on the fact that if the response of a circuit-under-test to an alternate test stimulus is sensitive to al l process variations that also affect its test specifications, then it is possible to predict all its test specifications from the test response without having to measure the specifications explicitly. Figure 2-2 shows the variations in process or circuit parameters and their effect on circuit specification and test [CAHK04]. Consider a vect or P defined as the process parameter space consisting of p process parameters, a vector S de fined as the specification space consisting of s

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36 Figure 2-2. Alternate test with response feature extraction test specifications and a vector R defined as the response/measurement space corresponding to the applied alternate test stimul us. A variation in the process parameter space P may or may not cause a variation in the specifi cation space S by a corresponding sens itivity factor. If there is no perturbation in S we need not be concerned about the variation in P. Otherw ise, the variation in P also affects the measurement data in the response space R by a corresponding sensitivity factor. So if there is a variation in response space R, then the variation in P can be determined from the measurements/responses rather th an the specifications. In genera l, there exists a nonlinear mapping function for any point in P onto the specification space S denoted by f: P S. Similarly, there also exists a mapping from any point in P onto the response space R denoted by f: P R. Therefore, if the measurements are designed in su ch a way that any arbitr ary variation in P that causes a variation in S also causes a variation in R, then it follows that the specification tests in S

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37 can be replaced by measurements R as all process variations that affect the performance of the DUT can be detected by the measurements R. In th is case, it follows that there exists a mapping f: R S that can be used to compute the valued of all the DUTs specifications S from the transient or AC response measurements R. First, the goal is to find a de terministic or pseudo-random test stimulus input such that the response R of the circuit under test to the applied s timulus is sensitive to a ll process variations in P that also affect its specifi cation space S. So, initially conve ntional tests are run on the DUTs from various fabrication runs in order to de termine the nonlinear mapping functions between the spaces. Several papers in the l iterature reported the successful application of alternate test approach to circuits such as op-amps, filter circuits, and high-frequency RF modules while mentioning that response acquis ition circuits in alternate tes ting of analog/RF modules is difficult and still in the development stage. 2.4 Motivation and Contributions of this Work The key to success in any of the above-dis cussed methodologies in analog/mixed-signal embedded test lies in creating (Figure 2-3), On-chip high quality test signal gene rators or stimuli generators, and On-chip test response data acquisition circuits. Data acquisition circuits also called as feature extractors [CA HK04] are used in both direct measurement of circuit specifications and de riving the nonlinear mapping functions between various parameter spaces in the alternate test. Th is research work addres ses two important kinds of these circuits, Capturing a snapshot of on-ch ip signals waveform shape Measuring on-chip signal strength

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38 Figure 2-3. Test setup and c ontributions of this work 2.5 Capturing Signals Waveform Shape Increasing unity gain frequencies of todays tr ansistors enable circu it designers to design very high-speed on-chip circuitr y [LS93]. To understand various signal integrity problems such as crosstalk, supply noise and ground bounce in thes e high-speed systems it is essential for a test engineer responsible for validating and testing the functionality of th e chip to be able to look at the high-speed real-time behavior of on-chip signals. For exampl e, real-time behavior of the signal on a Vdd line in a complex di gital circuit contains informa tion about the amount of current drawn from the power supply at a clock event triggering the dig ital gates in the circuit. The L(di/dt) noise details of the line can be extracted from this waveform. Similarly, shapes of clock signals at the start and at the end of a long on-chip interconnect can be studied to determine the delays in this interconnect, and degradation of rise/fall times caused by this interconnect.

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39 However, preserving the shape of an on-chip waveform and exporting it off-chip without degrading signal quality poses an interesting challenge. Capturing techniques of an on-ch ip signals waveform shape can be broadly classified into two types, (1) off-chip techni ques (2) on-chip techniques. 2.5.1 Off-Chip Techniques Off-chip techniques are usually invasive wher e as on-chip technique s give less invasive time-domain information of waveforms. Some of the common off-chip techniques fo r characterizing on-chip signal integrity [CBS01] are Low frequency probing methods E-beam probing S-parameter measurements Time-domain reflectometry Probing methods: This method uses high-impedance pr obe tips to probe a required signal node on silicon directly. This el iminates the signal transmissi on through the package leads and board traces, which adds a lot of capacitive and inductive parasitics. However, in order to be probed on the silicon, the signal needs to be pr obed via a metal area where the probe tip is landed. This metal adds capacitanc e and can effect the measurement. The loading of the probes also effects the measurement. Effective calibrati on techniques need to be employed to cancel such effects. These drawbacks confine the measurement to few gigahertz ranges. E-beam probing: Measurements using E-beam probing are completely non-invasive as it is a contact less measurement. There are no lo ading effects of the measurement equipment involved. However, the disadvantag es are it requires a very expensive measurement setup and requires top-level metal to carry the signal to be measured.

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40 S-parameter measurements: At high frequencies, Eo and Eisenstadt [EE93] described a technique to determine the characteristic im pedance of a transmi ssion line including the conductance effect of the line and capacitance variation due to varying permittivity. The sparameters of the line under test are measured by a probe-tip calibration w ith those of an ideal transmission line. This technique which has been improved upon is widely used as the preferred way to obtain high frequency characterization of interconnects by givi ng the interconnect sparameters. Time-domain reflectometry: A time-domain reflectometer is similar to VNA but operates in the time domain. It emits a fast rise-time st ep signal, and measures the reflected transient amplitude. Again, using the reflected voltage, th e impedance of the line under test can be extracted. In the time domain, the impedance m easured represents the instantaneous impedance. Although this method effectively characterizes the package and PCB trace impedance, the crosstalk effects between on-ch ip interconnects cannot be char acterized precisely. Comparison between various off-chip methods is shown in Table 2-2 [VB04]. Table 2-2. Comparison between off-chip methods Probing techniques E-beam probing S-parameter techniques Time-domain reflectometry Bandwidth <1-2GHz 10GHz 70GHz 15GHz Cost High Very High Very High High Measurements Dynamic Dynamic Impedance Dynamic Drawbacks invasive, loading effects of the probetips requires availability of signal on toplevel metal, very expensive calibration needed, conversion of msmts. to timedomain specific test patterns

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41 2.5.2 On-Chip Techniques On-chip techniques to measure the shape or analog properties of signals rely on sampling techniques. The challenge here is to capture the details of a fast changing signal. A sub-sampling technique is most commonly used to sample an on-ch ip signal that is periodic or a signal that is made repetitive by having the IC operate in test mode rather than in its normal operation mode. The shape of the signal is reconstructed off-ch ip. In this type of sampling, high-frequency information of the signal is converted to low fr equency that can be easily transported off-chip without degradation. Sampling techniques offer a less invasive time domain measurement of waveforms. The idea is to deploy on-chip samplers at various places of interest on the chip to sample the node information. The information captured by th ese can be used not only to analyze various signal integrity issues in a high-speed system but also to generate models for validation and simulations to emulate the electric al behavior of on-chip circuit elements. Some of the causes for unwanted effects of parasitics such as de lay, crosstalk, supply and ground bounce, and the application of samplers to character ize them are briefly discussed here. Interconnect delay measurement: Transmission line is the term that is commonly used for todays interconnects. An interconnect can be considered as a lumped element or a distributed RLGC model depe nding on its physical lengths relation to the wavelength (frequency) of the signal that it is carrying. As a rule of thumb, if the physical length of an interconnect is larger than one-t enth of the wavelength of the signal in the line it should be considered as a distributed line. When interconnect response is treated through distributed RLGC models, the voltage along the le ngth of interconnect is not co nstant but is position and time dependent. The signal takes a finite time to trav el across this interconne ct and gets distorted because of the lines lossy circuit elements (R, G) in the model. Therefore, the signal is delayed

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42 and attenuated at the other end of this interconne ct. Deployment of the sa mplers at the beginning and at the end of such a long in terconnect will help in capturi ng the waveforms at these nodes from which the delay can be measured (Figure 2-4). Figure 2-4. Application of sample rs to measure interconnect delay Supply and ground bounce characterization: Simultaneous switching of gates in an IC at clock events causes the circuit to draw a huge amount of current from the power supply generating current spikes. Power supply lines are re sistive and inductive in nature and so these current spikes cause the voltage on a power lin e to bounce from its ideal Vdd or ground levels. This noise is commonly referred to as the L(di /dt) noise in digital circuits (Figure 2-5). Application of samplers to measure this noise fr om the shape of waveform is shown in Figure 26. Crosstalk characterization: Crosstalk happens when a signal transition on one interconnect effects the signal on the nearby interconnects. The fo rmer is called the aggressor and the later is called the victim. The coupling of energy between the aggre ssor and the victim as a result of mutual capacitance (electric field) and mutual inductance (m agnetic field) provides a path for unwanted noise from one net to the other.

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43 Figure 2-5. L(di/dt) noise generation in circuits Figure 2-6. Application of samplers to characterize supply and ground bounce Figure 2-7. Application of samplers to characterize crosstalk effects

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44 2.6 Measuring On-Chip Signal Strength Signal-strength measurement circuits play an important role in the embedded test of circuits. Accurate measurement of signal strengths at various locations on a wireless chip is almost indispensable. In addi tion, in mobile communication syst ems, knowledge of the strength of the received signal by the receiver is essential to mon itor and control the signal levels transmitted by the base station. Constant mon itoring of the transmitted and received signal strengths can help in dynamic adjustments of the power transmitted by the base station that reduces the power consumption. Bu ilt-in-test problem may be br oken down into two aspects. First, the DUT must be stimulated with the help of high-speed test stimulus generators developed on-chip and second, the DUTs response should be an alyzed with the help of high-speed on-chip acquisition circuits. Signal strength detectors can be used as part of a data analyzing circuit. Typically two types of circui ts are being used, peak dete ctors and rms detectors [YEF04. ZEF04]. A limiting amplifier based detector in this work gives an indication of amplitude of the envelope of the input signal in the log domain. This is useful in calibrating other test circuits, which ensures they work correctly, measuring signals entering the device, which ensures the input signal is within the de sired specifications. The meas urements however depend on the accuracy and calibration of the detector. It is desi rable that the characteristics of the detector be less dependent on process variations and has high accuracy in the detect ion. Besides accuracy it is necessary that the detector ha ve high bandwidth and dynamic range.

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45 CHAPTER 3 CAPTURING ON-CHIP SIGNAL WAVEFORM SHAPE 3.1 Introduction Current test methodologies are challenged in te sting circuits that are operated with high clock speeds. It should be noted th at there is no guarantee that a signal at a node in the circuit operated in the test mode is exactly the same as it is when the chip is operated at full speed. For example, supply noise is not periodic on a chip during its normal operation. Autocorrelation of the supply noise can be used to measure the no ise spectrum by treating supply noise as a random process [ASH05]. However, an id eal solution is to measure a full time-domain waveform during the chips at-speed operation. While realizing such a system is difficult, a novel architecture is proposed in this chapter that wi ll enable sampling a signal in r eal time for a certain period of time following a triggering event. The sampled valu es are stored and can be exported off chip easily. Real-time behavior of the signal on a V dd line in a complex digital circuit contains information about the variations in the current demands of a circuit from the power supply during a clock event triggering the digital gates in the circuit. The L(di/dt) noise details of the line can be extracted from this waveform. This noise is seen as voltage transi ents such as ringing, overshoots and undershoots on the si gnal. Effects of parasitics are more pronounced for signals with high frequency content. Amplitudes of these unwanted voltage transients on the supply line are highest during and immediately after the cloc k transition as the frequency content in the signal at the transitions is very high. The effects of the parasi tics die down gradually when the clock signal is stabilized. In t odays microprocessor where the num ber of transistors is in the order of billions, the noise generated can be cata strophic for the functionalit y of the circuit. This problem should be properly addressed by techniques such as sufficient bypass capacitors, voltage

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46 regulators etc that keep the voltage transients with in the acceptable range in order to deliver as much performance as possible while maintaining reliable operation. Figure 3-1 shows the fluctuations in the pow er supply of a microprocessor due to large di/dt and IR events [MTRA04]. The fluctuations are a result of th e interaction of the parasitics with changes in current demand. Clearly, the demands are highest at the clock events. Figure 3-1. Microprocessor pow er supply line fluctuations. Preserving the shape of an on-chip waveform and exporting it off-ch ip without degrading signal quality is not easy. An architecture capab le of taking snapshots of signals for a certain length of time following a triggering event is demonstrated in this chapter. Timing issues such as clock skew, clock jitter and thei r effects on this architecture are also discussed in detail here. While this chapter deals with the system anal ysis, performance, measurement results of the complete architecture of a device-under-test (on-di e interconnect), the next chapter deals with the circuit design details of indivi dual blocks in the architecture a nd their stand-alone performances and measurement details for system characterization.

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47 3.2 Proposed System Architecture In order to be able to capture enough details describing the signal at a node on the chip, the signal needs to be sampled in real-time at very high-speed. High resolution in the sample points is important for an effective characterization of the signal. Sampling at high-speeds requires a very high-speed clock. The architecture shown he re in Figure 3-2, however, does not require a high-speed clock to provide samples of the signa l with high resolution. The signals of interest here are triggered in the devi ce-under-test by the clock signal a nd are sampled by a number of parallel samplers each using th e same low frequency clock (Peri od = T). Notice that the sampling instants of two consecutive parallel samplers ar e separated by a certain delay, t to achieve the resolution in the sample points. This way each sampler captures new information about the signal. In essence, the sampli ng of the input signal is perfor med in real time unlike a subsampling technique where each sample of the inpu t periodic signal is taken in a different period. The parallel outputs are then extracted and the sa mples are interlaced with the timing information of the delay between the parallel samplers to reproduce the original signal. In this case, effective sampling rate = 1 t ; length of the snapshot = ( K 1) t ; K = number of parallel samplers; t = delay between sampling instants of two consecutive parallel samplers. Increasing the number of input samples can in crease the signal to noise ratio of the reconstructed signal. Figure 3-5 shows a modified version of this archite cture that takes more samples of the signal. By making the input si gnal repetitive and usi ng a Vernier delay line (VDL) a fine adjustment of the resolution or time spacing between the samples can be achieved.

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48 Also, compared to the earlier architecture, this modified version requires fewer parallel samplers to capture the same number of signal sample point s. The delay line is used to provide two clock Figure 3-2. System Architecture signals (CLK1, CLK2). The condition on the sele ct signals for the decoder/multiplexer in the delay line determines the delay between the cloc k edges of the two signals as shown in Figure 33. The minimum delay between CLK1 and CLK2 is the effective resolution (td) between signal samples.

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49 Figure 3-3. Vernier delay line (VDL) CLK1 is called the event-triggering clock a nd is connected to the DUT. CLK 2 is called the sampling clock that propagates in the para llel samplers. The sampling instants of two consecutive parallel samplers ar e separated by t. Consider, for example, that enough details of the shape of one period of the signal are obtaine d by interlacing 16 sample s with a spacing of td between each sample. Then, the architecture in Figure 3-2 needs 16 para llel samplers with a delay td between the sampling instants of any two consecutive samplers. However, in the case of the modified architecture, if the mi nimum delay between CLK1 and CLK2 is td then different delays such as td, 2td, 3td, and 4td can be achieved with a decoder/multiplexer that has 2 control bits. Effectively, 16 sample points are obtained with just 4 pa rallel samplers in this case. In general, for this architecture, effective sampling rate = 1 t ; length of the snapshot = ( K 1) t 2mtd; K = number of parallel samplers; t = delay between sampling instants of two consecutive parallel samplers;

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50 td = minimum delay between CLK1 and CLK2; m = number of select bits to the decoder/multiplexer in the VDL. Figure 3-4 compares the sampling instants of different samples of the signal between the two architectures. A large numbe r of samples is obtained from the modified architecture for different select conditions on the Vernier delay li ne. However, the input signal has to be made repetitive. Figure 3-4. Comparison of sampli ng instants. A) First architectur e. B) Modified architecture. Another important advantage of the modified ar chitecture is it has less noise due to timing errors in the sampling instants if the Vernier delay line generates exact integral multiples of minimum delay (td) for different select conditions. This is explained later in the discussion about clock skew. 3.3 Errors in Timing Instants of the Samplers This section discusses the effect s on the output signa l from the snapshot architecture due to errors/offsets in actual timing instants from ideal instants (i.e., clock sk ew, clock jitter) for the

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51 Figure 3-5. Modified system architecture parallel samplers. The occurrence of such deviations in the sampling instants gives rise to a timedistorted output signal. Clock skew and clock jitter are two different terms that describe different effects on the architectures performance. While cloc k skew is defined as a constant timing offset in the sampling edge of the clock from the ideal sampling edge, cl ock jitter is a random

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52 distribution of the sampling edge around the actual sampling edge of the clock (Figure 3-6). Therefore, clock skew is deterministic and cloc k jitter is random. While clock jitter error in sampling instant gives rise to an increased noise floor, constant clock skew error gives rise to unwanted spectral lines in the out put spectrum. However, both eff ects add noise in the spectrum and degrade signal to noise ratio of the output signal. Figure 3-6. Clock skew and clock jitter 3.3.1 Effects of Random Clock Jitter Consider an input sinusoidal signal V in( t ) A osin(2 f ot ). When this signal is sampled by a jitter-free clock of frequency f s (period = T s ), then the output time disc rete samples are given by Vout[ n ] A osin(2 f on T s ). (3-1) Now, assuming a random variable for jitter (tj) that follows a Gaussian distribution N (0,j 2), the actual sampling instant occurs at t nTs tj and the actual output time discrete samples are given by Vout[ n ] A osin(2 f o( nTs t j)). Therefore, Vout[ n ] A osin(2 f on T s)cos(2 f o t j) A ocos(2 f on T s)sin(2 f o t j),

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53 If random jitter variable tj is assumed to be much less than T s then Vout[ n ] A osin(2 f on T s) A o2 f otjcos(2 f on T s). (3-2) In Equation 3-2 the jitter term is separated fr om the signal term. Therefore, from Equations 3-1 and 3-2, voltage error due to jitter is given by, Vj[ n ] Ao2 f o t jcos(2 f on T s) Vj[ n ] dVin( t ) dt t nTs tj This implies that timing error due to jitter woul d cause large sample error at fast transitions of the input signal. The noise power value due to jit ter is given by, Pj V2 j RMS[ n ] Ao2fo2 2j 2 22fo 2Ao 2j 2 (3-3) This noise power due to jitter is seen as the noise floor in the output spectrum. The architecture in this discussion has been mode led behaviorally in MATLAB and the simulation results of the output spectrum without and with jitter (MATLAB function: normrnd(mean,variance,rows,columns) ) are shown in Figure 3-7. Noise floor seen here is the effect of random Gaussian jitter in the clock si gnal for the samplers. Here in the simulation, 8 parallel samplers are considered and for now clock skew in the delays between parallel samplers is assumed to be zero. Hence there are spectral lines only at the input signal frequency. Input signal frequency is 25Hz and sampling frequency is 100Hz. 3.3.2 Effects of Deterministic Clock Skew Presence of clock skew, a constant offset in the sampling instant from its ideal sampling instant, causes unwanted noise represented as sp ectral lines in the spectrum of the output sampled signal. The following discussion analyses the architecture with and without a Vernier delay line. The number of noise spectral lines in the output spectrum is less for the modified

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54 A B Figure 3-7. MATLAB simulations for jitter. A) Jitter-free sampling. B) Sampling with jitter architecture using a Vernier delay line. A mathema tical expression is derive d to prove this effect of the Vernier delay line on the systems perfor mance. The mathematical observations are then verified with modeling and simulating the architect ure including clock skew and jitter effects in MATLAB. As sinusoidal signals play an important role in signal analysis, the following analysis is discussed for a sinusoidal input signal Vin( t ) A osin(2 f ot ).

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55 Consider the arrangement of parallel samplers as shown in the Figure 3-8. The total number of samplers considered is K and a buffer from its previous sampler delays the sampling clock to a sampler by a delay t. Without the loss of generality, we assume the timing reference as zero at the input of the 1st buffer (buffer 0). Case i: If the delays of a ll the buffers are perfectly matched and equal to t as shown, then the first sample point from the first sampler (O0) is at time t with resp ect to reference time, the first sample point from the second sampler (O1) is at time t with respect to reference time and so on. Finally, when all the samples are interlaced the output signal is as shown in the Figure 39. Figure 3-8. Parallel sa mplers with buffers

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56 Figure 3-9. Output signal fr om uniformly sampled signal This corresponds to uniform sampling of th e input signal at a sa mpling rate equal to 1 t or sampling period equal to t. The spectrum of su ch an output signal is given by the well-known spectrum representation [PL76], Xout() 1 t X k 2Kt k where X () 2(0) (3-4) It is seen that Xout ( ) is periodic in with period 2 Spectral lines in the output spectrum are at = 0. There are no other noise spectral lines as the signal is uniformly sampled with zero skew between samplers. Case ii: If the delays of the buffers are not matche d, the output signal is a result of what is called the non-uniform sampling. In the presence of constant skew for each buffer but different from other buffers, we can assume the following for the sampling instants of the samplers. Unlike case i, where the final interlaced samples are at times t, 2t, 3t with respect to the reference time, we can assume the samp les in this case to be at times t0, t1, t2, with respect to

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57 the reference time. Finally, when all the samplers are interlaced, the output signal is as shown in the Figure 3-10. The digital spectr um of such a non-uniformly sa mpled signal has been derived in [Jen88], and is given by Xout() 1 t 1 K e j k 2Kt rmte jkm 2K m 0 K 1 X k 2Kt k where rm mt tmt (3-5) For the case of sinusoidal input, X ( )=2 ( 0) the above equation can be written as Xout() 1 t A ( k )20 k 2Kt k where A ( k ) 1 K e j0rmt e jkm 2K m 0 K 1 (3-6) Figure 3-10. Output signal of a non-uniformly sampled signal Here, A (k) is periodic on k with period K, hence the spectrum Xout( ) is periodic on with period equal to s (sampling frequency). Clearly, one period of the spectrum has noise

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58 spectral lines at frequencies equal to f0 k K fs, k 1,2,3... (Figure 3-11). These noise spectral lines are due to the clock skews in the buffers between the samplers and degrade the signal to noise ratio (SNR) as input frequency increases. Figure 3-11. Spectrum of a non-uniformly sampled signal Case iii: This case describes about the analysis of the improved architecture using VDL to generate fine resolution between samples. If the delay line has m control bits, it can generate p=2m cases of delays between CLK1 (event trigge ring clock) and CLK2 (sampling clock). When all the samples from this architecture are interl aced, the output signal is as shown in the Figure 312. Figure 3-12(A) shows the samples from the arch itecture in an ideal case where all the delays of the buffers between samplers are matched (t) and Figure 3-12(B) shows the case when the delays are irregular between the samplers due to clock skew. Assume that the VDL generates exact integral multiples of minimum delay between the two clock edges for different conditions on the select signals for the multiplexer. A de lay locked loop based Vernier delay line is discussed in the next chapter that achieves this assumption. Then, all the samples in the output signal that are obtained from the 1st sampler have to be interlaced with the same offset from their ideal sampling instants and the samples from 2nd sampler have to be interlaced with the same offset from their ideal sampling instants and so on Thus, let n sets of samples are obtained with

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59 each set having p=2m samples that are off from their ideal sampling instants by the same amount. Here, m is the number of cont rol bits to the delay line. Figure 3-12. Same t between samplers ideal case and irregular t between samplers Considering this effect of the Vernier dela y line in Equation 3-5, we can derive the following for a sinusoidal input whose spectrum is given by X ( )=2 ( 0). For complete derivation of (3-7), refer to appendix a. Xout() 1 td 1 K e j0t0tde jk 2np m m 0 p 1 e j0t1tde jk 2np m m p 2 p 1 ... e j0tn 1tde jk 2np m m ( n 1) p np 1 20 k 2Ktd k (3-7) where ti, i = 0,1,2,..,(n-1) are the offsets for each one of the n sets of samples.

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60 Again, the spectrum Xout( ) in Equation 3-7 is periodic on with period equal to s (sampling frequency). Clearly, one period of the spectrum has noise spectr al lines at frequencies equal to f0 k K fs, k 1,2,3.... These noise spectral lines are due to the clock skews in the buffers between the samplers and degrad e the signal to noise ratio (SNR) as input frequency increases. Additionally, the summation terms e j0titde jk 2np m m ip ( i 1) p 1 in Equation 3-7 become zero when k is an integral multiple of n. This implies that in this architecture, noise spectral lines due to clock skew effects at these values of k become zero (Figure 3-13). Therefore, the snapshot architecture with Vernier delay line has (p-1) le ss noise spectral lines and increased SNR in the reconstructed signal when compared to case ii. Figure 3-13. Reduction of noise spectral lines with an id eal VDL in the architecture 3.4 Modeling and Simulating in MATLAB Modeling and simulating the ar chitectures in MATLAB has been done to verify the observations and mathematical derivations describe d earlier. The effects of clock jitter and clock skew are included in the timing instants generator in the model. In this model 8 parallel samplers are considered. Input signal frequency is 25Hz and sampling frequency is 100Hz. The noise floor

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61 is due to random Gaussian jitter. Reduction in th e number of noise spectral lines can be seen by the architecture using ideal Vernier delay line. Case i: Simulation of architecture without VDL. Observation: Total number of spectral lines [0,fs/2] = 8; 1 signal and 7 noise Case ii: Simulation of modified version; n = 4, p = 2. Observation: number of spectral lines [0,fs/2] = 7; 1 signal and 6 noise; (p-1) = 1 less from Case i. Case iii: Simulation of modified version; n = 2, p = 4. Observation: number of spectral lines [0,fs/2] = 5; 1 signal and 4 noise; (p-1) = 3 less from Case i. Figure 3-14. Spectrum of output signal Figure 3-15. Spectrum of output signal (n=4, p=2)

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62 Figure 3-16. Spectrum of output signal (n=2, p=4) 3.5 Measurement Results This section describes about the measurement results from the prototype of the snapshot architecture designed in AMI 0.5um process with a 5V power supply. Full system occupies an area of 0.329 mm2 excluding bond pads and ESD devices. Figure 3-17 shows the boards and the measurement apparatus. Figure 3-17. Measurement board and setup The goal of this architecture is to be able to reproduce the shape of an on-chip signal waveform off-chip. Figure 4-18 shows the meas urement strategy. In the layout, a 8mm long interconnect in this 3-metal layer process is considered as the devi ce-under-test (DUT). The

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63 clock signal degradation after tr ansmission through this long in terconnect is reproduced by the snapshot architecture. The loading of the measurem ent circuit at the end of the interconnect was not a problem as the input capacitance of the circ uit was a lot lower than the capacitance of the 8mm long interconnect. The samples obtained from the parallel architecture are interlaced based on the timing information obtained by characteri zing each sub-block used in the architecture. These characterization results are shown in the ne xt chapter when the design of each sub block is considered individually. After inte rlacing the samples, the shape of the signal reproduced from the measurement circuit is then compared with the shape displayed on a real-time oscilloscope using a high-impedance probing method. Figure 3-18. Strategy of waveform co mparison (DUT 8mm long interconenct) Figure 3-19 (A) shows the clock signal at the end of the DUT captured on a real-time oscilloscope with a high-impedance probe. The part of the signal of interest here is enlarged in Figure 3-19 (B). The length of the signal of in terest here is approximately 15ns, which was compared to the signal obtained from the measurement circuit.

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64 Figure 3-19. Clock signal at the end of DUT. A) From a real time oscilloscope. B) Part of signal zoomed for comparison. Figure 3-20 shows this signal reproduced by the samples from the architecture. The total number of samples is 40 for a length of approxima tely 15ns of the signal. These sample values are an average of a large number of measurem ents. Finally, Figure 321 compares the signals obtained from the measurement circuit and the oscilloscope on a same graph. Figure 3-20. Signal reproduced by the snapshot architecture

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65 Figure 3-21. Waveform comparison between measurement circuit and oscilloscope It can be seen from the Figure 3-21 that the shape of the on-chip si gnal has been closely reproduced from the samples obtained by the paralle l samplers in the architecture. The difference between the shapes obtained from the real-time oscilloscope and th e snapshot architecture is due to the inability of the samplers to sample signal levels that are beyond the provided supply voltage. This can be verified by slowing the rise-time of the clock signal so that the overshoots due to on-chip inductive effects ar e suppressed. However, the problem is that the on-chip buffers providing the clock signal to the DUT (8mm interconnect) reshap e the clock signal and rebuild the rise-time. Therefore, instead of slowing down the rise-time of the input clock si gnal, external sinusoidal signal is given as input to sample for the spare archit ecture. This bypasses the DUT in the system and the goal here is to see the perf ormance of the architectur e in reproducing signals that extend beyond the supply. Figur e 3-22 (A) shows the sinusoidal signal of frequency 15MHz. Snapshot window of approximately 15ns is plotted from the 10 para llel samplers. It is observed that for a signal extending beyond supply voltage, the samplers maxed out in their held voltages

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66 and cannot track the input signal. In this case, th e supply voltage is 5V. The parallel line in the figure shows the maximum voltage from the sample rs. On the other hand, for signals that are below Vdd, the reproduced signal is a close matc h to the input signal (F igure 3-22 (B)). This inability of the samplers to sample reliably the voltages that extend beyond supply voltage is addressed in the next chapter and an improved switch based on bootstrapping techniques is proposed. The results from the switch are discussed there. A B Figure 3-22. System performance. A) For signa ls beyond Vdd (=5V). B) For signals below Vdd

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67 Table 3-1 compares various on-chip measuremen t circuits to capture on-chip signal details in the available literature with this architecture. Table 3-1. Comparison of On -chip measurement circuits This Work Reference [HAMWMH98][TMN02] Prototype Simulations Process 0.25um 0.13um 0.5um 65nm Sampling Technique Sub-sampling Sub-sampling Real time or Subsampling Real time or Subsampling Design Complexity Simple Complex Simple Moderate Sampling Rate 35GHz 100GHz 4GHz 70GHz Target Measurement High-Speed signals Substrate noise HighSpeed signals High-Speed Signals Input Range Full Swing Beyond Supply Full Swing Beyond Supply In summary, the architectures discussed in this chapter can be used as on-chip measurement circuits. They have been verifi ed behaviorally in MATLAB and the system performance is demonstrated for a device-under -test (8mm long interconnect). The degradation of a signal transmitted along the DUT is reproduced by the architecture and compared with the measurement from a real time oscilloscope. The next chapter presents the circuit designs and measurement results of individua l blocks in the architecture. The characterization of timing information of these sub-blocks is essential fo r reconstructing the signa l from the input signal samples obtained by the snapshot architecture.

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68 CHAPTER 4 DELAY GENERATORS AND HIGH-SPEED SAMPLERS 4.1 Introduction This chapter details the circuit design issues of the sub-blocks used in the architectures proposed in Chapter 3 for capturing snapshots of events on the die. The discussion here mainly deals with the design of on-chip samplers, delay generators between parallel samplers, the design of a Vernier delay line for prec ise skew generation between the event triggering clock for the device-under-test and the sampling clock used in the architectures The prototype demonstrated in the previous chapter used the AMI 0.5um pr ocess technology with a power supply voltage of 5V. As previously discussed, ji tter and clock skew in the samp ling clock signal gives rise to a proportional amount of noise in the output spec trum. Gaussian random jitter increases the noise floor and constant clock skews in ject noise spectral powers in the output spectrum along with the signal power thus reducing the overa ll signal to noise ratio of th e snapshot architecture. These jitter and clock skew tolerances of the architecture become very stringent and important in deep sub-micron processes. Therefore, the design of these circuits in state-of-the-art processes involves the implementation of mo re robust design techniques. While measurements are made on the delay elements in AMI 0.5um process designed for the prototype, circuit design and simulation results of a delay-lo cked loop based Vernier delay line and delay chain are presented for a TI 65nm process with a 1.2V power supply. Also, master-slave type samplers are built and measured in AMI 0.5u m process. These circuits are used as sampling switches in oscilloscope arch itectures. However, unless an elaborate calibration method is used, conventional transistor sampling sw itches cannot be used in testing circuits in todays low Vdd designs because such switches do not offer constant conductance in the entire signal range. Also, in low Vdd processes, such switches do not conduct fo r certain voltages in

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69 the signal range. These problems with the conve ntional sampling switches can be eliminated by using bootstrapping techniques. An improved bootstrap switch that can reliably sample signals beyond the supply voltage is designed in IBM7WL 0.18um process with a 1.8V power supply and TI 65nm process with a 1.2V power supply. This chapter also reviews the sub-sampling technique commonly used in on-di e oscilloscopes and used to va lidate the perfor mance of switch circuits. 4.2 Delay Generators and Vernier Delay Line A simple delay element is a buffer consisti ng of two CMOS inverters as shown in the Figure 4-1. However, this delay element does not provide any cont rollability on the delay of the circuit after fabrication. Figure 4-1. Simple delay cell The current starved inverter style delay el ement shown in Figure 4-2 on the other hand provides the user with the capability to adjust th e delay of the circuit [LCMK94]. This is most essential in achieving desired timing between two nodes in a circuit.

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70 Figure 4-2. Current starved delay cell Control of the delay is provided through cu rrent starving by tran sistors N3 and N5. Transistors N4 and N6 act as w eak shunt devices that limit the delay when the control voltage for N3 and N5 is below the threshold voltage. Proper sizing of transistors is essential to make sure the rise times and fall times of the transitions at the output are approximately equal. Figure 4-3 shows the delay versus contro l voltage in AMI 0.5um process with a 5V power supply. Figure 4-3. Delay versus control vol tage (AMI 0.5um process Vdd = 5V)

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71 In the architecture discussed in Chapter 3 fo r taking snapshots of events on a die following a triggering event, two clocks need to be gene rated: an event trigge ring clock and a sampling clock that propagates across the pa rallel samplers. The time delay between the transition edges of these two samplers can be generated by a Vernier delay line [DSH00]. This time delay is related to the resolution of the information captured by th e architecture. As shown in the Figure 4-4, a decoder/multiplexer can be used to adjust this time delay in multiples of the minimum delay equal to (tp1-tp2). Figure 4-4. Vernier delay line. A) System. B) Current starved i nverters in the top delay chain (buffer delay = tp1). C) NOR gate based inverters in the bottom delay chain (tp2)

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72 Table 4-1. Separation between CLK1 and CLK2 edges for select signals A0 A1 Separation between clk1 and clk2 edges 0 0 (tp1-tp2) 0 Vdd 2(tp1-tp2) Vdd 0 3(tp1-tp2) Vdd Vdd 4(tp1-tp2) 4.2.1 Measurement Results Vernier delay line discussed in the previous section has been designed in AMI 0.5um process with a 5V supply for the snapshot architecture discussed in the previous chapter. The timing delay information of each block used in th e architecture is very important for accurate interlacing of the samples obtained from the pa rallel samplers. Different sub-blocks of the architecture are designed and laid out as standalone circuits for evaluating the performance in the overall system design. The layout in Figure 4-5 is repeated from previous chapter here. It highlights the stand-alone circui ts used for the characterizatio n of the system. The following measurements are performed for an input fullswing (0-Vdd) clock signa l of frequency 10MHz. Figure 4-5. Layout of s ub-blocks in the system

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73 Table 4-2 shows the measured separation between th e two clock edges for different control signals in the multiplexer. Figure 4-6 shows the measurements from a real-time oscilloscope. Table 4-2. Measurements of Vernier delay line (average time separation = 397ps) A0 A1 Measured separation between clk1 and clk2 edges 0 0 375ps 0 Vdd 770ps Vdd 0 1193ps Vdd Vdd 1591ps Figure 4-6. Average time separation increments of 397ps between clock1 and clock2

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74 Skew-less clock signals are important for the master-slave type sampling switches in the samplers. This is important so that the charge is not inadvertently lost. The trick to obtain skewless design is described here. Figure 4-7 shows the circuit co nsisting of CMOS inverters. Figure 4-7. Skew-less clock generator To provide skew-less clock generation, it is im portant that devices are sized such that the sum of pull-up delays in path 1 is equal to the sum of pull-up dela ys in path 2. Similarly, pulldown delays in path 1 must be equal to pull-down delays in path 2. Such a design is made in AMI 0.5um process for use in th e architecture. Table 4-3 shows the measured crossover points for clock and inverted clock for an input full swing clock signals of frequencies 1MHz and 10MHz. Table 4-3. Measured cr ossover voltage values Input clock frequency Measured cross-over voltage Ideal cross-over voltage 1MHz 2.43V 2.5V 10MHz 2.33V 2.5V 4.2.2 Delay Locked Loop Based Vernier Delay Line in 65nm As discussed in Chapter 3, jitter and clock skew causes non-uniform sampling of the input signal. This results in a propor tional amount of noise in the output spectrum. Gaussian random jitter increases the noise floor and constant clock skews inject noise spectral powers in the output

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75 spectrum along with the signal power, thus reduc ing the overall signal to noise ratio of the snapshot architecture. These jitter and clock skew tolerances of the architecture become very Figure 4-8. Measurements of a skew-less cl ock generator on a real-time oscilloscope stringent and important in deep sub-micron processe s. Therefore, the design of these circuits in the state-of-the-art process involves the impl ementation of more robust design techniques. Besides the timing errors in the parallel samplers, the timing errors from the Vernier delay line propagate into the parallel sampling system. We have already seen from the mathematical derivation that the number of noise spectral lines in the output signal spect rum can be reduced if the delay line generates precise integral multiples of minimum delay (tp1-tp2) between the event triggering clock (CLK1) and the sampling clock (CLK2) for different conditions on the select signals to the multiplexer. Therefore, it is necessary to be able to generate the clock signals that are stable against temperat ure and process variations. Multiple phases of clocks with low jitter can be generated by using a delay locked loop (DLL). DLL design takes a considerably long de sign time. For this work, the most commonly used and previously reported [MH93, Man96] DL L circuit is designed in a 65nm process. This

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76 section shows the simulation results of a delay locked loop based Vernie r delay line. The basic blocks of a DLL are shown in Figure 4-9. Figure 4-9. Delay locked loop The phase of the reference clock is compared to the phase of the output clock from the voltage-controlled delay line. Any phase error between the two clock signals is detected in the phase-frequency detector (PFD) and generates an appropriate vo ltage on the loop filter via a charge pump circuit. This voltage on the loop filte r adjusts the delay in ea ch stage of the voltage controlled delay line until the pha se error between the reference clock and output clock is zero. The negative feedback in the loop reduces the phase erro r gradually to zero. When the phase of the output clock from delay line is aligned with the phase of th e reference clock, the DLL has achieved its locked state. At this point, the di fferent outputs of the volta ge controlled delay lines have stable clock signals with equal phase shifts between th em. For a reference clock period equal to T, the delay in each st age of the VCDL in an N-stage delay line is given by T/N in the locked state. In order to generate two clock signals, two de lay locked loops can be used as shown in Figure 4-10. The number of stages in each delay lo cked loop is different. Assume that DLL 1 has

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77 N stages in its voltage controlled delay line a nd DLL 2 has M stages in its voltage controlled delay line. When the DLLs are in locked state, the delay from each stage in DLL 1 is equal to T/N and delay from each stage in DLL 2 is equal to T/M. Figure 4-10. Delay locked loop based Vernier delay line Therefore, the time delay between the eventtriggering clock and sampling clock is given by (T/N-T/M). Simulations have been perfor med on such a Vernier delay line with DLL 1 having 14 stages and DLL 2 having 16 stages. Simu lation results for an in put clock signal of frequency 625MHz show a mini mum separation of 14.3ps as shown in Figure 4-11. Figure 411(A) shows the control voltage of the DLL a nd the CLK1 and CLK2. Figure 4-11(B) zooms the time difference between them. 4.3 High-Speed Samplers The following subsection briefly reviews the sub-sampling technique commonly used in sampling oscilloscopes and testing sampling sw itches. Designs of high-speed samplers to reliably sample signals that extend beyond suppl y are discussed following this subsection.

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78 4.3.1 The Sub-Sampling Technique Exporting on-chip high-speed signals off-chip without degrading the signal quality poses an interesting challenge in todays design envi ronments. Measuring high-speed waveforms is A B Figure 4-11. Simulations of DLL based VDL. A) Vctrl, CLK1, and CL K2 signals. B) Time separation between CLK1 and CLK2

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79 made possible by the use of sub-sampling t echnique [LS93, HAMWMH 98, TMN02, CBS01]. This technique relies on the concept that any pe riodic signal can be reco nstructed from samples of the signal sampled once in every period, but at different time instants with respect to previous periods. Figure 4-12 shows time domain desc ription of the subsampling technique. If the signal to be measured is periodic with period T then let the period of the sampling clock be ( T + t ) where t is a small fraction of T Thus, every sample of the signal sampled by the clock in the next period is delayed so th at each sample has new information about the original signal. If n cycles of sampling clock are required to sample the information contained in one period of the input signal, then the time period of the resulting sampled signal is, n(T + t) where n = T t Therefore, the period of the sampled signal =T t ( T t ). This implies that the frequency of the sampled signal =1 T t ( T t ) t T ( T t ) which is exactly the beat frequency of the input signal and the sampling clock =1 T 1 T t Therefore, f out f input f samplingclock. The sub-sampling technique provides a magnifi cation in the time domain and a reduction in frequency of the output signal. This helps to export information stored in the samples easily off-chip with a low cost test equipment wit hout degrading the signal quality. Low frequency circuits or software can be used for analyzing the information of the signal from the stored samples.

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80 Figure 4-12. Sub-sampling technique in time-domain 4.3.2 Master-Slave Type Sampling Switches Figure 4-13 shows the master-slave type sa mple-and-hold switches commonly used in subsampling oscilloscopes [HAMWMH 98]. Dummy transistors are inse rted to reduce the channel charge injection and clock feed-t hrough. Assuming that exactly ha lf of the channel charge is injected onto the hold capacitor at the output of the sampling switch when it is turned off, the dummy transistor is designed to be half the si ze of the sampling transistor [Raz01]. A separate non-overlapping clock generator is used to ge nerate the clock phases phi1, phi2 and their complementary signals. It is esse ntial to have non-overlapping clocks in order to guarantee charge is not inadvertently lost.

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81 Figure 4-13. Master-Slave t ype Sample-and-Hold circuitt However, the problem with this type of sample-and-hold circuit is that the sampling transistors conductance is not constant over the entire supply range. Figure 4-14(A) shows the variation of the resistance of NMOS and PMOS transistors wi th supply voltage. Figure 4-14(A) also shows the resistance variation of a tran smission gate. Though transm ission gates appear to have constant resistance for a certain si gnal range and can poten tially replace the MOS transistors in the switch circ uits, they have a non-conducting region in low-Vdd technologies. The threshold voltages of the devices have not scal ed down at the same rate as the supply voltage because low threshold voltage devices are susceptib le to more leakage problems. In technologies where Vdd is less than the sum of the threshold voltages, a transmission gate has a region of nonconductance as shown in Figure 4-14(B). For accurate measurements, switc hes with constant impedance over the entire signal range and that can be operated in low-Vdd technologies are needed The second-generation sampling switches designed here use TI 65nm technology with a 1.2V pow er supply. For the reasons described above, alternate design techniques had to be used for reliable signal measurements.

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82 4.3.3 Low-Voltage Bootstrapped Switches Problems with the conventional sample-andhold switches discussed previously can be eliminated with the use of boot strapped switches [Ste99, AG99, DK01]. Figure 4-15 describes Figure 4-14. Resistance variati on of NMOS, PMOS, and a TG. A) Vdd > |Vtn| + |Vtp|. B) Vdd < |Vtn| + |Vtp|. the bootstrapping concept that helps in keeping th e gate-to-source voltage of the sampling switch constant when the switch is conducting. Th e on-resistance of the switch is given by, Ron 1 Cox W L Vgs Vth (4-1) If the variation in threshold voltage due to bulk effect is neglected then Ron of a bootstrapped switch is nearly cons tant. The operation of a bootstra pped switch is described here. During the off state (phibar), the sampling swit ch is cut off by connecting its gate to ground while the capacitor (Cb) is pre-charged to approximately Vdd in this off state. During the on state (phi), the signal to be measured is applied to the sampling switch and the gate voltage is boosted

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83 by the capacitor (Cb) to approximately (Vdd + Vin). This implies, Vgs = Vg-Vs = (Vdd + Vin) Vin = Vdd Figure 4-15. Conceptual diag ram for bootstrapping technique Certain node voltages in the bootstrapped switc h exceed the supply voltage. Care should be taken while designing such switches so that the device reliability ru les are not violated [AG99]. The limitations on the terminal voltages set by the device breakdown mechanisms in an MOS transistor are brie fly described here. Oxide breakdown sets a limit on the Vgs and Vgd that can be applied to a transistor for reliable operation. Hot electron effects limit the Vgs and Vds that can be applied. Gate-induced drain leakage currents also limit the voltage that can be applied across the gate oxide. Finally, punch-through determines the Vds that can be applied when the device is off. A more detailed discussion of the breakdown mechanisms can be found in [AG99, MH90, Hu94]. For reliable operation, the terminal voltages in a MOS transist or with respect to each other should not exceed the Vdd provided by the technology [(Vgs, Vgd, Vds) < Vdd]. The absolute terminal voltages, however, can be larger than Vdd.

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84 Constraints for different voltages in an MOS transistor [AG99]: Oxide breakdown: Vox E bd t ox Gate-Induced drain leakage: V gd E gidl t ox 1.2 V V FB Hot electron effects: V ds V dsat( L ) E c ( l 2 l LDD) l2 0.2 tox 1 3 Xj 1 2 Punch-through mechanism: Vds Vp NsubL3Xj 3 tox where, tox is thickness of gate oxide, Ebd is typically 5mV/cm, Egidl is the electric field in the oxide that induces GIDL currents, VFB is transistors flat-band voltage, Xj is the drain/source junction depth, lLDD is the effective length of the lightly doped drain. 4.3.3 Improved Bootstrapped Switch Figure 4-16 shows the conventi onal bootstrap switch. Transist or N1 performs the actual sampling and the rest of the circuit is used to boost the gate voltage of N1 to keep its gate to source voltage constant and to keep the relative terminal voltages of th e transistors small enough for reliable operation. However, the circuit descri bed in Figure 4-16 cannot be used for sampling input voltages larger than the supply voltage. Duri ng the on state (phi) input voltage is applied to the drain of the PMOS transistor P2. If this inpu t voltage is larger than the bulk potential of P2 (equal to Vdd in this design) it can forward bi as the p-n diode at the junction between the source/drain and the well of the transistor P2 [AASM05]. Such a forward bias could damage the circuit permanently. This problem can be avoided by exploitin g the ability to connect the well potential of a PMOS to any appr opriate voltage in an n-well pro cess. A voltage larger than Vdd has to be generated on the chip to which the bulk of this PMOS (P2) can be connected. A charge pump circuit shown in Figure 4-17 ca n be used to achieve this requirement. The operation of this circuit can be explained as follows. When phibar changes from low to high

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85 Figure 4-16. Conven tional bootstrap switch (0Vdd), node A changes from 0Vdd. This turns on the transistor whose gate is connected to node A pulling node B to approximately (Vdd-Vt ). When phibar changes from high to low (Vdd0) and phi from low to high (0Vdd), node B is boosted from (Vdd-Vt) to (2Vdd-Vt). This in turn pulls node A to Vdd. In the next iteration, node A boosted to 2Vdd and node B is pulled to Vdd. From here on, nodes A and B switch between Vdd and 2Vdd. The improved Bootstrapped circuit is shown in Figure 4-18. A separate charge pump is used to generate a voltage 2Vdd when the main sw itch is on. In this circuit, the bulk of PMOS transistor P2 switches between 2Vdd and V dd when the sampling switch is on and off respectively. This avoids the forward biasing of the p-n diode for input voltages larger than supply and the switch can be used reliably for sampling signals beyond Vdd. The inset in this figure shows how this switch will be represented in the rest of this chapter. A separate nonoverlapping clock generator genera tes the clock signals phi and phi bar in the circuit. In this

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86 circuit the source/drain to well potential of P2 can reach a voltage as high as 2Vdd depending on the input signal of the switch. However, the re verse breakdown voltage of this p/n junction in modern technologies is much larger than the supply voltage [FSR06]. Figure 4-17. Charge-pump circuit Figure 4-18. Improved bootstrap switch

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87 Figure 4-19 shows the tr ansient plot of Vgs of the main transistor (N1) in the improved switch. From the figure, it can be seen that when the switch is on (phi) Vgs is nearly constant irrespective of input sign al. Figure 4-20 shows the transient plot of the bulk voltage of the PMOS transistor (P2). The bulk voltage of this PMOS switches between Vdd and 2Vdd depending on whether the switch is off and on, respectively. Simulation results showing the complete switch behavior are shown in Fi gure 4-21. The plot shows the clock si gnal (phi), boosted gate voltage of N1, input sinusoidal signal and th e output signal. The switch transist or N1 together with the load capacitance will form an RC circuit. The sample rs front end RC bandwidth of N1 and load capacitance is ~ 6 Ghz. Figure 4-19. Clock (phi) and Vgs of the main switch transistor (N1)

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88 Figure 4-20. Clock (phi) and the bulk vo ltage of the PMOS transistor (P2) Figure 4-21. Simulated proposed bootstrap swit ch behavior (Clock ( phi), gate voltage (Vg) of N1, input and output signals)

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89 4.3.4 Measurement Results In this work, different switch circuits have been designe d using IBM7WL 180nm technology with 1.8V power supply. Figure 4-22 shows the boards with the circuits. The chips on the boards also contain high-speed I/O driver s designed to create test signals for the characterization of the packag e. Switching of these drivers generates ground bounce and power supply fluctuations. Samplers are deployed at various places on the ch ip to measure these critical signals. These samplers not only help measuring signals but also help in debugging a packaged chip for functionality where the internal node s are inaccessible for probing. Figure 4-23 shows the chip microphotograph. Figure 4-22. Board with the c onventional sample-and-hold circuit Figure 4-23. Chip microphotograph

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90 Figure 4-24 shows the layout of the entire ch ip. A stand-alone sampler is used for calibration purposes. Measurement results from this stand-alone sampler are explained here. Measurements have been recorded for an inpu t sinusoidal signal of frequency 155MHz and a sampling clock frequency of 150MHz. Therefore, the output signal from the sampling switches should be a 5MHz signal corres ponding to the beat frequency of the input signal and the sampling clock (Figure 4-25). Figure 4-24. Layout of the chip (IBM7WL 0.18um process) Figure 4-25. Output sub-samp led signal (frequency = 5MHz)

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91 The frequency spectrum of the output signa l captured on a spectrum analyzer for a different measurement condition is shown in th e Figure 4-26. For an input 110 MHz sinusoidal signal and 100 MHz sampling clock, the hi ghest frequency component is at 10MHz corresponding to the output si gnal. The second highest peak is approximately 24.76dB lower than the peak at 10MHz. This number is the figur e of merit for the nonlinearity of the circuit. Figure 4-26. Frequency sp ectrum of the output signal Another set of measurements ha s been recorded for an input clock signal of frequency 208MHz and a sampling clock of frequency 200M Hz. The waveforms are captured using an external oscilloscope. Figure 427(a) shows the signals from the sampler in time domain. The frequency of the output signal from the external oscilloscope is observed to be 7.67MHz, which is approximately the beat fre quency between the input and the sampling clock. Figure 4-27(b) shows the switching of the I/O drivers. In summary, this chapter presented the circu it designs of the sub-blocks in the snapshot architecture. The prototype circuits are fabricated in a 0.5um pro cess with a 5V power supply. In

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92 order for this system to be fabricated in a st ate of the art CMOS pro cess, more robust design techniques have to be employed for better perfor mance. Such circuit desi gn suggestions are also made in this chapter. The next chapter presents another important on-chip test circuit, a signal strength measurement circuit that can be used as a signal feature extrac tor in embedded test. A B Figure 4-27. Measurement results. A) From co nventional sampling switche s. B) Switching at the I/O drivers.

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93 CHAPTER 5 LOG AMPLIFIER: LIMITING AMPLIFIER BASED SIGNAL-STRENGTH INDICATOR Logarithmic amplifiers can be used in dete rmining on-chip signal amplitudes because of their capability of handling a la rger dynamic range while cons uming less power with simple circuitry. As discussed in Chapte r 2 a built-in-test problem can be broken down into two aspects. First, the DUT must be stimulated with the help of high-speed test stimulus generators developed on-chip and second, the DUT response should be an alyzed with the help of high-speed on-chip acquisition circuits. Sign al strength detectors discussed in this chapter can be used as an analyzing circuit. This chapter talks about the design of limiting amplifier based signal-strength indicators and their usefulness in embedded test of circuits. 5.1 Introduction Detectors play an important role in the embedde d test of circuits. A ccurate measurement of signal strengths at various places on a wireless ch ip is almost indispensable. In addition, in mobile communication systems, know ledge of the strength of the received signal by the receiver is essential to monitor and control the signal levels transmitted by the base station. Constant monitoring of the transmitted and received signal strengths can help in dynamic adjustments of the power transmitted by the base station that reduces the power consumption. A logarithmic amplifier is a limiting amplifier based signal-strengt h indicator and is widely used in cellular phones that require an on-chip circuit to measur e the received signal stre ngth. A typical front-end circuitry in a wireless receiver and a typical application of loga rithmic amplifiers is shown in Figure 5-1 [HCW00]. Organization of this chapter is as follows. First, a brief overview of logarithmic amplifier techniques is discussed followed by a complete mathematical analysis of logarithmic amplifiers, which describes the operation of the circuit quantitatively. Er ror involved in realizing a

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94 Figure 5-1. Typical frontend of a wireless receiver logarithmic amplifying function in circuits is desc ribed in the error analysis of log amplifiers. Next, circuit design of limiting amplifiers, rect ifiers and dc offset cancellation circuits is discussed. Finally, the layout of the chip, re sults from the simulation and measurements are presented to verify the functionali ty of the overall circuit. This chapter is concluded with a case study of an application of logar ithmic amplifier based signal streng th detectors in substrate noise measurement. 5.2 Logarithmic Amplifiers Logarithmic amplifier is an indispensable tool in many measurement circuits where a precise knowledge of the signal amplitude is necessary. This magnitude control of the signals can be achieved by using an automatic gain co ntrol (AGC) circuit but an AGC system has a limited useful instantaneous input dynamic ra nge before saturation occurs. A logarithmic amplifier helps in compressing and mapping a wide dynamic range at the i nput to a small range at the output. Logarithmic amplifiers are able to replace AGC circuits, as an input dynamic range in excess of 80dB is not unc ommon with log amps [Hug86].

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95 Exact logarithmic response can be obtained by us ing the logarithmic I-V characteristics of an inverting operational amplifie r with a diode or a transconduc tance feedback (Figure 5-2). Figure 5-2. Transconductance f eedback logarithmic amplifiers. A) Diode. B) Transistor I Ise VoutVT 1 ; (Or) Vout kT q ln VinRs *Is (5-1) However, these structures have strong temp erature dependence as shown in Equation 5-1 and need elaborate compensation techniques. Also since these techniques rely on the logarithmic characteristic of a physical elect ronic device in their feedback l oops, they become less practical at higher frequencies where the device res ponse is degraded [Gre92]. A more powerful logarithmic technique is the approximation of a logarithmic function by the summation of straight-line segments. This method relies on the circuit arch itecture known as the successive detection architecture (Figure 5-3) to produce a ps eudo-logarithmic transfer function rather than a particular devices V-I charac teristics. The transfer function is called pseudo-logarithmic for the reason that it is an approximation to an ideal logarithmic curve. The degree of this approximation to the ideal logari thmic curve depends on certain design parameters, which will be discussed later in the chapter.

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96 Successive detection architect ure also known as piece-wise linear model is shown in Figure 5-3 and consists of a cascade of limiting amplif iers with full-wave rectifiers at the outputs of each amplifier to implement the logarithmic amplification [H ug86]. Full-wave rectifiers are shown as detectors (Det) in the figure. The outpu ts of the detectors ar e summed and passed to a low pass filter. A low-pass RC circuit is used to remove the ripple of the full-wave rectified signal. This architecture produ ces two outputs: first, the clipped output from the limiting chain and the rectified DC output from the low pass filter that gives the information about the logarithm of the signals envelope amplitude. Th e dynamic range of a log amplifier is limited on the upper end when the firs t stage in the amplifier chain starts to clip and limited on the lower end when all the gain cells are amplifying the inpu t signal linearly. However, in practice, if the noise floor of the equipment at the input of the log amplifier or the amplifiers noise causes the last stage to clip, it will determine the lower end of the dynamic range. A complete mathematical analysis of how this architecture operates as a logarithmic amplifier is explained in the next section. Figure 5-3. Successive de tection architecture of logarithmic amplifiers

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97 5.3 Mathematics of Logarithmic Amplifiers Two key parameters that need to be decide d before designing a log amplifier are the number of stages (N) in the successive dete ction architecture and the log-error of the architecture. The piece-wise linear approximation to a log curve is shown in Figure 5-4. Logerror analysis gives a measure to the degr ee the piece-wise linear approximation of the architecture conforms to the ideal log curve. Factors and analysis involved in deciding the number of stages and a complete mathematical de rivation of log amplifiers is described in this section. Figure 5-4. Piece-wise linear approximation to a log curve 5.3.1 Operation Analysis Including E rror Analysis of Log Amplifiers Consider a limiting amplifier with N identical gain cells (Figur e 5-3). Let each gain cell be characterized by a gain A and a 3-dB frequency f And, let the output of the mth stage be just limiting and subsequent stages outputs clipped. Let VL be the limiting voltage of the gain cells. The output of the mth stage = VL (limiting voltage). Theref ore, the input of the mth stage is equal to V L A Am 1Vin where Vin is the input voltage to the first stage. Thus,

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98 m log A log VLVin m log VLVin log A (5-2) When the circuit sums the outputs of the gain cells, the output of the summer is, Vin AVin A2Vin A3Vin ...... Am 1Vin N m 1 VL 1 A A2 A3 ...... Am 1Vin N m 1VLif A 1 AmA 1 Vin N m 1VL VLA 1 N 1 log VLVin log A VL N 1 1 A 1 log VinVL log A VL VLlog A log Vin N 1 1 A 1 log VLlog A VL (5-3) Equation 5-3 represents the equation of a st raight line, y = mx + c, with a linear relationship between the output and th e log of the input. The slope m = VLlog A and intercept c = N 1 1 A 1 log VLlog A Once the limiting voltage ( VL) and the small-signal voltage gain ( A ) are known, the signal strength of any input si gnal can be predicted using Equation 5-3.

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99 The number of stages ( N ) mainly determines the precisi on of the signal strength of the input signal detected by the su ccessive detection architecture. The maximum error of Equation 53 compared with an ideal logarith mic curve is derived as [HCW00], Errormax(dB) = 10 1 A Alog A A 1log A3 A 12 A 2 A 1 (5-4) Figure 5-5. Maximum error (dB) versus number of gain cells (N) This maximum error in dB plotted against the number of stages in the limiting amplifier of a total gain of 90dB is shown in Figure 5-5. Clearly, the maximum error in the detection decreases with increasing number of stages. Howe ver, increasing the number of stages increases the chip area. Embedded test ci rcuits should be area efficien t and consume low power. Power consumption of a log amplifier is discussed here. Si nce, the gain of a singl e cell is assumed to be A and the 3-dB frequency to be f the total gain of the limiting amplifier is Atot = AN, and the total 3-dB frequency is given by

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100 1 ftotf 2 N 2 ftot f 21N 1 (5-5) Normalizing each gain cells parameters with the total gain and 3-dB frequency, we get Normalized gain of single stage = Anorm A Atot Atot1N Atot Atot1N 1 (5-6) Normalized 3-dB frequency of single stage = fnorm f ftot 1 21 N 1 (5-7) Total power consumption ( Pt) can be calculated using singl e stage gain-bandwidth product [HCW00] and is given by P t N *( GBW )2. Implies, Pt N Atot 1/ N. 1 21/ N 1 ftot 2. (5-8) The plots showing the normalized values of gain and bandwidth versus number of gain cells is shown in Figure 5-6. Also shown in th e figure is the total pow er consumption of the limiting amplifier versus number of stages. For a total gain of 90dB, from Figure 5-6, the optimum value for the number of gain cells in the limiting amplifier is 7 or 9. However, when the number of stages is 7, from Figure 5-5, the maximum error in dB slightly exceeds 1dB. Hence, in this design, nine stages have been chosen with a slight penalty of area. The total gain of the limiter is 90dB and the total bandwidth is ap proximately 100Mhz. Simulation results of this circuit are shown in the later sections of this chapter. 5.4 Circuit Design There are three main circuit components in a lo garithmic amplifier. Th ey are the gain stage that is used in the limiting amplifier chain, the fu ll-wave rectifier used as a detector at the outputs

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101 Figure 5-6. Gain, bandwidth and total pow er consumption versus number of stages of each gain stage and the DC offset cancellation circuit. Since the limiting amplifier has a large gain, a DC offset cancellation is required to suppress any offsets due to device mismatches, which may otherwise cause the am plifier to saturate and smear off any small input signal coming from the RF front-end. This section describes the circuit design techniques used in the design of the log amplifier. 5.4.1 Limiting Amplifier Design Each gain stage in the limiting amplifier chain can be a conventional simple differential pair with a diode load. A differential pair has been chosen in this design because of its two important advantages. First, it is primarily sens itive to the difference between two input voltages, allowing a high degree of rejection of signals common to both inputs. Second, cascades of differential pairs can be directly connected to one another without interstage coupling capacitors, which is essential for the limiting amplifier chain. A NMOS differential pair with NMOS diode-

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102 connected loads is shown in Figure 5-7(a). Assu ming a perfectly balanced source-coupled pair, the small-signal differential gain of this topology can be derived using th e half-circuit concept as 11 33(/) (/) gmWL A gmWL (5-9) Clearly, the gain is a function of the aspect ratios (device dime nsions) of the transistors and first-order independent from process parameters However, in deriving Equation 5-9, the body effect of the load devices is neglected. It is important to note that neglecting gmb of the input transistors (M1 and M2) from this analysis has no effect on the small-signal gain because the voltage across the tail current s ource is constant for a pure di fferential input and there is no small-signal change in the voltage from the sour ce to the body of these i nput transistors. Where as, the load devices do suffer body effect and cau ses the small-signal gain of the circuit to depend not only on gm but also gmb of the NMOS loads. Using a PMOS load would eliminate this body effect but then the gain would depend on the ratio of mobility, a process parameter of both NMOS input transistor and PMOS load device. When using a loga rithmic amplifier as a detector of signal strengths in the embedded test of wireless circuits, it is essential that the gain of each gain cell is independent of proce ss variations and variations in th e temperature. This ensures high accuracy in the detection of the signal strength This problem is eliminated in the topology shown in Figure 5-7(b). Though the NMOS loads in this circuit do not suffer body effect, the gain of such circuit depends on the accuracy of the current mirrors. Other drawbacks include more area, extra power consumption and degraded frequency response. A triple-well NMOS transistor used as a load device in a differential pair can eliminate the body effect and the need for a current mirror. The sm all-signal gain of such a differential pair is then a function of device sizes only. Another important advantag e of this topology is by using mainly NMOS devices the temperature dependency cancels out in a first order approximation.

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103 However, the drawback of this topology is the tr iple-well transistors o ccupy slightly more area when compared to regular NMOS loads but the gain is more predictable. Figure 5-8 shows the circuit connections of a discrete NMOS triple-w ell transistor and the gain cell employing these transistors as load devices. For this current design, such transistors are provided by IBM SiGe process that enables the tying of the source termin al to the bulk of the transistor. Also, the input and output common-mode levels are de signed to be the same so that the gain stages that form the limiting amplifier chain can be cascaded directly. Figure 5-7. CMOS limiting amplifiers 5.4.2 Rectifier Design The second main circuit component in the desi gn of logarithmic amplifier is the detector cell. The detector cell provides a current proportional to the rectif ied input voltage of the cell. A full-wave rectifier that r ectifies the balanced signal at each ta p in the cascade can be used as a detector cell. A low-pass filter that ties all the full-wave rectifiers outputs is required to remove the ripple of the AC value of the summed outputs and produce a DC-like indicating voltage proportional to the logarithm of the amplitude of the input signal. A four-quadrant MOS

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104 Figure 5-8. Amplifier circuit. A) A discrete triple-well transistor. B) Gain cell in limiting amplifier. multiplier, shown in Figure 5-9, based on the widely used Gilbert Cell in many analog and communication systems can be used as a rectifier [KRA95]. This ci rcuit obtains the rectification of the signals by multiplying the signal by itself, exploiting the fact that a negative half-wave multiplied by a negative half-wave gives a posi tive half-wave again. Th e Gilbert cell based MOS multiplier has four transistors stacked in it maki ng it inappropriate for the designs in low power applications. An MOS full-wave rectifier th at can be operated with low supply voltages is shown in Figure 5-10. The rectifier is real ized by using two identical unbala nced source-coupled pairs with different aspect ratios [Kim93]. The inputs of the differential pairs ar e cross-coupled and the outputs are connected in parallel The DC transfer characteristics of a single unbalanced differential pair approximate the characteristics of a half-wave re ctifier and when two such pairs are used, it approximates the characteristics of a fullwave rectifier. In the circuit, the transistors M1, M2 and M3, M4 are the input transistors of tw o differential pairs. The widths of the devices M1 and M4 are a factor K times more than the widths of the devices M2 and M3. This unbalance

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105 in the input transistors of the differential pair helps in steeri ng and sharing the current between the larger and smaller transistor s depending on the input voltage. Figure 5-9. CMOS multiplier based on Gilbert cell. Figure 5-10. CMOS full-wave rectifie r with unbalanced source-coupled pairs

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106 Let Vi=V+-V-. The simulated DC transfer characterist ic or the input-output characteristics of the CMOS full-wave rectifier with unbalanced source-coupled pairs is shown in Figure 5-11. The three plots in the figure are the output current from the rectifier ( I = (ID1+ID4) (ID2+ID3)), the sum of currents in the larger transistors M1, M4 (xK currents), and th e sum of currents in the smaller transistors M2, M3 (x1 currents) plotted against the input voltage Vi. When the input voltage is small, most of the current flows th rough the larger transistors M1 and M4. However, as the input voltage increases, the smaller tran sistors M2 and M3 star t carrying significant currents and the currents through the larger transi stors start to decrease Therefore, the total current is shared between the different sized tran sistors and the effective output current from the rectifier depends on the input voltage Vi. Figure 5-11. Various current s in the rectifier (Simulat ed DC transfer curve) Assuming matched devices and a square law current equation for the transistors in active or saturation region, the differen tial output current of the rectifier I = (ID1+ID4) (ID2+ID3) can

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107 be mathematically represented by th e following equations [Kim93] where is the transconductance parameter with effective surface mobility and gate capacitance per unit area Cox. I ID 1 ID 4 ID 2 ID 3 2 K 1 K 1 I0 2 KK 1( K 1)2 Vi 2whenVi 2 I0K K 1KVi 2 2 KVi K 12 I0 KVi 2 K 12 2 KI0K 1 when 2 I0K Vi 2 I0 0 whenVi 2 I0 where ,CoxW L (5-10) If I = 0, then Vi 2 I0 whereas, the output current I imitates logarithmic function when 2 I0K Vi 2 I0 5.4.3 DC Offset Cancellation Techniques Reliable offset control is very important in the design of a limiti ng amplifier. Since a logarithmic amplifier consists of a chain of limiting amplifiers, the gain of a logarithmic amplifier is large. Any device mismatch will cause significant DC offset and may even saturate the output of the amplifier chain smearing any small input signal co ming from RF front-end. This section discusses about diffe rent DC offset cancellation techniques briefly and the one used in the current design in detail A quantitative explanation to how DC offset cancellation is achieved when the last stage in the amplif ier chain is clipped is also discussed. Offset cancellation is realized using resistors and capacitors to obtain a large time-constant to extract the DC component at output. The resi stors and capacitors used in the RC circuit are

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108 large as its frequency is near DC and hence are usually external. One-way of suppressing DC offsets is to insert capacitors a nd resistors as shown in Figure 512(A). In this figure, a high pass filter is realized in the signal path between the stages. To avoid affecting low frequency signal components the high pass filter cutoff frequency is set very low. This results in a long settling time when the circuit is activated for normal ope ration. The coupling capacito rs help in blocking DC bias of one stage to affect th e DC bias of the next stage. Ho wever, the resistors provide input DC voltage of the next stage. The drawback of this technique is the cap acitors have to be onchip. Since the high pass filter cut off frequency is set very low, these capacitors are usually very large and realizing large passive elemen ts on-chip occupies a large area. A B Figure 5-12. DC offset cancellation technique s. A) High-pass real ization. B) Low-pass realization

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109 In the current logarithmic amplifier design, th e approach in Figure 5-12(B) is used to suppress the DC offsets. It uses a DC feedback circ uit, which is a low pass filter. It filters out the DC information at the output and feeds it back to the input. This DC value is then subtracted from input to form a closed-loop system. The la rge DC loop gain from the cascaded chain of limiters of the forward path will reduce the output offset. Such a negative feedback type offset cancellation mechanism is used because it introduces less chip area overhead. Clearly, when all the gain cells in the amplifier chain are linearly amplifying the input signal and not clipping, the negative feedback helps suppressing the offsets. However, an interesting question that needs to be answered he re is how does this ci rcuit suppress DC offsets when the last stages in the chain are limiting or clipping. The offset in an amplifier is usually modeled as an input referred o ffset. A comparison of a limiting amplifier chain with zero DC offset and a chain with non-zero DC offset is shown in the Figure 5-13. As shown, the duty-cycle of the output from the chain with zero input re ferred DC offset is not degraded whereas dutycycle degradation can be seen in the case wher e there is a non-zero inpu t referred DC offset. Fourier series of a periodic function ca n be represented by the following equation. f ( t ) a0 ( ancos n0t bnsin n0t )n 1 where the term a0 represents the dc information in the signal. For a non-50% duty-cycle waveform, a0 A T where is the pulse width, A is the amp litude of the pulse and T is the period of the pulse. In the case of a clipped wave form at the output of the amplifier chain, pulsewidth is a function of offset voltage ( = f (VOS)). Clearly when this si gnal is filtered using a low pass filter, information about the offset in th e amplifier chain is being fed back to the input

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110 in terms of and the negative feedback in the loop stil l helps to suppress the offsets even when the last stage is clipping. Figure 5-13. Duty cycle degradation with non-zero input referred offset. 5.5 Results In this work, the logarithmic amplifier or the limiting amplifier based signal strength detector discussed in the above sections has been designed, simu lated and fabricated in a 0.18um

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111 IBM BiCMOS SiGe process. This section discus ses mainly about the simulation results of the design and the measurement results of the prototype detector. 5.5.1 Simulation Results For the reasons discussed in Section 5.3, a limiting amplifier with nine stages is considered for the design of the logarithmic amplifier. The total gain of the limiting amplifier is set to 90dB with each stages gain equal to 10dB. The input and output common-mode levels are the same so that the stages can be cascaded directly. Triple-well NMOS loads are used in each gain cell. The frequency responses of a single gain cell and the nine stages are shown in Figure 5-14. The 3-dB frequency of a single stage is observed to be 2.47 GHz and that of nine stages is observed to be 390MHz. The simulations in the following disc ussions have been performed at 25 C for an input sinusoidal signal of frequency 100Mhz. Figure 5-15( A) compares the RSSI output voltage of a log amplifier with regular NMOS loads to a log amplifier with triple-well loads. The input dynamic range of the log amplifier with triple-well loads is slightly more than in the case of NMOS loads. The effect of the loads on the i nput dynamic range can also be seen in Figure 515(B) in which the log conformance of the successi ve detection architecture is plotted as output error in dB against input power. 5.5.2 Measurement Results Figure 5-16(A) shows the measurement se tup and Figure 5-16(B) shows the chip photograph. It occupies an area of 0.96 mm2, including the bond pads in IBMs 0.18um BiCMOS SiGe process. The gain cell in the limit ing amplifier is designed as a fully differential circuit. A power splitter (MiniCircuits ZFSCJ-2-4, 50-1000Mhz) has been used to split the input power from the signal source fo r the two inputs of the amplifier. Summed outputs from the fullwave rectifiers are filtered by an external o ff-chip resistor (100kohms ) and capacitor (1uF) to

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112 A B Figure 5-14. Frequency response curves. A) From single stage. B) From nine stages

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113 A B Figure 5-15. Simulation results of the logarithmi c amplifier. A) Output voltage versus input power. B) Error curve. produce a DC-like measurement proportional to the logarithm of the amplitude of the input RF signal. Measurement results are shown in Figur e 5-17, which show the signal strength indicator outputs and the log conformance of the logarith mic amplifier chips. The measurements have characterized an input dynamic range of more than 75dB for a 100MHz sinusoidal signal with a

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114 1.8V power supply. It can be obser ved that it conforms to the log curve with an error of 0.2dB over the input dynamic range of 75dB. A Figure 5-16. Measurements sp ecifics of a logarithmic amplifier. A) Setup. B) Chip microphotograph B Figure 5-16. Continued.

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115 A Figure 5-17. Measurement results. A) Meas ured RSSI output. B) Output error curve. B Figure 5-17. Continued.

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116 5.6 Application in Substr ate Noise Measurement Logarithmic amplifiers can be used in the measurement of substrate noise. As shown in Figure 5-18, a broadband embedded measurement t echnique has been proposed to measure and characterize substrate noise in RF/microwave ICs [He06]. Substrate noise is introduced by injecting well-defined signal from an external signal source into the substrate. An external LO signal is supplied to the on-chip mixer at a freq uency slightly offset from the injected signal frequency. The detected signal is down-converted to baseband and fed to logarithmic amplifier. The logarithmic amplifier works as a signal strength indicator and tells the received signal level. By varying input signal frequency and LO si gnal frequency correspondingly, substrate noise coupling over very wide frequency range can be investigated us ing low-frequency test equipment. Comparing to a linear AGC-based measurement method, the advantage of such technique is that it can detect broadband signals and compre ss a much wider input dynamic range into a small ra nge at the output. Figure 5-18. Down conversion based substrate noise measurement. In summary, this chapter presented an important on-chip test circuit that can be embedded along with the device under test. Th e signal strength detect or circuit described here is fabricated in a 0.18 um process and occupies very small area. This circuit can be used as a part of a data analyzing circuit.

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117 CHAPTER 6 SUMMARY AND FUTURE WORK 6.1 Summary Important contributions of this work to the field of analog/mixed-signal test are summarized in this chapter. The goal of this research was to develop measurement circuits that can be embedded on the chip for both built-in and built-off test strategies. Information extracted from signals in the circuit-under-test by these meas urement circuits can be analyzed to evaluate the circuits performance and reliability. Existing approaches for analog/mixed-signal test such as direct measurement of circuit specification and indirect measurement based on alternate test are described in Chapter 2. Architecture for capturing on-die events is proposed in Chapter 3 and is completely analyzed. By using a Vernier delay line for fine spacing between the sample points, it is observed that noise spectral lines, due to non-uniform sampling, can be reduced. Mathematical derivation of this observation is included in the a ppendix. Measurement results of the architecture are described by measuring a part of the clock signal at the end of a long 8mm interconnect. The parasitics of the interconnect cause overshoots and un dershoots on the signal and th e shape of such a signal is reconstructed off-chip by the samples from the parallel samplers. The prototype system is built in AMI 0.5um process with a power supply of 5V Circuit design suggestions are made for advanced processes such as a 65nm process with a power supply of 1.2V. In these advanced processes, jitter and skew tolera nces are very important for th ey have adverse effects on the signal to noise ratio of the reconstructed signal. An impr oved switch based on bootstrapping technique is designed to sample signals that extend beyond the supply. Finally, on-chip measurement techniques are discussed in Chapter 5. A signal strength detector with an input dynamic range of more than 75dB based on successive detection

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118 architecture has been reported. Diode connected triple-well NMOS transistors are load devices in each gain cell of the cascade of limiting amplifiers to make the gain a function of device sizes only. The fabricated chip occupies an area of 0.96mm2 in 0.18um CMOS process with a 1.8V power supply. 6.2 Suggested Future Work The goal of this research is to develop on-chip measurement circuits that can exhaustively characterize the increasing signal integrity problems in integrated circuits. It has been shown that parallel sampling can be applied to measure on-chip signals without sampling the signal at very high sampling rates. However, this architectur e is in its development stage and many areas remain to be studied so that it evolves into a complete system that can be integrated as an embedded test circuit. Some simple design change s should allow this arch itecture to be deployed to measure any critical signals. Most important issues that need to be addresses in future evolutions are Non-destructive probing Reducing system jitter and skew errors, increasing output SNR Reducing silicon area, most important test metric in embedded test Non-destructive probing: Power and ground lines on a chip are designed to drive huge loads and so this measurement circuit would not really load these nodes when signals on them need to be measured. Similarly, measuring signals at the outputs of the clock buffers in a highspeed digital circuit would not be a problem. These clock signals are routed to a number of sequential logic circuits on the chip, and the buffers are design ed to drive larg e capacitive loads in the circuit. However, when measuring critic al nodes that are not designed to drive large capacitances, this on-chip signal sh ape capturing circuit should not load the node that is being probed. Non-invasive or non-destruct ive probing is very important. In such cases, there is a need

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119 for a buffer design that provides the measurement circui t with the signal without having the circuit load the node that is pr obed. If the signals to be sample d have rail-to-rail swings, then techniques such as voltage di vision, or higher supply for the bu ffer circuit can be explored. Reducing system jitter a nd increasing output SNR: In Chapter 3, effects of timing errors are discussed on the measurement circuit s output signal-to-noise ratio. In a deep submicron manufacturing processes, tolerances of ji tter and clock skew errors are very limited. In such tight constraints, delay-locked loop a nd Vernier delay lines based on DLLs can produce delays and clock signals with re duced jitter and skews. A delaylocked loop based Vernier delay line has been simulated in 65nm process with a 1.2V power supply. Reducing silicon area, most importan t test metric in embedded test: The prototype demonstrated in this work uses 10 parallel samplers, and voltages on each channel are exported off-chip via a bond pad. Bond pads occupy a lot of silicon area. This problem can be addressed by multiplexing the outputs via n:1 analog multiplexer. The voltages from the channels can be converted to corresponding currents using a single gm device in each channel and the currents can be multiplexed via analog current mirrors to a single bond pad. This reduces the silicon area required by the system by a huge factor. All the above discussions regarding future work are shown in Fi gure 6-1. Exploring and addressing these issues in this may allow this to be an inexpensive solu tion to measuring on-chip signals.

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120 Figure 6-1. Addressing loadi ng, jitter and silicon area.

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121 APPENDIX SPECTRUM OF OUTPUT SIGNAL FROM THE SNAPSHOT ARCHITECTURE If the delays of the buffers are not matched between the parallel samplers, the output signal is a result of what is called the non-uniform sa mpling. In such a case, a ssuming a constant skew for each buffer but different from other buffers, we can assume the following for the sampling instants of the samplers. Unlike uniform sampling (Figure A-1), where the final interlaced samples are at times t, 2t, 3t with respect to the reference time, we can assume the samples in this case to be at times t0, t1, t2, with respect to the reference time (Figure A-2). The digital spectrum of such a non-uniformly sampled signal has been derived in [Jen88], and is given by Xout() 1 t 1 K e j k 2Kt rmte jkm 2K m 0 K 1 X k 2Kt k where rm mt tm t (A-1) Figure A-1. Uniform sampling

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122 Figure A-2. Non-uniform sampling Here, the total number of samples is K. Architect urally if changes are made such that these K samples can be divided into n sets with p samples in each set (Figure A-3) and that all the samples in each set are off from their ideal samp le instants by the same amount, we can derive the following. This change in the architecture can be brought by the addition of a Vernier delay line that is discussed in detail earlier. The goal he re in this appendix is to derive the equation to represent the spectrum of the signal that is obta ined from the samples satisfying the condition K = np. The sample sets are, (0,1,2,3,.., p 1)0,( p p 1,...,2 p 1)1,(2 p ,2 p 1,...,3 p 1)2,...,(( n 1) p ,( n 1) p 1,..., np 1)n 1 For this condition in (A-1), we have, r0 r1 ... rp 1 t0rp rp 1 ... r2 p 1 t1: r( n 1) p r( n 1) p 1 ... rnp 1 tn 1

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123 Figure A-3. Sampling instants with same t between samplers and irregular t between samplers. Therefore, we can write (A-1) as, Xout() 1 t 1 K e j k 2Kt t0te jkm 2K m 0 p 1 e j k 2Kt t1te jkm 2K m p 2 p 1 ... e j k 2Kt tn 1te jkm 2K m ( n 1) p np 1 X k 2Kt k 1 t 1 K e j k 2Kt tite jkm 2K m ip ( i 1) p 1 i 0 n 1 X k 2Kt k 1 t 1 K e j k 2Kt tite jkm 2K m ip ( i 1) p 1 i 0 n 1 X k 2Kt k (A-2) For the case of sinusoidal input, X ( )=2 ( 0) the above equation can be written as Xout() 1 t 1 K e j0 k 2Kt tite jk ( m ti) 2K m ip ( i 1) p 1 i 0 n 1 20 k 2Kt k Xout() 1 t 1 K e j0tite jkm 2K m ip ( i 1) p 1 i 0 n 1 20 k 2Kt k That is the digital spectrum is represented by the following equation.

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124 Xout() 1 t 1 K e j0t0te jk 2np m m 0 p 1 e j0t1te jk 2np m m p 2 p 1 ... e j0tn 1te jk 2np m m ( n 1) p np 1 20 k 2Kt k (A-3)

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125 LIST OF REFERENCES [AASM05] D. Aksin, M. A. Al-Shyoukh, and F. Maloberti. A Bootstrapped Switch for Precise Sampling of Inputs with Signal Range beyond Supply Voltage. IEEE 2005 Custom Integrated Circuits Conference 2005. [AG99] A. M. Abo and P. R. Gray. A 1.5V, 10-bit, 14.3MS/s CMOS pipeline analog-to-digital converter. IEEE Journal of Solid-State Circuits vol. 34, no. 5, pp. 599-606, May 1999. [ASH05] E. Alon, V. Stojanovic, and M. A. Horowitz. Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise. IEEE Journal of Solid-State Circuits vol. 40, no. 4, April 2005. [ATRCA06] S. S. Akbay, J. L. Torres, J. M. Rumer, A. Chatterjee, and J. Amtsfield. Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation. IEEE International Test Conference pp. 1-10, October, 2006. [Awa98] S. S. Awad. Analysis of Accumu lated Timing Jitter in the Time domain. IEEE Transactions on Instrumentation and Measurement vol. 47, no. 1, pp. 69-74, February, 1998. [Bak05] R. J. Baker. CMOS Circuit Design, Layout and Simulation. IEEE Press, Wiley Interscience, 2005. [Bog04] E. Bogatin. Signal Integrity-Simplified. Pren tice Hall, Upper Saddle River, New Jersey, 2004. [Boh03] M. Bohr. High-Performance Logic Technology and Reliability Challenges. IEEE International Reliab ility Physics Symposium 2003. [BR01] M. Burns and G. W. Roberts. An Introduction to Mixe d-Signal IC Test and Measurement. Oxford Univ ersity Press, New York, 2001. [BRD96] K. Baker, A. M. Richardson, and A. P. Dorey. Mixed-Signal TestTechniques, Applications and Demands. IEE Proceedings Circuits Devices Systems vol. 143, no. 6, December, 1996. [CAHK04] A. Chatterjee, S. S. Akbay, A. Halder, and D. Keezer. Low-Cost Test of Embedded RF/Analog/Mixed-Si gnal Circuits in SoPs. IEEE Transactions on Advanced Packaging vol. 27, no, 2, pp. 352-363, May 2004. [CBS01] F. Caignet, S. Bendhia, and E. Si card. The challenge of signal integrity in deep submicrometer CMOS technology. Proceedings of the IEEE vol. 89, no, 4, pp. 556-573, April 2001.

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126 [CEF03] S. Choi, W. R. Eisenstadt, and R. M. Fox. Design of programmable embedded IF source for design self test. Proceedings of the 2003 International Symposium on Circuits and Systems vol. 5, pp. 241-244, May 2003. [CP96] R. Chandramouli and S. Pateras. Testing Systems on a Chip. IEEE Spectrum November. 1996. [DK01] M. Dessouky and A. Kaiser. Very Low-voltage digital-audio Modulator with 88-dB dynamic range using local switch bootstrapping. IEEE Journal of Solid-State Circuits vol. 36, no. 3, March 2001. [DSH00] P. Dudek, S. Szczepanski, and J. V. Hatfield. A High-Resolution CMOS Time-to-Digital Converter Uti lizing a Vernier Delay Line. IEEE Transactions on Solid-State Circuits vol. 35, no. 2, February 2000. [EE93] Y. Eo and W. R. Eisenstadt. High-Speed VLSI Interconnect Modeling Based on S-Parameter Measurements. IEEE Trans. Comp. Hybrids Manuf. Technol. vol. 16, pp. 555-562, August, 1993. [EFYYZ04] W. R. Eisenstadt, R. M. Fox, Q. Yin, J. S. Yoon, and T. Zhang. On-Chip Microwave Test Circuits fo r Production IC Measurements. 64th ARFTG conference December 2004. [FSR06] C. J. B. Fayomi, M. Sawan, and G. W. Roberts. Low-voltage Analog Switch in deep submicron CMOS: design technique and experimental measurements. IEICE Trans. Fundamentals vol. E89, no. 4, April, 2006. [Gre92] J. C. Greer. Error Analysis for Pseudo-Logarithmic Amplification. Meas. Sci. Technol. 3, 1992. [GM93] P. R. Gray and R. G. Meyer. An alysis and Design of Analog Integrated Circuits. Wiley, New York, 1993. [GVC98] A. V. Gomes, R. Voorakaran am, and A. Chatterjee. Modular fault simulation of mixed signal circuits with fault ranking by severity. IEEE International Symposium on Defect a nd Fault Tolerance in VLSI Systems pp. 341-348, November 1998. [HAMWMH98] R. Ho, B. Amrutur, K. Mai, B. Wilburn, T. Mori, and M. A. Horowitz. Applications of on-chip samplers for test and measurement of integrated circuits. Symposium on VLSI Circuits, Digest of Technical Papers pp. 138-139, June 1998. [HBC03] A. Halder, S. Bhattacharya, and A. Chatterjee. Automatic multitone alternate test generation for RF ci rcuits using behavioral models. Proceedings International Test Conference vol. 1, pp. 665-673, September 2003.

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127 [HCW00] P. Huang, Y. Chen, and C. Wang. A 2-V 10.7MHz CMOS Limiting Amplifier/RSSI. IEEE Journal of Solid-State Circuits vol. 35, no, 10, pp. 1474-1480, 2000 [He06] M. He. Embedded Substrate Noise Measurement for MixedSignal/RF/Microwave ICs. Ph.D. Dissertation University of Florida, 2006. [HR03] M. M. Hafed and G. W. R oberts. Techniques for High-Frequency Integrated Test and Measurement. IEEE Transactions on Instrumentation and Measurement vol. 52, pp. 1780-1786, Dec. 2003. [Hu94] C. Hu. Ultra large scale integr ation device scaling and reliability. Journal of Vac. Sco. Tech. B vol. 12, no. 6, pp. 3237-3241, November, 1994. [Hug86] R. S. Hughes. Logarithmic Amplif ication with Application to Radar and E.W. Artech House, Dedham, MA, 1986. [IBM02] IBM RF & Analog Test Developmen t. Lowering Test Costs for RF ICs. IBM Technical Note, Dec. 2002. [ITR01] The International Technology Roadmap for Semiconductors 2001, pp. 1011, 2001. [ITR03] The International Technology Roadmap for Semiconductors 2003, pp. 2730, 2003. [Jen88] Y. C. Jenq. Digital Spectra of Non uniformly Sampled Signals: Fundamentals and High-Speed Waveform Digitizers. IEEE Transactions on Instrumentation and Measurement vol. 37, no. 2, pp. 245-251, June, 1988. [Jin87] R. P. Jindal. Giga hertz-band high-gain low-noise AGC amplifiers in fineline NMOS. IEEE Journal of Solid-State Circuits vol. 22, no. 4, pp. 512521, August 1987. [Kim92] K. Kimura. Some circuit desi gn techniques for bipolar and MOS pseudologarithmic rectifiers oper able on low supply voltage. IEEE Circuits and Systems I: Fundamental Theory and Applications vol. 39, no. 9, pp. 771777, September 1992. [Kim93] K. Kimura. A CMOS Logarithmic IF Amplifier with unbalanced sourcecoupled pairs. IEEE Journal of Solid-State Circuits vol. 28, no. 1, pp. 7883, January 1993.

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128 [KIO01] H. Kim, M. Ismail, and H. Olsson. CMOS Limiters with RSSIs for Bluetooth Receivers. Proceedings of 44th IEEE 2001 Midwest Symposium on Circuits and Systems vol. 2, pp. 812-815, 2001. [KKMSK01] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi. Explicit Analysis of Channel Mismatch Effects in TimeInterleaved ADC Systems. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications vol. 48, no. 3, March, 2001. [KMKO99] H. Kobayashi, M. Morimura, K. Kobayashi, and Y. Onaya. Aperture Jitter Effects on Wideband Sampling systems. IEEE Instrumentation and Measurement Technology Confernece pp. 880-885, Venice, Italy, May, 1999. [KRA95] S. Khorram, A. Rogougaran, and A. A. Abidi. A CMOS Limiting Amplifier and Signal-Strength Indicator. Symposium on VLSI Circuits Digest of Technical Papers pp. 95-96, 1995. [Lar99] P. Larsson. Power Supply Noise in Future ICs: A Cr ystal Ball Reading. IEEE Custom Integrated Circuits Conference 1999. [LCMK94] C. Ljuslin, J. Chiristiansen, A. Marchioro, and O. Klingsheim. An Integrated 16-channel CMOS time to digital converter. IEEE Transactions on Nucl. Sci. vol. 41, pp. 104-108, August, 1994. [LS93] P. Larsson and C. Svensson. Meas uring high-bandwidth signals in CMOS circuits. Electronic Letters vol. 29, no. 20, pp. 1761-1762, September 1993. [Man96] J. G. Maneatis. Low-jitter Pr ocess-Independent DLL and PLL Based on Self-Biased Techniques. IEEE Journal of Solid-State Circuits vol. 31, no. 11, November, 1996. [MH90] R. Moazzami and C. Hu. Projecting gate oxide reliability and optimizing reliability screens. IEEE Transactions on Electron Devices vol. 37, no. 7, July 1990. [MH93] J. G. Maneatis and M. A. Ho rowitz. Precise Delay Generation Using Coupled Oscillators. IEEE Journal of Solid-State Circuits vol. 28, no. 12, December, 1993. [MTRA04] A. Muhtaroglu, G. Taylor, and T. Rahal-Arabi. On-Die Droop Detector for Analog Sensing of Power Supply Noise. IEEE Journal of Solid-State Circuits vol. 39, no. 4, April, 2004. [PL76] A. Peled and B. Liu. Digita l Signal Processing, Theory, Design and Implementation. John Wiley & Sons, New York, 1976.

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129 [Raz01] B. Razavi. Design of Analog CMOS Integrated Circuits. McGraw-Hill, New York, 2001. [Rus04] S. Rusu. Trends and Challenges in High-Performance Microprocessor Design. Electronic Design Processes Monterey, CA, April, 2004. [SAW90] M. Shinagawa, Y. Akazawa, and T. Wakimoto. Jitter Analysis of HighSpeed Sampling Systems. IEEE Journal of Solid-State Circuits vol. 25, no. 1, pp. 220-224, February, 1990. [Ste99] J. Steensgaard. Bootstra pped low-voltage analog switches. Proceedings of IEEE International Symp. On Circuits and Systems vol. 2, pp 29-32, 1999. [SZ03] K. L. Shepard and Y. Zheng. On -chip oscilloscopes for noninvasive timedomain measurement of waveforms in digital integrated circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems vol. 11, issue 3, pp. 336-344, June 2003. [TMN02] M. Takamiya, M. Mizuno, a nd K. Nakamura. An On-Chip 100GHz Sampling Rate 8-channel Sampling oscilloscope with embedded sampling clock generator. ISSCC, Session 11, TD: RF/High-Speed Technologies 2002. [VB04] B. Vrignon and S. Bendhia. On-c hip Sampling sensors for high frequency signals measurement: evolution and improvements. Proceedings of the fifth IEEE International Caracas C onference on devices, circuits and systems Dominican Republic, November, 2004. [VC98] P. Variyam and A. Chatterjee. Enhancing test effectiveness for analog circuits using synthe sized measurements. 16th IEEE Proceedings VLSI Test Symposium pp. 132-137, April 1998. [VC00] P. Variyam and A. Chatterjee. Specification Driven Test Generation for Analog Circuits. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems vol. 19, no, 10, pp. 1189-1201, October 2000. [VCC02] P. Variyam, S. Cherubal, a nd A. Chatterjee. Prediction of analog performance parameters using fast transient testing. IEEE Transactions on Computer Aided Design of Inte grated Circuits and Systems vol. 21, no. 3, pp. 349-361, March 2002. [Vin98] B. Vinnakota. Analog and MixedSignal Test. Prentice Hall PTR, Upper Saddle River, New Jersey, 1998.

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130 [Vog05] C. Vogel. The Impact of Combined Channel Mismatch Effects in TimeInterleaved ADCs. IEEE Transactions on Instrumentation and Measurement vol. 54, no. 1, February, 2005. [Voo00] R. Voorakaranam. Test genera tion for accurate prediction of analog specifications. 16th IEEE Proceedings VLSI Test Symposium pp. 137-142, May 2000. [WW88] K. D. Wagner and T. W. Williams Design for Testability of Mixed-Signal Integrated Circuits. International Test Conference pp. 823-828, September 1988. [YEF04] Q. Yin, W. R. Eisenstadt, and R. M. Fox. A Translinear based RF RMS Detector for Embedded Test. Proceedings of the 2004 International Symposium on Circuits and Systems vol. 1, pp. 1245-1248, 2004. [ZEF04] T. Zhang, W. R. Eisenstadt, a nd R. M. Fox. A Novel 5GHz RF Power Detector. Proceedings of the 2004 International Symposium on Circuits and Systems vol. 1, pp. 1897-1900, 2004.

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131 BIOGRAPHICAL SKETCH Sudeep Puligundla was born in Andhra Pradesh, India. He received his Bachelor of Engineering degree in electronics and communi cations engineering fr om Andhra University, India in 2001 and his M.S. degr ee in electrical engineering from Clemson University, South Carolina in 2002. He was awarded Gr aduate Alumni Fellowship by th e University of Florida in Gainesville, Florida where he received a Ph.D degree in electrical engineering in 2007. During the summer and the fall of 2006, he worked as a Graduate Techni cal Intern at Intel Corporation, Hillsboro, Oregon and during the summ er of 2002, he worked as an Engineering Intern at Raritan Computer Inc., New Jersey. His research interests are in the areas of analog/mixed-signal/RFIC design, circuit validation, and embedded IC design for test.