Citation
Evaluation of Utilizing PMOS Transistors for Substrate Noise Reduction in a 2.4-GHz Receiver

Material Information

Title:
Evaluation of Utilizing PMOS Transistors for Substrate Noise Reduction in a 2.4-GHz Receiver
Creator:
YU, CHIKUANG ( Author, Primary )
Copyright Date:
2008

Subjects

Subjects / Keywords:
Electric potential ( jstor )
Inductance ( jstor )
Noise measurement ( jstor )
Noise reduction ( jstor )
Noise spectra ( jstor )
Power lines ( jstor )
Signals ( jstor )
Simulations ( jstor )
Transistors ( jstor )
White noise ( jstor )

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Source Institution:
University of Florida
Holding Location:
University of Florida
Rights Management:
Copyright Chikuang Yu. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Embargo Date:
5/31/2009
Resource Identifier:
659871411 ( OCLC )

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1 EVALUATIONOFUTILIZINGPMOS TRANSISTORSFOR SUBSTRATE NOISE REDUCTION IN A 2.4 GHz RECEIVER By CHIKUANG YU A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2007

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2 ” 2007 Chikuang Yu

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3 Tomymother,.Hersupport,encouragement,andconstantlovehave sustained me throughout my life.

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4 ACKNOWLEDGMENTS Iwouldliketoexpressmydeepgratitudeandappreciationtomyadvisor,Professor KennethK.O,forhispatient,constantencouragementanddevotion.Underhissupervision,Ihad opportunitiestoworkinmicroelectronics,whicheventuallybecameajoyforme.Ialsowould liketothankProfessorJenshanLin,ProfessorRizwanBashirullahandProfessorLocVu-Quoc for their interest in this work and serving on my Ph.D. supervisory committee. IwouldliketothankalltheformerandcurrentcolleaguesintheSiMICSresearchgroup fortheirhelpfuldiscussions,advice,andfriendship.Somenamesarelistedhere:XiaolingGuo, HaifengXu,XiLi,ZenbiaoLi,BrianFloyd,Chih-MingHung,Feng-JungHuang,YochuolHo, NamkyuPark,Seong-MoYim,Dong-JunYang,RanLi,Jau-JrLin,Hsin-TaWu,YuSu, ChanghuaCao,YanpingDing,Eun-YoungSeok,Kwang-ChunJung,SwaminathanSankaran, Chuying Mao, Seon-Ho Hwang, Myoung-Hwan Hwang, and Ning Zhang. MuchappreciationgoestoTexasInstruments,Dallas,Texas,forsupportingmyresearch project. Finally,Iamgratefultomytwobrothers,andtomyMother,towhomthisworkis dedicated.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 CHAPTER 1INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.1Attention to Substrate Noise Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.2Review of Substrate Noise Problems on Radio Frequency (RF) Blocks. . . . . . . . . . .20 1.2.1 Effects of Substrate Noise on Low Noise Amplifiers (LNAs) . . . . . . . . . .20 1.2.2 Effects of Substrate Noise on Voltage Control Oscillators (VCOs) . . . . . .21 1.2.3 EffectsoftheSubstrateNoiseCouplingonPhase-LockedLoop(PLL) Jitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.3Review of the Substrate Noise Coupling Mechanism and Modeling . . . . . . . . . . . . .24 1.3.1 Coupling Mechanisms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.3.2 Modeling Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.4Substrate Noise Reduction Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 1.4.1 Guard Ring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 1.4.2 High-Resistivity Substrate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 1.4.3 Triple Well Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 1.4.4 Design Consideration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 1.5Substrate Noise Suppression Using P-Channel Mental-Oxide-Semiconductor (PMOS) Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 1.6Design Challenge of Substrate Noise Suppression Using PMOS Transistors. . . . . . .41 1.7Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 2METHODOLOGY OF STUDYING SUBSTRATE NOISE COUPLING . . . . . . . . . . . . . .44 2.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 2.2Noise Generation Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 2.2.1 Time Domain Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 2.2.2 Frequency Domain Measurement Results. . . . . . . . . . . . . . . . . . . . . . . . . .48 2.3SubstrateStorm and DC Measurements for Substrate Modeling. . . . . . . . . . . . . . . . .50 2.3.1 SubstrateStorm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 2.3.2An Example of the Layout Extraction and Simulation . . . . . . . . . . . . . . . .54 2.3.3 Substrate Model Extraction Using DC Measurement . . . . . . . . . . . . . . . . .55 2.4Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

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6 3LNA AND MIXER DESIGN AND MEASUREMENT RESULTS . . . . . . . . . . . . . . . . . . .58 3.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.2Topology and Design Consideration of P and N-Channel Metal-OxideSemiconductor Low Noise Amplifier (PMOS and NMOS LNAs). . . . . . . . . . . . . . .59 3.3Measurement Results of PMOS and NMOS LNAs. . . . . . . . . . . . . . . . . . . . . . . . . . .64 3.3.1 Gain of LNAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 3.3.2 Noise Figure of LNAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 3.3.3 Isolation and Linearity of LNAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 3.4Topology and Design Consideration of PMOS and NMOS Mixers . . . . . . . . . . . . . .69 3.5Measurement Setup and Results of PMOS and NMOS Mixers . . . . . . . . . . . . . . . . .71 3.5.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 3.5.2 Measurement Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 3.6Flicker Noise Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 3.7Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4EFFECTS OF THE NOISE COUPLING ON LNAS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.2Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 4.3Noise Figure Measurement Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 4.4Effects on Shared and Separated Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 4.5Output Spectra Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 4.6Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 5NOISE IN A BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 6 5.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 5.2Noise in Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 5.2.1 Flicker Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 5.2.2 White Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 5.3Noise from Input Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 5.4Output Noise of 8-Stage Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 5.5A Simple Noise Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 5.6Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 15 6NOISE COUPLING MECHANISMS BETWEEN LNAS AND BUFFERS . . . . . . . . . . .117 6.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.2Noise Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 9 6.2.1 Buffer Output Spectrum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 6.2.2 Switching Noise in the 8-stage Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . .120 6.2.3 Transistor Back-Gate Network Modeling . . . . . . . . . . . . . . . . . . . . . . . . .123 6.3Substrate Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 6.4Package Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 6.4.1 Inductive Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 6.4.2 Capacitive Coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 6.4.3 Summary of Model and Grounding Issues . . . . . . . . . . . . . . . . . . . . . . . .134

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7 6.5Noise Coupling Mechanisms in LNAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 6.5.1 Noise at NMOS LNA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 6.5.2 Noise at NMOS LNA Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 6.5.3 Comparison of PMOS and NMOS LNA. . . . . . . . . . . . . . . . . . . . . . . . . .139 6.5.4 Simulation with Substrate Model Only. . . . . . . . . . . . . . . . . . . . . . . . . . .141 6.6Measurement Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 6.7Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 43 7SUMMARY AND FUTURE WORK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 7.1Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 46 7.2Suggestions for Future Work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 APPENDIXSUBSTRATE RESISTANCE MODELS AND PACKAGE MODELS. . . . . . .150 LIST OF REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 57 BIOGRAPHICAL SKETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

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8 LIST OF TABLES T able page 3-1Performance of PMOS versus NMOS LNAs.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 3-2Performance of PMOS versus NMOS mixers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 5-1Rise time (psec) of the first-4-stage inverters in the 8-stage buffer. . . . . . . . . . . . . . . . . .107 6-1Average output noise power of LNAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 6-2Variation of 20 measurements in 4 different samples. . . . . . . . . . . . . . . . . . . . . . . . . . . .143 6-3Variation of 5 different measurements in each PMOS and NMOS LNA . . . . . . . . . . . . .143 A-1NMOS LNA substrate resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 A-2PMOS LNA substrate resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 A-3Chip-on-board PMOS LNA coupling coefficients and inductances.. . . . . . . . . . . . . . . . .154 A-4Chip-on-board NMOS LNA coupling coefficients and inductances. . . . . . . . . . . . . . . . .155 A-5Packaged PMOS LNA coupling coefficients and inductances.. . . . . . . . . . . . . . . . . . . . .155 A-6Packaged NMOS LNA coupling coefficients and inductances. . . . . . . . . . . . . . . . . . . . .156

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9 LIST OF FIGURES Figure page 1-1Substrate noise coupling in a single chip with system-on-chip design.. . . . . . . . . . . . . . . .18 1-2The LNA output spectrums with only amplified input signal. . . . . . . . . . . . . . . . . . . . . . .20 1-3The LNA output spectrum in the presence of substrate noise. . . . . . . . . . . . . . . . . . . . . . .20 1-4Spurious tones appearing at both side of the VCO oscillation frequency (3.5GHz) when VCO is under 1MHz switching noise injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1-5Comparison of the simulated and measured results of spur power versus injected noise frequency.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1-6Supply/ground line connections between the noise source and PLL circuits.. . . . . . . . . . .22 1-7Jitters in PLL1 and PLL2. (A) Jitter of PLL2 with a bandwidth (BW) of 1 and 4 MHz under noise injection conditions and (B) jitter of PLL1 as function of the frequency difference between NCk and Fref.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1-8Coupling mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1-9Types of substrates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1-10Coupling paths in (A) high resistivity and (B) low resistivity substrates.. . . . . . . . . . . . . .25 1-11Macro models of the substrate for different frequency range.. . . . . . . . . . . . . . . . . . . . . . .26 1-12Small signal model for body effect in a CMOS transistor. . . . . . . . . . . . . . . . . . . . . . . . . .27 1-13Small signal model in a CMOS transistor under substrate noise injection with noise amplitude Vnat node B.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1-14Metal shielding structure to reduce inductive coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1-15Macromodel for a heavily doped substrate.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1-16A 4-port substrate model.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 1-17P+ guard ring in p-substrate and n+ guard ring in n-well . . . . . . . . . . . . . . . . . . . . . . . . . .33 1-18Isolation comparison between no guard (P_P_PW_50) and guard structure (PGR_50). . .34 1-19Inductance between on-chip ground and the package ground. . . . . . . . . . . . . . . . . . . . . . .34

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10 1-20Isolation (S21) comparison between high, medium, and low resistivity substrates. . .. . . .35 1-21Triple well process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 1-22Isolation (S21) comparison between isolated p-well (deep n-well, triple well process), guard ring and normal substrate in p+ and p-substrate.. . . . . . . . . . . . . . . . . . . . . . . . . . . .36 1-23Isolated p-well using special N-type buried layer process. . . . . . . . . . . . . . . . . . . . . . . . . .37 1-24Isolation comparison between special N-type buried layer process and normal substrate..37 1-25Body tie structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 1-26Typical floorplan for the mixed-signal design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 1-27Noise coupling in NMOS and PMOS transistors.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2-1Concept of the experimental observation.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 2-28-stage tapered buffer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 2-3Layout of the buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 2-4Buffer measurement setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 6 2-5Time-domainoutputwaveformsofthebufferwhenthebufferisworkingat(A)13MHz (B) 47MHz (C) 500MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 2-6Bypass capacitor in series with the inductor on the power supply line causes power line bouncing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 2-7Frequency domain measurement results of the buffer when the buffer is working at (A) 13, (B) 47, and (C) 500 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 2-8The output noise floor of buffer at the frequency around 2.3222 GHz when the buffer is working at 13, 47, and 500 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 2-9A simulation flow diagram of the SubstrateStorm.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2-10Substrate model.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2-11Resistor and capacitor networks.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2-12Conceptualization of regions and cross-sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2-13A simple test structure of two p+ implant regions with separated distance D. . . . . . . . . . .54

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11 2-14Comparison between the simulated and theoretical results. . . . . . . . . . . . . . . . . . . . . . . . .55 2-15The concept of extracting the substrate model using DC measurement.. . . . . . . . . . . . . . .56 2-16Test structures for DC measurement.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3-1Direct conversion receiver architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3-2The LNA circuit schematics.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3-3Input matching of the PMOS LNA.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 3-4The consideration of LNA bypass circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3-5The LNA die photographs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3-6A packaged LNA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3-7A simplified schematic of the source degeneration NMOS LNA. . . . . . . . . . . . . . . . . . . .65 3-8Small-signal noise model of an LNA with inductive source degeneration. . . . . . . . . . . . .67 3-9Circuit schematics of mixers.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3-10The die photographs of mixers.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 3-11A packaged mixer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 3-12The measurement setup for PMOS mixer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 3-13A single-balanced mixer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 3-14Measured noise figure and gain at varying LO power levels.. . . . . . . . . . . . . . . . . . . . . . .74 3-15Flicker noise measurement setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 3-16Flicker noise measurement results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4-1PMOS and NMOS LNA test chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 4-2Types of measurement setups.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 4-3Thegainandnoisefiguremeasurementresultsof(A)NMOSand(B)PMOSLNAwhen the buffer is working at 13MHz with shared ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

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12 4-4Gain and noise figure measurement results of (A) NMOS and (B) PMOS LNA when buffer is working at 47MHz with shared ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 4-5Large scale noise figure measurement results of (A) NMOS and (B) PMOS LNA when buffer is working at 13MHz with shared ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 4-6The spur frequencies (integer multiples of 13MHz buffer working frequency) and the frequencies (2-2.03GHz) measured by noise figure meter . . . . . . . . . . . . . . . . . . . . . . . . .84 4-7Large-scale noise figure measurement results of (A) NMOS and (B) PMOS LNA when buffer is working at 47MHz with shared ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 4-8Large-scale noise figure measurement results of (A) NMOS and (B) PMOS LNA when buffer is working at 500MHz with shared ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4-9Output noise power spectrum density of buffer in (A) NMOS and (B) PMOS LNA test structures. (C) NMOS and (D)PMOS LNA under buffer noise injection. . . . . . . . . . . . . .86 4-10Effects of the noise figure of (A) PMOS and (B) NMOS LNA on shared and separated ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 4-11Effects of the noise figure of (A) PMOS and (B) NMOS LNA on shared and separated ground in larger scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 4-12Output Spectra of (A) NMOS and (B) PMOS LNAs with shared and separated ground. Mean difference between shared and separated grounds for (C) NMOS and (D) PMOS LNAs.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 4-13BufferandLNAoutputspectra.(A)Outputspectraofbufferswhenbuffersareworking at13MHz.(B)Thedifferenceofbufferoutputpower.(C)NMOSandPMOSLNAoutput spectra under 13MHz buffer noise injection. (D) LNA output power difference (shared ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 4-14Buffer and LNA output spectra. (A) Buffer output spectra when buffers are working at 47MHz.(B)Thedifferenceofbufferoutputpower.(C)NMOSandPMOSLNAoutput spectraunder47-MHzbuffernoiseinjection.(D)LNAoutputpowerdifference(shared ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 4-15Buffer and LNA output spectra. (A) Buffer output spectra when buffers are working at 13MHz. (B) Difference of buffer output power. (C) NMOS and PMOS LNA output spectra under 13MHz buffer noise injection. (D) Difference of LNA output power (separated ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 4-16BufferandLNAoutputspectra.(A)Outputspectraofbufferswhenbuffersareworking at 47 MHz. (B) Difference of buffer output power. (C) Output spectra of NMOS and

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13 PMOSLNAunder47-MHzbuffernoiseinjection.(D)DifferenceofLNAoutputpower (separated ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 5-1Noise reduction with different switching frequency.. . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 5-2Phase noise of (A) the HP8640B signal generator and (B) the buffer at 13MHz.. . . . . . .104 5-3Phase noise of (A) the HPE4421B signal generator and (B) the buffer at 13MHz. . . . . .105 5-4Phase noise of (A) the HP8640B signal generator and (B) the buffer at 47MHz.. . . . . . .105 5-5Phase noise of (A) the HPE4421B signal generator and (B) the buffer at 47MHz. . . . . .105 5-6Noise is added in input signals in circuit simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 5-7Simulated output noise spectrum of the 8-stage buffer when the buffer input signals are 13, 47,and 500-MHz sinusoidal waves.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 5-8Simulated output noise spectrum of the 8-stage buffer when buffer input signals are 13, 47, and 500 -MHz square wave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 5-9Simple inverter model.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 5-10Time-domain wave forms.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 5-11A system block diagram of noise in a inverter.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 5-12Simulated PSD of output voltage v.s. input frequencies. . . . . . . . . . . . . . . . . . . . . . . . . .114 5-13Simulated PSD of output voltage v.s. different rise time.. . . . . . . . . . . . . . . . . . . . . . . . .114 6-1System simulation of noise coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 6-2Clocking signal for the buffer is provided by an external source through an AC probe. .118 6-3Measured (solid line) and simulated (circle symbol) output spectra of buffer . . . . . . . . .119 6-4Distributed model for the last stage of the buffer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 6-5Measurement and simulation including parasitic gate resistance and output capacitance.120 6-6Switching noise in 8-stage buffer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 6-7The voltage spectrum at S node. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

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14 6-8A bypass capacitor in series with the inductor on the power supply line causing power line bouncing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 6-9Simulation (solid line) and measurement (circle symbols) of power line noise . . . . . . . .123 6-10The measurement setup for modeling the back-gate network of transistors in the buffer.123 6-11Measured S-parameters (dark lines) and simulated S-parameters (gray line). . . . . . . . . .124 6-12Extracted circuit model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 6-13Conceptual model of the DC substrate model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 6-14A simplified substrate model for NMOS LNA test structure . . . . . . . . . . . . . . . . . . . . . .127 6-15A simplified substrate model for PMOS LNA test structure. . . . . . . . . . . . . . . . . . . . . . .127 6-16transistor layouts in PMOS and NMOS LNAs.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 6-17The LNA and buffer with separated substrates.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 6-18MeasuredspectraatLNAoutputwhensubstratesofLNAandbufferareconnected(gray line) and separated by 10 m m (dark black line). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 6-19Averaged spur power at LNA output with respect to different separation between LNA and buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 6-20ThecircuitmodelforNMOSLNAand8-stagebufferwhilethesubstratesareseparated by 10 m m.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2 6-21Capacitive coupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 6-22Inductive coupling model in the package model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 6-23LNA Inductive coupling model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 6-24Chip-on-board (A) PMOS and (B) NMOS LNAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 6-25Packaged (A) PMOS and (B) NMOS LNAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 6-26Chip-on-board NMOS LNA output noise spectrum.. . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 6-27Packaged NMOS LNA output noise spectrum.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 6-28NMOS LNA input noise spectra.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

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15 6-29Chip-on-board PMOS LNA output and input noise spectra.. . . . . . . . . . . . . . . . . . . . . . .140 6-30Packaged PMOS LNA output and input noise spectra.. . . . . . . . . . . . . . . . . . . . . . . . . . .141 6-31Simulatedversusmeasuredoutputnoisespectraforpackaged(A)NMOSand(B)PMOS LNAs.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 A-1The circuit schematics and substrate ports of NMOS LNA and 8-stage buffer.. . . . . . . .150 A-2The circuit schematics and substrate ports of PMOS LNA and 8-stage buffer. . . . . . . . .153

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16 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulllment of the Requirements for the Degree of Doctor of Philosophy EVALUATIONOFUTILIZINGPMOS TRANSISTORSFOR SUBSTRATE NOISE REDUCTION IN A 2.4 GHz RECEIVER By Chikuang Yu May 2007 Chair: Kenneth K. O Major: Electrical and Computer Engineering System-on-chip(SoC)designcombiningfront-endcircuits,basebandanalogcircuits,and digitalsignalprocessing(DSP)circuitsisbecomingthesolutionofchoicefortheconsumer communicationmarket.However,thishighlevelofcomplexityandintegrationresultsinnoise couplingfromthedigitalcircuitrytotheRFandanalogcircuitry.Thenoisecouplingifnot properlyhandledcansignicantlydegradethesystemperformance.Reducingthisnoisecoupling is important and essential. Useofp-channelmetaloxidesemiconductor(PMOS)transistorsinanisolatedn-wellfor implementingRFcircuitstolowertheeffectsofsubstratenoisecouplingisexamined.2.4-GHz PMOSandNMOSlownoiseampliers(LNAs)forBluetoothapplicationsaredevelopedusing 0.18m mCMOStechnology.Bothutilizethecommon-sourcesingle-endedtopologywith inductivesourcedegeneration.ThePMOSandNMOSLNAsachieve15-and20-dBpowergain with3-and2-dBnoisegure,respectively.ComparedtoNMOSLNA,PMOSLNAhas~3dB lowergainand~1dBhighernoisegure.However,thePMOSLNAhasbetterlinearity.TheIIP3ofPMOSLNAisabout6-8dBhigherthanthatofNMOSLNA.BothPMOSandNMOSLNA are acceptable for Bluetooth applications.

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17 PMOSandNMOSmixersforBluetoothapplicationsarealsodevelopedusing0.18m m CMOStechnology.BothareGilbert-celldouble-balanceactivemixers.ThePMOSandNMOS mixersachieve6-and9-dBconversiongainwith8-and9-dBnoisegure,respectively. ComparedtotheNMOSmixer,thePMOSmixerhas~3dBlowergain,slightlylower double-sided-bandnoisegure(DSBNF),andcomparablethirdorderinputinterceptpoint(IIP3) andinput 1-dBcompressionpoint(IP1dB).ThePMOSmixerhas~10dBlowerickernoisethan the NMOS mixer so the PMOS mixer is better for direct conversion mixers. An8-stagetaperedbufferwhichcangenerateswitchingnoiseandtheLNAsarebuiltona singlechip.TheincreaseofnoisegureofPMOSLNAinthepresenceofbufferdigitalnoise injectionisabout10-15dBlowerthanthatfortheNMOSLNAatharmonicfrequenciesand ~0.2-0.4dBlowerforwhitenoise.NoisecouplingforLNAwiththesharedgroundwiththe bufferis~2-3dBhigherthanthosewithseparatedgrounds.Themeasurementsindicatethatthe PMOS LNA has better noise immunity than the NMOS LNA. TheLNAnoiseguredecreasesasthefrequencyofinputsignalisincreased.Thisisdue tothefactthatwhitenoisegeneratedbythebufferisdominatedbythenoiseofinputsourceand itsimpactonbufferoutputnoiseincreaseswithincreasingriseandfalltimes,becausethenoiseis amplied by the buffer for a longer duration. Thesimulationsandmeasurementsindicatethatthedominantnoisecouplingisinductive couplingthroughthebufferon-chippowerlineandLNAinputbondwire.Asamatteroffact,in the LNA/buffer test structure used in this study, the substrate coupling was negligible.

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18 CHAPTER 1 INTRODUCTION 1.1 Attention to Substrate Noise Coupling Withthescalingdownofthetransistorgatelengthtothedeepsub-micronregime,the high-frequencyperformanceofComplementaryMetal-OxideSemiconductor(CMOS)technologyhasbeendramaticallyimproved,makingitsuitableforcontemporaryhigh-speedcircuit design.InsteadofusingIII-Vcompoundmaterials,astandardCMOSprocessisbeingusedfor radiofrequency(RF)circuitstoreducethecostandchipsize.Withtheincreasingdemandfor morefunctions,stand-aloneRFproductsarenolongercompetitive.Instead,system-on-chip (SoC)designcombiningfront-endcircuits,basebanddemodulators,anddigitalsignalprocessing (DSP)circuitsisbecomingasolutionfortoday’scompactcommunicationmarket.Oneofthe problematicissuesinimplementingthissingle-chipsystemisthesubstratenoisecouplingas showninFigure1-1.Inasystemwhereallcircuitsarelocatedinonesubstrate,noisecancouple fromthedigitalcircuits,suchaslogicgatesorbufferofbase-bandandDSPcircuits,throughthe Digital circuits Analog circuits Substrate noise Digital circuits Analog circuits substrate noise (A) (B) Figure 1-1.Substrate noise coupling in a single chip with system-on-chip design.(A)Top view and (B) Cross section view.

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19 substratetoanalogcircuits,suchaslownoiseamplier(LNA),mixer,andvoltagecontroloscillator(VCO),anddegradetheperformanceofthecircuits.Forexample,inaBluetoothsystem,the receivingsignalpowerattheinputoftheLNAcanbeaslowas-90dBm.Ifthepowerlevelof coupledsubstratenoisefromthenearbydigitalcircuitsishigherthanthis,thenthisnoisewill overpowertheinputsignalanddegradethesensitivityofthesystem.Therefore,manyeffortshave been made to investigate this problem, and to try to predict and prevent this. Substratenoisecouplinghasbeenaddressedsincethe1970s[Cha01].Researchisgenerally grouped into following categories [Xu01]: Experimentalreports:reportingimpactsofsubstratenoiseonRFandmixed-modecircuit blocks. Substratemodeling:usingnumericalsimulationormodelextractionbasedonmeasurementto simulate noise coupling in the substrate. Noiseisolation:reducingnoisecouplingbydevelopingthetechniquessuchasthetriplewell process or guarding rings. Theprogresstodatecanbedividedintotwocategories.Thestudiesintherstcategory focusedonindividualcircuitblocks.Understandingthemechanismofnoisecouplingisimportant.Themechanismofnoisecouplingincludesthenoiseinjection,thenoisecouplingpath,and thenoisereception.Whereisthepossiblenoisesourceindigitalcircuits?Howisthisnoise injectedintothesubstrateorcircuits?Whatisthenoisecouplingpath?Howisthisnoiseabsorbed bythesensitiveanalogcircuits?Thestudiesintherstcategoryseektoanswerthesequestions. Thesecondcategoryofstudiesemphasizesthecouplingbetweentheblocksinanentiresystem. Thenoisemodelsforindividualcircuitblockshavebeenestablishedbasedonthestudiesinthe rstcategory.Theblocknoisemodelscanincludethecriticalnoisecouplingbehaviorparameters ofeachcircuitblock.Byusingamodelofthiskindinsystem-levelsimulations,thecomplexityof

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20 systemanalysiscanbesimpliedandtherequirementforcomputingtimeandmemorycanbe alleviated. 1.2 Review of Substrate Noise Problems on Radio Frequency (RF) Blocks 1.2.1 Effects of Substrate Noise on Low Noise Ampliers (LNAs) SubstratenoisecancoupletotheoutputoftheLNAandcorrupttheoutputspectrumofthe LNA.Thesenoisecouplingeffectshavebeenreported[Dic02,Haz04,Soe03,Xu01].Thetypical measurementresultsareshowninFigures1-2and(1-3)[Xu01].Figure1-2showstheLNAoutputspectrumwithonlytheampliedLNAinputsignalandFigure1-3showstheLNAoutput spectrumincludingtheampliedLNAinputsignalandcoupledsubstratenoise.Fromthegures, itcanbeseenthatcouplednoisecouldappearattheoutputofLNA.Ifthenoisefrequencyis Figure 1-2.The LNA output spectrums with only amplied input signal. Frequency (MHz) Power (dBm) Figure 1-3.The LNA output spectrum in the presence of substrate noise.

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21 locatedrightattheLNAsignalfrequency(1.575GHz)andtheampliedsignalisnotbigenough (smallerthan-60dBm),couplednoisecaneasilycorrupttheoutputsignal.AsreportedbyScott Hazeboom[Haz04],thenoisecouplinginaLNAcouldbethroughthebodynodeofthetransistorsortheinductoroftheLNA.ThiscouplingpathstronglydependsonthelayoutoftheLNA, location of the noise source, and the characteristics of the substrates. 1.2.2 Effects of Substrate Noise on Voltage Control Oscillators (VCOs) SubstratenoisecancoupletotheVCOoutputandbecomespuriousnoiseattheVCOoutputspectrum.TheinuencesofthesubstratenoisecouplingonVCOsarereportedbySoensetal. [Soe05]andLiaoetal.[Lia03].Figure1-4showstheoutputspectrumofa3.5GHzVCOunder substratenoiseinjection.Whenthesubstratenoise(fnoise)iscoupledtotheVCOandmixedwith theVCOoutputsignal(fLO),twospursatfrequencyoffLO-fnoiseandfLO+fnoiseareproducedand presentattheVCOoutputspectrum.Figure1-5showsthespurpowervarieswiththeinjected noisefrequency.Threemodelsrepresentingthreedifferentcouplingpathsarecomparedwiththe Figure 1-4.SpurioustonesappearingatbothsideoftheVCOoscillationfrequency (3.5GHz) when VCO is under 1MHz switching noise injection.

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22 measurementresults.Theresultsindicatethatmostnoiseimpactisduetonon-idealon-chip ground and inductor coupling. 1.2.3 Effects of the Substrate Noise Coupling on Phase-Locked Loop (PLL) Jitters ThesubstratenoisecanalsoaffectthePLLjitterperformance.Thissubstratenoisenot onlycouplesthroughthesubstratebutalsothroughtheglobalsupplyorgroundlines.These effectshavebeenillustratedindetailbyPatrickLarsson[Lar01].Figure1-6showsthedifferent Figure 1-5.Comparisonofthesimulatedandmeasuredresultsofspurpowerversus in j ected noise fre q uenc y . AVddAVssFigure 1-6.Supply/ground line connections between the noise source and PLL circuits. DigitalPLL0 VddVss AVddAVss DigitalPLL1 VddVss AVddAVss DigitalPLL2 VddVss (A) (B) (C)

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23 considerationsofthesupply/groundlineconnectionsbetweenthenoisesourceandthePLLcircuits.Withdifferentcongurations,noiseeffectsaredifferent.Figure1-7(A)showsthejitter inducedbyinjectednoisewithvaryingfrequencies(NCk)intoPLL2.Thejitterisreducedwith higherPLLbandwidth(4MHz),indicatingthatinjectednoisepossiblycomesfromthelooplter orVCO,bothofwhichhavethecharacteristicofthehigh-passlter.Increasingthebandwidthof PLL0alsoreduceditsjitter,sonoiseisagainfromthelooplterorVCO.Figure1-7(B)shows thejitterofPLL1asafunctionofthefrequencydifference(NCk-Fref)betweentheinjectednoise frequency(NCk)andPLLreferencefrequency(Fref).Thejitterincreasessignicantlywhenthe frequencydifferencebetweentheinjectednoisefrequencyandPLLreferencefrequencydrops belowPLLbandwidthof1and4MHz,indicatingthatthenoisecannotbesuppressedbyPLL feedbackloopwiththecharacteristicofalow-passlter.Theinjectednoisepossiblycomesfrom the phase detector (PD) or divider in the PLL feedback loop. Usually,analyzingthenoisecouplinginacomplexsystemismorechallengingthanina simplecircuitblock.Asintheexample,thepossibleplacesfornoisereceptioninthePLLinclude Figure 1-7.JittersinPLL1andPLL2.(A)JitterofPLL2withabandwidth(BW)of1and4 MHzundernoiseinjectionconditionsand(B)jitterofPLL1asfunctionofthe frequency difference between NCk and Fref.

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24 allcircuitblockssuchasVCO,PD,chargepumpanddividercircuits.Identifyingthemostvulnerableblocksisthekeytoreducingthenoisecouplingand,further,toimprovingthenoiseimmunity of the circuits. 1.3 Review of the Substrate Noise Coupling Mechanism and Modeling 1.3.1 Coupling Mechanisms 1.3.1.1 Resistive coupling Iftheintermediatebetweennoiseinjectionnodeandnoisereceptionnodeisaresistive structure,thennoisecouplesthroughtheresistivenetwork.Thistypeiscalledresistivecoupling. Forinstance,atlowerfrequencies,usuallybelow5GHz,thenoisecouplingbetweentwosubstrate contacts(AandB)asshowninFigure1-8(A)ismainlyresistivecoupling.Thecurrent,In1,is injectedintothesubstratethroughanohmiccontactandtravelsviatheresistivesubstratetosubstrate contact B. Fordifferenttypesofsubstrates,theseresistivecouplingpathscanbedifferent.Different couplingpathsleadtodifferentsubstrateresistancevalues(Rsub).Intoday’sCMOStechnology, twotypesofsubstratesarecommonlyusedasshowninFigure1-9Oneisthelightlydopedsubstrateformixed-signalICdesign.Theresistivityofthelightlydopedsubstrateisusuallybetween AB C D (p-substrate) (A) Resistive coupling (B) Capacitive coupling p+ p+ p+ n+ In1In2Figure 1-8.Coupling mechanism.(A) Resistive coupling. (B) Capacitive coupling. RsubRsub

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25 2to50 W -cm.Theotheristheheavily-dopedsubstratefordigitalICdesign.Theresistivityofthe heavily-dopedsubstrateisaround0.001 W -cm.Theformerhasnoepi-layer,butthelatterhasa lightlydopedepi-layer(10-15 W -cm)ontopoftheheavilydopedsubstrate.Figure1-10showsan exampleofthesubstrateresistancebetweentwonodesindifferenttypesofsubstrates.RA,RB, RC,andRDrepresenttheverticalresistanceandRsub,highandRsub,lowrepresentthehorizontal resistanceinthesubstrates.Inthehighresistivitysubstrate(Figure1-10(A)),thetotalresistance betweenAandBissumofRA,RB,andRsub,high.Thistotalresistanceincreasesastheseparation p + 0.1 W -cm p2-50 W -cm p+ 1 W -cm p10-15 W -cm p+ 0.001 W -cm 1 m m 10 m m 300 m m 1 m m 400 m m Figure 1-9.Types of substrates.(A) Lightly-doped and (B) heavily-doped substrates. (A) (B) AB C D Low resistivity High resistivity substrate substrate Rsub,highRsub,lowRARBRCRDFigure 1-10.Coupling paths in (A) high resistivity and (B) low resistivity substrates. (A) (B)

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26 betweenAandBincreases.Inthelowresistivitysubstrate(Figure1-10(B)),thesubstrateresistanceRsub,lowissmall.TotalresistancebetweenCandDisapproximatelyequaltosumofRCand RD.RCandRDstayapproximatelyconstantwhentheseparationbetweenCandDincreases. Therefore,thetotalresistancecanstayapproximatelyconstant.So,tonoisecurrent,thislow resistivitysubstrate(~0.001 W -cm)canactlikeaconductorandbecomeaglobalnoiseconnection to sensitive circuits. 1.3.1.2 Capacitive coupling Ifthecouplingprocessisviacapacitors,itiscalledthecapacitivecoupling.Asshownin Figure1-8(B)fromnodeCtoD,In2couplestonodeDthroughap/njunctioncapacitorformedby then+implantinp-substrate.Thistypeofcouplingusuallyhappensbetweenp-substrateand n-well or substrate and drain/source of the transistors. Inthesubstrate,thecouplingprocessdependsonthefrequency.AsreportedbyChenggangXu[Xu03],atlowfrequencies,lessthan1GHz,resistivecouplingisdominant.Thelow-frequencymodelisshowninFigure1-11(A).Athigherfrequencies,between1to5GHz,capacitive effectmustbetakenintoaccount.Aresistorshuntedwithacapacitorisdepictedinthemodelas showninFigure1-11(B).Asthefrequencygoesevenhigher,themorecomplexmodelin Figure1-11(C) is used. This high-frequency model is directly extracted using a tting method. (A) (B) (C) Figure 1-11.Macro models of the substrate for different frequency range.(A)Below1GHz. (B) Between 1 and 5 GHz. (C) Between 5and 10 GHz.

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27 1.3.1.3 Coupling through body of the transistor Substratenoisecanmodifythebodyvoltageofatransistor.Bymodulatingthe body-to-sourcevoltage,noiseistransferredtothedrainnodeofthetransistor.Thistypeofcoupling is usually modeled by threshold voltage (Vt) [Cha01] ,(1.1) where eSiisthesubstratedielectricpermittivity,NAisthesubstratedoping,Coxisthegateoxide capacitanceperarea,2 ffthesurfaceinversionpotentialandVsbthesource-to-bodypotential.In thesmallsignalmodelasshowninFigure1-12,thisnoisetransferringeffectcanbeexplainedby back-gate transconductance (gmb) [Cha01] (1.2) where gm is the small-signal transconductance. S B D gmbVBSroCDBCSBFigure 1-12.Small signal model for body effect in a CMOS transistor. V t V t0 2q e Si N A C ox ---------------------------2 f f V sb +2 f f – () + = g mb g m ---------2q e N A 2C ox 2 f f V sb + ------------------------------------------=

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28 Forapplicationsaroundafewgigahertz,couplingthroughthebodyofthetransistorisa moreseriousproblemthancapacitivecouplingthroughthejunctioncapacitorbetweenthebody anddrainofthetransistor,CDB.Figure1-13showsthetransistorundersubstratenoisecoupling. Ifthenoisevoltage,vn,isinjectedintothebodynodeofthetransistor,thetotaloutputnoisecurrent at drain noise is given by (1.3) whereCDBisthedrain-to-bodycapacitance.Thetypicalvalueofthejunctioncapacitance,CDBandCSB,is~100fFfora300 m mwidetransistorin0.18 m mCMOStechnologies,sothevalueof w CDBfora2.4GHzapplicationis~j1.5mS . Thetypicalratioofgmbtogmis~1/4in0.18 m m CMOSprocess,whichgivesthevalueofgmbof~10mS.Comparedto w CDB,gmbislarger.This indicatesthatnoisecurrentinducedbygmbislargerthanthatcoupledthroughbody-to-drain capacitance CDB. 1.3.1.4 Power and ground line coupling Indigitalsystems,thelargenumberoflogicgatesandip-opsproduceswitchingnoise intopowerandgroundlines.ThenoisepropagatesthroughthepowerandgroundlinestotheRF oranalogcircuits.Thecouplingmechanismcanberesistive,inductiveorcapacitive.Inductive i o v n j w C DB g mb – () = S B D gmbVBSCDBCSB IoVnFigure 1-13.SmallsignalmodelinaCMOStransistorundersubstratenoiseinjectionwit h noise amplitude Vnat node B.

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29 andcapacitivecouplingusuallyoccurbetweentwometallinesormetalplanes.Figure1-14shows theinductivecouplingbetweenconductor1andconductor2.Toreducetheinductivecoupling,a metalshieldwithtwoendsshortedtogroundisused.Thetwo-end-groundedshieldaroundconductor2formsaloopbetweenshieldandgroundtoprovidepathforcurrentIsinducedbynoise sourceIninconductor1toowthroughtheshield.ThisinducedcurrentIsfurtherinducesanother currentIssinconductor2tocanceloutthenoisecurrentInninducedbynoisesourceIn.Toreduce thecapacitivecoupling,agroundedmetalshieldcanbeusedtopreventtheshieldedmetalfrom electric elds and disruptive capacitive coupling. 1.3.2 Modeling Methods 1.3.2.1 Numerical modeling methods InSoC(system-on-chip)design,millionsoftransistorsareusuallyinvolvedinthecouplingprocess.Tosystematicallyanalyzethesubstratenoisetransportmechanismandpredictthe noiseinuenceonthecircuitsduringthedesignstage,aidfromsimulationtoolsisrequired.Two numericalmethodsbasedonelectromagnetictheoryhavebeenreported:boundary-element method[Gha98]andnite-differencemethod[Ver96].BothmethodsarederivedfromPoisson’s InIsInnIss Figure 1-14.Metal shielding structure to reduce inductive coupling. Metal shield Conductor2 Conductor1

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30 equationandcontinuityequation.Asimpliedformoftheseequationsthatdescribesthesubstrate behavior outside the active region can be written as follows [Ver93]: (1.4) where eSiisthepermittivityofsiliconsubstrate,istheelectriceld,and r isthecarrierconcentrationinthesubstrate.Withthisdifferentialequation,theentiresubstratecanbe solvedusingthenite-differencemethod.Alternatively,Equation(1.4)canberewrittenas Laplace’s equation (1.5) where F(r) isthepotentialattheobservationpoint.Intheelectrostaticlimit,ithasaintegralform (1.6) WhereG(r,r’)istheGreen’functionandJisthesourcecurrentdensity.Usingthisintegralform, boundary-element method is developed. Finite-differencemethodcommonlyemploysdiscretizationinthesubstrateproleand appliesdifferenceequationsateachnode.Formoreaccuratecalculation,usuallynediscretizationisrequiredbutnediscretizationproducesalargesparsematrix.Thislargematrixrequires hugememory.Boundary-elementmethodisnotverydiscretization-dependent,whichdramaticallyreducesthesizeofimpedancematrix.Howeverthematrixisfullydense[Ver96]andlonger computationtimeisrequired.Therefore,choosingapropermethodusuallydependsonthesize andcomplexityofthecircuitsinthesimulation.Recently,toolssuchasseismIChavebeendevelopedtoutilizeacombinationofthetwotechniquestoimproveaccuracywithacceptablecomputation time. e Si t E () 1 r -E () +0 = E 2F 0 = F r () Jrr , () Grr , () rd3r =

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31 1.3.2.2 Macromodel based on lumped elements Numericalcomputationandanalysisofthesubstratemodelareusuallyperformedafter layoutextraction.Duetothehugedigitalcircuitryandthelayoutcomplexity,arecursiveiteration betweenthecircuitsimulationandthepostlayoutvericationisatime-consumingjob.Asimple andscalablepoint-to-pointmacromodelbasedonlumpedelementswasproposedbyAnil Samavedam[Sam00].Figure1-15showsthemacromodelforaheavilydopedsubstrate.Inthis testsubstrate,ap+implantisusedasanoisesourcetoinjectsignalintosubstrateandanotherp+ implantisusedforthenoisesensortoreceivesignalfromthesubstrate.R1A(G1A)andR1B(G1B) aretheresistorsfromsourceandsensortothebulk.R2(G2)isthecross-couplingresistorbetween sourceandsensor.Duetosymmetryofstructures,G1AandG1Bareequalandcanbeexpressedas G1.ThenthetwoportY-parametersforthesubstratemacromodelbetweensourceandsensorcan be written as follows: G2G1BG1A W2W1p+ p+ x Source SensorFigure 1-15.Macromodel for a heavily doped substrate.

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32 .(1.7) Then, the Z-parameters are obtained by Y-parameters and written as follows: (1.8) where D isthenormofmatrixZ.Basedonexperimentalobservation,G2canbemodeledasan exponential function depending on separation x between source and sensor: (1.9) where a and b areconstantsextractedfrommeasurements.Theotherassumptionisthatthe self-impedanceofthesource(Z11)andsensor(Z22)areconstantvalue x .Thisself-impedanceis independentoftheseparationbetweentwoports.Basedontheabovetwoobservations,G1(x)can be solved as Y y 11 y 12 y 21 y 22 G 1 G 2 +G 2 – G 2 –G 1 G 2 + == Z z 11 z 12 z 21 z 22 Y 1 – 1 D --G 1 G 2 +G 2 G 2 G 1 G 2 + === D , G 1 2 2G 1 G 2 + = G2x ()a e b x – = (A) (B) Figure 1-16.A 4-port substrate model.(A)Schematicoftwoinverterswiththe4-port substrate model (B) Schematic of 4-port substrate model.

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33 (1.10) Themodelcanbealsoexpandedtoincludevariousdiffusionsizesandseparations.Moreover,a4-portsubstratemodelcanbeconstructedfromthetwoportmatrixasshownin Figure1-16 to represent the substrate model between ampliers. Utilizingamacromodelnotonlyspeedsthenoisecouplinganalysis,butalsogivesinsight intothenoisetransportmechanism.However,thisdoesn’tsolvealltheproblems.Theremaining includedistinguishingcriticalnoisesourcesandsensitivenodesinthecircuits,andanalyzingthe possible noise coupling paths in the substrate in order to generate a correct substrate network. 1.4 Substrate Noise Reduction Techniques 1.4.1 Guard Ring Oneofthemostefcientandeconomicalwaystoisolatethenoisecouplingistousep+or n+diffusionasguardringstructures.Figure1-17showsap+guardringinp-substrateandn+G 1 x () 1 2 x -----G 2 x () – 1 2 x -----14 x 2 G 2 2 x () + + = p-substrate n-well p+n+p+n+p+n+ n-well p+ n+ n+p+ p+n+ p-substrate p+ guard ring n+ guard ring Figure 1-17.P+ guard ring in p-substrate and n+ guard ring in n-well

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34 guardringinann-well.Aguardringabsorbsnoisecurrentfromnoisegeneratingcircuitsandpreventsthenoisecurrentfromreachingtosensitivecircuits.Equivalently,usingguardrings increasestheisolationbetweencircuits[To01,Lee03,Yeh04,Su93].Withtheguardring (P_P_PW_50inFigure1-18),theisolationimproves~10dBcomparedtothestructureswithouta guardring(PGR_50).Mostoftheresultsaremeasuredon-chipwithgoodgroundconnection. However,practically,packagingisrequiredformostcommercialproducts.The ~10dB Figure 1-18.Isolationcomparisonbetweennoguard(P_P_PW_50)andguardstructur e (PGR_50). Chip Package gndlee (Package) Down bond On-chip groundFigure 1-19.Inductance between on-chip ground and the package ground.pad

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35 down-bond-relatedparasiticsmustbeconsidered.Thisparasiticinductanceisbetweenon-chip groundandthepackagegroundasshowninFigure1-19 . Thisinductance(~0.2-0.5nH)increases theimpedancebetweentheguardringandground,anddecreasestheefciencyoftheguardring to drain out the noise. Therefore, it is important to reduce this common ground inductance. 1.4.2 High-Resistivity Substrate Anotherwaytoreducecouplingistousehigh-resistivitysubstrate.High-resistivitysubstratesimpedethenoisecurrentowbetweenthenoisesourceandnoise-sensitivecircuits.When comparedtothatforlow-resistivitysubstrate(Rsub<5 W -cm),themeasuredisolation(S21)for high-resistivitysubstrate(Rsub>1000 W -cm)isabout10-20dBhigherasshownin Figure1-20[Yan02]. Althoughusinghigh-resistivitysubstratesolvesthenoisecouplingproblem,otherproblems, such as latch-up effects and higher substrate cost, may become troublesome 1.4.3 Triple Well Process Triplewellisolationisoneofthemostefcientandpopularisolationtechniquesintoday’s ICdesign.Byhavingadeepn-wellatthebottomandregularn-wellsatthesideinap-substrate, Figure 1-20.Isolation (S21) comparison between high, medium, and low resistivity substrates.

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36 anisolatedp-wellisformedasshowninFigure1-21[Yeh04].Thisisolatedp-wellhasnoresistive connectiontothecommonp-substrate.Therefore,theresistivenoisecouplingfromthesubstrate canbeeliminated.Theisolation(S21)ofthetriplewellinp+orinp-substrateiscomparedto guard-ringandno-guard-ringstructuresinFigure1-22[To01].Forbothp+andp-substrate,isolatedp-well(socalleddeepn-wellortriplewellprocess)cansignicantlyimproveisolationcomp+ n+ n+ p+ PWNW NW DNW STI Isolated p-well Deep n-well p-substrate (STI: shallow trench isolation) Figure 1-21.Triple well process. Figure 1-22.Isolation(S21)comparisonbetweenisolatedp-well(deepn-well,triplewell process), guard ring and normal substrate in p+ and p-substrate.

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37 paredtoano-ringstructure.Atlowfrequencies,theisolationimprovementisgreaterthanthatat higher frequencies due to less capacitive effect. Asimilarconcept,usingadifferentprocessingtechniquetoincreasetheisolationcapability,isreported[Lee03].AsshowninFigure1-23,then-typeburiedlayerisformedbytheimplantationofarseniconap-typesiliconsubstratebeforegrowingap-epitaxiallayer.Afterthep-epitaxiallayerdeposition,thensidewellsareformedbyimplantationanddiffusionofthe dopantstotheburiedn-typelayer.Thisprocessformsanisolatedpocket.Unlikethestandardtrin-type buried layer F igure 1-23.Isolated p-well using special N-type buried layer process. pepitaxial layer n-well side well ~25dB Figure 1-24.IsolationcomparisonbetweenspecialN-typeburiedlayerprocessandnorma l substrate.

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38 plewellprocesswhichusesadeepn-wellwithaside-welln-well,thistypeofburiedlayerwith higherdopingconcentrationcanprovideevenbetternoiseisolation.AsshowninFigure1-24,the isolation(S21)usingburiedlayermethodimprovesby~25dBcomparedwiththatwithoutany shield. This is about 10-15 dB better than that can be achieved using the regular triple wells. Althoughisolatedp-wells(triplewellprocess)arecommonlyused,thepenaltyofhigher costisinevitableduetotherequirementofadditionalprocesses.Thishighercostmayreducethe protofintegratingthesystemintoasinglechip.So,sufcientlyimprovingtheisolationand,at the same time, keeping production costs low are important. 1.4.4 Design Consideration Inadditiontotheabove-mentionedlayout-and-process-basedoptimizationtechniques, noise-aware circuit design is also important. 1.4.4.1 Multiple down bonds AsmentionedinSection1.4.1,multipledownbondshelptoreducetheinductance betweenon-chipgroundandboardgroundsothatthenoisecouplingthroughon-chipgroundcan be reduced. 1.4.4.2 Separating the supply and ground line between the noisy and sensitive circuits Supply/groundlinesneededtoprovidethepowerforlargenumberofcircuitsarelong. TheselonglinesarenotperfectlyACgroundedathighfrequencies.Noisecantravelfromanalog todigitalcircuitblocksthroughtheselines,soseparatingtheselineandisolatingtheblocksare essential. 1.4.4.3 Increasing the distance between noisy and sensitive circuit blocks Inlightlydopedsubstrates,increasingthedistancebetweennoisyandsensitivecircuit blockscanefcientlyincreasetheresistanceandreducethenoisecoupling.However,inaheavily

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39 dopedsubstrate,thismethodisnoteffectivebecausetheheavilydopedsubstratecanactlikea low-resistivity metal plate to conduct the noise current. 1.4.4.4 Separating the body ties of transistors from guard rings Inordertoreducelossthroughsubstrate,thesubstrateresistanceofatransistorisdesigned tobesmallinsomeRFcircuits.Thisresistance,usually~5-15 W, increasesthepossibilityof receivingthenoise.Thenoisecancouplefromanoisesourcethroughanimperfectlygrounded bodytiewithinductanceL1anddownbondinductanceL2tothebodyofthetransistorathighfrequenciesillustratedinFigure1-25(A).Usingaseparateguardringincreasestheimpedance betweenthenoisesourceandbodynodeofthetransistoranddecreasesthenoisereceivedbythe transistor as shown in Figure1-25(B). 1.4.4.5 Floorplanning issue in RF and mixed-signal circuit design Atypicaloorplanforthemixed-signaldesignhasbeendiscussedbyRaminderpalSingh[Sin99](Figure1-26).Thebasicstrategyistokeepawayhighpowergenerationcircuitssuchas digitaloutputbuffersandprotectloweramplitudeanalogcircuitssuchasLNAsandmixers.This Body tie Noise source Poly Drain/source of the transistor Separated body tie L1L2 Guard ring (A) (B) Figure 1-25.Body tie structures.(A)Animperfectlygroundedbodytie.(B)Aseparatethe body tie. and guard ring

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40 strategycanbeachievedbylayoutarrangement,however,it’sstillhardtoquantifythenoise reduction.Formoredetailedapproach,asubstratemodelingtoolmustbeusedtoprovideasystemlevelsimulation.Thesystemlevelsimulationusuallyreliesonatransistor-levelmodeling. ThetimerequiredtocompletethesimulationforahugeRFormixed-signalsystemisprohibitive. Inordertoreducethecomputationtimeandspeeduptheanalysis,lessnoisycircuitscanbe ignored.So,itisimportanttorecognizethemostvulnerablecircuitsineachRFblocksandunderstand the fundamental noise coupling mechanism and relative noise levels. 1.5 Substrate Noise Suppression Using P-Channel Mental-Oxide-Semiconductor (PMOS) Transistors Inthisresearch,anewnoisereductiontechniqueisproposed.ThistechniqueusesPMOS transistorsinisolatedn-wellstodesignRFcircuitssuchthattheeffectsofsubstratenoisecouplingcanbereduced.Figure1-27showsPMOSandNMOStransistorsundernoiseinjection.Due tothep-njunctionofn-well,PMOStransistorsinann-wellshouldsufferlessnoisecouplingthan NMOStransistorsinap-substrate.Ithasbeenreported[Ros03]thatforfrequenciesbelow 200-300MHz,isolationbetweennoise-generatingcircuitsandPMOStransistorsinan-well,and Figure 1-26.Typical oorplan for the mixed-signal design. Low amplitude analogue circuits Medium amplitude analogue circuits High amplitude analogue circuits p+ Guard Ring Low speed digital circuits High speed digital circuits Digital output buffers

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41 betweenthesamecircuitsandNMOStransistorsinap-wellinadeepn-wellareabout10dBbetterthanthatbetweenthecircuitsandNMOStransistorsoutsideadeepn-well.Thisresultimplies thepossibilityofusingpurePMOStransistordesignsinRFcircuitstoachievebetternoiseisolation. UsingPMOS-baseddesignforRFcircuitsisfeasiblefortoday’sgigahertzcommunication systemdesign.DuetotheadvancedCMOStechnology,theunitycurrentgainfrequency(fT)ofa PMOStransistorhasbeengreatlyimprovedtoovertensofgigahertz.Thismeansthatspeedisno longeraproblemforPMOStransistors.Thismeansthenoisecouplingcouldbereducedbyusing PMOS-based design. 1.6 Design Challenge of Substrate Noise Suppression Using PMOS Transistors InordertooptimizethePMOS-basedRFcircuitdesignandreducesubstratenoisecoupling,understandingthecouplingmechanismisessential.Thedifcultyhereisaccuratelypredictinghowmuchnoisecouplesthroughsubstratetothenoise-sensitivecircuits.Toachievethe goal,thesubstrate,downbond,andnoisesourcesmustbecarefullymodeled.Inasubstrate,noise owisthreedimensional.Tomodelthesubstrate,anumericalanalysismethodcanbeused(Secp-substrate n-well n+ n+ p+ p+p+n+ p+ NMOS PMOS Noise source P/N junction Substrate noise Figure 1-27.Noise coupling in NMOS and PMOS transistors.

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42 tion1.3.2).However,toacircuitdesigner,thenumericalmodelistoocomplexandmustbesimpliedtoalumpedcircuitmodel,whichmayreducetheaccuracyofthemodel.Additionally, effectsofthedown-bondinductancearealsoimportant.InRFcircuitdesign,multipledown bondsarefrequentlyused.Duetothedifferinglocationsofthedownbondsonachip,theeffectivedown-bondinductanceisdifferent.Thisresultsindifferingguardringefciency.Modeling thedistributedeffectsofdown-bondinductanceisdifcultandcomplex.Inordertostudysubstratenoisecouplingmechanism,anoisesourceisrequiredtosimulatethenoiseinjectionprocess,andquantifyinghowmuchnoiseisinjectedintoasubstrateiscritical.Thenoiseinjection processstronglydependsonthesurroundingsubstratestructure.Tocalibratethenoisesource,a simplenoisereceptormustbeusedtomeasuretheinjectednoise.However,thissimplenoise receptordiffersfromtherealcircuits,changingtheoriginalloadofthenoisesourcesuchthatthe amountofinjectednoisecanbedifferentcomparedtorealcase.Therefore,usingpropersubstrate models for simulation of different cases is important. YetanotherchallengeinthisresearchistherealizationofPMOS-basedRFcircuits.There aremanydifferentdesignconsiderationsbetweenPMOS-basedRFcircuitdesignandtraditional NMOS-basedRFcircuitdesign.Forexample,intheLNA,abond-wireinductorisusuallyused forinductivesourcedegeneration.Thishigh-Q(high-quality-factor)bond-wireinductorprovides theLNAinputpowermatchingandminimizestheLNAnoisegure[Sha97].However,inPMOS design,theinductorforsourcedegenerationmustbeconnecteddirectlytopowerinsteadof ground,whichpreventtheuseofahigh-Qbondwireinductor.Newdesignapproachestothis challengeareunderinvestigation.AnotherissueassociatedwiththePMOSdesignisthesizeof then-well.Asmallern-wellgivesbetternoiseisolationbutalsoincreasesthesubstrateresistance of the transistor, which may increase the power loss through the substrate.

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43 1.7 Overview Thisproposedresearchfocusesontheunderstandingofthenoisecouplingmechanismsin RFreceivercircuitblocks.AsapotentialsolutiontoreducenoisecouplingofRFreceivercircuit blocks using pure PMOS transistors are evaluated. TheinuenceofthesubstratenoiseonLNAswillbemeasuredandanalyzed.Thecouplingmechanismofthenoisewillbeidentied.PurePMOS-basedLNAsandmixersforBluetoothapplicationwillbebuilttodemonstratethattheirperformanceissufcient.InChapter2,the methodologyofstudyingthesubstratenoisecouplingwillbeintroduced.InChapter3,designand measuredcharacteristicswillbepresentedforPMOSLNAandmixer.Theirperformancewillbe alsocomparedtothoseofNMOSversions.FlickernoisemeasurementsofPMOSandNMOS mixersarecompared.InChapter4,theeffectsofsubstratenoisecouplinginLNAarediscussed. TheoutputspectrumandnoisegureoftheNMOSandPMOSLNAsunderdigitalnoiseinjectionarepresented.InChapter5,thenoiseof8-stagebufferusedtogeneratenoiseforinvestigatingtheimpactofswitchingnoiseinRFcircuitoperationisdiscussed.InChapter6,thenoise couplingtoLNAsarepresented.Theworkissummarizedandfuturedirectionsaresuggestedin Chapter 7.

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44 CHAPTER 2 METHODOLOGY OF STUDYING SUBSTRATE NOISE COUPLING 2.1 Introduction Themethodologyofstudyingsubstratenoisecouplinginthisresearchisdividedintotwo parts:experimentalobservationandmodeling.Theexperimentalobservationportionfocuseson theimpactofnoisecouplinginRFreceiverblocks.Toinvestigatetheimpact,ataperedbufferasa noisegenerationcircuitisbuilttoemulatetheswitchingnoisegeneratedbydigitalcircuitsas showninFigure2-1.Thistaperedbufferisfedbyaexternalsignalsuchthatthefrequencyand amplitudeoftheinjectionnoisecanbeadjusted.Theperformanceofthisbufferisdiscussedin Section2-2.Furthermore,RFreceiverblocksareusedasreceptorstoreceiveswitchingnoise fromthebuffer.TheperformanceoftheseRFblocksundernoisecouplingareinvestigated.For modeling,asubstratemodelwillbebuiltbyusinganumericalsimulationtool(SubstrateStorm) orDCmeasurementmethod.ThesemethodsarediscussedinSection2-3.Finally,acompletecircuitcombinedwiththesubstratemodelandoriginalRFblockswillbesimulatedinaSPICE-like simulator to understand the possible noise coupling mechanism. Tapered buffer External signal source RF Receiver blocks Substrate noise Single chip Figure 2-1.Concept of the experimental observation. 50 W Spectrum analyzer or noise gure meter

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45 2.2 Noise Generation Circuits TosimulatearealisticnoiseinjectionsituationinRFblocks,inthisresearch,a8-stage taperedbufferusingTSMC0.18m mtechnologyischosenasanoisesource,asshowninFigure 2-2.TherststageNMOSandPMOStransistorshavethewidthof0.5and1 m mwiththeminimumlengthof0.18 m m.Inthesecondstage,thesizeofbothNMOSandPMOStransistorsismultipliedby3tooptimizethetotaldelaytimeofthe8-stagebuffer.Attheoutputofthebuffer,a 4-pFcapacitorischosenastheloadofthebuffer.Apassivationopeningforcuttingtheconnection VDD4 pF Input Output VDD 1 m m 0.5 m m 3 m m 1.5 m m VDD2187 m m 1093.5 m m 1x 2x 8x Figure 2-2.8-stage tapered buffer. OUT GND GND INPUT GND VDD Figure 2-3.Layout of the buffer. passivation opening long strip-shaped buffer last stage input stage

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46 betweenthebufferoutputandtheloadcapacitorisincludedtoprovideanalternativeopen-load optionforthebuffer.ToreducetheimpactoftheVDDandgroundlinebounceathighfrequencies, a40-pFbypasscapacitorisaddedbetweentheVDDandgroundpad.Figure2-3showsthelayout ofthisbufferwhichisalongstrip-shapedstructure.Inordertoeliminatethepackageeffectssuch ascouplingbetweentheboundwiresorimperfectboardgrounding,thebufferisintentionally designedtobemeasuredonchip.Thepadshaveapitchof150 m mandcanbeusedforhighfrequency probe measurements. Theperformanceofthisbufferistestedin3workingfrequencies,13,47,and500MHz. Thesefrequenciesarechosentobesimilartothoseusedinbase-banddigitalcircuitsexceptfor 500MHz.Figure2-4showsthemeasurementsetupofthebuffer.Sine-wavesignalsat13,47,and 500MHzaregeneratedbyHPE4421Bsignalgeneratorandfedintothebufferinput.Ashunt on-chip50W resistorisincludedattheinputofthebuffertoprovideinputmatchingforthesignal.ADCprobewitha1m Foff-chipbypasscapacitorisusedtoprovidethe1.8-Vpowerforthe buffer.Theoutputpowerspectrumandthewaveformareobservedusingaspectrumanalyzeror an oscilloscope with the input impedance of 50 W . HP E4421B Buffer chip Probe Probe Spectrum analyzer or oscilloscope Figure 2-4.Buffer measurement setup. Package Input Output

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47 2.2.1 Time Domain Measurement Results Figure2-5showstheoutputtime-domainwaveformwhenthebufferisworkingat13,47, and500MHz.Atlowfrequencies,13and47MHz,thewaveformsareexpectedclosetoasquare waveexceptforsomebouncingduringthetransients.Thisisduetotheresonancebetweenthe inductanceassociatedwiththeDCprobeandtheon-chipbypasscapacitanceasshowninFigure 2-6.Theresonancefrequencyisaround500MHz.At500MHz,theshapeofoutputwaveformis worse.Thisisduetoinadequatedrivingcapabilityofthebufferat500MHz.Thelargeoutput capacitance4pFandtheparasiticcapacitanceassociatedwiththedrainnodeofthelast-stage PMOS and NMOS transistors as well as 50W load slow the pull-up and pull-down process. (A) 13MHz (B) 47MHz (C) 500MHzFigure 2-5.Time-domainoutputwaveformsofthebufferwhenthebufferis working at (A) 13MHz (B) 47MHz (C) 500MHz 3.0e-085.0e-087.0e-08 Time (sec) -0.4 -0.2 0.0 0.2 0.4 0.6Amplitude (v) 3.6e-08 3.8e-084.0e-084.2e-08 Time (sec) -0.4 -0.2 0.0 0.2 0.4 0.6Amplitude (v) 1.0e-081.1e-072.1e-07 Time (sec) -0.4 -0.2 0.0 0.2 0.4 0.6Amplitude (v) 2.2e-079.0e-08 Bouncing

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48 2.2.2 Frequency Domain Measurement Results Figure2-7showsthefrequencydomainmeasurementresultofthebufferworkingat13, 47,and500MHz.Thespectraaremeasuredonlyaround1.7to2.7GHzforallthreeinputworkingfrequencies.Inthisfrequencyrange,onlythehigherharmonicsofthebuffer’sworkingfrequencyappears.Thepoweroftheseharmonicsishigherwhenthebuffer’sworkingfrequencyis higher.ThiscanbeunderstoodusingtheFourierseries.IntheFourierseries,thecoefcientof high-order harmonics is smaller than that of low-order harmonics. Inordertounderstandhowmuchwhitenoisegeneratedbythebuffer,thenoiseoorof bufferoutputat2.3222GHzismeasuredasshowninFigure2-8.Thenoiseoorismeasuredwith aspectrumanalyzerwithinaverynarrowbandwidtharound100KHzfrom2.32215to2.32225 GHz.Therangeischosentoavoidalltheharmonicsofbuffer’sworkingfrequency.Inthismeasurement,anamplierwithgainof30dBandnoisegureof4dBisaddedafterthebufferto amplifytheoutputsignals.Themeasurementresultsshowthatasthebuffer’sworkingfrequency increases, the noise oor actually decreases. input VDD 40 pF 1 m F ~3 nH Figure 2-6.Bypasscapacitorinserieswiththeinductoronthepowersupplylinecauses power line bouncing. 4 pF output

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49 (A) 13MHz (B) 47MHz (C) 500MHz Figure 2-7.Frequencydomainmeasurementresultsofthebufferwhenthe buffer is working at (A) 13, (B) 47, and (C) 500 MHz 1.71.92.12.32.52.7Frequency (GHz) -120.0 -100.0 -80.0 -60.0 -40.0 -20.0dBm 1.71.92.12.32.52.7Frequency (GHz) -120.0 -100.0 -80.0 -60.0 -40.0 -20.0dBm 1.71.92.12.32.52.7Frequency (GHz) -120.0 -100.0 -80.0 -60.0 -40.0 -20.0dBm

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50 ThesamebehaviorcanbeseenwhenthenoisecouplestotheLNAoutputandwillbediscussed later in section 4.3. 2.3 SubstrateStorm and DC Measurements for Substrate Modeling 2.3.1 SubstrateStorm Substratecouplingisacomplex3-dimensionproblem.Noisecantravelnearthesurfaceof thesubstrateordeepintothesubstrate.AsdiscussedinSection1.3.1,fordifferentsubstrates,the resistancebetweentwopointscanbedifferent,eventhroughthesetwopointshaveequalseparation.Tohandlethis,SubstrateStorm,anumericalsimulator,isusedinthisresearch.SubstrateStormcanconstructasubstratemodelbasedonalayoutextractionlegeneratedbyDIVAlayout extractiontoolsandasubstratedopingproleprovidedbyafoundry.Figure2-9showsthesimulationowdiagramoftheSubstrateStorm.Aftersimulation,acomplexsubstratemodelisgenerated,usuallyahugemeshincludingresistorsandcapacitors.Thismeshnetworkcanbereducedto asimpliedsubstratemodelusinganRCreductiontechnique[Ker96].Figure2-10showsan exampleofthissimpliedsubstratemodel.Themodelconsistsof5substrateportsandonesub2.322152.32225 Frequency(GHz) -120.0 -110.0 -100.0 -90.0 -80.0 -70.0dBm 13M 47M 500M Figure 2-8.Theoutputnoiseoorofbufferatthefrequencyaround2.3222GHzwhenthe buffer is working at 13, 47, and 500 MHz.

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51 stratenetwork.PortsAtoDrepresentthenoiseinjectionorthenoise-sensitivenodesofthe devicesorwholecircuits.Thesenodescanbethedrain/sourceofNMOSorPMOStransistors, bodyties,andguardrings.PortEistheback-sidecontactofthesubstrate.Thisnodecanbe oatedorgrounded.Inthesubstratemodel,theelectricalcharacteristicofthesubstrateis describedbyaresistor/capacitornetwork.Theinterfacebetweenn-wellandp-substratecanbe modeledasajunctioncapacitorasshowninFigure2-11.Withinthesamewell,theresistorscould beusedtoformaresistornetwork.TheformatofoutputmodelleiscomposedofSPICE-like circuitdescription.ThismodellecanbelinkedtotheCadencecircuitsimulatorforpost-layout simulation. Topreparethesubstratedopingproleles,atoolcalledSubstrateStormTCTisused. SubstrateStormdividesthewholesubstrateintoseveraldifferentregions.Theseregionsareseparatedbyp-njunctionsasshowninFigure2-12.Inthesameregions,thesubstrateiseitherp-type Layout extraction le Substrate prole le Complex substrate model Simplied model RC reduction SubstrateStorm simulator Figure 2-9.A simulation ow diagram of the SubstrateStorm.

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52 orn-typedoping.Regionscanben-well,triplewellorp-substrate.P-substrateisnormallydened asthedefaultregion.Inaregion,cross-sectionisalsodenedtospecifytheverticaldopingprole P-substrate N-well n+n+p+p+p+n+ Substrate model generated by SubstrateStorm A B C D E ABC D E NMOS p+ contact n+ contact Figure 2-10. Substrate model.(A) Substrate ports. (B) A substrate network. PMOS (A) (B) n+n+p+p+p+n+ NMOS p+ contact n+ contact G N-well A BC D F P-substrate E Figure 2-11. Resistor and capacitor networks. Junction capacitor PMOS

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53 foreachsubstrateport.Cross-sectionsaredifferentindifferentregions.Insameregions,the cross-sections can be re-used for different ports with the same structures. Inthesubstratedopingprolele,thediscretizatonofsubstrateinverticaldirectionis required.Discretizationdividestheverticalsubstrateproleintoseveralsubdivisions.Moresubdivisionsimplybettermodelaccuracy.However,thecomputationaltimepenaltyisusuallysignificant.SubstrateStormTCTalsospeciesthecriticaldepthofthesubstrate,suchasthejunction between the n-well and p-substrate and the back-side depth. Inthisresearch,layoutisextractedusingDIVAlayoutextractiontoolavailableinthe Cadencedesignenvironment.Toperformextraction,aDIVAextractionruleleisneeded.They includetheidenticationsofthesubstrateports,regions,andcross-sections.Associatedwith theseidentications,eachsubstrateporthasitsowncross-sectiondenition.Theseidentications n+n+p+p+p+n+ NMOS p+ contact n+ contact n-well A B C DF P-substrate E PMOS Region 1 (Region 2) P-substrate Region 2 CS-ACS-B CS-C Region boundary Cross-section Figure 2-12. Conceptualization of regions and cross-sections chip backside (Region 2) (Region 1)

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54 arestoredintwolayerscalledSCRandSCAP.SCRrepresentstheregionofthen-wellandSCAP representsthesubstrateports.Bothofthesenewlayersareextractedandrecordedinthelayout extraction les to be used for SubstrateStorm. 2.3.2 An Example of the Layout Extraction and Simulation ToverifytheSubstrateStorm,asimpleteststructureasshowninFigure2-13isdesigned. Thisstructureconsisttwop+regionswithalengthof1000 m mandawidthof1 m m,separatedby adistanceD.Theresistivityofthesubstrateisassumedas8 W -cmandthethicknessofthesubstrateis1cm.ByfollowingthesimulationowinFigure2-9,theresistancesbetweentwop+regionsfordifferentdistancesDarecomputedandplottedinFigure2-14.Inthesamegure,the theoretical results calculated by Equation (2.1) [Joh75] are also plotted. (2.1) where r istheresistivityofthesubstrate.Whencomparingthesimulatedandtheoreticalresistancecurves,bothshapesarefoundtobesimilar,butthesimulatedresistancesareconstantly higherthantheoreticalvalues.ThismeanstheresistancedifferenceforanytwodifferentseparaD W=1 m m L=1000 m m Figure 2-13.A simple test structure of two p+ implant regions with separated distance D. port1 port2 R sub 2 r D 2W -------D 2W -------2 1 – + ln p L -------------------------------------------------------------------=

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55 tionsissimilarforsimulatedandtheoreticalresults.However,theresistancevalueofthesimulatedresultishigherthanthatoftheoreticalresult.Thisdiscrepancyshouldbefurtherinvestigated by an experimental study. 2.3.3 Substrate Model Extraction Using DC Measurement Analternativewaytobuildasubstratemodelistodirectlymeasuretheresistancenetwork betweenoneportandanotherportusingarealsubstrate.Figure2-15(A)showstheconcept [Col98].Nodes1to4arethesubstrateportsinthesubstrateasshowninFigure2-15(A)(B).In ordertomeasuretheresistorvaluebetweenport1and2,avoltagesourceisconnectedtonode1 andanammeterisconnectedtonode2.Duringthemeasurement,allothernodesareconnectedto thegroundasshowninFigure2-15(B).Assumingtheresistanceoftheammeterissufciently smallsothatthevoltageacrosstheammetercanbeneglected,allthecurrentowingthroughR1,2ismeasuredbytheammeter.ThevalueoftheR1,2canbecalculatedbythevoltagereadfromthe voltagemeterdividedbythecurrentreadfromtheammeter.Theaccuracyofthismeasurement mainlydependsontheseriesresistanceRainthecurrentmeterandtheresolutionoftheammeter. 0.020.040.060.080.0100.0 D ( m m) 100.0 200.0 300.0 400.0Resistance ( W ) Simulation results Theoretical results Figure 2-14.Comparison between the simulated and theoretical results.

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56 Toreduceseriesresistanceintheammeter,highcurrentmeasurementmodeshouldbeselected. However,inthismode,thecapabilityofmeasuringtheminimumcurrentislimited.Thislimits theammeter’sabilitytomeasureabigresistance.Inthiswork,Agilent34401Aisused.Themaximumresistancethatcanbemeasuredis0.4M W withthesupplyvoltageof2volt.Tomeasurethe resistancenetwork,anewteststructuremodiedfromtheoriginallayoutisrequired.Inthistest structure,allthesubstrateportsofinterestarereplacedbythep-substrateorn-wellcontacts.For example,drain/sourcenodesofNMOStransistorsonap-substratearereplacedbythep+diffu2 3 1 AR1,2R1,3 I1,2 V=0.1 V~I1,2Ra=0.1 W R1,4 4 R3,4R2,3R2,4 1 2 3 4 substrate model V A substrate(A) (B) Figure 2-15.The concept of extracting the substrate model using DC measurement.(A) The substrate model to be extracted. (B) Measurement method.

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57 sionsasshowninFigure2-16(B).Thesubstrateportsinthen-wellarereplacedbyn+diffusions (Figure2-16(C)(A)(C)).Finally,thesetwonetworksarecombinedtogetherandconnectedbyan n-well junction capacitor as shown in Figure 2-11. 2.4 Summary Inthischapter,ataperedbufferfornoisegenerationispresented.Time-domainwaveforms andfrequency-domainspectraofthetaperedbufferaremeasured.Inthischapter,itisestablished thatthewhiteswitchingnoisegeneratedfromthebuffer,inadditiontotheharmonics,candegrade nearbyRFcircuitperformance.SubstrateStormandDCmeasurementareintroducedforusein substratemodelextraction.Thesemodelswillbeusedinacircuitsimulationtosimulatethenoise coupling effects to RF blocks. p-substrate N well n+n+p+p+p+n+ p+ contact n+ contact polypoly p-substrate p+p+p+ p+ implant p+ (B) Test structure in p-substrate N well n+n+n+ n+ contact poly (C) Test structure in n-well p-sub n+ implant (A) Original layout Figure 2-16.Test structures for DC measurement.

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58 CHAPTER 3 LNA AND MIXER DESIGN AND MEASUREMENT RESULTS 3.1 Introduction Alownoiseamplier(LNA)andamixeraretwoimportantblocksinradiofrequency (RF)receiverdesign.Figure3-1showsthebasicRFdirectconversionreceiverarchitecture.Ina directconversionreceiver,theLNAampliesthereceivedsignalsfromtheantenna(ANT)and theband-passlter(BPF).AftertheLNA,theampliedsignalsaredeliveredtothemixerand directlydown-convertedtoDC.Inordertolowerthebit-error-rate(BER)ofthereceivedsignals, theoutputsignal-to-noiseratioshouldbeincreased.Theoutputsignal-to-noiseratioismainly determinedbythenoisegureandlinearityofareceiver.Therefore,improvingthegain,noise gureandlinearityiscriticalinreceiverdesign.Inthedirectconversionreceiver(Figure3-1), gain,noisegureandlinearityarepredominantlydeterminedbytheLNAandmixer.Therefore, optimizing both blocks is critical. LNA Divided by 2 VCO Synthesizer Demod. Figure 3-1.Direct conversion receiver architecture ANT BPF Mixer LPF

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59 Inthiswork,asimple2.4-GHzRFreceiverstructure[Blu]ischosentosimplifythecomplexityofthenoiseinvestigation.TheLNAandmixerblocksareintendedforBluetoothreceivers. TheBluetoothreceiverisusedintheIndustrial,ScienticandMedical(ISM)radiobandbetween 2.4and2.4835GHzwithachannelspace1MHz.Therequiredbiterrorrate(BER)islessthan 0.1%.ThesensitivityoftheBluetoothRFreceivershouldbebeloworequalto-70dBm.Both characteristicsofPMOSandNMOSLNAsandmixerswillbecomparedanddiscussedinthis chapter. 3.2 Topology and Design Consideration of P and N-Channel Metal-Oxide-Semiconductor Low Noise Amplier (PMOS and NMOS LNAs) Figure3-2showstheschematicsofboththePMOSandNMOSLNAs.BothLNAsoperateat2.4GHzandusecommonsourcetopologywithinductivesourcedegeneration.Acascode structureisutilizedtoimproveisolationandtoreducetheMillereffect.Theinputandoutput impedanceofLNAsarematchedto50 W .Theinputmatchingisformedwithanoff-chipseries inductorandashuntcapacitor.Thecircuitsarepackagedinan8-pinpackagewithanexposed paddle[Zen]aswellasusingchip-on-boardtechnology.Although,thetopologyisthesame,there aresubtledifferencesbetweentheNMOSandPMOSLNAsarisingfromthefactthatthedcbias pointforsourceoftheNMOSM1isground,whilethatforsourceofthePMOSM1isconnected toVDD.ThequalityfactoroftheinputmatchingnetworkQin(Figure3-2)issetto4totolerate processvariations[O03].InordertokeeptheQinaswellastheinputresistancelookingintogate ofM1thesameforbothNMOSandPMOSLNAs,thewidthsofNMOSandPMOStransistorsare thesameandthevalueofthePMOSLNA’ssourceinductor(LSinFigure3-2(A))issettobe abouttimesbiggerthanthatoftheNMOSLNA’ssourceinductor(LSinFigure3-2(B)).To further explain this, the total impedance Zin looking into the input of the both LNAs is: 1 2.5---------------

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60 (3.1) InordertomachtheinputimpedanceZinofthebothLNAsto50 W attheresonantfrequency ( ), theimaginarypartoftheZinmustbezeroandtherealpartoftheZin()mustbesetto50 W .Asmentionedabove,theQin(1/ w R0Cgs1)ofbothPMOSand NMOSLNAis4andtheinputresistanceR0is50 W sothatCgs1ofthebothLNAsshouldbe equal. In long channel devices, gm can be written as following: (3.2) WandLarethewidthandlengthofthetransistor. m iscarriermobility.Coxistheunit capacitanceofgateoxide.IDisdraincurrentofthetransistor.Forthecomparisonpurpose,both LNAsareworkingatthesamesupplyvoltageandcurrentandwiththesameW/Lratiosothatgm1Zinj w LgLs+ () 1 j w Cgs1----------------gm1Cgs1---------Ls++ = 1L g L s + () C g s1 g m1 C gs1 -----------L s LgVg2LdVDDLsM1M2C1C2RLOut IN input matching output matching Vg2LdVDDLsM1M2C1C2RLOut Cb2 output matching input matching Cbypass,on-chip Lg IN Cbypass,off-chip (A) PMOS LNA (B) NMOS LNA Pad Ldown_bondPad Llead Cb2Figure 3-2.The LNA circuit schematics.(A) PMOS LNA. (B) NMOS LNA. gmW L ----m CoxID=

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61 ofPMOStransistor(M1)isaroundtimessmallerthanthatoftheNMOStransistor.Thisis duetothesmallerholemobilityofPMOStransistorthantheelectronmobilityofNMOStransistor.Therefore,LsofthePMOStransistorshouldbetimesbiggerthanthatofNMOStransistorinordertosatisfythatZin()is50 W forbothPMOSandNMOSLNAattheresonant frequency . Theadditionalon-chipinductorLs,on_chipinPMOSLNAisincludedforthispurpose asshowninFigure3.3.Thetypicalvalueofadown-bondinductance(Ldown_bond)isabout0.6-0.8 nHandLs,on_chipisabout0.5nH.ThetotalinductanceusedforthesourcedegenerationinPMOS LNAis1.1-1.3nH.IntheNMOSLNA,onlyonedown-bond(Ldown_bond)isusedforthesource degeneration. IntheNMOSLNA,a50-pFoff-chipbypasscapacitor(Cbypass,off-chip)betweenthecircuit VDDandboardgroundisusedtoreducethehugeseriesinductanceduetotheDCwireLwireand bypasstheACsignaltotheboardgroundasshowninFigure3-4(A).ForthePMOSLNA,the sourcenodeofthetransistorM1isconnectedtotheVDD.IftheACsignalisbypassedfromthe sourcenodeofthetransistorM1viaaleadofthepackagetotheboardgroundthroughaoff-chip capacitor,totalsource-degenerationinductanceLSincludingtheon-chipandleadinductance(2.5 1 2.5--------------2.5 g m1 C gs1 -----------L s LgVDDLs,on_chipM1 IN Cbypass,on-chip Pad Ldown_bondinput matching Figure 3-3.Input matching of the PMOS LNA.

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62 nH)istoobig.Therefore,a20-pFon-chipbypasscapacitor(Cbypass,on-chip)isreplacedasshown inFigure3-4(B)todirectlybypassACsignaltothepackagegroundandavoidhugeleadinductance, Llead. ThephotographsofPMOSandNMOSLNAdiesandpackagesareshowninFigures3-5 and3-6.Bothlayoutsaresimilarexceptforthetransistortype,on-chipsourcedegeneration inductor,andon-chipbypasscapacitors,asdiscussed.Thedieareais1154 m mx856 m mfor Chip Package gnd (Package) (off-chip)VDD LwireCbypassLleadLbond_wire Package gnd (Package) (on-chip) VDD LwireCbypassLdown_bond LNA LNA (A) Off-chip bypass in NMOS LNA (B) On-chip bypass in PMOS LNA LleadFigure 3-4.The consideration of LNA bypass circuits.(A) NMOS LNA. (B) PMOS LNA. Circuit VDD

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63 PMOSLNA,and1300 m mx856 m mforNMOSLNA.ThepadarrangementsoftwoLNAsare similar,whichhelpstokeepthelayout-and-package-inducedparasiticcapacitancesandinductances similar (A) PMOS LNA(B) NMOS LNA Figure 3-5.The LNA die photographs.(A) PMOS LNA. (B) NMOS LNA. Figure 3-6.A packaged LNA.

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64 3.3Measurement Results of PMOS and NMOS LNAs 3.3.1 Gain of LNAs Table3-1summarizesthemeasurementresultsofPMOSandNMOSLNAs.Threesamplesaremeasuredforeachcase.Thesupplyvoltage(VDD)andcurrent(ID)are1.8Vand3mA, respectively.ThepowerconsumptionfortwoLNAsareequal.DuetothelowerfTofPMOStransistors,thePMOSLNAexhibits~16dBtransducerpowergain,whichis~3dBlowerthanthe NMOSLNAgain.Thedifferencecanbeexplainedindetailbysolvingthegainexpressionofthe bothLNAs.FortheNMOSLNAwithinductivesourcedegeneration(Figure3-7),thevoltage gain Av can be derived as follows: [Flo01] (3.3) PMOS LNANMOS LNA Sample #IIIIIIIIIIII f0(GHz)2.342.402.322.382.22.20 VDD/ID(mA)1.8/31.8/3 NF(dB)3.653.653.302.672.242.25 GT(dB)15.51617.218.518.918.5 S11(dB)-11.3-15.5-10.5-13-13.2-16 S22(dB)-13.5-10-10.5-16-17.5-20 S12(dB)-23-21.5-24.7-31-29.8-32.7 IIP3(dBm)1.4-2.67-1-6.75-9-9.17 IP1dB(dBm)-19.2-20-22.4-24.4-26.6-26.4 Table 3-1.Performance of PMOS versus NMOS LNAs. A v ww o = V gs1 V S ------------V d1 V gs1 ------------V d2 V d1 ---------V Out V d2 ------------= 1 2 -Q in g m1 dw o () Q Ld w o L d () q w () =

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65 where (3.4) and .(3.5) woistheLNAworkingfrequency.QinistheeffectiveinputqualityfactoroftheLNAwithout includingRs(Figure3-7).gm1andgm2arethetransconductancesofM1andM2.QLdisthequality factoroftheloadinductorLd.Cd1isthetotalcapacitanceinthedrainnodeofthetransistorM1. C1andC2arethecapacitorsusedfortheoutputmatchingnetwork.RListheloadresistance.In thePMOSandNMOSLNAdesigns,themajordifference(3.3)isthetransconductance,gm1and gm2.Toevaluate(3.3), d ( w )mustbesolvedrst.Fromthesimulation,Cd1andgm2oftheNMOS LNAisaround400fFand38mS,respectively.Therefore,in(3.4), w Cd1isaround6mSandthe absolutevalueof d ( w )is~0.99.Thetransconductancegm2ofthePMOSLNAisabout smallerthanthatoftheNMOSLNA.ThecapacitanceCd1ofthePMOSLNAisabout1.3 dw () g m2 g m2 j w C d1 + ---------------------------------= q w () j w C 2 R L 1j w C 1 C + 2 () R L + ------------------------------------------------R L Q Ld w o L d ---------------------------------== Vg2LdLsM1M2C1C2RLOut output matching input matching Lg RsVsFigure 3-7.A simplied schematic of the source degeneration NMOS LNA. 1 2.5---------------

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66 biggerthanthatoftheNOMSLNAduetoslightlyhigherdrainvoltageofthePMOStransistor M1.Hence,theabsolutevalueof d ( w )ofthePMOStransistorisaround~0.94.Thevalueof d ( w ) forbothPMOSandNMOSisslightlydifferentbutthedifferenceissmallsothatitcanbe neglected.Theonlymajordifferenceleftin(3.3)isgm1.Asmentionedabove,gm1ofthePMOS transistorisaroundtimessmallerthanthatoftheNMOStransistorduetothelowerhole mobility m inthePMOStransistor.Therefore,theabsolutevoltagegainAv(3.3)ofthePMOS LNAistimessmallerthanthatoftheNMOSLNAatresonancefrequency w0.Toevaluate thedifferenceinthepowergain(GT),loadandsourceresistance(RSandRL)ofbothLNAsmust be considered. The forward transducer gain of a LNA can be written as follows: [Gon97] (3.6) Inthisdesign,RsandRLareequalto50 W sothatGTbecomes.Therefore,theratioofthe PMOSLNAtransducergainGTpdividedbytheNMOSLNAtransducergainGTncanbewritten as (3.7) wheregmpandgmnarethetransconductancesofM1ofthePMOSandNMOSLNA.Therefore, GTofthePMOSLNAisfoundtobearoundtimesofthatoftheNMOSLNA.InTable3-1, themeasuredGTofthePMOSLNAisaroundtimesofthatoftheNMOSLNA.Thedifferenceisabout1dBsmallerthanthecalculatedvaluein(3.7).ThisisduetorelativelyhigherQinfor PMOS LNA than that for NMOS LNA in the real samples. 1 2.5--------------1 2.5--------------GTPLoadPAVS--------------S21 24 VOutVS------------2RSRL-----4Av 2RSRL-----==== 4Av 2 G Tp G Tn ----------A Vp 2 A Vn 2 ----------------g mp 2 g mn 2 ------------1 2.5 ------= = 1 2.5--------------1 2---------

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67 3.3.2 Noise Figure of LNAs InpreparationforcomparisonofthenoiseguresofPMOSandNMOSLNAs,thefundamentalnoisetheoryisreviewed.Figure3-8showsasmall-signalnoisemodelofanLNAwith inductivesourcedegeneration.Inthemodel,thenoisesourcesofthecascodeM2transistorand theoutputmatchingnetwork(Figure3-2)areneglectedduetotherelativelysmallnoisecontribution.OnlythenoisesourcesintheinputmatchingnetworkingandM1transistoraretakeninto accountinthenoiseanalysis.Thesenoisesourcesarethethermalchannelnoiseandthegate noisecurrentinducedbytheuctuationsinthetransistorchannelcharge[Zie86].Thenoise factor (F) is [Sha97] (3.8) where ,(3.9) i d 2 i g 2 F1 g a --c Qin-------w0wT-----+ = Ls Rs gmvgs+ vgsCgsi out 2 i d 2 v s 2 i g 2 Figure 3-8.Small-signalnoisemodelofanLNAwithinductivesourcedegeneration. a gmgd0--------

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68 .(3.10) g isthecoefcientofchannelthermalnoise,QinistheeffectiveinputqualityfactoroftheLNA withoutRS, w0istheLNA’sworkingfrequencyaswellastheresonantfrequencyoftheLNA’s inputmatchingnetwork, d isthecoefcientofthegatenoise,cisthecorrelationcoefcient betweenthegatenoiseanddrainnoise, a istheratioofdevicetransconductancegmandzero-bias drainconductancegd0,and wTistheunitcurrentgainofthetransistor.Asmentioned,inthis design,Qinissettobe4forbothPMOSandNMOSLNAs.Assumingthatc, a ,and g aresimilar forthebothLNAs, c (3.10)isalsosimilarforthebothLNAs.Accordingtotheabovediscussion and assumption, the ratio of PMOS and NMOS LNAs’ noise factors is related to (3.11) ThemeasuredaveragenoisegureofthePMOSandNMOSLNAsinTable3-1isaround 3.52dBand2.38dB,respectively.Therefore,themeasuredratioin(3.11)isapproximately1.7 whichishigherthanthecalculatedvalue1.58.Thereasoncanbeduetothedifferencesofc, a , and g on the PMOS and NMOS transistors. 3.3.3 Isolation and Linearity of LNAs FromtheTable3-1,theisolationofPMOSLNAisworsebyaround8dBcomparing totheNMOSLNA.IIP3ofthePMOSLNAisabout6-8dBhigherthanthatoftheNMOSLNA. Afterfactoringoutthegaindifference,itisstill3-5dBhigher,whichisduetothehighervoltage headroom(VGS-VT)ofthetransistorM1ofthePMOSLNA.Undertheparticularsetofbiasconditionsforthecomparison,VGS-VTofthetransistorM1ofthePMOSLNAis0.15V,whilethat c fQin() 1 =2cQinda 2 5 g --------da 2 5 g ---------1Qin+ () ++ = F p 1 – F n 1 – --------------1 w Tn ---------1 w Tp -------------------g mp g mn ---------2.51.58 ~ = S12

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69 oftheNMOSLNAisonly0.05V.Regardlessofthedifferencesabove,themeasuredperformances of both LNAs are acceptable for Bluetooth applications. 3.4 Topology and Design Consideration of PMOS and NMOS Mixers Figure3-9showstheschematicsoftheMOSdownconversionmixers.ThemixersareGilbertcelldoublebalancedactivetype.Intermediatefrequency(IF)ofthemixersischosentobe20 MHzandRFis2.4GHz.Bothmixershaveanidenticalstructureexceptforthefactthatallthe NMOStransistorsarereplacedbythePMOStransistors.Theinputsofthemixersarematchedto 50 W withoff-chipinductorsandcapacitors.Theoutputloadofthemixersisanoff-chiptransformer,whichtransformstheoutputloadofmixertoa50W resistor.ForthePMOSmixer,the transformratiois16:1andthatfortheNMOSmixeris8:1.TheM2gateisconnectedtoasignal generatorthroughabiasteeandthematchingnetwork,whileM3gateisACgroundedthrougha (A) PMOS mixer (B) NMOS mixer M7M2M3L2R L1M5M4M6Lo+ IN OUT VDD M1 Lo+ LoVDDM4M5M6M7OUT CbCbM3M2R L1L2M1VbVb IN Lo+ LoLo+ Figure 3-9.Circuit schematics of mixers.(A) PMOS and (B) NMOS mixer.

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70 40-pFbypasscapacitor[Li01].A50W shuntresistorisusedtoprovide50W inputmatchingfor theswitchingtransistors(M4-M7).TheLOpoweris1.33dBmwhichgeneratesa0.74-Vp-psine waveattheinputofLOtransistors.Chipsarewirebondedinthesamepackagesandtestedonthe samePCboardasthatusedfortheLNAs.Figure3-10showsthediephotographsofmixersand Figure 3-11 show the packaged mixers. The die area is 1446 m m x 720 m m. (A) PMOS mixer (B) NMOS mixer Figure 3-10.The die photographs of mixers.(A) PMOS and (B) NMOS mixer. Figure 3-11.A packaged mixer.

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71 3.5 Measurement Setup and Results of PMOS and NMOS Mixers 3.5.1 Measurement Setup Figure3-12showsthemeasurementsetupforPMOSmixer.Thesamesetupisalsoused fortheNMOSmixermeasurement.Inthesetup,thetwosignalgeneratorsprovidethe2.4-and 2.38-GHzsignalsattheRFandLOpinsofthemixer.Abalunisusedtoconvertsingle-endedsignalfromthesignalgeneratortothedifferentialLOsignal.Anoff-chiptransformerisusedasthe loadofthemixertotransferdifferentialsignaltosingle-endedsignal.AnHP8563Espectrumanalyzer is used to measure the down-converted output signal of the mixer at 20 MHz. 3.5.2 Measurement Results 3.5.2.1 Conversion gain measurements ThemeasurementresultsofmixersaresummarizedinTable3-2.Onceagain,threesamplesaremeasured.VDDandbiascurrentare1.8Vand16mA,respectively.ThePMOSmixers IF+ IFRF LO+ VDDM1M2M3LOLO+ 50 W HP8563E Spectrum analyzer (20MHz) Signal (2.4GHz) generator VSSVb Signal (2.38GHz) Balun generator Off-chip transformer Figure 3-12.The measurement setup for PMOS mixer.

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72 have~6dBconversiongainwhichi s~3dBlower thanthatoftheNMOSmixers.Partially,this isduetothelowerfTofthePMOSRFtransistors.Inordertoquantitativelyexplainthedifference, a general conversion gain expression of a single-balanced mixer (Figure 3-13) is (3.12) wheregmisthetransconductanceoftheM1(Figure3-12)andcisaconstantnumberwhich dependsontheswitchingefciencyofLOtransistors(M2,M3)[Ter99].Foridealswitching (square wave), c approaches 2/ p . The conversion voltage gain is*LO power level: +1.33dBmPMOS MixerNMOS Mixer Sample #IIIIIIIIIIII RF(GHz)/ IF(MHz) 2.4/202.4/20 VDD(V)/ID(mA)1.8/161.8/16 Output transformer ratio 16:18:1 Input matching(dB) <-10<-10 Conversion Gain(dB) 6.55.845.679.33109 DSB NF(dB)7.638.087.728.537.9410.32 IIP3(dBm)2.92.131.331-3.90.5 IP1dB(dBm)-16-12-13.5-14-17-11 LO-IF isolation(dB) 3332.534.543.238.538 RF-IF iisolation(dB) 11.613.51214.28.3311.8 Table 3-2. Performance of PMOS versus NMOS mixers. g c cg m =

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73 ,(3.13) whereQinistheeffectiveinputqualityfactorofthemixerwithoutincludingRS,andZListhe equivalent output impedance of the mixer. The conversion transducer power gain is ,(3.14) whereVSisthesourcevoltage,andRsisthesourceimpedance.Therefore,theconversiongain ratio of the PMOS mixer (GTp) and NMOS mixer (GTn) is (3.15) AsdiscussedinSection3.3.1,withthesamecurrentowingthroughPMOSandNMOS transistor,theratioofgmpandgmnis~.Assumingthatoutputimpedanceratio isapproximatelyequalto2duetohighertransformerratioforPMOSmixer. A v Q in g c Z L cQ in g m Z L == LSLO+ M1 LOVB RSVSLSLDLD+ VOVDDFigure 3-13.A single-balanced mixer. M2M3 G T P out P avs ----------V S 2 --------Q in g c 2 Z L V S 2 --------2 R s -----------------------------------------------A V 2 R S Z L ---------=== G Tp G Tn ----------g cp 2 Z Lp g cn 2 Z Ln --------------------------c p 2 g mp 2 Z Lp c n 2 g mn 2 Z Ln --------------------------------------= 12.5 ( ) Z Lp Z Ln

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74 Therefore,GTp/GTncanbere-writtenas,whichimpliesthatthedifferenceontheconversiongainisduetothedifferenceonswitchingefciencyoftheLOtransistor. Fromthemeasurementresult,GTp/GTnisaround0.5(~3dB).Therefore,cp/cnis~0.79.This resultindicatesthatNMOSmixerhasbetterswitchingefciencythanPMOSmixersuchthatconversiongainofNMOSmixerishigh.Despitethelowerconversiongain,thePMOSmixerstill satises the Bluetooth application. 3.5.2.2 Noise gure measurement InTable3-2,thenoiseguresofPMOSmixersarefoundtobecomparableorslightlybetterthanthoseofNMOSmixers.Figure3-14showsthemeasurednoisegureandgainofPMOS andNMOSmixersforthevaryingLOinputpower.Thenoiseguresofbothmixersdecreaseas theLOpowerincreases,whichisduetotheincreasedconversiongainofthemixersatthehigher LOpower.OncetheLOpowerishigherthan0.5dBm,noisegureofthePMOSmixerisconsistentlyfoundtobelowerthanthatoftheNMOSmixer,whichimpliesthatthenoisegeneratedby thePMOStransistorsissmallerthanthatgeneratedbytheNMOStransistors.WhentheLO c p c n () 2 12.5 () 2 () -10-50510 LO power (dBm) -5 0 5 10 15 20Gain & NF (dB) Gain of NMOS mixer NF of NMOS mixer Gain of PMOS mixer NF of PMOS mixer Figure 3-14.Measured noise gure and gain at varying LO power levels.

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75 powerishigherthan7.5dBm,theconversiongainofthebothmixersdrops.However,thenoise gurealmoststaysthesameorjustslightlydrops.AtthehigherLOpower,theswitchingtransistors(M4-M7inFigure3-9)canpartiallyworkinthelinearregioninsteadofthesaturationregion whichdecreasestheloadimpedance.Thedecreasedloadimpedancelowerstheconversiongain of the mixers, however, it has almost no inuence on the noise gure. 3.5.2.3 IP1dB and IIP3 measurements IP1dBforbothmixerarecomparableasshowninTable3-2.IIP3ofPMOSmixeris~1dB higherthanthatofNMOSmixer.Despitesomedifferences,performanceofthesePMOSand NMOS mixer are acceptable for Bluetooth applications. 3.6 Flicker Noise Measurements ForRFSoCdesign,adirectconversionreceiverarchitectureisfrequentlyusedtominimizethenumberofoff-chipcomponents.However,amajorissueis1/fnoise.Toreducethe impact,a900-MHzmixerutilizingmostlyPMOStransistorsofa0.35m mCMOSprocesswith lower1/fnoisehasbeenproposed[Man01].Previousworkshavealsoshown[Hun00,Par01]that PMOStransistorswithpureSiO2gatedielectriclayersina0.25m mCMOSprocesshavelower1/ fnoisethanNMOStransistors.Inthissection,1/fnoiseofmixersusing0.18m mPMOSand NMOStransistorswithpureSiO2gatedielectriclayersarecomparedatthefrequencyrangefrom 100to100kHzunderswitchingandnon-switchingconditions.Tomeasureattheselowfrequencies,theoff-chiptransformerforbothmixerswasreplacedwitha220W resistor.ThemeasurementsetupisshowninFigure3-15.Apre-amplierisdirectlyconnectedtothedifferentialload ofmixerandfollowedbyanHPDynamicSignalAnalyzertomeasuretheoutputdifferentialvoltageamplitude.TheRFinputportisterminatedwitha50W resistor.AsignalgeneratorisconnectedtotheLOinputporttoapplya2.38-GHzsinewave.Abalunandacouplerareusedto

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76 convertthesingle-endedsignaltodifferentialsignalandisolatelowfrequencypowerlinenoise. DifferentVSSofthePMOSmixersandVDDoftheNMOSmixersarechosentokeepthesame DCbiasvoltageandcurrentinthecircuitsasthoseinthenormaloperationdiscussedinSection 3.5.1. Figure3-16showsthemeasuredresults.WhentheLOtransistorsarenotswitching (switchingoff),thePMOSmixerhasabout10dBlower1/fnoisethanthatoftheNMOSmixers. ThisissimilartotheresultsobservedincomparingonlyPMOSandNMOStransistors.Whenthe LOtransistorsareswitching,bothmixersshow5-9dBreductionof1/fnoisedependentonfrequency.Thepossiblereasonsarethattheswitchingre-distributesthenoisepoweraroundDCand themultiplesofswitchingfrequency[Gie99]anddisruptsthetrappingandde-trappingprocessin semiconductor-oxideinterfacewithlongtimeconstants[Blo99]neededfor1/fnoisegeneration. IF+ IFRF LO+ VDDM1M2M3 LOLO+ 50 W 220 W 220 W Preamp. HP3561A Signal 100-100KHz Signal 2.38GHz Balun generator VSSDynamic Analyzer Vb Figure 3-15.Flicker noise measurement setup. Coupler

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77 Accordingtothe1/fnoisemeasurements,PMOSmixersarebetterthanNMOSmixersinadirect conversion RF receiver. 3.7 Summary 2.4-GHzNMOSandPMOSLNAsandmixersarefabricatedina0.18m mfoundryCMOS process.MeasurementsatthesamepowerconsumptionshowthatPMOSLNAshave~3dBlower gainand~1dBhighernoisegurethantheNMOSLNAs,whilePMOSmixershavealso~3dB lowergainthanNMOSmixersandhavecomparableorslightlylowernoisegurethanNMOS mixers.TheIIP3ofPMOSLNAsisbetterand1/fnoiseofPMOSmixersislower.IIP3ofPMOS mixeris~1dBhigherthanthatofNMOSmixer.Moreimportantly,thecharacteristicsofthese PMOSLNAsandmixersaresuitableforBluetoothapplications,indicatingthefeasibilityofusing PMOStransistorsforRFapplicationstopotentiallyimprovenoiseisolationwithoutaddingany process modications and cost. 102 103 104 105 10-18 10-17 10-16 10-15 10-14 10-13 10-12 Freq.(Hz) Output Noise PSD (dBm/Hz)switching on switching off switching on switching off PMOS mixer NMOS mixer Figure 3-16.Flicker noise measurement results.

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78 CHAPTER 4 EFFECTS OF THE NOISE COUPLING ON LNAS 4.1 Introduction Thisnoisegeneratedfromtheadjacentdigitalcircuitscanbecategorizedintotwoparts: unwantedspursandwhitenoise.Whendigitalcircuitsareswitching,periodicswitchingsignals aregenerated.Theseperiodicswitchingsignalsincludenotonlythesignalatthefundamental workingfrequencybutalsoharmonics,thesignalsatintegermultiplesofthefundamentalfrequency.TheseharmonicsarecoupledthroughsubstratetotheLNAtobecomeunwantedspursin theLNAoutputspectrum.Thewhitenoisecomesfromthetransistorsofnearbydigitalcircuits. Usually,thespurscanbeavoidedbyproperlychoosingtheworkingfrequencyofdigitalcircuits sothatitsharmonicsdonotfallinthebandofinterest.However,thismethodcannotbeusedfor avoidingwhitenoise.CoupledwhitenoiseappearsattheworkingfrequencyoftheLNAand degradestheLNA’ssignal-to-noiseratio.Theonlywaytoreducecoupledwhitenoiseareincreasingisolationofcircuitandreducingthenoisegeneratedfromdigitalcircuits.Thus,whitenoiseis more problematic than spurs in substrate noise coupling. Inthischapter,deterministicandindeterministicnoiseinPMOSandNMOSLNAarediscussed.ParticularlynoiseguresandoutputspectraofLNAsundernoiseinjectionareinvestigated.ThePMOSandNMOSLNAstestedandreportedinChapter3areused.Thetaperedbuffer discussedinChapter2areutilizedasthedigitalcircuitnoisegenerator.Finally,theinuenceof shared and separated grounds between LNAs and buffer on noise performances are investigated. 4.2 Measurement Setup Twoteststructures,featuringPMOSandNMOSLNA’sandtaperedbuffersonasingle chip,arefabricated.Intheseteststructures,buffersareplacedrightundertheLNAcircuitsas

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79 showninFigure4-1.TheminimumdistancebetweenthebufferswitchingtransistorstotheLNA transistorsisabout300 m m.Ahugesubstrate-connectionareaisincludedbetweenthebufferand LNA.Thissubstrate-connectionareaisconnectedtotheon-chipgroundsuchthatbuffer-to-LNA noisecouplingcanbereduced.TheLNAispackagedsothattheeffectsonthecommonground inductanceasdiscussedinChapter1.4.1canbeinvestigated.Additionally,thebufferisintentionallydesignedforon-chipprobingonly,inordertoavoidanycouplingthroughthebondwiresor package.Tounderstandtheeffectofsharedon-chipgroundbetweentheLNAandbuffer,theLNA groundisdirectlyconnectedtothebuffergroundthroughthetopmetallayer.Thisgroundconnectioncanbecutthroughapassivationopeningsuchthattheeffectofseparatedgroundbetween LNA and buffer can be investigated. TwosetupsareusedforthenoisecouplingmeasurementsasshowninFigure4-2(A)and (B).Insetup(A),asignalgeneratorisusedtogeneratethesignalsat13,47and500MHzfor buffers.Thesesignalsarefedintothebufferinputbydirectlylandingaprobeonthewaferto avoidanypackageinducedcoupling.OnthesamesideastheLNA,anoiseguremeterisusedto NMOS LNATapered Buffer Substrate connection OUT IN OUT IN Figure 4-1.PMOS and NMOS LNA test chips IN OUT Tapered Buffer Substrate connection OUT INPMOS LNA Passivation opening Transistors

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80 measurethenoisegureofLNAsundernoise-injectionandno-noise-injectionconditions.The frequencyrangeofthisnoiseguremeterissetbetween1.7and2.7GHz.Thefrequencystepis 10MHz.Insetup(B),aspectrumanalyzerisusedtomeasuretheoutputspectrumoftheLNAs. During the measurements, input port of LNA is terminated with a 50W resistor. 4.3 Noise Figure Measurement Results ThenoiseguresofNMOSandPMOSLNAaremeasuredwhenthebufferisworkingat 13MHzasshowninFigure4-3.Thinandthicksolidlinesshowthegainandnoiseguresofthe LNAsunderno-noise-injectioncondition(bufferisoff)andnoise-injectioncondition(bufferis on),respectively.Incomparingthetwoconditions,noiseguresarefoundtochangedramatically whentheLNAisundernoise-injectioncondition.Thisincreaseofnoiseoccursnotonlyateach harmonicfrequency(spurfrequency)butalsoatthefrequenciesbetweenanytwoharmonics(dip frequencies).Thisresultindicatesthatcouplednoiseisderivedfromnotonlyharmonicsbutalso LNATapered Buffer Noise Test chip (HP8970B) Noise Figure Meter LNATapered Buffer Packaged LNA Freq. step = 10MHz Freq. resoluiton=1MHz LNATapered Buffer Noise Test chip (HP8563E) Spectrum Analyzer 50W Figure 4-2.Types of measurement setups.(A)Noiseguremeasurementsetup.(B)Output spectrum measurement setup. (A) (B)INOUT IN OUT Signal generator (500M,47M,13MHz) Signal generator (500M,47M,13MHz) Packaged LNA

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81 thewhitenoiseofthebuffer.Moreover,comparingthechangeinthenoisegureofPMOSLNA tothatofNMOSLNAateachspurfrequency(Figure4-3(A)and4-3(B)),theformerisfoundto bemeasurablysmaller.Inthemeasurements,bothLNAsareusingthesamebufferstructure,such thatthenoisegeneratedfromthebufferisthesameforbothcases.However,thePMOSLNAhas lesschangeinitsnoisegureatspurfrequencies.ThismeansthatcomparedtotheNMOSLNA, thePMOSLNAcouldreceivelessnoisefromthebuffer.ThenoisegureofLNAundernoise injection is (4.1) wherePSisthenoisepowerfromthesourceresistance(50 W ),Gaistheavailablepowergainof LNA,PNisthenoisepowerfromLNA,andPBisthecouplingnoisefromthebuffer.Whenthe Figure 4-3.Thegainandnoiseguremeasurementresultsof(A)NMOSand(B)PMOS LNA when the buffer is working at 13MHz with shared ground.NMOS LNA Gain:~19dB NF:2.5dB PMOS LNA Gain:~14dB NF:3.5dB 1.71.92.12.32.52.7 Frequency (GHz) 0.0 10.0 20.0 30.0 (B) NF of PMOS LNA at 13MHz noise injection 1.71.92.12.32.52.7 Frequency (GHz) 0.0 10.0 20.0 30.0 (A) NF of NMOS LNA at 13MHz noise injection Noise Figure and gain (dB) Noise Figure and gain (dB) Gain Noise Figure With no noise injection With noise injection With no noise injection With noise injectionNF10 P S G a P N P B ++ P S G a -----------------------------------------log101 P N P S G a ------------P B P S G a ------------++ log ==

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82 injectednoiseisnotpresent,thecouplingnoisetermPBiszero.Therefore,thenoiseonlycomes fromtheLNAitself.Inthiscondition,thenoisegureofLNAcanbewrittenas .Whentheinjectednoiseispresent,PBisnotzero.ThechangeinnoisegurecanbewrittenaswhereF0is,LNAnoisefactorwhennoiseis notpresent.ThenoisegureresultsshowthatthechangeofPMOSLNAatspurfrequenciesis smaller than that of NMOS LNA. This can be mathematically expressed as (4.2) wherethenoisefromsourceimpedances,PSNandPSP,areequal.Moreover,forthefrequency rangebetween1.7and2.6GHz(Figure4-3),thepowergainofPMOSLNA(GaP)isabout4-5dB similarthanthatofNMOSLNA(GaN).ThenoisegureofPMOSLNA(F0P)isonly1dBhigher 101 P N P S G a ------------+ log 10 P B P S G a F 0 -------------------log 1 P N P S G a -------------+ P BN P SN G aN F 0N ---------------------------------P BP P SP G aP F 0P ------------------------------> At spur frequency 1.71.92.12.32.52.7 Frequency (GHz) 0.0 10.0 20.0 30.0 (A) NF of NMOS LNA at 47MHz noise injection 1.71.92.12.32.52.7 Frequency (GHz) 0.0 10.0 20.0 30.0 (B) NF of PMOS LNA at 47MHz noise injection Noise Figure and gain (dB)Noise Figure and gain (dB)Figure 4-4.Gainandnoiseguremeasurementresultsof(A)NMOSand(B)PMOSLNA when buffer is working at 47MHz with shared ground With no noise injection With noise injection With no noise injection With noise injection

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83 thanthatofNMOSLNA(F0N).Therefore,thecouplednoisepowerinPMOS(PBP)mustbe smallerthanthatinNMOSLNA(PBN).Measurementsatadifferentworkingfrequencyof47 MHzshowsimilarresults(Figure4-4).ItisclearthatthePMOSLNAexhibitsbetternoiseimmunitythanNMOSLNAatspurfrequencyundernoise-injectionconditionswhenthebufferisworking at 13 and 47 MHz. Changesofthenoisegurealsooccuratthefrequenciesbetweenanytwospurfrequencies.Inordertocomparethechangesatfrequenciesawayfromtheharmonicfrequencies,the measurementresultsinFigure4-3areredrawninFigure4-5.InthecaseofNMOSLNA(Figure 4-5(A)),themeasurednoisegures(thethicksolidline)arenotreducedtoitsoriginalvalue(the thinsolidline).Forexample,inFigure4-5(A)atfrequenciesbetweenthe154th(2.002GHz)and 156th(2.028GHz)harmonicsofthebufferinputfrequency,thenoisegureat2.01GHzis2.7dB insteadof2.3dBinno-noise-injectioncondition.Thenoisegureiselevatedbyabout0.4dBeven 1.71.92.12.32.5 Frequency(GHz) 1.0 2.0 3.0 4.0 5.0Noise Figure (dB)(A) NF of NMOS LNA at 13MHz Noise Injection 1.0 2.0 3.0 4.0 5.0 (B) NF of PMOS LNA at 13MHz Noise Injection 1.71.92.12.32.5 Frequency(GHz) 154th 156th ~0.5dB Noise Figure (dB) at 2.01GHzFigure 4-5.Largescalenoiseguremeasurementresultsof(A)NMOSand(B)PMOSLNA when buffer is working at 13MHz with shared ground With no noise injection With noise injection With no noise injection With noise injection

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84 betweentheharmonicsofthebufferworkingfrequency.Thisincreaseinthenoisegureoccursat frequenciesinbetweenharmonicfrequenciesoverafrequencyrangeof1.7to2.7GHz,which indicateswhitenoisecoupling.Figure4-6showsindetailtherelationshipbetweenthespurfrequenciesandthefrequenciesmeasuredbythenoiseguremeter.For47Mcase(Figure4-7(A)), atthefrequenciesbetweenthe43th(2.021GHz)and44th(2.068GHz)harmonicsofthebuffer working frequency, the noise gure difference is about 0.2dB. 154th155th 156th (2.002GHz)(2.015GHz)(2.028GHz) (2.01GHz) Figure 4-6.Thespurfrequencies(integermultiplesof13MHzbufferworkingfrequency)and the frequencies (2-2.03GHz) measured by noise gure meter (2.02GHz)(2.03GHz) (2.00GHz) 1.0 2.0 3.0 4.0 5.0 (A) NF of NMOS LNA (na1) at 47MHz Noise Injection 1.71.92.12.32.5 Frequency(GHz) 1.0 2.0 3.0 4.0 5.0 (B) NF of PMOS LNA (pa4) at 47MHz Noise Injection 1.71.92.12.32.5 Frequency(GHz) 43rd 44th 0.2dB Figure 4-7.Large-scalenoiseguremeasurementresultsof(A)NMOSand(B)PMOSLNA when buffer is working at 47MHz with shared ground With no noise injection With noise injection With no noise injection With noise injection Noise Figure (dB)Noise Figure (dB)

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85 ForthePMOSLNA,thenoiseguredegradationisreduced.AsshownintheFigure 4-5(B)(C),atfrequenciesbetweenharmonics,thenoisegureofPMOSLNAundernoise-injectionconditions(thicksolidline)isclosetothatunderno-noise-injectionconditions(thinsolid line).Forexample,atthefrequencyaround2.01GHz,thenoisegurestaysalmostthesamewith andwithoutnoiseinjection.Thisresultdemonstratesthatforthewhitenoise-injection,PMOS LNAonceagainhasbetternoiseimmunity.Theconclusionsarethesamewhenthebufferis working at 47MHz (Figure 4-7). However,thechangeinthenoisegurecannotbeobservedforbothNMOSandPMOS LNAwhenthebufferisworkingat500MHz.Figure4-8showsthemeasurementresultswhenthe bufferisworkingat500MHz.Thedifferencebetweennoise-injectionandno-noise-injection cases for both NMOS and PMOS LNA is almost indistinguishable. 1.0 2.0 3.0 4.0 5.0 (A) NF of NMOS LNA at 500MHz Noise Injection 1.0 2.0 3.0 4.0 5.0 (B) NF of PMOS LNA at 500MHz Noise Injection 1.71.92.12.32.5 Frequency(GHz) 1.71.92.12.32.5 Frequency(GHz)Figure 4-8.Large-scalenoiseguremeasurementresultsof(A)NMOSand(B)PMOSLNA when buffer is working at 500MHz with shared ground With no noise injection With noise injection With no noise injection With noise injection Noise Figure (dB) Noise Figure (dB)

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86 ThechangeintheNMOSLNAnoisegureis0.4-0.5dBforthe13-MHzcase,0.2dBfor the47-MHzcaseandisindistinguishableforthe500-MHzcase.Whydoesthechangeinnoise guredependonthebufferworkingfrequency?Toexplainthisquestion,theoutputpowerspectrumofthebufferismeasuredataround2.3222GHzwhenthebufferisworkingat13,47,and500 MHzasshowninFigure4-9.Figures4-9(A)(B)and(B)showsthebufferoutputnoiseat 2.32215-2.32225GHz(spanof100K)forboththeNMOSandPMOSLNAteststructures.Figures 4-9(A)and(D)showstheoutputnoiseofNMOSandPMOSLNAundernoiseinjection.The resultsaremeasuredbyaspectrumanalyzerwithaamplierconnectedatLNAoutputtoamplify thenoise.Theamplierhasgainof30dBandnoisegureof3dB.Figure4-9(A)showsthelower noiseoorwhenbufferisoff.Whenthebufferison,thenoiseoorincreases.Thisnoiseisgener2.322152.32225 Frequency(GHz) (A) Buffer output Spectrum of NMOS LNA test structure 2.322152.32225 Frequency(GHz) -105.0 -101.0 -97.0 -93.0 -89.0 -85.0dBm(C) NMOS LNA output Spectrum 2.322152.32225 Frequency(GHz) (B) Buffer output Spectrum of PMOS LNA test structure 2.322152.32225 Frequency(GHz) -105.0 -101.0 -97.0 -93.0 -89.0 -85.0dBm(D) PMOS LNA output Spectrum 13M 47M 500M 13M 47M 500M 13M 47M 500M 13M 47M 500M *Resolution band width(RBW):1KHz Buffer off Buffer on -120.0 -110.0 -100.0 -90.0 -80.0 -70.0 -120.0 -110.0 -100.0 -90.0 -80.0 -70.0dBm dBmFigure 4-9.Outputnoisepowerspectrumdensityofbufferin(A)NMOSand(B)PMOS LNAteststructures.(C)NMOSand(D)PMOSLNAunderbuffernoiseinjection. Under no noise injection Under 13MHz noise injection

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87 atedbythetransistorsinthebufferduringswitching.Thismeasurednoisedecreasesasthebuffer inputfrequencyincreases.Inaddition,similarresultscanbeobservedattheLNAoutput.As showninFigure4-9(C),forthe13-MHzcase,theLNAoutputnoiseishigherthanthoseat47M and500MHz.Duetothenoiseoorofthemeasurementsetup,thedifferencesforthelatertwo casesareindistinguishable.TheseresultsindicatethatthechangesofnoiseatLNAoutputare mainlyduetothestrengthsofthenoisesource.Abuffergeneratinglessnoiseathigherworking frequenciesresultsinlesschangeoftheLNAnoisegure.InthePMOScaseasshowninFigure 4-9(D),thechangeinthenoiseoorcomparedtotheLNAnoiseoorisindistinguishableand hardtoobserve,whichindicateslessnoisecouplingandchangeinthenoisegureofPMOSLNA during noise injection. 4.4 Effects on Shared and Separated Ground Inthissection,theeffectsofsharedandseparatedgroundareinvestigatedusingthesame noisegureandspectrummeasurementsetupshowninFigure4-2.Figure4-10showsgainand Gain Noise Figure 1.71.92.12.32.52.7 Frequency (GHz) 0.0 10.0 20.0 30.0 (A) NF of NMOS LNA at 13MHz noise injection Noise Figure and gain (dB)Figure 4-10.Effectsofthenoisegureof(A)PMOSand(B)NMOSLNAonsharedand separated ground. 0.0 10.0 20.0 30.0 (B) NF of PMOS LNA at 13MHz noise injection 1.71.92.12.32.52.7 Frequency (GHz)Noise Figure and gain (dB) Shared ground Separated ground Shared ground Separated ground

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88 noiseguremeasurementresults.Thinandthicklinesshowtheresultswithsharedandseparated ground,respectively.Atthepeakfrequencies,noisegureswithsharedgroundarebiggerthan thosewithseparatedground.ThisresultisvalidforbothPMOSandNMOSLNAcases.These resultsindicatethatnoisefromthebuffercantransportthroughthecommonground(on-chip ground)totheLNA.Thisimperfecton-chipgroundisduetotheniteimpedanceofdownbonds (Figure1-19).Smallchangescanalsobeseenatdipfrequenciesinlarge-scaleplotsasshownin Figure4-11(A).NMOSLNAwithsharedgroundtendtohaveahighernoisegure(thinline) thantheseparatedgroundcase(thickline)atthefrequencieshigherthan2.2GHz.Butforthecase of PMOS LNA, this change seems immeasurable. Tofurtherverifythisresult,theoutputspectraofLNAsaremeasured.Figure4-12shows themeasuredoutputspectraofPMOSandNMOSLNAsundernoiseinjectionwhenthebufferis workingat13MHz.BlacklinesrepresenttheoutputspectrumofLNAswithsharedground.Gray 1.0 2.0 3.0 4.0 5.0 6.0Noise Figure (dB)(A) NF of the NMOS LNA at 13MHz noise injection 1.7 1.9 2.1 2.3 Frequency (GHz) 1.0 2.0 3.0 4.0 5.0 6.0Noise Figure (dB)(B) NF of the PMOS LNA at 13MHz noise injection 1.7 1.9 2.1 2.3 Frequency (GHz) Shared ground Separated ground Figure 4-11.Effectsofthenoisegureof(A)PMOSand(B)NMOSLNAonsharedand separated ground in larger scale. Shared ground Separated ground

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89 linesrepresenttheoutputspectraofLNAswithseparatedground.Figure4-12(C)and(D)show thedifferenceofthespurpowerbetweentheseparatedandsharedgroundcases.Thehorizontal 1.72.22.7 Frequency(GHz) -100.0 -60.0 -20.0 20.0Output power in dBm(A) NMOS LNA output spectrum (13MHz) (B) PMOS LNA output spectrum (13MHz) 1.72.22.7 Frequency(GHz) -100.0 -60.0 -20.0 20.0Output power in dBm(C) Average output power difference of NMOS LNA with shared and separated ground (D) Average output power difference of NMOS LNA with shared and separated ground 1.72.22.7 Frequency (GHz) -10.0 -6.0 -2.0 2.0 6.0 10.0Difference in dB 1Figure 4-12.OutputSpectraof(A)NMOSand(B)PMOSLNAswithsharedandseparated ground.Meandifferencebetweensharedandseparatedgroundsfor(C)NMOS and (D) PMOS LNAs. 1.72.22.7 Frequency (GHz) -10.0 -6.0 -2.0 2.0 6.0 10.0Difference in dB 2 Shared Separated Shared Separated mean of difference mean of difference

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90 linesaremeanofthedifferences.TheaveragedifferencesforNMOSandPMOSLNAsare1and 2 dB. These results indicate that more noise is coupled to the LNA output with ground is shared. 4.5 Output Spectra Comparison AsdiscussedinSection4.3,thePMOSLNAhaslessdegradationtoitsnoisegurethan theNMOSLNA.Theseresultscanbeveriedbydirectlymeasuringtheoutputspectrumofthe LNAs.ThemeasurementsweredonebyusingthesetupinFigure4-2(B).Inthemeasurements, spurscanalsobeobservedatboththePMOSandNMOSLNAoutputspectrawhenbuffersare turned on. Figure4-13(A)showstheoutputspectraofthebufferforPMOS(grayline)andNMOS LNA(blackline)teststructures(Figure4-1)whentheinputbufferfrequencyis13MHz.Figure 4-13(B)showsthedifferenceofpowerforharmonics.Figure13(C)showstheoutputspectrumof PMOS(grayline)andNMOS(blackline)LNAswhenthebufferinputfrequencyis13MHz.Figure4-13(D)showsthedifferencebetweenspursfortheNMOSandPMOSLNAs.Figure4-13(B) showsthattheoutputpowerdifferencebetweenthetwobuffersislessthan5dB.Attheoutputof LNA’s(Figure4-13(C)),theNMOSLNAreceivesabout5-20dBmorenoisepowerthanPMOS LNA(Figure4-13(D)).Bysubtractingthegaindifference(5-7dBat1.7-2.1GHzand0-5dBat 2.1-2.7GHz)betweentheNMOSandPMOSLNA(Figure4-3),theNMOSLNAstillexhibits about5-15dBmorenoisecouplingthanthePMOSLNA.Thisresultgivesmoreevidencethatthe PMOS LNA has better noise immunity than NMOS LNA under the same noise injection. Similarmeasurementsarerepeatedforabufferworkingat47MHzwithsharedground (Figure4-14)and13and47MHzwithseparatedground(Figures4-14and4-15).Alltheresults consistently shows that the PMOS LNA picks up smaller noise.

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91 1.72.22.7 Frequency(GHz) -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0dBm(A) Buffer output spectrum (13MHz) 1.72.22.7 Frequency (GHz) -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0dBm(C) LNA output spectrum (13MHz) 1.72.22.7 Frequency (GHz) -25.0 -15.0 -5.0 5.0 15.0 25.0Difference in dB (B) Difference of buffer output spectrum 1.72.22.7 Frequency (GHz) -25.0 -15.0 -5.0 5.0 15.0 25.0Difference in dB (D) Difference of LNA output spectrum Buffer in NMOS LNA test structure Buffer in PMOS LNA test structure NMOS LNA output power PMOS LNA output powerFigure 4-13.BufferandLNAoutputspectra.(A)Outputspectraofbufferswhenbuffersare workingat13MHz.(B)Thedifferenceofbufferoutputpower.(C)NMOSand PMOSLNAoutputspectraunder13MHzbuffernoiseinjection.(D)LNAoutput power difference (shared ground).

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92 1.72.22.7 Frequency(GHz) -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0dBm(A) Buffer output spectrum (47MHz) 1.72.22.7 Frequency (GHz) -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0dBm(C) LNA output spectrum (47MHz) 1.72.22.7 Frequency (GHz) -25.0 -15.0 -5.0 5.0 15.0 25.0Difference in dB 1.72.22.7 Frequency (GHz) -25.0 -15.0 -5.0 5.0 15.0 25.0Difference in dB Buffer in NMOS LNA test structure Buffer in PMOS LNA test structure NMOS LNA output power PMOS LNA output power (D) Difference of LNA output spectrumFigure 4-14.BufferandLNAoutputspectra.(A)Bufferoutputspectrawhenbuffersare workingat47MHz.(B)Thedifferenceofbufferoutputpower.(C)NMOSand PMOSLNAoutputspectraunder47-MHzbuffernoiseinjection.(D)LNA output power difference (shared ground).(B) Difference of buffer output spectrum

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93 1.7 2.2 2.7 Frequency (GHz) -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0dBm(C) LNA output spectrum (13MHz) 1.7 2.2 2.7 Frequency (GHz) -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0dBm(A) Buffer output spectrum (13MHz) NA3 1.72.22.7 Frequency (GHz) -25.0 -15.0 -5.0 5.0 15.0 25.0Difference in dB 1.72.22.7 Frequency (GHz) -25.0 -15.0 -5.0 5.0 15.0 25.0Difference in dB (D) Difference of LNA output spectrum Buffer in NMOS LNA test structure Buffer in PMOS LNA test structure NMOS LNA output power PMOS LNA output powerFigure 4-15.BufferandLNAoutputspectra.(A)Bufferoutputspectrawhenbuffersare workingat13MHz.(B)Differenceofbufferoutputpower.(C)NMOSand PMOSLNAoutputspectraunder13MHzbuffernoiseinjection.(D)Difference of LNA output power (separated ground)(B) Difference of buffer output spectrum

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94 1.72.22.7 -80.0 -60.0 -40.0 -20.0 0.0 20.0 1.72.22.7 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0dBm(A) Buffer output spectrum (47MHz) Frequency(GHz) 1.72.22.7 Frequency (GHz) -25.0 -15.0 -5.0 5.0 15.0 25.0Difference in dB (B) Difference of buffer output spectrum Frequency (GHz)dBm(C) LNA output spectrum (47MHz) 1.72.22.7 Frequency (GHz) -25.0 -15.0 -5.0 5.0 15.0 25.0Difference in dB Figure 4-16.BufferandLNAoutputspectra.(A)Outputspectraofbufferswhenbuffersare workingat47MHz.(B)Differenceofbufferoutputpower.(C)Outputspectraof NMOSandPMOSLNAunder47-MHzbuffernoiseinjection.(D)Differenceof LNA output power (separated ground).(D) Difference of LNA output spectrum Buffer in NMOS LNA test structure Buffer in PMOS LNA test structure NMOS LNA output power PMOS LNA output power

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95 4.6 Summary ThenoiseguresofPMOSandNMOSLNAssignicantlychangeduringnoiseinjection. Thisnoiseincludesspursandwhitenoisegeneratedfromthebuffer.Inthenoiseguremeasurement,thenoisegureofPMOSLNAhassmallerdegradationthanthatofNMOSLNAwhenthe bufferisworkingat13and47MHz:about10-15dBsmallerfortheunwantedharmonicsand about0.2-0.4dBsmallerforthewhitenoise.ThisindicatesthatthePMOSLNAhasbetternoise immunitythantheNMOSLNA.Thesameresultsareveriedbymeasuringtheoutputspectraof PMOSandNMOSLNAsundernoiseinjection.ThespurpoweratthePMOSLNAoutputis about5-10dBlessthanthatofNMOSLNAaftercorrectingforthegaindifference.Thisindicates thePMOSLNAhasbetternoiseimmunitythantheNMOSLNA.Comparingthemeasurement resultsforseparatedandsharedgroundcases,thenoiseinjectiontoLNAswithsharedgroundis higher than that with separated ground.

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96 CHAPTER 5 NOISE IN A BUFFER 5.1 Introduction PerformanceofanalogorRFcircuitscanbeseverelydegradedbydigitalnoisecoupling. Accordingtothecharacteristicofnoise,noisegeneratedbydigitalcircuitssuchasabuffercanbe dividedintotwocategories:switchingnoiseandwhitenoise.InSection4.3,themeasurements haveshownthatthenoiseofan8-stagebufferdecreasesathigherinputfrequencywhenthebuffer isdrivenbyasinusoidalwave.Inthischapter,aqualitativeexplanationfortheincreasednoise will be given. Aninverter-baseddigitalfrequencydividerconsistsofachainofip-ops.These ip-opsareconstructedbyinvertersdrivenbyareferenceclocksource.Thenoisefromthetransistorsinsideinvertersorfrominputsignalsgeneratestimeuncertaintyineachclockperiodproducingjitter.Theperiodjitterisavariationofperiod.InRFcircuitdesign,thisnoiseis representedasphasenoiseinfrequencydomain.Themathematicaldescriptionofphasenoisein frequencydomainistheFouriertransformofautocorrelationfunctionofphase.Therelation betweenphasenoiseandjittercanbefoundinmanypublications[Abi06].Intimedomain,the mathematical expression of jitter is ,(5.1) where tiistheperiodofithcyclewhichisequaltophasedifferencebetweenti+1andtimoment, and 1/f0 is the nominal period. In frequency domain, this becomes ,(5.2) t i 1 2 p f 0 -----------f t i1 + ()f t i () – () 1 2 p f 0 -----------f i D == S t f () S f f () p f f 0 ----sin 2 p f 0 () 2 ------------------------=

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97 whereSt(f)andSf(f)areFouriertransformofautocorrelationfunctionsofperiodandphase, respectively.Inadivider,theperiodvariation(periodjitter) tiisassumedunchanged[Ega90], therefore in (5.1) phase variation (phase noise) Df increases with frequency increases. Accordingtothediscussionaboveand(5.1),toexplainthedecreaseofnoiseinan8-stage bufferathigherinputfrequencies, t shouldbereducedwithfrequencies.Toexaminethis,understandingofhowthenoisefromthebufferdependonfrequencyandinputsourceaffectthefrequencydependenceofoutputnoiseisneeded.InSection5.2,thenoisesourcesintransistorswill be considered and in Section 5.3, the noise from external input signal will be discussed. 5.2 Noise in Transistors 5.2.1 Flicker Noise Flickerandchannelnoiseinatransistorarethetwonoisesourcesintransistors[Jin06], [Nem01],[Jak96].Atlowfrequencies,1/fnoiseisthemajornoisesourceinCMOStransistors. Thefundamentalphysicalunderstandingofthisnoiseisstillanactiveresearcharea.Thereare threemaintheories:1)Carriernumbeructuationtheory:ThistheoryisproposedbyMcWorther [McW57].1/fnoiseisattributedtothetrappinganddetrappingofchargecarriersinthetrapsat theoxide-semiconductorinterface.2)Mobilityuctuationtheory:Hoogeshowsthat1/fnoise resultsfrombulkmobilityuctuationcausedbyphononscattering[Hoo94].Hooge’stheoryis moresuccessfulinexplainingthebehaviorof1/fnoiseinPMOStransistorswhereinput-referred 1/fnoiseisstronglydependentonthegate-to-sourcevoltage.3)Unied1/fnoisemodel:This modelcorrelatesthenumberandmobilityuctuationandwaspresentedbyJayaramanandSodini [Jay89].Theunied1/fnoisemodeliscommonlyusedintoday’scompactMOSmodel,suchas BSIM3andBSIM4.However,theuniedmodelisstillnotrobustenoughtofullydescribethe1/f noise behavior in all operating regimes of PMOS and NMOS transistors [Van00].

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98 AlthoughthephysicaloriginofFlickernoiseisstilluncleartoday,toacircuitdesigner, expressionstodescribethebehaviorsofFlickernoiseareuseful.Simpleequationsofinput referrednoisevoltageSvganddrainnoisecurrentSidinlinearandsaturationregionsarereported [Jak96]. 5.2.1.1 At strong inversion in linear region Basedoncarriernumbeructuationtheory,1/fnoiseisrelatedtothetrapsinoxide-semiconductorinterface,andtheinput-referrednoisevoltageisindependentofsource-gatevoltageof an NMOS transistor and drain current. Svg is written as ,(5.3) whereNotistheequivalentdensityofoccupiedoxidetraps,qiselementarycharge,Coxisoxide capacitance per unit area, W and L are transistor length and width, and f is frequency. Not is ,(5.4) whereNtisthedensityofoxidetrapsperunitvolumeandunitenergy,and g istheMcWhorter tunnelingparameterwhichdependsontheeffectivemassofthetunnelingcarrierandbarrier height between the oxide and trap. SidisSvgmultipliedbysquaredtransconductancegmandforalongchannelMOSFETis given by ,(5.5) where VGS is the gate-to-source voltage, VT is the threshold voltage and Id is the drain current. S vg q 2 C ox 2 ---------N ot WL --------1 f -= N ot kTN t g ------------= S id g m 2 S vg I d V GS V T – -------------------------2 S vg ==

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99 5.2.1.2 At strong inversion in saturation region Svghasthesameformas(5.3)[Jak96].TransconductanceatsaturationischangedandSidis written as .(5.6) 5.2.1.3 At weak inversion SvgisrelatedtotheratioofinversioncapacitanceCinvtothesumofoxide,diffusion,and inversion capacitance (Cox, Cd, and Cinv) and is given by .(5.7) Sid is Svg multiplied by squared transconductance, gm and is given by ,(5.8) where gm is given by ,(5.9) wherenisthebodyeffectcoefcient, ftiskT/q(around0.026voltatroomtemperature),andIDis drain current at weak inversion and is given by ,(5.10) S id g m 2 S vg @m C ox W L ----I d S vg = S vg C inv C ox C d C inv ++ -----------------------------------------2 q 2 C ox 2 ---------N ot WL --------1 f -@ S id g m 2 C inv C ox C d C inv ++ -----------------------------------------2 q 2 C ox 2 ---------N ot WL --------= g m I D nV T -----------=I DS I 0 e V GS n f t -----------1e V DS n f t ------------ – – =

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100 whereI0isproportionaltoW/L,VDSandVDSarethegate-to-sourceanddrain-to-sourcevoltages, andnisbodyeffectcoefcientequalto1+ h . h isequaltogmb/gmwhichistherelatedtoratioof bulk depletion capacitor to oxide capacitor (Cd/Cox). ForNMOStransistorsoperatingatstronginversioninlinearandsaturationregions,inputreferrednoisevoltagesaresimilar.ForPMOStransistorsoperatinginthesameregimes,the input-referrednoisevoltageisstronglydependentongate-to-sourcevoltage.ForPMOSand NMOS transistors operating at subthreshold, input-referred noise voltage Svg decreases. TheFlickernoiseinCMOStransistorsunderswitchingbiasconditionisalsoworthtodiscuss.AsmentionedinChapter3,Flickernoiseunderswitchingconditionissmallerthanthat undernormalDCbiasconditions.HowdoesFlickernoisespectrumchangeswitchingfrequency? Toanswerthequestion,themeasurementresultreportedbyA.P.vanderWelisdepictedin Figure5-1.Inthemeasurement,anNMOStransistorisusedandthegateoftransistorisdrivenby asquare-wavewithamplitudeof2.5voltforswitchingfrequenciesfrom100to1MHz.PSDof Flickernoisereducesatthefrequenciesbelowswitchingfrequency(Figure5-1).Forexample,for Figure 5-1.Noise reduction with different switching frequency. Relative noise power (dB) Frequency (Hz)

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101 100KHzswitchingfrequency,reductionofPSDat1000Hzisabout10dB,comparedwiththatin aconstantbiascondition.For10KHz,thereductionis7dB.Atfrequenciesabovetheswitching frequency,spectraaresimilartothatforconstantbiascondition.Intheexample,Flickernoiseis reducedmorewithhigherswitchingfrequencies,whichissimilartothenoiseperformancementionedinSection4.3.Inaddition,Flickernoisecanbeupconvertedtotheharmonicfrequencies duetotransistorswitching.Therefore,Flickernoisemaybeoneoftheexplanationsforthebuffer whitenoisemeasurementresults.However,ina0.18m mCMOStechnologythecornerfrequency ofFlickernoiseforatransistorisaroundfewMHz,atthefrequencieshigherthanthecornerfrequencythetransistornoiseisdominatedbythethermalnoiseoftransistors.Also,themeasured noiseisatthefrequenciesbetweentwoharmonicswhichishigherthanthecornerfrequency.This suggest that Flicker noise is not the answer for the buffer white noise measurements. 5.2.2 White Noise Atransistoratconstantbiasconditionproducesvaryingdraincurrentwithbroadbandfrequencyresponsecalledwhitenoise.Atstronginversionregion,thisnoiseisthermalnoisecaused bythethermalmotionofcarrierinachannel.Atweakinversion,thecharacteristicofthenoiseis eithershotnoiseorthermalnoiseorboth.Theexactoriginisstillnotclear[Tsi99].However,both arewhite.Anexpressionderivedbasedonthermalnoiseassumptionwithaformofshotnoiseis commonlyusedtodescribethenoisebehavioroftransistorsinweakinversion.Inthissection,the white noise in different operation regimes of transistors is summarized. 5.2.2.1 At strong inversion Powerspectraldensity(PSD)ofchannelnoiseofatransistorisrelatedtothetotalinversionlayerchargeswhichistheintegrationofallinversionchargesalongthechannel.Consequently,thetotalinversionlayerchargesisfunctionofoverdrivevoltage(VGS-VT)and

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102 drain-to-sourcevoltageVDS.Tosimplifytheequation, x isusedtorepresentVDSdependenceand the PSD for a long channel MOS transistors is written as ,(5.11) wherekistheBoltzmannconstant,Tistemperature,Wiswidth,Lislength, m ismobility,VGSis gate-to-sourcevoltage,VTisthresholdvoltage,and x isavariablerelatedtoVDS.Inlinearregion VDSis small so that x is approximately equal to 1. The equation becomes (5.12) wheregsd0isthesource-to-drainconductanceinthelimitasVDSapproacheszero.Insaturation region, x is equal to 0. The equation is .(5.13) Formoreinformationabout x ,areadercanreferto[Tsividis].Fromtheaboveequation, thenoiseinlinearregionisexpectedtobe2/3timeslargerthanthatinsaturationregionduetothe factthatnumberofinversionchargesinlinearregionislargerthanthatinsaturationregion,ifthe same VGS is applied. 5.2.2.2 At weak inversion Atweakinversion,draincurrentisanexponentialfunctionofgate-to-sourcevoltageVGS.PSD of channel noise has a mathematical form similar to shot noise, given by ,(5.14) whereqistheelementarycharge,IDS0isthedraincurrentIDSwhenVDSismuchgreaterthan ftand ftis kT/q (around 0.026 volt at room temperature). IDS is given by (5.10). S4kT W L ----m C ox V GS V T – () 2 3 -1 xx 2 ++ 1 x + -----------------------= S4kT W L ----m C ox V GS V T – () 4kTg sd0 == S4kT 2 3 -W L ----m C ox V GS V T – () 4kT 2 3 -g sd0 == S2qI DS0 1e V DS f t – + =

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103 In(5.14),VDSisusuallygreaterthann ftwherenisbetween1.1and1.4(inordertocontrolbodyeffect),andPSDdependsonVGSaswellastheinversionchargedensity.Therefore,for atransistor,whitenoiseatweakinversionisexpectedtobesmallerthanthatatstronginversion due to fewer inversion charges. Applyingabovediscussiontoaninverter,attransitionregionwhenbothNMOSand PMOStransistorsareatsaturation,totaloutputwhitenoiseisthesumofnoisefromNMOSand PMOStransistors,whichisequalto2/3*4kT(gDS0n+gDS0p).Attheoperationregionwhenthe outputvoltageofbufferisequaltoeithersupplyvoltageorzero,theoutputshort-circuitnoisecurrentiseither4kTgDS0nor4kTgDS0p.Thus,whitenoiseispresentatalltimeevenwhenoneofthe transistoristurnedonandtheotherisoff.Therefore,thedependenceofwhitenoiseonthe inverter switching frequency is weak, which can explain the effect of buffer output noise. 5.3 Noise from Input Source A simple expression for the noise from an input source is written as ,(5.15) wheren(t)isadditivenoiseand f (t)isphasenoise.Ifthewhitenoiseatinverteroutputismainly contributedbytheadditivenoiseofinputsignals,thenoisewhenbothPMOSandNMOStransistors are at saturation region can be written as ,(5.16) whereInistheshort-circuitoutputnoisecurrent, b is m Cox(W/L),VDDisthesupplyvoltage,VTisthethresholdvoltage,gmpandgmnarethetransconductancesofPMOSandNMOStransistors. In(5.16), b andVTofPMOSandNMOStransistorsareassumedtobethesame.Thisisareasonableassumptionduetothatinaninverterdesign,thewidthofPMOStransistorsisusuallysized biggertoensurethesameriseandfalltimes.VDDcomesfromthesumofgate-to-sourcevoltages V in t () A w t f t () + () cosnt () + = I n t () g mp g mn + () –nt () b –V DD 2V T – () nt () = =

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104 ofPMOSandNMOStransistors.Whentheoutputvoltageofaninverterisequaltoeithersupply orzerovoltage,thenoisecontributionfromtheinputsignalissmallerduetothesmalltransconductance and can be neglected. 5.4 Output Noise of 8-Stage Buffer AsmeasurementresultsdiscussedinChapter2,theoutputnoiseofthe8-stagebuffer decreaseswithinputfrequencyincreases.Forthistothecase,thewhitenoiseoftransistorscan notbethedominantnoisesourcebecausethedependenceofwhitenoiseontheinverterswitching frequencyisweak(Section5.2.2).Flickernoiseisnotthenoisesourcecausingtheproblem(Section 5.2.1). Other possible noise source is the noise from the input source. Toinvestigatethis,thephasenoiseoftherstharmonicofbufferoutputsignalsismeasuredwhileusingdifferentinputsignalsourcesandshowninFigure5-2(B)and5-3(B).Theinput frequencyis13MHz.HP8640BandHPE4421Bsignalgeneratorsareused.Thephasenoiseof sourcesisalsomeasuredandgiveninFigure5-2(A)and5-3(A).Theshapesofbufferoutput phasenoiseforbothcaseareverysimilartothatofinputsignals.Thisindicatesthatthebuffer outputnoiseismainlydeterminedbythenoisefromtheinputsignalsource.Thebufferoutput noise power is higher than the thermal noise and similar to the source 102104106108Frequency offset from carrier (Hz) -170 -150 -130 -110 -90 -70Noise to carrier (dBc/Hz) 102104106108Frequency offset from carrier (Hz) -170 -150 -130 -110 -90 -70Noise to carrier (dBc/Hz) Figure 5-2.Phase noise of (A) the HP8640B signal generator and (B) the buffer at 13MHz. (A) (B)

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105 . 102104106108Frequency offset from carrier (Hz) -170 -150 -130 -110 -90 -70Noise to carrier (dBc/Hz) 102104106108Frequency offset from carrier (Hz) -170 -150 -130 -110 -90 -70Noise to carrier (dBc/Hz) Figure 5-3.Phase noise of (A) the HPE4421B signal generator and (B) the buffer at 13MHz. (A)(B) 102104106108 -160.0 -140.0 -120.0 -100.0 -80.0 -60.0 102104106108 -160.0 -140.0 -120.0 -100.0 -80.0 -60.0 Figure 5-4.Phase noise of (A) the HP8640B signal generator and (B) the buffer at 47MHz.Frequency offset from carrier (Hz)Noise to carrier (dBc/Hz)Frequency offset from carrier (Hz)Noise to carrier (dBc/Hz)(A)(B) 102104106108 -160 -140 -120 -100 -80 -60 102104106108 -160 -140 -120 -100 -80 -60 Figure 5-5.Phasenoiseof(A)theHPE4421Bsignalgeneratorand(B)thebufferat47MHz.Frequency offset from carrier (Hz)Noise to carrier (dBc/Hz)Frequency offset from carrier (Hz)Noise to carrier (dBc/Hz)(A)(B)

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106 Thephasenoiseofoutputsignalat1-MHzoffsetfromthecarrierisabout-130dBc/Hz (Figure5-3(B)).Thepowerofcarrieratthebufferoutputisaround8.7dBm.PSDofthenoise around14MHzoffsetintheoutputnoisespectrumis-121.3dBm/Hzwhichismuchhigherthan thenoisecangeneratedbythetransistors.Thesamephenomenonisobservedat47MHz.Inorder tounderstandhownoisefromtheinputsourceisprocessedbythe8-stagebuffer,theoutputnoise issimulatedusingPeriodicSteadyState(PSS)analysisinCadence.Thespectrum(Figure5-6)is addedtotheinputsignalstosimulatethenoisefromthesignalgenerators.f0isthefrequencyof inputsignalanditis13,47,and500MHz.ThePSDofnoisespectrumwithin1MHzoffsettof0is notat.Abovethe1MHzoffsetfrequency,PSDofnoisespectrumisatandhasaconstantvalue of-126dBm/HzwhichisequaltothewhitenoisePSDintheHPE4421Bsignalgenerator. Figure5-7showsthesimulatedoutputnoisespectrumofthe8-stagebuffer.Thenoiseoor decreasesasthebufferinputfrequencyisincreased.Thissimulationresultshavethesametrend as the measurement. Thenoisefromtheinputsourceisampliedandtransferredtotheoutputwhenboth PMOSandNMOStransistorareinsaturationregion,whichistransitionregionoftheinverters.If f0+104f0f0+105f0+106f0-106f0-105f0-104 -126 -116 -106 dBm/Hz HzFigure 5-6.Noise is added in input signals in circuit simulation.

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107 risetimeorfalltimeoftherstinverterislonger,thenthesourcenoiseisampliedandtransferredtotheoutputforlongerperiods.Toexploretherelationshipbetweenworkingfrequency andnoisePSD(noiseoor),therisetimesofrst-4-invertersaresimulatedandlistedin Table5-1.Risetimeisdenedasthetimerequiredforoutputvoltageofaninvertertochange from10%to90%ofthesupplyvoltage.Forhigherinputfrequency,risetimeofthe1st-two inverterstagesaresmaller.Thisisbecausethatinputsignalsaresinusoidalwaveswiththesame amplitude(1.58volts)butdifferentriseandfalltimes.Highfrequencysinusoidalwavehas shorterrise/falltime,comparedwithlowfrequencyone.Thisisthemainreasonfortheincrease of output noise with increasing input frequency. Table 5-1.Rise time (psec) of the rst-4-stage inverters in the 8-stage buffer Frequency(Hz)1st2nd3rd4th 13M975232175172 47M417162165171 500M2558215783 0123 Frequency (GHz) -160 -140 -120 -100 -80PSD (dBm/Hz) 13MHz 47MHz 500MHzFigure 5-7.Simulatedoutputnoisespectrumofthe8-stagebufferwhenthebufferinput signals are 13, 47,and 500-MHz sinusoidal waves. 13 MHz 47 MHz 500 MHz

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108 Tofurtherverifythis,squarewaveswiththesamerisetimeandfalltimesbutdifferentfrequenciesareusedasinputsignals,andtheresultsareshowninFigure5-8.Incontrasttothepreviousresults,thenoiseoordecreasesastheinputfrequencyisdecreased.Usingsquarewaves ensuresthatallinvertershaveapproximatelytheriseandfalltimeforallinputfrequencies.The sameriseandfalltimemeansthatthenoiseisampliedbythebufferforthesamedurationduring eachswitchingevent.However,withthesameriseandfalltimebutdifferentinputfrequency,the averagenoisepowerinoneperiodisdifferent.Atlowerfrequency,theaveragenoisepoweris lowersinceperiodsarelonger,resultinglowernoisePSDatthebufferoutput.Thiscanbealso explainedbythesamplingtheory.Aninvertercanbetreatedasaswitch.WhenbothPMOSand NMOStransistorsareon,theinvertercanbethoughtofasasamplerofinputnoises.Whenone transistorison,theinvertercannotamplifythenoiseofinputsource.Ofcourse,thesampledoutput noise PSD is lower at lower sampling frequency. 0123 Frequency (GHz) -180 -160 -140 -120 -100PSD (dBm/Hz) Figure 5-8.Simulatedoutputnoisespectrumofthe8-stagebufferwhenbufferinputsignals are 13, 47, and 500 -MHz square wave. 13MHz 47MHz 500MHz 13 MHz 47 MHz 500 MHz

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109 Fromtheabovediscussion,thebehaviorofwhitenoise(noiseoor)atthebufferoutput dependsontheinputfrequencyandtheriseandfalltimeoftherst-twoinverterstages.Larger riseandfalltimescouldincreasetheoutputnoiseoorofbuffereventhoughtheinputfrequency islower.Thiseffecttoreduceoutputnoise,lowerriseandfalltimeaswellashigherinputfrequency are preferred for sinusoidal input signals. 5.5 A Simple Noise Model Inaninverter,inputnoiseisampliedanddeliveredtoaloadcapacitorwhenbothPMOS andNMOStransistorareon.Whenonlyonetransistorison,theoutputcapacitoriseitherconnectedtoVDDorgroundasshowninFigure5-9(A).Duringthisperiod,noampliedinputsource noiseappearsattheoutput.ThisissimilartoswitchingbetweenanamplierandaACground.If thedurationfortheamplicationistp,thenthedurationfortheACgroundingisT-tpwhereTis halfperiodofinputsignals.Asimpliedsmallsignalmodelrepresentingthisisshownin Figure5-9(B).Duringtp,theinputnoisen(t)isampliedbytransconductanceGmwhichisequal to b (VDD-2VT)(5.16)assumingthatthetransconductanceisconstantwhenbothtransistorsareon andthelongchannelapproximationisutilized.Theinputnoiseistransferredtonoisecurrentin(t) owingintotheloadcapacitor,producinganoisecurrentino(t)andanoisevoltagevno(t)whichis theintegrationofnoisecurrentino(t)dividedbytheloadcapacitance.DuringT-tp,thenoiseisdisVDD n(t) ino(t) vno(t) Gm*n(t) + n(t) in(t) vno(t) + tpT-tpFigure 5-9.Simple inverter model.(A)Asimpleinverterand(B)itssimpliedsmallsignal model. ino(t) (A) (B)

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110 chargedtotheACgroundimmediatelyifonresistanceoftransistorsisinnitelysmall.The switchingbetweenanamplierandaACgroundcanberepresentedbyadeterministicfunction G(t)togglingbetween1and0fortpandT-tpperiodasshowninFigure5-10.n(t)isthesource noiseandVo(t)isthebufferoutputvoltagewithoutaddingoutputnoisevno(t).Theoutputnoise currentino(t)istheproductofG(t)andin(t).Duetotheswitchingnatureofinverter,theoutput noisecurrentisperiodicallyturnedonandoffduringtpandT-tpperiod.Iftheinputnoisen(t)isa wide-sensestationary(WSS)randomprocess1,thenino(t)isacyclostationaryrandomprocess. ThemeanminoandautocorrelationRinoofino(t)areperiodicwiththetimeperiodTandhavefollowing relationships: ,(5.17) 1.Arandomprocessiswide-sensestationaryifitsmeanfunctionm(t)isindependentoftimeandits autocorrelation R(t1,t2) only depends on the time difference t1-t2. n(t) Vo(t) G(t) ino(t) tpT T-tp T-tp tp 2T tp T T-tpFigure 5-10.Time-domain wave forms. m ino tT + () m ino t () =

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111 and (5.18) foralltandu,wheretistimeanduistimedelayfromt.Thesystemislinearperiodically time-varying(LPTV).Thenoisevoltagevno(t)istheintegrationofnoisecurrentino(t).Because thisintegrationistimevariant,atimeinvariantapproximationisused.Acommonwaytorepresenttheintegrationistopassino(t)throughalinearblockwhosetransferfunctionistheLaplace transform Wtp(s) of the rectangular window wtp(t) given by [Abi06] .(5.19) The Laplace transform of wtp(t) is written as [Abi06] .(5.20) The frequency response of its magnitude is .(5.21) R ino tTuT + , + () R ino tu , () = w tp t () 10tt p 0otherwise = W tp s () 1e st p – – s ---------------------= W tp f () t p c p ft p () t p p ft p () sin p ft p ----------------------= sin = G(t) n(t) in(t) vno(t) Gm wtp(t) Figure 5-11.A system block diagram of noise in a inverter. ino(t)

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112 AsystemblockdiagramisshowninFigure5-11.Theoutputnoisevoltagevno(t)canbe written as .(5.22) wherevno(t)isacyclostationaryrandomprocessandG(t)isaperiodicfunctionwhichcanbe expressed as a Fourier series ,(5.23) whereanisFouriercomponentsofG(t).Ifthevno(t)ismeasuredbyaspectrumanalyzer,thenits spectrumcanberepresentedbythetime-averagePSD,SR(f),whichistheFouriertransformof the time average of autocorrelation function of vno(t) denoted by [Ter02] ,(5.24) where Rvno(t+ t ,t) is a cyclostationary random process, t is the time delay and Rvno is (5.25) whereRin(t)andRino( t ,t)aretheautocorrelationofin(t)andino(t).Ifinputnoisen(t)isastationaryrandomprocess,thenRin(t)isastationaryrandomprocessandRino( t ,t)isacyclostationary random process. From (5.23), (5.24), and (5.25), SR(f) is given by v no t () i n t () Gt () () w tp t () =i n t h – () Gt h – () () w tp h () hd – = Gt () a n e j 2 p n T --------t n – = = R t () 1 T --R vno t t +t , () td0 T = R vno t t t , + () R in p t q – + () Gtp – () Gt t q – + () w tp p () w tp q () qdpd qp= R ino t t , () w tp t () w tp t – () = E =i n t t + () Gt t + () () w tp t t + () {} i n t () Gt () () w tp t () {} []

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113 (5.26) whereS RinoistheaveragingPSDofino(t)andSRinisthePSDofin(t).Becausein(t)isstationary whitenoise,itsPSDisconstantthroughtheentirespectrum.IfPSDofin(t)isNin,thenapplying Parseval’s theorem. S R is rewritten as (5.27) where (5.28) istheaveragepowerofwaveformG(t).Iftherisetimetpismuchsmallerthantheperiodofinput signal T and (5.16) is applied, then PSD of output voltage can be rewritten as (5.29) where Nn is the PSD of the input noise n(t). Accordingtotheabovediscussion,PSDofvno(t)isinverselyproportionaltotheperiodof inputsignalswhentherisetimetpiskeptconstant.ThisappliestothesituationinSection5.4 whenthe8-stagebufferisdrivenbysignalsatthreedifferentfrequencieswiththesamerisetime. Toverifytheanalysisthenoiseofasingle-stageinverterissimulated.Aninverterwitha10-fF loadcapacitorisdrivenwithfourdifferentsquare-wavesignals(10,50,100,and500MHz)with thesameriseandfalltime.AplotofPSD(V2/Hz)fortheoutputvoltageat10MHzversusfreS R f () S Rino f () W tp f () 2 = a n 2 S Rin fnf 0 – () n – = t p p ft p () sin p ft p ----------------------2 = S R f ()a N in t p p ft p () sin p ft p ----------------------2 = a a n 2 n – = 1 T --Gt () 2 td0 Tt p T ---=== S R f () t p 3 T ---N in = t p 3 T ---b V DD 2V T – () N n =

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114 quencyisshowninFigure5-12.Clearly,isproportionalto1/T.Toexaminetherelationship betweentherisetimetpandPSDofoutputvoltageS R,thesquarewaveswithsamefrequencyand differentrisetimesareappliedtotheinverter.SimulatedPSDofoutputvoltageat10MHzisplottedversusrisetime(Figure5-13)whentheinputfrequencyis50MHz.Thecirclesanddashed linearethesimulateddatapointsandidealastraightlinewithslopeof3.Thesimulationsshow Figure 5-12.Simulated PSD of output voltage v.s. input frequencies. 101001000 Frequency (MHz) 10-1710-1610-1510-14 (V2/Hz) slope of 1V no 2 V no2 0.11 tp (psec) 10-1610-1510-1410-1310-12 slope of 3 Figure 5-13.Simulated PSD of output voltage v.s. different rise time. (V2/Hz) V no 2

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115 thetrendin(5.29).However,theslopeof3onlyoccursneartherisetimearound4sec.Thismay due to the approximation error. 5.6 Summary Inthischapter,ickerandwhitenoiseintransistorshasbeenbrieyreviewed.Theeffect of buffer output nose oor versus input frequency has been understood. Inthebufferoutputnoisemeasurement(Figure4-9(A)),themeasurednoisepowerlevels for13,47and500MHzare-140,-144,and-152dBm/Hzataround2.322GHzandinthesimulation(Figure5-7),thepowerlevelsare-138,-141,and-147dBm/Hz,respectively.Themeasured noisedifferencesbetween13and47MHzandbetween47and500MHzare4and8dBandin simulation,thedifferencesare3and6dB,respectively.Theoutputnoiseof8-stagebuffer decreasesathigherworkingfrequency,whichisduetothefactthatathigherworkingfrequency therisetimesofthersttwoinverterstagesareshorter.Shorterrisetimereducestheamplication and propagation of noise of input source to the output. Finally,asimplemodelispresentedtodescribethebehaviorofoutputwhitenoiseina inverterwithacapacitiveload.Thismodelisbasedonalinearperiodicallytime-varying(LPTV) systemwithinputnoisewhichiswide-sensestationary(WSS).Themodelsuccessfullypredicts thattheoutputnoisevoltagePSDisinverselyproportionaltotheperiodofworkingfrequency whentheriseandfalltimesoftheinputsignalarekeptthesame.Inaddition,theoutputnoiseis proportional to a cubic of rise time due to the integration associated with the load capacitor. Applyingtheabovesimplemodeltothe8-stagebuffer,thereducednoisebetween13and 47-MHzinputfrequencyisaround5.4dBduetothe+5.6and-11-dBdifferencesinfrequency andrisetime(Table5-1).Thepredicted5.4-dBdifferenceisclosetothemeasured4-dBone. However,thenoisedifferencebetween47and500MHzpredictedbythesimplemodelisnot

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116 matchedtothemeasurement.Thepossiblereasonisduetothecascadestagesinthe8-stagebuffer which is not modeled in the one stage inverter model.

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117 CHAPTER 6 NOISE COUPLING MECHANISMS BETWEEN LNAS AND BUFFERS 6.1 Introduction Inthischapter,thenoisecouplingmechanismsbetweenthePMOSandNMOSLNAsand 8-stagebufferarediscussed.Theanalysisisbasedonlumpedelementmodels.DistributedsubstrateresistancebetweenLNAsandbuffersaremodeledbyaresistornetwork(Chapter2). On-chipmetalgroundplaneismodeledasasinglegroundnode.Thepurposeofusingalumpelementmodelistodevelopintuitiveexplanationofthemechanismswithoutusingacomplexelectromagnetic eld simulator that can used by a circuit designer. SystemsimulationofnoisecouplingeffectbetweenanLNAandabufferrequiresthree components:LNAandbuffercircuits,asubstratemodelandapackagemodelasshownin Figure6-1.ThecircuitschematicsofLNAsandbuffersinChapter3areusedinhere.ADCsubstratemodelextractedfromtheteststructureisusedforsubstratemodelingandwillbediscussed inSection6.3.PackagemodelingwillbedescribedinSection6.4.Systemmodelingwillbesummarized in Section 6.4.3. Figure 6-1.System simulation of noise coupling LNA circuit buffer circuit substrate model package mode l noise coupling simulation inductive coupling DC substrate model capacitive coupling

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118 Noisecouplingprocesscanbedividedintothreeparts:generation,propagation,and reception.Correctlymodelingthenoisesourceisimportant.InSection6.2,thenoiseof8-stage buffer circuit will be presented. Groundbounceduetodigitalcircuitswitchingisaseriousprobleminpackagedcircuits. Duetotheniteinductance,thenoiseproducedbytheswitchingnoiseinthedigitalcircuitcouplesthroughtheon-chipgroundtoanalogandRFcircuits,degradinganalogandRFcircuitperformance.Byseparatingthegroundconnection,theproblemcanbemitigated.However,the methodcannotpreventthegroundbouncingnoiseinjectingintosubstrate.Still,noisecancouple through substrate to vulnerable point in analog and RF circuits. Inthiswork,clockingsignalofbufferisprovidedbyexternalsignalsourceandthesignal groundisconnectedtoLNAon-chipground(Figure6-2).Inthisway,groundofinputsignalis referredtotheon-chipground,andthusgroundbouncingproblemisreduced.Nevertheless, bouncingduetoparasiticinductanceinbondwire(Lbond_wire)andon-chippowerline (Lon_chip_powerline)cannotbeneglected.Thesebondwiresandpowerlineshavenoconnectionto LNA PCB ground Buffer on-chip ground Ldown_bondCby A Lbond_wireLbond_wireLon_chip_powerlineFigure 6-2.ClockingsignalforthebufferisprovidedbyanexternalsourcethroughanAC probe external signal source+

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119 substrate.Mostly,noisegeneratedfromthesebondwiresorpowerlinescoupletosubstrateor LNA circuit through an inductive and capacitive coupling. 6.2 Noise Source Inthissection,the8-stagebuffer’soutputspectrum,powerlinenoisespectrum,and back-gate resistance of transistors are veried. 6.2.1 Buffer Output Spectrum Outputspectrumofbuffer(solidline)ismeasuredfrom10Mto2.7GHzasshownin Figure6-3.Comparingwiththesimulationresultsofanideal8-stagebuffer(circlesymbols),the 00.30.50.81.11.41.61.92.22.42.7 Frequency (GHz) -100 -80 -60 -40 -20 0dBm Figure 6-3.Measured (solid line) and simulated (circle symbol) output spectra of buffer 8-stage buffer output Figure 6-4.Distributed model for the last stage of the buffer. input of last stage

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120 measuredspurpowerdecreasesfasterwithfrequency.Thisdiscrepancyiscausedbytheparasitic resistanceinthelastinverterstage.Thelastbufferstageisalongstrip-shapedstructure (Figure2-3).Tomodelthisfourgateresistorsandanoutputresistorareaddedinthecircuitand thelaststageinverterismodeledbyfoursub-inverterstoincludethedistributedeffect (Figure6-4).DuetotheadditionalR-Celements,thesimulatedspuramplitudesdecreasefaster with frequency and better match the measurements (Figure6-5). 6.2.2 Switching Noise in the 8-stage Buffer Inthemeasurement,DCpower(VDD)ofthebufferisprovidedbyanexternalsource throughbondwiresorDCprobes.TheparasiticinductanceofbondwiresandDCprobesarenot negligible(Figure6-6(A)).Currentgeneratedbyaninverterproducesavoltageuctuationacross theinductance(Lbfbw).Thisistheswitchingnoisealsoknownasdi/dtnoise.ThisvoltageuctuationcancoupletoRFandanalogcircuitsandproducenoisespursatoutputspectrum,degrading thecircuitsperformance.Theshapeofthisspectrumcanbemodeledwithasimpliedmodel showninFigure6-6(B)includingacurrentsourceI(t)andaLCnetwork.ThecurrentsourcerepresentsthecurrentowingoutfromthesourceofPMOStransistor.TheLCnetworkiscon00.30.50.81.11.41.61.92.22.42.7 Frequency (GHz) -100 -80 -60 -40 -20 0dBm Figure 6-5.Measurementandsimulationincludingparasiticgateresistanceandoutput capacitance.

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121 structedbyC1,C2,andLbfbwwhichareon-chip,off-chipbypasscapacitorsandtheinductanceof VDD and ground bond wires as well as that for the off-chip bypass capacitor. Assumingthatthebufferisworkingat47MHzwithrisetimeof570psec(fromsimulation),intimedomain,thecurrentwaveformI(t)canbeapproximatedbyasquarewavewith periodof10.638nsec(1/47MHz)anddutycycleof5.36%.Infrequencydomain,thespectrumof I(t)containsamainlobewithbandwidthof1.75GHz(1/570psec).TheLCnetworkiscomposed ofa20-pFon-chipbypasscapacitor(C1),a1m Foff-chipbypasscapacitor(C2),anda3.5-nH bondwireinductor(Lbfbw)withthreepolesandtwozeros.Thetwopolesareat (=~),600MHz,andtheotherisatorigin.Thetwozerosareat , 3 MHz. Figure6-7showsmeasuredvoltagespectrumatSnodeofthe8-stagebufferinFigure6-6 aswellasoutputofsmallsignalmodel.DuetotheresonanceofC1andLbfbw,apeakfrequency around500MHzismeasuredwhichisalittlebitlowerbutclosetotheprediction.Adipfrequency isat1.8GHzclosetothepredictedmainlobebandwidthofinputcurrentI(t).Tofurtherverifythe conceptofsimpliedmodel,anexternal5.7-nHinductorisaddedinserieswiththebond-wire input VDD (20 pF) (1 m F) 4 pF output Figure 6-6.Switching noise in 8-stage buffer.(A)SwitchingnoiseatsourceofPMOS transistor (S node). (B) The small signal model.S LbfbwS (A) (B)Lbfbw (3.5 nH) C1C2C1C2I(t) 1 2 p LC 1 C 2 || () --------------------------------------1 2 p LC 1 --------------------1 2 p LC 2 ---------------------

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122 (Figure6-8(A))tolowerthepeakfrequencyaswellasthepolefrequencyintheLCnetwork.The measurementresultisshowninFigure6-8(B).Thepeakfrequencyisaround300MHzwhichis close to the expected value of 290 MHz. The8-stagebufferincludingtheeffectsofoff-chipbondwiresandon-chipbypasscapacitorsissimulated.Theresult(circlesinFigure6-9)isclosetothemeasurement(solidline)except thatthesimulatedmainlobebandwidthisslightlysmallerthanthemeasuredone.Accordingto 00.30.50.81.11.41.61.92.22.42.7 Frequency (GHz) -120 -100 -80 -60 -40 -20dBm Figure 6-7.The voltage spectrum at S node. peak frequency dip frequency input VDD 40 pF 1 m F 2.5 nH 4 pF output 5.7 nH Figure 6-8.Abypasscapacitorinserieswiththeinductoronthepowersupplylinecausing power line bouncing 00.30.50.81.11.41.61.92.22.42.7 Frequency (GHz) -120 -100 -80 -60 -40 -20dBm (A)(B) peak frequency

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123 thesimplemodelmentionedabove,thedipfrequencyismainlydeterminedbythespectrumofthe widthofcurrentwave,whichisthetimeperiodduringwhichthetransistorsswitch.Becauseof this, the time period in simulation is slightly longer than that in the measurement. 6.2.3 Transistor Back-Gate Network Modeling Noisecanbegeneratedinmanylocationsinabuffer.Onetypicalplaceisthedrainto back-gatejunction.Owingtoniteresistancebetweentransistor’sback-gateandnearbysubstrate tie,noiseisinjectedbytransistorstoothercircuitsthroughtheback-gatenode.Therefore,itis importanttoproperlymodelthesubstratenetwork.Figure6-10depictsthesetupformeasuring 00.30.50.81.11.41.61.92.22.42.7 Frequency (GHz) -100 -80 -60 -40 -20 0dBm Figure 6-9.Simulation (solid line) and measurement (circle symbols) of power line noise buffer (A2) LNA ground plane (A1) port1 port2 port2 port1 50 W Figure 6-10.Themeasurementsetupformodelingtheback-gatenetworkoftransistorsinthe buffer. A1A2

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124 theback-gatenetworkofthetransistorsinthe8-stagebuffer.TheareaA1istheLNA’sground planeandtheA2istheareaofbuffercircuit.TheLNAgroundplaneisusedasanoisereception areatocollectthebuffernoise.Thisgroundplaneisametalgroundplaneseparatedfrombuffer ground.Toextracttheback-gate-to-groundresistance,two-portmeasurementisperformed betweentheback-gateoftransistor(port1)andLNAgroundplane(port2).Themeasured S-parameters(darklines)andsimulatedS-parameters(graylines)areshowninFigure6-11and theextractedcircuitmodelisshowninFigure6-12.Accordingto,theback-gate-to-ground resistanceisaround3.5 W .A350-nHinductorisaddedinserieswiththeresistortomodelthelong groundmetallineofbuffer.Inaddition,increaseswithfrequency,whichisduetothe capacitivecouplingbetweenthebuffer’spowerlineandLNAgroundplane.A100-fFcapacitoris extracted from the and added to simulate the effect. S11 S 21 S 21 012 3 Frequency (GHz) -45 -40 -35 -30 -25dBS21 0123 Frequency (GHz) -10 -8 -6 -4 -2 0dBS11 0123 Frequency (GHz) -10 -8 -6 -4 -2 0dBS22 Figure 6-11.Measured S-parameters (dark lines) and simulated S-parameters (gray line)

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125 6.3 Substrate Modeling Inthiswork,thesubstrateismodeledwithalumped-resistornetworkincludingaresistor meshandsubstrateports.TheresistorscanbeobtainedbyDCmeasurement(orSubstrateStorm simulation)asmentionedinChapter2.Choosingpropersubstrateportsiscritical.Inabuffer, VDD 3.5 W 100fF 200 22 350pH LNA ground plane ( A extracted substrate model Port 1 Port2 Figure 6-12.Extracted circuit model LgVg2LdVdd(LNA) LsM1M2C1C2out Cb2 in output matching out Vdd(buffer) LNA on-chip gnd buffer on-chip gnd 0.2 nH substrate model Figure 6-13.Conceptual model of the DC substrate model in

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126 theseportsrepresentnoiseinjectionnodeswhileinaLNAtheseportsrepresentnoisereception nodes.Theycouldbetransistorbackgates,signalinputoroutputpads,N-wellsandothers. Figure6-13conceptuallydepictsthesubstratemodelthatcanbeusedtostudythenoisecoupling betweenanLNAandabuffer.Iftoomanynodesareincluded,themeasurementscanbecome tedious.Somesubstrateportswhichareexpectedtocontributesmallernoisesuchassmallsize transistorsinthe8-stagebufferareneglected.Onlythoseinthelasttwostagesofthebufferare usedforsubstrateresistornetworkextraction.Inaddition,theportforinductorPGS(patterned groundshield)isneglectedduetotworeasons.First,thecapacitorbetweeninductormetaland PGSissmallsuchthatmostnoisereceivedbyPGSisshortedtoon-chipground.Second,areaof PGSisbigaswellasitssubstrateport.Abigareasubstrateportwithlowerresistivityeffectively changesthesubstrateresistanceoforiginalcircuit.Therefore,theinductorsubstrateportsare intentionally avoided. Thesubstrateresistornetwork(DCsubstratemodel)extractedbyDCmeasurementare listedinAppendixAppendix.Thisnetworkcontainsalargenumberofresistors.Itisdifcultto knowwhichcouplingpathsarethecriticalones.Withthehelpofacircuitsimulator,themost noisyandnoise-sensitivenodesinthesubstrateareexplored.ThesearethebackgateofthetransistorsinthebufferandLNAs.ThesimpliedsubstratemodelofthesecouplingpathsforNMOS and PMOS LNA are shown in Figure6-14 and 6-15. Inthesimpliedmodels,theresistancebetweenbuffer’sandtwoLNA’son-chipgroundis smallbecauseLNA’sandbuffer’son-chipgroundareconnectedthroughanon-chipmetalground plane.Owingtothesheetresistanceofmetal,thereisaniteresistancebetweenthetwoon-chip grounds.Theresistancebetweenbufferback-gateandbufferon-chipgroundis4 W whichisclose totheresult(3.5 W )reportedintheprevioussection.Theresistancebetweenback-gateofM1

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127 transistorandtheLNAon-chipgroundisabout40 W whichisabouttwicelargerthanthevalue (16 W )directlymeasuredbetweenthetwonodesintheteststructure.However,ifconsidering neglectingthe2.4 W resistance,if40 W isshuntedbythe34 W theresistancebetweentransistor Lg Vg2 Ld VDD(LNA) Ls M1 M2 C1 C2 RL output Cb2 input output VDD(buffer) Buffer NMOS LNA 403 4 2.4 40 34 36 LNA on-chip gnd buffer on-chip gnd 0.16 nH substrate modelFigure 6-14.A simplied substrate model for NMOS LNA test structureinput output VDD(buffer) Buffer 4.7K 3.6 4.3 150 340 85 buffer gnd Lg V2LdVDD(LNA) Ls M1 M2 C1 C2 RLoutput Cv2 input 2.5pF 0.2nH 60pF 1.5p 9 64 18 LNA on-chip gnd PMOS LNA N-well pad Figure 6-15.A simplied substrate model for PMOS LNA test structure

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128 back-gateandbufferon-chipground,thentheequivalentvalueis18 W whichiscloseto16 W .For PMOSLNA,theresistanceis150 W whichislargerthanthatofNMOSLNA.InPMOSLNA, thisresistorrepresentstheresistancebetweentheN-wellandLNAon-chipground.Usually,the bodytiesofNMOStransistorsareveryclosetothetransistor’sactiveregionsasshownin Figure6-16sothatthepowerlossthroughthesubstratecanbereduced.InPMOStransistors,the bodytiesarelocatedintheN-wellandthenumberofp-typesubstratecontactsoutsidetheN-well arereduced.ReducingthenumberofsubstratecontactsoutsideN-wellincreasestheresistance betweenN-wellandLNAon-chipgroundandtheresistancebetweenN-wellandtransistor back-gate in buffer. TheDCsubstratemodelisapurelyresistivemodelthatrepresentthesubstrateresistance network.However,intheSection6.2.3capacitancebetweenthebufferpowerlineandtheLNA groundplanealsocontributesthecoupling.Thisindicatesthatthecouplingpathsarenotonly throughthesubstratebutalsothemetaltracesbetweentheLNAandbuffercircuits.Toinvestigate theeffects,thepackagecouplingincludingcapacitiveandinductivecouplingisdiscussedinSection 6.4. substrate tie N-well substrate tie Figure 6-16.transistor layouts in PMOS and NMOS LNAs.(A)NMOSLNAtransistor layout. (B) PMOS LNA transistor layout. (A) (B) NMOS

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129 6.4 Package Modeling 6.4.1Inductive Coupling Noisecouplesnotonlythroughresistivecouplingbutalsoinductivecoupling.Inductive couplingisaphenomenonresultingfromtheFaraday’slaw.Ifmagneticuxthroughaconductor suchaswiresisnotconstant,acurrentcanbeinducedinaconductororonasurface,which meansthatnoisecanbeinduced.Magneticuxcanbegeneratedinvariouspartsofthebuffer suchaspowerandgroundlines.ThisinducescurrentinmetaltracesofLNAcircuit,bondwires orevenmetaltracesonaPCB(printedcircuitboard).Tomodeltheseeffects,thecouplingcoefcientsareextractedbyFastHenry.Byemployingthesecalculatedcouplingcoefcientsincircuit simulations,inductivenoisecouplingcanbeproperlyestimated.Thecouplingbetweenthe on-chippowerlineofbufferandbondwiresturnedouttobecritical.Toobservetheimpactof couplingbetweenon-chippowerlineandbondwiresonLNAperformance,thebuffercircuitis separatedfromtheLNA(Figure6-17)byhorizontallycuttingonechipintotwopieces.Sincethe substratesaredisconnectedandmountedonaPCboardgroundplane,thecouplingthroughsubstrate is ignored. 220 m m on-chip power line of buffer bond wires Figure 6-17.The LNA and buffer with separated substrates.(A)220m mseparation.(B) 100m m separation. 100 m m(A) (B)

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130 Inthemeasurementsetup,chip-on-boardtechnologyisusedforpackaging.TheinputsignalofbufferisdirectlyprovidedbyACprobeinsteadofbondwires.SothebufferisdirectlyconnectedtotheLNAon-chipground,notPCBgroundsothatthegroundbounceproblemis reduced.TheLNAisbiasedthroughbondwirestometaltracesonthePCBandtheoutputof LNAisconnectedthroughtheon-boardtransmissionlinesandanSMA(SubMiniatureversionA) connectors to a spectrum analyzer. Figure6-18showsthemeasuredspectraatLNAoutputwhenLNAisbiasedandbufferis workingat47MHz.ThegraylineistheoutputspectrumofLNAwhenthesubstrateofLNAand bufferareconnected.Thedarkblacklineisoutputspectrumwhenthesubstratesareseparatedby 10 m m.Thespurpowerlevelsforthetwocasesaremostlywithin10dB.Forthosespursclosethe LNAworkingfrequency(2.2GHz),thedifferencesaremuchsmaller.Themeasurementresults demonstratethatcouplingthroughair(notsubstrate)issignicantandcannotbeignored.Tofurtherstudythecouplingphenomena,thecouplingnoiseismeasuredfordifferentseparations betweenthebufferandLNA.Figure6-19showstheaveragedspurpowerlevelatLNAoutputver1.72.22.7 Frequency(GHz) -120.0 -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 -50.0dBm Figure 6-18.MeasuredspectraatLNAoutputwhensubstratesofLNAandbufferare connected (gray line) and separated by 10 m m (dark black line).

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131 susdifferentseparationwhenthebufferisworkingat47MHz.Theaveragedspurpoweristhe geometricmeanofthepowerlevelsofallthespursbetween1.7and2.7GHz.Thereasonfor usingthegeometricmeaninsteadofarithmeticmeanisbecausethatspectralpowerisdenotedin dBm,alogarithmicscale.Wheninarithmeticmeanisused,theresultisdominatedbythedifferenceinspurswithlargestpowerlevelswhichuseofthegeometricmeancapturesthecontributionsfromthespurswithlargerandsmallerpowerlevelsequally.InFigure6-19,theaverage powerat10m mseparationisabout-76dBmwhichis4-dBbelowthatofnormalsubstrate(no-cut substrate).Onemayarguethatthe4-dBdifferencecouldbethecontributionfromsubstrate. Again,bylookingatFigure6-18carefully,thespurpowerlevelsarecomparablearoundtheLNA workingfrequency(around2.2GHz).Thismeansthataround2.2GHzthedifferenceismuch smallthan4dB.Astheseparationbecomesbigger,thecouplingnoisegraduallydecreases.However,evenat1000m mseparation,averagenoisepowerisstillsignicantandcannotbeneglected. The above measurement indicates that substrate is not the only dominant coupling mechanism. Ifthesubstrateisnottheonlydominantcouplingpath,whatareotherpossiblecoupling paths?Toanswerthequestion,inductiveandcapacitivecouplingsareconsidered.Forinductive 02004006008001000 Separation ( m m) -84.0 -80.0 -76.0 -72.0dBmNMOS LNA output spectrum (47MHz) no cut 10 m m 100 m m 200 m m 1000 mmFigure 6-19.AveragedspurpoweratLNAoutputwithrespecttodifferentseparationbetween LNA and buffer

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132 coupling,inductanceandcouplingcoefcientaregovernedbythesizeoftheinductors.Looking atthebuffercircuit(Figure6-17),thebiggeststructureistheon-chippowerline.IntheLNA,the biggestonesarethebondwires.Inductivecouplingshouldmostlyoccurbetweentheon-chip powerlineandoff-chipbondwires.Thiseffectiscarefullyconsideredinsystemsimulationsand will be discussed in Section 6.5. Intheaboveexample,noisecannotpropagatesthroughthesubstrate.However,itispossiblefornoisetocouplebetweenthetwosubstratesidewalls.Toinvestigatetheproblem,twosimulationsarecompared.Intherstsimulation,thesubstratesofNMOSLNAand8-stagebufferare connectedtogether(normalcircuitstructure)anditscircuitschematicisshowninFigure6-14.In thesecondsimulation,thetwosubstratesareseparatedby10 m m(Figure6-20).Cs1(300fF)is usedtomodelthecapacitorbetweenLNAandbuffersubstratesidewalls,whichiscalculated LgVg2LdVDD(LNA) LsM1M2C1C2RLoutput Cb2 input output VDD(buffer) Buffer NMOS LNA 403 4 2.4 40 34 36 LNA on-chip gnd buffer on-chip gnd 0.16 nH substrate modelFigure 6-20.ThecircuitmodelforNMOSLNAand8-stagebufferwhilethesubstratesare separated by 10 m m. 300 fF 100 fF Cs1Cs2

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133 usingtheequationforaparallel-platecapacitor(C= e *A/Dwhere e ispermittivityconstant,Ais area,andDisseparation).Thematerialbetweentwosubstratesidewallsisairso e 0of 8.85e-14(F/cm)isused.Areaofthesubstratesidewallisaround400x850 m m^2andseparationis 10 m m.Thecapacitanceisaround300fF.Cs2isthecapacitancebetweenbufferon-chipground andLNAon-chipground.Inthebufferlayoutthepowerandgroundlinemetalshavethesame area,sothesamecapacitance(100fF)inFigure6-12isusedhere.Thesimulationresultsshow thatLNAoutputspurpowerlevelsinthesecondsimulationis~26dBsmallerthanthatintherst simulationatthefrequenciesbetween1.7and2.7GHz.Theresultshowsthatcouplingbetween two substrate side walls is negligible. 6.4.2 Capacitive Coupling Possiblepathsforcapacitivecouplingarethroughsubstrateandlargemetalstructuresin circuits.However,atfrequenciesaroundfewgigahertz,capacitivecouplinginasubstrateisusuallyignoredexceptthen-wellcapacitor(Figure2-11).Then-wellcapacitorwillbeconsideredin thePMOSLNAandincludedinthesubstratemodel.Theotherpossiblepathsarethroughthe metalstructuresinthecircuits.Figure6-21(A)showsdiephotooftheNMOSLNA.Themostsignicantcapacitivecouplingpathsarebetweenthelongstrip-shapedmetalpowerlineofbuffer andLNAmetalgroundplaneandpowerlinesandthesubstrateareabeneaththepowerlines. Othermetallinearenotconsideredbecausetheirareasaremuchsmaller.ThecircuitrepresentationofthecapacitormodelingisdepictedinFigure6-21(B)whereCaisthecapacitorbetweenthe bufferpowerlineandLNAgroundplaneandCbisbetweenthebufferpowerlineandsubstrate node.Cb(140fF)iscalculatedfromvendor’sprocessinformationandCa(100fF)istheextracted value in Figure6-12 (A).

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134 6.4.3 Summary of Model and Grounding Issues AblockdiagramhasbeenshowninFigure6-1.Figure6-22and6-23(A)showtheinductivecouplingmodelofNMOS/PMOSLNAsandbufferinpackagemodel.Theinductorsinthe packagearelabeledinitalic.TheblockdiagramsalsoshowtheconnectionsbetweentheLNAs, andbuffer(Figure6-23(B)and(C)).Theinductorvaluesandcouplingcoefcientsusedinthe blockdiagramscanbefoundinAppendixAppendix.Theblockdiagramofsubstrateisshownin Figure6-23(D).ThemodelsforcapacitivecouplingisinFigure6-21(B).Groundofbufferis referredtotheon-chipgroundandLNA’son-chipgroundisconnectedtothePCBground(instrumentground)throughmultipledownbonds(0.2nH)(Figure6-2).NMOSandPMOSLNA on-chipgroundisconnectedtothebuffergroundthroughmetallinesonchipandtheresistance arearound2.4and4.3 W ,respectively(Section6.3).PCBandLNAon-chipgroundsaredenoted in different symbols as shown in the up-right corner of Figure6-22. Inthisresearch,twopackagingmethodsareused.AnLNAchipdirectlysittingonaPCB willbecalleda“chip-on-boardLNA”andanLNAsittinginanRF0248-pinpackage[Zen]will LgV2Ld VDD(LNA) Ls M1 M2 C1 C2 output input output VDD(buffer) Buffer NMOS LNA LNA on-chip ground buffer on-chip ground 0.2nH Substrate model input Figure 6-21.Capacitive coupling.(A)Adiephotoshowsthepossiblepathforcapacitive coupling and (B) its circuit model.CbCaCb long strip-shaped power line LNA metal ground plane

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135 becalleda“packagedLNA”.Figure6-24andFigure6-25showthephotosofchip-on-boardand packagedLNAs.TheonlydifferencebetweenthesetwoLNAsinthesystemmodelingisthat RF0248-pinmodelisincludedonlyinthepackagedLNAs,whichisnotusedinforthe chip-on-board LNAs. LgLdVDDLsM1M2C1C2Out In input matching output matching Lsbw LVDD Lgbw LV2 LdbwLc2bw Lout In VDD 20 pF 1 m F OutLbfpl Lbfbwor Ldcprobe M3 M4Figure 6-22.Inductive coupling model in the package model.(A)PMOSLNAand(B)buffer inductive coupling models. (A) (B) PCB ground on-chip ground pad buffer gnd CbyCby LdVDDLsbwM1M2C1C2Out output matching input matching Lgbw In Ldbw LV2 Lg Lc2bw Lout LgbwLV2LoutLdbwLsbwLc2bw LbfplLbfbwpackage model (coupling efficient)Figure 6-23.LNA Inductive coupling model.(A)NMOSLNAinductivecouplingmodel. Block diagrams of (B) PMOS and (C) NMOS LNA package models. LgbwLV2LoutLdbwLsbwLc2bw LbfplLbfbwpackage model (coupling efficient) PMOS LNA NMOS LNA LVDD(A) (B) (C) PCB ground on-chip ground pad

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136 6.5 Noise Coupling Mechanisms in LNAs ThenoisecouplingissimulatedusingCadenceSpectreRF.Theresultsshowedthatmost ofnoiseinductivelycouplesfromthebufferon-chippowerlinesandbondwirestoLNAbond wires.Theformercontributesmostlytothehigh-frequencynoiseandthelattercontributesmostly tothelow-frequencynoiseatLNAoutput.AsdiscussedinSection6.4.1,measurementhasshown thatsubstrateisnottheonlydominantcouplingpath.ThesimulationstudiessuggestthatinducFigure 6-24.Chip-on-board (A) PMOS and (B) NMOS LNAs LbfbwLbfpl LgbwLv2LdbwLoutLc2bw Lsbw In OutLesd(A) PMOS LNA (B) NMOS LNA LVDDLgbwLv2LdbwLoutLbfbwLbfpl Lc2bw Lsbw InOutLesd LVDDLgbwLv2LdbwLoutLbfpl In OutLesdLc2bw Lsbw Lbfpl LgbwLv2LdbwLoutLc2bwLsbw In OutLesd Figure 6-25.Packaged (A) PMOS and (B) NMOS LNAs (A) PMOS LNA (B) NMOS LNA

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137 tivecouplingismuchmoresignicant.Asamatteroffact,thesubstratecouplingissmallandcan beneglected.Inthissection,basedonsimulation,noisecouplingmechanismathigh-frequency range(1.7-2.7GHz)(normalLNAworkingfrequency)andlow-frequencyrange(0.1-1.7GHz) will be discussed. 6.5.1Noise at NMOS LNA Output Fourtypesofsamplesaremeasured:packagedandchip-on-boardPMOSandNMOS LNAs.Figure6-26showsthesimulated(circlesymbols)andmeasured(solidlines)outputnoise spectraofchip-on-boardNMOSLNA.Twomainlobescanbefoundataround0.1-1.7and1.7-2.7 GHz.Atthehigherfrequencyrangefrom1.7to2.7GHz,noisecouplingiscausedmainlyby buffer’son-chippowerline(LbfplinFigure6-24).Thenoisegeneratedonbufferon-chippower lineresultingfromswitchinginductivelycouplestoLNAinputbondwire(Lgbw).Thenoiseis furtherampliedbythegainstage,showingupatLNAoutput.DuetothegainofLNA,thepower levels of noise spurs are peaked at around 1.7-2.7GHz. Atthelowfrequencyrange(0.1to1.7GHz),thenoiseismainlyfromthebuffersupply bondwires(Lbfbw).Onceagain,duetoswitching,noiseisgeneratedalongbuffersupplybond Figure 6-26.Chip-on-board NMOS LNA output noise spectrum. 00.511.522.5 Frequency (GHz) -130 -110 -90 -70 -50dBm

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138 wires.ThisnoisecouplestoLNAdrain(Ldbw),outputbondwires(Lout),anddown-bondwires (Lc2bw)ofoutputmatchingnetwork,eventuallyappearingattheLNAoutput.Unlikethehigh-frequencynoise,thelow-frequencynoiseisdirectlycoupledtotheLNAoutput.Thenoisecoupled throughtheinputstageofLNAissmallatlowfrequencyrange,becausethegainissmallerinthis frequencyrange.Inaddition,duetothefactthatthelow-frequencynoisecomesfromthebuffer bondwirenoise,thefrequencydependencefortheenvelopofspurlevelsaresimilartothatofthe bufferpowersupplynetworkcomposedofabondwire(Lbfbw)andoff-chip/on-chipbypass capacitors(C1andC2)(Figure6-6).Bufferon-chippowerlinenoisealsocontributestothe low-frequencynoise.However,thecontributionissmall.Becausetheinductance(0.55nH)of on-chippowerlineislowerthanthatofthe3.2-nHbufferoff-chipsupplybondwireinductance. Figure6-27showsthemeasurementresultsofpackagedNMOSLNA.ThenoisecouplingmechanismoftheLNAissimilartothechip-on-boardLNA.Instead,thelowfrequencynoiseiscontributed by DC probe inductive coupling not bond wire coupling. Figure 6-27.Packaged NMOS LNA output noise spectrum. low-frequency peak high-frequency peak 00.511.522.5 Frequency (GHz) -130 -110 -90 -70 -50dBm

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139 6.5.2 Noise at NMOS LNA Input Figure6-28showsthenoisespectrumattheinputofchip-on-boardandpackagedNMOS LNAs.SimilarlytothenoiseattheNMOSLNAoutput,twomainlobesataround0.1-1.7and 1.7-2.7GHzarepresent.Basedonthesimulations,thehigh-frequencynoiseiscausedbythecouplingbetweenthebufferon-chippowerline(Lbfpl)andLNAinputbondwire(Lgbw).Forthelow frequencynoise,thecouplingisviathepathbetweenbuffersupplybondwire(Lbfbw)andLNA inputbondwire.Comparingthesimulationswithmeasurements,simulatednoiseatfrequencies above2GHzareabout5-10and20dBlargerthanmeasuredoneinthechip-on-boardandpackagedNMOSLNAs.ThemismatchisprobablyduetotheimperfectcircuitmodelofLNAinput matching network including off-chip components and PCB model. 6.5.3Comparison of PMOS and NMOS LNA Figure6-29showsthenoiseatoutputandinputofPMOSLNA.Themeasuredspectraare similartothatofNMOSLNAcounterpart.Thedifferenceismagnitudesofspurs.Insimulations, couplingmechanismsforhighandlowfrequencyrangenoisearesimilartothosediscussionin NMOSLNA.ToconvenientlycomparethemagnitudeofnoisespurpowerlevelsaroundtheLNA Figure 6-28.NMOS LNA input noise spectra.(A)Chip-on-boardNMOSLNAinputnoise spectrum. (B) Packaged NMOS LNA input noise spectrum. (A) (B) 00.511.522.5 Frequency (GHz) -130 -110 -90 -70 -50dBm 00.511.522.5e Frequency (GHz) -130 -110 -90 -70 -50dBm

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140 operatingfrequency(1.7-2.7GHz),theaverageoutputspurpowerlevelsarecalculatedandshown inTable6-1.Thesimulatedaveragespurpowerlevelsareabout1.5-4dBlowerthanthemeasured averagepowerlevels.Thisindicatesthatcouplingisstrongerinmeasuredcircuits.Forboththe chip-on-boardandpackagedLNAs,simulationsandmeasurementsshowthatNMOSLNAshave higheraveragespurpowerlevelsthanPMOSLNAs.ThedifferencesbetweenNMOSandPMOS LNAsforchip-on-boardandpackagedversionsare6.3and9.8dB,respectively,whichareclose to7.1and11.6dBinmeasurements.Ifthegaindifference5dB(Figure4-3)issubtractedfrom thespurpowerdifferences,NMOSLNAsstillhave1.3and4.8-dBhigherforthechip-on-board andpackagedcases.ThisismainlyduetothefactthatPMOSLNApowersupplybondwire (LVDD)providestheshieldingeffecttothePMOSLNAinputbondwire(Lgbw)(Figure1-14). ThePMOSLNALVDDandinputbondwire(Lgbw)areparalleltoeachother.Oneendofthe LVDDisconnectedtoaACgroundthroughabypasscapacitorandtheotherendisconnectedto thesameACgroundthroughaon-chipbypasscapacitorandadown-bondwire(Lsbw) (Figure6-22).Sothenoisecouplingfromthebufferpowerline(Lbfpl)tothePMOSLNAinput bondwirecanbereducedaswellastheoutputspurpowerlevels.Theaveragespurpowerlevelof Figure 6-29.Chip-on-board PMOS LNA output and input noise spectra.(A)Outputnoise spectrum. (B) Input noise spectrum. 00.511.522.5 Frequency (GHz) -130 -110 -90 -70 -50dBm 00.511.522.5 Frequency (GHz) -130 -110 -90 -70 -50dBm (A) (B)

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141 chip-on-boardPMOSLNAishigherthanthatofpackaged.Becauseforchip-on-boardPMOS LNA, Lsbw is longer, coupling is stronger (Figure6-24). Theabovediscussionsarebasedonthesimulationsandshouldbefurtherveriedbymeasurements.Nevertheless,thesesimulationshaveshownthatthecouplingbetweenthebuffer on-chipbondwireandLNAinputbondwireiscritical.ThecouplingdegradestheLNAperformance and must be avoided. 6.5.4 Simulation with Substrate Model Only Ifonlythesubstrateeffectisconsidered,thenthesimulatednoisespurpowerlevelis muchsmallerthanthemeasurement(Figure6-31).Thecirclesandsolidlinesarethesimulated andmeasurednoisespurs,respectively.Mostofthesimulatednoisespurs(circles)areabout20 dBlowerthanthemeasuredones,whichindicatethatthesubstratecouplinghasnegligiblecontriTable 6-1.Average output noise power of LNAs NMOS LNA PMOS LNA measurementsimulationmeasurementsimulation chip-on-board LNA-72.0-75.3-79.1-81.6 packaged LNA-72.2-76.2-83.6-86.0 Figure 6-30.Packaged PMOS LNA output and input noise spectra.(A)Outputnoisespectrum. (B) Input noise spectrum. 00.511.522.5 Frequency (GHz) -130 -110 -90 -70 -50dBm 00.511.522.5 Frequency (GHz) -130 -110 -90 -70 -50dBm (A)(B)

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142 butioncomparedtotheothercouplingmechanisms.ThemeasurementinFigure6-18corroboratesthesimulationresults.EvenwithoutasharedsubstrateforbufferandLNA,thenoise coupling (around working frequency) can still be similar to those with shared substrates. Basedonabovediscussions,thesubstrateofapackagedLNAinpresentofbuffer’snoise maynotbethemostsignicantpathfornoisecoupling.Theothercouplingpathsuchasthe inductivecouplingdegradesthenoiseperformanceofLNAmuchmore.Thisworkhasshownthat modelingthesubstrateandpackagearenotsufcienttoaccountfornoisecoupling.Theinteraction between the package and on-chip structure must be included. 6.6 Measurement Variations Itisimportanttounderstandthevariationsintheinjectednoiseandthenoisecouplingto theLNAoutputinordertoquantitytheuncertaintyofnoisemeasurements.However,itisdifcult todirectlymeasuretheinjectednoiseduetothefactthatnoiseisinjectedintoanLNAviaso manydifferentpaths,addinganextrapad/loadformeasurementsineachpathisnotpractical. Instead, buffer output power is monitored. Figure 6-31.Simulatedversusmeasuredoutputnoisespectraforpackaged(A)NMOSand (B) PMOS LNAs. 1.72.22.7 Frequency (GHz) -140 -120 -100 -80 -60dBm 1.72.22.7 Frequency (GHz) -140 -120 -100 -80 -60dBm (A)(B)

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143 Table6-2summariesthevariationofaveragebufferoutputspurnoisewhenbufferis workingat47MHz.FouridenticalbuffersintwoPMOSandNMOSLNAteststructuresaremeasuredandeachofthemaremeasuredatvedifferenttimeinstantsothattotalof20samplesare taken.Foreachsample,averageandstandarddeviationofspurpowerlevelsbetween1.7-2.7GHz arecalculated.Thestandarddeviationandthedifferencebetweenmaximumandminimumpower ofthese20samplesis0.56and2dB.IfGaussiondistributionisassumed,theprobabilityofsampleshavingdeviationgreaterthan1.2dB(twiceofthedeviation)islessthan2.28%,meaningthat most of buffer output power should have the variation less than1.2 dB. Table6-3showsthevariationofLNAoutputnoisepower.Fivemeasurementsaretakenat differenttimesforeachNMOSandPMOSLNA.Themaximumdeviationamongthemis0.63so twice of the deviation is1.3 dB. 6.7 Summary Inthischapter,noisecouplingmechanismsbetweentheLNAsand8-stagebufferhasbeen discussed.The8-stagebufferasanoisegenerationcircuithasbeencharacterized.Powerline noiseandtheback-gateresistanceoftransistorsinthe8-stagebufferhavebeeninvestigated.DC Table 6-2.Variation of 20 measurements in 4 different samples Average output noise of buffer between 1.7-2.7 GHz 47 M average buffer output spur power (dBm)-43.6 Power (dBm)-43.0 ~ -45 standard deviation (dB)0.56 Table 6-3.Variation of 5 different measurements in each PMOS and NMOS LNA PMOS LNANMOS LNA average LNA output power (dBm)-79.4-68.4 max.-min. power (dBm)-79.0~-80.0-67.6~-69.4 standard deviation (dB)0.390.63

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144 substratemodelshavebeenextractedfrommeasurementsandpackagemodelincludinginductive andcapacitivecouplingshasbeenextracted.Finally,noisecouplingsimulationshavebeenperformedandthenoisecouplingmechanismsintheLNAsand8-stagebufferhavebeenunderstood. Inthe8-stagebuffer,parasiticgateresistanceoftransistorsincreasethebufferdelay.The resistance is considered in the simulation to increase the model accuracy. Thesupplybounceiscausedbythesupplybond-wireinductance.Duetotheltering effectofthesupplynetworkincludingthebondwireandon-chipandoff-chipbypasscapacitors, andcurrentwaveformsofinverters,apeakandadipat600MHzand1.8GHzareobservedinthe spectrum of supply line. ThesubstrateisnotthedominantcouplingpathbetweentheLNAsand8-stagebuffer. Separating the substrates of buffer and LNA has minor impact on the coupled noise. Inductivecouplingisthemajorcouplingpath.ThenoisespursintheLNAoutputspectrumaremainlyfromthetwonoisesourcesinbuffer:bufferon-chippowerlineandoff-chipbond wires.Thenoisefromtheon-chippowerlinemostlydeterminesthehigh-frequencynoisespurs andthenoisefromtheoff-chipbondwiresdeterminesthelow-frequencynoisespursattheLNA output.Thehigh-frequencynoisegeneratedintheon-chippowerlineinductivelycouplestothe LNAinputbondwire.ThisnoiseisampliedbythegainandappearsupattheLNAoutput.The low-frequencynoisegeneratedfromtheoff-chipbondwirecouplestotheLNAinputbondwire and bond wires of output matching network, appearing at both the input and output of LNA. Themeasurementvariationisquantied.Thevariationforaveragebufferoutputspur powerfrom1.7to2.7GHzislessthan1.2dB.ThevariationofaverageLNAoutputpowerisless than1.3dB.

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145 Thedesignissuesforreducingnoisecouplingaresuggested.Thelongstrip-shapedpower/ groundlineswhichcanincreasesinductiveandinductivecouplingsshouldbeavoidedindigital circuits. Second, LNA input bond wires should be placed far away from the digital circuits.

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146 CHAPTER 7 SUMMARY AND FUTURE WORK 7.1 Summary 7.1.1 PMOS LNAs and Mixers Fabricated in a 0.18m m Foundry CMOS Process InChapter3,2.4-GHzNMOSandPMOSLNAsandmixersfabricatedina0.18m m foundryCMOSprocessarepresented.MeasurementsshowthatPMOSLNAshaveabout3dB lowergainand~1dBhighernoisegurethantheNMOSLNAs.PMOSmixershaveabout3dB lowergainandcomparableorslightlylowernoisegurethanNMOSmixers.InadditionPMOS mixerhavebetterIIP3andlower1/fnoise.Moreimportantly,theperformanceofPMOSLNAs andmixersaresuitableforBluetoothapplications.UsingPMOSLNAandmixerforRFapplications is feasible. 7.1.2 Degradation of PMOS and NMOS LNA Performance by Digital Noise Coupling InChapter4,performanceofPMOSandNMOSLNAswasmeasuredinthepresenceof digitalnoiseofana8-stagebuffer.ThenoiseinPMOSandNMOSLNAsincreasessignicantly. Thenoiseincludesspursandwhitenoisegeneratedfromthebuffer.ThenoisegureofPMOS LNAhaslessdegradationthanthatofNMOSLNAwhenthebufferisworkingat13and47MHz. Thepowerlevelsofspursareabout10-15dBsmallerandthenoiseguredegradationdueto whitenoiseis0.2-0.4dBsmaller.ThisindicatesthatthePMOSLNAhasbetternoiseimmunity thantheNMOSLNA.ComparingthemeasurementresultsforseparatedandsharedgroundconnectionfortheLNAandbuffer,thenoiseinjectiontoLNAswithsharedgroundishigherthanthat with separated ground. 7.1.3 Dependence of Output Noise of the 8-stage Buffer on the Input Frequency In Chapter 5, Flicker and white noise in a transistor has been briey reviewed.

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147 Theoutputnoiseoorof8-stagebufferdecreasesathigherinputfrequencies,whichisdue tothefactthatathigherinputfrequenciesriseandfalltimesofthersttwoinverterstagesare shorter.Shorterriseandfalltimesreducethenoiseinjectedfromtheinputsignalandbufferoutput noise. Finally,asimplemodelispresented,describingthebehaviorofoutputwhitenoiseinan inverterwithacapacitiveload.Thismodelisbasedonalinearperiodicallytime-varying(LPTV) systemwithinputnoisewhichiswide-sensestationary(WSS).Themodelsuccessfullypredicts thattheoutputnoisevoltagePSDisinverselyproportionaltotheperiodofinputfrequencywhen theriseandfalltimesoftheinputsignalarekeptthesame.Outputnoiseisproportionaltoacubic of rise and fall times. 7.1.4 Noise Coupling Mechanism of LNAs InChapter6,noisecouplingmechanismstoPMOSandNMOSLNAshavebeenexplored. First,thenoisegenerationcircuit,8-stagebuffer,hasbeencharacterized.Inthebufferoutputnoisespectrum,spurpowerdecreasesfasterathigherfrequencies.Thisisduetothelonger propagationdelaytimeofinverterscausedbytheparasiticgateresistanceinthelaststageof 8-stagebuffer.Thesupplybounceinthe8-stagebuffercausedbytheswitchingoftransistorsand the nite supply bond-wire inductance and bypass capacitors is investigated. Second,noisecouplinghasbeenmeasuredwhilethesubstratesofLNAand8-stagebuffer areseparated.Themeasurementsshowthatnoisecouplingissignicantevenwhenthesubstrates ofbufferandLNAareseparated.ThisindicatesthatthesubstrateisnottheonlydominantcouplingpathbetweentheLNAsand8-stagebuffer.Theinductivecouplinghasbeenshowntobethe most signicant coupling path by simulation studies.

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148 Third,simulatedspursattheinputandoutputofLNAhavebeencomparedtothemeasurements.TheLNAspursaremanlyfromtwonoisesourcesinthebuffer:on-chippowerline andoff-chipbondwire.TheOn-chippowerlineandoff-chipbondwirearethehigh-frequency andlow-frequencynoisesourcesofLNAs.Thenoisegeneratedbyon-chippowerlinecouplesto theinputbondwireofLNAandisampliedbytheLNAandnallyshowsupattheLNAoutput. Thenoisegeneratedbytheoff-chipbondwirepropagatestoLNAinputbondwireandoutput bondwire, directly appearing at the LNA output. Finally,themeasurementvariationshavebeenquantied.Theaveragebufferoutputspur powerfrom1.7to2.7GHzis-43.6dBmandthevariationislessthan1.12dB.Thevariationof average LNA output power is 1.2 dB. 7.2 Suggestions for Future Work Based on the work presented in this thesis, few future works are suggested. 7.2.1 Higher Output Spur Power Levels and White Noise of NMOS LNA ThemainnoisecouplingmechanismduetoinductivecouplingisdiscussedinChapter6. ThemeasuredoutputaveragespurnoisepowersofNMOSLNAsarehigherthanthatofPMOS LNAsduetoshieldingeffectprovidedbythePMOSLNApowersupplybondwire(LVDD)to inputbondwire(Lgbw).However,theexplanationsarebasedonthesimulationsandshouldbe veried by measurements. ThewhitenoisecharacteristicsofbufferhasbeenstudiedinChapter5.ThecoupledLNA whitenoisecanbealsosimulatedtoinvestigatethedegradationofLNAperformanceunderthe 8-stage buffer white noise coupling.

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149 7.2.2ContinuouslyExaminingNoiseIsolationCapabilityofN-wellinPMOSTransistorby Reducing Bond Wire Coupling ThemaincouplingmechanismbetweentheLNAsand8-stagebufferareinductivecoupling,notsubstratecoupling.Alongstrip-shapedpowerlineinabuffershouldbeavoided, becausealongstrip-shapedlineincreasesinductivecouplingtobondwires.Theseparation betweenthebufferbondwireandLNAinputbondwireshouldbeincreased.Thelengthofbond wiresshouldbereduced.Analternativewayistoreducethebodyties(guardrings)between LNAsandbuffer,whicheffectivelyreducestheresistancebetweenthebufferandbackgateof transistorsothatthesubstratenoisecouplingcanbeincreasedandthenoisereductionproperties of N-well can be investigated. Inaddition,thesizeofN-wellcontainingPMOStransistorsshouldbereducedtodecrease the junction capacitance, and noise coupling from the substrate. 7.2.3 Mixer Noise Modeling Amixerisanotherimportantbuildingblockinaradio.Thefunctionofamixeristodown orupconvertsignalssothatthesignalscanbeprocessedbybasebandreceiverortransmitted. Thenoisefromdigitalcircuitsshouldalsodegrademixerperformance.Forexample,ifspursgeneratedbyadigitalcircuitarelocatedattheimageofradiofrequency,thespurscanbedownconvertedtothesignalbandaroundtheintermediatefrequency.Thisdown-convertednoisedecreases sensitivityandreducessignal-to-noiseratioofareceiver.Agoodfrequencyplanningcaneliminatethespurnoiseproblem.However,thewhitenoisefromdigitalcircuitisdifculttoavoid. Instead, the coupling mechanisms must be understand and approaches to mitigate must be found.

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150 APPENDIX SUBSTRATE RESISTANCE MODELS AND PACKAGE MODELS TablesA-1andA-2arethelistsofresistorsinDCsubstratenetworksofNMOSand PMOSLNAs.FiguresA-1andA-2aretheschematicsofNMOSandPMOSLNAsandtheirsubstrate ports. In VDD 20 pF 1 m F OutLon_chip_pl Loff_chip_bw M8 M7(a) NMOS LNA (b) 8-stage buffer PCB ground on-chip ground pad b_l cbout cby_bfr M6 M5 b_m M4 M3 b_s 8-stage buffer substrate portFigure A-1.The circuit schematics and substrate ports of NMOS LNA and 8-stage buffer. Vg2LsM1M2C1 Lg In ls_pad rf_in cby_esd esd m1 m2 ld_pad C2Out Lc2bw Lout c2_pad c2 c1 rfout LV2 cby_m2 LdVDD pad Ldbw Lgbw

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151Table A-1.NMOS LNA substrate resistance.agndbls_padcrndesdem1fm2gcby_esdhld_padirfoutjc1kc2lcby_m2mc2_padnb_socby_bfrpb_lqb_mbls_pad317.69crn295.65954.24desd479.74.67K1.29Kem126,161.51K1.40K2.27Kfm237.892.16K1.94K2.92K198.39gcby_esd42.952.37K2.11K3.12K225.94289.73hld_pad387.669.14K7.41K10.68K1.93K2.50K2.45Kirfout574.4827.33K23.7K36.80K2.93K3.93K3.89K15.29Kjc11.22K50.7K47.22K76.41K5.98K8.28K8.47K62.2K41.70Kkc21.20K51.4K46.94K76.14K5.83K8.42K8.74K62.96K45.1K13.4Klcby_m242.182.4K2.29K3.7K236.2354.78370.893.22k4.67K8.78K8.48Kmc2_pad529.2523.4K22.6K38.66K2.81K4.15K4.29K31.96K12.7K30.61K17.96K4.18Knb_s1.48K78.38K75.27K125.6K9.04K13.22K14.14K116.9K156.1K295.9K257.7K14.64K35.78Kocby_bfr816.6525.80K28.49K51.08K4.03K5.93K6.26K47.85K43.15K79.34K61.28K6.15K2.05K2Kpb_l8.77713.776421.04K73.19105.72115.90967.31.44K2.55K2.45K113.221.18K2.37K1.14Kqb_m18.711.33K1.20K2.18K146.93207.17229.601.87K2.99K5.28K4.95K224.12.17K6.03K1.96K46.67rcbout1.18K6.79K12.5K29.79K5.07K7.10K7.69K44.11K84.81K139.6K141.6K7.26K46.33K157.6K27.87K1.91K758.66agnd: on-chip ground.bls_pad:bond pad of the source inductor.crn: rnput pad.desd:pad of esdem1:body of rf input transistor.fm2:body of the cascode transistor.gcby_esd: bypass cap. of esd.hld_pad:bond pad of the drain inductor.irfout:ouputpad.jc1:c1inFigureA-1.kc2:c2inFigureA-1.lcby_m2:bypasscap.ofthecascodetransistor.mc2_pad:bondpadofc2.nb_s:1thinvertorcellinthebuffer.ocby_bfr:bypasscap.ofthebuffer.pb_l:large invertor cell in the buffer.qb_m: middle invertor cell in the buffer.rcbout: load cap. in the buffer output.

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152Table A-2.PMOS LNA substrate resistance.agndbls_padsnwellcrndesdgcby_esdhld_padjc1irfoutkc2lcby_m2tcby_lnamc2_padulna_padnb_socby_bfrpb_lqb_mbls_pad 262.5snwell 123.512.3Kcrn 440.151.94K216.6desd 503.895.65K2.8K1.13Kgcby_esd 43.292.31K468.372.32K2.27Khld_pad 372.119.56K4.05K7.25K9.24K1.47Kjc1 1.19K49.3K15.4K48.5K72.5K7.16K50.3Kirfout 545.226.0K7.87K26.3K30.0K2.62K11.78K46.1Kkc2 1.12K49.2K17.5K49.6K79.4K8.3K57.7K1.35K45.7Klcby_m2 40.352.29K931.222.75K4.07K410.043.37K6.91K4.93K8.38Ktcby_lna 295.810.5K4.99K13.8K35K2.83K21.2K53.4K31.5K51.0K933.92mc2_pad 364.9317.9K7.58K20.3K37.6K3.34K24.4K31.2K13.4K19.5K2.85K18Kulna_pad 295.2714.8K6.59K17.1K26.7K2.79K21.5K46.3K25.2K41.6K2.34K15.2K1.03Knb_s 1.39K76.7K33.6K75.8K133K15.1K114.2K315K170K269K14.1K87.11K79.5K33.6Kocby_bfr 763.825.2K14.6K32.3K57.9K6.89K50.4K111.6K63.4K97.5K6.08K29.3K11.4K2.38K1.99Kpb_l 7.17661.5283.1666.951.11K124.28957.032.72K1.46K2.36K118.21756.54891.26722.672.88K1.16Kqb_m 16.11.2K554.931.26K2.29K246.821.87K5.4K2.91K5.09K234.541.52K1.87K1.47K5.6K2.14K46.0rcbout 1.07K6.29K12.8K15.2K36.8K8.3K48.1K156K89.7K149K7.82K31.0K51.0K39.1K195.K30.8K1.66K720.08agnd: on-chip ground.bls_pad:bond pad of the source inductor.crn: rnput pad.desd:pad of esdem1:body of rf input transistor.fm2:body of the cascode transistor.gcby_esd: bypass cap. of esd.hld_pad:bond pad of the drain inductor.irfout: ouput pad.jc1: c1 in Figure A-1.kc2: c2in Figure A-1.lcby_m2: bypass cap. of the cascode transistor.mc2_pad: bond pad of c2.nb_s: 1th invertor cell in the buffer.ocby_bfr: bypass cap. of the buffer.pb_l: large invertor cell in the buffer.qb_m: middle invertor cell in the buffer.rcbout: load cap. in the buffer output.snwell: nwell of PMOS transistors.tcby_lna: on-chip bypass cap. of the PMOS LNA.ulna_pad: bond pad of the on-chipbypass cap.

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153 LgLdVDDLsM1M2C1C2Out In Lsbw LVDD Lgbw LV2 LdbwLc2bw Lout In VDD 20 pF 1 m F OutLon_chip_pl Loff_chip_bw M8 M7(a) PMOS LNA(b) 8-stage buffer PCB ground on-chip ground pad ls_pad nwell rn cby_esd lna_pad c2_pad c2 c1 rfout ld_pad cby_m2 esd cby_lna b_l cbout cby_bfr M6 M5 b_m M4 M3 b_s 8-stage buffer substrate portFigure A-2.The circuit schematics and substrate ports of PMOS LNA and 8-stage buffer. Vg2

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154 TablesA-3,A-4,A-5,andA-6listthecouplingcoefcientsandinductancesusedinthe packagemodel.ThevaluesarecalculatedbyFastHenry.Someofvaluesareadjustedtotmeasurements.Thefacteringnumberoradjustmnetsaredenotedbelowthecalculatedvalue.Ifthe multiplied factors are equal to 0.001, the coupling coefcients are considered being turn-off. Table A-3.Chip-on-board PMOS LNA coupling coefcients and inductances.aLbfpl bLbfbw cLgbw dLsbw eLoutput fLdbw gLV2 hLc2bw iLesd jLVDDaLbfpl0.55nH (0.35nH)bLbfbw0.00443.2nH (2nH)cLgbw0.00800.0205 (x0.7) 1.3nHdLsbw0.0040.1534 (x0.01) 0.05780.9nHeLoutput0.00330.0549 (x0.1) 0.05570.06562.9nHfLdbw0.00230.02420.03540.02440.09072.8nHgLV20.00130.01160.04570.03350.00010.02401.5nHhLc2bw0.00250.03510.01840.24240.01790.00640.01720.47nHiLesd0.00190.00470.15480.05340.03660.01520.15440.02311.2nHjLVDD0.00840.0222 (x0.1) 0.34260.04950.05270.03430.02780.01070.10721nHaLbfpl: buffer power line inductance. bLbfbw:buffer bond wire inductance.cLgbw: LNA input-bond-wire inductance.dLsbw:LNA’s source-bond-wire inductance.eLoutput: LNA output-bond-wire inductance.fLdbw: LNA drain-bond-wire inductance.gLV2: cascode transistor gate-bond-wire inductance.hLc2bw: bond-wire inductance of LNA output-matching capacitor C2..iLesd: LNA ESD-bond-wire inductance.jLVDD: LNA VDD-bond-wire inductance

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155 Table A-4.Chip-on-board NMOS LNA coupling coefcients and inductances.aLbfpl bLbfbw cLgbw dLsbw eLoutput fLdbw gLV2 hLc2bw iLesd aLbfpl0.55nH (0.35nH)bLbfbw0.00443.2nH (4nH)cLgbw0.00960.02181.36nHdLsbw0.00210.00690.06370.8nHeLoutput0.00350.07110.06050.01071.9nHfLdbw0.00350.0338 (x0.4) 0.04520.01270.08352.3nHgLV20.00170.01390.03070.00930.01290.06601.4nHhLc2bw0.00530.0838 (x0.01) 0.04510.00760.08260.03250.00400.5nHiLesd0.00210.00400.13860.03370.04760.00680.14360.03121.2nHjLpcb0.00050.00410.15070.01220.0530.01540.06900.03880.1139aLbfpl: buffer power line inductance.bLbfbw:buffer bond wire inductance.cLgbw: LNA input-bond-wire inductance.dLsbw:LNA’s source-bond-wire inductance.eLoutput: LNA output-bond-wire inductance.fLdbw: LNA drain-bond-wire inductance.gLV2: cascode transistor gate-bond-wire inductance.hLc2bw: bond-wire inductance of LNA output-matching capacitor C2..iLesd: LNA ESD-bond-wire inductance.jLpcb:inductance of PCB’s input metal trace(2.8nH).Table A-5.Packaged PMOS LNA coupling coefcients and inductances.aLbfpl bLdcprobe cLgbw dLsbw eLoutput fLdbw gLV2 hLc2bw iLesd jLVDDaLbfpl0.55nH (0.35nH)bLdcprobe0.00093.5nH (2nH)cLgbw0.00800.00371.2nHdLsbw0.00110.01500.03250.5nHeLoutput0.00220.01410.00930.10351.2nHfLdbw0.00320.00350.07750.03530.05701.6nHgLV20.00220.00780.00750.04290.06840.03470.9nHhLc2bw0.00320.01070.04600.20940.05200.04890.03050.4nHiLesd0.00030.00670.09700.05210.06110.06700.15900.04770.7nHjLVDD0.00860.00480.31220.02430.00830.06320.00920.04050.05371.3nHaLbfpl: buffer power line inductance.bLdcprobe:inductance of DC probe.cLgbw: LNA input-bond-wire inductance.dLsbw:LNA’s source-bond-wire inductance.eLoutput: LNA output-bond-wire inductance.fLdbw: LNA drain-bond-wire inductance.gLV2:cascodetransistorgate-bond-wireinductance.hLc2bw:bond-wireinductanceofLNAoutput-matching capacitor C2..iLesd: LNA ESD-bond-wire inductance.jLVDD: LNA VDD-bond-wire inductance

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156 Table A-6.Packaged NMOS LNA coupling coefcients and inductances.aLbfpl bLdcprobe cLgbw dLsbw eLoutput fLdbw gLV2 hLc2bw iLesd aLbfpl0.55nH (0.35nH)bLdcprobe0.00063.5nH (2nH)cLgbw0.01020.01511.3nHdLsbw0.00870.00640.13350.8nHeLoutput0.00210.0076 (x0.3) 0.00100.00881.15nHfLdbw0.00370.01570.07010.04810.06101.55nHgLV20.00220.00040.00230.03240.06620.04461.1nHhLc2bw0.00460.00400.05490.00340.04490.06350.02630.45nHiLesd0.00020.00400.05470.01170.06300.06410.18320.04400.73nHjLeadin0.00040.00030.17250.04810.06850.07990.07510.03160.1028kLeadout0.00040.00820.05950.01370.17330.10050.05500.08660.0664lLeadLd0.00140.00230.05920.02220.05700.20430.04490.06410.0565aLbfpl: buffer power line inductance.bLdcprobe: inductance of DC probe.cLgbw: LNA input-bond-wire inductance.dLsbw:LNA’s source-bond-wire inductance.eLoutput: LNA output-bond-wire inductance.fLdbw: LNA drain-bond-wire inductance.gLV2: cascode transistor gate-bond-wire inductance.hLc2bw: bond-wire inductance of LNA output-matchingcapacitorC2..iLesd:LNAESD-bond-wireinductance.jLeadin:inputlead(1.35nH).kLeadout:outputlead(1.35nH).lLeadLd: lead of drain inductor (1.42nH).

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162 BIOGRAPHICAL SKETCH ChikuangYuwasborninTaipei,Taiwan,inDecember,1970.HereceivedhisBachelorof ScienceinphysicsfromTamkangUniversity,Taiwan,in1993andhisMasterofSciencefrom NationalChiao-TungUniversity,Taiwan,in1995.In2002,hereceivedhisMasterofEngineering degreeinelectricalengineeringfromtheUniversityofFlorida,Gainesville,Florida,USA.Since 1999,hehasbeenworkingtowardthePh.D.degreeattheSiMICS(SiliconMicrowaveIntegrated CircuitsandSystems)ResearchGroupintheDepartmentofElectricalandComputerEngineering at the University of Florida, Gainesville, Florida. Currently, he is a Ph.D. degree candidate. ForhisPh.D.dissertationresearch,hehasbeeninvestigatingthenoisecoupling mechanisms between the digital and RF circuits.