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Embedded Substrate Noise Measurement for Mixed-Signal/Radio Frequency/Microwave Integrated Circuits

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Title:
Embedded Substrate Noise Measurement for Mixed-Signal/Radio Frequency/Microwave Integrated Circuits
Creator:
HE, MING ( Author, Primary )
Copyright Date:
2008

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Subjects / Keywords:
Amplifiers ( jstor )
Electric potential ( jstor )
Integrated circuits ( jstor )
Noise measurement ( jstor )
Noise reduction ( jstor )
Signal detection ( jstor )
Signals ( jstor )
Simulations ( jstor )
Substrate specificity ( jstor )
Transistors ( jstor )

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University of Florida
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University of Florida
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Copyright Ming He. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Embargo Date:
12/31/2008
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659814001 ( OCLC )

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1 EMBEDDED SUBSTRATE NOISE MEASUREMENT FOR MIXED-SIGNAL/RADIO FREQUENCY/MICROWAVE INTEGRATED CIRCUITS By MING HE A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006

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2 Copyright 2006 by Ming He

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3 ACKNOWLEDGMENTS I would like to begin by thanking my adviso rs, Professors William R. Eisenstadt and Robert M. Fox, for their guidance and support thr oughout the course of this work. Without their support and guidance, my exploration in this re search could not succeed. I also would like to thank the members of my supervisory committ ee --Professors John G. Harris and Oscar D. Crisalle -for their guidance and interest in th is work. I also thank Marcy Lee for her countless help on ordering equipment. Much appreciation goes to the Semiconductor Research Corporation (SRC) and National Science Foundation (NSF) for f unding this work, as well as IBM and Mosis for providing test chips. I would also like to thank fellow stude nts Tao Zhang, Xueqing Wang, Du Chen, Xuelin Wu, Xiaoqing Zhou, Qizhang Yin, Yu Su, Cha nghua Cao, Yanping Ding, Chikuang Yu, Haifeng Xu, Dongming Xu, Xiuge Yang, Xuege Wa ng, Sanghoon Choi, Inchang Seo, Jangsup Yoon, Okjune Jeon, Kooho Jung, Jongshick Ahn and Sud eep Puligundla for their helpful discussions, advice and friendship. Finally, I am grateful to my wife, Xiaoxiang Gong. Her love and dedication have been essential to the fulfillment of this work. Also, I would like to thank my parents and my grandmother for their love and encouragement throughout the years.

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4 TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................3 LIST OF TABLES................................................................................................................. ..........7 LIST OF FIGURES................................................................................................................ .........8 ABSTRACT....................................................................................................................... ............13 CHAPTER 1 INTRODUCTION................................................................................................................. .15 1.1 Background of Radio Fre quency/Microwave Test...........................................................15 1.2 Future of Testing: Embedded Test...................................................................................18 1.3 Challenges and Approaches in Embedded RF/Microwave Test......................................20 1.3.1 Direct Measurement of Specifications...................................................................21 1.3.2 Alternate Testing Methods.....................................................................................22 1.3.3 Summary.................................................................................................................2 4 1.4 Organization of the Dissertation.......................................................................................25 2 EMBEDDED SUBSTRATE NOISE MEASUREMENT......................................................27 2.1 Introduction............................................................................................................... ........27 2.2 Substrate Noise Coupling Mechanism..............................................................................28 2.3 Substrate Noise Reduction Techniques............................................................................32 2.3.1 Substrate Engineering.............................................................................................33 2.3.2 Device Isolation Methods.......................................................................................33 2.3.3 Grounding Effects..................................................................................................37 2.3.4 Noise-Reduction-Oriented Circuit Design Techniques..........................................38 2.4 Substrate Noise Coupling Mode ling and Extraction Strategies.......................................39 2.5 Substrate Noise Measurement..........................................................................................42 2.5.1 DC Measurements..................................................................................................42 2.5.2 Direct Probing Measurement..................................................................................42 2.5.3 Embedded measurem ent techniques.......................................................................43 2.6 Proposed Embedded Substrate Noise Measurement........................................................45 2.6.1 Potential Benefits....................................................................................................46 2.6.2 Design Issues..........................................................................................................46 2.7 Research Goals............................................................................................................. ....47 3 AUTOMATIC GAIN CONTROL BASED MEASUREMENT SYSTEM...........................49 3.1 Introduction............................................................................................................... ........49 3.2 Theory of AGC.............................................................................................................. ...49 3.3 Circuit Design............................................................................................................. ......53

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5 3.3.1 Variable Gain Amplifier.........................................................................................54 3.3.2 Peak Detector..........................................................................................................57 3.3.3 Loop Filter and Gm-1 Block..................................................................................59 3.3.4 On-chip Bias and Voltage Reference Circuits........................................................60 3.3.5 T-switch................................................................................................................. .60 3.3.6 Overall System with Embedded Test Points..........................................................61 3.4 Simulation of AGC Design...............................................................................................62 3.5 Measurement Results........................................................................................................ 65 3.6 Conclusions................................................................................................................ .......67 4 LOGARITHMIC AMPLIFIER DETECTOR........................................................................68 4.1 Introduction............................................................................................................... ........68 4.2 Review of Various Logarithmic Amplifier Techniques...................................................68 4.3 Logarithmic Amplifier Circuit Design.............................................................................71 4.3.1 Limiter Design.................................................................................................74 4.3.2 Rectifier Design...............................................................................................76 4.3.3 DC Offset Cancellation...................................................................................80 4.4 Simulation Results and Analysis......................................................................................81 4.5 Conclusions................................................................................................................ .......89 5 DOWN-CONVERSION BASED MEASUREMENT SYSTEM..........................................90 5.1 Introduction............................................................................................................... ........90 5.2 Down-Conversion Mixer..................................................................................................91 5.2.1 Introduction............................................................................................................9 2 5.2.2 Circuit Design.........................................................................................................96 5.3 Verification of Mixer Design............................................................................................96 5.3.1 Test Setup and Calibration..............................................................................97 5.3.2 Measurement Results......................................................................................99 5.4 Summary and Conclusions.............................................................................................101 6 MODELING AND VERIFICATION METHODOLOGY FOR SUBSTRATE COUPLING EFFECTS........................................................................................................102 6.1 Test Structures for Substrate Coupling Investigation.....................................................102 6.2 Substrate Model Extraction............................................................................................105 6.3 Measurement Results......................................................................................................10 9 6.4 Discussions................................................................................................................ .....111 6.4.1 Effect of Measurement Errors on Model Extraction............................................111 6.4.2 Multiple-contact Coupling Problem.....................................................................112 6.5 Conclusions................................................................................................................ .....114 7 SUMMARY AND FUTURE WORK..................................................................................115 7.1 Summary.................................................................................................................... .....115 7.2 Future Work................................................................................................................ ....117

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6 APPENDIX A ERROR ANALYSIS FOR PSEUDO-LOGARITHMIC AMPLIFICATION.....................121 B CALIBRATION FOR ONE-PO RT MEASUREMENT SYSTEM.....................................125 C EMBEDDED SUBSTRATE COUPLING MEASUREMENT AND SEMI-PHYSICAL MACROMODEL EXTRACTION.......................................................................................129 C.1 Embedded Substrate Coupling Measurement................................................................129 C.2 Semi-physical Macromodel...........................................................................................132 LIST OF REFERENCES............................................................................................................. 139 BIOGRAPHICAL SKETCH.......................................................................................................146

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7 LIST OF TABLES Table page 1-1 Typical RF and IF measurements made on a RF device...................................................17 4-1 Logarithmic amplifier output variati ons under different conditions (10mV 100MHz sinusoid input)................................................................................................................ ....88 4-2 Logarithmic amplifier output variati ons under different conditions (100mV 100MHz sinusoid input)................................................................................................................ ....88 C-1 Typical values of R12 as a function of separation distance..............................................135 C-2 Typical values of C12 as a function of separation distance..............................................135 C-3 |G12| variations under different frequenc ies (separation distance = 220µm)...................138 C-4 |G12| variations under different frequenc ies (separation distance = 1200µm).................138

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8 LIST OF FIGURES Figure page 1-1 System integration of co re semiconductor technologies...................................................15 1-2 The evolution from (a) c onventional test with high-cost ATE to (b) embedded test with low-cost ATE.............................................................................................................1 9 1-3 Variation in process or circuit paramete r and its effect on circ uit specification and test........................................................................................................................... ...........23 2-1 Overview of the substr ate noise coupling problem............................................................27 2-2 Body effect represented by a dependent current source....................................................30 2-3 Commercial substrate do ping profiles: (a) high-resist ivity substrate, (b) lowresistivity substrate.......................................................................................................... ...32 2-4 The effect of guard rings with different substrate doping profiles....................................34 2-5 Guard ring isolation versus fr equency as a function of width...........................................35 2-6 Guard ring isolation versus frequenc y as a function of package inductance.....................35 2-7 Triple-well isolation strategy............................................................................................. 36 2-8 Deep trench isolation...................................................................................................... ...37 2-9 Separating the LNA and mixer grounds increased isolation.............................................37 2-10 Floor planning for substrate coupling reduction................................................................38 2-11 Typical verification flow for substrate noise analysis.......................................................39 2-12 Two-port setup for high-frequenc y substrate coupling measurement...............................43 2-13 Measurement setup of substrate noise coupling................................................................44 2-14 Embedded substrate noise measurement...........................................................................45 3-1 AGC circuit block diagra m and linearized loop model.....................................................50 3-2 Constant settling time AGC with arbitrary VGA gain and Gm control characteristic.......52 3-3 VGA cell schematic......................................................................................................... ..54 3-4 DC offset cancellation for VGA causing multiple feedback loops....................................56

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9 3-5 Start-up circuit solves the multiple operating point problem in VGA...............................57 3-6 Half-wave peak detector and full-wave peak detector.......................................................58 3-7 Loop filter................................................................................................................ ..........59 3-8 Differential difference amplifie r (DDA) (CMFB circuit not shown)................................59 3-9 Wide-swing constant-gm bias circuit..................................................................................60 3-10 Transmission gate and T-switch........................................................................................61 3-11 Overall AGC system with embedded te st points and embedded test point implementation................................................................................................................. .62 3-12 Gain tuning curve of VGA blocks.....................................................................................63 3-13 Frequency response of two-stage VGA.............................................................................63 3-14 Linearity of two-stage VGA in THD (%) versus input signal strength.............................64 3-15 Input versus output charact eristic of peak detector............................................................64 3-16 Transient response of AGC to a 10MHz sinusoidal input with varying amplitude...........65 3-17 Microphotograph of the AGC system................................................................................66 3-18 Bias circuit with exte rnal resistor connection....................................................................67 4-1 Transconductance feedback l ogarithmic amplifiers with (a ) diode or (b) transistor.........68 4-2 Simplified block diagram of successi ve-detection logarithmic amplifier.........................70 4-3 Signal flow in a successive-d etection logarithmic amplifier.............................................70 4-4 Normalized gain, bandwidth and gain-b andwidth product for a single stage versus the number of stages for overall gain of 80dB...................................................................73 4-5 Maximum input error versus the number of stages for overall gain of 80dB....................74 4-6 Limiting amplifiers........................................................................................................ ....75 4-7 Limiting amplifier using triple-well NMOS loads.............................................................76 4-8 Gilbert cell based rectifier............................................................................................... ...77 4-9 Full-wave rectifier with unba lanced source-coupled pairs................................................77

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10 4-10 Signal flow in a successive-detection l ogarithmic amplifier w ith pseudo-logarithmic rectifiers..................................................................................................................... ........79 4-11 Simulated DC transfer curve for full-w ave pseudo-logarithmic rectifier and ideal VLOG curve versus input voltage........................................................................................79 4-12 DC offset cancellation techniques.....................................................................................80 4-13 Simulated AC response of (a) singlestage and (b) 9-stage limiting amplifier..................81 4-14 Simulated RSSI output and i nput error versus input voltage.............................................82 4-15 Output error versus input voltage......................................................................................83 4-16 Output error versus temperature........................................................................................83 4-17 Logarithmic amplifier output distributi ons with mismatch, process variation and mismatch plus process variati on (10mV 100MHz sinusoid input)....................................86 4-18 Logarithmic amplifier output distributi ons with mismatch, process variation and mismatch plus process variati on (100mV 100MHz sinusoid input)..................................87 4-19 Logarithmic amplifier output voltages fr om Cadence simulation versus theoretical values......................................................................................................................... ........89 5-1 Down-conversion based substrate noise measurement......................................................90 5-2 Multiplication based mixer and its signals spectrum.........................................................92 5-3 Simplified mixer........................................................................................................... .....92 5-4 Single-balanced and double-balanced mixers....................................................................93 5-5 Down-conversion mixer schematic....................................................................................96 5-6 Microphotograph of th e down-conversion mixer..............................................................97 5-7 Mixer measurement setup..................................................................................................97 5-8 External buffer............................................................................................................ .......98 5-9 Mixer Reflection Coeffi cient (S11) at RF Port................................................................100 5-10 Mixer output linearity ve rsus input signal level..............................................................101 6-1 Test structures for embedded substrate noise measurement............................................103 6-2 Microphotograph of the test chip containing the substr ate noise test structure...............104

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11 6-3 Measurement setup for substrate coupling investigation.................................................104 6-4 HFSS model of test structure...........................................................................................106 6-5 Equivalent circuit of the test structure.............................................................................107 6-6 Semi-physical equivalent circuit for G12..........................................................................108 6-7 Comparison of measurement and simula tion results of isolation for different separation distances between two substrate contacts.......................................................110 6-8 A two-dimension view of isolation vers us separation distances and frequencies...........110 6-9 Comparison of measurement and simulation results of |G12| for different separation distances between two substrate contacts........................................................................111 6-10 Errors in|G12| because of random errors in measurement...............................................112 6-11 Substrate noise coupling between multiple contacts.......................................................113 6-12 Substrate impedance networ k between multiple contacts...............................................113 7-1 Improved down-conversion based substrate noise measurement scheme.......................117 7-2 Logarithmic amplifier out put versus input voltage..........................................................118 7-3 Output error versus input voltage....................................................................................118 7-4 Example of down-conversion based em bedded substrate noise measurement................119 A-1 Piecewise linear approximation to a logarithmic curve...................................................121 A-2 Signal flow of a successive-d etection logarithmic amplifier...........................................122 A-3 Characteristics of an N-stag e pseudo-logarithmic amplifier...........................................123 A-4 Maximum input error as a function of single stage gain.................................................124 B-1 S-parameter measurement with calib ration setting the reference plane..........................125 B-2 Flow graph of the hypot hetical error adapter...................................................................126 C-1 Measurement setup for embedde d substrate coupling detection.....................................129 C-2 Equivalent circuit of the test structure.............................................................................130 C-3 De-embedding bondpad and interconnection..................................................................131 C-4 Semi-physical equivalent circuit for G12..........................................................................133

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12 C-5 R12 versus different separation distan ces between two substrate contacts......................134 C-6 C12 versus different separation distan ces between two substrate contacts......................134 C-7 |G12| distributions at different freque ncies (separation distance = 220µm).....................136 C-8 |G12| distributions at different freque ncies (separation distance = 1200µm)...................137

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13 Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy EMBEDDED SUBSTRATE NOISE MEASUREMENT FOR MIXED-SIGNAL/RADIO FREQUENCY/MICROWAVE INTEGRATED CIRCUITS By Ming He December 2006 Chair: William R. Eisenstadt Cochair: Robert M. Fox Major Department: Electrical and Computer Engineering Due to the ever-growing demand for IC produc tion cost reduction, there are more and more system-on-chip (SoC) designs that requ ire the integration of analog/radio frequency (RF)/microwave and digital ci rcuits on the same die arise and which pose challenges to RF/microwave testing. Traditional RF/microwave testing that re lies on expensive automated test equipment (ATE) systems cannot keep up with the pace of th e growing complexity of the testing process without increasing test cost a nd is becoming one of the major obstacles for overall IC production cost reduction. Embedded testing is a potential solution to answer those challenges. The basic idea of embedded testing is to move high-speed and high-bandwidth portions of expensive ATE system onto the IC device-under-test (DUT) by a dditional design-for-test (DFT) circuitry, thus reducing the requirements and eventually the cost of external ATE system. SoC designs suffer from substrate noise coupling due to the finite isolation provided by the semiconductor substrate. The study of substrate c oupling effects is especially challenging in terms of circuit design and modeling.

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14 The proposed embedded substrate noise measur ement system consists of an off-chip broadband signal source and exampl e test circuits integrated with the DUT. The signal source acts as a noise generator and injects well-controll ed signals into the substrate, and then the embedded test circuit will extract useful informa tion from the response of the detector and report the data as baseband signals; th e baseband signals are delivered off-chip to an external tester. First, a low-frequency, on-chi p substrate noise measurement test vehicle is designed and used to demonstrate the embedded system feas ibility. Next, a system capable of measuring substrate noise coupling over a ve ry wide frequency span up to the millimeter wave range is demonstrated. Finally, an appli cation of the embedded measuremen t system is presented and a semi-physical macromodel is extr acted based on experimental data.

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15 CHAPTER 1 INTRODUCTION The growth of the personal communicati on market in recent years has led to a relentless push for IC cost reduction, which has quickly dr iven cost-sensitive radio frequency integrated circuit (R FIC) integration levels from single-function parts in 1995 to full front ends and simple handset functions on a chip today. In the future, the demand for more system functionality (Figure1-1) on a single die (system-on-chip, SoC) or in a single package (system-in-package, SiP) will increasingly blur the lines between traditional digital, analog, RF/microwave and mixed-signal devices. This trend will drive test equipment toward a highly configurable, single platform solution that can test any application. Figure1-1. System integration of core semiconductor technologies 1.1 Background of Radio Fre quency/Microwave Test Traditionally, RF design and silicon manu facturing have contributed the highest overall IC cost component, thus the test cost received little attention. Improvements in manufacturing technology, and relaxed perfor mance requirements of some application

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16 domains, lead to high-yield lo w-area design processes, and th e cost of manufacturing RF dies has reduced appreciably. Ho wever, the test cost has not reduced at the same rate, and indeed has been an increasing per centage of the overall IC cost. The first high-volume microwave chip test s were relatively simple, including the tests of switches, amplifiers, mixers, LNA/ mixer combinations, etc., and they were typically performed after ICs were packaged in cheap small outline integrated circuit (SOIC) packages since package scrap costs were very low. Wafer-level tests were used to prune away catastrophically defective dies before packaging and the RF path was completely by-passed in wafer-level test. As the IC complexities have increased, the yields are lower, the package costs become an appreciable component of the overall cost, and the need for wafer-level RF path test before packaging has arisen. Since 1999, there has been a steady increase in the number of high-volume RFICs that are tested on-wafer instead of, or in addition to, being tested at package level. In addition, an increasing number of bare dies are being used in bump-bonded circuitry. In the past 30 years, wafer probing above a GHz has progressed from impossible, to a useful R&D tool, to a necessary produc tion tool, and to a mainstream very largescale integration (VLSI) topic. With the development of high-performance and highfrequency on-wafer probes and probe stations , wafer-level test and characterization can be performed before the ICs were dice d and packaged. Current RFIC testing methodologies require performance-based measur ements (i.e., using external outside-thechip instruments), and the complexity of app lications increases the number of instruments in a given test system (Table 1-1) [1].

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17 Table 1-1. Typical RF and IF measurements made on a RF device AM-PM conversion (static) Adjacent channel power Nth order intermodulation Two-tone IP3, IP5 Complex demodulation Digital input-threshold voltage Phase noise/jitter (CW) Modulated Digital output levels Efficiency (RF out/DC in) Frequency CW vs. time (tune drift) Power (dBm) Output power vs. bias voltage Gain or loss vs. control voltage or digital state Gain compression Pout @ N dB, saturation Pulsed RF measurement Frequency Power S-parameter Pulsed RF profile signal overshoot & ringing Harmonic distortion dBc SOI, TOI RF rise time (10% to 90%) I/Q modulator imbalance (static) Amplitude & phase error S-parameter Gain/loss isolation, match, VSWR, gamma I/Q modulator suppression Carrier & unwanted sideband Spurious signals @ known frequency, search Isolation Supply currents Enabled, sleep mode Minimum detectable signal Mixer conversion gain or loss Switching speed D digital input to D gain or D frequency Mixer leakages LO RF, LO IF, carrier feed through Noise Figure VCO frequency vs. voltage Tune linearity Tune range Tune sensitivity (dc-freq) vs. digital state VSWR Voltages Notes: amplitude modulation (AM), phase m odulation (PM), carrier wave (CW), decibel (dB), in dB with respect to carrier (dBc), second order intercep t (SOI), third order intercept (TOI), in-phase/quadr ature-phase (I/Q), local osci llator (LO), voltage standing wave ratio (VSWR), 3rd intermodulation product (IP3), 5th in termodulation product (IP5), dB below one milliwatt (dBm), vo ltage controlled oscillator (VCO). Extremely complex, million-dollar automated test equipment (ATE) systems have now become readily available from a variet y of vendors that integrate all of these

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18 functions and provide a much higher throughput capability than typical rack-and-stack equipment. The number of RF ports varies from two, for a minimal system for power amplifiers, to 20 or more for complex RFICs. All ATE systems provide DC power supplies for powering and controlling the devi ce-under-test (DUT) and measuring various voltages and currents. As RF front-end chips star t to integrate intermediate frequency (IF) functions, mixed-signal subsystems are bei ng added to ATE systems, which typically provide analog signal stimuli, such as arbitrar y waveform generators (AWGs). This trend of increasing instrument number s, complexity and performan ce is expected to continue. Conventional analog/RF/microw ave IC tests use ATE systems. However, the cost associated with ATE systems has significan t impact on total manufacturing test cost. First, the complexity of the test systems need s to be matched to the complexity of the ICs to be tested and generally the cost of the A TE system is proportional to the complexity of the devices it can test. The increasing inte gration density of ICs nowadays will drive up the cost of ATE systems and eventually the overall test cost. Also, the ATE system is costly to operate and has a complicated test procedure development, which will make the situation even worse. Alternative soluti ons must be found to reduce test cost. 1.2 Future of Testing: Embedded Test There are three approaches in terms of test cost reduction: test le ss, test earlier or test faster [2]. “Test less” reduces unnecessary or duplicated test steps in different test phases (i.e., wafer test vs. package test). Wafe r-level testing is a perfect example for “test earlier”. Package scrap is saved by perfor ming screening and RF path test before packaging. The “test faster” strategy involves the use of test parallelism and/or highthroughput testers. For some product groups (e.g., memory), current wafer probe technologies can handle pa rallel testing of 32 to 256 and more devices.

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19 Embedded test is a potential and advanced solution that addre sses the above listed needs and an efficient way to reduce ATE capital expenditures. (a) Conventional Test (b) Embedded Test Figure 1-2. The evolution from (a) conventiona l test with high-cost ATE to (b) embedded test with low-cost ATE Conventional test methods use external test ers to generate test stimulus and the DUT response is directly measured from the stimulus. High-bandwidth data transfer is done at the operation speed of the DUT. The measurement results include the transmission properties of the interconnection, such as wire s, connectors, probe cards, etc., and require interconnect uniformity (matched impedance throughout the signal

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20 path). Extra effort and cost to decouple th e response of the interconnection from the actual response of the DUT are needed to ensure accurate measurement results. The integration of embedded test circuitr y into the DUTs results in a new on-chip and off-chip distribution of te st resources compared to th e conventional test resource partitioning, as shown in Figure 1-2. Embedded test integrates the capability of highspeed and high-bandwidth portions of the extern al ATE circuits directly into the DUTs. With these embedded circuits (i.e., multiplexer/demultiplexer, signal generators, samplers, converters, response compressors, etc. ), high-speed test stimulus and response signature generation functions can be customi zed per test applica tion type, and on-chip test data compression reduces ATE data logging requirements. 1.3 Challenges and Approaches in Embedded RF/Microwave Test However, embedded test has to face the following major challenges before becoming successful: On-chip generation of high-quality and hi gh-speed test signals using low-cost hardware; High-speed on-chip response acquisition followed by analysis or response compaction. The IEEE 1149.1 (JTAG) boundary scan standard [3] provides an effective means for test access to intern al modules of the DUT for testing stat ic faults in digital ICs [4]. Its JTAG counter part in mixed-signal testing, the IEEE 1149.4 standard [5], is seen in various publications [6-7]. Although some improvements [8] have been shown to overcome the low-bandwidth limit of boundary-scan test on RF pins, more research in this area is needed. Digital built-in-self-test (BIST) circuits us ually return a simple pass/fail bit or a multi-bit “signature” that allows the ATE tester s to evaluate the quality of the device [9].

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21 Since the DUT tests itself using BIST, a mu ch less expensive ATE tester can be used. Unfortunately, analog BIST technology has al ways lagged behind digital BIST because of the required high accuracy of signal s generated and measured on-chip. Design-for-test (DFT) techniques have been introduced and are becoming an industry-wide practice. DFT strategies genera lly fall into two cate gories: some methods follow the tradition production test procedur e and measure the specifications of the DUT directly using dedi cated circuits; while some ot her approaches evaluate DUT performance indirectly. 1.3.1 Direct Measurement of Specifications Traditional production test examines the f unctional specificati ons of analog/mixedsignal circuits by using the appr opriate tester resources and using the same kind of test stimuli and configuration with respect to wh ich the specifications ar e defined [10] (i.e., gain for codec, multi-tone signal generator for distortion measurement, etc.). The measurement procedures are consistent w ith the intuitive m eaning of the module behaviors, and it is easy to in terpret the measurement results. Various implementations of on-chip signal ge nerators for testing analog/RF circuits are reported in the literature [ 11-15]. Note that the on-chip microwave signal source in [15] can generate pure sinewave and multitone signals above the GHz range, which enables on-chip microwave te st [16]. An on-chip spectru m analyzer using a direct conversion technique with 8-bit resoluti on is reported in [17]. An on-chip sampler/oscilloscope based on sub-sampling of periodic signals was proposed by P. Larsson [18], and some of its applications can be found in [19-20]. These works show the feasibility of using embedded test circu its for high-frequency and high-performance

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22 analog/RF blocks measurement, even though the chip area overhead brought by the additional circuitry might be a potential obstacle. However, a direct measurement method might not be suitable for multiplespecification measurements. First, multiple specification measurements require different kinds of resources, which will make the chip area overhead problem more severe. Also, if the measurement of multiple sp ecifications cannot be performe d at the same time, overall test time will be longer and overall manufacturing cost will go up. 1.3.2 Alternate Testing Methods The concept of alternate test was proposed in [21-23] by A. Chatterjee. The basic idea of alternate test is to relate DUT perf ormance to process vari ations, and to perform less costly additional tests instead of explicit measurements to evaluate DUT performance. Similar to the direct measuremen t method, alternate test also applies a test stimulus and measures DUT response. But the test stimuli have to be optimized so that DUT specifications can be predicted accu rately from alternate response. As shown in Figure 1-3(a), after the m easurement, feature extraction and mapping have to be done to obtain corresponding DUT specifications. Figure 1-3(b) illustrates the effect of variation of process paramete rs on the specificati on and the corresponding measurement data. The variation in parame ter space P (i.e., gate oxide thickness, threshold voltage, temperature, etc.) aff ects the specification space S by a corresponding sensitivity factor. Similarly, the variation in P also influences the measurement space M. Given the parameter space P, any point in P can be mapped onto the specification space S by fps and onto the measurement space M by fpm.

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23 (a) Process Parameter Space (P)Measurement Space (M) Specification Space (S) Distribution of a parameter corresponding to the process/netlist Distribution of a measurement data corresponding to parameter perturbation Distribution of a specification due to non-zero tolerance in parameter value Region of operation of a “good” system Nominal or design valueps f p m f ms f (b) Figure 1-3. Variation in process or circuit parameter and its e ffect on circuit specification and test Therefore the region of acceptance in specification space S has a corresponding accepted region in process parameter space P, wh ich in turn defines the accepted region

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24 in M. Nonlinear statistical multivariate regression can be used to construct a mapping function between M and S: fms. By mapping measurement data to specification through fms and comparing with various specification thresholds, we can predict whether the DUT is faulty or not. The key issues of alternate test are to fi nd a suitable transient test stimulus and to predict circuit specifications accurately from alternate test responses. Several papers in the literature reported applications of alternate test to op-amps, low-frequency filter circuits [24], and even highfrequency RF modules [25]. But current methods require a large number of samples to validate an alternate test, and more efficient statistical or analytical methods to verify fault coverage have to be developed for proliferation of alternate te sts. Also, built-in response acquisition in alternate testing of RF circuits is difficult to complete and still in the development stage [26]. 1.3.3 Summary Even though the above approaches (i.e ., boundary scan, BIST, DFT) do not give complete answers for the challenges of embedde d test, it is still of interest to develop embedded RF/microwave test circuits taking account the tradeoffs among the ATE tester cost, product testability and chip area. Inte gration of a wider array of digital CMOS circuits, mixed-signal and even optical/mechanic al silicon together in future products will continue to make embedded test attractive rath er than to increase the platform complexity of ATEs towards a “do all” platform, as ma ny more critical RF/microwave nodes will be unobservable and/or uncontrollable by today’s test techniques.

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25 1.4 Organization of the Dissertation This Ph.D. dissertation consists of seven chapters. An overview of the research is given in this current chapter (Chapter 1), including the background of RF/microwave test, motivation for embedded RFIC test, challe nges and existing techniques for embedded test. Chapter 2 reviews some background know ledge on substrate noise coupling analysis. Basic concepts of substrate noise coupling mechan ism and reduction techniques are described, and some features and trends of current substrate noise measurement are presented. An embedded substrate noise meas urement test scheme is then proposed. Research goals and the scope of this work will be discussed. Chapter 3 describes an AGC based low-fre quency substrate noise measurement test vehicle. A design based on analysis of c onventional AGC loops is then presented. Fundamentals of AGC operation are al so reviewed in that chapter. Chapter 4 presents the design and simulati on of pseudo-logarithmic amplifier based on successive-detection architecture. This amplif ier can be used as a signal detector and the limitations of it will be discussed. A down-conversion mixer based high-fre quency substrate noise measurement system with very wide frequency bandwidth and dynamic range is presented in Chapter 5. The test setup and measurement resu lts on a prototype chip demonstrate the practicality of the circuit for on-ch ip embedded substrate noise test. Chapter 6 shows the embedded substrate c oupling measurement results and a semiphysical macromodel based on experimental data . Error analysis and application of this model to multiple-contact coupling problem are also discussed.

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26 A summary of research work discussed in this dissertation and suggestions for the future work are presented in Chapter 7.

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27 CHAPTER 2 EMBEDDED SUBSTRATE NOISE MEASUREMENT 2.1 Introduction Driven by cost-constrained applications such as telecommunications, computing and consumer/multimedia and facilitated by continuing miniaturization in the CMOS VLSI technology, designers are given the oppor tunity to integrate multiple system components (i.e., analog, digital, RF secti ons) onto a few chips or even on one single multi-million transistor chip – a so-called System-on-chip (SoC). This pays dividends in enhanced performance, as well as dram atically-reduced area, power, and most importantly, the overall system cost. Howeve r, the integration of both analog/RF and digital circuits on the same die also opens th e door to a host of ch allenging noise coupling effects which create mixed-signa l signal integrity problems. P Substrate Package n+ n+ n+ n+ Vdd Digital FETAnalog FET + p+ p+ Figure 2-1. Overview of the s ubstrate noise coupling problem As shown in Figure 2-1, the sw itching activity of digital circuits injects spurious signals into the substrate, a nd the fluctuations couple th rough metal lines and through the

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28 substrate to the sensitive anal og parts of the chip. Substrat e noise can cause performance degradation, or complete functional failures in the worst case. 2.2 Substrate Noise Coupling Mechanism All the currents that are injected into th e substrate will cause fluctuations of the substrate voltage, and these fluctuations ar e called substrate noise. Substrate noise currents in CMOS circuits are produced by several mechanisms, of which the dominant are impact ionization currents, source/dra in capacitive currents and supply coupling currents. Impact ionization occurs in a saturated MOSFET channel when the electrical field strength is high enough to cause hot electrons . These electrons can release excess energy by colliding with nearby latti ce sites and create additional electron-hole pairs [27]. For the NMOS device, additional electrons are swep t into the drain, and the holes are injected into the substrate creating a positive substrat e current. This substrate current for NMOS devices can be estimated [27-28] by the fo llowing semi-analytical expression (Equation 2-1): 1/31/2 2 1()expoxj subdsdsatd dsdsatCtx ICVVI VV (2-1) where Id is the drain current, Vds is the drain-to-source voltage, Vdsat is the drain-to source voltage at saturation, tox is the gate oxide thickness and xj is the source/drain junction depth. C1 and C2 are semi-empirical constants. Note that the substrate current is directly proportional to the drain current Id, which means wider MOS de vices operating as digital switches will generate more substrate current since they conduct more current. A wider device also indicates larger pinch-off region, giving rise to a larger number of hot carriers. Another trend worthy of mention is that device scaling is likely to worsen this

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29 problem due to shorter channel length, incr eased channel fields, smaller gate oxide thickness tox and decreased junction depth xj. Due to the junction capacitances between th e source/drain of the transistors and the bulk/well, voltage fluctuations on the source or drain can c ouple to the bulk/well. The resulting substrate voltage s hows the same characteristic as the switching node voltage. In digital circuits, the su pply current causes large ohmic I R voltage drops while the fast current transients of the switching gates cause large inductive di L dt voltage drops ( I noise) in the supply network. This s upply noise couples capacitively into the substrate from VDD via the n-we ll junction capacitance, and resistively from VSS via the substrate contacts. Voltage fluctuations across the passive components can also affect substrate potential. Passive components in typical se miconductor processes include resistors, capacitors, inductors and local diffusions. On -chip resistors are either poly-type or diffused. Both resistor types can inject noise into substrat e through parasitic capacitance. On-chip capacitors can be poly-to-poly, metal-to -metal or poly-to-subst rate types. All of these can be significant substrate noise inje ctors. On-chip induct ors and interconnects inject noise into the substrate through the pa rasitic oxide capacitance to the substrate. Local diffusions in the substrate can be p-t ype or n-type. N-type diffusions can inject noise into the substrate through a reverse bi as capacitance. P-type diffusions are often used as substrate contacts or guard rings . The grounding for guard rings should be properly done; otherwise they can be very e ffective path for substrate noise injection. Similar to substrate noise injection, th e reception of substrate noise by the MOS devices can take place through the source/drai n depletion junction. MOS devices also

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30 exhibit a more severe form of substrate in teraction due to the body effect. The substrate potential dependence of the threshold voltage can be shown by Equation 2-2: 0(22)thtFSBFVVV (2-2) where VSB is the source to bulk potential, Vt0 is the threshold voltage for VSB equal to zero, 2F is the surface inversion potential and 2 s isub oxqN C denotes the body effect coefficient. The bulk potential influences the threshold voltage a nd directly affects the saturation current of the MO S transistor, which is gi ven by Equation 2-3 (ignoring channel-length modulation effect): 21 () 2DnoxGSthW I CVV L (2-3) Figure 2-2. Body effect represen ted by a dependent current source In some sense [30-31], the bulk acts as a second gate and can be modeled by a current source connected between drain and source (Figure 2-2). mbg can be expressed as (Equation 2-4): ()()th D mbnoxGSth BSBSV IW gCVV VLV (2-4) And gmb can be related with gm, the small-signal transconductance of the MOS device by Equation 2-5:

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31 22mbmm FSBggg V (2-5) and the factor is typically in the range of 0.1 to 0.3, which means the body-to-drain gain is only 10-14 dB lower than the gate-todrain gain. At low to medium frequencies, this will make MOSFET devices ve ry vulnerable to substrate noise. Substrate coupling can have different effect s in different types of substrates. There are two commonly used substrate profiles in commercial foundries, as shown in Figure 23. The first substrate consists of a thin surface buried-p region of 1-2 m thickness and a highly resistive bulk region of re sistivity in the range of 10-30 -cm. This substrate is used in certain BiCMOS processes. The low-re sistivity surface layer serves as a channelstop layer for MOSFETs, reduces CMOS latc h-up and raises the surface inversion potential under the field oxide . The second substrate is used in most CMOS processes. Some processes have a thin channel-stop im plant at the surface, approximately 0.5-1 m thick, with a resistivity in the range of 0.5-1 -cm. The epitaxial la yer thickness is about 10um with resistivity of 10-15 -cm. The bulk region is heavily doped, with a low resistivity of about 10-100m -cm, and thickness in the range of 100-400 m. At low and medium frequency, all substrates typically s how a resistive behavior. This assumption is accurate to a cut-off frequency, fc, which is defined by Equation 2-6 [32]. 11 22c s ubsubsubSif RC (2-6) where Rsub and Csub are the resistance and capac itance of the substrate, and s ub and Si are the resistivity of the substrate and th e permittivity of the silicon, respectively.

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32 (a) Heavily Doped p-Substrate ~10-100m -cm Lightly Doped Epi Layer p-type ~10-15 -cm 1 m 10 m ~300 m Channel-stop region P-type 1 -cm(b) Figure 2-3. Commercial substr ate doping profiles: (a) high-re sistivity substrate, (b) lowresistivity substrate. Equation 2-6 provides a good reference fo r designers looking to use a proper substrate model. As an example, fo r silicon substrate resistivity of 100 -cm, cut-off frequency is in the range of 1.5 GHz. It is important to understand these limitations so that they can serve as guidelines in the choice of the substrate resistivity to be used for a given technology. Different t echniques used for the modeling of substrate noise coupling will be discussed in Section 2.4.2. 2.3 Substrate Noise Reduction Techniques The principal strategies to limit or redu ce substrate noise coupling can be grouped into the following four categories: Techniques reducing the noise generation from the noise source/generator (eg. Switching digital circuits), Techniques attenuate substr ate noise from the noise generator to its bulk node, Techniques changing the propagation of the noise to the sensitive circuits through the substrate (not so effective in low-resistivity substrate), Techniques that make the analog circuit in sensitive to the substrate noise coupling to its bulk node.

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33 The techniques in first category are be yond the scope of our discussion here, and this dissertation will only concentrate on th e techniques in the last three categories. 2.3.1 Substrate Engineering High-resistivity substrates have been proposed as a solution for suppressing substrate noise and for increas ing the quality factor (Q) of the passives [33] [34]. Improvement of Isolation (S21) about 1020 dB for high resistivity substrate (Rsub > 1000 -cm) has been reported. Some other approaches followed similar idea by locally increasing substrate resistance by a very larg e factor, such as the “high energy proton bombardment” method [35]. But substrate resi stivity cannot be rais ed without limits, and other problems such as latch-up effect s will arise and have to be solved. SOI is often considered as a solution fo r substrate noise coupling [36], but the buried oxide layer will lose its advantage at high frequency and becomes transparent to substrate noise. 2.3.2 Device Isolation Methods Guard ring structures around a noise source provide a low impedance path for AC grounding and minimize the amount of noise injected into the substrate. Sensitive circuits can use guard rings to decouple noise from the substrate. Figure 2-4 shows the effectiveness of us ing N-well guard rings compared to P+ guard rings in low-resistivity (“heavily doped”) and high-resistiv ity (“lightly doped”) substrates [37]. P+ guard rings are more e ffective than the N-well guard rings, because they are resistively linked to the p-type substrate.

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34 Figure 2-4. The effect of guard rings with different substrate doping profiles Guard rings typically provide more effective isolation in a high-resistivity substrate, and their efficiency also depends on their width, the noise frequency and the package inductance [38]. Figure 2-5 and Figure 2-6 show how guard ring efficiency is affected by different factors. The appropriate use of guard rings will be determined by the frequency of noise to be suppressed, the available space, and the required attenuation. Lower package inductance is very effective at reducing substrate coupling but sometimes is an expensive approach because of the extra package costs.

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35 Figure 2-5. Guard ring isol ation versus frequency as a function of width Figure 2-6. Guard ring isolati on versus frequency as a f unction of package inductance Triple-well (“deep N-well”) is now a common option in most CMOS processes. Figure 2-7 shows the cross sect ion of a triple well transistor with measured isolation results as presented in [39]. The triple-well ex ample showed in [39] exhibits an additional ~20dB isolation at low frequency compared to conventional P+ guard ring scheme. But

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36 there is no publication yet showing how well this technique can be extended into the mmwave regime. Figure 2-7. Triple-well isolation strategy Deep trench isolation (Figure 2-8) is available in bipolar/BiCMOS processes, which use high-resistivity substrates. The deep trench forces substrate current down into the high-resistivity region of the substrate an d attenuates the substrate noise coupled into the sensitive circuits on the same substrate.

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37 Figure 2-8. Deep trench isolation 2.3.3 Grounding Effects It has been common practice to have separated supplies and grounds for analog and digital sections on the same chip, for the is olation of switching noise generated by digital parts from the sensitive analog circuitry. In [40], it showed (Figure 2-9) an example based on this concept: substrate noise coupling between different s ections on the same substrate can be attenuated by providing them with different substrate grounds. Figure 2-9. Separating the LNA and mixer grounds increased isolation

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38 2.3.4 Noise-Reduction-Oriented Ci rcuit Design Techniques Other than processand layout-based met hods discussed above, noise-aware circuit design techniques are also employed to reduce the substrat e coupling effect. Careful floor planning is playing an impor tant role in RF/mixed-signal designs. Increasing the distance between noisy and sensiti ve circuit blocks is a natural thought for substrate noise isolation. For a low-resistivity substrate, substrate resistance between two surface contacts is a function of distance, and it can help to reduce the substrate coupling. However in high-resistivity substrates, most of the substrate current will propagate vertically in the epitaxial layer and the bulk is considered as a singl e electrical node [37]. In this case, distance cannot be used to isol ate sensitive and perturbing cells. Figure 2-10 shows a typical floor plan for mixed-signal design [41]. Proper substrate modeling and good understanding of noise distribution among i ndividual blocks are of great importance for the designers to decide whether substrate coupling has been reduced sufficiently and create the optimum floor plan. Figure 2-10. Floor planning fo r substrate coupling reduction

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39 Other substrate noise reduction techniques, such as using “active guard band filter” [42] [43] and guard ri ng diode [44], have also been reported. 2.4 Substrate Noise Coupling Modeling and Extraction Strategies As discussed in the previous section, the various techniques used to mitigate substrate noise are heavily employed by So C designers, guided by rules of thumb, intuition, or past experience. However, withou t the ability to analyze and manage the true effects of substrate noise, ma ny of these techniques are of ten over deployed (i.e., overspacing of digital and analog blocks, excessi ve guard rings, highcost low-parasitic packages, etc), resulting longer design cy cles and increased manufacturing costs. Complete Physical Design Extract Substrate Network Compute Substrate Noise Simulation including Noise-sensitive Devices Modify Design Using Provided Information Figure 2-11. Typical verification fl ow for substrate noise analysis

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40 To understand and model the effects of s ubstrate noise coupling in SoC designs, substrate parasitics should be combined with the circuits for simulation. However, simulating an entire SoC design that includes all substrate parasitics is beyond the scope of traditional circuit simulators. A complete analysis of substrate noise coupling effects requires both substrate noise modeling as well as circuit simulation. A typical flow for substrate noise analysis is shown in Figure 2-11. Given the model as discussed in Section 2.2, there exist se veral techniques to analyze and compute the substrate network in integrated circuits, each with a different trade-off between accuracy, flexibility and computation speed. Some techniques [37] [45] based on fin ite-element method (FEM) were published for detailed numerical analysis in a few standard situations . They use a full numerical analysis of all potentials and currents in the substrate, either by simulation of a 3D resistance mesh of the complete substrat e or by device simulation. However, these approaches are not efficient enough for im plementation in a standard CAD system. Furthermore, they do not provide a circuit m odel for the designer as a direct feedback between the circuit design, the layout de sign and the substrate coupling problems. An alternative approach is based on a numer ical [46] [47] or semi-analytical [48] [49] solution of the differenti al equations that describe s ubstrate transport. By using a boundary-element method (BEM), with a suitab le choice of the Green Â’s function, it is possible to derive circuit models for the para sitic substrate cross-talk directly from the layout. This avoids a full discretization of th e complete substrate a nd allows a straight forward computation of a fully specifi ed equivalent elec trical network.

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41 The differences in discretization met hodology give rise to differences in computation speed. The 3D discretization of the FEM results in a dramatically large system of equations to be solved compar ed to the 2D discretization of the BEM. However, the FEM system is sparse, while the BEM system is full. For each method, highly optimized specific solution methods are typically used. For the FEM, popular solution methods include GMRES-like methods [45] and for the BEM, they include the so-called fast multipole method [50] and th e Schur method [51]. Alternatively, hybrid FEM/BEM methods could combine the advantages of both methods [52]. Numerical analysis and com putation of the substrate model is usually performed after layout extraction and does not provide a priori insight to the circuit designers. Due to the ever growing density and complexity of the integrated system, recursive iteration between the transistor-level circuit simula tion and the post-layout verification could be very time-consuming. It is desirable to obtai n a compact representati on of the interactions of circuit elements that c ouple through the substrate. A popular approach consists of creating equivalent circuits or simple analytical models (macromodels), whose parameters are selected to fit either measur ed or simulated substrate conduction behaviors [53] [54]. Macromodels will help the designer in the early stage of the design and they can be used to guide the placement of various components before the final layout is done. However, this method brings new challenges to the circuit designers, including how to distinguish critical noise sour ces and sensitive nodes in the circuits, and how to identify the possible noise coupling paths in order to generate a correct substrate network.

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42 2.5 Substrate Noise Measurement Substrate noise measurement is an intuitive way to verify the results of substrate modeling or to study time-dom ain or frequency-domain e ffects of substrate noise. Various schemes have been reported in publis hed papers and they a ddress the problem of substrate noise estimation from different perspectives. 2.5.1 DC Measurements Substrate coupling can be treated as a tw o-port problem, with one port acting as a noise injector and the other as a noise sensor . The simplest way to do so is to directly measure the resistance network between one port and another port in the real substrate [49]. A voltage source can be attached to the injection node and by measuring the current flowing out of the sensor, the DC resistance between these two substrate contacts can be obtained. The same procedure can be repeat ed for each pair of ports until the whole resistive matrix is completed. However, this method is only valid at DC and low frequency. As discussed in Section 2.2.1, [32] points out that a frequency limit exists for the substrate resistive behavior assumption. 2.5.2 Direct Probing Measurement As discussed earlier, substrate coupling is a two-port problem, a nd it is possible to make such a measurement up to very high fr equencies, using high frequency scattering parameter measurement techniques. In [55] [56] the authors ha ve used a two-port test stru cture, as shown in Figure 212, to verify the validity of the simulator a nd the equivalent circu it of the substrate.

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43 G1 S1 G1 G2 S2 G2 Noise Injector Noise Sensor Figure 2-12. Two-port setup for high-fre quency substrate coupling measurement Since all the measurements in [32] [55] ar e made on wafer, it is very difficult to study coupling effects that occur only through the substrate in the presence of package parasitics. Direct coupling be tween the probes used for the measurement also sets the noise floor of measurements. In [56], an advanced de-embedding met hod has been introduced to eliminate the crosstalk between the RF probes and impr ove measurement accuracy. However, this method requires RF probes spacing to rema in constant throughout the measurement sequence, and an ultrasonic cutter has to be used in order to change the connection for calibration. 2.5.3 Embedded measurement techniques A scheme is presented in [ 37] [57] to use the thres hold voltage modulation of a single MOSFET to sense the transient substr ate noise. The outputs of the MOS devices are measured as the RMS noise voltage indu ced on an external node , as shown in Figure 2-13.

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44 Figure 2-13. Measurement setup of substrate noise coupling Another scheme using a statistical approach is presented in [58] [59]. High-gain voltage comparators are used as noise sens ors, information desc ribing substrate noise generated by an on-chip inverters bank is extr acted using statistical analysis techniques. However, this technique neglects the spectra l domain information of the injected noise, which might be crucial in certain applications. Both measurement techniques discussed a bove cannot measure the substrate noise directly but through the influence of s ubstrate voltage on the MOSFET current or comparator state. A real-time direct measurement technique is proposed in [59] [60] by using an analog amplifier. A differential amplifier is used as substrat e noise sensor, with one input connected to the substrate and the other to a “quite” reference, to directly measure the substrate voltage. But this technique has a limited bandwidth only up to 1GHz, mostly determined by the bandwi dth of the amplifier. In [61], a scheme to measure narrow-ba nd noise injected by an on-chip VCO is presented. The basic idea is to implement an on-chip heterodyne down-converter, which will translate detected signals to a different frequency and bring them off-chip. This make

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45 it possible to avoid the contam ination of the substrate coupl ed signals caused by direct coupling through the package or through the board. Measurement results for narrow band signal in GHz range are also reported. 2.6 Proposed Embedded Substrate Noise Measurement In any measurement scheme discussed before, the paths taken by the coupled noise are difficult to distinguish from each other. For example, package-induced and substratecoupled signals are especially difficult to discriminate if their coupling strengths are similar. Detection of the coupling signal paths and strengths at different operating frequencies is also important, since signal coupling mechanisms typically will vary with frequency. Attempting to answer these challenges, our proposed work integrates the substrate noise measurement as an embedded system th at can detect broadband signals and deliver low-frequency analog test outputs through IC pa ds to a simple external test setup. DUT On-/Off-Chip Signal source Low Frequency Analog Output (To Tester) DUT Embedded Test circuits Substrate Contact LowFrequency External Tester Wafer Figure 2-14. Embedded substrate noise measurement

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46 As shown in Figure 2-14, the basis of em bedded substrate noise measurement is an on-/off-chip broadband signal sour ce plus some test circuitr y integrated with the DUT. The signal source acts as a noise generato r and injects well-know n signals into the substrate, and then the embedded test circuit will extracts useful information from the response of the detector into baseband signa ls, which are deliver off-chip to external tester. 2.6.1 Potential Benefits Compared to other existing substrate noi se measurement methods, the potential benefits offered by the proposed embedded test methods are listed as follows: The broadband signal detection enables th e investigation of substrate signal propagation mechanism at different operati on frequencies and the study of substrate parasitic influence on advan ced high-speed/RF circuits. Low-frequency output provides excellent is olation between input and output signal ports, and greatly improves the accuracy of the measurements. Crosstalk problem between RF probes is no longer a serious issue, and calibrati on procedure with rigid probe location control as mention in [46] can be avoided. Also low-frequency output will alleviate the requi rements for an external tester and help to cut down the test cost, as discussed in Chapter 1. On-chip test circuits will detect desire d signals and extract useful information before the signals are routed off-chip, thereby allowing the study on the effects of signal coupling through substrate and/or other paths separately (i.e. package parasitics induced substrate noise). Also, on-chip test circuits can be used for measurement in any type of semiconducto r substrate and simplify the measurement setups. 2.6.2 Design Issues Although our proposed work has all the adva ntages described above, several design issues have to be solved before the implem entation of such a system to be practically useful.

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47 First, the chip area overh ead brought by the additional test circuitry must be minimized due to economic considerations. It is not easy to shrink the system design without degrading the performan ce of on-chip test circuits. Secondly, calibration of on-chip test circuits is a substa ntial effort in order to guarantee and further extend the measuremen t accuracy. Precise, yet easier calibration techniques are desired to si mplify the calibration procedure and cut down the test cost. The third issue is the introduction of additi onal on-chip test circuitry should have few effects on other circuits on the same chip without degrading their original performance significantly. Finally, the on-chip test circuits should be done with minimal power consumption. If an on-chip signal source is employed, the power of the generated test stimulus should be kept low without compromising the signal quality. All the design issues listed here will be further discussed in the next few chapters when the designs of components in the proposed work are presented. 2.7 Research Goals A set of preliminary specifications for the embedded substrate noise measurement system was developed thr ough interactions with TI: Small detector size Sensitivity: 10’s of mV (for large ICs )/a few µV (for small ICs ) Bandwidth: 10 30 MHz Based on the specs above, our first goal of this work is to develop a low-frequency (10MHz) on-chip substrate noise measurement test vehicle to demonstrate the embedded system feasibility.

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48 The second goal is to develop a system capable of measuring substrate noise coupling over a very wide frequency span up to millimeter wave range.

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49 CHAPTER 3 AUTOMATIC GAIN CONTROL BASED MEASUREMENT SYSTEM 3.1 Introduction Automatic gain control (AGC), is one of the most useful circuits in modern communications receivers, and it is employed in systems where the input signal level varies over a wide dynamic range. AGC will det ect the amplitude of the receiv ed signal and automatically adjust the gain in order to maintain a constant output signal level. Since th e output signal level is always fixed, one can predict the input signal leve l if the gain information is known. This makes it possible to use an AGC as a signal strength meter for embedded substrate noise measurement. In this chapter, an AGC based embedded s ubstrate noise measurement test vehicle is presented as follows: first, the principle of AGC operation is discussed; next, detailed circuit designs are described; finally, si mulation results and measurement re sults are shown to verify the design. 3.2 Theory of AGC An AGC system is an intuitively nonlinear sy stem, and there seldom are general largesignal solutions to the nonlinear equations that describe the syst em dynamics. However, for most systems, an approximate solution can be de rived in terms of a small-signal model. A method is proposed in [62] to obtain consta nt AGC loop settling time independent of the received signals. Two assumptions are made for th e discussion: first, It is assumed that the AGC loop only responds to the signal amplitudes and all the signals are represented in terms of their amplitudes; second, the peak detector is assume d to extract the peak amplitude linearly and instantly (it operates much faster th an the basic operation of the loop).

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50 (a) (b) Figure 3-1. AGC circuit block di agram and linearized loop model The basic elements of an AGC system is shown in Figure 3-1(a). The input signal is amplified by a variable gain amplifier (VGA) whose gain depends on a control signal Vc. The peak detector measures the peak amplitude, Aout, of the amplified signal Vout and is compared with a DC reference signal Vref. The difference between these two signals (error signal) is then filtered and used to control the gain of the VGA, until the measured peak amplitude, VP, is made equal to Vref. Figure 3-1(b) illustrates a linearized AGC system that can be solved analytically. The transfer function of the VGA can be written as 1 1expln[()]ln()IN OUTVC VA AKGV K (3-1), where AOUT and AIN are the amplitudes of the input and output signals, respectively.

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51 The output y in Figure 3-1(b) is given by ln()CyxGV (3-2), and the gain control voltage is expressed as 2 0 t m CREFVG VVKyd C (3-3). Taking the derivative of Equation 3-2 w ith respect to time and we can get () 1 ()C CdGV dydx dtdtGVdt (3-4). Equation 3-3 can be rewritten with E quation 3-4 substituted in to yield 2 m REFVG dydx KVKy dtdtC 2()mm VREFGG dydx KKyKV dtCdtC (3-5), where () 1 ()C CCdGV K GVdV . Equation 3-5 describes a first-or der linear high-pass system a nd its time constant is given by 1 2 m VG KK C . Achieving a constant settling time will allo w the AGC loop bandwidth to be maximized for fast signal acquisition while maintaining st ability over all operating conditions. In classical designs, Gm and C are held constant, and criterion for constant AGC settling time comes to () 1 ()C CCdGV K GVdV =constant, which leads to the well-know exponential VGA gain characteristic requirement: 2()C K V CGVKe [63]. However, in CMOS technology, achieving an exponential relationship is not as obv ious as in bipolar technology. An additional degree of freedom can be obtained if the loop filter (Gm/C) is made nonlinear. As shown in Figure 3-2, a constant se ttling time AGC system can be realized with a Gm -1 block to generate the inverse function of the VGA. Assume the capacitance C is fixed and all the transconductances in the AGC loop are functions of VCP:

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52 11()()miCPimCPGVKGV , for i=1, Â… , N ()()mjCPjmCPGVKGV , for j=2, 3 (3-6), then the criterion for constant becomes 2()() ()mCPCP CPCPGVdGV GVdV =constant. Figure 3-2. Constant settling time AGC with arbitrary VGA gain and Gm control characteristic. It can be shown that AGC constant settli ng time can be satisfied for any monotonic nonlinear VGA gain versus control signal (VCP) relationship if the Gm has the same nonlinear function within a cons tant proportionality. Inside the Gm -1 block, Gm3(VCP) replicates the nonlinearity of VGA and integrator transconductances and is used to generate the inverse transcon ductance function. The negative feedback loop with the OPAMP will force32()CmCPLDCVGVRV ; hence, the inverse function is generated as: 1 32C CPm LDCV VG KRV (3-7).

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53 Note that function Gm( ) must be monotonic for Gm -1( ) to be valid. The VGA gain is the product of th e gains of N stages and is 11 1()()N CPmiCPLi iGVGVR (3-8). Using Equation 3-8, the VGA gain and loop filte rÂ’s transconductance ca n be written as a function of VC: 11 1 32()N N C CiLi i LDCV GVKR KRV (3-9), 2 2 32()C mC LDCKV GV KRV (3-10). Similarly, the overall time constant of the AGC in Figure 3-2 can be derived and is 3 2 2 D C L REFKV CR NKV (3-11). Note that zero gain state for loop filter tran sconductance must be prev ented; otherwise, the feedback loop will become broken indefinitely. A practical circuit implementation to eliminate zero gain state will be discussed later. 3.3 Circuit Design Our test vehicle will be designed based on the constant settling AGC st ructure in Figure 32. The Gm -1 block not only generates the inverse tran sconductance function that is important in the derivation, but also it provi des valuable information of V GA stage gain. When the loop is stable, one can write 32'()CDCmCPLVVGVR ; hence, the transconductance is 3 2' ()C mCP D CLV GV VR (3-12). Using Equation 3-8, the VGA ga in can be expressed as

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54 11 1 32' ()N N C CPiLi i LDCV GVKR KRV (3-13). By measuring VCÂ’ and setting the reference voltage Vref, the input signal amplitude can simply be calculated by Vref/G(VCP). Note both voltages are DC signals, which require very simple external measurement setup. 3.3.1 Variable Gain Amplifier As shown in Figure 3-3, the proposed VGA cons ists of a linear tr ansconductance cell, Gilbert cell-type differential pa irs and load resistors. The fixed input transconductor is a differential pair linearized through resistor degeneration. The differe ntial pairs of Gilbert cell are used to tune the output currents of the transc onductor and steer the co rresponding portion to the load resistors, which makes the VGA gain adjustable. The additional transistors, M21 and M22, are used to keep the VGA gain greater than zero. M11M12 M14 M13 Vdd Vdd Vdd Vdd Vdd Vdd M1M2 M9M10 M3M4 M7M8 M5M6 M17 M18 M16 M15 M19 M20 Vp1 VcVin+VinRs RL RL Vout+ VoutVp1 Vp2 Vn1Vn1 Vc+ VcVc+ I0I0ISI1I2 2I0 2I0 2I0-I3 2I0-I4 I3 I4 I5 I6 I7 I8 I9 IL I10 M21 M22 Vc+ Vc+ I7a I6a Figure 3-3. VGA cell schematic

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55 VGS,M1 and VGS,M2, are maintained constant due to the feedback provided by M5 and M6, which forces a constant current through the input transistors, M1 and M2. As a result, the differential input voltage appear s across the input resistor Rs, providing a constant transconductance1/mGRs . By observing the input currents, we then have 10S I II and 20S I II (3-14). The output currents, I1 and I2, of the input transconductor are 1:1 mirrored to the gain tuning differential pair: 13 I I and 24 I I . The control voltages, Vc+ and Vc-, are applied to the differential pairs, M11-M12 and M13M14, to adjust the currents to the load resistor: 50312C I fVII and 6032C I fVII (3-15), 80412C I fVII and 7042C I fVII (3-16), 67 672aa I I II (3-17), where 10CfV . The output stage consists of load resistors with common-mode feedback and current sources (M19 and M20). Since910 I I , 956 aL I III and 1078 aL I III , the output load current is 56782aa L I III I (3-18). Using Equation 3-14, 3-15, 3-16 and 3-17 , Equation 3-18 can be rewritten as 1LCS I fVI (3-19). The voltage gain of the VGA is then

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56 21 2 21CSL LLL V C SfVIR IRR Vout AfV VinVinVinR (3-20) where S SVin I R . For 10CfV , VGA zero gain state can be prevented. (a) M11M12 M14 M13 Vdd Vdd Vdd Vdd Vdd Vdd M1M2 M9M10 M3M4 M7M8 M5M6 M17 M18 M16 M15 M19 M20 Vp1 VcVin+VinRs RL RL Vout+ VoutVp1 Vp2 Vn1Vn1 Vc+ VcVc+ M21 M22 Vc+ Vc+ (b) Figure 3-4. DC offset cancellation for VGA causing multiple feedback loops Figure 3-4(a) shows the DC offset cancellation scheme used for the VGA stages. Multiple feedback loops are formed inside the VGA cell with DC feedback path applied. There are two negative feedback loops (Vin+-M1-RS-M2-M6-M18-M14 and Vin+-M1-M5-M17-M12-M21-RL-M20) and one positive feedback loop (Vin+-M1-M5-M17-M12-M21-RL-M22). Due to the presence of positive feedback loops (Figure 3-4(b)), there can be multiple operating points [64]. By doing DC sweep simulation on input bias voltage Vin and Vout, it shows (Figure 3-5(b)) three possible

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57 operating points for the VGA circuit when the DC offset cancellation st ructure is applied. Undesired operating points have to be removed to guarantee the stabil ity of the VGA circuit. (a) Desired operating point (b) Figure 3-5. Start-up circu it solves the multiple operating point problem in VGA In order to eliminate the unde sired operating points, a star t-up circuit is designed and added to the VGA cells, as shown in Figure 3-5(a). The simulation result in Figure 3-5(b) shows that the two extra operating points are avoided and the start-up circuit is transparent to the normal operation of the VGA. 3.3.2 Peak Detector The analog peak detector is a key piece in our AGC system. It detects the peaks of VGA output signals and holds the value to compare w ith the reference value (the desired value for

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58 VGA output), feeding the comparison results (errors) to the loop filter and Gm -1 stages to create a proper gain control signal [65]. (a) (b) Figure 3-6. Half-wave peak detect or and full-wave peak detector The simplified schematic of a classical half-wav e peak detector is shown in Figure 3-6(a). When a input signal Vin(t) arrives and is higher than the hold voltage Vout, the OTA will generate a sharp negative transition that switches M1 on. The current mirror M1-M2 will charge the hold capacitor C until Vout equals Vin. A simplified schematic of the proposed full-wave peak detector is shown in Figure 3-6(b). The tracking behavior of the p eak detector can be varied by tuning the transc onductance of the unidirectional current mirror a nd the loading capacitor C.

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59 3.3.3 Loop Filter and Gm-1 Block Figure 3-7. Loop filter As discussed in Section 3.2, the transconducta nce of the loop filter has to have the same gain versus control signal relati onship with a constant of prop ortionality as a VGA cell does. The loop filter consists of a “scaled ” version of the VGA cell and an integration capacitor at the output node (see Figure 3-7). The transfer func tion of the loop filter can be expressed as 1CmL inLVGR VsCR . Figure 3-8. Differential di fference amplifier (DDA) (CMFB circuit not shown) A differential difference amplifier (DDA) is used as the OPAMP in the Gm -1 block because the loop operates in differential mode. As shown in Figure 3-8, the proposed DDA has two differential input pairs and a differential output pa ir. When used in negati ve feedback with very large loop gain, the DDA forces the two differential inputs ( ccVV and''ccVV) to be

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60 identical and generates the corr esponding control voltage for the VGA stages. To ensure a wide output control voltage range, the DDA is implem ented as a folded cascade structure. A CMFB circuit is used to set common mode voltages of the two output nodes. 3.3.4 On-chip Bias and Voltage Reference Circuits As shown in Figure 3-9, a wide-swing consta nt-gm bias circuit is applied to provide onchip bias reference. A start-up circuit is in cluded to prevent zero current state for all the transistors. This bias circuit is consists of fo ur different feedback loops. The addition of the resistor RS kills the positive feedback loop gain, whic h makes the loop stable (the loop gain is less than one). However, if RS decreases, the positive feedback loop gain will increase and the system could become unstable. This effect will be discussed later in more detail. Vdd Vdd Vdd Vdd VddM8 M9 M1 M2 RSM7 M6 M4 M3 M11 M10 M5 M14 M15 M13 M12 M16 M17 M18Vbiasp Vcascp Vcascn Vbiasn Bias LoopCascode BiasStart-up Circuit IREF Figure 3-9. Wide-swing constant-gm bias circuit 3.3.5 T-switch To increase testability of the whole system, so me of the internal nodes need to be tested. One of the common ways to provide access to inte rnal analog signals is through analog test

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61 buses. The external tester can gain access to internal nodes by op ening and closing the appropriate transmission gates or other switching structures. (a) Vcontrol Vout Vin M0 (b) Figure 3-10. Transmission gate and T-switch The most common CMOS structure for implem enting an analog transmission gate is a back-to-back PMOS and NMOS transistor pair [9]. As shown in Figur e 3-10(a), complementary control signals are applied to the two transistor so that they are both on and off at the same time. However, a capacitive coupling path (drain-tosource capacitance) exists even when the transmission gate is turned off. This circuit will suffer from cr osstalk problem between input and output nodes. To avoid this problem, a T-switch is used in our design (Figure 3-10(b)). The ground transistor M0 is closed whenever the switches are opened, thereby shunting any crosstalk signals to ground. 3.3.6 Overall System with Embedded Test Points The proposed overall system, including two VGAÂ’s, peak detector, loop filter and Gm -1 block, is shown in Figure 3-11(a). Two embedded test points, SW1 and SW2, are inserted into the design for more testability. Each test point c onsists of six T-switches (all the signal paths are differential), as shown in Figure 3-11(b). Additi onal control signals are provided to control the signal paths of the embedded test points in differe nt test modes. For example, if SW1 is turned

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62 on, then the VGA output nodes are disconnected fr om the internal signal path to the peak detector and connected to the buffer so that they can be externally accessed. (a) (b) Figure 3-11. Overall AGC system with embedd ed test points and embedded test point implementation 3.4 Simulation of AGC Design The proposed AGC circuits were simulated using Cadence Spectre with IBM7wl BiCMOS 0.18um models. Figure 3-12 shows gain tuning curve of th e VGA in the inverse gain control loop (DC gain) and a VGA in the signal am plification path. Gain inform ation of signal amplification (VGA) stage can be predicted by obtaining th e gain control characteristic of VGA in Gm -1 block. Constant offset between two gain tuning curves can be calibrated easily. The average gain tuning sensitivity is around 25dB/V.

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63 Figure 3-12. Gain tuning curve of VGA blocks Frequency responses of the two-stage VGA in di fferent gain modes are shown in Figure 313. The upper -3dB corner frequency is 20MHz. Figure 3-13. Frequency response of two-stage VGA The linearity of the two-stage VGA is specif ied by single-tone total harmonic distortion (THD) in maximum output swing mode (400mVpk) in Figure 3-14. It shows around 1% THD for input signal range from 40mV to 200mV.

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64 Figure 3-14. Linearity of two-stage VGA in THD (%) versus input signal strength Figure 3-15 shows the input versus output char acteristic of the peak detector for DC input and 10MHz sine wave input. The tr ansfer function is reasonably linear when input is in the range of 5mV to 400mV. Figure 3-15. Input versus output characteristic of peak detector

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65 The proposed AGC system in Figure 3-11 is simulated using the transient response for a 10MHz sine wave whose initial input amplitude is 10mVpk, but every 4µs the input signal strength is increased to 20mVpk, 50mVpk. Th e response of VGA output is shown in Figure 316. The difference of settling time is due to the different initial startup transient when the input signal strength is changed. Figure 3-16. Transient response of AGC to a 10 MHz sinusoidal input wi th varying amplitude 3.5 Measurement Results The proposed AGC system in Figure 3-11 was laid out using IBM7wl 0.18µm process with 7 metal layers. Figure 3-17 shows the die p hoto for the fabricated AGC chip. The total chip area including bond pads is 2000 x 2000µm, wh ereas the actual AGC circuit area is 1500 x 1300µm. The 10pF loading capacitor for peak det ector is integrated on chip, while two 100pF capacitors for loop filter are provided externally. With all prepared measurement setups, an unexpected problem were found during basic DC measurement. The bias circuit, shown in Fi gure 3-18, consists of current mirrors providing gate voltages to cascade structures of PMOS an d NMOS transistors. An external resistor is connected to allow the bias current to be adjusted for process variations. It is designed to provide

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66 50µA current with an external resistor of 2.2K . A grounded variable resistor RS is connected through DC probe to the chip. However, at cer tain frequency, the positive feedback loop oscillates because th e parasitic capacitor CP (provided by bond pad, DC probe decoupling capacitor, connection wire, etc.) reduces the impedance at the source of M2. A solution for the stability problem is to keep the loop gain of positive feedback smaller than one all the time. Instead of using external resistor, a fixed value onchip resistor can be applied to insure the stability of bias ci rcuit (by minimizing the parasitic capacitance Cp at the drain of M2). SW1 BUF Peak Detector -1 SW2 Figure 3-17. Microphotogr aph of the AGC system Due to the on-chip bias circuit oscillation, the evaluation of overall system performance is impossible at this time. Additional chip fabrication is needed in the future.

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67 Figure 3-18. Bias circuit with external resistor connection 3.6 Conclusions For low-power application, the linear am plification (AGC) has a limited useful instantaneous input dynamic range before saturati on occurs. Also, the frequency response of the peak detector sets the limit for AGC on high-frequency signal pr ocessing. Finally, the large chip area overhead of the embedded AGC circuits preven ts the practical application of this technique.

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68 CHAPTER 4 LOGARITHMIC AMPLIFIER DETECTOR As discussed in Chapter 3, in order to develop a compact embedded system capable of measuring substrate noise coupling over a very wide frequency span, alternative methods must be found. 4.1 Introduction A logarithmic amplifier can be employed as an embedded signal strength indicator for substrate coupling measurements. Compar ed to a linear AGC-based measurement method, the advantage of this technique is that it can detect broadband signals and compress a much wider input dynamic range into a small range at the output. This chapter is organized as follows. First, existing logarithmic amplifier techniques are discussed. Next, the circuit design of a logarithmic amplifier is described, followed by simulation results. Finally, limitations of this method for embedded substrate noise measurement will be discussed. 4.2 Review of Various Logarit hmic Amplifier Techniques Logarithmic amplifiers can be found in many applications in the fields of communication and of measurement systems [66]. A logarithmic amplifier can be realized with an inverting operational amplif ier circuit with nonlinear feedback (Figure 41), which obtains excellent logarithmic response from the PN junction I-V characteristic. + VinVLOGRin(a) (b) Figure 4-1. Transconductance feedback loga rithmic amplifiers with (a) diode or (b) transistor

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69 Assume the forward conducted diode obeys the following constitutive law LOG TV V diodesIIe (4-1), where VT=kT/q, k is Boltzman constant, T is absolu te temperature, q is the charge of an electron, and Is is the scale current proportiona l to the area of diode junction. By writing current node equati on at the negative input of the op-amp in Figure 4-1, in diodein inV II R (4-2), and combine with Equation 4-1, the log output of the transconductance feedback logarithmic amplifier can be obtained as: log()in LOGT SinV VV I R (4-3). However, elaborate compensation techni ques (i.e., temperature compensation) are required to make the transconductance feedb ack logarithmic amplifiers meet the demands of most applications. Dynamic range and re sponse time also limit their application. A more powerful logarithmic techniqu e is the use of successive-detection architecture, wherein the summation along a cascade of identical limiting amplifiers approximates the logarithmic function as a piecewise-linear function. This method depends on the circuit archite cture to produce a (pseudo-)log arithmic transfer function without relying on a physical deviceÂ’s nonlinearity. A simplified block diagram of a commonly used pseudo-logarithmic amplifier is shown in Figure 4-2. Several identical lim iting amplifiers are cascaded to obtain limiter outputs and each limiter output is fed into rect ifier. The output curren ts of the rectifiers are summed with a low pass filter (LPF), whic h is used to determine the received signal level.

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70 Figure 4-2. Simplified block diagram of successive-detection logarithmic amplifier Consider a logarithmic amplifier with N cascaded stages, each having a smallsignal voltage gain of AV, with a limiting voltage VL. As shown in Figure 4-3, assume the mth stage is driven to voltage-limited output, m VinLAVV , where Vin is the amplitude of the sinusoidal input signal. As the signal progresses down the gain chain to the subsequent stages, it will begin to clip. And th e output of the summer will be written as: 231...(1) 1 (1) 1m LOGinVinVinVinVinL m V inL VVVAVAVAVAVNmV A VNmV A (4-4). Vin Lim Out Log Out 1st2ndmth(N-1)thNth (m+1)th VinAVVinAV 2VinAV mVin=VLVLVLVL VinAVVinAV 2VinAV mVin=VLVLVLVL Low Pass Filter VLOG Figure 4-3. Signal flow in a succ essive-detection logarithmic amplifier

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71 If1VA, then Equation 4-4 can be simply written as: 1(1) log 1 1 log log 1 log1 loglogm VinL in L LL VV LL inL VVVAVNmV V V NVV AA VV VNV AAA (4-5). Equation 4-5 shows a linear relationship between the output of the detector and log()inV . The slope of the transfer function is given by logL VV A , and VL and AV will be obtained from calibration of the circuit. Then the nominal output voltage of the logarithmic amplifier for any input level w ithin the linear range of the device can be predicted by using Equation 4-5. 4.3 Logarithmic Amplif ier Circuit Design Considering the multistage limiting amplifie r structure shown in Figure 4-2, input signal dynamic range and frequency determine total gaintotA and overall 3-dB bandwidthtot . In order to achieve desired accura cy and minimize power consumption, the following questions need to be answered . What is the optimum number of stages which will require the least gain-bandwidth product per stage? What is the output log conformance (error) within the input signal range? To simplify the problem, assume that each stage is represented by an ideal voltage amplifier A0, an output resistance Rout, and a load capacitance CL [67]. The overall transfer function is then given by:

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72 0 0() 1nA Hs s (4-6) where1 0()outLRC is the 3-dB bandwidth of each stage. To determine the optimum number of stages, we employ the 3-dB bandwidth tot of the overall system as a measure of its speed. Assumetots and calculate the value of 0 such that 00 2 02 1n n totAA (4-7) Thus, one obtains 021n tot (4-8). For2 n , (4-5) can be approximated as: 00.9totn (4-9). Let B denote the gain-bandwidth product of a single stage and assume B to be constant for a given power dissip ation in a given technology, then 1 000.9tot n totn BAA (4-10) 10.9tot n totB An (4-11). To minimize the denominator, 1n totDAn , take its natural logarithmic and differentiate with respect to n:

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73 2111 ln 2totD A Dnnn (4-12). The optimal number of stages can be calculated as 2ln()opttotnA (4-13). Figure 4-4 shows single stage gain A0, bandwidth 0, gain-bandwidth product B and as a function of the number of st ages with overall 3-dB bandwidth (tot ) of 100MHz and overall cascaded gain (Atot) of 80dB. 1 5 10 15 20 25 29 0.01 0.05 0.1 0.5 1 1 5 10 15 20 25 29 1 5 10 Figure 4-4. Normalized gain, bandwidth a nd gain-bandwidth produc t for a single stage versus the number of stag es for overall gain of 80dB As derived in Appendix A, the accuracy of logarithmic amplifier (defined as input error) is closely related to single stage gain A0, which is determined by Atot and the number of stages. As shown in Figure 4-5, input error decreases for smaller value of single stage gain A0.

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74 0 5 10 15 20 25 30 35 40 10-2 10-1 100 101 Stage numberMaximum Error (dB) Figure 4-5. Maximum input error versus the nu mber of stages for overall gain of 80dB From the discussion above, the optimal nu mber of stages is determined by both bandwidth and accuracy. Depending on the system specifications, tradeoffs must be made to satisfy the bandwidth and accuracy requirements. The initial specifications for the proposed logarithmic amplifier detector are to operate at 100MHz with ±1dB accuracy and w ith sensitivity within µV range. Hence the 3-dB bandwidth and overall gain are chosen to be 100MHz and 80dB. From Figure 4-5, the optimum stage number for ±1dB error is 9. Using Eqn. (4-9), the -3dB frequency corner for a single amplif ier stage is about 333MHz. 4.3.1 Limiter Design An NMOS differential pair with NMOS load is often used for limiting amplifier stages (Figure 4-6 (a)). The advantage of this configuration is that the gain depends on the ratio of input transistor size and load transistor size. Using the square law equation

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75 (ignoring body effect) of NMOS transistors, the voltage gain of this circuit can be shown as: 11 33(/) (/) g mWL A g mWL (4-14) (a) (b) Figure 4-6. Limiting amplifiers But in a n-well CMOS process, the NMOS loads suffer body effect and therefore the gain also depends on gmb of the loads. The body effect can be eliminated using current mirrors (Figure 4-6 (b)). But then the gain of such a circuit depends on the accuracy of the current mirrors. Other drawbacks of the second configuration include extra power consumption and degraded frequency response. The triple-well transistor provided by IBM SiGe process enables one to get rid of body effect on the load transistor with the penalty of slightly increased chip area. Figure 4-7 shows a discrete triple-well NMOS transistor and the limiting amplifier using triple-well NMOS loads. Deep nwell shields the bulk of the transistor from substrate and the source can be tied to the bulk.

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76 (a) Cross-section view of a triple-well NMOS transistor G S D Nwell Contact P-Sub Vdd Vin+VinM1M2 M3M4 (b) Limiting amplifier Figure 4-7. Limiting amplifier using triple-well NMOS loads 4.3.2 Rectifier Design In an architecture of piecewise linear approximation (Figure 4-2), each piece of linear session is obtained by rectifying each ga in cell output of the limiting amplifier. All the rectified waveforms are then summed a nd filtered to yield a DC-like indicating voltage. Multipliers based on Gilbert cells (Figure 4-8) can be used as full-wave rectifiers. Transistor M1-M4 act as switches and M5-M6 act as a differential pair. Rectification is achieved by turning on M1-M4-M5 and M2-M3-M6 alternatively during positive and negative cycle of Vin. But they are not appropriate for low voltage operation because they use four stacked transistors.

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77 Vin+M5 M1M2 VinM6 M4 M3 Vdd M7M8M9 Vin+ Vin+ VinIout Figure 4-8. Gilbert cell based rectifier Kimura proposed a technique for CMOS ps eudo-logarithmic rectifiers operable on low supply voltages [68] [69]. Vin xN M3 M1M2 ID2+ID3xN x1x1 M4 ID1+ID4I0I0 (a) (b) Figure 4-9. Full-wave rectifier w ith unbalanced source-coupled pairs Figure 4-9(a) shows two identical unbalan ced source-coupled pairs with one pair size N times as large as the other. The circu it schematic of complete full-wave rectifier with unbalanced source-coupled pairs is show n in Figure 4-9(b). A ssume all transistors are operating in the saturation regi on, the differential output current, Iout , is calculated in Equation 4-15.

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78 1423 0 2 0 00 22 0 0 2 0()() , 1(1) 24 11 , 2(1)4(1) 2 , (1)1 , 0outDDDD in in in ininin inIIIII I whenV N NNN IV NN II whenV N I NNVNVNNV NI NN I whenV (4-15), where 1 () 2noxW C L, µn is the effective surface mobility, COX is the gate capacitance per unit area, W is the gate width and L is the gate length for an NMOS transistor. When input voltage is small ( 0 in I V N ), most of the current will flow through the larger size transistors (M1 and M4), and Iout is a parabolic func tion of input voltage. As input voltage increases ( 00 in I I V N ), smaller size transistors (M2 and M3) start to contribute current on the left, and Iout can be approximated as a logarithmic function. When input voltage 0 in I V , the output current is zero. As shown in Figure 4-10, assume the mth stage is driven to voltage-limited output, m VinLAVV and the rectifier output can be approximated aslog()outinVKV . Using Equation (4-15), the output of the summer will be written as:

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79 21log()log()log()...log() 1 [(1)log()log()] 2m L OGinVinVinVin VinVKVKAVKAVKAV mKmAV (4-16), which will exhibit a negative slope in output tr ansfer curve, as shown in Figure 4-11 and 4-14. Figure 4-10. Signal flow in a successive-det ection logarithmic amplifier with pseudologarithmic rectifiers 2I0 6X 8X 16X 0 V in I VLOG VLOG Figure 4-11. Simulated DC transfer curve fo r full-wave pseudo-logarithmic rectifier and ideal VLOG curve versus input voltage Figure 4-11 shows DC transfer curve for di fferent values of N. If the ratio of unbalanced source-coupled pair (N) increase s, the pseudo-logari thmic function input

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80 range are widened. However, larger N means more input parasitic capacitance for the input transistors, which will degrade the fr equency response of the rectifier. N=6 is chosen for the proposed rectifier design. 4.3.3 DC Offset Cancellation DC offset cancellation is a very important issue in the limiter design since the mismatch of the devices could cause significant offset and smear the small input signals. CCCC RRRR Bias (a) (b) Figure 4-12. DC offset cancellation techniques Two different approaches are considered for DC offset cancellation. The first method (Figure 4-12(a)) is to use coupling capacitors between each stage of the limiting amplifiers. The coupling capacitors eliminate DC offsets and the re sistors provide input DC bias voltage for the next stage. The values of C and R determined the high pass corner. The major drawback of this method is that passive compone nts occupy large chip area. The other method (Figure 4-12(b)) is to us e DC feedback circuit, which requires an external capacitor C2. The second method was chosen because it leads to less chip area overhead.

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81 4.4 Simulation Results and Analysis The useful dynamic range of a successive-d etection logarithmic amplifier is limited on the lower end when all stages are in the linear region or input noise floor causes the last stage to its limiting voltage. And the uppe r limit is reached when the input causes the first stage in the cascade structure to clip. The proposed logarithmic amplifier is de sign and simulated with IBM7wl BiCMOS 0.18um models. For the simulation, the power supply is 1.8V and the DC bias current is 7.85mA. (a) (b) Figure 4-13. Simulated AC response of (a) single-stage and (b) 9-stage limiting amplifier

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82 AC response of single-stage and 9-stage limiting amplifier are shown in Figure 413, which ensures the proper operation of loga rithmic amplifier at the desired frequency (100MHz). The -3dB frequency of entire amplif ier chain is 316 MHz, which also can be estimated using Equation 4-9. Figure 4-14 shows the logari thmic amplifier RSSI output (logarithmic output) and the input signal dynamic range at 100MHz. At 25C , the log conformance is to within ±1dB for an input in the range of -80 to 0 dBV (100µV to 1V), which satisfies the system accuracy requirement. Figure 4-14. Simulated RSSI output a nd input error versus input voltage The performance of the logarithmic amplif ier at different temperatures is also examined. From Figure 4-15, it is found that th e input error (as define d in Appendix A) is around ±1dB for temperature variation from -40 to 100C when input signal level is in the range of -80 to 0 dBV, which is accepta ble for measurement system specifications. As shown in Figure 4-16, for 100MHz si nusoid input with 10mV amplitude, the output voltage variation is around ±0.06dB for temperatur e varying from -40 to 100C . By examining the relation between the input voltage and output voltage in Equation (4-

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83 14) and (4-15), it can be shown this varia tion mainly results from the “proportional-tothe-absolute-temperature” (P TAT) bias tail current I0. If the bias circuit is improved to be temperature independent, it is expected that the output variation will be further reduced. Figure 4-15. Output erro r versus input voltage Figure 4-16. Output erro r versus temperature The fabrication procedure of CMOS inte grated circuits is highly complex nowadays. Most submicron MOS technology us e more than 10 masks for over 100 steps of chemical processes to depos it oxide layers and phot oresist materials, to transfer mask patterns to wafers with optical lithography, followed by chemical etchings. Even with computer-controlled high-precision fabrication steps, some errors, for example, in mask

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84 alignment, doping or implantation of targeted amounts of impurities, chemical etching of polysilicon gate lengths of MO S transistors, and thickness co ntrol of the thin-gate oxide layer are inevitable. The performance of logarithmi c amplifier circuit critically depends on the geometry characteristic of MOS transistors, which can vary due to process variations and mismatches between devices. To account for the process and mismatch variations, which have a more vital impact on production yields as processes continue to be scaled down to smaller geometries, Monte Carlo analysis or corner analysis can be employed to the proposed logarithmic amplifier. Monte Carlo analysis allows the study of how the manufacturing variations affect the production yield of the design. Typically statistically varying parameter values are included in device models and the shape of each statistical distri bution represents the manufacturing tolerances on devices. Monte Carlo analysis performs multiple simulations, with each simulation using differe nt parameter values for the devices based on the assigned statistical distributions. The distribution of performances will provide designer useful information to examine how manufacturing tolerances affect the overall production yield of the design and change th e design to improve the yield. However, Monte Carlo simulations are co mputationally extremely expens ive, especially for large circuits. One method of reducing the computati onal requirements of Monte Carlo simulations is to perform desi gn verification at a set of corn ers, which are expected to represent the conditions that re sult in worst-case performan ces. Corner analysis looks at the performance outcomes generated from the most extreme variations expected in the

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85 process, supply voltage, and temperature values (“the corners”). With this information, it can be determined whether the circuit performa nce specifications will be met, even with the combination of random pr ocess variations in their most unfavorable patterns. Compared to Monte Carlo analysis, the adva ntage of corner analysis is its relative simplicity. However, the biggest issue with co rner analysis is if the corners are not provided, then the designer may not know wh at the corners actually are, which will frequently lead to wastes of design time, or even a design impossibl e to realize. Since no worst case corners are available in IBM7wl and the technology provides statistical models, Monte Carlo analysis is pref erred here for design verification. In the first Monte Carlo analysis, the size of sample is 200 and 100MHz sinusoid input is assumed with 10mV amplitude. Within three standard deviations ( ) of the mean (µ), simulation with mismatch only (Figur e 4-17(a)) shows 1.99% variation of output voltage. Figure 4-17(b) shows 9.97% variat ion of the output volta ge caused by process variation. Mismatch plus process variation led to 9.17% variation of output voltage, as shown in Figure 4-17(c). Figure 4-18(a), 4-18(b) a nd 4-18(c) shows the simulated logarithmic amplifier output distributions with mi smatch, process variation and mismatch plus process variation from the second Monte Carlo analysis. The input signal amplitude is changed to 100mV while with same frequency 100MHz as the first analysis. Within three standard deviations ( ) of the mean (µ), simulation results show 2.35% output voltage variation by mismatch, 11.29% output voltage variati on by process variation, and 10.51% output voltage variation by mismatch plus process variation.

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86 0.515 0.52 0.525 0.53 0.535 0.54 0.545 0 5 10 15 20 25 30 35 40 45 50 Vlog (V)Number of samples = 0.5280V= 0.0035V (a) 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 0 10 20 30 40 50 60 Vlog (V)Number of samples = 0.5267V= 0.0175V (b) 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0 5 10 15 20 25 30 35 40 45 Vlog (V)Number of samples = 0.5266V= 0.0161V (c) Figure 4-17. Logarithmic amplifier output dist ributions with mismatch, process variation and mismatch plus process variat ion (10mV 100MHz si nusoid input).

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87 0.41 0.415 0.42 0.425 0.43 0.435 0 5 10 15 20 25 30 35 40 45 50 Vlog (V)Number of samples = 0.4204V= 0.0033V (a) 0.37 0.38 0.39 0.4 0.41 0.42 0.43 0.44 0.45 0.46 0.47 0 5 10 15 20 25 30 35 40 45 Vlog (V)Number of samples = 0.4198V= 0.0158V(b) 0.38 0.39 0.4 0.41 0.42 0.43 0.44 0.45 0.46 0.47 0 5 10 15 20 25 30 35 40 45 Vlog (V)Number of samples = 0.4196V= 0.0147V (c) Figure 4-18. Logarithmic amplifier output dist ributions with mismatch, process variation and mismatch plus process variat ion (100mV 100MHz si nusoid input).

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88 Table 4-1. Logarithmic amplifier output va riations under different conditions (10mV 100MHz sinusoid input) Condition Mean output VLOG (V) Output voltage standard deviation (V) Output voltage variation (%) Mismatch 0.5280 0.0035 1.99 Process Variation 0.5267 0.0175 9.97 Mismatch plus process variation 0.5266 0.0161 9.17 Table 4-2. Logarithmic amplifier output va riations under different conditions (100mV 100MHz sinusoid input) Condition Mean output VLOG (V) Output voltage standard deviation (V) Output voltage variation (%) Mismatch 0.4204 0.0033 2.35 Process Variation 0.4198 0.0158 11.29 Mismatch plus process variation 0.4196 0.0147 10.51 The performance of the logarithmic am plifier under different conditions is summarized in Table 4-1 and 4-2. For the Mo nte Carlo simulations discussed here, it is assumed ideal external resistor and capacitor are used at the output (LPF). The results all show very small variation of VLOG ( max=0.0175V), demonstrating the processindependent merit of the successive detecti on architecture for small signal (10mV) and large signal (100mV) measurement. As shown in Figure 4-19, a good agreement of logarithmic amplifier output voltage between Cadence simulation (assuming perfect matching, with nominal power supply

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89 1.8V at 25C ) results and theory va lues calculated from Equa tion (4-16) was found and it shows ±0.4dB output erro r for over 80dB input signa l range (-90 to 0 dBV). Figure 4-19. Logarithmic amplifier output voltages from Cadence simulation versus theoretical values 4.5 Conclusions Comparing to linear AGC-based detector , the proposed logarithmic amplifier detector has a much wider input signal dynami c range, occupies smaller chip area (904 x 476µm including bond pads, active circuit area 5 00 x 185 µm). Circuit simulations were performed under different temperature, mism atch and process variation conditions. Small variations of the output voltage show the robustness of the logarithmic amplifier. Temperature compensation and careful layout techniques will further improve the circuit performance. However, for a given accuracy requirement, frequency response of the rectifiers and the multi-stage amplifier structure set the fundamental limit for signal detection frequency (hundreds of MHz).

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90 CHAPTER 5 DOWN-CONVERSION BASED MEASUREMENT SYSTEM In order to develop a compact embedded system capable of measuring substrate noise coupling over a very wide frequency span, a new technique based on frequency translation is proposed. 5.1 Introduction As shown in Figure 5-1, a new broadba nd embedded measurement technique is proposed to measure and characterize substr ate noise in RF/microwave ICs. Substrate noise is introduced by injecting a well-defined signal from an external signal source into the substrate. An external LO signal is s upplied to the on-chip mixer at a frequency slightly offset from the injected signal fr equency. The detected signal is down-converted to baseband and fed to low frequency external test equipment. By varying input signal frequency and LO signal frequency correspondi ngly, substrate noise coupling over a very wide frequency range can be investigat ed. Comparing to linear AGC-based and logarithmic amplifier based measurement meth ods, the advantage of such technique is that it can detect broadband signals. Figure 5-1. Down-conversion base d substrate noise measurement

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91 This chapter is organized as follows . First, the down-conversion based measurement technique is presented. Next , a down-conversion mixe r circuit design is described. This is followed by the test se tup and measurement results that verify the circuit performance. In addition, Appendix B introduces the fundamentals of calibration for RF measurement, which is helpful for the understanding of the substrate coupling measurement setup and data extraction. 5.2 Down-Conversion Mixer The key piece of the system is the downconversion mixer, which will translate an incoming RF signal (from the substrate) to a lo wer frequency, so that an external tester could perform signal strength detection at IF or low frequencies. Down-conversion mixers based on signal multiplication are usually preferred because ideally they generate only the desired intermodulation product. Also, good isolatio n between all three signals (RF, LO and IF) can be achieved because of the separate ports for the different signal sources [70]. Most down-conversion mixers are three-po rt devices, as show n in Figure 5-2(a). They take two input signal s: the RF signal, Asin( RFt) and the LO (local oscillator) signal, Bsin( LOt). The output is a mixing product of these two inputs and is an intermediate frequency (IF) signal: sinsincos()cos() 2RFLORFLORFLOAB AtBttt (5-1). The output contains the su m (“up-conversion”) and diffe rence (“down-conversion”) of the two input frequencies. For down-conve rsion mixers, the lowe r frequency (“IF”) component is the desired one and can be obtained by low-pass filtering the mixer output signal, as shown in Figure 5-2(b).

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92 Down Conversion Mixer LO RFIFsinRF A t sin L O B t (a) RFLO RFLO L O RF (b) Figure 5-2. Multiplication based mixer and its signals spectrum 5.2.1 Introduction Active mixers can provide large voltage gain by proper choice of device size and bias current. By virtue of their gain, active mixers reduce the noise contributed by subsequent stages. Figure 5-3. Simplified mixer The simplified version of perhaps the most popular multiplier is shown in Figure 53. RF voltage signals are fi rst converted into current IRF and then the multiplication is

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93 done in the current domain. Two possible topologies of implementing CMOS active mixers are shown in Figure 5-4. (a) VLO M1M2 M4 M3 M5 M6 VIF Vdd VRF(b) Figure 5-4. Single-balanced and double-balanced mixers The advantage of single-balanced mixer is its simplicity. But the major problem of such a configuration is the LO-IF feed-through. Usually VLO is chosen large enough so that the transistors M2 and M3 switch alternatively all of the tail current from one side to the other at the LO frequency. Now c onsider a more realistic case when M2 and M3 are both on for certain part of th e period. During this time, M2 and M3 operate as a differential pair, thus amplifyi ng the LO signal. The large LO content at the output might desensitize the succeeding stages . In the case of doubl e-balanced mixer of Figure 5-4(b), two differential pairs are connected in antiparallel in terms of LO, providing a firstorder cancellation. Therefore, the LO terms sum to zero at the out put, providing a high degree of LO-IF isolation. Conversion gain of a mixer is defined as th e ratio of desired IF output to the value of the RF input. For the multiplier described in Figure 5-2, ignoring the “up-conversion”

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94 component in Equation (5-1), the conversion gain can be calculat ed as the IF output amplitude, 2ABdivided by amplitude of RF input, A. Hence the conversion gain is 2V B A , which is half of the LO amplitude. In practice, the LO provides a periodic switching input rather than a sinusoidal waveform. For a square waveform with period 2LO , it can be expressed as: 1,3,5...4sin() ()cos() 444 cos()cos(3)cos(5)... 35LOLO n LOLOLOn Vtnt n ttt (5-2). For the mixer shown in Figure 5-4(a), RF input is converted into current through M1, thus 1()cos()RFmRFRF I tgVt (5-3). Combine Equation (5-2) and (5-3), the output can be obtained as: 1411 ()[cos()cos(3)cos(5)...]cos() 35outmLLOLOLORFRFVtgRtttVt (5-4). Ignoring the high order harmonics of the LO signal and the up conversion term, the output and the conversion gain of a dow n-conversion mixer can be shown as: 12 ()cos()outmLRFRFLOVtgRVt (5-5) 12out VmL RFV AgR V (5-6).

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95 By increasing bias current or W Lof M1, we can increase gm1 and therefore the conversion gain of the mixer. This result also can be applied to double-balanced downconversion mixers (Figure 5-4(b)). Noise analysis in mixers is different from traditional white noise analysis for linear and time invariant systems. It can be shown that thermal noise in an RF input transistor is totally transferred to output, as in a single-stage amplifier [73]. For a single-balanced mixer shown in Figure 5-4(a), during the time interval when LO voltage is less than Vds,sat of the switching transistors M2 and M3, both transistors are turned on and contribute to th e output noise, behaving like a differential pair. The noise from switching pairs can be solved using a stochastic differentia l equation [71] [72]. Simple and fast estimation tec hniques for mixer noise analysis are presented in [73] [74]. It is shown in [73] that the corresponding output noise PSD is: 2 23 23168()mm n mmgg ikTkTGt gg (5-7). where 23 23()2mm mmgg Gt gg , gm is the gate transconductance, k is BoltzmannÂ’s constant, T is the absolute temperature, and is 2/3 for long-channel tran sistors but can be higher for short-channel devices. Increasing the channel length of switching transistors is desi rable because this decreases gm2 and gm3, reducing the output noise contribu tion. However, larger transistors size will introduce more parasitic capacitance, which can degrade the mixer performance at high frequencies and can repr esent a larger load for the ci rcuit driving the mixer. Large LO amplitude increases the conversion gain and also reduces the noise contribution of switching pair.

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96 5.2.2 Circuit Design Schematic of the double-balance down-conve rsion mixer used in this design is shown in Figure 5-5. This mixer is employe d as down-conversion se nsor, with one input terminal capacitively coupled to the substrate contact (“ detection node”) through a MOS cap and the other tied to a “quiet” reference. Figure 5-5. Down-conversion mixer schematic 5.3 Verification of Mixer Design The down-conversion mixer shown in Figur e 5-5 was fabricated in the IBM7wl BiCMOS 0.18µm process. The microphotograph of mixer test stru cture is shown in Figure 4-14. The whole chip area is 1016 x 576 µm, which is mostly limited by bond pads. The core active area is only 232 x 296 µm and takes around 12% of the entire chip area. The input coupling and bypass capacito rs are 9.2pF each. The poly resistors Rb1 and

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97 Rb2 are 100K and isolate the RF input bias from RF signal source. The 50 resistor Rrf is also integrated on-chip for broadband input matching. GND GND GND RF LO+LO-GND Ref GND IbiasVRFGNDVDDGND IF Out+ IF OutGND Active Area 232×296 µm2 Figure 5-6. Microphotograph of the down-conversion mixer 5.3.1 Test Setup and Calibration The DC measurement is quite easy to set up. By applying correct DC biases to the corresponding pads through DC probe, one can obs erve the total bias current and output bias voltage. The bias curre nt is tuned by adjusting a potentiometer connected to Ibias pad. A star grounding scheme is us ed to avoid ground loop problem. RF BALUN Bias T Figure 5-7. Mixer measurement setup

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98 The characterization of a mixer is complicated procedure and the basic measurement setup is shown in Figure 5-7. Unlike DC measurement, RF measurement does not give instant, accurate results. All the elements on the signal propagation path will bring signal loss and reflect ion; hence the actual input signal power into the DUT will not be equal to the one coming out of the signal generator. Calibration has to be employed in order to obtain actual incident power and accurate experiment data. The oneport SOL calibration scheme is discussed in Appendix B. Since the mixer output impedance and spect rum analyzer input impedance is not matched, an off-chip OPAMP based external buffer is used to provide isolation between mixer output and spectrum analyzer. (a) (b) Figure 5-8. External buffer

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99 The configuration of an OP-AMP based buffer is shown in Figure 5-8(a), low distortion differential driver (AD8138 from Analog Devices) and differential driver evaluation board are used in actual buffer de sign (Figure 5-8(b)). This driver has low output harmonic distortion of -85dBc at 20MHz offset, low input voltage noise of 5nV/ Hz, and 3-dB bandwidth of 320MHz. For single-ended input signal, the buffer input impedance and the voltage gain can be calculated as follows: 1 2()G in F GFR R R R R (5-8) 4out F V inGV R A VR (5-9). A high impedance probe can also be used as output buffer and it provides zeroing control for more accurate measurement resu lt. In our measurement, a GGB picoprobe (Model 34A) is employed as the external buffe r. The input impedance is approximately 10M shunted by 0.1pF with a probe rise-time of around 120ps. It attenuates the output signal by a factor of 20:1 and its outp ut was designed to plug into a 50 input impedance instrument. The 3-dB bandwidth of this high impedance probe is 3GHz. 5.3.2 Measurement Results For the test chip measurement, the power s upply is 2.5V and the DC bias current is 1mA. The external LO power applied to one LO port is about 2dBm, equivalent to a peak-to-peak voltage swing of 0.8V. At the RF port of the down-conversion mixe r, the measured reflection coefficient (S11) is below -10dB from 5GHz to 20GHz, as shown in Figure 5-9. It shows good input

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100 impedance matching over wide frequency span , which is achieved by the use of on-chip 50 resistor. Figure 5-9. Mixer Reflection Co efficient (S11) at RF Port The second measurement is to determine th e linearity of the mixer. It is very important because the mixer is the first block of the system and it determines sensitivity of the overall system. By obtaining the output ve rsus input characterist ic of the mixer, RF input signal level can be predicte d from the measured IF output. Measurement results for input signals at different frequencies (5GHz to 20GHz) are shown in Figure 5-10. Note that the sensitiv ity (from less than -60 dBm to greater than 2dBm) of the mixer is more than adequate to meet the initial system specification mentioned in Chapter 2. The voltage conversi on gain of the mixer is around 10dB and the measured LO-RF isolation is below -37dB up to 20GHz.

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101 Figure 5-10. Mixer ou tput linearity versus input signal level 5.4 Summary and Conclusions The successful development of down-convers ion mixer as substrate noise detector has shed light on the future of RF embedded substrate noise coupling measurements. This technique can be applied to s ubstrate parasitics extraction for RF/microwave integrated circuits. The applications of this embedded measurement system will be discussed in the next chapter.

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102 CHAPTER 6 MODELING AND VERIFICATION METHODOLOGY FOR SUBSTRATE COUPLING EFFECTS The successful development of a down -conversion mixer as substrate noise detector has been demonstrated in previous chapter. In this chapter, a down-conversion based embedded substrate noise measurement system and its application are presented as fo llows: first, the test structures designed and fabricated for the investigation of substr ate coupling under different coupling conditions (e.g., coupling with different separation distance s at different frequenc ies) is described, followed by the on-wafer measurement results of the test structures up to 20GHz. Next, the extraction of the substrate macromodel a nd the determination of its element values are discussed in detail. The results obtained from extracted model wi ll be verified through comparison to experimental results and erro r analysis results will be shown. Finally, application of this extracted model on ha ndling multiple-contact coupling problem will be discussed. 6.1 Test Structures for Substrate Coupling Investigation Special test structures were designe d and fabricated in IBM7wl 0.18µm technology, to investigate s ubstrate coupling under differe nt conditions by on-wafer measurement. As shown in Figure 6-1, the test structures include s ubstrate noise injection (“aggressor”) points on the left and one subs trate contact on the ri ght as detection node (“victim”) connected to the mixer (“embe dded measurement”) on the same chip. By changing test signal injection location (S1-S10), substrate coupling distance between the injection point and detection node will be changed. Also, by changing test signal frequency, the effect of operation frequency on substrate coupling can be investigated.

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103 S5 S4 S1 S2 S3 S6 S7 S10 S9 S8 D Chip edges “Aggressors” “Victim” Figure 6-1. Test structures for em bedded substrate noise measurement Figure 6-2 shows the microphotograph of fabri cated test chip with test structures and embedded mixer detector. The test ch ip measured 2000 x 2000 µm. All the substrate contacts used in the test structures are of the same size 20 x 20 µm, and the separation distance between these substrate contacts is from 220µm to 1200µm. The resistivity of the lightly-doped Psubstrate is 11-16 -cm. The thickness of the chip is 250µm with non-conductive epoxy on its backside. A sheet of glass with sufficient thickness (1000 µm) is place between the chip and the chuck of the probe station to avoid any additional interaction. Thus the backside of the chip can be treated as well insulated.

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104 Figure 6-2. Microphotograph of th e test chip containing the s ubstrate noise test structure Figure 6-3. Measurement setup for substrate coupling investigation Figure 6-3 shows the simplified measurem ent setup for test-structure/embedded mixer detector including the probe pads. One port of the test structure is driven by the RF signal (V1) from an external signal generator (HP ESG series signal generator E8257B,

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105 250kHz-40GHz) through bond pad S1, and the other port (V2) is connected to the input of the mixer. The output of the mixer VO will be measured on a spectrum analyzer (HP8563E spectrum analyzer, 30Hz-26.5GHz) w ith the high-impedance probe (GGB picoprobe Model 34A, DC-3GHz) de scribed in previous chapter. 6.2 Substrate Model Extraction Before constructing an equivalent circuit model, substrate coupling test structures are simulated using the electromagnetic tool HFSS (High Frequency Structure Simulator by Ansoft). The whole 3-D simulation model is shown in Figure 6-4. The radiation boundary (air) is defined to allowed waves to radiate in finitely into far space. Inside the air box is the test chip model, which consists of (fro m top to bottom): silicon-dioxide (passivation on top of the chip), silicon (the wafer die under test, including substr ate contacts, p-well and p-substrate), glass. The thickness of each level is given as physical dimensions which are obtained from MOSIS [75]. Beneath th e glass is a perfect conductor plane, representing the metal chuc k of the probe station. From the top and cross section views of th e simulated structure, it can be observed that most of the radiation patterns of the c oupling signal die out within the test structure model and only a negligible fraction reaches deep into the substrate, which means the back plane connection condition has little e ffect on the simulation results. The HFSS simulation result confirms that the glass at the bottom isolate the back plane of the test chip from the metal chuck of the probe stati on in the embedded measurement. Thus in the following analysis, a floating back plane for th e test chip is assumed. The equivalent circuit model based on this assumption will be discussed next.

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106 Figure 6-4. HFSS model of test structure The substrate test structure discussed here can be described by a two-port equivalent circuit of Figure 6-5, where G12=G21 is assumed because of reciprocity and YMX is the input admittance of the embedded mixe r detector. From the equivalent circuit, G12, the transadmittance between two substrate contacts, which represents the substrate coupling, can be calculated as, 2 121222 1 M XV GGGY V (6-1). Y-parameters of the test structure ar e calculated from a measured set of Sparameters, which also yields the output admittance G22 of the test structure. The substrate contacts in all test structures are of the same size and shape, so G11=G22. Then the two-port Y-parameters for the equivalent circuit are given by:

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107 1112111212 2122122212yyGGG Y yyGGG (6-2). Figure 6-5. Equivalent circ uit of the test structure From Equation (6-2), G12 and G22 can be calculated from Y-parameters as: 1212222212, GyGyy (6-3). Combining Equation (6-1) and (6-3), Equation (6-1) can be rewritten as: 2 1222 1 M XV GyY V (6-4). For the measurement described below, in the first step, the S-parameter measurement is performed, which yields the output admittance y22 of the test structure. An additional deembedding step is used to remove the influence of the pad capacitances and interconnection inductances. In the th ird step, the amplitudes of input signal V1 and mixer output signal VO are measured. 2 1V V can be calculated from 22 11O OV VV VVV and 2OV V is the voltage conversion gain of embedded mixer detector, which is already obtained

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108 from the measurements discussed in the previ ous chapter. Isolation between two substrate contact, I, is defined here as 2 120log V I V (6-5). As discussed in detail in [ 32], a semi-physical equivalent circuit (shown in Figure 6-6) is used to model G12 in the test structure. A capacitor C12, which represents the dielectric behavior of the bulk substrat e and depends on the substrate permittivity s i , is shunted to the substrate resistance R12. Note that C12 and R12 are related by 1212/sisubCR (6-6), where s i and s ub are the permittivity and resistivity of the bulk substrate, respectively. This can be derived from MaxwellÂ’s e quations considering the electrical field E determines both the curry density /JE (corresponding to 1/R) and the displacement current density DE (corresponding to C). 1212 121 GjC R Figure 6-6. Semi-physical equivalent circuit for G12 For given substrate contact size, G11 and G22 have constant values and G12 is a function of the separation dist ance (d) between the two cont acts and the frequency of injected signal (f). Since R12 increases as the distance d is increased, the variation of R12 with d can be characterized efficiently as a polynomial in d, i.e., 2 12012...m m R kkdkdkd (6-7),

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109 Where ki and the polynomial order, m can be determined by first pre-computing the actual parameters and then using a suitable curve fitting technique. The curve fitting is required only once for a given process. The re sulting polynomials can th en be stored in a library and used for the extraction of other di fferent structures in the same technology. 6.3 Measurement Results In this section, the results obtained wi th the embedded measurement technique are presented and compared to the simulation results based on the semi-physical model discussed in Section 6.2. Figure 6-7 shows the measured and simulate d isolation for the test structures in Figure 6-1. Due to space limitations, only so me of the measurement results are shown here. A very good agreement is observed fo r different separation distances with frequency up to 20GHz. It is clear from the figure that the isolation is about 5dB lower when frequency increases from 5GHz to 20 GHz. The isolation is weakly dependent on the separation distance, impr oving about 5dB when the distan ce increases from 220um to 1200um. This is so b ecause the value of R12 is comparable to the reactance of C12 in this frequency range and C12 starts to play a role for substrate coupling. The simulation result of isolation based on macromodel is shown again in Figure 6-8. As shown in Figure 6-9, the good agreement of |G12|, the magnitude of G12, between measurement and simulation results de monstrates the suitability of embedded substrate coupling measurement and th e accuracy of extracted macromodel. The macromodel proposed in the previous sections has been validated through measurement of the test chip described above up to 20GHz. From simulation results based on extracted macromodel, the effect s of separation distance (d) and operation frequency (f) on substrate coupling are clearly shown (Figure 6-8).

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110 109 1010 1011 -50 -45 -40 -35 Frequency (Hz)Isolation (dB) Meas:220um Sim: 220um Meas:1200um Sim: 1200um Figure 6-7. Comparison of measurement and si mulation results of isolation for different separation distances between two substrate contacts Figure 6-8. A two-dimension view of isolation versus separation distances and frequencies

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111 109 1010 1011 0.5 1 1.5 2 2.5 3 3.5 4 x 10-4 Frequency (Hz)G12(mag) (-1 ) Meas:220um Sim: 220um Meas:1200um Sim: 1200um Figure 6-9. Comparison of measurement and simulation results of |G12| for different separation distances between two substrate contacts 6.4 Discussions 6.4.1 Effect of Measurement E rrors on Model Extraction All measurement systems, including vect or network analyzer (VNA) employed in our measurement, can be plagued by three types of measurement errors: systematic errors, drift errors and random errors. System atic errors are caused by imperfections of the test equipment and test setup. Drift erro rs occurs when a test systemÂ’s performance changes after a calibration ha s been performed. Random errors vary randomly as a function of time and they are not predictable. Systematic errors can be characterize d through calibration (i .e., SOL calibration) and mathematically removed after the actual measurement. Drift er rors are primarily caused by temperature variation and assume d to be already minimized by periodic recalibration. The main contributors to random errors are instrument noise (i.e., sampler

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112 noise, IF noise floor) and connection repeatab ility. Therefore they cannot be removed by calibration, and the effect of random errors on model extr action must be evaluated. It is not uncommon to see 2% factory uncertainty [80] on measurement equipment after calibration process. From Equati on (6-1), assuming 2% variations on 2 1V V , y22 and YMX, the errors of G12 are shown in Figure 6-10. Within five standard de viations of the mean, magnitude error of |G12| is less than ±0.35dB, which compares reasonably to the random errors. 109 1010 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 Frequency (Hz)|G12| (dB) Worst case error mag. Figure 6-10. Errors in|G12| because of random errors in measurement 6.4.2 Multiple-contact Coupling Problem The substrate noise coupling model describe d in previous sections is originally developed for two contacts. Impedance values are extracted for a pi-network that includes a cross coupling impedance betw een the two contacts (“ports”). However, substrate noise coupling involves multiple contacts (“ports”), wh ich are illustrated in Figure 6-11, i.e.,

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113 the effect of D3 must be taken into account when cons idering the substrate coupling between D1 and D2. Figure 6-11. Substrate noise coupling between multiple contacts By using two-port Z parameters extracted from each contact pairs, a lumped impedance network [76] can be used to model coupling between multiple contacts, as shown in Figure 6-12. For example, the proce ss for an N contact problem consists of the following steps. First, two-port Z parameters are extracted by considering one contactpair at a time. An N x N Z-matrix is then constructed, whose entries corresponding to the two contacts (i.e., i and k) are given in Equation (6-8). Finally, the impedance values will be calculated from the overall Z-matrix. Figure 6-12. Substrate impedance network between multiple contacts

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114 ............ ........ ............ ........ ............iiik ikkkzz Z zz (6-8). A problem with this impedance determina tion method from Z-matrix is that beyond a certain size, the matrix becomes too larg e to solve. For a pr actical SoC IC, the computation time required will be prohibitiv ely long to attempt a full scale circuit simulation. Partitioning the full matrix into smaller sections can help to make quick approximations [77]. By i gnoring the impact of dist ant contacts, coarse-fine approximation techniques [49] can be employe d to improve simulation efficiency. Other acceleration techniques such as multi-pole method [78], FFT method [79] are also reported. 6.5 Conclusions The goal of embedded substrate test is to generate a macro model out of finite simple test structures, aiming at results of ge neral validity. This model can be used as a guideline for SoC designers at the early stage of system integration, providing a more intuitive view of substrate noise coupling. A simple and accurate macromodel based on curve fitting has been described and it agre es quite well with the embedded measurement results, up to 20GHz. This model is scalable with separation dist ance and coupling signal frequency. Techniques of adapting extracted two-port macromodel to solve multi-port problem are also discussed.

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115 CHAPTER 7 SUMMARY AND FUTURE WORK 7.1 Summary This research work focused on embedded substrate noise coupling measurement circuits for RF/microwave integrated circuits , as one of the alternative solutions for IC testing cost reduction. First, fundamental background knowledge describing substrate noise coupling was introdu ced. Second, several existing embedded measurement and substrate modeling methods were investigat ed and a new embedded test concept for RF/Microwave circuits was proposed. The de signs, simulation and measurement results of the necessary components for the proposed embedded substrate measurement were discussed. These included an AGC based det ector, logarithmic amplifier based detector and down-conversion mixer based detector. Fi nally, an application of this embedded measurement system was described, and a semi-physical macromodel based on experiment data was presented. The major contributions of th is dissertation work are summarized as follows. Based on the fundamentals of substrate noise measur ement and existing embedded test methods, the conception of embedded noise measur ement for high-frequency circuits was proposed, which was mainly composed of an offchip signal generator plus test circuitry (detector) integrated with the test structures for substrate parameter extraction. After an external signal source launched a test signa l onto the wafer, the on-chip signal detector received the signal from the output of test structure, and then extracted the useful information into baseband signals, which were finally transmitted back to the external low-frequency tester. Some of the potential advantages included : broad-band and widedynamic range signal detection, excellent input/output port isolation, versatile

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116 applications for different technologies, eas y measurement setup and hence test cost reduction. A low-frequency on-chip substrate nois e measurement test vehicle based on constant-settling time AGC sy stem was designed. A 10MHz linear (THD ~1%) variable gain amplifier with 40dB gain tuning range was designed and simulated. Op-amp based peak detector, loop filt er and voltage reference circuit were designed and simulated. Due to unexpected oscillation problem with on-chip bias circuit, the evaluation of the overall system was impossible. On the other hand, the complexity and la rge chip area overhead (1500 x 1300µm) of the system prevented the application of this measurement scheme. A 100MHz CMOS pseudo-logarithmic amp lifier detector based on successivedetection architecture was designed and si mulated. Although a wide-dynamic range (-80 to 0dBV), good detection accuracy (log conformance within 1dB), and a much smaller overhead (500 x 185µm) were achie ved, the frequency response of amplifier and rectifier sets the upper limit for the fre quency range of signal detection. In order to satisfy the requirement of a high dynamic range and broad band signal detection, a down-conversion based dete ction scheme was proposed. A CMOS downconversion mixer detector was designed, a nd the measurement results showed it could work with signal up to 20GHz and had a dynamic range over 70dB, with very compact size (232 x 296µm). Based on the success of the development of down-conversion dete ction circuit, a practical application for embedded substrate noise measurement was demonstrated. First, isolation measurements on test structures we re performed. A semi-physical macromodel was then extracted from the experimental data and it was scalable with separation

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117 distance and coupling signal frequency. The application of this macromodel to multiplecontact coupling problem was also discussed. 7.2 Future Work The ultimate goal of our research was to realize a substrate noise coupling measurement system on-chip. The successful development of down-conversion mixer as substrate noise detector has demonstrated the feasibility of the embedded system for substrate noise measurement. However, the detected signal amplitude measurement is performed by external tester (spectrum analyzer) and exte rnal buffer (high-impedance probe) has to be used for impedance matching purpose. One possible improvement of the proposed embedded substrate noise measurement scheme is to add on-chip signal amplitude ex tractor (logarithmic amplifier) as shown in Figure 7-1. In this way, measurement set ups for substrate coupling will be greatly simplified – only DC measurement will be required at the output. The robustness of logarithmic amplifier as a signal amplitude extractor versus temperature and process variations is discussed in detail in Chapter 4. Figure 7-1. Improved down-c onversion based substrate noise measurement scheme The improved embedded substrate coupling measurement system is simulated with IBM7wl BiCMOS 0.18um models. The simu lated logarithmic amplifier outputs for sinusoid input signals at different frequenc ies (10GHz to 20GHz) are shown in Figure 7-

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118 2. The frequency offset between the injected signals and LO is 100MHz, so the frequency of input signals to the loga rithmic amplifier is 100MHz. An over 80dB (-90 to -10dBV) input signal dynamic range is achieved and the output of logarithmi c amplifier is very consistent (dB) under diffe rent frequencies of input signal (Figure 7-3). Figure 7-2. Logarithmic amplifie r output versus input voltage Figure 7-3. Output erro r versus input voltage

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119 The down-conversion mixer detectors can be inserted on virtually any nodes of interest in the SoC with good is olation to the circuits under investigation. One possible application of embedded detectors (mixers) plus an on-chip signal amplitude extractor (logarithmic amplifier) is shown in Figure 74. Each mixer “MX” output is connected through a switch “SW” with cont rol logic that effectively is olates the mixer output from the logarithmic amplifier input (i.e., T-switch discussed in Chap ter 3), if the mixer is to be de-activated. Figure 7-4. Example of downconversion based embedded substrate noise measurement Within the conception of the proposed embedded substrate noise measurement, a few possible future tasks are suggested as follows. The proposed embedded test scheme is only applied to unshielded substrate coupling (direct coupling between two substrate contacts wit hout any isolation structures) measurement in a high-resistivity substrate. And the coupling behaviors in different

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120 substrates (i.e., low-resistivity substrate, SOI substrate) under different shielding conditions (i.e., p+/n+ guardrings, deep tr ench) are worth furthe r investigation. Macromodel extraction based on experimental data can be extended to predict the coupling for different CMOS processes and to evaluate the effects of different substrate noise isolation structures. This model also needs to be validated in larger circuit examples. Another possible applicati on for this embedded test scheme is package/board characterization. By performing two separa te embedded measurements, the effects of package/board induced signal coupli ng can be characterized properly.

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121 APPENDIX A ERROR ANALYSIS FOR PSEUDO-LOGARITHMIC AMPLIFICATION A pseudo-logarithmic transfer curve is defi ned to be an approximation to an ideal logarithmic curve. A simple example of appr oximation to a logarithmic curve is shown in Figure A-1. The logarithmic curve is appr oximated by a series of line segments of varying length and slop e. For a fixed range of the original curve, more line segments improve the approximation. Vin (V)Vout (V) Figure A-1. Piecewise linear appr oximation to a logarithmic curve Shown in Figure A-2 is the successive-detect ion architecture which is studied and discussed in this section. Th e figure is repeated (Chapter 4, Figure 4-3) here for convenience. Figure A-3 [66] shows the composite output response of a pseudologarithmic amplifier comparing with a true l ogarithmic response. We can also take it as a semi-logarithmic version of Figure A-1 (with logarithmic response at the breakpoints).

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122 The logarithmic curve becomes linear and the straight-line segments appear curvy on such a scale. The true logari thmic curve can be shown as 12log()outinVKKV (A-1) where 1log()L VV K A , 1 2n V LA K V . Vin Lim Out Log Out 1st2ndmth(N-1)thNth (m+1)th VinAVVinAV 2VinAV mVin=VLVLVLVL VinAVVinAV 2VinAV mVin=VLVLVLVL Low Pass Filter VLOG Figure A-2. Signal flow of a successi ve-detection logarithmic amplifier When 1LL in NmNm VVVV V AA or (1)LoutLmVVmV , the equation describing any arbitrary straight-line se gment of the composite logarithmic response is 11 () 11nm in outVL VVV VAmV AA (A-2) where n is the total number of line segments (limiting amplifier stages), and m is an index of the line segment (limiting amplifier stage) being discussed. Select any output voltage outV and we can solve Equation (A-1) and (A-2) for ideal logarithmic input voltage, ,loginV and the actual input volta ge of pseudo-logarithmic amplifier, ,inactualV . Input error (in dB) is defined by:

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123 , ,log20loginactual inV Error V (A-3) L N VV A 1 L N VV ALV2 L V L N m VV A 1 L Nm VV A ... L mV(1) L mV L nV L VV A ... VinVout Figure A-3. Characteristics of an N-stage pseudo-logarithmic amplifier When 1LL in NmNm VVVV V AA or(1)LoutLmVVmV , define 1 'Nm V inin LA VV V (A-4) 'out out LV Vm V (A-5) Rewriting Equation (A-1) and (A-2), we can get '' ,logoutV inVVA (A-6) '' ,(1)1inactualVoutVAV (A-7)

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124 Now the input error can be express as '' , ' ,log '20log (1)1 20logoutinactual in Vout V VV Error V AV A (A-8) From inspection of Figure A-2, we can see that maximum input errors occur where the slopes of the two curves are equal. As shown in Figure A-3, th e input error decreases for smaller values of single stage gain AV. 0 5 10 15 20 25 30 10-2 10-1 100 101 Single stage gain (dB)Maximum Error (dB) Figure A-4. Maximum input error as a function of single stage gain

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125 APPENDIX B CALIBRATION FOR ONE-PORT MEASUREMENT SYSTEM Unlike digital multimeter, a microwave s-parameter measurement system (i.e., a network analyzer) does not give accurate data instantaneously. Calibration must be performed in order to guarantee the accuracy and repeatability of measur ements. Calibration procedure will also create a well defined reference plane at the interface of the measurement system and the DUT (Figure B-1). Reference Plane Figure B-1. S-parameter measurement with calibration setting the reference plane For on-wafer measurement we will define the reference plane between the microwave probe tips and the landing bond pads which co nnect to the DUT. The other parts in the measurement system including cables and test fixtur es can be calibrated using standards that are traceable to the National Bureau of Standards (NBS). The calibration of the connection path as a whole can be done with one-port (Short-OpenLoad, SOL) calibration method introduced by Wijnen [81]. Figure B-2 shows a flow graph of a hypothetical error adapter, repr esenting the error m odel for one-port measurement system. The signal flow is visualized by the arrows: a0 and b0 are the incident and re flected waves detected

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126 by the test set (i.e., at the output of coaxial cable ); a1 and b1 are the wave s associated with the DUT (i.e., at microwave probe tips ). Four error terms are used to define the system errors: Directivity error, e00: represents all the signa ls that are reflected before they could reach the reference plane of microwave probe tips. Frequency response errors, e10 and e01: repres ent the errors caused by a non-ideal signal path from test set to the probe tips (i.e., cable loss). Port match error, e11: represents the reflect ed signal as a result of non-ideal effective source impedance when looking back into the reference plan of probe tips. L Figure B-2. Flow graph of the hypothetical error adapter The error terms can be obtained by the calibration with open, short and load standards. In practice, e10 and e01 cannot be distinguished from each other and will be used together as a product. The measured data at the output of the cable are: 0110 _00 111mopenee e e (B-1) 0110 _00 111mshortee e e (B-2) _00 mloade (B-3) The error terms can now be calculated us ing Equation (B-1), (B-2) and (B-3):

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127 00_ mloade (B-4) __ 11 __12mloadmshort mopenmshorte (B-5) ____ 0110 __()() 2mopenmloadmloadmshort mopenmshortee (B-6) Applying simple flow graph rules to Figure B-2, the measured reflection coefficient m is equal to: 0 000110 0111actual m actualb eee ae (B-7) Solving foractual, (B-7) can be rewritten as: 00 11000110()m actual me eeee (B-8) Substitution of Equation (B-4), (B -5) and (B-6) into (B-8) lead s to the following equation: _ __ __ __2()mmload actual mloadmshort mmloadmmopen mopenmshort (B-9) The power delivered to the DUT can be derive d from the error model as follows. We know the signals b0 and b1 in Figure B-2 are 1010111baeae 010 1 111actualae b e (B-10) The available power from the source is 2 0 availablePa , and the power delivered to the DUT is 2 22222 1 1111 2 111DUTactuala Pbabb b (B-11)

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128 From Equation (B-10), we can get 2 222 10 1 1111 1DUTactualavailableactual actuale PbP e (B-12)

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129 APPENDIX C EMBEDDED SUBSTRATE COUPLING MEASUREMENT AND SEMI-PHYSICAL MACROMODEL EXTRACTION C.1 Embedded Substrate Coupling Measurement The simplified measurement setup for test-struc tures plus an embedded mixer detector is shown in Figure C-1. The figure is repeated (Chapter 6, Figure 6-3) here for convenience. One port of the test structure is driven by the RF signal (V1) from an external signal generator (HP ESG series signal generator E8257B 250kHz-40GHz) through bond pad S1, and the other port (V2) is connected to the input of th e mixer. The output of the mixer VO will be measured on a spectrum analyzer (HP-8563E 30Hz-26.5GHz sp ectrum analyzer) with the high-impedance probe (GGB picoprobe Model 34A) de scribed in previous chapters. S1 G Test Structure Mixer 50 V2V1Vo External LO External Signal Source Chip EdgeTo high-imp. probe & spectrum analyzer Figure C-1. Measurement setup for em bedded substrate coupling detection The first measurement is to characterize the S-parameters of test structures. The test structures were measured using two groundsignal-ground (GSG) microwave probes (Cascade Microtech Microprobe ACP40, DC-40GHz), contacting at port1 (V1) and port2 (V2) as indicated in Figure C-1. A symmetrical layout was chosen so that a good contact of the probes can be ensured by comparing the reflection at both ports. The mandatory connections of the ground pads are realized in the top metal levels w ith thick oxide layer (typ ical oxide thickness is

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130 4 µm for metal6 and metal7), so that the inte raction with the substrate is minimized. The Sparameters are measured from 1GHz to 20GHz with a HP-8510C vector network analyzer (30Hz-26.5GHz). Accurate calibration was ensured by Short-Open-Load (SOL) method discussed in Appendix B. The power of test si gnal delivered to the test structure can be calculated using Equation (B-12). Figure C-2. Equivalent circ uit of the test structure Figure C-2 shows the equivalent circuit of the test structure in the measurement described above. The two-port Y-parameters (between V1 and V2) for the equivalent circuit are given by: 1112111212 2122122212yyGGG Y yyGGG (C-1). Y-parameters of the test structure are calculated from the measured S-parameters, which are given by: 11221221 11(1)(1) SSSS y (C-2) 12 122 S y (C-3) 21 212 S y (C-4)

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131 11221221 11(1)(1) SSSS y (C-5) where 11221221(1)(1) SSSS . The substrate contacts in our test structure are of the same size and shape and assume symmetrical layout, so G11=G22. Then from Equation (C-1), G12 and G22 can be calculated from Y-parameters as: 1212222212, GyGyy (C-6). Pad DUT Ypad+ YIntYDUT Gnd Ytot(a) Pad Ypad+ YInt Gnd Yopen(b) Figure C-3. De-embedding bondpad and interconnection An additional measurement step is perfor med to remove the influence of the bondpad capacitances and interconnection inductances. Figure C-3(a) s hows a simplified diagram of onwafer input admittance measurement of a DUT. Th e DUT is connected to external equipment through interconnection and a bondpad. The measured admittance (Ytot) is the total admittance of bondpad (Ypad), interconnection (Yint) and the DUT (YDUT). In order to characterize the true

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132 admittance of a DUT, a “dummy” open-structure (Figure C-3(b)) with just the bondpad and the interconnection, is carefully designed and measured. By measuring the admittance of this openstructure (Yopen), the admittance of bondpad and interc onnection is de-embedded, hence the actual admittance of the DUT can be easily calculated as: int() D UTtotpadtotopenYYYYYY (C-7). The third measurement is to characterize th e down-conversion mixer. By measuring the Sparameters and performing the de-embedding measurement step described above, input admittance of the mixer (YMX) can be accurately obtained. Mi xer linearity (conversion gain) measurement is also performed, as discussed in Chapter 5. From Figure C-2, 2 1V V can now be calculated from 22 11 O OV VV VVV and 2 OV V is the voltage conversion gain of embedded mixer detector . The transadmittance between two substrate contacts, G12, which represents the substrate coupling, can be calculated as, 2 121222 1 M XV GGGY V (C-8). Combining Equation (C-6) and (C-8), Equation (C-8) can be rewritten as: 2 1222 1 M XV GyY V (C-9). C.2 Semi-physical Macromodel As discussed in detail in Chapter 6, a semiphysical equivalent circuit (shown in Figure C4) is used to model G12 in the test structure. A capacitor C12, which represents the dielectric behavior of the bulk substrate and depends on the substrate permittivity s i , is shunted to the substrate resistance R12. Note that C12 and R12 are related by 1212/sisubCR (C-10),

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133 where s i and s ub are the permittivity and resistivity of the bulk substrate, respectively. 1212 121 GjC R Figure C-4. Semi-physical equivalent circuit for G12 For given substrate contact size, G11 and G22 have constant values and G12 is a function of the separation distance (d) between the two contac ts and the frequency of injected signal (f). Since R12 increases as the distance d is increased, the variation of R12 with d can be characterized efficiently as a polynomial in d, i.e., 2 12012...m m R kkdkdkd (C-11), where ki and the polynomial order, m can be dete rmined by first pre-computing the actual parameters and then using a suitable curve fitting technique. The substrate resistances (R12) obtained from macromodel simulation and embedded measurements are plotted in Figure C-5 as a function of the separati on distance between two substrate contacts in the test structure. The values of parasitic capacitances (C12) associated with substrate resistance (R12) are shown in Figure C-6, also as a function of the separation distance. The macromodel proposed Chapter 6 has been va lidated through measurement of the test chip described above up to 20GHz. Typical values of R12 and C12 as a function of separation distance are summarized in Table C1 and C-2. The good agreement of R12 and C12, between embedded measurement and macromodel simulation results demonstrates the suitability of embedded substrate coupling measurement a nd the accuracy of ex tracted macromodel.

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134 0 200 400 600 800 1000 1200 5 6 7 8 9 10 11 12 13 14 15 Separation Distance (m)R12 (k) Figure C-5. R12 versus different separation distan ces between two substrate contacts 0 200 400 600 800 1000 1200 1.5 2 2.5 3 3.5 4 Separation Distance (m)C12 (fF) Figure C-6. C12 versus different separation distan ces between two substrate contacts

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135 Table C-1. Typical values of R12 as a function of separation distance Separation (µm) Measurement (k ) Macromodel (k ) Error (dB) 220 8.36 8.20 -0.168 484 11.15 11.17 0.016 656 12.22 12.17 -0.036 890 13.29 13.25 -0.026 1156 14.20 14.18 -0.012 Table C-2. Typical values of C12 as a function of separation distance Separation (µm) Measurement (fF ) Macromodel (fF) Error (dB) 220 2.72 2.83 0.344 484 2.04 2.01 -0.129 656 1.87 1.89 0.092 890 1.71 1.73 0.101 1156 1.60 1.61 0.054 As discussed in Chapter 6, random errors in measurement cannot be removed by calibration, and it is not uncommon to see 2% factory uncertainty [80] on measurement equipment after calibration proce ss. Assuming all measurements (calibration and verification) are made with 1000 averages, Figure C-7 show s the distributions of magnitude of G12 at 5GHz (a), 10GHz (b) and 20GHz(c) for separation distan ce of 220µm. Within three standard deviations ( ) of the mean (µ), it shows 2.79%, 2.81% a nd 2.75% variations at 5GHz, 10GHz and 20GHz, respectively.

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136 1.42 1.43 1.44 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 x 10-4 0 50 100 150 200 250 G12(mag) ( -1)Number of samples = 1.468x10-4= 1.364x10 -6(a) 2.02 2.04 2.06 2.08 2.1 2.12 2.14 2.16 x 10-4 0 50 100 150 200 250 300 G12(mag) ( -1)Number of samples = 2.08x10-4= 1.945x10 -6(b) 3.5 3.55 3.6 3.65 3.7 3.75 3.8 x 10-4 0 50 100 150 200 250 300 G12(mag) ( -1)Number of samples = 3.627x10-4= 3.322x10 -6(c) Figure C-7. |G12| distributions at different freque ncies (separation distance = 220µm)

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137 8.4 8.5 8.6 8.7 8.8 8.9 9 x 10-5 0 50 100 150 200 250 G12(mag) ( -1)Number of samples = 8.647x10-5= 7.858x10-7(a) 1.19 1.2 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 x 10-4 0 50 100 150 200 250 G12(mag) ( -1)Number of samples = 1.229x10-4= 1.086x10-6(b) 2.06 2.08 2.1 2.12 2.14 2.16 2.18 2.2 2.22 2.24 x 10-4 0 50 100 150 200 250 300 G12(mag) ( -1)Number of samples = 2.136x10-5= 1.997x10-6(c) Figure C-8. |G12| distributions at different freque ncies (separation distance = 1200µm)

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138 Table C-3. |G12| variations under different frequenc ies (separation distance = 220µm) Frequency (GHz) Mean ( --1) Standard deviation ( --1) Variation (%) 5 1.47 x10-4 1.36 x10-6 2.79 10 2.08 x10-4 1.95 x10-6 2.81 20 3.63 x10-4 3.32 x10-6 2.75 Table C-4. |G12| variations under different frequenc ies (separation distance = 1200µm) Frequency (GHz) Mean ( --1) Standard deviation ( --1) Variation (%) 5 8.65 x10-5 7.86 x10-7 2.73 10 1.23 x10-4 1.15 x10-6 2.80 20 2.14 x10-4 2.00 x10-6 2.81 The distributions of magnitude of G12 at 5GHz (a), 10GHz (b) and 20GHz(c) for separation distance of 1200µm are shown Figure C-8. The vari ations are 2.73% at 5GHz, 2.80% at 10GHz and 2.81% at 20GHz. The variations of |G12| under different frequencies for different separation distances are summarized in Table C-3 and C-4.

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139 LIST OF REFERENCES [1]. D. A. Gahagan, “RF (gigahertz) ATE production testing on wafer: options and tradeoffs,” Proceedings International Test Conference, pp. 388 – 395, September 1999. [2]. E. Strid, “Roadmapping RFIC Test,” Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 20th Annual Technical Digest, pp. 3-6, November 1998. [3]. IEEE Standard Test Access Port and Bound ary-Scan Architecture, IEEE STD 1149.12001, pp. i-200, 2001. [4]. P. P. Fasang, “Boundary scan and its appli cation to analog-digital ASIC testing in a board/system environment,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 22.4/1.4/4, May 1989. [5]. IEEE Standard for a Mixed-Signal Test Bus, IEEE STD 1149.4 -1999, 2000. [6]. M. Slamani and B. Kanminska, “Fault observability analysis of analog circuits in frequency domain,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, no. 2, pp. 134-139, February 1996. [7]. S. Sunter, “The P1149.4 mixed signal test bus: Costs and benefits,” IEE Proceedings Circuits, Devices and Systems, pp. 444-450, December 1996. [8]. T. Huang, P. Wu, R. Liu, J. Tsai, H. Wang and T. Chiueh, “Boundary scan for 5GHz RF pins using LC isolation networks,” 22nd IEEE VLSI Test Symposium, Proceedings., pp. 347-350, April 2004. [9]. M. Burns and G. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, Oxford Univ. Press, New York, 2001. [10]. P. Duhamel and J. C. Rault, “Automatic test generation techniques for analog circuits and systems: A review,” IEEE Transactions on Circuits and Systems, vol. 26, no. 7, pp. 411439, July 1979. [11]. E. M. Hawrysh and G. W. Roberts, “An integrated memory-based analog signal generation into current DFT architectures,” IEEE Transactions on Instrumentation and Measurement, vol. 47, no. 3, pp. 528-537, June 1998. [12]. B. Dufort and G. W. Roberts, “On-chip analog signal generation for mixed-signal built-in self-test,” IEEE Journal of Solid-State Circuits , vol. 34, no. 3, pp. 318-330, March 1999. [13]. M. M. Hafed, N. Abaskharoun and G.W. Roberts, “ A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits,” IEEE Journal of Solid-State Circuits , vol. 37, no. 4, pp. 449-514, April 2002.

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146 BIOGRAPHICAL SKETCH Ming He was born in Guangzhou, China in 1977. He received his B.S. degree in Electrical Engineering from South China University of Technology, Guangzhou, China in 2000 and his M.S. degree in electrical engineer ing from the University of Florid a, Gainesville, in 2002. In the fall of 2002, he worked as an intern in the Nati onal Semiconductor, in Santa Clara, CA. He is currently working toward the Ph.D. de gree in electrical engineering. His research interests are in the areas of analog/mixed-signal/RF IC design and embedded IC design-for-test.