Citation
Physics-Based Modeling and Analysis of Nonclassical Nanoscale CMOS with Circuit Applications

Material Information

Title:
Physics-Based Modeling and Analysis of Nonclassical Nanoscale CMOS with Circuit Applications
Creator:
ZHANG, WEIMIN ( Author, Primary )
Copyright Date:
2008

Subjects

Subjects / Keywords:
Capacitance ( jstor )
Cells ( jstor )
Doping ( jstor )
Electric current ( jstor )
Electric potential ( jstor )
Electrons ( jstor )
Modeling ( jstor )
Simulations ( jstor )
Threshold voltage ( jstor )
Transistors ( jstor )

Record Information

Source Institution:
University of Florida
Holding Location:
University of Florida
Rights Management:
Copyright Weimin Zhang. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Embargo Date:
8/31/2011
Resource Identifier:
658216669 ( OCLC )

Downloads

This item is only available as the following downloads:


Full Text

PAGE 1

PHYSICS-BASED MODELING AND ANALYSIS OF NONCLASSICAL NANOSCALE CMOS, WITH CIRCUIT APPLICATIONS By WEIMIN ZHANG A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006

PAGE 2

ii ACKNOWLEDGEMENTS IamdeeplyindebtedtomyadvisorandmentorProfessorJerryG. Fossumforhisdevotedguidanceandunrelentingsupportthroughoutthe yearsofmygraduatestudy.Hisvisioninthefieldofsemiconductordevice andhisdedicationtoworkhavealwaysbeenandwillalwaysbeaconstant encouragementandinspirationtome.Iwouldalsoliketoextendmy sinceregratitudetothemembersofmysupervisorycommittee(Professors RobertM.Fox,ScottE.Thompson,andSusanB.Sinnott)fortheir guidanceandwillingservice.IappreciateErlindaLaneandMarcyBryant fortheirhelppreparingtripsfornumerousresearchreviewsand conferences. IamgratefultotheFreescaleSemiconductorInc.andthe SemiconductorResearchCorporationfortheirtechnicalandfinancial support.Especially,IthankMr.LeoMathewatFreescaleSemiconductor Inc. for providing much of the data and information in this work. Iwouldalsoliketothankmyfellowstudents,MurshedM. Chowdhury,Seung-HwanKim,VishalTrivedi,Ji-WoonYang,ZhichaoLu, LixinGe,QizhangYin,HuiLiufortheirinsightfulandtechnical discussionsandfriendships.ImustsayIamfortunatetohaveknownall

PAGE 3

iii thefriendsherewhohaveencouragedandcheeredmeupthroughoutall the years. Iamobligedtoexpressheartfeltthankstomyfather,Mingquan Zhang,andmymother,XiuqinXu,fortheirendlessloveandsupportin manywaysthroughtheyears.Indeed,IwouldalsoliketothankGodfor his grace and blessings that have made this pursuit possible.

PAGE 4

iv TABLE OF CONTENTS page ACKNOWLEDGEMENT..........................................................................ii LIST OF TABLES...................................................................................vii LIST OF FIGURES...............................................................................viii KEY TO ABBREVIATIONS....................................................................xii ABSTRACT...........................................................................................xiv CHAPTER 1 INTRODUCTION...................................................................................1 2PHYSICS-BASED MODELING OF STRAINED SI/SI1-XGEX MOSFET AND ITS IMPLEMENTATION WITH UFPDB MODEL........................9 2.1 Introduction..................................................................................9 2.2 Threshold Voltage Model............................................................10 2.2.1 Strain-Induced Threshold Voltage Shifts..........................10 2.2.2 Model Development...........................................................14 2.2.3 Model Calculations for D Vt(SS)(x)......................................23 2.3 Modeling of Scaled SS CMOS in UFPDB Model.........................30 2.3.1 SS Channels in Bulk-Si CMOS.........................................30 2.3.2 SS Channels in PD/SOI CMOS.........................................38 2.4 Conclusion...................................................................................40 3 PERFORMANCE PROJECTIONS OF SCALED CMOS DEVICES AND CIRCUITS WITH STRAINED SI-ON-SIGE CHANNELS....................43 3.1 Introduction................................................................................43 3.2 SS Channels in Bulk-Si CMOS...................................................43 3.3 SS Channels in PD/SOI CMOS (SSOI).......................................56 3.4 Further Discussion of Performance Loss Due to Vt Redesign.....64 3.5 Conclusion...................................................................................67

PAGE 5

v 4 PHYSCIAL INSIGHTS REGARDING DESIGN AND PERFORMANCE OF MULTIPLE INDEPENDENT-GATE FINFETS (MIGFETS)..........71 4.1 Introduction................................................................................71 4.2 MIGFET......................................................................................72 4.2.1 DC Characteristics............................................................72 4.2.2 Physical Insights Regarding VGbS Dependences...............75 4.2.3 Device Design Considerations...........................................79 4.3 Mixer...........................................................................................86 4.4 Conclusion...................................................................................98 5 SRAM CELL DESIGN WITH MIGFET..............................................100 5.1 Introduction..............................................................................100 5.2 DG FinFET SRAM Cell Performance........................................101 5.3 Use of MIGFET for Access Transistors.....................................107 5.3.1 The MIGFET Ion/Ioff and Its VGbS Dependence...............107 5.3.2 Dynamic Gb Bias Design and Its Leakage Problem........111 5.3.3 Static Gb Bias Design.....................................................115 5.4 Structural Sensitivities of the Cell...........................................125 5.5 SRAM Cell Layout....................................................................134 5.6 SRAM Cell Access Speed...........................................................138 5.7 Conclusion.................................................................................141 6 THE ITFET: A NOVEL FINFET-BASED HYBRID DEVICE.............144 6.1 Introduction..............................................................................144 6.2 The ITFET Design and Analysis...............................................145 6.3 ITFET Applications: SRAM......................................................162 6.4 A More Scalable ITFET with Doped SOI Body.........................170 6.4.1 Davinci Simulations for Optimal Design........................173 6.4.2 UFDG Simulation Issues.................................................183 6.5 Summary...................................................................................184 7 A NOVEL 2-TRANSISTOR FLOATING-BODY MEMEORY CELL...186 7.1 Introduction..............................................................................186 7.2 The 2T-FBC Concept.................................................................188 7.3 Principles of the 2T-FBC...........................................................194 7.4 Simulations of 2T-FBC Operation for Voltage Sensing............204 7.4.1 Significant Impact of T2-Gate Fringe Capacitance.........204 7.4.2 Design to Suppress the Fringe-Capacitance Effect.........211 7.4.3 Issues with Device Reliability and Data Retention.........216 7.5 Simulations of 2T-FBC Operation for Current Sensing............221 7.6 Summary and Discussion of Pragmatic Design Issues.............225

PAGE 6

vi 8 SUMMARY AND SUGGESTIONS FOR FUTURE WORK.................229 8.1 Summary...................................................................................229 8.2 Suggestions for Future Work....................................................234 REFERENCE LIST...............................................................................237 BIOGRAPHICAL SKETCH...................................................................247

PAGE 7

vii LIST OF TABLES Table page 2.1Model-predicted,withm=1.3,SS-inducedthresholdvoltageshifts,in SS nMOSFETs and pMOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.2Theoretical predictions of low-field electron [Tak96] and hole [Obe98] mobility enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.3Numerically determined [Hat01] Ion enhancements . . . . . . . . . . . . .36 3.1Relevant UFPDB parameters for Lgate = 60nm Si-control and Vt-adjusted strained-Si1-xGex CMOS devices . . . . . . . . . . . . . . . . . . . . . . .49 3.2Relevant UFPDB parameters for Lgate = 60nm Si-control and Vt-adjusted strained-Si1-xGex pMOSFETs. . . . . . . . . . . . . . . . . . . . . . . . . .50 3.3UFPDB-predicted features of 60nm strained-Si/SiGe CMOS devices with and without Vt control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.4UFPDB-predicted propagation delays of 9-stage unloaded CMOS inverter-based ring oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.5Key UFPDB parameters for Lgate= 60nm Si-control and Vt-adjusted SSOI CMOS devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.6UFPDB-predictedpropagationdelays(initial,withouthysteresis)and relative speed enhancements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7.1Word-line and bit-line biases applied for voltage-sensing . . . . . . . .208 7.2Word-line and bit-line biases applied for voltage-sensing . . . . . . . .214 7.3Word-line and bit-line biases applied for current-sensing. . . . . . . .223

PAGE 8

viii LIST OF FIGURES Figure page 1.1Various nonclassical CMOS device options to be explored . . . . . . . . .2 2.1Cross-sectional view of biaxially strained-Si/Si1-xGex . . . . . . . . . . . .11 2.2Energy (in V)-band diagrams at the flat-band condition. . . . . . . . . .19 2.3Model-predicted (curves/X’s), with m = 1.3, and measured (points with Lgate or Leff specified) SS-induced threshold voltage. . . . . . . . .24 2.4Schematic of band structure of strained-Si channels. . . . . . . . . . . . .29 2.5Qualitative illustration of transverse electric-field dependences of electron and hole mobilities in SS-channel MOSFETs. . . . . . . . . . . .34 2.6Cross-sectionalviewofstrained-Si/Si1-xGexPD/SOIMOSFET(SSOI) structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.1UFPDB-predicted IDS-VGS characteristics . . . . . . . . . . . . . . . . . . . . .46 3.2UFPDB-predicted IDS-VDS characteristics. . . . . . . . . . . . . . . . . . . . .48 3.3UFPDB-predicted propagation-delay enhancement . . . . . . . . . . . . .55 3.4UFPDB-predicted IDS-VGS characteristics . . . . . . . . . . . . . . . . . . . . .59 3.5UFPDB-predicted IDS-VDS characteristics. . . . . . . . . . . . . . . . . . . . .60 3.6UFPDB-predicted speed enhancement of SSOI CMOS . . . . . . . . . . .63 4.1UFDG-predicted IDS-VGS characteristics (per hSi) . . . . . . . . . . . . . .73 4.2UFDG-predicted IDS-VGS characteristics (per hSi) . . . . . . . . . . . . . .76 4.3Effective body-effect parameter, or D Vt/ D VGbS. . . . . . . . . . . . . . . . . .78 4.4The Vt(VGbS) variation, for the practical range of back-gate bias. . .81

PAGE 9

ix 4.5Effective body-effect parameter versus the normalized position of the charge centroid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 4.6UFDG-predicted IDS-VGS characteristics (per hSi). . . . . . . . . . . . . . .85 4.7Mixer schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 4.8UFDG-predicted transconductance (per hSi) . . . . . . . . . . . . . . . . . . .92 4.9UFDG-predicted frequency-modulated output signal . . . . . . . . . . . .94 4.10 UFDG-predicted component amplitudes of the output signal . . . . .96 5.1Schematic of a double-gate MOSFET-based SRAM cell. . . . . . .103 5.2UFDG-predicted butterfly curves of the FinFET-based SRAM cell at VDD = 1.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 5.3UFDG-predicted write ’ and write ’ curves. . . . . . . . . . . . . . .106 5.4UFDG-predicted Ion with varying VGbS of the nMIGFET . . . . .109 5.5UFDG-predicted Ioff with varying VGbS of the nMIGFET. . . . .110 5.6UFDG-predicted write/hold margins. . . . . . . . . . . . . . . . . . . . . . . . .114 5.7UFDG-predicted butterfly curves with varying VGb(acc) . . . . . . . . .117 5.8UFDG-predicted read SNM and write margin vs. VGb(acc) . . . . . . .118 5.9UFDG-predicted butterfly curves of the MIGFET-cell. . . . . . . . . . .120 5.10UFDG-predicted read SNM and write margin of the MIGFET-cell vs. VGb of pMOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 5.11UFDG-predicted write/hold margins vs. cell suppy voltage. . . . . . .124 5.12UFDG-predicted Ion and Ioff of the nMIGFET. . . . . . . . . . . . . . . . .126 5.13UFDG-predicted Ion and Ioff of the pMIGFET. . . . . . . . . . . . . . . . .127 5.14UFDG-predicted butterfly curves with 10% tSi variations . . . . . . .129 5.15 UFDG-predicted read SNM and write margin versus10% variations in Lgate as well as in tSi of the access transistors . . . . . . .131

PAGE 10

x 5.16 UFDG-predicted read SNM/write margin/hold SNM variations of the MIGFET-cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 5.17Layout of the FinFET-cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 5.18LayoutoftheMIGFET-cell, whereonlytheaccesstransistorsarebiased in single-gate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 5.19LayoutoftheMIGFET-cell,whereboththeaccessandloadtransistors are biased in single-gate mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .l37 5.20 Medici-predicted C-V characteristics . . . . . . . . . . . . . . . . . . . . . . . .139 6.1Cross-section of the ITFET structure . . . . . . . . . . . . . . . . . . . . . . . .146 6.2UFDG-predicted IDS-VGS characteristics per width. . . . . . . . . . . . .149 6.3UFDG-predicted IDS-VGS characteristics per pitch . . . . . . . . . . . . .150 6.4Davinci-predicted IDS-VGS characteristics per pitch . . . . . . . . . . . .152 6.5Davinci-predicted electron density profiles. . . . . . . . . . . . . . . . . . . .154 6.6Cross-sectional TEM image of an ITFET . . . . . . . . . . . . . . . . . . . . .156 6.7UFDG-predicted per-pitch IDS-VGS characteristics . . . . . . . . . . . . .159 6.8UFDG-predicted Ion/Ioff ratio, along with the percentage Ion enhancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 6.9Schematic of the CMOS 6T-SRAM cell. . . . . . . . . . . . . . . . . . . . . . .163 6.10UFDG-predicted butterfly curve . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 6.11UFDG-predicted read stability and static power comsumption versus SOI thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 6.12UFDG-predicted read stability versus power supply voltages. . . . .169 6.13UFDG-predicted read stability versus mismatch in tSi . . . . . . . . . .171 6.14UFDG-predicted minimum SNM for mismatches . . . . . . . . . . . . . .172 6.15Davinci-predicted per-pitch IDS-VGS characteristics . . . . . . . . . . . .175 6.16Davinci-predicted per-pitch IDS-VGS characteristics . . . . . . . . . . . .176

PAGE 11

xi 6.17Assumed doping-density (gaussian) proles. . . . . . . . . . . . . . . . . . .177 6.18Davinci-predicted per-pitch IDS-VGS characteristics . . . . . . . . . . . .178 6.19Davinci-predicted per-pitch IDS-VGS characteristics . . . . . . . . . . . .179 6.20Davinci-predicted mid-channel inversion-electron density . . . . . . .181 6.21Davinci-predicted IDS-VGS characteristics . . . . . . . . . . . . . . . . . . . .182 7.1A unit 2T ITFET/FinFET DRAM Cell in a matrix integration . . . .189 7.2Network representation for the UFDG model . . . . . . . . . . . . . . . . .192 7.3UFDG-predicted impact-ionization current . . . . . . . . . . . . . . . . .197 7.4Band diagram of gate-body tunneling in accumulation. . . . . . . . . .201 7.5UFDG-predicted gate capacitance-voltage characteristics. . . . .206 7.6UFDG-predicted transient operation. . . . . . . . . . . . . . . . . . . . . . .207 7.7UFDG-predicted transient operation. . . . . . . . . . . . . . . . . . . . . . .210 7.8UFDG-predicted IDS-VGS characteristics . . . . . . . . . . . . . . . . . . .212 7.9UFDG-predicted transient operation. . . . . . . . . . . . . . . . . . . . . . .215 7.10 UFDG-predicted retention/disturb characteristics . . . . . . . . . . .218 7.11UFDG-predicted continuous ‘read’ of the 2T-FBC . . . . . . . . . . . . . .219 7.12 UFDG-predicted transient operation. . . . . . . . . . . . . . . . . . . . . . .222 7.13 UFDG-predicted transient current . . . . . . . . . . . . . . . . . . . . . . . .224

PAGE 12

xii KEY TO ABBREVIATIONS 1T-FBCone transistor floating-body cell 2T-FBCtwo transistor floating-body cell BJTbipolar junction transistor CMOScomplementary metal-oxide-semiconductor DGdouble-gate DIBLdrain-induced barrier lowering DOSdensity-of-states DRAMdynamic random access memory FBfloating body FBCfloating-body cell FDfully depleted FETfield-effect transistor FDFETplanar fully-depleted MOSFET GIDLgate-induced-drain leakage HPhigh performance ITFETFinFET-based inverted-T FET LOPlow operating power LSTPlow standby power MIGFETmultiple-independent-gate FinFET MOSFETmetal-oxide-semiconductor field-effect transistor

PAGE 13

xiii nFETn-type field-effect transistor nFinFETn-type FinFET nITFETn-type ITFET nMOSFETn-type MOSFET PDpartially depleted pFETp-type field-effect transistor pMOSFETp-type MOSFET QMquantum mechanical QMEquantum mechanical effect ROring oscillator SCEshort-channel effect SGsingle gate SOIsilicon-on-insulator SRAMstatic random access memory SSstrained Si SSOIstrained Si channels in PD/SOI CMOS UFDGUniversity of Florida double-gate (model) UFPDBUniversityofFloridapartiallydepletedSOIandbulk MOSFET (model) UTBultra-thin body

PAGE 14

xiv Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy PHYSICS-BASED MODELING AND ANALYSIS OF NONCLASSICAL NANOSCALE CMOS, WITH CIRCUIT APPLICATIONS By Weimin Zhang August 2006 Chairman: Jerry G. Fossum Major Department: Electrical and Computer Engineering Thisdissertationaddressesphysicalmodelinganddesignissuesof nonclassicalnanoscalecomplementarymetal-oxide-semiconductor (CMOS)withregardtopragmaticapplicationstodigitalandanalog circuits. AstheCMOStechnologyaggressivelyscales,noveldevice structuresandmaterialsintegrationarebeingintensivelyexaminedfor continuedperformanceimprovement.Biaxiallystrained-Si(SS)channels onSiGesubstrate,introducedtoenhancecarrier-transportpropertiesin nanoscalebulk-Siandpartially-depleted(PD)silicon-on-insulator(SOI) CMOS,hasbeenactivelypursuedforextendedscalinglimit.However, deviceredesign,mandatedbystrain-inducedshiftsinthethreshold voltage(Vt),andtheenhancedparasiticstherebyimplied,tendto underminetheperformanceenhancement.AdetailedmodelingonstraininducedVtshiftsandontheenhancedcarrier-transportpropertiesand

PAGE 15

xv parasiticsispresented.Themodelingenablessubsequentdeviceand circuitsimulations,withtheUniversityofFloridaphysics-basedcompact MOSFETmodelforbulk-SiandPD/SOI(UFPDB)implementedinSpice3, topredicttheCMOSelectricalcharacteristics,andthespeed-performance enhancementsinSSchannelsonbulkSi,andonPD/SOI,versustheGe content. Ultra-thin-body(UTB)transistorsonSOIsubstrate,notablythe double-gate(DG)FinFET,provideanalternativetoCMOStechnology scaling.Themultiple-independent-gateFinFET(MIGFET),wouldallow dynamicmodulationofelectricalcharacteristicssuchasVtinnanoscale circuitapplications.Importantphysicalinsightsaregainedregardingthe performancecharacteristicsanddesignoftheMIGFET.Novel applicationsoftheMIGFETtoacompactlow-power/lowvoltageRFmixer circuitandananoscalesix-transistorstaticrandomaccessmemory (SRAM)cellaredemonstratedwithUFDG(UniversityofFloridaphysicsbased compact DG MOSFET model) simulations. AFinFET-basedhybriddevice,namelytheinverted-T(IT)FET,is proposedforimprovingcurrentdriveperpitchbyfabricatingasingle-gate fully-depleted(FD)SOIMOSFETintheunusedportionofthepitcharea. PhysicalinsightsregardingthedesignandperformanceoftheITFETare gainedwiththeUFDGmodelinSpice3,combinedwithsimulationsdone withthe3-DnumericalsimulatorDavinci,withdesigngoalstoachieve goodcurrent-voltagecharacteristics,i.e.,highIon/pitchandhighIon/IoffwithacceptableVt.Itsadvantagesineffectingagooddesignofananoscale SRAMcellandofanoveltwo-transistorfloating-bodymemorycell(2TFBC) are proposed and analyzed.

PAGE 16

1 CHAPTER 1 INTRODUCTION WiththerapidscalingoftheCMOStechnologybeyondthe conventionalbulk-Sisolutions,noveldevicestructuresandmaterials integrationarebeingintensivelyexaminedtosustaincontinued improvementindevicesforhigh-performanceandlow-power requirementsindigitalIC,aswellastoachievedenseCMOSlogic.For theformer,continuedenhancedcurrentdrivewithrobustcontrolof deviceelectrostatics,i.e.,shortchanneleffects(SCEs),thresholdvoltage (Vt),etc.,isneededtomaintainagoodCMOSIon/Ioffcharacteristic.The variousoptionsinpursuitincludeintegratingnewmaterials,suchas thoseusedforenhancedcarriertransport,forminimizedsource/drain parasiticresistance,andforsuppressedgateleakage,orconstructing newdevicearchitectures,suchasultra-thin-body(UTB)transistorsto improvetheelectrostaticsofthenanoscaleMOSFETs.TheCMOSdevice structureswearegoingtoexplore,definedasnonclassicalCMOSinthis dissertation,asdistinguishedfromtheclassicalconventionalbulk-Siand PD/SOI CMOS, are illustrated in Figure 1.1, and introduced as follows. Withnocompromiseonlayoutpenalty,aneasysolutionappearsto beincorporatingstrainintothechannelregion,e.g.,strainedSiand/or strainedSiGe,etc.,eitheruniaxiallyorbiaxiallyforenhancedcarrier transportinthechannel[Rim00,Tho02].Thestrainmodifiestheenergy

PAGE 17

2 Si Substrate Buried Oxide if SSOI Strained Si or SiGe Si Substrate Buried Oxide n+ Source n+ Drain Gate n+ Source n+ Drain Gate Transport-enhanced UTB SOI MOSFETs MOSFETsFigure 1. The various nonclassical CMOS device options to be explored in this dissertation, with comparative notes.Biaxial or Uniaxial strainPlanar FD/SOI with UTBDG FinFET with UTBInverted-T FET HP CMOSHP, LOP and LSTP CMOS HP, LOP and LSTP CMOS HP, LOP, and LSTP CMOS Enhanced carrier transportGood SCE control; bulk inversion Scalable to ~10nm; convertible to MIGFET for LOP and LSTP appli. Improvedlayoutefciency, i.e., current per pitch Difcult to implement biaxial strain; questionablescalability> 50nm Very thin Si body is required, which limits scalability > 25nm Sublithographic n thickness required; discrete n width Ungated n-base leakage; scalability limited by the FD/SOI SOI thickness? DG FinFET SG SOI FETSOI GateSiO2 SD G SD G SD G G

PAGE 18

3 bandstructureinboththeconductionandvalencebands,whichresults inincreasedcarriermobilityduetoreducedintervalley(interband) scatteringandsmallerconductivityeffectivemass[Fis96,Tak96,Obe98]. Further,thecarrierenergyrelaxationtimeisenhancedduetoreduced densityofstatesinstrained-Si(SS)channels,whichgivesriseto improved velocity overshoot in short channel devices [Rim00, Hat01]. Thetypicalbiaxialtensilestraincanbeintroducedviaathin epitaxialSichannelgrownonarelaxedSiGesubstrateforimproved electronandholemobilities.Enhancedspeedperformancesthatcanbe achievedwithbiaxiallySSchannelsinbulk-Siaswellaspartially depleted(PD)SOICMOS,havebeendemonstratedexperimentally [Rim01,Miz02].However,thetechnologyhasbeendifficulttoimplement becauseofmisfitandthreadingdislocations,Geup-diffusion,integration complexityandcost[The03].Also,littleholemobilityenhancementis gainedathightransverseelectricfields,andsubstantialdecreasein nMOSFETthresholdvoltage(Vt)occurs[Rim02].Mostrecently,uniaxial tensilestrainforimprovedelectronmobilityandcompressivestrainfor holemobilityenhancement,introducedthroughlow-costtechniques(i.e., selectiveepitaxyand/orcappinglayers),isgainingincreasedattention andinterestduetomuchbetterholemobilityenhancementanda relativelysmallnMOSFETthresholdvoltageshift[Tho04,Tho05]. UniaxiallystrainedSihasbeenimplementedinahigh-volume manufacturing90nmlogictechnologywithimpressiveperformance results [Tho02].

PAGE 19

4 However,inthelongrun,SSchannelsbuiltonclassicalCMOSare eventuallylimitedbythesamedifficultyincontrollingSCE’swith continuedscalingbeyond50nm.Ontheotherhand,UTBtransistorson SOIsubstrate,i.e.,fullydepleted(FD)single-gate(SG)MOSFETand double-gate(DG)MOSFET,havedemonstratednotonlyhighcurrent drive,butalsoexcellentnanoscaledeviceelectrostaticsduetotheir inherentsuppressionofSCEsandsubthresholdleakage[Kim01,Tri03]. TheplanarFD/SOIMOSFETisscalabledowntoabout25nmgatelength, limitedbythetechnologicalconstraintontheUTBthickness,whichis probablyabout5nm.TheDGFinFETtechnologyisofmostinterestand promisingbecausetheutilityofthesecondgateprovidesenhancedgate controlofchannelcharges,whichrendersCMOSscalableevendownto 10nmgatelength;furthermore,itsfabricationandprocessintegration are compatible with conventional CMOS process [Fri01, Kim01, Yan04]. AstheUTBtransistorsarepreferredundoped[Tri03],gate materialswithnear-midgapworkfunctionaretypicallyrequired. Technologically,though,itisstillchallengingtopreciselycontrolthe gateworkfunction,whichthusrendersVtcontrolinflexible.Recently, independentgatecontroloftheFinFET,asinFreescale’sMIGFET, selectivelyconvertedfromFinFETsusinga“masklessetch-based process”[Mat04],hasbeendemonstrated,whereeitherstaticordynamic modulationofelectricalcharacteristicssuchasVtcanbeattainedby biasingthesecondgate[Mat04].AlthoughtheMIGFET,operatedin single-gatemode,tendstoyieldrelativelyweakerdrivecurrentand

PAGE 20

5 degradedsubthresholdslopeduetochargecouplingfromthebackgate, suchnoveldeviceswithflexibleelectrostaticscontrol,forexample,could relaxrequirementsforgatework-functionengineeringforVtcontrol, enableCMOSintegratedcircuitstobeoptimallydesignedwithvariableVtdevices,andallowforcreativeconstructioninnovelcircuit applications,whereareaefficiencyandlowoperatingand/orstandby power are critical. Mostrecently,anotherinterestingdevicestructurethatcombines therobustelectrostaticsoftheDGFinFETwithimprovedcurrentdrive perpitchbyincorporatingasingle-gate(SG)FD/SOIUTBMOSFETin theunusedportionofthepitchareahasbeenproposed[Mat05].This devicecanpotentiallyovercomethelayoutinefficiencyofthecurrent FinFETtechnology,whosewidthis“digital”andwhosefinheightis limitedbytechnologicalconstraintonthefinaspectratio.Further,the FD/SOIdevicewidthiscontrollable,whichoffersacertainflexibilityin deviceandcircuitdesign.Theviabilityofthishybrid-deviceconcept stemsfromthefactthatSG(withthickBOX)andDGMOSFETswith undopedUTBshaveaboutthesamethresholdvoltagewhentheSCEsare wellcontrolled[Tri03,Kim05].Theprocessingofsuchahybriddevice, whichwecalltheInverted-T(IT)FETbecauseofitscross-sectionalshape, hasbeendemonstrated[Mat05],butnoanalysisofitsdesignnor performance potential in nanoscale CMOS applications has been done. Thewholeideaofthisdissertationistoexplorethedesignand performanceofthesenovel,nonclassicalnanoscaledevicestructures,

PAGE 21

6 withourprocess/physics-basedcompactmodels(i.e.,UFPDB[Fos02a] andUFDG[Fos05]),addressingtheimportantdesigngoalsforoptimal currentdriveandcontrollabledeviceelectrostaticswithregardto pragmatic circuit applications. Adetailedphysicalmodelingofthemajorimpactsofbiaxialstrain ontheattributesofbulkSiandPD/SOIMOSFETsispresentedin Chapter2,basedonthemodifiedelectronicbandstructureas documentedinliteratureandontheoreticalworkontheenhancedcarrier transportpropertiesofstrained-Sichannels.Notealthoughthecarriertransportpropertieshavebeenextensivelystudied,lessattentionhas beenpaidtothestrain-inducedVtshifts,whicharetypicallynot negligibleinthebiaxiallySSCMOS.Theytendtounderminethe performanceenhancementthatcanbeobtainedwithSSCMOS technologybecauseofthenecessaryredesignofthedevices.Therefore,VtshiftsinSSCMOSdevicesarefirst carefullyexaminedintermsofthe shifted2-Denergysubbandsandthemodifiedeffectiveconduction-and valance-banddensitiesofstates.Thenfurthermodelingoftheenhanced carrier-transportpropertiesandparasiticsduetoSSchannelsonbulkSias wellasonPD/SOIisaddressed,anditsimplementationwithourprocess/ physics-based UFPDB model is overviewed. WiththemodelingasnotedfromChapter2,theCMOSelectrical characteristicsandspeed-performanceenhancementthatcanbeexpected fromstrained-Si/Si1-xGexchannelsinbulkSi,andinPD/SOI(SSOI),are projectedinChapter3,versustheGecontentx.Theuncertaintiesabout

PAGE 22

7 theelectronicbandstructureinSSchannelsduetothewiderangeof deformationpotentialsreportedintheliterature,whichmightrenderthe calculatedVtshiftsequivocal,andtheirimpactontheperformancelosses due to Vt redesign are examined. Importantphysicalinsightsregardingdesignandperformanceof theMIGFETaregainedinChapter4,viameasureddataandsimulations donewithourprocess/physics-basedUFDGmodel.Inparticular,the sensitivityoftheMIGFETVttovariationsinVGbSisstudiedand explained.InChapter4andinChapter5,novelapplicationsofthe MIGFETtopracticalcircuitsareproposed,andthendemonstratedto greatlybenefitfromtheindependent-gatecontroloftheMIGFET.The utilityoftheMIGFETinacompactlow-powerRFmixercircuit,with regardtodesigngoalsofminimumdeviceparasiticsandsubstrate coupling,smallarea,lowvoltage,andlowpower,isstudied,aswellas compromisesregardingconversiongainanddynamicrangeunderlowvoltageandlow-powerconstraints.ThentheMIGFETusedinthedesign ofananoscale6T-SRAMcellwithregardtoread/writestability-speed trade-offs is explored. InChapter6,weuse UFDG,combinedwithsimulationsdonewiththe 3-DnumericalsimulatorDavinci,togaininsightsregardingthedesignand performanceoftheITFET,withdesigngoalstoachievegoodcurrent-voltage characteristics,i.e.,highIon/pitchandhighIon/IoffwithacceptableVt. However,signicantsubthresholdleakagethatmightresultfromtheungated

PAGE 23

8 n-baseregionoftheITFET structurecanunderminethebenefitsof enhancedcurrentdrive.Therefore,weexploredesignoptionsaswellas considerationsofdevicegeometryforminimizedsubthresholdleakage, whichareessentialtoachievethedesireddesigngoals.Wealsoconsider thescalabilityoftheITFETtechnology.TheITFETcouldhave widespreadapplications.Foroneapplication,itsadvantageineffectinga gooddesignofthe6T-SRAMcellwithregardtothearea-performance trade-off is evaluated and demonstrated. ForanotherapplicationoftheITFETtechnology,weproposeandstudy inChapter7anovelnanoscaletwo-transistoroating-bodyDRAMcell(2TFBC)basedontheITFETtechnology.The workingprinciplesanddesign conceptsofthe2T-FBCareexplored,theresultsofwhichhelptoclarify someofthemisconceptionaboutthebody-chargedynamicsinanFD/SOI MOSFET,whichunderliesthedesignofthe1T-FBCaswell.The2T-FBC functionalitywithbothvoltage-sensingandcurrent-sensingschemesis demonstrated with our UFDG model in Spice3. InChapter8,thisdissertationisconcludedwithasummaryand suggestions for future works.

PAGE 24

9 CHAPTER 2 PHYSICS-BASED MODELING OF STRAINED SI/SI1-XGEX MOSFET AND ITS IMPLEMENTATION WITH UFPDB MODEL 2.1 Introduction AsSi-basedCMOSisbeingscaledtowardapalpablelimit(near Lgate=50nm),thereisgrowinginterestinMOSFETsdesignedwith strained-Si/SiGechannelsbecauseofthepotentialenhancementin performanceduetoimprovedcarrier-transportproperties,i.e.,mobility andhigh-fieldvelocity[Hat01,Rim01,Rim02].Althoughthetechnologies havenotbeenperfectednortheunderlyingphysicscompletely understood,enhancedperformancesthatcanbeachievedwithstrained-Si channels(SS)inbulk-Siaswellasinpartiallydepleted(PD)SOICMOS havebeendemonstratedexperimentally[Rim95,Rim00,Rim01,Miz02, Rim02],andimportantphysicalmechanismshavebeenidentifiedand characterized theoretically [Fis96, Tak96, Obe98, Hat01]. ForthecaseofaSilayer(channel)underbiaxialtensilestrain causedbythelatticemismatchofanunderlyingrelaxedSi1-xGexlayer [Arm98,Rim00,Cur01],theenergy-bandstructureismodifiedandthe inversion-carriertransportpropertiesareenhanced,withdependenceon theGecontentx.Theenhancementfollowsfromimprovedvelocity saturationandovershooteffects,aswellasincreasedmobility[Fis96, Tak96,Arm98,Obe98,Rim00,Cur01,Hat01].Theimprovedovershoot

PAGE 25

10 wasshowntoresultfromastrain-inducedincreaseinthecarrierenergyrelaxationtime[Rim00].Further,theband-structuremodification effectivelyresultsinshiftsofbothconductionbandandvalenceband edges,andthereforeanarrowedenergybandgap,dependentonx[Peo86, Arm98],whichtendstoyieldareducedthresholdvoltage[Tau98]forthe heterostructure MOSFET relative to the Si counterpart. Inthischapter,adetailedphysicalmodelingofthemajor impactsofbiaxialstrainontheattributesofbulk-SiandPD/SOI MOSFETsispresented,basedonthemodifiedelectronicbandstructure asdocumentedinliteratureandontheoreticalworkontheenhanced carrier-transportpropertiesofstrained-Sichannels.Inthefirstpart,the thresholdvoltageshifts( D Vt(SS)relativetoVtofSi-controldevices)instrainedSi/Si1-xGex(SS)CMOSdevicesarecarefullyexaminedintermsoftheshifted 2-Denergysubbandsandthemodifiedeffectiveconduction-andvalance-band densitiesofstates.Then,modelingofthestrain-enhancedcarrier-transport propertiesandparasiticsinstrainedSi-on-SiGeinbulk-SiandPD/SOICMOS, anditsimplementationwithourprocess/physics-basedUFPDBmodelare addressed and overviewed. 2.2 Threshold Voltage Model 2.2.1 Threshold Voltage Shifts in Strained Si TheSSMOSFET,illustratedinFigure2.1,tendstohavea reducedthresholdvoltage(Vt(SS)),anditsadjustmentviaredesignofthe deviceunderminestheactualperformanceenhancementthatcanbe achieved.Heavierchanneldoping,forexample,canbeeasilydoneto

PAGE 26

11 Poly-Si Gate Strained Si SourceDrain Relaxed Si1-xGex Buffer Si Substrate Figure 2.1Cross-sectionalviewofbiaxiallystrained-Si/Si1-xGexbulk-Si MOSFET.

PAGE 27

12 compensateforreducedVt(SS),butsuchdesigndegradestheenhanced carriermobilityandincreasessource/drainjunctioncapacitance, significantlylimitingthespeedperformanceimprovementinSSCMOS [Fos03].Optimizingthechanneldopingand/orusingametalgatehave beenutilizedinattemptstoovercomethisproblem[Goo03a,Xia03],but thetechnologicalissuesarenottrivial.Tofacilitatesuchdesign optimization,aswellastoreasonablypredictthespeedperformance improvementthatcanbeachievedwithSSCMOS,weneedmoreaccurate physicalmodelingoftheVt(SS)shift( D Vt(SS))intermsofthevariationsof bandgap,electronaffinity,andeveneffectiveconduction-andvalenceband densities of states. Recentliteratureshows,however,thatthereseemstobemuch confusionandmisunderstandingofexactlyhow D Vt(SS)isdefinedinterms oftheGecontent(x)intheunderlyingSi1-xGexbufferlayer,especially whenbothn-channelandp-channeldevicesareconsidered.Someworkers havesaidbandgapnarrowinginSSisthemainreasonfor D Vt(SS)[Cav02, Buf03],butothershavesaidtheelectron-affinitychange,orbandoffset betweenSSandSiGe,isallthatmatters[Sug02,Goo03b];andsome experimentalistshavementionedbotheffectsaspossibleexplanationsfor theirVt(SS)data,butwithoutdetaileddiscussion[Rim01,Rim02].Even the D Vt(SS)datathathavebeenpublishedarescatteredandconfusing. Rim,etal.[Rim02]indicatethatasmuchas~100mVthresholdshift resultsforlong-channelSSMOSFETswithx=0.20,whileinshortchannelnMOSFETs,forexample,enhancedAsdiffusioninSiGecanadd

PAGE 28

13 another~100mVtoit.Goo,etal.[Goo03b]indicatebynumericaldevice simulationsthata100mVreductioninVt(SS)ofSSnMOSFETsoccurswith each0.10incrementalincreaseinx,andthatthereductionis40mVforSS pMOSFETs.Theirexperimentaldata[Xia03]for25nmnMOSFETs indicatethatthe“band-offsetinducedVtshift”is~200mVforx=0.20.For SSpMOSFETs,Sugii,etal.[Sug02]showexperimentallythatx=0.30 givesalmostthesameVt(SS)asunstrained-SipMOSFETs,whichthey attributetopossibletrappedchargeattheSS/SiGeinterfacethatdefines a“balancing”shiftinflat-bandvoltage.Armstrong,etal.[Arm98]report that~250mVreductioninVt(SS)(magnitude)occursinaSSpMOSFET withx=0.30whenastrainedgrade-backSiGebufferlayerissandwiched betweentheSSlayerandtherelaxedSiGelayertoavoidconfinementof holesattheSS/SiGeinterface.However,quantitativeexaminationof Vt(SS)inSSpMOSFETsbyNumata,etal.[Num03]indicatesthatwhen theSSlayerisrelativelythick(~20nm)orwhenagrade-backSiGelayer isused,Vt(SS)(magnitude)actuallyincreasesbyasmuchas~50mVwith x increasing to 0.40, instead of decreasing. Thepurposeofthissectionistoremoveconfusionregarding D Vt(SS)versusxbygivingphysicalinsightsonthepredominantdifferences betweenSSandSichannelsthatunderlieit.Inparticular,wemodel D Vt(SS)(x)forSSnMOSFETsandpMOSFETsinbulkSi(themodelsare applicabletoPD/SOIMOSFETsaswell),withcomparisonstopublished datathatimplyhowSSaffectsthedeviceprocessing.InChapter3,wewill useourmodelstoprojecthowtheinherentSSCMOSspeedperformance

PAGE 29

14 isunderminedbytheneedtoredesignthedeviceswithadjustedVt(SS)for off-state current control. 2.2.2 Model Development Weconsiderascaledbiaxially-SSMOSFETstructureinbulkSi, asillustratedinFigure2.1,havingasuper-steepretrograded,orsuperhalochanneldopingprofile[Tau98].Themaximumdepletionwidth(td) underthegateisthuscontrolledinthetechnology. Generally, D Vt(SS)will dependonthethicknessoftheSSlayer(tSS)relativetotdsincethematerial propertiescanvaryacrossthedepletionregion[Num03].To makeour physicalmodelsimpleandclear,andavoidthenoteddependence,wefirst assumethattSS>td,whichisnotuncommonfornanoscaledevices.Later, wediscusscomplicationsimpliedbytSS
PAGE 30

15 Asweknowfortheconductionband(innMOSFETs),thestrain inducesasubbandenergysplitting, DES~67meVforeach0.10increment inx,betweentheperpendicular D2andparallel D4subbandladders [Hoy02],thusincreasingtheoverallsplittingoverthatassociatedwiththe quantizationeffect[Tau98].Similarlyforthevalenceband(in pMOSFETs),whereasthequantizationfavorstheoccupancyoftheheavyholesubband,thestraininducesanenergysplitting, DES~40meV/(0.10/ x),ofthelight-holeandheavy-holebandsthattendstooffsetthe quantizationeffectandpushthelight-holebandupinenergyandinto predominance[Buf03].Inbothdevicesthen,thebandgapintheSSlayer is effectively narrowed according to [Peo86, Arm98, Num03]: (eV) .(2.1) (Althoughrecentlynoteddeformationpotentials[Lim04]implyuncertaintyin thisclassicalcharacterization,weuseitnonetheless.) Further,thestrain modifiesthecarriereffectivemassesaswellastheeffectivedensitiesof states(DOS)inboththeconductionandvalancebands;thelatterare reducedbyfactorsof~5and~3,respectively,forx0.20[Nak02].All these changes must be accounted for in our models for D Vt(SS). Wefirstderive,fortheSSnMOSFET,therequiredshiftin surfacepotential, Dys(SS),todefinethesameinversionelectroncharge densityatthresholdasinthecontrol-Sichannel.Forthethreshold conditionatroomtemperature,weassumethemajorityoftheelectrons occupy the lowest-energy subband, in the D2ladder, with energy [Tau98] D E gSS () E gSi () E gSS () – 0.4 x ==

PAGE 31

16 (2.2) abovetheconduction-bandedgeEc;mxistheeffectivemassofelectronsin thequantum-confinementdirection (<100>) perpendiculartothesurface, and Esiselectricfieldinthesamedirectionnearthesurface.(Notethat thestrainwillshifttheabsolutesubbandenergyandEcidentically [Hoy02],andhenceE0isfixed.)Thetotalinversionchargeperunitarea is thus related to the surface potential ysn as [Tau98] (2.3) whereistheintrinsiccarrierconcentration,Ncand Nvaretheeffectivedensitiesofstatesinthe(3-D)conductionandvalance bands,respectively,mdnistheelectronDOSeffectivemassinthe D2ladder,andNCHisthechanneldopingdensity.Forthecontrol-Sidevice, definestheincreasedVtduetothequantization[Tau98], where yB=(kT/q)ln(NCH/ni)istheFermipotential.FortheSSchannelat threshold, ysn is changed by Dysn(SS) in accord with .(2.4) Combining (2.3) and (2.4) then gives, for the SS nMOSFET, E 0 9 hqE s 162 m x ---------------------2 3 --= Q iSS () QM 4 p qkT h 2 N CH -------------------n i 2 N c -----2 m dn E 0 kT ------ – exp q y sn kT -----------exp =n i N c N v E g 2 kT – () exp = y sn 2 yBDy snQM+ =Q iSS () QM y sn 2 y B Dy snSS () Dy sn QM ++ = Q iSi () QM y sn 2 y B Dy sn QM + = =

PAGE 32

17 (2.5) where,becauseof(2.4),Esisnotdependentonthestrain.Notethat Dysn(SS)<0wouldreflectadecreaseinVtn(SS).Thethirdtermin(2.5)can beassumednegligiblesincetheelectronmasses(mx,myandmzforthe D2ladder)varyonlyslightlyasaresultofthestrain[Fis96](asdotheDOS masses, which are given by). Thus, for the SS nMOSFET, ,(2.6) which depends on how Nv changes, as well as D Eg(SS). ThetotalVtshiftwilldependonhowtheflat-bandvoltage(VFB) shifts,aswellason Dysn(SS)in(2.6),ascanbeseenfromthebasicMOS (Faraday) relation [Tau98] ,(2.7) whereQsisthetotalchargedensityinthesiliconbody,whichatthe thresholdconditionisapproximatelythedepletionchargedensityQd. When the channel is strained, we can perturb (2.7) as follows: (2.8) Dy snSS () kT q -----N v m dn () Si N v m dn () SS ----------------------------ln D E gSS () – 1 q -9 hqE s 162 ---------------2 3 --1 m x -----SS1 3 --1 m x -----Si1 3 --– + = m dn m y m z = Dy snSS () kT q -----N v Si () N v SS () -----------------ln D E gSS () – @ V GB V FB – y sn Q s C ox --------- – = D V GS V FB – () SS Dy snSS () 1 C dm C ox ----------+ m Dy snSS () ==

PAGE 33

18 whereisthedepletioncapacitanceandmisthebodyeffectcoefficient.Applying(2.8)atthethresholdcondition,VGS=Vtn(SS), gives the total threshold voltage shift as ,(2.9) where m is assumed to be independent of the strain. ThechangeinVFBisduetoeffectiveconduction-bandlowering aswellas D Eg(SS),asillustratedbytheenergy-banddiagraminFigure2.2. FortheassumedstructurewithtSS>td,thecharacterizationofVFBinthe SSdeviceisstraightforward.Weneglectoxidecharge,andassumeVFB(SS)is just the gate-SS work function difference: (2.10) forthenMOSFETwithn+-polysilicongate,where cSiand cSSaretheSi andSSelectronaffinities,respectively,EvistheSSvalence-bandedge, andEFistheFermilevel(allnormalizedtobeinunitsofV).Notethat . For the control-Si nMOSFET, .(2.11) Therefore, from (2.10) and (2.11), (2.12)C dm D Q d – ()D y snSS () =D V tnSS () D V FBnSS () m Dy snSS () + = V FBnSS () F MSSS () c Si c SS – E gSS () – E F E v – () SS + ==E F E v – () kTq () N CH N v () ln – =V FBnSi () E gSi () – E F E v – () Si + = D V FBnSS () D E c – D E gSS () kT q -----N vSi () N vSS () -----------------ln – ++ =

PAGE 34

19 cSi cSiGe D Ec Eg(Si) -VFBEg(SiGe) Eg(SS)ElEFg, Ec EvElElEcEFsEv tSS cSSn+ poly-Si SS Si(1-x)Gex Buffer cSi cSiGe D Ec Eg(Si) -VFBEg(SiGe) Eg(SS)El Ec EFg, EvElElEcEFsEv tSS cSS p+ poly-Si SS Si(1-x)Gex Buffer SiO2SiO2 (a) (b) Figure 2.2Energy(inV)-banddiagramsattheflat-bandconditionfor strained-Si/Si1-xGex(a)nMOSFETsand(b)pMOSFETs, whereand; Elrepresentsthelocalvacuum,orreference,energylevel, andEFgandEFsaretheFermilevelsinthegateandSi substrate,respectively.ThedifferencesbetweenNcandNvof the SS layer and the SiGe buffer layer are ignored.D E c c SS c Si – () 0.57 xeV () == E gSS () E gSi () 0.4 – xeV ()=

PAGE 35

20 whererepresentstheconduction-bandloweringintheSS; note, a commonly used D Ec(x) is given as [Num03] (eV) .(2.13) (Asnotedfor(2.1),thereissomeuncertaintyin(2.13)tooduetothewiderange of deformation potentials reported in literature [Lim04]. With(2.5),(2.9),and(2.12),wecannowexpresstheVt(SS)shift in the SS nMOSFET as .(2.14) Interestingly,sincemistypically1.3-1.4fornanoscaleMOSFETs,the firstterm,i.e.,thechangeinelectronaffinity,canbethepredominant componentof D Vtn(SS),althoughthesecond(commonlyassumed)andthird (commonlyneglected)termscanbesignificant.Wenotethatevenifour assumptiontSS>tdisnottrue,(2.14)wouldstillbevalidsinceneither Dysn(SS)in(2.6)nor D VFBn(SS)in(2.12),asreflectedbyFigure2.2,would change. ThederivationofthethresholdvoltageshiftoftheSSpMOSFET, ,(2.15) issimilar,buttheresultisdifferent.Theshiftsinsurfacepotentialand flat-band voltage for this device, with p+-polysilicon gate, areE c D – c Si c SS – =D E c 0.57 x = D V tnSS () D E c – m 1 – ()D E gSS () – m 1 – () kT q -----N vSi () N vSS () -----------------ln + = D V tpSS () D V FBpSS () m Dy spSS () – =

PAGE 36

21 (2.16) and ,(2.17) wheremdpisthe2-DholeDOSeffectivemassinthepredominant subband.Note Dysp(SS)<0wouldreflectanincreaseinVtp(SS),ora decreaseinitsmagnitude.Again,althoughthecomplexshapeofthe valance-subbandenergysurfacesaresomewhataffectedbystrain,we ignorethiseffectandneglectthethirdtermin(2.16)sinceitshouldbe relatively small. Now, (2.15)-(2.17) define .(2.18) Noteherethat D Vtp(SS)<0wouldmeanthatthemagnitudeofVtp(SS)(whichisnegative)isincreasedbythestrain.In(2.18),boththebandgap narrowingandtheincreaseinelectronaffinitycontributesignificantlyto thethresholdshift,butwithdifferentsigns.Thethirdtermin(2.18)could berelativelysmall,andthefourthtermmaynotbesignificantatall.On theonehand,unliketheDOSeffectivemassinthecontrol-SipMOSFET, mdp(Si),whichisdefinedbytheheavy-holesubbandduetothehole Dy spSS () kT q -----N c m dp () Si N c m dp () SS ----------------------------ln D E gSS () – 1 q -9 hqE s 162 ---------------2 3 --1 m x -----SS1 3 --1 m x -----Si1 3 --– + = D V FBpSS () D E c – kT q -----+ N cSi () N cSS () -----------------ln = D V tpSS () E c D – m D E gSS () m 1 – () – kT q -----N cSi () N cSS () -----------------m – ln kT q -----m dp Si () m dp SS () --------------------ln + =

PAGE 37

22 confinementintheinversionlayer,theDOSeffectivemassintheSS pMOSFET,mdp(SS),isdefinedbythelight-holesubband,whichhasbeen pushedupbythestrain.Butontheotherhand,mdp(SS)actuallyincreases withincreasingstrain,asshownin[Fis96].Therefore,itisreasonableto assumethatmdp(Si)/mdp(SS)isabout1-2,whichmakesthefourthterm relatively small. FortheSSpMOSFET,ifourtSS>tdassumptionisnottrue,then Vtp(SS)couldbeaffected(reducedinmagnitude)bytheexistenceofa buriedchannelattheSS/SiGeinterfaceduetothesmallerelectron affinityintheSiGe[Num03].Thiseffectwouldchange Dysp(SS)in(2.16), but D VFBp(SS)in(2.17)wouldnotchange,asreflectedbyFigure2.2. Typically,however,theinversion-holechargedensityintheburied channelwouldnotgreatlyexceedthatintheSSchannel(modeled analogouslyto(2.3)),andhence D Vtp(SS)wouldnotdiffersignificantly from that given in (2.18). The D Vt(SS)expressionsin(2.14)and(2.18)werederivedbased onequalQiatthethresholdcondition.Torelateourmodelstomeasured thresholdvoltageshiftsbasedoncurrent,wemayneedtoaccountforthe enhancedlow-fieldmobilityintheSSMOSFETs, mSS> mSi.This enhancement,andthesubthresholdcurrent-voltageexpression[Tau98], define another term, (2.19) D V tSS () Dm SS () m kT q -----m SS m Si --------ln =

PAGE 38

23 where+and-applytothepMOSFETandthenMOSFET,respectively. However,sincetypically mSS/ mSi<2,thistermcouldberelatively unimportant. 2.2.3 Model Calculations for D V t(SS) (x) A. D Vt(SS)(x) Based on Equations (2.1) and (2.13): Thedependencesof D Vt(SS)in(2.14)and(2.18)onxare,inlarge part,definedby D Eg(x)and D Ec(x).Basedontheclassicalrelationsin(2.1) and(2.13),ourmodeling,includingtherelativelysmallDOSterms,then predicts,withassumedm=1.3,theVtshiftsforSSnMOSFETsand pMOSFETsplotted,versustheGecontent,inFigure2.3.Weincludein thefigureseveralmeasuredshiftsthathavebeenreportedinthe literature[Rim00,Sug02,Xia03,andPrivateCommunication].Whereas therearesomediscrepanciesbetweenthemeasuredandpredictedshifts, themodelsfor D Vtn(SS)(x)and D Vtp(SS)(x)seemtoshowtherighttrends. Forx=0.20,forexample,wepredictaVtn(SS)reductionof129mVinSS nMOSFETs,andaVtp(SS)reductionof46mVinSSpMOSFETs,which actuallymeansan increaseinthemagnitudeofVtp(SS).Themeasureddata generallyreflectsmallermagnitudesofVtn(SS)(x)andVtp(SS)(x).Partof thediscrepanciescouldbeattributedtouncertaintiesin(2.1)and(2.13), aswehavediscussed.TheDOSterms,whichareindicatedinTable2.1, arerelativelysmall,buttheydotendtoincreasethemagnitudesof Vtn(SS)(x)andVtp(SS)(x),andhencetheycouldbeoverestimated. Accountingfor D Vt(SS)( DmSS)in(2.19),alsoindicatedinTable2.1,would

PAGE 39

24 Leff = 0.24 m m [Sug02] Lgate = 0.13 m m [Rim00] Lgate = 25nm [Xia03] Leff= 0.24 m m [Sug02] Lgate = 1 m m pMOSFETs nMOSFETs 0.000.100.200.300.400.50 x -400.0 -350.0 -300.0 -250.0 -200.0 -150.0 -100.0 -50.0 0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0D Vt(SS) (mV) following from well accepted D Ec(x) and D Eg(x) following from Van de-Walle bandalignment theory Figure 2.3Model-predicted(curves/ X ’s),withm=1.3,andmeasured (pointswithLgateorLeffspecified)SS-inducedthreshold voltageshifts,inSSnMOSFETsandpMOSFETs,versus the Ge content in the underlying Si/Si1-xGexbuffer layer. [Private Communication]

PAGE 40

25 bring,insomecases,themodelpredictionsandmeasureddatacloser together.However,someofthediscrepanciescouldbeassociatedwithSSandSi-deviceprocessingdifferences,whichcouldyielddifferentdevice structuresandSCEs,andhencecontributetothemeasured D Vt(SS).We thusincludegate(oreffectivechannel)lengths (LgateorLeff) withthe experimentaldatainFigure2.3.TheSCEs[Tau98]depend,forexample, ontd,which,infact,couldbedifferentintheSSandSi-controldevices becauseof,forexample,differentdopantdiffusivitiesintherespective devices[Hoy02].Non-optimizedprocessingofSSnMOSFETsmayindeed x=0.10.20.30.40.5 D Vtn(SS) (mV) -64-129-198-267-336 D Vtn(SS) (mV) w/o DOS-related terms -69-138-207-276-345 D Vtn(SS) (mV) w/ D Vtn(SS)( Dmn) -77-147-216-285-354 D Vtp(SS) (mV) -39-46-51-56-61 D Vtp(SS)(mV) w/o DOS-related terms -5-10-15-20-25 D Vtp(SS) (mV w/ D Vtp(SS)( Dmp) -32-28-22 -25 -29 Table 2.1Model-predicted,withm=1.3,SS-inducedthresholdvoltage shifts,inSSnMOSFETsandpMOSFETs,versustheGe contentintheunderlyingSi/Si1-xGexbufferlayer. ContributionsoftheDOStermsin(2.14)and(2.18)and D Vt(SS)( Dm ) in (2.19) are also indicated.

PAGE 41

26 worsenSCEs,causingsignificantVtreductionduetoenhancedAs diffusioninSiGe,whichleadstodeeperS/Djunctiondepthandshorter LeffinSSnMOSFETs[Rim01,Miz03].Over-thinnedtSSinpMOSFETs mayresultinaparasiticSiGeburiedchannel,aswepreviouslynoted, which leads to worse SCEs and reduced Vt [Num03]. B. D Vt(SS)(x) Based on Van De-Walle Band Theory: Notethatalthough(2.1)and(2.13)arewellacceptedin literature,thereareuncertaintiesaboutthemduetoawiderangeof deformationpotentialsreportedinliterature,astheycannotbedirectly measured.Here,wecalculate D Eg(x)and D Ec(x)basedonVanDe-Walle band-alignmenttheory,usingthedeformationpotentialsrecommendedby C.VanDe-Walle[Van86],whoperformedthebasicstudiesonbandoffset inthestrained-SiGesystem.Accordingtothetheory,thebiaxialstrain e intheepitaxialplanecanbeconsideredashydrostaticdeformation superposedbyauniaxialstrainperpendiculartotheplane.Hydrostatic strainshiftstheaveragepositionofthevalenceandtheconductionbands by D Ec,avand D Ev,av,respectively,whereasuniaxialstrainsplitsthe degeneracy,andthereforefurthershiftsthesubbandswithrespecttothe average position by D Ec ’s and D Ev ’s: (2.20) (2.21) D E cav , 2 e 12 n – 1 n – --------------a c = D E vav , 2 e 12 n – 1 n – --------------a v =

PAGE 42

27 (2.22) (2.23) (2.24) (2.25) where n(=0.28 forSi)isthePoissonratio,and ac/ av(=4.18/2.46forSi),bc/ bv(=9.16/-2.35forSi),respectively,representthedeformationpotentials forhydrostaticstrainandforuniaxialstrainintetragonaldistortedcubic latticecells.Notethatstraineffectonthespinorbitsplit-offband interaction is ignored here. For strained-Si channel on relaxed-SiGe buffer, (2.26) wherexisGecontentintheSiGebuffer.Therefore,(2.20)and(2.22)yield the effective conduction band lowering ,(2.27) whereas (2.22) and (2.24) yield the effective valence band shift-up (2.28) D E c 2 g () 2 3 -- – e 1 n + 1 n – -----------b c = D E c 4 g () 1 3 -e 1 n + 1 n – -----------b c = D E v lh () 2 – e 1 n + 1 n – -----------b v = D E v hh ()e 1 n + 1 n – -----------b v = e 0.042 x = D E c 0.241 x = D E v 0.477 x =

PAGE 43

28 forstrainedSi.Theeffectiveband-gapnarrowinginstrainedSicanthen be calculated as .(2.29) ThecalculatedbandstructureofstrainedSi,asshownbythe schematicrepresentedinFigure2.4,is,fardifferentfromwhat(2.1)and (2.13)imply,consistentwithamostrecentstudyonthebandstructureof biaxiallystrainSi,usingthemostrecentlyaccepteddeformation potentials[Lim04].Substituting(2.27)and(2.29)into(2.14)and(2.18), withassumedm=1.3,thenyieldsthresholdvoltageshiftsversusGe contentforbothnMOSFETandpMOSFETrepresentedbythedashed linesinFigure2.3.Comparedtocalculationsfollowedfrom(2.1)and (2.13),Vtn(SS)(x)decreasesmoreslowlywithincreasingGecontentat approximatelyarateof0.4xormore,whereas|Vtp(SS)(x)|alsodecreases, almostlinearlywithincreasingGecontentatapproximatelyarateof0.5x ~0.6x,ratherthanincreaseorstayapproximatelyconstantaspredicted from(2.1)and(2.13).Both,however,deviatefartherfromthedatapoints. Notethatwehavetokeepinmindthatasidefromtheuncertainties mainlyassociatedwiththebandstructureandDOStermsinstrained-Si channel,thereareproblemswithprocessingdeviationsduetodifferent diffussivityofdopantsinstrained-Sitechnology,whichmightcontribute tolargediscrepanciesfromtheexpectedvaluesofVt(SS).Further,the availabledataarelimited.Inthenextsection,wheremodelingofscaled D E gSS () E gSi () E gSS () – D E c D E v + 0.718 x ===

PAGE 44

29 EcEv0.215x 0.126x 0.684x 0.526x Eg(Si)Eg(SS) = Eg(Si) 0.718x unstrainedhydrostatic strain uniaxial strain Figure 2.2Schematicofbandstructureofstrained-Sichannels(a)impliedby classicalrelations(2.7)and(2.8)and(b)calculatedbasedonVan De-Wallebandalignmenttheory,usingdeformationpotentials recommended by C. Van De-Walle. EcEv Eg(Si)unstrained Eg(Si) 0.4x strained (hydrostatic + uniaxial) 0.57x (a) (b)

PAGE 45

30 strained-SiCMOSanditsimplementationwithourprocess/physics-based UFPDBcompactmodel[Fos02a]isoverviewed,andalsoinChapter3, wherethespeedenhancementthatcanbeachievedwithscaledstrainedSitechnologyisprojected,wewillfurtherdiscusstheuncertaintiesof relations D Eg(x), D Ec(x),andtheDOStermsinourthresholdvoltage modeling and their impact on the speed performance. 2.3 Modeling of Scaled SS CMOS with UFPDB model 2.3.1 SS Channels in Bulk-Si CMOS ToprojecttheCMOSspeed-performanceenhancementthatcan beexpectedfromstrained-Si/SiGechannelsinbulkSiandinPD/SOI CMOS,theimprovedinversion-carriertransportpropertiesinstrained-Si channels,andtheenhancedparasiticeffects,suchastheundesirable source/drainjunctioncapacitancesaswellasstrainedinducedVtshift, whichmandatesdeviceredesign,needtobeproperlymodeledand implementedwiththeUFPDBmodel.Themodelisunifiedforbulk-Siand PD/SOIMOSFETs.ThesmallsetofUFPDBparametersrelatedirectlyto theMOSFETstructureandthepertinentdevicephysics,andhencecanbe wellestimatedwithoutcopiousdatasetsofmeasuredelectricaldevice characteristics.Forexample,theretrogradedchannelofascaled MOSFETisrepresentedinthemodelformalismbythreestructural parameters:NBL,thechanneldopingdensity;NBH,thehigherdoping densityunderthechannel;andTB,theeffectivelow-highjunction,or depletion,depth.TheutilityofUFPDBwasrecentlydemonstratedby usingit,implementedinSpice3,toprojecttheperformanceadvantageof

PAGE 46

31 PD/SOICMOSwithfloatingbodiesoverthebulk-Sicounterpartasthe technologies are scaled to Lgate < 100nm [Pel02]. Forthisstudy,UFPDB(Ver.2.0)wasinitiallyupgradedtoallow astrained-Si/SiGeoption.Onenewparameter(GEX,whichisalsoaflag fortheoption)specifiestheGecontentxinthebufferlayer,whichisused internallytodefinethebandgapnarrowinginthestrainedSi-channel/ depletionregionandintheunderlyingSiGebufferlayerbasedon(2.1). TheUFPDBformalism[Fos02a]usesabandgapnarrowedbystrainto directlymodeltheinversionchargeandchannelcurrent,thereby implicitly predicting the reduced Vtas approximately (2.30) forbothstrained-SinMOSFETsandpMOSFETs,whichisabout0.4xto 0.6x,dependingonthevalueofm.Notethisinitialassumptionimpliedby (2.30)isnotunreasonable,owingtothenoteduncertaintiesaboutthe electronicbandstructureinstrained-Sichannels;numericallythe thresholdshiftspredictedwith(2.30)arewellwithintheuncertaintiesof thecalculatedVt(SS)(x)asindicatedinFigure2.3,andapproximatethose predictedbyfollowingtheVanDe-Wallebandalignmenttheory.The errorsthatareintroducedbythisapproximationwillnotundermineour conclusionontheperformanceenhancementthatareexpectedofstrainedSi technology, as will be further discussed in Chapter 3. Forthestrained-Si/SiGeoptioninUFPDB,therearefourother process/physics-basedparametersthataredefinedbyx.Twoofthem(UO V D tSS () m 0.4 x =

PAGE 47

32 andTHETA)definethetransverseelectricfield-dependentcarrier mobility in the channel: (2.31) whereEx(eff)isthebias-dependenteffectivetransversefield,whichis definedintheUFPDBformalism[Fos02a].Thelow-fieldmobilityUO, whichisnormallydefineddirectlybythechanneldoping(NBL),is enhancedinstrained-Sichannelsduetoreducedphononscatteringand carrierredistributioninthemodifiedenergy-subbandstructure[Tak96, Obe98].Theenhancement(em)isdefinedforelectronsandholesbasedon theoreticalmodels[Hat01,Tak96,Obe98]astabulatedversusxinTable 2.2. Thus, (2.32) whereUOSithelow-fieldmobilityintheSicounterpartdevice.Notein Table2.2thatforxincreasingabove~0.30,emin(2.32)forelectronsand m UO 1 THETAExeff () + --------------------------------------------------= UOemUOSi = x0.100.200.300.400.50 em (nMOSFET)1.461.681.701.701.70 em (pMOSFET)1.251.682.352.522.55 Table 2.2Theoreticalpredictionsoflow-fieldelectron[Tak96]andhole [Obe98]mobilityenhancements(em,definedrelativetomobility inSicounterpartMOSFETs)instrained-Sichannelsonrelaxed Si1-xGex buffer layers of heterostructural MOSFETs.

PAGE 48

33 holessaturates.Thissaturationoccurswhenconductionandvalence subbandshavebeenseparatedinenergybythestraintothepointwhere singlesubbandspredominate,andintervalley/interbandphonon scatteringhasbeenvirtuallyeliminated[Tak96,Obe98].Thepredicted enhancementsconformwellwithrecentlymeasureddata[Cur01,Rim01, Rim02].Forexample,[Rim01]reportsanapproximate70%enhancement (em@ 1.70)inelectronmobilityforx=0.20,evenforEx(eff)ashighas 1.5MV/cm.Thesustainedelectronmobilityenhancementatsuchhigh fields,illustratedqualitativelyinFigure2.2relativetotheuniversal curveforSiMOSFETs[Tau98],maybeattributedtoreducedsurfaceroughnessscatteringassociatedwiththetensilestraininnMOSFETs [Rim01],inadditiontothereducedphononscattering.Contrarily, whereasthelow-fieldholemobilityinstrained-Si/SiGepMOSFETsisalso enhancedbyabout70%fo rx=0.20,recentlymeasureddata[Rim02]show thatitdegradesmoresharplywithincreasingfield,asillustratedin Figure2.2(althoughthereissomeexperimentalevidence[Hoy02]that,for relativelylargeGecontent,thehole-mobilityenhancementcanstillbe sustainedathighfields).Thishigh-Ex(eff)degradationcanbeexplainedby afield-induceddecreaseintheenergyseparationofthelight-holeand heavy-holesubbands,whichtendstocompensatetheincreasedseparation duetothestrain,thusenhancingtheinterbandphononscattering [Miz02].TheUFPDBparameterTHETAin(2.31)isevaluatedsimply,but withanaccountingforthedifferent m (Ex(eff))dependencesinstrained-Si/ SiGenMOSFETsandpMOSFETsreflectedbyFigure2.2.Fortheformer,

PAGE 49

34 Ex(eff)Si Si/SiGe Si Si/SiGe mnmp ~1.5MV/cm Figure 2.3Qualitativeillustrationoftransverseelectric-field dependencesofelectronandholemobilitiesinSS-channel MOSFETscontrastedtothose(universalcurves[Tau98]) in Si counterpart devices.

PAGE 50

35 weassumethatthestrained-SielectronmobilityathighEx(eff)isemtimes the Si electron mobility, like at low Ex(eff); then (2.31) yields (for nMOSFET) .(2.33) Forthelatter,weassumethatthestrained-Siholemobilitydegradesat high Ex(eff) to equal the Si hole mobility; then (2.31) yields (for pMOSFET) .(2.34) TheothertwoUFPDBparameters(VSATandVO)thatare dependentonxinthestrained-Si/SiGeMOSFETrelatetothehigh longitudinalelectric-fieldcarriervelocity,whichismostimportantin deep-submicrondevices[Tau98]andwhichcanbemoresignificantthan thecarriermobilityindefiningtheperformanceenhancementofstrainedSi/SiGedevices[Rim00,Hat01].VSATistheclassicalsaturateddrift velocity,which,basedontheoreticalpredictionsandonmeasurements andnumericalsimulationsofthestrain-inducedenhancementof transconductanceinshortandlongnMOSFETsandpMOSFETs[Rim00], is increased by about 10% in the strained Si: ,(2.35) which we assume for all x. VOisaparameterfromthevelocity-overshootmodeling[Ge01] inUFPDB.Themodelingisphysical,havingbeenderivedfromthefirst andsecondmomentsoftheBoltzmanntransportequation,andVO,the THETATHETASi= THETAemTHETASi @ VSAT 1.1 VSATSi @

PAGE 51

36 nominalvalueofwhichisunity,canbelinkedtotheenergy-relaxation time( tw)inthelatter.Thenotedworkin[Rim00]showedthat twis increasedinstrained-Sichannels,andtheeffectofthatincreaseon currentwasquantified,versusx,in[Hat01]bycomparingresultsof numericaldevicesimulationsusingdrift-diffusion(DD)andenergytransport(ET)tools.Theresults,forLgate=50nmstrained-Si/SiGe MOSFETs,aretabulatedinTable2.3.Notethatforx=0.20thetotal enhancementinon-statecurrent(Ion),forbothn-channelandp-channel devices,isabout40%relativetotheSicounterparts,andthatthevelocity nMOSFET Total Ion Enhancement Due to SS Channel FractionofEnhancement DuetoVelocityOvershoot x = 0.1030%0.73 0.2043%0.74 0.3045%0.73 0.4045%0.73 0.5045%0.73 pMOSFET Total Ion Enhancement Due to SS Channel FractionofEnhancement DuetoVelocityOvershoot x = 0.10 15%0.20 0.2042%0.36 0.3074%0.43 0.4083%0.45 0.5084%0.45 Table 2.3Numericallydetermined[Hat01]Ionenhancements(defined relativetocurrentinSicounterpartMOSFETs)duetovelocity overshootinstrained-SichannelsonrelaxedSi1-xGexbufferlayers of heterostructural MOSFETs; Lgate = 50nm.

PAGE 52

37 overshootaccountsforasubstantivefractionoftheenhancement.Infact, forallx,thevelocityovershootcontributessignificantlytothecurrent enhancement,especiallyinthenMOSFET,whichrendersanyuncertainty in(2.35)insignificant.(Sincethestraineffectsonbandgap(via(2.1))and onsurfacescattering(i.e.,(2.33)vs.(2.34))werenotaccountedforin [Hat01],theresultsinTable2.2maynotbeabsolutelyaccurate,butthe relativeresultsstressedhereshouldbereasonablyaccurate.)Foreach strained-Si/SiGedevicemodeledwithUFPDB,VOwasevaluated,versus x,bymatchingthevelocity-overshootenhancementsderivedin[Hat01] andgiveninTable2.2.Fortheseevaluations,thehighersignificanceof overshootimpliedbytheslightlyshorterLgatein[Hat01],relativetoLgate=60nmwhichwewilluse,wasaccountedforbyusingalowervalueof VSATtunedtomatchtheIonenhancementduetoincreasedmobilityonly as predicted by the DD simulations in [Hat01]. Finally,forthestrained-Si/SiGeoptioninUFPDB,theareal(AJ) componentsofthesource/drain-junctioncapacitance(CJASandCJAD)are increasedbasedonx[Kim02].Theseincreasesareduetothesmaller junctionpotentialbarrier( fB)andthehigherpermittivity( ex)inthe relaxedSi1-xGexlayer.UFPDBisacharge-basedmodel,andhenceCJASandCJADarecharacterizedbymodelingthedepletioncharge(QdSand QdD)underthesource/drainregionsinthesubstrate/well,thedoping density(NSUB)ofwhichisassumedtobemuchlowerthanthatinthe source/drain.FortheSiGeoption,thesubstrate/wellistherelaxedSi1-xGexlayerasshowninFigure2.1,andhence(genericallyforthe

PAGE 53

38 nMOSFET)CJA=-dQd/dVJwhere,fromthedepletionapproximation [Tau98], (2.36) with fB= fB(Si)D Eg(SS)and,basedonasimpleinterpolationbetweenSi andGe, ex=(11.7+4.6x) e0[Gro67];VJ,thereversebias,is-VBSforthe sourcejunctionand(-VBS+VDS)forthedrainjunction(whereusuallyVBS=0forbulk-SiCMOSdevices).Notethatherewehaveignoredthepossible variationofdensityofstatesinstrained-Sichannels,whichwould effectivelyamelioratetheeffectoftheactualbandgapnarrowingonthe increaseofCJASandCJAD.However,itsimpactontheCJAdegradationis minimal,comparedtothatoftherequiredhigherNSUBfordevice redesign,inprojectingtheperformanceadvantageofscaledstrained-Si technology, as will be discussed in the next chapter. 2.3.2 SS Channels in PD/SOI CMOS Themodelingofstrained-Sichannelsonbulkandits implementationwithUFPDBinsection2.3.1applytostrained-Si channelsonPD/SOIaswell,whichisillustratedinFigure2.6,sinceboth themodifiedelectronicbandstructureandtheenhancedtransport carriersversusxduetostrainarenotsomuchdifferentfromthoseinbulk Si. However, additional consideration of parasitic effects is needed. GiventhattheincreasedCJASandCJADduetostrainasreflected in(2.36)areavoidedduetothethickBOXinPD/SOIstructure,the QdAJNSUB 2 q exfBVJ+ () []12 – =

PAGE 54

39 Gate Strained Si SourceDrain Si Substrate Si1-xGexBOX S Si substrate Figure 2.4Cross-sectionalviewofstrained-Si/Si1-xGexPD/SOI MOSFET (SSOI) structure.

PAGE 55

40 increaseofperipheralchargecomponents,definedbythehigherchannel retrograde/halodopingdensity(NBH),correlatedwithincreasedchannel dopingforIoffcontrol,thenbecomesdominant,whichmightaffectthe speedperformanceenhancementthatcanbeexpectedofstrained-Si CMOS on PD/SOI. Further,fortheSOImode,withfloating-body(FB)effects controlledbyseveralcarrierrecombination-generationmechanisms [Fos02a],thereducedbandgapin(2.1),whichalsodefinesanincreased intrinsiccarrierdensity,isalsousedtodefineincreasedsource/drain junctionrecombination-generationrates.TheassociatedUFPDB parametersweresetbasedonmeasurementsofFBeffectsinscaledPD/ SOIdevices,fabricatedwithimprovedjunctionengineeringforcontrolof theDCeffectsonIoff.Amuchhighertrapdensity(NTR)andincreased recombination-generationcurrentcoefficient(JRO),relativetothoseof thebulk-SiCMOSdevices,arethusused.Thelatter,especiallyathigh operatingtemperatures,atwhichwewillperformthedeviceandcircuit simulations,tendstorenderanyincreasesinimpact-ionization,GIDL, junction-tunneling,andparasitic-BJTcurrents[Fos02a]dueto D Eginsignificant for relatively low VDD. 2.4 Conclusion Thresholdvoltageshifts( D Vt(SS))inbiaxiallystrained-Si/Si1-xGexCMOSdevices,definedbytheshifted2-Denergysubbandsand modifiedeffectiveconduction-andvalance-banddensitiesofstates,have beencarefullystudied.Increasedelectronaffinityaswellasbandgap

PAGE 56

41 narrowingintheSSlayerwerefoundtobepredominantcomponentsof D Vt(SS),whichisgenerallylesssensitivetothemodifiedDOSeffects.The generalmodeling,forbothn-channelandp-channelSSdevices,gives importantphysicalinsightsonhowthestrain,inadditiontothe quantization,shiftsthe2-Dsubbands,andhowthevariedthreshold surfacepotentialandtheshiftedflat-bandvoltagedefine D Vtn(SS)(x)and D Vtp(SS)(x).ThemodeledVt(SS)shiftsinsection2.2.3predictthesame trendsrevealedbypublisheddata,althoughthedataarescatteredand themodelscontainuncertainties.Infact,themodel-datadiscrepancies couldbereflectingprocess-relatedmodificationsinSSCMOSdevice structuresandSCEs.Noteworthyisthepredictionofnegativeandsmall D Vtp(SS)forSSpMOSFETs,butnegativeandsubstantial D Vtn(SS)(x)for nMOSFETsbasedontheclassicalband-structureandGecontent relationship.However,byfollowingthecalculatedbandstructurefrom VanDe-WalletheoryinSection2.2.4,bothsubstantial| D Vt(SS)(x)| reduction is predicted for both SS nMOSFETs and pMOSFETs. Theimplementationofthestrained-SioptionintheUFPDB modelfurthernecessitatesthemodelingoffourotherprocess/physics basedparametersthatrelatetotheenhancedtransportpropertiesin strained-Sichannels,aswellasincreasedareacomponentsofsource/ drainjunctioncapacitance.Additionalmodelingoftheperipheral componentsofsource/drainjunctioncapacitanceinstrained-SiPD/SOI MOSFETs,andseveralrecombination-generationmechanismsrelatedto

PAGE 57

42 thefloating-bodyeffects,whichareaffectedbythenarrowedbandgap ( D Eg), are also accounted for with our UFPDB model. Thepropermodelingoftheaboveimportantphysical mechanismsinstrained-SiCMOSwithourUFPDBmodelinthischapter facilitatesthereasonableprojectionofperformanceenhancementsthat canbeexpectedfromscaledstrained-SichannelsinbulkaswellasinPD/ SOI CMOS in Chapter 3.

PAGE 58

43 CHAPTER 3 PERFORMANCE PROJECTIONS OF SCALED CMOS DEVICES AND CIRCUITS WITH STRAINED SI-ON-SIGE CHANNELS 3.1 Introduction Theaimofthischapteristoproject,versusGecontentx,the CMOSspeed-performanceenhancementthatcanbeexpectedfrom strained-Si/Si1-xGexchannels(SS)inbulkSiaswellasinPD/SOICMOS, thedevicestructuresofwhichareillustratedinFigures2.1and2.6in Chapter2.Suchprojectionismadepossiblewithourprocess/physicsbased compact model UFPDB. InSections3.2and3.3,deviceandcircuitsimulationswiththe UFPDBmodel,implementedinSpice3,aredoneforSSchannelsinbulk SiandinPD/SOICMOS,respectively,basedonthemodelingofimportant physicalmechanismsduetostrain,anditsimplementationwiththe UFPDBmodelinChapter2.InSection3.4,theuncertaintiesaboutthe electronicbandstructureinSSchannelsduetothewiderangeof deformationpotentialsreportedforbiaxialstrainintheliterature,which tendstorenderthecalculatedthresholdvoltageshiftsequivocal,andtheir impact on the performance losses due to Vt redesign are examined. 3.2 SS Channels in Bulk-Si CMOS Weconsiderbulk-SiCMOSscaledtonearitslimit.Basedon2-D numericaldevicesimulationsdonewithMEDICI,wecalibratedUFPDB-

PAGE 59

44 2.0[Fos02]toarepresentativeLgate=60nmnMOSFET(Leff=50nm).The generalparameterevaluationfolloweddirectlyfromtheMEDICIdevice structure and the physical modeling used. Forthisretrograded-channeldevicewithn+-polysilicongate,the physicaloxidethicknessis1.3nm,thechanneldopingdensity(NBL)is 1.0x1018cm-3,thehigherretrogradedopingdensity(NBH)is2.0x1018cm-3, andthelow-highjunctiondepth(whichcouldbedefinedpartlybysuper haloes)is10nm(yieldingTB=29nm,effectivelyaccountingforthe depletionchargeinthehighsideofthejunction).Thelow-Ex(eff)electron mobility(UOSi=277cm2/V-s)isdefinedbyNBLviapublishedbulk-Si dependencesondopingdensity[Tau98].Thesamedevicestructure,but withp+-polysilicongate,wasassumedforthepMOSFET,meaningthatits low-Ex(eff)holemobility(UOSi=153cm2/V-s)islowerbyaboutafactorof two[Tau98].Further,weassumeitssource/drainseriesresistance parameters(RSandRD)arehigherbythesamefactor.WeassumedNSUB =5x1017cm-3fortheSi-controldevices,andthesource/drainareas(AJin (2.36))weredefinedbasedona6 l designruleforlength,with l =65nm. BasedontheseSi-controldevices,theMEDICI-predictedcharacteristicsof whicharecomparabletothemeasuredonesofthelow-Vt60nmMOSFETs describedin[Tho01],strainedSi/Si1-xGex-channelcounterpartdevices, withxrangingfrom0.10to0.50,werethendefinedwithUFPDB-2.0by specifyingGEX,whichdefinesthereducedVtasin(2.30)andwhich activatestheincreasedCJAdefinedby(2.36),andbymodifyingtheother fourx-definedmodelparametersasdescribedinChapter2.AlthoughRS

PAGE 60

45 andRDtendtobehigherinthestrained-Si/SiGedevices[Rim02],they wereassumedtobethesameasintheSidevices(300 W m mforthe nMOSFETsand150 W m mforthepMOSFETs).Also,theincreasein source/drain-junctionleakagecurrentduetothenarrowedbandgapwas ignored,assuming(inthebestcase)thattheoff-statecurrent(Ioff)is predominantlydefinedbychannelcurrentforviablex[Rim02].The strained Si-layer thickness was assumed to be TB. UFPDB-predictedIDS-VGScharacteristicsofthestrainedSi/ SiGe-channeldevicesforx=0.20arecontrastedtothepredicted characteristicsoftheSi-control(x=0)devicesinFigure3.1.Obviously, thenarrowedbandgapinthechannel,whichlowersVtandincreasesIoffbymorethananorderofmagnitude,mustbecompensatedforina redesignoftheSi/SiGedevice.SuchVtadjustmentismosteasilydoneby increasingNBL,whichwillalsodecreaseUOin(2.31)(whereUOSiis definedbyNBL)becauseofincreasedionized-impurityscattering. Further,increasingNBLimpliesthatNSUB(andNBH)mustbehigher [Kim02],whichwillincreaseCJAevenmoreasreflectedby(2.36).We assume(intheworstcase)thatNSUBincreasesproportionallywiththe increaseinNBL.Then,withNBLsettorenderIoffequaltothatoftheSicontroldevice,theUFPDB-predictedcurrent-voltagecharacteristicsare revisedasshowninFigure3.3.(Sincetheshort-channeleffectsarewellcontrolledintheSi-controldevices,weneglectedanychangeinthemdue tothehigherdopingdensitiesinthestrained-Si/SiGedevices.)The predictedIDS-VDScurves,comparedwiththoseoftheSi-controldevices,

PAGE 61

46 -1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0 VGS (V) 10-1010-910-810-710-610-510-410-310-2IDS (A/ m m) Si Si on Si1-xGex w/o Vt adjust Si on Si1-xGex w/Vt adjust (NBL) pMOSFETs nMOSFETs |VDS| = 1.0V Figure 3.1UFPDB-predictedIDS-VGScharacteristicsofLgate=60nm bulk-SiCMOSdeviceswithstrained-Si/Si1-xGexchannels, withandwithoutVtcontrol(viaincreasedchanneldoping density),contrastedwiththecharacteristicsoftheSicontroldevices.TheGecontentintherelaxedbufferlayer is x = 0.20.

PAGE 62

47 areshowninFigure3.2.NotethatwiththeVtadjust,theSi/SiGe nMOSFETstillyieldsa30%increaseinIon(forVDD=1.0V),butthereis onlya10%increaseinIonforthepMOSFET.Forthelatterdevice,the increasedNBL,coupledwiththeseveredegradationofholemobilityat highEx(eff)(see(2.34)andFigure2.5),limitstheIonenhancement.This trendobtainsforalltheassumedvaluesofx,forwhichtherelevant UFPDBparametersfortheVt-adjusteddevicesaresummarizedinTable 3.1. ThenotedproblemwiththeSi/SiGepMOSFETcanpossiblybe resolvedbyusingadifferentgatematerialtoadjustVt,ratherthanby increasingNBL.Useofap+poly-Si1-zGezgatehasbeeninvestigated recently[Lee98a].Itwasshownthat,foragivenGecontentxinthe channelofthepMOSFET,theGecontentzinthep+gate,whichdefines thegateworkfunction,canbeadjustedtocontrolVtandIoff.(Sincez affectsmainlythebandgap,andnottheelectronaffinity,suchtuningof thegateworkfunctionandVtwillnotworkforthenMOSFETwithann+poly-Si1-zGezgate[Lee98a].)Therefore,werecheckedthe60nmstrainedSi/SiGepMOSFETswithVtcontrolledviap+poly-Si1-zGezgates.Forthe ztuning,wesetthegate-channelwork-functiondifference(parameter WKFinUFPDB),foreachassumedvalueofx,togetthesameIoffasinthe Si-controlpMOSFET,leavingNBLunchanged.TherelevantUFPDB parametersaresummarizedinTable3.2.Wenote,basedonexperimental datain[Pon00],thattheWKFshiftsneededforxincreasingto0.50

PAGE 63

48 -1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0 VDS (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8IDS (mA/ m m) Si Si on Si1-xGex w/Vt adjust via NBL Si on Si1-xGex w/Vt adjust via WKF 10% higher Ion19% higher Ion30% higher Ion|VGS| = 0.2 1.0V Figure 3.2UFPDB-predictedIDS-VDScharacteristicsofLgate=60nm bulk-SiCMOSdeviceswithstrained-Si/Si1-xGexchannels andVtcontrol(viaincreasedchanneldopingdensity,and byap+poly-SiGegateforthepMOSFET),contrastedwith thecharacteristicsoftheSi-controldevices.TheGe content in the relaxed buffer layer is x = 0.20.

PAGE 64

49 nMOS DEG (eV) NBL (cm-3) UO (cm2/V-s) THETA (cm/V) VSAT (cm/s) VO x = 00 1.0x1018277. 0.9x10-67.0x1061.0 0.100.04 1.41x1018347. =238.x1.46 0.9x10-67.7x1061.27 0.200.08 1.78x1018360. =214. x 1.68 0.9x10-67.7x1061.37 0.300.12 2.13x1018338. =199. x 1.70 0.9x10-67.7x1061.39 0.400.16 2.49x1018316. =186. x 1.70 0.9x10-67.7x1061.39 0.500.20 2.86x1018299. =176. x 1.70 0.9x10-67.7x1061.39 pMOS DEG (eV) NBL (cm-3) UO (cm2/V-s) THETA (cm/V) VSAT (cm/s) VO x = 00 1.0x1018153. 0.9x10-67.0x1061.0 0.100.04 1.36x1018170. =136. x 1.25 1.13x10-67.7x1061.22 0.200.08 1.74x1018208. =124. x 1.68 1.51x10-67.7x1061.52 0.300.12 2.13x1018270. =115. x 2.35 2.12x10-67.7x1061.61 0.400.16 2.48x1018267. =106. x 2.52 2.27x10-67.7x1061.67 0.500.20 2.86x1018265. =104. x 2.55 2.30x10-67.7x1061.69 Table 3.1RelevantUFPDBparametersforLgate=60nmSi-controlandVtadjustedstrained-Si1-xGexCMOSdevices.TheVtadjustwas effected by increasing NBL as indicated.

PAGE 65

50 correspondt oz<~0.40inthepoly-SiGegate.Notethatuseofapoly-SiGe gatealsoavoidstheincreaseofNSUBintheSi/SiGepMOSFET,which increasedCJAwhenNBLwasusedforVtcontrol.(Wenotefurtherthat useofap+poly-SiGegatecanameliorategatedepletionandboron penetrationinthechannelofthepMOSFET[Lee99],butthesebenefits were not accounted for in our simulations.) Forx=0.20,theUFPDB-predictedIDS-VDScharacteristicsfor thestrained-Si/SiGepMOSFETwithVtcontroleffectedviaap+poly-SiGe gate(withz @ 0.17[Pon00])areincludedinFigure3.4.Notetheenhanced Ion,whichisnow19%higherthanthatoftheSi-controlpMOSFET.Table pMOS DEG (eV) WKF (V) UO (cm2/V-s) THETA (cm/V) VSAT (cm/s) VO x = 001.03 153. 0.9x10-67.0x1061.0 0.100.040.97 191. =153. x 1.25 1.13x10-67.7x1061.22 0.200.080.92 257. =153. x 1.68 1.51x10-67.7x1061.52 0.300.120.86 360. =153. x 2.35 2.12x10-67.7x1061.61 0.400.160.81 386. =153. x 2.52 2.27x10-67.7x1061.67 0.500.200.76 390. =153. x 2.55 2.30x10-67.7x1061.69 Table 3.2RelevantUFPDBparametersforLgate=60nmSi-controlandVtadjustedstrained-Si1-xGexpMOSFETs.TheVtadjustwas effectedbydecreasingWKF(correspondingtoap+poly-SiGe gate) as indicated.

PAGE 66

51 3.3summarizesthepredicted60nmCMOSdevicefeatures(Ion,Ioff,Vt)for bothmethodsofVtcontrolinth ex=0.20strained-Si/SiGeMOSFETs.For comparison,thetablealsoincludesthefeaturesofthestrained-Si/SiGe devices without Vt control, and those of the Si-control devices. Tocheckthespeed-performanceenhancementaffordedbythe strainedSi/SiGe-channelMOSFETsinthe60nmCMOStechnology, UDPDB/Spice3wasusedtosimulate9-stageunloadedinverter-basedring oscillators(ROs).ThesupplyvoltageusedwasVDD=1.0V.Wenotethat nMOSFET Vt(sat)(V) @ VDS = 1.0V, IDS = 100nA*Wgate/LgateIoff(A/ m m)Ion(A/ m m) (%increase) Si Control0.14 6.8x10-80.54x10-3Si/SiGe0.02 1.4x10-60.92x10-3(70%) Si/SiGe w/Vt(NBL)adjust 0.13 6.8x10-80.70x10-3(30%) pMOSFET Vt(sat)(V) @ VDS = 1.0V, IDS = 100nA*Wgate/LgateIoff(A/ m m)Ion(A/ m m) (%increase) Si Control-0.17 3.5x10-80.33x10-3Si/SiGe-0.06 6.3x10-70.46x10-3(40%) Si/SiGe w/Vt(NBL)adjust -0.16 3.5x10-80.36x10-3(10%) Si/SiGe w/ Vt (WKF) adjust -0.16 3.5x10-80.39x10-3(19%) Table 3.3UFPDB-predictedfeaturesof60nmstrained-Si/SiGeCMOS devices with and without Vt control as indicated; x = 0.20.

PAGE 67

52 theoscillationfrequencyandpropagationdelay( td)dependonlyweakly ontheratioofthepMOSFET/nMOSFETgatewidths.Inaccordwith [Hat01], we set this ratio to 1.4 to minimize td. WetabulateinTable3.4UFPDB/Spice3-predictedpropagation delaysfromsimulationsofstrained-Si/Si1-xGexCMOSROswithx=0.20. ThetableincludesthepredicteddelayoftheSi-control(x=0)CMOSRO, andtherelativespeedenhancementsyieldedbythestrained-Si/SiGe channels.Further,togainmorephysicalinsightontheenhancements,the tableincludesdelaysfornoVtadjusts,aswellasforVtadjustedviaNBL increasesasinTable3.1andviaWKFdecreasesforthepMOSFETsasin Table3.2.Finally,theeffectsoftheincreasedCJAareindicatedinTable CMOS Devices / Vt Adjust td (ps/stage)RelativeSpeed Enhancement (wrt Ref.) Si Control / None10.4Ref. Si/SiGe / None6.934% Si/SiGe / NBL9.95% Si/SiGe w/o increased CJA / NBL9.113% Si/SiGe / NBL for nMOSFETs, WKF for pMOSFETs 8.914% Si/SiGew/oincreasedCJA/NBL for nMOSFETs, WKF for pMOSFETs 8.419% Table 3.4UFPDB-predictedpropagationdelaysof9-stageunloadedCMOS inverter-basedringoscillators:strained-Si/Si1-xGex(x=0.20) versusSi-control(x=0)devices,withvariationsinVtcontrol,and with and without increased CJA.

PAGE 68

53 3.4byincludingdelayspredictedwithCJA(unrealistically)forcedtoequal tothatoftheSi-controldevices.NotethatwithouttheVtadjusts,a prodigious34%speedenhancementispredictedforthestrainedSi/SiGechannelCMOS,whichisduetothehigherIon’sgiveninTable3.3. However,withtherequiredVtadjusts,thisenhancementisreduced substantively.Whenincreasedchanneldoping(NBL)isusedtoproperly increaseVtofboththen-channelandp-channeldevices,thepredicted enhancementdropstoanearlyinsignificant5%.Ifap+poly-SiGegate (WKF)canbeusedtoadjustVtofthepMOSFET,therebyretainingthe benefitofincreasedholemobility,thespeedenhancementispredictedto be14%,whichperhapssuggeststhatthistechnologyisworthpursuing. NotefinallyinTable3.4thesignificantspeedlossduetotheincreased arealsource/drainjunctioncapacitanceintheSi/SiGedevices.Forthe assume dx=0.20andNBL-basedVtadjusts,theCJAincreaseisgreater than30%,wheretheeffectofhigherNSUBcorrelated(intheworstcase) withhigherNBLaccountsforthemostpart,andthespeedlossisabout 8%,whichvirtuallyeliminatesanybenefitofthestrained-Si/SiGe channels.(OptimalprocessintegrationcouldperhapsyieldlowerNSUB fortheneededNBL,and/orsmallerAJ,andtherebyreduceCJAandthis speedloss.)FortheWKF-basedVtadjustinthepMOSFET,thespeedloss duetotheSiGe-definedhigherCJAisreducedto5%,sinceNSUBisnot changedforstrained-SipMOSFETinthistechnology.Indeed,theselosses implyanadditionalspeedadvantageforPD/SOICMOS[Pel02]overthe bulk-Sicounterpartifstrained-Si/SiGechannelscanbeincorporatedin

PAGE 69

54 thinSOIdevices[Kim02,Miz02],whichhavenegligiblearealcomponents ofjunctioncapacitanceduetothethickbackoxideunderthesource/drain regions.Further,asindicatedinTable3.4,NBL-basedVtadjustswould beacceptableinPD/SOI,retainingabouta13%speedenhancementfrom the strained-Si channels as opposed to the noted 5% for bulk-Si CMOS. AlthoughhigherGecontentsimplytechnologicalproblems [Qui00],wesimulatedtheringoscillatorwithstrained-Si/Si1-xGexdevices forxrangingupto0.50.Forallassumedvaluesofx,littlerelativespeed enhancementwaspredictedwhenhigherNBLwasusedtocontrolVtin bothdevices;thepeakenhancementisthe5%forx=0.20.However,when thepMOSFETVtwascontrolledviap+poly-SiGegates(WKFdecreases), theresultsaremuchbetter.WeplotinFigure3.3thepredictedspeed enhancementsversusxforthistechnology.Notethattheenhancement peaksatx=0.30,withthepeakbeing16%.Thispeakresultswhen,for increasingx,theneededVtadjustreflectedby(2.30)becomessolargethat itobviatesthebenefitsofincreasedcarriermobility(butwithsaturating emin(2.32)asnoted)andvelocitytoIonreflectedbyTables3.1and3.2. Figure3.5suggeststhatx @ 0.20isoptimalsincehighervaluesyieldonly minimaladditionalspeedimprovements,whilecausingmoresevere technologicalproblems[Qui00].Foremphasis,wealsoshowinFigure3.5 thepreviouslynotedspeedenhancementpredictedforx=0.20whenthe increased CJA is ignored. Wenotedearlierthatrecentlymeasuredholemobilities[Hoy02] intimatedthat,forhighervaluesofx,someenhancementinstrained-Si/

PAGE 70

55 w/ enhanced high-Ex(eff) hole mobility w/o increased CJA 0.000.100.200.300.400.50 x 0.0 5.0 10.0 15.0 20.0 25.0 30.0Relative Speed Enhancement(%) Figure 3.5UFPDB-predictedpropagation-delayenhancementof strainedSi/Si1-xGex-channelCMOS,relativetotheSicontrolCMOSdelay,versustheGecontentintherelaxed bufferlayerfromUFPDB/Spice3simulationsof9-stage unloadedinverter-basedringoscillators.TheVtcontrolwas effectedbyhigherchanneldopingdensity(NBL)inthe nMOSFETsandbyp+-poly-SiGegates(WKF)forthe pMOSFETs.ThegatelengthsareLgate=60nm,the pMOSFET/nMOSFETwidthratiois1.4 m m/1.0 m m,andthe supplyvoltageisVDD=1.0V.Forx=0.20,thesinglepoint indicatesthedelaypredictedwhentheincreasedsource/ drainjunctioncapacitanceinthestrained-Si/SiGedevices wasignored.Forx=0.30,thesinglepointindicatesthe delaypredictedwhenitwasassumedthatthehigh transverse-fieldholemobilityisenhancedbythestrainasis the electron mobility.

PAGE 71

56 SiGepMOSFETchannelscouldpossiblybesustainedathightransverse electricfields,thusresultinginhigherfield-effectmobilitiesthanwe assumedvia(2.34).Tostressthesignificanceofthispossibility,wealso showinFigure3.3,forx=0.30,theUFPDB/Spice3-predictedROspeed enhancementthatcouldbeexpectedfromstrained-Si/SiGechannelsifthe surfacescatteringofholeswerereducedasitappearstobeforelectrons; inotherwords,if(2.33)appliedtoholesaswellaselectrons.The enhancementincreasesdramaticallyfrom16%to26%.Thisresultreflects howdetrimentalthelackofanyreducedhightransverse-fieldsurface scatteringinthestrained-Si/SiGepMOSFETsis,whetherVtiscontrolled via WKF (as in Figure 3.3) or via NBL. 3.3 SS Channels in PD/SOI CMOS (SSOI) Thesimulationsintheprevioussectionhasquantifiedthe substantialspeedlossforstrained-Si/SiGeCMOSonbulkduetothe increasedarealcomponentsofsource/drainjunctioncapacitance, especiallywhentheVtcontrolwaseffectedviaincreasedchanneldoping. Thisimpliesanewperformanceadvantageforfloating-bodyPD/SOI CMOSwhenstrained-Si/SiGechannelsareincorporated(SSOI)[Kim02, Miz02]asillustratedinFigure2.6.Inthissection,weuseourprocess/ physics-basedcompactmodel,UFPDB[Fos02a],whichisunifiedforbulkSiandPD/SOIMOSFETs,toproject,versusx,thespeedperformanceof scaledSSOICMOS,andtoassessitsenhancementrelativetoPD/SOI CMOSatatypicalelevatedoperatingtemperature.Further,we

PAGE 72

57 demonstrateandestimatetheaddedperformanceadvantageofSOIover bulk-Si CMOS resulting from strained-Si channels in the technologies. WeconsiderPD/SOICMOSscaledtonearitslimit.Basedon2Dnumericaldevicesimulations,wefirstcalibratedUFPDB(Ver.2.5)to representativeLgate=60nm(Leff=50nm)bulk-SiCMOSdevices.The source/drainareasweredefinedbasedona6 l designruleforlength,with l=65nm.ThePD/SOIcounterpartdeviceswerethendefineddirectlywith UFPDB,whichreplacesthewell/substratewithathickbackoxide(BOX) fortheSOImode.BasedonthesecontrolSOIdevices,strainedSi/Si1-xGexchannel(SSOI)devices,withxrangingfrom0.10to0.40,werethen definedwithUFPDBbyspecifyingGEXasx,anddefiningtheotherfour x-dependentparametersproperlyforthenMOSFETsandthepMOSFETs. Key parameters are listed in Table 3.5 for pragmatic x = 0.20. nMOSFET NBL (cm-3) UO (cm/V-s) THETA (cm/ V) VSAT (cm/s)VO x=0 1.0x1018270. 0.9x10-67.0x1061.0 0.20 1.89x1018351. 0.9x10-67.7x1061.4 pMOSFET NBL (cm-3) UO (cm/V-s) THETA (cm/ V) VSAT (cm/s)VO x=0 1.0x1018150. 0.9x10-67.0x1061.0 0.20 1.85x1018203. 1.5x10-67.7x1061.5 Table 3.5KeyUFPDBparametersforLgate=60nmSi-controlandVtadjustedSSOICMOSdevices.TheVtadjustwaseffectedby increasing NBL as indicated.

PAGE 73

58 UFPDB-predictedIDS-VGScharacteristicsoftheSSOI(x=0.20 withVtadjust)andcontrolSOI(x=0)devices,atatypicalelevated operatingtemperatureof100oC,areshowninFigure3.5,alongwiththose ofthestrained-channelbulk-Sicounterparts.Foralldevices,Vtwas increasedtogetIoffequaltothatoftheoriginalunstrained-channelbulkSidevicesbyincreasingthechanneldopingdensity(NBL),implyinga reductioninlow-fieldmobility(UO)andincreasesinassociateddoping densities(NBHandNSUB).WenotethattheDCFBeffectsintheSOI devicesat100oCarewell-controlled,anddidnotmandateanyadditional Vtincreases.ThepredictedIDS-VDScurvesfortheSSOIdevices,also comparedwiththoseoftheSOIandstrained-channelbulk-Si counterparts,areshowninFigure3.5.NotethattheSSOInMOSFET showsa32%increaseinIon(forVDD=1.0V)relativetotheSOIcontrol device,whiletheSSOIpMOSFETshowsan11%increase,limitedbythe noteddegradationofholemobilityathighEx(eff)in(2.31)asillustratedin Figure2.5.NotealsothattheSSOIdevicesshowonlyasmallcurrent advantage(4-5%)overthebulk-SicounterpartsduetoDCFBeffects, whicharelargelysuppressedbecauseofthenotedsource/drain-junction engineering that yields high recombination (JRO) currents. Tocheckthespeed-performanceenhancementaffordedbythe 60nmSSOICMOSrelativetotheSOIcounterpart,andtocomparethe enhancementwiththatofstrained-channelbulk-SiCMOS,weused UDPDB/Spice3tosimulate9-stageunloadedinverter-basedring oscillatorsat100oC.WeusedapMOSFET/nMOSFETgate-widthratioof

PAGE 74

59 -1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0 VGS (V) 10-910-810-710-610-510-410-3IDS(A/ m m) SSOI w/ Vt Adjust Bulk Si/SiGe w/ Vt Adjust PD/SOI pMOSFETsnMOSFETs Figure 3.6UFPDB-predictedIDS-VGScharacteristicsofLgate=60nm SSOICMOSdeviceswithVtcontrol,contrastedwiththe characteristicsofstrained-channelbulk-SiCMOSdevices withVtcontrol,andwithPD/SOICMOSdevices.TheGe content in the relaxed buffer layer is x = 0.20. |VDS| = 1.0V T = 100oC

PAGE 75

60 -1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0 VDS(V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8IDS (mA/ m m) 11% higher Ion vs. PD/SOI 4% higher Ion vs. 32% higher Ion vs. PD/SOI 5% higher Ion vs. bulk-Si counterpart Figure 3.7UFPDB-predictedIDS-VDScharacteristicsoftheLgate= 60nmSSOICMOSdevices,contrastedwiththe characteristicsofthestrained-channelbulk-SiCMOS devices,andwiththePD/SOICMOSdevices.TheGe content in the relaxed buffer layer is x = 0.20. SSOI w/ Vt Adjust Bulk Si/SiGe w/ Vt Adjust PD/SOI bulk-Si counterpart

PAGE 76

61 1.4,whichminimizedthepropagationdelay( td),althoughthedependence ontheratiowasweak.WetabulateinTable3.6thepredicteddelaysforx =0.20atVDD=1.0V,andtherelativeenhancements.NotethatSSOI CMOS(withtheVtadjusts)givesa13%speedenhancementrelativetothe SOIcounterpart,dueinlargeparttotheincreasedIonofthenMOSFETs indicatedinFigure3.5.NotefurtherthespeedpenaltyfortheVtadjusts, withoutwhichSSOIwouldgivea33%relativeenhancement.Thepenalty isaugmentedbythereducedcarriermobilitiesduetothehigherchannel dopingdensities(NBL)usedtoincreasetheVt’s.ComparingSSOIversus strained-channelbulk-SiCMOS,wepredicta33%speedenhancement, whichreflectsanaddedSOIadvantageoverthatduetodynamicFB effects(i.e.,dynamickinkeffect,transientcurrentovershoot,etc.)and reduced(Si-)junctioncapacitance.AsindicatedinTable3.6,wepredict CMOS Devices / VtAdjust td (ps/ stage) SpeedEnhancement(wrtRef.) Bulk Si (x=0) / Ref.11.1Ref.-Bulk Si/SiGe (x=0.2) / Yes10.55%-Ref. PD/SOI (x=0) / Yes8.027%Ref.SSOI (x=0.20) / Yes7.0-13%33% SSOI (x=0.20) / No5.4-33%SSOI (x=0.20) w/o increased CJ / Yes 6.8-15%Table 3.6UFPDB-predictedpropagationdelays(initial,withouthysteresis) andrelativespeedenhancementsof9-stageunloadedCMOS inverter-basedringoscillators:strainedSi/Si1-xGex(x=0.20) versusSi-control(x=0)devices,withandwithoutVtcontrol;VDD= 1.0V, T = 100oC.

PAGE 77

62 thelatterSOIadvantagetobe27%.Hence,wecaninfertheadded advantage,resultingfromtheincorporationofstrainedchannelsinthe technologies,tobeapproximately6%,assumingthattheFBeffectsare comparableinSSOIandSOICMOS.Thisnewadvantageresultsfromthe higherarealcomponentofsource/drain-junctioncapacitance(CJ)inthe strained-channelbulk-SiCMOS,whichisavoidedinSSOICMOSviathe thickBOX.NoteinTable3.6thatthiscapacitance,duetohigherNSUB (assumedtocorrelatewiththeincreasedNBL)aswellastheeffectsof D Egandthehigher exinSiGe,limitsthespeedbenefitofstrainedchannelsin bulk-SiCMOStoonly5%.(Optimalprocessintegrationandscalingcould perhapsyieldlowerNSUBfortheneededNBL,and/orsmallerjunction area,andtherebyrelaxthisspeedlimitation.)Contrarily,inSSOI,the lossisdueonlytothehigherperipheraljunctioncapacitance(definedby thehigherNBH, D Eg,andhigherex),andisminimal(2%)asreflectedby thesimulationresultsinTable3.6obtainedwiththecapacitance (unrealistically) forced to equal to that of the SOI control devices. AlthoughhigherGecontentsimplytechnologicalproblems [Qui00],wealsosimulatedtheringoscillatorwithSSOIdeviceshavingx rangingupto0.40.WeplotinFigure3.6thepredictedspeed enhancements(i.e.,relativetdreductions)yieldedbySSOICMOS,versus x,relativetothecontrolSOICMOSandtothestrained-channelbulk-Si CMOS,againat100oCwithVDD=1.0V.Notethattheformerpeaksforx =0.20-0.30,withthepeakbeing13%asinTable3.6.Thispeakresults when,forincreasingxabove~0.30,theneededVtadjustbecomessolarge

PAGE 78

63 0.000.100.200.300.40 x -5.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0SSOI Relative Speed Enhancement (%) Relative to PD/SOI Delay Relative to Bulk-Si Counterpart Delay w/ reduced pMOSFET surface scattering Figure 3.7UFPDB-predictedspeedenhancementofSSOICMOS, relativetothePD/SOICMOSandthebulk-Sicounterpart delays,versustheGecontentintherelaxedbufferlayer fromUFPDB/Spice3simulationsof9-stageunloaded inverter-basedringoscillators;Lgate=60nm,VDD=1.0V, T=100oC.TheVtcontrolwaseffectedbyhigherchannel dopingdensity(NBL).Forx=0.30,thesinglepoint indicatestheSSOIvs.SOIenhancementpredictedwhen hightransverse-fieldsurfacescatteringisassumedtobe reducedbythestraininthepMOSFETslikeinthe nMOSFETs.

PAGE 79

64 thatitobviatesthebenefitsofincreasedcarriermobilityandvelocityto Ion.ThelatterplotinFigure5peaksatx=0.30,withthepeakbeing35%, abithigherthanthatfo rx=0.20inTable3.6.Hence,thenewaddedspeed advantageofSSOICMOSoverthebulk-Sicounterpartcanpotentiallybe 8%.Theimprovednewadvantageathigherxfurtherreflectsthe detrimentaleffectofhigher(areal)junctioncapacitanceinthestrainedchannelbulk-SiMOSFETs,whichincreaseswithx.FinallyinFigure5,to stressthelimitsimposedbythelackofhole-mobilityenhancementathigh Ex(eff)instrained-Sichannels,weshow,fo rx=0.30,theUFPDB/Spice3predictedrelativespeedenhancementofSSOIthatcouldbeexpectedif enhancedholemobilityathighEx(eff)issustainedasitappearstobefor electrons,i.e.,ifthepMOSFETshadthesameTHETAin(2.31)asthe nMOSFETs.Theenhancementincreasesfrom13%to26%,reflectinga substantial13%speedlossduetothelackofhole-mobilityenhancement at high Ex(eff) in the strained-channel pMOSFETs. 3.4 Further Discussion of Performance Loss Due to V t Redesign Notethesimulationsintheabovetwosectionshavebeendone assumingreducedVt(SS)asdefinedby(2.30)forbothnMOSFETsand pMOSFETswithstrained-Sichannels.Thisdefinitioninitiallyresults fromalackofknowledgeofdefinitiveelectronicbandstructure modificationduetostrain.Numericallythethresholdshiftspredicted with(2.30)arewellwithintheuncertaintiesofthecalculatedVt(SS)(x)as indicatedinFigure2.3,andapproximatetothosepredictedbyfollowing theVanDe-Wallebandalignmenttheory.Comparedto(2.30)though,the

PAGE 80

65 Vande-Wallebandalignmentcalculationspredictabitlower|VtnSS(x)| reduction,whereasabithigher|VtpSS(x)|reduction;thepossiblebenefit oftheformerwould,however,benegatedbythelatter.Notethe improvementoftheSSCMOSintrinsicdelaytendstobemorelimitedby SSpMOSFET,asIonenhancementinthepMOSFETisseverely suppressedduetobarelyenhancedmobilityenhancementathigh transverseelectricfield,aswellasmobilitydegradationduetoincreased channeldoping.Therefore,itsustainstheconclusionthatlittlespeed enhancement(~5%)isachievablewithstrainedSionbulkCMOS, whereas~13%isachievablewithstrainedSionPD/SOICMOS technology. ThecalculatedVtn(SS)(x)andVtp(SS)(x)basedon(2.1)and(2.13), representedassolidlinesinFigure2.3,ontheotherhand,raisenew questionsaboutthepossiblyhigherperformanceenhancementthatcanbe expectedofstrained-SiCMOSduetonothavingtoadjustVtoftheSS pMOSFET.ForapragmaticGecontentof0.20,therefore,were-examined, for60nmSSCMOSonbulkSi,thelossofperformancewhenonlySS nMOSFETsneedtoberedesignedbycompensatingtheincreasedoff-state currentviaincreasedchanneldoping.Andtheresultisnotunexpected, sinceinSection3.1,wehaveprojectedtheperformanceenhancementfor strained-SiCMOSonbulk,whentheVtcontrolwaseffectedbyhigher channeldopingdensity(NBL)inthenMOSFETsandbyp+poly-SiGe gates(WKF)forthepMOSFETs,assuming|Vt(SS)|reductiondefinedby (2.30)forbothSSnMOSFETandpMOSFET.Withtherequiredadjustof

PAGE 81

66 Vtn(SS)=~120-130mVfora nx=0.20SSnMOSFET,the~70%low-field mobilityenhancementwillbereducedtoonly~30%duetotheneeded increasedchanneldopingdensity,whichleadstoanonly~30%on-state currentenhancement,wherethesource/drainseriesresistancesare minimized.Thesource/drainarealjunctioncapacitance(CJA)could increasebymorethan30%duetocorrespondinglyincreasedsubstrate dopingdensity(NSUB).Allthis,coupledwiththefactthatthehole mobilityintheSSpMOSFETisnotenhancedathightransversefields [Rim02],andhencelimitstheon-statecurrentenhancementtoonly~19%, substantivelyunderminesthespeedperformanceenhancementthatcan beachievedwithSSCMOStechnology,eventhough D Vtp(SS)(<0)might not be an issue as we have shown. Ring-oscillator(RO)simulationsusingourprocess-based MOSFETmodelUFPDBinSpice3revealthattheneededredesignofthe n-channeldopingtocompensatefor D Vtn(SS)intheSSnMOSFETwithx =0.20reducestheSSCMOSspeedenhancement,relativetothespeedof thecontrol-SiCMOS,toonly~14%,comparedto~34%whennoVtn(SS)adjustisdoneatall.Afairassessmentofthe D Vtn(SS)penaltyismade, however,bycomparingthe~14%enhancementwiththatofahypothetical SSCMOSinwhichthegateworkfunctionsofboththen-channelandpchannelSSdevicesaretunedtogetthesameoff-statecurrentsasinthe Si-controldevices.Thepredicted,hypotheticalenhancementis~24%, meaningthatthe D Vtn(SS)penaltyisalossofmorethan40%inSSspeed enhancement.Wenotethatabouthalfofthispenaltyisduetothe

PAGE 82

67 increasedNSUB,whichpredominantlydefinestheCJAincreaseintheSS nMOSFET.NotethisCJApenaltyduetoincreasedNSUBwouldbeavoided instrained-Si/SiGeCMOSonthinSOI,andhenceanadditionalspeed advantageofPD/SOICMOSoverthebulk-Sicounterpartisintimated,an ~5%ofwhichwouldbeareasonableestimationbasedonthespeed enhancementprojectionsinTable3.4whenp+poly-SiGeisusedasthe gateinSSpMOSFETonbulkforIoffcontrol,withorwithoutCJAincrease. (However,wealsonotethattheSSCMOSspeedenhancementgiven herein,basedon D Vtp(SS)<0(i.e.,anincreased|Vtp(SS)|),couldbetoo optimisticbecausethegenerallyreportedlow-fieldholemobility enhancementinSSpMOSFETsissmallerthantheenhancement predictedtheoretically,whichweassumedinoursimulations.)Note,with referencetoFigure2.3,thatGecontentshigherthan0.20implyevenmore speed-enhancementlossduetolargerrequiredVtn(SS)adjusts,thereby further casting doubt on the feasibility of biaxially SS CMOS on bulk Si. 3.5 Conclusion Deviceandcircuitsimulationsusingaprocess/physics-based compactMOSFETmodel(UFPDB)inSpice3weredonetoprojectthe CMOSspeed-performanceenhancementthatcanbeexpectedfrom strained-SichannelsonrelaxedSi1-xGexbufferlayersinbulkSiandPD/ SOICMOS.TheSiGeoptioninUFPDBusesparametersrelatedtocarrier mobilityandvelocity,anddefinesthereducedthresholdvoltageswithin reasonableuncertainties,allofwhichareevaluatedbasedontheGe contentx.Themodifiedbandstructurenecessitatesanincreasein

PAGE 83

68 thresholdvoltageforIoffcontrol,andsimulationsweredonebasedonthis controlbeingeffectedviaincreasedchanneldopinginbothn-channeland p-channel devices, and via p+ poly-SiGe gates for the pMOSFETs. UnloadedCMOSring-oscillatorsimulationsrevealthatthe formerdesignyieldslittlespeedenhancement(e.g.,apeakofonly5%for x=0.20)forstrained-Sichannelsinbulk-Si,becauseofsmallIonincrease inthepMOSFETswithheavychanneldoping,inwhichnosignificanthigh transverse-fieldenhancementofholemobilitywasassumed,and increasedCJAinbothnMOSFETsandpMOSFETsduetothehigherwell doping,assumedtobecorrelatedwiththechanneldoping,aswellasthe higherpermittivityandnarrowerbandgappropertiesofSiGebufferlayer. Thelatterdesign,similartothecasewhennoVtreductioninSS pMOSFEToccurs,barelyimpactsonthecarrier-transportpropertiesand parasiticCJAinthepMOSFETs,andthereforeyieldsbetterenhancement (14-16%foroptimalx=0.20-0.30).Nevertheless,CMOSring-oscillator simulationsshowthattherelativespeedperformanceenhancementhas beenseverelydiminishedviaVtredesigninthenMOSFET,e.g.,bymore than 40%, to an ~14% for strained-Si CMOS on bulk with x=0.20 Thesimulationsalsoquantifiedthesignificantspeedlossfor strained-Si/SiGeCMOSonbulkduetotheincreasedarealcomponentsof source/drainjunctioncapacitance,especiallywhentheVtcontrolwas effectedviaincreasedchanneldoping.Thislosswouldbeavoidedin strained-Si/SiGeCMOSonthinSOI,andhenceanadditionalspeed advantageofPD/SOIoverthebulk-Sicounterpartisintimated.Unloaded

PAGE 84

69 CMOSring-oscillatorsimulationsrevealthatatanoptimalx=0.20-0.30, aspeedenhancementof~13%isyieldedbySSOIrelativetoPD/SOI CMOS,whichintimatesanaddedadvantageof~8%withstrained-Si channels,inSOICMOSrelativetobulk-SiCMOS.Similarly,ifnoVtreductioninSSOIpMOSFEToccurs,anestimatedashighas~19%speed enhancementisachievablebySSOICMOSrelativetoPD/SOICMOSatx = 0.20. However,withallthetheoreticalpredictionsofbiaxiallySS CMOSspeedenhancementsgivenherein,limitedbythebarelyenhanced SSpMOSmobilityathighEx(eff),andthenecessityofVtadjustmentvia increasedchanneldopinginSSnMOS,wefurtherarguethatthe predictionscouldbeoptimisticbecausethegenerallyreportedlow-field holemobilityenhancementinSSpMOSFETsissmallerthanthe enhancementpredictedtheoretically,whichweassumedinour simulations.Theimmaturetechnologycouldpartiallyaccountforthis, whichhasbeendifficulttoimplementbecauseofmisfitandthreading dislocations,Geup-diffusion,differentdopantdiffusionpropertiesinthe SiGebuffer.Theformertwomechanismsadverselyaffectthemobility enhancementthroughenhancedCoulombscatteringandfurtherdegrade theSSMOSFETscharacteristicsbyinducingsignificantjunctionleakage (dueto highthreadingdislocationdensitynearthesource/drainregionsor mistpathsbetweensourceanddrain,andetc.)and gateleakage(dueto defectsinthedielectricandtheG-S/Doverlapregion).Thelattertendsto leadtohighersource/drainresistanceanddeeperS/Djunctionand

PAGE 85

70 reducedLeffinSSnMOSFET,andthereforeworseSCEsinSSnMOSFET. Otherproblemsincludethewaferfabricationandprocessintegration complexity and higher cost associated with it. Ontheotherhand,uniaxialtensilestrainforimprovedelectron mobilityandcompressivestrainforholemobilityenhancement, introducedthroughlow-costtechniques,i.e.,selectiveepitaxyand/or cappinglayers,aregainingincreasedattentionandinterestduetoits advantagesversusbiaxialstraininboththemuchbetterholemobility enhancementandarelativelysmallnMOSFETthresholdvoltageshift. Mostrecently,uniaxialstrainedSihasbeenimplementedinahigh volumemanufacturing90nmlogictechnologywithimpressive performanceresults.Inthelongrun,however,SSchannelsbuilton classicalCMOSareeventuallylimitedbythesamedifficultyincontrolling SCE’swithcontinuedscalingbeyond50nm.Alternatively,ultra-thinbody (UTB)transistorsonSOIsubstrate,i.e.,fully-depleted(FD)MOSFETand double-gate(DG)MOSFET,havedemonstratednotonlyhighcurrent drive,butexcellentnanoscaledeviceelectrostaticsduetotheirinherent suppressionofSCEsandsubthresholdleakage.Inthenexttwochapters, novelMOSFETstructuresbasedontheUTBonSOItechnologywillbe studied.

PAGE 86

71 CHAPTER 4 PHYSICALINSIGHTSREGARDINGDESIGNANDPERFORMANCEOF MULTIPLE INDEPENDENT-GATE FINFETS (MIGFETS) 4.1 Introduction Thedouble-gate(DG)FinFEThasbeenwidelyexaminedrecently becauseofitsperformancepotential,andexcellentsuppressionofshortchanneleffects(SCE)andcommensuratescalability,allstemmingfrom thedynamicchargecouplingbetweenthetwogatesaffordedbytheultrathinSi-finbody[Kim01],andbecauseofitsrelativelyeasyfabricationand goodintegrationfeatures[Fri01].Mostrecently,reportsoffabricationof independent-gateFinFETs,withdesirabledevicecharacteristicssuchas dynamicthresholdvoltage(Vt)controlandtransconductancemodulation, havebeenpresented[Liu03,Fri04,Mat04].Suchnoveldevicescouldrelax requirementsforgatework-functionengineeringforVtcontrol,and enableCMOSintegratedcircuitstobeoptimallydesignedwithvariableVtdevices.Uniqueamongthesedevicesisthemultipleindependent-gate FinFET(MIGFET)[Mat04],thetechnologyforwhichalsoenablesDG FinFETs to be fabricated on the same chip. Thegoalofthischapteristogainphysicalinsightsregarding designandperformanceoftheMIGFET,aswellastoshowanovel applicationofittoacompactlow-powerRFmixercircuit,viameasured dataandsimulationsdonewithourprocess/physics-basedcompactmodel

PAGE 87

72 (UFDG)[Fos04]forDGMOSFETs.Forthisstudy,UFDG,whichincludes adirectPoisson-Schrdinger-basedaccountingforthecarrier-energy quantizationinthethinbody,hasbeenupgraded(Ver.3.0)withanewD”splineformalismintermsofboththefront-gate(VGfS)andback-gate (VGbS)biases[Tri05a].The2-Dsplinesforcurrentandchargein moderate-inversionregionsofoperation,andotherassociatedupgrades, renderUFDGagenericfour-terminalmodel(withthefifthfloating-body terminal)thatisphysicallyandnumericallystableirrespectiveofdevice symmetryandarbitraryVGfSandVGbS.WithUFDGinSpice3,the sensitivityoftheMIGFETVttovariationsinVGbSwillbestudiedand explainedintermsofdevicestructure,andtheutilityoftheMIGFETin anRFmixerapplication,withregardtodesigngoalsoflowvoltage,low power,andsmallareawillbedemonstrated,notingcompromises regardingconversiongainanddynamicrangeunderlow-voltageandlowpower constraints. 4.2 MIGFET 4.2.1 DC Characteristics TheMIGFETstructureinitiallyassumedinthisstudyhasan undopedfin-bodyofthickness,orwidthwSi=25nm,andfrontandback gate-oxidethicknessestoxf=toxb=2.0nm.Bothgatesaren+polysilicon. UFDG-predictedIDS-VGfScharacteristics(perfinheighthSi)ofanLgate(= Leff)=80nmn-channelMIGFET,comparedwithmeasuredcharacteristics ofadevicewithalmostthesamestructure[Mat04],arepresentedfor varyingVGbSinFigure4.1.Themodelpredictionsareingoodaccordwith

PAGE 88

73 10-210-310-410-510-610-710-810-910-1010-11(a) -1.0-0.50.00.51.0 VGbS = -1.2, -1, -0.5, 0, 0.5, 1, 1.2V VGfS (V)IDS (A/ m m)VDS = 1.2V (gates tied together) DG mode (b) -1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0 VGfS (V) 10-1710-1610-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-310-2IDS (A/ m m) VDS = 0.1V VDS = 1V VGbS = -1 to 1V (0.2 V steps) (gates tied together) DG mode Figure 4.1(a)UFDG-predictedIDS-VGScharacteristics(perhSi)ofanLgate= 80nmn-channelMIGFETforvaryingback-gatebias;wSi=25nm, toxf=toxb=2.0nm.(b)Measuredcurrent-voltagecharacteristics (perhSi)ofanLgate=70nmMIGFETforvaryingback-gatebias, thestructure(wSi=25nm,toxf=toxb=2.4nm)ofwhichis comparable to that of (a).

PAGE 89

74 themeasureddata,andshowthatthesubthresholdslope,orgateswing S,aswellasVtaremodulatedsignificantlybyVGbSvaryingbetween-1V and+1V.NotethatthesensitivitiesofVtandStotheVGbSvariation dependonthenominalvalueofVGbS.Predictedandmeasured characteristicsofthedeviceintheDGmode(VGbS=VGfS)arealsoshown inFigure4.1.TheDG-modeS=64mVandDIBL=20mV/Vreflectvery goodcontroloftheSCE,duetothelowwSi/Lgateratio[Yan05].TheDIBL oftheMIGFETisalsolow,butvarieswithVGbSasthetransverseelectric fieldinthefin-bodyvaries[Tri05a].However,SoftheMIGFETismuch higherthanthatofthedeviceintheDGmodebecauseofdifferentGf-Gb coupling, which underlies the VGbS dependences as we now discuss. ToeffectivelyexploittheMIGFETVt(VGbS)dependencein variable-Vtcircuitdesign,thedependence,anditsconnectiontothedevice structure,mustbewellunderstood.FornegligibleSCE,thisdependence waspreviouslyapproximatedbysolvingthe1-DPoissonequationinthe fullydepletedfin-body,assumingafront-surfacesheetofinversioncharge [Lim83, Kim01]: (4.1) whereCof/b= eox/toxf/bandCb= eSi/wSiarethefront-andbackgate-oxide capacitancesandbodycapacitance,respectively;theright-hand-side approximationreflects eSi/ eox@ 3.Theparameterrisabody-effect constantdefinedbythedevicestructure,whichreflectsthefactthataDG V t D V D GbS -------------------r – C b C ob C of C b C ob + () ----------------------------------------- – == 3t oxf 3t oxb w Si + --------------------------------- – @

PAGE 90

75 MOSFEToperatedinsingle-gate(SG)modegiveselectrical characteristicscomparabletothoseofabulk-Sicounterpart[Fos02b].For controlled SCE then [Kim01, Fos02b], .(4.2) Clearly,thesimpleexpressionsin(4.1)and(4.2)donotrepresent theMIGFETsofFigure4.1well.ThemeasuredandUFDG-predictedD Vt/ D VGbSislargerthanthatgivenby(4.1),anditincreaseswithincreasing VGbS,asdoesS,unlikein(4.2).Evidently,theassumptionofacharge sheet[Lim83]isinappropriate,and,further,2-Deffects,orSCE,and effectsofthequantum-mechanicalconfinement(QME)intheSifin-body [Ge02] could be important. 4.2.2 Physical Insights Regarding V GbS Dependences TohelpexplaintheactualdependencesonVGbS,weshowin Figure4.2(a)UFDG-predictedcurrent-voltagecharacteristicsforthe MIGFETofFigure4.1(a),butwithlongLgate=1 m m,withthequantization modelingturnedoff(QM=0).Notethat(4.1),withr @ 0.2asdefinedby thedevicestructure,doesnotadequatelycharacterizetheUFDGpredictedVt(VGbS)dependencereflectedinFigure4.2(a).Further,the predictedSisalsomodulatedbyvaryingVGbS,whichisinconsistentwith (4.2).Thesubthreshold,orweakinversion-chargedistributioninthethin body,i.e.,volume,orbulkinversion[Tri05a],isobviouslyimportant. Indeed,boththefront-andback-gatebiasesare,inFigure4.2(a), S1r + () kT q ------10 () ln =

PAGE 91

76 (a) (b) -1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0 VGfS(V) 10-1710-1610-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-3IDS(A/ m m) VDS = 1.0V VGbS = -1.4 to 0.8V (0.2V steps) QM = 1 -1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0 VGfS(V) 10-1710-1610-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-3IDS(A/ m m) VDS = 1.0V VGbS = -1.4 to 0.8V (0.2V steps) QM = 0Figure 4.2UFDG-predictedIDS-VGScharacteristics(perhSi)ofalong Lgate=1 m mn-channelMIGFETforvaryingback-gatebias, with(a)andwithout(b)thecarrier-energyquantization accountedfor.TheVGbSrangein(b)isextendedtothe onset(near-1.4V)ofsignicantcarrieraccumulationnear the back surface.

PAGE 92

77 simultaneouslycontrolling,ormodifyingthechargedensityandits distribution,orthecentroidpositionintheSi-finbody.Inotherwords,toxfandwSi(ortoxb)in(4.1)areeffectivelymodifiedbyVGfSandVGbS,defining reff(VGfS,VGbS)inplaceofrandthusgivingbiasdependenceto D Vt/ D VGbSand to S. WithregardtoVt,definedbyaspecifiedcurrentlevel(i.e., 100nA(Wgate/Lgate),whichimpliesaparticularintegratedweak-inversion chargedensity),forVGbSmuchlessthanVGfS=Vt,theinversion-charge centroidisnearthefrontsurface,renderingreffclosetorin(4.1).For increasingVGbS,Vtdecreases,andthecentroidshiftstowardstheback surfaceoftheSibody,renderinganincreasingreffduetotheeffectivetoxfincreasingandtheeffectivewSi(ortoxb)decreasing.UntilVGbSismuch higherthanVGfS=Vt,reffcontinuestoincrease,butthentendstowarda constantvaluewhenthechargecentroidisclosetothebacksurfaceofthe Sibody.ThiseffectoftheshiftingchargecentroidonVt(VGbS)is illustratedinFigure4.3wherereff=D Vt/ D VGbSasextractedfromthe UFDG simulation results in Figure 4.2(a) is plotted versus VGbS. TheshiftingchargecentroidalsounderliestheS(VGbS) dependenceinFigure4.2(a),whichisalsoplottedinFigure4.3.For increasingVGbS,andthecentroidshiftingtowardsthebacksurfaceofthe Sibody,thefrontgatelosescontrolofanincreasingfractionofthecharge, causingStoincrease.Indeed,thisincreaseinSischaracterizedwellby (4.2) with r replaced by reff in Figure 4.3.

PAGE 93

78 -1.0-0.8-0.6-0.4-0.20.0 0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0S (mV) -1.0-0.8-0.6-0.4-0.20.0 VGbS (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0reff Lgate = 1 m m, QM =1 {Figure 4.2(b)} Lgate = 80nm, QM = 1 {Figure 4.1(a)} Lgate = 1 m m, QM = 0 {Figure 4.2(a)}Figure 4.3Effectivebody-effectparameter,orD Vt/ D VGbS,versus back-gatebiasextractedfromtheUFDG-predicted MIGFETcharacteristicsinFigure2(a),contrastedwith thosefromFigure1(a),whichshowtheSCEinfluence,and fromFigure2(b),whichshowtheQMEinfluence.The subthresholdswingversusback-gatebiasfromFigure2(a) is also shown.

PAGE 94

79 Besidesthenotedsensitivityofrefftotheshiftingcharge centroidwithchanginggatebiases,theQMEandtheSCEcanfurther modifyreff.AcomparisonoftheUFDG-predictedcharacteristicsofthe Lgate=80nmMIGFETinFigure4.1(a)withthoseoftheLgate=1 m mdevice inFigure4.2,with(Q M=1in Figure4.2(b))andwithout(Figure4.2(a)) quantizationaccountedfor,reflectshowreffandthebiasdependencesof VtandSareinfluencedbytheQMEandSCE.Weillustratetheinfluences inFigure4.3,whererefffromFigure4.1(a)(whichshowsboththeQME andSCEinfluences)andfromFigure4.2(b)(whichshowstheQME influence)arecontrastedwiththatfromFigure4.2(a)(whichshows neitherinfluence).NotethattheQMEtendstoincreasereffforlowVGbS, butdecreaseitforhighVGbSwhenthechargecentroidisneartheback surfaceoftheSibody.Thesetrendsareconsistentwiththefactthatthe quantizationtendstomovetheinversionchargeawayfromthesurfaces wheretheconfinementisoccurring.TheSCE,whichismostapparentin Figure4.3whenVGbS~Vt,tendstofurtherincreasereff.Thiseffectcan beexplainedbynotingthatthe2-DeffectsintheSi-finbodyaremost severewherethetransverseelectricfieldislowest,thustendingto increasethebulkinversionchargedensityandmovethecentroidaway from the surfaces. 4.2.3 Device Design Considerations Knowingthatreffdependsontheinversion-chargedistribution intheSibody,wecannowexploreoptimaldesignoftheMIGFET structureforVt(VGbS)sensitivity,aswellasattainableVtrangefor

PAGE 95

80 practicalback-gatebiases.Toillustratesuchdesignoptimization,we extractVt(atIDS=100nA(Wgate/Lgate))foreachvalueofVGbSfromFigure 4.2(b),andplotitinFigure4.4,focusingonapracticalVGbSrange(-1.4to -0.2V)fortypicalcircuitapplications.NotethatforVGbS>-0.2V,excessive back-channelconductionrenderstheVt(VGbS)sensitivity(i.e.,reff) unpredictablylargeandhardtocontrol,asevidentinFigure4.3,withS in(4.2)high.ForVGbS<-1.4V,excessiveholeaccumulationchargeatthe backsurfacescreenstheVGbS-modulatedelectricfieldanddecouplesthe backgatefromthefront(reff@ 0).Theaccumulationalsotendstoforma floating“neutral”bodyregion,whichinducesasubthresholdkinkeffect, asevidentinFigure4.1(b),andproducesuncontrollablecharacteristics. (Theholeaccumulationandassociatedfloating-bodyeffectsarenot accountedforinUFDG.)Further,VGbSmustbelimitedtoavoid breakdownoftheback-gateoxide,which,infact,couldoccurunderthe drain(drivenbyVGbD)priortothenotedaccumulationeffects.Therefore, asseeninFigure4.4,thepracticalrangeofVt(VGbS)isabout0.5V,from ~-0.1Vto~0.4V,achievedwithVGbSvarying~1.2Vasnoted,forthelongLgate MIGFET structure defined. NotethatwecanshifttherangeofachievableVtbyadjustingthe workfunctionofthefrontgate,andwecanshifttheneededrangeofVGbSbychangingtheworkfunctionofthebackgate.Forexample,ap+polysiliconbackgatewouldshifttheusableVGbSrangeupbyabout1V,to ~-0.4Vto~0.8V.Further,modifyingthedevicestructure,e.g.,thegateoxidethicknesses,canbeneficiallyaffectthepracticalrangesofVtaswell

PAGE 96

81 -1.4-1.2-1.0-0.8-0.6-0.4-0.2VGbS (V) -0.20 -0.10 0.00 0.10 0.20 0.30 0.40Vt (V) Lgate = 1 m m, QM =1Figure 4.4TheVt(VGbS)variation,forthepracticalrangeofback-gate bias,extractedfromtheUFDG-predictedcharacteristicsof theLgate=1 m mMIGFETinFigure2(b).Notethevirtual Vt(VGbS) linearity within this VGbS design space.

PAGE 97

82 asVGbS.Moreinsightonsuchdesignmodificationcanbegainedby extending(4.1),aswenotedearlierwithreferencetoFigure4.3,to include,tofirstorder,dependenceontheinversioncharge-centroid position xc (0 < xc < wsi): (4.3) wheretoxf(eff)andwSi(eff)areeffectivethicknessesdefinedbyxc(andthe differencebetween eSiand eox).Plotsofreff=D Vt/ D VGbSvs.xc/wSifor differentwSiandtoxbareshowninFigure4.5;comparisonwithFigure4.3 putstheplotsinFigure4.5inperspectivewithregardtoVGbS.ThereffdependencesonwSiandtoxbaremostsignificantwhenthecentroidisnear thebacksurface,which,aswehaveshown,isnotgooddesignspace.In gooddesignspace,wherexc/wSi<~0.5,theplotsinFigure4.5(a)showthat reffisvirtuallyindependentofwSi.Note,infact,thatforxc/wSi=0.5, whichcorrespondstoVGbS=VGfS=Vtfortheassumedsymmetrical MIGFETstructure,reff=1asgivenby(4.3),andasreflectedbyFigure4.3 withFigures1and2.So,thefin-bodythicknessissetexclusivelyforSCE control.Varyingtoxb,however,couldgiveusefuldesignflexibility.The plotsinFigure4.5(b)showthatincreasingtoxbdecreasesreff,asisobvious in(4.3),butalsoreducesitsdependenceontheinversioncharge distribution,i.e.,onxc/wSi.Thus,perhapsbenefitsofbulkinversion [Tri05a]couldbeexploited.Further,athickertoxbdefinesalarger r eff 3t oxfeff () 3t oxb w Sieff () + ----------------------------------------------3t oxf x c 3 + () 3t oxb w Si x c – () + -------------------------------------------------@@

PAGE 98

83 0.00.10.20.30.40.50.60.70.80.91.0 xc/wsi 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0reff wsi = 15nm wsi = 25nm wsi = 40nm xc/wsireff toxb = 2nm toxb = 5nm toxb = 20nm wsi = 25nm toxf = toxb = 2nm(a) (b) 0.00.10.20.30.40.50.60.70.80.91.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 toxf = 2nmFigure 4.5Effectivebody-effectparameterversusthenormalized positionofthechargecentroidintheSi-nbodyfor(a)varying wSiand(b)varyingtoxb,asgivenby(4.3).Thesolidcurvesare for the nominal MIGFET design assumed

PAGE 99

84 practicalVGbSrange,limitedbytheonsetsofaccumulation,inversion,and oxide breakdown as we previously discussed. AnotherapproachtogettingmoreoptimalVtcontrolusingthe MIGFETcouldbethe“synchronizeddrivingmodeofoperation”[Liu03],by whichVGbS=VGfS-VOSwhereVOSisaconstantoffsetvoltage.Thismode isactuallyanasymmetricalDGmodeofoperation[Kim01].Plotsof UFDG-predictedcurrent-voltagecharacteristicswithvaryingVOSforthis modeofoperationoftheLgate=80nmMIGFETwithn+polysilicongates areshowninFigure4.6.Inthiscase,ignoringtheSCEandQME,withthe sameassumptionofaninversion-chargesheetusedtoderive(4.1),weget ,(4.4) whichislessthanthesensitivityin(4.1)byafactorof(1+r).However, (4.4)doesnotfullymodelthecharacteristicsinFigure4.6either.The samephysicalmechanisms,thatis,theshiftingchargecentroidwith varyingbiasesandthebias-dependentinfluencesoftheSCEandQME,as explainedfortheunsynchronizedmodeofoperation,applytothe synchronizeddrivingmodeaswell.Thecouplingfactorrcan,therefore,be effectivelyreplacedwithreffin(4.4)torepresenttheactualsensitivityof D Vttothechangingbias D VOS.Unlike(4.3),however,thesensitivityin (4.4)isalwayslessthanunity,anditchangeslinearlywiththeshifting charge-centroidposition.Theuniqueadvantagesofthesynchronized drivingmodeofoperationareclearlyreflectedinFigure4.6bytheideal V t D V OS D ----------------r 1r + -----------@

PAGE 100

85 -1.0-0.8-0.6-0.4-0.20.00.20.40.60.81.0VGfS (V) 10-1710-1610-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-310-2IDS (A/ m m) VDS = 0.1 V VDS = 1.0 V VOS = 1.0 to -1.0 V (-0.2V steps)Figure 4.6UFDG-predictedIDS-VGScharacteristics(perhSi)ofthe Lgate=80nmMIGFETinFigure2(a),withvaryingoffsets (OS)betweenthefront-andback-gatebiases(VGbS=VGfSVOS) in the “synchronized driving mode of operation.”

PAGE 101

86 subthresholdcharacteristicsaswellasthehighersaturationcurrentsdue totheDGmodeofoperation[Kim01].Asshownin[Kim01],subthreshold slopesofMIGFETsoperatedinthesynchronizeddrivingmodewithwellcontrolled SCE are S @ (kT/q)ln(10) = 60mV at 300K. 4.3 Mixer OneofthenovelapplicationsoftheMIGFET,asdemonstratedin [Mat04],isacompactlow-powersingle-transistorRFmixer.In[Mat04], theMIGFETmixerwasoperatedat~50KHz.Withthenew2-Dspline formalismimplementedintheUFDGmodel,weareabletodynamically sweepboththefrontandbackgatesoftheMIGFETsimultaneouslyto simulatethissimplemixer,andexplore,forthefirsttime,itsperformance aswellasitsdesign.Arecentsimulation-basedstudy[Pei04]ofsucha DG-MOSFETmixerwaslimitedtolongchannellengths(20 m m),forwhich thegate-gatecouplingisnonquasi-staticduetothelongtransittime.The predominantcouplingisthuscontrolledbyan“interchannelreshuffling time,”whichisshortandenablesveryhigh-frequencyoperation.Here,we examinethemorepracticalshort-channelMIGFETmixerinwhichthe couplingisquasi-static,asstudiedinSec.II,andhighoperating frequencies are enabled by the short channel transit time. Theschematicofthesimplesingle-MIGFETmixerisshownin Figure4.7(a).AsmallRFsignal(),withaDC biasVGfS0,isappliedtoonegatewhilealargesquare-waveLO(local oscillator)signal(withfundamental-frequencycomponent v RF V RF 2 p f RF t () cos =

PAGE 102

87 RF+RF+ RFLO+ LO+ VOUTVoutRL = 500 W VDD = 1V Ground Ground RL = 500 W RL = 500 W RF LO VDD = 1V (a) (b) VDD = 1V Figure 4.7Mixerschematics:(a)mixerusingoneMIGFET;(b)doublebalancedmixerusingfourMIGFETs.NotethatRF+/RFand LO+/ LOare antiphase signals.

PAGE 103

88 )isappliedtotheothergate,andtheoutputatthe desiredintermediatefrequency()isextractedfromthe drainnode.WithtypicalVDD=1.0VandRL=500 W ,theMIGFETis generallybiasedinthesaturationregionforcommongatebiases.The mixingreliesonthechargecouplingofthetwogatesprovidedbythethin Sifin-body,andthereforedependsonthebiasconditionsofthetwogates aswellasthedevicestructureasweshowedinSec.II.Itcanoccureither whentheMIGFETisoperatingfullyswitched,withtheLOsignallarge enoughtoturnthedeviceonandoff,orsomewhereinbetween,witha nonlinearrelationbetweendraincurrent,IDS,andVGfSandVt(VGbS) definingthemixing.Intheformercase,thevoltage-conversiongain, whichisdefinedastheratioofthedesiredIFoutputvoltagetotheRF input voltage, is given by [Lee98b] (4.5) wheregmisthetransconductanceofthesingletransistor,whichvaries with both gate biases asindicated in Sec. II. Inthelattercase,thesquare-lawbehaviorisdrawnfromthe nonlinearIDS(VGfS,Vt(VGbS))relationoftheMIGFETforthedesired mixing,asmanysuchnonlinearitiesarewellapproximatedbyasquarelawshapeoversomelimitedrangeofinputamplitudes[Lee98b].Withthe MIGFETbiasedinsaturation,forexample,thedraincurrentvaries roughly as V LO 2 p f LO t () cos IFf RF f LO = G c 1 p -g m R L =

PAGE 104

89 (4.6) whereWeff(=hSi)istheeffectivewidthofthedevice,and1
PAGE 105

90 onbothgatebiases,includingthecharge-couplingdependence(reff(VGfS, VGbS)asreflectedinFigure4.3)aswellasthenonlinearityfactorn. However,forthe2nd-orderpower-seriesapproximationin(4.9),with regard to the vRF signal, we have ;(4.11) andassumingasmall vRFamplituderelativetothelargeamplitudeofthe back-gate LO signal,, we get from (4.10) and (4.11) .(4.12) Wenotethat(4.6)mightnotentirelycharacterizethenonlinear IDS(VGfS,Vt(VGbS))relationoftheMIGFETforallbiases.However,with (4.5)and(4.12),theruleofmodulating/optimizingtheconversiongain throughproperbiasesofthemixerinourcasecanbegeneralized,focusing onthequadraticterminthenonlinearIDS(VGfS,Vt(VGbS))oftheMIGFET. TheRFsignalfedthroughthefrontgateissmall,withavirtuallyconstant gate-sourcevoltage,whereastheLOsignalfedthroughthebackgateis large,andhencecangenerallymodulatethefront-gatetransconductance atagivenfrontgatebiastodefinethemixing.Theoptimalfront/back gate-biasrangeisthendefinedtobewheretheappliedLOcanmodulate thetransconductancethemost.Foranidealsquare-waveLOsignal,this means,inaccordwith(4.12),thelargerthedifferenceof g m W eff nV GfSOD n1 – nn1 – () V GfSOD n2 – v RF r eff v LO + () + ~ V GbS0 V ' LO G c 1 4 -R L g m V GfSOD V , GbS0 V ' LO + () g m V GfSOD V , GbS0 V ' LO – () – ( ) @

PAGE 106

91 transconductancescorrespondingtothealternatingLObiaspointsfora given RF DC bias, the higher the conversion gain. Toverifyanddemonstratethisinsightregardingtheconversion gain,simulationsoftheMIGFETmixerinbothtimeandfrequency domainsweredoneusingUFDG/Spice3.Theresultsconfirmourinsight almostprecisely.Then-channelMIGFETforthemixersimulationisthe sameLgate=80nmMIGFETinitiallyassumedinSec.IIandcharacterized inFigure4.1(a).Thelow-fieldelectronmobilityisassumedtobe500cm2/ V-s,whichmaybeabithighfortheusual<110>fin-channelorientation, butisachievable[Mat04,Tri05a].TheS/Dseriesresistancesareassumed tobeRS=RD=300 W-m m,thoughtheycouldbeevenhigherandbiasdependentdependingontheFinFETtechnology.Thefinheighthereis assumedtobe100nm,inaccordwithatypicalfinaspectratio(hSi/wSi= 4).However,tomeetthemixerconversion-gainrequirementreflectedby (4.11)and(4.12),multi-findevices(weuse80here)canbeusedforlarger Weff,thoughthenumberisgenerallyconstrainedbythepowerandarea requirements,andlimitedbythedesiredIFfrequencysincetheoutput bandwidthisdegradedbythehigherparasiticcapacitancesassociated with larger widths. TheUFDG-predictedtransconductanceoftheMIGFETisplotted versusVGfSatvariousvaluesofVGbSinFigure4.8,withtheminimum VGbSlimitedto-1.0VduetoLOpowerconsiderations.TheoptimalRFand LObiaspointsformaximumGcasimpliedby(4.12)canbefoundas indicatedintheplot,thatis,withthefrontgatebiasedatVGfS0~0.22V,

PAGE 107

92 -1.0-0.50.00.51.0VGfS (V)0.00 0.10 0.20 0.30 0.40 0.50gm (mA/Vm m) VGbS = 0.0 to -1.0 V (-0.2 V steps) VDS = 1.0 V optimal RF and LO bias points for maximum mixer conversion gain Figure 4.8UFDG-predictedtransconductance(perhSi)versusfrontgatevoltageoftheLgate=80nmMIGFETforvaryingbackgatebias,withtheminimumVGbSlimitedto-1.0V.The dashedcurveplotsthedifferentialtransconductanceover theallowedrangeofVGbS(-0.2Vto-1.0V),indicatingthe optimalVGfSandalternatingLObiasesformaximumgmvariation.

PAGE 108

93 andVGbSswitchingbetween-0.2Vand-1.0V,i.e.,thebackgatedriven withVGbS0=-0.6VandV’LO=0.4V.NotethatbeyondagivenVGbS(inthis caseVGbS>-0.2V)atthegivenVGfS0,thefront-gatetransconductance graduallydecreaseswithincreasingVGbSsincetheback-surface conductionbecomesmoresignificant,aswediscussedinSec.II.Transient andFouriersimulationsofthemixerweredonewithUFDG/Spice3at thesegatebiases,withfRF=1.8GHzandfLO=1.6GHz.Thetransient resultsareshowninFigure4.9(a).Fordownconversion,Gc=-8dbforthe 80-finMIGFET,andthecorrespondingpowerconsumptionatthegiven biasesisverylowat0.3mW.Morefingerswouldbeneededtoincreasethe conversiongain,butwithcompromiseofthepowerandarea specifications. Further,mixersarerequiredtohavelargedynamicrange,which isdefinedbythenoiseflooratthelowerendandnonlinearityatthehigher end,withthelatterbeingthemorecruciallimitingfactorthatcauses distortionandsaturationofthesignal.Thenoisefigureshouldbe relativelylowforamixeronanSOIsubstrateliketheMIGFETmixer, withrelativelylowsubstratenoise[Ada02];thedominantnoisesourcein themixeristhechannelthermalnoiseofthetransistor.Thelinearityof themixergenerallydependsonthelinearityofthecurrent-voltage characteristicsofthemixertransistoractingasatransconductor.Inour case,tobemoreexact,itreliesonthecharacteristicsofthedifferential transconductanceoftheMIGFETasaresultofalternatingLObiasesat thegivenDCbiasoftheRFsignal,asimpliedby(4.12)andillustratedin

PAGE 109

94 0.05.010.015.020.0 Time (ns) -1.0 0.0 1.0 2.0Input and Output Signals (V) RF = 0.22+0.05sin[2 p( 1.8GHz)] V LO = -0.6 + 0.4squarewave[2 p( 1.6GHz)] V 0.05.010.015.020.0 Time (ns) -0.10 -0.05 0.00 0.05 0.10Output Signal (V) output signal with no filtering down-converted output signal (a) (b)RF = 0.22+0.05sin[2 p( 1.8GHz)] V LO = -0.6 + 0.4squarewave[2 p( 1.6GHz)] Vfiltered through simple LC tankFigure 4.9UFDG-predictedfrequency-modulatedoutputsignalintime domainfrom(a)thesimplemixerusingasingleMIGFETand (b)thedouble-balancedmixer.In(a),thedown-converted outputsignal(IF=fRF-fLO)lteredthroughasimpleLCtank is also shown, as well as the RF and LO signals.

PAGE 110

95 Figure4.8.ThewidertheRFinputsignalrange,inwhichthe characteristicscanbekeptrelativelyconstant(i.e.,withminimalhigherorderderivativeswithrespecttoVRF),thebetterthelinearityofthemixer is.Apparently,thelinearityimpliedinFigure4.8,withVGfS0~0.22V optimizedforconversiongain,sufferswhenthedifferential transconductanceischangingsharplywithVGfSasshowninthefigure. Whereaslinearitycanbeimprovedforshort-channeldevicesinGilberttypemixersbyincreasingthegateoverdrivevoltage,withapenaltyof morepowerconsumption[Li02],doingsoinourMIGFETmixerappears todegradelinearityuntilGcisunacceptablylow.Toimprovethelinear rangeoftheMIGFETmixeratthemaximumconversiongain,wecould lowertheminimumLObiasdownto-1.4V,whichtendstoofferhigher mixerconversiongainduetohigherVGfS0,butmoreimportantlyprovides awiderrangeofRFinputsignalamplitudewithinwhichthemaximum conversiongaincanbeheldrelativelyconstant.Gatework-function engineeringcanbeutilizedforthedesiredLODCbias.Infact,ithasbeen arguedthatminimizinggate-depletioneffectswillimprovethelinearityin short-channeldevices[Cho03],implyingsuperiorityofmetalgatesover the traditional polysilicon gates in this regard. Oneofthemajordrawbacksofthesingle-MIGFETmixeristhe poorLO-RFandLO-IFisolation,withthelatterbeingmoreseriousasis evidentintheFourierresultsinFigure4.10(a)wherethecomponent amplitudesoftheoutputsignalareplottedversusfrequency.Thepoor isolationresultsbecausetheLOsignalistypicallylarge,andeasily

PAGE 111

96 0.0e+001.0e+092.0e+093.0e+094.0e+09 Frequency (Hz) 0.0 0.2 0.4 0.6 0.8 1.0 1.2Normalized Amplitude of Output Signal 0.0e+001.0e+092.0e+093.0e+094.0e+09 Frequency (Hz) 0.0 2.0 4.0 6.0 8.0 10.0 12.0Normalized Amplitude of Output Signal (a) (b)fLO feedthrough fLO fRFfLO + fRFfLO fRFfLO + fRFFigure 4.10UFDG-predictedcomponentamplitudesoftheoutputsignalin thefrequencydomainfor(a)themixerusingasingleMIGFET and(b)thedouble-balancedmixer.Theamplitudesineachplot arenormalizedtotherespectiveamplitudesat200MHz,the primarydown-conversionfrequency.SubstantialLOsignal feedthroughintheoutputin(a)issuppressedbythedoublebalancedmixercongurationin(b),whichfurtheryieldsgood up-conversion as well as down-conversion.

PAGE 112

97 couplesthroughtotheoutputviatheparasiticG-Dcapacitance[Kim06]. Further,themixingitselfwillintroducespurioussignalsatfLO,fRF,2fLO, 2fRF,andahostofotherspectralcomponentsduetothenonidealsquarelaw behavior, as well as unwanted DC components in the output. Alternatively,adouble-balancedmixerconfigurationusingfour MIGFETs(eachwith80fins)canberealizedasshowninFigure4.7(b). HereallfourtransistorsactastransconductorsthatconverttheRFinput totheoutputwhileLOsignalsarefedtothecoupledbackgates.The UFDG/Spice3-predictedfrequency-modulatedoutputsignalofthedoublebalancedMIGFETmixerisreflectedinthetimeandfrequencydomainsin Figures.9(b)and10(b),respectively.Thecircuitfunctionswellatlow supplyvoltage.Theamplitudeofthedown-conversion,200MHz componentoftheoutputsignal,indicatedinFigure4.10(b),isactually~4timesthatofthesingle-MIGFETmixerinFigure4.10(a).Therefore,the (differential-output)conversiongainisimprovedto~4db,butcircuit noise,powerconsumption,andarearequirementare~4-timeshigherthan thoseofthesingle-transistormixer.Thelinearityisimprovedsincethe second-ordernonlinearitiesinthelarge-signaltransferfunctionare cancelledoutwithawell-balancedstructure.Andaboveall,perfectport isolationisobtained,ormoreexactly,theLOfeedthroughiscompletely cancelledoutattheoutputwithawell-balancedstructure,ascanbeseen inFigure4.10(b).However,wealsonotethatprocess-inducedmismatches inthedouble-balancedmixercanstillresultinsomeLOsignal

PAGE 113

98 feedthroughtotheoutput,whichneedstobefilteredoutbyaproperly designed filter at the subsequent stage. 4.4 Conclusion Importantphysicalinsightsregardingdesignandperformanceof independent-gateFinFETsweregainedfromIDS-VGfScharacteristics measuredfromtheMIGFETtechnologyandpredictedbyourprocess/ physics-basedDGMOSFETmodel,UFDG,whichwasupgradedwitha novel2-Dsplineformalism.Inversioncharge-centroidshifting,modulated bygatebiasesaswellasbyquantum-confinementandshort-channel effects,underliesthesensitivityofVttothechangingback-gatebias. Therefore,toachievethedesiredVt(VGbS)distributionforflexibleVtcontrolinlow-powercircuitapplicationswithapracticalVGbSrange,as wellasgoodDCcharacteristics,carefulstructuraldesignoftheMIGFET, includingbackgate-oxidethicknessandgateworkfunction,iscritical. OperationofMIGFETsinthe“synchronizeddrivingmode”isan alternative,betteroptiontoachievingflexibleVtcontrolduetothehigher saturation current and excellent subthreshold characteristics. NovelimplementationofaRFsimplemixeranditsdoublebalancedcounterpartusingMIGFETswasexploredwithUFDGinSpice3. Fortheformer,asmallRFsignalandalargeLOsignalappliedtothetwo gatesofasingleMIGFETyieldmixingviathechargecouplingbetween thegates.Anaccountingofthemixingbasedonthegeneralelectrical characteristicsoftheMIGFET,aswellastheexpectedperformanceofthe mixers,wasstudied.Reasonablygooddesignofthemixerintermsofgood

PAGE 114

99 conversiongainandlinearity,whilestillsatisfyingsmall-size/low-voltage/ low-powerrequirementsforspecificapplications,canbeachievedwith optimumbiasesofthetwogatesandgooddesignofthetransistor.The double-balancedmixerusesfourMIGFETs,andgenerallyoffersbetter conversiongain,linearity,andsuperbportisolationatthecompromiseof largerpowerconsumptionandarea.Sincethesingle-MIGFETmixer wouldneedequallyalargenumberoffin-fingerdevicesforreasonably good gain, it might not be a good option in terms of port isolation.

PAGE 115

100 CHAPTER 5 SRAM CELL DESIGN WITH MIGFET 5.1 Introduction Asweknow,theSRAMmemoryhasbeenconstantlydrivenby therequirementsofhighdensity,andlow-poweroperationatreasonably highspeeds.However,itisbecomingevermorechallengingtominimize thecelltransistorleakagecurrentandprocess-variationeffectsas technologycontinuestoscale.Softerrorsduetoscaled-downvoltageand capacitance,andhardfailsduetoenhancedthresholdvoltagevariationas aresultofrandomdopantfluctuationsinthenanoscalebulkCMOSSRAM cell are posing as potential issues [Fra03]. Withitssuperiorscalability,theFinFEThasemergedasthe leadingcandidatetoreplacebulk-SiandPD/SOICMOS.SRAMdesign basedontheFinFEThasbeeninvestigatedmostrecently[Now02,Guo05]. Unlikethescaledbulk-Sitransistor,whichrequireshighchanneldoping, theFinFETutilizesdouble-gatechargecouplingwithinathinfully depletedfinbodytoyieldexcellentcontrolofshort-channeleffects(SCE), anditistypicallydesignedwithundopedbodyandmidgapgate,which helpsreducethecellleakageaswellaseliminatethresholdvariationsdue torandomdopantfluctuation.Inaddition,itisbuiltonSOIsubstrate, whichhelptoreducesofterrorsduetodecreasedcollectionvolume [Fra03].Further,thesource/drainjunctioncapacitanceoftheFinFETis

PAGE 116

101 negligible,whichrendersthebit-lineload(Cbl)overthelengthofthe entireSRAMarraymainlyinterconnect,therebybenefitingthecellaccess speed.Finally,thelayoutareapercelltendstobeimproved,asthe numerousbodycontactsarenotneeded,andn-welltop-wellspacingis eliminated,whichallowsthenMOSFETandpMOSFETdevicesinthe same cell to share the same drain contact. Inthischapter,anLgate=28nmsix-transistorFinFETSRAMcell isfirstintroduced.ThentheutilityoftheMIGFETsastheaccess transistorsinthecellisexploredforenhancedcellperformance.Insights regardingoptimalcelldesigntradeoffsamongtheread/write/hold stabilities,andtheirsensitivitiestostructuralvariationsintheMIGFETs aregainedwithourUFDGmodel,andthecompromiseoncelllayoutarea and cell speed is also discussed. 5.2 DG FinFET SRAM Cell Performance ImprovingthereadstabilityoftheFinFET-basedSRAMcellis problematicduetothediscretewidthofthefintechnology.Toillustrate theread-stabilityproblemofananoscaleFinFET-basedSRAMcell,weuse UFDGinSpice3,assumingthegatelength,Lgate=28nmforalltransistors equalsthemetallurgical,oreffectivechannellength(Leff).Wefurtherassume agate-oxidethickness(tox,orEOT)of1nm(asprojectedforhigh-performance 28nmCMOSintheSIAITRS[ITRS05]).AllFinFETsaredesignedwith undopedbodieswithacommonmidgapmetalgate.Ultra-thinbodywith thicknessorwidthwSi=14nmischosentoeffectivelysuppressSCEsintheDG FinFETs. The n height is assumed to be 56nm for a typical n aspect ratio.

PAGE 117

102 TheFinFET-based6T-SRAMcellisthenillustratedin Figure5.1, wherethetwogatesofeachtransistoraretiedindouble-gatemode.Here wedefineVDDasthemaximumpowersupplyvoltagefortheentireSRAM arrayaswellastheperipheralcircuits,whereasVCCassupplyvoltageof thecell,whichcanbeloweredfromVDDforimprovedcellstabilityduring thewriteoperations,aswillbedemonstratedlater.Thereadstabilityis quantifiablewiththereadstaticnoisemargin(SNM),whichisdefinedby thesidelengthofthelargestsquarethatcanfitintothebutterflycurves (steady-stateVRvs.VLinFigure5.1)ofthecross-coupledinverterswithin thecell.Toillustrate,weplottheUFDG/Spice3-predictedbutterflycurves ofthecellatVDD=1.0VinFigure5.2,whereasinglefinisassumedfor alltransistors.AnSNMof144mVisobtained;however,foramorereliable readstability,abetterreadSNMwillbedesirable.Process-induced mismatchesorvariations,suchasinwSi,Lgate,gateworkfunction,etc.of eachtransistormaydramaticallydegradethereadSNMinananoscale SRAM cell. ThereadSNMcanbeimprovedbyenhancingthecellpull-down ratio,whichiscorrelatedwiththecellpull-downcapabilityanddefinedby theratioofrelativecurrentstrengthsofpull-downtransistorstothe accesstransistors.Todothis,multiplefinsforthepull-downtransistors and/orlargegatelengthfortheaccesstransistorscanbeused.To illustratewiththeformer,forinstance,weaddtoFigure5.2theUFDG/ Spice3-predictedbutterflycurvesofthecell,whendouble-finsareusedfor thepull-downtransistors.Wetherebyobtainasignificantimprovementin

PAGE 118

103 BLBL WL VCCM1M3 M2M4 M5 M6 VLVR Figure 5.1Schematicofadouble-gateMOSFET-basedSRAMcell. NoteVDDisthemaximumpowersupplyvoltageforthe entireSRAMarrayaswellastheperipheralcircuits; whereasVCCissupplyvoltageofthecell,whichcanbe loweredfromVDDforimprovedcellstabilityduring write.VGb(acc)standsfortheback-gatebiasoftheaccess nMOSFETs(M5andM6),andVGb(p)istheback-gatebias of the load pMOSFETs (M2 and M4).VGb(acc)VGb(acc)VGb(p)VGb(p)VDD = 1V

PAGE 119

104 0.00.20.40.60.81.0 VL (V) 0.0 0.2 0.4 0.6 0.8 1.0VR (V) Single-n FinFET-cell Double-n FinFET-cell Figure 5.2UFDG-predictedbutterflycurvesoftheFinFET-based SRAM cell at VDD = 1.0V.VDD = 1V

PAGE 120

105 SNM,whichnowreaches195mV.However,thisdesignsubstantially sacrificesthelayoutarea,whereasthenotedlatterdesignmodification increasestheWLcapacitanceaswellasnegativelyimpactsthelayout area.Otherwise,mixedfinsurfaceorientation,i.e.,(100)forthepull-down and(110)foraccesstransistors,canbeused,alsoatconsiderablelayout penalty.In[Guo05],thesetradeoffshavebeenquantifiedbasedonstudy ofanLgate=22nmFinFET-basedcell,wherea36%improvementinthe readSNMisachieved(whichiscomparabletotheresultsofourUFDG simulations)byusingdoublefinsforthepull-downtransistors,witha 16.6%areapenalty;anda15%improvementinthereadSNMisobtained byrotatingthefinofthepull-downtransistors,witha13.3%areapenalty. Ontheotherhand,thewritabilityofaconventionalSRAMcellis generallylessofaconcern,asthepull-upstrengthofthepMOSFETload istypicallysizedlessthanthepull-downstrengthoftheaccesstransistor. ThewritabilitycanbesimulatedbyholdingthewordlineatVDD=1.0V whilerampingasinglebitline;thecorrespondinginternalnodewithinthe cellisthenpredicted,therebydefiningthewrite’(or’)marginasthe maximum(minimum)bit-linevoltagethatwritesa’(or’).Forthe FinFET-basedSRAMcell,weillustratethewritabilityinFigure5.3, where‘write’resultsofbothsingle-finanddouble-finsforthepull-down transistorsaresimulated.Thewritemarginsofbothareexcellent.The formerhasawrite-0marginof~400mV,whereasthelatterhaslesswrite0margin,becauseofthereducedtrippointofthecross-coupledinverters. Notethesimulatedhysteresiswindowforthelatteriswidenedcompared

PAGE 121

106 Single-n FinFET-cell Double-n FinFET-cell write ’write ’Figure 5.3UFDG-predictedwrite’andwrite’curvesofthe FinFET-based SRAM cell. 0.00.20.40.60.81.0 VBL (V) 0.0 0.2 0.4 0.6 0.8 1.0VR (V)

PAGE 122

107 tothatoftheformer,whichactuallyimpliesabettercellstabilityand immunity to disturbance during read. 5.3 Use of MIGFET for Access Transistors Inthissection,wearegoingtoexploreanotherstrategyto achieveimprovedreadstability,i.e.,usingthedouble-gatemode(i.e., FinFET)forthepull-downtransistorandthesingle-gatemode(i.e., MIGFET)fortheaccesstransistorbyproperlybiasingthebackgate.The backgatecanbeeitherstaticallybiasedforanoptimizedcellratio,or connectedtothecellstoragenodestoprovidedynamicadjustmentofthe cellratio.Infact,thelatteroptionhasbeenexaminedin[Guo05]withthe Lgate=22nmFinFET-basedcell.However,wewillexaminethelatter approachmorecloselywithourUFDGmodel,whichwillleadtoourmain focusontheformerapproachtoimprovingthecellperformance.The feasibilityandtradeoffsofthedesignwithregardtoproperback-gate biasingforoptimalcellstabilitywillbeexplored,anddesignissues regarding layout area and cell speed will also be addressed. 5.3.1 MIGFET I on /I off and Its V GbS Dependence. TotestthisnewconceptofimprovingFinFET-basedSRAM performanceinnanoscaleregime,wefirstlyexaminethecurrentdrive capabilitiesoftheLgate=28nmFinFEToperatedinthedouble-gateand single-gatemodes,whichwillreflectthecellratiooftheSRAMcelltobe studied.Furthermore,forarobustcellwithminimizedpenaltyinstatic powerconsumption,wealsomonitortheoff-stateleakagecurrentofeach transistormodeforvariousbiasingconditions.TheUFDG-predictedIon

PAGE 123

108 andIoffwithvaryingback-gatebiasofthenMIGFETfrom-0.6Vto0.6V aresummarizedinFigure5.4andFigure5.5,respectively,alongwith those of the FinFET operated in double-gate mode. ThecurrentdrivecapabilityoftheFinFETinthedouble-gate modeismuchbetterthanthatinsingle-gatemodeforthegivenVGbSrange,whichwouldimplyapotentiallystrongcellratiooftheSRAMcell. NoteIonismuchlesssignificantlymodulatedthanIoffwithvaryingVGbS, duetothescreening-outofthechargecouplingbyinversioncarriersin stronginversion.Nevertheless,withVGbS>0V,thecellratiocanstillbe flexiblyreduced;whereasIoffwillbesacrificedconsiderablycomparedto thatofthenFinFET.NotethatbiasingbeyondVGbS=0.5Vwouldnotbe adesirableconditionfortheaccesstransistorsintheSRAMcell,asthe Ion/Ioffratioisreducedto~100,meaningthatbit-lineprechargedvoltages canbeeffectivelypulleddownbyexcessivesubthresholdleakagecurrent fromaccesstransistorsoftheentireSRAMarrayatthe‘off’condition. Thisresultsinlessbit-linedrop-down,andthereforelessdifferential signalthanexpectedforthesenseamplifierduring‘read’;further,itleads toincreasedstaticpower.ForVGbS<0V,however,thecurrentdrivewill besignificantlyreduced,raisingmoreconcernforreadspeedand writabilityoftheSRAMcell.Furthermore,itisnotcommontogeneratea negative bias in digital logic circuits. Infact,becauseofthemuchweakeneddrivecurrentoftheaccess transistorsinthesingle-gatemode,comparedtothedouble-gatemode,the pull-uppMOSFETofthecross-coupledinvertersmustalsobeweak

PAGE 124

109 pMIGFET nMIGFET nFinFET pFinFET Ion ( m A/pitch) -0.6-0.4-0.20.00.20.40.6 VGbS (V) 0 10 20 30 40 50 60 Figure 5.4UFDG-predictedIonwithvaryingVGbSofthenMIGFET from-0.6Vto0.6V,alongwiththosewhenthetransistor is operated in double-gate mode.VDS = 1V

PAGE 125

110 -0.6-0.4-0.20.00.20.40.6 VGbS (V) 10-1510-1410-1310-1210-1110-1010-910-810-710-6Ioff (A/pitch) pMIGFET nMIGFET nFinFET pFinFET Figure 5.5UFDG-predictedIoffwithvaryingVGbSofthenMIGFET from-0.6Vto0.6V,alongwiththosewhenthetransistor is operated in double-gate mode.VDS = 1V

PAGE 126

111 enoughtoensureproperwritability,whichsuggeststhepossibleuseofthe single-gatemodeforthepMOSFETsintheSRAMcelltoo.Therefore,we alsoaddtheUFDG-predictedIonandIoffwithvaryingback-gatebiasfrom -0.6Vto0.6VforthepMIGFETtoFigure5.4andFigure5.5,alongwith thoseofthedouble-gatemodepFinFET.Arelativecomparisonofthe pMOSFETcurrentdrivewiththatofthenMOSFETindicatestheneedto carefullychoosetheVGbSbiasforthepull-uppMIGFET,relativetothat of the access nFinFETs. ThepeculiarhumpnearVGfS=VGbSinFigure5.5arereal, althoughperhapsexaggerated.Theyareassociatedwiththetransversefielddependenceofthequantizationeffectintheweakinversionregion [Tri05b]. 5.3.2 Dynamic Gb Bias Design and its Leakage Problem. In[Guo05],dynamicback-gatebiasingoftheaccesstransistors toimprovethereadSNMwithnocompromiseonthecelllayoutareawas examined.Inthisdesign,theback-gatesoftheaccesstransistorsare connectedtothecorrespondingstoragenodes,sothatstrengthofthe accesstransistorwithback-gateconnectedtothe’storagenodeis effectivelyweakenedduringread.A77%readmarginimprovementwas achieved,thoughthewritestabilitywasseverelydegradedasaresultof weakenedaccesstransistors.However,a‘column-baseddynamicpower switching’schemewasproposedmostrecently[Zha05],aswasutilizedin [Guo05]toimprovethewritestabilitygreatly.There,thewritingtothe cellismadeeasierbyselectivelyloweringthecellsupplyvoltageVCC

PAGE 127

112 alongthecolumnthatcontainsthecellviaadynamiccontrolcircuit.As theWLturn-onvoltageissustained,itisthenpossibletoachievegood writemarginwithoutcompromisingtheSNMduringread.TheholdSNM, whichisameasureofcellstabilityinthestandbymode,ofothercells connectedtothesamebitlinesis,however,degradedwithdecreasingcell voltage.Therefore,adesigntradeoffcanbemadebyappropriateVCClowering. Despiteboththeexcellentread/writemarginsoftheSRAMcell achievedwhencombinedwiththecolumn-basedcellsupply-voltage loweringschemeasin[Guo05],aconcernarisesaboutthepossibleserious staticleakageproblemassociatedwiththedynamicbiasingoftheaccess transistors,whichtheauthorsdidnotseemtopointout.Itoccurswhen thecellsareinstandbymode,andthebitlinesareeffectivelypulledup/ downlessthanVDD,whichresultsintheaccesstransistorswithbackgatesconnectedtothe’storagenodepartiallyorfullyturnedondueto thepositiveVGbS=VDS;substantialleakagefromtheentirecolumncells ontothebitlinesisthuslikely.CarefuldesignoftheSRAMoperation sequences,i.e.,makingsurethebitlinesarestaticallyheldat(or prechargedto)VDDatalltimesexceptforread/writeoperations,iscrucial. Further,thebit-linepull-downvoltagefromVDDduringareadoperation hastobeminimal.However,whenoneofthebitlinesispulleddownto groundduringwrite,therewillbealargeamountoftransientleakage.In fact,UFDGpredictsthatfortheLgate=28nmMIGFETdesignwith midgapgateandwhenVGbS=VDD=1V,theoff-statecurrentisonlya

PAGE 128

113 factorof~2lowerthantheon-statecurrent,whichimpliesthetransient leakagefromtheentirecolumnontothebitlinewouldbesignificantly largerthanthewritecurrent.Further,thecellholdSNMisdegradedas a result. However,whendynamiccellsupplyvoltageloweringisutilized duringwrite,theamountofleakagedecreasesduetothereducedVGbS= VDSaswellaslessDIBL.Tofindouthowmuchgainweachievewiththis scheme,wesummarizetheUFDG/Spice3-predictedwrite/holdmargins, alongwiththeamountofcurrentleakingfromtheaccesstransistorper cellfortheLgate=28nmback-gateddesign,fordecreasingcellvoltage downto0.4VinFigure5.6.Notetheholdmarginsaresimulatedto emulatethecellsinstandbymode,whenoneofthebitlinesispulleddown togroundtowritetoasinglecellinthesamecolumn.Indeed,witha positivevoltagedifferenceof,forexample,0.4VbetweentheWLandthe cellsupplyvoltage,i.e.,VCC=0.6V,thewritemargincanbefurther enhancedbyafactorof~2,whereastheholdmarginsofothercellsin standbymodeconnectedtothesamebitlinesarereducedto218mV. Further,theleakageproblemoftheaccesstransistorsisalleviatedby approximatelytwoordersofmagnitudepercell.ForVCCreducedfurther to0.4V,theleakagecurrentfromtheaccesstransistorcanbeeven reducedto~10nApercell;however,theholdmarginalsodropsdown below150mV.Therefore,adesigncompromisehastobeachievedbetween thedegradingholdSNMandtheinherentleakageproblemvia appropriate VCC lowering.

PAGE 129

114 hold margin write margin Ioff(ac) 0.400.500.600.700.800.901.00 100.0 150.0 200.0 250.0 300.0 350.0 400.0write/hold margin (mV) 0.400.600.80 VCC (V) 10-910-810-710-610-510-4Ioff(ac) (A/pitch) Figure 5.6UFDG-predictedwrite/holdmargins,alongwiththe amountofcurrentleakingfromtheaccesstransistorper cell for the Lgate = 28nm MIGFET-cell.VDD = 1V

PAGE 130

115 Onewaytofurtheramelioratetheleakageproblemcouldbeto applynegativeWLvoltagetothecellsinthestandbymodetoreducethe subthresholdleakage.However,itisnoteffectiveunlessthedynamiccell supply-voltageloweringschemeisutilized,asstrong-inversioncharge inducedbylargepositiveVGbSisalreadyscreeningouttheVGfSeffect. Negativesubstratebiascouldbeappliedsimultaneouslyforthecellsin thestandbymode,buttheburiedoxidelayerhastoberelativethinto effectivelyreducetheleakagefurther.Usingmuchhighergatework functionthanmidgapforalltransistorswillalsoreducetheleakage. However,thecurrentdriveofeachtransistoralsodecreases,which degradestheaccessspeedofthecell;also,thewritemarginisreduced more due to its sensitivity to current drive in the access transistors. 5.3.3 Static Gb Bias Design Here,westudyanotherback-gateddesignforimprovedread SNM,thatis,staticallybiasingtheaccesstransistorsinsingle-gatemode. Forconvenience,wedefineVGb(acc)astheback-gatebiasoftheaccess nMOSFETs(M5andM6),andVGb(p)astheback-gatebiasoftheload pMOSFETs(M2andM4),asnotedinFigure5.1.Asaresult,theleakage fromtheaccesstransistorcanbeeffectivelycontrolledwithproper selectionofVGb.Agoodwritability,however,willnotnecessarilybe guaranteedasaresultofweakenedaccesstransistors.Toimproveit,the useofsingle-gatemodeforthepull-uptransistorintheSRAMcellmight help,asthepMOSFETpull-uphastobeweakerthanthatoftheaccess transistorinordertowritea’tothecell.Anylayoutareapenaltydueto

PAGE 131

116 theneedfortheadditionalcontactswillbeinvestigated,andhopefully minimized.Analternativetoenhancingthewritemarginbasedonthe ‘column-baseddynamicpowersupply’schemewillalsobeutilizedforthis staticback-gateddesign.Finally,wediscusssomeinsightsgainedabout the impact of using MIGFETs on the access speed during read. a) VGb Varying for the Access nMIGFETs WesimulatewithUFDGthewritabilityaswellasreadSNMof theSRAMcellforavarietyofbiasingconditions.Initially,weletboththe pull-downnFinFETsandthepull-uppFinFETsbeindouble-gatemode andvaryVGboftheaccessnMIGFETsinsingle-gatemode.Toillustrate itseffectonthereadSNM,theUFDG/Spice3-predictedbutterflycurves withincreasingVGb(acc)areplottedinFigure5.7,alongwiththoseofthe single-finFinFET-basedcellforcomparison.Notebychangingthe strengthoftheaccesstransistor,theoutputsofthebutterflycurvesare eachpulleddowntoadifferentmarginfrom0V,whentheinputreaches VDD.Thesimulatedread/writemarginsarethensummarizedinFigure 5.8,whereVGb(acc)isbiasedupto0.5V.Asexpected,significantSNM enhancementisachievedforallVGbduetothemuchstrongerpull-down capabilityofthecelloverthatofthesingle-finFinFET-basedcell;with increasingVGbthough,theSNMslowlydecreasesastheaccesstransistor strengthens.WhereasthewritemarginisnotevenwritableatVGb=0V, itsteadilyimprovesuntilitreaches @ 160mVatVGb=0.5V.NoteforVGbbeyond0.5V,asshowninFigure5.5,theleakagefromonesingleaccess

PAGE 132

117 FinFET-cell MIGFET-cell w/ VGb(acc) = 0, 0.2, 0.4VFigure 5.7UFDG-predictedbutterflycurveswithvarying VGb(acc),alongwiththoseofthesingle-finFinFETbased cell.VDD = 1V 0.00.20.40.60.81.0 VL (V) 0.0 0.2 0.4 0.6 0.8 1.0VR (V)

PAGE 133

118 write margin of the MIGFET-cell read SNM of the MIGFET-cell read SNM of the FinFET-cell 0.000.100.200.300.400.50 VGb(acc) (V) 0.0 50.0 100.0 150.0 200.0 250.0 300.0read SNM/write margin (mV) Figure 5.8UFDG-predictedreadSNMandwritemarginvs.VGb(acc). Forcomparison,thereadSNMoftheFinFET-basedSRAM cell is also indicated.VDD = 1.0V

PAGE 134

119 transistorwillbemuchmorethan100nA,whenVDSoftheaccess transistor reaches 1V, which would not be a desirable condition. b) VGb Varying for the Load pMIGFETs Next,toseeifwecanimprovethewritemarginoftheback-gated designotherwise,weexploreanotheroption:lettheback-gateofthe accesstransistorsbegrounded,andtrybiasingthepull-uppMOSFETsin single-gatemodewithvaryingVGb(p).Noteforpracticalreasons,welimit theadditionalsupplyvoltageforback-gatebiasingtoone.Firsttheback gatesofpMOSFETsareconnectedtoVDD,i.e.,VGbS(p)=0V.Wethencheck thewritabilityofthecell.Indeed,thecellisnotwritablewithbackgateof accesstransistorsgrounded,unlessthepMOSFETpull-uptransistorsare alsobiasedinsingle-gatemodetoberelativelyweakerthantheaccess transistors.Nevertheless,thewrite’didnotoccuruntilthebitlineis stronglypulleddown,leavingonlyamarginof @ 150mV,whichismuch smallerthanthat( @ 400mV)obtainedfortheFinFET-basedSRAMcell,as notedintheSectionI.Evidently,aweakenedaccesstransistorhasexerted muchstrongernegativeimpactonthewritemargin.Althoughthewrite margincanbeenhancedwithweakenedpMOSFETpull-up,thereduced trippointsofthecross-coupledinvertersasaresulttendstoundermine the enhancement. Withtheabovebiasingconditions,wethenexaminetheread SNMofthecell.TheUFDG/Spice3-predictedbutterflyplotofthecellat VDD=1.0VisshowninFigure5.9.Forcomparison,wealsoshowinthe samefigurethebutterflyplotspredictedwhenallFinFETsarebiasedin

PAGE 135

120 0.00.20.40.60.81.0 VL (V) 0.0 0.2 0.4 0.6 0.8 1.0VR (V) MIGFET-cell w/ VGb(acc) = 0 V FinFET-cell and VGb(p) = 1 V Figure 5.9UFDG-predictedbutterflycurvesoftheMIGFET-cellat VDD=1.0V,whentheback-gatesoftheaccesstransistors andofthepMOSFETsaregroundedandconnectedto VDD, respectively, along with those of the FinFET-cell.VDD = 1.0V

PAGE 136

121 double-gatemode.Despitethemuchstrongerpull-downcapabilityofthe cell,theSNMhasbeenimprovedmodestly(by @ 25mV).Evidently,the SNMimprovementofthecellhasbeenseverelylimitedbythereducedtrip pointsofthecross-coupledinverters,duetothesignificantlyweakened pMOSFET current drive capability. Thetrippointofthecross-coupledinverterscanactuallybe relaxedbybiasingtheback-gateofthepull-uppMOSFETsbelowVDDfor morestrength,which,however,compromisesthestaticpowerofthecell duetotheenhancedsubthresholdleakageinthepMOSFETs.TheUFDGpredictedreadSNM’sandwritemarginswithchangingVGb(p)are summarizedinFigure5.10.NotewithdecreasingbiasofthepMOSFET backgatesdownto0.5V,thepMOSFETIonincreasesatasteadyrate showninFigure5.4,andtherebyrelaxingthetrippointofthecrosscoupledinverters.TheSNMsteadilyclimbsupto246mV,closingontothat obtainedwhenpMOSFETsarebiasedindouble-gatemode.However,the writemarginsaredegradeddownto~100mVwhenVGb(p)isdownto0.6V, andanuptotwoordersofmagnitudesubthresholdleakageinpMOSFETs issacrificed,asindicatedinFigure5.5.Anoptimalbiasrangeof0.7Vto 0.9VforthepMOSFETbackgateswouldleadtoa48%SNMimprovement, andwellabove100mVwritemarginaswellasnomorethananorderof magnitude leakage increase per cell. c) Column-Based Dynamic Power Switching Scheme Aswehavefoundout,relaxingthepull-upratiobypositivebackgatebiasingofeithertheaccesstransistorand/ortheloadtransistorsin

PAGE 137

122 0.500.600.700.800.901.00 VGb(p) (V) 50.0 100.0 150.0 200.0 250.0SNM/write margins (mV) read SNM of MIGFET-cell write margin of MIGFET-cell read SNM of FinFET-cell Figure 5.10UFDG-predictedreadSNMandwritemarginofthe MIGFET-cellvs.VGbofpMOSFETs,whenthebackgatesoftheaccesstransistorsaregrounded.For comparison,thereadSNMoftheFinFET-basedSRAMcell is also indicated.VDD = 1V

PAGE 138

123 single-gatemodehelpstoimprovethewritemarginofthecell,limitedby considerationforimprovementofreadSNMandcellleakage.However, morewritemarginwouldbedesiredforreliablewrite.Obviously,the column-baseddynamicpowerswitchingschemewouldbeabetter alternativetoovercometheinherentlylowwritemarginoftheback-gated celldesign.Figure5.11summarizestheUFDG/Spice3-predictedwrite/ holdmarginsversusdecreasingcellsupplyvoltageofthecellwhenthe back-gateoftheaccesstransistorsisgrounded,whereasleavingthe pMOSFETsindouble-gatemode.Evidently,abetterdesigntradeoff betweenthecellhold-andwrite-marginscanbemadebasedonthis scheme,ascomparedtothatbetweenread-andwrite-marginswiththe pull-uppMOSFETsbiasedinsingle-gatemode.AtVCCnear~0.55V,a goodwritemargin( @ 210mV)isachievedwithoutsignificantlysacrificing the hold margin ( @ 210mV). Infact,ifweallowthebackgateoftheaccesstransistorstobe somewhatpositivelybiased,significantlybetterwritemargincanbe achievedwithproperVCCloweringduringwrite,andlittleimpactonthe holdSNM.WeaddtoFigure5.11thesimulatedwritemarginwhen VGb(acc)=0.3V,andVCCisloweredto0.6V.A @ 310mVwritemarginis obtainedwhentheholdmarginis @ 230mV.Mostimportantly,theread SNMismaintainedatanexcellent249mV.Ontheotherhand,ifweletthe backgateoftheaccesstransistorsbegrounded,butallowbiasingthe pMOSFETsinsingle-gatemodewithVGb(p)=VCC=0.8V,forexample, duringwrite,thena261mVwritemarginisobtainedwhenboththehold

PAGE 139

124 0.400.500.600.700.800.90 VCC (V) 0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0Hold/write margin (mV) MIGFET-cell hold margin MIGFET-cell write margin (a) Figure 5.11UFDG-predictedwrite/holdmarginsvs.cellsupplyvoltage loweringoftheMIGFET-cellduringwriteoperationofa singlecell,when(a)VGb(acc)=0V,andpMOSFETsin double-gatemode.(b)VGb(acc)=0.3V,andpMOSFETsin double-gate mode. (c) VGb(acc) =0V, and VGb(p) = VCC.VDD = 1V (b) (c)

PAGE 140

125 SNMandreadmarginare @ 200mV.Indeed,staticback-gatebiasingofthe cellcanprovideanexcellentcellperformancewitheasierdesigntradeoff when dynamic power supply switching is used as well. Notethedynamicswitchingofthecellsupplyvoltagealsoallows substantialleakagepowerreductioninstandbymodeduetoreduced DIBL,whichrenderstheadditionalactivepowerassociatedwithdynamic switchingofVCCandwiththeaddedperipheralcircuitsforVCCcontrol andtimingnegligible.Further,theadditionaloverheadinareaandin accesstimeinlargeSRAMarraysoperatedathighfrequencyshouldbe minimal. 5.4 Structural Sensitivities of the Cell Wearealsoconcernedaboutthestructuralsensitivitiesofthe SRAMcellperformance,thatis,read/writestabilityaswellasstatic leakagepowerofthecell,totheprocess-inducedvariationsofthescaled MIGFETtechnology,ascomparedtotheFinFETtechnology.Tofindout, wefirstexaminethedeviceperformancesensitivitiesofbothtechnologies totheprocess-inducedvariationswithourUFDGmodel.WithtSivaried by10%,IonandIoffofthenMIGFETwithVGbS=0aswellaswithVGbS=0.3V,andofthepMIGFETwithVGb=0.8V,aresummarizedinFigure 5.12andFigure5.13,respectively.Forcomparison,IonandIoffofthe FinFETsindouble-gatemodewiththesametSivariationarealsoadded tobothplots.InFigure5.12,IoffofthenMIGFETwithVGbS=0V,which isidenticaltothatofnFinFET,changesbyroughlyhalfanorderof magnitude,subjectto10%tSivariation.WhenVGbSisraisedto0.3V,Ioff

PAGE 141

126 -10.0-5.00.05.010.0 tSi% 10-1010-910-810-7Ioff(A/pitch) -10.0-5.00.05.010.0 20 25 30 35 40 45 50 55 60 Ion ( m A/pitch) nMIGFET with VGb = 0 V nFinFET nMIGFET with VGb = 0.3V Figure 5.12UFDG-predictedIonandIoffofthenMIGFETwithVGbS=0aswellaswithVGbS=0.3V,alongwiththoseofthe nFinFET, versus tSi variation.

PAGE 142

127Ion ( m A/pitch) -10.0-5.00.05.010.0 10-1110-1010-910-8Ioff(A/pitch) -10.0-5.00.05.010.0 tSi% 10 15 20 25 30 35 40 pMIGFET with VGbS = -0.2 V pFinFET Figure 5.13UFDG/Spice3-predictedIonandIoffofthepMIGFETwith VGbS=-0.2V,i.e.,VGb=0.8V,alongwiththoseofthe pFinFET, versus tSi variation.

PAGE 143

128 risesupbyapproximatelyanorderofmagnitude,withtSisensitivity almostunchanged.Ontheotherhand,Ion’softhenMIGFETwithVGbS= 0VandVGbS=0.3Varerespectively~50%and~30%lowerthanthatofthe nFinFET.WhereasIonofthenFinFETisbarelysensitivetotSivariation, IonofthenMIGFETschangeswithtSi,thoughslightly.Noteeveninthe worst-casewhenVGbS=0.3V,and10%highertSiiseffected,amorethan threeordersofmagnitudeofIon/Ioffratioisretained,whichshould guaranteethenormalfunctionalityoftheSRAMcell,providedthenumber of cells per column is kept low. ForthepMOSFETsshowninFigure5.13,bothIonandIoffare degradedwhenbiasedinsingle-gatemode.However,roughlythesame amountofvariationswithtSiasthosewhenbiasedindouble-gatemodeis observed. ToexaminethesensitivitiesofthereadSNMandwritemargin tostructuralvariationsintheMIGFETs,i.e.,theaccesstransistorsbiased insingle-gatemode,weletVGb(acc)=0.3VandassumeadynamicVCCloweringto0.6Vforwrite.Withthesame10%tSivariationinboththe accesstransistors,weplottheUFDG-predictedbutterflycurvesinFigure 5.14.Asreflectedbytheshiftedpull-downvoltageinthebutterflycurves, theSNMisslightlysensitivetotSivariation.Contrarytotheoptimization ofSNMinabulk-SiSRAM,whereweneedtodesign‘highVt’foraccess transistorsviaaheavydopingconcentration[See87],hereintheFinFET/ MIGFET-basedSRAM,the‘lowerVt’orhighersubthresholdleakagedue todegradedSCE’sdonotnecessarilycontributetotheSNMdecrease.A

PAGE 144

129 w/o variations w/ 10% tSi variations w/ 50mV FGate variations 0.00.20.40.60.81.0 VL (V) 0.0 0.2 0.4 0.6 0.8 1.0VR (V) Figure 5.14UFDG-predictedbutterflycurveswith10%tSivariations inboththeaccesstransistors,andwith50mVvariations in the gate work function from midgap.

PAGE 145

130 10%increaseintSiincreasesthesubthresholdleakageconsiderably,but onlyslightlymodifiesthecurrentdriveoftheaccesstransistorsatVGfS= VDD,whichactuallycorrespondstowhenthewordlineisturnedonduring read/write in an SRAM cell. Tosummarize,weplotinFigure5.15bothreadSNMandwrite marginversus10%variationsinLgateaswellasintSioftheaccess transistorsinthedesignedSRAMcell.Notelessthan3%degradationof SNMisinduced,andamaximum6%reductioninthewritemarginoccurs, whicharewelltolerablefor10%structuralvariationsintheaccess MIGFET.Evidently,process-inducedmismatchesorstructural asymmetryintheMIGFETsoftheSRAMcellwillnotbeproblematicin termsofeitherreadorwritestability,giventhatsubstantialreadSNMs and write margins are obtained. WefurtherexaminethesensitivityoftheSNMtothework functionofthemetalgateusedinthetechnology.Previously,anideal midgapmetalgatehasbeenassumedforalltransistorsintheSRAMcell, whichtendstoyieldarelativelyhighVt,andthereforelowoff-state leakageaswellasreducedcurrentdrive.Inrealdevices,thegatework functionofthegatecouldbeabithigherorlower,dependingonthe technology.Forassumedgatework-functionvariationinalltransistorsof 50mV,theUFDG-predictedbutterflycurvesareaddedtoFigure5.14. Notewith50mVdecreaseingateworkfunction,IoffofthenMIGFET degradesbyafactorofabout4,whichisstilltolerable(<100nA);theread SNMisdegradedwithdecreasinggateworkfunctionduetothereduced

PAGE 146

131 Read SNM with tSi variation Read SNM with Lgate variation Write margin with tSi variation Write margin with Lgate variation -10.0-5.00.05.010.0 Dimensional variation% 200.0 250.0 300.0 350.0Read SNM/Write margins (mV) Figure 5.15UFDG-predictedreadSNMandwritemarginversus10% variationsinLgateaswellasintSioftheaccesstransistors. NoteadynamicVCCloweringto0.6Visassumedduring write.

PAGE 147

132 trip-pointofthecross-coupledinvertersandtheweakenedpull-down capabilityattheoutputwhentheinputreachesVDD,wherethelatter impliesstrongerimpactofhighergateoverdriveonthedrivecurrentin the MIGFET than in the FinFET. TheSNMvariationoftheback-gatedcell,alongwiththatofthe FinFET-cellisthensummarizedinFigure5.16.NotetherelativeSNM enhancementoftheformeroverthelatterismaintained,astheread SNMsofbothcellsdropataboutthesameratewithdecreasinggatework function.Foranoverallpictureofthecellperformance,wealsoaddthe writemarginaswellastheholdmarginvariationtoFigure5.16,where VCC=0.6Visassumed.Thewritemargindropssubstantivelywith increasinggateworkfunction,asthecurrentdriveoftheaccessMIGFETs weakensandthatofthepMOSFETsstrengthens.Nevertheless,agood writemargin( @ 230mV)maintainswhenthegateworkfunctionis50mV higherthanmidgap.Noteforthegateworkfunctionlowerthanmidgap, thewritemarginbecomesmoresignificant,whichwouldevenallow redesignofthecellbyrelaxingVGbtoasmallervalueforbetterdesign tradeoff,whichaccentuatestheadvantageoftheback-gateddesignin improvingtheoverallcellperformancewhengateworkfunctionofthe technologyislowerthanthemidgap.Notethesameadvantageapplies whendualmetalgatesareusedfortheSRAMcell,asboththewrite marginandthereadSNMaremostsensitivetothecurrentdriveinthe access transistor.

PAGE 148

133 read SNM of MIGFET-cell read SNM of FinFET-cell write margin of MIGFET-cell hold SNM of MIGFET-cell 4.554.604.65 Gate work function (V) 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 450.0Read SNM/write/hold margins (mV) Figure 5.16UFDG-predictedreadSNM/writemargin/holdSNM variationsoftheMIGFET-cellversusgateworkfunctionof theSRAMcell.Forcomparison,thereadSNMversusgate workfunctionoftheFinFET-cellisalsoindicated.Notea dynamic VCC lowering to 0.6V is assumed during write.

PAGE 149

134 5.5 SRAM Cell Layout TheSRAMcelllayoutdesignhasbeencrucialtoachievehigh densitymemoryaswellasreliablemanufacturabilitywithregardto scaling.Oneofthelayoutdesigntypes,whichallowsforprecisedevicedimensioncontrol(straightpolylinescrossingstraightactivelines),was usedin[Guo05]tostudynanoscale(Lgate=22nm)FinFET-basedSRAM cell;thelayoutwasgeneratedusingalinearlyscaledversionof90nmnode logicdesignrules.Itwastherebyshownin[Guo05]that13.3%and16.6% areapenaltiesresultfromrotatingthefin(forhigherelectronmobility along(100)channelsurface)andusingdoublefins,respectively,forthe pull-downtransistors.Tomakeastraightforwardcomparisonwiththose areapenaltiesasnoted,weusethesame‘linearlyscaledversion’ofthe 90nmdesignrule,asmarkedin[Guo05]forlayingoutourLgate=28nm MIGFET/FinFET-based SRAM cell. Forreference,weshowthelayoutoftheFinFET-basedSRAM cellinFigure5.17.Thecelllayoutareaiscalculatedas0.76x0.475= 0.36 m m2.Thelayoutsoftheback-gatedcellwithpMOSFETsbiasedin double-gatemodeandinsingle-gatemodearethenshowninFigure5.18 andFigure5.19,respectively.Duetotheadditionalcontactsneededfor thebackgatesoftheaccesstransistors,thereisa13%areapenaltyfor bothcases.Notetheadditionalcontactsneededforthebackgatesofthe pMOSFETswhenbiasedinsingle-gatemodedonotincurareapenalty,as shown in Figure 5.19.

PAGE 150

135 475 nm760nm 80 50 50 50 50 25 70 20 60 25 10 ACCESS LOAD NPDFigure 5.17LayoutoftheFinFET-cell,wherea‘linearlyscaled version’ of the 90nm design rule is used.

PAGE 151

136 Figure 5.18LayoutoftheMIGFET-cell,whereonlytheaccess transistorsarebiasedinsingle-gatemode.Thesame designruleasinFigure5.17isused.Notethepolyontop oftheaccesstransistorisetchedawaytoconvertfromthe FinFETs into MIGFETs 475 nm860nm etched away ACCESS LOAD NPD

PAGE 152

137 Figure 5.19LayoutoftheMIGFET-cell,whereboththeaccess transistorsandloadtransistorsarebiasedinsingle-gate mode.ThesamedesignruleasinFigure5.17isused.Note thepolyontopoftheaccesstransistorisetchedawayto convert from the FinFETs into MIGFETs 475 nm860nm etched away ACCESS LOAD NPD

PAGE 153

138 5.6 SRAM Cell Access Speed Ashasbeennoted,theweakenedaccesstransistorswill compromisetheSRAMdelay.Toanalyzeit,weexpressthemajortwo components of SRAM delay as ;(5.1) thatis,word-linedriverdelay( tWL)andbit-linedelay( tBL),respectively. Theformercomprisestheinverterdelaytodirectlydrivetheword-line capacitance(Cwl),andthedelayofcascadedinverterchainontheword line( twl-drivers),whereasthelatteristhetimerequiredforthedifferential voltage( D Vsense)detectablebythesenseamplifiertodevelopbetweenthe bitlines.In(5.1),Ion-driverandIon-cellarecurrentsthroughtheword-line driverinverterandthecellpull-downcurrentthroughM5(orM6)and M1(or M3) during access, respectively. AsindicatedinFigure5.4,Ion-cellhasbeendegradedbyafactor ofasmuchas1.5withVGb(acc)=0.3V,comparedtowhentheyarebiased inthedouble-gatemode.Ontheotherhand,wealsonotethatsinceCwlcomesfromtheaccesstransistors(Cwl-acc)alongtheentireSRAMrow,as wellasinterconnect(Cwl-int),weactuallyreduceCwl-accviabiasingthe accesstransistorsinsingle-gatemode.TheamountofCwl-accreductionis illustratedinFigure5.20,wheretheC-Vcharacteristicsoftheaccess transistorsbiasedinsingle-gatemodeandindouble-gatemodeoverthe operatingvoltagerangeofthecellarecomparedvia2Dnumerical t SRAM t wldrivers – C wl V DD I ondriver – ------------------------------+ WL C bl V sense D I oncell – ------------------------------BL +=

PAGE 154

139 0.00.20.40.60.81.0 VGS (V) 0.0 0.5 1.0 1.5 2.0CG (fF/ m m) FinFET MIGFETFigure 5.20Medici-predictedC-Vcharacteristicsoftheaccess transistorsbiasedinsingle-gatemodeandindouble-gate mode over the operating voltage range of the cell.VDS= 50mV 42% lower 50% lower

PAGE 155

140 simulations.Agateelectrodethicknessthatiscomparabletothegate lengthwasassumedforthesimulations.Asmuchasafactorof~2 reductionofgatecapacitanceispredictedforthehighergate-biasregion. Noteevenforthelower-VGSregionwhenparasiticcapacitancesdominate, a42%-lowercapacitanceispredictedfortheformerthanforthelatter, whichimpliesthatthefinitebodycapacitancewhenbiasedinsingle-gate modeissignificantlysmallerthanthecombinedinnerandoutergatefringecapacitances.Furthermore,theFinFET/MIGFET-basedSRAMhas theinherentspeedadvantageasCblhasbeensignificantlyreducedto mainlyinterconnectcapacitance.Therefore,theoverallSRAMspeed shouldbebetterthantheSRAMcellbasedonbulk-Sitechnology.Infact, sincescaledSRAMcellsareoftendesignedwithhigh-Vttransistors,ithas beenshownthatread-delaydegradationassociatedwiththeuseofhighVtnMOSFETtransistors(relativetoallnominalVttransistors)isnot significant[Jos04].OnereasonisobviouslythattheoverallSRAMaccess delayisalsomoreorlesscontributedbytheword-linedelay,asindicated in (5.1). Inourcase,however,thesingle-gatemodeoperationofthe accesstransistorshasconsiderablyreducedIon-cell.Ifweassume tWLand tBLarecomparablein(5.1)forFinFET-basedSRAMcell,whichisa reasonableassumption[Ana04],wecanmakeaquickbutrough estimationontheread-delaydegradationrelativetotheFinFET-based SRAMcell.AsimpliedforVGbS=0.3VinFigure5.4, tBLisincreasedby about50%,whichgivesatotal-delaydegradation( tSRAM)ofabout25%.

PAGE 156

141 WithCWLreductionaccountedfor,thedegradationisreducedbyanother 2-3%basedonthestage-ratiomodelofthecascadedinverter-chain optimized for speed [Wes93 ]. 5.7 Conclusion Insummary,wehaveexploredtheideaofutilizingtheMIGFET conceptinanLgate=28nmFinFET-basedSRAMdesignforenhancedcell performance.Insightsastooptimaldesigntradeoffsamongtheread/ write/holdstabilityweregainedwithourUFDGmodel,andthe compromise on cell layout area and cell speed were discussed. Dynamicback-gatebiasingoftheaccesstransistorsintheSRAM cellgreatlyimprovesreadSNM.However,causeofconcernarises associatedwithseverestaticleakageoftheaccesstransistorduringread/ writeoperationsofothercellsinthesamememorycolumn,whenthe accumulatedleakagefromtheentirecolumnontothebitlinecouldbe comparabletoormorethantheread/writecurrent.Usingthe‘columnbaseddynamicpowersupplyswitching’schemeonthecellnotonly enhanceswritestabilitysignificantly,butamelioratesthestaticleakage oftheaccesstransistorsaswellduringwriteoperationofanothercellin thecolumn.However,adesigncompromisehastobeachievedbetweenthe degradingholdSNMandtheinherentleakageproblemviaappropriate VCC lowering. Ontheotherhand,staticback-gatebiasingoftheaccess transistorsintheSRAMallowsamoreflexibledesigntradeoff.Awritable cellwithsignificantSNMimprovementaswellasreasonablycontrolled

PAGE 157

142 leakagecanbeachievedviaappropriateback-gatebiasingoftheaccess transistorand/ortheloadtransistorsinsingle-gatemode.Toguaranteea morereliablewrite,however,thecolumn-baseddynamicpowerswitching schemecanbeutilized.Infact,agreatwritemargin( @ 310mV)aswellas holdmargin( @ 230mV)wasachievedsimultaneouslywithproperbiasing conditions,alongwithanexcellentreadSNM(249mV)basedonthis scheme. ThesensitivityofthecellSNMandwritemargintodevice dimensionalvariationsintheaccessMIGFETs,whendynamicsupply voltageloweringisusedduringwrite,issmallandwelltolerable,because unlikesubthresholdleakage,currentdriveisonlyslightlysensitiveto structuralvariationsintheMIGFETs.Variationsinthegatework functionofthetechnology,ontheotherhand,showmuchstrongerimpact onboththereadSNMandwritemarginofthecellduetotheshiftedtrip pointofthecross-coupledinvertersandthemodifiedpull-downcapability. Nevertheless,theSNMimprovementovertheFinFET-cellisretained; andagoodwritemarginisguaranteedwithin50mVincreasesofgatework function from midgap. Thelayoutpenalty( @ 13%)ofthecellduetotheadditional contactsrequiredwasillustratedandquantifiedbasedondesignruleofa linearlyscaledversionof90nmtechnology.Alsothespeedofthecellwas showntobecompromisedduetotheweakenedaccesstransistors. However,thereducedgatecapacitanceoverthewholerangeofgatebias whenbiasedinsingle-gatemodewillalleviatethecellspeeddegradation.

PAGE 158

143 Incomparison,strengheningthepull-downnMOSFETsvia doublefinsor(100)surfaceorientationyieldsrelativelymodest improvementsinthereadSNMandincurscomparableormorearea penalty;thereadaccessspeed,ontheotherhand,isdesirablyenhanced duetothehigherreadcurrent.Increasingthegatelengthoftheaccess transistorsforaweakercurrentdriveisanotheroptiontoimprovethe readSNM,whichtendstohavelessnegativeimpactonthelayoutarea; however,bothword-lineandbit-linedelaysworsenduetoincreasedwordlinecapacitanceandreducedreadcurrent.Theback-gatedcelldesign turnsouttogreatlyimpactthecurrentdriveintheaccesstransistors,and therefore,degradethewritemarginandaccessspeedsignificantly.This designoptionwillnotgainmuchadvantagewhenthecurrentdriveinthe accesstransistorsislimitedbytheuseofmidgaporhighergatework function for the access transistors.

PAGE 159

144 CHAPTER 6 THE ITFET: A NOVEL FINFET-BASED HYBRID DEVICE 6.1 Introduction WithCMOStechnologybeingrapidlyscaled,nonclassicalsilicon devicestructureswithfullydepleted(FD)ultra-thinbodies(UTBs)are beinginvestigatedforfuturegenerations[Kim01,Tri03].Thedouble-gate (DG)FinFET[Hua99]isofmostinterestbecauseofitsexcellent suppressionofshort-channeleffects(SCEs)anditsrelativelyeasy fabricationandintegration.And,ifthefinheight(hSi),subjecttoitsthin width(wSi)neededfortheSCEcontrol[Yan05],canbemadegreaterthan aboutthehalf-pitchoftheCMOStechnology[ITRS05],thentheFinFET canyieldbetterlayout-areaefficiencythanthatofconventionalplanar MOSFETs[Yan05],evenwhenonlyonethinfinperpitchisallowedand mostofthepitchareaisunused.However,thedevicewidthis“digital,” andthelayoutefficiencycanbecompromisedbytherestrainedcurrent perpitchdefinedbythetechnologicallimitofthefinaspectratio,Rf=hSi/ wSi, which is typically 3-5. Toimprovethelayoutefficiency,orcurrentperpitch,ofFinFET technology,wehavesuggestedthatasingle-gate(SG)planarFD/SOI MOSFETbefabricatedintheunusedportionofthepitcharea,and mergedwiththeDGFinFETtoformasingledevicewithacommongate [Mat05a].Theviabilityofthishybrid-deviceconceptstemsfromthefact

PAGE 160

145 thatSG(withthickBOX)andDGMOSFETswithundopedUTBs(which mustbeusedfornonclassicalnanoscaledevices[Tri03])haveaboutthe samethresholdvoltagewhentheSCEsarewellcontrolled[Tri03, Kim05b].Theprocessingofthehybriddevice,whichwecalltheInvertedTFET(ITFET)becauseofitscross-sectionalshape(Figure6.1),hasbeen demonstrated,showinginfacttechnologicalbenefitssuchasmechanically stabilizedfins[Mat05b],butnoanalysisofitsdesignnorperformance potentialinnanoscaleCMOSapplicationshasbeendone.Inthischapter, weuseourprocess/physics-basedgenericcompactmodelforDG MOSFETs,UFDG[Fos05],inSpice3,combinedwithsimulationsdone withthe3-DnumericalsimulatorDavinci[Dav03],togaininsights regardingthedesign,performance,andscalabilityoftheITFET.UFDG, whichisapplicabletoSGFD/SOIMOSFETstoo,includesrigorous accountingsfortheSCEs,thequantizationeffects,andthecarrier mobilityintheUTB,and,becauseofitsprocessbasis,isquasi-predictive andhencequiteusefulinstudiessuchasthisone.BasedonUFDG/Spice3 simulations,wealsonotethepotentialbenefitsoftheITFETineffecting gooddesignoftheFinFET-based6T-SRAMcellwithregardtotheareaperformance tradeoff [Guo05]. 6.2 The ITFET Design and Analysis Across-sectionalillustrationoftheITFET,withonefinper pitch,isshowninFigure6.1.Forourstudy,wefirstuseagatelengthLg=28nm,andassumethatitequalsthemetallurgical,oreffectivechannel length(Leff).(Morethanlikely,nonclassicalMOSFETswillbedesigned

PAGE 161

146 Figure 6.1Cross-sectionoftheITFETstructure,inthegatedregion betweenthesourceanddrain,withtheungatedn-base shown shaded. DG FinFET SG SOI MOSFET hSi wSi P (pitch) BOX SOI tSi Gate SiO2 Si Substrate x z Basic inverted-T structure

PAGE 162

147 withgate-source/drainunderlapsuchthatLeffwillexceedLg[Tri05].)We furtherassumeagate-oxidethickness(tox,orEOT)of1nm(asprojected forhigh-performance28nmCMOSintheSIAITRS[ITRS05])forboththe FinFETandtheSOIMOSFETthatconstitutetheITFET.And,sinceboth nanoscale,fullydepleteddevicesmustbedesignedwithundopedbodies, weuseamidgapmetalgatecommontobothasillustratedinFigure6.1. TheUTBsoftheFinFETandtheFD/SOIMOSFET(FDFET)mustbethin enoughtosuppressSCEs.Recent3-Dnumericalsimulationsofthe undopedFinFETstructure,variedfromvirtuallyDG,withRf>>1,to triple-gatetovirtuallySG,withRf<<1,showedthatwSioftheundoped DGFinFETmustbescaledto~Leff/2,whereastheSOIthickness(tSi)of theundopedSGFDFETmustbescaledmuchmore,to~Leff/5[Yan05].So, for our ITFET, we let wSi = 14nm and, initially, tSi = 5.6nm. Further,withregardtocarriertransport,e.g.,mobility,inthe ITFET,weassumethattheFinFETaswellastheFDFETsurfacesare {100}-oriented.WenotethattypicallytheFinFETsurfacesare{110},and thedifferentmobilitytherebyimpliedwouldmodifyourresults concerningcurrentenhancementintheITFET.However,the modificationswouldnotbetoosignificantduetothecarriervelocity saturationinthenanoscaledevices,andhencewouldnotunderminethe conclusions of our study. TheITFETdesigngoalistoachievegoodcurrent-voltage characteristics,i.e.,highIon/pitchandhighIon/Ioffwithacceptable thresholdvoltage(Vt).QuantizationeffectsintheUTBs[Ge02],aswellas

PAGE 163

148 theSCEs,influencethecharacteristics,butarenotaccountedforwellin commercialsimulationtools.Theyaremodeledwellinourphysics-based UFDG.WemustalsobeconcernedabouttheungatedportionoftheITFET structure,atthebaseofthefinasindicatedinFigure6.1,whichcan possiblyunderminethedevicecharacteristics.Thisisa(3-D)geometrical issue, which can be examined effectively with Davinci. CharacterizingaMOSFETintermsofcurrent/pitchis uncommon,anddoingsofortheundopedITFETrequiressome preliminaryclarificationandperspective.UFDG-predictedcurrentvoltagecharacteristicsoftheconstituent(n-channel)FinFETareshown inFigure6.2.TheSCEs,i.e.,subthresholdslope,orgateswingS @ 80mV, andDIBL @ 100mV/V,arewell-controlledasexpected.Thecurrent, however,givenperhSiascommonlydone,isnotagoodreferenceforthe ITFETcurrent.So,usingthepitch,P=140nmasprojectedintheITRS [ITRS05]forLg=28nm,weplotinFigure6.3theUFDG-predictedcurrent perpitch,atVDS=1.0V,fortheFinFETwithRfvaryingfrom3to5.(Note thatthecurrentsinFigure6.3arejustthatinFigure6.2multipliedbyhSi=RfwSi.)IncreasingRfincreasesboththeper-pitchIonandIoffas expected,inproportiontohSi,theproperlydefinedeffectivewidth(Weff) oftheundopeddeviceinwhichbulkinversionissignificant[Kim05b].The per-pitchIonhencedependsontheachievablehSi,subjecttowSi,aswell astheper-Weffcurrent,definedbythecarrierinversionchargeand transport[Kim05b].Withonlyonefinperpitchandthehighmidgap-gate

PAGE 164

149VGS(V)IDS(A/ m m)0.05V VDS = 1.0V S @ 80mV DIBL @ 100mV/V 0.00.20.40.60.81.0 10-1010-910-810-710-610-510-410-3 Figure 6.2UFDG-predictedIDS-VGScharacteristicsperwidth(hSi)of anLg(=Leff)=28nmnFinFETdesignedwithundopedbody and midgap metal gate; wSi = 14nm, tox = 1.0nm.

PAGE 165

150VGS(V)IDS(A/pitch) VDS = 1.0V Rf = hSi/wSi = 3, 4, 5 0.00.20.40.60.81.0 10-1010-910-810-710-610-510-4 Figure 6.3UFDG-predictedIDS-VGScharacteristicsperpitchoftheLg=28nmnFinFETinFigure6.2,withthenaspectratio varied from 3 to 5.

PAGE 166

151 workfunctionoftheFinFET,thiscurrentmetriccanpossiblybelower than that of a classical planar MOSFET [Yan05]. Now,relativetotheFinFETcurrentinFigure6.3,weexpecta substantiallymorecurrentdrivefromtheITFET,asimpliedbythe increasedper-pitchWeff@ hSi+(P-wSi)andtheratio(fDG[Kim05b])of theper-Weffon-statecurrentsintheDGFinFET(withWeff=hSi)andSG FDFET(andperhapslargerRfenabledbythebetterfinstability [Mat05b]).NotethatfDGcanactuallybegreaterthan2[Fos02b],its commonlyassumedvalue,whichmeanslessrelativeIonincreasethan mightbeanticipated.ForfDG=2,therelativeincreaseis(P-wSi)/(2hSi), whichis113%forourdevicewithRf=4.However,becausetheweakinversionchargeinboththeFinFETandtheFDFETisuniformly distributedinthebody[Kim05b],therelativeincreaseinIoffwillbe higher,byabout(P-wSi)/hSi(225%)ifSCEsintheFDFETareaswellcontrolledasintheFinFET,andiftheungatedfin-baseisnotsignificant. Thelatter‘if’requiresexamination.Tocheckthefin-base leakage,weuseDavinci.WeplotinFigure6.4theDavinci-predictedperpitchcurrent-gatevoltagecharacteristic,atVDS=1.0V,oftheITFETwith anRf=4fin,contrastedwiththoseoftheconstituentFinFETandFDFET. (Notethatsincethemodelingofcarriertransportandquantum confinementinDavinciisinadequateforUTBdevices,andsilicon properties,suchaselectronaffinity,bandgap,andeffectivedensityof states,usedinDavinciaredifferentthantypicallyassumed[Tau98],asin UFDG,thecharacteristicsDavincipredictsareslightlydifferentfrom

PAGE 167

152 0.00.20.40.60.81.0 VGS (V) 10-1010-910-810-710-610-510-410-3IDS (A/pitch) FinFET ITFET FDFET VDS = 1.0VFigure 6.4Davinci-predictedIDS-VGScharacteristicsperpitchoftheLg= 28nmnITFET,alongwiththeseparatecharacteristicsofthe constituentFinFETandFDFET;Rf=4.Notethesignicant Ioff in the ITFET, which is due to the ungated n-base.

PAGE 168

153 thoseinFigure6.3predictedbyUFDG.Thisdiscrepancy,however,does notundermineouranalysisofthefin-baseleakage.)Asexpected,the Davinci-predictedIonoftheITFETisapproximatelythesumofthoseof theFinFETandFDFET,buttheITFETIoffisabouttwoordersof magnitudehigherthanthatoftheFinFET,adifferencethatismuchmore thanthecontributionoftheconstituentFDFET.Clearly,theungatedfinbasesupportsprodigiousweak-inversionleakagecurrent.And,additional Davincisimulationsshowthatthisleakagecurrentisnotstrongly sensitivetothecurvatureofthegatenearthefin-basecorners,whichin actualITFETshasfiniteradius[Mat05b],unlikethesharpcornersin Figure 6.1. TheDavinci-predictedelectrondensityprofilesdownthefin(i.e., n(x=wSi/2,z)inFigure6.1,atthemiddleofthechannel)oftheITFET, plottedinFigure6.5forweakandstronginversion,contrastedwiththose oftheFinFETconfirmthisconclusion.Notethesignificantdensityof weak-inversion(VGS=0V)electronsinthefin-base(z>hSi=56nm)ofthe ITFET,whichevenextendsupintothegatedfin.Thiselectrondensity resultsmainlyfromthesource/drainelectric-fieldfringinginthethick (200nm)BOX[Tri03]underthefin.(Notethatthefringingeffectalso tendstooccurinthethick(50nm)oxideontopofthefin,butthatthegate extendingabovethefin(seeFigure6.1)preventsitandevensuppresses n(z)inthetopportion(z~0)ofthefin.)Thedifferencebetweenn(z)inthe ITFETandFinFETforstrong-inversion(VGS=1.0V)inFigure6.5is

PAGE 169

154 0102030405060 z (nm) 10121013101410151016101710181019n (cm-3) FinFET ITFET VGS = 1.0V VGS = 0V x = wSi/2 Fin-Base hSiy = Lg/2 Figure 6.5Davinci-predictedelectrondensityprolesdownthen (i.e.,n(x=wSi/2,z)inFigure6.1atthemiddleofthe channel)ofthenITFETofFigure6.4,forweak(VGS=0V) andstrong(VGS=1.0V)inversion,contrastedwiththoseof theconstituentFinFET;VDS=1.0V.Theexcessiveelectron densityinthen-baseoftheITFETattheoffconditionis obvious.

PAGE 170

155 negligiblewithregardtoIon;thefringingfieldintheBOXisrelatively small compared to that induced by the gate in this case. TheundopedITFETofFigure6.4,withhighdrivecurrentatthe expenseofveryhighoff-statecurrent,couldbeusefulinparticular applications,butnotgenerally.Tomakeitmoreviable,thefin-base leakagemustbeeliminated.Onewayofdoingthis,atleasttheoretically, istoheavilydopethefin-basetosuppresstheelectrondensityinthe ungatedregion.Technologically,thiswouldresultalsoindopingmuchof thefinandtheSOIfilm,andtheincreasedVtwouldnecessitateadifferent gate,e.g.,n+polysiliconforthenITFET.Davincisimulations,donewith uniformbodydopingeverywhere,showthatthisworks,butthedoping densityrequiredis~1019cm-3.Suchdopingisnottechnologicallyfeasible inUTBs[Tri03],anditleadstootherproblemssuchasmobility degradation and gate depletion if polysilicon is used. Anotherwayofsuppressingthefin-baseleakagecurrent,which involvesnewprocesstechniques,istoextendathinnerversionofthe FinFETgatedowntotheunderlyingBOX,therebygatingthefin-base.We havedemonstratedthetechniquesusingapolysilicongate,asshownby theTEMimageinFigure6.6.Metalgatestackssuchastitanium-nitride ortantalum-carbidewithpolysiliconoverthemcanbeusedinsucha processsincethepolysiliconactsasahardmasktothemetaletch,andthe metalfillstheregionsbetweenthevertical(FinFET)andhorizontal (FDFET)channels.Theprocessisaself-alignedflow.Theverticalsilicon enablestheformationofaspacerthatisusedtodefinetheregiontobe

PAGE 171

156 Figure 6.6Cross-sectionalTEMimageofanITFETwiththeFinFET polysilicongateextendeddowntotheBOX.Ultimately, thespacingbetweentheverticalsiliconnandthe horizontalSOIwillbereduced,andmetalwillbe integratedintothegatestack.Theimageisprovidedby Leo Mathew from Freescale Semiconductor, Inc.

PAGE 172

157 removedbetweentheverticalandhorizontalsiliconregions. Combinationsofwetandplasmaetchesareusedtoexposeandremovethe thinsiliconregionsadjacenttothefin-base,betweentheFinFETandthe planarFDFET.Thespacerandthetopmaskingnitrideservetodefinethe etch,providingroomforthefin-gateextension.Thepreviouslynoted mechanicalstabilityoftheITFETstructure[Mat05b]isrequiredmainly duringtheprocessoftrimmingandwetetchingthesacrificialoxide formedonthefins.TheprocessofseparatingtheverticalFinFETand planarFDFETiscarriedoutaftersuchtrimmingandetch,andhencethe mechanicalstabilityprovidedbytheITFETchannelformationisstill effectedduringthosecrucialsteps.Further,theFinFETgateextension canbelimitedtoonlythegatedportionofthefinbyusingthesource/drain epitaxialgrowthprocesstomergetheverticalandhorizontalsilicon portions, thus giving more fin stability. Theextended-gatestructuredescribedeffectsuseoftheentire heightofthefinintheITFET(i.e.,hSi hSi+tSi),yieldingmorecurrent perpitchwithoutanyabnormaleffectssuchassignificantcorner conduction[Yan05].Infact,DavincisimulationsofthisupgradedITFET, withundopedUTBs,indicatethatitisvirtuallyequivalenttoaparallel combinationoftheconstituentFinFETandFDFET,yieldingcomposite currentcharacteristicsthatcanbeoptimizedwithproperchoiceofwSi,tSi, and the FDFET width per pitch, which can be easily varied. So,withtheFinFETgateextension,wecanuseUFDGtomodel theITFETasacompositeDGFinFETandSGFDFET,andexamineits

PAGE 173

158 designandpotentialperformance.Weplot,inFigure6.7,UFDG-predicted per-pitchcurrent-voltagecharacteristicsofourLg(=Leff)=28nmnITFET atVDS=1.0V,butwithtSivaryingoveraviablerangeof5nm(Leff/5,the ITFETsubthresholdcharacteristicsaredegradedandarevirtually identicaltothoseoftheconstituentFDFET,whichareunderminedby SCEs,includingfieldfringingintheBOX[Tri03],anddecreasedVtdueto less quantization [Tri05b]. TheIon(tSi)andIoff(tSi)dependencesoftheITFET,extracted fromFigure6.7,areclearlyrevealedinFigure6.8wherethepredicted high-performance/low-powermetricIon/IoffandtheIonenhancement( D Ion) achievedwiththeITFETrelativetotheFinFETareplotted.Notethatthe relativeIon/IoffdegradesdramaticallywithincreasingtSi,despitethe

PAGE 174

159VGS (V)IDS (A/pitch) FinFET FDFET ITFET VDS = 1.0V tSi = 5, 7, 9nm 0.00.20.40.60.81.0 10-1110-1010-910-810-710-610-510-410-3 Figure 6.7UFDG-predictedper-pitchIDS-VGScharacteristicsoftheLg= 28nmnITFET,foraviablerangeofSOIthickness,compared with those of the constituent FinFET and FDFET; Rf = 4.

PAGE 175

160 5.06.07.08.09.0 10-310-210-1100101(Ion/Ioff)ITFET / (Ion/Ioff)FinFET 5.06.07.08.09.0 tSi (nm) 130.0 135.0 140.0 145.0 150.0D Ion/(Ion)FinFET(%) VDS = 1.0VFigure 6.8UFDG-predictedIon/Ioffratio,alongwiththepercentage Ionenhancement,oftheLg=28nmnITFETrelativeto the constituent FinFET, versus SOI thickness; Rf = 4.

PAGE 176

161 increasingrelative D Ionwhichnominallyislargeat @ 140%.TheIonenhancementislargerthanthat(113%)estimatedpreviously,indicating thatherefDG<2.But,onlywiththewell-controlledSCEsand quantizationyieldedbythethinnestachievabletSi=5nmdoesthe enhancedIonrenderamuchhigherIon/Ioffratio(by @ 2X)fortheITFET compared to the FinFET. Anotherissueinthisregardistheaddedgatecapacitanceofthe ITFETrelativetotheFinFET,andwhethertheCV/Ispeedmetricis undermined.Althoughthisispossible,wenotethatCV/Iisnotagood metricforundopednonclassicaldevices[Fos02],andwesurmisethatthe benefitsoftheITFET(i.e.,higherachievabledevicedensityand eliminationofthedigitalwidthoftheFinFET)relatedtotheenhanced current drive are most important. ScalingtheITFETbeyond28nmwillrequireredesignsince furtherthinningoftSiisprobablynotpossibletechnologically,nor desirableelectricallybecauseofseverequantizationeffectsandincreasing Vt[Tri05b].TheminimumviablethicknessofplanarSOIisgenerallysaid tobeabout5nm.RedesignoftheconstituentFDFETforITFET scalability,whichisunlikescalingtheconventionalFD/SOIMOSFET [Tri03],isnotimpossible.SignificantenhancementoftheFinFETIoncouldstillpossiblybeachieved,withoutmuchconcernforSCEsinthe FDFET,byincreasingVtoftheFDFET,e.g.,viaimprecisedopingofthe bodyand/orincreaseofthegateworkfunction.Notethestudyofthe formerapproachbasedonthesameLgate=28nmnodeaswellasits

PAGE 177

162 applicationwasactuallyinitiated,andisnowdocumentedinSection6.4; itwillprovidebasisforamoreelaborateexaminationonscalabilityas wellasonviabilityincertainapplications,suchasanSRAMcell,whichis beyondthescopeofthisdissertation.Suchdesign,however,mustbedone withattentiongiventopossibledetrimentaleffectsofsubstantially differentVt’softhetwoconstituentdevices.Evenwithoutsuchredesign, theundopedITFETcouldfindapplicationsinscaledCMOSinwhichdrive currentisapremiumandoff-statecurrentislesssignificant,e.g.,asI/O devices. 6.3 ITFET Applications: SRAM AproperlydesignedITFET,e.g.,theLg=28nmdeviceanalyzed inSec.II,couldhavewidespreadapplicationsbecauseoftheadded, variablecurrentdriveperpitchafforded,especiallyinFinFETcircuits thatrequiredeviceratioing.Forexample,itcouldyieldanoptimaldesign oftheFinFET-CMOS6T-SRAMcell[Guo05]byprovidingthehigherdrive neededinthepull-downnMOSFETsforbetterreadstabilityandspeed, withoutincreasingtheleakagecurrentofthecellandwithnoareapenalty atall.Toillustratethisapplication,wesimulatetheSRAMcell,shownin Figure6.9,withUFDG/Spice3,usingLg=28nmITFETs(withtSi=5nm initially,andWeff=120nmfortheFDFETs,andwiththefin-baseleakage assumedsuppressedasdiscussedwithreferencetoFigure6.6)forthe pull-downnMOSFETs(M1andM3),andFinFETsfromFigure6.2,with theirp-typecounterparts,fortheaccess(M5andM6)andload(M2and M4)transistors,respectively.Minimum-size,i.e.,single-fin,devicesare

PAGE 178

163 BLBL WL VDDM1M3 M2M4 M5 M6 VLVRFigure 6.9SchematicoftheCMOS6T-SRAMcell.FortheITFET design,M1andM3areITFETs,andtheotherdevices are DG FinFETs.

PAGE 179

164 usedforalltransistorsformaximumSRAMdensity,andRf=4(i.e.,hSi= 56nm) is assumed. TheUFDG/Spice3-predictedbutterflycurve(steady-stateVRvs. VLinFigure6.9)ofthe28nmITFET/FinFETSRAMcellwithVDD=1.0V isshowninFigure6.10.Notethatexcellentstaticnoisemargin(SNM @ 220 mV)isobtained,duetotheaddedstrengthaffordedM1andM3[See87] bytheITFETs.Forcomparison,wealsoshowinthesamefigurethe butterflyplotspredictedwhensingle-finFinFETsareusedforthepulldownnMOSFETs,insteadoftheITFETs,andwhenlarger-areadouble-fin FinFETsareused.Intheformercase,theSNM( @ 140mV)issignificantly smallerbecausethesingle-finFinFETs(M1andM3)arenotstrong enough,relativetotherespectivepasstransistors(M5andM6),topullthe outputvoltagedowneffectively[See87],resultinginalargeoutputdisturb voltageofabout200mVwhentheinputvoltageisatVDD.Inthelatter case,theSNM( @ 200mV)isimprovedbytheaddedstrengthofM1andM3, butisstillsmallerthanthatofthecellwiththeITFETs(M1andM3are toostrong[See87])eventhoughthecellareaisenlargedconsiderably(M1 andM3covertwopitchesinsteadofone).With45nmdesignrules [ITRS05],anSRAMcelllayout-areapenaltyofabout17%wouldresult from using two fins for M1 and M3 instead of one [Guo05]. Aswehavenoted,theSOIthicknessisacrucialparameterinthe ITFETdesign,andithasbeenthinnedtonearitstechnologicallimit.To checkeffectsofvariationsoftSiontheITFET/FinFETSRAMperformance, wevaryitfrom4nm(whichisthinnerthanthelimit)to9nm,andobtain

PAGE 180

165 0.00.20.40.60.81.0VL (V) 0.0 0.2 0.4 0.6 0.8 1.0VR (V) Single-fin FinFETs Double-fin FinFETs ITFETs 220mV 140mV VDD = 1.0VFigure 6.10UFDG-predictedbutterycurvefortheLg=28nmSRAMcell withITFETs(tSi=5nm,Weff=120nmfortheFDFETs)used forpull-down(M1andM3),comparedwiththoseofSRAM cellswithsingle-nFinFETsanddouble-nFinFETsforpulldown,respectively;VDD=1.0V.VRandVLaretherightand leftstoragenodevoltagesofthecellasindicatedinFigure6.9.

PAGE 181

166 theUFDG/Spice3-predictedbutterflycurvesshowninFigure6.11(a). RememberthatincreasingtSidoesnotstronglyaffectIonoftheITFET, butdoesincreaseIoffandlowerVtduetothedeterioratingSCEswithless quantizationintheconstituentFDFET.Thisdeteriorationisreflectedin Figure6.11(a)bythedegradedSNMofthecellforincreasingtSi,whichis plottedinFigure6.11(b).Asareference,wealsoincludeinthefigurethe SNM( @ 140mV)obtainedwhensingle-finFinFETsareusedforthepulldowntransistors.TheSNMisexcellent(>200mV)fortheultra-thintSi,for whichtheSCEcontrolintheFDFETkeepstheITFETVtatitsproper value.However,fortSi> @ 6nm,itdegradesatarateof @ 20mV/nmasVtis lowered,despitethesustainedrelativestrengthoftheITFETs.FortSi> 8nm,morethan50%oftheSNMbenefitaffordedbytheITFETsrelative tothesingle-finFinFETsislost.ThislossofSRAMperformance,which correlateswiththeincreasedIoff,furtherdemonstratestheimportanceof thecontrolofthefin-baseleakageintheITFET,aswediscussedinSec.II. ThetSivariationnotonlyaffectsSNM,butgovernsthestatic powerconsumptionofthecellaswell.Toshowitssignificanceinthis regard,weincludeinFigure6.11(b)UFDG/Spice3-basedcalculationsof averagestaticpowerpercell(Pstatic)versustSiatVDD=1.0V,and,for reference,thecalculatedpowerforthesingle-finFinFETcell.These calculationsfollowfromthefactthatintheidleorprechargephaseofthe SRAMcell,eithertransistorsM1,M4,andM6(forVL=1)orM2,M3,and M5(forVL=0)areintheoff-state,whichrenders(e.g.,forVL=1) [Mam03]

PAGE 182

167(a) 0.00.20.40.60.81.0 VL (V) 0.0 0.2 0.4 0.6 0.8 1.0VR (V) tSi = 4, 5, 6, 7, 8, 9 nmVDD = 1.0V 10-1010-910-810-710-610-5Pstatic (W/cell) 4.05.06.07.08.09.0 tSi (nm) 0 50 100 150 200 250SNM (mV) VDD = 1.0V FinFET Cell (b)Figure 6.11UFDG-predictedreadstabilityandstaticpowerconsumption versusSOIthickness:(a)butterycurvesforthe28nmITFET/ FinFETSRAMcellforvariousSOIthicknesses;VDD=1.0V. (b)thestaticnoisemarginextractedfrom(a),alongwith UFDG/Spice3-basedaveragestaticpowerconsumptionofthe SRAMcell,versusSOIthickness.ThecorrespondingSNMand Pstatic of the FinFET cell are shown for comparison.

PAGE 183

168 ;(6.1) wehaveignoredgate-tunnelingleakage,assumingitiswellcontrolled. Eveninthereadandwritephasesofthecell,(6.1)canberepresentative ofstaticpowerconsumptionpercellaveragedoveramemoryarraysince manyothercellsinthearraywouldbeintheidleorprechargephase.At VDD=1.0V,Figure6.11(b)showsthattSicanberelaxedupto @ 7nmfora tolerableorder-of-magnitudeincreaseinPstatic(~10-8W/cell),without severe degradation of SNM ( @ 200mV). LowerVDDcanbeusedtoreducePstatic,attheexpenseoflower SNMduetothesmallerdifferencebetweentheinverterswitch-point voltageandVDD[See87].FortSi=6nm,theUFDG/Spice3-predicted butterflycurvesoftheITFET/FinFETSRAMcellwithdecreasingVDDshowninFigure6.12(a)revealtheSNMdegradation,eventhoughSNM >>0.1VDDforVDDloweredto0.4V.ForeachVDDassumed,thepredicted SNMversustSiisplottedinFigure6.12(b),alongwiththoseforthesinglefinFinFETSRAM.AtVDD=0.8V,theSNMislowerbyupto @ 50mV,but itremainssignificantlyhigherthanthatoftheFinFETcell,andwell above100mVevenfortSi=9nm.Thelowerrateofdegradationwith increasingtSi,relativetothatatVDD=1.0V,isduetolessDIBL.TheSNM advantageaffordedbytheITFETs,however,islostforVDD< @ 0.6V.This lossreflectsthelossofIonenhancementfordecreasingVDD.Note, however,thatboththeITFETandtheFinFETSRAMcellsoperateeven at VDD = 0.4V, where the SNM is @ 70mV for tSi < @ 7nm. P static V DD I offM1 () I offM4 () I offM 6 () ++ [] =

PAGE 184

169VL (V) 0.00.20.40.60.81.0 0.0 0.2 0.4 0.6 0.8 1.0VR (V) tSi= 6nm VDD = 1.0, 0.8, 0.6, 0.4V 4.05.06.07.08.09.0 tSi (nm) 0 50 100 150 200 250SNM (mV) FinFET Cell VDD = 1.0, 0.8, 0.6, 0.4V(a) (b)Figure 6.12UFDG-predictedreadstabilityversuspowersupply voltage:(a)butterycurvesatdifferentsupplyvoltagesfor the28nmITFET/FinFETSRAMcell;tSi=6nm.(b)the staticnoisemarginsextractedforeachVDDversusSOI thickness.ThecorrespondingSNMsoftheFinFETcellare shown for comparison.

PAGE 185

170 AsevidentinFigures.11and12,theITFETinthe28nmSRAM cellisbeneficialevenfortSiasthickas @ 7nm.However,technological controloftSiisaformidabletask,andsensitivityoftheSNMtorandom variationsintSimustbechecked.Todoso,weassumeaprocess-induced mismatchoftSiintheM1andM3ITFETsofthecell,whichcauses asymmetryintheUFDG/Spice3-predictedbutterflycurveasexemplified inFigure6.13(a).KeepingtSi(M3)=6nm,andvaryingtSi(M1)asmuchas 2nmaroundthisnominalvalue,wegettheminimumSNM(leftvs.right) versustSiplottedinFigure6.13(b)atVDD=1.0V.IncludedinFigure 6.13(b)istheworst-caseSNMthatresultswhentSi(M1)=4nmandtSi(M3) =8nm.TheseresultsshowthatmoderatemismatchesintSiofupto @ 20% could be tolerable. Process-inducedvariationsinLgandwSi,whichaltertheSCEs andvaryVt,mustalsobecontrolled,intheFinFETsaswellastheITFETs oftheSRAMcell.TheUFDG/Spice3predictionsoftheminimumSNM correspondingtoM1-M3mismatchesinLg(=Leff)andwSi,centered around28nmand14nm,respectively,areplottedinFigure6.14.They show @ 15%mismatchinLgandquitelargemismatchesinwSiare tolerable. 6.4 A More Scalable ITFET with Doped SOI Body TheITFETdesignswehavepreviouslyexamineduseundoped bodiesandametalgate,orhighlydopedbodiesandapolysilicongate [Mat04],buttheyarenotscalablebecauseoftechnologicallimitationson ultra-thinSOIanddoping,respectively.Further,theungatedfin-base,

PAGE 186

171(a) (b) 0.00.20.40.60.81.0 VL (V) 0.0 0.2 0.4 0.6 0.8 1.0VR (V) tSi(M3) = 6nm VDD = 1.0V SNMLSNMRtSi(M1) = 4nm 4.05.06.07.08.0 tSi(M1) (nm) 150 200 250SNM = min(SNML, SNMR) (mV) tSi(M3) = 8nm (worst case) tSi(M3) = 6nm VDD = 1.0VFigure 6.13UFDG-predictedreadstabilityversusmismatchintSiofM1 andM3:(a)butterycurveforthe28nmITFET/FinFET SRAMcellforanassumedmismatchintSi;VDD=1.0V.(b) extractedminimumSNM(SNMLorSNMRasindicatedin(a)) forM1-M3tSimismatchesdenedbyvaryingitinM3.The worstcaseindicatedcorrespondstoa2nmvariationoftSiin M1 and M3, respectively, from the nominal tSi = 6nm.

PAGE 187

172 1213141516 wSi(M1) (nm) 150 250 2426283032 Lg(M1) (nm) 200SNM = min(SNML, SNMR) (mV) Lg(M3) = 28nm wSi(M3) = 14nm wSi(M3) = 16nm (worst case) Lg(M3) = 32nm (worst case) VDD = 1.0VFigure 6.14UFDG-predictedminimumSNMformismatchesinwSiandLg(=Leff)ofM1andM3,relativetothenominalwSi=14nmandLg=28nm,respectively;VDD=1.0V.The worstcasesindicatedcorrespondtoa2nmvariationof wSianda4nmvariationofLginM1andM3, respectively, from the nominal values.

PAGE 188

173 highlightedintheITFETcross-sectioninFigure6.1,posesasevere leakageproblem.HereweproposeanovelITFETstructure,anduse3-D numericaldevicesimulationstocheckitsoptimaldesignandtoshowits scalabilityandperformancepotential.Itsimplementationwithour process/physics-based UFDG model will also be discussed. 6.4.1 Davinci Simulations for Optimal Design ThenoveltyoftheITFETdesignweproposehereisinthe constituentSOIMOSFET.WhereasconventionalSOIMOSFETsarenot scalabletotheendoftheITRS,duetoundoablechanneldoping requirementsinthepartiallydepleted(PD)deviceandtoprohibitive ultra-thinSOIinthefullydepleted(FD)device,ourconstituentdevice, andhencethenovelITFET,arescalable.WedesigntheSOIMOSFET withhighthresholdvoltage(Vt),definedbythenear-midgapwork functionofametalgate,whichissharedwiththeundoped,scalable FinFET,andbyhighdopingdensity(NB)inanSOIbody(UTB)of moderatethickness(tSi).ThehighVtmeansthatweneednotbetoo concernedwithshort-channeleffects(SCEs),andhencerequirementson NB(x)andtSicanberelaxed.Weneedonlyensurethattheleakagecurrent (Ileak),duetoS/Delectric-fieldfringingintheBOXaswellastheungated fin-base,isnotexcessive,whileVtislowenoughtoyieldasignificant enhancement of Ion over that of the FinFET. WestudythenovelITFETfirstusingDavinci[Dav03],a3-D numericaldevicesimulator.WeinitiallycheckuniformNB,assumingthat lateraldiffusionwilleffectivelydopethenarrowfin-base,andrelatively

PAGE 189

174 thicktSi=25nm.Weassumeann-channelITFETwithLgate(=Leff)= 28nmandanEOT(ortox)of1nm,asprojectedforhigh-performance28nm CMOSintheITRS.WeletthefinwidthwSi=Leff/2=14nmforgoodSCE control(S @ 80mVandDIBL @ 100mV/V)intheundopedconstituent FinFET[Yan05],andthefinheighthSi=4wSi=56nm(abovethepedestal SOIlayer).TheSOIMOSFETwidthis(P-wSi),wherePisthepitch (140nm[ITRS05]).Davinci-predictedper-pitchcurrent-voltage characteristicsoftheconstituentSOIMOSFET,withNBrangingfrom 1018cm-3to1019cm-3,andoftheFinFET(withouttheungatedfin-base) andITFETareshowninFigures6.15and6.16,respectively.Notethatfor NB=1018cm-3,IoffisextremelyhighduetoIleak.ForNB=1019cm-3,Ileakissuppressed,butVtistoohightoyieldgoodIonenhancementinthe ITFET.ForNBbetweentheseextremes,IonandIoffcanbetraded-offas indicated.ForNB=5x1018cm-3,IonoftheITFETis57%higherthanthat oftheFinFET,butwiththesacrificeofmorethananorder-of-magnitude increaseinIoffduetoIleak.Notethatthepredictedsubthresholdcurrent intheNB=1019cm-3ITFETisactuallylowerthanthatintheFinFET, whichisduetothesuppressionoftheleakagecurrentinthelatter induced by field fringing in the BOX. ToimprovetheIon-Ioffdesigntradeoff,weincorporateasimple gaussianvariationinNB(x)acrosstheSOIbody,aswellassomethinning oftSi,asshownbythedopingprofile(a)inFigure6.17.TheDavincipredictedcurrent-voltagecharacteristicsoftheSOIMOSFET,andofthe FinFETandITFET,areshowninFigures6.18and6.19,respectively.

PAGE 190

175 Figure 6.15Davinci-predictedper-pitchIDS-VGScharacteristicsofthe constituent28nmSOInMOSFET,withuniformdoping density ranging from 1018cm-3 to 1019cm-3; tSi = 25nm. 0.00.20.40.60.81.0 VGS (V) 10-1010-910-810-710-610-510-410-3IDS (A/pitch) NB = 1x1018, 5x1018, 1x1019cm-3VDS = 1.0V

PAGE 191

176 Figure 6.16Davinci-predictedper-pitchIDS-VGScharacteristicsofthe 28nmnITFET,withtheSOIMOSFETdopingdensityranging from1018cm-3to1019cm-3;tSi=25nm.Thepredicted characteristicoftheconstituentundopedFinFET(withoutthe ungated n-base) is shown as well. 0.00.20.40.60.81.0 VGS (V) 10-1010-910-810-710-610-510-410-3IDS (A/pitch) FinFET ITFET NB = 1x1018, 5x1018, 1x1019cm-3VDS = 1.0V

PAGE 192

177 Figure 6.17Assumeddoping-density(gaussian)prolesintheconstituent SOIMOSFET;x=0isthetopsurfaceoftheSOIlm.Proles (b)and(c)applyfortSi=10nm,andreectimplantdosesof 80% and 60% of that in (a), respectively. x (nm) 0.05.010.015.020.025.0 10181019NB (cm-3) (a) (b) (c)

PAGE 193

178 Figure 6.18Davinci-predictedper-pitchIDS-VGScharacteristicsofthe 28nmSOInMOSFETwithNB(x)denedbyprole(a)in Figure6.17,fordecreasingtSi.Forcomparison,thedevicewith uniformNB=1x1019cm-3andtSi=25nmisalsoshown(dashed curve). 0.00.20.40.60.81.0 10-1010-910-810-710-610-510-4IDS (A/pitch) tSi = 25, 20, 15, 10, 5nm VGS (V) VDS = 1.0V

PAGE 194

179 Figure 6.19Davinci-predictedper-pitchIDS-VGScharacteristicsofthe 28nmnITFET,comprisingtheundopedDGFinFET(predicted characteristicshownbydashedcurve)andtheSOIMOSFET withNB(x)denedbyprole(a)inFigure6.17,fordecreasing tSi. 0.00.20.40.60.81.0 VGS (V) 10-1010-910-810-710-610-510-410-3IDS (A/pitch) tSi = 25, 10, 5nm VDS = 1.0VtSi(nm) Ion(mA/pitch) Ioff(nA/pitch) 250.1020.177 100.1220.232 50.1240.738 FinFET0.0730.629

PAGE 195

180 NotethatIleakisnoweffectivelyeliminatedirrespectiveoftSi,whileVtis reducedvialessdepletioncharge,whichcanbetailoredbythinningtSi.A goodIon-IofftradeoffcannowbeeffectedfortheITFET,asshowninFigure 6.19.AstSiisdecreasedfrom25nm,initiallythereisnotmuchchangein thecurrentsincetheSOIdeviceisPD,buteventuallythereiswhenit becomesFD.AttSi=10nm,theITFETcurrentis66%higherthanthatof theconstituentFinFET,andIoffismuchlowerduetonegligibleIleak.More thinningoftSito5nmsignificantlyincreasesIoffandlow-VGScurrentdue tolowerVt,butnotIonsince,asshowninFigure6.20,theinversionchargecentroidshiftstowardtheSOIbulk,thusloweringthegate capacitance.FortSi=10nm,thenotedNB(x)gaussiancanbeeasily achievedviaimplantationintotheBOXandsubsequentup-diffusioninto theSOI.Reductionoftheimplantationdose,asindicatedinFigure6.17, givesmoreIonenhancementasshownbythepredictionsinFigure6.21, butultimatelyattheexpenseofincreasedIoff.For80%reductioninthe dose(profile(b)inFigure6.17),thecurrentenhancementis83%with negligibleIoffincrease,whereasfor60%dosereduction(profile(c)),the enhancementisincreasedto93%,butwithIoffincreasedbyafactorof @ 3. WenotethatthemobilityandquantizationmodelinginDavinci, basedmainlyonbulkMOSFETs,isequivocalforUTBdevices.Wethus needtocheckourITFETdesignsusingUFDG[Fos05],ourprocess/ physics-basedcompactmodelforDG(andSGFD/SOI)MOSFETs.The mobility[Tri05a]andquantization[Ge02]modelinginUFDGisQMbased,withdependencesontSiandSi-surfaceorientationaswellas

PAGE 196

181 Figure 6.20Davinci-predictedmid-channelinversion-electrondensity acrosstheUTBoftheconstituentSOIMOSFETofFigure6.18 and 6.19, for two values of tSi; VDS = VGS = 1.0V. 0.02.04.06.08.010.0 x (nm) 10131014101510161017101810191020n (cm-3) tSi = 5nm tSi = 10nm

PAGE 197

182 Figure 6.21Davinci-predictedIDS-VGScharacteristicsofthe28nm nITFETwithNB(x)denedbyproles(a),(b),and(c)inFigure 6.17;tSi=10nm.Thepredictedcharacteristicsofthe constituentDGFinFETandSOIMOSFETareshownaswell. 0.00.20.40.60.81.0 VGS (V) 10-1010-910-810-710-610-510-410-3IDS (A/pitch) FinFET ITFET SOI MOSFET (a), (b), (c) VDS = 1.0V

PAGE 198

183 transversefield,andtheBOXfieldfringingisaccountedfor.Wefindthat DavinciunderpredictstheVtincreaseduetoquantization,andhencethe optimalNB(x),seeminglyprofile(b)inFigure6.17,isoverestimated; profile(c)ismoreoptimal.LowerNB(x)willincreaseIleak,ascanbe inferredfromcomparisonsofIDS(VGS)fortheSOIMOSFETs,theITFETs, andtheFinFETinFigure6.21,butthefin-baseleakagecanbecontrolled viarefinedprocessing.HigherIoffoftheITFETcanbeoptimallytradedoff for higher Ion, depending on the application. 6.4.2 UFDG Simulation Issues Now,withmoderatetSi=10nmthinenoughtoyieldanFDbody, asreflectedinFigure6.18,theITFETcanbesimulatedwithUFDGbya subcircuitcomprisingtheundopedDGFinFETandthedopedSGFD/SOI MOSFET.Further,itsperformancepotentialincircuitapplications,such as a 6T-SRAM cell can be examined with UFDG. Untilnow,thestrong-inversionformalismintheUFDGmodel wasdoneassumingneligibledepletioncharge;therfore,higher subthresholdslopeandVtoftheFDFETrequirecarefultuningofthe upperboundaryconditionofthemoderateinversionregion(viatheUFDG parameterSFACT)forcorrectpredictionsoftheon-statecurrents. Furthermore,thelatestcarriermobilityandballisticmodelsonlyapplies toUTBtransistorswithundopedbody,andthemoreempiricalmobility modelcanbeusedinstead;however,aneducatedtuningofthemobility parametersisnecessaryduetothegaussianprofilesassumedfortheUTB. Inaddition,tuningoftheBOXfield-fringingparametersintheUFDG

PAGE 199

184 modelisrequiredtoaccountfortheeffectofgaussiandopingprofiles,so thatthepredictedSCEsareinaccordwiththeDavincipredictions.More refinementsoftheUFDGmodeltoaccountforthebodydopingeffectsare desirableforunequivocalperformancepredictionsoftheITFETwith doped SOI body. TheDavincisimulationsdiscussedcanprovideabasisforamore elaborateexaminationwiththeUFDGmodelonscalabilityaswellason viability(includingsensitivityanalyses)incertainapplications,suchas anSRAMcell.However,thatworkisbeyondthescopeofthisdissertation. 6.5 Summary Anovel,hybriddevice(theITFET)thatincorporatestheplanar FD/SOIMOSFET(FDFET)intoFinFETtechnologytomoreefficiently utilizepitchareahasbeenexaminedwithourprocess/physics-based compactmodelUFDGand3-Dnumericalsimulations.Theundoped ITFET,comprisingaDGFinFETandanSGFDFETwithacommon, midgapmetalgate,yieldssignificantlyhigherdrivecurrentperpitchthan theFinFET.However,substantiveleakagecurrentduetotheungatedfinbasemustbesuppressed,andthiscanbedoneviaprocessingthatextends athinnerversionoftheFinFETgatedowntotheunderlyingBOX.Then, theoff-statecurrentofnanoscaleITFETsisgovernedmainlybytheSOI thicknessoftheFDFET,asinFD/SOItechnology,andhencetheminimum tSiachievable( @ 5nm)willultimatelynecessitateredesignoftheFDFET forscalabilityoftheITFET.Theredesignachievedby,e.g.,imprecise dopingoftheplanarSOIbody,whichincreasestheVtoftheconstituent

PAGE 200

185 FDFETandrelaxestheSOIbodythickness,wasexamined.Further scalingoftheITFETbeyondLgate=28nmisthereforeimplied.Withgood designofthestructure,theITFETcanyieldasignificantincreaseinIonperpitchwithlittleornoincreaseinIoff,yieldingsubstantivelyenhanced Ion/IoffrelativetotheFinFET.TheITFETcouldhavewidespread applications,especiallyincircuitsthatrequiredeviceratioing.Agood exampleistheFinFET-CMOS6T-SRAMcell,inwhichITFETsusedfor thepull-downnMOSFETscanensurecellstabilitywithnoincreasein layoutarea.UFDG/Spice3simulationsofsuchanSRAMcellwith28nm gatelengthsshowedoutstandingstaticnoisemargin,evenwithVDDas lowas0.4V.Further,moderateprocess-inducedvariations/mismatchesin theITFETstructuraldimensions(i.e.,tSi,wSi,andLg)werefoundtobe tolerable,withoutunderminingtheITFETbenefittotheSNMnor severely increasing the static power consumption.

PAGE 201

186 CHAPTER 7 A NOVEL 2-TRANSISTOR FLOATING-BODY MEMORY CELL 7.1 Introduction TheconventionalDRAMcell,withonetransistor(1T)andone capacitorrequiresacomplicatedstackcapacitororadeep-trench capacitor,whichleadstoprocessingcomplexityasthememorytechnology isscaled[Ohs02].So,aboutadecadeago,theconceptofacapacitorless1T DRAMcellthatutilizesthefloatingbodyofapartiallydepleted(PD)SOI MOSFETasstoragenodewasproposed[Wan93,Ohs02].Inthisfloatingbodycell(FBC),thememorystatesaredefinedbythebodybeingcharged oruncharged,andaresensedviathelinearchannel-currentdifference ( D IDS)thatresultsfromthethresholdvoltage(Vt)variationwiththebody chargecondition,orbodyvoltage(VBS)[Pel02].Thescalabilityofthiscell beyondthe50nmnodecomesintoquestionbecauseofcomplex,heavy channel/bodydopingdensityneededforSCEcontrol,aswellastheneed tosustainaPD,orpartiallyquasi-neutralbody.Further,theheavydoping enhancestrap-assistedjunctiontunnelingandseverelydegradesthe body-chargeretentiontime.Therefore,severalreportsona1Tfully depleted(FD)SOIDRAMcellhaveproposedtheideaofemulatingaquasineutralbodyinanundopedFD/SOIMOSFETbynegativelybiasingthe substrate/backgate[Kuo03,Ran04,Tan04].Suchamemorycellis

PAGE 202

187 potentiallyscalable,butlimitedbytheultimatethinness( @ 5nm)ofthe SOI ultra-thin body (UTB) [Tri03]. Mostrecently,a‘zero-capacitorRAM(Z-RAM)’cellbasedonthe FDdouble-gate(DG)FinFETstructureonSOIwasexperimentally fabricatedandstudied[Nag05];thisdevicecouldpotentiallyextendthe scalabilityofthe1T-FBCconceptmore.However,withtheSOIsubstrate biasedaslargeas-30Vtogettheneeded‘potentialwell’,asignal (programming)window( D IDS)wasmeasuredatonly~10 m AonamultiplefinLgate=100nmFinFET.Thislimitedmarginderivesfromthebasic floating-bodyeffect[Pel02]asimpliedbyourMIGFETanalysesimpliedin Chapter4,i.e., D Vt= r D VBS,wherethebodyfactorr @ 3toxf/tSiisdefined bythedevicestructureandistypicallylimitedtolessthan~0.3.Asin [Nag05],therefore,alargenumberoffins(andhencelayoutarea)would beneededforgoodsignalmargin( D IDS~W D Vt)intheFinFETtechnology; whereaslargewidthofthedevicewouldbeneededifthe1T-FBCis implementedinaplanarFD/SOIMOSFETasnoted[Ohs02,Ran04, Yos06]. Also,allthe1T-FBCconceptsmustrelyoncurrentsensing, ratherthanvoltagesensingasintheconventionalDRAMcell.Thelatter ispreferred;theformerrequiresmoresophisticatedsenseamplifiers,and consumesmorepoweraswell.Inthisreport,wethereforeexplorea different,two-transistor(2Tasopposedto1T)approachtoembedded memorybasedonfloating-bodychargestorage,onethatstemsfromthe ITFET structure studied in Chapter 6.

PAGE 203

188 7.2 The 2T-FBC Concept TheITFETtechnologynotonlyallowsflexiblecontrolofthe hybrid-MOSFETwidthforenhancedtotalcurrentdrive,butalsocan provideabodycontactfortheFinFET.Thishasinspiredusonanovelidea ofexploringthedesignofananoscaletwo-transistor(2T)FBC,utilizing thestoredhole-chargedynamicsinthebodyoftheFDDGFinFET.The planarSOIprovidesabodycontacttotheFinFET,andVBS,controlledby thebodycharge,isusedtodriveasecond,adjacentDGFinFETtoeffect thememorycell.Aswewillshow,the2T-FBCyieldsbettersignalmargin thanthe1Tcell,andvoltagesensingcanbeused.Hence,eventhoughtwo transistorsareneeded,thiscellcangivebetterlayoutefficiencythatthe 1T-FBC,which,asnoted,requiresseveraltransistorspercellfor acceptable margin. Ourproposed2T-FBCconcept,basedontheITFETtechnology, isillustratedinFigure7.1.Similartothewritingoperationsofthe1TFBC,holeswillbeinjectedintothebodyofthefirstconstituentFinFET (T1,inanITFETstructure)viaimpactionizationinthehigh-fieldregion neardrain,andevacuatedviafastcarrierrecombinationbypulsingthe drainnodenegatively.Toreadthedatastoredinthememorycell,the secondconstituentFinFET(T2)isdrivenwiththehole-charged/ dischargedbodystoragenode(B1),withtheplanarSOIoftheITFET structureprovidingtheB1-to-G2connection.Thememorystatescould, therefore,besensedviatheinduceddraincurrentvariationinT2witha currentsenseamplifier,asinthe1T-FBCcells,but,morepreferably,by

PAGE 204

189 Figure 7.1Aunit2TITFET/FinFETDRAMcellinamatrix integration,where‘B1’representsthebodystoragenodeof the first DG FinFET, T1 in an ITFET structure. ITFET ( T1 ) FinFET ( T2 ) B1 Word Line Source Line Bit Line 1Bit Line 2 (Ground)

PAGE 205

190 thevoltagelevelattheprechargeddrainnodeofT2,similartothesensing usedintheconventionalDRAMtechnology.Forthelattervoltagesensing, the2T-FBCDRAMcellwillhavetobedesignedsuchthatT2willbe turnedonandoffbythehole-charged/dischargedbodynodeinthe’and ’states,respectively.(NotethatsinceT2inverts,stored’and’ correspondtochargedandunchargedbodies,respectively,unlikeinthe conventionalDRAMandinthe1TFBCs.)Therefore,asinFigure7.1,we needtohaveabitline(BL1)connectingalldrainnodesoftheT1 transistorsalongthecolumnoftheDRAMarrayforprogramingthecells, andalsoanotherbitline(BL2)connectingalldrainnodesoftheT2 transistors along the column for sensing the data stored in the cells. LiketheFinFET-based1T-FBC,the2T-FBChasarobust structureforscaling,butunlikethe1T-FBC,itisoperatedinthecommon DGmodewithnoneedforlargesubstratebiasing.Further,fewerfins (smallerarea)areneededforthe2T-FBC.Forvoltagesensing,whichis notanoptionforthe1T-FBC,onlyonefin(i.e.,twoFinFETs)isneededas wedemonstratelater.Forcurrentsensing, D IDSismuchlargerinthe2TFBC,because D VBSdirectlydrives D IDSviaT2,incontrastto D Vt< D VBS(i.e.,r<1)defining D IDSinthe1T-FBC.Since D IDS~W D Vt,whereWis theeffectivewidthofthetransistor,WT2=rW1Twillyieldthesame D IDS; andsincetwoFinFETscomprisethe2T-FBC,the2T-FBC/1T-FBCarea ratioforthesamecurrentmarginisabout2r(~0.5).Eventhoughthe2TFBCrequirestwoFinFETs(persub-cell),asopposedtooneforthe1TFBC,ittakesuplessarea(<50%),irrespectiveofthetypeofsensingused.

PAGE 206

191 Inthisstudy,weexplorethedesignandfunctionalityofour proposed2T-FBCnanoscaleDRAMcell.Thevoltagesensingofthe memorystatesforthe2T-FBCwillbeexploredfirst,asitsimplementation isrelativelysimple,andwhencombinedwithavoltagesenseamplifier, thecircuitiscompact,aswellasarea-andpower-efficient.Thecurrent sensingofthememorystatesforthe2T-FBCwillalsobeexploredasan alternative,forperformanceadvantagesthatwillbeclarifiedlater.The currentsenseamplifiersaregenerallymoresophisticated,andconsume moreareaanddynamicpower[Ohs02];so,voltagesensing,notpossible with the 1T-FBC, is preferred. Allsimulationswillbecarriedoutwithourprocess/physicsbasedandcharge-basedgenericcompactmodelforDGMOSFETs,UFDG [Fos05],inSpice3.ThechargemodelinginUFDG,physicallylinkedtothe channel-currentmodeling,accountsfortheintegratedchargecomponents forallfiveterminals(i=D,S,Gf,Gb,andB)viachargeneutrality,and definestheterminalchargingcurrentsbasedonthequasi-static approximation: (1) which,forscaleddevices,properlyaccountsforalltranscapacitances;j= D,Gf,Gb,andB.TheequivalentnetworkoftheUFDGmodelis representedinFigure7.2.Theintrinsictransientbodynodalequation, which characterizes the charge storage dynamics, is expressed as dQ i dt --------Q i V js ----------jdV js dt -----------=

PAGE 207

192 ICHIBJT -IRGt(VB’D’) IRGt(VB’S’) D’ S’ B’ Gf Gb B D S IGi (w/ IGIDL) RSRB dQGf/dt dQD/dt dQS/dt dQB/dt dQGb/dt RDFigure 7.2Network representation for the UFDG model.

PAGE 208

193 (2) whereIGandIRrepresentallthecarriergenerationandrecombination currentslinkedtothebody,anddQB/dtisthebodychargingcurrent, definedbythecapacitances/transcapacitancesindicatedin(7.1).Tobetter conveythechargedynamicsofthe2T-FBC,wecanrewrite(7.1)and(7.2) as (3) whereCBk(k=D,S,Gf,Gb)representthecapacitivecouplingofthebody totheotherterminals;Gf=GbfortheDGmodeofinteresthere.Notefrom (7.3)thatCBk,and/orextrinsiccapacitance,mustbesufficientlyhighto enableenoughchargestorageforFBCfunctionality.Inthe1T-FBC,this requirementisactuallywhatnecessitatesthenotednegativesubstrate biasandthesubsequentaccumulation,whichyieldshighbody capacitance.Inthe2T-FBC,thegateofT2providestheneeded capacitance without requiring the accumulation. That is, from (7.3), (4) wherewehaveneglectedthefirsttwocharging-currentcomponentsin (7.3)(duetoultra-thinfin-bodythicknesswSi),havecombinedthelasttwo I G I R – dQ B dt ----------= I G I R – C BD dV BD dt --------------C BS dV BS dt -------------C BGf dV BGf dt -----------------C BGb dV BGb dt ------------------+++ = I G I R – C BG dV BG dt --------------C GT 2 () dV GT 2 () dt -----------------------+ =

PAGE 209

194 (duetoVBGf=VBGb=VBG),and(symbolically)addedtheextrinsicT2gate charging current. TheUFDGmodelalsoaccountsfortheparasiticBJTeffects [Yan04],drivenbytransientbodychargingcurrentduetocapacitive coupling,thermalgeneration,andimpact-ionizationcurrents,thelatterof whichischaracterizedbyanon-local,carriertemperature-dependent modelfortheionizationrateintegratedacrossthechannelanddrain [Kri96].Themodelthusallowsustophysicallyandcompletelysimulate the dynamic floating-body effects during the operation of the 2T-FBC. 7.3 Principles of the 2T-FBC Inthissection,weexaminetheworkingprinciplesofthe2T-FBC aswellasthoseofthe1T-FBCforcomparison.Inessence,bothcellsshare thebasicbodychargedynamicsandworkingprinciplesfortypicalcell operationsthatincludeprogramming,i.e.,writingeithera’or’into thebodynode,readingmemorystatesfromthebodynode,andholding memorystates.Thebodychargedynamicsinafloating-bodyMOSFETis not,seemingly,fullyunderstood,asreflectedinliterature.Inthemost recentstudies[Kuo03,Ran04]onthe1TFD/SOIFBC,thecapacityofthe bodytoholdtheexcessholesinducedbyimpactionizationhasbeen attributedtotheso-called‘deeppotentialwell,’whichnecessitatesthe negativelybiasedsubstrate/back-gate.Thisisactuallyamisconception, andthereforepartiallyinvalidatesthebasicunderstandingandapproach to designing the memory cell that have been published.

PAGE 210

195 Aswenotedby(7.4),thebodycanholdadequateholecharge whenCBG,or/andCG(T2)ishighenough.Inthe1T-FBC,whenanegative back-gatebiasinducesaccumulationinthebody,CBGbin(7.3)becomes high,asopposedtoCBGb@ 0whenthebodyisFD.IrrespectiveofCBk,VBStendstoapproachapositivesteady-statevaluedefinedbyIGandIRin (7.3)whenthebodyisbeingcharged[Fos95,Kri96].However,thisVBS> 0isnotusefulintheFBCapplicationunlessaCBkishighenoughsince theretentiontimefornormaloperation(i.e.,readandhold)isnotlong enough.Thisbasicprincipleunderliesthedesignprinciplesofour proposed2TITFET/FinFETDRAMcell,aswellasthe1TFD/SOIDRAM cell.Inourproposed2T-FBC,mainlythegatecapacitanceofT2givesthe neededbodycapacitance,withouttheneedforbias-inducedaccumulation. Todemonstratethebasicoperationofthe2T-FBC,weassumefor T1asingle-finITFETstructurethatiscomprisedofanLgate=28nmDG FinFETwithundopedbody(wSi=14nm,hSi=56nm)andmidgapgate,and aplanarSOIlayerthatonlyprovidesabodycontactfordrivingthegate ofT2,anadjacentDGFinFETidenticaltoT1butwithoutthebody contact.TheSOIcontactcouldeasilybedopedandtiedtothegateofT2 without any major modification of the ITFET processing [Mat05a]. Asnoted,thewrite’operationinvolvesimpactionizationinT1 athighdrainbias,whichinjectsholesintothefin-UTB.Therefore,an efficientwriting’operationwithproperbiasselectioniscriticalto achievefastprogrammingwithinafewnanosecondsaswellasgood enoughmarginbetweenthememorystatesfornormalcelloperation.To

PAGE 211

196 examineit,wesimulateandplottheUFDG-predictedimpact-ionization current(IGi)inT1versusgatebiasfordifferentVDSinFigure7.3.Forthe UFDGimpact-ionizationmodel[Kri96],wehaveassumedrepresentative valuesfortheimpact-ionizationparameters,i.e., a=2.45 x10-6cm-1and b= 1.92x10-6V/cm for a typical n-channel device, where (5) istheionizationrateinthechannelnearthedrain;Aisaconstant dependentonthecarrierenergy-relaxationlength,andTeandT0arethe carriertemperatureandlatticetemperature,respectively.Thereis uncertainty,though,in a and b foraquasi-planarFinFETstructure,as theassumedvalueswerederivedbasedonplanarMOSFET measurements.However,theyshouldberepresentative.NoteinFigure 7.3thatIGi(=(M-1)Ich,where(M-1)isdefinedbytheintegralof aGiover thehigh-Teregionnearthedrain[Kri96])forallhighVDSrisesfastasVGSisincreasedduetotheincreaseofchannelcurrent,andultimatelypeaks in/nearthemoderate-inversionregion,beforedroppinginstronginversion duetothedecreasingelectricfieldnearthedrain.Therefore,toachieve themaximumimpact-ionizationrateforfastwrite’operationatagiven highVDS,weneedtoproperlyselectVGS,i.e.,thewordline(WL)voltage, whichinfacthasnotalwaysbeendoneinpreviousFBCworks.Further, formoreenhancedprogrammingspeedandwidercellmargin,wecanuse a Gi a b AT e T – () ------------------------- – exp =

PAGE 212

197 -0.20.00.20.40.60.81.0 VGS (V) 10-1610-1510-1410-1310-1210-1110-1010-910-810-7IGi(A/fin) VDS = 1.2, 1.4, 1.6, 1.8VFigure 7.3UFDG-predictedimpact-ionizationcurrentversusgatebiasateachhighdrainbiasforthe2TFBC.Notethatwith hSi=56nm,IGiperfinheight(A/ m m)istheper-fincurrent given times about 18.

PAGE 213

198 higherVDS(BL1),limitedbythedevicereliability(hot-carriereffects,etc.) and power considerations. Then,towrite’efficiently,weneedtopulsethedrainnode (BL1)ofthebody-chargedT1negativelyenoughinordertoadequately forward-biasthebody-drainjunction(by @ 0.7V).Notethattheselection/ raisingofthegatevoltage(WL)beforehandalsoraisesthebodyvoltage viagate-bodycapacitivecoupling,furtherincreasingtheforwardbias (VBD)forefficientevacuationofholechargefromthebodyviafastcarrier recombination.Therateofdischargingasdefinedbytherecombination current(IR)intheUFDGmodelisexponentiallyrelatedtoVBD(orVBS) as follows [Wor99]: (6) viaparametersJR0,m,andSeff,whicharethejunctionrecombination coefficient,junctionrecombinationidealityfactor,andeffectivesurface recombinationvelocityinthesource/drain,respectively.Withtypical valuesassumed,i.e.,JR0=1x1011A/m,m=2,andSeff=105cm/s,asfora typicaln-channelFD/SOIMOSFET,thefirsttermin(7.6)tendstobe predominantformoderateVBS/D.Again,notethatuncertaintyinthese parametersforanon-planarFinFETstructureimpliessomeequivocation in the predicted characteristics of the 2T-FBC. I R V BSD () WJ R 0 V BSD mV T ------------------Wt Si qn i 2 N DSeff () -----------------------S eff V BSD V T ------------------exp + exp =

PAGE 214

199 Afterprogrammingthedata,WListhenturnedofftoanegative holdingvaluesothatthebodyvoltagedropsviagate-bodycapacitive coupling,andthebody-drain/sourcejunctionsbecomestronglyreversebiasedfordataholding;BL1issubsequentlyreturnedtogroundtodefine theholdingstates.Duringhold,however,BL1willbepulsedforwriting eithera’or’toothercellsconnectedtothesameline.Suchdynamic pulsingofBL1,whichcanbeconsideredasaccumulatedstaticdisturb, degradesthecellmarginandeventuallydefinestheretentiontimeofthe FBC.PositivepulsingofBL1forwritinga’toothercellstendsto enhancethethermalgenerationduetothereverse-biasedbody-drain junction,albeitslightly,intheundopedbodyofthecellinhold;whereas negativepulsingofBL1forwritinga’toothercellstendstoinduce carrierrecombinationinthebodyduetotheforward-biasedjunction. Therefore,toachievethebestdisturbandretentioncharacteristics,we wanttobringdownthebodyvoltageofT1viagate-bodycapacitive coupling to an optimum compromise by adjusting the WL holding value. NotethatbecauseofthenegativeWLholdingvoltage,theT1finbaseleakagecurrentisnotaproblemforthe2T-FBC.Typically,aT1gate voltageof-1Veasilypreventsthecarrierinversioninthefinbasethat,at theoffcondition,iscausedbyS/Delectric-fieldfringingintheunderlying BOX. Forgateoxidethicknessasthinas1nmthough,attentionmust bepaidtothegate-bodytunnelingwhenalargenegativegatevoltageis appliedonthegate,whichtendstodischargethebodyduringtheholding.

PAGE 215

200 Therateofdischargingissubjecttothepotentialdropacrossthegate oxide,i.e.,VGS-VBSfswhere Fsisthesurfacepotential,whichis virtuallypinned( @ -0.4to-0.5Vatthesourceside)foraccumulationinan undoped/lightlydopedbody[Tri05].Goodcapacitivecouplingofthebody voltagetothegatevoltagebeyondaccumulationis,therefore,criticalfor suppressingthebodydischargingduetotunnelingduringhold.Notethat boththeelectrontunnelingcurrentfromthemetalgatetothebody(JMeG) andtheholetunnelingcurrentfromtheaccumulatedbodytothegate (JVBhB)contributetothedischarging,asillustratedinFigure7.4.Witha metalgatewithmidgapworkfunction,theelectrontunnelingbarrierfor JMeGismuchhigherthanthatforapolysilicongate,whichreducesJMeG; however,asthereisnoenergygapinthegate,JVBhBtendstodominate the gate tunneling current for relatively low gate bias [Hou04]. Toreadthedatastoredinthe2T-FBC,WLisselectedandraised, followedbytheriseofVBSinT1viagate-bodycapacitivecoupling. Dependingonthedataheld,VBSwillreachdifferentlevelsseparatedby thecellmargin.Forthe1T-FBC,thebitlineisraisedbyasmallamount, inordertodetectthelinearcurrentdifferenceeffectedbythedifferent thresholdvoltagesduetobodyeffect.However,forthe2T-FBC,therising VBSdirectlydrivesthegateofT2,whichisexpected,dependingonthe storeddata,orbodycharge,todischargeormaintaintheBL2voltagethat hasbeenpresettoacertainvoltageleveljustbeforereading.Thememory states,invertedandamplifiedbyT2,arethenreadoutfromBL2.A successfulread’operationwillcriticallydependonwhetherthe

PAGE 216

201 JMe GJVBhBEF EFFigure 7.4Band diagram of gate-body tunneling in accumulation.

PAGE 217

202 maximumamountofholechargeavailable,i.e.,thatinjectedintothebody duringimpactionization,sufficestoturnonT2anddriveenoughcurrent todischargeBL2withinafewnanoseconds.FortheFinFET-basedDRAM, thedraincapacitanceislow,andhencethebitlinecapacitanceismainly attributedtotheinterconnectcapacitance,whichsignificantlybenefits thedischargingrate.Further,wenotethataproperlydesignedvoltage sense amplifier will greatly accelerate the read. Aroughestimationoftheamountofholechargedensity(per area)storedintheT1body(andonCG(T2)ala(7.4))foraread’canbe made via ,(7) whichfollowsfrom(7.2);IGi,IGt(VBD),andIR(VBS)representthebody chargingcurrentsduetoimpactionization,thermalgeneration,and recombinationduringwritetime D t,respectively.WeassumeIGi@ 2.5x10-9(A/fin),whichroughlycorrespondstothepeakingimpact ionizationcurrentofthesingle-finITFETatVDS=1.4VinFigure7.3;and IGt(VBD)<
PAGE 218

203 (e.g.,thegatecapacitanceofT2)isneededtorenderthe2T-FBCoperable aswediscussed.So,forawritingpulsewidthof D t=10ns,wehave approximately ;(8) wehavesubstitute dL=28nman dW=hSi=56nm.Thefactthatthe estimatedQbodyin(7.8)iscomparabletoatypicalstrong-inversioncharge densityimpliesasuccessfulread’operationviaT2.Withproper selectionofBL1andWLforimpactionization,wecontroltheamountof bodychargingduringwriting,andwithproperselectionofWLduring reading,wecontroltheVBSriseusedtodrivethegateofT2.Notethat duringreading,itisnotadvisabletoraiseVBSexcessivelyviagate-body capacitivecoupling(e.g.,higherthanthatobtainedduringprogramming) astheenhancedcarrierrecombinationratewillquicklydegradethesignal margin via loss of hole charge. Asnoted,severelossofholechargecouldoccurduringthehold condition,eitherasaresultofcarrierthermalrecombinationsubjectto frequentBL1disturb,orgate-bodytunnelingleakagecurrentthroughthe thingateoxidewhenexcessivepotentialisdroppedacrosstheoxidelayer. Inlightof(7.8),wecanthenroughlyestimateforT1theamountofbody leakagecurrentthatcanbetoleratedforagivenholdretentiontime,say ~100 m s to discharge only ~1% of the total body charge: Q body I Gi WL -------t D 1.6 x 10 6 – Coulombcm 2 q 10 13 cm 2 – ~ =

PAGE 219

204 ,(9) whichisexactlysixordersofmagnitudesmallerthanthatusedforIGiin (7.8).Tokeeptheleagagecurrentbelow(7.9)andguaranteegoodhold/ disturbcharacteristics,thebodyvoltagemustbebroughtdowntowithin @ 0.5VoftheBL1minimum,asimpliedby(7.6).Further,thegate tunnelingcurrent(forbodyaccumulation)hastobelessthan @ 10-4A/cm2inordernottounderminethememorystatesduringa1%holdtimeofat least 100 m s. 7.4 Simulations of 2T-FBC Operation for Voltage Sensing 7.4.1 Significant Impact of T2-Gate Fringe Capacitance Asnotedin(7.4),theT2gatecapacitanceenhancesthecapacity ofthebodytoholdsufficientholechargefornormaloperationofthecell. However,excessivecapacitanceaddedtothebodywillalsonecessitate largebodycharginganddischargingcurrentinordertoachieveefficient writingwithinalimitedamountofprogrammingtime.Further,the capacitivecouplingofthebodynodetoBL1andWLwillbeundermined. Toexaminethewholesetofoperationsofthe2T-FBC,weuseUFDGin Spice3tosimulatethebodyvoltagevariationinT1,withtime-dependent gate/drainpulsingforprogramming/readingoperationsofthecell.Forthe followingsimulations,weassumeprogrammingpulsesof10ns(including 1nsriseandfalltimes),and,forqualitativeunderstandinginitially,we alsoassumethesamedurationforthereadingpulses.Wealsoassumean I leak WL Q body x 10 2 – t RET --------------------------------1.6 x 10 4 – Acm 2 WL 2.5 x 10 15 – A ==

PAGE 220

205 idealB1-G2contactwithnoresistance;i.e.,VG(T2)=VB1.Theactual resistanceintheITFETstructure,anditseffectsonthe2T-FBC performance,willhavetobeexaminedinthefuture.Clearly,itmustbe minimizedtoavoidlong,underminingtimeconstantsintheT2gate circuit. Mostrecently,theUFDGmodelhasbeenupgradedwithanew parasiticcapacitancemodel[Kim06],whichaccountsforbothouterand innerG-S/Dfringecapacitances(Cf)innonclassicalMOSFETs.Asverified by2Dnumericalsimulations,Cfsubstantiallyincreasesthegate capacitanceinallregionsofbias.TheUFDG/Spice3-predictedgate capacitance-voltagecharacteristicsforourLgate=28nmDGFinFET,with andwithouttheparasiticcapacitance,alongwiththatpredictedwith MEDICIatVDS=50mVarepresentedinFigure7.5.Notesignificantly morefringecapacitanceexistsinthelower-VGSregion;forstrong inversion, the innerfringe component is effectively screened out. ToevaluatetheimpactofCfonthe2T-FBC,transient-simulation resultsofthe2T-FBCpredictedfirstwithouttheparasiticcapacitanceare showninFigure7.6,where,basedonthepreviousdiscussion,wehave usedgateanddrainbiasesforalloperationsassummarizedinTable7.1. TheUFDGmodelpredictstherighttrendoftheT1body(B1)-voltage variationwithgateanddrainbiasing.TheB1voltageiscloselycoupledto theG1,orWLvoltageovertherangeofgateswing,whichgoesuptoa maximum0.44V;whereastherateofbodycharginganddischargingas definedbyIGiandIRduringwritingiscontrolledviaproperD1,orBL1

PAGE 221

206 0.00.20.40.60.81.0 VGS (V) 0.0 0.5 1.0 1.5 2.0CG (fF/ m m) Inner + outer Cf’s outer Cf MEDICI UFDG w/ Cf’s UFDG w Cf’s UFDG w/o Cf’s w/ Les=Led = 4nmFigure 7.5UFDG-predictedgatecapacitance-voltagecharacteristics fortheLgate=28nmnFinFET,withandwithoutthe parasiticG-S/Dcapacitance,alongwiththatpredictedwith MEDICIatVDS=50mV.Forcomparison,theUFDG/Spice3predictedCG-VGScharacteristicoftheFinFETwith assumed4nm(=Les=Led)effectiveG-S/Dunderlapisalso shown.VDS = 50mV

PAGE 222

207 010203040 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 48Voltage (V)Time (ns)Figure 7.6UFDG-predictedtransientoperationresultsofthe28nm 2T-FBCwithouttheparasiticG-S/Dcapacitance.Forread operations, BL2 is precharged to 1.0V. BL1 WL B1 BL2Write 0 Hold 0 Read 0 Hold 0 Write 1 Hold 1 Read 1

PAGE 223

208 pulsingduringprogramming.Hereforthegivenbiases,aprogramwindow (orsignalmargin)of @ 0.5Visobtained,asindicatedbythedifferenceof the B1 voltage between the read ’ and read ’ operations. NoteappropriateWLpulsing(to0.1Vhere)for‘read’isneeded toraisetheB1voltagetoalevelwellaboveorbelowVtofT2forstate’ or’.Thisoperationisconfirmedbythepredictedtransientvoltage outputsensedatthedrainnodeofT2,i.e.,BL2,inFigure7.6,whichneeds tobeprechargedbeforereadingeithera’or’.Hereaprechargevoltage VDD=1.0Vwasselected.Indeed,withtheT1bodycharged(stored’), BL2dropsquicklywithin4nsofgatepulsing-upforread,astheB1voltage turnsonT2;thiscorrespondstoaread’.WiththeT1bodydischarged (stored’),BL2remainsatitsprechargedvalue(1.0V)astheB1voltage fallsfarshortofVt;thiscorrespondstoaread’.Efficientreadsofboth ’and’havebeensuccessfullydemonstratedwithreasonablepulsing biases.Write ’ Write ’ Read (1V, 0V) (w/ BLr precharge) Hold WL0.43V0.43V0.1V-1V BL1(BLw)1.4V-1V00 BL2( BLr)00(1V)0 Table 7.1Word-lineandbit-linebiasesappliedforvoltage-sensingoperation of the 28nm 2T-FBC.

PAGE 224

209 Next,wecheckonoperationofthecellwiththeparasiticG-S/D fringecapacitance.TheUFDG/Spice3transient-simulationresultsofthe 2T-FBCareshowninFigure7.7,wherethesamesetofbiasesinTable7.1 areused.Theimpactofthefringecapacitanceontheresultsissignificant. BoththeratesofB1voltagerisingandfallingduringholeinjection/ evacuationareseverelydegraded,duetothecharginganddischargingof thesubstantiveparasiticcapacitanceofT2.Asaresult,theB1charging anddischargingisincomplete,andseverelossinthesignalmarginoccurs, mainlybecauseBL2remainsfiniteduringtheread’.Theincomplete dischargingofBL2resultsbecausetheholechargeintheT1bodymust supporttheT2fringe-capacitivecharge,yieldinglessT2inversioncharge. Further,theT1gate-bodycapacitivecouplingiscompromised,which rendersitdifficulttobringdowntheB1voltagetoanacceptablenegative levelforeffectiveholding,asdiscussedintheprevioussection.Notealso theB1voltagedegradesbymorethana100mVintheread’pulsing. Evidently,theaddedG-Dfringecapacitancehasresultedinastronger capacitivecouplingbetweenB1andthedrainnodeofT2,asBL2is prechargedanddischargedduringread.Thistransientdoesnotinvolve lossofbodycharge,andhencewouldnotbedetrimentaltothenormal functionalityofthe2T-FBCthough.However,theaddedG2-D2capacitive couplingtendstoraisetheB1voltageasBL2isprechargedforaread’, whichactuallydegradestheB1voltagewindow,ormargin.Thereforea morenegativeBL1biasisneededtoreliablywritea’.Clearly,theG-S/

PAGE 225

210 010203040 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 48 Time (ns)Voltage (V)BL1 WL B1 BL2 Figure 7.2UFDG-predictedtransientoperationresultsofthe28nm 2T-FBC,withtheparasiticG-S/Dcapacitance.Forthe read opeations, BL2 is precharged to 1.0V.Write 0 Hold 0 Read 0 Hold 0 Write 1 Hold 1 Read 1

PAGE 226

211 Dparasiticfringecapacitanceshouldbeminimizedforreliable,efficient operation of the 2T-FBC. 7.4.2 Design to Suppress the Fringe-Capacitance Effect IncorporatingG-S/DunderlapintotheFinFEThasbeenshown tosignificantlyreducetheparasiticfringecapacitanceduetothelarger physicaldistancesbetweengateandsource/drain[Kim06].Weincludein Figure7.5theUFDG/Spice3-predictedCG-VGScharacteristics,atVDS= 50mV,oftheLgate=28nmFinFETwithassumed4nm(=LES=LED) effectiveG-S/Dunderlap.Thefringecapacitanceisreducedsubstantially inweakinversionbytheunderlap,butvirtuallyunaffectedinstrong inversion.Nevertheless,suchreductionshouldbenefittheperformanceof the2T-FBC.However,theT2currentdrivetendstobedegradedwiththe underlapsduetotheenhancedsource/drainresistance[Tri05c],which wouldtendtoslowdownaread’.Adesigntrade-offisnecessary,butan underlapshouldalleviatethenotedfringe-capacitanceproblemofthe2TFBC, and should be investigated in the future. Alternatively,apragmaticthickergateoxidewouldreducethe fringecapacitance,althoughitalsoweakensthegate-bodycapacitive couplingaswellasdegradestheT2drivecurrent.Weexaminethisdesign trade-offforthe2T-FBC,notingitalsowillreducethegate-bodytunneling leakagediscussedearlier.Thethickeroxidewillrequireredesignofthe device,suchasthinnerwSi,tomaintainrelativelythesameamountof SCEsandthereforethesameVtofT2.Toillustrate,weplotinFigure7.8

PAGE 227

212 0.00.20.40.60.81.0 VGS (V) 10-1010-910-810-710-610-510-4IDS (A/pitch) tox = 2nm, wSi = 11nm (design II) tox = 2nm, wSi = 14nm (design III) tox = 1nm, wSi = 14nm (design I) VDS = 0.05V VDS = 1.0V Figure 7.3UFDG-predictedIDS-VGScharacteristicsoftheLgate= 28nmFinFETcontrastedwiththoseofdeviceswith thicker tox, with wSi varied.

PAGE 228

213 theUFDG-predictedcurrent-voltagecharacteristicsoftheLgate=28nm FinFETwithtoxincreasedto2nmandwSireducedto11nm(designII), comparedwiththecharacteristicsoftheoriginaldesign(I)andwiththose ofanotherone(designIII)withthethickertoxandtheoriginal,thicker wSi.NotethatIonisreducedbyonly @ 25%bythethickertox,andthatthe thinner wSi is needed for Ioff (SCE) control. Thereducedgate-bodytunnelingaswellasbetteroxide reliabilityaffordedwiththethickertoxalsoenableuseoflargerbiasesto furtherremedythe2T-FBCperformanceissuesreflectedinFigure7.7. Thatis,theinsufficientB1voltagelevelforstored’canactuallybe recoveredbyusinghigherBL1voltageduringholeinjection,andthe excessiveB1voltagelevelforstored’canbesuppressedviamore negativeBL1voltageduringholeevacuation;whereasthecompromised gate-bodycapacitivecouplingcanbere-adjustedwithanenhancedgate swing,inordertobringdowntheB1voltageforeffectiveholding.Alower prechargedBL2voltageisalsopreferred.Itnotonlyreducestheamount ofB1-voltagevariationduetoBL2charging/dischargingviatheG2-D2 fringe-capacitancecoupling,whichtendstodegradetheB1voltagelevel duringaread’,butitalsominimizesanyimpactionizationthatmay occurinT2,whichcanpurturbtheB1voltageviacapacitivecouplingas well during continuous read. Toillustratethebenefitofthethicker-toxdesign,were-adjust the2T-FBCbiasesassummarizedinTable7.2,andplottheUFDG/Spice3-

PAGE 229

214 predictedtransientsimulationresultsinFigure7.9,withBL2precharged to0.5Vbeforereading.WeselecteddesignIIforbothT1andT2.Herethe drainbiaseswereselectedtoguaranteebothanefficientread’andread ’withagoodmarginwellbelowandaboveVtofT2,respectively.TheWL holdingvoltagehas,however,beenloweredto-2.2V,inordertobring downtheB1voltagetowithin0.5VoftheminimumBL1voltage(for writing’)tomaintaingoodretention/disturbcharacteristics.Note, however,thenegativeBL1voltageforawrite’herecanactuallybe relaxedmore,solongastheB1voltagelevelduringread’isnegligibly reducedduringthedischargingofBL2.Forexample,ifwecanrelaxBL1 to-1V,allowingforaslightdischargingofBL2duringaread’as illustratedinFigure7.7,thentheWLholdingvoltagecanberelaxedupto -1.6V,whichissignificantlyhigherthanthe-2.2Vweusedforthe simulations of Figure 7.9.Write 0 Write 1 Read 0, 1 (w/ BL2 precharge) Hold WL0.43V0.43V0.0V-2.2V BL11.45V-1.3V00 BL2000V, 0.5V0 Table 7.2Word-lineandbit-linebiasesappliedforvoltage-sensing operation of the redesigned 28nm 2T-FBC.

PAGE 230

215 010203040 Time (ns) -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5Voltage (V) 48Figure 7.3UFDG-predictedtransientoperationresultsofthe28nm 2T-FBCwiththeparasiticG-S/DcapacitanceasinFigure 7.7,butalsowiththickergateoxideandwiththeWL/BL biasesreadjustedasgiveninTable7.2.Fortheread operations, BL2 is now precharged to 0.5V. BL1 WL B1 BL2 Write 0 Hold 0 Read 0 Hold 0 Write 1 Hold 1 Read 1

PAGE 231

216 7.4.3 Issues with Device Reliability and Data Retention Thelargemagnitudesofgate(WL)holdingvoltageanddrain (BL1)voltagewouldnormallyraiseconcernaboutthedevicereliability, e.g.,withregardtogate-oxidebreakdowninthelongterm.However,the amountofbodyvoltagethatcapacitivelyfollowsthegatevoltage,aswell asthefiniteflat-bandvoltage(VFB=-0.29V)andsurfacepotential,greatly reducethepotentialdropacrossthegateoxide.Thethickeningofthegate oxidefurtherrelievesthelong-termDCstress.Withproperdesignthen, devicereliablitiyshouldnotbeproblematic,especiallywiththerelaxed biases as mentioned. Thegate-bodytunnelingcurrent,withthegivenmagnitudeof VGBashighas1.4V,tendstodischargethebodyduringhold,andmustbe limited.Asdiscussedpreviously,agatetunnelingcurrentof @ 10-4A/cm2canbetolerated.Indeed,iftheSiONgatedielectriccouldbereplacedwith highk dielectric,thetunnelingcurrentwouldnotbeaproblematall [Hou04].However,thethick-toxdesigntradeoffthatwesuggestedcanalso beeffectiveinlimitingthegatecurrent.Thegatetunneling-current formalismisnotyetintheUFDGmodel,andthereforefurther examination in this regard is necessary. Assumingthatthegatecurrentisadequatelylimited,wefurther checkthedisturbcharacteristicsofthe2T-FBCofFigure7.9,asgood retention/disturbcharacteristicsunderholdconditionsareessentialto achieverobustcelloperation.UFDG/Spice3-predictedretentionresults (i.e.,transientVB1)emulatingworst-casedisturbconditionsatroom

PAGE 232

217 temperaturearepresentedinFigure7.10,wherethe2T-FBCwithbiases usedinFigure7.9andsummarizedinTable7.2areused.WhenWLis maintainedat-2.2V,andB1isexposedtoBL1fixedatpositiveand negativevoltagescorrespondingtoprogrammingothercellsinthesame column,theretentionisgood,yetmuchworsethanthatfornormalWL andBL1switching.ThesimulationsshowthatthechargedbodyofT1does notlosesubstantivechargeforabout100 m swithafixedVDS=-1.3V disturb,duetoonlymoderateforwardB1-D1junctionbias(VBD~0.5V); whereasthedischargedbodyonlystartstobeslightlychargedatabout 10mswithaVDS=1.45Vdisturb.Evidently,withthegivenbiases,agood retentiontime(tRET)ofatleast100 m sisyieldedbythe2T-FBC.The relativelylongtRET,definedbytheundopedB-S/Djunction recombination/generationpropertieswithG-S/Dunderlap,reflectsa significantadvantageoverthe1TPD/SOIFBC,forwhichtRETisseverely reducedduetooverlapandhighbodydopingdensity,andtheGISL/GIDL, junctiontunneling,aswellashighratesofrecombination/generationthey imply.ToachievelongertRETinthe2T-FBC,amorenegativeWLholding voltagewouldbeneededtofurtherbringdowntheB1voltageandreduce the carrier recombination rate during the negative-VDS disturb. Similarly,thedynamicpulsingofWLduringreadoperationon othercellswillalsodisturbthestoredchargeandVB1.Weemulatethis disturbonbothmemorystatesatroomtemperatureascontinuous‘read’, i.e.,WLisraisedtoandmaintainedat,inourcase,0V.TheUFDG/Spice3predictedresultsareshowninFigure7.11.Thedegradationofthe

PAGE 233

218 10-710-610-510-410-3Time (ns) -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2B1 Voltage (V) VDS = -1.3V disturb for charged-body state VDS = 1.45V disturb for discharged-body state VDS = 1.45V disturb for discharged-body state VDS = -0.8V disturb for charged-body state read via current sensing read via voltage sensingFigure 7.4UFDG-predictedretention/disturbcharacteristics,or VB1(t)duringholds,ofthe2T-FBC,emulatingtheworstcase BL1 (VDS) disturb conditions.

PAGE 234

21910-710-610-510-410-3Time (ns) -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8B1 Voltage (V)Figure 7.5UFDG-predictedcontinuous‘read’ofthe2T-FBC, emulatingdataretentionduringdisturbsduetoreading other cells. Continuous ‘read’ for charged-body state Continuous ‘read’ for discharged-body state read via voltage sensing read via current sensing

PAGE 235

220 charged-bodyVB1withtimeisexpected,duetotheforwardbiasingofboth theB1-D1andB1S1junctions,butitisnotsubstantiveuntilabout100 m s; thedischarged-bodystatedoesnotdegradeatallwithinthesimulated 5ms.Thedegradation,orrecombinationrateduringread’correlates withhowstronglythebodycapacitivelycouplestootherterminalsduring read,asimpliedby(7.2),whichdefinestheread’retentionofthecell. TheCf-enhancedCG2addedtothebodystoragenodeactuallyimproves this retention time. Thedischarged-bodystateismuchmorestable,asthereareno apparentbodychargingmechanismstoundermineitduringread;the junctionthermalgenerationrateisverylow.Note,however,careshould betakenthattheamountofprechargedvoltageonBL2islowenoughso astonotinduceexcessiveimpact-ionizationcurrentinjectedintothebody ofT2.Thiscurrentwouldbemuchlessthan10fAat0Vgatevoltagefor BL2prechargedtolessthan1V,asindicatedinFigure7.3.However,over thelongretentiontime,itwouldtendtodisturbthememory’statein theT1bodystoragenode,whichiscapacitivelycoupledtothebodynode of T2. AcellreadtRET~100 m shasbeenpredictedforthe2T-FBCwith thegivenbiases.Note,however,thesimulationsdonotreflectthepossible dischargingmechanismsofstate’duetochargepumpingbytheconstant WLdisturb[Ohs06].This‘quasi-nondestructive’readoutneverthelessis differentfromthedestructiveread-outoperationintheconventional1T-

PAGE 236

221 1CDRAMcell,andcanbemadeadvantageousfordesignefficiencyofthe senseamplifier[Ohs06].Infact,asenseamplifierexploitingthisfeature wasdesignedsoastoreplenishtheholesthatarelostbythedisturbin everyreadandwritecyclein[Ohs06],whichenablesreducedrefreshbusy rateaswellaslowpoweroperation.Similarly,thedesignofsense amplifierforthe2T-FBCisalsoanimportantdesigncomponent,whichis, however,beyondthescopeofthisdissertation.Itcanbeessentialtothe viabilityofthecell,asthemodernnanoscaleDRAMtechnologyrequires that refresh cycle time be as high as 64ms [ITRS05]. 7.5 Simulations of 2T-FBC Operation for Current Sensing Sofar,ourfocushasbeenonvoltagesensingofBL2,which requiresthattheholechargethatcorrespondsto’and’beabletoturn onandoffT2.Therefore,sufficientlynegativedrainbiasisrequiredto fullydischargethebodyforstate’,whichinturnnecessitateslarge negativegatebiasinordertobringdowntheB1voltageduringhold.This willnotbenecessaryifwesensethememorystateviathedraincurrent differencethatflowsthroughthechannelofT2.(Suchcurrentsensingis theonlyoptionforoperationofthe1T-FBC.)Further,theB1voltage duringreadwillnotbeaffectedbythecapacitivecouplingfromBL2 charginganddischarging,asBL2isbiasedatafixedvoltage.TheUFDG/ Spice3-predictedtransientB1voltagevariationfortypicaloperationsof thecell,usingcurrentsensing,isshowninFigure7.12,wherewe prechargeBL2to0.5V.Notethegate/drainbiasesaresignificantly

PAGE 237

222 Figure 7.6UFDG-predictedtransientoperationresultsofthe2TFBCdesignedandbiased(asinTable7.3)forcurrent sensing.010203040 Time (ns) -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5Voltage (V)48 BL1 WL B1 Write 0 Hold 0 Read 0 Hold 0 Write 1 Hold 1 Read 1

PAGE 238

223 relaxedforthecurrent-sensingscheme,assummarizedinTable7.3.Both memorystatesnowturnonT2,andtheachieved D VBSbetweenthe memorystatesbecomes @ 0.45V.Notethat D VBScanstillbeenhancedby usingrelativelylargergate/drainbiasing,sothatthefullychargedbody statecanstronglyturnonT2.TotestthecurrentdifferenceinT2asa result,weplotthetransientcurrentforthecorrespondingoperation sequenceinFigure7.13.Agoodcurrent-sensingmarginof~13 m Afromthe 2-FinFETcellispredictedduringread.Toattainsuchamarginwiththe 1T-FBC, at least four fins would be needed [Nag05]. Wealsoexaminethedisturbcharacteristicsunderthehold conditionsforthecelldesignedforcurrentsensing,whenWLis maintainedat-1.3VandthecellisexposedtotheBL1switchingdueto writingothercells.TheUFDG/Spice3-predictedresultsareincludedin Figure7.10.Asexpected,similarcharacteristicstothoseobtainedwith thevoltage-sensingschemearepredicted,astheVBDinT1duringdisturb inbothschemesisdesignedtobecomparable.Notewithvoltagesensing,Write 1 Write 0 Read Hold WL0.48V0.48V0.3V-1.3V BL1(BLw)1.45V-0.8V00 BL2( BLr)000.5V0 Table 7.3Word-lineandbit-linebiasesappliedforcurrent-sensing operation of the redesigned 28nm 2T-FBC.

PAGE 239

224 Figure 7.4UFDG-predictedtransientcurrentcorrespondingtothe 2T-FBCoperationsequenceinFigure7.12.Agoodcurrent sensing margin of @ 13 m A is predicted. 010203040 Time (ns) -5 0 5 10 15 20IDS(T2) (A/cell) 48Write 0HoldRead 0 Hold Write 1 Hold Read 1 @ 13 m A

PAGE 240

225 tREThastobedefinedrelativetotheVtofT2;whereaswithcurrent sensing,tRETiscustomarilydefinedasthetimewhenonlyhalfofthe originalprogramwindowstillremains,whichisamorerelaxeddefinition. AlongertRETofabout1msispredictedforthecurrent-sensingscheme, butthemarginisunderminedrelativetothatofthevoltage-sensing design. Similarly,weaddtoFigure7.11theread-retention characteristicsofthecelldesignedforcurrentsensing,i.e.,whenWLis raisedtoandmaintainedat0.3V.Thecharged-bodyvoltagetendstodrop earlierthaninthecelldesignedforvoltagesensingduetoabitlargerVBSandVBDduringread;nevertheless,areadtRETofmorethan100 m sis achieved. 7.6 Summary and Discussion of Pragmatic Design Issues Anovelmemorycellbasedonfloating-bodychargestorate,the 2T-FBC,hasbeenpresented.Oursimulationsoftheoperationofthe2TFBChavedemonstrateditsfeasibility,buthavebeendonewithafew majoruncertaintiesassociatedwithUFDGmodelparametersthatwere previoulsyevaluatedbasedonplanarSOIdevices.Theimpact-ionization andcarrier-recombination/generationparametersfornon-planar FinFETsarenotknownnowbecauseofalackofreliablemeasureddevice data.AnenhancedJRO,forexample,wouldnecessitateredesignofthe biasingconditions,butingeneralwouldtendtoworsentheretention characteristicsduringreadandhold.Goodcontroloftheprocessing conditionsforminimizedrecombinationrateinthejunctionregionsis

PAGE 241

226 thereforecritical.Westress,however,thatduetotheundopedUTB,the retentioncharacteristicsshouldbemuchbetterthanthoseofthe1T-FBC with high body doping density. Thebiasingconditionsneededarealsodefinedbytheamountof capacitivecouplingofthebodystoragenodewiththeotherterminals,as wellastheimpact-ionizationandrecombination/generationcurrents.The substantialgatefringecapacitanceinT2thereforenecessitatesrelatively largegate/drainbiases,whichraiseconcernsofdevicereliabilityandgatebodytunneling.However,acelldesignedwiththickergateoxide,andwith G-S/Dunderlap,hasreducedfringecapacitancewithgreatlyimproved device/cellreliability.And,thebiasingconditionsarerelaxed significantly. Notealsothat,comparedtotheconventional1T-1CDRAMcell, thereismoreactivepowerconsumptioninboththe1T-FBCandthe2TFBCduetothesubstantialchannelcurrentthatflowsduringthewriting operations.Onewaytoreducethiscurrent,assuggestedin[Yos06],isto useGIDL,insteadofimpactionization,toinjectholesintothebodyduring programming.TherequiredoverlapstructurefortheGIDLmechanism, however,wouldnecessitatemorestringentbiasingconditionsforour2TFBCduetotheextraamountofgateparasiticcapacitanceintroducedas aresultoftheoverlapstructures.Nevertheless,itisadesignoptionthat wouldmeritstudy,perhapsforcellsdesignedforcurrentsensing.Inour design,wehaveusedrelativelylowgate-overdrive,andlowdrainbiases duringprogrammingofthecellwithoutcompromisingfunctionalityofthe

PAGE 242

227 cell, and thereby minimized the power consumption. Insummary,the2T-FBChasgreatpotentialtocompetewiththe 1T-FBCastechnologyscales.Thelattercellrequireslargesubstrate biasingand/oroperatesinsingle-gatemode,andreliesonthecurrentsensingschemewithsignalmargin (D IDS~Wr D VBS)limitedbythebody factor(r)anddevicewidth(W).The2T-FBCoperatesinthecommonDG modewithnoneedforlargesubstratebiasing,andismoreflexibleinits sensingscheme,allowingpreferredvoltagesensing.Further,itrequires fewfins,i.e.,smallerarea(<50%ofthatofthe1T-FBC)fornormal functionalityofthecell,irrespectiveofthetypeofsensingused.For voltagesensing,onlyonefin(i.e.,twoFinFETs)isneeded;forcurrent sensing, D IDSismuchlargerinthe2T-FBCbecause D VBS(> D Vt)directly drives D IDSviathesecondtransistor.Infact,the2T-FBC/1T-FBCarea ratio for the same current margin is about 2r (~0.5). Tofurthervalidatethefeasibilityofthe2T-FBCthough,more pragmaticdesignofthe2T-FBCcellwithexperimentalknowledgeofkey deviceproperties,suchascarriergenerationandrecombinationrates,will benecessary,especiallyathigher(typical)operatingtemperatures. Generallyspeaking,higheraimpact-ionizationrateisdesirable,whereas ahighercarrierrecombinationratetendstodegradetheretention characteristicsofthecell,andthereforeshouldbeminimizedthrough technology,suchasachievingagood-quality(low-defect)Sifinand interfacewiththeoxidelayer.Furthermore,pragmaticstructuraldesign oftheITFET,suchasusingthickergateoxideand/orgateunderlap/

PAGE 243

228 overlap,andpreciseknowledgeormodelingofgate-bodytunneling currentintheUFDGmodelarealsorelevantandneededfortheoptimal designofthe2T-FBC.Inaddition,agoodsenseamplifiercircuitdesign thatutilizesthefeatureofquasi-nondestructivereadouteffectively reducestherefreshbusyrate,andthereforecanbeessentialtoachievea viableDRAMtechnologythatmeetstheITRSrequirements.And,finally, process-inducedvariations,forexampleofthegatelengthaswellasSi-fin thickness,whichcanseverelyimpactVtofT2andthereforecausefailure in read operations, must be controlled.

PAGE 244

229 CHAPTER 8 SUMMARY AND SUGGESTIONS FOR FUTURE WORK 8.1 Summary Thisdissertationaddressedphysicalmodelinganddesignissues ofnonclassicalnanoscaleCMOS,includingbulk-SiandPD/SOICMOS withbiaxiallystrainedchannels,independent-gate(double-gate) MOSFETs,andadouble-gateFinFET-basedhybridMOSFET,withregard tosomepragmaticapplicationstodigitalandanalogcircuits.Themajor contributions of the research are summarized as follows. InChapter2,thresholdvoltageshifts( D Vt(SS))inbiaxially strained-Si/Si1-xGexCMOSdevices,definedbytheshifted2-Denergy subbandsandmodifiedeffectiveconduction-andvalance-banddensitiesof states,werecarefullystudied.Increasedelectronaffinityaswellas bandgapnarrowingintheSSlayerwerefoundtobepredominant componentsof D Vt(SS),whichisgenerallylesssensitivetothemodified DOSeffects.Themodeling,forbothn-channelandp-channelSSdevices, givesimportantphysicalinsightsonhowthestrain,inadditiontothe quantization,shiftsthe2-Dsubbands,andhowthevariedthreshold surfacepotentialandtheshiftedflat-bandvoltagedefine D Vtn(SS)(x)and D Vtp(SS)(x).Theimplementationofthestrained-SioptionintheUFPDB modelfurthernecessitatesthemodelingoffourotherprocess/physics basedparametersthatrelatetotheenhancedtransportpropertiesin

PAGE 245

230 strained-Sichannels,aswellastheincreasedareacomponentsofsource/ drainjunctioncapacitance.Additionalmodelingoftheperipheral componentsofsource/drainjunctioncapacitanceinstrained-SiPD/SOI MOSFETs,andseveralrecombination-generationmechanismsrelatedto thefloating-bodyeffects,whichareaffectedbythenarrowedbandgap ( D Eg), were also accounted for with our UFPDB model. InChapter3,deviceandcircuitsimulationsusingUFPDBin Spice3weredonetoprojecttheCMOSspeed-performanceenhancement thatcanbeexpectedfromstrained-SichannelsonrelaxedSi1-xGexbuffer layersinbulkSiandPD/SOICMOS.TheSiGeoptioninUFPDBuses parametersrelatedtocarriermobilityandvelocity,anddefinesthe reducedthresholdvoltageswithinreasonableuncertainties,allofwhich areevaluatedbasedontheGecontentx.Themodifiedbandstructure necessitatesanincreaseinthresholdvoltageforIoffcontrol,and simulationsweredonebasedonthiscontrolbeingeffectedviaincreased channeldopinginbothn-channelandp-channeldevices,andviap+polySiGegatesforthepMOSFETs.UnloadedCMOSring-oscillator simulationsshowthattherelativespeedperformanceenhancementis severelylimitedbytheneedtoredesigntheSSnMOSFETviaenhanced channeldoping,andbythebarelyimprovedholemobilityathigh transversefieldintheSSpMOSFET.Thesimulationsalsoquantifiedthe significantspeedlossforstrained-Si/SiGeCMOSonbulkduetothe increasedarealcomponentsofsource/drainjunctioncapacitance.Thisloss isavoidedinstrained-Si/SiGeCMOSonthinSOI,andhenceanadditional

PAGE 246

231 speedadvantageofPD/SOIoverthebulk-Sicounterpartwas demonstrated via UFPDB/Spice3 simulations. InChapter4,importantphysicalinsightsregardingdesignand performanceofindependent-gateFinFETsweregainedfromIDS-VGfScharacteristicsmeasuredfromtheMIGFETtechnologyandpredictedby ourprocess/physics-basedDGMOSFETmodel,UFDG,whichwas upgradedwithanovel2-Dsplineformalism.Inversioncharge-centroid shifting,modulatedbygatebiasesaswellasbyquantum-confinementand short-channeleffects,underliesthesensitivityofVttothechangingbackgatebias.Therefore,toachievethedesiredVt(VGbS)distributionfor flexibleVtcontrolinlow-powercircuitapplicationswithapracticalVGbSrange,aswellasgoodDCcharacteristics,carefulstructuraldesignofthe MIGFET,includingbackgate-oxidethicknessandgateworkfunction,is critical.NovelimplementationofasimpleRFmixeranditsdoublebalancedcounterpartusingMIGFETswasexploredwithUFDGinSpice3. Anaccountingofthemixingbasedonthegeneralelectricalcharacteristics oftheMIGFET,aswellastheexpectedperformanceofthemixers,was studied.Reasonablygooddesignofthemixerintermsofgoodconversion gainandlinearity,whilestillsatisfyingsmall-size/low-voltage/low-power requirementsforspecificapplications,canbeachievedwithoptimum biases of the two gates and good design of the transistor. InChapter5,weexploredtheideaofutilizingtheMIGFETinan Lgate=28nmFinFET-basedSRAMdesignforenhancedcellperformance. SignificantSNMimprovementaswellasreasonablycontrolledleakage

PAGE 247

232 canbeachievedviaappropriateback-gatebiasingoftheMIGFETasthe accesstransistor.However,the‘column-baseddynamicpowerswitching scheme’needstobeutilizedforagoodandreliablecellwritemargin. Insightsregardingitsoptimaldesigntrade-offsamongtheread/write/hold stability,andtheirsensitivitiestostructuralvariationsintheMIGFETs weregainedwithourUFDGmodel,andthecompromiseoncelllayout area and cell speed were also discussed. InChapter6,anovel,hybriddevice(theITFET)that incorporatestheplanarFD/SOIMOSFET(FDFET)intoFinFET technologytomoreefficientlyutilizepitchareawasexaminedwithour process/physics-basedcompactmodelUFDGand3-Dnumerical simulations.TheundopedITFET,comprisingaDGFinFETandanSG FDFETwithacommon,midgapmetalgate,yieldssignificantlyhigher drivecurrentperpitchthantheFinFET.However,substantiveleakage currentduetotheungatedfin-basemustbesuppressed,andthiscanbe doneviaprocessingthatextendsathinnerversionoftheFinFETgate downtotheunderlyingBOX.Then,theoff-statecurrentofnanoscale ITFETsisgovernedmainlybytheSOIthicknessoftheFDFET,asinFD/ SOItechnology,andhencetheminimumtSiachievable( @ 5nm)will ultimatelynecessitateredesignoftheFDFETforscalabilityoftheITFET. Withgooddesignofthestructure,theITFETcanyieldasignificant increaseinIonperpitchwithlittleornoincreaseinIoff,yielding substantivelyenhancedIon/IoffrelativetotheFinFET.TheITFETcould havewidespreadapplications,especiallyincircuitsthatrequiredevice

PAGE 248

233 ratioing.AgoodexampleistheFinFET-CMOS6T-SRAMcell,inwhich ITFETsusedforthepull-downnMOSFETscanensurecellstabilitywith noincreaseinlayoutarea.UFDG/Spice3simulationsofsuchanSRAMcell with28nmgatelengthsshowedoutstandingstaticnoisemargin,even withVDDaslowas0.4V.Further,moderateprocess-inducedvariations/ mismatchesintheITFETstructuraldimensions(i.e.,tSi,wSi,andLg) werefoundtobetolerable,withoutunderminingtheITFETbenefittothe SNM nor severely increasing the static power consumption. InChapter7,theworkingprinciplesanddesignconceptsofa noveltwo-transistor(2T)floating-body-cell(FBC)derivedfromtheITFET technologywasstudiedandanalyzed.Thestudyalsohelpedtoclarify someofthemisconceptionaboutthebody-chargedynamicsinaFD/SOI MOSFETthatunderliesthedesignofthe1T-FBCaswell.The2T-FBC functionalitywithbothvoltagesensingandcurrentsensingschemeswere demonstratedwithourUFDGmodelinSpice3.The2T-FBChasgreat potentialtocompetewiththe1T-FBCastechnologyscales.Thelattercell requireslargesubstratebiasingand/oroperatesinsingle-gatemode,and reliesonthecurrentsensingschemewithsignalmargin (D IDS~Wr D VBS) limitedbythebodyfactor(r)anddevicewidth(W).Theformercell operatesinthecommonDGmodewithnoneedforlargesubstratebiasing, ismoreflexibleinitssensingscheme,andtakesupfewerfins,i.e.,smaller area(<50%)fornormalfunctionalityofthecell,irrespectiveofthetypeof sensingused.Forvoltagesensing,onlyonefin(i.e.,twoFinFETs)is needed;forcurrentsensing, D IDSismuchlargerinthe2T-FBC,because

PAGE 249

234 D VBS(>r D VBS)directlydrives D IDSviathesecondtransistor.Infact,the 2T-FBC/1T-FBCarearatioforthesamecurrentmarginisabout2r(~0.5). 8.2 Suggestions for Future Work Biaxialstrainincorporatedintothebulk-SiandPD/SOICMOS channelstendstoyieldlimitedspeed-performanceenhancement; technologically,itisalsochallengingtoimplement.Uniaxialstrain,onthe otherhand,introducedthroughlow-costtechniques,isgainingincreased attentionandinterestduetoitsmuchbetterholemobilityenhancement, andarelativelysmallVtshiftinthenMOSFET.Betterinsightwillbe gainedintothistechnology,anditsperformancepotentialintechnology scaling,fromphysicalmodelingoftheuniaxial-straineffectsinnanoscale CMOS, and implementation in, for example, the UFPDB model. TheMIGFETtechnologyallowsforcreativedesigninnanoscale circuitapplicationstoachieveoptimalperformanceand/orarea-and power-efficiency.Itsphysicalmechanismsandelectricalcharacteristics arewellcharacterizedbytheUFDGmodel.Theclassicalsolutionsofthe UFDGmodelaccuratelymatchwiththosepredictedbythenumerical simulatorMedici,forbiaseswheretheinducedholeconcentrationinthe Sibodyisnegligible.However,thequantizationsolutionoftheUFDG modelpredictedfortheMIGFETisnotverified.PreliminarySCHRED simulationsindicatethattheUFDGsimulationstendtooverestimatethe VtshiftduetoquantumeffectfortheMIGFET,asaresultofassumingthe majoritycarriersoccupyingthelowestsubbandintheweak-inversion formalismforanundopedSifilm.Thisassumptionneedstobefurther

PAGE 250

235 examined,andthequantizationmodelinginagenericasymmetrical double-gate MOSFET with undoped body, updated accordingly. Forcasesincircuitapplicationswhenaconsiderableamountof holeconcentrationispresentintheUTB,whichtendstoscreenoutthe gate-gatechargecoupling,weneedtobeawareoftheoverestimated couplingfactorreffpredictedwithUFDG.Thiserrorisreflectedinthe subthresholdcharacteristicsoftheMIGFETforlarge,negative(forthenchannel device) values of VGbS. TheITFETtechnologyintegratesasingle-gateSOIMOSFET withtheDGFinFET,coveringtheunusedportionofthepitchareafor enhancedlayoutareaefficiency.However,thescalingoftheITFET beyond28nmrequiresdeviceredesignsincefurtherthinningoftSiis probablynotpossibletechnologically. RedesignoftheconstituentFDFETby increasingVtoftheFDFET(e.g.,viaimprecisedopingofthebodyand/or increaseofthegateworkfunction),withoutmuchconcernforSCEsinthe FDFET,couldstillyieldsignicantenhancementoftheFinFETIoninfurther scaledversionsoftheITFET.Theconceptofsuchredesign,andthe performancetherebyobtainable,however,needstobeexaminedfurther,with attentiongiventopossibledetrimentaleffectsofsubstantiallydifferent Vt’s of the two constituent devices. Theproposedconceptofthe2T-FBC,derivedfromtheITFET technology,hasbeenstudiedbasedonknowledgeofrepresentativecarrier generationandrecombinationparametervaluesinatypicalFD/SOI MOSFET.Experimentalknowledgeoftheseparametervalueswillbe

PAGE 251

236 necessary,especiallyathigheroperatingtemperature(i.e.,~85oC),to furthervalidatetheviabilityofthe2T-FBC.Generallyspeaking,higher impact-ionizationrateisdesirable,whereashighercarrierrecombination ratetendstodegradetheretentioncharacteristicsofthecell,and thereforeshouldbeminimizedthroughtechnology,suchasachievinga good-quality(lowdefects)Sifilmandinterfacewiththeoxidelayer. Furthermore,pragmaticstructuraldesignoftheITFET,suchasusing thickergateoxide,and/orgateunderlap/overlap,andpreciseknowledgeor modelingofgate-bodytunnelingcurrentintheUFDGmodelarealso relevantandneededfortheoptimaldesignofthe2T-FBC.Inaddition,a goodsenseamplifiercircuitdesignthatutilizesthefeatureofquasinondestructivereadouteffectivelyreducestherefreshbusyrate,and thereforecanbeessentialtoachieveaviableDRAMtechnologythatmeets theITRSrequirements.Andlast,butnottheleast,istheissueofprocessinducedvariationsofthegatelengthaswellasUTBthickness,whichcan, forexample,severelyimpacttheVtofthesecondtransistor,andtherefore causefailureinread.Effectsofsuchprocess-inducedvariationsmustbe thoroughlyexaminedsothattheneededprocesscontrolcanbe ascertained.

PAGE 252

237 REFERENCE LIST [Ada02]A.O. Adan,T. Yoshimasu,S.Shitara,N.Tanba,M.Fukurni, “LinearityandLow-NoisePerformanceofSOIMOSFETsforRF Applications,” IEEE Trans. Electron Devices,vol.49,pp.881-888, May 2002. [Ana04]H.Ananthan,A.Bansal,K.Roy,“FinFETSRAM-Deviceand CircuitDesignConsiderations,” Proc. 5th Intern. Symp. on Quality Electronic Design, pp. 511-516, San Jose, CA, 2004. [Arm98]G.A.ArmstrongandC.K.Maiti,“Strained-SiChannel HeterojunctionP-MOSFETs,” Solid-State Electron.,vol.42, pp. 487-498, Apr. 1998. [Buf03]F.M.BuflerandW.Fichtner,“ScalingandStrain DependenceofNanoscaleStrained-Sip-MOSFET Performance,” IEEE Trans. Electron Devices,vol.50,pp. 2461-2466, Dec. 2003. [Cav02]N.CavassilasandJ.-L.Autran,“Capacitance-Voltage CharacteristicsofMetal-Oxide-StrainedSemiconductorSi/ SiGeHeterostructures,” Nanotech 2002,vol.1,pp.600-603, Apr. 2002. [Cho03]C.-H.Choi,Z.Yu,R.W.Dutton,“ImpactofPoly-Gate DepletiononMOSRFLinearity,” IEEE Electron Device Lett., vol. 24, pp. 330-332, May 2003. [Cur01]M.T.Currie,etal.,“CarrierMobilitiesandProcessStability ofStrainedSin-andp-MOSFET’sonSiGeVirtual Substrates,” J. Vac. Sci. Technol.B,vol.19,pp.2268-2279, Nov./Dec. 2001. [Dav03] Davinci-2003.06UserGuide .Durham,NC:Synopsis,Inc., 2003. [Fis96]M.V.FischettiandS.E.Laux,“BandStructure,Deformation Potentials,andCarrierMobilityinStrainedSi,Ge,andSiGe Alloys,” J. Appl. Phys., vol. 80, pp. 2234-2252, 1996.

PAGE 253

238 [Fos95]J.G.Fossum,S.Krishnan,O.Faynot,S.Cristoloveanu,C. Raynaud,“SubthresholdKinksinFullyDepletedSOI MOSFET’s,” IEEE Electron Device Letters,vol.16,pp.542544, Dec. 1995. [Fos02a]J.G.Fossum,“UFSOIMOSFETModels(Ver.7.0)User’s Guide,”UniversityofFlorida,Gainesville(http:// www.soi.tec.ufl.edu), June 2002. [Fos02b]J.G.Fossum,L.Ge;M.-H.Chiang,“SpeedSuperiorityof ScaledDouble-GateCMOS,” IEEE Trans. Electron Devices, vol. 49, pp. 808-811, May 2002. [Fos03]J.G.FossumandW.Zhang.,“PerformanceProjectionsof ScaledCMOSDevicesandCircuitsWithStrainedSi-on-SiGe Channels,” IEEE Trans. Electron Devices,vol.50,pp.10421049, Apr. 2003. [Fos05]J.G.Fossum,“UFDGUser’sGuide(Ver.3.5),”Univ.of Florida, Gainesville, Feb. 2005. [Fra03]D.J.Frank,R.H.Dennard,E.Nowak,P.M.Solomon,Y. Taur,H.-S.Wong,“DeviceScalingLimitsofSiMOSFETsand TheirApplicationDependencies,” Proc. of the IEEE,Vol.89, pp. 259-288, Los Angeles, CA, March 2003. [Fri01]D.M.Fried,A.P.Johnson,E.J.Nowak,J.H.Rankin,C.R. Willets,“ASub-40nmBodyThicknessN-typeFinFET,” Proc. Device Research Conf.,pp.24-25,NotreDame,IN,June2001. [Fri04]D.M.Fried,J.S.Duster,K.T.Kornegay,“HighPerformance P-typeIndependent-GateFinFETs,” IEEE Electron Device Lett . , vol. 25, pp. 199-201, Apr. 2004. [Ge01]L.Ge,J.G.Fossum,andB.Liu,“PhysicalCompactModeling andAnalysisofVelocityOvershootinExtremelyScaled CMOSDevicesandCircuits,” IEEE Trans. Electron Devices, vol. 48, pp. 2074-2080, Sept. 2001. [Ge02]L.GeandJ.G. Fossum,“AnalyticalModelingofQuantizationand VolumeInversioninThinSi-FilmDGMOSFETs,” IEEE trans. Electron Devices, vol. 49, pp. 287-294, Feb. 2002.

PAGE 254

239 [Goo03a]J.-S.Goo,Q.Xiang,Y.Takamura,W.Haihong,J.Pan,F. Arasnia,E.N.Paton,P.Besser,M.V.Sidorov,E.Adem,A. Lochtefeld,G.Braithwaite,M.T.Currie,R.Hammond,M.T. Bulsara,M.-R.Lin,“ScalabilityofStrained-SinMOSFETs Downto25nmGateLength,” IEEE Electron Device Lett.,vol. 24, pp. 351-353, May 2003. [Goo03b]J.-S.Goo,Q.Xiang,Y.Takamura,F.Arasnia,E.N.Paton,P. Besser,J.Pan,M.-R.Lin,“BandOffsetInducedThreshold VariationinStrained-SinMOSFETs,” IEEE Electron Device Lett., vol. 24, pp. 568-570, Sept. 2003. [Guo05]Z.Guo,S.Balasubramanian,R.Zlatanovici,T.-J.King;B. Nikolic,“FinFET-BasedSRAMDesign,” ISLPED,Aug.810, 2005, San Diego, California, USA. [Gro67]A.S.Grove, Physics and Technology of Semiconductor Devices, New York: John Wiley and Sons, 1967. [Hat01]T.Hatakeyama,K.Matsuzawa,andS.Takagi,“Impactof Strained-SiChannelonComplementaryMetalOxide SemiconductorCircuitPerformanceundertheSub-100nm Regime,” Jpn. J. Appl. Phys.,vol.40,pp.2627-2632,Apr. 2001. [Hou04]Y.-T.Hou,M.-F.Li,T.Low,andD.-L.Kwong,“MetalGate WorkFunctionEngineeringonGateLeakageofMOSFETs,” IEEE Trans. Electron Devices, vol. 51, pp. 1783-1789, Nov. 2004. [Hoy02]J.L.Hoyt,H.M.Nayfeh,S.Eguchi,I.Aberg,G.Xia,T.Drake, E.A.Fitzgerald,D.A.Antoniadis,“StrainedSiliconMOSFET Technology,”in IEDM Tech. Dig.,pp.23-26.SanFrancisco, CA, Dec. 2002. [Hua99]X.Huang,W.-C.Lee,C.Kuo,D.Hisamoto,L.Chang,J. Kedzierski,E.Anderson,H.Takeuchi,Y.-K.Choi,K.Asano, V.Subramanian,T.-J.King,J.Bokor,andC.Hu,“Sub-50nm FinFET:PMOS,” IEDM Tech. Dig.,pp.67-70,Washington DC, Dec. 1999. [ITRS05] Internat.Tech.RoadmapforSemiconductors .Austin,TX: Semiconductor Industry Assoc./Internat. SEMATECH, 2005. [Jos04]R.V.Joshi,S.Mukhopadhyay,D.W.Plass,Y.H.Chan,C. Chuang;A.Devgan,“VariabilityAnalysisforSub-100nmPD/ SOICMOSSRAMCell,” 30th ESSCIRC,pp.211-214,Leuven, Belgium, Sept. 2004

PAGE 255

240 [Kim01]K.KimandJ.G.Fossum,“Double-GateCMOS:SymmetricalVersusAsymmetrical-GateDevices,” IEEE Trans. Electron Devices, vol. 48, pp. 294-299, Feb. 2001. [Kim02]K.Kim,C.-T.Chuang,K.Rim,andR.V.Joshi,“Performance AssessmentofScaledStrained-SiChannel-on-Insulator (SSOI)CMOS,” Proc. IEEE Internat. SOI Conf.,pp.17-19, Williamsburg, VA, Oct. 2002. [Kim05a]J.-J.Kim,K.Kim,andC.-T.Chuang,“Back-GateControlled ReadSRAMwithImprovedStability,” Proc. IEEE Internat. SOI Conf., pp. 211-212, Honolulu, HI, Oct. 2005. [Kim05b]S.-H.Kim,J.G.Fossum,andV.P.Trivedi, “BulkInversionin FinFETsandImpliedInsightsonEffectiveGateWidth,” IEEE Trans . Electron Devices, vol. 52, pp. 1993-1997, Sept. 2005. [Kim06]S.-H.Kim,“NonclassicalNanoscaleCMOS:Performance Projections,DesignOptimization,andPhysicalModeling,” Ph.D. Dissertation, University of Florida, 2006. [Kri96]S.Krishnan,“AnalysisandModelingofNonlocaland DynamicFloating-BodyEffectsforApplicationinScaledSOI CMOSTechnology,”Ph.D.Dissertation,UniversityofFlorida, 1996. [Kuo03]C.Kuo,T.-J.King,andC.Hu,“ACapacitorlessDoubleGate DRAMTechnologyforSub-100nmEmbeddedandStandAloneMemoryApplications,” IEEE Trans. Electron Devices, vol. 50, pp. 2408-2416, Dec. 2003. [Lee98a]W.-C.Lee,Y.-C.King,T.-J.King,andC.Hu,“Investigationof Poly-Si1-xGexforDual-GateCMOSTechnology,” IEEE Electron Device Lett., vol 19, pp.247-249, July 1998. [Lee98b]T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, New York: Cambridge University Press, 1998. [Lee99]W.-C.Lee,B.Watson,T.-J.King,andC.Hu,“Enhancement ofPMOSDevicePerformancewithPoly-SiGeGate,” IEEE Electron Device Lett. , vol. 20, pp. 232-234, May 1999. [Li02]Q.LiandJ.S.Yuan,“LinearityAnalysisandDesign Optimizationfor0.18 m mCMOSRFMixer,” IEE Proc.Circuits Devices Syst.,Vol.149,No.2,Scottsdale,AZ,April 2002.

PAGE 256

241 [Lim83]H.LimandJ.G. Fossum,“ThresholdVoltageofThin-Film Silicon-on-InsulatorMOSFET’s,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1244-1251, Oct. 1983. [Lim04]J.Lim,S.ThompsonandJ.G.Fossum,“Comparisonof ThresholdVoltageShfitsforUniaxialandBiaxialTensileStressedn-MOSFETs,” IEEE Electron Device Lett.,vol.25, pp. 731-733, Nov. 2004. [Liu03]Y.X.Liu,M.Masahara,K.Ishii,T.Tsutsumi,T.Sekigawa, H.Takashima,H.Yamauchi,E.Suzuki,“FlexibleThreshold VoltageFinFETswithIndependentDoubleGatesandan IdealRectangularCross-SectionSi-FinChannel,” IEDM Tech Dig., pp. 986-988, Washington DC, Dec. 2003. [Mam03]M.Mamidipaka,K.Khouri,N.Dutt,M.Abadir,"Leakage PowerEstimationinSRAMs,” CECS Technical Report #0332, University of California, Irvine, Sept 2003. [Mat04]L.Mathew,Y.Du,A.V.-Y.Thean,M.Sadd,A.Vandooren,C. Parker,T.Stephens,R.Mora,R.Rai,M.Zavala,D.Sing,S. Kalpat,J.Hughes,R.Shimer,S.Jallepalli,G.Workman,W. Zhang,J.G.Fossum,B.E.White,B.-Y.Nguyen,J.Mogab, “CMOSVerticalMultipleIndependentGateFieldEffect Transistor(MIGFET),” Proc. IEEE Internat. SOI Conf.,pp. 187-189, Charleston, South Carolina, Oct. 2004. [Mat05a]L.MathewandJ.G.Fossum,“Hybrid-FETandits ApplicationasSRAM,”FreescaleU.S.PatentApplication, Feb. 2005. [Mat05b]L.Mathew,M.Sadd,S.Kalpat,M.Zavala,T.Stephens,R. Mora,S.Bagchi,C.Parker,J.Vasek,D.Sing,R.Shimer,L. Prabhu,G.O.Workman,G.Ablen,Z.Shi,J.Saenz,B.Min,D. Burnett,B.-Y.Nguyen,J.Mogab.,M.M.Chowdhury,W. Zhang,andJ.G.Fossum,“Inverted-TchannelFET(ITFET)FabricationandCharacteristicsofVertical-Horizontal,Thin Body,Multi-gate,Multi-OrientationDevices,ITFETSRAM Bit-cellOperation.ANovelTechnologyfor45nmandBeyond CMOS,” IEDM Tech. Dig.,pp.731-734,WashingtonDC,Dec. 2005. [Med99]Avant!-MEDICI4.0:Two-DimensionalDeviceSimulation Program, Fremont, CA: Avant! Corp., 1999.

PAGE 257

242 [Miz02]T.Mizuno,N.Sugiyama,T.Tezuka,T.Numata,S.Takagi, “HighPerformanceCMOSOperationofStrained-SOI MOSFETsusingThinFilmSiGe-on-InsulatorSubstrate,” Symp. VLSI Tech. Dig.,pp.106-107,Honolulu,HI,June2002. [Nag05]M.Nagogal,S.Okhonin,C.Bassin,P.Fazan,W.Xiong,C.R. Cleavelin,T.Schulz,K.Schruefer,M.Gostkowski,P. Patruno,C.Maleville,“RetentionCharacteristicsofZeroCapacitorRAM(Z-RAM)CellBasedonFinFETandTri-Gate Devices,” Proc. IEEE Internat. SOI Conf.,pp.203-204, Honolulu, HI, Oct. 2005. [Nak02]H.Nakatsuji,Y.Kamakura,K.Taniguchi,“AStudyof SubbandStructureandTransportofTwo-DimensionalHoles inStrainedSip-MOSFETsUsingFull-BandModeling,” IEDM Tech. Dig., pp. 727-730, San Francisco, CA, Dec. 2002. [Now02]E.J.Nowak,B.A.Rainey,D.M.Fried,J.Kedzierski,M. Ieong,W.Leipold,J.Wright,M.Breitwisch,“AFunctional FinFET-DGCMOSSRAMcell,” IEDM Tech. Dig.,pp.411414, San Francisco, CA, Dec. 2002. [Num03]T.Numata,T.Mizuno,T.Tezuka,J.Koga,S.Takagi,“Control ofThresholdVoltageandShortChannelEffectsinUltra-thin Strained-SOICMOS,” Proc. IEEE Internat. SOI Conf.,pp. 119-121, Newport Beach, CA, Sept. 2003. [Obe98]R.Oberhuber,G.Zandler,andP.Vogl,“SubbandStructure andMobiltyofTwo-dimensionalholesinstrainedSi/SiGe MOSFET’s,” Phys. Rev. B, vol. 58, p. 9941, 1998. [Ohs02]T.Ohsawa,K.Fujita,T.Higashi,Y.Iwata,T.Kajiyama,Y. Asao,K.Sunouchi,“MemoryDesignUsingaOne-Transistor GainCellonSOI,” IEEE Journal of Solid-State Circuits,vol. 37, pp. 1510-1522, Nov. 2002. [Ohs06]T.Ohsawa,K.Fujita,K.Hatsuda,T.Higashi,T.Shino,Y. Minami,H.Nakajima,M.Morikado,K.Inoh,T.Hamamoto, S.Watanabe,S.Fujii,T.Furuyama,“Designofa128-MbSOI DRAMUsingtheFloatingBodyCell(FBC),” IEEE Journal of Solid-State Circuits, Vol. 41, pp. 135-145, Jan. 2006. [Pel02]M.M.PelellaandJ.G.Fossum,“OnthePerformance AdvantageofPD/SOICMOSWithFloatingBodies,” IEEE Trans. Electron Devices, vol. 49, pp. 96-104, Jan. 2002.

PAGE 258

243 [Peo86]R.People,“PhysicsandApplicationsofGeSi/SiStrainedLayerHeterostructures,” IEEE J. Quantum Electronics,vol. QE-22. pp. 1696-1708, Sept. 1986. [Pon00]Y.V.Ponomarev,P.A.Stolk,S.Salm,J.Schmitz,andP.H. Woerlee,“High-PerformanceDeepSubmicronCMOS TechnologieswithPolycrystalline-SiGeGates,” IEEE Trans. Electron Devices, vol. 47, pp. 848-855, Apr. 2000. [Qui00]E.J.Quinones,S.John,S.K.Ray,andS.K.Banerjee, “Design,Fabrication,andAnalysisofSiGeCHeterojunction PMOSFETs,” IEEE Trans. Electron Devices,vol.47,pp.17151725, Sept. 2000. [Ran04]R.Ranica,A.Villaret,C.Fenouillet-Beranger,P.Malinge,P. Mazoyer,P.Masson,D.Delille,C.Charbuillet,P.Candelier, T.Skotnicki,“ACapacitorlessDRAMCellon75nmgate length,16nmThinFullyDepletedSOIDeviceforHigh DensityEmbeddedMemories,” IEDM Tech. Dig.,pp.277-280, San Francisco, CA, Dec. 2004. [Rim00]K.Rim,J.L.Hoyt,andJ.F.Gibbons,“Fabricationand AnalysisofDeepSubmicronStrained-SiN-MOSFET’s,” IEEE Trans. Electron Devices, vol. 47, pp. 1406-1414, July 2000. [Rim01]K.Rim,S.Koester,M.Hargrove,J.Chu,P.M.Mooney,J.Ott, T.Kanarsky,P.Ronsheim,M.Ieong,A.Grill,H.-S.Wong, “StrainedSiNMOSFETsforHighPerformanceCMOS Technology,” Symp. VLSI Tech. Dig.,pp.59-60,Kyoto,Japan, June 2001. [Rim02]K.Rim,J.Chu,H.Chen,K.A.Jenkins,R.Roy,J.Newbury, J.Ott,K.Petrarca,P.Mooney,D.Lacey,S.Koester,K.Chan, D.Boyd,M.Ieong,H.-S.Wong,“CharacteristicsandDevice DesignofSub-100nmStrainedSiN-andPMOSFETs,” Symp. VLSI Tech. Dig., pp. 98-99, Honolulu, HI, June 2002. [See87]E.Seevinck,F.J.List,andJ.Lohstroh,“Static-NoiseMargin AnalysisofMOSSRAMCells,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 748-754, Oct. 1987. [Sug02]N.Sugii,D.Hisamoto,K.Washio,N.Yokoyama,S.Kimura, “PerformanceEnhancementofStrained-SiMOSFETs FabricatedonaChemical-Mechanical-PolishedSiGe Substrate,” IEEE Trans. Electron Devices,vol.49,pp.22372243, Dec. 2002.

PAGE 259

244 [Tak96]S.Takagi,J.L.Hoyt,J.J.Welser,andJ.F.Gibbons, “ComparativeStudyofPhonon-LimitedMobilityofTwoDimensionalElectronsinStrainedandUnstrainedSiMetalOxide-SemiconductorField-EffectTransistors,” J. Appl. Phys., vol. 80, pp. 1567-1577, 1996. [Tan04]T.Tanaka,E.Yoshida,andT.Miyashita,“ScalabilityStudy onaCapacitorless1T-DRAM:FromSingle-gatePD-SOIto Double-gateFinDRAM,” IEDM Tech. Dig.,pp.919-922,San Francisco, CA, Dec. 2004. [Tau98]Y.TaurandT.H.Ning, Fundamentals of Modern VLSI Devices, New York: Cambridge University Press, 1998. [Tho01]S.E.Thompson,M.Alavi,R.Arghavani,A.Brand,R. Bigwood,J.Brandenburg,B.Crew,V.Dubin,M.Hussein,P. Jacob,C.Kenyon,E.Lee,B.Mcintyre,Z.Ma,P.Moon,P. Nguyen,M.Prince,R.Schweinfurth,S.Sivakumar,P.Smith, M.Stettler,S.Tyagi,M.Wei,J.Xu,S.Yang,M.Bohr,“An Enhanced130nmGenerationLogicTechnologyFeaturing 60nmTransistorsOptimizedforHighPerformanceandLow Powerat0.7-1.4V,”in IEDM Tech. Dig.,pp.257-260, Washington DC, Dec. 2001. [Tho02]S.E.Thompson,N.Anand,M.Armstrong,C.Auth,B.Arcot, M.Alavi,P.Bai,J.Bielefeld,R.Bigwood,J.Brandenburg,M. Buehler,S.Cea,V.Chikarmane,C.Choi,R.Frankovic,T. Ghani,G.Glass,W.Han,T.Hoffmann,M.Hussein,P.Jacob, A.Jain,C.Jan,S.Joshi,C.Kenyon,J.Klaus,S.Klopcic,J. Luce,Z.Ma,B.Mcintyre,K.Mistry,A.Murthy,P.Nguyen,H. Pearson,T.Sandford,R.Schweinfurth,R.Shaheed,S. Sivakumar,M.Taylor,B.Tufts,C.Wallace,P.Wang,C. Weber,M.Bohr,“A90nmLogicTechnologyFeaturing50nm StrainedSiliconChannelTransistors,7LayersofCu Interconnects,LowkILD,and1 m m2SRAMCell,” IEDM Tech. Dig., pp. 61-64, San Francisco, Dec. 2002. [Tho04]S.E.Thompson,M.Armstrong,C.Auth,S.Cea,R.Chau,G. Glass,T.Hoffman,J.Klaus,Z.Ma,B.Mcintyre,A.Murthy, B.Obradovic,L.Shifren,S.Sivakumar,S.Tyagi,T.Ghani,K. Mistry,M.Bohr,Y.El-Mansy,“ALogicNanotechnology FeaturingStrained-Silicon,” IEEE Electron Device Lett.,Vol. 25, pp. 191-193, April 2004.

PAGE 260

245 [Tho05]S.E.Thompson,R.S.Chau,T.Ghani,K.Mistry,S.Tyagi,M. T.Bohr,“InSearchof“Forever,”ContinuedTransistor ScalingOneNewMaterialataTime,” IEEE Trans. on Semiconductor Manufacturing, Vol. 18, pp. 26-36, Feb. 2005. [Tri03]V.P.TrivediandJ.G.Fossum,“ScalingFullyDepletedSOI CMOS,” IEEE Trans. Electron Devices,vol.50,pp.2095-2103, Oct. 2003. [Tri05a]V.P.Trivedi,“PhysicsandDesignofNonclassicalNanoscale CMOSDeviceswithUltra-ThinBodies,”Ph.D.Dissertation, University of Florida, 2005. [Tri05b]V.P.TrivediandJ.G.Fossum,“Quantum-MechanicalEffects ontheThresholdVoltageofUndopedDouble-Gate MOSFETs,” IEEE Electron Device Lett. , vol.26,pp.579-582, Aug. 2005. [Tri05c]V.P.Trivedi,J.G.FossumandM.M.Chowdhury,“Nanoscale FinFETswithGate-Source/DrainUnderlap,” IEEE Trans. Electron Devices, vol. 52, pp. 56-62, Jan. 2005. [Van86]C.G.VandeWalleandR.M.Martin,“Theoretical CalculationsofHeterojunctionDiscontinuitiesintheSi/Ge System,” Phys. Rev. B, Condensed Matter,vol.34,pp.56215634, 1986. [Wan93]H.-J.WannandC.Hu,“ACapacitorlessDRAMCellonSOI Substrate,” IEDM Tech. Dig.,pp.635-638,SanFrancisco,CA, Dec. 1993. [ Wes93]N.H.E.Weste,K.Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective,2nded.Reading,MA: Addison-Wesley, 1993. [Wor99]G.O.Workman,“PhysicalModelingandAnalysisofDeepSubmicronSilicon-on-InsulatorCMOSDevicesandCircuits,” Ph.D. Dissertation, University of Florida, 1999. [Xia03]Q.Xiang,J.Goo,J.Pan,B.Yu,S.Ahmed,J.Zhang,M.Lin, “StrainedSiliconNMOSwithNickel-SilicideMetalGate,” Symp. VLSI Tech. Dig.,pp.101-102,Kyoto,Japan,June2003. [Yan04]J.-W.Yang,“AnalysisandModelingofParasiticEffectsin AdvancedSOICMOSTechnology,IncludingNon-Classical TransistorsinUltra-ThinSi-Film,”Ph.D.Dissertation, University of Florida, 2004.

PAGE 261

246 [Yan05]J.-W.YangandJ.G.Fossum,“OntheFeasibilityofNanoscale Triple-gateCMOSTransistors,” IEEE Trans. Electron Devices, pp. vol. 52, 2005. [Yos06]E.Yoshida,andT.Tanaka,“ACapacitorless1T-DRAM TechnologyUsingGate-InducedDrain-Leakage(GIDL) CurrentforLow-PowerandHigh-SpeedEmbeddedMemory,” IEEE Trans. Electron Devices, pp. 692-697, vol. 53, 2006. [Zha05]K.Zhang,U.Bhattacharya,Z.Chen,F.Hamzaoglu,D. Murray,N.Vallepalli,Y.Wang,B.Zheng,andM.Bohr,“A 3GHz70MbSRAMin65nmCMOSTechnologywith IntegratedColumn-BasedDynamicPowerSupply,” ISSCC, pp. 474-475, San Francisco, Feb. 2005.

PAGE 262

247 BIOGRAPHICAL SKETCH WeiminZhangwasborninBeijing,China.HereceivedtheB.S. degreeinmaterialsphysicsfromUniversityofScienceandTechnology, Beijing,China,in1997,andM.S.degreeinelectricalengineeringfromthe University of Florida, Gainesville, FL, in 2003. Since2002,hehasbeenpursuingaPh.D.degreeindevice electronicsasagraduateresearchassistantattheUniversityofFlorida. Hisresearchinterestsinvolvedevicedesign,analysis,andmodelingof nonclassicalnanoscaleCMOS,andapplicationsindevice/circuitdesign optimization.