Citation
Time-Mode Circuits for Analog Computation

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Title:
Time-Mode Circuits for Analog Computation
Creator:
RAVINUTHULA, VISHNU ( Author, Primary )
Copyright Date:
2008

Subjects

Subjects / Keywords:
Capacitors ( jstor )
Comparators ( jstor )
Electric potential ( jstor )
FIR filters ( jstor )
Signals ( jstor )
Simulations ( jstor )
Supernova remnants ( jstor )
Tours ( jstor )
Transistors ( jstor )
Weighted averages ( jstor )

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Source Institution:
University of Florida
Holding Location:
University of Florida
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Copyright Vishnu Ravinuthula. Permission granted to University of Florida to digitize and display this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Embargo Date:
8/31/2006
Resource Identifier:
649815337 ( OCLC )

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Full Text











TIME-MODE CIRCUITS FOR ANALOG COMPUTATION


By

VISHNU RAVINUTHULA

















A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA


2006

































Copyright 2006

by

Vishnu Ravinuthula

































My parents and brother have brought me to where I stand today. This work is

dedicated to them for trusting me and standing by me through all hardships.















ACKNOWLEDGMENTS

I owe a special debt of gratitude to Dr. Harris for his expert guidance and

stimulating discussions. His perception, insight, and experience have contributed

immensely to the clarity and rigor of my research. The faith he showed was the

motivating force towards my contribution. My association with him has been an

enlightening and refreshing experience.

I am immensely thankful to Dr. Jose Fortes for his help when I was in a

quagmire and it was a privilege working under him.

I am also grateful to the analog genius Dr. Robert Fox, for he went out of

the way to help me even when I was not working under him. He is one of the few

professors I feel proud that I got to work with.

This work was supported by National Aeronautics and Space Administration

(NASA) under award no. NCC 2-1363 and Semiconductor Research Corporation

(SRC) under Task ID: 1049 Crosscut Research. I would like to thank Dr. M. P.

Anantram, Dr. Harry Partridge, and Dr. T. R. Govindan at NASA Ames Research

Center, CA, for the confidence they showed in me and all their support during my

internship at NASA.

Thanks are due to the administrative staff of the Department of Electrical and

Computer Engineering: Ellie, Janet, Linda, and Shannon for their co-operation.

Furthermore, I take this opportunity to express my appreciation to all those who

helped me in the completion of my work.

I would like to thank my former and current labmates: Pravin, Vaibhav,

Rama, Du, Xi ,i:;: iw- Yuan, Harpreet, Mark, Meena, Harsha, and Ismail for









their support and encouragement. Lastly, but not the least, I thank my friends,

roommates and colleagues for making my stay at UF memorable.















TABLE OF CONTENTS
page

ACKNOWLEDGMENTS ................... ...... iv

LIST OF TABLES ...................... ......... ix

LIST OF FIGURES ................................ x

ABSTRACT ................... .............. xiv

CHAPTER

1 INTRODUCTION ........................... 1

1.1 Biological Motivation ........... ............... 3
1.2 Engineering Motivation ........... .............. 3
1.3 ('C! pter Summ ary ........................... 5

2 THE WEIGHTED AVERAGE CIRCUIT ........ ......... 6

2.1 Time-Mode Weighted Averaging Circuit ............... 6
2.1.1 Reset Stage . . . . . . 9
2.1.2 Measured Results ......... .............. 10
2.1.3 Discussion ................... ....... 12
2.2 Theoretical Analysis of Signal-to-Noise Ratio and Dynamic Range 14
2.2.1 Output Noise due to Timing Jitter at the Inputs ...... 14
2.2.2 Output Noise due to Fundamental Noise Sources in the Circuit 15
2.2.2.1 Noise in tour due to noise in current source I1 16
2.2.2.2 Noise in tour due to noise in current source 2 .* 17
2.2.2.3 Noise in tour due to noise in the comparator .. 18
2.2.3 Discussion ......... ... ......... 21
2.3 Scaling of Time-Mode Weighted Average Circuit with Technology 21
2.3.1 Simulation Setup .................. .... .. 22
2.3.2 Results and Inferences ................ .. 23
2.3.3 Discussion .................. ......... .. 26
2.3.4 Drawbacks ......... ...... ......... 27
2.4 Carbon Nanotube Based Time-Mode Weighted Averaging Circuit 30
2.4.1 Carbon Nanotube Field Effect Transistors (CNFETs) and
Their Spice Models . . ........ ... 30
2.4.2 Physics Governing the Operation of CNFET . ... 32
2.4.3 Simulation Results .................. .. 32









2.4.4 Discussion .... . . ......... 33
2.5 Reliable Time-Mode Weighted Average Circuit . . .... 34
2.5.1 M otivation .................. ......... .. 34
2.5.2 Time-Mode Median Circuit .................. .. 36
2.5.3 Redundancy in Time-Mode Computation . .... 37
2.5.4 Discussion .................. ......... .. 40

3 SNR COMPARISON OF WEIGHTED AVERAGING CIRCUITS .... 42

3.1 Voltage-Mode Averaging Circuit .. .......... .. .43
3.1.1 Noise Contribution at the Output due to Ai2 . ... 45
3.1.2 Noise Contribution at the Output due to Av22 . ... 45
3.1.3 Noise Bandwidth .................. .... .. 46
3.2 Current-Mode Averaging Circuit. . . ..47
3.3 Discussion ...... .......... . . ..52

4 OTHER TIME-MODE CIRCUIT EXAMPLES . ...... 53

4.1 Weighted Subtraction Circuit .................. .. 53
4.2 Weighted Sum Circuit .................. ..... .. 54
4.3 Scalar Multiplication Circuit..... . . ..57
4.4 Maximum(\!A.X)/l\ iiiiiiiiiii(\1 IN) Circuit . . ...... 58

5 APPLICATION OF TIME-MODE CIRCUITS . . ..... 60

5.1 Time-Mode Edge Detection Circuit ................. .. 60
5.1.1 Basic Formulation .................. .... .. 60
5.1.2 Smoothing .................. ......... .. 62
5.1.3 Thresholded Difference ................ .... 63
5.1.4 Results ...... .................... .. 64
5.1.5 Discussion . . ...... ....... .. 69
5.2 3-Tap 1-Quadrant Time-Mode Finite Impulse Response Filter .. 69
5.2.1 Finite Impulse Response Computation in Time . ... 70
5.2.2 3-Tap 1-Quadrant Time-Mode FIR Filter Architecture .. 74
5.2.3 Step-by-Step Description of the Functionality . ... 79
5.3 Simulation Results ......... . . ... 79
5.4 Signal-to-Noise Ratio/Dynamic Range Analysis . ... 91
5.4.1 Noise in tour due to Noise in Current Source II . 91
5.4.2 Noise in tour due to Noise in Current Source I2 ...... ..92
5.4.3 Noise in tour due to Noise in Current Source . 92
5.4.4 Noise in tour due to Noise in Current Source 4 . 93
5.5 Performance of the FIR Filter under Input Time Jitter ...... ..95
5.6 Advantages of Time-Mode FIR Filters ............ .. 96
5.7 Limitations of Time-Mode FIR Filters ............ .. 96









6 NON-LINEAR TIME-MODE COMPUTATION ....... ..... 98

6.1 Implementing Non-Linear Arithmetic by Introducing Non-Linearity
in the Existing Linear Computational Blocks ............. 98
6.1.1 Time-Mode Multiplication .................. .. 98
6.1.2 Time-Mode Division . . . ... 101
6.2 Implementing Non-Linear Arithmetic Using Time-Mode Multi-LiT r
Perceptron ......... .. ...... ...... 103
6.2.1 Time-Mode Multi-Layer Perceptron . . 103
6.2.2 Hardware Implementation of Time-Mode MLP ........ 106

7 CONCLUSION AND FUTURE WORK ............. .. 113

7.1 Conclusion. ................ .......... .. 113
7.2 Future work ............... .......... .. 114

REFERENCES ................... ... ........ 116

BIOGRAPHICAL SKETCH .................. ......... .. 119















LIST OF TABLES
Table page

2-1 Measured performance characteristics of time-mode weighted averaging
circuit .................. .................. .. 13

4-1 Classification of Time-mode computational circuits. Relative time reference
implies that the inputs and outputs are defined with respect to a reference
time (start of a frame). Absolute time reference implies that inputs and
outputs are not defined with respect to a reference time. . ... 59















LIST OF FIGURES


Figure page

1-1 Different modes of computation ................ ... 2

2-1 Time-mode weighted average circuit. A) Circuit schematic. B) Idealized
graph showing the capacitor voltage at different time periods. . 6

2-2 Inputs tl, t2 and output tour are defined within a frame . . 9

2-3 Plot of tour for varying I (C = 20pF, VTH = 2.5V). The block was
given one step input. ............... ..... .... 10

2-4 Plot of tour for varying I (C = 20pF,I = 1.0476pA, VTH = 2.5V). The
block was given one step input. ............. ... 11

2-5 Plot of tour for varying 2 (C = 20pF,I = 1.0476pA, VTH = 2.5V with
tl fixed at lps, 8.5/s and 32.5/s.) ..... ........... .... 12

2-6 Plot of touT for varying t2 (C 20pF,11 = 1.46pA, I2 = 0.29pA, VTH =
2.5V with tl fixed at 1/s, 8.5ps and 32.5ps.) . . ..... 13

2-7 Variation of capacitor charging current with scaling technology . 24

2-8 Variation of dynamic power with scaling technology . . ... 24

2-9 Variation of average power with scaling technology . . 26

2-10 Variation of energy consumed per averaging operation with scaling technology 27

2-11 Comparison of calculated and simulated time-mode averaging outputs
over technologies ................ . .... .28

2-12 Comparison of calculated and simulated time-mode averaging output
noise over technologies .................. ......... .. 28

2-13 Comparison of calculated and simulated time-mode averaging SNR values
over technologies .................. ............ .. 29

2-14 Variation of dynamic range with scaling technology ........... ..29

2-15 PCNFET ID-VGS plots for varying VDS. ................. 33

2-16 NCNFET ID-VGS plots for varying VDS . . . . 34

2-17 Nano-weighted average circuit simulation outputs . . 35









2-18 Capacitor charging/discharging current in a nano-weighted average circuit 35

2-19 Time-mode median circuit for 3-inputs .................. 36

2-20 Time-mode median circuit for N-inputs .................. 37

2-21 Von Neumann's two-out-of-three ii Pii ii y circuit . . 38

2-22 Block diagram of a reliable time-mode weighted average circuit . 39

2-23 Plot showing the increase in reliability of the redundant circuit as compared
to the individual elements .................. ....... .. 40

3-1 Voltage mode weighted averaging circuit ................. 44

3-2 Voltage mode weighted averaging circuit with noise sources . ... 45

3-3 Current mode weighted averaging circuit ................. ..48

3-4 Current mode weighted averaging circuit with noise sources ...... ..48

3-5 Half of the noise current from each transistor flows to the output .. 50

3-6 Calculated and simulated SNR values of a time-mode weighted averaging
circuit over technology .................. ......... 52

4-1 Weighted subtraction circuit. A) Circuit schematic. B) Idealized graph
showing the capacitor's voltage at different time periods. . ... 53

4-2 Weighted sum circuit. A) Circuit schematic. B) Idealized graph showing
the capacitor's voltage at different time periods. ............ ..56

4-3 Scalar multiplication circuit. A) Circuit schematic. B) Idealized graph
showing the capacitor's voltage at different time periods. . ... 57

4-4 Circuit schematic of MAX circuit...... . . ..58

4-5 Circuit schematic of MIN circuit... . . ..58

5-1 Edge detection by derivative operators .................. 60

5-2 Data flow in time-mode edge detection .................. 62

5-3 Circuit to smooth pixel intensities .................. ..... 62

5-4 Circuit used to obtain thresholded differences on the smoothed steps 64

5-5 MATLAB simulation results showing the original image, smoothed image
and the detected edges of an image .................. .. 66

5-6 Simulation results showing the original image, smoothed image and the
detected edges of a 16 pixel image .................. ..... 67









5-7 Outputs from different stages in time-mode edge detection . ... 68

5-8 Computational block to be used in the FIR filter .......... 71

5-9 Voltage across the computational block's capacitor at various times .. 72

5-10 3-tap time-mode FIR filter architecture ............. .. .. 76

5-11 The architecture of the input conditioning block ........... .77

5-12 3-tap FIR filter's input, digital preconditioning block and its outputs .78

5-13 State of the FIR filter as input tl enters ................. .. 80

5-14 State of the FIR filter as input t2 enters ................. 81

5-15 State of the FIR filter as input t3 enters ................. 82

5-16 State of the FIR filter as input t4 enters the system and with frame 4
discharging computational block 1 .................. ..... 83

5-17 State of the FIR filter before frame 5 starts ............... ..84

5-18 Pole-zero plots of the FIR filter .................. .. 86

5-19 Time-mode FIR filter's magnitude response (sampling freq = 100 kHz) 86

5-20 Time-mode FIR filter's phase response .................. 87

5-21 Time-mode FIR filter's group delay .................. .. 88

5-22 Time-mode FIR filter's input and output waveforms (in time domain) 88

5-23 Energy of FIR filter's input and output signals .............. ..89

5-24 Cadence simulation results for the time-mode 3-bit FIR filter ...... ..90

6-1 Scalar multiplication circuit .................. ..... .. 99

6-2 Timing details of the 2-input time-mode multiplier . ..... 100

6-3 Schematic of the 2-input time-mode multiplier .............. .101

6-4 Schematic of the 2-input time-mode divider ............... ..102

6-5 Feedforward multi-l ir perception .................. .. 104

6-6 Fully connected 2-input feedforward MLP with one hidden l- v r and one
output l-.-r .................... ............. .. ..105

6-7 Non-linear model of a neuron .................. ..... 105

6-8 Time-mode scalar multiplication and summing circuit . . ... 108









6-9 Time-mode piece-wise linear activation circuit . . 109

6-10 Variation of output mean square error with epochs . . .. 111

6-11 Time-mode MLP desired and actual outputs . . 111

6-12 Cadence simulation results ............... .... .. 112















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

TIME-MODE CIRCUITS FOR ANALOG COMPUTATION

By

Vishnu Ravinuthula

August 2006

C'!h In': John G. Harris
Major Department: Electrical and Computer Engineering

We introduce a set of basic circuit building blocks for analog computation

using a temporal step function representation for the inputs and outputs.

Time-mode circuits are described that use a step function representation for

computing the weighted average, weighted difference, weighted sum, scalar product,

maximum, minimum, multiplication, division and thresholded difference operations.

Time-mode circuits are alternatives to well-known voltage- and current-mode

approaches which could be used to perform these same mathematical operations.

Time-mode circuits grow more appealing as C'\ IOS process technologies

scale since they minimize the amount of analog circuitry and use noise robust

.i-vnchronous time events as inputs and outputs. Time-mode circuits provide a

seamless interface to the growing number of time-based sensors which already

output compatible timing events. An example is given where a time-mode edge

detector is developed to directly interface to the output of a time-to-first-spike

imager. Time-mode circuits have simple architecture, provide high signal-to-noise

ratio, dynamic range, consume low power, and hence, prove advantageous in

architecturally complex applications like finite impulse response filters.















CHAPTER 1
INTRODUCTION

All analog signal processing circuits must represent signals using physical

quantities such as voltage, current, charge, frequency or time duration. In

analog literature, we have seen extensive use of voltage-mode, current-mode

and charge-mode circuits that generally represent input and output signals as

voltage, current and charge respectively:

* Voltage-mode circuits are the most common example, wherein voltages are
used to represent both input and output signals. These circuits have a long
history including classic opamp based designs [1] and GmC style circuits
common in todw'i's analog very large scale integration (VLSI) designs [2].

* Current-mode circuits are also very popular where currents are used
for both inputs and outputs [3]. These designs include Barrie Gilbert's
original translinear circuits that rely on the exponential voltage to current
relationships of bipolar or complementary metal oxide semiconductor (C' IOS)
subthreshold circuits [4]. More recent log domain filters [5] are also generally
considered to be current-mode circuits.

* Another physical quantity is charge, and charge-mode circuits have been
employ, ,1 in various applications, particularly for charge coupled devices
(CCDs) [6].

These different modes of signal representation have respective advantages and

drawbacks and can therefore be used in different parts of the same system. The

voltage representation makes it easy to distribute a signal in various parts of a

circuit, but implies a large stored energy V2 into the node's parasitic capacitance

C. The current representation facilitates the summing of signals but complicates

their distribution. Replicas must be created which are never exactly equal to

the original signal. It has been observed that it is problematic to clearly define

the distinction between current-mode and voltage mode circuits [7]. The charge










representation requires time sampling but can be nicely processed by means of

CCDs or switched-capacitor techniques. In actual fact, every circuit uses voltage,

current and charge in its operation and sometimes semantics and philosophy are

debated when definitively categorizing these classes of circuits [7].

Temporal coding is used as the dominant mode of signal representation for

communication in biological nervous systems. Signals represented in this manner

are easy to regenerate and this representation might therefore be preferred for

long-distance transfers of information. It is discontinuous in time, but the phase

information is kept in .-vinchronous systems. We introduce time-mode circuits

as another category of analog signal processing circuits that represent input and

output signals in the temporal domain. Figure 1-1 depicts block diagrams for

voltage-, current-, and time-mode circuits. Time-mode circuits use temporal events,

in this case voltage steps, to represent signals.


+
VOLTAGE-MODE VO
V1 COMPUTATION OUT

V2





I CURRENT-MODE IOUT
SS- COMPUTATION

12





t, TIME-MODE tUT
COMPUTATION

t2

Figure 1 1: Different modes of computation.









1.1 Biological Motivation

The idea of performing computation using the timing of events is shared

with the most powerful existing computer: the human brain. The brain is an

analog computer, but it does not transmit continuous analog voltages, likely due

to noise and cross-talk susceptibility. Instead, information is represented and

transmitted using the timing of .i- vchronous digital-like timing pulses. However,

an important difference is that time-mode circuits described in this thesis use a

step function representation because of the resulting circuit simplicity compared to

pulse representations in mathematical computations.

Since we are using a step function representation, we cannot represent

information in terms of firing rates (where we need multiple spikes to represent

an analog variable). This new approach is similar to temporal coding by single

spikes [8] rather than on the traditional interpretation of analog variables in terms

of firing rates.

Maass [8] points out that a spiking neuron in principle will be able to compute

in temporal coding of inputs and output a linear function if its ] ..-I -vi-i itic

potential can be described or approximated by a linear function during some

initial segment. As we will see in C'!i lpter 2, time-mode circuits perform linear

computations by linearly mapping the temporal inputs to a voltage across a

capacitor. Also, Maass points out that networks of noisy spiking neurons are

universal approximators they can approximate with regard to temporal coding

any given continuous function of several variables. This observation is proved

in ('!i lpter 6 where we use a network of time-mode circuits to implement an

approximation of the multiplication function (non-linear function).

1.2 Engineering Motivation

Independent of any biological motivation, it is also making more and more

sense to consider analog computation using the timing of .-i- vchronous events









from a purely engineering perspective. Through the electronics revolution over

the past decades, C'\ OS process technology is shrinking the usable voltage swing,

wreaking havoc on traditional analog circuit design. However, the faster "digital"

transistors are better able to process timing signals leading us to consider analog

computation more similar to that of the brain. This trend will likely continue

with nanotechnology since even smaller voltage ranges and even faster devices are

promised. Of course, C'\ IOS technology is primarily scaling in favor of faster and

faster digital devices, however power consumption is beginning to limit how far

these digital circuits can scale.

Time-based signal representations have been in use for many years, including

such techniques as pulse-width modulation and sigma-delta converters but

temporal codes are becoming even more common with the rising popularity of

such techniques as class D amplifiers, spike-based sensors and even ultra-wideband

(UWB) signal transmission. However, these temporal codes are typically

used as temporary representations and computation is only performed after

reconstruction back to a traditional analog or digital form. There are instances

where amplifiers use temporal signals as inputs and outputs [9], but they do not

perform computation with them.

There are architectures like the PALMO [10] where the inputs and outputs

are represented by temporal signals, but using pulses. In such architectures, the

input temporal pulses are immediately converted to voltage and they lose the

computational advantages that the time-based representation promises. Similarly,

Murray discusses the implementation of arithmetic functions like addition and

multiplication using voltage or current pulses [11]. Another approach by Sarpeshkar

uses pulses for scalable hybrid computation [12]. However, all the above mentioned

architectures use pulses for computation with more complicated circuits than the

time-mode circuits.






5


In this thesis we describe a set of basic circuit building blocks for computation

using an analog temporal step function representation for both inputs and outputs.

1.3 Chapter Summary

The thesis is divided into the following chapters:

* C'! lpter 2: The Weighted Average Circuit. This chapter introduces time-mode
computation by describing the details of the weighted average circuit in
terms of functionality and fabricated chip measurements. We then proceed
to see how new and emerging silicon/carbon-nanotube technologies affect the
performance of this prototype time-mode circuit. Later we introduce a method
to improve the reliability of this time-mode circuit.

* C('! lter 3: SNR Comparison Of Weighted Averaging Circuits. In this
chapter we derive expressions for the Signal-to-noise ratio of voltage-mode,
current-mode and time-mode 2-input weighted average circuits, use these
expressions to compare and contrast the SNR performances of those circuits
and verify the observations with simulations.

* C('! lter 4: Other Time-Mode Circuit Examples. This chapter describes other
time-mode circuit examples including the weighted difference, weighted sum,
scalar product, maximum, minimum and thresholded difference operations.

* C'!i lter 5: Application Of Time-Mode Circuits. In this chapter we talk
two applications of linear time-mode computational circuits: We start
with the design of a time-mode edge detector that interfaces directly to a
time-to-first-spike imager. Later we describe the design of a 3-tap time-mode
FIR filter. We analyze these two applications and describe the advantages of
using time-mode circuits for these applications.

* C'!i lter 6: Non-Linear Time-Mode Computation. In this chapter we discuss
two different methods of performing non-linear computation using time-mode
circuits: The first method implements non-linear arithmetic using a time-mode
multi-li-r perception and the second method implements non-linear
arithmetic by introducing non-linearity in the existing linear computational
blocks.

* ('!i lter 7: Conclusion And Future Work. This chapter concludes the thesis by
recapitulating all the main points of the thesis. We also discuss possible future
research work.















CHAPTER 2
THE WEIGHTED AVERAGE CIRCUIT

2.1 Time-Mode Weighted Averaging Circuit







temp
Vc

M 2TH .




0 t -- t --
St 2 OUT t

A) B)

Figure 2-1. Time-mode weighted average circuit. A) Circuit schematic. B)
Idealized graph showing the capacitor voltage at different time periods.


Figure 2-1A illustrates the basic elements used to perform a weighted sum of

temporal signals. In general, the circuit can process many input steps but only two

are shown for simplicity. The circuit consists of a single capacitor and comparator

plus an inverter, current source and pfet for each input1 The rising edges of the

input steps correspond to the time values tl and t2 representing the two input

values. The PMOS transistors M1 and I[.l act as switches. The two current sources

I, and I2 are connected to the sources of the PMOS transistors to start charging

the capacitor C when the step inputs rise. The comparator senses the voltage

across the capacitor and outputs a step when the voltage reaches the threshold




1 The inverters would not be necessary if nfets were used to sink current or if an
inverted step function was used to represent input and output values. Furthermore,
source signalling should be used to reduce charge injection effects as explained in
[13].









voltage VTH. Once the block outputs a step, an appropriate reset stage (not shown

in the figure) resets the capacitor to OV. The current sources I, and I2 charge the

capacitor during different time periods as shown in Figure 2-1B.

Initially, the voltage across the capacitor (Vc) is reset to ground. For

simplicity, let tl < t2 < tOUT. The capacitor voltage Vc stays at OV until the

first step arrives at time tl. Transistor M1 turns on and the voltage Vc linearly

increases with the current source I1 charging capacitor C. This linear increase

continues until time t2 when the second step arrives. For purposes of the following

discussion, the capacitor voltage at that instant is labeled Vtemp.

The value of Vtmp is computed during the period tl to t2 as

I6
Vtemp (t2 t1) (2-1)
C

Similarly, during the period t2 to touT (the time for the capacitor to charge to

VTH)
II + I2
VTH Vtemp = (tOUT t2) (22)
C

Solving Eqs. 2-1 and 2-2 gives:

Iltl + I2t2 CVTH
tour + (2-3)
Il + 12 Il + 12

where tour is the time when the output step makes its transition from low to high

voltage. Eq. 2-3 is symmetric with Iltl and I2t2 so the assumption that tl < t2 can

be relaxed. However, we still need to assume that tour occurs after t1 and t2 to

ensure the validity of the equations.

The minimum value of tour in Eq. 2-3 occurs if tour = t2 and substituting

into Eq. 2-3, gives


I2t2 Itl = CVTH


(2-4)









Therefore for general values of tour above the minimum value,


I2t2 Iltll < CVTH


(2-5)


Eq. 2-5 provides the relation to be met for Eq. 2-2 to be valid. For the special case

where II = 12 = I, then the output step time tot is the mean of tl and t2 plus a

programmable constant (CVTH/21).

For unequal values of I1 and 12,


Iltl + 12t2 CVTH
toUTr = + 1
li + I 2 I + 12


(2-6)


where CVTH is a constant. The above equation is valid, when


lIlt1 12 l < CVTH


(2-7)


In this case, then the output time step is the weighted average of t1 and t2 plus a

constant.

We can summarize the results obtained above in a single equation:

VTH
tl + ] for Ilitl 2t2l > CVTH and tl < t2 (2-8a)

CVTH
tour = 2 + for I1tl 12| l > CVTH and t2 < t (2-8b)

Iltl + 2t2 CVTH
t + 1t2 otherwise (2-8c)
I1 + 12 I1 + 12
In general for N input steps,

t, Intn CVTH
toUT + (29)


provided that VTH is large enough. The circuit can be further generalized to handle

negative weight values in several v--,v: for instance, using current sources that

sink current to ground as long as the output voltage stays positive and eventually

reaches VTH.









Inputs ti, t2 and output tour of the weighted average circuit are time-steps

and these time-steps are defined within a frame (Frame 1) as shown in Figure 2-2.

When a frame (Frame 1) ends, the inputs and the output steps also end and the

circuit is reset. As the next frame starts (Frame 2 in the figure), the circuit would

be ready to process the next set of inputs t1 and t2. Each frame should be long

enough to allow the weighted average circuit to produce its output. For bounded

frame lengths, there is a chance that the output will not occur.

FRAME 1 FRAME 2

tfl

INPUT 1
ti
INPUT 2


OUTPUT

tour

Figure 2-2. Inputs ti, t2 and output tour are defined within a frame


2.1.1 Reset Stage

In the circuit shown in Figure 2-1A, we have not shown an explicit reset stage.

Setting the capacitor's voltage to its initial voltage VTH through a transmission

gate is the functionality desired from the reset stage and this can be integrated

with the application's reset stage.

Later in this dissertation, we will discuss some applications of this time-mode

weighted average circuit: an edge detection circuit and a 3-tap FIR filter. These

applications have custom reset stages and the reset for the basic block is integrated

in these custom reset stages.











2.1.2 Measured Results

The weighted averaging circuit was fabricated using the AMI 0.6pm C\ !OS

process. Figure 2-3 shows the measured output tour when just one input is

provided to the circuit. The output tour is plotted for varying I. The values of

C and VTH in the circuit are 20pF and 2.5V respectively. Figure 2-4 also shows

the output tour when only one input occurringg at tl) is provided to the circuit.

The current source I is fixed at 1.05pA The input transition time ti was varied

externally and the output tour was measured and plotted. The output expected

from the block touT +CVH was also plotted. The values of C and VTH in

the circuit are 20pF and 2.5V respectively. The root mean squared error (VMSE)

between the expected results and the measured results obtained of the output tour

obtained was 0.26/s.

x 10-4 Output tout for varying current I1 with C=20 pF, Vref=2.5V
4.5

4 Expected results
Measured results
3.5

3





1.5
1

0.5-

0
05 ~ ~~^~~~-- -- ^

0 0.5 1 15 2 2.5 3
Charging Current 11 in Amps 106
x 10

Figure 2-3. Plot of touT for varying I (C = 20pF, VTH = 2.5V). The block was
given one step input.


Figure 2-5 shows the output tour when both the inputs are provided to the

circuit but the current sources I1 and I2 are fixed at 1.552/A. The first input

entering the block was fixed as lis, 8.5ps and 32.5/s for three different sets of

measurements. The input transition time t2 was varied externally for different











1x 10-5 tout with varying tl
I = 1.0476 uA
11 C=2.5pF
Vref=2.5V

10-

9-
U)
c8-

7-

6-

5 -Expected Results
Measured Results

4
0 1 2 3 4 5 6 7
0 t1 in secs
x10

Figure 2-4. Plot of tour for varying I (C = 20pF,I = 1.0476A, VTH =2.5V). The
block was given one step input.


values of tl and the output tour was measured and plotted. The output expected

from the block tour = t2 + CVT was also plotted. The values of C and VTH

in the circuit are 20pF and 2.5V respectively. The vMSE between the expected

results and the measured results obtained of the output tour obtained was 0.3ps.

Figure 2-6 shows the output tour for the case when both inputs are provided

to the circuit but the current sources 11 and 12 are different and are fixed at 1.46/A

and 0.29/A respectively. Similar to the above case, the first input entering the

block was fixed as 1/s, 8.5ps and 32.5/s for three different sets of measurements.

The input transition time t2 was varied externally for different values of tj and

the output tour was measured and plotted. The output expected from the block

tour I=i+ 22 + ( was also plotted. The values of C and VTH in the circuit

are 20pF and 2.5V respectively. The VMSE between the expected results and the

measured results obtained of the output tour obtained was 1.9ps.











x 10-5 tout for varying t2
6.5 x-.....

C = 20 pF
=1.552 uA
Vref = 2.5V
5.5 -
tl = 32.5 us
5-


I / tl = 8.5 us
4-

.5-

3- tl= 1 us

2.5



1.5
0 1 2 3 t. 4 5 6 7
t2 in sees _
x 10

Figure 2-5. Plot of tour for varying t2 (C = 20pF,I = 1.0476pA, VTH =2.5V with
tl fixed at lis, 8.5ps and 32.5ps.)


2.1.3 Discussion

Errors in the weighted average calculation arise from a number of sources

including:


* mismatches in capacitor and current source values.


* fundamental noise sources causing jitter in the timing of the input and output
step functions.


* transistor time d.l i for example through the comparator.

Each of these errors can be reduced somewhat with careful layout, larger

circuits, more power consumption, and/or calibration procedures. These tradeoffs

must be taken based on the demands of particular applications. Particular

advantages and disadvantages of the weighted average circuit and other time-mode

circuits must be carefully considered. It is likely that time-mode circuits will have

larger dynamic ranges than conventional designs but high speed operation will

be compromised since time is used in the representations. General claims are

difficult, especially considering that it even difficult to cite general advantages of










x 10-5 tout with varying t2

11 = 1.46u
6.5 12 = 0.29u
C = 20pF
6- Vref=2.5V tl = 32.5u

5.5 1'-

5-

4.5- tl =8.5u

4-

3.5&
tl =lu
3"-

2.5
S 1 2 3, 4 5 6 7
3t2 in secs 5 6 7
x 10-

Figure 2-6. Plot of tour for varying t2 (C = 20pF,1i = 1.46pA, I2 = 0.29pA,
VTH = 2.5V with tl fixed at 1is, 8.5ps and 32.5/s.)


current-mode circuits vs. voltage-mode circuits [7]. A big advantage of time-mode

circuits however is that more and more sensors are being designed with step

outputs [14] [15] and the time-mode circuits can directly interface to these sensors.

Table 2-1. Measured performance characteristics of time-mode weighted averaging
circuit.

Performance specification Value
Power consumption 0.6pW
SNR 56dB
Differential-mode dynamic range 62dB
Common-mode dynamic range Effectively infinite


By performing computation using temporal step functions, the averaging

block was able to achieve almost infinite common-mode dynamic range, 62dB

differential-mode dynamic range and SNR of 56dB with very low power consumption

of 0.6/pW. This power consumption was on the order of nanowatts, when the

comparator were operated in the sub-threshold region. But, the operating speed

of the comparator was slow. Therefore, we had to strike a trade-off between the









comparator's operating speed and the power consumption. The measured circuit

specifications are tabulated in Table 2-1.

2.2 Theoretical Analysis of Signal-to-Noise Ratio and Dynamic Range

There are two sources of output noise in a time-mode circuit.

1. output noise due to timing jitter at the inputs.

2. output noise due to fundamental noise sources in the circuit.

2.2.1 Output Noise due to Timing Jitter at the Inputs

We know that the output from the block shown in Figure 2-1A is:

1ltl + I2t2 CVTH
toUT = + Z; (2-10)
II + 12 Il + 12

Jitter At1 (across different input values it has a mean value of At1 and a variance

of At12 ) in the input t1, causes the following output

11(tl + At) + 12t2 CVTH
toUT = -+ (2-11)
II + 2 12 + 12

The jitter at the output AtouT1 is given by:


AtouT1 toUT1 tour
(tl + At,) + 12t2 CVTH Iltl 12t2 CVTH
I + 2 I1 + 2) 1 + 2 + +2
IA- (2-12)
II + '2

which is a simple scalar multiplication of Atl.

The mean of the output jitter scales accordingly as,

liAt1
AtouT (2-13)
I + I2

The variance of this noise can be easily derived to be,

I2At12l
AtouIT12 (2 14)
(I, + 12)2









Similarly, the variance if the output noise caused by the input time jitter At2

(corresponding to input t2),


AtOUT22 (2-15)
(I, + 12)2

The total variance of the noise at the output is given by,


AtOUT2 =AtOUT12 + AtOUT2
I2At 12 22 2t2
=( )+( 2At2)
(I + 12)2 (I + 2)2
I2At12 + 'At22
(216)
(I1 + 12)2

If II = 2, then

Atour2 A (2-17)
4
Since only a fraction (" 7 ) of the jitter at the inputs affect the output jitter, we

can v- that the time-mode weighted average circuit effectively reduces the jitter at

the inputs.

2.2.2 Output Noise due to Fundamental Noise Sources in the Circuit

Figure 2 -A illustrates the basic elements used to perform a weighted sum of

temporal signals. We already know that the output from this block is:

Iltl + 2t2 CVTH
tour T + (2 18)
Il + 12 I + 12

We will now derive an expression for the signal-to-noise ratio of this time-mode

weighted averaging circuit.

The first step towards the derivation is to define the signal. Assuming a

differential representation, let us refer the inputs and outputs of the averaging

block to its first input. For simplicity, let us assume ti as the first input. The two

inputs to the averaging block are defined as, t1 = tl tl = 0 and t2 t2 tl.

The output is defined as tour = tour t1. This output is defined as the signal. In









words, the signal is defined as the output tour of the averaging block referred to

the input tl.

Therefore, tour is given by:


tou = tour -tl
Itl + 12t2 CVTH
=( + ) -tl
II + 12 I1 + 12) t
Iltl + I2t2 + CVTH Iltl 2tl
II + 12
2(t2 tl) + CVTH (
(219)
II + '2

There are 3 noise sources that dominate the noise performance of this circuit.

1. Noise due to the current source I1.

2. Noise due to the current source I2.

3. Noise due to the voltage comparator.

These noise sources are uncorrelated and therefore we can consider the impact

of each of these noise sources individually on the output of the circuit.

2.2.2.1 Noise in tour due to noise in current source II

Let us assume that current source I1 is noisy with a noise current of AI1.

Therefore, the total current from the current source is given by I1 + Al1. Since

currents II + All and I2 charge the capacitor, the new output from the weighted

average circuit is given by,

2(t2 t) + CVTH (
toT1 + A ( 20)
II + AI1 + /2








The noise at the output AtouT can be calculated as shown below:

AtouT1 = tUTI iOUT
12(t2 tl) + CVTH 2(t2 tl) + CVTH
11 + AI + 12 1 + 12
(12(2 tl) + CVTH)(-A1)
(Il + A 1 + 12)(I1 12)
(12t2- 12tl + CVTH)(-Al1)
(221)
(I, + 12)2

The variance of this noise is given by
AOUT 2 (12t2 -21 + CVTH)2(AIl2) (2 22)
A ( (22)22)


2.2.2.2 Noise in touT due to noise in current source I2

Let us assume that current source I2 is noisy with a noise current of AI2.
Therefore, the total current from the current source is given by 12 + A12. Since
currents I, and I2 + Al2 charge the capacitor, the new output from the weighted
average circuit is given by,

(12 + A2)(t2 tl) + CVTH (
toUT2 = (2 23)
II + 12 + A12

The noise at the output AtouT can be calculated as shown below:

AtoT2 = tout ^OUT
(12 + A2)(t2 t) + CVTH 2(2 tl) +CVTH
1 +12 + A2 11 + 12
(t2- tl)(IlA12) ( A12
+ CVTH(
(I1 + 2 + A2) (I1 + 2) (I1 + 12 + A12)(1 + 2)
(t2 1)(1A2) A2T
(I 2)2 ++ CVT (1 + 12)2
12(tII2 1) CVTH
( 2)2 ) (2 24)
(II + 72 2









The variance of this noise is given by

At OUT2 2 (12 (t ) CVTH)2(A122)
(1I + 12)4

(11(t1- 2) + CVTH)2(A22) (
(I, + I2)4

2.2.2.3 Noise in tour due to noise in the comparator

Let us assume that current sources IA and I2 are noiseless and noise in the
comparator is given by AV. The output from the weighted average circuit for these

assumptions is given by,

(t2 ti) + C(VTH + AV)
tOUT3 (2 26)
1I + 2

The noise at the output AtOUT can be calculated as shown below:

AtOUT3 tOUT3 toUT
2(t2 tl) + C(VTH + AV) 12(t t) + CVTH
II + 12 I+ 12
CAV (2-27)
(I1 + 12)2

The variance of this noise is given by

S(CAV2)
AtOUT32 (2-28)
(I + 2) 4

For typical values, the noise variation denoted by Eq. 2-28 is negligible
compared to the noise variances shown in Eqs. 2-22 and 2-25. Therefore, in the

forthcoming calculations we neglect the noise contribution of the comparator.

Therefore, the total noise at the output of the averaging block is given by

2 (2t2 2t + CVTH)2(A12) (Ilt It2 + CVTH)2(A2 2
AOUT +-- 29)
(II + I2)4 (Il + :4









The noise in the current sources i1 and I2 is dominated by shot noise. In

general, shot noise due to a current source I is given by [16],


A12 -- (2-30)
5-

where r is the time during which the current source is ON and contributes to the

output and e is the charge of an electron.

Current source I, charges the capacitor during the time period tour tl.

Noise in the current source would affect the circuit only during this time period.

Therefore,


TI = tour tl

= (touT tl) (tl tl)

=toUT tl
I2(t2 t) + CVTH (
(2 31)
I1 + 12

Therefore,

Al ell
12 (t2-tl)+CVTH
11 +12
ell(Il + I2)
(2-32)
I2(t2 tl) + CVTH

Current source 12 charges the capacitor during the time period tour t2. Only

during this time period, the noise in the current source would affect the circuit.

Therefore,


72 o oUT t2

S(toUT tl) (t2 tl)
I2(t2 -tl) + CVTH (
(t2 tl)
l1 + 12
Il(tl t2) + CVTH
I +(2 )
II + 12









Therefore,


lel2
11(tl-t2)+CVTH
11+12
eI2(I1 + 2)
I1(t1 t2) + CVTH

Substituting Eqs. 2-32 and 2-34 into (2-29), we get


2 2t2 -2 12t VTH)2(ttl)+CITH

eli(I2(t2 ti) + CVTH) + e2(I1(t1 -
(I1 + I2)3
eCVTH(Il + 12)
(11 + I2)3
eCVTH
(11 + 12)2

The signal-to-noise ratio is given by:


I + CV H 2( ei2(I1+I2)
(I1tl t2 + CVTH) (il-t+CTH
S(I1 + 2)C
t2) + CVTH)


(2-35)


(2-36)


Eq. 2-36 gives the SNR for a time-mode weighted average circuit.

For an averaging circuit, I1 = I2 = I. Therefore,


SN (I(t2 tl) + CVTH)2
SNR =CV
eC VT H


The maximum value of this SNR occurs when


SCVTH
t2 tl =
I


(2-34)


(12(t2-tl)+CVTH)2
SNR = 11+12-
(11+12)2
(12(t2 ) + VTH)2
eCVTH


(2-37)




(2-38)









Substituting Eq. 2-38 into Eq. 2-37, we get

(I (CVT) + CVTH
SNRMAX CCVTH 7 2

(CVTH + CVTH)2
eCVTH
4(CVTH)2
eCVTH
4(CVTH) (2-39)
(2-39)
e

To quantify this peak SNR value, we substituted C = 2pF and VTH = 5V

(max value) in Eq. 2-39 and obtained a value of 84dB. This peak value can

be increased by further increasing the value of the capacitance. For a 20pF

capacitance, we get a SNR of 88dB.

2.2.3 Discussion

We should note that the SNR value obtained through the hand calculations

shown above is an approximation. We have neglected the effect of jitter at the

inputs and matching errors in the currents II, I2. Since these effects affect our noise

measurements and therefore the measured SNR value, we obtain different values for

calculated and measured SNR values.

2.3 Scaling of Time-Mode Weighted Average Circuit with Technology

As we have seen previously time-mode circuits promise very high dynamic

range and good SNR. An important question is how does the performance of

time-mode circuits scale as technology scales. Since the time-mode weighted

average circuit is the prototype of all the time-mode circuits discussed in this

thesis, we will project how the time-mode weighted circuit performs in terms

of Signal-to-Noise Ratio, Dynamic Range, Power Consumption and Energy

Consumption as technology scales.

We choose the current 180nm as the reference technology and 90nm, 65nm,

45nm and 32nm as future technologies for our simulations. PT:\i HSpice transistor









models are used for all the technologies Predictive technology models are

developed by the N ii..,- i. Integration and Modeling Group at Arizona State

University [17].

2.3.1 Simulation Setup

We used Synopsys HSPICE to simulate the time-mode weighted average

circuit in different current/future technology nodes. Low voltage cascode current

mirrors were used for current sources and a five transistor single-ended differential

amplifier (PMOS input pair, NMOS current mirror load) was used as a comparator.

In the differential amplifier, a higher W/L ratio for the PMOS inputs and smaller

W/L ratio for the loads was chosen to minimize noise and the effects of mismatch.

The comparator's systematic offset would affect only the constant component -

CVTh of the output and can be calibrated out later, if necessary.

To compare the performance of the weighted average circuit as technology

scales, the capacitance C and reference voltage VTH were kept constant across

different future technology nodes. This ensures that charging currents I, and I2

are the only variable circuit parameters and it allows an apt comparison of the

trends in dynamic range, power and SNR of the weighted average circuit across

technologies. To vary li and I2, we had to change the sizes of the transistors in the

low-voltage cascode current sources. For simplification, the two charging currents

I1 and I2 were kept constant. The transistors in the weighted average circuit (the

transistors of the low-voltage cascode current mirrors, comparator and the digital

switches) were sized for two possible scenarios:

* For every technology, the circuit was designed for the lowest possible current
to keep all transistors in active/saturation.

* The transistor sizes were fixed for the 180nm process and the transistor sizes
were scaled down by the factor with which the technology scales down.









It was argued previously that the only noise sources that contribute heavily

to the noise of the time-mode weighted averaging circuit are the shot noises of

the DC current sources I, and I2. The noise of the comparator is negligible.

To characterize the noise performance of the weighted average circuit across

various future technologies, noise analysis during transient simulation is required.

Since such an analysis is not readily available in our Cadence software setup, to

achieve this two noise current sources (with Guassian distribution) were generated

randomly in MATLAB and their RMS values were set according to equations

previously derived. These current sources model the shot noise of the current

sources I, and I2 and are connected in parallel to their respective current sources

during the simulations. These noise current sources were switched on only during

the period when the time steps turned on the DC current sources.

The timing of the first step is chosen as the time reference and was kept

constant for all technologies. In this way the output time had the same reference in

all technologies.

2.3.2 Results and Inferences

* Power Supply: The VDD was decreased from 1.3 V to 0.6 V with scaling of
technologies and the circuit worked well for all values. This shows that the
time mode circuits are not dependent on voltage ranges and hence voltage
supplies can be reduced easily without changing the design.

* C('! iging Current: With scaling of technology, charging currents I1 and
I2 follow a monotonically decreasing trend as shown in Figure 2-7. This
is because as technology scales, transistor sizes reduce and therefore, the
current conducted by the transistors scale down exponentially (following the
well-established large-signal long-channel/short-channel current equations).

* Dynamic Power/Average Power: As dynamic/average current scales down
exponentially with technology, dynamic power/average power scales down
exponentially as well. This trend can be seen in Figures 2-8 and 2 9.

* Dynamic Range: The dynamic range is defined as the maximum allowable
time difference between two time steps. If tl < t2, the maximum allowable
time difference between two time steps of a weighted average circuit is given
















Variation of Current With Scaling of Technology


Figure 2-7.










30



25



20
-


c 15
o-
a


Variation of capacitor charging current with scaling technology


Variation of Dynamic Power With Scaling Technology


- Constant Scaling
---Saturation Scaling


Scaling Technology


Variation of dynamic power with scaling technology


Figure 2-8.









by CVT. With the capacitor C and threshold voltage VTH fixed in our
1 "
simulations, the dynamic range is inversely dependent on current. With
an almost exponential decrease in current we would expect an exponential
increase in dynamic range and the same trend can be noted in Figure 2-14.

* Energy Consumed: As power consumed by the weighted average circuit
scales down exponentially with technology, so does the energy consumed by
the circuit per weighted average operation. This trend can be noted from
Fig. 2-10.

* Weighted Average Outputs: From Figure 2-11 comparing the simulated and
calculated values of the output of the weighted average circuit, we see that the
simulated results match the calculated results well. We believe that the slight
difference in results as technology scales is due to inaccuracy in circuit models
at low current levels.

* Output Noise: The simulated noise and calculated output noise values match
closely as shown in Figure 2-12 confirming the accuracy of the derived
expression for noise of this circuit. Also, noise is inversely proportional to
current with all other factors remaining the same. Hence with exponential
type decrease in current we see an exponential type increase in noise.

* SNR: Observations similar to those made for the output noise can also be
made with the simulated and calculated SNR values as shown in Figure 2-13.
The signal, which is the time taken by the weighted average circuit to produce
an output, increases as we scale technology. With the noise also increasing
with scaling technology we note that the ratio of signal power and noise power,
the SNR, actually decreases only slightly with scaling technology. This is
in accordance to what was predicted by our equations. With more detailed
analysis, (with all other factors constant) we can note that the SNR is slightly
dependent on the current. So as current decreases with technology, SNR also
decreases. However, in Eq. 2-37, the I(t2 tl) term is much smaller than the
CVTH term causing SNR to be almost a constant. Also, slight variations in the
simulated SNR results confirm this analysis.

For all the above mentioned performance measures, for both the transistor

sizing scenarios sizing the transistors so that the transistors are in the active

region and sizing the transistors by the technology scaling factor, we see the same


performance trend.











Variation of Average Power With Scaling Technology
60
--- Constant Scaling
Saturation Scaling
50


40 -


.c 30
a0






---
1 Snm 90nm 65nm 45nm 32nm
Scaling Technology


Figure 2 9. Variation of average power with scaling technology



2.3.3 Discussion

We see that the dynamic range of inputs supported by the time-mode circuits

keeps increasing exponentially with scaling technology. For voltage mode and

current mode circuits as technology scales the input dynamic range supported

reduces (because scaling technology reduces the supply voltage and the maximum

current supported by the devices). But, for time-mode circuits, as technology scales

the input DR supported increases (scaling technology does not affect information

stored in time). This is a very promising aspect of time-mode circuits when

compared to voltage-mode and current-mode circuits.

With scaling technology, though the noise performance of the circuit gets

worse the SNR stays a constant. Therefore, applications using time-mode circuits

can expect the SNR performance of the time-mode circuits to remain constant with

new technologies.











As technology scales, time-mode circuits become more power and energy

efficient. Therefore, they can be chosen for low-power applications across different

device technologies.


X 10 Variation of Energy Consumed Per Averaging Operation With Scaling Technology
\ --- Constant Scaling
\e -e-Saturation Scaling
2.5 -

\
2-


1\.5

i\



0.1-
0.5 s --



1 0nm 90nm 65nm 45nm 32nm
Scaling Technology


Figure 2-10. Variation of energy consumed per averaging operation with scaling
technology



The results from the experiments are very encouraging and reinforce the

fact that time-mode circuits would scale well with technology and show good

performance.

2.3.4 Drawbacks

Time-mode circuits have shown promising results, however certain design

issues can limit their performance.


* Right now the measurement of the output timing was done when the input of
the comparator reached the threshold. The d. 1iv of the comparator would be
another offset but this would be highly dependent on the load. When these
circuits are used with larger fan out, the offset caused due to the capacitive
load at the output would not remain constant.


* While the current sources are charging the capacitor the VDS across the input
switching transistors does not remain constant and causes variations in the
















Comparison of calculated and simulated time-mode averaging outputs over technologies
-- Simulated Constant Scaling
-E-Calculated Constant Scaling
---Simulated Saturation Scaling
-*-Calculated Saturation Scaling


0.35

S0.3
o)
S0.25
E
H 0.2


0 15I


Scaling Technology


Figure 2-11.










0.7


0.6


0.5


= 0.4-


0.3


Comparison of calculated and simulated time-mode averaging

outputs over technologies







Comparison of calculated and simulated time-mode averaging output noise over technologies
-B- Simulated Constant Scaling
-e- Calculated Constant Scaling
-*--Simulated Saturation Scaling
*--Calculated Saturation Scaling


65nm 45nm
Scaling Technology


Figure 2-12. Comparison of calculated and simulated time-mode averaging output

noise over technologies














Comparison of calculated and simulated time-mode averaging SNR values over technologies




--- -- -- -------4------ *-----












-- Simulated Constant Scaling
-a-- Calculated Constant Scaling
-*--Simulated Saturation Scaling
-4--Calculated Saturation Scaling


65nm
Scaling Technology


Figure 2-13.


Comparison of calculated and simulated time-mode averaging SNR
values over technologies






Variation of Dynamic Range With Scaling Technology


-- Constant Sca
- -Saturation Sc


0.7

0.6


ling
aling



/-







^a




.--o--8-------- ^___
/f
Il'l
II~ll **//I /*l} /


0.2 -


----
1 3nm


90nm


65nm
Scaling Technology


Figure 2-14. Variation of dynamic range with scaling technology


45


40


30onm


45nm









current. Having larger lengths for these transistors is critical for accurate
operation.

* Input switching causes coupling between the gate and drain and we see a large
spiking current initially. If the tour to be calculated is small, this can cause
problems in accuracy.

* A limitation to the accuracy of these results is due to limitations of the
simulator as we try to operate at very low currents and measure up to six
significant digits. This is especially true in case of noise current, where we
believe the errors creep in due to numerical methods and round off. However,
these precision issues do not change the trend in the results.

2.4 Carbon Nanotube Based Time-Mode Weighted Averaging Circuit

To see if the time-mode weighted averaging circuit would scale well in the

nano-technology regime, we replace the traditional BSIMv3.1 AMI 0.5pm Si

transistor models by carbon nanotube FET models [18] and simulate our prototype

weighted average circuit. Transistors MI, 1., Current Sources II, I2, and the

inverters of the weighted averaging circuit are realized using NCNFET and

PCNFET models developed by Roy et al of INAC/Purdue. The circuit is simulated

using HSPICE. The NCNFET and PCNFET transistor models used in our

simulations have only a single carbon nanotube representing their channels. The

'I-.-, -I advantage of this single carbon nanotube technology is that the transistors

have extremely small gate and channel capacitances; thus, promising very high

speed operation.

2.4.1 Carbon Nanotube Field Effect Transistors (CNFETs) and Their
Spice Models

Carbon nanotubes are nano-diameter cylinders consisting of a single

graphene sheet wrapped up to form a tube. Since their invention in the early

1990s, researchers have been actively exploring the electrical properties of these

devices and their potential applications in electronics. One of the most promising

applications of carbon nanotubes, the carbon nanotube transistor (CNTFET) -

first reported in 1998, is currently considered as the most promising building block









of a future nano-electronic era. The reason for this is not just their small size, but

their inherent properties like low power dissipation, possible ballistic transport,

high current densities, high mobility, low resistance and the facilitation of making

transistors and interconnects using semi-conducting and metallic carbon nanotubes.

For a typical nanotube geometry of 100nm length and 3nm diameter, C is of

order 4aF. The channel resistance can be as small as 6.25kQ. Therefore, the RC

frequency is equal to 6.3THz [19]. Let us compare this frequency with the fT of

a minimum size NMOS transistor in the AMI 0.5u Si process. The fr of a NMOS

transistor can be roughly expressed as,


fT (VGS VTH) (2-40)
27rL2

with p the mobility, L the channel length, VGS the gate to source voltage and

VTH the threshold voltage. Substituting typical values of p = 449.98cm2/Vs,

L = 0.6pm, VGS VTH 4V for AMI 0.5u Si process, we get fT 80GHz. This

shows that the speed limit intrinsic to a nanotube transistor is several orders of

magnitude greater than a Si transistor.

The CNFET model used in our simulations is a simplistic model that

was developed to assess circuit performance of single walled semiconducting

CNFETs. It is an appropriate model to evaluate d4-i-,, estimate power in

circuits and simulate the performance degradation due to interconnect and device

parasitics. The modeling technique used is generic in the sense that it can faithfully

represent a wide range of CNFET geometries and gate materials with reasonable

operating voltages and user specified temperature conditions. The model has a

strong foundation on the underlying physics of operation along with necessary

simplifications and assumptions. This makes a multiple-transistor circuit simulation

possible.

The assumptions made to arrive at the CNFET spice model include,









Bulk-type CNFETs: In the literature, two types of carbon nanotube

transistors have been studied extensively. They are respectively, the Schottky

barrier CNFET and the bulk-type CNFET. Though the Schottky barrier

CNFET has its own advantages, the model assumes a bulk-type CNFET as

this MOSFET-like device has a higher on-current and, hence, would define the

upper limit of performance.

Ballistic transport: Recent experiments have demonstrated that a CNFET

can typically be used in the MOSFET-like mode of operation with near ballistic

transport.

2.4.2 Physics Governing the Operation of CNFET

It is a well established fact that gate voltage induces charge in the CNFET

channel and also modulates the top of the energy band between the source and the

drain. As the source-drain barrier is lowered, current flows between the source and

the drain. Since we are dealing with ballistic transport, all scattering mechanisms

are neglected.

2.4.3 Simulation Results

The rail-to-rail supply voltage used in our simulations is 0.6V. The simulation

outputs are shown in Figure 2-17. For the simulations we chose t1 = Ins, t2 3ns,

C = 7fF and VTH = 0.5V. Since the CNFET spice models are simplistic models

and not ideal for analog simulations instead of the 5-transistor comparator, we

chose an ideal op-amp to perform the comparator's functionality. The expected

tour and the calculated tour values match closely and they are approximately

equal to 9ns. The small difference between the two tour values can be attributed

to the OFF current of the CNFETs charging the capacitor. The carbon nanotube

transistors have very high current drive as can be seen from Figures 2-15, 2-16

and from Figure 2-18 we can see that the off-current of these carbon nanotubes is

also high (in the order of 30nA). These high off-currents can produce an offset that







33



introduces some jitter in the output. In spite of the large off currents, the average

power consumed by the circuit is 0.33/ W.

100u -
10 0 u --- ,. . . . ..--- -.----------- -- --------- --------------------------.. .
,ydrain=O
90u ....----------- - ------- ----------- --- --- - ----


70u --- ---' ------------ ----------------- -- -------------------------- ---
70u '- '

Vdrain=.3A %

650u ----vd =- l--------------
50u --- ;.-;- :...--------------------------- -------------------------- ---
rain



Vdrain .5
20u ----------*--------------
-, ,.


0 _-Vdrain=g.6__________ ---Vg _--- ---- --.... -----

0 200m 400m 600m
Voltage X (lin) (VOLTS)

Figure 2-15. PCNFET ID-VGS plots for varying VDS



2.4.4 Discussion

We did not plot the performance results of these carbon nanotube transistor

based time-mode circuits with the Si technology scaling curves discussed in the

previous section because these CNFET models are totally different from the PTA\

models used for all the Si processes. But, it would be extremely useful if we can

still compare the performance numbers obtained from the scaling Si simulations

and the CNFET based circuit's simulations. The carbon nanotube transistor based

time-mode circuits have parasitic capacitances in the range of aF (compared to

fF for the silicon based transistors), have high current drive therefore high speed

(because of the high current drive of carbon nanotube transistors) and are very

power efficient (power even lower than the corresponding 32nm process based

averaging circuit's power). Since nano-technology promises very attractive features







34





-10u
o --l -...... ----------. --- --- -- --- -- --- -- --... .. .. .. .. .. .. .. .. .. .. .. .. .. .. ...----- -



0u ....... ..... ....
0u --- ... ......................-- ...- ..............-- -----: -- -a.-, '----
-40u
-70u


40u







-100u
S- ---. .... ... ......... .; .- .. ............ T


20 'm. "400m .m
Voltage X (lin) (VOLTS) ri=.2
-70u - --......... -.-....... .. -......... .. ..... .....i.. .. .-- - -


2.5 Reliable Time-Mode Weighted A Vdrage Circuit










2.5.1 MotivationVate
0 200m 400m 600rn
Voltage X (lin) (VDLTS)

Figure 2 16. NCNFET ID-VGS plots for varying VDS



and performance for time-mode circuits, we can safely -i that time-mode circuits

scale well into the future technologies.

2.5 Reliable Time-Mode Weighted Average Circuit

2.5.1 Motivation

The reliability of integrated circuits is a i i, Pr concern for the electronics

industry and becomes more of a concern as processes scale down to deep

sub-micron C'\ OS and future nanotechnologies [20]. As these process technologies

become more and more complex, higher levels of integration used in the ICs will

increase the chip failure rate. These failures underscore the importance of reliability

for manufacturing of nano-scale systems. It is, therefore, imperative that circuits

are designed with reliability in mind.

Construction of reliable digital systems with the use of redundant components

was first considered by Von Neumann for certain cases of intermittent failures of

elements [21]. His ground-breaking work was extended by Dickinson and Walker

for the case of permanent failures of logic elements [22]. But the works of Von















































0 En 10n 15n 20n
Time (lin) (TIME)


Figure 2-17. Nano-weighted average circuit simulation outputs


0 -

-5n .

-100n

-150n

-200n

-250n

-300n

-350n

-400n

-450n

-500n

-550n


*---------------------- ------





- --- --------------- ------------------- ------------------- ----------------- --





--- ---------- ----- ------------------- *- ------------------- I ----------------- --
















0 5n o1n 15n 20n
Time (lin) (TIME)


Figure 2-18. Capacitor charging/discharging current

circuit


in a nano-weighted average









Neumann, Dickinson and Walker and many others were all dedicated to improving

the reliability of digital circuits. In this chapter, we discuss the design of reliable

analog nanocomputational circuits using redundancy. As an example, we will

explain the design of a reliable analog time-mode weighted average circuit.

2.5.2 Time-Mode Median Circuit

Figure 2-19 illustrates the basic elements used to find the median of an

odd-number of input temporal signals. In general, the circuit can process many

input steps, but only three are shown here for simplicity. The circuit consists of an

inverter, a current source of value I and a PMOS transistor for each input and a

current source of value I connected to the drains of the transistors MI, I and

i The rising edges of the input steps correspond to the time values t1, t2 and t3

which represent three input values. The PMOS transistors MI, I and I act as

switches.





M1 L M2 M



31
2 tOUT


Figure 2-19. Time-mode median circuit for 3-inputs


To aid the explanation of the operation of this circuit, we assume that

tl < t2 < t though such a condition is not necessary for the operation of the

circuit. Since the input step making its low-high transition at time tl enters the

median block first, it switches transistor M1 on. Since the current source of value

3 is discharging the parasitic capacitance Cp, there won't be any charge built up
across the parasitic capacitance. However, when the second step enters the block
across the parasitic capacitance. However, when the second step enters the block









at time t2, a net current of 1 charges the parasitic capacitance and starts adding
charge to the capacitor and we will get an output step at time tour. Since the

parasitic capacitance gets quickly charged after the second step enters the median

block,

tour t2 (2-41)

Thus, we see that the output obtained in Eq. 2-41 is the median of the three
inputs tl, t2 and t3. In general, this median circuit can process N-input steps -

provided that N is odd. The circuit is shown in Figure 2-20. Depending on the

value of N, the value of the current source that pulls-down the capacitor's voltage
is chosen to be N. It is to be noted that using conventional voltage-mode and

current-mode analog circuit designs it is difficult to design such a simple circuit to

perform a median operation among various inputs.




rrr
M M2 nA IZ"l M


NI
2 toUT


Figure 2-20. Time-mode median circuit for N-inputs


2.5.3 Redundancy in Time-Mode Computation

We will explain the concept of improving reliability using redundancy through

the design of a reliable analog time-mode weighted average circuit that has an
architecture similar to Von Neumann's 2-out-of-3 1i lini i ly circuit shown in

Figure 2-21 and perform win 1 ,-i- to quantify its reliability.

Von Neumann's 2-out-of-3 i, lin i ly circuit shown in Figure 2-21 uses a
i, i ii ly circuit fed by three independent devices which operate from the same


















Figure 2-21. Von Neumann's two-out-of-three i li, i ily circuit


source of input information [21]. Dickinson and Walker analyzed the circuit in

detail and proved that the circuit has a resultant reliability greater than that of

its elements [22]. As mentioned above, their work was only applicable to digital

circuits. Here, we use their concept to improve the reliability of analog circuits. We

will extend the work of Dickinson and Walker to design a reliable analog time-mode

weighted average circuit as shown in Figure 2-22. Von Neumann's 2-out-of-3

i I .i ii ly circuit is essentially used polling between inputs and can only be used for

digital applications. Therefore, it is being replaced by a time-mode median circuit

as shown in Figure 2-19. For our failure analysis, we assume that the median

circuit never fails. The same assumption is made for the digital voting circuits

discussed above. The only failures to be considered are those of the three elements

(weighted average blocks) which feed the median circuit.

The time-mode weighted average block has components like current sources,

digital switches, comparator and a capacitor. It is possible for any of these

components to fail and introduce errors in the output of the circuit. For explanation

purposes, let the output of the weighted average circuit when there are no failures

in its components be toidJl and the output when there are some failures be t tned.

The weighted average blocks can fail in two modes:

1. tbtired < tide. This also includes the case where due to failure there is no
output from the weighted average block (tobtained is close to infinity).


















INPUTS Th e AVERAGE tVIY iit ------y- s
CIRCUIT CIRCUIT OUTPUT




WEIGHTED
AVERAGE
CIRCUIT


Figure 2-22. Block diagram of a reliable time-mode weighted average circuit


2. ttied > otail. This also includes the case where due to failure, the weighted
average block fires an output immediately after its internal nodes are reset
(the reset stage is not shown in the figure) (titie"d is close to zero).

Let us assume that the probability that any weighted average block will

function correctly is Ro. The probability that the redundant system is not going to

fail R1 is given by the sum of the three cases mentioned below:

1. All the three time-mode weighted average blocks function correctly. The
probability that the redundant system is not going to fail in this case is given
by R3.

2. One of the weighted average blocks fail in any of the two modes (tbtgined
t ) o (obtaied < ideao) mentioned earlier and the other two function
correctly, in which case the output of the system would still be correct. The
probability for this case is given by (1 Ro)Rl Since this case can happen in
three different v--,v, the total probability for this case is 3(1 Ro)R,.

3. Two of the three weighted average blocks fail in this case but we assume that
the elements have equal probability of failing in either of the modes. That
means that there is a probability of 1 that the two weighted average blocks
will fail in opposite directions (one block firing output early and the other
firing output late), in which case the output of the redundant system would
still be correct. The probability that two elements fail and the others still









function correctly is (1 Ro)2R0 and this can happen in three different v--v.
Therefore, the probability for this case is given by (1 Ro)2Ro.

Therefore, the total probability that the redundant system is not going to fail

R1 is given by the sum of the probabilities obtained in the above mentioned three

cases [22]:


R1 R + 3(1- Ro)R (1 Ro)2p
2
3 1
= o 3 (2-42)
2 2


100







-- Reliability of the redudalt eircfit
2^





S- -Reliability of tie individual elements

10-6
S --Reliability of the redudanit circuit



103 102 101 100
Probability of failure of the individual elements

Figure 2-23. Plot showing the increase in reliability of the redundant circuit as
compared to the individual elements


From the result shown in Eq. 2-42, we see that the redundant time-mode

weighted average circuit is ahv-- -i more reliable than the individual elements.

This can also be realized from the reliability curve in Figure 2-23. As shown in

that figure, there is a considerable improvement in the reliability of the redundant

circuit as compared to the reliability of the individual elements.

2.5.4 Discussion

We see that for the above 2 cases, redundancy provides additional reliability

for the weighted average circuit. 1_ f, circuit designers would be concerned






41


that such redundancy would increase the chip area. But, most of the real time

applications would compromise on the chip area than on the reliability of the

circuits. Also, this redundant weighted average circuit can be seen as a stepping

stone towards improving the reliability of nanocomputational circuits.

In C'! lpter 2, we will see how the performance of the time-mode weighted

averaging circuit with its voltage-mode and current-mode counterparts.















CHAPTER 3
SNR COMPARISON OF WEIGHTED AVERAGING CIRCUITS

We have quantified the performance of time-mode circuits in terms of

key measures such as SNR, DR and power consumption. These performance

metrics are not clear-cut. For instance, dynamic range is a well-defined concept

in voltage-mode and current-mode but must be carefully considered for some

time-mode circuits whose inputs can be arbitrarily large.

We need to compare the performance measures such as SNR and DR of

time-mode circuits to corresponding voltage-mode and current-mode circuits by

making a ceteris paribus (other things being equal) comparison. Since it is difficult

to compare all possible voltage-mode, current-mode and time-mode computation

circuits, we would like to start by restricting ourselves to the comparison of

weighted average circuits shown in the Figures 3-1, 3-3 and the time-mode

weighted averaging circuit discussed in C!i lpter 2. We will quantize their SNR

and DR, compare their performances, and comment on them. The main criteria

for the choice of these voltage and current mode weighted average circuits are low

complexity and low power consumption. The choice would enable us to perform a

fair comparison with the basic two-input time-mode weighted average circuit.

The first circuit operating in voltage-mode computes

SgiVV + g2V2 (3
VOUT = (3-1)
g + 92

where gi and g2 represent the transconductances of the two OTAs in the circuit.

The transconductances are set by the individual bias voltages applied to the OTAs.

V1, V2 are the two input voltages and VOUT is the output voltage of the circuit.









The second circuit operating in current-mode computes

ek1 + ek212
loUT (3-2)
eki + Ck2

where i1, I2 are the two input currents and VOUT is the output current of the

circuit. kl, k2 are the voltages applied to the transistors in the circuit. These

voltages contribute to the weights ek1 and ek2 applied by the circuit to compute the

weighted average.

And, as we have seen in C'i plter 2, the time-mode weighted averaging circuit

computes
1ltl + I2t2 CVTH
toUT + (3 3)
IIl + 12 1I + 12
As mentioned earlier, though we can come up with more efficient circuits,

the voltage-mode, current-mode and time-mode averaging circuits compared in

this paper are chosen such that their circuit architecture is extremely simple and

consume very low power.

To quantify the SNR relations obtained for voltage-mode, current-mode and

time-mode averaging circuits, let's make the following assumptions.

* no load capacitance is connected at the output node.

* for simplicity, we assume that all the transistors involved in the analyses have
the same dimensions: W = 6pm and L = 20/m.

* the transistors operate at room temperature.

* process parameters of AMI 0.5/ process are used.

3.1 Voltage-Mode Averaging Circuit

Figure 3-1 illustrates the basic elements used to perform a weighted average of

voltage-mode signals V1 and V2. It consists of two transconductance amplifiers GC

and G2 connected in unity feedback configurations.


















V,



Figure 3-1. Voltage mode weighted averaging circuit


The output of the circuit is given by the equation:

giVi + g2V2
VOUT = (3-4)
gl +g2

For SNR calculations, we need to define a reference for the inputs and outputs.

Let us define the input V as the reference.

Now, VOUT defined with respect to the reference would be given by,


VOUT VOUT VI
91gi Vi+g2 2V2
gi + g2
glV + g2V2 g1V g2Vi
g9 + g2
g2(V2 V)(3 )
gl + g2

There are two noises sources in this circuit as shown in Figure 3-2.

1. Avi2 noise due to operational transconductance amplifier g, referred to its
positive input.

2. Av22 noise due to operational transconductance amplifier g2 referred to its
positive input.

Since these two noise sources are not correlated, we can derive the individual

contribution of each of these noise sources at the output and add up the contributions

by applying superposition.










V:



VOLJT

AV2VU
V2g2


Figure 3-2. Voltage mode weighted averaging circuit with noise sources


3.1.1 Noise Contribution at the Output due to Av12

At one particular instant in time, if the instantaneous noise of OTA1 is Avl,

then the instantaneous noise at the output is give by,

A U 92(V2 (VI + A)) g2(V2 VI)
Vou -T = -
91g +92 91 + 92
( A) (3-6)
91 +92

The variance of the noise at the output is given by,

Ug2AV12
AVOUT g9 (3 7)
(g + 92)

Similar calculations are done for the noise contribution from OTA2.

3.1.2 Noise Contribution at the Output due to Av22

At one particular instant in time, if the instantaneous noise of OTA2 is Av2,

then the instantaneous noise at the output is give by,

gO 92((V2+A 2) -Vi) 92 (V2 Vi)
A VOUT2
91 +92 91+ 92
S(A ) (3-8)
9g + g2

The variance of the noise at the output is given by,

./2 2
AVOUT22 2 A-2 (3-9)
(g9 + g)92









Therefore, the total noise contribution at the output due to the two noise

sources is given by,
2- g(A +A1+2 A2)
AVOUT22 = 92 + AY-2- (3-10)
(g9 + g2)2
Assuming that the OTAs are basic 5-transistor differential input/single

ended output OTAs, we would have noise contributions from the input transistors

and the mirror transistors. Neglecting flicker noise of these transistors (valid

for intermediate and high frequencies) and taking only thermal noise into our

calculations, the input referred noise variances are given by:


AVouT12 4(k)Af (311)
3gl

8kT
VOUT22 = 4( )Af (3-12)
3g2

3.1.3 Noise Bandwidth

The voltage-mode weighted averaging circuit has a pole at its output that

occurs at
1
fc = (3-13)
27 ROUTCOUT

where, COUT is the capacitance at the output node, usually defined by the load

capacitance CL.
1 1 1
ROUT = 11 | (3-14)
gl g2 1 + 92
Hence,
1 gl + g2
f 1 +2 (3 15)
27 CouT 2i COUT
91+92
If an amplifier has just one pole at fc, then the noise bandwidth is given by


Af 2f 2 = (1 ) = 2 (3 16)
2 f2 2CCoUT 4COUT









The signal-to-noise ratio is given by
2g(V2-Vl)2
SNR (91+92)2
SNR =
g9 (Av12 +Av22)
(91+92)2
(V2 Vl)2
(Av2 + Av22)
(V2 V1)2
4( 8T + 8))Af
39 31 2 /392
(V2 V1)2
48kT + 8kT)( 91+92
329 32 4COUT
(V2 V1)2
S8kT ( 9l+2 ( 91+92
3 9192 4COUT
3 (V V1)2192CouT
(3-17)
8kT (gl + g2)2

For an averaging circuit, g = g2 and the SNR relation becomes,

3
SNR = (V2 V)2COUT (3 18)
32kT

For AMI 0.5p process, maximum value of V2 VI that could be achieved

3.5V (thought the rail-to-rail voltage is 5V, to maintain the transistors of the

OTA in saturation the input voltage swing would be lower). Also, through hand

calculations we found out that the output node capacitance is 0.4pF. Substituting

all the values to Eq. 3-18, we get maximum SNR of 80dB.

3.2 Current-Mode Averaging Circuit

Figure 3-3 illustrates the circuit that performs weighted average of currents I,

and I2. In this circuit, transistors M1-M4 operate in the sub-threshold region and

they are in saturation.

We assume that in all the sub-threshold current equations below that K = 1.

By using KCL at nodes 1 and 2 in Figure 3-3, we can write

K2-VA K1 VA
S= Ise VT +Ise VT
VA K1 K2
= Ise [e + eV] (3-19)




















Figure 3-3.


Current mode weighted averaging circuit


and


K2 VB K1 VB
SIse VT + Ise VT
VB K1 K2
=Ise g [e T + e ]


From Eqs. 3-19 and 3-20, we get

VA
li e VT
12 C VT

The output current is given by

K1-VA K2 VB
ouT = Ise T + Ise VT


Figure 3-4. Current mode weighted averaging circuit with noise sources


(3-20)


(3-21)


(3-22)










Substituting Eq. 3-21 in Eq. 3-22, we get

VA K1 12 K2
IouT Ise VT [eV' + e- ]
K1 K2
VA [I/eVr + I2eC T
Ise VT (323)
I1

Using Eq. 3-19 in Eq. 3-23, we get
K1 K2
ierV + I2 eV
IOUT = 1 K2 (3-24)
eVT + CVT

Figure 3-4 shows the current mode weighted averaging circuit with noise

sources. As shown in the figure, there is noise associated with each transistor in the

circuit and the equivalent noise variances can be represented using current sources

connected in parallel to the transistors. The noise current source All sees the

source resistance 1 of transistor M1 and the source resistance 1 of transistor
9ml 9m2
if[. as shown in Figure 3-5. Since K = K2, g91 g 2. Therefore, half of the

current All flows through transistor 11 and contributes to noise in the output

current louT. Similarly only half of noise currents AI2, A13 and AI4 contributes to

output noise.

Therefore, the total output noise current is given by


A1U + AI2 + A13 + A4)
AlouT = (325)
2

The variance in the output noise current is given by

A T2 A12 + A22 +A32 +2 a (42
Alour (3-26)
4

Neglecting flicker noise, the noise current of a transistor operating in the

subthreshold region is given by 2KTgm. Substituting this noise current expression









in Eq. 3-26, we get

T2 Al12 + A22 AI + A 42
4
(2KTgm + 2KTg9m2)Af + (2KTgm3 + 2KTg4)Af (3
(3-27)
4

where the noise currents of transistors M1 and i [. would have a noise bandwidth

determined by R-C time constant of node 1 and noise currents of transistors i..

and M4 would have a noise bandwidth determined by R-C time constant of node 2.

Since K = K2, for subthreshold transistors gmi = gm2. Similarly, g,3 g9 4.

Therefore,

AIouT2 (KTgmrl)Afl + (KTgm3)Af2 (3-28)






11/g
b M Al2





I
Figure 3-5. Half of the noise current from each transistor flows to the output


The pole contributed by node 1 is given by:

1 gl9m
fnodel
f 2odel w 1 l (3 29)
2 !- 1-i~nodel 7 Cnodel

Noise bandwidth for noise currents of transistors M1 and i [. is given by,

Aflt f 7r ( )gmi gm (3 30)
2 2 TTCnodel 2Cnodel

The pole contributed by node 2 is given by:

1 gm3
fnode2 1 (3 3)
27r "- node2 7node2









Noise bandwidth for noise currents of transistors .1 and M4 is given by,

if -F gm3 gm3
Af node2 ) 9Tf (3 32)
2 2 T Cnode2 2Cnodel

as parasitic capacitance Cnodel = Cnode2-

The variance in the output noise current is given by,

A T 2 / \9mnl \9m3
AIT = (KTgmi) + (KTgmm3) 3
2Cnodel 2Cnode2
kT
= C0 (19g1 + 9gm2
2Cnodel
kT
okT 1 2) (3 33)
2Cnode IVT,

Since the discussions would get too complex, let us just focus our discussions

here to current mode averaging functionality. Lets assume that K = K2. The

output IouT in this case is given by IOUT = 1+2 The output referred to the first

input I1 is given by,


IOUT = IOUT II
II + I2
2
I I2
S12 (3-34)


The signal-to-noise ratio is given by

(12-11)2
SNR = 4
2kT 2 (J21 Ij22)

VT2 Cod (12 1)2 (
2kT(1I2 + 22)

To quantify the SNR equation, we substituted these nominal values: Cnode =

0.4pF (as in the voltage-mode case), I, = InA (low sub-threshold current) and

I2 = 20nA (high subthreshold current) in Eq. 3-35. The maximum SNR that can

be obtained from this circuit is 44dB.






52



3.3 Discussion

Clearly, the SNR achieved by the time-mode weighted average circuit is higher

than the SNR achieved by voltage-mode and current-mode weighted average

circuits. The SNR values obtained from simulations differ only by 1 from the

SNR values obtained through hand-calculations as shown in Figure 3-6.

Comparison of calculated and simulated SNR Values


Simulated
Calculated
32nm


30
130nm


Figure 3-6. Calculated and simulated SNR values of a time-mode weighted
averaging circuit over technology



So far we have just discussed a single type of time-mode circuit the weighted

averaging circuit. In C(i lpter 4, we will describe other time-mode computational

circuits.















CHAPTER 4
OTHER TIME-MODE CIRCUIT EXAMPLES

In this chapter, we will introduce a family of time-mode circuits that can

perform linear computations like weighted subtraction, weighted sum, scalar

multiplication, maximum and minimum computations.

4.1 Weighted Subtraction Circuit

By replacing the PMOS transistor I. by an NMOS transistor and changing

the direction of the I2 of the basic block in Figure 2-1A, we obtain a circuit that

can perform weighted subtraction of steps occurring at t and t2 as shown in

Figure 4-1A.

VC


M CHARGED DISCHARGED
BY I BY I 211


T v V -- --- -- -- -
M2 (with initial TH
t2 1 voltage VTH)
SOUTH

A) B)

Figure 4-1. Weighted subtraction circuit. A) Circuit schematic. B) Idealized graph
showing the capacitor's voltage at different time periods.


We will assume that the capacitor is initially charged to a voltage VTH, tl < t2,

I2 > I1. As soon as the first step enters the block at time tl, the current source I1

starts to charge the capacitor. When the input step occurs at time t2, net current

I2 I1 (with I2 > I1) starts discharging the capacitor as shown in Figure 4-1B.

When the capacitor voltage reaches VTH, the comparator outputs a step at time

touT. The output of the comparator contains an unwanted pulse at the reference









time because the positive and negative terminals of the comparator carries the

same voltage VTH. The AND gate connected to the output of the comparator

ensures that the output from the block contains only a step output at time tour.

Once the block outputs a step, an appropriate reset stage (not shown in the figure)

resets the capacitor to OV.

The output tour from the block is given by the equation,

I t2 1ti
tour 12t2 (4-1)
2 I1

We see from the equation above that, the block applies a weight 12/(12 II) to t2

and a weight 11/(I2 1) to t1. This block has a single-ended output.

Without the assumptions made above, different outputs given out by the block

can be summarized in a single equation:

12t2 1t
'2t2 t for tl < t2, 2 > I (4-2a)
toUT Iltl 12t2
lt II
touT, for ti > t2,2 < II (4-2b)
II 2
No output, otherwise (4-2c)

As in the weighted averaging circuit, inputs tl, t2 and output tour are

time-steps and are defined within a frame. When the frame ends, the inputs and

the output steps also end and the circuit is reset. As the next frame starts, the

circuit would be ready to process the next set of inputs ti and t2.

4.2 Weighted Sum Circuit

The circuit shown in Figure 4-2A is again a minor modification of the basic

block shown in Figure 2-1A. We will assume that the capacitor is initially charged

to a voltage VTH, tl < t2, 12 I < I3. As soon as the frame starts (at time tREF),

net current II + 12 I starts to charge the capacitor as shown in Figure 4-2B.

When the first temporal signal enters the block at time ti (where ti is defined

as t1 with respect to reference time tREF) the current source I1 stops charging









the capacitor and net current I2 3 charges the capacitor C. When the second

signal enters the block at time t2 (where t2 is defined as t2 with respect to reference

time tREF), current source 13 discharges the capacitor. A comparator senses the

voltage across the capacitor and outputs a step when the voltage reaches the

threshold voltage VTH. The output of the comparator would contain an unwanted

pulse at the reference time because the positive and negative terminals of the

comparator carry the same voltage VTH. The AND gate connected to the output of

the comparator ensures that the output from the block contains only a step output

at time tour = tour tREF. Once the block outputs a step and the frame ends, an

appropriate reset stage (not shown in the figure) would reset the capacitor voltage

to VTH at reference time tREF.

tour is the time when the output step of the block, makes its transition from
low to high voltage.

tour = ( )ti + (2)t (4-3)
13 13
From the above equation, we observe that the block computes a weighted sum of

the two input time steps occurring at times ti and t2.

An output from the block occurs when


(I1 + 1 13)t + (12 13)(2 1) > 0 (4-4)

Solving Eq. 4-4, we would get


t11+ 12t2 > 13t2 (4-5)

Eq. 4-5 can be interpreted as,

11
t2 > 1ti (46)
12 13

Since tj < t2 was assumed, it follows that 1 > 1 or 13 > 12 I.










If we assume that t2 occurs before ti, we would get an output from the block,

when

(1 + 1)t2 + (I1- ) )(l i2) > 0 (4-7)

Solving Eq. 4-7 gives 13 > I1 2.

VC
CHARGED
BY 1213
I, ( ( 12 CHARGED DISCHARGED
BY \ BY 13
iM2I


(w ilth initial C 1J 1-I
voltage VTJ) v| I
STtREF t t2 OUT t

A) B)

Figure 4-2. Weighted sum circuit. A) Circuit schematic. B) Idealized graph
showing the capacitor's voltage at different time periods.


In both cases, I1 = 2 = I results in


toUT = l + 2 (4 8)


This case corresponds to the sum of two input time steps occurring at tl and t2.

Thus, we see that by controlling the current sources, we achieve two different

functionalities from the block sum and weighted sum.

Without the assumptions made above, different outputs given out by the block

can be summarized in a single equation:

( 1 + (2 for tl < t2,13 > (12 I1) or tl > t2, 3 > (I -( Ta)
13 13
touT = +t 2, for t < t2 or t1> t2, I1 2 = (4-9b)

No output, otherwise (4-9c)

The circuit has a single-ended output; the inputs and outputs occurring at ti,

t2 and tour are defined with respect to a time reference tREF (start of the frame).










4.3 Scalar Multiplication Circuit

By removing the PMOS transistor M1 that controlled current source I,

charging the capacitor, replacing PMOS transistor i[_. by an NMOS transistor i .

and changing the direction of the I2 of the basic block in Figure 2-1A, we obtain a

circuit that can be used for scalar multiplication of a temporal signal entering the

block at time t2 as shown in Figure 4-3A.

VC

CHARGED /\DISCHARGED
BY I BY 1 211


TH
M2 (with initial VT tH
t1 2 _vLoltage VTH) I I
REF t OUT

A) B)

Figure 4-3. Scalar multiplication circuit. A) Circuit schematic. B) Idealized graph
showing the capacitor's voltage at different time periods.


Assuming that the capacitor is initially charged to a voltage VTH, the current

source I, starts to charge the capacitor as soon as the frame starts (at time tREF).

The input step occurs at time t2 where, as above, t2 is defined as t2 with respect

to reference time tREF. The current source 2 I1 starts discharging the capacitor

as shown in Figure 4-3B. When the capacitor voltage reaches VTH, the comparator

outputs a step at time tour. The output of the comparator would also contain an

unwanted pulse at the reference time because the positive and negative terminals

of the comparator would carry the same voltage VTH. The AND gate connected to

the output of the comparator ensures that the output from the block contains only

a step output at time tour. Once the block outputs a step, an appropriate reset

stage (not shown in the figure) would reset the capacitor to VTH at reference time

tREF-






58


The output tour from the block is given by the equation,


tOUT = ( )t2 (4-10)
2 I1

We see from the equation above that, the block multiplies time 2 with a scalar

12/(12 -).

Without the assumptions made above, different outputs given out by the block

can be summarized in a single equation:

( 12
(12 )t2, for 12> 11 (4 lla)
toUT = 2 I1
No output, for 12 < 1 (4-11b)

This block has a single-ended output and the inputs and outputs are defined

with respect to a time reference tREF(the start of the frame).

4.4 Maximum(MAX)/Minimum(MIN) Circuit


I--
ti
tOUT



t2

Figure 4-4. Circuit schematic of MAX circuit




ti
t1--T -

tOUT



t2

Figure 4-5. Circuit schematic of MIN circuit


The MAX and MIN circuits shown in Figures 4-4 and 4-5 support inputs

and outputs that have absolute time as the reference. The output from the MAX









and MIN circuits are single-ended. This block processes two temporal signals -iv,

the time steps occurring at t1 and t2 as shown in the figure, and determines the

max(ti, t2) or min(tl, t2) of the two steps. If the signal was to be represented

using voltages, a complex circuit would be required to compute max(VI, V2) or

min(VI, V2). In time-based analog computation, the circuitry to compute these

functions is straightforward.

The time-mode linear computational circuits we have discussed so far and the

thresholded difference block (to be discussed in C'!i pter 5) can be classified into

different subclasses based on their output style, shown in Table 4-1.

Table 4 1. Classification of Time-mode computational circuits. Relative time
reference implies that the inputs and outputs are defined with respect to
a reference time (start of a frame). Absolute time reference implies that
inputs and outputs are not defined with respect to a reference time.

Output Single-ended Differential
Absolute time reference Weighted Averaging Circuit Thresholded difference
Weighted Subtraction Circuit block of Edge detection
MAX circuit
MIN circuit
Relative time reference Sum circuit
Scalar Multiplication Circuit


So far, we have discussed time-mode computational circuits to perform

computations like weighted average, weighted subtraction, weighted sum, scalar

multiplication, maximum and minimum. In C! Ilpter 6, we will discuss a couple of

applications a time-mode edge detection circuit and a time-mode 3-tap FIR filter.















CHAPTER 5
APPLICATION OF TIME-MODE CIRCUITS

5.1 Time-Mode Edge Detection Circuit

Time-mode circuits provide a seamless interface to the growing number of

time-based sensors which already output compatible timing events [14], [15]. In

this section, an example is given where a time-mode edge detector is developed to

directly interface to the output of a time-to-first spike imager [14].



Image





Profile of a
horizontal line



First derivative


SSecond derivative



Figure 5-1. Edge detection by derivative operators


5.1.1 Basic Formulation

Edge detection in image processing has been studied for many years and is

well understood [23]. An edge is the boundary between two regions with relatively

distinct grv i-k-v. properties. In all the discussions below, we assume that the









regions in question are sufficiently homogeneous so that the transition between two

regions can be determined on the basis of gray-level discontinuities alone.

Traditionally, the idea underlying most edge-detection techniques is the

computation of the local derivative operator. This concept is illustrated in

Figure 5-1. The figure shows a synthetic image of a light object on a dark

background, the gr iv-k-1 profile along a horizontal scan line of the image,

and the first and second derivatives of the profile. We note from the profile that

an edge (transition from dark to light) is modeled as a ramp, rather than as an

abrupt change of gray level. The first derivative of an edge modeled in this manner

is 0 in all regions of constant gray level, and assumes a constant value during a

gray-level transition. The second derivative, on the other hand, is 0 in all locations,

except at the onset and termination of a gray-level transition. Based on these

remarks, it is evident that the magnitude of the first derivative can be used to

detect the presence of an edge, while the sign of the second derivative can be used

to determine whether an edge pixel lies on the dark (background) or light (object)

side of an edge. The sign of the second derivative in Figure 5-1 for example, is

positive for pixels lying on the dark side of both the leading and trailing edges of

the object, while the sign is negative for pixels on the light side of these edges.

Although the discussion thus far has been limited to a one-dimensional horizontal

profile, a similar argument applies to an edge of any orientation in an image.

In this chapter, we will discuss the design of a time-mode edge detector

that performs a first derivative operation on the pixel outputs through a novel

time-mode thresholded differencing block to detect both the presence and the sign

of the edges. Significant changes in scene illuminance are typically detected with a

spatial derivative operation following a spatial smoothing process that reduces high

frequency noise. Figure 5-2 shows the basic data flow in the proposed time-based

edge detection scheme. Initially the time steps corresponding to pixel intensities










are smoothed. Next, the smoothed time steps are fed to a thresholded differencing

block that finds the difference between the input steps and thresholds the result.

The output of the thresholded derivative block can either be positive or negative

implying a positive or negative edge between pixels.


Figure 5-2. Data flow in time-mode edge detection


5.1.2 Smoothing

We have previously fabricated a time-to-first spike C'\ IOS imager in our lab

[24],[14]. This imager provides output steps whose timing encodes illumination

information at each pixel. These spatial information must be smoothed to eliminate

noise in the image as well as noise introduced by the electronics.


Step (plxel 1)


t3
Step (plxel 3)


SMOOTHED STEP
SMOOTHED STEP


C VTH


Figure 5-3. Circuit to smooth pixel intensities


Figure 5-3 shows a circuit that could be used to perform smoothing of these

pixel intensities. We implement a standard convolution mask with weights of 1-2-1









by appropriately scaling the current source values. Since the circuit shown in

Figure 5-3 is a special case of the weighted averaging circuit explained in ('!i Ilter

2, we can easily derive the smoothing block's output expressed below:

t' + 2t2 + t3 CVTH
touT = + (5-1)
4 41

5.1.3 Thresholded Difference

The threshold difference block performs a spatial first derivative operation on

the smoothing circuit's outputs. By replacing one PMOS transistor by an NMOS

transistor and changing the direction of the corresponding current source in the

time-mode weighted averaging circuit, we obtain a circuit that can be used to

obtain thresholded differences of steps shown in Figure 5-4. There are two cases to

be considered assuming that Vc is initially reset to a midrange voltage:

* One of the smoothed steps enters the thresholded difference block first, starts
to linearly charge (or discharge) the capacitor until it hits the positive (or
negative) threshold VTH (or -VTH) before the second smoothed step enters the
block. Here, we have a step from the positive (or negative) output of the block
at time
toUT = ti + (5-2)
I
The threshold implemented by this block is CVTH/I. This threshold value can
be programmed by choosing desired values for VTH and I.

* The two smoothed step inputs arrive within the threshold time CVTH/I. Since
the positive and negative current sources exactly cancel one other, no step
is generated from either the positive or negative output indicating no edge
between pixels. Mismatches between the two current sources will eventually
cause one of the outputs to fire, but at a time much longer than the frame
time of the system.

If the thresholded difference block fires an output, we can know the presence

of edges between .,li i: ent pixels. Also, depending on whether we get positive

output or negative output we can infer the sign of the edges. That is, a positive

output implies that pixel 1 is brighter than pixel 2. Thus, from the outputs of the











Smoothed Step
(plxel 1)

J-7>


POS I IVE U I PUI FROM
THRESHOLD DERVIATIVE
BLOCK


Smoothed Step
(plxel 2)


BLOCK


-VTH

Figure 5-4. Circuit used to obtain thresholded differences on the smoothed steps


threshold differentiation block (that performs a spatial first derivative operation),

we can detect both the presence and the sign of the edges.

5.1.4 Results

Using the time-mode edge detection concepts explained above, we processed

a noisy JPEG image to detect edges. The whole operation is completed within

3 frames. The frames are defined by the imaging process typically 30ms. The

MATLAB simulation results are shown in Figure 5-5. In the first frame, we

converted the pixel magnitude information (between 0 and 255) of each pixel to

timing information using reverse coding. A bright pixel would fire earlier compared

to a dark pixel, that is, with respect to the frame the bright pixel would have a

smaller temporal amplitude compared to a dark pixel. In the second frame, we

remove the spurious noise in the image by using time-mode smoothing circuits.

After smoothing, we perform the spatial first derivative operation by running the

smoothing block's outputs through time-mode thresholded difference blocks in the

third frame.

For better understanding, let us restrict our analysis to 16 pixels. The original

noisy image, smoothed image and the detected edges are shown in Figure 5-6. The

noisy original image and the smoothed image are shown in dotted lines and solid









lines respectively. The edges detected are shown special characters in the figure.

From the results shown, we can infer that the time-based edge detection method is

extremely accurate.

For these 16 pixels, Figure 5-7 shows the Cadence simulation outputs from

different stages in the time-based edge detection process. The length of the frame

and the threshold we chose for the thresholded difference block are 30ms and 15ms

respectively. In the figure, the original image is shown followed by the temporal

signals output by the imager. It is followed by the outputs of the smoothing

and thresholded difference blocks. The edge detection circuits needs 3 frames to

complete their operations. The final results indicate that only three edges were

detected to be above the threshold. The power consumed by the edge detection

circuits for these 16 pixels was in the order to 35/W.






66





































; : / :







Figure 5-5. MATLAB simulation results showing the original image, smoothed
image and the detected edges of an image























Time-based Edge Detection

Original Imag
Smoothed Imr
Edges obtainE






















-****************** :* **>>********#******* ***********
'. 'I, .. "I.I


e
age
ed


Pixel


Figure 5-6.


Simulation results showing the original image, smoothed image and
the detected edges of a 16 pixel image


200


100


































































A *


/


(Il
a-



IZ
C- C

uL




1



C)




0
I
O



[7F'7HIll1HHF]FThiF]F]F2F~~iz


I :

~rT

ITi






rT


. ..r .r .l ..


,,

,,


I .AL ,,.









5.1.5 Discussion

The length of the frame that governs the operation of the time-mode edge

detection circuit has a very important tradeoff. If we opt for longer frames, the

DR of inputs that can be processed by the edge detection circuits is large. With

short frames, the speed of the entire edge detection operation is increased and the

leakage currents of the transistors in the thresholded difference block won't cause

erroneous outputs.

From Eq. 5-2, we can easily infer that by controlling C, VTH or I we can

program the desired threshold in the thresholded difference block. But, once a edge

detection chip is designed, it is tough to vary the value of C. Therefore, to vary the

threshold, we should either tune VTH or I off-chip.

5.2 3-Tap 1-Quadrant Time-Mode Finite Impulse Response Filter

FIR realization for a N-tap FIR filter follows directly from the convolution sum

relationship written in the form:

N-1
y(n)= w(k)x(n k) (5-3)
k-0

For a 3-tap filter,
2
y(n) = w(k)x(n k) = w(O)x(n) + w(1)x(n 1) + w(2)x(n 2) (5-4)
k-0

From Eq. 5-4, we see that to compute the n-th sample of the output of a 3-tap

FIR filter, we need the current input x(n) and two previous inputs x(n 1) and

x(n 2). For example, the output at the 3rd sampling period is given by,


y(3T) = w(0)x(3T) + w(1)x(2T) + w(2)x(1T) (5-5)


If the input and output at the 3rd sampling period are represented in time by

tfI and OUfT respectively, then we can implement a time-mode FIR filter if we can









implement,

tUT = w(O)t + w(l)t + w(2)tTN (5-6)

From Eq. 5-6, we see that we would need inputs tfT and tTN other than t4T to

obtain tOjT. To do this, we can either

* delay t2T by one sampling period and tN by two sampling periods, or

store t2T for one sampling period and tT for sampling periods,

so that these inputs would be available during the sampling period 3T when

the computation shown in Eq. 5-6 is to be performed.

When the information is in time, delaying that information (information is

encoded in the rising edge of a time step referenced to the start of a frame) would

involve converting the time information to voltage and then converting that voltage

back to time (information again is a time step but referenced to a new frame)

using analog components. Since we are considering the implementation of a 3-tap

FIR filter, we would need two delay stages. Since the delay stages involve analog

components like current sources and capacitors that have matching constraints,

we might end up with inaccurate d4-1i- that might lead to erroneous outputs.

Therefore, the better option would be store the information over various sampling

periods. Since, we have not yet come up with the circuit that would store time

information directly in time, we convert the time information to voltage and store

it on a capacitor.

5.2.1 Finite Impulse Response Computation in Time

The circuit shown in Figure 5-8 is similar to the prototype time-mode

weighted average circuit except that this figure also shows the reset functionality.

Three inputs that enter this block are

1. train of frames these act as reference for the input and output steps.


2. train of input steps.


















CHIP
RESET



FRAME
INPUT

SIGNAL
INPUT


FRAME


IN1I


IN2


NEG IN


COMPUTATION
RESET

OUT








CHIP
RESET
VT


COMPUTATION
RESET


41


OUT

toUT


Figure 5-8. Computational block to be used in the FIR filter










3. chip reset.

Lets postpone the discussion of the input processing that should be done to

the two input trains to generate signals IN1, IN2, IN3, NEG_IN and COMPUTATION

RESET to the next section. These signals are the inputs to the computational

block shown in Figure 5-8. Before any of the input trains enter the system, the

chip reset signal would reset the capacitor's voltage to VTH. As the first frame

starts, IN1 generated by the input processing block turns on the switch M1 for a

period t1. This let's the current source I1 charge the capacitance C for the period

t1 as shown in Figure 5-9.


Charged by I I
current I,2


Charged by
current I
II II
VTH----- ---------------
II I I



ItFRAME I 2tFRAME I 3tFRAME
I II

t I I t

CHIP RESET

Figure 5-9. Voltage across the computational blo



The voltage across the capacitor is given by,


ltl
V = VTH +
c


Discharged by
current Ia


Time


tOUT

ck's capacitor at various times


(5-7)


The capacitor in this block performs two functionalities simultaneously:









* input tl is stored as voltage until the computation ends (at the end of the
fourth frame) to facilitate the FIR type computation (assuming that the
capacitor has minimal or no leakage).

* a weight of 1 is applied to the input t1 (though that weight is not the final
weight applied to the input).

After the second frame starts, IN2 turns on the switch if[. causing I2 to charge

the capacitance C for a period t2. The new voltage across the capacitor is given by,

V2 lt I2t2 8)
Vj VTH + + (58)


Now, the capacitor is holding both inputs ti, t2 and has applied weights 'I and 2

respectively. When the third frame starts, IN3 turns on the switch if. causing I3

to charge the capacitance C for a period t3. Now, the capacitor holds inputs ti,

2, t3 and has applies weights 1, 2 and I respectively as shown by the capacitor

voltage Eq. 5-9.
Vj3 V 1 12t2 1t3 (
Vc = VTH + + + (5-9)
C C C

As frame 4 starts, the signal NEG_IN turns on switch M4 and the current 14 starts

to discharge the capacitance C. With the voltage across the capacitance being

continuously monitored by the comparator, voltage across the capacitance slowly

decreases as 14 discharges it and when the voltage reaches VTH the comparator fires

a step output. The rising time of this output step referenced to the fourth frame

gives the desired output tour.

C(V VTH)
toUT
I4
C( )
14
+ +12t2 13 (5-10)
14 14 4

From Eq. 5-10, we see that the computational block applies weights 1, 1 and

13 to signals tl, t2 and t3 and sums them together. After the block performs this
I4









computation, the capacitor voltage is reset to VTH by the computation reset signal

generated by the input processing block.

We made the following basic assumptions to arrive at the above result:

* The inputs tl, t2 and t3 do not saturate the capacitance C.

* Frame 4's ON period is large enough to discharge the capacitance C (until the
voltage across the capacitance reaches VTH) and produce the output tour.

Since, ti, t2, t3 and tour are defined with frames 1,2,3 and 4 as reference

respectively, we can write Eq. 5-10 as,

4T I1T +12 2T 13 3T
tout ()t +( 2)t +( )t3f (511)
74 1 14 4

As mentioned in the assumptions above, the ON period of frame 4 should be large

enough atleast to produce an output at time tour. Therefore, t'ONe tOUT

Assuming that the OFF period of the frame where the capacitor is reset to VTH

is extremely small, tframe tour. Therefore, the minimum possible frame length

tour and the maximum possible sampling speed =
If the Eq. 5-11 can be interpreted in terms of samples then,

II /2 I3
toUT(4) = )tl(1) + ( )t(2) + ( )tl(3) (5-12)
14 14 14

Comparing Eq. 5-12 with the conventional 3-tap FIR equation shown below,


y(3) = w(2)x(1) + w(1)x(2) + w(0)x(3) (5-13)

we see that tour has an extra sample delay when compared to the conventional

FIR output. In other words, the FIR filter's computation block has an extra pole

at the origin as compared to the conventional FIR filter.

5.2.2 3-Tap 1-Quadrant Time-Mode FIR Filter Architecture

The main functional block of the 3-tap 1-quadrant time-mode FIR filter

architecture is the computational block shown in Figure 5-8. Let's -i- that









the computational block processes inputs tIN(1) referenced to frame 1, tIN(2)

referenced to frame 2, tIN(3) referenced to frame 3 and produces an output toUT(4)

referenced to frame 4. The computational block gets ready to process the next set

of inputs only at the end of frame 4 where the capacitor is reset to VTH. The next

output this block would produce is touT(8) processing tIN(5), tIN(6) and tIN(7).

Since this block cannot produce the intermediate outputs touT(5), touT(6) and

toUT(7), we would need three more computational blocks to produce those outputs.
Therefore, the 3-tap FIR filter would need in total, four computational blocks to

continuously process the input time signals. In general, for a N-tap FIR filter, we

would need N+1 computational blocks to construct the FIR filter.

The complete architecture of a 3-tap time-mode FIR filter is shown in

Figure 5-10. The FIR filter block needs the same 3 inputs as the computational

block a chip reset, a train of frames and a train of time steps as shown in

Figure 5-12. Every input step (example, tl) in the train of time steps is defined

with respect to a frame (example, frame 1) in the train of frames as shown in

Figure 5-12. The trains of frames and time steps are fed to a input conditioning

block. The architecture of the input conditioning block is shown in Figure 5-11.

The input conditioning block performs the following functions:

* the train of frames and input steps that enter the filter are decoded onto
different lines so that they can be fed to the various computational blocks'
inputs.

* generates the necessary charging/discharging pulses for the computational
blocks.

* generates the reset pulses necessary to reset the capacitors of the computational
blocks to their initial voltage VTH.

Each computational block needs 3 inputs in different lines because we are

designing a 3-tap FIR filter. Also, since there are four computational blocks that

process the following different sets of inputs (t1,2,t3), (t2,t3,t4), (3,t4,t) and
























SIG_IN1 -
SIG IN2 -
SIG IN3 -
NEGIN1 -
CHIP RESET
RESET IN1


SIGIN3 -


SIG IN4-
SIG IN2 -
SIG IN3 -
SIG IN5 SIG IN4-
NEGIN2-
SIG IN6 CHIP RESET-
RESET IN -


NEG IN1


NEG IN2


RESET IN1


RESET IN2


INPUT CONDITIONING
BLOCK


SIG IN3 -
SIG_IN4
SIG IN5 -
NEG IN3 -
CHIP_RESET-
RESET IN3 -






SIG IN4 -
SIG IN5 -
SIG IN6 -
NEG IN4 -
CHIP RESET -
RESET IN4 -


COMPUTATION BLOCK 1

tl

t4
4 tour
CHIP RESET
COMPUTATION
RESET


COMPUTATION BLOCK 2


t,
t2


CHIP RESET
COMPUTATION
RESET


COMPUTATION BLOCK 3


t,
t2


CHIP RESET
COMPUTATION
RESET


COMPUTATION BLOCK 4

tl
t2
ts tOUT


CHIP RESET
COMPUTATION
RESET


Figure 5-10. 3-tap time-mode FIR filter architecture


FRAME
INPUT












SIGNAL
INPUT


FIR OUTPUT


4 INPUT
-OR- GATE


CHIP RESET














FRAME SIGIN1
INPUT 2-bit QO 24 SIGIN2
SIGNAL CLK Counter Q1 Decoder SIG_IN3
INPUT
IN


Q- SIGIN4
3-bit 1 3-8 SIG_IN5
CLK Counter Decoder SIG_IN6
Q2

(counts only
3, 4, 5)

Q- NEG IN1
FRAME 3-bit QI -- NEG IN2
INPUT NEG IN3
INPUT Counter Decoder NEG IN4

(counts only
3,4, 5, 6)


NEGIN1 RESET ]NI


NEGN2 ---RESETIN2


NEG_IN3 _
EG IN3 RESET_IN3


NEGCIN4 L RESETIN4


Figure 5-11. The architecture of the input conditioning block







78




(t4,t5,t6) that is, at every sample (frame), we would need 6 inputs in 6 different

lines for the 4 computational blocks. To keep moving these inputs at different

input lines during every frame, we have used 2 counters a 2-bit counter and a

3-bit counter (that counts between 3 and 5) followed by decoders. Similarly, since

we need the frames to discharge the capacitances of the computational blocks,

we have a 3-bit counter followed by a decoder to decode the frame train onto 4

different lines.

FRAME Frame 1 Frame 2 Frame 3 Frame 4 rame 5 Frame 6 Frame 7
INPUT

SIGNAL
INPUT

tl t2 tt3 ( to

SIG_IN1
tl ts -



SIG IN3

SIG IN4


FRAME SIG IN5

SIG INB t
Frame 4
NEG_IN1


FramFramee 5


SIGNAL Frame
INPUT NEG IN4


RESET IN1

RESETIN2

RESET IN3

RESETIN4 _

INPUT CONDITIONING
BLOCK

Figure 5-12. 3-tap FIR filter's input, digital preconditioning block and its outputs









The architecture shown is for a 1-quadrant FIR filter. That is, it can only

process positive inputs and apply positive weights to those inputs. By adding extra

circuitry, we can extend this architecture to process both positive and negative

inputs and apply both positive and negative weights to those inputs.

5.2.3 Step-by-Step Description of the Functionality

1. Figure 5-13 describes the state of the computational blocks as input tl enters
the blocks. At sampling instant tFRAME, we can see only the capacitance of
the computational block C1 being charged by current II.

2. As input ta enters the blocks at sampling instant 2tFRAME ,
I2 charges capacitor C1, and,
1i charges capacitor C2 of computational block 2,
as shown in Figure 5-14.

3. As input ts enters the blocks at sampling instant 3tFRAME as shown in
Figure 5-15,
Is charges capacitor C1 of computational block 1,
I2 charges capacitor C2 of computational block 2, and
II charges capacitor C3 of computational block 3,

4. At sampling instant 4tFRAME as frame 4 and input t4 enter,
frame 4 charges capacitor C1,
I3 charges capacitor C2, and,
I2 charges capacitor C3
as shown in Figure 5-16.

5. As frame 4 is about to finish as shown in Figure 5-17,
capacitor C1 is reset to VTH and it is ready for frame 5 and input ts,
voltage of capacitor C2 stays a constant, and,
voltage of capacitor C3 stays a constant,

5.3 Simulation Results

To test the filter functionality of the circuit shown in Figure 5-10, we chose the

following values for the current sources: II = 302nA, I2 = 400nA, 3 = 302nA and

14 = lpA with C=5pF and VTH = 2.5V (for a supply voltage of 5V). The weights


applied to inputs become I'
14


.302, 2- .4, = .302.
14 14


























touT


Vcl



OtCarged by
I current I1
FRAME
I I Time

SIG IN1


tow















tOUT
















tout


RESET


Figure 5-13. State of the FIR filter as input tl enters


















JL J L 1 2 I' Vc1 Charged by
SIGIN -> ->Acurrent 12
M sIGN2 SIG_IN3
RESET

c ,E M'-trRAM A A'-ME B
VTHTi








S SIG IN3 SIG IN4
CHIP / __-

R ES T V arged by
IEG I current I,
RESETN / J- Time
VT SISIGINN2








IGIN M S>G_

SIG IN4 SIG IN5

CHIP
RESET --
RN3 V 17-arged by












VTH lEG IN3
3j M44 RESET IN
VTH


11( 12





SIG_ N I >2 3 M,
SIG IN5 SG IN6




RESET IN


Figure 5-14. State of the FIR filter as input t2 enters



















n I n nCharged by



H I
VIi cu rret I


CIHI 1 I Iime
SSIIG N3


RT Z I ~ I. 93 -jv Charged by
SIG IN2 SIG IN3



4 tFAME FRAME tIF
RESETIN






VTHTime






SII _IN





CHIP
SV, Charged by








SIG I current 1U
ESIGIN3 SIG IN4



V H FRAME 3 FRAME






RESET I Time

VH S S IGIN3
S- IN SIGl IN5

RESET E IVTarged by
V7H ^ 1EG IN3 ~-(1 1hrrent 1,
-T VTM4 13t 4

RESETIN I Time
VTH LeJ SIGJIN3



Al ) I, A 12 J l1 a
SIG JNI>.l M,
SIG IN5 SISJN6
CHIP
RESET JEG-IN4 VTH


RESET IN4 T C


Figure 5-15. State of the FIR filter as input ts enters




















b ,1,, lX- I, Ve
SIGIN M I







ICharged by
RESET current I \




H IP IN 4 |_I
VT_ NEGIN1

EtFRAME FRAME tFRAM
SGI NXM, _>L vC2

RESETI -I -

R I EG V3tFRAME FRAME FRi



















1 R I cuIrrent I1
RESETI 1I Time
SJSIG> MN4
SIG IN4 \ SIG IN5
RESET









Figure 5 State of the FIR filter s input er the system and with frame 4



dish in computational block 1
RESET CHarged by
u t-- ^ current I

RESETIN TL 1 Time



Figure 5-16. State of the FIR filter as input t4 enters the system and with frame 4
discharging computational block 1































































tnUT







tour







>OlT


RESET


tf E IRAME 4tFAME 4tFRME Tme






Vc2






2tFRAME FRAME 4tFRAME

Time


Vc3






3tFRAME 4tFRAME
Time






V04






4tFRAME

Time


Figure 5-17. State of the FIR filter before frame 5 starts


RESETII









CF
RE;



RESET


IuT









The output of the computational block was previously derived as,


touT(4) ( 7)tN(1) + (2)t(2)+ (3)tN(3) (5-14)

The general expression for this output can be written as,

II 12 3
touT(n) = (-)tIN(n 3) + ()tr(n 2) + (N)tlN(n 1) (5-15)
14 14 14

Taking z-transform of this output, we would get

II I2
touT(z) = ()tiNN(z)z-3 + ItN( -2 + )NtiN(z2-1
tourT() II -3 2 2 13 1
O Z) ( )z-3 + (2) + ()z-
ti N (z) 14 4 4
H(z) = ()z-3 (2)-2 +()Z-1 (516)
14 14 14

Substituting the weights in Eq. 5-16 we get,

H(z) = 0.302z-3 + 0.4z-2 + 0.302z-1 (5-17)


The poles and zeros of this FIR filter are shown in Figure 5-18. The sampling

frequency chosen for the simulations is 100KHz. The FIR filter's magnitude

response and phase response are shown in Figures 5-19 and 5-20 respectively.

From the plots, we see that the choice of coefficients II = 60.4nA, 2 = 80nA,

I3 = 60.4nA and 14 = 100nA has tuned the FIR filter to function as a low pass

filter with a cut-off frequency of t 10KHz, stop-band attenuation of a 20dB and

a passband attenuation of t ldB. Similarly, by choosing different values (either

positive or negative) we can come up with high pass, band pass and notch filters.

It is important to note that the architecture shown in Figure 5-10 can handle only

positive currents. If negative currents are to be handled, the circuit architecture

would have to be altered.












Pole/Zero Plot
Real Part: -0.6607202
Imaginary Part: 0.7506323
.. ..... ..


-q


C0


-1 -0.5


0
Real Part


1 1.5


Figure 5-18.


Pole-zero plots of the FIR filter


Magnitude Response (dB)


-20

-40

-60


-80

-100
0 10


Figure 5-19: Time-mode FIR
kHz)


20 30 40
Frequency (kHz)


filter's magnitude response (sampling freq = 100


0.5


-r


a


-C 5


-1


-1.5





''''''''


. .. . .


. . .




Full Text

PAGE 4

IoweaspecialdebtofgratitudetoDr.Harrisforhisexpertguidanceandstimulatingdiscussions.Hisperception,insight,andexperiencehavecontributedimmenselytotheclarityandrigorofmyresearch.Thefaithheshowedwasthemotivatingforcetowardsmycontribution.Myassociationwithhimhasbeenanenlighteningandrefreshingexperience.IamimmenselythankfultoDr.JoseFortesforhishelpwhenIwasinaquagmireanditwasaprivilegeworkingunderhim.IamalsogratefultotheanaloggeniusDr.RobertFox,forhewentoutofthewaytohelpmeevenwhenIwasnotworkingunderhim.HeisoneofthefewprofessorsIfeelproudthatIgottoworkwith.ThisworkwassupportedbyNationalAeronauticsandSpaceAdministration(NASA)underawardno.NCC2-1363andSemiconductorResearchCorporation(SRC)underTaskID:1049-CrosscutResearch.IwouldliketothankDr.M.P.Anantram,Dr.HarryPartridge,andDr.T.R.GovindanatNASAAmesResearchCenter,CA,forthecondencetheyshowedinmeandalltheirsupportduringmyinternshipatNASA.ThanksareduetotheadministrativestaoftheDepartmentofElectricalandComputerEngineering:Ellie,Janet,Linda,andShannonfortheirco-operation.Furthermore,Itakethisopportunitytoexpressmyappreciationtoallthosewhohelpedmeinthecompletionofmywork.Iwouldliketothankmyformerandcurrentlabmates:Pravin,Vaibhav,Rama,Du,Xiaoxiang,Yuan,Harpreet,Mark,Meena,Harsha,andIsmailfor iv

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v

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page ACKNOWLEDGMENTS ............................. iv LISTOFTABLES ................................. ix LISTOFFIGURES ................................ x ABSTRACT .................................... xiv CHAPTER 1INTRODUCTION .............................. 1 1.1BiologicalMotivation .......................... 3 1.2EngineeringMotivation ......................... 3 1.3ChapterSummary ........................... 5 2THEWEIGHTEDAVERAGECIRCUIT ................. 6 2.1Time-ModeWeightedAveragingCircuit ............... 6 2.1.1ResetStage ........................... 9 2.1.2MeasuredResults ........................ 10 2.1.3Discussion ............................ 12 2.2TheoreticalAnalysisofSignal-to-NoiseRatioandDynamicRange 14 2.2.1OutputNoiseduetoTimingJitterattheInputs ....... 14 2.2.2OutputNoiseduetoFundamentalNoiseSourcesintheCircuit 15 2.2.2.1NoiseintOUTduetonoiseincurrentsourceI1 16 2.2.2.2NoiseintOUTduetonoiseincurrentsourceI2 17 2.2.2.3NoiseintOUTduetonoiseinthecomparator ... 18 2.2.3Discussion ............................ 21 2.3ScalingofTime-ModeWeightedAverageCircuitwithTechnology 21 2.3.1SimulationSetup ........................ 22 2.3.2ResultsandInferences ..................... 23 2.3.3Discussion ............................ 26 2.3.4Drawbacks ............................ 27 2.4CarbonNanotubeBasedTime-ModeWeightedAveragingCircuit 30 2.4.1CarbonNanotubeFieldEectTransistors(CNFETs)andTheirSpiceModels ....................... 30 2.4.2PhysicsGoverningtheOperationofCNFET ......... 32 2.4.3SimulationResults ....................... 32 vi

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............................ 33 2.5ReliableTime-ModeWeightedAverageCircuit ............ 34 2.5.1Motivation ............................ 34 2.5.2Time-ModeMedianCircuit ................... 36 2.5.3RedundancyinTime-ModeComputation ........... 37 2.5.4Discussion ............................ 40 3SNRCOMPARISONOFWEIGHTEDAVERAGINGCIRCUITS .... 42 3.1Voltage-ModeAveragingCircuit .................... 43 3.1.1NoiseContributionattheOutputdueto v12 45 3.1.2NoiseContributionattheOutputdueto v22 45 3.1.3NoiseBandwidth ........................ 46 3.2Current-ModeAveragingCircuit ................... 47 3.3Discussion ................................ 52 4OTHERTIME-MODECIRCUITEXAMPLES .............. 53 4.1WeightedSubtractionCircuit ..................... 53 4.2WeightedSumCircuit ......................... 54 4.3ScalarMultiplicationCircuit ...................... 57 4.4Maximum(MAX)/Minimum(MIN)Circuit .............. 58 5APPLICATIONOFTIME-MODECIRCUITS .............. 60 5.1Time-ModeEdgeDetectionCircuit .................. 60 5.1.1BasicFormulation ........................ 60 5.1.2Smoothing ............................ 62 5.1.3ThresholdedDierence ..................... 63 5.1.4Results .............................. 64 5.1.5Discussion ............................ 69 5.23-Tap1-QuadrantTime-ModeFiniteImpulseResponseFilter ... 69 5.2.1FiniteImpulseResponseComputationinTime ........ 70 5.2.23-Tap1-QuadrantTime-ModeFIRFilterArchitecture .... 74 5.2.3Step-by-StepDescriptionoftheFunctionality ......... 79 5.3SimulationResults ........................... 79 5.4Signal-to-NoiseRatio/DynamicRangeAnalysis ........... 91 5.4.1NoiseintOUTduetoNoiseinCurrentSourceI1 91 5.4.2NoiseintOUTduetoNoiseinCurrentSourceI2 92 5.4.3NoiseintOUTduetoNoiseinCurrentSourceI3 92 5.4.4NoiseintOUTduetoNoiseinCurrentSourceI4 93 5.5PerformanceoftheFIRFilterunderInputTimeJitter ....... 95 5.6AdvantagesofTime-ModeFIRFilters ................ 96 5.7LimitationsofTime-ModeFIRFilters ................ 96 vii

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.............. 98 6.1ImplementingNon-LinearArithmeticbyIntroducingNon-LinearityintheExistingLinearComputationalBlocks ............. 98 6.1.1Time-ModeMultiplication ................... 98 6.1.2Time-ModeDivision ...................... 101 6.2ImplementingNon-LinearArithmeticUsingTime-ModeMulti-LayerPerceptron ................................ 103 6.2.1Time-ModeMulti-LayerPerceptron .............. 103 6.2.2HardwareImplementationofTime-ModeMLP ........ 106 7CONCLUSIONANDFUTUREWORK .................. 113 7.1Conclusion ................................ 113 7.2Futurework ............................... 114 REFERENCES ................................... 116 BIOGRAPHICALSKETCH ............................ 119 viii

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Table page 2{1Measuredperformancecharacteristicsoftime-modeweightedaveragingcircuit. ..................................... 13 4{1ClassicationofTime-modecomputationalcircuits.Relativetimereferenceimpliesthattheinputsandoutputsaredenedwithrespecttoareferencetime(startofaframe).Absolutetimereferenceimpliesthatinputsandoutputsarenotdenedwithrespecttoareferencetime. ......... 59 ix

PAGE 10

Figure page 1{1Dierentmodesofcomputation. ....................... 2 2{1Time-modeweightedaveragecircuit.A)Circuitschematic.B)Idealizedgraphshowingthecapacitorvoltageatdierenttimeperiods. ...... 6 2{2Inputst1,t2andoutputtOUTaredenedwithinaframe ......... 9 2{3PlotoftOUTforvaryingI(C=20pF,VTH=2:5V).Theblockwasgivenonestepinput. ............................. 10 2{4PlotoftOUTforvaryingI(C=20pF,I=1:0476A,VTH=2:5V).Theblockwasgivenonestepinput. ....................... 11 2{5PlotoftOUTforvaryingt2(C=20pF,I=1:0476A,VTH=2:5Vwitht1xedat1s,8:5sand32:5s.) ..................... 12 2{6PlotoftOUTforvaryingt2(C=20pF,I1=1:46A,I2=0:29A,VTH=2:5Vwitht1xedat1s,8:5sand32:5s.) ................ 13 2{7Variationofcapacitorchargingcurrentwithscalingtechnology ...... 24 2{8Variationofdynamicpowerwithscalingtechnology ............ 24 2{9Variationofaveragepowerwithscalingtechnology ............ 26 2{10Variationofenergyconsumedperaveragingoperationwithscalingtechnology 27 2{11Comparisonofcalculatedandsimulatedtime-modeaveragingoutputsovertechnologies ............................... 28 2{12Comparisonofcalculatedandsimulatedtime-modeaveragingoutputnoiseovertechnologies ............................ 28 2{13Comparisonofcalculatedandsimulatedtime-modeaveragingSNRvaluesovertechnologies ............................... 29 2{14Variationofdynamicrangewithscalingtechnology ............ 29 2{15PCNFETID-VGSplotsforvaryingVDS 33 2{16NCNFETID-VGSplotsforvaryingVDS 34 2{17Nano-weightedaveragecircuitsimulationoutputs ............. 35 x

PAGE 11

35 2{19Time-modemediancircuitfor3-inputs ................... 36 2{20Time-modemediancircuitforN-inputs ................... 37 2{21VonNeumann'stwo-out-of-threemajoritycircuit ............. 38 2{22Blockdiagramofareliabletime-modeweightedaveragecircuit ...... 39 2{23Plotshowingtheincreaseinreliabilityoftheredundantcircuitascomparedtotheindividualelements .......................... 40 3{1Voltagemodeweightedaveragingcircuit .................. 44 3{2Voltagemodeweightedaveragingcircuitwithnoisesources ........ 45 3{3Currentmodeweightedaveragingcircuit .................. 48 3{4Currentmodeweightedaveragingcircuitwithnoisesources ....... 48 3{5Halfofthenoisecurrentfromeachtransistorowstotheoutput .... 50 3{6CalculatedandsimulatedSNRvaluesofatime-modeweightedaveragingcircuitovertechnology ............................ 52 4{1Weightedsubtractioncircuit.A)Circuitschematic.B)Idealizedgraphshowingthecapacitor'svoltageatdierenttimeperiods. ......... 53 4{2Weightedsumcircuit.A)Circuitschematic.B)Idealizedgraphshowingthecapacitor'svoltageatdierenttimeperiods. .............. 56 4{3Scalarmultiplicationcircuit.A)Circuitschematic.B)Idealizedgraphshowingthecapacitor'svoltageatdierenttimeperiods. ......... 57 4{4CircuitschematicofMAXcircuit ...................... 58 4{5CircuitschematicofMINcircuit ....................... 58 5{1Edgedetectionbyderivativeoperators ................... 60 5{2Dataowintime-modeedgedetection ................... 62 5{3Circuittosmoothpixelintensities ...................... 62 5{4Circuitusedtoobtainthresholdeddierencesonthesmoothedsteps .. 64 5{5MATLABsimulationresultsshowingtheoriginalimage,smoothedimageandthedetectededgesofanimage ..................... 66 5{6Simulationresultsshowingtheoriginalimage,smoothedimageandthedetectededgesofa16pixelimage ...................... 67 xi

PAGE 12

........ 68 5{8ComputationalblocktobeusedintheFIRlter ............. 71 5{9Voltageacrossthecomputationalblock'scapacitoratvarioustimes ... 72 5{103-taptime-modeFIRlterarchitecture .................. 76 5{11Thearchitectureoftheinputconditioningblock .............. 77 5{123-tapFIRlter'sinput,digitalpreconditioningblockanditsoutputs .. 78 5{13StateoftheFIRlterasinputt1enters .................. 80 5{14StateoftheFIRlterasinputt2enters .................. 81 5{15StateoftheFIRlterasinputt3enters .................. 82 5{16StateoftheFIRlterasinputt4entersthesystemandwithframe4dischargingcomputationalblock1 ...................... 83 5{17StateoftheFIRlterbeforeframe5starts ................ 84 5{18Pole-zeroplotsoftheFIRlter ....................... 86 5{19Time-modeFIRlter'smagnituderesponse(samplingfreq=100kHz) 86 5{20Time-modeFIRlter'sphaseresponse ................... 87 5{21Time-modeFIRlter'sgroupdelay ..................... 88 5{22Time-modeFIRlter'sinputandoutputwaveforms(intimedomain) .. 88 5{23EnergyofFIRlter'sinputandoutputsignals ............... 89 5{24Cadencesimulationresultsforthetime-mode3-bitFIRlter ....... 90 6{1Scalarmultiplicationcircuit ......................... 99 6{2Timingdetailsofthe2-inputtime-modemultiplier ............ 100 6{3Schematicofthe2-inputtime-modemultiplier ............... 101 6{4Schematicofthe2-inputtime-modedivider ................ 102 6{5Feedforwardmulti-layerperceptron ..................... 104 6{6Fullyconnected2-inputfeedforwardMLPwithonehiddenlayerandoneoutputlayer .................................. 105 6{7Non-linearmodelofaneuron ........................ 105 6{8Time-modescalarmultiplicationandsummingcircuit ........... 108 xii

PAGE 13

............... 109 6{10Variationofoutputmeansquareerrorwithepochs ............ 111 6{11Time-modeMLPdesiredandactualoutputs ................ 111 6{12Cadencesimulationresults .......................... 112 xiii

PAGE 14

Weintroduceasetofbasiccircuitbuildingblocksforanalogcomputationusingatemporalstepfunctionrepresentationfortheinputsandoutputs.Time-modecircuitsaredescribedthatuseastepfunctionrepresentationforcomputingtheweightedaverage,weighteddierence,weightedsum,scalarproduct,maximum,minimum,multiplication,divisionandthresholdeddierenceoperations.Time-modecircuitsarealternativestowell-knownvoltage-andcurrent-modeapproacheswhichcouldbeusedtoperformthesesamemathematicaloperations. Time-modecircuitsgrowmoreappealingasCMOSprocesstechnologiesscalesincetheyminimizetheamountofanalogcircuitryandusenoiserobustasynchronoustimeeventsasinputsandoutputs.Time-modecircuitsprovideaseamlessinterfacetothegrowingnumberoftime-basedsensorswhichalreadyoutputcompatibletimingevents.Anexampleisgivenwhereatime-modeedgedetectorisdevelopedtodirectlyinterfacetotheoutputofatime-to-rst-spikeimager.Time-modecircuitshavesimplearchitecture,providehighsignal-to-noiseratio,dynamicrange,consumelowpower,andhence,proveadvantageousinarchitecturallycomplexapplicationslikeniteimpulseresponselters. xiv

PAGE 15

Allanalogsignalprocessingcircuitsmustrepresentsignalsusingphysicalquantitiessuchasvoltage,current,charge,frequencyortimeduration.Inanalogliterature,wehaveseenextensiveuseofvoltage-mode,current-modeandcharge-modecircuitsthatgenerallyrepresentinputandoutputsignalsasvoltage,currentandchargerespectively: 1 ]andGmCstylecircuitscommonintoday'sanalogverylargescaleintegration(VLSI)designs[ 2 ]. 3 ].ThesedesignsincludeBarrieGilbert'soriginaltranslinearcircuitsthatrelyontheexponentialvoltagetocurrentrelationshipsofbipolarorcomplementarymetaloxidesemiconductor(CMOS)subthresholdcircuits[ 4 ].Morerecentlogdomainlters[ 5 ]arealsogenerallyconsideredtobecurrent-modecircuits. 6 ]. Thesedierentmodesofsignalrepresentationhaverespectiveadvantagesanddrawbacksandcanthereforebeusedindierentpartsofthesamesystem.Thevoltagerepresentationmakesiteasytodistributeasignalinvariouspartsofacircuit,butimpliesalargestoredenergyCV2 7 ].Thecharge 1

PAGE 16

representationrequirestimesamplingbutcanbenicelyprocessedbymeansofCCDsorswitched-capacitortechniques.Inactualfact,everycircuitusesvoltage,currentandchargeinitsoperationandsometimessemanticsandphilosophyaredebatedwhendenitivelycategorizingtheseclassesofcircuits[ 7 ]. Temporalcodingisusedasthedominantmodeofsignalrepresentationforcommunicationinbiologicalnervoussystems.Signalsrepresentedinthismannerareeasytoregenerateandthisrepresentationmightthereforebepreferredforlong-distancetransfersofinformation.Itisdiscontinuousintime,butthephaseinformationiskeptinasynchronoussystems.Weintroducetime-modecircuitsasanothercategoryofanalogsignalprocessingcircuitsthatrepresentinputandoutputsignalsinthetemporaldomain.Figure 1{1 depictsblockdiagramsforvoltage-,current-,andtime-modecircuits.Time-modecircuitsusetemporalevents,inthiscasevoltagesteps,torepresentsignals. Figure1{1: Dierentmodesofcomputation.

PAGE 17

Sinceweareusingastepfunctionrepresentation,wecannotrepresentinformationintermsofringrates(whereweneedmultiplespikestorepresentananalogvariable).Thisnewapproachissimilartotemporalcodingbysinglespikes[ 8 ]ratherthanonthetraditionalinterpretationofanalogvariablesintermsofringrates. Maass[ 8 ]pointsoutthataspikingneuroninprinciplewillbeabletocomputeintemporalcodingofinputsandoutputalinearfunctionifitspostsynapticpotentialcanbedescribedorapproximatedbyalinearfunctionduringsomeinitialsegment.AswewillseeinChapter2,time-modecircuitsperformlinearcomputationsbylinearlymappingthetemporalinputstoavoltageacrossacapacitor.Also,Maasspointsoutthatnetworksofnoisyspikingneuronsare|universalapproximators|theycanapproximatewithregardtotemporalcodinganygivencontinuousfunctionofseveralvariables.ThisobservationisprovedinChapter6whereweuseanetworkoftime-modecircuitstoimplementanapproximationofthemultiplicationfunction(non-linearfunction).

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fromapurelyengineeringperspective.Throughtheelectronicsrevolutionoverthepastdecades,CMOSprocesstechnologyisshrinkingtheusablevoltageswing,wreakinghavocontraditionalanalogcircuitdesign.However,thefaster\digital"transistorsarebetterabletoprocesstimingsignalsleadingustoconsideranalogcomputationmoresimilartothatofthebrain.Thistrendwilllikelycontinuewithnanotechnologysinceevensmallervoltagerangesandevenfasterdevicesarepromised.Ofcourse,CMOStechnologyisprimarilyscalinginfavoroffasterandfasterdigitaldevices,howeverpowerconsumptionisbeginningtolimithowfarthesedigitalcircuitscanscale. Time-basedsignalrepresentationshavebeeninuseformanyyears,includingsuchtechniquesaspulse-widthmodulationandsigma-deltaconvertersbuttemporalcodesarebecomingevenmorecommonwiththerisingpopularityofsuchtechniquesasclassDampliers,spike-basedsensorsandevenultra-wideband(UWB)signaltransmission.However,thesetemporalcodesaretypicallyusedastemporaryrepresentationsandcomputationisonlyperformedafterreconstructionbacktoatraditionalanalogordigitalform.Thereareinstanceswhereampliersusetemporalsignalsasinputsandoutputs[ 9 ],buttheydonotperformcomputationwiththem. TherearearchitectureslikethePALMO[ 10 ]wheretheinputsandoutputsarerepresentedbytemporalsignals,butusingpulses.Insucharchitectures,theinputtemporalpulsesareimmediatelyconvertedtovoltageandtheylosethecomputationaladvantagesthatthetime-basedrepresentationpromises.Similarly,Murraydiscussestheimplementationofarithmeticfunctionslikeadditionandmultiplicationusingvoltageorcurrentpulses[ 11 ].AnotherapproachbySarpeshkarusespulsesforscalablehybridcomputation[ 12 ].However,alltheabovementionedarchitecturesusepulsesforcomputationwithmorecomplicatedcircuitsthanthetime-modecircuits.

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Inthisthesiswedescribeasetofbasiccircuitbuildingblocksforcomputationusingananalogtemporalstepfunctionrepresentationforbothinputsandoutputs.

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Figure2{1. Time-modeweightedaveragecircuit.A)Circuitschematic.B)Idealizedgraphshowingthecapacitorvoltageatdierenttimeperiods. Figure 2{1 Aillustratesthebasicelementsusedtoperformaweightedsumoftemporalsignals.Ingeneral,thecircuitcanprocessmanyinputstepsbutonlytwoareshownforsimplicity.Thecircuitconsistsofasinglecapacitorandcomparatorplusaninverter,currentsourceandpfetforeachinput 13 ]. 6

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voltageVTH.Oncetheblockoutputsastep,anappropriateresetstage(notshowninthegure)resetsthecapacitorto0V.ThecurrentsourcesI1andI2chargethecapacitorduringdierenttimeperiodsasshowninFigure 2{1 B. Initially,thevoltageacrossthecapacitor(VC)isresettoground.Forsimplicity,lett1
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ThereforeforgeneralvaluesoftOUTabovetheminimumvalue, Eq. 2{5 providestherelationtobemetforEq. 2{2 tobevalid.ForthespecialcasewhereI1=I2=I,thentheoutputsteptimetoutisthemeanoft1andt2plusaprogrammableconstant(CVTH=2I). ForunequalvaluesofI1andI2, whereCVTH Inthiscase,thentheoutputtimestepistheweightedaverageoft1andt2plusaconstant. Wecansummarizetheresultsobtainedaboveinasingleequation: (2{8c) IngeneralforNinputsteps, providedthatVTHislargeenough.Thecircuitcanbefurthergeneralizedtohandlenegativeweightvaluesinseveralways;forinstance,usingcurrentsourcesthatsinkcurrenttogroundaslongastheoutputvoltagestayspositiveandeventuallyreachesVTH.

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Inputst1,t2andoutputtOUToftheweightedaveragecircuitaretime-stepsandthesetime-stepsaredenedwithinaframe(Frame1)asshowninFigure 2{2 .Whenaframe(Frame1)ends,theinputsandtheoutputstepsalsoendandthecircuitisreset.Asthenextframestarts(Frame2inthegure),thecircuitwouldbereadytoprocessthenextsetofinputst1andt2.Eachframeshouldbelongenoughtoallowtheweightedaveragecircuittoproduceitsoutput.Forboundedframelengths,thereisachancethattheoutputwillnotoccur. Figure2{2. Inputst1,t2andoutputtOUTaredenedwithinaframe 2{1 A,wehavenotshownanexplicitresetstage.Settingthecapacitor'svoltagetoitsinitialvoltageVTHthroughatransmissiongateisthefunctionalitydesiredfromtheresetstageandthiscanbeintegratedwiththeapplication'sresetstage. Laterinthisdissertation,wewilldiscusssomeapplicationsofthistime-modeweightedaveragecircuit:anedgedetectioncircuitanda3-tapFIRlter.Theseapplicationshavecustomresetstagesandtheresetforthebasicblockisintegratedinthesecustomresetstages.

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2{3 showsthemeasuredoutputtOUTwhenjustoneinputisprovidedtothecircuit.TheoutputtOUTisplottedforvaryingI.ThevaluesofCandVTHinthecircuitare20pFand2:5Vrespectively.Figure 2{4 alsoshowstheoutputtOUTwhenonlyoneinput(occuringatt1)isprovidedtothecircuit.ThecurrentsourceIisxedat1:05A.Theinputtransitiontimet1wasvariedexternallyandtheoutputtOUTwasmeasuredandplotted.TheoutputexpectedfromtheblocktOUT=t1+CVTH Figure2{3. PlotoftOUTforvaryingI(C=20pF,VTH=2:5V).Theblockwasgivenonestepinput. Figure 2{5 showstheoutputtOUTwhenboththeinputsareprovidedtothecircuitbutthecurrentsourcesI1andI2arexedat1:552A.Therstinputenteringtheblockwasxedas1s,8:5sand32:5sforthreedierentsetsofmeasurements.Theinputtransitiontimet2wasvariedexternallyfordierent

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Figure2{4. PlotoftOUTforvaryingI(C=20pF,I=1:0476A,VTH=2:5V).Theblockwasgivenonestepinput. valuesoft1andtheoutputtOUTwasmeasuredandplotted.TheoutputexpectedfromtheblocktOUT=t1+t2 Figure 2{6 showstheoutputtOUTforthecasewhenbothinputsareprovidedtothecircuitbutthecurrentsourcesI1andI2aredierentandarexedat1:46Aand0:29Arespectively.Similartotheabovecase,therstinputenteringtheblockwasxedas1s,8:5sand32:5sforthreedierentsetsofmeasurements.Theinputtransitiontimet2wasvariedexternallyfordierentvaluesoft1andtheoutputtOUTwasmeasuredandplotted.TheoutputexpectedfromtheblocktOUT=I1t1+I2t2

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Figure2{5. PlotoftOUTforvaryingt2(C=20pF,I=1:0476A,VTH=2:5Vwitht1xedat1s,8:5sand32:5s.) Eachoftheseerrorscanbereducedsomewhatwithcarefullayout,largercircuits,morepowerconsumption,and/orcalibrationprocedures.Thesetradeosmustbetakenbasedonthedemandsofparticularapplications.Particularadvantagesanddisadvantagesoftheweightedaveragecircuitandothertime-modecircuitsmustbecarefullyconsidered.Itislikelythattime-modecircuitswillhavelargerdynamicrangesthanconventionaldesignsbuthighspeedoperationwillbecompromisedsincetimeisusedintherepresentations.Generalclaimsaredicult,especiallyconsideringthatitevendiculttocitegeneraladvantagesof

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Figure2{6. PlotoftOUTforvaryingt2(C=20pF,I1=1:46A,I2=0:29A,VTH=2:5Vwitht1xedat1s,8:5sand32:5s.) current-modecircuitsvs.voltage-modecircuits[ 7 ].Abigadvantageoftime-modecircuitshoweveristhatmoreandmoresensorsarebeingdesignedwithstepoutputs[ 14 ][ 15 ]andthetime-modecircuitscandirectlyinterfacetothesesensors. Table2{1. Measuredperformancecharacteristicsoftime-modeweightedaveragingcircuit. PerformancespecicationValue Powerconsumption0:6WSNR56dBDierential-modedynamicrange62dBCommon-modedynamicrangeEectivelyinnite Byperformingcomputationusingtemporalstepfunctions,theaveragingblockwasabletoachievealmostinnitecommon-modedynamicrange,62dBdierential-modedynamicrangeandSNRof56dBwithverylowpowerconsumptionof0:6W.Thispowerconsumptionwasontheorderofnanowatts,whenthecomparatorwereoperatedinthesub-thresholdregion.But,theoperatingspeedofthecomparatorwasslow.Therefore,wehadtostrikeatrade-obetweenthe

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comparator'soperatingspeedandthepowerconsumption.ThemeasuredcircuitspecicationsaretabulatedinTable 2{1 1.outputnoiseduetotimingjitterattheinputs. 2.outputnoiseduetofundamentalnoisesourcesinthecircuit. 2{1 Ais: Jittert1(acrossdierentinputvaluesithasameanvalueof t1andavarianceof t12)intheinputt1,causesthefollowingoutput ThejitterattheoutputtOUT1isgivenby: tOUT1=tOUT1tOUT=(I1(t1+t1)+I2t2 whichisasimplescalarmultiplicationoft1. Themeanoftheoutputjitterscalesaccordinglyas, tOUT1=I1 Thevarianceofthisnoisecanbeeasilyderivedtobe, tOUT12=I21

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Similarly,thevarianceiftheoutputnoisecausedbytheinputtimejittert2(correspondingtoinputt2), tOUT22=I22 Thetotalvarianceofthenoiseattheoutputisgivenby, tOUT2= tOUT12+ tOUT22=(I21 IfI1=I2,then tOUT2= t12+ t22 Sinceonlyafraction(25%)ofthejitterattheinputsaecttheoutputjitter,wecansaythatthetime-modeweightedaveragecircuiteectivelyreducesthejitterattheinputs. 2{1 Aillustratesthebasicelementsusedtoperformaweightedsumoftemporalsignals.Wealreadyknowthattheoutputfromthisblockis: Wewillnowderiveanexpressionforthesignal-to-noiseratioofthistime-modeweightedaveragingcircuit. Therststeptowardsthederivationistodenethesignal.Assumingadierentialrepresentation,letusrefertheinputsandoutputsoftheaveragingblocktoitsrstinput.Forsimplicity,letusassumet1astherstinput.Thetwoinputstotheaveragingblockaredenedas,^t1=t1t1=0and^t2=t2t1.Theoutputisdenedas^tOUT=tOUTt1.Thisoutputisdenedasthesignal.In

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words,thesignalisdenedastheoutputtOUToftheaveragingblockreferredtotheinputt1. Therefore,^tOUTisgivenby: ^tOUT=tOUTt1=(I1t1+I2t2 Thereare3noisesourcesthatdominatethenoiseperformanceofthiscircuit. 1.NoiseduetothecurrentsourceI1. 2.NoiseduetothecurrentsourceI2. 3.Noiseduetothevoltagecomparator. Thesenoisesourcesareuncorrelatedandthereforewecanconsidertheimpactofeachofthesenoisesourcesindividuallyontheoutputofthecircuit.

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ThenoiseattheoutputtOUTcanbecalculatedasshownbelow: tOUT1=tOUT1^tOUT=I2(t2t1)+CVTH (I1+I1+I2)(I1+I2)(I2t2I2t1+CVTH)(I1) (I1+I2)2 Thevarianceofthisnoiseisgivenby tOUT12(I2t2I2t1+CVTH)2( I12) (I1+I2)4(2{22) ThenoiseattheoutputtOUTcanbecalculatedasshownbelow: tOUT2=tOUT2^tOUT=(I2+I2)(t2t1)+CVTH (I1+I2+I2)(I1+I2)+CVTH(I2 (I1+I2)2+CVTH(I2 (2{24)

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Thevarianceofthisnoiseisgivenby tOUT22(I1(t2t1)CVTH)2( I22) (I1+I2)4(I1(t1t2)+CVTH)2( I22) (I1+I2)4 ThenoiseattheoutputtOUTcanbecalculatedasshownbelow: tOUT3=tOUT3^tOUT=I2(t2t1)+C(VTH+V) Thevarianceofthisnoiseisgivenby tOUT32=(C (I1+I2)4(2{28) Fortypicalvalues,thenoisevariationdenotedbyEq. 2{28 isnegligiblecomparedtothenoisevariancesshowninEqs. 2{22 and 2{25 .Therefore,intheforthcomingcalculationsweneglectthenoisecontributionofthecomparator. Therefore,thetotalnoiseattheoutputoftheaveragingblockisgivenby tOUT2(I2t2I2t1+CVTH)2( I12) (I1+I2)4+(I1t1I1t2+CVTH)2( I22) (I1+I2)4

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ThenoiseinthecurrentsourcesI1andI2isdominatedbyshotnoise.Ingeneral,shotnoiseduetoacurrentsourceIisgivenby[ 16 ], I2=eI (2{30) whereisthetimeduringwhichthecurrentsourceisONandcontributestotheoutputandeisthechargeofanelectron. CurrentsourceI1chargesthecapacitorduringthetimeperiodtOUTt1.Noiseinthecurrentsourcewouldaectthecircuitonlyduringthistimeperiod.Therefore, Therefore, I12=eI1 CurrentsourceI2chargesthecapacitorduringthetimeperiodtOUTt2.Onlyduringthistimeperiod,thenoiseinthecurrentsourcewouldaectthecircuit.Therefore,

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Therefore, I22=eI2 SubstitutingEqs. 2{32 and 2{34 into( 2{29 ),weget tOUT2=(I2t2I2t1+CVTH)2(eI1(I1+I2) (I1+I2)4+(I1t1I1t2+CVTH)2(eI2(I1+I2) (I1+I2)4=eI1(I2(t2t1)+CVTH)+eI2(I1(t1t2)+CVTH) (I1+I2)3=eCVTH(I1+I2) (I1+I2)3=eCVTH Thesignal-to-noiseratioisgivenby: Eq. 2{36 givestheSNRforatime-modeweightedaveragecircuit. Foranaveragingcircuit,I1=I2=I.Therefore, ThemaximumvalueofthisSNRoccurswhen

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SubstitutingEq. 2{38 intoEq. 2{37 ,weget ToquantifythispeakSNRvalue,wesubstitutedC=2pFandVTH=5V(maxvalue)inEq. 2{39 andobtainedavalueof84dB.Thispeakvaluecanbeincreasedbyfurtherincreasingthevalueofthecapacitance.Fora20pFcapacitance,wegetaSNRof88dB. Wechoosethecurrent180nmasthereferencetechnologyand90nm,65nm,45nmand32nmasfuturetechnologiesforoursimulations.PTMHSpicetransistor

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modelsareusedforallthetechnologies-PredictivetechnologymodelsaredevelopedbytheNanoscaleIntegrationandModelingGroupatArizonaStateUniversity[ 17 ]. Tocomparetheperformanceoftheweightedaveragecircuitastechnologyscales,thecapacitanceCandreferencevoltageVTHwerekeptconstantacrossdierentfuturetechnologynodes.ThisensuresthatchargingcurrentsI1andI2aretheonlyvariablecircuitparametersanditallowsanaptcomparisonofthetrendsindynamicrange,powerandSNRoftheweightedaveragecircuitacrosstechnologies.TovaryI1andI2,wehadtochangethesizesofthetransistorsinthelow-voltagecascodecurrentsources.Forsimplication,thetwochargingcurrentsI1andI2werekeptconstant.Thetransistorsintheweightedaveragecircuit(thetransistorsofthelow-voltagecascodecurrentmirrors,comparatorandthedigitalswitches)weresizedfortwopossiblescenarios:

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Itwasarguedpreviouslythattheonlynoisesourcesthatcontributeheavilytothenoiseofthetime-modeweightedaveragingcircuitaretheshotnoisesoftheDCcurrentsourcesI1andI2.Thenoiseofthecomparatorisnegligible.Tocharacterizethenoiseperformanceoftheweightedaveragecircuitacrossvariousfuturetechnologies,noiseanalysisduringtransientsimulationisrequired.SincesuchananalysisisnotreadilyavailableinourCadencesoftwaresetup,toachievethistwonoisecurrentsources(withGuassiandistribution)weregeneratedrandomlyinMATLABandtheirRMSvaluesweresetaccordingtoequationspreviouslyderived.ThesecurrentsourcesmodeltheshotnoiseofthecurrentsourcesI1andI2andareconnectedinparalleltotheirrespectivecurrentsourcesduringthesimulations.ThesenoisecurrentsourceswereswitchedononlyduringtheperiodwhenthetimestepsturnedontheDCcurrentsources. Thetimingoftherststepischosenasthetimereferenceandwaskeptconstantforalltechnologies.Inthiswaytheoutputtimehadthesamereferenceinalltechnologies. 2{7 .Thisisbecauseastechnologyscales,transistorsizesreduceandtherefore,thecurrentconductedbythetransistorsscaledownexponentially(followingthewell-establishedlarge-signallong-channel/short-channelcurrentequations). 2{8 and 2{9

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Figure2{7. Variationofcapacitorchargingcurrentwithscalingtechnology Figure2{8. Variationofdynamicpowerwithscalingtechnology

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byCVTH 2{14 2{10 2{11 comparingthesimulatedandcalculatedvaluesoftheoutputoftheweightedaveragecircuit,weseethatthesimulatedresultsmatchthecalculatedresultswell.Webelievethattheslightdierenceinresultsastechnologyscalesisduetoinaccuracyincircuitmodelsatlowcurrentlevels. 2{12 conrmingtheaccuracyofthederivedexpressionfornoiseofthiscircuit.Also,noiseisinverselyproportionaltocurrentwithallotherfactorsremainingthesame.Hencewithexponentialtypedecreaseincurrentweseeanexponentialtypeincreaseinnoise. 2{13 .Thesignal,whichisthetimetakenbytheweightedaveragecircuittoproduceanoutput,increasesaswescaletechnology.Withthenoisealsoincreasingwithscalingtechnologywenotethattheratioofsignalpowerandnoisepower,theSNR,actuallydecreasesonlyslightlywithscalingtechnology.Thisisinaccordancetowhatwaspredictedbyourequations.Withmoredetailedanalysis,(withallotherfactorsconstant)wecannotethattheSNRisslightlydependentonthecurrent.Soascurrentdecreaseswithtechnology,SNRalsodecreases.However,inEq. 2{37 ,theI(t2t1)termismuchsmallerthantheCVTHtermcausingSNRtobealmostaconstant.Also,slightvariationsinthesimulatedSNRresultsconrmthisanalysis. Foralltheabovementionedperformancemeasures,forboththetransistorsizingscenarios-sizingthetransistorssothatthetransistorsareintheactiveregionandsizingthetransistorsbythetechnologyscalingfactor,weseethesameperformancetrend.

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Figure2{9. Variationofaveragepowerwithscalingtechnology Withscalingtechnology,thoughthenoiseperformanceofthecircuitgetsworsetheSNRstaysaconstant.Therefore,applicationsusingtime-modecircuitscanexpecttheSNRperformanceofthetime-modecircuitstoremainconstantwithnewtechnologies.

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Astechnologyscales,time-modecircuitsbecomemorepowerandenergyecient.Therefore,theycanbechosenforlow-powerapplicationsacrossdierentdevicetechnologies. Figure2{10. Variationofenergyconsumedperaveragingoperationwithscalingtechnology Theresultsfromtheexperimentsareveryencouragingandreinforcethefactthattime-modecircuitswouldscalewellwithtechnologyandshowgoodperformance.

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Figure2{11. Comparisonofcalculatedandsimulatedtime-modeaveragingoutputsovertechnologies Figure2{12. Comparisonofcalculatedandsimulatedtime-modeaveragingoutputnoiseovertechnologies

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Figure2{13. Comparisonofcalculatedandsimulatedtime-modeaveragingSNRvaluesovertechnologies Figure2{14. Variationofdynamicrangewithscalingtechnology

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current.Havinglargerlengthsforthesetransistorsiscriticalforaccurateoperation. 18 ]andsimulateourprototypeweightedaveragecircuit.TransistorsM1,M2,CurrentSourcesI1,I2,andtheinvertersoftheweightedaveragingcircuitarerealizedusingNCNFETandPCNFETmodelsdevelopedbyRoyetalofINAC/Purdue.ThecircuitissimulatedusingHSPICE.TheNCNFETandPCNFETtransistormodelsusedinoursimulationshaveonlyasinglecarbonnanotuberepresentingtheirchannels.Thebiggestadvantageofthissinglecarbonnanotubetechnologyisthatthetransistorshaveextremelysmallgateandchannelcapacitances;thus,promisingveryhighspeedoperation.

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ofafuturenano-electronicera.Thereasonforthisisnotjusttheirsmallsize,buttheirinherentpropertieslikelowpowerdissipation,possibleballistictransport,highcurrentdensities,highmobility,lowresistanceandthefacilitationofmakingtransistorsandinterconnectsusingsemi-conductingandmetalliccarbonnanotubes. Foratypicalnanotubegeometryof100nmlengthand3nmdiameter,Cisoforder4aF.Thechannelresistancecanbeassmallas6:25k.Therefore,theRCfrequencyisequalto6:3THz[ 19 ].LetuscomparethisfrequencywiththefTofaminimumsizeNMOStransistorintheAMI0:5uSiprocess.ThefTofaNMOStransistorcanberoughlyexpressedas, withthemobility,Lthechannellength,VGSthegatetosourcevoltageandVTHthethresholdvoltage.Substitutingtypicalvaluesof=449:98cm2=Vs,L=0:6m,VGSVTH4VforAMI0:5uSiprocess,wegetfT=80GHz.ThisshowsthatthespeedlimitintrinsictoananotubetransistorisseveralordersofmagnitudegreaterthanaSitransistor. TheCNFETmodelusedinoursimulationsisasimplisticmodelthatwasdevelopedtoassesscircuitperformanceofsinglewalledsemiconductingCNFETs.Itisanappropriatemodeltoevaluatedelays,estimatepowerincircuitsandsimulatetheperformancedegradationduetointerconnectanddeviceparasitics.ThemodelingtechniqueusedisgenericinthesensethatitcanfaithfullyrepresentawiderangeofCNFETgeometriesandgatematerialswithreasonableoperatingvoltagesanduserspeciedtemperatureconditions.Themodelhasastrongfoundationontheunderlyingphysicsofoperationalongwithnecessarysimplicationsandassumptions.Thismakesamultiple-transistorcircuitsimulationpossible. TheassumptionsmadetoarriveattheCNFETspicemodelinclude,

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Bulk-typeCNFETs:Intheliterature,twotypesofcarbonnanotubetransistorshavebeenstudiedextensively.Theyarerespectively,theSchottkybarrierCNFETandthebulk-typeCNFET.ThoughtheSchottkybarrierCNFEThasitsownadvantages,themodelassumesabulk-typeCNFETasthisMOSFET-likedevicehasahigheron-currentand,hence,woulddenetheupperlimitofperformance. Ballistictransport:RecentexperimentshavedemonstratedthataCNFETcantypicallybeusedintheMOSFET-likemodeofoperationwithnearballistictransport. 2{17 .Forthesimulationswechoset1=1ns,t2=3ns,C=7fFandVTH=0:5V.SincetheCNFETspicemodelsaresimplisticmodelsandnotidealforanalogsimulationsinsteadofthe5-transistorcomparator,wechoseanidealop-amptoperformthecomparator'sfunctionality.TheexpectedtOUTandthecalculatedtOUTvaluesmatchcloselyandtheyareapproximatelyequalto9ns.ThesmalldierencebetweenthetwotOUTvaluescanbeattributedtotheOFFcurrentoftheCNFETschargingthecapacitor.ThecarbonnanotubetransistorshaveveryhighcurrentdriveascanbeseenfromFigures 2{15 2{16 andfromFigure 2{18 wecanseethattheo-currentofthesecarbonnanotubesisalsohigh(intheorderof30nA).Thesehigho-currentscanproduceanosetthat

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introducessomejitterintheoutput.Inspiteofthelargeocurrents,theaveragepowerconsumedbythecircuitis0:33W. Figure2{15. PCNFETID-VGSplotsforvaryingVDS

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Figure2{16. NCNFETID-VGSplotsforvaryingVDS 2.5.1Motivation 20 ].Astheseprocesstechnologiesbecomemoreandmorecomplex,higherlevelsofintegrationusedintheICswillincreasethechipfailurerate.Thesefailuresunderscoretheimportanceofreliabilityformanufacturingofnano-scalesystems.Itis,therefore,imperativethatcircuitsaredesignedwithreliabilityinmind. ConstructionofreliabledigitalsystemswiththeuseofredundantcomponentswasrstconsideredbyVonNeumannforcertaincasesofintermittentfailuresofelements[ 21 ].Hisground-breakingworkwasextendedbyDickinsonandWalkerforthecaseofpermanentfailuresoflogicelements[ 22 ].ButtheworksofVon

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Figure2{17. Nano-weightedaveragecircuitsimulationoutputs Figure2{18. Capacitorcharging/dischargingcurrentinanano-weightedaveragecircuit

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Neumann,DickinsonandWalkerandmanyotherswerealldedicatedtoimprovingthereliabilityofdigitalcircuits.Inthischapter,wediscussthedesignofreliableanalognanocomputationalcircuitsusingredundancy.Asanexample,wewillexplainthedesignofareliableanalogtime-modeweightedaveragecircuit. 2{19 illustratesthebasicelementsusedtondthemedianofanodd-numberofinputtemporalsignals.Ingeneral,thecircuitcanprocessmanyinputsteps,butonlythreeareshownhereforsimplicity.Thecircuitconsistsofaninverter,acurrentsourceofvalueIandaPMOStransistorforeachinputandacurrentsourceofvalue3I Figure2{19. Time-modemediancircuitfor3-inputs Toaidtheexplanationoftheoperationofthiscircuit,weassumethatt1
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attimet2,anetcurrentofI Thus,weseethattheoutputobtainedinEq. 2{41 isthemedianofthethreeinputst1,t2andt3.Ingeneral,thismediancircuitcanprocessN-inputsteps-providedthatNisodd.ThecircuitisshowninFigure 2{20 .DependingonthevalueofN,thevalueofthecurrentsourcethatpulls-downthecapacitor'svoltageischosentobeNI Figure2{20. Time-modemediancircuitforN-inputs 2{21 andperformanalysistoquantifyitsreliability. VonNeumann's2-out-of-3majoritycircuitshowninFigure 2{21 usesamajoritycircuitfedbythreeindependentdeviceswhichoperatefromthesame

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Figure2{21. VonNeumann'stwo-out-of-threemajoritycircuit sourceofinputinformation[ 21 ].DickinsonandWalkeranalyzedthecircuitindetailandprovedthatthecircuithasaresultantreliabilitygreaterthanthatofitselements[ 22 ].Asmentionedabove,theirworkwasonlyapplicabletodigitalcircuits.Here,weusetheirconcepttoimprovethereliabilityofanalogcircuits.WewillextendtheworkofDickinsonandWalkertodesignareliableanalogtime-modeweightedaveragecircuitasshowninFigure 2{22 .VonNeumann's2-out-of-3majoritycircuitisessentiallyusedpollingbetweeninputsandcanonlybeusedfordigitalapplications.Therefore,itisbeingreplacedbyatime-modemediancircuitasshowninFigure 2{19 .Forourfailureanalysis,weassumethatthemediancircuitneverfails.Thesameassumptionismadeforthedigitalvotingcircuitsdiscussedabove.Theonlyfailurestobeconsideredarethoseofthethreeelements(weightedaverageblocks)whichfeedthemediancircuit. Thetime-modeweightedaverageblockhascomponentslikecurrentsources,digitalswitches,comparatorandacapacitor.Itispossibleforanyofthesecomponentstofailandintroduceerrorsintheoutputofthecircuit.Forexplanationpurposes,lettheoutputoftheweightedaveragecircuitwhentherearenofailuresinitscomponentsbetidealoutandtheoutputwhentherearesomefailuresbetobtainedout. Theweightedaverageblockscanfailintwomodes: 1.tobtainedout
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Figure2{22. Blockdiagramofareliabletime-modeweightedaveragecircuit 2.tobtainedout>tidealout.Thisalsoincludesthecasewhereduetofailure,theweightedaverageblockresanoutputimmediatelyafteritsinternalnodesarereset(theresetstageisnotshowninthegure)-(tobtainedoutisclosetozero). LetusassumethattheprobabilitythatanyweightedaverageblockwillfunctioncorrectlyisR0.TheprobabilitythattheredundantsystemisnotgoingtofailR1isgivenbythesumofthethreecasesmentionedbelow: 1.Allthethreetime-modeweightedaverageblocksfunctioncorrectly.TheprobabilitythattheredundantsystemisnotgoingtofailinthiscaseisgivenbyR30. 2.Oneoftheweightedaverageblocksfailinanyofthetwomodes-(tobtainedout>tidealout)or(tobtainedout
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functioncorrectlyis(1R0)2R0andthiscanhappeninthreedierentways.Therefore,theprobabilityforthiscaseisgivenby3 2(1R0)2R0. Therefore,thetotalprobabilitythattheredundantsystemisnotgoingtofailR1isgivenbythesumoftheprobabilitiesobtainedintheabovementionedthreecases[ 22 ]: 2(1R0)2R0=3 2R01 2R30 Figure2{23. Plotshowingtheincreaseinreliabilityoftheredundantcircuitascomparedtotheindividualelements FromtheresultshowninEq. 2{42 ,weseethattheredundanttime-modeweightedaveragecircuitisalwaysmorereliablethantheindividualelements.ThiscanalsoberealizedfromthereliabilitycurveinFigure 2{23 .Asshowninthatgure,thereisaconsiderableimprovementinthereliabilityoftheredundantcircuitascomparedtothereliabilityoftheindividualelements.

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thatsuchredundancywouldincreasethechiparea.But,mostoftherealtimeapplicationswouldcompromiseonthechipareathanonthereliabilityofthecircuits.Also,thisredundantweightedaveragecircuitcanbeseenasasteppingstonetowardsimprovingthereliabilityofnanocomputationalcircuits. InChapter2,wewillseehowtheperformanceofthetime-modeweightedaveragingcircuitwithitsvoltage-modeandcurrent-modecounterparts.

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Wehavequantiedtheperformanceoftime-modecircuitsintermsofkeymeasuressuchasSNR,DRandpowerconsumption.Theseperformancemetricsarenotclear-cut.Forinstance,dynamicrangeisawell-denedconceptinvoltage-modeandcurrent-modebutmustbecarefullyconsideredforsometime-modecircuitswhoseinputscanbearbitrarilylarge. WeneedtocomparetheperformancemeasuressuchasSNRandDRoftime-modecircuitstocorrespondingvoltage-modeandcurrent-modecircuitsbymakingaceterisparibus(otherthingsbeingequal)comparison.Sinceitisdiculttocompareallpossiblevoltage-mode,current-modeandtime-modecomputationcircuits,wewouldliketostartbyrestrictingourselvestothecomparisonofweightedaveragecircuitsshownintheFigures 3{1 3{3 andthetime-modeweightedaveragingcircuitdiscussedinChapter2.WewillquantizetheirSNRandDR,comparetheirperformances,andcommentonthem.Themaincriteriaforthechoiceofthesevoltageandcurrentmodeweightedaveragecircuitsarelowcomplexityandlowpowerconsumption.Thechoicewouldenableustoperformafaircomparisonwiththebasictwo-inputtime-modeweightedaveragecircuit. Therstcircuitoperatinginvoltage-modecomputes whereg1andg2representthetransconductancesofthetwoOTAsinthecircuit.ThetransconductancesaresetbytheindividualbiasvoltagesappliedtotheOTAs.V1,V2arethetwoinputvoltagesandVOUTistheoutputvoltageofthecircuit. 42

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Thesecondcircuitoperatingincurrent-modecomputes whereI1,I2arethetwoinputcurrentsandVOUTistheoutputcurrentofthecircuit.k1,k2arethevoltagesappliedtothetransistorsinthecircuit.Thesevoltagescontributetotheweightsek1andek2appliedbythecircuittocomputetheweightedaverage. And,aswehaveseeninChapter2,thetime-modeweightedaveragingcircuitcomputes Asmentionedearlier,thoughwecancomeupwithmoreecientcircuits,thevoltage-mode,current-modeandtime-modeaveragingcircuitscomparedinthispaperarechosensuchthattheircircuitarchitectureisextremelysimpleandconsumeverylowpower. ToquantifytheSNRrelationsobtainedforvoltage-mode,current-modeandtime-modeaveragingcircuits,let'smakethefollowingassumptions. 3{1 illustratesthebasicelementsusedtoperformaweightedaverageofvoltage-modesignalsV1andV2.ItconsistsoftwotransconductanceampliersG1andG2connectedinunityfeedbackcongurations.

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Figure3{1. Voltagemodeweightedaveragingcircuit Theoutputofthecircuitisgivenbytheequation: ForSNRcalculations,weneedtodeneareferencefortheinputsandoutputs.LetusdenetheinputV1asthereference. Now,VOUTdenedwithrespecttothereferencewouldbegivenby, ^VOUT=VOUTV1=(g1V1+g2V2 TherearetwonoisessourcesinthiscircuitasshowninFigure 3{2 1. v12-noiseduetooperationaltransconductanceamplierg1referredtoitspositiveinput. 2. v22-noiseduetooperationaltransconductanceamplierg2referredtoitspositiveinput. Sincethesetwonoisesourcesarenotcorrelated,wecanderivetheindividualcontributionofeachofthesenoisesourcesattheoutputandaddupthecontributionsbyapplyingsuperposition.

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Figure3{2. Voltagemodeweightedaveragingcircuitwithnoisesources VOUT1=g2(V2(V1+v1)) (3{6) Thevarianceofthenoiseattheoutputisgivenby, VOUT12=g22 SimilarcalculationsaredoneforthenoisecontributionfromOTA2. VOUT2=g2((V2+v2)V1) (3{8) Thevarianceofthenoiseattheoutputisgivenby, VOUT22=g22

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Therefore,thetotalnoisecontributionattheoutputduetothetwonoisesourcesisgivenby, VOUT22=g22( v12+ v22) (g1+g2)2(3{10) AssumingthattheOTAsarebasic5-transistordierentialinput/singleendedoutputOTAs,wewouldhavenoisecontributionsfromtheinputtransistorsandthemirrortransistors.Neglectingickernoiseofthesetransistors(validforintermediateandhighfrequencies)andtakingonlythermalnoiseintoourcalculations,theinputreferrednoisevariancesaregivenby: VOUT12=4(8kT VOUT22=4(8kT 2ROUTCOUT(3{13) where,COUTisthecapacitanceattheoutputnode,usuallydenedbytheloadcapacitanceCL. Hence, 21 Ifanamplierhasjustonepoleatfc,thenthenoisebandwidthisgivenby f=

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Thesignal-to-noiseratioisgivenby v12+ v22) (g1+g2)2=(V2V1)2 v12+ v22)=(V2V1)2 8kT(V2V1)2g1g2COUT Foranaveragingcircuit,g1=g2andtheSNRrelationbecomes, 32kT(V2V1)2COUT(3{18) ForAMI0:5process,maximumvalueofV2V1thatcouldbeachieved=3:5V(thoughttherail-to-railvoltageis5V,tomaintainthetransistorsoftheOTAinsaturationtheinputvoltageswingwouldbelower).Also,throughhandcalculationswefoundoutthattheoutputnodecapacitanceis0:4pF.SubstitutingallthevaluestoEq. 3{18 ,wegetmaximumSNRof80dB. 3{3 illustratesthecircuitthatperformsweightedaverageofcurrentsI1andI2.Inthiscircuit,transistorsM1-M4operateinthesub-thresholdregionandtheyareinsaturation. Weassumethatinallthesub-thresholdcurrentequationsbelowthat=1.ByusingKCLatnodes1and2inFigure 3{3 ,wecanwrite VT+ISeK1VA VT=ISeVA VT[eK1 (3{19)

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Figure3{3. Currentmodeweightedaveragingcircuit and VT+ISeK1VB VT=ISeVB VT[eK1 (3{20) FromEqs. 3{19 and 3{20 ,weget VT VT(3{21) Theoutputcurrentisgivenby VT+ISeK2VB VT(3{22) Figure3{4. Currentmodeweightedaveragingcircuitwithnoisesources

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SubstitutingEq. 3{21 inEq. 3{22 ,weget VT[eK1 VT[I1eK1 UsingEq. 3{19 inEq. 3{23 ,weget Figure 3{4 showsthecurrentmodeweightedaveragingcircuitwithnoisesources.Asshowninthegure,thereisnoiseassociatedwitheachtransistorinthecircuitandtheequivalentnoisevariancescanberepresentedusingcurrentsourcesconnectedinparalleltothetransistors.ThenoisecurrentsourceI1seesthesourceresistance1 3{5 .SinceK1=K2,gm1=gm2.Therefore,halfofthecurrentI1owsthroughtransistorM2andcontributestonoiseintheoutputcurrentIOUT.SimilarlyonlyhalfofnoisecurrentsI2,I3andI4contributestooutputnoise. Therefore,thetotaloutputnoisecurrentisgivenby IOUT=I1+I2+I3+I4 Thevarianceintheoutputnoisecurrentisgivenby IOUT2= I12+ I22+ I32+ I42 Neglectingickernoise,thenoisecurrentofatransistoroperatinginthesubthresholdregionisgivenby2KTgm.Substitutingthisnoisecurrentexpression

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inEq. 3{26 ,weget IOUT2= I12+ I22+ I32+ I42 (3{27) wherethenoisecurrentsoftransistorsM1andM2wouldhaveanoisebandwidthdeterminedbyR-Ctimeconstantofnode1andnoisecurrentsoftransistorsM3andM4wouldhaveanoisebandwidthdeterminedbyR-Ctimeconstantofnode2. SinceK1=K2,forsubthresholdtransistorsgm1=gm2.Similarly,gm3=gm4.Therefore, IOUT2=(KTgm1)f1+(KTgm3)f2(3{28) Figure3{5. Halfofthenoisecurrentfromeachtransistorowstotheoutput Thepolecontributedbynode1isgivenby: 21 NoisebandwidthfornoisecurrentsoftransistorsM1andM2isgivenby, f1= Thepolecontributedbynode2isgivenby: 21

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NoisebandwidthfornoisecurrentsoftransistorsM3andM4isgivenby, f2= asparasiticcapacitanceCnode1=Cnode2. Thevarianceintheoutputnoisecurrentisgivenby, IOUT2=(KTgm1)gm1 (3{33) Sincethediscussionswouldgettoocomplex,letusjustfocusourdiscussionsheretocurrentmodeaveragingfunctionality.LetsassumethatK1=K2.TheoutputIOUTinthiscaseisgivenbyIOUT=I1+I2 ^IOUT=IOUTI1=(I1+I2 (3{34) Thesignal-to-noiseratioisgivenby (3{35) ToquantifytheSNRequation,wesubstitutedthesenominalvalues:Cnode1=0:4pF(asinthevoltage-modecase),I1=1nA(lowsub-thresholdcurrent)andI2=20nA(highsubthresholdcurrent)inEq. 3{35 .ThemaximumSNRthatcanbeobtainedfromthiscircuitis44dB.

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3{6 Figure3{6. CalculatedandsimulatedSNRvaluesofatime-modeweightedaveragingcircuitovertechnology Sofarwehavejustdiscussedasingletypeoftime-modecircuit-theweightedaveragingcircuit.InChapter4,wewilldescribeothertime-modecomputationalcircuits.

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Inthischapter,wewillintroduceafamilyoftime-modecircuitsthatcanperformlinearcomputationslikeweightedsubtraction,weightedsum,scalarmultiplication,maximumandminimumcomputations. 2{1 A,weobtainacircuitthatcanperformweightedsubtractionofstepsoccurringatt1andt2asshowninFigure 4{1 A. A)B) Figure4{1. Weightedsubtractioncircuit.A)Circuitschematic.B)Idealizedgraphshowingthecapacitor'svoltageatdierenttimeperiods. WewillassumethatthecapacitorisinitiallychargedtoavoltageVTH,t1I1.Assoonastherststepenterstheblockattimet1,thecurrentsourceI1startstochargethecapacitor.Whentheinputstepoccursattimet2,netcurrentI2I1(withI2>I1)startsdischargingthecapacitorasshowninFigure 4{1 B.WhenthecapacitorvoltagereachesVTH,thecomparatoroutputsastepattimetOUT.Theoutputofthecomparatorcontainsanunwantedpulseatthereference 53

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timebecausethepositiveandnegativeterminalsofthecomparatorcarriesthesamevoltageVTH.TheANDgateconnectedtotheoutputofthecomparatorensuresthattheoutputfromtheblockcontainsonlyastepoutputattimetOUT.Oncetheblockoutputsastep,anappropriateresetstage(notshowninthegure)resetsthecapacitorto0V. TheoutputtOUTfromtheblockisgivenbytheequation, Weseefromtheequationabovethat,theblockappliesaweightI2=(I2I1)tot2andaweightI1=(I2I1)tot1.Thisblockhasasingle-endedoutput. Withouttheassumptionsmadeabove,dierentoutputsgivenoutbytheblockcanbesummarizedinasingleequation: Nooutput;otherwise (4{2c) Asintheweightedaveragingcircuit,inputst1,t2andoutputtOUTaretime-stepsandaredenedwithinaframe.Whentheframeends,theinputsandtheoutputstepsalsoendandthecircuitisreset.Asthenextframestarts,thecircuitwouldbereadytoprocessthenextsetofinputst1andt2. 4{2 AisagainaminormodicationofthebasicblockshowninFigure 2{1 A.WewillassumethatthecapacitorisinitiallychargedtoavoltageVTH,t1
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thecapacitorandnetcurrentI2I3chargesthecapacitorC.Whenthesecondsignalenterstheblockattime^t2(where^t2isdenedast2withrespecttoreferencetimetREF),currentsourceI3dischargesthecapacitor.AcomparatorsensesthevoltageacrossthecapacitorandoutputsastepwhenthevoltagereachesthethresholdvoltageVTH.TheoutputofthecomparatorwouldcontainanunwantedpulseatthereferencetimebecausethepositiveandnegativeterminalsofthecomparatorcarrythesamevoltageVTH.TheANDgateconnectedtotheoutputofthecomparatorensuresthattheoutputfromtheblockcontainsonlyastepoutputattime^tOUT=tOUTtREF.Oncetheblockoutputsastepandtheframeends,anappropriateresetstage(notshowninthegure)wouldresetthecapacitorvoltagetoVTHatreferencetimetREF. ^tOUT=(I1 Fromtheaboveequation,weobservethattheblockcomputesaweightedsumofthetwoinputtimestepsoccurringattimes^t1and^t2. Anoutputfromtheblockoccurswhen (I1+I2I3)^t1+(I2I3)(^t2^t1)>0(4{4) SolvingEq. 4{4 ,wewouldget Eq. 4{5 canbeinterpretedas, ^t2>(I1 Sincet1
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Ifweassumethatt2occursbeforet1,wewouldgetanoutputfromtheblock,when (I1+I2I3)^t2+(I1I3)(^t1^t2)>0(4{7) SolvingEq. 4{7 givesI3>I1I2. A)B) Figure4{2. Weightedsumcircuit.A)Circuitschematic.B)Idealizedgraphshowingthecapacitor'svoltageatdierenttimeperiods. Inbothcases,I1=I2=Iresultsin ^tOUT=^t1+^t2(4{8) Thiscasecorrespondstothesumoftwoinputtimestepsoccurringat^t1and^t2.Thus,weseethatbycontrollingthecurrentsources,weachievetwodierentfunctionalitiesfromtheblock-sumandweightedsum. Withouttheassumptionsmadeabove,dierentoutputsgivenoutbytheblockcanbesummarizedinasingleequation: ^tOUT=8>>>><>>>>:(I1 (4{9a) ^t1+^t2;fort1t2;I1=I2=I3 Nooutput;otherwise (4{9c) Thecircuithasasingle-endedoutput;theinputsandoutputsoccurringatt1,t2andtOUTaredenedwithrespecttoatimereferencetREF(startoftheframe).

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2{1 A,weobtainacircuitthatcanbeusedforscalarmultiplicationofatemporalsignalenteringtheblockattimet2asshowninFigure 4{3 A. A)B) Figure4{3. Scalarmultiplicationcircuit.A)Circuitschematic.B)Idealizedgraphshowingthecapacitor'svoltageatdierenttimeperiods. AssumingthatthecapacitorisinitiallychargedtoavoltageVTH,thecurrentsourceI1startstochargethecapacitorassoonastheframestarts(attimetREF).Theinputstepoccursattime^t2where,asabove,^t2isdenedast2withrespecttoreferencetimetREF.ThecurrentsourceI2I1startsdischargingthecapacitorasshowninFigure 4{3 B.WhenthecapacitorvoltagereachesVTH,thecomparatoroutputsastepattimetOUT.TheoutputofthecomparatorwouldalsocontainanunwantedpulseatthereferencetimebecausethepositiveandnegativeterminalsofthecomparatorwouldcarrythesamevoltageVTH.TheANDgateconnectedtotheoutputofthecomparatorensuresthattheoutputfromtheblockcontainsonlyastepoutputattimetOUT.Oncetheblockoutputsastep,anappropriateresetstage(notshowninthegure)wouldresetthecapacitortoVTHatreferencetimetREF.

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TheoutputtOUTfromtheblockisgivenbytheequation, ^tOUT=(I2 Weseefromtheequationabovethat,theblockmultipliestime^t2withascalarI2=(I2I1). Withouttheassumptionsmadeabove,dierentoutputsgivenoutbytheblockcanbesummarizedinasingleequation: ^tOUT=8<:(I2 Nooutput;forI2I1 Thisblockhasasingle-endedoutputandtheinputsandoutputsaredenedwithrespecttoatimereferencetREF(thestartoftheframe). CircuitschematicofMAXcircuit Figure4{5. CircuitschematicofMINcircuit TheMAXandMINcircuitsshowninFigures 4{4 and 4{5 supportinputsandoutputsthathaveabsolutetimeasthereference.TheoutputfromtheMAX

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andMINcircuitsaresingle-ended.Thisblockprocessestwotemporalsignalssay,thetimestepsoccurringatt1andt2asshowninthegure,anddeterminesthemax(t1;t2)ormin(t1;t2)ofthetwosteps.Ifthesignalwastoberepresentedusingvoltages,acomplexcircuitwouldberequiredtocomputemax(V1;V2)ormin(V1;V2).Intime-basedanalogcomputation,thecircuitrytocomputethesefunctionsisstraightforward. Thetime-modelinearcomputationalcircuitswehavediscussedsofarandthethresholdeddierenceblock(tobediscussedinChapter5)canbeclassiedintodierentsubclassesbasedontheiroutputstyle,showninTable 4{1 Table4{1. ClassicationofTime-modecomputationalcircuits.Relativetimereferenceimpliesthattheinputsandoutputsaredenedwithrespecttoareferencetime(startofaframe).Absolutetimereferenceimpliesthatinputsandoutputsarenotdenedwithrespecttoareferencetime. OutputSingle-endedDierential AbsolutetimereferenceWeightedAveragingCircuitThresholdeddierenceWeightedSubtractionCircuitblockofEdgedetectionMAXcircuitMINcircuitRelativetimereferenceSumcircuitScalarMultiplicationCircuit Sofar,wehavediscussedtime-modecomputationalcircuitstoperformcomputationslikeweightedaverage,weightedsubtraction,weightedsum,scalarmultiplication,maximumandminimum.InChapter6,wewilldiscussacoupleofapplications-atime-modeedgedetectioncircuitandatime-mode3-tapFIRlter.

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14 ],[ 15 ].Inthissection,anexampleisgivenwhereatime-modeedgedetectorisdevelopedtodirectlyinterfacetotheoutputofatime-to-rstspikeimager[ 14 ]. Figure5{1. Edgedetectionbyderivativeoperators 23 ].Anedgeistheboundarybetweentworegionswithrelativelydistinctgray-levelproperties.Inallthediscussionsbelow,weassumethatthe 60

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regionsinquestionaresucientlyhomogeneoussothatthetransitionbetweentworegionscanbedeterminedonthebasisofgray-leveldiscontinuitiesalone. Traditionally,theideaunderlyingmostedge-detectiontechniquesisthecomputationofthelocalderivativeoperator.ThisconceptisillustratedinFigure 5{1 .Thegureshowsasyntheticimageofalightobjectonadarkbackground,thegray-levelprolealongahorizontalscanlineoftheimage,andtherstandsecondderivativesoftheprole.Wenotefromtheprolethatanedge(transitionfromdarktolight)ismodeledasaramp,ratherthanasanabruptchangeofgraylevel.Therstderivativeofanedgemodeledinthismanneris0inallregionsofconstantgraylevel,andassumesaconstantvalueduringagray-leveltransition.Thesecondderivative,ontheotherhand,is0inalllocations,exceptattheonsetandterminationofagray-leveltransition.Basedontheseremarks,itisevidentthatthemagnitudeoftherstderivativecanbeusedtodetectthepresenceofanedge,whilethesignofthesecondderivativecanbeusedtodeterminewhetheranedgepixelliesonthedark(background)orlight(object)sideofanedge.ThesignofthesecondderivativeinFigure 5{1 forexample,ispositiveforpixelslyingonthedarksideofboththeleadingandtrailingedgesoftheobject,whilethesignisnegativeforpixelsonthelightsideoftheseedges.Althoughthediscussionthusfarhasbeenlimitedtoaone-dimensionalhorizontalprole,asimilarargumentappliestoanedgeofanyorientationinanimage. Inthischapter,wewilldiscussthedesignofatime-modeedgedetectorthatperformsarstderivativeoperationonthepixeloutputsthroughanoveltime-modethresholdeddierencingblocktodetectboththepresenceandthesignoftheedges.Signicantchangesinsceneilluminancearetypicallydetectedwithaspatialderivativeoperationfollowingaspatialsmoothingprocessthatreduceshighfrequencynoise.Figure 5{2 showsthebasicdataowintheproposedtime-basededgedetectionscheme.Initiallythetimestepscorrespondingtopixelintensities

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aresmoothed.Next,thesmoothedtimestepsarefedtoathresholdeddierencingblockthatndsthedierencebetweentheinputstepsandthresholdstheresult.Theoutputofthethresholdedderivativeblockcaneitherbepositiveornegativeimplyingapositiveornegativeedgebetweenpixels. Figure5{2. Dataowintime-modeedgedetection 24 ],[ 14 ].Thisimagerprovidesoutputstepswhosetimingencodesilluminationinformationateachpixel.Thesespatialinformationmustbesmoothedtoeliminatenoiseintheimageaswellasnoiseintroducedbytheelectronics. Figure5{3. Circuittosmoothpixelintensities Figure 5{3 showsacircuitthatcouldbeusedtoperformsmoothingofthesepixelintensities.Weimplementastandardconvolutionmaskwithweightsof1-2-1

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byappropriatelyscalingthecurrentsourcevalues.SincethecircuitshowninFigure 5{3 isaspecialcaseoftheweightedaveragingcircuitexplainedinChapter2,wecaneasilyderivethesmoothingblock'soutputexpressedbelow: 5{4 .TherearetwocasestobeconsideredassumingthatVCisinitiallyresettoamidrangevoltage: ThethresholdimplementedbythisblockisCVTH=I.ThisthresholdvaluecanbeprogrammedbychoosingdesiredvaluesforVTHandI. Ifthethresholdeddierenceblockresanoutput,wecanknowthepresenceofedgesbetweenadjacentpixels.Also,dependingonwhetherwegetpositiveoutputornegativeoutputwecaninferthesignoftheedges.Thatis,apositiveoutputimpliesthatpixel1isbrighterthanpixel2.Thus,fromtheoutputsofthe

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Figure5{4. Circuitusedtoobtainthresholdeddierencesonthesmoothedsteps thresholddierentiationblock(thatperformsaspatialrstderivativeoperation),wecandetectboththepresenceandthesignoftheedges. 5{5 .Intherstframe,weconvertedthepixelmagnitudeinformation(between0and255)ofeachpixeltotiminginformationusingreversecoding.Abrightpixelwouldreearliercomparedtoadarkpixel,thatis,withrespecttotheframethebrightpixelwouldhaveasmallertemporalamplitudecomparedtoadarkpixel.Inthesecondframe,weremovethespuriousnoiseintheimagebyusingtime-modesmoothingcircuits.Aftersmoothing,weperformthespatialrstderivativeoperationbyrunningthesmoothingblock'soutputsthroughtime-modethresholdeddierenceblocksinthethirdframe. Forbetterunderstanding,letusrestrictouranalysisto16pixels.Theoriginalnoisyimage,smoothedimageandthedetectededgesareshowninFigure 5{6 .Thenoisyoriginalimageandthesmoothedimageareshownindottedlinesandsolid

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linesrespectively.Theedgesdetectedareshownspecialcharactersinthegure.Fromtheresultsshown,wecaninferthatthetime-basededgedetectionmethodisextremelyaccurate. Forthese16pixels,Figure 5{7 showstheCadencesimulationoutputsfromdierentstagesinthetime-basededgedetectionprocess.Thelengthoftheframeandthethresholdwechoseforthethresholdeddierenceblockare30msand15msrespectively.Inthegure,theoriginalimageisshownfollowedbythetemporalsignalsoutputbytheimager.Itisfollowedbytheoutputsofthesmoothingandthresholdeddierenceblocks.Theedgedetectioncircuitsneeds3framestocompletetheiroperations.Thenalresultsindicatethatonlythreeedgesweredetectedtobeabovethethreshold.Thepowerconsumedbytheedgedetectioncircuitsforthese16pixelswasintheorderto35W.

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Figure5{5. MATLABsimulationresultsshowingtheoriginalimage,smoothedimageandthedetectededgesofanimage

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Figure5{6. Simulationresultsshowingtheoriginalimage,smoothedimageandthedetectededgesofa16pixelimage

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Figure5{7. Outputsfromdierentstagesintime-modeedgedetection

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FromEq. 5{2 ,wecaneasilyinferthatbycontrollingC,VTHorIwecanprogramthedesiredthresholdinthethresholdeddierenceblock.But,onceaedgedetectionchipisdesigned,itistoughtovarythevalueofC.Therefore,tovarythethreshold,weshouldeithertuneVTHorIo-chip. Fora3-taplter, FromEq. 5{4 ,weseethattocomputethen-thsampleoftheoutputofa3-tapFIRlter,weneedthecurrentinputx(n)andtwopreviousinputsx(n1)andx(n2).Forexample,theoutputatthe3rdsamplingperiodisgivenby, Iftheinputandoutputatthe3rdsamplingperiodarerepresentedintimebyt3TINandt3TOUTrespectively,thenwecanimplementatime-modeFIRlterifwecan

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implement, FromEq. 5{6 ,weseethatwewouldneedinputst2TINandtTINotherthant3TINtoobtaint3TOUT.Todothis,wecaneither sothattheseinputswouldbeavailableduringthesamplingperiod3TwhenthecomputationshowninEq. 5{6 istobeperformed. Whentheinformationisintime,delayingthatinformation(informationisencodedintherisingedgeofatimestepreferencedtothestartofaframe)wouldinvolveconvertingthetimeinformationtovoltageandthenconvertingthatvoltagebacktotime(informationagainisatimestepbutreferencedtoanewframe)usinganalogcomponents.Sinceweareconsideringtheimplementationofa3-tapFIRlter,wewouldneedtwodelaystages.Sincethedelaystagesinvolveanalogcomponentslikecurrentsourcesandcapacitorsthathavematchingconstraints,wemightendupwithinaccuratedelaysthatmightleadtoerroneousoutputs.Therefore,thebetteroptionwouldbestoretheinformationovervarioussamplingperiods.Since,wehavenotyetcomeupwiththecircuitthatwouldstoretimeinformationdirectlyintime,weconvertthetimeinformationtovoltageandstoreitonacapacitor. 5{8 issimilartotheprototypetime-modeweightedaveragecircuitexceptthatthisgurealsoshowstheresetfunctionality.Threeinputsthatenterthisblockare 1.trainofframes-theseactasreferencefortheinputandoutputsteps. 2.trainofinputsteps.

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Figure5{8. ComputationalblocktobeusedintheFIRlter

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3.chipreset. LetspostponethediscussionoftheinputprocessingthatshouldbedonetothetwoinputtrainstogeneratesignalsIN1,IN2,IN3,NEG INandCOMPUTATIONRESETtothenextsection.ThesesignalsaretheinputstothecomputationalblockshowninFigure 5{8 .Beforeanyoftheinputtrainsenterthesystem,thechipresetsignalwouldresetthecapacitor'svoltagetoVTH.Astherstframestarts,IN1generatedbytheinputprocessingblockturnsontheswitchM1foraperiodt1.Thislet'sthecurrentsourceI1chargethecapacitanceCfortheperiodt1asshowninFigure 5{9 Figure5{9. Voltageacrossthecomputationalblock'scapacitoratvarioustimes Thevoltageacrossthecapacitorisgivenby, Thecapacitorinthisblockperformstwofunctionalitiessimultaneously:

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Afterthesecondframestarts,IN2turnsontheswitchM2causingI2tochargethecapacitanceCforaperiodt2.Thenewvoltageacrossthecapacitorisgivenby, Now,thecapacitorisholdingbothinputst1,t2andhasappliedweightsI1 5{9 Asframe4starts,thesignalNEG INturnsonswitchM4andthecurrentI4startstodischargethecapacitanceC.Withthevoltageacrossthecapacitancebeingcontinuouslymonitoredbythecomparator,voltageacrossthecapacitanceslowlydecreasesasI4dischargesitandwhenthevoltagereachesVTHthecomparatorresastepoutput.TherisingtimeofthisoutputstepreferencedtothefourthframegivesthedesiredoutputtOUT. FromEq. 5{10 ,weseethatthecomputationalblockappliesweightsI1

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computation,thecapacitorvoltageisresettoVTHbythecomputationresetsignalgeneratedbytheinputprocessingblock. Wemadethefollowingbasicassumptionstoarriveattheaboveresult: Since,t1,t2,t3andtOUTaredenedwithframes1,2,3and4asreferencerespectively,wecanwriteEq. 5{10 as, Asmentionedintheassumptionsabove,theONperiodofframe4shouldbelargeenoughatleasttoproduceanoutputattimetOUT.Therefore,tframe4ON=tOUT.AssumingthattheOFFperiodoftheframewherethecapacitorisresettoVTHisextremelysmall,tframetOUT.Therefore,theminimumpossibleframelength=tOUTandthemaximumpossiblesamplingspeed=1 IftheEq. 5{11 canbeinterpretedintermsofsamplesthen, ComparingEq. 5{12 withtheconventional3-tapFIRequationshownbelow, weseethattOUThasanextrasampledelaywhencomparedtotheconventionalFIRoutput.Inotherwords,theFIRlter'scomputationblockhasanextrapoleattheoriginascomparedtotheconventionalFIRlter. 5{8 .Let'ssaythat

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thecomputationalblockprocessesinputstIN(1)referencedtoframe1,tIN(2)referencedtoframe2,tIN(3)referencedtoframe3andproducesanoutputtOUT(4)referencedtoframe4.Thecomputationalblockgetsreadytoprocessthenextsetofinputsonlyattheendofframe4wherethecapacitorisresettoVTH.ThenextoutputthisblockwouldproduceistOUT(8)processingtIN(5),tIN(6)andtIN(7).SincethisblockcannotproducetheintermediateoutputstOUT(5),tOUT(6)andtOUT(7),wewouldneedthreemorecomputationalblockstoproducethoseoutputs.Therefore,the3-tapFIRlterwouldneedintotal,fourcomputationalblockstocontinuouslyprocesstheinputtimesignals.Ingeneral,foraN-tapFIRlter,wewouldneedN+1computationalblockstoconstructtheFIRlter. Thecompletearchitectureofa3-taptime-modeFIRlterisshowninFigure 5{10 .TheFIRlterblockneedsthesame3inputsasthecomputationalblock-achipreset,atrainofframesandatrainoftimestepsasshowninFigure 5{12 .Everyinputstep(example,t1)inthetrainoftimestepsisdenedwithrespecttoaframe(example,frame1)inthetrainofframesasshowninFigure 5{12 .Thetrainsofframesandtimestepsarefedtoainputconditioningblock.ThearchitectureoftheinputconditioningblockisshowninFigure 5{11 Theinputconditioningblockperformsthefollowingfunctions: Eachcomputationalblockneeds3inputsindierentlines-becausewearedesigninga3-tapFIRlter.Also,sincetherearefourcomputationalblocksthatprocessthefollowingdierentsetsofinputs-(t1,t2,t3),(t2,t3,t4),(t3,t4,t5)and

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Figure5{10. 3-taptime-modeFIRlterarchitecture

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Figure5{11. Thearchitectureoftheinputconditioningblock

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(t4,t5,t6)-thatis,ateverysample(frame),wewouldneed6inputsin6dierentlinesforthe4computationalblocks.Tokeepmovingtheseinputsatdierentinputlinesduringeveryframe,wehaveused2counters-a2-bitcounteranda3-bitcounter(thatcountsbetween3and5)-followedbydecoders.Similarly,sinceweneedtheframestodischargethecapacitancesofthecomputationalblocks,wehavea3-bitcounterfollowedbyadecodertodecodetheframetrainonto4dierentlines. Figure5{12. 3-tapFIRlter'sinput,digitalpreconditioningblockanditsoutputs

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Thearchitectureshownisfora1-quadrantFIRlter.Thatis,itcanonlyprocesspositiveinputsandapplypositiveweightstothoseinputs.Byaddingextracircuitry,wecanextendthisarchitecturetoprocessbothpositiveandnegativeinputsandapplybothpositiveandnegativeweightstothoseinputs. 5{13 describesthestateofthecomputationalblocksasinputt1enterstheblocks.AtsamplinginstanttFRAME,wecanseeonlythecapacitanceofthecomputationalblockC1beingchargedbycurrentI1. 2.Asinputt2enterstheblocksatsamplinginstant2tFRAME, asshowninFigure 5{14 3.Asinputt3enterstheblocksatsamplinginstant3tFRAMEasshowninFigure 5{15 4.Atsamplinginstant4tFRAMEasframe4andinputt4enter, 5{16 5.Asframe4isabouttonishasshowninFigure 5{17 5{10 ,wechosethefollowingvaluesforthecurrentsources:I1=302nA,I2=400nA,I3=302nAandI4=1AwithC=5pFandVTH=2:5V(forasupplyvoltageof5V).TheweightsappliedtoinputsbecomeI1

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Figure5{13. StateoftheFIRlterasinputt1enters

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Figure5{14. StateoftheFIRlterasinputt2enters

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Figure5{15. StateoftheFIRlterasinputt3enters

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Figure5{16. StateoftheFIRlterasinputt4entersthesystemandwithframe4dischargingcomputationalblock1

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Figure5{17. StateoftheFIRlterbeforeframe5starts

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Theoutputofthecomputationalblockwaspreviouslyderivedas, Thegeneralexpressionforthisoutputcanbewrittenas, Takingz-transformofthisoutput,wewouldget SubstitutingtheweightsinEq. 5{16 weget, ThepolesandzerosofthisFIRlterareshowninFigure 5{18 .Thesamplingfrequencychosenforthesimulationsis100KHz.TheFIRlter'smagnituderesponseandphaseresponseareshowninFigures 5{19 and 5{20 respectively.Fromtheplots,weseethatthechoiceofcoecientsI1=60:4nA,I2=80nA,I3=60:4nAandI4=100nAhastunedtheFIRltertofunctionasalowpasslterwithacut-ofrequencyof10KHz,stop-bandattenuationof20dBandapassbandattenuationof1dB.Similarly,bychoosingdierentvalues(eitherpositiveornegative)wecancomeupwithhighpass,bandpassandnotchlters.ItisimportanttonotethatthearchitectureshowninFigure 5{10 canhandleonlypositivecurrents.Ifnegativecurrentsaretobehandled,thecircuitarchitecturewouldhavetobealtered.

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Figure5{18. Pole-zeroplotsoftheFIRlter Figure5{19: Time-modeFIRlter'smagnituderesponse(samplingfreq=100kHz)

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Figure5{20. Time-modeFIRlter'sphaseresponse TheFIRlter'sinputandoutputwaveformsinthetimedomainandfrequencydomainareshowninFigures 5{22 and 5{23 .Fromthetimedomainwaveform,weseethattheoutputwaveformisessentiallyadelayedversionoftheinputwaveform(aswouldbeexpectedfromalowpasslter)withthedelaybeingequalto2samples=20s.This2-sampledelayisalsoconrmedbythegroupdelayplotshowninFigure 5{21 wherethegroupdelayoftheFIRlterwasobtainedas2samples.Inthefreqdomain,weseethattheFIRlterattenuatestheinputsignal'senergyforfrequenciesabove10kHzby20dB. Figure 5{24 showstheCadencesimulationresultsfora3-taptime-modeFIRlter.Thevariousplotsshowninthegureare:Inputframetrain,Inputtimesteptrain,outputsofthefourcomputationalblocksandthenaloutputfromtheFIRlter.Wecanseefromthegurethatfort1=10s,t2=40s,t3=70s,fromsimulationswegettOUT=41:1s.Fromhandcalculations,weexpecttOUT=40:2s.Thesmalldierencebetweentheexpectedoutputtimeandtheexpectedoutputtimeshouldbeattributedtothedelayofthedigitalblocksprocessingtheinputs,delayofthecomparatorandtheleakagecurrents

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Figure5{21. Time-modeFIRlter'sgroupdelay Figure5{22. Time-modeFIRlter'sinputandoutputwaveforms(intimedomain)

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Figure5{23. EnergyofFIRlter'sinputandoutputsignals chargingthecapacitance.TheDCpowerconsumedbytheFIRlteris89:45W.Thespeedofoperationofthelteris25kHz.Thereisaninterestingtrade-obetweenspeedandinput/outputdynamicrangeintime-modeFIRlters.Asinformationisrepresentedintime,toaccommodateaveryhighdynamicrangeintheinputswemayhavetoincreasethedurationofaframe.Thisinturnmeansthatthesamplingfrequencyisreduced.Therefore,thespeedofoperationisreduced.This,weseethatthereisadirecttradeobetweenthespeedofoperationoftheFIRlteranditsinput/outputdynamicrange.

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Figure5{24. Cadencesimulationresultsforthetime-mode3-bitFIRlter

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Thereare4noisesourcesthatdominatethenoiseperformanceofthiscircuit. 1.ShotnoiseoftheDCcurrentsourceI1. 2.ShotnoiseoftheDCcurrentsourceI2. 3.ShotnoiseoftheDCcurrentsourceI3. 4.ShotnoiseoftheDCcurrentsourceI4. Thesenoisesourcesareuncorrelatedandthereforewecanconsidertheimpactofeachofthesenoisesourcesontheoutputofthecircuit.Also,aspreviouslydonefortheSNRanalysisoftheprototypeweightedaveragecircuitweneglectthenoisecontributedbythecomparatorandwealsoneglectthenoiseoftheresettransistors(astheircontributionstotheoutputnoisewouldbesmallercomparedtothenoisecontributionsoftheDCcurrentsources). I12).Therefore,thetotalcurrentfromthecurrentsourceisgivenbyI1+I1.SincecurrentsI1+I1,I2,I3arechargingthecapacitorandI4isdischargingthecapacitor,thenewoutputfromtheweightedaveragecircuitisgivenby,

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ThenoiseattheoutputtOUT1canbecalculatedasshownbelow: tOUT1=tOUT1tOUT=((I1+I1 Thevarianceofthisnoiseisgivenby tOUT12=( I12 I22),thetotalcurrentfromthecurrentsourceisgivenbyI2+I2.Thenewoutputfromtheweightedaveragecircuitforthiscaseisgivenby, ThenoiseattheoutputtOUT2canbecalculatedasshownbelow: tOUT2=tOUT2tOUT=((I1 Thevarianceofthisnoiseisgivenby tOUT22=( I22 I32).Therefore,thetotalcurrentfromthecurrentsourceisgivenbyI3+I3.Thevarianceofnoiseattheoutputcanbederivedbyfollowingsimilar

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stepsasintheabovetwocases.Thevarianceofthisnoiseisgivenby tOUT32=( I32 I42).Therefore,thetotalcurrentfromthecurrentsourceisgivenbyI4+I4.SincecurrentsI1,I2,I3chargethecapacitorandI4+I4dischargethecapacitor,thenewoutputfromtheweightedaveragecircuitisgivenby, ThenoiseattheoutputtOUT4canbecalculatedasshownbelow: tOUT4=tOUT4tOUT=(I1t1+I2t2+I3t3 (5{27) Thevarianceofthisnoiseisgivenby tOUT42=( I42 Therefore,thetotalnoiseattheoutputoftheaveragingblockisgivenby tOUT2= tOUT12+ tOUT22+ tOUT32+ tOUT42=( I12 I22 I32 I42

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AspreviouslymentionedinChapter2,theshotnoiseduetoacurrentsourceIisgivenby, I2=eI (5{30) whereisthetimeduringwhichthecurrentsourceisONandcontributestotheoutputandeisthechargeofanelectron. TheshotnoisesofcurrentsourcesI1toI4aregivenby, I12=eI1 I22=eI2 I32=eI3 I42=eI4 5{29 ,weget tOUT2=( I12 I22 I32 I42 Thesignal-to-noiseratioforthecomputationalblockandtheFIRlterisgivenby, (5{32) Theequationcanalsobewrittenas, 2e) (5{33)

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SubstitutingtOUT=40:1s,I4=200nAinEq. 5{31 ,wegettheoutputnoisevarianceas tOUT2=64:16as2andthermsnoiseattheoutputas8ns.FromEq. 5{32 ,wegetSNR64dB. Sincethedynamicrangeisgivenbytheratioofthemaximumoutput(andthemaximumtOUTisequaltothelengthoftheframe)totheminimumoutput(minimumtOUTgivenbythenoiseoor),weget Therefore,theDRoftheFIRlterisalsoequalto64dB. Assumingthatinputt1hasatimejittert1.Withthistimejitter,theoutputofthecomputationalblockwouldbecome, Therefore,thenoiseattheoutputisgivenby tOUT=tOUT1tOUT=((I1 Theoutputnoisevarianceisgivenby, tOUT2=I21 FortheweightchoseninoursimulationsI1 tOUT20:09 t12.Thus,weseethattheeectoftheinputjitterisnotpronouncedattheoutputwhenthe

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weightshaveamagnitudelessthan1.Ifthemagnitudeoftheweightismorethan1,theoutputjitterwouldbemorethantheinputjitter. 33 ]involvetheuseofInputBuers,TrackandHoldCircuits,UnityGainAmpliers,Multiplexers,LevelShiftersandMultipliersorDACs.Thearchitectureofthetime-modeFIRltersisverysimpleandwouldoccupysmallerareawhencomparedtotheseanalogFIRarchitectures.A3-tapFIRlterneedsonly4computationalblocks.Ingeneral,aNtaplterwouldrequireonlyN+1computationalblocks. 5{10 ).

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Wehaveexploredtwowaysofimplementingnon-lineararithmetic: 1.Implementingnon-lineararithmeticusingatime-modemulti-layerperceptron. 2.Implementingnon-lineararithmeticbyintroducinganon-linearityintheexistinglinearcomputationalblocks. 6.1.1Time-ModeMultiplication Theschematic,theinput/outputtimingsandthecapacitorvoltagewaveformofascalarmultiplicationcircuitareshowninFigure 6{1 .Let'sneglecttheoperationofthiscircuitduringframe1.Asshowninthegure,weseethattheinputt2isdenedwithrespecttoframe2(startingattimetF2.Theoutputofthecircuitisgivenby, ThisoutputtOUTisdenedwithrespecttoreferenceframe3(startingattimetF3).Duringframe1(startingattimetF1)ifwecanmakeI1alinearfunctionoft1,sayI1=kt1wherekisaconstant,then I2)t1t2(6{2) Thus,wecanachievethenon-linearmultiplicationfunctionusinglinearcomputationcircuits. 98

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Figure6{1. Scalarmultiplicationcircuit Thecomplete2-inputtime-modemultiplicationcircuitisshowninFigure 6{3 andtheinput/outputtimingdiagramsareshowninFigure 6{2 .AsshowninFigure 6{3 ,initiallythetwosignals-inputt1andreferenceframe1areXORedandthisXORoutputcontrolsthecurrentsourceIXchargingthecapacitorC1.Thus,thetimedierencebetweentF1(referenceframe1)andtheinputt1isconvertedtovoltageacrossthecapacitorC1whereVC1=IXt1

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Figure6{2. Timingdetailsofthe2-inputtime-modemultiplier Oncereferenceframe2starts,thetransmissiongateconnectedtothecapacitorC1isturnedON.Thetransconductanceampliernowproducesacurrentoutput, (6{3) ThisIOUTactsasthecurrentsourceI1inthescalarmultiplicationcircuitshowninFigure 6{1 .Therefore,theoutputfromthe2-inputtime-modemultiplicationcircuitisgivenby, (6{4)

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Eq. 6{4 showshowthe2-inputtime-modemultiplicationcircuitproducesthedesiredoutputt1t2scaledbytheexpressionI2C1 ToarriveattheexpressionshowninEq. 6{4 ,wehavemadethefollowingassumptions. Theaccuracyoftheoutputdependsonthelinearityofthetransconductanceamplier.Sincetheoutputisvalidonlyinthelinearrangeofthetransconductance,thedynamicrangeoftheinputt1supportedbythemultiplierdependsonthelinearityofthetransconductance.Therearemanywaystoimprovethelinearityofthetransconductanceandthosetechniquescanbeemployedinthiscircuittoimprovethedynamicrangeofinputs/outputssupported. Figure6{3. Schematicofthe2-inputtime-modemultiplier IfwecanmakeI2alinearfunctionoft1,sayI2=kt1wherekisaconstantandsubstituteitintheoutputofthescalarmultiplicationcircuittOUT=I1t2

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wouldget, Thus,wecanachievethenon-lineardivisionfunctionusinglinearcomputationcircuits. Figure6{4. Schematicofthe2-inputtime-modedivider Thecomplete2-inputtime-modedivisioncircuitisshowninFigure 6{4 andtheinput/outputtimingdiagramsareshowninFigure 6{2 .Asinthemultipliercircuit,theinputt1isconvertedtovoltageacrossthecapacitorC1whereVC1=IX1t1 (6{6) ThisIOUTactsasthecurrentsourceI2inthescalarmultiplicationcircuitshowninFigure 6{1 .Therefore,theoutputfromthe2-inputtime-modedivisioncircuitisgivenby, (6{7)

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Eq. 6{7 showshowthe2-inputtime-modedivisioncircuitproducesthedesiredoutputt2 Aninterestingcaseariseswhent1tF1isequaltozero.Whent1tF1isequaltozero,therewouldbenocurrentchargingC1.So,VC1doesnotchangeanditstaysatitsinitialvoltageVTH.Therefore,thetransconductanceamplierwouldnotproduceanycurrent,capacitorVC2willnotbedischargedandtherewon'tbeanyoutputfromthedivisioncircuit.Thiseectivelymeansthattheoutputfromthedivisioncircuitisveryhigh(maximumoutputfromthedivisioncircuitisequaltothelengthofaframebecauseweresetthewholecircuitattheendofeachframe). ToarriveattheexpressionshowninEq. 6{7 ,wehavemadethefollowingassumptions. 6{5 .Inthischapter,wewillrstprovideabriefintroductiontotheMLP,animportantclassofneuralnetworks.Wewillthendiscussatechniquetoimplementatime-modefeed-forwardMLP. 30 ].Theinput

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' Figure6{5. Feedforwardmulti-layerperceptron signalpropagatesthroughthenetworkinaforwarddirection,onalayer-to-layerbasis.Eachunitperformesaweightedsumonitsinputsandthenoutputsthesumthroughanon-linearactivationfunction.MLPshavebeenappliedsuccessfullytosolvemanydicultanddiverseproblems.Usuallytheyaretrainedinasupervisedmannerwiththeerrorback-propagationalgorithm.Thisalgorithmisbasedontheerror-correctionlearningrule.Assuch,itmaybeviewedasageneralizationoftheleast-mean-square(LMS)algorithm. Inaneuralnetwork,theneuronsareorganizedintheformoflayers.Figure 6{6 showsthesimplestexampleofamultilayerfeedforwardnetwork.Thisnetworkhasaninputlayerofsourcenodes,ahiddenlayerofneuronsandanoutputlayerofneurons.ThenetworkofFigure 6{6 isstrictlyafeedforwardtypenetworksincethereisnofeedbackofasignalfromtheoutputofanyoftheneuronstoitsinput.This2-inputMLPhas2sourcenodes,2hiddenneuronsand1outputneuron.Wewillimplementthis2-inputMLPusingtime-modecomputationalcircuitsandusethisneuralnetworktoimplementthenon-lineartimeoperation:multiplicationoftwotimesignals.

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Figure6{6. Fullyconnected2-inputfeedforwardMLPwithonehiddenlayerandoneoutputlayer Theneuronisfundamentaltotheoperationoftheneuralnetwork.TheneuronmodelshowninFigure 6{7 formsthebasisfordesigningariticialneuralnetworks.Therearethreebasicelementsoftheneuronalmodel: 1.Asetofsynapses,eachofwhichischaracterizedbyaweightorstrengthofitsown.Specicallyasignalxjattheinputofsynapsejconnectedtoneuronkismultipliedbythesynapticweightwkj. 2.Anadderforsummingtheinputsignals,weightedbytherespectivesynapsesoftheneuron. 3.Anactivationfunctionforlimitingtheamplitudeoftheoutputofaneuron. Figure6{7. Non-linearmodelofaneuron

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Inmathematicalterms,theneuroncanbedescribedbywritingthefollowingpairsofequations: and wherex1,x2,...,xmaretheinputsignals;wk1;wk2;:::;wkmarethesynapticweightsofneuronk;ukisthelinearcombineroutputduetotheinputsignals;bkisthebias;'(:)istheactivationfunction;andykistheoutputsignaloftheneuron.Assumingthatthebiasbkiszero,Eq. 6{9 becomes, 31 ].Forseveralyearspulse-streamtechniquehasbeenusedbyseveralresearchersforthehardwareimplementationofarticialneuralnetworks[ 32 ],whichleadstoverycomplexcircuits.AsshowninChapters2and3,thetime-modecircuitsareextremelysimpleandveryecientevenforcomplexcomputationssuchastheweightedaverage.Therefore,itwouldbeadvantageoustousetime-modecircuitsincomputationallyintensestructuressuchastheMLP. Wehavedevelopedatime-modefeedforwardmulti-layerperceptronwithonehiddenlayertoimplementacomplexnon-lineararithmeticoperation:multiplication.TrainingoftheweightsoftheMLPisdonebyusingrunningaerrorback-propagationalgorithminacomputerandthenapplyingtheresultantweightso-chipandprogrammingtheweightsoftheMLP.ToimplementtheMLPusingtime-modecircuits,wehavetorstimplementthenon-linearmodelofthe

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neuronusingtime-modecircuits.Thatis,wehavetorstimplementtheEqs. 6{8 and 6{9 ThecircuitshowninFigure 6{8 isverysimilarinoperationtothebasiccomputationalblockoftheFIRlterdiscussedpreviously.Thiscircuitperformsthefollowingcomputation: where,weightsI1 Therefore,thecircuitshowninFigure 6{8 canbeusedtoperformthecomputationmentionedinEq. 6{8 Theactivationfunctiondenotedby'(v),denestheoutputofaneuronintermsoftheinducedlocaleldv.Traditionally,threebasictypesofactivationfunctionshavebeenused:thethresholdfunction,thepiecewise-linearfunctionandthesigmoidfunction.Themostcommonlyusedformofnon-linearityisthesigmoidalnon-linearitydenedbythelogisticfunction: 1+exj(6{13) wherexjistheweightedsumofallsynapticinputsplusthebiasandyjistheoutputoftheneuron.Thepresenceofnon-linearitiesensuresthattheinput-outputrelationshipofthenetworkisnotthesameasthesingle-layerperceptron.Sincewehavebeensuccessfulinbuildinglineartime-modecomputationalcircuits,wechooseapiecewise-linearfunctionshowninFigure 6{9 toimplementthesigmoidfunction. Therefore,byconnectingthecircuitsinFigures 6{8 and 6{9 ,wecandesignanon-linearneuronshowninFigure 6{7 .ByconnectingmultipleneuronstogetherasshowninFigure 6{6 ,wecanimplementa2-layermulti-layerperceptron.

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Figure6{8. Time-modescalarmultiplicationandsummingcircuit

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Figure6{9. Time-modepiece-wiselinearactivationcircuit

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Thedesignedperceptronwastrainedusingbackpropagationalgorithmtoimplementthemultiplicationfunctiont1t2 6{9 TheMLPwastestedforawiderangeofinputs(rangingbetween1nsand200s).Thetestresultswereverypromising.WeobtainedalowMSEasshowninFigure 6{10 .Thedesiredoutputsandtheactualoutputsofthetime-modeMLPareshowninFigure 6{11 .Figure 6{12 showscadencesimulationresultsforaparticularcombinationoft1andt2.Wecaninferfromthegurethatthesimulationresultsdierbyapproximately3%fromthedesiredresults.Thisdierencecanbeattributedtomismatchbetweencurrentsourcesandthedelayofthecomparatorsusedinvariousneuroncircuits.

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Figure6{10. Variationofoutputmeansquareerrorwithepochs Figure6{11. Time-modeMLPdesiredandactualoutputs

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Figure6{12. Cadencesimulationresults

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Astechnologyscales,digitaltransistorsbecomefasterandfasterwhilevoltage-modeandcurrent-modeanalogdesignsbecomemorecomplex.However,theperformanceofthetime-modecircuitsactuallyimprovewithscalingtechnologies.Wehaveshownthattime-modecircuitsareexpectedtoperformwellinnewsilicontechnologiesandemergingcarbonnanotubetechnologies. Therearesomesimilaritiesbetweenthesetime-modecircuitsandsingle/dual-slopeADCsconverters.Theseconvertersalsochargeand/ordischargeacapacitorandoutputastepwiththeoutputvoltagereachesathreshold.However,theseconvertershavenotbeenusedforcomputation.AswasalreadypointedoutinChapter2,alargenumberofresearchershavestudiedpulse-basedcomputationbutthesecircuitshavebeenlimitedintheircomputationalpower. Thereisalsoastrikingsimilaritybetweenthestepfunctioncomputationsdescribedhereandsimplemodelsofspikingneurons.Ineachcase,digitaleventsfromotherneuronsareweightedandsummed,increasingtheneuroncellpotential. 113

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Whenthecellpotentialreachesaxedthreshold,adigitaleventoccursattheoutput.Localprocessingisanalogbutglobalcommunicationisasynchronousdigital.Themajordierencebetweenthearchitecturesisthatstepshavebeenusedherewhileneurons(andtheirmodels)usepulses.Thisdierencemaybesmallerthanitmayinitiallyappearsince,asMaasspointedout,ifthesynapticresponsefunctionisapproximatelylinearontheoutset,thenneuronscouldbeimplementingaweightedaveragecomputation[ 25 ]. Fromanengineeringperspective,astepinputcanprovideaguaranteethattheneuronwilleventuallyreduetoasingleinput(atleastfortheall-positive-weightcase).Pulsesarenotasstraightforwardtoprocessandmanytimesengineeringpulsecomputationboilsdowntojustdeterminingwhethersetsofpulsearrivesimultaneouslyornot.However,pulsebasedcomputationdoesn'trequireanexternalresetasdoesthestepbasedcomputationdescribedhere. CurrentlytheFIRlterdesignworksonlyforpositiveweights.Inthefuture,thisFIRlterdesignwillbeslightlymodiedtoworkforbothpositiveandnegativeweights;thatis,ensuretheFIRlterworksinallfourquadrants.Thisway,allpossiblelterscanbeimplementedusingtime-modecircuits.Also,thepowerconsumedbytheFIRlterhastobeoptimizedandcomparedtothepowerconsumedbyexistinglow-powervoltageandcurrentmodealternatives. Thetime-modeMLPisinitsveryearlystage.Moreworkisnecessarytooptimizeitsimplementationandfullycharacterizeitsperformance.

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Overall,time-modecircuitsprovideaveryappealingalternativetotraditionalvoltage-modeandcurrent-modecomputationalcircuits.Sincetime-modecomputationalcircuitshaveadvantageslikelowcomplexity,lowpowerconsumption,highSNRandDR,wewillcomeupwithmorecomputationalapplicationswheretheuseoftime-modecircuitswouldproveveryadvantageous.Furtherworkinscalingthesecircuitstodeepsubmicronsiliconandnanotechnologiesisnecessary.Ifamechanicalthresholdelement(orneuron)replacesthefunctionalityofthecapacitorandthecomparatorinthetime-modeweightedaveragecircuit,thecircuitimplementationwouldbegreatlysimpliedanditwouldopennewdoorstowardsintegratingNEMSandtime-modecomputationalcircuits.

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[1] P.HorowitzandW.Hill,TheArtofElectronics,CambridgeUniversityPress,NewYork,1989,SecondEdition. [2] D.A.JohnsandK.Martin,AnalogIntegratedCircuitDesign,JohnWileyandSons,Inc.,NewYork,1997. [3] C.ToumazouandD.G.HaighandF.J.Lidgey,AnalogueICDesign:TheCurrent-ModeApproach,PeterPeregrinusLtd,London,1993. [4] B.Gilbert,\TranslinearCircuits:AProposedClassication,"ElectronicsLetters,vol.11,no.1,pp.14{16,1975. [5] D.R.Frey,\Log-domainltering:Anapproachtocurrent-modeltering,"Inst.Elec.Eng.Proc.,vol.140,no.6,pp.406{416,Dec1993. [6] A.J.P.Theuwissen,Solid-StateImagingwithCharge-CoupledDevices,KluwerAcademicPublishers,NewYork,1995,FirstEdition. [7] H.Schmid,\WhyCurrentModeDoesNotGuaranteeGoodPerformance,"AnalogIntegratedCircuitsandSignalProcessing,vol.35,pp.79{90,2003. [8] W.Maass,\Fastsigmoidalnetworksviaspikingneurons,"NeuralComputa-tion,9:279{304,1997. [9] M.OulmaneandG.W.Roberts,\ACMOSTimeAmpliferforFemto-SecondResolutionTimingMeasurement,"IEEEInternationalSymposiumonCircuitsandSystemsCD,May2004. [10] K.PapathanasiouandA.Hamilton,\PulsebasedSignalProcessing:VLSIimplementationofaPalmoFilter,"IEEEInternationalSymposiumonCircuitsandSystems,vol.1,pp.270{273,May1996. [11] W.Maass,PulsedNeuralNetworks,Chapter3,MITPress,Cambridge,Massachusetts,1999. [12] R.SarpeshkarandM.O'Halloran,\ScalableHybridComputationwithSpikes,"NeuralComputation,vol.14,pp.2003{2038,Sep2002. [13] G.CauwenberghsandA.Yariv,\Fault-tolerantDynamicMulti-levelStorageinAnalogVLSI,"IEEETransactionsonCircuitsandSystems.PartII,vol.41,pp.827{829,1994. 116

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[14] X.QiandX.GuoandJ.G.Harris,\ATime-to-rstSpikeCMOSImager,"IEEEInternationalSymposiumonCircuitsandSystems,May2004. [15] H.S.NarulaandJ.G.Harris,\ATime-BasedVLSIPotentiostatforIonCurrentMeasurements,"IEEESensorsJournal,vol.6,no.2,pp.239{247,Apr2006. [16] F.N.H.Robinson,NoiseFluctuationsinElectronicDevicesandCircuits,ClarendonPress,Oxford,1974. [17] W.ZhaoandY.Cao,\NewgenerationofPredictiveTechnologyModelforsub-45nmdesignexploration,"7thIEEESymposiumonQualityElectronicDesign,pp.585{590,2006. [18] A.RaychowdhuryandS.MukhopadhyayandK.Roy,\ACircuitCompatibleModelofBallisticCarbonNanotubeFieldEectTransistors,"IEEETransactionsonComputerAidedDesign,vol.23,no.10,pp.1411{1420,Oct2004. [19] P.J.Burke,\ACPerformanceofNanoelectronics:TowardsaBallisticTHzNanotubeTransistor,"SolidStateElectronics,48(10),pp.1981{1986,2004. [20] M.ButtsandA.DeHon,andS.C.Goldstein,\Molecularelectronics:devices,systemsandtoolsforgigagate,gigabitchips,"Proc.IEEE/ACMIntl.ConferenceonComputerAidedDesign,pp.433{440,Nov2002. [21] J.VonNeumann,ProbabilisticLogics,AutomataStudies,PrincetonUniversityPress,Princeton,1956. [22] D.E.DickinsonandR.M.Walker,\ReliabilityImprovementbytheUseofMultiple-ElementSwitchingCircuits,"IBMJ.Res.Develop.,vol.2,no.2,April1958. [23] R.C.GonzalezandP.WintzDigitalImageProcessing,AddisonWesley,Reading,1987,SecondEdition. [24] X.Guo,\ATime-BasedAsynchronousReadoutCMOSImageSensor,"Ph.D.ThesisattheUniversityofFlorida,2002. [25] W.Maass,PulsedNeuralNetworks,Chapter2,Computingwithspikingneuwons,MITPress,Cambridge,Massachusetts,1999. [26] C.T.JinandP.L.RolandiandP.H.W.Leong,\Non-volatileprogrammablepulsecomputationcell,"ElectronicLetters,vol.35,pp.256{267,Issue:17,19,Aug1999. [27] D.Marr,Vision,W.H.FreemanandCompany,SanFrancisco,1982. [28] C.Mead,AnalogVLSIandNeuralSystems,Addison-Wesley,Reading,1989.

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[29] S.NorsworthyandI.PostandS.Fetterman,\A14-bit80-KHzSigma-DeltaA/Dconverter:Modelling,Design,andPerformanceEvaluation,"IEEEJ.ofSolidStateCircuits,vol.24,pp.256{267,1989. [30] S.Haykin,NeuralNetworks:AComprehensiveFoundation,PearsonEducation,UpperSaddleRiver,2ndedition,July1998. [31] G.CairnsandL.Tarassenko,\LearningwithanalogueVLSPMLPs,"MicroelectronicsforNeuralNetworksandFuzzySystems,pp.67{76,Sep1994. [32] J.N.TombsandL.TarassenkoandA.F.Murray,\NovelanalogueVLSIdesignformultilayernetworks,"IEEProceedingsofRadarandSignalProcessingF,vol.139,Issue6,pp.426{430,Dec1992. [33] X.WangandR.R.Spencer,\Alow-power170-MHzdiscrete-timeanalogFIRlter,"IEEEJournalofSolid-StateCircuits,vol.33,no.3,pp.417{426,Mar1998.

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VishnuRavinuthulanishedhisB.E.degreeinelectricalandelectronicsengineeringfromtheCollegeofEngineering,AnnaUniversity,Chennai,India,andhisM.S.degreeinElectricalEngineeringfromtheUniversityofFlorida,Gainesville,U.S.in2000and2003,respectively.HeiscurrentlydoingdoctoralresearchworkonBio-inspiredanalogcircuitsandnano-delaycircuitsattheComputationalNeuroEngineeringLaboratoryofUniversityofFloridaundertheguidanceofDr.JohnG.Harris.HedidasummerinternshipatNASAAmesResearchCenter,CaliforniawherehewasworkingwithDr.M.P.Anantram,Dr.T.R.GovindanandDr.HarryPartridgedoingresearchontheprosandconsofusingcarbonnanotubebasedtransistorsforanaloganddigitalapplications.HewillsoonbeworkinginTexasInstruments,Dallasasananalogdesignengineerdevelopingtheanalogcircuitsforhigh-speedSERDESapplications. 119