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Design and Characterization of Frequency Conversion Circuits for Wireless Applications

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Design and Characterization of Frequency Conversion Circuits for Wireless Applications
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VERMA, ASHOK KUMAR ( Author, Primary )
Copyright Date:
2008

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Diodes ( jstor )
Electric potential ( jstor )
Inductors ( jstor )
Microwaves ( jstor )
Oscillators ( jstor )
Power efficiency ( jstor )
Receivers ( jstor )
Signals ( jstor )
Transconductance ( jstor )
Transistors ( jstor )

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University of Florida
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University of Florida
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Copyright Ashok Kumar Verma. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
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5/31/2008
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496613318 ( OCLC )

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DESIGN AND CHARACTERI ZATION OF FREQUENCY CONVERSION CIRCUITS FOR WIRELESS APPLICATIONS By ASHOK KUMAR VERMA A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006

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Copyright 2006 by Ashok Kumar Verma

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iii ACKNOWLEDGMENTS I would like to express my d eepest gratitude to my advisor, Professor Jenshan Lin, for his guidance and encouragement throughout the course of this work. His constant support, patience, and encouragement have b een instrumental duri ng the course of my research. I would also like to thank th e members of my supervisory committee; Dr. Kenneth O, Dr. William R. Eisenstadt and Dr. Fan Ren for their guidance and interest in this work. I specially thank Mrs. Wenhsing Wu for her help with fabrication of test devices. I would like to thank Dr. Ren and S oohwan Jang for their help in providing me with GaN devices which I have used extensiv ely for my research. I would like to thank my colleagues (Yanming Xiao, Xiuge Ya ng, Tien Yu Chang, Sangwon Ko, Hypgoo Yeo, Jaeseok Kim, Jaeshin Kim, Lance Covert a nd Jerry Jun) for their companionship and technical discussions. I would lik e to thank Dr. Li Gao for he r help during the starting phase of my work in the field of RF circu it design. I would also like to thank Yu Su, Chikuang Yu, Changhua Cao, and Zhenbiao Li fo r their help in testing of my designs. Finally, I am deeply thankful to my pa rents for their love and support. Their constant encouragement and understanding enab led me to confront the many challenges of the past years of my graduate studies. I also thank my sister and brother for unconditional support. And last but not the least, I thank Nidhi Mohta for being my best friend.

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iv TABLE OF CONTENTS page ACKNOWLEDGMENTS.................................................................................................iii LIST OF TABLES............................................................................................................vii LIST OF FIGURES.........................................................................................................viii ABSTRACT.....................................................................................................................xiii CHAPTER 1 INTRODUCTION...................................................................................................1 1.1 CMOS Technology: High-Freque ncy Low-Power Applications................1 1.2 Gallium Nitride (GaN) Technol ogy: High-Power Applications..................4 1.3 Overview of the Dissertation.......................................................................5 2 DOUBLE-BALANCED GILBERTCELL UP-CONVERSION MIXER..............8 2.1 Introduction..................................................................................................8 2.2 Mixer Performance Characterization Parameters........................................9 2.2.1 Power Consumption.........................................................................9 2.2.2 Conversion Gain..............................................................................9 2.2.3 Gain Compression..........................................................................10 2.2.4 Third Order Intermodulation Distortion........................................11 2.2.5 Noise Figure...................................................................................12 2.2.6 Port Return Loss............................................................................14 2.2.7 Port-To-Port Isolation....................................................................14 2.3 Design Considerations: Gilbert-Cell Mixer...............................................15 2.3.1 Bias Point Optimization.................................................................17 2.3.2 Local Oscillator (LO) Tr ansistor Size Optimization.....................19 2.3.3 Input/Output Matching Networks..................................................20 2.4 Experimental Results.................................................................................22 2.5 Simulation and Measurement Discrepancy Analysis................................27 2.6 Conclusion.................................................................................................30 3 DOUBLE-BALANCED DUAL-GATE UP-CONVERSION MIXER.................32 3.1 Introduction................................................................................................32

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v 3.2 Design Considerations: Dual-Gate Mixer..................................................34 3.2.1 Bias Point Optimization.................................................................34 3.2.2 Local Oscillator (LO) Tr ansistor Size Optimization.....................36 3.2.3 Input/Output Matching Networks..................................................38 3.3 Experimental Results.................................................................................42 3.4 Conclusion.................................................................................................49 4 DOUBLE-BALANCED GILBERT-C ELL DOWN-CONVERSION MIXER.....50 4.1 Introduction................................................................................................50 4.2 Design Considerations: Broa d-Band Gilbert-Cell Mixer..........................50 4.2.1 Input Matching and Driver Stage...................................................50 4.2.2 Local Oscillator (LO) Tr ansistor Size Optimization.....................52 4.2.3 Output Matching Network.............................................................55 4.3 Experimental Results: Broad-Band Down-Conversion Mixer..................56 4.4 Experimental Results: Narro w-Band Down-Conversion Mixer................62 4.5 Conclusion.................................................................................................65 5 DOUBLE-BALANCeD PASSIVE RING MIXER...............................................67 5.1 Introduction................................................................................................67 5.2 Experimental Results: Down-Conversion Passive Mixer..........................70 5.3 Experimental Results: Up-Conversion Passive Mixer...............................72 5.4 Conclusion.................................................................................................74 6 BASE STATION RECEIVERS: DOWN-CONVERTER MODULE..................75 6.1 Introduction................................................................................................75 6.2 Base Station (BTS) R eceiver Specifications..............................................76 6.2.1 Digital Cellular Syst em (DCS1800) and Personal Communications System (P CS1900) Specifications.....................76 6.2.2 Universal Mobile Telecomm unications System (UMTS) Specifications.................................................................................77 6-3 Design Considerations and Experime ntal Results: Low Noise Amplifier (LNA) and Down-converter.......................................................................79 6.3.1 Low-Noise Amplifier.....................................................................80 6.3.2 Down-Converter............................................................................84 6.4 System Level Modeling and Simulations..................................................88 6.4.1 Heterodyne Receiver Performance................................................89 6.4.2 Homodyne Receiver Performance.................................................90 6.5 Conclusion.......................................................................................................91 7 LOW-PHASE NOISE HIGHPOWER OSCILLATOR.......................................92 7.1 Introduction................................................................................................92 7.2 Gallium Nitride (GaN) High Electr on Mobility Transistor (HEMT): Measurements and Modeling.....................................................................94 7-3 Design Considerations: Oscillator.............................................................96

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vi 7.4 Experimental Results.................................................................................98 7.5 Conclusion...............................................................................................103 8 HIGH-POWER RECTIFIER using gallium nitride diodes.................................105 8.1 Introduction..............................................................................................105 8.2 Properties and Principles of Be amed Microwave Power Transmission for Free Space Transmission....................................................................106 8.3 Wireless Power Transmission (WPT): System Configuration................110 8.4 Effect of Diode Parameters on RF-to-DC Conversion Efficiency...........113 8.5 Experimental Results: Gallium Nitride Ring Diodes...............................119 8.6 Experimental Results: Gallium Nitride HEMT Diodes...........................121 8.7 Conclusion...............................................................................................127 9 SUMMARY AND SUGGESTIONS FOR FUTURE WORK............................128 9.1 Summary..................................................................................................128 9.2 Suggestions for Future Work...................................................................131 LIST OF REFERENCES.................................................................................................132 BIOGRAPHICAL SKETCH...........................................................................................139

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vii LIST OF TABLES Table page 3-1 Performance summary of mixers operating in K-Band...........................................49 4-1 Measured performance summary of broad-band and narrow-band downconversion mixers....................................................................................................65 4-2 Performance summary of mixers operating in K-Band and above..........................66 6-1 Base station rece iver specifications..........................................................................79 6-2 Simulated receiver chain performance.....................................................................89 7-1 Comparison of different substrate materials............................................................93 7-2 Extracted Curtice-cubic model parameters..............................................................96 7-3 Performance summary of GaN oscillators.............................................................104 8-1 Input power level versus corresponding efficiency and RL values........................116 8-2 Input power level versus corresponding efficiency and V0 values........................118

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viii LIST OF FIGURES Figure page 1-1 A 24-GHz transmitter system.....................................................................................3 1-2 A 24-GHz super-heterodyne receiver system............................................................3 2-1 Gain compression in a non-linear device.................................................................10 2-2 Spectrum showing the corruption of de sired channel due to third-order intermodulation........................................................................................................11 2-3 Gain response of fundamental a nd third-order intermodulation product.................12 2-4 Single Side-band signa l translation to IF ( SSB ).......................................................13 2-5 Double Side-band signal translation to baseband ( DSB ).........................................14 2-6 Gilbert-cell mixer core.............................................................................................16 2-7 Up-conversion Gilbert-cell mixer with input and output matching networks.........16 2-8 Up-conversion Gilbert-cell mixer............................................................................22 2-9 Measurement setup for the differential mixer..........................................................23 2-10 Measured input return loss.......................................................................................23 2-11 Measured output return loss.....................................................................................24 2-12 Measured conversion-gain versus IF........................................................................25 2-13 Measured conversion-gain versus RF......................................................................25 2-14 Measured conversion-gain versus current consumption..........................................26 2-15 Measured 1-dB compression response.....................................................................26 2-16 Simulated and measured output return loss..............................................................27 2-17 Simulated and measured conversion-gain versus IF................................................28

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ix 2-18 Corrected model for MOS device............................................................................30 3-1 Double-balanced dual-gate up-conversi on mixer with input and output matching networks...................................................................................................................33 3-2 Dual-gate device usi ng cascode structure................................................................34 3-3 Time varying transconductance of lower transistor.................................................35 3-4 Simulated available LO voltage le vel versus LO transistor width...........................37 3-5 Simulated conversion-gain and input P1dB versus LO transistor width....................37 3-6 Simplified schematic of output matching network..................................................40 3-7 Dual-gate up-conversion mixer................................................................................41 3-8 Isolation between LO-to-RF and LO-to-IF ports.....................................................42 3-9 Measured input return loss.......................................................................................43 3-10 Measured output return loss.....................................................................................43 3-11 Measured conversion-gain versus IF........................................................................44 3-12 Measured conversion-gain versus RF......................................................................45 3-13 Measurement setup to determine third-order intermodulation (IIP3)......................45 3-14 Measured output P1dB and OIP3 versus IF...............................................................47 3-15 Measured output P1dB and OIP3 versus RF..............................................................47 3-16 Measured output P1dB and OIP3 versus LO power..................................................48 3-17 Measured output P1dB and OIP3 versus current consumption..................................48 4-1 Down-conversion Gilbert-cell mixer w ith input and output matching networks.....51 4-2 Simulated noise figure ve rsus LO transistor size.....................................................53 4-3 Local Oscillator (LO) waveform with different amplitudes to show the time when both transistors of a switch pair are ON.........................................................54 4-4 Simulated noise figure versus LO power.................................................................54 4-5 Simulated noise figure versus frequency.................................................................55 4-6 Down-conversion Gilbert-cell mixer (broad-band)..................................................56

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x 4-7 Measured input return loss.......................................................................................57 4-8 Measured conversion-gain versus RF......................................................................58 4-9 Measured output return loss.....................................................................................58 4-10 Measured conversion-gain versus IF........................................................................59 4-11 Measured input P1dB and IIP3 response....................................................................60 4-12 Noise figure measurement setup..............................................................................60 4-13 Measured noise figure versus LO power..................................................................61 4-14 Measured noise figure versus frequency at different LO power..............................62 4-15 Down-conversion Gilbert-cell mixer (narrow-band)...............................................63 4-16 Measured input and output return loss.....................................................................64 4-17 Measured conversion-gain versus current consumption..........................................64 5-1 Passive CMOS ring mixer........................................................................................67 5-2 Simulated return loss at input and output ports........................................................69 5-3 Passive CMOS mixer die-photo...............................................................................70 5-4 Measured conversion-gain versus LO powerDown-conversion passive mixer.....71 5-5 Measured conversion-gain versus RF powerDown-conversion passive mixer.....71 5-6 Measured IIP3 response...........................................................................................72 5-7 Measured conversion-gain versus LO powerUp-conversion passive mixer..........73 5-8 Measured conversion-gain versus RF powerUp-conversion passive mixer..........73 6-1 Broad-band low-noise amplifier...............................................................................81 6-2 Low-noise amplifier die-photo.................................................................................81 6-3 Measured LNA S-parameters...................................................................................82 6-4 Measured noise figure versus frequency..................................................................83 6-5 Measured input P1dB and IIP3 versus frequency......................................................83 6-6 Down-converter (passive mixer, LO buffer and IF buffer)......................................84

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xi 6-7 Down-converter module die-photo..........................................................................85 6-8 Measured return loss at IF port................................................................................86 6-9 Measured return loss at RF and LO ports................................................................86 6-10 Measured conversion ga in versus frequency...........................................................87 6-11 Measured input P1dB, IIP3 and IIP2 versus frequency.............................................87 6-12 Heterodyne receiver architecture.............................................................................89 6-13 Homodyne (direct-conversi on) receiver architecture...............................................90 7-1 Gallium Nitride HEMT............................................................................................94 7-2 Measured and modeled S-parameter performance...................................................95 7-3 Measured and modeled DC I-V performance..........................................................95 7-4 Negative impedance oscillat or circuit (Oscillator I)..............................................97 7-5 Fabricated oscillator ci rcuit board (Osc illator I)....................................................97 7-6 Feedback oscillator circuit (Oscil lator-II)................................................................98 7-7 Fabricated oscillator ci rcuit board (O scillator-II)....................................................98 7-8 Measured output spectrum of oscillator-I..............................................................100 7-9 Measured output spectrum of oscillator-II.............................................................100 7-10 Frequency and output power versus gate bias voltage (Oscillator-I).....................101 7-11 Frequency and output power versus gate bias voltage (Oscillator-II)....................101 7-12 Measured DC-to-RF conversion effi ciency versus gate bias voltage....................102 7-13 Measured phase noise versus offset frequency (Oscillator-I)................................102 7-14 Measured phase noise versus offset frequency (Oscillator-II)...............................103 8-1 Collection efficiency between receiver and transmitter apertures as a function of Goubau’s parameter...............................................................................................107 8-2 Simplified wireless power transmission system.....................................................111 8-3 Equivalent representation of Schottky barrier diode..............................................113 8-4 Efficiency versus load resistance...........................................................................115

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xii 8-5 Efficiency versus input power level.......................................................................115 8-6 Efficiency versus DC output voltage level.............................................................117 8-7 Efficiency versus input power level.......................................................................117 8-8 Gallium Nitride ring diode device..........................................................................119 8-9 Forward DC-IV characteristics of GaN ring diode................................................120 8-10 Measured RF-to-DC conversion efficien cy and DC output voltage versus input power......................................................................................................................120 8-11 Gallium Nitride HEMT device...............................................................................121 8-12 Forward DC-IV characteristics of HEMT diode....................................................122 8-13 Voltage-doubler rectifier circuit.............................................................................122 8-14 Fabricated circuit boa rd on FR-4 substrate............................................................123 8-15 Measured RF-to-DC conversion efficiency and DC output voltage versus input power (Rload=1-k )..............................................................................................124 8-16 Measured RF-to-DC conversion efficien cy and DC output voltage versus input power (Rload=5.4-k )...........................................................................................125 8-17 Measured RF-to-DC conversion efficiency versus frequency for different values of load resistance....................................................................................................125 8-18 Measured RF-to-DC conversion efficiency versus frequency for different values of load resistance....................................................................................................126

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xiii Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy DESIGN AND CHARACTERI ZATION OF FREQUENCY CONVERSION CIRCUITS FOR WIRELESS APPLICATIONS By Ashok Kumar Verma May 2006 Chair: Jenshan Lin Major Department: Electrical and Computer Engineering The demand for wireless applications has gr own at a tremendous rate over the past few years. With the development of sub-micron complementary metal oxide semiconductor (CMOS) technologies, it has become possible to implement radio frequency (RF-CMOS) circuits in low cost CMOS technology at hi gher frequencies. The use of CMOS for design of RF circuits enable s the design of a true single chip radio with the RF and baseband circuits put together on the same substrate. Also, with the increase in frequencies the antenna size becomes smaller and hence the use of an on-chip antenna becomes feasible making the radio a true single chip transceiver. This dissertation presents the desi gn, implementation and experimental performance of up and down-conversion mixe rs operating at fre quencies above 20-GHz, built in 130nm logic CMOS process. Tw o up-conversion and two down-conversion active mixers were designed. The up-conversion dual-gate mixer exhib its very linear and broad-band performance at low power levels and is suitable for applications in the 22-29

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xiv GHz ultra wide-band range. The down-convers ion mixers achieved excellent noise figure and broad-band response while maintaining very low power consumption. Tradeoffs between power consumption and the frequency response were demonstrated by the design of a narrow-band and a wide-band dow n-conversion mixer. It was observed that the narrow-band circuit exhibited similar performance at almost half the power consumption of the broad-band design. The LNA and Down-converter module can meet the requirements of Digital Cellular Systems (DCS1800), Personal Communications System (PCS1900) and Universal Mobile and Telecommunications System (UMTS) standards in a heterodyne as well as homodyne architecture, which demonstrate the use of CMOS in applications usually dominated by Gallium Arsenide (GaA s) devices. The ease of operation and ubiquitous natu re of wireless communication led to the idea of wireless transfer of actual power as well. Wireless pow er transmission system s operate at higher power levels, which necessita te the use of technologies like Gallium Nitride (GaN) suitable for high power handling capabilities. In this work, the design and measurement of a high-power high-voltage ra dio-frequency to direct-curre nt (RF-to-DC) GaN rectifier circuit are presented which is an essentia l module of a wireless power transmission (WPT) system. Using high power devices can be a key to reduce the size of overall WPT system.

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1 CHAPTER 1 INTRODUCTION 1.1 CMOS Technology: High-Freque ncy Low-Power Applications Wireless technologies have evolved expone ntially over the past few decades. Commercial application driven demands have ma de the research in the field of wireless products very competitive. Everything from hand-held devices to widely spread sensors now rely on wireless technology for their ope ration. For typical radio frequency (RF) applications at the beginning of the wireless era, SiGe used to be the technology of choice because of its excellent performance at high frequencies [1]-[5]. Previously, baseband circuits in transceiver systems used to be implemented in complementary metal oxide semiconductor (CMOS) technology and the RF section was mainly done in other technologies. With the ever increasing demand to build a true single chip radio with both RF and Digital circuitry has drawn a lot of attention in the field of CMOS RF circuit design. Over the past decade extensive re search has been done on RF-CMOS circuits mainly for commercial applications in the frequency range of 900MHz (GSM) 2.45 GHz and 5.8 GHz (WLAN). True CMOS transmitters and receivers have evolved that achieve comparable performance to their SiGe counter parts. The process of putting all the basic blocks needed for a transcei ver has brought down the cost rapidly. With the increasing crowding of frequencies in the lower freque ncy bands due to increase both in the number of applications and users has led researcher s to shift to higher frequencies where the available frequency spectrum is not as crowde d yet. Again for a long time at such higher frequencies hetero-junction bipolar (HBT) t echnologies dominated the RF design area

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2 because of their superior performance at higher frequencies. Technology scaling in CMOS has made it possible to achieve very high cut-off freque ncies and CMOS is starting to gain popularity as th e technology of choice for RF ci rcuits at such frequencies or higher. The driving force for this evoluti on is the reduction in cost associated with CMOS technology. RF-CMOS circuits operating in the 22-29GHz ultra wide-band range are becoming possible [6]-[9]. Such circuits ca n be used in radars, wireless local area networks; local multipoint distribution services (LMDS) and other ISM band applications. Single chip transceiver concept requires th e RF building blocks to be put on the substrate which is primarily optimized for di gital needs. A primary challenge encountered by RF circuit designers using the digital proce ss is the need to deve lop suitable accurate models of active devices and passive compone nts for use in RF circuit design. Digital design is always done using a spec ific set of rules. The main tradeoffs in digital circuits are between speed and power consumption, whereas design of RF circuits involves tradeoff among several factors like linearit y, gain, noise, speed, power dissipation etc. Lack of accurate modeling for analog co mponents in such technology has made it difficult to optimize the design without requirin g several iterations. RF circuits usually lag behind to utilize the full potential in terms of speed offered by a scaled digital technology. Also with continued scaling, the supply voltage requirement for deep submicron devices has become very low, of the order of about 1.0-V [10]. This supply voltage limitation makes it even harder to achieve good linearity performance desirable for successful operation of RF circuits.

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3 Most part of this dissertation is devo ted to design of CMOS high frequency low power mixers built in Digital CMOS process. The mixers described in this work were built as individual components to evaluate their use in a fully integrated CMOS transmitter and superheterodyne receiver sy stem-with operating frequency of 24-GHz. The schematic of the transmitter and receiver utilizing the designed mixer blocks are shown in Figure 1-1 and Figure 1-2. Figure 1-1. A 24-GHz transmitter system Figure 1-2. A 24-GHz super-het erodyne receiver system The primary goal of the system is to minimize the power consumption; hence the main design focus was to reduce the current c onsumption of individual blocks as much as possible. The up-conversion mixers in differe nt architectures were designed for the transmitter. Two down-conversion mixers to be used after the LNA to convert the RF signal to first IF frequency were designed. Finally passive mixer block was designed to convert the first IF signal down to baseband.

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4 While low cost CMOS technologies ha ve already achieved high levels of integration in hand-set receivers. The challenge to use CMOS circuits for base station applications still remains a challenge a nd is still dominated by GaAs and SiGe technologies. Implementation of base-stati on silicon chipset in CMOS technology has also been addressed, which proves the usef ulness of CMOS for base-station as well receiver front end design. 1.2 Gallium Nitride (GaN) Technology: High-Power Applications The RF/microwave technologies also bring to fore their applicability to Wireless Power Transmission (WPT). In order to fully exploit the benefits of “Wireless” it is imperative that the wireless communication systems are endowed with on-board energy harvesting devices to power themselves. One ty pe of energy harvesti ng device is the RFto-DC rectifying antenna that converts RF energy to DC power. Such a capability would lead to elimination of exhaus tible battery power supplies that are cu rrently being used. This essentially requires designi ng rectification circuits that can efficiently generate DC power at high frequencies of operation. Hist orically, WPT draws a ttention from energy industry as an innovative way to deliver el ectricity. Today, a wide spectrum of problems can be addressed using WPT. Spatially separa ted intractable sensors can now be powered wirelessly, thereby eliminating the n eed for human maintenance, which was indispensable previously due to the necessity for timely repl enishments of portable power sources. It also finds usage in a number of military applications where power could be transmitted to sensors located in hostile locations. Even though CMOS is the technolo gy of choice for design of wireless communication systems for low power applica tions, it is not suitable for use in high-

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5 power rectification and other applications. This is due to the lower power handling capability of CMOS technology. On the other hand, new wide-bandgap device technologies like Gallium Nitride (GaN) have shown to achieve very high breakdown voltage which makes them a viable option in the design of high power rectifier circuits. For instance, in space applica tions between a base-station a nd a receiver where very high power levels can be transmitted and cost is not a major issue, technologies like GaN emerges as a good alternative. Oscillators us ing GaN high electron m obility transistors (HEMT) can achieve high power levels even at higher frequency le vels. CMOS devices with very large device size might be used but the frequency response degrades as compared to GaN devices with similar power handling capability. Design of high performance oscillators using GaN HEMT de vices is addressed. GaN HEMT diodes have been used to achieve (Radio Frequency-to -Direct Current) RF-to-DC rectification at power levels of around 30 dBm a nd have shown to achieve even better performance with further increase in power levels. 1.3 Overview of the Dissertation This Ph.D. work mainly focuses on the desi gn of frequency converter devices to be used in a 24 GHz transmitter and receiver system. CMOS design has been the primary focus for low power designs and use of GaN devices has also been evaluated for high power applications. Low power, high freque ncy CMOS mixer have been designed in 130-nm CMOS technology and serves as impor tant building blocks of an ultra small sized transceiver chip which is pr ojected to occupy an area of 1.5 mm2. An overview of performance metrics of mixers such as noise figure, linearity, conversion gain, isolation, power c onsumption has been described in Chapter 2. It also describes the design and the measured resu lts of a double-balanced Gilbert-cell up-

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6 converter which operates in K-Band convert ing signals from 2-3 GHz to K-Band. The mixer was built in Digital Logic process whic h was not optimized for RF applications. Due to this the measured performance showed considerable deviations from simulated results. Discrepancy analysis to determin e the cause of such deviations has been addressed. Chapter 3 describes the design and measured performance results of a dualgate up-conversion mixer. The design was fo cused to achieve broad-band performance while keeping the power consumption low as was the case in Gilbert-cell design. The design achieves a 3-dB conversion gain bandwidth of 10-GHz at the output port and 2GHz at the input port. Chapter 4 describes the design of two down-conversion mixer modules both implemented in double-balanced Gilbert-cell archite cture. The designs differ from each other in the choice of devi ce size and matching network. Very low noise figure performance has been achieved. The narrow-band mixer achieves similar performance as the broad-band design while consuming just half the power required for the broad-band mixer thereby verifying th e tradeoff between power consumption and bandwidth response. Chapter 5 describes the measured performance of a CMOS passive ring mixer to be used at the receiver end af ter the first active mixer (Figure 1-2) to convert the signal from 2.7GHz down to baseband. Matchi ng network was not used so the design can reversibly be used to conve rt signals from baseband frequencies up to higher frequencies and vice versa. The meas ured results for both cases have been presented. Chapter 6 describes the design and measur ed performance of an LNA+downconverter fabricated in 0.25-m CMOS pro cess. Both LNA and mixer achieves broadband and linear performance which makes th em suitable for use in DCS1800, PCS1900 and UMTS bands in superheterodyne as we ll as direct conversion architecture. Chapter 7

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7 describes the measurements and modeling of high power GaN HEMT devices. High power oscillator circuit have been designe d which can achieve output power level of 21.5-dBm at 1.8-GHz and a phase noise of -127 dBc at 1-MHz offset. Chapter 8 describes the design of an RF-to-DC rect ifier circuit for high power wireless power transmission applications, implemented usi ng GaN diode. Design equations for choice of a suitable Schottky diode to be used at give n power level and frequency of operations are discussed. Lastly a summary of the work and suggestions for future work are listed in Chapter 9.

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8 CHAPTER 2 DOUBLE-BALANCED GILBERTCELL UP-CONVERSION MIXER 2.1 Introduction Mixers are frequency translat ion devices which provide either the sum or difference of two frequencies as required by the transmitte r or the receiver, respectively. In contrast with other frequency translation devices like dividers and multipliers, the modulation properties of the signals are preserved when it goes through a frequency translation in a mixer. Any device with non-linear characteristics can be used for mixing of two signals but it is difficult to achieve the desired performance like a mixer. Mixers should have high linearity, low noise and adequate freque ncy response based on the desired frequency range. Mixers can be broadly classified in two categories, passive and active. These topologies have their own design trade-o ffs. Choice of a passive or active topology primarily depends on the system specifications for power consumption, linearity and noise. Mixers are typically implemented in CMOS, Si-bipolar (Si BJT) and GaAs MESFETs. These choices offer tradeoffs betw een performance and cost and should be taken into consideration for desired mixer performance. In a transmitter and receiver chain, the overall performance depends on the performance of the individual blocks. Typical RF parameters that are used to characterize a transceiver performance are gain, nois e figure, gain compression, third order nonlinearity and power consum ption [11]-[13]. Section 2.2 describes the performance metrics of a mixer block which in turn aff ects the performance of the whole system.

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9 2.2 Mixer Performance Characterization Parameters 2.2.1 Power Consumption For wireless applications that run off ba tteries it is required to keep the power consumption low. Power optimization of a mixer should be done in a way as to not increase the power consumpti on of other building blocks li ke low noise amplifier (LNA) and voltage controlled oscillat or (VCO) and thereby increasing the overall system power budget. For example, if the noise figure of a mixer is high, gain requirement for the LNA increases, which in turn increases the power co nsumption of the LNA. Also if the gain of LNA is high then the linearity requirement of the down-convert er needs to be increased to meet the system linearity specifications, which in turn increases the power consumption of the mixer. Mixers should be operable with lower local oscillator (LO) power level. If the re quired LO power level is high, pow er consumption of the LO output buffer increases. So the power consump tion optimization for a mixer should be considered from overall system perspec tive thereby minimizing overall power budget. 2.2.2 Conversion Gain Mixer stages are required to have some amount of signal amplification. In a heterodyne receiver chain the downconversion mi xer is followed by IF filters which have high losses associated with them. The downc onversion mixer should provide some gain to compensate for the loss of IF stage ther eby reducing the noise co ntribution due to the IF stages. However, gain should not be very large as mixer output can get saturated due to the presence of a strong signal. Gilbert-cel l topology is a highly favored architecture in CMOS technology for mixer design because of the conversion gain associated with it. Though its performance is not as broad as pa ssive mixers, it can operate with low LO power levels. This is primarily important in low supply voltage technologies where it is

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10 difficult to generate high LO drives especia lly at high frequencies. Conversion gain for mixer is specified as power gain in the designs presented in this work. 2.2.3 Gain Compression Gain compression for a mixer is specifie d in terms of 1-dB compression point which is defined as the power level where th e power gain is reduced by 1-dB compared to the linear gain response of the mixer for smaller power levels. Figure 2-1 shows the gain response of the mixer as a function of input power level demonstrating the 1-dB compression point. Voltage supply limitations and presence of non-linearities in mixer causes gain compression when the input signal magnitude is high. Figure 2-1. Gain compressi on in a non-linear device Behavior of gain compression is differe nt when it is caused by circuit nonlinearities and voltage suppl y limiting. In modern CMOS technologies where voltage supply headroom is of the order of 1 V, this effect has become more severe. Gain usually drops more gradually when the main cause of compression is circui t non-linearity rather than supply voltage limiting. When input signal power level ex ceeds 1-dB compression point, signal at the output port gets distorted. This distortion further can cause amplitude

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11 modulation to phase modulation conversion. Due to phase modulation of the desired signal, the detection accuracy is reduced, whic h in turn increases the bit error rate and deteriorates system performance. A high 1-dB compression point is desired for a mixer as large undesired blocker signals may be present at the input of the mixer. Overloading of the mixer occurs in such cases, which lead s to reduction of conversion gain for the desired signal, which is undesira ble as it can lead to an incr ease in the noise contribution of IF stages on the system noise figure. 2.2.4 Third Order Interm odulation Distortion Circuit non-linearitie s can produce undesirable in termodulation products at different frequencies at the output of the mixer along with the desired sum/difference frequency. In heterodyne receiver archite cture third order in termodulation is the dominant non-linearity, which cau ses unwanted signals to fall in the desired signal band. Due to the odd-order nonlineari ties in the transfer function of the mixer, the presence of two undesired signals in the adjacent channel give rise to third-order intermodulation (IM3) products at the output of the mixer. Figure 2-2. Spectrum showing the corruption of desired channel due to third-order intermodulation

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12 If two adjacent channel frequencies are f1 and f2, two IM3 products are generated at frequencies of 2f1-f2 and 2f2-f1. As shown in Figure 2-2, one of the IM3 products can corrupt the desired signal if it falls within th e desired channel. As power levels increase, other higher order non-linearitie s start to become important. Power of fundamental signal increases linearly and power of third harmonic increases as the cube of the input signal power. The desired fundamental output si gnal and IM3 product can be linearly extrapolated and the point of intersection of the two curves gives the IIP3, which is shown in Figure 2-3. Figure 2-3. Gain response of fundamental and third-order intermodulation product 2.2.5 Noise Figure Noise figure is an important figure of merit used in receiver systems to specify the noise performance of the circu it. Input signal to noise ratio divided by the output signal to noise ratio is referred to as noise factor. It can be expressed as, in in out outS N F S N (2.1)

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13 and the noise figure is defined as, 10log() NFF (2.2) where Sin and Nin are the signal and noise power levels at input and Sout and Nout are signal and noise power levels av ailable at the output. Noise figure is always referred to some source impedance which is generally 50 in RF systems. When used in a receiver chain, a low value of noise figure for the mixe r is needed to relax the gain requirements of the LNA. In mixers, noise in the RF and image band mixes with the LO and gets translated to IF. Two kinds of noise figures can be defined for a mixer, Double Side Band (DSB) and Single Side Band (SSB). For hetero dyne architecture, si ngle side band noise figure should be measured. It is called singl e side band because only one of the side bands (RF band) of LO is converted to IF a nd the other band (Image band) is rejected by the image reject filter, as is shown in Figure 2.4. In the case of homodyne architectures, double side band noise figures ar e defined. Here the RF signal is directly converted to baseband. As evident from Figure 2-5, it is called double band as signal side lobes from both sides of LO are converted to baseband. For single side band the noise contributors are twice as many as compared to double si de band. The noise power is normally 3 dB higher than the corresponding double side band measurement. Figure 2-4. Single Side-band signal translation to IF ( SSB )

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14 Figure 2-5. Double Side-band si gnal translation to baseband ( DSB ) 2.2.6 Port Return Loss For optimum power transfer from the input port to the output port the impedances should be matched. If the input port impedance is not matched to source impedance, part of the incident power gets reflected back. Ra tio of this reflected power to the incident power is defined as return loss at that port. Typically the RF and LO port impedances are matched to 50 , whereas IF impedance is most often matched to IF filter. RF impedance matching helps to avoid signal loss due to refl ection and also reduces passband ripple for filter inputs. Impedance matching at LO port can be a little relaxed and return loss degrades. In such cases high LO drive might be needed for optimum performance, which in turn leads to higher power consumption fo r the overall receiver. Also, if excessive amount of LO signal is reflected back it may gi ve rise to LO-pulling. A typical figure of merit for return loss is -10 dB. 2.2.7 Port-To-Port Isolation Good isolation between the mixer ports is imperative for nominal operation of the receiver. Otherwise, signal corruption due to unwanted leakage from other signals becomes an issue. High amount of LO to RF isolation is generally desired because the two frequencies are usually close to each other. In a transmitter system, if a large amount of LO signal appears at the RF port it mi ght start to leak from the antenna causing

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15 potential corruption of the desired signal of the neighboring systems. Good amount of LO-IF and RF-IF isolations ar e also desired though they ar e not as critical as LO-RF isolation. If large amount of LO or RF signals appear at IF port then the large signal response might be degraded leading to a lower value of 1-dB compression (P1dB) for the mixer. 2.3 Design Considerations: Gilbert-Cell Mixer Gilbert Cell is a four quadrant linear mu ltiplier. It is the most commonly used topology for double balanced mixers in m onolithic systems [14]-[15]. It provides reasonable conversion gain, good rejection at RF and LO ports and reasonable noise figure. Double-balanced structure means if either the LO or RF signal is zero, then output is always zero. Double-balan ced topology has inherent a dvantage of high port-to-port isolation because of symmetry in its architectu re. This configuration can be modified to a single balanced configuration using a co mmon source transconductance stage and a switching pair. The single balanced topology suffers from high LO port to RF port feedthrough as compared to the double balanced structure. It has lo wer noise figure than the double-balanced architecture because of less number of no ise generating sources. The basic design procedure is similar for both t opologies. Double balanced structure offers the flexibility to be driven by single ended i nput and LO signals. In such cases the other side of the transconductance pair or the switching quad is ac-g rounded. Gilbert-cell topology is shown in Figure 2-6. It includes a tail current source (M7), a differential transconductance stage (M1, M2 ), and a switching quad (M3-M6). The output can be driven to a resistive or reactive tuned load. Mixer schematic can primarily be divided into three stages, the driver stage, switching stage and load stage. The driver stage is required

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16 to amplify the input signals in order to compensate for the attenuation caused by the switching stage. It also helps to reduce the noise contribution due to the switching stage. Figure 2-6. Gilbert-cell mixer core In low voltage designs the tail current source used for biasing can be replaced with an inductor. It helps to increase the available voltage s upply headroom for active devices. The simulation models for the design were from 130 nm Digital CMOS Logic process. The technology offers eight layers of coppe r metallization. Input and output matching networks for the Gilbert-cell mixer are shown in Figure 2-7. Figure 2-7. Up-conversion Gilbert-cell mixer with input and output matching networks

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17 2.3.1 Bias Point Optimization Optimization process starts from dc-analysis. The circuits were designed to achieve broad-band performance while keeping the power consumption as low as possible. Optimum performance requires act ive devices to be biased at appropriate dc-quiescent points. Degenerated transconducta nce stage (lower stage) pair (M1, M2) is biased at a fixed operating point in satura tion region. Saturation region o ffers largest conversion gain and the current also becomes less susceptible to voltage variations across the transistors [12]. With the assumption of long channe l approximation, the transconductance (gm) of a transistor operating in sa turation region is given by, ()mnoxGSTHW gCVV L (2-3) Conversion gain of mixer is directly pr oportional to the transconductance of the lower transistors. Gain improvement can al so be achieved by keeping L constant and increasing W. Since transconductance is direc tly proportional to bias current (Equation 24), 2 ()D m g sthI g VV (2-4) Increasing the bias current also helps to improve conversion gain. Also source degeneration can be reduced to boost the gain of the circuit at the expense of some drop in linearity. Gate overdrive voltage (VGS-VT) can be used to control the linearity of the circuit. Switching pairs M3-M4 and M5-M6 are biased in saturation region and then driven with a LO drive to establish paired on-off switching. In pres ence of LO signal one of the branches conduct at a time. When VLO is high enough, current through one switch becomes saturated and other switch is closed. In presence of degeneration VLO required for proper switching is larger compar ed to the non-de generated case. VLO also increases

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18 with increase in over-drive voltage levels. Bi as points for the LO-transistors should be chosen so as to provide enough voltage head room at the output which is required to prevent higher input signals from clipping. Increasing the current also helps to improve conversion gain. Also source de generation can be reduced to boost the gain of the circuit at the expense of some drop in lin earity. If resistive degeneration (Rs) is used with a load resistance of (RL) the transconductance of the degenerated driver stage (Gm) becomes, 1m m msg G g R (2-5) The driver stage converts the i nput voltage signal to current signal which then mixes with the switching LO signal (which can be repr esented as a Fourier Series) to give the resulting IF stage output current, which can be approximated as 44 xcos()xcoscos3..... 3omIFIFLOLOIGVtwtwt (2-6) where, I0 is the output current, VIF is the amplitude of RF signal and Gm is the transconductance of the dege nerated driver stage and IF and LO are the IF and LO frequencies, respectively. LO switching has been assumed to be perfect for this case i.e. LO signal is assumed to be a perfect squa re wave. For an up-conversion mixer the sum term is required and the difference term can be filtered out at the output. Assuming the load impedance to be RL at output node the conversion gain becomes, 2vmLAGR (2-7) The gain expression is valid only for LO amplitudes greater than Vgs-Vth of the switching pair devices. In case of lower LO amplitude the assumption of perfect

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19 switching is not valid and the conversion gain reduces. Both the switching transistors are on for a fraction of time ( ) which can be approximated as, 22() g sth LOLOVV V (2-8) During time interval , no mixed signal appears at the output and gain contribution for this interval can be subtracted from ov erall gain and gain can be expressed as, 2() 22 (1)1gsth vmLmL LOLOVV AGRGR TV (2-9) 2.3.2 Local Oscillator (LO) Transistor Size Optimization After the dc operating points are fixed to appropriate values, the need to optimize conversion gain and linearity of the mixer as a function of LO signal amplitude arises. Conversion gain increases with an increase in the LO drive level to higher value because of improved switching of LO devices. Typical ly, the transconductance stage dominates the nonlinearity of the mixer. This ho lds true if the cut-off frequency (fT) of the device is much higher than the frequency of the LO si gnal (typically more th an 10 times). Still the switching pair contributes a little towards th e non-linearity pe rformance. Linearity of the mixer is increased with an increase in the LO signal amplitude up-to a certain level, after that non-linearity of the sw itching pair dominates the mixe r linearity and causes linearity degradation at large LO amp litudes [16]. Degradation in lin earity is caused by the nonlinearity of Cgs of the LO switch transistors. High LO switching leads to high amount of current being pumped into the common sour ce point of the switching pair through the non-linear capacitance Cgs .This leads to degradation in linearity and conversion gain. At high frequencies larger size for LO transistors leads to increased load at the LO port and

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20 reduces the available LO swing, which might again lead to gain degradation. The LO transistor size was chosen to be 20-m for the design. 2.3.3 Input/Output Matching Networks Due to variations associated with the fabrication process, it is desired to keep the quality factor for the input and output matc hing networks to be low [17]-[18]. A high value of quality factor can reduce the power consumption but the circuit becomes more susceptible to process variations and a wide-band response cannot be achieved. A Qin value of 1.5 is chosen for the input matc hing network in order to accommodate wide range of input signals. Inductive degeneration Ls (Ls1 and Ls2) along with gate inductance Lg (Lg1 and Lg2) has been used to match the input impedance to the source impedance of 50.. A simplified approximate expression for the impedance Zin looking into the gate of transistors M1 and M2 can be written as (Equation 2-10), 01 () (2)IFms inIFgs IFgsgdjgL Z ZjLL jCC (2.10) Optimization of gain was the prime goal for the design and Ls (100-pH) is made very small. Hence Ls can be neglected in Equation-2.10 compared to Lg. Quality factor of the input matching network (Qin) including the source impedance Z0 can be expressed in terms of Lg and capacitances 001 22(2)IFg in IFgsgdL Q ZZCC (2-11) Using Equation 2-11, the value of Lg is found to be ~8 nH for the chosen Qin value of 1.5. Owing to this large value the gate inductors occ upy a significant amount of chip area. Sizes of transistors M1-M2 are cal culated based on the requirements for Cgs and Cds and are fixed for the chosen Qin. Transconductance (gm) is governed by conversion gain

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21 requirement and current consumption of the circuit. Large sized transistors (M1-M2) were required to provide the necessary amount of capacitance for th e IF of 3-GHz, which comes from the low Qin requirement. Effectively choice of a particular Qin value sets the entire input matching netw ork. A large inductor Lc is inserted between the ground and the common node of the source degeneration inductors (Ls1 and Ls2). Inductance value of 8.5 nH is chosen. The inductor pr ovides an impedance of ~160looking into the inductor at the input frequency of 3-GHz. It helps to re duce the effect of co mmon mode signal on the operation of the circuit. For the output matching network, an L-sect ion consisting of a shunt-L-series-C is used. To achieve broad-band response at outpu t it is required to choose a low value for the quality factor of output matching network (Qout), which leads to a reduction in conversion gain. The drains of the cross c oupled transistor pair s M3-M5 and M4-M6 are connected to the power suppl y through the inductors Ld1 and Ld2, respectively. The inductor resonates with th e capacitance at the output node which includes output capacitance of transistors and the series drain capacitance Cd (Cd1 and Cd2). Capacitance Cd1 and Cd2 are realized using metal insulator me tal capacitors (MIM) capacitors. Metal 6 and 8 are used for top layer and bottom plate is formed using metal 5 and 7. These MIM capacitors have associated parasitic capacitance (Cpar) associated whose value was chosen to be ~10% of actual MIM capacitance value in the simulations. This parasitic capacitance (Cpar) makes is difficult to achieve high gain and broad-band response simultaneously. A higher value of inductance is favorable to achieve high gain, which decreases if series capacitance Cd and hence, Cpar is high. Voltage drop across Cd is high when the chosen value for Cd is low. Ld value is chosen to ge t good gain at expense of

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22 broad-band response. Simulated peak conversiongain was 8-dB for the chosen values of Ld and Cd. Simulation results included the effects of parasitic associated with the metal interconnects in layout. A die photo of the fabricated mixer is shown in Figure 2-8. The chip occupies an area of 870m x 600 m. LO ports are terminated with 50resistors to better control the amplitude of LO signal during testing. Layout is made symmetrical to minimize the offsets caused by unbalance and also to maintain a high common mode rejection. An on-chip bypass capacit or is placed between the ground and Vdd node to reject the power supply noise affects on the performance of the mixer. Figure 2-8. Up-conversion Gilbert-cell mixer 2.4 Experimental Results The noise figure and gain of an up-convers ion mixer are not as important as they are for a down-conversion mixer because the baseband signal to noise ratio is typically higher for a transmitter. It is important th at the up-converter mixer should be operable with moderate LO power so as to av oid interference and unwanted LO-feedthrough problem, which are caused by mixer imbalances due to asymmetry in layout and the variations associated with the fabrication process. The performance was characterized

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23 using a pair of groundsignal-signal-ground probes and dc probe for Vdd. Four bias Tees were used to bias each of the differential RF and LO signal. Baluns were used at IF and LO port to convert the single ended signal from the signal generator to differential signals. The differential RF output was combin ed using a balun to single ended signal. Measurement setup to determine the conversiongain of the mixer is shown in Figure 2-9. Figure 2-9. Measurement set up for the differential mixer Figure 2-10. Measured input return loss

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24 Broad-band performance was achieved for the mixer at the IF port. Figure 2-10 shows the impedance matching for the IF input. Measured return loss was better than -10 dB between 2.3-3.6GHz. The circuit opera ted optimally at 2.8 GHz where maximum conversion gain was achieved. For the output impedance matching, the return loss was better than -10 dB for a range of 4.3 GHz from 17.5 GHz to 21.8 GHz. A plot of measured return loss at the output port is shown in Figure 2-11. Figure 2-11. Measured output return loss Conversion gain for the circuit was measur ed for varying IF signals where the LO was varied to keep the RF constant at 20 GHz. Measurements were performed at a current consumption of 6.8-mA with a 3 dB m LO drive level. A 3-dB conversion gain bandwidth of 1.1-GHz between 2.2-3.3 GHz wa s achieved at the IF port. Gain bandwidth is defined as the frequency range where the ga in drops by 3-dB from the peak value of 1dB. Measured conversion-gain versus IF is shown in Figure 2-12. Measured 3-dB conversion gain bandwidth at output port wa s 5-GHz which is shown in Figure 2-13. The measured conversion gain increases with the in crease in current because of an increase in

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25 the transconductance value and peaks at 1.7-dB at a current consumption of 8-mA. There is no further increase in gain as the transistor nonlinearites start to become significant and gain compression occurs. A plot of current consumption versus th e conversion gain is shown in Figure 2-14. Figure 2-12. Measured conversion-gain versus IF Figure 2-13. Measured conve rsion-gain versus RF

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26 Figure 2-14. Measured conversion-ga in versus current consumption Linearity performance of the mixer was ev aluated at a current consumption of 6.8 mA. The circuit achieved an input referred 1dB compression point of -12 dBm, when the input LO power was 3-dBm. Figure 2-15 show s a plot of measured output power level versus input power level. Figure 2-15. Measured 1-dB compression response

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27 Small amount of degeneration used in the design is the main cause of this not so good linearity. Performance deviations were observed between the simulated and the measured performance of the circuit. A disc repancy analysis to find the cause of such deviations is described in the next section. 2.5 Simulation and Measurement Discrepancy Analysis Discrepancies were observed between meas ured and simulated conversion-gain and the optimum frequency of operation. The goa l was to achieve optimum performance at intermediate frequency of 2.7-GHz and RF of 24-GHz. In high fre quency circuit design, it has generally been observed that there are always some parasitic that are not accounted for in the simulation model files and the optim um frequency of operation of RF circuits shift to a lower value than e xpected. Figure 2-16 shows the sh ift of optimum frequency of operation from 27-GHz down to 20-GHz. Figure 2-16. Simulated and m easured output return loss

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28 Figure 2-17 shows the deviation between m easured and simulated conversion gain performance versus the input intermediate frequency. Figure 2-17. Simulated and measur ed conversion-gain versus IF A margin of 15% was taken as a guideline, and the circuit was simulated to operate optimally at RF of 27 GHz (whi ch is almost 15% higher than the desired RF of 24 GHz). The simulated conversion gain was around 8 dB. The measured response however, deviated from the simulated response in optimum frequency of operation as well as achieved conversion gain. The measured conve rsion gain was ~1 dB and the optimum frequency of operation shifted down to 20 GHz. One reason for this mismatch is possibly the values of passive components in the circuit. MIM capacitors and sp iral inductor values used in simulation did not match well with actual values which caused gain and frequency mismatches. MIM capacitors had parasitic capacitances associated with them whose value was taken as 10% of actual capacitor value in simulations. Test circuits were designed for the on-chip components to

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29 verify their values with that used in the si mulation [19]. Measurement of test structures showed that the actual capacitance was 1.2 times the value used in simulations. Also parasitic capacitance of MIM capacitors was 15% instead of 10% of the actual value. Inductor test structure results showed that measured inductance and bond-pad capacitance values were also a little higher than that us ed in the simulation. On using the corrected values of passive elements in cadence simu lations, the operating frequency shifted down to 26-GHz. It is concluded that the deviati ons associated with the values of passive elements is not the main cause for disagr eement between measurements and simulations.. Another reason for the frequency shift was becau se of incorrect simulation models for the active transistors. A test stru cture to compare the measured and simulated performance of the active transistor was built (width=14m length=0.13-m). From the measured behavior of the transistor, it was concluded that the drain to body (Cjd) and source to body (Cjs) capacitances were almost two times the ones used in the simulation files. The effect of the measured series resi stance between the substrate and ground was also taken into account. The Rsub (45) between the body of the tr ansistor to chip ground was much higher than that used in cadence simulations (10). At low frequency values, effect of Rsub mismatch does not effect the output resi stance of the transi stor as the Q of Cjd ( 1 j dsubQ CR ) is high and hence, equivalent parallel representation of Rsub (2(1)parsub R RQ ) is high. At high frequency Q drops down to a low value and Rpar decreases. Lowering of Rpar decreases the output resistance of the transistor (Rout) which lowers the conversion gain. LO transistor width for the mixer design was 20-m and due to unaccounted Cjd and Rsub the optimum frequency of ope ration shifted down to 20-GHz and achieved conversion gain was also lower than simulation. A corrected model that

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30 matches the actual performance for a transistor is shown in Figure 2-18, where additional capacitances and resistances are added to ma tch the simulated performance to actual performance of the active device. The reduction in gain is also attributed to the fact that measured current was 2-mA less than expected. This leads to a decrease in the transconductance which in turn leads to a re duction in conversion gain. The quality factors of the on-chip inductors were lower th an expected which also contributed to the reduction in gain. Figure 2-18. Corrected model for MOS device 2.6 Conclusion Measured performance of a double-bala nced Gilbert-cell up-conversion mixer fabricated in 130-nm CMOS Logic process shows that it is possible to achieve reasonable performance from CMOS up-conversion mixers for frequencies in K-band range. The designed circuit was one of the first to be implemented in CMOS technologies that worked at frequencies of 20-GHz or higher at relatively lower power consumption levels. The mixer achieved a 3-dB conversion gain ba ndwidth of 1.1-GHz at the input (IF) port and a 3-dB conversion gain bandwidth of 5-GHz at the output (RF) port. The circuit also

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31 achieved good isolation perfor mance between the ports. Linearity performance of the circuit still needed to be im proved. To improve the linearity another test structures was designed in dual-gate topology. Re sults of the dual-gate mixer are presented in Chapter 3.

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32 CHAPTER 3 DOUBLE-BALANCED DUAL-GA TE UP-CONVERSION MIXER 3.1 Introduction Dual-gate topology also has been a popular choice to build active mixer along with the common Gilbert-cell topology [20]-[25]. Such mixers have been widely used in hand held radios and communication systems for several decades. These mixers typically exhibit good intermodulation ch aracteristics and reasonable noise figure. In dual-gate architecture, LO and RF signa ls are applied to two sepa rated gates. Good isolation between the RF and LO ports can be achieved in this architect ure. It also becomes easier to match LO and RF separately to the input impedance which results in optimum performance at low power levels. LO-to-RF is olation is very important in a transmitter system as LO signal might leak to the RF port and then leak thr ough the antenna causing interference to adjacent channels. In practice, it is diffi cult to fabricate an actual fourterminal dual gate device with controlled characteristics. Furthermore the absence of theoretical distortion analysis for such four terminal devices makes the optimization of performance characteristics very difficult in such mixers. This difficulty can be alleviated by using a pair of cascode transist ors to serve as a dual-ga te device [26]. Use of cascode transistors as a dual-g ate device provides the flexibil ity to choose different sizes for the transistors which is useful when th e two input frequencies are widely spaced. A double balanced topology has been chosen for the mixer design because of its inherent property of good isolation between the ports. Figure 3-1 shows the schematic of the designed mixer with input and output matching networks.

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33 Figure 3-1. Double-balanced dual-gate up-conversion mi xer with input and output matching networks Although the topology looks similar to comm only used Gilbert-cell, the principal of mixing operation is very different in a dualgate mixer. In a dual-gate mixer, a finite LO signal must be present at the drai n of the lower FET which causes the Vds of the transconductance stage (lower st age) to change. Due to this , the transconductance of the lower FET (gm) is modulated by switching the de vice between linea r and saturation regions. In a Gilbert mixer, the LO signal at the drain of the differential pair is ideally zero and the mixing is caused by switching act ion of the LO pair between cutoff and saturation region [18]. In a G ilbert mixer, the transconductanc e stage is primarily biased in saturation region whereas in a dual-gate mixer the lower FET operates in linear region during most of the LO cycle, resulting in lower transconductance than a FET biased in saturation region. Because of th is, the conversion gain of Gilbert cell design is normally higher than that for dual-gate architecture . Dual-gate mixers, on the other hand, have moderately better intermodul ation performance than the Gilbert cell. The design

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34 considerations and choice of component para meters for the dual-gate mixer are described in next section. 3.2 Design Considerations: Dual-Gate Mixer 3.2.1 Bias Point Optimization DC-biasing plays an important role to ach ieve optimum performance in a dual-gate mixer design. In dual-gate topology transistor s are biased such that upper transistors (M5M8) remain in saturation throughout the ope ration and the lower transistors (M1-M4) operate in linear region near the edge of saturation. Although the dual-gate topology employs the cascode structure, biasing scheme makes their operations very different from cascode amplifiers. For cascode amplifier to achieve maximum conversion gain both upper and lower transistors should operate in saturation region. In dual-gate mixer, upper transistor remains in saturation and lower transistor remains in linear region most of the time [21]. A simple dual-gate schematic to de scribe the DC-current characteristics is shown in Figure 3-2. Figure 3-2. Dual-gate devi ce using cascode structure

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35 Current in the lower FET is controlled by the voltage VG1S1 and current in the upper FET is controlled by VG2S2. Voltage VDS1 is floating and it takes values between Vdd and 0 so as to satisfy the requirement of equa l current in M1 and M2. Due to changes in VG2S2, the voltage of the floating node (VDS1) also changes. For maximization of conversion gain, both transistor s should operate in saturation ; this can only happen over a narrow range of gate-bias voltages when an LO signal is applied to the gate of M2. M1 and M2 are simultaneously in saturation when VD1S1 and VD2S2 are greater than VDS1,sat and VDS2,sat. For such a situation, the required bias condition should be such that VG1S1 is approximately equal to VG2S2. The amplitude of the LO sign al at the gate of M2 is generally high, and VG2S2 changes according to the applied LO level. This disturbs the condition of equal gate-source voltages for M1 and M2, which makes it difficult for both M1 and M2 to be in saturation at the sa me time. In presence of LO signal, VD1S1 keeps switching between low and high values. This in turn modulates the transconductance (gm) of M1. Figure 3-3 shows a plot of the tim e varying transconductance of the lower transistor in presence of LO si gnal at gate of upper transistor. Figure 3-3. Time varying transc onductance of lower transistor When VD1S1 is low, M1 operates in linear re gion and the transconductance is low, and the drain to source conductance (gds1) is relatively high. When VD1S1 increases to a

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36 high value, M1 goes into sa turation, transconductance (gm1) increases and the drain to source conductance (gds1) decreases. The fluctuation of M1 between linear and saturation regions causing modulation of transconductance (gm1(t)) and conductance (gds1(t)) is the only mechanism possible for mixing to occur in dual-gate topology. U pper transistor is biased such that it remains in saturation throughout LO cycle and its transconductance remains almost constant. If device M1 was to be kept in saturation throughout the time of operation, the parameters would remain unc hanged with applied LO signal and mixing would not occur. 3.2.2 Local Oscillator (LO) Transistor Size Optimization The cascode structure based dual-gate design provides flexibility to choose different gate widths for upper and lower tr ansistors and optimizes the design according to the frequency inputs. As the IF frequenc y (2.7-GHz) for the up-conversion mixer is lower (~7 times) than the LO frequency (21.3-GHz)), in order to match the input port and to achieve conversion gain, the transconductance transistors are chosen to be larger than the LO transistors. The choice of LO tran sistor sizes depends on the tradeoff between noise figure, linearity and the amount of LO drive av ailable in the low power environment. If the LO transistors are ch osen to be the same as that for the transconductance stage, then th e parasitic capacitance at th e floating nodes (F1-F4 in Figure 3-1) increases, leading to a decrease of the voltage swing at the node thereby degrading conversion gain. With an incr ease in the LO drive level modulated transconductance of lower tran sistors increases which incr eases the conversion gain. Figure 3-4 shows a plot of the minimum and maximum LO voltage level for different chosen widths of LO transistors.

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37 Figure 3-4. Simulated available LO voltage level versus LO transistor width Figure 3-5. Simulated conve rsion-gain and input P1dB versus LO transistor width For smaller size of LO transistors peak -to-peak LO swing is larger which increases the amplitude of the modulated transconductance and hence conversion gain.

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38 Also the minimum level of LO signal is lesser for smaller size which ensures operation of lower transistor in linear region for a larger fr action of time as compar ed to larger device and hence linearity is also better for smaller sizes. Fi gure 3-5 shows the simulated conversion gain and input 1-dB compression po int versus different transistor widths. In presence of a larger LO drive the lowe r transistor remains in linear region for a longer period of time and improves the linearity of the circuit. A larger width for the LO transistor can result in some improvement in noise figure but noise is not an important design criterion for an up-convert er design so the size s of the LO transistor (M5-M8) gate width has been kept to be 20m to make the load for LO drivers not excessive. Conversion gain of a dual-gate mixer is propo rtional to the amplitude of the modulated transconductance which is directly proportional to available LO driv e. Although, at very high LO drive non-linearities of LO transistor s start to dominate and prevent further improvement in overall linearity. 3.2.3 Input/Output Matching Networks To achieve broad-band impedance matching and tolerance to component variations at the IF and RF ports, the quality factors of the input and output matching networks (Qin and Qout) are designed to have low va lues. A value of ~1.0 for Qin is chosen. The measured 3-dB conversion gain bandwidth for input signals (IF) is 2.2-GHz. Gate inductor Lg (Lg1 and Lg2) and source degeneration inductor Ls (Ls1 and Ls2) are used to match the input to 50. For this particular value of Qin and resonant frequency of 2.6 GHz, Lg value of 6.6-nH can be obtained using E quation 2-6. Because of its large value, this inductor occupies a si gnificant amount of chip area. Having source degeneration also helps improve the linearity at some expe nse of conversion gain. The transconductance (gm) is limited by the maximum tolerable current consumption and partially determines

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39 the conversion gain. Assuming the use of minimum channel length devices, once Qin is set, the widths of transist ors M1-M4 can also be determined using Equation 2-6. IF transistor gate widths are chosen as 165-m, to provide the capacitance required for input matching, at IF of 2.7-GHz. A large inductor Lc (~7.0-nH) has been placed between the ground and the common node of the degeneration inductors. At resonance frequency of 2.6-GHz this provides an impedance of ~115. This helps to reduce the effects of common mode signals in the circuit For output matching, an L-matching network consisting of a shunt Ld (Ld1 or Ld2), and a series Cd (Cd1 or Cd2) has been used. The drains of coupled transistors M5-M6 and M7-M8 are connected to the power supply through the inductors Ld1 and Ld2 (0.34-nH). The quality factor of output matching network is kept low to cover the 22-29-GHz band for ultra-wideband applicati ons. The quality factor Qout is chosen to be ~2.2 at the centre frequency of 25-GHz, which is related to the quality factor of drain inductor (QLd) and resistance looking into drain of LO transistors (D1-D2 in Fig. 1) as expressed in Equation (4) [24]. To achieve Qout of 2.2, inductor Q (QLd) only needs to be ~8.9 at 25-GHz (Equation (3)). One terminal of the drain inductors Ld1 and Ld2 is connected to Vdd, which is an AC ground. For each output side the spiral inductor Ld ( Ld1 or Ld2) along with its parasitic series resistance RLd (~6 ) can be equivalently repr esented with a parallel combination of Ld(1+1/QLd 2) and RLd(1+QLd 2). For QLd of ~8.5, Ld(1+1/QLd 2) is ~Ld. A simplified schematic of the output matc hing network is shown in Figure 3-6.

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40 Figure 3-6. Simplified schematic of output matching network 11 11() ()d dRFd L L L imagY Q realYR (3-1) To match the impedance at the ou tput port, shunt resistance of ZL in Fig. 4 should be RLd(1+QLd 2) || Rds, where Rds (~460 ) is the resistance looking into the drain nodes D1 and D2 in Fig. 1. When this is satisfied, Qout at the resonant frequency (RF) is given by Equation 3-2. 2(1)|| 2ddLLds out RFdRQR Q L (3.2) The conversion gain for a dual gate mixer can be represented as, 22 1,0dLdTmampinoutLGgQZQRQ (3-3) Gain is directly proport ional to the amplitude of modulated transconductance (gm1,amp) which can be increased with a higher LO drive level. A higher LO drive level thus is essential to achieve gain in dual-gate mixers. Also gain is proportional to the quality factors Qin and Qout. This shows that to achieve broad-band frequency response as

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41 quality factor are lowered th e gain also decrease. Also the gain is proportional to QLd and can be increased by choosing a higher value for Ld.The LO ports have been terminated with 50 resistors. This helps to achieve br oad-band impedance matching to cover the wide LO signal range and to better control the applied LO signal amplitude at the ports during testing. The effects of parasitic a ssociated with the sp iral inductors, metal interconnects and bond pads have also been take n into account. The chip occupies an area of 600m x 860 m. An on-chip bypass capac itor has been placed between the ground and Vdd. The die micrograph is shown in Figure 3-7. In the layout, shielded pads are employed at RF, LO and IF ports [25]. The ground shield reduces the signal power loss and noise generation associated with the substrate resistance. Wide ground rings are placed around all the transistors at minimum distances allowed to reduce the substrate losses. To mitigate the LO feed-through problem, the layout was made symmetric. Figure 3-7. Dual-gate up-conversion mixer

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42 3.3 Experimental Results The mixer was characterized on wafe r using differential (GSSG) probes. Measurements were performed at an LO power level of 3 dBm. Measurement setup was similar to the setup used in Figure 2-9. The measured LO-to-RF isolation was better than 30 dB, LO-to-IF isolation was better than 55 dB and IF-to-RF and IF-to-LO isolations were both better than 50 dB. Isolation betw een LO-to-RF and LO-to-IF was better than 30 and 50 dB for LO frequency variation from 14-26-GHz as is shown in Figure 3-8. Good impedance matching was achieved at the input (IF) and output (RF) ports. Measured input port return loss was better than -10dB between 2.4 to 3.5 GHz. For output port measured return loss was better th an -10 dB between 19.5 to 25 GHz. Figures 3-9 and 3-10 show the impedance matchi ng at the IF and RF ports, respectively. Figure 3-8. Isolation between LO -to-RF and LO-to-IF ports

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43 Figure 3-9. Measured input return loss Figure 3-10. Measured output return loss

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44 Measurements were performed to characterize the performance for a wide range of input frequencies. For this measurement IF and LO were varied in a manner so as to keep the RF constant at 23-GHz. A 3-dB conversion gain bandwidth of2.1-GHz was achieved between 1.5-3.6 GHz. Figure 3-11 s hows the plot of conversion gain for different IF at a current c onsumption of 6.8 mA with Vdd=1.2V. Maximum conversion gain of 0.7 dB is achieved at IF of 2.3 GHz. The circuit also exhibited broad-band performance at the RF port. Input signal fr equency (IF) was kept fixed at 2.3 GHz and LO frequency was varied to achieve different output frequency (RF). LO power level was kept at 3 dBm for the measurement. Current consumption was kept constant at 6.8 mA from 1.2 V supply. Measured 3 dB convers ion-gain bandwidth was 10 GHz between 1828 GHz as is shown in Figure 3-12. The pow er consumption for the measurement was 8mW and the applied LO signal power was 3-dBm. Figure 3-11. Measured conve rsion-gain versus IF

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45 Figure 3-12. Measured conve rsion-gain versus RF Primary emphasis of this design was to achieve improved linearity response as compared to the previously measured lineari ty of the Gilbert-cell up-conversion mixer. The mixer had a simulated conversion gain of 5 dB with input 1-dB compression point of -6.0 dBm. Linearity response was also charac terized for a wide range of input and output frequencies. Similar to conversion-gain, the mixer achieved flat lin earity response at both input and output ports. The measurement setup used to measure the third order intermodulation response is shown in Figure 3-13. Figure 3-13. Measurement setup to dete rmine third-order intermodulation (IIP3)

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46 Measurements were performed at a current consumption of 6.8 mA from a supply of 1.2 V. LO power was kept at 3 dBm. Th ird order intermodulati on characteristics and gain compression were measured. For input po rt 1-dB compression and OIP3 were flat over more than 1.5 GHz of input frequencie s. Figure 3-14 shows th e measured linearity performance with varying IF. Measured 1dB compression and OIP3 performance at output port is shown in Figure 3-15. OIP3 valu es of better than 2dBm and an output 1-dB compression value of better than -9 dBm were achieved for a wide range of 10 GHz. The flat linearity and gain performance achieve d by the design demonstrates that CMOS mixer for ultra-wide band applications can be successfully implemented in CMOS technology. The behaviors of conversion-ga in and 1-dB compression behavior as a function of LO drive were also characterized. At a fixed bias point, as the LO drive is increased, the lower FETs operate in the linear region for a larger frac tion of an LO cycle, and overall linearity is improved. A plot of measured output 1-dB compression point and conversion gain versus LO drive at a constant current consumption of 6.8mA is shown in Figure 3-16. Conversion gain is also im proved as the amplitude of modulating transconductance also incr eases with increased LO drive [ 11]. An increase of LO power beyond 6.0 dBm does not further improve P1dB as the non-linearity of LO transistors becomes dominant. Measured conversion-gain and 1-dB compression performance were also characterized as a function of current cons umptions of the circuit while keeping LO power fixed at 3 dBm. At current consumption of 9 mA the circuit achieved a gain of 1.7 dB and an output 1-dB compre ssion point of -3.4 dBm. Fi gure 3-17 shows the measured conversion-gain and 1-dB compression performa nce versus varying current consumption.

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47 Figure 3-14. Measured output P1dB and OIP3 versus IF Figure 3-15. Measured output P1dB and OIP3 versus RF

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48 Figure 3-16. Measured output P1dB and OIP3 versus LO power Figure 3-17. Measured output P1dB and OIP3 versus current consumption

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49 3.4 Conclusion The design and measured characterist ics of a broadband CMOS up-conversion mixer working at K-band are presented. By carefully choosing the qua lity factors of the input and output matching ne tworks, wide band response was achieved at IF and RF ports for a simple dual-gate configuration. A lis t of the performance of present design and previously published CMOS [27]-[28] and Si Ge [29]-[31] mixers operating at similar frequency ranges is shown in Table 3-1. Th e dual-gate mixer presented in this paper achieves very good isolation be tween all the ports and flat linearity response over a bandwidth of more than 10-GHz at output RF port, while consuming only 8 mW from a 1.2 V supply. Compared to the 20-GHz Gilbert cell up-conversion mixer [27], OP1dB is 46 dB higher while consuming the same power. These results successfully show that an up-conversion mixer for ultra-wideband radars operating in the 22-29 GHz [32] can be implemented in low-cost and low-voltage Logic CMOS process. Table 3-1. Performance summary of mixers operating in K-Band Reference/ Technology RF [GHz] LO Power Level [dBm] Gain [dB] Output P1dB [dBm] OIP3 [dBm] Power [mW] [27] 0.13m CMOS 20 3 1 -11 -8.0 [28] 0.13m CMOS 16.619.6 -4 4.2 13 93 [29] SiGe HBT 20 7.5 11 1 10 32 [30] SiGe HBT (fT 85 GHz) 28 -3 -5 -742 [31] SiGe (fT 47GHz) 17 5.4 9 --10 17.8 This work 18-28 3 -2 – 0.7-7.0 -5.2 3 5.8 8.0

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50 CHAPTER 4 DOUBLE-BALANCED GILBERTCELL DOWN-CONVERSION MIXER 4.1 Introduction Down-conversion mixer is a key block th at affects overall linearity and noise performance of a receiver system. Desi gn of a down-conversion mixer involves optimization of noise performance in additions to linearity and gain. Lower noise figure (NF) for mixer can help re duce the NF and gain requirements of preceding LNA stage and thereby reduce the power consumption of LNA. Good third order linearity is also required in order to avoid si gnal corruption due to falling of unwanted signals in the desired band. Some gain should be associat ed with a down-conversion mixer to help reduce the noise contribution of further stages. In order to optimize the power consumption it should be operable with lower LO power level so that power consumption of LO driver can also be kept low. For the 24-GHz receiver chain, the down-converter mixer converts signals from 24-GHz down to IF of 2.7-GHz. Gilbert cell designs have shown to achieve a good tradeoff between th e required performance parameters. Design considerations for performance optimiza tion of mixer are described below. 4.2 Design Considerations: Br oad-Band Gilbert-Cell Mixer 4.2.1 Input Matching and Driver Stage Double balanced Gilbert cell mixer topology has been chosen for the design. To optimize the performance all transistors shoul d be biased in saturation region. When driver stage transistors are biased in satura tion their gain is maximum, this helps to compensate for the effect of loss due to the switching stage. LO st age transistors should

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51 also be biased in saturation. Schematic of the circuit with i nput and output matching network is shown in Figure 4-1. Figure 4-1. Down-conversion Gilbert-cell mixer with input and output matching networks Linearity of the differential pair driver stage and thus overall linearity can be improved by adding degeneration. Degeneration can be resistive, capacitive or inductive. Reactive degeneration is preferred over resi stive degeneration in down-conversion mixers as reactive elements do not introduce additional noise as compared to resistor. Amount of degeneration is limited by gain and linearity tradeoff. Driver stage using inductive degeneration has shown to achieve better linearity for same bias current and transconductance levels [33], so inductive dege neration is the best tradeoff between noise and linearity. Gate inductors Lg1 and Lg2 are used along with the degeneration inductors Ls1 and Ls2 to match the input to 50 . The design was targeted to achieve broad-band response hence the quality factor of the input matching network ( Qin) was chosen to be ~1. A lower value of Qin also helps to reduce the gate induced noise and thus lowers noise

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52 figure. For this choice of quality factor, the value of inductors Lg1 and Lg2 can be approximated from Equation 2-6, which also gi ves an estimate of the transistor sizes based on the requirements for capacitance Cgs and Cgd. Minimum allowable length of 0.12m has been used for the transistors. Use of minimum channel length devices increase the transconductance of the driver stage and hence gain. As can be seen from equation (2-16), transistor sizes (M1M2) are inversely proportional to Qin. For smaller Qin larger sized transistors are needed wh ich provide higher transconductance and more gain for driver stage which in turn helps to compensate for signal associated with switching stage. So the choice of lower Qin to achieve broad-band response proves to be little beneficial for noise figure performance. Width of driver stage transistors was 32 m for the chosen Qin value of 1. 4.2.2 Local Oscillator (LO) Transistor Size Optimization A proper choice of LO power le vel and LO transistor sizes is important to achieve good noise figure performance. Size of the LO transistors are decided by the tradeoff between the linearity and noise figure performa nce. In order to achieve good noise figure performance it is required to minimize the loss associated with the switching stage. For a given LO amplitude it is desira ble to increase the size of th e switching transistors till the conversion gain of the switching st age reaches it maximum value of 2/ . Further increase in size is not preferred as it does not increase the gain of the switching stage and may lead to an increase in the noise coming from the LO port. It also introduces higher capacitances which cause deterioration in pe rformance at higher frequencies and also represents a large load to the LO signal. For optimization, noise figure performance was simulated for different chosen values of LO transistor widths, keeping the minimum length of 120-nm. Minimum channel length is preferred for the switching pair devices as

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53 larger length reduces the gain of the switching stage. Longer channel length also requires larger channel widths for operation with si milar LO amplitude and bias current which introduces higher capacitance and degrades the performance at higher frequencies. Simulated noise figure versus the LO transi stor size is shown in Figure 4-2. For the present design the LO transistor sizes were kept to be 50 m which shows good performance in terms of noise figure and linearity tradeoffs. Figure 4-2. Simulated noise figur e versus LO transistor size Also the noise figure decreases with an in crease in the amplitude of the LO signal [34]-[36]. In Figure 4-3 (Equation 2-8) represents the tim e when both the transistors of a switch pair are ON. Time interval shortens with increase in LO signal amplitude. At lower LO power levels the both transistors ar e simultaneously on for a larger fraction of period. During this time the switches act li ke cascode amplifiers and contribute more noise at the output. This incr eases the noise figure at lo wer LO power levels. After certain LO amplitude the time interval does not improve much a nd also the loss of the

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54 switching stage becomes constant thereby re ducing any further improvement in noise figure with increase in LO amplitude. A plot of simulated noise figures versus LO power level is shown in Figure 4-4. Figure 4-3. Local Oscillator (LO) waveform with different amplitudes to show the time when both transistors of a switch pair are ON Figure 4-4. Simulated noise figure versus LO power Keeping the LO power consta nt at -1 dBm the simulate d noise figure values at different input frequency values is shown in Figure 4-5. Design was optimized at 3-GHz

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55 and with chosen width of 50m for the LO transistors a noise figure of 8-dB can be obtained at 3-GHz. Figure 4-5. Simulated noise figure versus frequency 4.2.3 Output Matching Network Broad-band response was desire d at output so as to accomm odate large range of IF signals. For the output matching network two sections of shunt-L-series-C networks are employed. Using two sections can help to ac hieve lower quality factor as compared to one shunt-L-series-C and ther eby increasing impedance matc hing range at output. The drains of transistor pairs M3-M5 and M4-M6 are connected to the power supply through the inductors Ld1 and Ld2. These provide a convenient way to bias the ci rcuit while not significantly reducing th e voltage supply headroom as th ere is only small DC voltage drop across the inductors. The inductors also add lower noise. Ld1 and Ld2 are designed to have a larger value so as to maximize the conversion gain.

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56 A 1.5-nH inductor, Lc has been insert ed between ground and the common node of source degeneration inductors. This provides an impedance of around 180 looking into the inductor at 19 GHz and helps to reduce th e effect of common mode signals. LO ports have been terminated with 50resistors. This ensures broad-band impedance matching at LO ports and also helps to control the am plitude of LO signal during testing. Parasitic associated with bond-pad and interconn ects were taken into account during layout/simulations. The chip occupies an area of 770m*690m and the die photograph is shown in Figure 4-6. Figure 4-6. Down-conversion Gilb ert-cell mixer (broad-band) 4.3 Experimental Results: Br oad-Band Down-Conversion Mixer Special attention was paid to make the layout symmetric so as to minimize the mismatches that causes unwanted feed-t hrough. Performance was characterized using GS-SG probes. The quality factor of the input matching network ( Qin) was chosen to 1. Transconductance ( gm) was limited by power consumption, and can be controlled by

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57 setting VGS-VTH. Assuming use of the minimum channel length devices, once Q in is set, widths of transistors M1 a nd M2 were chosen to be 34m, to meet the capacitance requirements. Mixer was characterized at Vdd=1.2V. Measurement setup is similar to setup shown in Figure 2-9. Measured input re turn loss was better than -10 dB between 16-21 GHz as is shown in Figure 4-7. Figure 4-7. Measured input return loss At input port, 3-dB conversion gain bandw idth was calculated w ith a variable RF and LO, while keeping IF constant at 2.7GHz . The measurements were done at a current consumption of 5.7mA at Vdd=1.2V. The circuit achieved a 3-dB bandwidth of 6 GHz at input frequency range of 16-22 GHz. Plot of conversion gain as a function of RF is shown in Figure 4-8. Due to lower choice of quality factor for the output matching network, broad-band impedance matching has be en observed at output port. Return loss is better than -10 dB for a band-widt h of more than 2-GHz. (Figure 4-9)

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58 Figure 4-8. Measured conve rsion-gain versus RF Figure 4-9. Measured output return loss

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59 Figure 4-10. Measured conve rsion-gain versus IF Broad-band matching at output port also ensured fairly flat conversion gain response at the output. A 3-dB conversion gain bandwidth of 1.4 GHz was obtained at the output around IF of 2.7-GHz which is more than 50% of the IF value. Measurements were done at a current consumption of 5.7mA at Vdd=1.2V. Gain variation is dB for a bandwidth of more than 1-GHz around the IF of 2.7-GHz, as is shown in Figure 4-10. Isolation performances were also measured for the circuit. RF-IF, LO-IF, LO-RF are better than 36dB, 50dB and 41 dB respectively, which are excellent and are almost constant over the respective frequency range. Gain compression and intermodulation res ponse have also been measured. The circuit shows an input 1-dB compression point of -12dBm at a current consumption of 5.7mA with Vdd=1.2V. The third order intercept point has been measured with a two tone input signal. An IIP3 of -2dBm has been achie ved at same power consumption. Figure 411 shows a plot of output power versus input power when the RF and IF are kept to be 19GHz and 2.7GHz respectively.

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60 Figure 4-11. Measured input P1dB and IIP3 response Measurement setup to measure the noise fi gure of the down-conversion mixer is shown in Figure 4-12. Figure 4-12. Noise figure measurement setup

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61 At input frequencies around 20 GHz, there is significant loss associated the baluns and probes. To measure the actual noise fi gure of the mixer chip, it is required to calibrate the losses of baluns and probes at RF and IF frequencies [37]. Losses at RF frequencies were 4-5dB and 1-2dB at IF fre quencies. As noise figure meter calibrates upto the output of noise source, noise figure of entire system including baluns and probes at RF and IF ports was measured. Noise figure of standalone mixer can then be determined using Friis’ equation [38]. 2132 1 112()1()1 ()outout totals AAAFZFZ FFR GGG (4-1) Figure 4-13. Measured noise figure versus LO power A plot of measured noise figure performa nce with varying LO power at IF = 2.3 GHz, is shown in Figure 4-13. Noise figure as low as 7.6 dB can be achieved when LO power is 3-dBm. Noise figure increase at lowe r LO power levels as both of the switch

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62 transistors are simultaneously on for a larger fraction of period. During this time the switches act like amplifiers and contribute more noise at the output, which increases the noise figure. The switching pair transistors should be driven with large LO signals to reduce their noise contribution. In low voltage and low power environment, available LO signal is limited by linearity , power consumption and volta ge supply headroom. Noise figure performance was also observed as a function of output frequency and shown in Figure 4-14. Noise figure stayed below 13 dB for a bandwidth of 1-GHz between 2.53.5GHz. Figure 4-14. Measured noise figure vers us frequency at different LO power 4.4 Experimental Results: Na rrow-Band Down-Conversion Mixer Design emphasis of previous mixer was to achieve broad-band performance by lowering the quality factors of the input a nd output matching networks and also to achieve reasonable noise figure performance. Power consumption of the circuit increases

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63 for lower choice of quality factors. To eval uate the penalty associ ated with the wide bandwidth response another Gilbert cell downconversion mixer was designed to achieve an output bandwidth of 500MHz. The quality f actors were chosen to keep the power consumption at around half of the broad-ba nd mixer. A die photograph of the mixer is shown in Figure 4-15. Figure 4-15. Down-conversion Gilb ert-cell mixer (narrow-band) Measured input and output return lo ss is shown in Figure 4-16. The mixer achieved comparable performance as the broa d-band mixer in terms of conversion gain, noise figure and linearity characteristics, at around half power consumption compared to the broad-band design. Conversion gain wa s measured as a function of current consumption, shown in Figure 4-17. Mixer wa s able to achieve a conversion gain of around 2.8-dB at current consumption of 5mA from Vdd=1.2 V.

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64 Figure 4-16. Measured input and output return loss Figure 4-17. Measured conversion-ga in versus current consumption

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65 Table 4-1 lists the measured performa nce summary of narrow band and broadband mixer. Similar performance for narrowband mixer was obtained at half of the power consumption of broad-band mixer, whic h verifies the tradeoffs between band-with and power consumption under similar performance conditions. Table 4-1. Measured performance su mmary of broad-band and narrow-band downconversion mixers Specifications Broad-Band Narrow-Band Supply Voltage 1.2 V 1.2 V Peak Conversion Gain 1 dB 1 dB 3 dB, BW Gain 1.4 GHz 500 MHz RF-IF Isolation 36 dB 31 dB LO-IF Isolation 50 dB 45 dB LO-RF Isolation 41 dB 38 dB |S11| (-10 dB BW) 5 GHz 4.5 GHz |S22| (-10 dB BW) 1.7 GHz 0.55 GHz Power Consumption 6.9 mW 3.5 mW IIP3 -2 dBm -3 dBm LO Power 1 dBm 1 dBm 4.5 Conclusion Performance of published CMOS mixer designed in Logic CMOS process, operating at K-Band is presented. Circuits were simulated to operate around 24-GHz but the optimum frequency of operation was shif ted down due to unaccounted parasitic as described in chapter 2. The ci rcuit achieved a conversion-g ain bandwidth of 1.4 GHz at the output port and an excellent noise figure performance. Noise figure value as low as 8 dB was measured at a low LO power consum ption of 1 dBm. Compared to previous

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66 published mixers the power consumption is es pecially low. Mixer operated successfully at a low power consumption of 8 mW from a 1. 2 V supply. When used in a receiver, this mixer can significantly relax the noise figure a nd gain requirements of LNA and help to minimize the overall power consumption of the receiver. A performance summary of mixers operating in K-band frequency range is listed in Table 4-2. Table 4-2. Performance summary of mixers operating in K-Band and above Reference/ Technology RF [GHz] Gain [dB] Noise Figure [dB] Linearity [dBm] Power Consumption [mW] [10]/ 0.8m SiGe HBT 17 9.0 11.5 (DSB) -10.0 (IIP3) 18 [41]/Si Bipolar 11.2 16.1 9.4 (DSB) -14.1 (Input P1dB) 42 [42]/SiGe HBT 30 2.9 17 -1 (IIP3) 32.4 0.13m CMOS (Narrow-Band) This work 20 1 9 -3 (IIP3) 3.6 0.13m CMOS (Broad-Band) This work 19 1 9 -2 (IIP3) 7

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67 CHAPTER 5 DOUBLE-BALANCED PASSIVE RING MIXER 5.1 Introduction Passive mixers have superior frequency response and linearity characteristics as compared to active mixers [11]. A popular t opology is the balanced ring structure, where the differential LO signal is fe d to the gates of the transi stors and input and output are taken from the interconnected source and drai n nodes [42]-[43]. As there is no drain to source bias, there is no current consumption for this circuit. Mixer schematic is shown in Figure 5-1. Figure 5-1. Passive CMOS ring mixer Mixer schematic has four transistors, M1-M4. Transistors M1-M2 are driven by LO+ signal and transistors M3-M4 are driven by LOsignal, which are 1800 out of phase. When M1-M2 are on, IF port is connected to BB port with a positive polarity, when M3-

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68 M4 are on IF port is connected to BB port with a negative polarity. M1-M4 acts as switches on application of LO si gnals. Each switch is driven into the “on” and “off” state when the LO signal is applied to the gate. Fo r optimum transfer of LO power level, the LO signal should be applied along with a dc ga te bias around the thre shold voltage of the transistors, so as to make the switching acti on more efficient [44]-[45]. In the “on” state the transistor’s drain to source impedance (Ron) is equivalent to the low drain-to-source channel resistance Rds(t). In the “off state the drain-to-source impedance (Coff) is equivalent to the drain-to-source capacitor and it can be assumed that the channel resistance is very high during this stage. When driven by a sinusoidal LO signal, theoretical optimum conversion loss fo r a double balanced passive mixer is, 2 20log()3.9 LossdB (6.1) The drain to source resistance depends dire ctly on the transistor geometry, as shown {()}ds noxgsthdsL R CWVVV (6.2) where L is the gate length, n is the average electron mobility in the channel, Cox is the gate oxide per unit area and W is the gate width. Equation 6.2 shows that, minimum Rds can be achieved with a small L and a large W. Usual tendency is to use a large W, but it leads to higher capacitance be tween the gate-to-source and drain-to-source nodes, which degrade circuit performance at higher frequenc ies. Also a higher gate voltage swing can reduce the resistance. From the two stat e representation, the maximum operating frequency of the passive mixer is controlled by the Ron and Coff product. Fully differential structure of the mixer provides virtual gr ound at each port by the cancellation of even

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69 order harmonics. Because the “on” stage repr esentation of such transistor switches is a resistor, this topology can achieve broad-ba nd frequency response. The disadvantage of using such a mixer is that the LO drive re quired for their successful operation is high, which might be difficult to generate in a low power environment. LO ports are terminated with 50terminations, so as to give a better control on the amount of LO drive available for the circuit and achieve good return loss for L port. Matching was not used for both input and output ports, which makes this de sign suitable for use as an up-converter as well as a down-converter. Width of 100-m was chosen for transistors. Simulated return loss at input and output port s is shown in Figure 5.2 Figure 5-2. Simulated return lo ss at input and output ports Special consideration has to be incorporated in the layout to achieve optimum performance. Wider metal lines have been used to minimize the parasitic series resistance, in order to enable th e device to handle larger signals. Care was taken in the

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70 layout in order to achieve exact symmetry in RF, LO and IF pa ths. The chip occupies an area of 740-m 550-m. The die phot ograph is shown in Figure 5-3. Figure 5-3. Passive CMOS mixer die-photo 5.2 Experimental Results: Down-Conversion Passive Mixer The performance of the mixer was charac terized using ground-signal-signal-ground (GS-SG) probes. A DC voltage of 300-mV wa s applied to the gates along with the LO signal. Conversion gain depends on the amount of LO drive, which is required to be high for this circuit. The transistors show a be tter switching action fo r a higher LO drive, which in turn decreases the conversion loss. Measurements were performed with RF of 2.7-GHz and the IF was kept at 100-MHz. A pl ot of conversion gain with LO power is shown in Figure 5-3. The gain compression ch aracteristics were measured with different LO amplitude levels. An input 1-dB compre ssion level of -3 dBm was measured when the LO power level was 1.5-dBm. A plot to show the 1-dB compression points at different LO drive levels is shown in Figure 5-4.

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71 Figure 5-4. Measured conversion-gain vers us LO powerDown-conversion passive mixer Figure 5-5. Measured conversion-gain vers us RF powerDown-conversion passive mixer

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72 Input third order intermodul ation point (IIP3) of +7dB m was also achieved by the system (Figure 5-6). As input and output ports are symmetrical the design was also suitable for up-conversion configuration. Re sults are shown in the following section Figure 5-6. Measured IIP3 response 5.3 Experimental Results: Up-Conversion Passive Mixer For an up-converter the performance was measured to evaluate the broad-band performance of the circuit. Input freq uencies of 100MHz and 200MHz and LO frequencies of 1-GHz and 2-GHz , were used in the measurement. Circuit performance remained almost flat for all the input combin ations. Conversion gain was measured for all the inputs with a varying LO power level, conversion gain of better than -6.5 dB was observed for an LO power level of 3 dBm, wh ich is shown in Figure 5-7. Also the 1-dB compression point was measured with different input frequencies, for varying LO power level. Input referred 1-dB co mpression point of -2 dBm wa s achieved at an LO power level of 3 dBm. The measured results are s hown in Figure 5-8. Is olations performance

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73 was also measured. Isolations of better th an 22dB, 25 dB were achieved between the BBIF and BB-LO ports, respectively. Figure 5-7. Measured conversion-gain vers us LO powerUp-conversion passive mixer Figure 5-8. Measured conversion-gain ve rsus RF powerUp-conversion passive mixer

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74 5.4 Conclusion A passive ring mixer built in 130-nm CMOS technology has been presented. It can be used for down-conversion of RF signal to base-band and up-conversion of base-band signal to RF frequencies. Circuit can be used for wide range of RF input frequencies. Good conversion gain, gain compression and third order intermodul ation performance has been achieved by the design at re latively low LO power requirement.

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75 CHAPTER 6 BASE STATION RECEIVERS: DOWN-CONVERTER MODULE 6.1 Introduction Increasing demand to support multimedia applications requires high data rates. Third generation (3G) cellular wireless syst ems offer low cost, high-capacity mobile communications with data rates of up to 2 Mb it/s, with global roaming and advanced data services. For commercial applications it is required to develop low cost, high dynamicrange radios, both for base transceiver sta tions (BTS) and for mobile stations (MS). Advancement in CMOS technologies have alre ady made it possible to achieve high level of integration for hand-set transceivers but th e reduction of size and cost of base stations circuits using CMOS technology still remains a challenge. Typically base station radios use high performance but costly GaAs technol ogy, with a low level of integration and a high number of external RF passive co mponents [46]-[47]. Recently, it has been demonstrated that it is possible to meet GS M base station specifi cations using silicon BiCMOS and CMOS heterodyne receivers in 900and 1800-MHz bands [48]-[50], and BiCMOS and SiGe direct-conversion r eceivers in UMTS band [51], [52]. Universal Mobile Teleco mmunication System (UMTS) is becoming the popular choice for third generation air interface. GSM and UMTS base-station specifications impose stringent linearity and sensitivity requirement on the receiver front-end as compared to that of user terminals [53] -[54]. Unlike a handset which receives and transmits just one channel at a time, a base station system supports multiple channels simultaneously and thus requires a higher dynamic range. Receivers suitable for BTS

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76 applications must meet two demanding requi rements: low noise fi gure and high linearity. While silicon RFIC technology is steadily impr oving, it is still ch allenging to achieve noise figure (NF), linearity, and phase noise requirements with presently available devices. For heterodyne receiver s input and output third order intercept points (IIP3 and OIP3) are considered. For direct-conversi on receiver architectures second order intermodulation products can cau se corruption of the desi red signal band. For such receivers, input and output second order in tercept points (IIP2 and OIP2) must be considered [55]-[56]. This chapter discusses the perfor mance of a down-converter (LNA+down-conversion mixer) module with br oad-band performance suitable to meet the requirement of 2-G and 3-G systems. Sy stem level specifications for 2-G and 3-G BTS receivers are described in the following section. 6.2 Base Station (BTS) Receiver Specifications 6.2.1 Digital Cellular System (DCS1800) and Personal Communications System (PCS1900) Specifications DCS1800 and PCS1900 specifications can be derived from GSM 0.5.05 document [53]. These two standards esse ntially use the same specifications. Reference sensitivity level for base station receiver for both DC S1800 and PCS1900 is -104 dBm. To meet the desired BER performance the Signal to Noise ratio (S/N) of 9-dB is specified. Bandwidth (B) for both systems is 200-kHz a nd operating temperature is 290-K. Using Equation 6.1 the NF of the system can be achieved as, 17410log()refS NFSdBmB N (6-1) Equation 6.1 gives an NF value of 8-dB for both standards. For intermodulation (IIP3) requirements the references sensitivity should be maintained when two tones of interferer signals (Pint) and a signal 3-dB above the reference sensitivity are input to the

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77 receiver. Pint is -49dBm for both DCS1800 and PCS1900. Carrier to intermodulation ratio is 12-dB for both cases. Equati on 6-2 provides the IIP3 requirem ents of the receiver for a given interferer and signal power level. int int() 3 2refC PS N IIPP (6-2) IIP3 value of -8dBm for DCS1800 and 17dBm for PCS1900 can be obtained from Equation 6-2. For Direct conversion receiver s a high value of IIP2 is required. The AM suppression characteristics set the IIP2 re quirement for DCS1800 and PCS1900 and are same for both standards. A single modulated blocker, with power level of -35 dBm for normal BTS, causes the second order intermodula tion due to even orde r non-linearities in the receiver. The required si gnal should be -101dBm, which is 3 dB above the base station receiver reference sensi tivity level of -104 dBm. To keep the DC product below 9dBc, the second order intermodulation produc t (IM2) level must be lower than -110 dBm. The required IIP2 can be calculated using Equation 6-3: kerker2(2)reqblocblocIIPPPIM (6.3) Equation 6-3 shows that minimum IIP2 re quired at the antenn a input is 40-dBm, which is very stringent. 6.2.2 Universal Mobile Telecommunications System (UMTS) Specifications The requirements for a UMTS receiver ar e based on the technical specifications established by the 3rd Generation Partnership Project (3GPP). In particular, document 3GPP TS 25.104 (UTRA FDD: Radio Transmissi on and Reception) [54] covers the RF requirements for the entire base stati on. UMTS, or wide-band CDMA (WCDMA) standard is based on direct sequence spread spectrum t echnology, with code division

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78 multiple access (CDMA) scheme. User information bits are spread over a wide bandwidth by multiplying the user data with quasi-random bits (called chips) derived from CDMA spreading codes. All users in on e cell share same frequencies all the time, and signal is “spread” over th e whole bandwidth of a channel. This “spreading” of the signal results in a proc essing gain, allowing for the detec tion of signal levels below the noise floor. The receiver sensitivity is speci fied as dBm for a 12.2 kbps channel. At this level, the bit error rate (BER ) is expected not to exceed 0.1%. Eb/N0 of 5.2 is required to achieve this BER performance. For a bi t rate (R) of 12.2 kbps and bandwidth of 3.84MHz this Eb/N0 is equal to signal to noise ratio (SNR) of -20 dB. In UMTS system the quantity R/B is called as processing gain. SNR of -20 dBm implies that in UMTS system it is possible to detect signals wh ich are lower than thermal and interference power levels. This implies th at to achieve the desired BE R of 0.1%, SNR should be at least dB. Reference sensitivity requi rement for 3GPP is -121-dBm and channel bandwidth (B) is 3.84MHz. Using Equation 61, the maximum noise figure that can be tolerated is 7 dB. Thermal noise floor of a 3.84GHz channel is -108 which gets increased to -101dBm for NF of 7-dB. With the requi red dB SNR, a si gnal level of dBm could still be detected with the required BER. The IIP3 specification of the UMTS receiver is defined by intermodulation characteristics in TS 25.104 [54], which states that reference performance should be met when the following three signals are pres ent at the BTS ante nna input: a dBm wanted signal, a dBm unmodulated in terferer at 10 MHz offset, and a dBm modulated interferer at 20 MHz offset. As SNR is -20 dB, intermodulation component combined with noise can be 20 dB higher than the wanted signal a nd the signal can still

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79 be detected. In the worst cas e that intermodulation component and noise have the same power, the signal to interferer ratio doubles to -17 dB. Using Equation 6-2 an IIP3 requirement of -23 dBm can be calculated . IIP3 requirement for UMTS systems is significantly more relaxed than that for 2G GSM receivers [57]. Similar to IIP3, IIP2 requirements for direct conversion receivers are also more stringent for DCS1800 and PCS1900 and are very relaxed for UMTS band. Here a modulated blocker with average power level of -40dBm is appl ied at 10 MHz offset. Wanted signal level is -115 dBm, and an SNR requirement of -20 dBm sets th e maximum tolerable IM2 level to -95dBm. Using Equation 6-3, IIP2 is calculated to be +15dBm at the antenna connector. In summary, UMTS has a tighter specifi cation in receiver noise figure, whereas GSM (DCS1800 / PCS1900) has a tighter specifica tion in receiver linea rity. Therefore, to design a receiver chip set that meets all ba se station requirements of UMTS, DCS1800, and PCS1900, the integrated receiver should have its NF meeting the UMTS requirement of 7dB, and IIP3 and IIP2 meeting the DSC1800 requirements of -17dBm and 40 dBm respectively. Table 6-1 summ arizes NF, IIP3, and IIP2 requirements for DCS1800, PCS1900 and UMTS bands. Table 6-1. Base station receiver specifications Standard DCS1800 PCS1900 UMTS Frequency 1710-1785 1850-1910 1920-1980 NF [dB] 8 8 7 IIP3[dBm] -17 -17 -23 IIP2[dBm] 40 40 15 6-3 Design Considerations and Experimental Results: Low Noise Amplifier (LNA) and Down-converter Both chips were designed using 0.25-m CM OS process. This process offers five metal levels, with 3 m thick top level meta l for improved inductor quality factor (Q).

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80 Top level metal was also used for RF signal r outing whenever possible, as well as in the layout of CMOS devices, to minimize resist ive loss in conductor. Substrate resistivity was about 10 /cm. Inductor Q values of around 10 were achieved for inductance of 1 to 12-nH. All inductors, including the input matching inductor of LNA, were integrated on chip. 6.3.1 Low-Noise Amplifier Low noise amplifier is typically the firs t stage in wireless receivers and thus determines the sensitivity of the receiver chai n. Linearity is also an important parameter, particularly in BTS applications, since a number of wanted and unwanted signals with wide variations in signal strength can be pr esent at the receiver input. Therefore an LNA typically must exhibit low noise figure (N F) and high linearity simultaneously. Since CMOS devices exhibit minimum NF of under 0.5 dB [58] and low third-order intermodulation distortion due to near square -law current versus voltage behavior [59][60], it is possible to achieve good NF and lin earity simultaneously [61]. It was also demonstrated that it is possible to achiev e both low NF and high IIP3 for LNA’s in 0.25m BiCMOS technology, using optimum device size and bias current [62]. The schematic of the LNA is shown in Fi gure 6-1. A single st age, common source configuration was chosen for optimum linear ity and NF. The gate size of about 170-m was selected to provide best linearity and NF input matc h at the design frequency, without degrading gain signi ficantly. Minimum NF (NFmin) of this large device was measured to be 0.5-0.8 dB at 1-2 GHz, for dr ain bias of 3 V, and drain current in the range of 10-60 mA. Since the device NFmin is sufficiently low, it was possible to use series on-chip inductors for input matchi ng and still meet the NF specifications. Degeneration inductance was a dded at the source terminal, to improve the IIP3, and the

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81 input and output return losses. A current mirro r with smaller transistor size was used to set the gate bias voltage, and help with pr ocess and temperature compensation. Drain voltage is supplied through a biasing inductor, which in pa rallel with the small capacitor forms a high impedance RF choke across the th ree frequency bands of interest. Chip size for LNA is 1.2 mm x 1.1 mm . A die photograph of the LNA is shown in Figure 6-2. Figure 6-1. Broad-band low-noise amplifier Figure 6-2. Low-noise amplifier die-photo

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82 Figure 6-3 shows the LNA S-parameters across the three fr equency bands of interest. Gain of over 12-dB is achie ved across the whole bandwidth, with S22 better than -15dB, and S11 close to -10dB, without any external matching. Figure 6-3. Measured LNA S-parameters The LNA also achieves good noise figure pe rformance. Noise figure is below 1.6 dB in all three bands as is shown in Figure 6-4. In addition, input P1dB of above 4dBm and IIP3 as high as 13dBm were achieved as is shown in Figure 6-5. LNA performance was evaluated for bias current from 10 mA to 40mA, with minimum performance degradation. With 3V bias voltage, bias cu rrent of 28 mA was f ound to be the optimum bias point for best linearity and noise figure. With half th e drain current, IIP3 is lowered only by about 1dB, and NF is increased by only about 0.2 dB. This makes CMOS amplifier performance very r obust to changes in bias c onditions due to process and temperature variations.

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83 Figure 6-4. Measured nois e figure versus frequency Figure 6-5. Measured input P1dB and IIP3 versus frequency

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84 6.3.2 Down-Converter The down-converter consists of an active LO balun and a passive mixer. Passive mixers achieve a higher linearity than active mixers, and are thus more suitable for base station receivers. The resistive FET mixer, traditionally implemented using GaAs FET devices, has a very high input IP3 compared w ith other mixer types [11]. Due to the fact that a single MOSFET transistor device can be used as a switch, CMOS mixers can also be realized in passive form, achieving sim ilar performance at much lower cost [42]. In addition, passive CMOS mixers require no DC bias, and thus exhibit lower 1/f noise [63], [64], making them particularly suitable for di rect conversion architectures. Schematic of the down-converter block is shown in Figure 6-6 Figure 6-6. Down-converter (passive mixer, LO buffer and IF buffer)

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85 The LO buffer amplifier converts single-end ed LO input to differential output of sufficient power (around 10-dBm) to drive th e double-balanced re sistive MOSFET mixer for high IIP3. The circuit configuration is a di fferential amplifier with one input terminal AC grounded. Cascode structure provides very good isolation between output and input that makes impedance matching easier. A common-mode rejection output impedance matching network and an LC resonator at coupled source node provide enhanced common mode rejection that keep s the phase bala nce close to 1800. The chip size is 2.4 mm x 1.5 mm. A die photograph of the downconverter is shown in Figure 6-7. Figure 6-7. Down-convert er module die-photo The down-converter return loss at IF, RF (and LO) ports is shown in Figure 6-8 and 6-9 respectively. RF return loss is lower th an -15dB over the three bands of interest, while it is close to -10dB at the LO port , which is less critical for the receiver performance. IF return loss is lower th an -12dB for frequencies up to 500 MHz, indicating that the downconverter is suitable for a wide ra nge of IF frequencies, as well

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86 as for direct conversion architect ure. The chip operates with a bias voltage of 3V and the current consumption is 40mA. Figure 6-8. Measured re turn loss at IF port Figure 6-9. Measured return loss at RF and LO ports

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87 A conversion loss of better than -7dB wa s obtained for the frequency ranges of all standards as is shown in Figur e 6-10. Lowest conversion loss of -6.5 dB was achieved at 2-GHz for an LO power of 4-dBm. Figure 6-10. Measured convers ion gain versus frequency Figure 6-11. Measured input P1dB, IIP3 and IIP2 versus frequency

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88 Measured input P1dB, IIP3 and IIP2 for different RF frequencies are shown in Figure 6-11 and were found to be above 8-dBm, 17-dBm and 57-dBm respectively for the frequency range of 1.7-GHz to 2.5-GHz. This highly linear second and third order response makes the use of this downconverter suitable for both he terodyne and direct conversion receivers. 6.4 System Level Modeling and Simulations To evaluate the performance of the chip set when implemented in base station receivers, both heterodyne and direct-conversion architect ures were designed and simulated. Standard off-the-shelf parts were selected for external components. Systemlevel receiver chain performance was simu lated using Agilent ADS. The behavioral models for the LNA and the down-converter were constructed in Agilent ADS based on the measured data. These models incorporate both linearity and NF data as a function of frequency, in addition to the S-parame ters. The Amplifier, DataAccessComponent (DAC), Mixer and Mixer2 components in ADS library have been used for the modeling purpose. The measured data for the S-parame ters, the noise figure and the linearity (P1dB, IIP3 and IIP2) can be specified in a file for di fferent frequency values and can be selected based on an index mapping to a particular oper ating frequency. This index can be chosen for a particular frequency band and linked to the stored values of the performance parameters in the file which is accessed by the DAC component. The DAC in turn is invoked by the amplifier/mixer instance. The performance parameters are then retrieved from the data stored in the file. This beha vioral modeling provides a convenient and fast way of measuring the system level performance such as the noise figure and the intermodulation performance of the complete receiver chain based on the measured performance of individual blocks.

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89 6.4.1 Heterodyne Receiver Performance The indirect-conversion architecture is shown in Figure 6-12. Two LNA stages were used to provide sufficient gain. For hete rodyne receiver archit ecture, the choice of IF frequency is critical to th e system performance, mainly due to the high-order mixing products (spurs) generated af ter down-conversion mixer. Figure 6-12. Heterodyne receiver architecture The high-order spurs may cause the receive r to fail the system test when strong blockers are present. In this design the IF frequency was chosen at 170 MHz. Calculation of NF includes components from the antenna co nnector to the analog-to-digital converter, whereas the calculation of IIP3 includes com ponents from the antenna connector to the channel-select filter where out-of band thirdorder intermodulation products are removed. As indicated in Table 6-2, the heterodyne r eceiver chain achieves NF lower than 4.5dB and IIP3 higher than -5dBm in all three bands, thus meeting and exceeding DCS1800, PCS1900 and UMTS requirements outlined in Table 6-1. Table 6-2. Simulated receiver chain performance Heterodyne Receiver Standard DCS1800 PCS1900 UMTS NF [dB] 4.2 4.3 4.3 IIP3[dBm] -4.4 -3.7 -3.1 Direct Conversion Receiver NF [dB] 5.4 5.6 5.8 IIP2 [dBm] 40.5 42.4 44.2 IIP3[dBm] -0.4 0.3 1.2

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90 6.4.2 Homodyne Receiver Performance The receiver performance was also evalua ted in direct-conversi on architecture, as shown in Figure 6-13. Compared to the heter odyne design, this ar chitecture is simpler and requires no image reject filter. A passive chan nel-select filter is used in this design so that its linearity would not be a limiting fact or of the system linearity performance. Since the RF input port of the mixer is AC -coupled, the low frequency second order intermodulation component at the LNA output is significantly attenuated. However, the LNA amplifies in-band blockers. Therefore th e linearity of the mixer will dominate the IIP2 performance. Since GSM specifications set a tighter IIP2 requirement, a 3-dB attenuator is inserted before the second stag e LNA to improve the linearity and meet the stringent IIP2 specifi cation for DCS1800. Figure 6-13. Homodyne (direct-c onversion) receive r architecture As shown in Table 8-2, in this architect ure IIP3 and IIP2 of better than 0-dBm and 40-dBm respectively were achieve d in all three bands, with a noise figure of less than 6 dB, indicating that 2G and 3G specificati ons are met. Although the 3-dB attenuator increases NF slightly, the improvement in lin earity increases IIP2 to meet the stringent GSM requirement. Considering the tradeoff betw een noise figure and linearity, a tunable attenuator can be used to set the optimal value to meet the requirement in each band.

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91 6.5 Conclusion Measured performance of a broad-band LNA and down-converter are presented. The circuits achieved good linearity as well as noise figure for a wide frequency range. Measured performance of the blocks is mode led in ADS which is then used to perform system level simulations to verify the use of the designed circuit. It has been shown that with the LNA and down-converter module, th e noise and linearity specifications of DCS1800/ PCS1900 and UMTS bands can be me t in both super-het erodyne as well as direct-conversion receiver. The results successf ully demonstrate that CMOS devices can be used for base station rece iver applications that have stringent linearity requirements.

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92 CHAPTER 7 LOW-PHASE NOISE HIGHPOWER OSCILLATOR 7.1 Introduction Though the semiconductor industry in today’s world is dominated by silicon transistors, Gallium Arsenide (GaAs) based High Electron Mobility Transistors (HEMTs) and hetero-junction bipolar tran sistors (HBTs) have a reputa ted niche for high-frequency capabilities. Gallium Nitride (GaN) devices, on the other hand, have emerged as the material of choice for handling both high freque ncies and high power. As far as power is concerned however, GaAs-based devices ar e not ideally suited due to the smaller bandgap of GaAs. In addition to being a narrow bandgap device, GaAs substrate has higher thermal resistivity than silicon, which makes it difficult to remove the heat generated in high-power applications. Also, th e critical electric field of GaAs is about one-fifth of GaN. Silicon Carbide (SiC) me tal-semiconductor field-effect transistors (MESFETs) can be a good choice for high power applications because of their excellent thermal conductivity [65]-[68]. However, SiC has very low electron mobility compared to GaN which is due to the absence of hetero junction technology in th is material system. Also SiC substrates are expe nsive and have very low manuf acturing yield. These factors make it difficult for SiC to compete in the cost-sensitive commercial market. Silicon Germanium (SiGe) HBTs are another alte rnative which find applications in many microwave and mixed signal products. SiGe HBTs can offer cost effective high performance products previously unavailable on a silicon platform. However, the SiGe HBT device structure remains a relatively lo w power configuration and is an unlikely

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93 candidate for high power applications. Another device suitable for high power applications is the Silicon laterally diffused metal-oxide semiconductor (LDMOS). These structures result from pushing the limits of silicon power MOS transistor technology to its high-frequency limits. Silicon LDMOS offers excellent cost and performance ratios in this segment. However, due to the increasi ng demand of speed, power handling capability and linearity of next-generation system s, continued use of Silicon LDMOS is questionable. GaN devices offer an advantag e over other materials in terms of power handling, high frequency operation as well as cost. Table 7-1 lists the properties of different substrate materials. Table 7-1. Comparison of different substrate materials Property Silicon GaAs SiC GaN Suitable for high power Medium Low High High Suitable for high frequency Medium High Medium High HEMT Structure No Yes No Yes Low Cost Yes No No Yes GaN has an energy gap value that approaches 3.4-eV at room temperature, enabling GaN devices to support peak internal electric fi elds about five times higher than silicon or gallium arsenide (GaAs). Higher electric field strength results in higher breakdown voltages a critical attribute for handli ng high power requirements and for achieving much higher efficiencies th rough the use of higher supply voltages. GaN devices have higher electron mobility than Si and GaAs which can further be enhanced by using AlGaN material with GaN. Efficiency refers to the ability of the transistor and amplifier/oscillator to convert electrical power into output power. One way of achieving higher efficiencies using GaN is through highe r supply voltages. GaN devices are mostly

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94 suitable for power amplifiers [69]-[70]. Higher data rate modulation schemes and multicarrier amplification systems currently being designed require high-linearity power amplifiers, which depend on power transist ors with high compression points, excellent thermal stability and increasingly high fre quency response. High power density allows a smaller chip to handle large amount of power which can resu lt in more chips per wafer and hence lower costs. GaN oscillators ha ve shown to achieve high output power and good phase noise performance [71]-[74]. 7.2 Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT): Measurements and Modeling GaN HEMT structures were available as disc rete parts and their use in the design of a circuit required the development of suita ble models for simulations. Hence, IC-CAP modeling software was used to obtain Curti ce cubic model for the measured DC and AC performance and the parameters were furthe r optimized in Agilent Advanced Design System (ADS) simulator. Figure 7-1 show s a die photograph of the HEMT device. Simulated model performance matched closely to the measured data for both AC and DC performance. Figure 7-2 and 7-3 shows the ma tching of measured and simulated AC and DC performance respectively. Figure 7-1. Gallium Nitride HEMT S G D S S S

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95 Figure 7-2. Measured and mode led S-parameter performance Figure 7-3. Measured and m odeled DC I-V performance

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96 Table 7-2 lists the extracted parameters of the developed Curtice-cubic model which closely matched the measured behavior of the HEMT device. Table 7-2. Extracted Curtice-cubic model parameters Parameter Value Parameter Value Beta 8.527m Rgd 54.12 Gamma 2.35 Rd 7.2 A0 284.6m Rg 1 A1 138.7m Rs 12.4 A2 21.05m Ld 23pH A3 1.035m Lg 10pH Cgs 1480fF Ls 10pH Cgd 55.89fF N 4.3 Cds 80fF Is 85.5nA 7-3 Design Consider ations: Oscillator To evaluate the performance of the HE MT device, an oscillator circuit was designed at 2 GHz. Simulation re sults showed that the oscilla tor could achieve an output power level of 24.0 dBm at a current of 49 mA from a 10 V supply. The simulated efficiency for DC-to-RF power conversion wa s 51%. Better efficien cy implies a better phase noise response. Schematic of the os cillator circuit is sh own in Figure 7-4. Capacitive degeneration was us ed at the source. This provi des a negative resistance looking into gate node of the HEMT. A large si zed inductor was placed in parallel with the capacitor to provide DC current path from Vdd to ground. Transmission lines network

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97 was used at the gate node which provides an inductive component at the frequency of operation. Length of the transmission lines was adjusted to make the circuit oscillate at a frequency of 2 GHz. Gate and drain biasi ng was provided using large inductors which acts as short to DC current. Output si gnal was taken at the drain node through a transmission line with characteristic impedance of 50 . The circuit was fabricated on FR4 board (dielectric constant 4.4, loss tangent 0.02, thickness -1.6mm). A die photo of the oscillator circuit is shown in Figure 7-5. Figure 7-4. Negative impedance osc illator circuit (Oscillator I) Figure 7-5. Fabricated oscillator circuit boa rd (Oscillator I) Another oscillator circuit was built in a common source configuration. The schematic of the circuit is shown in Figure 7-6.

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98 Figure 7-6. Feedback oscillat or circuit (Oscillator-II) A phase shift of 1800 is provided by the common source configuration and a feedback circuit was built using transmissi on lines and bypass capacitors which provides another 1800 of phase shift for the signal at 2-GHz. This circuit also was fabricated on FR-4 substrate. Gate and drain biasing was provided using large inductors which acts as short to DC current. Output signal was take n at the drain node through a transmission line with characteristic impedance of 50 . A die photo of the oscill ator circuit is shown in Figure 7-7. Figure 7-7. Fabricated oscillat or circuit board (Oscillator-II) 7.4 Experimental Results The circuit ware designed to operate at 2.0-GHz but actually operated optimally at 1.88-GHz and 1.73 GHz respectively. Circuit -I achieved an output power level of 21.5RLoad

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99 dBm at a current consumption of 50.4mA from a 10 V supply and circuit-II achieved an output power level of 20.5-dBm. Measured c onversion efficiency from DC power to RF power was 28% and 16% respectively. The main cause of such reduction in efficiency from simulated value is the change in behavi or of the circuit afte r including bond-wires. In simulations, the inductan ce associated with the bond wires was taken as 1mm which was less than the actual inductance. Measured DC current under similar bias condition as the stand alone device was less which leads to a decrease in the e xpected power level. Measured spectrum of the oscillator I and II ar e shown in Figure 7-8 and 7-9 respectively. Power level of the second harmonics signal is 21.0 dB below fundamental signal power level for circuit I and is 20 dB below for circuit II. Tuning range of the oscilla tor I was 110-MHz when the gate voltage was varied from -0.5 V to 3.5 V and was 76-MHz for oscill ator II. Gate capacitance changes with the change in bias voltage which causes a shift in the frequency of oscillation. Figure 7-10 and 7-11 shows a plot of the operating fre quency and respective power levels with different gate bias voltages for circuit I and II respectively. Output signal power level was more than 17.0 dBm for the entire tuning range for both the osci llators. A plot of achieved efficiency with differe nt gate bias voltages is s hown Figure 7-12. According to Leeson’s formula phase noise of an oscillator circuit is i nversely proportiona l to output power level. 2 0 211 ()10log11 22c m msmff FkT Lf fQPf (7-1) where Q is the loaded quality factor, f0 is the oscillation frequency, fc is the flicker corner frequency of the device, fm is the offset frequency and Ps is the output power.

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100 Output power level has been maximized to achieve better phase noise performance. Phase noise performance was measured usi ng HPE5500 Frequency Discriminator. Phase noise response for the circuits are shown in Figure 7-13 and 7-14 respectively. At 1-MHz offset phase noise is -130dB c/Hz from the 1.88 GHz carrier for circuit I and -126dBc/Hz from the 1.73 GHz carrier for circuit II. Figure 7-8. Measured output spectrum of oscillator-I Figure 7-9. Measured output spectrum of oscillator-II

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101 Figure 7-10. Frequency and output power ve rsus gate bias vol tage (Oscillator-I) Figure 7-11. Frequency and output power vers us gate bias volta ge (Oscillator-II)

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102 Figure 7-12. Measured DC-toRF conversion efficiency versus gate bias voltage Figure 7-13. Measured phase noise vers us offset freque ncy (Oscillator-I)

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103 Figure 7-14. Measured phase noise vers us offset frequenc y (Oscillator-II) 7.5 Conclusion Design and measured results of two high pow er oscillator circuit fabricated on FR4 substrate using high power GaN HEMT are pr esented. Output power level of 21.5-dBm and 20-dBm were achieved at frequency of 1.88GHz and 1.71 GHz. A DC-to-RF conversion efficiency of 28% and 16 % was achieved by designs I and II. The designs achieved comparable performance as previ ously published results on AlGaN/GaN HEMT oscillators [72]-[74].

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104 Table 7-3. Performance summary of GaN oscillators Reference Fundamental Frequency [GHz] Fundamental Power [dBm] Efficiency [%] Phase Noise 100 kHz 1MHz [dBc/Hz] [72] 6 27 13.9 -92 -120 [73] 5 20.5 14.1 -105 -123 [74] 4.16 25.9 8.8 -86.3 -115.7 this work 1.71 20 16 -98 -125 this work 1.88 21.6 28 -102 -130

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105 CHAPTER 8 HIGH-POWER RECTIFIER USIN G GALLIUM NITRIDE DIODES 8.1 Introduction Portable device market has grown exponen tially and continued efforts have been undertaken to make things small as well as ‘wir eless’ for ease of use. In order to fully exploit the benefits of “wireless” it is imperative that the wireless communication systems are endowed with on-board energy ha rvesting devices to power themselves. The RF/microwave technologies bring to fore their applicability to Wireless Power Transmission (WPT). WPT applications i nvolve transmission of very high power microwave signals over large distances. WPT is suitable for space applications as well as earth-based remote terrain for distribution of electricity. Historically, the idea of WPT began over 100 years ago as a concept propos ed by Tesla. Continuing efforts for WPT were carried by researchers in Japan and U.S. A which did not prove to be successful for commercial use. Due to the abstruse nature of problems associated with generating high power at microwave frequencies, WPT was conf ined to being a highly futuristic research goal and was never really close to a practical implementation. Due to advanced research in the field of microwave tubes, it became possible to generate high power at microwave frequencies. In 1960, Raytheon Company de veloped high-power microwave tubes which had the (Direct Current-to-Radio Frequency) DC-to-RF conversion efficiency of 81%, which further led to the m odern era of WPT [75]. Later on, Raytheon developed a rectenna (antenna and rectif ier) circuit which achieved good (Radio Frequency-to-Direct Current) RF-to-DC conversion efficiency. Con tinuing efforts led to increased RF-to-DC

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106 conversion efficiencies. Best conversion efficiency ever recorded was achieved by Brown, Raytheon Company [76] . A conversion efficiency of 90.6% was achieved at a microwave power level of 8 W, using GaAs-P t Schottky barrier diode. Traditionally, high frequency communication is c ongenial for high directivity and low transmission losses. Experiments were also carried to realize WPT at higher frequencies (35-GHz) [77]-[78]. This was done in order to achieve reduction in the size of the transmitting and receiving antenna and to increase the transmission ra nge. The components required to generate high power levels at 35-GHz were expensiv e and the efficiency was also not good. However, as system needs arise and devi ce technologies advance, WPT at higher frequencies may be practical in near future. Today, a wide spectrum of problems can be addressed using WPT. Spatially separated intractable sensors can now be pow ered wirelessly, thereby eliminating the need for human maintenance, which was indi spensable previously due to the necessity for timely replenishments of portable power s ources. It also finds usage in a number of military applications where power could be transmitted to sensors located in hostile environs. Also sharing the same microwave spectrum are the ISM (I ndustrial, Scientific and Medical) applications in which a growi ng interest has been demonstrated for WPT (Wireless Power Transmission) systems. For civilian applications, perennially running wireless devices like cell phones and biological electronic accessories like pacemakers are a few examples. 8.2 Properties and Principles of Beamed Microwave Power Transmission for Free Space Transmission Beamed microwave power tr ansmission has the following unique features as a means of transferring energy fr om one point to another,

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107 No need for massive cables for energy transportation from source to destination Transfer of energy at the speed of light and flexibility to ch ange direction of energy transfer No energy is lost in transmission in space through vacuum and very little loss in Earth’s atmosphere at lower frequencies Energy transfer between points is in dependent of grav itational force between the source and destination Collection efficiency between the transmitter and receiver antenna through free space if directly related to th e sizes of the transmitter and receiver apertures, the distance over which the energy is being sent and fre quency of the microwave beam. A relationship between these parameters has been studied and experimentally ve rified by Goubau’s and other. The relationship between the parameter and aperture to aperture collection efficiency is shown in Figure 8-1, wher e is given by given Equation 8-1, [79] Figure 8-1. Collection efficiency between receiver and transmitter apertures as a function of Goubau’s parameter

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108 trAA D (8-1) where, At is the transmitter area aperture, Ar is the receiver area aperture, is the wavelength of microwave beam and D is th e separation between the two apertures. Collection efficiency is also affected by atmospheric attenuation which is related to operating frequency and weather conditions. In order to achieve very high collec tion efficiencies the transmitted beam characteristic should be truncat ed Gaussian tapered distribu tion with very low side band levels. A tapered distribution results in a higher power density at the transmitter aperture. The choice of the taper depends on the syst em constraints of collection efficiency, sidelobe levels, peak power density, and si ze of the apertures. A tapered Gaussian distribution at the transmitter results in a si milar distribution at th e receiver. Conversion efficiency at the receiver is strongly relate d to the power density distribution across the receiver aperture. With the assumption of a uni form taper at the transmitter and negligible mismatches the directivity can be expressed as, 0 24tmA D (8-2) This directivity expresses the gain factor by which the main beam is amplified in a certain direction. Atm is the maximum effective transmitter area. For aperture antennas Atm is same as At. The magnification is reduced by d ecay of field strength by a factor ( 21 4 D). Using directivity gain and decay e xpression the peak power density at the center of the receiver aperture at a distance D from the transmitter can be expressed as, , 22 tt dcenter A P P D (8-3)

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109 where Pd,center is the peak density of receiver power which is achieved at the center of the aperture. Power density and achieved DC output power across the receiver follow the same distribution as the transmitter. Gaussian distribution at the receiver is specified in terms of peak power density and half pow er beam bandwidth (HPBB) which can be approximately written as [80], 2 03240032400 4tHPBB DA (8-4) Using HPBB the half power beam radius can be achieved for the Ga ussian distribution on the receiver aperture which can be expressed as 0360hpHPBB rD (8-5) The Gaussian power density distributi on on the receiver aperture is given by 2 , 2()exp()ln(2)ddcenter hpr PrP r (8-6) Total power received can be obtained by inte grating the power density distribution over the aperture area. Average power density is given by total power divided by the total area, which can be written as (). ,drx daverage rxPrdA P A (8-7) Equation 8-7 shows that for given total received power leve l a high value of Pd,average requires a smaller receiver area. Power handling capability of the receiver depends on material type of antenna, total antenna area and the power density ra ting of the rectifying elements. Power handling of rectifying diode s is related to their breakdown voltage. Rectifying elements are the bottleneck to achie ve high efficiency at higher power density

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110 levels. To increase the power handling capabilit y of this bottleneck link it is required to use diodes that give high efficiency at hi gher power levels. GaN diodes with very high power handling capability can serve as a good candidate for WPT systems involving very high power density transmission. 8.3 Wireless Power Transmission (WPT): System Configuration Wireless power transmission system can be viewed as a system that transfers electrical power from one location to another without support of actual cables. WPT system can be integrated to other systems at relatively low implementation cost. It was estimated that power carried th rough a microwave beam can be four times less expensive than electricity produced by phot ovoltaic panels [81]. Most important requirement for a WPT system is to achieve high overall tran sfer efficiency (DC-to-DC). WPT system consists of three major building blocks as shown in Figure 8-2. The first block converts the DC (or AC) power to microwave energy. Microwave energy is then radiated through an array of antennas and converted to a focuse d beam. This focused beam is then radiated across free space towards the collector antenna. Microwave energy is then collected using receiver antenna which is then rectified back to DC power according to rectenna efficiency. The choice of antennas used at tr ansmitter and receiver ends depends on the power handling capability of the devices and th e collection efficiency. Overall efficiency of the WPT system can be divided in th ree sub-efficiencies: DC-to-RF conversion efficiency ( t), collection efficiency ( c), RF-to-DC rectification efficiency ( r). To achieve maximum system efficiency it is required to maximize the efficiency of individual stages. Efficiency of a system can be expressed as the ratio of useful output power to the total input power deliver ed to the system. (Equation 8-8)

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111 Figure 8-2. Simplified wireless power transmission system x100 %out inP Efficiency P (8-8) For the transmitter, it is required to achieve high levels of microwave power from DC. Vacuum tube devices such as magnetron can efficiently convert DC power into RF power. Magnetrons with DC-to-RF conversion e fficiency in the range of 70% to 85% are available in lower frequency ranges of 15 GHz. Magnetrons are ch eap devices and can provide high power levels at good efficiency compared to t ypical solid-state FET device. Suitable choice of antenna type and size is re quired for both transmitter and receiver end. Slotted waveguide antenna can be used at the transmitter end when magnetrons are used as RF sources. Slotted waveguide antennas ar e a suitable choice for transmission of RF power when magnetrons are used as the RF source. These antennas have high efficiency and high power handling capability. Such structur es can also provide a low cost solution. Efficiency of antenna is defined as the ratio of antenna gain and directivity. A large number of antenna and sources need to be used to achieve sufficiently high RF power levels. The radiated RF power should be effi ciently collected by a receiver antenna which

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112 is usually larger in size compared to transmitter antenna. For a constant collection efficiency at fixed operati ng frequency, the parameter is constant and transmitter and receiver aperture area product is also constant as described in Equa tion 8-x. Transmitter antenna size can be maximized to enhance the beamed characteristics but is limited by the approximation of far field region of operation which depends on the separation between the receiver and transmitter. Typically receiver aperture area is kept larger than transmitter to efficiently collect the radiat ed energy. An array of smaller antenna elements which are connected to the rectifier circuit comprises the w hole receiver system. In order to achieve a reduction in the number of antenna elements, it is required to collect higher power levels per unit area which can be used by the rectifier circuit to achieve high DC output power. RF-to-DC conversion e fficiency of a Schottky barrier diode at higher power levels is limited by the breakdo wn voltage. GaN diodes prove to be a suitable candidate for rectification when RF input power levels are very high because of their excellent power handli ng capabilities. CMOS and GaAs Schottky diodes have fewer parasitic and can provide good conversion efficiency at hi gher frequencies [82]-[83]. However these devices suffer from the limitatio n of requiring many such devices in order to achieve larger output voltages. This is turn , leads to an increase in the overall area as the requirement for the number of antenna elements also increases. GaN Schottky diodes are suitable for applications requiring hi gh DC voltage levels, which becomes possible due to their high breakdown voltages. The fo llowing section describes the relationship between diode parameters and achievable effici ency at different power levels and load conditions.

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113 8.4 Effect of Diode Parameters on RF-to-DC Conversion Efficiency Diode conversion efficiency d is key measure to determine the overall efficiency of the WPT system. Diode efficiency is defi ned can be defined as the following ratio, dc output power RF power incident on the dioded (8-9) Efficiency of the rectifier circuit at a pa rticular frequency depends on the electrical parameters of the diode. A diode model suggest ed in [84]-[85] is us ed to approximately predict the behavior of rectification efficiency. Figure 8-3 Equivalent representa tion of Schottky barrier diode In Figure 8-3, Rs is the series resistance, Vbi is built in potential, Cjo is the zero bias junction capacitance and V0 is the DC voltage level across the load resistance RL. The model takes into account the electrical parame ters of the diode and the losses at the fundamental frequency of operation only. Eff ect of other harmonics is assumed to be negligible. A dynamic variable on which depends on the input power applied to the diode is defined as,

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114 tan 1s onon bi L oR V R V (8-10) Closed form equations for efficiency were determined which are expressed below [85]. RF-DC rectification efficien cy can be expressed as, 1d A BC (8-11) 2 21 111.5tan 2cosbi L onon soonV R A RV (8-12) 22 21tan 2cosLsj bion on oonRRC V B V (8-13) 1(tan)bibi L onon sooVV R C RVV (8-14) Equations 8-11 8-14 give an estimate of the maximum achievable efficiency for diode with fixed parasitic valu es when the RF input power le vel is changed. To get an estimate of the efficiency values with varying RL, V0 can be kept cons tant in Equation 8.10 and on can be determined for different RL values. GaN diode used in this work had Rs=19.5 , Cjo=1.4pF and Vbi=1.3 V. For the chosen V0 and RL values, output DC power available at load can be determined using Equation 8.15. Corresponding values of efficiency with available DC output power level gives the amount of input RF power level. 2 0 DC LV Power R (8.15) D C RF dPower Power (8-16)

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115 Efficiency has been plotted with different RL values for three different values of V0 (20-V, 25-V and 30-V) in Figur e 8-4. Plot of efficiency versus the corresponding input power level is shown in Figure 8-5. Figure 8-4. Efficiency versus load resistance Figure 8-5. Efficiency ve rsus input power level

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116 Conversion efficiency increas es with an increase in RL for constant V0 and then saturate with further increase in RL values. A larger chosen value of V0 helps to achieve better efficiency. Considering the achievable efficiency, RL and V0 values input RF power level can be obtained. A list of RL, efficiency and corresponding input power level is shown in Table 8-1. It can be seen that maximum achievable efficiency increases with an increase in RL value when RF power level is simultaneously decreased. Maximum efficiency of around 80% can be achieved for RL values greater than 2000 and input power level of around 25 dBm. Table 8-1. Input power level vers us corresponding efficiency and RL values V0 = 20 V V0 = 25 V V0 = 30 V Load Resistance [ ] Eff. [%] Input Power [dBm] Load Resistance [ ] Eff. [%] Input Power [dBm] Load Resistance [ ] Eff. [%] Input Power [dBm] 210 56.80 38.75 238 58.5 36.50 216 51.4 35.17 408 67.30 35.15 400 66.5 33.65 400 65.7 31.83 617 72.60 33.00 610 72.0 31.52 633 71.3 29.47 825 75.70 31.60 820 74.8 30.00 808 73.6 28.27 1000 77.50 30.60 1000 76.6 29.10 1044 75.7 27.04 1250 79.20 29.60 1380 78.8 26.80 1250 76.7 26.28 1560 80.50 28.55 1640 79.8 25.90 1500 77.9 25.25 1970 81.70 27.50 2080 80.7 25.50 2190 79.1 23.63 2530 82.50 26.30 2530 81.2 24.85 2485 79.3 23.07 3090 82.80 25.45 3060 81.4 24.00 3030 79.4 22.20 4100 82.60 24.20 4070 81.2 22.75 4120 78.9 21.00 5150 82.40 23.30 5110 80.6 21.80 5050 77.0 20.12

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117 Theoretical estimation of achieved effici ency was also desired for changing V0 conditions when RL was kept constant. Different values of on were obtained from Equation 8-10 and efficiency was calcula ted using Equation 8-11. The corresponding input power level was calcul ated from efficiency, RL and V0 values. Plots of efficiency versus V0 and input power level are shown in Figure 8-6 and 8-7 respectively. Figure 8-6. Efficiency vers us DC output voltage level Figure 8-7. Efficiency ve rsus input power level

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118 Conversion efficiency increas es with an increase in V0 for constant RL. In actual devices, efficiency starts to fall when V0 becomes higher than ha lf the breakdown voltage of the device. Considering the achievable efficiency, RL and V0 values of the input RF power level can be obtained using E quations 8-8 and 8-9. A list of RL, efficiency and corresponding input power levels is shown in Table 8-2. It ca n be seen that the maximum achievable efficiency increas es with an increase in RL value when RF power level is increased. Maximum efficiency of around 80% was achieved for V0 values greater than 30 V and input power level of around 35 dBm. Table 8-2. Input power level vers us corresponding efficiency and V0 values RL = 500 ohm RL = 1000 ohm RL = 1500 ohm Output Voltage (V) Eff. (%) Input Power (dBm) Output Voltage (V) Eff. (%) Input Power (dBm) Output Voltage (V) Eff. (%) Input Power (dBm) 2.32 46.64 13.63 2.85 51.40 15.00 2.35 46.5 13.75 5.72 59.20 20.43 5.50 62.40 19.86 5.90 64.0 20.40 7.60 62.17 22.69 11.63 71.30 25.78 11.00 72.4 25.30 11.00 65.24 25.73 15.64 73.70 28.22 15.00 75.5 27.75 19.40 68.47 30.40 18.09 74.70 29.42 20.90 78.2 30.50 24.80 69.47 32.48 21.39 75.70 30.82 25.90 79.5 32.30 30.40 70.15 34.20 23.52 76.30 31.61 33.90 80.90 34.5 39.10 70.83 36.25 29.28 77.30 33.45 48.65 82.30 37.6 45.63 71.18 37.35 38.64 78.40 35.80 62.00 83.00 40.0 54.68 71.53 39.22 45.90 78.90 37.27

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119 Results presented in Table 8-2 show that efficiency increases with an increase in the output voltage level, when the input power level is in creased. In order to achieve highest efficiency, a higher load at a high i nput power level is required. This observation is in contrast to the observa tion from Table 8-1, where highe st efficiency was achieved at higher load resistance values at lower input power levels. The tw o behaviors contrast with each other and it can be concluded that there exists an optim um load resistance value for a desired input power level that gives the highest RF-to-DC rectification efficiency. It was concluded that a resistance RL=1000 gives highest ef ficiency of 80% when operated at a power level of around 30 dBm. 8.5 Experimental Results: Gallium Nitride Ring Diodes GaN Schottky diodes were available in a ri ng structure. Four different sized diodes were available. Due to limitations imposed by minimum size required for wire-bonding in such a structure, only the biggest size diode was suitable for use. Inner diameter of the diode was 200-m. Due to their very high junction capacitance value; these diodes were suitable for operation only at lo w frequencies. A die photo of the ring diode is shown in Figure 8-8. Figure 8-8. Gallium Nitride ring diode device

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120 The diode had a very high break-down volta ge (> 120-V) which is essential for high voltage RF-to-DC rectificat ion. Forward bias characteri stics of the diode are shown in Figure 8-9. Diode had a series resistance of 10 and a junction capacitance of 5 pF. Figure 8-9. Forward DC-IV char acteristics of GaN ring diode Figure 8-10. Measured RF-to-DC conversion efficiency and DC output voltage versus input power

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121 Good efficiency could only be achieved at 300MHz. A plot to show the measured efficiency and output voltage level versus th e input power is shown in Figure 8-10. To achieve better efficiency at higher frequenc y level, it was required to minimize the parasitic capacitance value. Smaller sized ring diodes could not be used because of constraints of wire bonding. HE MT devices were available wh ich could also be used as rectifier diodes. Experimental results of RF -to-DC rectification e fficiency using HEMT devices are described in the following section. 8.6 Experimental Results: Gallium Nitride HEMT Diodes In order to achieve good efficiency at higher frequency level, junction capacitance plays an important role as was the cas e with GaN ring diodes. GaN HEMTs were available which had lower junction capacitanc e compared to ring diodes. A die photo of the HEMT which was used as a Schott ky diode is shown in Figure 8-11. Figure 8-11. Gallium Nitride HEMT device Diode behavior can be achieved using a HEMT by connecting the drain and gate node of the device. Due to the layout of the device, it was diff icult to connect the gate and drain together withou t introducing unwanted parasitic inductances. Therefore, only the gate-source diode was used. DC and small si gnal parameters were measured and diode model was derived using IC-CAP modeling so ftware. Model parameters of diodes used S G D S S S

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122 were Is = 7.1 nA, N=3.8, Rs = 19.5 , BV > 45V, Cjo=1.4pF. A plot of measured and modeled forward bias charac teristics of the HEMT diode s is shown in Figure 8-12. Figure 8-12. Forward DC-IV char acteristics of HEMT diode A half wave voltage-doubler configurati on has been used owing to its ability to achieve higher voltage output as compared to a single rectifier diode [86]-[87]. Single diode circuit on the other hand has the advant age of simplicity and lower cost. Figure 813 shows the schematic of the rectifier circuit. Figure 8-13. Voltage-doubl er rectifier circuit X

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123 In Figure 8-13, one Schottky diode is placed in parallel with the input RF signal. This lowers the input impedance and make s the design of matching network easier. During the negative half of the input cycle, diode D1 is forward biased whereas D2 is reverse biased. The capacitance C1 is then charged to the peak voltage of the incoming signal. During the positive half of the input cycle, D1 is off whereas D2 is on. At node X the incoming RF signal now increases the voltage already present on C1 and therefore increases the voltage across the load. Capacitor C2 acts as DC-pass filter which reflects the microwave energy arising from the di ode thereby producing DC voltage across RLoad. Figure 8-14 shows a photo of the AlGaN/GaN HEMT device used as a diode and the fabricated circuit on FR-4 board (relativ e permittivity=4.4, thickness=1.58 mm). Figure 8-14. Fabricated circ uit board on FR-4 substrate Two metal traces are put on each side of the signal trace to ease connections of shunt elements to ground. The traces are c onnected to the ground plane on the back using via holes. Wire-bonding is used to connect the diodes to the metal traces. The effect of wire-bonding inductance was taken into accoun t during the design. GaN diodes used in this work have a breakdown voltage of about 45-V and a relatively high ideality factor.

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124 The ideality factor of these de vices is ~3.8 which makes them not as suitable for use at lower input power levels; thus the achieved e fficiency at lower power levels would not be high. The circuits were measured using a powe r amplifier to boost the RF power level from the signal generator up to 30-dBm for high-power measurements. Figure 8-15 shows a plot of the maximum achieved RF-to-DC conversion efficiency and corresponding DC output voltage level versus input power level with RLoad=1-k , at the frequency of 900 MHz. Figure 8-15. Measured RF-to-DC conversion e fficiency and DC output voltage versus input power (Rload=1-k ) To evaluate the use of the re ctifier circuit to achieve ev en higher voltage levels, a load impedance of 5.4-k was used. At 1-W input power, the circuit achie ved an output voltage of 51-V at 900-MHz but conversion efficiency decreased to 51%. Figure 8-16

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125 shows the variation of RF-to-DC conversi on efficiency and co rresponding DC output voltage level versus input power level with RLoad=5.4-k . Figure 8-16. Measured RF-to-DC conversion efficiency and DC output voltage versus input power (Rload=5.4-k ) Figure 8-17. Measured RF-to-DC conversion e fficiency versus frequency for different values of load resistance

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126 To evaluate the frequency response of th e circuit, measurements were performed for a frequency range of 600-MHz to 1300-MHz with a constant input power level of 1W. Efficiency remained better than 65% up to 1100-GHz for load impedance of 1000. At up to 1000-MHz, efficiency better than 60% was achieved for a range of load impedance from 815to 1.3-k , as shown in Figure 8-17. Another test board was built with similar configuration. Inductance and capacitance values at the input side were tuned to make the circuit operate optimally at little higher frequencies. Efficiency response of the ne w test board was measured between 1-GHz– 1.7-GHz. Efficiency values of better than 63% were achieved up to 1.4GHz for load impedance of 815 . Figure 8-18 shows the achieved effi ciency versus frequency for an input power level of 1W for differe nt values of load impedances. Figure 8-18. Measured RF-to-DC conversion e fficiency versus frequency for different values of load resistance

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127 8.7 Conclusion A high power high efficiency RF-to-DC rectifier was fabricated using GaN Schottky diodes. The circuit achieves high output DC voltage and good RF-to-DC conversion efficiency. Conversion efficiency of 79% is achieved at 900-MHz at an input power level of 1-W. The circ uit can also achieve high output DC voltage level of around 50-V at increased load condition (RLoad=5.4-k ), at the expense of a reduction in conversion efficiency. Use of such high power rectifiers in a receive r system with high power density levels at the transmitting and r eceiving antenna can lead to a decrease in size of antenna elements required for a given power level. The experiment results show that high breakdown voltage GaN diodes indeed are a suitable candidate for high-voltage, high-power RF-to-DC rectifiers.

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128 CHAPTER 9 SUMMARY AND SUGGESTIONS FOR FUTURE WORK 9.1 Summary The work presented in this dissertation is focused on design of frequency converter devices (mixers, oscillators, RF-to-DC rectif iers) for wireless applications. Part of the work is focused on high frequency low power circuit design (mixers) in 130 nm Logic CMOS technology and the other is based on high power circuit design (oscillator and RFto-DC rectifier) using high power GaN technology. Design of RF-CMOS circuits with good pe rformance at high frequencies becomes more challenging when such circuits are de signed in a technology developed specifically for digital applications. Mixer designs presented in this work were all designed in a Logic CMOS process. Furthermore, in applications requiring high dynamic range, such as base station receivers, SiGe mostly outperforms CMOS devices. Measured performance of a high linearity LNA and down-convert er module suitable to be us ed in such receivers is presented. Mixers presented in this work ar e primarily designed as test structures to evaluate their use in a 24-GHz system calle d as Node, which is being developed by the SIMICS research group at the University of Florida. The Node is a true single chip radio incorporating on-chip antenna, transm itter, receiver, base-band processor and a sensor, thereby eliminating the need for hi gh frequency packaging and hence the cost. The Node system is intended to be capable of wireless transmi ssion and reception at 24GHz over short distances.

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129 An active up-conversion active mixer is designed in a Gilbert-cell topology. The design is among the first up-converters in standard CMOS technology that achieves reasonable performance at fre quency of 20 GHz. This mixer has been used in the Node transmitter system. The mixer achieves a conversion gain of 1-dB and input 1-dB compression power of -12 dBm at a power consumption of 8-mW. Good isolation performance is also achieved. To increase th e linearity of the mixer, a dual-gate mixer topology is also investigated. This mixer is de signed to operate at a center frequency of 24-GHz with a broad-band response in order to also be applicable in the 22-29 GHz ultrawide band range. Both input and output ports exhibit broad-band performance. Measurements are performed at a power level of 8 mW similar to the previous Gilbertcell design. The circuit achieves a 3-dB c onversion gain bandwidth of 2.1 GHz and 10 GHz at the input and output ports respectivel y. Excellent isolation performance between the ports, which is almost flat over the wide frequency range, is also achieved. A very flat 1-dB compression and third order in termodulation response is achieved in the frequency range of 17-29 GHz. An active down-conversion mixer is designe d in a Gilbert-cell topology to convert signals from 24 GHz down to 2.7 GHz. Due to inaccurate simulation models, the circuit operates optimally at 20 GHz. An excellent single side band noise figure of 8.5 dB is measured at LO power level of 0 dBm. Meas ured noise figure in the frequency range 23.5 GHz was less than 10 dB. The circuit also achieves a 3-dB conversion-gain bandwidth of 1.4 GHz at the output port, which is almost 50% of the intermediate frequency of 2.7 GHz. The circuit achieves an IIP3 of -2 dBm at a power consumption level of 6.9 mW from a 1.2 V supply. A narrow band down-conversion mixer has also

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130 been designed with different quality factors for input a nd output matching networks. The performance of this mixer is comparable to the broad-band design, at almost half of the power consumption. This design demonstr ates the performance tradeoff between frequency response and power consumption of the mixer. Advancement in CMOS technologies has made it possible to achieve high levels of integration in hand-set radios but their use in base station receiver applications still remain a challenge. The measured performa nce of an LNA and down-converter module is presented which achieves high linearity and low noise figure. System level simulations demonstrate the use of the module in a multi-band receiver. Specifications of DCS1800/PCS1900 and UMTS standards are met in super-heterodyne as well as directconversion receiver architecture, which demons trates that it is i ndeed possible to use CMOS based devices in base station receiv er. This will lead to higher levels of integration and cost reduction for such systems. CMOS technologies have shown to have the cost advantages over non-CMOS alternative but due to their lower breakdown vo ltages is it not conducive for use in high power applications. GaN devices prove to be a good alternative for high frequency and high power applications due to their inhere nt property of high breakdown voltages. A high power oscillator has been designed which can achieve an output power of 21.5 dBm at 1.88 GHz with an efficiency of 28%. Measured phase noise is -128dBc at 1 MHz offset. The ease of operation and ubiquitous na ture of wireless communication has led to the idea of wireless transfer of actual power as well. Wireless power transmission systems operate at higher power levels, whic h necessitate the use of technologies like GaN. Also, the design and measured performa nce of a high-voltage RF-to-DC rectifier

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131 circuit has been pres ented which is an essential modul e of a WPT system. Using highly directive antennas, higher power density can be achieved at the receiver which can be efficiently converted to DC power. The number and size of an tenna elements required to achieve a given DC output power level can thus be reduced, by transmission of power at higher density levels. 9.2 Suggestions for Future Work Development of high power high efficiency RF-to-DC rectifier circuits at higher frequency using high performance GaN devices with reduced capacitance. Also, the use of GaN devices to build high efficiency, hi gh power oscillators which can be used as transmitter source for the WPT system can be exhibited. It is important to achieve higher efficiency from a WPT system at higher fre quency levels in order to reduce the size of the antenna elements.

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139 BIOGRAPHICAL SKETCH Ashok Kumar Verma was born in October 1979 in Rajasthan, India. He received the Bachelor of Technology degree from Indi an Institute of Technology, Guwahati in 2002. In 2004, he received the Master of Scie nce degree in electri cal engineering from the University of Florida, Gainesville, Flor ida, USA. Since 2002, he has been working toward the Ph.D. degree at the RFSOC (Rad io Frequency System on Chip) Research Group in the Department of Electrical and Co mputer Engineering at the University of Florida, Gainesville, Florida. For his Ph.D. dissertation research, he has been investigating use of standard CMOS technology for high-frequency low-power transmitter and receiver mixer design and high-power GaN devices for wireless power transmission systems.