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Design and Optimization of 5GHz CMOS Power Amplifiers with the Differential Load-Pull Techniques

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Title:
Design and Optimization of 5GHz CMOS Power Amplifiers with the Differential Load-Pull Techniques
Creator:
KO, YUS ( Author, Primary )
Copyright Date:
2008

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Subjects / Keywords:
Amplifiers ( jstor )
Calibration ( jstor )
Electric potential ( jstor )
Power amplifiers ( jstor )
Power efficiency ( jstor )
Signals ( jstor )
Simulations ( jstor )
Transceivers ( jstor )
Transistors ( jstor )
Transmitters ( jstor )

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Source Institution:
University of Florida
Holding Location:
University of Florida
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Copyright Yus Ko. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Embargo Date:
12/31/2006
Resource Identifier:
443801797 ( OCLC )

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DESIGN AND OPTIMIZATION OF 5 GHZ CMOS POWER AMPLIFIERS WITH THE DIFFERENTIAL LOAD-PULL TECHNIQUES By YUS KO A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2005

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Copyright 2005 by Yus Ko

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This document is dedicated to my parents and my wife.

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ACKNOWLEDGMENTS I would like to acknowledge the continuous guidance and support of my committee chair, Dr. William R. Eisenstadt. He was always generous and confident in me and encouraged me to complete my dissertation successfully. I also appreciate the other committee members, Dr. Khai D. T. Ngo, Dr. John G. Harris, and Dr. Oscar D. Crisalle, for their constructive comments and expert assistance. I would like to specially thank Dr. Khai D. T. Ngo and Dr. Robert M. Fox for their interest in my work and their valuable comments to realize this dissertation. I would like to thank Intersil Incorporated (now Conexant Systems Incorporated), Palm Bay, Florida, for supporting my research project and giving me the opportunity to work as a summer intern. Much appreciation goes to James R. Paviol, Dr. Brent A. Myers at Conexant Systems Incorporated for their helpful and essential support and endless encouragement. I would also like to thank Mir Faiz for bondwire and package models, and Richard Kovacs for PCB design at Conexant Systems Incorporated. Special appreciation goes to my friends Sungphil Kim and Dongho Han who have always helped and encouraged me and my fellow graduate colleagues, Okjune Jeon, Choongeol Cho, Jongshik Ahn, Kooho Jung, Jangsup Yoon, Hyeopgoo Yeo, Tao Zhang, Qizhang Yin, Ming He, Xiaoqing Zhou, Xueqing Wang, and Su Deep. Also, I would like to acknowledge MOSIS for the technical and fabrication support. I cannot express how grateful I am to my parents and brother for their endless belief, support, and understanding through the whole time of study. Finally, I would like iv

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to express my profound thanks to my lovely wife, Jione Jung, for never-ending love and unlimited trust. I thank them with all my heart. v

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TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................iv LIST OF TABLES ...........................................................................................................viii LIST OF FIGURES ...........................................................................................................ix ABSTRACT .....................................................................................................................xiii CHAPTER 1 INTRODUCTION........................................................................................................1 1.1 CMOS RF Power Amplifier and Differential Load-Pull........................................2 1.2 Research Objective and Contribution.....................................................................4 1.3 Organization...........................................................................................................6 2 OVERVIEW OF WIRELSS STANDARDS AND POWER AMPLIFIERS...............8 2.1 802.11a WLAN Standards......................................................................................9 2.1.1 System Specifications...................................................................................9 2.1.2 Transmitter Architecture............................................................................11 2.2 Basic Theory of Power Amplifier.........................................................................12 2.2.1 Device Process Technology Selection........................................................13 2.2.2 Power Amplifier Classes............................................................................14 2.2.3 Basic Parameters of Characterizing Power Amplifier................................21 2.2.4 Review of Literature on CMOS Transceivers............................................26 3 DESIGN METHODOLOGY FOR RF POWER AMPLIFIERS................................31 3.1 Specification for 5GHz Power Amplifier Design.................................................32 3.2 Concept and Key Design Issues...........................................................................33 3.2.1 Determination of Transistor Size................................................................34 3.2.2 Selection of Optimum Load Impedance.....................................................35 3.2.3 Biasing Circuit and Stability......................................................................37 3.2.4 Cutoff Frequency........................................................................................38 3.2.5 Issues on Fabrication Process and Layout..................................................40 3.2.6 Power Amplifier Design Procedure............................................................41 vi

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3.3 Optimum Matching Network Design...................................................................42 3.3.1 Small-Signal Conjugate Matching Method................................................43 3.3.2 Large-Signal Load-Line and Load-Pull Matching Method........................44 3.3.3 Matching Network Structure......................................................................46 3.4 Power Amplifier Schematic and Layout...............................................................47 3.4.1 Power Amplifier Schematic.......................................................................48 3.4.2 Power Amplifier Layout.............................................................................51 3.4.3 Bondwire and Package Parasitic Models and Diagrams............................53 4 DEVELOPMENT OF DIFFERENTIAL LOAD-PULL TECHNIQUES..................60 4.1 Load-Pull Techniques...........................................................................................61 4.2 Conventional Load-Pull Measurement Setup.......................................................62 4.3 Standard and Mixed-Mode S-Parameters.............................................................65 4.4 Differential Load-Pull Block Diagram and Simulation Results...........................68 4.4.1 Differential Load-Pull Block Diagram and Operation...............................69 4.4.2 Differential Load-Pull Simulation and Result............................................72 5 IMPLEMENTATION OF FULLY INTEGRATED 5GHZ CMOS POWER AMPLIFIER AND EXPERIMENTAL RESULTS....................................................77 5.1 Printed Circuit Board Design................................................................................78 5.1.1 Single-Ended Evaluation and Calibration Boards......................................79 5.1.2 Differential Evaluation and Calibration Boards.........................................80 5.2 Power Amplifier Simulation Results....................................................................82 5.2.1 Single-Tone and S-parameter Simulation..................................................84 5.2.2 Two-Tone Simulation.................................................................................85 5.2.3 Temperature Variation and MonteCarlo Simulation..................................87 5.3 Measurement Setup and Calibration.....................................................................89 5.3.1 Equipment Calibrations..............................................................................90 5.3.2 Single-Tone Power Sweep and S-parameter Measurement.......................90 5.3.3 Two-Tone Measurement............................................................................92 5.3.4 Multi-Tone and EVM Measurement..........................................................93 5.4 Power Amplifier Experimental Results and Measurement Analysis...................96 5.5 Characterization of Commercial WLAN Power Amplifiers..............................101 5.6 Automating WLAN Power Amplifier Distortion Test.......................................103 6 SUMMARY AND FUTURE WORK......................................................................107 6.1 Summary and Conclusion...................................................................................107 6.2 Implication for Future Work...............................................................................110 6.2.1 Potential Improvement of 5GHz WLAN Power Amplifier.....................110 6.2.2 Realization of the Differential Load-Pull System....................................111 LIST OF REFERENCES.................................................................................................112 BIOGRAPHICAL SKETCH...........................................................................................118 vii

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LIST OF TABLES Table page 1.1. Estimated market volumes by WLAN type (in millions of units)...............................2 2.1. Parameter characteristics of selected technologies for power amplifier....................14 2.2. Classification of power amplifier...............................................................................21 2.3. CMOS transceivers integrated with power amplifier................................................30 3.1. Design specifications for OFDM 5GHz power amplifier..........................................32 3.2. Component parameters for power amplifier schematics...........................................54 3.3. CMOS power amplifier package pin names in bondwire diagram............................59 4.1. Equipment lists for differential load-pull measurement system................................76 5.1. Three-stage CMOS power amplifier simulation performance...................................89 5.2. Two-stage CMOS power amplifier simulation performance.....................................89 5.3. Two-stage CMOS power amplifier measurement performance..............................101 5.4. Comparison of WLAN power amplifier measurement performance......................102 viii

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LIST OF FIGURES Figure page 2.1. Channel allocation in IEEE 802.11a standards..........................................................10 2.2. Transmit output power spectrum mask......................................................................11 2.3. Architecture for the 5GHz WLAN transmitter..........................................................12 2.4. Basic single-ended power amplifier topology...........................................................15 2.5. Current and voltage waveforms of the selected power amplifier classes..................17 2.6. Output power versus input power characteristic with single-tone sweep..................23 2.7. Spectrum of a power amplifier with a two-tone test..................................................24 2.8. Adjacent channel power spectrum.............................................................................25 2.9. Output spectrum mask with 5GHz OFDM signal.....................................................27 3.1. Three-stage power amplifier with matching networks..............................................33 3.2. Cascode output stage schematic and its equivalent circuit........................................34 3.3. Transistor I-V characteristics with the gate width of 1000um...................................35 3.4. Output optimum load resistance................................................................................36 3.5. Test circuit for stability..............................................................................................38 3.6. Equivalent circuit to calculate the cutoff frequency..................................................39 3.7. Cutoff frequency plot for the minimum transistor size..............................................39 3.8. Cutoff frequency plot with the total gate width of 1000m......................................40 3.9. The flow of design procedure....................................................................................42 3.10. S 11 and S 22 small-signal conjugate matching method using Smith chart.................43 3.11. Output power versus load resistance........................................................................44 ix

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3.12. Load-pull simulation block diagram........................................................................45 3.13. Load-pull simulation result......................................................................................46 3.14. Load-pull simulation result with the 0.18um short channel device.........................46 3.15. Input and output matching networks........................................................................47 3.16. Three-stage power amplifier schematic...................................................................49 3.17. Two-stage power amplifier schematic.....................................................................50 3.18. Three-stage power amplifier layout.........................................................................52 3.19. Two-stage power amplifier layout...........................................................................53 3.20. Initial estimated value of bondwire and package models........................................55 3.21. Equivalent circuit for bondwire model....................................................................56 3.22. Equivalent circuit for package model......................................................................57 3.23. Bondwire diagram for 1 st power amplifier...............................................................58 3.24. Bondwire diagram for 2 nd power amplifier..............................................................58 4.1. Instrument setup for load-pull system........................................................................63 4.2. Tuner characterization block diagram.......................................................................63 4.3. Load tuner characterization display...........................................................................63 4.4. Conventional single-ended load-pull block diagram.................................................64 4.5. Measurement result plot for the single-ended load-pull system................................65 4.6. Four-port differential circuits.....................................................................................66 4.7. Differential load-pull block diagram.........................................................................70 4.8. General mixer configuration......................................................................................71 4.9. Differential load-pull simulation block diagram........................................................74 4.10. Differential load-pull simulation result....................................................................75 5.1. PCB schematic for single-ended power amplifier with baluns..................................79 5.2. PCB layout for single-ended power amplifier (a) and calibration (b).......................80 x

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5.3. PCB schematic for differential power amplifier........................................................81 5.4. PCB layout for differential power amplifier (a) and calibration (b)..........................81 5.5. Photograph of the integrated power amplifier test board for single-ended (a) and differential (b)..........................................................................................................82 5.6. Test circuit for power amplifier simulation...............................................................83 5.7. CMOS power amplifier with bondwire and package models....................................83 5.6. Gain, output power, phase, and PAE plots................................................................84 5.7. S-parameter plots with small-signal and large-signal matching................................85 5.8. Two-tone transient output response...........................................................................86 5.9. Intermodulation products from the two-tone test.......................................................86 5.10. Gain variation over the temperature range...............................................................87 5.11. MonteCarlo simulation result for v th , g m , and i d ......................................................88 5.12. MonteCarlo simulation result for S 21 gain...............................................................88 5.13. Test setup for power sweep and s-parameter measurement.....................................91 5.14. AM/AM and AM/PM plot.......................................................................................91 5.15. Test setup for two-tone measurement......................................................................92 5.16. Two-tone output spectrum.......................................................................................93 5.17. Test setup for multi-tone measurement....................................................................94 5.18. Multi-tone output spectrum......................................................................................95 5.19. IEEE 802.11a EVM on VSA...................................................................................95 5.20. Test bench for power amplifier measurement.........................................................96 5.21. S-parameter measurement plot of two-stage power amplifier.................................98 5.22. Output power, gain, and PAE results of two-stage power amplifier.......................99 5.23. Two-tone IMD plot of two-stage power amplifier................................................100 5.24. Output power, gain, and PAE results of two-stage power amplifier at peak gain (5GHz)....................................................................................................................100 xi

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5.25. P1dB and gain comparison chart...........................................................................102 5.26. Current and efficiency comparison chart...............................................................103 5.27. Two-tone measurement setup using LabView program........................................105 5.28. Multi-tone measurement setup using LabView program.......................................106 xii

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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy DESIGN AND OPTIMIZATION OF 5GHZ CMOS POWER AMPLIFIERS WITH THE DIFFERENTIAL LOAD-PULL TECHNIQUES By Yus Ko December 2005 Chair: William Eisenstadt Major Department: Electrical and Computer Engineering This research focuses on radio frequency (RF) power amplifier circuit design for Wireless Local Area Network (WLAN) 802.11a applications. Since the IEEE WLAN 802.11a, b, and g standards were announced, WLAN system architectures have been developed for each specific wireless standard. With the huge demand of WLAN transceiver chipsets, it is preferable to design them at a low cost and highly integrated with the goal of a single chip solution. To achieve this goal, CMOS process technology is used in the power amplifier design. In this dissertation, a series of design procedures of RF CMOS power amplifier are described. Power amplifiers are the last output stage in transmitter architecture and widely used in various wireless transceiver applications. A fully integrated differential CMOS power amplifier is designed with 0.18m IBM BiCMOS SiGe process for 5GHz WLAN transceiver applications. xiii

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Power amplifier schematic, layout, simulation results, and measurement results are shown. Various CMOS power amplifier simulations and measurements are performed such as single tone, two-tone, s-parameter, load-pull, EVM, and Monte Carlo tests. The revision of the 5GHz WLAN power amplifier was optimized by extracting parasitic resistances, capacitances, and inductances for accurate modeling on the metal line of the RF signal path. The simulation and measurement performances are compared to those of other commercial power amplifiers. An automating WLAN power amplifier distortion test was developed and used to obtain efficient and accurate measurement results. With an introduction of the load-pull technique, a conventional single-ended load-pull system is presented. A new differential load-pull system is developed to characterize the differential power amplifier utilizing two existing single-ended tuners. To calculate mathematical transformation for differential-mode and common-mode test, the mixed-mode s-parameter technique for large-signal characterization is described. A block diagram of the differential load-pull is presented and simulated. Also, the equipment required for the differential load-pull system is described. xiv

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CHAPTER 1 INTRODUCTION Power amplifiers are the last output stage in a wireless system with the responsibility of amplifying the signal, transmitting it to an antenna in the transmitter architecture, and determining the overall power efficiency of a transmitter chain. Power amplifiers have been widely used in various wireless transceiver applications including portable communications, Bluetooth, and Wireless Local Area Network (WLAN) systems. Using radio frequency (RF) technology, WLAN systems transmit and receive data over the air while minimizing the need for wired connections. The Institute of Electrical and Electronics Engineers (IEEE) 802.11 working group ratified 802.11a and 802.11b standards in 1999. 1 Since the standards were announced, WLAN system architectures have been developed for each specific wireless standard. While the 802.11b/g operates in a 2.4GHz Industrial Scientific Medical (ISM) band with maximum data rate of 11/54Mbps using the Direct Sequence Spread Spectrum (DSSS) and Complementary Code Keying (CCK) modulation schemes for 802.11b and Orthogonal Frequency Division Multiplexing (OFDM) for 802.11g, the 802.11a operates in a 5GHz Unlicensed National Information Infrastructure (UNII) band with 54Mbps data rate using the OFDM modulation scheme [Iee99]. The 5GHz band 802.11a standards have more available spectrum than the 802.11b/g which shares 2GHz band with microwave ovens, Bluetooth, and cordless 1 More recently in 2003, 802.11g was newly added in the group of WLAN standards, which is capable of transferring higher data rate than 802.11b. 1

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2 phones, and therefore can have heavy congestion. For this reason, the interest in and significance of 802.11a is increasing. Table 1.1 presents the volumes (in millions) of each WLAN chipset available in the markets, estimated by In-Stat [McF02]. As the In-Stat report shows, the WLAN market follows a trend shifting from 2.4GHz to 5GHz and dual-band. Also, data rates have increased from 11Mbps to 108Mbps [McF04]. Table 1.1. Estimated market volumes by WLAN type (in millions of units) WLAN type Year 802.11b (2.4 GHz) 802.11a (5 GHz) Dual band 2002 12.8 0.7 0.7 2004 25.2 6.5 7.0 2006 23.6 16.3 29.3 Source: In [McF02], Table 1. 2002 In-Stat WLAN Market Estimates, p.11 1.1 CMOS RF Power Amplifier and Differential Load-Pull As the demand for WLAN systems increases, designing cost efficient circuits is necessary. Traditionally, Gallium Arsenide (GaAs) and Silicon Germanium (SiGe) processes have been commonly used for designing RF transceiver chips, due to their superior device performance. System designers worry about high transmitter reflected signal cases such as when an antenna is broken off. Even though there are also a number of technologies available for power amplifier design, the same is true for transceiver design, the choice of technology for RF power amplifier design is very important and should be considered in light of several parameters such as breakdown voltage, cutoff frequency, size, cost, and high current limit. Realizing that the major concerns at present are achieving a highly integrated system in a single chip and higher yields (with fewer defects per wafer), and reducing the cost of the chip, the only solution for such goals may be Complementary Metal Oxide

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3 Semiconductor (CMOS) technology. Designing with a CMOS process becomes a popular option in developing wireless transceiver building blocks. Concerning CMOS technology, many RF engineers have developed the transceiver chip sub-building blocks such as a Low Noise Amplifier (LNA), mixer, filter, frequency synthesizer, and Voltage Controlled Oscillator (VCO) using CMOS technology. However, when comparing with many other RF sub-circuits mentioned above, designing a power amplifier with CMOS technology one should be very careful about the breakdown performance, which is related to the voltage swing, and flowing huge amount of current through the transistor. The power amplifiers designed using CMOS technology are widely used in PCS and 2.4GHz band applications such as Bluetooth [Kno01, Mer02, Vat01] and WLAN 802.11b [Sar03], but it is very challenging to use CMOS technology in 5GHz band or above because of CMOS technology performance limitations. Many transceiver chipsets have been developed in a variety of wireless applications. Transceiver architectures composed of a transmitter and a receiver has been migrating toward differential structures from single-ended structures [Cop00]. The advantages of using the differential topology are negligible common-mode (even harmonic) effects, reduction in the impact of the ground inductance, and minimization of on-chip crosstalk. Differential circuits and systems are widely used for analog, RF, and microwave frequency applications; however, the accurate characterization of differential structures should be a priority. The load-pull technique is an essential procedure for designing large-signal circuits, especially power amplifiers. A conventional load-pull measurement system is useful to yield the desirable design parameters (e.g., optimum load impedance for output power,

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4 gain, and efficiency). While it is true for single-ended devices or single-ended circuits based power amplifier and baluns, the conventional load-pull technique may not be good enough to characterize large-signal phenomena. Therefore, a new differential load-pull technique for differential structures is necessary. The differential load-pull technique developed from this research will be used for characterizing the differential power amplifier to get the optimum performance. 1.2 Research Objective and Contribution This dissertation is concerned about whether a power amplifier developed using CMOS process technology can be useful for high frequency medium power application. Unlike other RF building blocks, traditionally, power amplifiers have been implemented using discrete or hybrid with compound power transistor and external components, which results in low integration and high cost. Therefore, the significance of this cost issue brings the CMOS technology into circuit designs. Even though CMOS technology gives a lot of advantages to digital, analog baseband, and RF integrated chip development, it should be further investigated from the RF power amplifier standpoint. Many business groups still have produced the transceiver chipsets integrated with power amplifiers using compound III-V and SiGe BiCMOS processes and only a few companies have developed CMOS transceiver chipsets. Occasionally, even though the transceiver chipsets except for power amplifier are designed with a CMOS process, an external power amplifier designed with other technologies is used because of its superior performance. Since the WLAN application chipset is quite commercial and a large volume product, a higher level of sub-component integrations are required to make smaller size, lower price, and better performance. By designing a power amplifier using CMOS

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5 technology, it enables an RF designer to make a higher level of integration that builds digital, analog baseband, and RF building blocks onto single chip. For this research, to design the CMOS differential power amplifier which requires a high linearity with sufficient efficiency for WLAN applications, the 0.18m IBM BiCMOS 7WL process is used. Given the performance requirements, the complete design process includes device selection, circuit design, circuit modeling and simulation, physical layout, board design, and measurement. The other main research in this dissertation is to develop a differential load-pull system to characterize the differential power amplifier. Using the existing instruments (i.e., two single-ended tuners, power meters, signal generators, and couplers) which are available in the laboratory for a single-ended load-pull system, a measurement system is set up for the differential load-pull technique and simulated in the Advanced Design System (ADS) software. Therefore, the major objectives of this research are to design the CMOS differential power amplifier for 5GHz WLAN applications and to develop a differential load-pull technique and then to apply the new development to design a CMOS differential power amplifier. The main contributions achieved by the author with respect to this research topic are summarized as follows. First, the standalone CMOS power amplifier for 5GHz WLAN applications is designed for the purpose of integrating on a CMOS transceiver chipset. Even though the output power performance is a little lower than the specification requirement, it shows the feasibility of integration into the whole CMOS transceiver design. With a good input and output tuning and a proper bypass capacitor selection, the differential CMOS power amplifier developed in this work will be good for 5GHz

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6 WLAN applications. Several discussions to improve the CMOS power amplifier performance will be presented in the last chapter. Second, semi-automated test set-ups are developed for power amplifier distortion tests such as two-tone and multi-tone measurements which needed significant data capture. Once measurement instruments required for each measurement are setup and calibrated in the programming block diagrams, the measurement data are automatically recorded over the input power range. Several power amplifiers for WLAN 2GHz and 5GHz band applications are evaluated. This test setup is very effective in terms of measurement time and accuracy. Finally, the differential load-pull technique is developed for CMOS differential power amplifiers designed in this research. Similar to the function of a conventional single-ended load-pull system for single-ended power amplifiers, this technique is useful for the differential power amplifier characterization by finding the optimum load impedance. In addition to that, this differential load-pull technique can be further used for any differential power amplifiers designing with other process technologies as well as CMOS technology. 1.3 Organization From this point, the dissertation presents the following five chapters, focusing on power amplifier design with CMOS technology, its testing issues, and the differential load-pull system. Chapter 2 gives a general overview of WLAN 802.11a standards that demonstrate the system specifications and transceiver architecture. The basics of power amplifier are described, and classes of power amplifiers and general characteristics are depicted. Also, some of the important design parameters determining the performance of power amplifiers are explained. Chapter 3 explains how the CMOS RF power amplifier is

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7 designed. The power amplifier specification is presented and the design techniques with several key design issues follow. Next, it is shown how the matching networks are built. The schematic, layout, and bondwire diagram on the power amplifier are shown. Chapter 4 begins with a brief introduction of load-pull technique and its setup. A differential load-pull system is developed. After reviewing the standard and mixed-mode s-parameters and developing the mathematical analysis, the differential load-pull system is described and its simulation results are shown. In Chapter 5, the simulation and experiment results of the power amplifier are presented. Also, measurement setups for distortion tests of the power amplifier are described. The performance of the power amplifier is compared with that of other commercial power amplifiers. Finally, Chapter 6 summarizes and concludes this dissertation and suggests future work related to how this CMOS power amplifier performance can be improved and optimized and how the differential load-pull system will be realized.

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CHAPTER 2 OVERVIEW OF WIRELSS STANDARDS AND POWER AMPLIFIERS Wireless Local Area Network (WLAN) systems use radio transmissions over the air to connect wirelessly between communication devices and to substitute for the functionality of wired local area network systems such as the Ethernet [Pav01]. WLAN chipsets can make wire-free computer communications available anywhere and anytime. The 5GHz WLAN has become more popular during the last few years, eventually is a part of in the dual band (2GHz and 5GHz) implementations. In the present chapter, the characteristics of the Institute of Electrical and Electronics Engineers (IEEE) 802.11a standard are introduced. As one of the most important requirements in transmitter, the transmitted output spectrum given a modulated input signal is described. Even though several transceiver architectures which can be implemented have been developed for standards, one transmitter architecture which is widely used for this application by considering the cost, complexity, and performance will be shown. A power amplifier is one of critical building blocks realizing the transceiver chipset. With a brief explanation of device technologies which are available for power amplifier design, various classes of power amplifiers distinguished by their operation, bias, linearity, and efficiency are presented. The main performance parameter for the power amplifier is the output power level, depending on the linearity and efficiency within a given specification. Both efficiency and nonlinear characteristics of power amplifiers are described in detail. 8

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9 With the trends moving towards a higher integration and a lower cost in wireless standards, many publications related to the transceiver design using CMOS technology in various applications have been reported. The literature on the design of CMOS transceivers and power amplifiers are reviewed. 2.1 802.11a WLAN Standards 2.1.1 System Specifications IEEE 802.11a WLAN standards operate in a 5GHz Unlicensed National Information Infrastructure (UNII) band, which employs Orthogonal Frequency Division Multiplexing (OFDM) modulation with the signal bandwidth of 300MHz. The 5GHz UNII band consists of three subbands with the corresponding power levels: low band operating from 5.15 to 5.25GHz; middle band operating from 5.25 to 5.35GHz; and high band using from 5.725 to 5.825GHz. 2 Figure 2.1 shows channel allocations in an 802.11a standard. The purpose of modulation in a transmitter is to transform the baseband information to a radio frequency (RF) carrier. The OFDM modulation is a new encoding technology applied only in 802.11a applications. It defines four 20MHz-wide channels in each 100MHz of two lower bands. Each of these channels is subdivided into 52 subcarriers and each subcarrier has 312.5KHz bandwidth. The subcarriers are then transmitted in parallel, and therefore, a huge amount of information will be sent at once supporting data rates with the range of 6, 9, 12, 18, 24, 36, 48, and 54Mbps. Depending on the rate, the data are modulated with either binary/quadrature phase shift keying (BPSK/QPSK), 16or 64-quadrature amplitude modulation (QAM) and mapped into 52 2 Recently, the frequency band extended from 4.9GHz to 6GHz.

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10 subcarriers of an OFDM signal. The maximum transmit output power levels in the United States are 40mW for the lower band, 200mW for the middle band, and 800mW for the upper band. While only 48 out of the 52 subcarriers are used for information, the rest remain for error correction. Figure 2.1. Channel allocation in IEEE 802.11a standards The output signal spectrum of a power amplifier must comply with the send-mask requirements set by the Federal Communications Commission (FCC). Figure 2.2 shows the transmitted OFDM output spectrum mask and an example of a WLAN 802.11a standard. When a modulated signal enters into a transmitter, if the curve of the output power spectrum does not exceed the required mask, the spectrum test is passed; otherwise, it is failed. The transmitted spectrum mask should not exceed a 0dBr within the bandwidth of f c 9MHz, -20dBr at 11MHz frequency offset, -28dBr at 20MHz frequency offset, and -40dBr at 30MHz frequency offset and above. This determines the level of nonlinearity in the transmitter.

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11 Figure 2.2. Transmit output power spectrum mask 2.1.2 Transmitter Architecture A transceiver consists of two parts: receiver and transmitter. Since receivers are not a matter of focus in this research, the dissertation examines transmitters, more particularly, power amplifiers. A transmitter transmits a signal converted from digital information over the air by performing modulation, upconversion, and power amplification. There are two common transmitter architectures: direct conversion transmitter (i.e., Homodyne or Zero-Intermediate Frequency (ZIF)) and low IF dual conversion transmitter (i.e., Superheterodyne). For the Superheterodyne, the following are necessary: an external component for channel IF filtering and two synthesizers. The dual synthesizers are larger circuit designs including isolation techniques (filters) requiring extra complexities. On the other hand, the Homodyne architecture reduces the number of components, particularly RF/Microwave filters, and therefore is better for fully integrated designs. However, there exist drawbacks in Homodyne transmitters such as dc offset problems, local oscillator (LO) pulling, and flicker noise [Zha03]. Depending

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12 on the specification of the application in consideration, the designers should carefully consider which architecture to choose. Figure 2.3 shows a general block diagram of the transmitter for a 5GHz WLAN application. Including a power amplifier, a transmitter also contains additional circuitry such as a converter, modulator, filter, and frequency translator. The baseband signal from a digital-to-analog converter (DAC) is low-pass filtered and upconverted to the RF carrier through a mixer. Then, an RF modulated signal is delivered to an antenna after power-amplifying. Since the signal drives into the single-ended antenna, differential to single-ended conversion should be performed using an on-chip or off-chip balun. In the next section, the power amplifier architecture is discussed in detail. Figure 2.3. Architecture for the 5GHz WLAN transmitter 2.2 Basic Theory of Power Amplifier A power amplifier plays a key role in converting DC power into a required amount of RF power. Power amplifiers are commonly divided into two categories: linear (small-signal) and nonlinear (large-signal) amplifiers. The distinctions between the various

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13 classes of power amplifiers can be explained by their circuit configurations, operational topologies, biasing point, modulation type, linearity, and efficiency. The linear amplifiers are classified as A, AB, and B. Among them, Class A is generally known as the most linear and least efficient. The nonlinear amplifiers are comprised of Class C, D, E, F, and S. The Class C amplifier has a similar topology to Class A, an active device acting as a current source. Class D, E, F, and S amplifiers use the transistor as a switch with ideally maximum efficiency of 100% [Ken00, Kra80]. The use of power amplifiers differs by the types of modulation: nonlinear power amplifiers are required for the standards such as Global System for Mobile Communication (GSM), Digital European Cordless Telecommunications (DECT), and HIgh PERformance Local Area Network (HIPERLAN) applications. They use constant amplitude modulation such as Frequency Shift Keying (FSK) and Gaussian Minimum Shift Keying (GMSK) to vary the frequency. On the other hand, Interim Standard (IS)-95 (the original digital mobile telephony standard) and WLAN 802.11a applications using variable amplitude modulation require linear power amplifiers [Raz99]. 2.2.1 Device Process Technology Selection Several technology options that a designer can select in RF design are discussed in this section. A number of active devices are currently available for designing power amplifiers: Metal Oxide Silicon Field Effect Transistor (MOSFET), Silicon Bipolar Junction Transistor (Si BJT), Silicon Germanium Heterojunction Bipolar Transistor (SiGe HBT), Gallium Arsenide (GaAs) Metal Semiconductor Field Effect Transistor (MESFET), and Complementary Metal Oxide Semiconductor (CMOS) [Pen02, Raa03a]. The main parameters in selection of the device are operating frequency, power,

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14 breakdown voltage, performance, and cost. The performances of selected active devices are summarized in Table 2.1. GaAs technology has been widely used to design power amplifiers due to its superior device performance. However, since it has high cost and a low level of integration compared to the silicon wafer, SiGe HBTs are a strong consideration for designing power amplifiers these days. Also Si BJTs have a slightly higher cutoff frequency. Although the CMOS technology has still several drawbacks such as low breakdown voltages, it currently challenges other technologies, following the trend of lower cost implementation for highly integrated large volume (hundreds of millions) parts. Currently, 0.25m or deep sub-micron CMOS technology is sufficient up to 5GHz for RF applications; however, it should be further investigated for RF power amplifier applications. Table 2.1. Parameter characteristics of selected technologies for power amplifier Key parameters Technology Cost Power density Linearity Frequency PAE SiGe Fair Medium Poor Excellent Low GaAs Competitive Medium Good Excellent Medium CMOS Lowest Medium Fair Good Medium 2.2.2 Power Amplifier Classes Power amplifiers are divided into several classes, depending primarily on input signal (bias condition), conduction angle, operating mode, and efficiency. There are four types of power amplifiers (Class A, B, AB, and C) which the active device acts as a controlled current source. On the contrary, power amplifiers which use the active device as a switch are Class D, E, F, and S. The characteristics of power amplifiers are discussed briefly with references [Ken00, Kra80, Lee98, Raz98, Smi98].

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15 Figure 2.4 shows a general, single-ended power amplifier architecture, which consists of an active device, input/output matching networks, blocking capacitors (C), a RF choke (L), a bias network, and the load impedance (R L ). The MOSFET as an active device which is capable of amplification can be changed to Bipolar or any other transistor type. An RF modulated signal, after being mixed, is amplified by the power amplifier and is delivered to the 50 load antenna. Figure 2.4. Basic single-ended power amplifier topology In a Class A power amplifier, the amplifying active device is biased in such a way that it always remains in the active (saturation) region, acting as a controlled current source. Although the Class A power amplifier has high linearity, the efficiency is low because the output drain current flows all the time, and therefore, the average power consumption is very high. This amplifier is used for a system required high linearity such as WLAN 802.11 b/g applications at the cost of efficiency. Assuming that a power amplifier is ideal, the drain current and voltage waveforms for the selected classes of power amplifiers are shown in Figure 2.5 [Raa02].

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16 To derive the efficiency of a Class A amplifier, if the transistor is biased with an input voltage signal, the drain current is )sin(I I t)(imaxDQdt (2.1) where I DQ is the bias current and I max is the peak sinusoidal current. The output current yields )sin(I t)(imaxot (2.2) Then, the output voltage will be )sin(V )sin(RI t)(vmaxLmaxott (2.3) The drain voltage which consists of DC and AC components is )sin(V V t)(vmaxDDdt (2.4) With an output DC current, I DC , LDDLmaxDQDCRV RV I I (2.5) The power from the supply is L2DDDCDDDCRV IV P (2.6) The RMS output power at the load, R L is L2DDL2maxoutR2V R2V P (2.7) Therefore, the peak overall drain efficiency for Class A power amplifier will be ideally 21 V2V PP 2DD2maxDCout (2.8) If the effect of the finite knee voltage of transistor is considered in practical applications, then the efficiency will be reduced because V DD should be replaced by V DD -V knee .

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17 Figure 2.5. Current and voltage waveforms of the selected power amplifier classes A Class B power amplifier is biased near the threshold of conduction at the gate and operates for only one-half of a cycle. The Class B operation is significantly more efficient, but less linear than the Class A, and its quiescent current or voltage is approximately zero. The Class B is generally employed in a push-pull configuration to produce a sine-wave output by adding two drain currents together. This class of operation can be used for the power amplifiers not required for high linearity such as portable mobile radio, base stations, and FM transmitters. In Class B, the output current and voltage as the same in Class A are )sin(I t)(imaxot (2.9) )sin(V t)(vmaxot (2.10)

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18 With the load current conducts for of a complete input cycle, (2.11) 2 00 )sin(I t)(imaxdttt The drain current, or dc component, is given by 2T0maxmaxDI dt |)sin(|IT1 It (2.12) The power from the supply is L2DDDDmaxDDDDCRV VI IV P (2.13) The output power at the load, R L is L2DDL2max02maxLoutR4V 4RI dt))sin(I(21R Pt (2.14) Therefore, the peak overall drain efficiency for Class B power amplifier will be ideally 4 RVR4V PP L2DDL2DDDCout (2.15) A Class AB power amplifier finds the middle ground between Class A and Class B operation lying with a conduction time between 50% and 100% of a cycle. The distortion of a Class AB amplifier is greater than that of Class A amplifier, but less than that of Class B amplifier. The efficiency of Class AB is in the middle between Class A and B (i.e., A < AB < B for efficiency). Class AB power amplifiers are consequently popular in many RF applications. In the Class C power amplifier the gate is biased below threshold with reducing the conduction time by less than 50% of a full cycle in the device. So the efficiency that can

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19 be reached is around 85% practically (ideally, 100%) because the current and voltage waveforms are both non-zero at the same time which means the device consumes power. This mode of operation can have a greater efficiency than Class A or B, but much more distortion than Class A or B. For an application using a constant envelope signal (LINC or out-phasing), Class C amplifier is preferred because it has very high efficiency compared to that of linear Class A and B amplifiers. For this Class C amplifier, the drain current is given by )cos-sin(I)dt I-)sin((IT1 ImaxDQmaxD21 t (2.16) where 2 = 2 1 and = /2 1 . The power from the supply is )cos-(sin VI IV PDDmaxDDDDC (2.17) The output power at the load, R L is 222L2max2DQmaxLout)sin2-(24RI dt )I-)sin((I21R P21t (2.18) The peak efficiency for Class C power amplifier will be )cos-4(sinsin2-2 PP DCout (2.19) Contrary to Class A, B, AB, and C amplifiers mentioned so far, additional classes of amplifiers which use the transistor as a switch, ideally turning on and off abruptly, such as Class D, E, F, and S are existed. High efficiency amplification is usually achieved

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20 by switching Class D, E, F, or S power amplifiers. To achieve high efficiency, the on-resistance of the switch-mode transistor should be small and the gate bias voltage must be a rectangular form. Class D power amplifiers are usually a transformer coupled design which is similar in structure to the transformer coupled Class B amplifiers. If the drain-to-source voltage is zero when the current conducts, the ideal efficiency will be close to 100% because no power will be dissipated in the active device. Class D amplifiers have recently been used in AM broadcast transmitters and low power HF transmitters modulated on a carrier such as Frequency Shift Keying (FSK). The Class E power amplifier, like a Class D switching amplifier, is a nonlinear amplifier and employs an active device acting as an ideal switch with zero on-resistance (zero voltage across it) and infinite off-resistance (zero current through it). It approaches the ideal efficiency of 100%, practically 70-90%, when considering loss, saturation voltage, and switching time. The Class E power amplifier is widely used in GSM applications. Class F power amplifier has a resonant circuit at one or more harmonic frequencies, the third harmonic frequency, 3f 1 as well as the fundamental frequency, f 1 to flatten out the voltage and produce a square wave output voltage. The principle of Class S power amplifier which uses a Pulse Width Modulation (PWM) input waveform amplifies this pulse width modulated signal with a highly efficient switching amplifier, and then recovers the input signal by low pass filtering. Table 2.2 summarizes the class mode of operation in terms of operating mode, conduction angle, maximum efficiency, linearity, and output power [Cri99, Su02].

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21 Table 2.2. Classification of power amplifier Class Operating Modes Conduction Angle Maximum Efficiency Linearity Output Power A 2 (100%) 50% Good Moderate B (50%) 78.5% Moderate Moderate AB -2 (50-100%) 50-78.5% Moderate Moderate C Current Source 0(50%) 100% Poor Small D (50%) 100% Poor Large E (50%) 100% Poor Large F Switch (50%) 100% Poor Large 2.2.3 Basic Parameters of Characterizing Power Amplifier For characterizing power amplifiers, output power, linearity, and power efficiency are the most important parameters in the design. In addition, gain, stability, bias network, and matching network are also important. The power amplifier consumes the most power in a transmitter and is therefore critical in designing higher efficiency transceivers. Also another major issue for designing the power amplifier is the linearity. As a number of users are increased in the allocated frequency band, the channels become close to each other as mentioned before. Since no channel interference is ideally desired, a high linearity is required in the power amplifiers. The tradeoff between the efficiency and linearity in a power amplifier should be considered because a linear power amplifier such as Class A has high power consumption with high linearity. Since the 5GHz WLAN application requires high linearity, a linear power amplifier can be used at a cost of efficiency to meet the system linearity specification. Another way to improve the linearity is to use a nonlinear power amplifier applied with linearization techniques which increases the cost and complexity. Efficiency (also called drain efficiency) is defined as Power delivered to the load / Power dissipated by the amplifier.

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22 Supply thefromDrawn Power Load the toDeliveredPower PP Efficiencydcout (2.20) In addition, as the input power is considered, Power Added Efficiency (PAE) is defined as Supply thefromDrawn Power SignalPower Input Load the toDeliveredPower G1-1 PPP PAEPdcinout (2.21) where P in is the RF drive input power, P out is the RF output power delivered at the load, P dc is the dc power drawn from the supply, and G P is the power gain. In the practical design of power amplifiers, the efficiency will be decreased by considering the matching network and a finite knee voltage. Severe reduction in efficiency can occur when packaging the amplifier. Linearity is also another key design parameter. There are several methods to measure the nonlinearity which can be characterized by output power 1dB (P1dB) compression point, 3 rd order Intermodulation Distortion (IMD3), 3 rd order Intercept Point (IP3), Adjacent Channel Power Ratio (ACPR), Multi-Tone Power Ratio (MTPR), and Error Vector Magnitude (EVM). The nonlinearity causing imperfect reproduction of the amplified signal is mainly created by the active component. In the MOSFET case, the transconductance (g m ) and C gs are the largest causes of the nonlinearity. Compared to a power amplifier operating in the linear region, one operating near the saturation region improves the efficiency, but signal distortion is increased. Amplitude distortion such as a P1dB compression curve shown in Figure 2.6 will be generated by clipping current or voltage waveforms. The 1dB compression point of an

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23 amplifier is defined as the output power level at where the amplifier’s transfer characteristic deviates 1dB from ideal curve of an amplifier. Figure 2.6. Output power versus input power characteristic with single-tone sweep A two-tone test is used for evaluating amplifier nonlinearity characteristics with a Continuous Wave (CW) signal. The two-tone signal varies the envelope of the input signal to measure the nonlinearity in the time-domain. After a Discrete Fourier Transform (DFT), the amplifier output spectrum of a two-tone test in the frequency-domain is shown in Figure 2.7. In an ideal power amplifier case, when applying a two-tone input signal into the amplifier, there should be only two amplified signals at fundamental frequencies f 1 and f 2 in the output spectrum; no other products should be within the band of interest. In reality, when applying a two-tone signal to an amplifier which has nonlinear characteristics, there exist a large number of harmonics and intermodulation products (i.e., IM3, IM5, IM7, and so on), at the output of amplifier.

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24 Figure 2.7. Spectrum of a power amplifier with a two-tone test Assuming that an amplifier with a transfer characteristic using standard power series formulation is ... t)(vK t)(vK t)(vK t)(v3i32i2i1o (2.22) With an input signal consisting of two equal amplitudes, )cos(A )cos(A t)(v21itt (2.23) The output voltage is ... ))cos( )(cos(AK ))cos( )(cos(AK ))cos( )(cos(AK t)(v3213322122211otttttt (2.24) After some trigonometric manipulation, the output is divided into the in-band (odd-order) intermodulation products and the out-of-band (even-order) intermodulation products. These in-band intermodulation terms, usually up to seventh-order, are produced at frequencies, f 1 , f 2 , 2f 1 -f 2 , 2f 2 -f 1 , 3f 1 -2f 2 , 3f 2 -f 1 , 4f 1 -3f 2 , and 4f 2 -3f 1 . Since the third-order spurious products at 2f 1 -f 2 and 2f 2 -f 1 are within the band of interest, the most commonly used measure of intermodulation distortion from a two-tone test is IMD3 which is defined as the ratio of the largest intermodulation product (IM3) to the amplitude of one

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25 of two fundamental tones. Also, IP3 is generally defined as the point where extensions of the first and third order responses intersect on the output power scale. Due to nonlinearities and spectral regrowth, ACPR can be characterized by how much transmitted signal leaks into adjacent channels causing interference for other users. ACPR is defined as the ratio of the amount of power transmitted in the channel band of interest to the power leaked into the adjacent channel shown in Figure 2.8. ACPR requirements for WLAN application are indicated in the power amplifier specifications in the following chapter. chadjPP ACPR (2.25) Figure 2.8. Adjacent channel power spectrum Amplitude Modulation to Amplitude Modulation (AM-AM) and Amplitude Modulation to Phase Modulation (AM-PM) nonlinearity characteristics for the power amplifier are obtained by measuring the gain and phase as a function of input power. As the input CW signal applied to a power amplifier increases until certain level of gain compression is produced, it is called AM-AM conversion. If the input signal is further increased, a slight phase shift of the amplifier will be generated, which is known as AM

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26 PM conversion. The most common AM-PM effects can be demonstrated with asymmetrical intermodulation products from the two-tone test or spectral regrowth from the ACPR test. Many amplifiers include a specification that shows a certain maximum value of AM-PM conversion. From the WLAN 802.11a power amplifier specification, -6 to 6 degrees at 1dB output power compression point is tolerable. EVM is the ultimate measure of distortion by measuring the modulation accuracy of the transmitter in high data rate modulation types such as IEEE 802.11a OFDM. Error vector represents the difference the measured signal and a reference signal. The EVM is defined by the RMS value of the error vector signal divided by the RMS value of the undistorted signal which is specified in percent. The adjacent channel power measures the power in the neighbor relative to the power in the unwanted channel. EVM can be expressed either as a percentage or in decibel [Voe95]. 100 magnitude signalpeak magnitudeerror average (%) EVM (2.26) (%) 100-(%) EVMlog20 (dB) EVM (2.27) A small magnitude error in a power amplifier causes a significant degradation in ACPR and EVM. The output spectrum mask of the power amplifier when applying OFDM WLAN is illustrated in Figure 2.9. 2.2.4 Review of Literature on CMOS Transceivers There are many examples in the published literature that relate to the transceiver design and commercial transceiver chipset products using CMOS technology. This section reviews further CMOS transceiver and power amplifier designs conducted over the last few years. It is also important to note that power amplifiers have been

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27 implemented with compound III-V semiconductor technologies. Recently, as a part of transceiver chip, microwave and RF CMOS power amplifiers have been developed and used in various applications such as Bluetooth, mobile personal communications, and WLAN. Figure 2.9. Output spectrum mask with 5GHz OFDM signal

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28 Since CMOS technology has been used for RF from 1990s, many RF building blocks as well as RF transceivers are designed with CMOS. From the middle 1990s, many research papers for RF CMOS power amplifiers have been published. Rofougaran et al. demonstrated CMOS power amplifier operating in the 900MHz band [Rof94]. They designed Class C power amplifiers with an off chip matching network to deliver 15dBm output power providing a controllable power between 20W and 20mW from 3V supply voltage. Su and McFarland designed a monolithic RF CMOS power amplifier which was fabricated in 0.8m CMOS technology [Su97]. The power amplifier which does not require linearity provides 1W of output power at 800MHz band with a single 2.5V supply voltage. The prototype CMOS power amplifier consists of input matching network, gain stages with Class A, AB, and D operations, and output stage with switch-mode operation including the output matching network. Research on CMOS power amplifiers is demonstrating various wireless transceiver applications. Gupta and Allstot designed a fully monolithic balanced power amplifier with Class AB operation [Gup98, Gup99]. To demonstrate the CMOS potentiality for RF applications around 2GHz band, Giry, Fournier, and Pons developed a two-stage single-ended CMOS power amplifier using 0.35m CMOS technology which obtained PAE of 35% with 23.5dBm output power [Gir00]. Continuing the effort of developing CMOS power amplifiers, for 1.9GHz band wireless applications, Asbeck and Fallesen [Asb00], and Chen et al. [Che00] have implemented CMOS power amplifiers integrated fully on-chip with medium output power. As well as developing many CMOS power amplifiers, the need for a single chip realization by integrating all building blocks is increasing. In the past, GaAs and

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29 BiCMOS processes have been dominant for RF transceiver system design. However, as wireless communication markets increase, CMOS technology is becoming a dominant technology for transceiver design to realize RF systems on a chip [Abi03]. With persistent progress on CMOS processes, several transceivers designed using CMOS technology are in the literatures and commercial products have been developed. Since 2001, CMOS transceiver chipsets have been developed for Bluetooth applications [Dar01, Dar05, Eyn01]. Bluetooth uses 2.4GHz ISM band and supports a data rate of 1Mb/s using a Gaussian Frequency Shift Keying (GFSK) modulation scheme. Eynde et al. achieved a low-cost integration of Bluetooth modem with all necessary analog and digital functions realized in the 0.25m CMOS technology. In this paper, the power amplifier is integrated on-chip and delivers up to 2dBm. Also, Darabi et al. developed a fully integrated radio transceiver including all the receiver and transmitter building blocks and analog sections using the TSMC 0.35m CMOS process. The power amplifier is designed with a fully differential structure which consists of a preamplifier and Class AB driver amplifier. CMOS technology has also been widely applied for WLAN 802.11 a/b/g applications. For the transceiver design, the superheterodyne architecture is widely used. However, the superheterodyne architecture is not a preferred solution because it requires an off-chip Surface Acoustic Wave (SAW) filter and two synthesizers while the direct conversion architecture uses only a small synthesizer. Even though the direct conversion architecture has a few drawbacks such as DC offset and local oscillator leakage, the direct conversion architecture becomes more popular in order to provide a low cost solution for high volume of products such as WLAN applications. Many WLAN

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30 transceiver chipsets have been developed with direct conversion using CMOS technology [Aoh04, Beh03, Mae05, Per04, Vas03, Zar02, Zha03]. Table 2.3 shows several transceivers designed with CMOS technology for WLAN 802.11a applications and compares the transceiver implementations with partially or fully integrated power amplifiers. If an integrated power amplifier should not deliver the required output power, then it can be used as a preamplifier to drive an external power amplifier. Some of transceivers utilize external power amplifiers to boost the output signal. Table 2.3. CMOS transceivers integrated with power amplifier Reference Papers Transceiver Architecture WLAN type PA Integration CMOS Process [Beh03] Direct a Class AB 0.18 m [Per04] Direct a/b/g External 0.25 m [Zar02] a Class A 0.18 m [Zha03] Direct a External 0.18 m [Vas03] Direct a Driver Amp. 0.18 m Also, as the data rate is increasing for WLAN applications, linear or linearized power amplifiers are needed because of stringent linearity requirement, for examples, WLAN 802.11a/g. If nonlinear power amplifiers are designed and used for such applications, then linearization or efficiency enhancement techniques which depend on what types of applications will be applied.

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CHAPTER 3 DESIGN METHODOLOGY FOR RF POWER AMPLIFIERS The power amplifier is the last output stage in the transmitter architecture; it provides the power amplification of an input signal to an antenna and plays a critical part in determining entire power efficiency of a transmitter. Among various types of power amplifiers described in the previous chapter, a Class A power amplifier was designed in this research. In the power amplifier built with several stages, the most critical stage is the output stage that consumes most of the current. Considering linearity, efficiency, output power, and bias current, the power amplifier provides sufficient linearity while maintaining reasonably high efficiency. After reviewing the basics of the power amplifier in the previous chapter, this chapter shows how CMOS power amplifier is designed in order to obtain a high performance power amplifier over the specification. The goal of this research is to design and implement a CMOS power amplifier that can be integrated in a CMOS transceiver. Selecting the power amplifier structure, the transistor size and the optimum load impedances for each stage are determined. Also, several key design parameters such as biasing circuit, stability, and cutoff frequency will be described and the layout issues are examined. To design the proper input and output matching networks in the power amplifier, the conjugate matching, load-line, and load-pull methods are used. The two schematics and layouts for CMOS power amplifiers are described. Since the power amplifier is 31

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32 measured at the board level, it should be packaged to be mounted on the board. The package and bondwire diagrams are shown in the last part of this chapter. 3.1 Specification for 5GHz Power Amplifier Design An RF CMOS power amplifier is designed for WLAN 802.11a applications. The fully integrated differential power amplifier, operating at the 5-6GHz bands, is implemented in a 0.18m IBM 7WL BiCMOS SiGe process. This process has seven metal layers and thin-oxide metal-metal capacitors which are high density. As a result, the chip size as well as the cost of the complete power amplifier is reduced. The configuration of the power amplifier is a three-stage cascaded structure with a common source-common gate cascode with 3.3V supply voltage. In addition to the general specification for the transmitter described in the previous chapter, the specific key design requirements for an OFDM 5GHz power amplifiers are listed in Table 3.1. Table 3.1. Design specifications for OFDM 5GHz power amplifier Design parameters Specification Supply voltage 3.3V Operating frequency range 5150 to 5825MHz Power/voltage gain 25 to 30dB Output power (P1dB) 25dBm (with CW signal) Efficiency (Power added efficiency) > 20% Input/output VSWR 2:1/3:1 Gain ripple over frequency 2dB Temperature -40 to 85 o C AM/PM -6 to 6 degrees at P1dB point -30dBc (f c +/11MHz) -38dBc (f c +/20MHz) ACPR -50dBc (f c +/30MHz) EVM 3% at Pout = 18dBm

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33 3.2 Concept and Key Design Issues Due to its stringent linearity requirement for 802.11a applications, a Class A power amplifier (which is the most linear) is chosen at the cost of efficiency. The design with the three-stage of cascaded amplification is chosen to achieve the required gain, more than 25dB (Figure 3.1). The output stage is designed to provide maximum output power while the first and second stages are designed for maximum gain. The design procedure starts from designing the output stage of the power amplifier due to its influence on the critical output power and efficiency performance requirement through the entire stage. Figure 3.1. Three-stage power amplifier with matching networks A differential architecture is chosen for the power amplifier design because of its advantages of reducing the effect of ground inductance as well as canceling the noise and even harmonics. Since a differential power amplifier drives a single-ended input of a system, the extra circuit converting from differential output to the single-ended input should be designed and placed after the power amplifier output (balun or transformer) at the expense of mismatch and cost. A cascode common-source common-gate configuration in a stage and its equivalent circuit are shown in Figure 3.2. The cascode structure increases the small-signal output resistance compared to the single transistor gain stage and also reduces the impact of the Miller capacitor. Furthermore, it provides good isolation between the input and output because there is no direct connection between them.

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34 Figure 3.2. Cascode output stage schematic and its equivalent circuit 3.2.1 Determination of Transistor Size Once the type and structure of an amplifier are established, all necessary component values for designing the power amplifier including I d , load impedance, transistor size, gain, and efficiency are calculated and selected. The transistor size is determined based on I-V characteristics of the NMOS transistor. As the transistor size changes, the proper bias point can be chosen by looking at the amount of current from the I d -V gs curve. This makes possible to pick a bias point, V gs . Figure 3.3 shows the drain current, I d , along with the V gs variations. The drain current, I d , in the saturation region, depends on the W/L ratio of transistor and gate bias voltage. 2tgsoxn2satd,satd,tgsoxnd)VV(LW2C 2VV)V(VLWC I (3.1) where the drain current has a square law dependence on V gs .

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35 Figure 3.3. Transistor I-V characteristics with the gate width of 1000um 3.2.2 Selection of Optimum Load Impedance Next, the optimal power load impedance, Z opt , related to the power amplifier performance usually differs from the typical 50 termination. To obtain the maximum output power with the maximum current and voltage swing at the drain, the optimum load resistance, R opt , should be determined. Figure 3.4 shows R opt as a value looking into the output of the amplifier. Given the conditions with the required output power of 300mW and supply voltage of 3.3V in a 50 antenna, the optimum load resistance (R opt ) is calculated as R 2V P2rms (3.2) opt2ddmax o,R2V P (3.3) 18 30023.3 P2V R2max o,2ddopt (3.4)

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36 Figure 3.4. Output optimum load resistance After considering knee voltage and losses from the matching network and interconnects, the optimum load resistance is selected, a 15 load. Then, the amount of drain current is around 200mA. From the output power versus output load simulation (which will be shown in a later section), the amplifier is the most linear when R opt equals around 15 to 20. After R opt is selected, it is transformed to the 50 load antenna through the output matching network. When output voltage swing approaches zero, the operation of the transistor is limited by cutoff (lower limit). On the other hand, it is limited by saturation (upper limit) when the output voltage swing approaches the supply voltage. The gate and drain voltage swing is also limited by the oxide breakdown voltage. It is the differential structure that overcomes those limits and doubles the output voltage swing.

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37 3.2.3 Biasing Circuit and Stability The bias circuit should be carefully designed because it may cause the power amplifier not to work properly. There are many analog bias circuits. In one example, the DC voltage from the DC supply is directly applied into the power amplifier circuits. However, it does not guarantee that the current amount flowing in the amplifier is accurately controlled. Another method to feed the DC signal to the circuit uses a passive device (resistor). A voltage divider with two resistors is rarely used because the resistor variation is large. So in this design, the cascode current mirror is used as a bias circuit which is capable of providing a predetermined amount of current. The stability is one of the important considerations in designing a power amplifier. One way to measure the stability of a power amplifier is the Rollette stability factor (k), which is based on S-parameter data. |S||S|2|SS-SS||S||S|1k 2112221122211222211 (3.5) If the k-factor is greater than unity at a certain frequency, then the amplifier with input and output matching is in a stable condition [Abr00; Raa03b]. However, this is only useful for the single-stage amplifier. Another approach to check for potential oscillations of the entire three-stage amplifier is using transient simulation up to 100nsec. In Figure 3.5, the test circuit to check for potential oscillations is shown. An input transient signal having three periods is applied into the amplifier. The output transient response should be zero after the third period. If the output signal keeps ringing, then the amplifier will oscillate.

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38 Figure 3.5. Test circuit for stability 3.2.4 Cutoff Frequency One of the parameters to describe a transistor’s speed is the current gain cutoff frequency, f T , sometimes called transition frequency, defined as the frequency when short circuit current gain equals, h 21 to 1. 1 )CC(g )C(vgv ii hgdgsmgdgsinminind21C (3.6) )CC(2g fgdgsmT (3.7) From Equation (3.6), using 0.18m technology values for C gs , C gd , and g m , the calculated value of the cutoff frequency is around 18.5GHz, with the NMOS transistor. (The output stage transistor was set with the 1000m gate width biased at 1.45V V gs .) The equivalent circuit of the bottom transistor of cascode is shown in Figure 3.6. Figure 3.7 illustrates the cutoff frequency for the minimum transistor size (L=0.18m,

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39 W=0.6m) from the simulation, which was around 24GHz. With the transistor size of L=0.18m and total W=1000m for the output stage, the cutoff frequency is around 18GHz shown in Figure 3.8. Comparing these two plots, with the downscaling MOS size, f T is increased, as C gs is decreased. Figure 3.6. Equivalent circuit to calculate the cutoff frequency Figure 3.7. Cutoff frequency plot for the minimum transistor size

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40 Figure 3.8. Cutoff frequency plot with the total gate width of 1000m 3.2.5 Issues on Fabrication Process and Layout CMOS technology has many advantages mentioned in previous chapter. However, as CMOS scales into deep sub-micron, it suffers from low breakdown voltage compared to other compound semiconductor technologies. Also, of concern are on-chip passive components. Especially, the Q-factor of the on-chip inductor is relatively poor compared to discrete passive components. All these difficulties make power amplifier design more challengeable to meet specifications. To layout high frequency power amplifiers needs careful considerations. Above all, the RF signal paths should be routed as short as possible. The on-chip inductors are placed at least 100m away from each other to prevent coupling effects. Similar to power amplifier applications providing the huge amount of current, Electromigration (EM) rules are carefully considered in the layout. Due to the EM

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41 failures caused by extremely high current density, metal width sufficient for the amount of current for connections and routing for each stage should be carefully determined. The maximum current can be estimated based on WtJ10 Imax-9max (3.8) where I max is the maximum current (in mA), J max is the maximum allowed current density (in A/cm 2 ), W is the width of the metal (in m), and t is the thickness of the metallization (in ) [Has01]. As an example, the estimated metal width is 2.8mA/1m for bottom metal layer and 5mA/1m for top metal layer. It is also important to decide the correct metal width when using an on-chip inductor. After the layout is done, the pattern density should be fulfilled to balance the density in the sparse and dense areas provided of the design. To meet the pattern fill requirement, several selected active or metal layers are filled up to certain area percentages over the entire layout size. This task is the most time consuming one required to pass this pattern rules. 3.2.6 Power Amplifier Design Procedure Finally, after designing each stage, all stages should be put together. The purpose of the interstage matching between stages is to make signals flow without reflections. Interstage match uses a simple shunt C and series L matching network which transforms the impedance seen looking into the next stage to the desired impedance of the previous stage. A high-pass topology with series C and shunt L is chosen as the interstage matching while minimizing the number of passive components. The coupling capacitor of Metal-Insulator-Metal (MIM) structure will be placed between stages so that dc bias can

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42 be separated. The flow chart of power amplifier design procedure is as follows (Figure 3.9). Figure 3.9. The flow of design procedure 3.3 Optimum Matching Network Design The previous section explained how the optimal load impedance was selected from the calculation. From this point, small-signal and large-signal matching methods are described. Unlike general amplifiers such as low noise or wideband amplifiers, for designing power amplifiers, a matching network configuration is required, e.g., gain conjugate matching and Cripps power matching [Cri99]. The output stage is initially designed using a complex conjugate matching method to obtain maximum power transfer

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43 to the antenna, and then, designed in a second phase using a load-line and load-pull approach to maximize the output power at the cost of maximum power transfer. 3.3.1 Small-Signal Conjugate Matching Method The best match for maximum power transfer is achieved by a simultaneously conjugate match of the input and output. From the s-parameter simulation, the S 11 and S 22 data can be obtained versus frequency simulated power amplifiers. S 11 and S 22 values are S 11 = 20 j130 and S 22 = 15 j36 at the frequency of 5.25GHz. For the conjugate input and output matching, the Smith chart graphically shows s-parameter data (impedance and admittance values). The path for the input (S 11 ) and output (S 22 ) matching in the Smith chart is illustrated in Figure 3.10. 3 Figure 3.10. S 11 and S 22 small-signal conjugate matching method using Smith chart 3 The path was drawn using Smith tool v1.2

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44 3.3.2 Large-Signal Load-Line and Load-Pull Matching Method In the case of matching network design for power amplifier output, it is useful for power matching to obtain maximum output power at the optimum load impedance. (Previously, conjugate matching was used to attain higher gain.) Since maximum output power and maximum power transfer cannot be achieved at the same time, power amplifier design should compromise between gain and output power using both conjugate matching and power matching. There are two large-signal matching methods: load-line and load-pull approaches. As mentioned before, the load-line approach is to find optimum load resistance, R opt , in order to utilize the maximum current and voltage swing of the transistor. Figure 3.11 shows the fundamental maximum output power along the different load resistance values from the simulation result. Figure 3.11. Output power versus load resistance

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45 The load-pull method finds the optimum impedance point for the power amplifier to obtain maximum output power while changing the load impedance value on the Smith chart. Load impedance is chosen with a compromise between PAE and power delivered. Then, a matching network is designed to set the desired impedances sought from the load-pull test. It is not possible to match the entire frequency band of interest. In Figure 3.12, a conventional single-ended load-pull block diagram is illustrated to perform the load-pull simulation. Figure 3.12. Load-pull simulation block diagram The optimum impedances of each stage from the load-pull simulation are Z opt1 = 150 + j78 for the first stage, Z opt2 = 75 + j55 for the second stage, and Z opt3 = 13 + j12 for the output stage (Figure 3.13). The load-pull simulation performances for three-stage and two-stage power amplifiers are compared in Figures 3.13 and 3.14. The output matching network is built based on this result.

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46 Figure 3.13. Load-pull simulation result Figure 3.14. Load-pull simulation result with the 0.18um short channel device 3.3.3 Matching Network Structure Once the source and load impedance are selected at a certain frequency, input and output matching networks are synthesized as shown in Figure 3.15. From the selected input impedance of amplifier, S 11 = 20 j130, it is transformed to 50 using the T-type matching structure. For the output matching network, the optimum impedance, Z opt3 = 13 + j12, obtained from the load-pull simulation is transformed to 50. In addition, the

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47 integrated on-chip DC-block capacitors (C s1 , C s2 ) are used as the parts of the input and output matching, consequently, there is no need to use a bias tee. When comparing with simple L-type matching network, this T-type and -type matching network brings an extra degree of freedom and makes the design of a matching network easy by using another matching component. Figure 3.15. Input and output matching networks 3.4 Power Amplifier Schematic and Layout There are two kinds of power amplifiers which were designed in this research. The first version of power amplifier is designed with three-stage cascaded structure and the second version of the power amplifier is designed with two stages. Two schematics and their corresponding layouts are presented in this section. Once the output stage has been designed first, the previous stages are designed in order to provide the required gain. Because the power amplifiers are measured on board level, the amplifier die should be mounted on the package. The bondwire diagram showing the connection between chip bond pads and package lead gives the pin description.

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48 3.4.1 Power Amplifier Schematic The first schematic of the CMOS differential power amplifier is shown in Figure 3.16. The power amplifier has three stages to provide sufficient gain. To achieve the desired output power at the power amplifier output, 1 unit transistor, 2 unit transistors, 10 unit transistors are placed in first, second, and output stages. Multiple transistors which have a unit transistor size of 0.4m length and 5m width with 20 fingers are connected together in parallel. The amounts of DC currents of each stage on a differential branch are around 5, 20, and 100mA, respectively. The cascode current mirrors with the ratio of 1:5, 1:20, and 1:100 are used in each stage as biasing circuits of the power amplifier. To prevent a bias oscillation in the low frequency band, proper bypassing capacitors, here 5pF and 2pF are placed on the paths between power supply and ground and also between DC bias and ground, respectively. The second power amplifier is designed with two stages. Compared to the first power amplifier schematic, the bottom transistor is changed to the minimum transistor of 0.18m length and the total number of cascode unit transistor for first and output stages is increased to 2 and 12, which provides 10mA and 120mA, respectively. The size of one unit transistor is 0.18m length and 5m width with 10 fingers for the bottom transistor and 0.4m length and 5m width with 20 fingers for the cascode transistor. By changing the length of the bottom transistor from 0.4m to 0.18m in cascode configuration, the parasitic capacitor, C gs , is reduced to two times less. In the second design, the bypass capacitors resided across power supply to ground are increased to 100pF. Figure 3.17 shows the two-stage power amplifier schematic with slightly different input and output matching networks.

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Figure 3.16. Three-stage power amplifier schematic 49

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Figure 3.17. Two-stage power amplifier schematic 50

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51 3.4.2 Power Amplifier Layout With the power amplifier schematics, two layouts were created for fabrication in this research. Unlike the other building blocks in transceiver, the layouts of the power amplifiers have to be carefully drawn because power amplifiers should handle huge current flow. The differential power amplifier circuits are laid out symmetrically with the same lengths on connections. The RF input and output signal paths are kept as short as possible between stages to minimize the parasitic resistance and capacitance for metal routing. The input and output pads are arranged in ground-signal-ground-ground-signal-ground (also called “G-S-G-G-S-G) with the spacing of 150m between pads. For the RF input and output signal paths, except for supply and ground, bond pads with deep trenchs are used to reduce the coupling to substrate to provide good isolation. Also, multiple bond pads for ground are used to minimize the ground inductance from bondwires for each stage. Here, by down bonding between ground bond pads and package paddle, the ground inductance value was reduced by approximately factor of 16. The layout of the first version of the power amplifier chip is presented in Figure 3.18 that shows the design filled with extra layers. To minimize the parasitic effect on the drain interconnections of multiple MOSFETs, a special metal structure is used. The chip area is 1.8mm1.8mm (3.24mm 2 ) including the 27 bonding pads, 10 bypass capacitors, and 12 on-chip inductors. In Figure 3.19, the layout of the second version of power amplifier chip is shown. The chip size of the layout is the same as that of the first power amplifier layout and the same package type and size and the same board are used. Instead of three-stage amplifier

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52 in the first version, this second power amplifier has two stages with 24 bonding pads and 8 on-chip inductors. The one large bypass capacitor is composed of 15 small capacitors in parallel, which one unit capacitor has 6.7pF, with overall capacitance being 100pF. The total layout size of one 100pF capacitor is 210m245m which is almost same as one 1.5nH inductor size. The component parameters including transistors, inductors, capacitors, and resistors for power amplifiers are shown in Table 3.2. Figure 3.18. Three-stage power amplifier layout

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53 Figure 3.19. Two-stage power amplifier layout 3.4.3 Bondwire and Package Parasitic Models and Diagrams Since the parasitic sources from the bondwire and the package significantly affect on the power amplifier performance, the entire power amplifier test circuit should include both bondwire and package parasitic models during the simulation. The die is mounted in the package and connected to the pin of the package through bondwires. Due to their parasitic effects, a precise parasitic estimation is needed for the whole design for a close coincidence between simulation and measurement results.

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54 Table 3.2. Component parameters for power amplifier schematics Component Parameter (Three-stage PA) Parameter (Two-stage PA) M 11 0.4m50m 0.18m100m M 13 0.4m50m 0.4m200m M 21 0.4m200m 0.18m600m M 22 0.4m200m 0.4m1200m M 31 0.4m1000m M 32 0.4m1000m M mirror, bottom 0.4m10m 0.18m5m M mirror, up 0.4m10m 0.4m10m C bypass, Vdd 5pF 100pF C bypass, bias 1.85pF 2pF L in1 2.41nH 4.249nH C in1 1.27pF 1.8pF L in2 1.16nH C in2 2pF L d1 1.23nH 0.785nH L d2 0.5nH 0.85nH L d3 1.3nH C 12 1.84pF 2.5pF C 23 2.5pF R f1 1k 1k C f1 1pF 1pF R bias 2k 2k L out1 0.98nH 1.23nH C out1 450fF 350fF C out2 1.83pF 2.5pF The estimated bondwire and package models provided by Conexant Systems, Inc. in both input and output matching network of power amplifier are included (Figure 3.20). For the initial design, the estimated values of 23pH/mil for inductor and 9m/mil for resistor are added in the earliest schematics. So the values for the bondwire length of 750m (=30mils) are 690pH and 270m on the RF input and output paths and 1nH and 350m on all other paths initially.

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55 Figure 3.20. Initial estimated value of bondwire and package models The parasitic bondwire inductance value for this bondwire model is about 25pH/mil with 1.0mil diameter gold bond wire. If a longer bondwire is used, then more parasitic inductance value is generated. One thing that may reduce the inductance by about 50% is having two parallel bondwires instead of one bondwire, but in that case a larger bond pad is necessary to fit the double bonds. Also, the plastic Micro Lead Frame (MLF) 44 16-pin package manufactured by Amkor Corporation is used in this research. Making a package plays an important role in RF chip design, here it enables a connection between the power amplifier die and PCB. This MLF package provides an exposed ground paddle which allows downbonds connecting between bond pads and paddle, not directly bonding from bond pads to a pin for ground connections. Originally, the package used in this design was 4mm4mm body size of a 16-pin MLF package. However, having the down bonds, this power amplifier chip whose size is 1.8mm1.8mm cannot be fit in this body size. For the 4mm4mm package, the paddle

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56 size is 2.3mm with 0.25mm clearance on each side for down bonds. This 4mm4mm package is only enough for the case without any down bonds. With down bonds, 0.66mm minimum on each side is required. So finally, a 5mm5mm body package which has a bigger paddle size (3.3mm3.3mm) was used. The die is attached with a conductive epoxy to the package paddle. The bondwire connects the bond pad in the chip to the pin lead in the package. Bondwires can be modeled with passive components, resistor, inductor, and mutual inductance of inductors. One of the bondwires shown schematically in Figure 3.21 represents an equivalent circuit model. The signal coming from the package lead goes to chip bond pad through this bondwire model. The range of parameters for bondwire models, which depend on the bondwire length, used in the power amplifier design is following: Resistor, R1: 232m ~ 453m, Inductor, L1: 0.35nH ~ 1nH, Mutual inductance, K: -0.002 ~0.14 Figure 3.21. Equivalent circuit for bondwire model

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57 In Figure 3.22, the equivalent circuit model for one of the package leads is presented. The signal coming from the external source (named here, “from external”) goes to the bondwire whose pin named, “to bondwire”, followed by an actual power amplifier chip through bond pads. The parameters for one package lead used in this model are approximately 100fF for C1, 39fF for C2, 110fF for C3, 40fF for C4, 0.39nH for L1, and 40m for R1. For the rest of package leads, the parameters are not much different with those values above. Figure 3.22. Equivalent circuit for package model Figures 3.23 and 3.24 show two bondwire and package diagrams; one is for three-stage first power amplifier, the other is for two-stage second power amplifier. These models were generated at center frequency, 5.25GHz. There are lots of down bonds for chip ground in the bondwire diagram to minimize the ground inductance produced from bondwires. The power amplifier package pin names corresponding to the bondwire diagram are listed in Table 3.3. There are seven V DD connections, where two V DD s for each stage and one for bias in the first diagram, whereas there are four V DD connections for two-stage in the second diagram.

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58 Figure 3.23. Bondwire diagram for 1 st power amplifier Figure 3.24. Bondwire diagram for 2 nd power amplifier

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59 Table 3.3. CMOS power amplifier package pin names in bondwire diagram Pin number 1 st power amplifier 2 nd power amplifier 1 Ground Ground 2 Input + Input + 3 Input Input 4 Ground Ground 5 V DD 4 Ground 6 V DD 5 V DD 3 7 V DD 6 V DD 4 8 V DD 7 Ground 9 Ground Ground 10 Output + Output + 11 Output Output 12 Ground Ground 13 Ground Ground 14 V DD 3 V DD 2 15 V DD 2 V DD 1 16 V DD 1 Ground

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CHAPTER 4 DEVELOPMENT OF DIFFERENTIAL LOAD-PULL TECHNIQUES In wireless communication systems, power amplifiers are the most power consuming block in a transceiver. To improve the output performance of power amplifiers, optimum load impedance should be determined for the best trade-off from the load-pull measurement in terms of efficiency, output power, and gain. Since the 1970s, research efforts have been devoted to develop the load-pull measurement system. Starting with a large signal s-parameter characterization of power transistors, there exist several methods to construct power contours. The automatic power load contour mapping technique was introduced using a computer controlled apparatus [Cus74]. Then, a theory, called Cripps method, was published [Cri83]. The Cripps method is able to predict the power load-pull contours using a convenient mathematical formulation. Since the principle of load-pull techniques has been published, load-pull systems have been broadly developed and used for the nonlinear large-signal characterization of amplifiers [Tak76]. Several companies developed the load-pull measurement systems with mechanical and automated tuners. Those load-pull systems are only restricted to single-ended circuits or systems. Since a differential load-pull system was introduced using the 180 o Hybrid component [Mah99], differential load-pull techniques have been popular for analog and RF designs. In this research, a fully differential power amplifier is implemented. As in single-ended load-pull systems, a differential load-pull system is necessary for 60

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61 differential circuits. This research attempts to develop a new differential load-pull system utilizing the existing facilities – two single-ended tuners instead of one differential tuner. Mixed-mode s-parameters developed by Bockelman and Eisenstadt [Boc95a; Boc95b] are used to calculate mathematical transformation for differential-mode and common-mode test. 4.1 Load-Pull Techniques Load-pull is necessary to obtain the optimum performance of power amplifiers by finding the optimum load impedance at any input power level. The principle of load-pull measurement techniques is to vary load impedances to get the amplifiers that are optimized for output power and efficiency. Load variation is performed by the automated load tuner running by the tuner controller. The incident and emerging powers are measured by power meter for various impedance positions. The result from load-pull measurement represents a set of constant output power contours which is plotted on a Smith chart showing all possible load impedances. While this traditional load-pull system is useful for characterizing single-ended devices, it may not adequately provide the performance of differential amplifiers. Recently, Focus Microwaves Inc. proposed a differential load pull system using a differential tuner [Foc03]. A single-ended unbalanced input signal is split into two balanced signals, which are injected into differential devices. Then, the signals amplified by the differential devices (called device under test (DUT)), are delivered to the output differential tuner and are finally transformed by the output balun transition board to unbalanced signals. The transmission loss of the baluns, differential tuners and differential test fixtures are calculated and calibrated.

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62 As a classical four-port network analyzer is inappropriate for large-signal characterization measurements, the differential load-pull technique can be used. In this research, a new differential load-pull technique is applied to characterize a differential power amplifier. Assuming that input is properly matched with the conjugate matching method, two single-ended independent tuners will be used to characterize the differential load-pull at the output of the power amplifier and directional couplers and a mixer measures a phase difference. This system can be realized at a lower cost without additional purchasing the differential tuners. 4.2 Conventional Load-Pull Measurement Setup In this section, a single-ended conventional load-pull measurement setup procedure is explained. The setup is required to perform the measurement. Before beginning a load-pull measurement, tuner characterization and calibration should be completed. After this step, the load-pull measurement will be accurately performed. First, after installing the software and GPIB board, measurement instruments which are properly setup for the load-pull measurement and connected through the GPIB. Model numbers and drivers for selected instruments are installed and addresses for them are assigned correspondingly. Then, each instrument, such as network analyzer, RF signal source, and power meter, is initialized and calibrated with the proper setting. Instrument setup for a load-pull system is shown in Figure 4.1. After all instrument setup is done, the s-parameter block diagram in the configuration file is made for characterizing the tuner in Figure 4.2. Setting up this block diagram with the network analyzer and tuner, the tuner is characterized at the frequencies, 2.4GHz and 5GHz, respectively. Figure 4.3 displays the characterization data with 274 positions shown in the Smith chart.

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63 Figure 4.1. Instrument setup for load-pull system Figure 4.2. Tuner characterization block diagram Figure 4.3. Load tuner characterization display

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64 After the calibration and characterization for tuner are completed, the load-pull measurement can be performed. A conventional single-ended load pull block diagram is presented (Figure 4.4). It was captured from the real measurement system. The single-ended load-pull system consists of tuner, tuner controller, signal generator, power meter or spectrum analyzer, bias tees, and power supply. The automated tuner is an electromechanical instrument, where a stepper motor controlled by the tuner controller moves a slug (RF probe) vertically or horizontally in a slotted transmission line and controls load reflection coefficients. After accurate calibration is completed, the tuner finds the optimum load impedance by changing the load impedance automatically, which is controlled by the tuner controller. Output power is measured using the power meter as input power levels supplied from the signal generator increase. The measurement result plot shows output power, gain, and efficiency contours at the optimum load (Figure 4.5). Also, the measurement values of output power, gain, and efficiency contours at the input power levels are listed. Figure 4.4. Conventional single-ended load-pull block diagram

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65 Figure 4.5. Measurement result plot for the single-ended load-pull system 4.3 Standard and Mixed-Mode S-Parameters Mixed-mode s-parameters represent the complete set of 44 matrix containing differential-mode, common-mode, and cross-mode s-parameters in a four-terminal device. Mixed-mode s-parameters are very useful to observe the circuits’ differential-mode and common-mode behavior over conventional standard s-parameters because standard single-ended s-parameter data do not show coupling effects. The conventional standard s-parameters and mixed-mode s-parameters for a four-port circuit can be shown as the following.

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66 Figure 4.6. Four-port differential circuits Mathematically, a conventional standard single-ended s-parameter, S std , for four-port circuit is expressed as 4 4321444342413433323124232221141312114321aaaa S S S SS S S SS S S SS S S S bbbb (4.1) where a n and b n are incident power waves and reflected power waves, respectively. The power waves related to voltages and currents are defined as )Re(Z2Zivannnnn ; )Re(Z2Zivbnnnnn (4.2) 4 Mathematical derivations for the relationship between a conventional single-ended and mixed-mode S-parameter follows [Kur65; Boc95a; Boc95b].

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67 From the relationship between the single-ended and mixed-mode voltages and currents, the differential-mode and common-mode voltages and currents are defined as 43c243d221c121d143c243d221c121d1ii i 2ii iii i 2ii i2vv vv v v2vv vv v v (4.3) With the definition of the incident and reflected power waves in Equation (4.3), the mixed-mode s-parameters, S mm , are defined as c2c1d2d1cc22cc21cd22cd21cc12cc11cd12cd11dc22dc21dd22dd21dc12dc11dd12dd11cccddcddc2c1d2d1aaaa S S S SS S S SS S S SS S S S ][S ][S][S ][S bbbb (4.4) where [S dd ] are the differential-mode s-parameters with 22 sub-matrix, [S cc ] are the common-mode s-parameters with 22 sub-matrix, [S cd ] are mode conversion from differential-mode to common-mode waves with 22 sub-matrix, and [S dc ] are mode conversion from common-mode to differential-mode waves with 22 sub-matrix. Using Equations (4.2) and (4.3), the relationship between standard and mixed-mode incident waves is as the following 4321c2c1d2d1aaaa 110000111100001121 aaaa (4.5) It is true for reflected waves.

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68 4321c2c1d2d1bbbb 110000111100001121 bbbb (4.6) With setting 110000111100001121M (4.7) From Equations (4.1) to (4.7), the relationship between single-ended s-parameters and mixed-mode s-parameters can be expressed with following equation S mm = M S std M 1 (4.8) where S mm are the mixed-mode s-parameters; and S std are the standard s-parameters. By applying the matrix relation in Equation (4.8) into the data set using the equation function in the simulation, the standard s-parameters are converted to mixed-mode s-parameters. Mixed-mode s-parameters provide more information (differential-mode, common-mode, cross-mode terms) and higher accuracy (dynamic range) than balun-based measurements. 4.4 Differential Load-Pull Block Diagram and Simulation Results First, equations for the differential load based on mixed-mode s-parameters are inserted to find the optimum output impedance using the equation function in the simulation window. Also, the mixed-mode matrix is added into the equation and then a differential load-pull is simulated with two tuners in the schematic. After obtaining a successful outcome from the simulation, the differential load-pull simulation result is presented with the output power and efficiency.

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69 4.4.1 Differential Load-Pull Block Diagram and Operation A differential load-pull block diagram to realize the measurement system is shown in Figure 4.7. From a conventional single-ended load-pull measurement system, two tuners are originally used for performing the source-pull and load-pull measurement which are placed before and after the DUT. Assuming that the conjugate matching at the input of the amplifiers is properly made, the source tuner is used in conjunction with another load-tuner to perform the differential load-pull measurement. The DUT in the block diagram is replaced with the three-stage CMOS differential power amplifier, which was designed in chapter 3. The basic operation of the differential load-pull system is as follows. Two signals are applied to the differential power amplifier (DUT) and each tuner finds the optimum load impedances which are specified on power contour plots. The output powers passed through the tuners are measured and recorded using power meters at the optimum load impedance. Since power meters are scalar instruments limited only to the measurement of magnitude, which means they do not contain phase information, two directional couplers and a mixer are used for measuring the phase. Here, the mixer is for relative phase detection by a difference of two signals which are coming from the directional couplers. The differential power is a maximum when the relative phase is 180 degree, whereas the differential power is a minimum when the relative phase is zero degree. Therefore, a relative phase measurement using the mixer is necessary for measuring the power because a relative phase between two powers are directly related to the differential output power. The dc output voltage is measured using a dc multimeter. Load-pull software can be revised so that intermediate mixed-mode s-parameter results that display the differential performance in the measurement system can be displayed during tuner

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70 characterization, calibration, and device measurement. This can indicate the differential performance of the system during all phases of using it. Figure 4.7. Differential load-pull block diagram Mixers are used for the frequency conversion or translation in communication systems. As depicted in Figure 4.8, when two signals at the different frequencies are inserted into two input ports, either a sum or a difference frequency component is appeared at a single output port, called down-conversion or up-conversion. Also, mixers are used in many applications which require phase information in the measurement systems. If continuous waves with an identical frequency are applied to two input ports, a dc output appears and is proportional to the phase difference between the two input signals. With two input signals of )cos(0t and )cos(0 t , the output is )cos()cos( V00o tt (4.9) Using the trigonometric identity,

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71 )cos(221 )cos(21 V0ot (4.10) The output results consist of a dc component and a component at twice the fundamental frequency. The output voltage waveform of a dc component is a sinusoidal as a function of phase difference. In this way, a mixer behaves as a phase detector. Considering unwanted harmonics in the system, the output is ...... termsfrequency order higher )cos(221 )cos(21 V0ot (4.11) With a filtering using a narrow-band low pass filter after a mixer, the 02 term and higher order frequency terms can be filtered out, then the output signal is )cos(21 Vo (4.12) Figure 4.8. General mixer configuration The differential load-pull block diagram developed in this research is different from the commercial differential load-pull system using differential tuners of Focus Microwaves. In the Focus system, the differential tuners contain two individual tuner units controlled by the software independently. The Focus system used balun transition boards to transform the differential output signal to unbalanced signals to be directly measured by unbalanced single-ended instruments. In this research, the differential load

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72 pull measurement is realized using the existing facilities, and no baluns are required. Baluns introduce errors in the differential measurement and cannot be perfectly calibrated in an unbalanced system at this time. Most of the power amplifier design laboratories have a load-pull system to perform a differential measurement. If a conventional single-ended load-pull system is available in the laboratory, this differential load-pull technique will be very helpful to perform the large-signal characterization of differential circuits or systems without additional expensive cost to purchase differential tuners. The differential load-pull system provides more accurate large-signal characterization in differential circuits compared to balun-based single-ended circuits using a conventional single-ended load-pull system because of the balun mismatch and cross-mode errors. Calibration and characterization could not be done in the simulation level. The calibration and characterization should be performed to improve the measurement accuracy in the real measurement system. 4.4.2 Differential Load-Pull Simulation and Result The differential load-pull simulation based on the block diagram is performed using the Agilent ADS software. The differential load-pull simulation schematic is presented in Figure 4.9. The symbol placed on the center of the schematic is the CMOS differential power amplifier without baluns, which were designed in this research. The discussion below describes how the simulation works. Source powers with anti-phases 0 and 180 voltages referred to 50 in the schematic can be generated using polar forms such as 0) ),(dbmtow(Ppolar Pinin1 (4.13)

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73 180) ),(dbmtow(Ppolar Pinin2 (4.14) The input powers are -6dBm at the fundamental frequency of 5.25GHz without setting other harmonic frequencies. Using the variable equation function in the schematic, the variables are written before performing the simulation. During the simulation, the tuners find the optimum load impedances to obtain the maximum output power or maximum efficiency and generate their power contours. The differential output impedance is found by applying Equation (4.8) using the equation function in the data display window (called data display server, .dds file) in the simulation, where M matrix are written in the equation function 1}} 0, 1, {0, 0}, 1, 0, {1, 1},0, 1, {0, 0}, 1,0, {{1,(1/sqrt2) M (4.15) Then, the mixed-mode s-parameters are 4)::3 ,4::3(S S2)::1 ,4::3(S S4)::3 ,2::1(S S2)::1 ,2::1(S Smmccmmcdmmdcmmdd (4.16) Based on the differential-mode voltages and currents which are defined above, the differential impedance is dndndnIV Z (4.17) The differential output impedance is 2)S( Z Zdd22outout diff, (4.18) The output reflection coefficient presented to the DUT is obtained by sdd11sdd21dd12dd22outS-1SS S (4.19)

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74 where )S S S (S0.5 S)S S S (S0.5 S)S S S (S0.5 S)S S S (S0.5 S43412321dd2134321412dd1244422422dd2233311311dd11 (4.20) The optimum impedances, maximum output power, and maximum efficiency are found as following equations from the simulation. ])0 ,0[ Z,P( Z Z0rsPAE_contouinEff opt, (4.21) ])0 ,0[ Z,P( Z Z0rsOUT_contouinPout opt, (4.22) 30)ivlog10(0.510 PloadloaddBmout, (4.23) DCwattin,wattout,P/)PP(100 PAE (4.24) where Z 0 is a reference impedance. Figure 4.9. Differential load-pull simulation block diagram

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75 From the simulation result shown in Figure 4.10, the maximum output power and maximum efficiency contours are plotted with the optimum differential impedance. The maximum efficiency is 20.72% at the load impedance of Z opt, Eff = 9.1 + j9.5 (=Z 0 (0.182 + j0.19)) and the maximum output power is 22.25dBm at the load impedance of Z opt, Pout = 9.3 + j8.55 (=Z 0 (0.186 + j0.171)). The result from the differential load-pull simulation is better than that from the single-ended load-pull simulation with the balun. The efficiency of 12.75% and the output power of 19.54dBm are obtained from the single-ended load-pull simulation. Figure 4.10. Differential load-pull simulation result Table 4.1 lists the equipment, which are available in the lab, required for the differential load-pull measurement system setup. Those instruments are connected through GPIB and are controlled by a PC with the software provided by Maury Microwave Company (tuner manufacturer). Other extra parts such as directional couplers

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76 and mixer are needed for a full description of the differential load-pull measurement system. Table 4.1. Equipment lists for differential load-pull measurement system Instruments Address Number Name and Features HP 437B Power Meter Power meter 13 8485A Power Sensor: -30 ~ 20dBm HP 8563E Spectrum Analyzer Spectrum analyzer 15 30kHz ~ 26.5GHz Signal generator 18 HP 83630A 10MHz ~ 26.5GHz HP 8510C Network Analyzer Network analyzer 16 10MHz ~ 26.5GHz GPIB board 0 National Instrument GPIB Interfaces PCII Automated Tuner Controller Tuner controller 11 Model MT986A02 Automated Tuner 0.8GHz ~ 18GHz Tuner 1, 2 Model MT982B01 Bias, power supply 5 HP E3630A MT 993 A, B, C, D, and G Software package MT956 D for Windows 98

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CHAPTER 5 IMPLEMENTATION OF FULLY INTEGRATED 5GHZ CMOS POWER AMPLIFIER AND EXPERIMENTAL RESULTS The fully integrated differential CMOS power amplifiers for 5GHz WLAN transmitter have been designed and fabricated using the 0.18m IBM BiCMOS 7WL process. 5 In chapter 3, the power amplifier circuit design was described. After the design and fabrication of the power amplifier was done, the power amplifier has been characterized for its performance with respect to s-parameter, output power, and intermodulation distortion in this chapter. Single-ended and differential evaluation boards are developed for the purpose of packaged power amplifier measurements. The simulation performances of two CMOS power amplifiers are first evaluated and summarized in the tables. Detailed descriptions of several measurement setups to evaluate the power amplifier performance are presented in section 5.3. The two-stage CMOS power amplifier has 20.2dBm P1dB output power with 22.8dBm saturation output power. The overall power-added efficiency is 12.1% and the power gain is 22.2dB. Results from CMOS power amplifier simulations and measurements are also presented with figures. The performances of CMOS power amplifiers from experimental measurements are compared to those of other commercial parts that were measured. The performance results are presented with comparison charts by Excel. Finally, the semi-automated measurement setup is developed using engineering software to measure the distortion of 5 Versions are V1.2.1.1DM for three-stage power amplifier and V1.2.1.3DM for two-stage power amplifier. 77

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78 WLAN power amplifiers [Pav02]. These setups are used for measuring WLAN power amplifiers very efficiently. 5.1 Printed Circuit Board Design In RF and Microwave application circuits, Printed Circuit Board (PCB) design and construction are as important as the circuit design because the PCB is necessary to measure the performance of a packaged chip. There are two types of PCBs designed in this research; one is single-ended board with baluns and the other is a differential board. The software that was used in this PCB design is Concept-HDL for the schematic and Allegro for the board layout. 6 These are both made by Cadence but are not the same as the software used for IC design. For FR4 board material for PCB design is 3.8 for 5GHz. The total board thickness for 4 layers is 0.062 inches (62mil). To estimate the PCB trace width for a specific characteristic impedance and board material at 5GHz operation, Equation (5.1) is used to calculate the width [Poz98]. For given characteristic impedance Z 0 , board dielectric constant r , board thickness h, and copper thickness t, the W/h ratio can be found as 2 hWfor 2e8e hW2AA (5.1) rrr21r0e12.023.01e1e 21e 60Z A (5.2) In this design, with Z 0 =50, r =3.8, h=62mil, t=12mil, and f 0 =5.25GHz, the transmission line width and length in PCB are 7.5mil and 236mil, respectively. All other V DD power supply lines have 25mil widths to guarantee sufficient high current capability. 6 The version is a Cadence PCB Design Studio 15.2

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79 5.1.1 Single-Ended Evaluation and Calibration Boards The PCB was developed and built for measuring the power amplifier performance. The schematic shown in Figure 5.1 is designed for single-ended power amplifier with chip baluns on the input and output. The chip baluns which are mounted on PCB, manufactured by Panasonic company are used to convert single-ended to differential, and vice versa. The PCB layout includes a 2-port single-ended input and output with balun in Figure 5.2(a) and calibration board in Figure 5.2(b). Basically, the calibration boards are just a “through” with the top as the input and the bottom as an output. For short, open, load, and through (SOLT) calibration, the short, open, load can be created such as a short by using a solder bridge, an open by cutting the line, and a load by soldering a 50 ohm resistor. The bypass capacitors which were mounted on boards are 0.1F. The PCB layout size which was fabricated is 1064mil1030mil. Figure 5.1. PCB schematic for single-ended power amplifier with baluns

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80 (a) (b) Figure 5.2. PCB layout for single-ended power amplifier (a) and calibration (b) 5.1.2 Differential Evaluation and Calibration Boards Another board was developed for differential power amplifier applications. From the schematic in Figure 5.3, a differential power amplifier was packaged and mounted on the PCB in Figure 5.4. The differential board is the same as the single-ended board except for differential input and output lines instead of baluns. The board layout for differential power amplifier is illustrated in Figure 5.4(a). The differential calibration board in Figure 5.4(b) is also made with the same method as the single-ended board. The total board size is 1224mil1073mil. The test board picture which was fabricated shows that the differential packaged power amplifiers, jumpers, SMA connectors, and bypass capacitors are mounted on PCB in Figure 5.5.

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81 Figure 5.3. PCB schematic for differential power amplifier (a) (b) Figure 5.4. PCB layout for differential power amplifier (a) and calibration (b)

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82 (a) (b) Figure 5.5. Photograph of the integrated power amplifier test board for single-ended (a) and differential (b) 5.2 Power Amplifier Simulation Results To evaluate the performance of the power amplifier designed in chapter 3, a variety of simulations such as single tone, s-parameter, two-tone, load-pull, and MonteCarlo were performed using Cadence SpectreS. The bondwire and package parasitic models are added in the power amplifier circuit for the simulation. The simulation results are shown in this section. The test schematic with bias circuit for power amplifier simulation is shown in Figure 5.6. Ideal transformers for the input and output are used to convert single-ended to differential and vice versa for the simulation. The turn ratio of 1:1.414 in a transformer gives 100 singled-ended termination to two 50 differential impedances. Those ideal transformers will be replaced by commercial baluns which are mounted on the boards. Figure 5.7 shows the entire circuit diagram which consists of the power amplifier core symbol in the right, the bondwire model in the middle, and the package model in the left. With the whole circuit, the gain, output power, efficiency, and linearity were measured from the simulation.

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83 Figure 5.6. Test circuit for power amplifier simulation Figure 5.7. CMOS power amplifier with bondwire and package models

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84 5.2.1 Single-Tone and S-parameter Simulation First, Figure 5.6 shows the 1dB compression point by measuring gains and output powers along with input power. As the signal source sweeps the CW single tone input power from -30dBm to -1dBm with 1dB step which injected into the input of the power amplifier, the amplifier starts to saturate at the certain point, showing nonlinearity. The output P1dB compression point was around 21dBm with 23.5dBm of saturation power. Figure 5.6. Gain, output power, phase, and PAE plots The s-parameter simulation measures the small-signal gain and reflection coefficients which provide the frequency domain analysis for high frequency circuits. There are two different s-parameter result plots designed with small-signal and large-signal matching networks in the power amplifier (Figure 5.7). When comparing two matching methods, the gain difference is around 2dB at 5.25GHz while the output reflection has greater differences.

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85 Figure 5.7. S-parameter plots with small-signal and large-signal matching 5.2.2 Two-Tone Simulation With the gain compression simulation, another way to measure nonlinearity is the two-tone test. Typically, the 3 rd Order Intermodulation Distortion (IMD 3 ) and 3 rd Order Intercept Point (IP 3 ) are measured from the two-tone test because intermodulation products are placed within the band of interest. When two-tone signals with 50MHz spacing (here, two fundamental frequencies at 5250MHz and 5300MHz) were applied into the input of the power amplifier, the transient response at the output of power

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86 amplifier is shown in Figure 5.8. After DFT, the IMD result plot at input powers -30dBm and -20dBm is shown in Figure 5.9. Figure 5.8. Two-tone transient output response Figure 5.9. Intermodulation products from the two-tone test

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87 5.2.3 Temperature Variation and MonteCarlo Simulation The temperature variation plays very important role in circuit design because it affects the chip performance. To investigate gain variation over the temperature range from the -40 to 100 degrees, s-parameter simulation is performed and its result is shown in Figure 5.10. The amount of gain variation is around 10dB over the temperature range, which is too high to meet the specification. Therefore, temperature compensation circuits should be considered in CMOS power amplifier design. Figure 5.10. Gain variation over the temperature range The MonteCarlo statistical analysis is to predict a circuit performance over a total process. After the power amplifier was designed, MonteCarlo statistical simulations are performed to see the process and mismatch variations. The output stage of a power amplifier was run by 20 times with random component values. Figure 5.11 shows v th , g m , and i d distributions over the variation while Figure 5.12 shows the gain distribution from the simulation.

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88 Figure 5.11. MonteCarlo simulation result for v th , g m , and i d Figure 5.12. MonteCarlo simulation result for S 21 gain

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89 Table 5.1 summarizes the overall simulation results from the three-stage CMOS power amplifier and Table 5.2 lists the simulation results from the two-stage CMOS power amplifier. When comparing the simulation performances of two CMOS power amplifiers, the results are almost same except for the gain. Table 5.1. Three-stage CMOS power amplifier simulation performance Frequency band 5.15 ~ 5.35 and 5.725 ~ 5.825GHz V DD , I DC 3.3V, 256mA P1dB, Psat 21dBm @Pin = -8dBm, 23.5dBm Power gain 30dB S 11 and S 22 < -10dB Efficiency 15% CM & DM gain, CMRR in dB -10.7dB, 27.6dB, 35.5dB OIP 3 , IMD 3 OIP 3 = 25dBm, IMD 3 = 28.1dB Layout size 1.8mm1.8mm (3.24 mm 2 ) Table 5.2. Two-stage CMOS power amplifier simulation performance Frequency band 5.15 ~ 5.35 and 5.725 ~ 5.825GHz V DD , I DC 3.3V, 262mA P1dB, Psat 21.2dBm @Pin = -16dBm, 23.6dBm Power gain 38dB S 11 and S 22 < -10dB Efficiency 15.1% OIP 3 , IMD 3 OIP 3 = 28.3dBm, IMD 3 = 27.5dB Layout size 1.8mm1.8mm (3.24mm 2 ) 5.3 Measurement Setup and Calibration As a final procedure after fabrication of the amplifier, the measurement should be performed to verify whether a circuit is properly working or not. To measure the power amplifier performance for the necessary overall specification, all required test equipment should be properly setup for each measurement. The power amplifier is packaged in 44 pin MLF to test on a board level. Then, the packaged PA is mounted on the evaluation board. The parameters such as power gain, input and output reflection coefficients,

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90 efficiency, and nonlinearity (IMD 3 and IP 3 ) for power amplifiers were measured. The test setups for one-tone power sweep with s-parameter measurement, two-tone, and multi-tone measurement are presented. 5.3.1 Equipment Calibrations There are several calibration factors which need to be determined and corrected. The signal generators are combined in a resistive combiner with 6dB loss and 1dB of cable connection loss to the amplifier under test. This loss factor constant is added to the signal generators to produce the power level with the amplifier removed. If the loss of the amplifier input line is to be compensated, additional correction is added to the input calibration factor. Also of note is that the total power levels to the input of the amplifier are reduced by 3dB when both two generators and a splitter are used in the two-tone tests. The generators were very well matched to each other in power output level, although care was taken to use identical interconnecting cables leading up to the combiner. Finally an output calibration was required due to the resistive 6dB loss splitter used to provide a simultaneous signal to the power meter and spectrum analyzer. This was measured and confirmed with the power amplifier removed in a calibration check at 0dBm. 5.3.2 Single-Tone Power Sweep and S-parameter Measurement The s-parameter and P1dB compression characteristics of the power amplifier are measured using the network analyzer in the setup shown in Figure 5.13. Also, power amplifier’s AM/AM and AM/PM characteristics can be obtained with this setup by measuring the gain and phase as a function of input power. A 20dB attenuator is used because the input capability of the equipment such as network analyzer and spectrum analyzer is only 20dBm. Either 1dB gain compression or 1dB output power compression of the amplifier along the swept input power only at particular frequency can be found

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91 from this measurement. Network analyzer calibration is achieved with typical SOLT standard kit at a certain power level and power calibration for accuracy is completed with power meter and sensor before performing the measurement. In Figure 5.14, the result plot for AM/AM and AM/PM characteristics of one commercial WLAN power amplifier is presented. Figure 5.13. Test setup for power sweep and s-parameter measurement Figure 5.14. AM/AM and AM/PM plot

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92 5.3.3 Two-Tone Measurement A two-tone test is essential to measure the nonlinearity of the amplifier. A two-tone test which measures the 3 rd order intermodulation distortion ratio and 3 rd order intercept point can be performed as a single-tone test shows P1dB compression point. Two-tone IMD testing requires two CW signal sources, a combiner, a spectrum analyzer, and for best accuracy, a RF power meter. Figure 5.15 describes how to setup the equipment to perform the two-tone IMD test. Two equal input signals produced from signal generators are combined using combiner, applied to the amplifier, and amplified by amplifier. Then, the output spectrum which shows all the power levels for intermodulation products is appeared in spectrum analyzer. The two-tone output spectrum of a 2GHz WLAN power amplifier is shown in Figure 5.16 when two-tone input signals at 2.45GHz and 2.46GHz are applied. The output spectrum will be somewhat different with respect to the tone spacing. The IMD 3 and IP 3 can be directly read from this plot. Figure 5.15. Test setup for two-tone measurement

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93 Figure 5.16. Two-tone output spectrum 5.3.4 Multi-Tone and EVM Measurement Increasing communication data rates within the same channel bandwidths requires higher order modulation scheme with more stringent linearity requirements on the radio

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94 chain. The Multi-tone Power Ratio (MTPR) measurement for this application requires an Arbitrary Waveform Generator (ARB) and a signal source capable of complex I-Q modulation inputs with GPIB connectivity. The multi-tone test measurement setup is shown in Figure 5.17. The signals were synthesized to have the same tone spacing and bandwidth as the IEEE 802.11a WLAN OFDM signal with 52 sub-carriers, but with a 9 sub-carrier notch. The multi-tone output spectrum of a commercial WLAN power amplifier is illustrated in Figure 5.18. The MTPR can be defined as the ratio between one of the multiple tones in wanted band and the highest intermodulation tone outside the wanted band that shows two markers in Figure 5.18. Error Vector Magnitude (EVM) requires a Vector Signal Analyzer (VSA) with a multi-tone test instruments to analyze the output waveform degradation of a complex waveform. When an IEEE 802.11a OFDM WLAN signal with 64-QAM go through a power amplifier, the EVM result is shown in Figure 5.19. This multi-tone and EVM measurement should be performed in WLAN 802.11a/g applications which require a higher order modulation scheme. Figure 5.17. Test setup for multi-tone measurement

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95 Figure 5.18. Multi-tone output spectrum Figure 5.19. IEEE 802.11a EVM on VSA

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96 The real measurement instruments pictured in Figure 5.20 are used for all the measurements such as S-parameter, one-tone, two-tone, multi-tone, EVM, and load-pull tests to evaluate the power amplifier performance. All the instruments setting in the laboratory can be controlled by either manually or automatically using PC-based software. Figure 5.20. Test bench for power amplifier measurement 5.4 Power Amplifier Experimental Results and Measurement Analysis With the measurement setup described in previous section, two-stage packaged power amplifier is tested at the board level. For accurate measurement, the loss for cables and attenuator are measured and compensated before measuring the power amplifiers. The S-parameter measurement that shows the gain, input and output reflection coefficients is performed from 4.5GHz to 6GHz with 3.3V supply voltage. Then, the

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97 output power is measured as the input power is increasing from -25dBm with a 1dB step at 5.25GHz. The power added efficiency is calculated based on the output power, supply voltage and current. Finally, two-tone measurements are performed at 5.25GHz and 5.26GHz with 10MHz spacing. Cable losses are 1.67dB for input connections and 0.96dB for output connections. For measuring two-tone test, the additional cable loss is and 1.33dB. The loss connecting back-to-back baluns is around 2.2dB at 5.15GHz, 5.25GHz, and 5.35GHz. The second fabricated CMOS power amplifier with two-stage was measured. Compared to the three-stage power amplifier, the number of stages is reduced to two whereas the 100pF bypass capacitors instead of 5pF are used. The power gain, input and output reflection coefficients from the s-parameter test, the output power from the single-tone test, nonlinearities from the two-tone test are measured and presented. The s-parameter measurement result which describes input and output reflection coefficients and the gain is shown in Figure 5.21. From the s-parameter measurement, the input and output matching results look good, but the gain is around 22dB at 5.25GHz because the peak gain is a little bit shifted down to the 5GHz. The bandwidth from the measurement is much narrower than that from the simulation. The reason that the tuning is not perfect is due to longer bondwires. Since the package must be changed to bigger size after the fabrication is done, this parasitic inductance would affect the tuning and the bandwidth. For example, as the input wire is increased by about 275m (10.5mils), the inductance is roughly increased by 0.25nH for this wire and so on.

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98 Figure 5.21. S-parameter measurement plot of two-stage power amplifier Next, the single-tone measurement is performed with the signal generator, power supply, and spectrum analyzer. With the 3.3V supply voltage, the total current of the power amplifier is 262mA. Shown in Figure 5.22, the gain and output power start to saturate from -5dBm input power, and the 1dB output power compression point (P1dB) is 20.17dBm at -1dBm input power. The power efficiency at P1dB compression point is 12.1% and the maximum power efficiency is 22.2% at the saturation output power of

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99 22.83dBm. Additionally, the output power is measured at 5GHz which shows the peak gain of amplifier in Figure 5.24. The two-tone measurement is performed at 5.25GHz and 5.26GHz with 10MHz spacing. From the two-tone test, the intermodulation products (IMP) of the power amplifier along with the input power swept from -20dBm to 1dBm with 1dB step are shown in Figure 5.23. The third-order intercept point is 25.7dBm and third-order intermodulation distortion ratio is 28.1dB from the measurement. The unequal tones of intermodulation products such as IMP3_L and IMP3_U, IMP5_L and IMP5_U can be explained by memory effects found in the reference [Car00, Del01, Ku03]. Figure 5.22. Output power, gain, and PAE results of two-stage power amplifier

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100 Figure 5.23. Two-tone IMD plot of two-stage power amplifier Figure 5.24. Output power, gain, and PAE results of two-stage power amplifier at peak gain (5GHz)

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101 The measurement performance of two-stage power amplifier is listed in Table 5.3. Due to the lack of this balun modeling, the measurement result will be somewhat different from the simulation result. Even though several measurements required to evaluate power amplifier performance with CW signal were performed, MTPR and EVM measurement with the modulated WLAN 802.11a input signal should be further performed if measurement instruments are available. Table 5.3. Two-stage CMOS power amplifier measurement performance Frequency band 5.15 ~ 5.35 and 5.725 ~ 5.825GHz V DD , I DC 3.3V, 262mA P1dB, Psat 20.2dBm @Pin = -1dBm, 22.8dBm Power gain 22.2dB @5.25GHz, 37.2dB @5GHz S 11 and S 22 less than -10dB Efficiency 12.1% OIP 3 , IMD 3 OIP 3 = 25.7dBm, IMD 3 = 28.1dB 5.5 Characterization of Commercial WLAN Power Amplifiers Since WLAN chipsets have been developed, the realization of transceivers is achieved with various IC technologies emphasizing on a smaller size and a lower cost. Most of building blocks in a transceiver have been successfully designed using CMOS technology, but power amplifiers are not the case. Depending on what types of applications are applied or how much power is required, they are building as integrated on-chip or external off-chip. With the power amplifier designed in this research, several commercial power amplifiers developed with GaAs and SiGe BJT technologies for 5GHz WLAN applications are measured to compare the performance. Table 5.4 shows the comparison of power amplifier experimental performances for four commercial products, two published papers, and one from this research. Even though two-stage CMOS power

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102 amplifier performance does not meet the specification, it shows the feasibility that the CMOS power amplifier with a slight improvement can be integrated on WLAN transceiver application. Based on the measurement results, the P1dB compression point and gain are compared in Figure 5.25 and the current and efficiency are compared in Figure 5.26. Table 5.4. Comparison of WLAN power amplifier measurement performance Power Amplifier Gain (dB) P1dB (dBm) I DC (mA) PAE (%) Company A 15.2 23 244 23 Company B 33.1 22.4 462 11.4 Company C 21.6 15.8 99.3 12.5 Company D 21.6 15.5 163.7 6.5 Paper 1 22 (Psat) 230 Poor Paper 2 15.1 15.4 85 27.1 (Max) Two-stage PA (at 5.25GHz) 22.2 20.2 262 12.1 (22.2) Two-stage PA (at 5GHz) 37.2 19.4 262 10.1 (16.9) Figure 5.25. P1dB and gain comparison chart

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103 Figure 5.26. Current and efficiency comparison chart 5.6 Automating WLAN Power Amplifier Distortion Test Distortion measurements in wireless power amplifiers are made by two-tone Intermodulation Distortion (IMD), Multitone Power Ratio (MTPR), and Error Vector Magnitude (EVM). Evaluating these distortion measurements over the power range in a typical transceiver requires a significant amount of data capture. The tasks can be both tedious and repetitive. Considering the engineering design iterations encountered in IC development and the required testing over temperature, semi-automated Automatic Test Equipment (ATE) set-ups in the engineering lab are used. The ATE language was selected by LabView. Program development progressed from setting the signal generators to a frequency and power level in order to read the power meter in a second subroutine. These were accomplished in one day’s effort. Next, the spectrum analyzer was programmed. This was a more difficult task. An instrument

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104 driver was available from National Instruments, and it required a day and a half to get it set on frequency, read in TOI, and read marker levels in dBm. Finally, the loops for the drive power levels were programmed. Based on two-tone and multi-tone test setups which are depicted in Figures 5.15 and 5.17, the programming block diagrams for two-tone test are shown in Figures 5.27 and 5.28. The test took about 30 minutes to execute 20 power steps, -20dBm to 0dBm by 1dB. By hand to Excel, this took two hours and was tedious. After setting up the automated test, the measurement is expected to be more efficient and accurate, and test times are reduced significantly.

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Figure 5.27. Two-tone measurement setup using LabView program 105

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Figure 5.28. Multi-tone measurement setup using LabView program 106

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CHAPTER 6 SUMMARY AND FUTURE WORK CMOS technology has become popular on building RF blocks. Accordingly, considerable research has been in progress for developing transceiver chipsets. However, applying CMOS technology in designing power amplifiers is still in question due to the CMOS performance limitations. The purposes of this research are to present a design methodology of CMOS power amplifiers and to develop a differential load-pull technique. In this dissertation, differential CMOS power amplifiers for 5GHz WLAN application are designed and their experimental results are presented. Also, a differential load-pull simulation result is shown. This chapter summarizes the results of this research and suggests future works. 6.1 Summary and Conclusion In this research, two fully integrated differential CMOS power amplifiers were fabricated with the 0.18m IBM BiCMOS 7WL process for a 5GHz WLAN transmitter. The three-stage and two-stage power amplifiers were implemented in a differential configuration. First, the three-stage power amplifier operated at 5GHz has 18.6dBm output power with a lower gain of 16dB. Due to the unstable supply voltage caused by small bypass capacitor, the performance is much lower than that was expected. The two-stage power amplifier has much better performance than the three-stage power amplifier. With a stable supply voltage for the two-stage power amplifier, the performance shows 20dBm output power, 22.2dB gain, and 12.1% power efficiency. 107

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108 A general overview on the specification of WLAN 802.11a standards such as transmitter spectrum mask and transceiver architecture was provided in Chapter 2. A basic theory of power amplifier design was also described. Classes of power amplifiers were introduced and the critical design parameters for power amplifiers were investigated. A series of the literature related to CMOS power amplifiers and transceivers was reviewed to construct a basic knowledge in power amplifier design. Chapter 3 described power amplifier design procedures. The configuration of the power amplifier was three-stage cascaded structure with common source-common gate cascode configuration with 3.3V supply voltage. Due to the linearity requirement for 802.11a applications, Class A power amplifier, which is the most linear class of amplifier, was chosen at the cost of efficiency. An extra circuit, an ideal transformer was used for conversion from the differential output to the single-ended input, and vice versa. All the necessary component values including I D , load impedance, transistor size, gain, and efficiency were determined. The output stage was designed using both a complex conjugate matching method and a load-line and load-pull approach for the purposes of obtaining maximum power transfer and output power, respectively. The parasitic effects were considered for the accurate comparison between simulation and measurement results. Power amplifier schematics and layouts were presented. Two bondwire diagrams with package were also illustrated. In chapter 4, a new differential load-pull system was developed by utilizing two existing single-ended tuners. With an introduction of a load-pull technique, a conventional load-pull setup and measurement were described. To calculate mathematical transformation for differential-mode and common-mode, a mixed-mode s-parameter

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109 technique was described. A block diagram of the differential load-pull system was presented and the simulation results were shown. Also, the equipment requirement realizing for the differential load-pull system was listed. Chapter 5 showed the simulation and measurement performance of the power amplifiers that were designed in this research. To measure the packaged power amplifier chip, PCB were designed and laid out with two types of boards: calibration board (for the calibration purpose) and evaluation board (for the measurement purpose). The calibration board was designed with short, open, load, and through (SOLT) configuration for the accurate calibration. Various simulations like single tone, two-tone, s-parameter, load-pull, and MonteCarlo tests were performed for the CMOS power amplifiers. The experimental performances such as total current, power gain, output power, and efficiency were compared to those of other commercial power amplifiers. Several commercial WLAN power amplifiers were characterized by measurement. Automating WLAN power amplifier distortion test was used to obtain efficient and accurate measurement results and reduce the test time. In conclusion, this research demonstrated that power amplifier design using CMOS process would be useful for the purpose of a higher level of integration in the whole transceiver chipset at a lower cost. The performance of the CMOS power amplifier designed in this study did not reach the specification. However, the output power, efficiency, and gain over the WLAN specification were improved. The power amplifier design with CMOS technology could be a promising candidate for CMOS WLAN transceiver single-chip realization.

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110 This study suggests that the differential load-pull technique could improve the performance of differential power amplifiers. The optimum load impedance for the differential power amplifier was found from the simulation. The simulation was performed with two load tuners at the amplifier output. The differential load-pull technique would be useful for the large-signal characterization of differential power amplifiers. 6.2 Implication for Future Work As the power amplifier and differential load-pull research presented at the previous chapters is well executed, several future works are considered to strengthen the output of the research to optimize the 5GHz WLAN power amplifier and to realize the differential load-pull measurement system. Specific discussions on two subjects are as follows. 6.2.1 Potential Improvement of 5GHz WLAN Power Amplifier Since the differential power amplifier derives the single-ended antenna, a balun should be placed on between power amplifier and antenna to convert differential output of a power amplifier to single-ended input of antenna. Balun mismatch degrades the power amplifier performance; therefore, an accurate balun modeling is required. Instead of balun modeling, another attempt is to design an on-chip broadband balun for the output of the differential power amplifier. It is difficult to make broader bandwidth designing IC version of balun, for example, about 1GHz bandwidth in this design. By using parallel double-tuned transformer which can be used as a part of the matching network, it is possible to cover the frequency bands [Kra80]. Class A power amplifier is the most linear, but it has the least efficiency among classes of power amplifiers. In order to improve the efficiency of the power amplifier, the most efficient way would be to employ class AB type amplifier, which represents a

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111 compromise between linearity and efficiency. Also, the power control optimizes the amplifier performance to reduce the power consumption by adaptively increasing or decreasing the transmit power. By adding a power control scheme, the efficiency can be improved. In this study, no temperature compensation was included in the power amplifier, accordingly, the gain variation over the temperature was very large. If the temperature compensation circuits such as PTAT or ITAT are added, the temperature variation problem may be solved. In the case of employing the short channel transistor in designing power amplifiers, the gate oxide capacitance of the transistor might be blown out due to the Electro-Static Discharge (ESD). In order to avoid the ESD problem, the extra current paths between power and ground nodes are added. A reliable ESD protection circuit modified from the design kit may be added to the power amplifier. 6.2.2 Realization of the Differential Load-Pull System The differential load-pull technique was evaluated at the simulation level. To realize the differential load-pull system based on this simulation result, the calibration issue in the differential load-pull measurement system should be considered. Similar to the conventional load-pull system, the software driver should be created to display the output load-pull contours. Finally, to verify the result, the performance of the differential power amplifiers using the differential load-pull measurement system should be compared with that of the balun-based single-ended power amplifiers using the conventional load-pull system.

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BIOGRAPHICAL SKETCH Yus Ko was born in Seoul, Korea, in 1971. In 1987, he was admitted to Dae-Won Foreign Language High School. He received a Bachelor of Science degree in the Department of Electronic Engineering at Kyunghee University, Korea, in 1998. To pursue a Master of Science degree, he came to the Department of Electrical and Computer Engineering at the University of Florida in 1998. Yus began working on the doctorate degree at the University of Florida under supervision of Dr. William R. Eisenstadt in 2001. His research interests involved analog and RF circuit design specializing in high frequency power amplifier designs and differential load-pull techniques. During the spring of 2001, he had an internship at Ashvattha Semiconductor, Jacksonville, Florida, where he worked on a 2.4GHz power amplifier design as a circuit design engineer of co-op position. Again, in 2002, he had an opportunity of pre-professional intern design engineer at Intersil Corporation, Palm Bay, Florida, working on the WLAN 802.11a and b power amplifier analysis, evaluation, and measurement. Upon graduation he will join Samsung Electronics in Korea. 118