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ANALOG BASEBAND PROCESSOR FOR CMOS 5GHZ WLAN RECEIVER By OKJUNE JEON A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2005 ACKNOWLEDGMENTS I would like to express my deep appreciation to my supervisory committee chair (Robert M. Fox) for his guidance and support. His insight into circuits and his patience and encouragement made my study possible. I also thank committee members William R. Eisenstadt, John G. Harris, and Oscar D. Crisalle for their helpful advice. Special thanks go to Dr. Brent A. Myers at Conexant Systems Incorporated for supporting my research project including two fabrications and giving me the summer internship experience. His realworld comments throughout the research work and advice as a committee member are greatly appreciated. I thank my fellow graduate colleagues, Yus Ko, Choongeol Cho, Hyeopgoo Yeo, Jangsup Yoon, Kooho Jung, Jongsik Ahn, Ming He, Tao Zhang, Qizhang Yin, Xueqing Wang (Andy), Xiaoqing Zhou, and Su Deep. Also, I thank Dr. Hyungjong Ko, Dr. Inchang Seo, Dr. Sanghoon Choi and Changjin Lee, who were former graduate students in the Analog Integrated Circuit Laboratory. My sincere thanks are given to my parents and parentinlaws. I would like to offer my greatest appreciation to my lovely wife Sanghyun and dear children Yerin and Hohyun, who always stand by me with love and prayer. Finally, I would like to give thanks and glory to the lord God of Ebenezer. TABLE OF CONTENTS IM Le ACKNOWLEDGMENT S .............. .................... ii LIST OF TABLES ............ ...... ._._ ...............v.... LIST OF FIGURES .............. ....................vi AB STRAC T ................ .............. xi CHAPTER 1 INTRODUCTION ................. ...............1.......... ...... 1.1 Motivation............... ............... 1.2 Research Goals .............. ...............2..... 1.3 Outline of the Dissertation. ................ ................. ......... ..............3 2 BACKGROUND ................. ...............5.......... ...... 2. 1 IEEE 802.11la Standard. ............... ... ...__ ...............5. 2.2 System Specifications for WLAN Receiver ................... .......... ................. .7 2.3 Receiver Architecture and Analog Baseband Signal Chain .............. ..................9 2.4 AGC Fundamentals .............. ...............12.... 3 OFDM SIGNAL AMPLITUDE ESTIMATION ................. ......... ................18 3.1 OFDM Signal Characteristics............... ............1 3.2 OFDM Signal Generation................... .... .......... .. .......2 3.3 Analog OFDM Signal Amplitude Estimation with Statistical Simulation ...........22 3.4 Accuracy Boundary for Received OFDM Short Training Symbols.....................26 4 SEVENTH ORDER ELLIPTIC LOWPASS GMC FILTER ................ ...............28 4. 1 Introducti on ................. ...............28........... ... 4.1.1 Specifications .............. ...............28.... 4. 1.2 Filter Topology ................. ...............30............... 4.2 Filter D esign I ................... ......... ..... ..... ...............32.. 4.2.1 GmC Filter with Amplitude Scaling .............. ...............32.... 4.2.2 Gm Cell Circuit Design ............ ......_ ...._ ..........3 4.2.3 Dealing with Parasitic Capacitance ......____ ........ ............_....3 4.3 Filter Design II............... ... .. ..............3 4.3.1 Avoiding Floating Capacitor .....__.....___ ..........._ ..........3 4.3.2 Parasitic Capacitance Compensation. ......____ ........__ ...............40 4.4 Simulation Results .............. ......_ ...............42.. 4.4.1 AC Response and Tuning Range............... ...............42. 4.4.2 Transient Response, Noise and Linearity ......____ ..... ...__ ..............43 5 AUTOMATIC GAIN CONTROL .............. ...............48.... 5 .1 Introducti on ................. ...............48........... ... 5.2 AGC Al gorithm .............. ...............50.... 5.3 Circuit Design ................. ............ ...............55..... 5.3.1 Variable Gain Amplifier............... ...............5 5.3.2 Differential Difference Amplifier ................. ...............61........... .. 5.3.3 RM S Detector ................. ...............62............... 5.3.4 Computation Block............... ...............64. 5.3.5 Switched Gain Control 2 .............. ...............69.... 5.4 IC Implementation and Measurement .............. ..... ...............73. 5.4. 1 IC Implementation with Embedded Test Points ................. ................ ...73 5.4.2 Simulation Results ................. ...............77................ 5.4.3 IC Measurement and Analysis............... ...............86 6 SUMMARY AND FUTURE WORK .............. ...............102.... 6. 1 Summary .................. .............. ...............102 ..... 6.2 Suggestions for Future Work............... ...............105. APPENDIX SCHEMATIC OF TEST BOARD ................ .............................107 LI ST OF REFERENCE S ................. ...............109................ BIOGRAPHICAL SKETCH ................. ...............113......... ...... LIST OF TABLES Table pg 21. Receiver performance requirements ................. ...............8............... 31. Statistical simulation result for 5000 symbols (Max Peak = 0.607)..........................24 41. Spreadsheet to compute parasitic capacitance, number of dummy cells, and main capacitor value at each node .........._.__......._.._ ...............39..... 42. Summary of characteristics of the two filters ........ ................. .............. ....47 51. Summary of the simulation and measurement results.........._.._.. ........__. ........101 LIST OF FIGURES figure pg 21. Frequency band allocation in the IEEE 802.11la standard............._ ........._ ......5 22. PLCP Protocol Data Unit frame format .............. ...............7..... 23. Specifications of the minimum sensitivity signal channel with adj acent and alternate adj acent channels for 6 and 54Mbps data rates ................ ............... .....9 24. Architecture for the 5 GHz WLAN receiver. ............. ...............10..... 25. Baseband signal chain block diagram ................. ...............11........... .. 26. Receiver gain distribution plots for 6Mbps data rate .............. .....................1 27. Receiver gain distribution plots for 54Mbps data rate .............. .....................1 28. AGC structure with (a) nonlinear feedback loop and (b) linearized loop representation .............. ...............15.... 31. A typical analog OFDM signal in the time domain............... ...............18. 32. OFDM modulator ................. ...............20................ 33. Short training symbols: (a) I channel one symbol (0.8Cls) and 7 symbols, and (b) Q channel one symbol (0.8Cls) and 7 symbols. ............. ...............21..... 34. Data symbol generation in the discrete time domain .............. .....................2 35. Data symbol generation in continuous time domain .............. ....................2 36. Data distribution plots for 6 detectors .............. ...............25.... 37. Standard deviation plot for 6 detectors ................. ...............25........... .. 38. OFDM short training symbol generation with channel effect ................. ................27 41. Channel attenuation requirements for the baseband lowpass filter ................... ........29 42. Frequency response (magnitude and group delay) for (a) 6th order elliptic, (b) 9th order Chebyshev II, (c) 3rd order elliptic, and (d) 4th order elliptic filters ...............31 43. LC prototype fi1ters for (a) 3rd order and (b) 4th order elliptic lowpass fi1ters..........31 44. 3rd order GmC Eilter............... ...............32. 45. Internal node voltage plot of the 3rd order GmC Eilter: (a) before scaling and (b) after scaling .............. ...............33.... 46. 3rd order GmC Eilter after voltage scaling for internal nodes .............. ..................33 47. Schematics of (a) unit Gm cell and (b) FC with CMFB unit .............. ...................35 48. DC transfer characteristics of a unit Gm cell: (a) VI plot, (b) Gm plot ................... .37 49. Fully differential 3rd order GmC filter. ......___ ... ....._ ....__ ..........3 410. Avoiding floating capacitor: (a) GmC filter with floating capacitor, (b) substitution of floating capacitor at node V1, (c) additional circuit for current source to node V 1 .............. ...............40.... 411. 3rd order GmC filter avoiding floating capacitor ................. ....___ ...............41 412. Internal node voltage plot of the 3rd order GmC filter avoiding floating capacitor ........... ..... ._ ...............41... 413. Internal node voltage plot of the 3rd order GmC filter avoiding floating capacitor ........... ..... ._ ...............42... 414. AC response simulation result for Filter 2............... ...............43... 415. AC response simulation result for Filter 2 with tuning .............. ....................4 416. Transient response of the Filter 2 at (a) 8.3 MHz and (b) 12 MHz ........................44 417. Noise in dB vs. frequency plot .............. ...............45.... 418. Linearity of 1 % THD vs. input signal voltage for (a) Filter 1 and (b) Filter 2 in nominal case ........._.__...... ..__ ...............46.... 51. Conventional AGC loop composed of VGA, Peak Detector and Loop Filter ...........49 52. Architecture of the proposed AGC algorithm; (a) block diagram and (b) time line ..50 53. Switched Gain Control 1 of the AGC algorithm ................................... 5 54. Switched Gain Control 2 of the AGC algorithm ................................... 5 55. AGC with Onestep Correction: the fine gainsetting step............._.._ ..........._..__...53 56. Schematic of the proposed VGA ................. ...............56............... 57. Schematic of the replica bias circuit for VGA ................. .............................60 58. Simulation result for finding operating point in the replica bias circuit. The result verifies that the bias circuit (for AV = 0.6 V) can operate only at the single operating point of VA = 1.26 V and VB = 0.66 V. ................ ......... ...............60 59. Schematic of the proposed Differential Difference Amplifier ................. ................62 510. Schematic of the proposed RMS detector ................. ............ ........ .........64 51 1. DC simulation results of the RMS detector with VCM = 0.48 and vin = 0.25 ~ 0.25 V: (a) currents II,2 after squarer and (b) currents 13,4 after rectifier..................64 512. VtoI and ItoV converters in (a) differential V to singleended I, (b) single ended VtoI, and (c) singleended I to differential V modes .............. .................66 513. Schematic of the proposed analog computation block. The arrows indicate the VGS S that form the translinear loop ................. ...............68.............. 514. Switched gain control block implementation using latched comparators and transmission gates .............. ...............70.... 515. DC simulation result of the singleended VtoI and Itodifferential V converters (singleended Vet versus differential Vo> cl)............... .....................71 516. Reference voltage generator VINIT has six taps for preset voltages and is implemented as serial and parallel connections of a root component resistor .........72 517. Reference voltage generator VTH prOVides threshold voltages (V20dBm, V22dBm and V30dBm) either for short training symbol signal or for sine wave signal...........73 518. Proposed AGC circuitry with 7 test points ........._.._ ...... .___ .. ......_. .....7 519. Output voltage buffer. ............_. ...._... ...............76.. 520. Test switches; (a) voltage switch, and (b) current switch............... .................7 521. DC gain control simulation for the VGA with inverse gain loop ................... ..........79 522. DC simulation for Vin versus Vout of the VGA at (a) 4 dB gain and (b) 16 dB gain ................. ...............79................. 523. AC response of the VGA; (a) gain and (b) phase ........................... ...............80 524. VGA input and output noise versus gain ................. ...............81.............. 525. Linearity of the 2stage VGA in THD (%) versus input signal voltage plots at (a) 8 dB, (b) 0 dB and (c) 32 dB gain settings ................. ...............81........... 526. Input versus output characteristic of RMS detector; (a) for sine wave signal and (b) for short training symbol .............. ...............82.... 527. Characteristic of VtoI converter; (a) input versus output linearity and (b) step response ................. ...............82................. 528. Input versus output characteristic of ItoV converter ................. ............. .......83 529. DC simulation results of the computation block for sine wave signal with the switched gain of (a) 3 dB, (b) 7 dB, (c) 17 dB, and (d) 17 dB ............... .... ...........84 530. DC simulation results of the computation block for short training symbol signal with the switched gain of (a) 3 dB, (b) 7 dB, (c) 17 dB, and (d) 17 dB ...............85 53 1. Transient simulation result (step response) of the computation block ........._.._........85 532. Transient simulation results of the AGC circuit for sine wave signal with Einal gain of (a) 3 dB, (b) 1 dB, (c) 4 dB and (d) 9 dB ................. .................8 533. Transient simulation results of the AGC circuit for sine wave signal with Einal gain of (a) 15 dB, (b) 20 dB, (c) 23 dB and (d) 28 dB .............. ....................8 534. Transient simulation results of the AGC circuit for short training symbol signal with Einal gain of (a) 3 dB, (b) 1 dB, (c) 4 dB and (d) 9 dB............... .................89 53 5. Transient simulation results of the AGC circuit for short training symbol signal with Einal gain of (a) 15 dB, (b) 20 dB, (c) 23 dB and (d) 28 dB.............................90 536. Full chip layout floor plan of the AGC circuit including ESD bonding pads and decoupling capacitor between positive supply and ground............... .................9 537. Die photo of the fabricated AGC circuit ........._._.......... .......__........9 53 8. Test board design for the 40pin AGC circuit package..........._._... ......._._.......93 539. Test board with a packaged AGC sample plugged in .............. ....................9 540. Bias circuit with external resistor connection: (a) can cause oscillation and (b) can Eix the problem............... ...............94 541. Measurement results on device characteristics with various embedded test point selections: (a) diodeconnected NMOS in RMS detector (W/L=5/10 Cpm), (b) diodeconnected NMOS in cascode current mirror (W/L=3/3 Cpm), (c) threshold voltage extraction (diodeconnected NMOS), and (d) measurement plot on bias current versus external resistor............... ...............95 542. Measurement of onchip resistor variation: (a) resistors between input nodes and (b) measurement results for 20 samples ................. ...............96............... 543. Gain control curve for the 2stage VGA ................. ................. ..............97 544. 2stage VGA gain with supply voltage variation .............. ...............97.... 545. Stability of VGA gain with (a) bias current and (b) temperature variations ............98 546. 2stage VGA characteristic at 12 dB gain: (a) inputoutput linearity, (b) SFDR.....99 547. Frequency response of the 2stage VGA: (a) measurement result and (b) simul ation result ................. ...............99.......... ..... 548. Measurement result for inputoutput characteristic of the RMS detector ..............100 549. Measurement result for inputoutput characteristic of the VtoI converter ..........100 550. Measurement result for inputoutput characteristic of the current mode computation block .........__._..... ..__. ...............101.... Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy ANALOG BASEBAND PROCESSOR FOR CMOS 5GHZ WLAN RECEIVER By Okjune Jeon December 2005 Chair: Robert M. Fox Major Department: Electrical and Computer Engineering This dissertation discusses the design of an analog baseband processor including channelselect filtering with automatic gain control (AGC) for a 5GHz CMOS WLAN receiver. Basic concepts and specifications of the IEEE 802. 11a standard are reviewed. Coded orthogonal frequency division multiplexing (OFDM), employed in this standard for high data rate capability in multipath environments, degrades signal detection in the receiver due to the high peaktoaverage power ratio (PAPR). Statistical simulation shows that RMS detection has the least error variance among several algorithms. Channelselect filters of the analog baseband processor are implemented as 3rd and 4th order cascaded elliptic lowpass GmC filters. The set of filters have been designed and fabricated in a 0.25 Clm CMOS process to meet all the specifications under expected process variations. The AGC part of the analog baseband processor has three variable gain amplifier (VGA) stages. One of them is placed before and the rest after the channelselect filter. A new gaincontrol algorithm for the OFDM baseband signal is proposed based on analysis of conventional AGC loops. The new AGC algorithm uses switched coarse gainsetting steps followed by an analog openloop fine gainsetting step to set the final gain of the VGAs. The AGC circuit is implemented in a 0. 18 Clm CMOS process using newly designed circuits including linear VGAs, RMS detectors, and currentmode computation circuitry. Experimental results show that the new AGC circuit adjusts OFDM short training symbols to the desired level within settlingtime requirements. CHAPTER 1 INTTRODUCTION 1.1 Motivation Wireless technologies are progressing rapidly, not only for voice, but also for data communications. The growing mobile computing environment combined with the demand for network connectivity has made wireless local area network (WLAN) popular. Since the Institute of Electrical & Electronics Engineers (IEEE) ratified two WLAN standards, 802.11la and 802. 11b, in 1999, many WLAN system architectures have been developed to implement them. The IEEE 802.11lb standard specifies operation in the 2.4GHz industrialscientificmedical (ISM) band using directsequence spreadspectrum (DSSS) technology. On the other hand, the IEEE 802.11la standard specifies operation in the recently allocated 5GHz unlicensed national information infrastructure (UNII) band and uses the orthogonal frequency division multiplexing (OFDM) scheme instead of DSSS. The IEEE 802. 11b standard, which supports data rates of up to 1 1Mbps, was implemented before the IEEE 802. 11a standard, which supports data rates of up to 54Mbps, because the latter has more complicated and strict transceiver design specifications than the former [ConO1, Lee02]. In addition to the right performance requirement, implementation of the 5GHz 802.11la RF transceiver with low cost and high power efficiency is another challenge. Along with several other silicon IC technologies, CMOS process technology can be a solution. It provides a lowcost advantage due to its compatibility with high levels of integration. Many CMOS processes also offer multiple metal layers, which enables the use of integrated inductors and linear capacitors. However, characteristics of these passive devices can be poor, due to process and temperature sensitivities. These drawbacks can be resolved by automatic frequency and gain control (AFC and AGC) algorithms [Zar02]. A typical 5GHz WLAN receiver with direct conversion consists of RF front end, analog and digital baseband blocks. In this type of architecture, most gain is in the analog baseband except for the gain of a low noise amplifier (LNA) and mixer in the RF front end. An analog baseband processor covers from the mixer' s output to the analog todigital (A/D) converter's input, including baseband lowpass filters and AGC circuits. Therefore, the main function of an analog baseband processor can be described as channelselect filtering with sufficient gain. OFDM signals have a large peaktoaverage power ratio (PAPR), which requires wide dynamic range in the receiver [Och01]. In order to deal with the wide dynamic range of the OFDM signal in the analog baseband processor, we need to devise an efficient gain control algorithm. 1.2 Research Goals The first goal of this research is to design a baseband lowpass filter which meets the specifications of the IEEE 802. 11a standard. The CMOS GmC elliptic filter can be a good candidate for its good onchip integration properties. Also, by using a simple Gm tuning scheme, the filter can adjust the transfer function to compensate for process and temperature variations. The second goal is to propose a gaincontrol algorithm to provide a constant level of signal to the digital baseband processor. In order to achieve this goal, the effect of PAPR characteristic of the OFDM data signal on the signal amplitude estimation should be simulated statistically, by which one can determine the best detector type for the OFDM signal. Based on analysis of conventional AGC loops, a new gaincontrol technique can be obtained. Finally, the proposed AGC algorithm is to be implemented in the circuit level design. This research completes an analog baseband processor for a CMOS WLAN receiver by making a whole signal chain with a filter and AGC circuits. To achieve experimental results, the AGC design is to be fabricated in TSMC 0.18Clm CMOS technology. 1.3 Outline of the Dissertation This Ph.D. dissertation consists of six chapters. An overview of the research is given in this current chapter (Chapter 1), including the motivation, research goals, and the scope of this work. Chapter 2 reviews some background knowledge on this research. Basic concepts and specifications of the IEEE 802. 11a standard are described, and the overall system architecture and analog baseband signal chain blocks are presented. Fundamentals of AGC operation are also reviewed in that chapter. In Chapter 3, a statistical simulation of OFDM amplitude estimation is presented. An OFDM signal generator (transmitter) is simulated, and signal detectors such as peak, average, RMS and pseudoRMS detectors are compared based on 802.11la standard using Matlab/Simulink. The simulation results show that given random input OFDMQAM signals, the RMS detector has the least error variance among detectors. Chapter 4 describes the design of 7th order elliptic lowpass filters for the baseband processor for a 5GHz WLAN receiver. The filter employs a technique to avoid floating capacitors which allows setting peak values of all internal node voltages identical, thus improving the maximum input signal level. The circuit's transconductors are implemented as sets of "unit gm" cells, by which processvariation effects are reduced. The Gm cells provide reasonable linearity and tunability using degeneration. A spreadsheet to deal with the parasitic capacitance simplifies the design process. Simulation results in a 0.25Clm CMOS process verify that the circuit meets all the specifications under expected process variations. Chapter 5 discusses the AGC part of the analog baseband processor. It has three stages of variable gain amplifiers (VGAs). One of them is placed in front of the lowpass filter to maximize the dynamic range of the signal. A new gaincontrol algorithm for the OFDM baseband signal is proposed based on analysis of conventional AGC loops. After the switched coarse gainsetting, a fine gainsetting scheme locks the final gain within the specification time. Circuit design for the proposed algorithm is implemented in a 0.18Clm CMOS process. A summary of research work discussed in the dissertation and suggestions for the future work are presented in Chapter 6. CHAPTER 2 BACKGROUND 2.1 IEEE 802.11a Standard The 802.11la standard specifies operation in the 5GHz unlicensed national information infrastructure (UNII) band with available signal bandwidth of 300 1VHz. The allocated frequency band is split into two blocks (5.15 ~ 5.35 GHz and 5.725 ~ 5.825 GHz) with three different powerlevel working domains as illustrated in Figure 21. The bottom 100 1VHz domain has a maximum power output restriction of 40 mW, while the next 100 1VHz allows up to 200 mW. The top 100 1VHz domain, intended for outdoor operation, allows power output up to 800 mW. 800mW 200mW 40mW 5.15G 5.25G 1 5.35G 5.725G 5.825G **52 carriers per channel, ' each 312.5KHz wide 201VHz Figure 21. Frequency band allocation in the IEEE 802.11la standard The 802.11la standard employs an encoding technology called coded orthogonal frequency division multiplexing (OFDM). OFDM subdivides a highspeed data carrier into several lowerspeed subcarriers, which are then transmitted in parallel. There are four 20 MHzwide carriers in each 100 MHz domain. Each 20 MHzwide carrier is subdivided into 52 subchannels, each subchannel with 312.5 KHz bandwidth. 48 of these 52 subchannels are used for data, while the remaining 4 are used for error correction. By using this OFDM scheme with low data rate subchannels, the signal channel is less susceptible to multipath effects during propagation. However, OFDM signals have large peaktoaverage power ratio (PAPR) which requires a large power backoff in the transmitter and a wide dynamic range in the receiver. For example, suppose each of the 52 subcarriers of the OFDM signal is a singletone sine wave. Then the wave form of the composite OFDM signal in the time domain will have large peaks and valleys. In the worst case, if the peaks of all 52 sine waves coincide in time, the peak voltage will be 52 times larger than that of a single sine wave, which results in a peaktoaverage ratio of 17 dB (101og(52)). Although some signal clipping can be accepted with an insignificant performance degrade in practice, this PAPR characteristic of the OFDM signal can complicate transceiver design [Zar02]. The OFDM system uses binary / quadrature phase shift keying (BPSK/QPSK), 16quadrature amplitude modulation (QAM) or 64QAM for subcarrier modulation. When BPSK is used, each subchannel carrier encodes data of 125 Kbps, resulting in a 6 Mbps data rate. The data rate doubles to 12 Mbps, 250 Kbps per subchannel with QPSK. Using 16QAM, the rate increases further to 24 Mbps. It is mandatory for 802.11la systems to provide these data rates. The standard also allows datarate extension beyond 24 Mbps. A data rate of up to 54 Mbps in a 20 MHz channel can be achieved by using 64QAM. The 802. 11 wireless LAN data service is provided by sending and receiving packet frames denoted as PLCP (physical layer convergence procedure) Protocol Data Unit frames. The packet frame format includes PLCP preamble, SIGNAL (header of the frame) and DATA parts as shown in Figure 22. The PLCP preamble is composed of 12 symbols: 10 repetitions of a "short training sequence" (used for AGC convergence, diversity selection, timing acquisition, and coarse frequency acquisition in the receiver) and two repetitions of a "long training sequence" (used for channel estimation and Eine frequency acquisition in the receiver). The SIGNAL part constitutes a single BPSK coded OFDM symbol which includes the RATE and LENGTH Hields required for decoding the DATA part of the packet. The DATA part, which includes the service data units, may consist of multiple OFDM symbols. The design considerations for an analog baseband processor deal with short training symbols of the preamble in this OFDM packet frame format. BPSK coded OFDM Coded OFDM PLCP Preamble SIGNAL DATA 12 Symbols One OFDM Symbol Variable Number of OFDM Symbols 10 short training symbols RATE and LENGTH + 2 long training symbols for DATA Figure 22. PLCP Protocol Data Unit frame format 2.2 System Specifications for WLAN Receiver The receiver specifications for the 5 GHz WLAN system are described as receiver performance requirements in the 802.11la standard. Table 21 specifies the receiver performance requirements with data rates of 6 Mbps through 54 Mbps. The minimum sensitivity is 82 dBm for 6 Mbps data rate and 65 dBm for 54 Mbps data rate. For the baseband signal channel at DC, the adj acent channel (at 20 MHz) rej section should be no less than 16 dB (6 Mbps data rate) or 1 dB (54 Mbps data rate). Similarly, alternate adj acent channel (at 40 MHz) rej section should be no less than 32 dB (6 Mbps data rate) or 15 dB (54 Mbps data rate). The relative constellation RMS error which is known as SIR (SignaltoInterference Ratio) should not exceed 5 dB (6 Mbps data rate) or 25 dB (54 Mbps data rate). Figure 23 shows specifications of the minimum sensitivity signal channel with adj acent and alternate adj acent channels for 6 and 54 Mbps data rates. Table 21. Receiver pefrmance reuirements Alternate Mimimum Adj acent Relative Data rate adjcen ~Mbp)sensitivity channel ~ a~~tconstellation (Mbs)(dBm) rej section (dB) richaonnel error (dB) 6 82 16 32 5 9 81 15 31 8 12 79 13 29 10 18 77 11 27 13 24 74 8 24 16 36 70 4 20 19 48 66 0 16 22 54 65 1 15 25 From the specifications above, we can get the attenuation requirements for the analog baseband channel selection filter. With the minimum data rate, 6 Mbps, channel rejection should be 16/32 dB for adjacent/altemnate adjacent channels. Adding 6 dB for SIR and 5 dB for margin, total attenuation should be 27/43 dB for adj acent/altemate adjacent channels. Channel rejection with 54 Mbps data rate should be 1/15 dB for adjacent/altemnate adjacent channels. This results in the total attenuation of 29/45 dB with 25 dB of SIR and 5 dB of margin. If we increase the margin to 10 dB, the filter attenuation requirements would be 34 dB for the adj acent channel and 50 dB for the alternate adj acent channel. n (6 Mbps) (54 Mbps) 50dBm 50dBm 66dm I65dBm ~~~66dBm dBtd 82ddm \ 8.3 11.7 31.7 f (MHz) 8.3 11.7 31.7 f (MHz) Figure 23. Specifieations of the minimum sensitivity signal channel with adj acent and alternate adj acent channels for 6 and 54Mbps data rates 2.3 Receiver Architecture and Analog Baseband Signal Chain The two most common choices in receiver architecture are direct conversion and lowIF dual conversion superheterodynee). Direct conversion is usually preferred in a fully integrated design because it has a simple architecture. However, it has drawbacks such as 1/f noise sensitivity and DCoffset problems. Dual conversion can reduce the disadvantages of direct conversion, but it requires extra complexity [Raz0 1]. In this work, we assume that direct conversion is used for the receiver architecture. As depicted in Figure 24, the receiver consists of a bandpass filter, lownoise amplifier (LNA), I/Q channel mixers and lowpass filters with automatic gain control (AGC) followed by analogtodigital converters. The given blocks have Eixed gains; 3 dB for bandpass filter, 20/0 dB selectablee) for LNA and 10 dB for mixers. As we know the receiver specifications, we can get the gain budget distribution for the AGC with given RF block gains. MixerI ANT C I J , AGC1> I~~ AGC2> A/D CI LPF BPF I Q GC1 Icl AGC2 A/D Q Mixero P Figure 24. Architecture for the 5 GHz WLAN receiver Input signal levels to the filter/AGC blocks can be computed by adding the gains of the BPF, LNA and mixer to the sensitivity. The minimum input signal level for 6 Mb/s data rate is: 82 dBm 3 dB + 20 dB + 10 dB = 55 dBm. For 54 Mb/s data rate, the minimum input signal level is: 65 dBm 3 dB + 20 dB + 10 dB = 38 dBm. The maximum input signal level of the adj acent and alternate adj acent channels at the AGC inputs are 39 dBm and 23 dBm, respectively. We assume that the input resistance of the A/D converter is 1 KGZ and that its input signal level should be 1 V,, in single ended mode. In differential mode, 1 V,, equals to 0.5 V,, (0.25 V,) and to 0.178 Vrms for a sine wave. This corresponds to 0.032 mW in 1 kGZ of input resistance, or 15 dBm. For OFDM data signals, however, the ratio between the peak and the RMS voltage varies due to the randomness of data and the effects of the channel. For OFDM short training symbols, which have fixed amplitudes specified in the 802. 11a standard, the RMS voltage of a short training symbol with 0.25 V, is 0. 105 Vrms. Its power level is computed as 0. 1052 / 1K = 0.011 mW, or 20 dBm. In practice, the effects of a random channel can change this relationship. 11 ________ DC offset canceller HPF aj 150 kHz Channel selection filter : ja 8.3 MHz I VGA 1 ~ CVGA23A/ Gm RF AGC 1 tuning  AGC 2 DSP I II Q~ VGA 1 3 VGA 2, A/D  DC offset canceller Figure 25. Baseband signal chain block diagram The proposed baseband signal chain is composed of three variable gain amplifier (VGA) stages with two AGC blocks plus a 7th order GmC Eilter implemented as shown in Figure 25. It also includes DCoffset canceling blocks such as capacitive coupling, highpass filter and/or feedback loop to remove dc offsets. One AGC block is placed before and one after the channelselection filter. Since the signals before and after the channelselect filter are different, we applied separate AGC blocks to provide optimum dynamic range (DR) for the fi1ter. The prefilter AGC block with one selectablegain VGA stage enables the desired channel to have the maximum gain in the presence of large adj acent channel signals by increasing the gain until the composite (desired channel plus adj acent channels) signal reaches the input saturation point of the filter. This pre filter AGC provides an approximately constantlevel composite signal to the channel selection filter, thus reducing the inputsignal dynamicrange requirement of the filter. The postfilter AGC with two VGA stages sets the gain so that the signal level of the selected channel gets to the desired output level. If we had used a single postfilter AGC, a lownoise filter with high DR and a high gainrange AGC would have been required in the worst case of low composite input signal. On the other hand, we would have needed an extra gain stage after the filter in the worst case of low desired signal level with high adj acentchannel signal level, if we had used a single prefilter AGC. To ensure the operation of the baseband signal chain for all data rates with worst case levels of adj acent channels, efficient gain distribution is needed for the two AGC blocks as illustrated in Figures 26 and 27. Given 16 dB as the input saturation point of the filter, the gain of the prefilter AGC should be 7 dB or more. The gain of the post filter AGC should be 4 dB (16 to 20 dBm) for the maximum signal and 28 dB (48 to 20 dBm) for the minimum signal, which specifies the gain range of each VGA to 2 to 14 dB. The selectable gain of the prefilter AGC can be set to 7 or 14 dB when all three VGA stages are identical. Adding 4 dB of gain margin, the VGA should be designed to have a gain range of 4 to 16 dB. 2.4 AGC Fundamentals In this section, a conventional closedloop AGC is analyzed mathematically based on the AGC loop analysis given by [Kho98] to elucidate AGC function. For the operation of the AGC loop, we assume that the AGC circuit only operates on signal amplitude; hence the AGC input/output signals are represented only in terms of their amplitudes. Another assumption is that the peak detector extracts the peak amplitude of Vout(t) linearly and instantly (much faster than the basic operation of the loop) so that peak voltage equals to the amplitude of Vout(t). This assumption enables omission of the peak detector function model in the analysis. 13 10 (a) 20 20 61 so     2 3 E 48 ,' so C82 90 100 7/14dB 4~28dB 0/20dB 10dB 3dB Mixer 3rd + 4th AGC1 AGC2 20 (b 25 202  47 E 66 8 70   _~ 74 * 82 90 100 Receiver Stages S V ig CHMnmm ~YAj CH (+20MYz) Alt.L~ Adj. CH (+40Mz Figure 26. Receiver gain distribution plots for 6 Mbps data rate. (a) Minimum signal 1. (b) Minimum signal 2. Figure 28 (a) shows a common structure of an AGC loop. The AGC loop consists of a VGA, a peak detector, a comparator, and a loop filter. The VGA amplifies the input signal Vin by the gain control signal V,. The output of the VGA is extracted by the peak detector and then is compared with the reference voltage Vrer. The error signal is filtered and fed back to the VGA to adjust the gain. The AGC loop is in general a nonlinear 96 Receiver Stages Sig CH iAdj. CH (+20MHz) a AILt Adj. CH (440MHz) 14 10 20  ~30 4 0      S50 C.j50 '~~~~~~~~~~ 80 90 100 rLNA 0/20dB 10~d 3dBMie 10 2  b ) 30 40 o66 80 9oo 23 .. 7 6 31 6 .2O 23 36 Figure 27. Receiver gain distribution plots for 54 Mbps data rate. (a) Minimum signal. (b) Maximum signal. system because the VGA operates like a mixer: Vout = Vin x f(V,). (21) Thus, we need to linearize the loop to simplify a mathematical analysis of the AGC loop. Figure 28 (b) shows a linearized structure of the AGC loop. By taking the natural logarithm of Equation 21, we can change the multiplier expression of the VGA to an adder expression: In(Vout) = In {Vin X f(Vc)} = In(Vin) + In(f(V,)). (22) (a) V Detector Loop FilterI V Vref VGA in  n out (b) In , I L I I+ z Figure 28. AGC structure with (a) nonlinear feedback loop and (b) linearized loop representation To linearize the feedback loop, two function blocks (the exponential block at the VGA output and the logarithm block at the control voltage input of the VGA) must be canceled. Hence, two shaded blocks (the logarithm block at the VGA output and the exponential block at the control voltage input of the VGA) are added in Figure 28 (b). We can write the control function to VGA as f(V,) = exp(kVe,), (23) and rewrite Equation 22 as In(Vot) = In(Vin) + In(exp(kVe,)) = In(Vin) + kV,. (24) Let In(Vin) = x and In(Vout) = y, then the Equation 24 is y = x + kV,. (25) The control function from the loop filter is expressed as Vc = 3, nVu) and In(Vout) = y, so Vc = (V,,, y)dv (26) Take derivative respect to time on Equations 25 and 26: dy dx~ dV, dVe g, dy dx~ g, +k, ye _V, y), . +k m(V,, y) (27) dt dt dt dt C dt dt C And take the Laplace transformation to Equation (27): sy = sx k(gm/C)y, (s + kgm/C)y = sx. . =H(s)= s x s k g (28) Equation 28 is an inputoutput transfer function of the linearized VGA with AGC loop. The transfer function is a 1st order highpass function and is stable since the pole is in the left half of the splane. This means that the gain control voltage of the feedback loop is input signal independent. AGC settling time is inverse proportional to the constant loop bandwidth f, = k(gm/C). In many AGC systems, the logarithm amplifier in shaded block in Figure 28 (b) can be omitted due to its complexity in realization. With this omission, the above condition can still be met under certain smallsignal approximations. The assumption is that the AGC loop is operating with the condition that the output amplitude of VGA is near its fully converged state, that is, Vout Vrer. In this case, the control voltage function can be writen as Vc = Km ~(Vrr i Vo,)dr, and since Vout = exp(y), VC = (V,, eY)dv (29) Take the derivative respect to time on Equations 25 and 29: dy dx~ dVe dVe g, dy dx~ g, +k (~ , e ), +k '(ye eY ). (210) dt dt dt dt C dt dt C Equation 210 is nonlinear because of the exp(y) term. Let In(Vrer) = z; then Vrer = exp(z). Under smallsignal approximation of Vout Vrer, we can get Vout Vrer 0, and In(Vout) In(Vrer) = y z 0. So, by Taylor series expansion, we can write e~~Y =e e=ee e (1+ y z) when z<<1 (211) .. e = e (1+ y z) Combine Equations (210) and (211): =y +L k, "' F 1 ) = +k"f (1 +y z)) (212) .dy i=+kX ( ,In(P er) ) dt dt C Take the Laplace transformation to Equation 212: sy = sx k(gm/C)Vreey, (s + kgm/CVrer)y = sx. y s S =H(s)= x g,, (213) s+k Equation 213 is the inputoutput transfer function of the linearized VGA with AGC loop under smallsignal approximation. The transfer function is a 1st order high pass function and is stable since the pole is in the left half of the splane. However, since we assumed Vrer = Vout = Vinf(V,), this system is fundamentally nonlinear and is input signaldependent. Loop bandwidth f, = k(gm/C)Vrer is not constant if the difference between Vout and Vrer changes. Therefore, AGC settling time increases linearly with respect to the difference (input step size). CHAPTER 3 OFDM SIGNAL AMPLITUDE ESTIMATION 3.1 OFDM Signal Characteristics OFDM is a multicarrier transmission technique, which divides the available spectrum into many carriers, each one being modulated by a low rate data stream. It is similar to Frequency Division Multiple Access (FDMA) in that the multiple user access is achieved by subdividing the available bandwidth into multiple channels, which are then allocated to users. However, OFDM uses the spectrum much more efficiently by spacing the channels much closer together. This is achieved by making all the carriers orthogonal to one another, preventing interference between the closely spaced carriers. A key drawback of OFDM is its high peaktoaverage power ratio (PAPR), that is, its signal in the time domain has noiselike amplitude with a very large dynamicrange [Och01]. Figure 31 shows a typical analog OFDM signal in the time domain. Figure 31. A typical analog OFDM signal in the time domain OFDM has gained considerable attention with the rapid growth of digital communication in recent years. It has been adopted for digital wireless broadcast and network standards, including IEEE802.11la wireless LAN standard. The 802.11la standard describes the specifications for 5 GHz wireless LAN transceivers using OFDM [IEE99]. As discussed in Chapter 2, it offers support for a combination of other modulation and coding alternatives such as phase shift keying (PSK) or quadrature amplitude modulation (QAM) with convolution encoding to generate data rates of 6 through 54 Mbps. A typical WLAN receiver consists of LNA, mixer, analog baseband processor and DSP blocks. An analog baseband processor includes AGC and channelselect filter blocks that deal with baseband signals in the time domain. The AGC sets the gain of variable gain amplifiers with respect to the detected output signal strength, which keeps the output signal level to the digital block constant. AGC systems use peak detectors to detect the strength of the output signal assume that its peak amplitude is constant if the signal strength does not change [Kho98]. However, peak detectors may not work properly with nonsinusoidal signals, that is, OFDM signal with high PAPR. Although RMS detectors have been widely used in nonsinusoidal signal amplitude estimation, no specific accuracy comparison among different types of detectors has been reported so far. In this chapter, an OFDM signal generator for the baseband frequency range is designed based on the 802. 11a specifications to estimate amplitude of analog OFDM signal in time domain using Matlab/Simulink. OFDM data symbols are simulated using randomly generated 64QAM sequences. Various detectors such as peak, average, and RMS detectors are tested by using the statistical simulation method in order to find out which has less variance for the OFDM amplitude estimate. Signal detectors will show averages of detected symbol amplitudes and statistical variances from multiple simulations. 3.2 OFDM Signal Generation In an OFDM system, the data is split into a number of streams, which are independently modulated on parallel closelyspaced carrier frequencies. An OFDM symbol is a sum of subcarriers that are individually modulated by using binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), 16QAM, or 64QAM. Figure 3 2 shows the basic OFDM signal generator with the data symbols d(n) = a(n) + jb(n). The real and imaginary parts correspond to the inphase and quadrature parts of the OFDM signal. They have to be multiplied by a cosine and sine of the desired frequency to produce the transmitted OFDM signal represented as [Cim85]: N1 D(t) = {~a(n) cos(mst)+ b(n) sin(mst)) } (31) n=0 o> sin mot cosmot SerialI d(n)=a(n)+jb(n) b(0 OFDM signal D(t) to :MUX Parallel a(1) sinwN~t cos ;v~t b(1) Figure 32. OFDM modulator The IEEE 802.11la standard specifies the physical layer convergence procedure (PLCP) which provides a framing format suitable for data exchange and information management. The PLCP preamble consists of 10 repetitions of a 'short training symbol' (10 x 0.8Cls), 2 guard intervals (2 x 0.8Cls), and 2 repetitions of a 'long training symbol' (2 x 3.2Cls). Seven out of ten short training symbols are used to allow time for signal detection, AGC convergence, and diversity selection. A short training symbol uses 12 subcarriers, which are modulated by the elements of the sequence S, given by: S26,26 = x {0,0,1+j,0,0,0,1j,0,0,0,1+j,0,0,0,1j,0,0,0,1j,0,0,0,1+j,0,0,0,0,r; C~C~ C~ C 0,0,0,1j,0,0,0,1j,0,0,0,1+j,0,0,0,1l+j,0,0,0,1l+j,0,0,0,1l+j,0,0}. The multiplication factor of \~normalizes the average power of the resulting OFDM symbol, which utilizes 12 out of 52 subcarriers. (a) (b) Figure 33. Short training symbols: (a) I channel one symbol (0.8Cls) and 7 symbols, and (b) Q channel one symbol (0.8Cls) and 7 symbols A short training symbol can be generated by adding 6 signal sources for each I and Q channel using Simulink. The 12 subcarriers, 14(1.25MHz), 18(2.5MHz), 12(3.75MHz), 16 (5MHz), 20(6.25MHz), and 24(7.5MHz), are modulated by the BPSK sequence as given above. The generated short training symbols (analog signal) for I and Q channels are illustrated in Figure 33. The 64QAM OFDM data symbols are generated as follows: First, binary input data is encoded, interleaved, and converted to QAM values. The 52 QAM values (48 data values and 4 pilot values) are then zero padded and modulated onto 64 subcarriers by applying the Inverse Fast Fourier Transform (IFFT). The output is converted to a serial symbol in the next stage. The end processing of the digital baseband block adds cyclic extension and window functions. Figure 34 shows the block diagram for data symbol generation in the discrete time domain. The OFDM data symbol signal in the continuoustime domain can be generated for I and Q channels by replacing the IFFT block in Figure 34 with a new block that combines the QAMmodulated analog subcarriers as shown in Figure 35. zeroat DC +26 C Vrt Ct _blackmnan RadmitGnerl IFF In O R dear nterger r ~fr 6 SG Conoa alinon Carrie soublion Pade t ei l nd Sgd aeoo Baebn an[H pnal uin S90E 26 SC Figure 34. Data symbol generation in the discrete time domain 3.3 Analog OFDM Signal Amplitude Estimation with Statistical Simulation The IEEE 802.11la standard reserves seven short training symbols for signal detection, AGC convergence and diversity selection. Since seven identical short training symbols are transmitted through an assumed unchanging channel, all of the available information about signal amplitude is available during each symbol duration. Thus, the short training symbol duration (0.8 Cls) is the optimal amplitudeestimation time. However, due to its high PAPR, detecting the OFDM signal within a time period as short as 0.8Cls can lead to high variance in the estimate. Moreover, the received signal might have multipath fading channel effects, which cause inaccurate amplitude estimation. Therefore, we can consider the variance of the estimated amplitude to compare the accuracy of estimation algorithms. We assume that the detector with lower variance is more accurate. In OFDM amplitude estimation, the accuracy of the estimate can be evaluated by statistical simulation; that is, the smaller the standard deviation is, the better the accuracy of the detector is. Unit oelay1l +26SC S1 M n Age subC1 rdut PhaseDelay t[,) hUnitDelay angle to id1 Smtch Randomly int GAenera  R ndear nterg~er u4 r~ Signdl Deleclar Baseband SC26 26 SC Figure 35. Data symbol generation in continuous time domain In order to compare the variances of the algorithms, we simulate the signal strength estimation using randomly generated data symbols. 64QAM random data signals are generated and modulated with subcarriers to make OFDM data symbols. Three typical detectors such as peak (PK), average (AVR) and RMS (RMS) detectors are considered for the accuracy analysis. Three pseudoRMS (PRMS ., PRMS3 and PRMS4) detectors are added to find out if they show variances significantly different from that of the exact RMS detector. Six detectors are implemented as follows: PK = max(S) AVR = Sd 1 ~Sd RS =,1 Isl d RM~S = Sd RS = S d TT TT PRM~S3 =3 Sd RSS4d where S is the amplitude of the OFDM signal and T(=0.8Cls) is the estimation time Table 31. Statistical simulation result for 5000 symbols (Max Peak = 0.607) Detector PK AVR PRMS'' RMS PRMS3 PRMS4 Arithmetic mean of 5000 0.318 0.118 0.129 0.140 0.160 0.176 results Backoff(dB) 5.612 14.216 13.425 12.714 11.585 10.750 A total of 5000 random data symbols are simulated for statistical purposes. The arithmetic means of the 5000 simulated outputs for each detector are shown in Table 31. Backoff represents the ratio of the maximum peak value to the arithmetic mean value of each detector. The simulation results show that the backoff value for the peak detector is the smallest and that of the average detector is the largest, as expected. Backoff values for RMS and pseudoRMS detectors decrease slowly from the average detector to the highorder estimation. Data distribution plots and standard deviation for each detector are shown in Figures 36 and 37, respectively. The standard deviation of the peak detector is almost twice those of the others, which means that it is not good for estimating OFDM signal strength. The RMS detector has the least standard deviation of all, but the differences between RMS detector and pseudoRMS detectors are small. Standard deviations of pseudoRMS detectors (PRMS1. and PRMS3) are only 4 to 6 % higher than that of the Standard Deviation 0.034074 iiiiiii .027"1 _0.2682 .0328550.36 peak verae p.MS(1.) RM(2) .RMS() p.MS(4 true RMS detector (RMS). The simulation results indicate that the RMS detector is the best one for OFDM amplitude estimation. However, a simple pseudoRMS detector could also be used, because there is no big difference in standard deviation values between an RMS and pseudoRMS detectors. Data Distribution Plots (5000 symbols for each detector) * peak =average  p.RMS(1.5) c RMS(2) p.RMS(3)  p.RMS(4) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 value Figure 36. Data distribution plots for 6 detectors Figure 37. Standard deviation plot for 6 detectors 3.4 Accuracy Boundary for Received OFDM Short Training Symbols In practice, OFDM symbols are transmitted through a radio link that can be modeled as randomly scrambling the phases and possibly changing the relative amplitudes of the signal [Cho01]. When such a signal is received, the amplitude of the estimated signal can be different from the transmitted one even if all transceiver blocks are assumed ideal. By taking this multipath channeleffect into account, we can estimate the error variance of the received OFDM signal. The RMS detector in the analog baseband processor is used for AGC, which must be performed within the first 7 short training symbol period. The accuracy of AGC is bounded by the error variance in the RMS value of the received short training symbols. So we need to estimate the accuracy boundary for the short training symbols to consider gain margin of the AGC. Figure 38 shows how the OFDM short training symbol generation and channel effect blocks were simulated in the discrete time domain. The short training symbols are generated by using the sequence given in Section 3.2 in the OFDM data symbol generation blocks. Multipath is implemented using Simulink library blocks. The Multipath Rayleigh Fading Channel block multiplies the input signal with samples of a Rayleigh distributed complex random process, while the additive white Gaussian noise (AWGN) block adds noise. From 100 simulations for short training symbol with channel effects, the average of the estimated RMS amplitudes is 0.266, and its standard deviation is 0.1. These values translate to the accuracy boundary of 5.5dB. This margin should be considered when designing the AGC for an analog baseband processor in 802.11la WLAN receiver. Figure 38. OFDM short training symbol generation with channel effect CHAPTER 4 SEVENTH ORDER ELLIPTIC LOWPASS GMC FILTER 4.1 Introduction Channelselect filters for the analog baseband processor in a WLAN receiver may be either offchip passive filters or onchip active filters. Onchip active filters are preferred for high integration and low cost, in spite of drawbacks such as limited receiver dynamic range, increased power consumption and chip area. GmC filters are well suited to high frequency applications as integrated continuoustime active filters. In the GmC filter, parasitic capacitances of Gm cells can be merged into the grounded capacitors, thus minimizing their side effects [Kar92]. The channelselect filter must pass only the desired channel to the analogtodigital (A/D) converter, suppressing adj acent and all other channels. Specifications are given to realize the filter. Elliptic filters are used to meet the given specifications and implemented in a 0.25Clm CMOS technology. This chapter describes the design of a CMOS fully differential 7thorder lowpass GmC filter for the baseband processor in 5 GHz WLAN receiver. The filter is implemented by cascading 3rd and 4th order elliptic filters. 4.1.1 Specifications Filter specifications were developed through discussions with the Inrtersll' wireless group to be consistent with IEEE 802.11la standard for a 5GHz WLAN transceiver. The specifications of an active filter in a WLAN receiver usually include the following issues [Beh00] . * Frequency response: passband ripple, stopband attenuation, selectivity and group delay * Input/output signal dynamic range, noise, linearity * Power consumption or supply voltage with current drain * Chip area and/or complexity The structure of the receiver uses I and Q channels for the baseband processing. The cutoff frequency of the lowpass filter can be set to half of the bandwidth. The occupied channel bandwidth is 16.6 MHz within the allocated 20 MHz bandwidth and there is a 3.4 MHz spacing between channels. Thus we can set the passband and stop band edge frequencies to 8.3 MHz and 11.7 MHz, respectively. Other specifications are minimum stopband attenuation against adjacent channel and alternative adjacent channel, given as 34 dB @ 20 MHz and 49 dB @ 40 MHz, respectively. Figure 41 shows the channel magnitude attenuation requirements for the filter. Passband ripple should be less than 1dB. Settling time of the system, including AGC settling, should be within 5.6 Cls (7 repetitions of the short training symbol), which requires fast settling time of the filter. In addition, less group delay spread would ease the signal processing of the OFDM signals. Figure 41. Channel attenuation requirements for the baseband lowpass filter 4.1.2 Filter Topology In the light of the required stopband attenuation and narrow transitionband, the specifications demand a relatively highorder filter. Elliptic filters have high selectivity (steep magnitude response), but require highQ poles that tend to cause long settling times, large group delay spread, and high sensitivity to element errors. Chebyshev II (Inverse Chebyshev) filters have less group delay variation, but need higher order (9th order) compared to elliptic type (6th order). Other filter types such as Bessel and Butterworth filters would require very high filter orders to meet the selectivity requirements. Simulations indicated that a cascade of 3rd and 4th order elliptic lowpass sections provided superior tradeoffs among delay, settling time and complexity. We can reduce the group delay variation of a highorder elliptic filter by cascading lowerorder ones. 3rd and 4thorder elliptic lowpass filters have 73 29 = 44 ns and 127 40 = 87 ns of maximum group delay variation in the passband, respectively [Men97]. Group delay variation of the cascaded filter is 44 + 87 = 13 1 ns, whereas that of the required 6th order elliptic filter is 403 79 = 324 ns. The cascaded filter shows even better result in group delay than the 9th order Chebyshev II filter which has 142ns of the maximum group delay variation in the passband. Graphs of the magnitude and group delay responses for each filter type are shown in Figure 42. The GmC filters were designed based on LC passive filter prototypes, with element values provided by a filter data book [Hue80] and by software (Filter solutions v.8.0). Figure 43 illustrates prototype circuits of cascaded 3rd and 4th order lowpass elliptic LC passive filters which meet the given specifications. Note that the input and output impedances are assumed to be 5 kGZ. 1ande(dB) 8n 40n ""' "" " 20n   r p delR s c O Magni ide (dB) 150n 120 30n (froup delBY (sec) 0 10M 20M 30M 40M Freq (Hz) (d) 9th Order Chebyshev II 6th Order Elliptic 540n Ide (dB) r 450 10M 20M 30M 40M (a) L 120 0 20 40 60 80 Freq 0 10M 20M 30M (b) 4th Order Elliptic 40M Freq (Hz) 180n 3rd Order Elliptic 0 10M 20M 30M 40M Freq (Hz) 0 (c) . 60 Figure 42. Frequency response (magnitude and group delay) for (a) 6th order elliptic, (b) 9th order Chebyshev II, (c) 3rd order elliptic, and (d) 4th order elliptic filters 73.88 uH BB.11 uH ooo ~2 ooo ~2 Figure 43. LC prototype filters for (a) 3rd order and (b) 4th order elliptic lowpass filters 4.2 Filter Design I 4.2.1 GmC Filter with Amplitude Scaling The elliptic GmC filters are built from the LC prototype by replacing both resistors and inductors with transconductors elements. The input/output resistance of 5 kGZ sets the transconductance gm to 200 CIA/V. The floating inductors are implemented using gyratorC circuits with C = Lgmlgm2. In order to minimize mismatch, transconductors are composed of "unit gm (gmu)" cells. This also makes it convenient for layout. All the transconductors in the filter are to be an integer multiple of gmu. Transconductor of 200 CIA/V is represented by 4gmu with unit gm of 50 CIA/V. The transconductors connected to the input will be doubled to remove the 6 dB loss from implementation of equally terminated LC prototype. Figure 44 shows the implemented 3rd order GmC filter. c3 =1.55pF V gmu~ V44gmu V 8gmu +) 4gmu 4gmui 4gmui 4gmu V ~CI =4.45pl CL =2.96pF LC2=4.45pF Figure 44. 3rd order GmC filter However, in this filter, the amplitude of the signal at internal nodes may be higher than the filter input. These peak voltages can drive internal transconductors into saturation, resulting in distortion of the output signal. This problem can be solved by applying amplitude scaling to the filter. That is, all node impedances are scaled so as to make their peak amplitudes remain near the input signal's level without changing the transfer function of the fi1ter. The 3rd order GmC Eilter has 3 nodes (two internal nodes and one output node). The second node n2 peaks at ~2.25 V in SPICE simulation, which is over twice the input voltage (1 V). This peak voltage can be reduced by half without changing the voltage at any other node of the fi1ter. We can achieve this by halving the currents flowing into the capacitor' s node (4gmu 2gmu) and doubling the currents emitting from the capacitor's node (4gmu 8gmu), simultaneously. The scaled internal node voltage plot and resulting GmC Eilter are given in Figures 45 and 46, respectively. &: agVF(/nt014") : mag(VF("/120/net14 5"')) .:mgV( tl4) : mag(VF('VI28etl45")) 1.48 (a) (b) Figure 45. Internal node voltage plot of the 3rd order GmC filter: (a) before scaling and (b) after scaling C1=4.45pII CL =2.96p F IC2=4.45pF Figure 46. 3rd order GmC Eilter after voltage scaling for internal nodes 4.2.2 Gm Cell Circuit Design The basic building block of the GmC filter is the integrator, which consists of a transconductor (Gm cell) and a capacitor. The characteristics of the filter such as frequency response, linearity, DC gain and tuning range depend on the Gm circuit. Real Gm circuits have a finite output impedance that modifies the transfer function of the integrator, introducing a low frequency pole pl. This low frequency pole pl limits the dc gain and varies the phase of the integrator, which may introduce distortions in the transfer function of the GmC filters [SanOO]. One general approach to deal with the low frequency pole is to use a folded cascode (FC) output stage. The folded cascode structure increases the output impedance of the Gm circuit, which shifts the low frequency pole to a much lower frequency, reducing effects on the filter' s transfer function. Since the filter will operate in fully differential mode, we need to add commonmode feedback (CMFB) to the folded cascade output stage to stabilize the commonmode output voltage. This circuit senses any change of the common mode output voltage and pushes it back to the reference point by controlling the bias current of the output stage through negative feedback. So the transconductor has two elements: a Gm unit and a FC with CMFB unit. The schematics of the Gm and FC with CMFB circuits are shown in Figure 47. The Gm cell has a pchannel differential pair as input stage. This can move the parasitic pole p2 to a higher frequency with smaller transistor dimensions in the output stage compared to the nchannel input stage case. That is because the parasitic pole p2 is mostly determined by the parasitic capacitance of an nchannel transistor in the FC stage. (b) Figure 47. Schematics of (a) unit Gm cell and (b) FC with CMFB unit The Gm cell uses source degeneration MOS resistors to improve linearity. One more voltagecontrolled degeneration transistor (M5) is added for tuning in parallel with the degeneration pair (M3,4) Of the wellknown fourtransistor input stage. In the degeneration scheme, the linearity is increased by reducing the transconductance of the differential pair (gm;/2). The transconductance of the linearized Gm cell can be found with small signal analysis. Vx y 7for small input signals, which makes the degeneration transistors M3,4 and Mg operate in the triode region. The degeneration resistance is defined as R = R1  Rz  Rg, by which we get the following equation for AC current i. V, V. = R i (41) We can also write g,,.,(F,, Vx) =i (42) and g,z(,, (P,,,F)= i (43) for the input transistors M1 and M2, TOSpectively, where go,l = gaze and F n, y,,, = y n. From Equations 41 through 43 we get: g,,, (F, Ri)= 2i (44) i = "" V(45) g,,, R +2 "" g,,, 1 :. G,, = Kn; 2 R Kn;1 ,7R(46) g,,, R +2 g,,, 1 2 + 2R Equation 46 shows that the transconductance of the proposed Gm cell is the parallel sum of the transconductances of the differential input stage and the degeneration transistors. The unit Gm cell is designed and simulated to have 50 CIA/V of transconductance through 1 V,, input signal range with 3 V supply voltage. Figure 48 illustrates the linear range of the DC transfer characteristics and transconductance. Vin vs. Iout Vin vs. Gm 401rA I ~ 601rA 20pA 301rA OV IV 2V 3V OV IV 2V 3V (a) (b) Figure 48. DC transfer characteristics of a unit Gm cell: (a) VI plot, (b) Gm plot 4.2.3 Dealing with Parasitic Capacitance The 3rd order filter in Figure 45 is redrawn in Figure 49 to show the fully differential structure with Gm cells, FC units, and capacitors. In reality, active blocks such as these Gm cells and FC units have parasitic capacitances at their input/output ports. Hence, we need to compute all of the parasitic capacitances of the active blocks connected to each main capacitor nodes, and modify the main capacitor value so that the total capacitance is the desired value. Also, to minimize process and temperature variations all nodes should have the same ratio of parasitic capacitance to main capacitance. An independent block composed of a FC output stage combined with CMFB is placed on capacitor node and used in common for all connected Gm cells. This is much simpler than including these functions in every Gm cell. The C1VFB circuit in Figure 47 uses two matched differential pairs for good linearity, and all nodes see low impedances to minimize highfrequency phase errors. The inputs remain linear for large differential signals up to near 1 V,,, which is consistent with the maximum input signal swing of the transconductors. In Figure 49, we can compute the number of FC units and Gm cells connected to each node. We keep track of the parasitic capacitances at each node for the output of each FC unit and the input of each Gm cell. The parasitic capacitances of each FC output port (Cout Fc) and Gm input port (Cin Gm) are eStimated from simulations [Kar92]. The parasitic capacitance at each node is calculated by the equation C, = (number of FC)  Cout FC + (number of Gm) Cin Gm. Let Ct be the total capacitance of each node. For each node, we set the ratio between 'main' and 'parasitic' capacitances as equal as possible to minimize the effects of processparameter variations. Let x be the largest value of C,/Ct for all nodes (x = 0. 14 at node 5 of 4th order filter). The main capacitance to be placed at each node is C = Ct (1x). The difference of the capacitance (Cd = t Cp C) Should be realized by parasitic capacitance to provide processparameter tracking. Therefore, we need to add dummy cells to all nodes with Cd except one. Finally, we can find the number of dummy cells (dummy#) and the main capacitor value (Ccap) for each node. A spreadsheet was developed to automate these calculations, as an example is shown in Table 41. Figure 49. Fully differential 3rd order GmC filter Table 41. Spreadsheet to compute parasitic capacitance, number of dummy cells, and main capacitor vt lue at each node filter odrnode FC# IGm C, Ct C Cd dummy dummy# dum~diff Ccap 3 FC1 4 6 5.69E13 4.45E12 3.82E12 6.24E14 1.16E+()( 1.()(E+()( 1.62E()1 3.83E12 3 FC2 1 16 3.33E13 2.96E12 2.54E12 8.61E14 1.6)E+()( 12.()(E+()()3.96E()1 2.51E12 3 FC3 3 6 4.47E13 4.45E12 3.82E12 1.85E13 3.45E+()( 13.()(E+()()4.45E()1 3.85E12 4 FC1 4 12 6.48E13 4 FC2 2 8 3.5()E13 4.55E12 3.9()E12 2.94E13 5.48E+()( 15.()(E+()()4.81E()1 3.93E12 4 FC3 3 6 4.47E13 4.84E12 4.15E12 2.4()E13 4.47E+()( 4.()(E+()()4.7)E()1 4.18E12 4 FC4 1 16 3.33E13 3.44E12 2.96E12 1.55E13 2.9()E+()()3.()(E+)( 1.()4E()1 2.95E12 4 FC5 3 6 4.47E13 3.15E12 2.7()E12 ().()(E+()( ().()(E+()( ().()()0 10E+())(.)(E ( 2.7()E12 FC#*CoutFe From Ct()C dC int. of remainder C + Filter spec. p mdmdummy of Cd dmdifP*Cd Gm#*Cm, m Cout Fe 1.226E13 1.3155E Cm am 1 5.3696E Cm dum 1 x 1.42E()1 4.3 Filter Design II 4.3.1 Avoiding Floating Capacitor The filter design in the previous section has embedded floating capacitors, which restricts nodevoltage scaling and thus limits the input dynamic range. Floating capacitors may also present a problem in the design due to their inaccuracy of the bottomplate capacitance. Hence, in this section, we designed another version of the filter which avoids floating capacitors. This new filter design replaces floating capacitors with compatible circuit blocks and results in all scalable internal nodes. The improved dynamic range is obtained at the expense of some added complexity. Figure 410 describes the floating capacitor avoidance technique. The 3rd order GmC filter in Figure 44 is repeated here as 410 (a), where the floating capacitor is connected between node Vt and node V2. As shown in Figure 410 (b), the floating capacitor to the node Vt can be replaced with a grounded capacitor C3 and a current source of sC3 2 which flows into the node, because its current is sC3 1, 2z). The current source of sC3V2 can be implemented in the following sequence; (i) duplicate all current sources at V2 (ii) drive these currents into R, (iii) get the desired current through scaled gm. This is illustrated in Figure 410 (c). The voltage of the duplicated node Vx2 is s(C2 C3)V2 gy2. Therefore, if we set the scaled gm as gxi = gy2 3/C 2 C3), then we get the desired current i = gxiVx2z= SC3Vy2. By applying the above technique to both nodes V1 and V2, the 3rd order GmC filter which avoids the floating capacitor is implemented, as shown in Figure 411. s(C3(1V1 c3 V1 V V5 + II+ + (a) 91 V 94 V V4 95' VX2 97 V2 VV I sC2 03)V2 I V, IIsC3V s.C3V1 g2 9X1 9X21 CI C7 s(C31 9 D2 (b) (c) Figure 410. Avoiding floating capacitor: (a) GmC filter with floating capacitor, (b) substitution of floating capacitor at node V1, (c) additional circuit for current source to node V1 4.3.2 Parasitic Capacitance Compensation All five internal nodes of the filter avoiding floating capacitors are scaled to maximize the input dynamic range of the filter. The internal node voltage plot after scaling is shown in Figure 412, where peak voltages of all five internal nodes are equal to 1 V, which is the peak voltage of the input signal. OHz 51VHz 101VHz 151VHz Figure 412. Internal node voltage plot of the 3rd order GmC filter avoiding floating capacitor Although the new filter presents scalability for better dynamic range, the extra circuits introduce two new nodes that are not connected to grounded capacitors. These floating nodes, Vxt and Vx2, depicted in Figure 413 (a) can add extra poles or zeros to the transfer function due to their parasitic capacitances. In order to solve this problem, _I ~C ,,I CL Figure 411. 3rd order GmC filter avoiding floating capacitor Internal Node Voltages CELL : : : : : C~~ C~~ C I I I  vL Iv we can add a 'negative capacitor' to the floating nodes of the filter. The negative capacitor circuit shown in Figure 413 (b) uses a crosscoupled differential structure to compensate AC current due to the parasitic capacitance by setting Co = C,. This circuit is applied to each floating node, by which the side effects from the parasitic capacitance are cancelled out [Wak90]. V1 V2Vd VpC IIVp Cl+C3 ; 9X2/ 9YX1 2 03 V Cpr xi g2 9X a Floating capacitor Node a 'nd Node b (a) (b) Figure 413. Internal node voltage plot of the 3rd order GmC filter avoiding floating capacitor 4.4 Simulation Results 4.4.1 AC Response and Tuning Range The 3rd4th order cascaded lowpass filter has been designed in two versions: namely, Filter 1 and Filter 2. Filter 1 includes floating capacitors whereas Filter 2 avoids the floating capacitors. The Cadence Spectre simulation results show that the characteristics of both filters meet the specifications. The following data in the format of valuel1/value2/value3, which represents the specifications, simulation results for Filter 1, and that of Filter 2, respectively. Passband ripple is less than 1/0.75/0.86 dB. Passband and stopband corner frequency attenuations are 1/0.96/0.78 dB and 28/32/40 dB, respectively. Stopband attenuations for adjacent (at 20 MHz) and alternate adjacent (at 40 MHz) channels are 34/47/44 dB and 49/58/54 dB, respectively. Worst case simulations with temperature, process and mismatch variations showed that the passband cutoff frequency varied from 7.7 MHz to 8.7 MHz for both filters while maintaining the shape of the AC response curve. Simulation results for AC response with tuning voltage of 0. 1 ~ 1.9 V showed the passband cutoff frequency tuning range of 7.2 ~ 1 1.7 MHz for both filters. This tuning range covers the worst case variation range. Therefore, these filters can tolerate temperature, process and mismatch variations by using a simple automatic tuning circuitry. Figures 414 and 415 show the AC simulation results for Filter 2. AC Response 70 B 10M 20M 30M 40M 50M 68M Figure 414. AC response simulation result for Filter 2 4.4.2 Transient Response, Noise and Linearity Figure 416 (a) gives the result of the transient simulation for passband signal at the edge frequency of 8.3 MHz. The output signal follows the input signal after initial settling period (~0.6 Cls). The plot shows the linear output signal with approximately 900 phase shift. Figure 416 (b) describes the attenuation for the stopband signal at 12MHz, which suppresses outofband signal after settling. AC Response +: vtune="1.9";/n x: vtune="l vtune="1.5";/n u, tune="l3j";/n o: .~ . 10 7": vtune="900m"/v: viune="" *l*; vtune="500m";/: vtune="300m";/o: 0. aj 10 20 40 80 0.0 10M 20M 30M 40M 50M 60M B 11.6786M 7181.B8ml slooe: 32.1245f Figure 415. AC response simulation result for Filter 2 with tuning I t~p i : a econr 800n 10 0 0 22 40 r e on s Figure. Noise Figure is commonly defined as [Raz94], NF = logo (47) / I 1 08z 100Hz 161K~z 1.OMI~z 100M~z 100Mz 10Lu~gvOG1fVONOISE*V(OINOISE) /20.35e9/20.35e9) Freqguency Figure 417. Noise in dB vs. frequency plot The linearity of a filter can be specified by either singletone total harmonic distortion (THD) or twotone input IP3. In this baseband filter design, the linearity of a filter is characterized by the signal voltage for 1 % THD. This figure of merit is used to quantify the nonlinearity of the filter. Filter 1 shows 1 % THD for an input signal of where SNRn and SNRour are the signaltonoise ratios measured at the input and the output, respectively. For a general calculation of the noise figure, the NF is usually specified for a 1Hz bandwidth at a given frequency. This is called as the "spot" noise figure to emphasize the very small bandwidth. This can be expressed as follows where A = ocA, and V2n,0ut TepreSents the total noise at the output. NF =log,(V(, + I Rs)2 V1g 2n,out 4kTRs l A2 4kTRs 48 In this design, we set A=1 and Rs=5kaZ, from which we get the noise figure from the simulation as NF = V2n,,ut/(20.35n)~2, as shown in Figure 417. The NF for the passband of the filter (156.25k 500m ~ .,.. 427 mV, while that of Filter 2 is 45 1 mV, in the nominal case (Figure 418). We can see that Filter 2 tolerates higher input signals than Filter 1, under the same linearity condition. This is the result of a superior amplitude scaling of Filter 2. The best/worst tuned case for the temperature, process and mismatch variation gives the maximum input signal range of 410 ~ 441 mV, and 424 ~ 503 mV, for Filter 1 and Filter 2, respectively. Transieni Response rni i egns 1.40 ,: thd(VT("/net99") Ze06 4e06 6i4) ~ ;a" hii(~lg~j 36eic 4 5011m 4sBm .Xn 400Rm 420m 4401m 420~m 440m 460m 480im A: (4 ) Vln i A: (4btd88Srm 1)Vo (a) (b) Figure 418. Linearity of 1 % THD vs. input signal voltage for (a) Filter 1 and (b) Filter 2 in nominal case The comparison between Filter 1 and Filter 2 is summarized in Table 42. Filter 1 is superior in power consumption and complexity, while Filter 2 shows better linearity. In conclusion, both 3rd4th order cascaded elliptic lowpass GmC filters satisfy the specifications for the analog baseband filter in a 5 GHz WLAN receiver. 47 Table 42. Summary of characteristics of the two filters Filter 1 Filter 2 Filter structure 3rd+4th elliptic with floating 3rd+4th elliptic avoiding floating capacitor caacitor Gm cells Unit Gm cells (50pAV Unit Gm cells + 10 extras number of MOS TRs 1364 2577 number of Caps 44 36 Total 21 mA 38 mA Max nputVpp820/854/882 mV 848/902/1006 mV (worst/nominal/best) Inband rms Noise 739.17 uV/9lHz 870.22 uV/9lHz DR (nominal input) 61 dB 60 dB CHAPTER 5 AUTOMATIC GAIN CONTROL 5.1 Introduction Automatic gain control (AGC) is an essential function in a WLAN receiver because the power received through the wireless channel is unpredictable. The AGC circuitry provides a known output voltage magnitude from an input signal with variable strength. In the IEEE 802.11la WLAN system, data pass through the channel in packet frames consisting of preamble, header and data segments as discussed in Chapter 2. The receiver estimates corrections for the channel's characteristics during reception of the preamble. These characteristics are assumed to stay constant throughout the transmission of the whole packet frame, typically up to 1 ms. The preamble consists of 10 repetitions of a predefined data stream called a short training symbol (10 x 0.8 Cls) and two repetitions of a long training symbol (2 x 4 Cls). In the proposed receiver system, the time for seven of the repeated short training symbols (5.6 Cls) is allocated for signal detection, AGC convergence and diversity selection [IEE99]. While multipath can significantly alter the waveform, we assume that the received signal is essentially repeated during each short training symbol duration, and that its characteristics establish the amplitude and phase references for use during the entire packet frame. Conventional closedloop analog AGCs use feedback loops to adjust the gain of the variablegain amplifiers (VGA) to set the desired output signal strength. In such AGC loops, as shown in Figure 51, input and output signals are typically represented by their peak amplitudes. This adequately represents signal levels for signals with constant PAPR such as sinusoids. For proper operation of closedloop AGCs, the time required to determine peak amplitude must be much less than the time constant (settling time) of the loop filter [Kho98]. When the input amplitude changes, the detected output amplitude is compared to the desired amplitude and the difference error is fed back to adjust the gain of the VGA to provide constant output amplitude. The negative feedback loop continuously responds to input amplitude variation. GA Peak c, Detector Loop 4 FilterI O Vref Figure 51. Conventional AGC loop composed of VGA, Peak Detector and Loop Filter However, in the 802. 11a application, due to the high PAPR of the OFDM signal, input or output peak amplitude is not a reliable measure of signal strength. The closed loop AGC with peak detector will not converge as the peak amplitude of the OFDM signal changes continuously. As discussed previously, the specifications require AGC settling within the time for seven short training symbols. Since seven identical short training symbols are transmitted through an assumed unchanged channel, all of the available information about signal amplitude is available during each symbol duration. So the short training symbol duration (0.8 Cls) is the optimal signalaveraging time. In the AGC loop, an average or RMS detector can replace the peak detector because signal strength can be estimated as an average or RMS over the symbol duration. The closed loop AGC with average or RMS detector will converge with the time constant of the loop 50 filter much longer than the signal estimation time. The resulting AGC settling time is much longer than system specifications allow. These issues preclude the use of a conventional closedloop AGC in this application. Based on these observations, a new openloop AGC circuitry is proposed in the following section. 5.2 AGC Algorithm Figure 52 illustrates the operation of the proposed AGC circuitry. The analog baseband circuits include three VGA stages plus a channelselection filter. VGA stage VGA1, with gain selectable as 7 or 14 dB, precedes the filter. Two VGA stages, with combined gain variable continuously from about 8 dB to about 32 dB, follow the filter. LNAI Switched Gain Control 1 I Switched Gain Control 2 I Gain=0/20dB ,  (a) R D1 R D2 R D3 D 3d+ 4t HPF VGA1 order elliptic HPF VGA2 VGA3 Vn LPF I RMS I Detector I AGC with OneStep Correction Iref Gain =4~28dB Short Training Symbols (b) 0.8 ps 1.6 ps 2.4 ps 3.2 ps 4.0 ps 4.8 p t1 t2 t3 t4 t5 t6 t7 Filter settling R Set GLNA=20dB G1 = 7dB G2 = 6dB COarse Coarse Fine G3 = 6dB Gain Set 1 Gain Set 2 Gain Set Figure 52. Architecture of the proposed AGC algorithm; (a) block diagram and (b) time line Separate AGC loops are provided for the pre and postfilter gain blocks, since they operate on different signals as discussed in Chapter 2. The AGC algorithm operates in three phases: two switched coarse gainsetting phases, followed by an openloop fine gainsetting phase. The coarse gainsetting steps ensure that all of the gain and filter stages operate linearly and that the gain is within +5 dB of its optimal value. The fine step sets the gain for the entire packet to within +1 dB of its optimal value. Before the reception of each packet, gains are initialized to 20 dB for the LNA, 7 dB for VGAl and 6 dB for VGA2 and VGA3. During the first short training symbol time (tt: 0 ~ 0.8 Cls), RMS detectors RD1 and RD2, located before and after VGA1, estimate the signal amplitude. These values are sampled and held, and used by 'Switched Gain Control 1', a logic block that selects the gains of the LNA and VGAl as shown in Figure 53. The LNA gain is set to 0 dB if the output of RD1 is greater than 23 dBm. If the output of RD2 is less than 23 dBm, the gain of VGA 1 is set to 14 dB. Otherwise, they keep their initial gains. After the signals settle down through the filter (the second short training symbol duration is allocated for filter settling), the postfilter AGC loop, Switched Gain Control 2' (Figure 54), selects the overall gain of the second and third VGAs (3, 7, 17 or 27 dB) based on the signal amplitude detected during the third short training symbol (t3: 1.6 to 2.4 Cls) using RMS detectors RD3 and RD4 located before and after the cascade of VGAs. The overall gain of VGA 2 and 3 is set to 3 dB if the output of RD3 is greater than 30 dBm or to 7 / 17 dB if the output of RD4 is greater than 20 / 30 dBm. If the output of RD4 is less than 30 dBm, the overall gain of VGA 2 and 3 is set to 27 dB. 52 Vc V LNA 7` V2d 1d oc VGA1 latched latched Scomparator comparator 23dBm 23dBm Figure 53. Switched Gain Control 1 of the AGC algorithm 12dB 2d t=0s t=1.6Cls latched latched comparator latched comparator 30dBm 20dBm Vc to VGA2 & 3 cmaao Figure 54. Switched Gain Control 2 of the AGC algorithm The final openloop fine gainsetting phase, 'AGC with OneStep Correction', is applied to VGA2 and VGA3. The circuits include three main components: an RMS detector, an analog computation block and an inversegain block. As discussed in Chapter 3, an RMS detector should be used for the most accurate amplitude estimation of the OFDM signal. In this phase, the RMS detector connected to the output of the third VGA (RD5) detects signal strength during the fifth short training symbol duration (t5: 3.2 ~ 4.0 Cls). The output voltage of the RMS detector is sampled and held, and the result, Vol, is used in computing the final gaincontrol signal for VGA2 and VGA3. The analog computation circuitry computes the new control voltage (VC2) fTOm Vol, the desired reference voltage (Vrer) and the initial control voltage (Vcl). The new control voltage is applied to VGA2 and VGA3 through the inversegain block [Kho98], which adjusts VGA gain to get the desired level of the output signal. Note that the subscripts 1 and 2 represent previous and new time steps respectively. VGA2 V~~n RMS V detector Vcs A Vc Sample & hold VGA4 Vet Vdc C Inverse Gain Block sqrt CIVref /Vo V Computation Block Ve Figure 55. AGC with Onestep Correction: the fine gainsetting step Designing a VGA with reasonable inputtooutput linearity is not too hard. However, accurately predicting the gain for a given gaincontrol input signal is quite difficult, especially in shortchannel CMOS technologies. The inversegain block uses feedback to set the predicted switched gain accurately. Opamp A in Figure 55 takes two positive DC voltage inputs, Vc and Vc, and uses feedback to find the AGC gaincontrol voltage Vep required to set the gain of VGA4 to A, = Vc / Vde. When Switch T is connected to Vct (the switchedgain value set during coarse gain step 2), the gain of VGA4, as well as VGA2 and VGA3, are set to A,1 = Vct / Vdc. (51) That is, the switched gain of the second coarse gainsetting phase (3, 7, 17 or 27 dB for 2stage VGAs) is set by the ratio of the selected voltage Vct and the fixed voltage Vdc. Note that VGA4 in the inversegain block must be matched to VGA2 and VGA3 in the main signal path. With the input voltage Vin applied during the fifth short training symbol time, the detected RMS output voltage is sampled and held: Voi = A g2Vin (52) The computation block computes the final control voltage: VC2 = Vcl9(Vre /Vol) (53) Then, VC2 is applied through Switch T to the inverse gain block, where the feedback loop of the opamp A forces the gain of the VGA to Av2 = VC2 / Vdc. (54) From Equations 53 and 54: Av2 = VC2 / Vdc = Vc1/ Vdc \IVre Vl, and from Equation 51: Av2 = Avy \(Vrer / Vol) (55) We can write the final output voltage as follows: Vo2 = Av22Vin = {Avl \(Vre /Vol)}2Vi = A g2Vin / Vol .Vrer = Vref This equation shows that the final openloop fine gainsetting AGC makes the output voltage Vo2 equal to the desired voltage Vrer with onestep gain correction. Note that the final gain is held constant throughout the transmission of the packet frame. We also note that both I and Q channels can use one AGC loop for identical gain control, so the RMS detector can estimate the output amplitude from both I and Q channel signals. In summary, the proposed AGC algorithm uses a threestep iterative openloop gain control method (two coarse gainsettings using switches, followed by a final fine gain setting using an openloop computation circuit). The algorithm converges within seven shorttrainingsymbol times, and holds the final gain throughout the whole packet frame. This avoids the settlingtime limits of a conventional closedloop AGC. 5.3 Circuit Design 5.3.1 Variable Gain Amplifier The transconductance of a MOS differential pair may be varied either with bias current, or by an adjustable degeneration resistor. A Gilbert multipliertype amplifier is well suited to implement a VGA with large gain and low noise, but its linearity is limited. A differential pair degenerated by a MOSFET resistor can handle large signals given a low power supply resulting in good linearity, because the degeneration does not degrade the voltage headroom in a simple differential pair. However, this degenerated differential pair has limited gain range and poor noise figure [Tad98]. High linearity in a transconductance cell requires the transconductance (Gm) to be independent of input signal. To cover the required gain range of 4 to 16 dB mentioned in Chapter 2, the VGA gain must be variable over a wide range. Also, it should have good linearity and low noise. To ensure that the VGA can fulfill these requirements, it is designed as a linear transconductance cell combined with crosscoupled differential pairs as in a Gilbert cell for gain control. A source follower with shunt feedback, the socalled flipped voltage follower (FVF), provides a lowimpedance output node with a constant current through the input transistor [Car05]. A highly linear transconductance cell can be achieved by placing a fixed resistor Rx between the lowimpedance nodes of the differential FVF to provide a constant transconductance Gm = 2/Rx. Feeding the output current of the transconductor to a fixedresistor load RL WOuld give a constant gain 2RL/Rx. The differential pairs of Gilbert cell are used to steer the tuned portion of the transconductor' s output current to the load to make the gain adjustable. This type of VGA structure can provide 4 to 16 dB gain with good linearity. V~ I~4aM ML~I I ~ Ix In*21 V1 IJI M~a Y3 M~aMlb Y4 M~ I3 I R X1 X~ X2RY el~n Mia M~tb IIla I I6 V V I I Ms Figure 56. Schematic of the proposed VGA The proposed VGA consists of a linear transconductance cell (differential FVF with linear resistor), Gilbert celltype differential pairs and load resistors, as shown in Figure 56. In the differential FVF transconductance cell, due to the feedback loop, input signal applied to transistors M1a, b does not affect the transconductance Gm = 2/Rx, that is, currents through M1a, b and M3a, b arT COnstant. Instead, the input signal changes voltages at the low impedance nodes X1, 2 and current Ix flows through resistor Rx sourcing from M3a, b: IX (1 I2)/2 = GmVin where Gm = 2/Rx. (56) The output currents (lI and It) Of the transconductor are mirrored to the differential pairs with a 1:1 ratio: li = IS and I2 14 (57) The crosscoupled structure of the Gilbert celltype differential pairs yields IS = 5 16 and I4 = 7 + 8. The control voltages (Vcl > VC2 > 0) are provided by a differential difference amplifier (DDA) and their differences adjust currents to the output stage: Is = I3f(VC2 Vc1), I6 = 3f(Vc1 VC2), 17 = 4f(Vc1 VC2), and Is = I4f(VC2 Vct), (58) where 1 > f(Vcl VC2) > 1/2, and f(VC2 Vcl) = 1 f(Vcl VC2). (59) The output stage consists of load resistors (RL1, 2) with commonmode feedback (CMFB), levelshift resistors (RS1, 2) and current sources (Msa, b). Since 19 10Il, Is + I, = 19 IL, and 16 8 10= l IL, (510) we can get the output current IL (6 17 8I I5)/2. (511) Using Equations 58 and 59, we can rewrite the output current IL (3 I4) {2f(Vc1 VC2) 1}/2, (512) and from Equations 56 and 57, IL = X {2f(Vc1 VC2) 1}. (513) The output voltage and voltage gain are Vout = IL.RL = 2VinRL/Rxf {2f(VTI_ VC2)\ 1}, (514) A, = Vout / Vin = 2RL/Rx {2f(Vcl VC2) 1}. (515) The maximum gain is achieved when the difference of the control voltages is maximum (f(Vcl VC2) ~ 1), that is, Av, ma 2RL/Rx. (516) Since DC biasing for the input stage is provided by output stage of an identical VGA stage, the output stage has levelshift resistors (Rsl and RS2) to match the input and output commonmode voltage ranges. Voltages in the VGA are highly constrained. For negative input swing M1 tends to go triode and M2 tends to go triode for positive input swing. To increase the usable input range, voltage levelshifter (IvRy) is added in the shunt feedback path of the FVF, which brings the drain voltages of M1 and M3 ClOser to the negative supply rail. To optimize the voltage swing of the linear transconductance cell, the appropriate range of the voltage levelshifter is analyzed. If all transistor pairs are well matched and differential inputs are given as VCM f Avin, we can write: Ix = 2Avin/Rx, and A~vout A~vin, where Avout represents voltage variation at node X1 (or X2) due to Avin. For the worst case of applied maximum input +Avin to the positive input port Vin+, transistors Mta, Mlb and Mgb should be in the active region. Conditions on Mta and Mlb set the lower limit of the levelshift voltage, while Mgb COndition set the upper limit. At the edge of the active region, VGS1 = VT1 + V DSAT1, VGS2 = VTO + V DSAT2 and VGS3 = VTN + V DSAT3, where VTN is NMOS threshold voltage without body effect, and VTO and VT1 are PMOS threshold voltages without and with body effect, respectively. To keep Mta in the active region, the voltage at node X1 must be less than VDD  VDSAT2, that is, Vx1 < VDD VDSAT2. (517) Let the levelshift voltage AV = lyRy, then Vyl = VDD VGS2a AV and Vxl = Vyl + VDSAT1 + Vout. From Equation 517, we can get AV > VDSAT1 + Vout VTO. (518) Simple calculation with maximum Avout of 0.25 V and nominal values like VDSAT1 = 0.2 V and VTO = 0.5 V shows 0.05 V as lower limit of AV. This means that no voltage levelshifter is needed in this case to ensure M2 Stage in the active region. To keep Mlb in the active region, the voltage at node Y2 must be less than VG2 + VT1, that is, VY2 < VG2 + VT1. (519) Solving Equation 519 for AV with VY2 = VDD VGS~b AV and VG2 = VcM Avin, we can get AV > VDD VDSAT2 VTO VT1 VcM + Avin (520) With an input commonmode voltage VcM of about 0.5 V, 1.8 V supply voltage and other nominal values as above, this condition requires a voltage levelshift of more than 0.25 V. The final condition is for NMOS transistor M3b to be in the active region: VY2 >V DSAT3. (521) Solving this for AV results in AV < VDD VTO VDSAT2 VDSAT3. (522) With similar rough calculation, this condition limits the voltage levelshift value to less than 0.9 V. Thus, by considering all three conditions, the voltage levelshift value must be selected in the range of 0.25 V < AV < 0.9 V. Since the two conditions for the voltage levelshift value reference the positive supply voltage, we must allow for supply voltage variation of 10% (1.6 ~2.0 V). Although we can select the levelshift value under the worstcase condition (0.25 + 0.2 V < AV < 0.9 0.2 V), to optimize signal swing for all VDD ValUeS, AV should be varied along with the variation of supply voltage. The levelshifters are implemented as linear resistors (Ryl and RY2) with current sources (M4a, b). The current sources are controlled by a voltage Vy from a replica bias circuit (Figure 57). The replica bias circuit finds Vy to make VD M1 match VD M12, referenced to ground rather than supply voltage. In this design, the voltage levelshift value AV is set to 0.6 V and the voltages near the positive supply voltage nodes (Y3 and Y4) vary with VDD while the other nodes (Y1 and Y2) almOst keep the same voltage. Inside the replica bias circuit, there are three feedback loops: two negative feedback loops (VYM4VAM2M1VBM1 1M13 and VA M2M1VBRY) and one positive feedback loop (VYM4VARY VBM11M13). Due to the positive feedback loop, there can be multiple operating points [Fox99]. We need to make sure that only one operating point exists in the replica bias circuit design by using DC simulation for VA and VB aS shown in Figure 58. Figure 57. Schematic of the replica bias circuit for VGA I I IT IIB I I r r VB 0.66 V IA = 0 Figure 58. Simulation result for finding operating point in the replica bias circuit. The result verifies that the bias circuit (for AV = 0.6 V) can operate only at the single operating point of VA = 1.26 V and VB = 0.66 V. The VGA structure shows good linearity with large gain range. However, there are tradeoffs among gain range, linearity, noise, frequency bandwidth and current consumption in circuit design. Input transistors M1a and Mlb have short channels to enhance gm, but increase flicker noise, so PMOS devices were used for this circuitry. Using longchannel transistors for NMOS output current sources (Msa, b) alSO improves noise performance. Scaling up current along with channel widths reduces noise without changing circuit performance but current consumption had to be limited. Although long channel devices reduce noise, they tend to degrade bandwidth due to large parasitic capacitances. Thus, shortchannel transistors are used for Gilbert celltype differential pairs and current mirrors to achieve adequate bandwidth. The currentmirror output of the VGA enables removing the PMOS tail current source, which saves voltage headroom. Constant current biasing is maintained by the balanced control voltages from the DDA. 5.3.2 Differential Difference Amplifier A Differential Difference Amplifier (DDA) is used for the amplifier in the inverse gaincontrol loop because the loop operates in differential mode. A DDA has two differential input pairs and a differential output pair. When used in negative feedback connection with very large open loop gain, the DDA forces the two differential input pairs identical [Hun97]. To ensure a wide output control voltage range, the DDA is implemented as a folded cascade structure as shown in Figure 59. It contains two simple differential pairs (M1, M2, M3 and M4) which compare the difference of the two differential input signal voltages (Vc~ and Vdc+). The differential cascode output stages, combined with a commonmode feedback (CMFB) circuit with levelshifters, provide differential output control voltages (Vcpl and Vep2) which change with the input difference. The CMFB circuit has a simple structure using source followers with level shift resistors. Source followers M15 and M16 detect the output voltages of the DDA at their gates, and their corresponding source voltage difference generates current through R1 and R2. This current shifts the commonmode voltage level VCM which is fed back to the gates of the cascode PMOS transistors M7 and Mil. The differential control voltages are set by the feedback as the inverse gain loop forces the two inputs to be identical. Since the DDA works with DC control voltages, two compensation capacitors (Ccl = CC2 = 10 pF), grounded in series with resistors, are added to the output nodes for stability. ,M7 19 M11 I edjpl nddl s M6 VCM pr 0 Mg M12 Vdc+ Vcpl, 4V M1M2 3 M4 dc M15 M16 M9 13 10 17 M18 M14 Figure 59. Schematic of the proposed Differential Difference Amplifier 5.3.3 RMS Detector The RMS detector estimates the RMS value of the output signal, integrated throughout one short training symbol duration. The RMS circuit is based on the approximately squarelaw characteristics of longchannel (~ 2 Clm) MOSFETs in strong inversion [See87, Han98]. The dynamic range of this circuit is rather narrow, which is acceptable because the coarse gainsetting step ensures the signals are not far from their optimal value. The RMS output voltage is stored as the difference of the VGSs Sof a pair of diodeconnected NMOS transistors (Vout+ Vout+). This signal is sampled and held on storage capacitors connected to the gates of NMOS transistors. The RMS detector in Figure 510 uses NMOS transistors in strong inversion as the input squarer. The differential output voltages of the VGA with commonmode voltage are fed to the gates of the NMOS transistors. Let the input signal VIN = VCM + vin. The squarer transistor M1 converts input voltage vin to output current li as follows: 1 w W~ fw1 W I, =KI (VGS1 V,)~ = KI (V,, +v, V,) 2 nLi\LI 1 2 nLu I 1 W\ K,, v,, V with VCM VT (523) 2 "Li The resulting drain current of M1 is almost proportional to the square of the input voltage if we set VcM ~ VT. Similarly, the drain current of M2 is almost proportional to the square of the input voltage when the input signal is positive. Above the NMOS squarer are two crosscoupled NMOS differential pairs (M3 ~ M6). They operate like switches to rectify the currents in differential mode. For the differential pairs to work as switches, their gates must be triggered by large signals at the input signal frequency. Hence, the input signals vin+ and vin are boosted as Vn and V, using amplifiers A and B, and supplied to the gates of the differential pairs. The currents li and I2 are rectified to Is when the input signal is positive and to I7 otherwise. Figure 511 plots DC simulation results for VtoI converted currents (lI and It) and rectified currents (I, and Is), which shows that current Is is nearly proportional to the square of the input voltage. Currents I7 and Is are averaged and squarerooted to complete the RMS detection. The averaging of the currents is performed using a cascade of two firstorder lowpass filters to meet the estimation time constraint of a short training symbol (0.8 Cps). To provide an acceptable tradeoff between smoothing and settling time, the onchip capacitors are set to C1 = 4 pF and C2 = 10 pF, where C2 is bigger because it also used as a storage capacitor. The output current of the first PMOS lowpass filter is mirrored to the second NMOS lowpass filter. In this second filter, the NMOS implements a squareroot function by converting the current to a voltage proportional to the squareroot of the current. The gate of the NMOS transistor and the storage capacitor are connected with a switch S (small geometry NMOS), which is opened after the symbol duration for the capacitor to hold the stored voltage. Figure 510. Schematic of the proposed RMS detector DC Response :: /1152/M2/D '12 1 DC Response .: /Il52/M19/S 120u .; : /Il52/M1/S 100u 801.0u 6g.W 40,0Ru 1 20.0u 12u r: / 12.0u . 6100u 4800u 60,0Ru . 40,0u 230m 48~nl~0m 730m 230m 480m 73 Vamp Vamp Figure 511i. DC simulation results of the RMS detector with VCM = 0.48 and vin = 0.25 ~ 0.25 V: (a) currents II,2 after squarer and (b) currents 13,4 after rectifier 5.3.4 Computation Block The coarse gainsetting step provides us with a voltage Vct that is applied to the inversegain block (along with Vde) to set the VGA gains to a value within +5 dB of their Vm+ Vn Vm V, optimal values. The resulting RMS value Vol of the output is measured during tS and is sampled and held. An analog computation block compares Vol to the desired value Vrer, and computes the new value of VC2 = Vcl(IVrer/Vol) as discussed in the previous section. The final control voltage VC2 must be applied to the inversegain block to force the gain to its optimal value. For the optimal gain after the final control, we assume that the precision of 1 dB is acceptable for the system (approximately 10.5 dB is achieved by this computation block) as a design target. However, it is not easy to realize the analog computation block with multiplier, divider and squareroot function blocks. The analog computation block is implemented using translinear circuits based on weakinversion FETs [Mul99], which reduces power dissipation and complexity of the circuit. This requires that the input and output signals be represented as small (~1 CIA) singleended currents. The singleended currentmode operation of the computation block tends to be noisier than the differential mode. This reduces the accuracy of the computation, but the noise does not couple into the VGA signal path, since the gain is fixed during transmission of the data packet. Figure 512 shows VtoI and ItoV converters with singleended and/or differential mode terminals. The differential voltage to singleended current converter in Figure 512 (a) is placed between RMS detectors (RD5) and the computation block, which converts the output differential voltage of RD5 to lot in the computation block. This VtoI converter provides a linear output current which is attenuated to around 1 LA. The NMOS input transistors M1 and M2 have 5 times less transconductance compared to the output NMOS transistors of the RMS detector. PMOS transistors Mg and M6 aef connected to the active loads (M3 and M4) Of the input devices with shunt feedback, and M1 Io M2c V, 8s 11 (a) oddlddd M3 4 2 3g widl ~~~rddl dlV2 dd Van ICM SRd 6~ M7 MS (b) (c) Figure 512. VtoI and ItoV converters in (a) differential V to singleended I, (b) singleended VtoI, and (c) singleended I to differential V modes work as source followers. The low impedance output nodes of the source followers are connected through a big linear resistor R (30 kGZ). The difference of the two input voltages creates a voltage between sources of Mg and M6, and thus a small amount of current IR aCTOss the resistor R. IR flOws through M6, Ms and M9, and is mirrored to lot via the 4: 1 attenuation cascode current mirror (Ms, M9, Mlo and Mil). This differential voltage to singleended current converter/attenuator provides around 1 CLA of single ended current output to the computation block for a voltage input of about 250 mV from RMS detector. The singleended VtoI converters in Figure 512 (b) convert singleended voltages Vrer and Vet to singleended currents herf and Ict. A low gm NMOS transistor (M1) with degeneration resistor Rd (15 kGZ) converts input voltage Vin to current Il. This current is mirrored through a 4: 1 attenuation cascode current mirror (M2, M3, M4 and Mg) and is mirrored again through the 2:1 attenuation current mirror (M6 and M7) to achieve an output current Io of around 1 CLA for the computation block. Singleended current to differential voltage converter in Figure 512 (c) converts the output current IC2 Of the computation block to the input differential voltage VC2 Of the inverse gain control block. This ItoV converter amplifies its input current using a 1:4 cascode current mirror (M1, M2, M3 and M4), and the amplified output current Io creates two equal voltage drops in seriesconnected resistors R1 and R2. Differential output voltages are supplied at the top of R1 and at the bottom of R2. The gate of the M5 connects to the node between R1 and R2 to set the commonmode voltage. M6 delivers a commonmode current IcM to the drain of Mg, which provides a commonmode voltage to the gate of Mg even when there is no input current applied. Singleended voltages Vct from the switched gain control block and Vde are converted to differential input voltages of the inverse gain control block through a cascade of a singleended VtoI converter and a singleended current to differential voltage converter to minimize mismatch with the other differential control voltage VC2 converted from the current mode computation block. Ict 7~ lot~ Irer PIC2 Figure 513. Schematic of the proposed analog computation block. The arrows indicate the VGS S that form the translinear loop. The schematic of the proposed analog computation block is shown in Figure 513. Applying the translinear characteristics in weak inversion, we get the desired computation as written in the following equations.  VGS C1 VGS C1 + VGS 01 VGS ref + VGS C2 + VGS C2 = 0 (524)  InIcl InIcl + Inlot InIrer + InlC2 + InC2 = 0 (525) lInC22 In C12 reIIf o I, (526) In(ICzcl2 C1 2 ref ol) (527) :. IC2 = C1.\IeT (528) This circuit provides an output current IC2 with expected computation when the input currents Ict, lot and herf are applied. To guarantee translinear operation in weak inversion with currents of about 1 CLA and lower, PMOS transistors are large sized: W/L = 200/1 Cpm for M1, M2, Ms and M9. For the differential pair M3 and M4, lOnger channel with smaller widths are used to provide good matching. M2, M3, M4 and M9 have separate nwells to remove errors due to bulk effect. Also, fast and stable operation is achieved by adjusting channel length for inner loop transistors Mg, M6 and M7. 5.3.5 Switched Gain Control 2 The switched gain control block is implemented using latched comparators, transmission gate switches, and two reference voltage generators (VINIT and VTH) aS shown in Figure 514. A latched comparator which is a foldedcascode differential amplifier with a dynamic latch load compares two inputs, Vin (output from RMS detector) and Vth (threshold voltage from the reference voltage generator VTH), and yields differential outputs to activate transmission gate switches: either SA Or SB. When the latch signal goes from 0 to 1, the crossconnected positive feedback loop forces the differential output voltages to be latched [Ock99]. The result of the comparison of the two inputs decides the polarity of the output. The output of the latched comparator is connected to the gates of transmission gate switches (SA and SB) which select between two voltage inputs. The switching connection to select Vct is completed when the transmission gate switch S1 is on. Three sets of latched comparators and transmission gates select gaincontrol voltage out of four initial voltages by comparing the outputs of the RMS detectors and the threshold voltages, as described in the AGC algorithm section. The initial voltage and threshold voltage generators provide reference voltages which are preset by resistor banks. The initial voltage generator VINIT prOVides six preset voltages V3dB, VodB, V7dB, V12dB, V17dB and V27dB. V3dB, V7dB, V17dB and V27dB are selectable Vct voltages, while VodB and V12dB are VDC VOltage and Vco voltage for the initial VGA gain, respectively. As we mentioned before, the inverse gain control loop sets the twostage VGA gain as Av = 40log(Vet/VDc) dB. So, Vet can be found such that Vet = VDe 10Av/40. (529) 70 VDC Vco V I3dB SWO~SW V, ITdO Ifv V 777, then Vo Vg, else Vo VA ."Latched Comparator 1 LC2 SW3 V27d I~ I oI LC3 ~itch V20dBm V30dBm I~ I T I V URD4 4 V RD3 Figure 514. Switched gain control block implementation using latched comparators and transmission gates With VDe = VCM 0 3 5 mV, the differences of the differential Vcl (including VDe and Vco) voltages for V3dB, VodB, V7dB, V12dB, V17dB and V27dB are 58.5, 70, 104.8, 139.6, 186.2 and 331.2 mV, respectively. Since singleended Vct is converted to a corresponding differential Vct through VtoI and ItoV converters, we can find the singleended voltages for V3dB, VodB, V7dB, V12dB, V17dB and V27dB by DC simulation of those two converters. Figure 515 shows DC simulation result of the singleended VtoI and Ito differential V conversion for gain control voltage Vet. 71 DC Response .: /Il33/Il57/net23 700m _.: /1133/157/nett0171 VOdB V12dB .V3dB V7dB V17dB V27dB 650m 950m 1.25 singleended V,, (V) Figure 515. DC simulation result of the singleended VtoI and Itodifferential V converters (singleended Vet versus differential V cl) The corresponding singleended Vet voltages for V3dB, VodB, V7dB, V12dB, V17dB and V27dB are 687, 716, 798, 871, 963 and 1279 mV. These preset control voltages for switched gain are implemented using resistor banks as shown in Figure 516. Applying an external 1.5 V supply voltage to a branch with total resistance of 15 kGZ enables tapping out the desired voltages with corresponding ratio of tapped resistors (Figure 516 (a)). In order to improve matching and to reduce process variations, each section of resistor is made of serial and parallel connections of a root component resistor as shown in Figure 516 (b) [Sai02]. For example, by choosing 2.32 kGZ as the root resistor RR, the 0.29 kGZ resistor between V3dB and VodB is realized as eight parallel connections of the root component. Another reference voltage generator VTH prOVides three threshold voltages (V20dem, V22dem and V30deng) for latched comparators. The reference voltage V20denz is preset to the positive output value of the RMS detector with 500 mV,, input signal (desired output 72 2.21k 3.16k 0.92k 0.73k 0. 82k 0.29k 6.87k< V7dB V~dB V3dB V27dB V17dB V12dB V (b) RR = 2.32 kGZ Figure 516. Reference voltage generator VINIT has six taps for preset voltages and is implemented as serial and parallel connections of a root component resistor. signal level). Other reference voltages V22dem and V30dem are preSet to the value of the RMS detector with 397.2 mV,, and 158.2 mV,, input signals which are 2 dB and 10 dB less than the desired one, respectively. These preset voltages are compared with actual output voltages of RMS detectors by latched comparators during the switching gain control step. Applying the same method used for VINIT, the reference voltage generator VTH is implemented using a resistor bank (Figure 517). Note that two different sets of threshold voltages are provided with signal type selection, since RMS values are different between sine wave signal (sine) and short training symbol (STS). V20dBm sine V22dBm~sine V30dBm sine Switch for m w ine/STS selection w v  W &RR 4.8 kGZ RR = 2.54 kGZ V20bdm STs V22dn~m STs~h, V30dI~mSTS Figure 517. Reference voltage generator VTH prOVides threshold voltages (V20dem, V. 22dem and V30dem) either for short training symbol signal or for sine wave signal . 5.4 IC Implementation and Measurement 5.4.1 IC Implementation with Embedded Test Points The portion of the AGC circuits following the channelselection filter in Figure 52, including two VGAs, switched gain control 2 and AGC with onestep correction, was fabricated using a 0. 18 Clm CMOS process available through MOSIS. Onchip embedded test points are included in the design for testability. Analog test buses provide access to internal nodes using switching structures [Bur01]. Figure 518 shows the AGC circuitry with 7 test points (SWT1 ~ SWT7). The main signal chain of the AGC circuit consists of two VGA stages as described in the previous section. Combined with external coupling capacitors (C 0.1 CLF), input bias voltages for VGA2 are provided by onchip resistors (R 240 ka) in a negative feedback loop from the output nodes of VGA3. This feedback loop works as an RC lowpass filter which provides dc bias voltage to the input stage. Output signals can be measured through voltage buffers which reduce the output impedance of the AGC circuit. Simple PMOS source followers are used as voltage buffers as shown in Figure 519. Since these buffers are for test purpose, 3 V devices are used to accommodate level shifted DC bias voltage (0.48 V 1.48 V). The current source M2 provides 1 mA of DC bias current for good sourcing capability which enables this buffer to sink a large current from the load concerning largesignal behavior. The bulk of Ml is tied to the source using a separate nwell, which eliminates nonlinearity due to body effect. As designated in Figure 518, seven test point switches are placed as follows: 1) at the output nodes of RD3, 2) between the output nodes of RD5 and the Vo input nodes of VtoI converter, 3) between the Io output branch of VtoI converter and the Io input branch of computation block, 4) between the herf output branch of VtoI converter and the herf input branch of computation block, 5) between the IC2 Output branch of computation block and the IC2 input branch of ItoV converter, 6) between the output nodes of Vcl/VC2 time switch and the V, input nodes of DDA, and 7) between the Vdc output nodes of ItoV converter and the Vdc input nodes of VGA4. Test switches 3), 4) and 5) are current switches implemented using current mirrors with transmission gate switches while others are voltage switches (transmission gate switches). VC2 Cm IV sw .DDA 1 v v1 v1 yref VGA4 1 Hv v1 D Onestep Gain Control Figure 518. Proposed AGC circuitry with 7 test points VtddJv Vp M2 out pmoissv n Md Figure 519. Output voltage buffer All test points are connected with differential in/out test buses through input/output test switches, and the test buses are connected to four pads (Test~in+, Test~in, Test~out+ and Test~out). From the test pads, we can access one out of seven test points, selectable using test switches. Internal signal paths are connected as normal when the test switches are off. However, one of the test switches is on, the internal signal path of the point is disconnected and the test point is externally accessible. For example, if we turn the test switches 7_IN and 7_OUT on, then the Vdc output nodes of the ItoV converter are connected to Test~out+ and Test~out pads, and the Vdc input nodes of DDA are connected to the Test jn+ and Test~in pads. In this switch selection, we can monitor internal Vdc from Test~out pads and force an external Vdc value to Test~in pads during measurement. The voltage switch SWT7 in Figure 520 (a) has two selections, that is, SWTi for test input and SWTo for test output, and eight transmission gates for differential signal paths, where four of them (A, B, C and D) are used for positive signal paths. Two internal nodes (Vip and Vop) are COnnected through transmission gates A and C when both switches are set to 0. Setting SWTo to 1 forces transmission gate A to off and B to on, which changes connection from VipVop to VipTop. Thus, internal voltage of node Vip can be monitored through the positive test output pad Top. Similarly, setting SWTi to 1 makes Vop COnnected to Tip, thus external input can be forced into Vop HOde through the positive test input pad Tip. Figure 520 (b) shows current switch SWT5, used for testing the Ic2 branch in the computation block. Two selections are SWTi for test input and SWTo for test output. Voltage switch box SWI connects Vn2 to VN node and ground (0) to VTi and VTo nodes when both switches are off. In this switch connection, the output current flows through the Ic2 branch via the M1M2M3M4 current mirror. When SWTi is set to on, the gate of M4 is switched to ground; hence, the Ic2 branch is disconnected from the computation block. At the same time, the gate voltages of M6 and M9 are switched from ground to Vn2, which enables connection from Tin to Ic2 via M6M7M8M9 current mirror. For the test output, switch sw5To is set to on. This makes transistor M4 off and transistor MS on, thus the output current flows through Tout branch via M1M2M3M5 current mirror. 5.4.2 Simulation Results The implemented AGC circuits were simulated using Cadence Spectre with TSMC 0.18 Clm models. Figure 521 shows DC simulation results for the VGA in the inverse gain control loop. By applying control voltage V, to the inverse gain loop, we can easily achieve a linear gain control characteristic with desired gain of A, = V,/Vde. With Vdc = 35 mV, we can get the VGA gain of 4 dB by setting V, = 22. 1 mV, of 0 dB by setting V, = 35 mV and of 16 dB by setting V, = 221 mV. When Vin is set to 39.6 mV, the simulation result shows that Vout changes from 25 mV to 247 mV with V,, a range of 4 to 16 dB. This is just a 0.1 dB gain error at the maximum gain (16 dB). Another DC simulation is for the inputoutput linearity of the VGA. ISWTo I~11n (b) Figure 520. Test switches; (a) voltage switch, and (b) current switch 79 J i' r Vout 1G~T~m 221150 m 121 55m 221.00m A: (22.1rn dla: (18m 2 2m) B: (21m  I soupe: 1.11575 Figure 521. DC gain control simulation for the VGA with inverse gain loop Figure 522 (a) shows Vin vs. Vout plot at the minimum gain (4 dB), while Figure 522 (b) shows the plot at the maximum gain (16 dB). The simulation results show that the linearity error for the maximum input (250 mV,) at the minimum gain is 0.36 dB and the linearity error for the maximum output (250 mV,) at the maximum gain is 0.1 dB. AC response plots of the twostage VGA shown in Figure 523 ensure the operation of the VGAs in the channel frequency range (156.25 KHz ~ 8.3 MHz). : /op1 800lm _: /on1 50Alm 25 m 40im : fop1 700;m _: /on1 400;m 300jm ~ 250m B: (25Dm  4 slope: 0l.0 Vamp delta: (79,2m 493,6Mm) slope: 6.23532 Figure 522. DC simulation for Vin versus Vout of the VGA at (a) 4 dB gain and (b) 16 dB gain 80 10.0 :"(a) 30.03 dB @ 48 MHz 70.0r (b) 200r 450 @ 9.6 MHz 8 1350 @ 28 MHz 1 100K 1M 10M 100M 1G Frequency  Figure 523. AC response of the VGA; (a) gain and (b) phase Noise simulation indicates that the total output noise of the VGA for the signal bandwidth (156.25 KHz ~ 8.3 MHz) at 0 dB gain is 221 LVrms. Input referred noise can be derived as: 221e6/\81e = 77.5 nV/EH. Figure 524 shows noise versus gain plot of the VGA. Input referred noise at the minimum gain (4 dB) is about 120 nV/9\Hz due to negative gain, but it goes down to 97 nV/E~H at the actual minimum gain without margin (2 dB). Moreover, as VGA1, located before channelselect filter, has 7 or 14 dB selectable gain, the input referred noise of the analog baseband processor would be below 40 nV/EH. The linearity of the 2stage VGA is specified by singletone total harmonic distortion (THD) in 8, O and 32 dB gain modes in Figure 525. The 2stage VGA shows 0.99 % THD at the maximum gain (32 dB), while it shows 1.03 and 1.36 % THDs at 0 dB and minimum (8 dB) gains, respectively. A; (2bdm 1.3b233) delta: (0 328.971m) A: (t).2dm 994.2/bm) B: (250m 1.03336) slope: undefined Figure 525. Linearity of the 2stage VGA in THD (%) versus input signal voltage plots at (a) 8 dB, (b) 0 dB and (c) 32 dB gain settings Figure 526 shows the input versus output characteristic of the RMS detector. Plots (a) and (b) are drawn in dB range, where (a) is for a sine wave input and (b) is for a short training symbol. The input versus output characteristics for sine waves and short training symbols have about 21 dB (18 to 3 dB) of dynamic range with reasonable linearity. Transient Response ,. : thd(VT("/net0157") Ze06 4e06 64 10000~r (C) M, t 700m. D (%) 600m. 500m 5.20m 5.601m 6.00m 6.401m Vn (V)' Vamp * out noise a in noise Gain vs. Noise 4 2 0 2 4 6 8 10 12 14 16 Gain (dB) Figure 524. VGA input and output noise versus gain Transient Response :: thd(V("net0157) Ze06 4e06 64 10 1,0 .s: thd V("net0157 ) Ze06 4e06 64 10 1.20 (a) THI 6001m t 4001m .... 150m 200m 250m Vs, (V)' vamp Figure 526. Input versus output characteristic of RMS detector; (a) for sine wave signal and (b) for short training symbol The input voltage versus output current characteristic of the VtoI converter is shown in Figure 527 (a). The VtoI converter takes the differential voltage from the RMS detector as input and converts it to a singleended output current which flows into the computation block as lot. To make sure the current mode circuit operate fast enough for the settling time constraints, the VtoI converter was designed with fast step response (Figure 527 (b)). Figure 528 shows the input versus output plot of the ItoV converter. DC Response Transient Response 1.40~u :. /1128/Iout R 700ln .a: /Il28/Iout 1.2u a600n 10Iut 1.00~u I0ut 500~n 400 200n *~i ** *** *** ** r ,,,. ,, ,,, ,,, I 200~n 20.10m 70.10m 120m 170m 0.0 500n 1.0u Vamp2 time ( s) B: (164.9;8m 1.362510) slope: B.1i6609u Figure 527. Characteristic of VtoI converter; (a) input versus output linearity and (b) step response 82 (a) RMS detector (sin) 12tl8 (b) RMS detector (STS) v uc Vln(dB) Vm (dB DC Response 700lm . 600m V ot+ V,, Idc A: r1_bu /bb.602m) deta: i0 498._2t8m) B: (1,5u 260.394m~slope: undefined Figure 528. Input versus output characteristic of ItoV converter The differential output voltage (0 ~ 500 mV,,) changes linearly along with the singleended input current (0 ~ 1.5 CLA). The small increase (~20 mV) of the common mode voltage over the range does not affect the differential output voltage of the ItoV converter. Simulation results of the proposed analog computation block for sine wave and short training symbol signals are shown in Figures 529 and 530, respectively. As discussed in the circuit design section, the computation block operates in current mode with three inputs (lot, herf and Ict) and generates one output (IC2). The plots show the output (IC2) VeTSus input (lor) characteristic, since the currents herf and Icl are fixed in the final gain setting step. The switched gain control current Icl is set to one of the four preset values: 256 nA (3 dB), 452 nA (7 dB), 794 nA (17 dB) and 1.397 CLA (27 dB). The reference current herf is set to 1.025 CLA for sine wave or to 631 nA for the short training symbol signal. Again, this computation block corrects the VGA gain, which was set to a switched gain with 5 dB error range, to the final gain with 1 dB error. Figure 529 shows simulation results for sine wave signals, with lot swept from 500 nA (6.2 dB from Irer) to 2 CLA (5.8 dB from Irer). The simulated control current IC2 is plotted in the 84 black curve while the ideal curve is drawn in gray. The largest error between the simulation and the ideal is 0.36 dB when lot is bigger (5.8 dB) than herf with 3 dB switched gain. Figure 530 shows the simulation results for short training symbol signals, with lot swept from 300 nA (6.5 dB from Irer) to 1.2 CLA (5.6 dB from Irer). In this simulation, the largest error is 0.4 dB when lot is smaller (6.5 dB) than herf with 27 dB switched gain. Figure 53 1 depicts the step response of the computation block, which demonstrates that the currentmode operation in weak inversion should meet the settling time constraints of the system. DC Response DC Response (a) :(2.561e07 sqrt((1.0246e06 /' IS( (b) ::(4.5183e07 sqrt((1.0246e3 6 / IS 4001n : /150/102 700n .: /Il50/Ic2 Irr rrorn 100n .. I 3 0 . . . 500n 1.30u 2.10u DC Response (c) :(7 9359e07 sqrt((1 0246e06 / IS 1.20u ': /1150/102 1.1lu 500 n .... ...........~~...... I l . .' .' 500n 1.30u 2.10ru 500n i 1.30u 2.10u I01 DC Response (d) : (1.397e06 sqrt((1 0246e06 / IS( 2.10~u 1: /Il50/Ic2 ..0u 1i0.27 dB error 5.00n13u .0 1.1R01 Figure 529. DC simulation results of the computation block for sine wave signal with the switched gain of (a) 3 dB, (b) 7 dB, (c) 17 dB, and (d) 17 dB DC Response (a) ;: (2.561e07 sqrt((6.307e07 / IS 400n an /Il50/Ic2 DC Response (b) : (4.sise07 sqrt((e.3B7e07 7 / s( 700n `: /Il50/~Ic2 600n 500 nIref 400  *****C1(7dB) 0.13 dB error 300[2n 800lln 1.30iu DC Response (d) ;: (1.397eB6 sqrt((e.307eov / IS( 2.10u :/l5/2 300n 750n 1.2u I01 ...... c1 (3dB) 0.21 dB error 300 n 200~n 100ln 300In 800n 1.30iu DC Response (C) ;: (7.936e07* sqrt((6 307e07/ IS( 1.30u 1: /1150/Ic2 0.22 dB error 300n 750n 1.2u 101 Figure 530. DC simulation results of the computation block for short training symbol signal with the switched gain of (a) 3 dB, (b) 7 dB, (c) 17 dB, and (d) 17 dB Transient Response .; /Il50l/Ic2 .,: /V9/PLUS ." " 1.R0u 900n 800~n 700n 600n 500n 40~n 300n 0.01.0u 2.0Iu time (s ) Figure 531i. Transient simulation result (step response) of the computation block The proposed AGC circuit in Figure 518 is simulated using transient response for both sine wave and short training symbol signals. Given a settling time requirement of 7 short training symbol times, the implemented AGC circuit uses symbol time duration from t3 through t7 (5x0.8 = 4 Cps). The initial gain for twostage VGA is set to 12 dB. The switched gain is selected during t4 and the final gain is adjusted during t6. Figure 5 32 shows output signals with the final gain of (a) 4 dB, (b) 1 dB, (c) 4 dB and (d) 9 dB, where the switched gain of 3 dB for (a) and (b), and 7 dB for (c) and (d) are selected. Simulation results with small sine wave inputs to get the final gain of (a) 15 dB, (b) 20 dB, (c) 23 dB and (d) 28 dB are shown in Figure 533. Similar simulations with short training symbol inputs are presented in Figures 534 and 535. From the simulation results, it can be observed that the AGC circuit adjusts signals to the desired level with gain error less than +1 dB through the actual gain range of 4 ~ 28 dB. 5.4.3 IC Measurement and Analysis The proposed AGC circuit in Figure 518 was laid out using the TSMC 0.18Cpm process with 6 metal layers. Figure 536 shows the full chip layout floor plan including 40 bonding pads. The total chip area including ESD (ElectroStatic Discharge) bonding pads is 2850 x 2850 Cpm, whereas the actual AGC circuit area is 750 x 750 pm. The die photo of the fabricated AGC circuit is shown in Figure 537. The fabricated parts are packaged in DIP40 (40pin ceramic package). The package samples were measured using a test board to get access to the embedded test points. Figure 538 illustrates the test board design for the packaged AGC circuit. The test board includes DIP switches for embedded test point selection and inputoutput matching connectors. The selectable output buffer stage is also included in the test board to provide matching with the 50 R test equipment. The test board shown in Figure 539 was designed and built by the support of Conexant" Systems. A detailed schematic of the test board is attached as an appendix. 1 dB " Error ...~ Error 1.0u 2.~u t me ( s i) i II 1. ...,, ,,.1,,, .,,,,1, ~YYYYYYYYYYYYY 1,,,,, ,,,1,,, ,,,,,1, ,,,,, j r ;r   11 IIl l :I .,j. 11.        a I, a .... ... ... .....1.1 A:i (j.18j48u 1 7006)~ delta : (2n bli4.BQm) t3 t4 t5 t6 t7 1.90 12 dB7 7 dB 9 dB . (d) 1.50 L F" I I O 0 1.0mu dm20us 3.01 4.0u . 4 dB 0 dB 1.00 1 Ou 2.Iu m~e ( s 3.0 ~ 4 OIu A: IS.isa5llu B: (3.19686u 1 busuq) 1.20004) : /Vop  :12 dB deltl: slope: 1(.en 133.3 3 dB 4YS.YUrrn 7M 2.00 1.50 1.00 0.49 dB 1.Tu 2.5u me ( s 3.0a 4 Ou A: (0.lobitou I toI14) B: (3.19006u 1.20265) aelu slop b e : 4n 0 0t.a9 i: 132.2?3M 7 dB : /Voo ~:12 dB1 4 dB 1.90 1.50 0.32 dB 3.00 4 O~u Error = 0.29 dB A 3.18398u 1.74029) AB: (3.1B298u 1.22338) delta: (in 516.9077m) slope: 516.907M Figure 532. Transient simulation results of the AGC circuit for sine wave signal with final gain of(a) 3 dB, (b) 1 dB, (c) 4 dB and (d) 9 dB : /Vop 2.00~ "12 dB  1.50 ~ bili .3 dB i :.1..Eror ~~ Error 1 Ou 2.0u ti;me ( s i) ., (       I I , , 1 1 ,      II I II I ....... .1... ..'. .. "..'. .I. AB: (3.1B~44444u 1.22857) sl~ope 259.9 1p6M) t3 t4 t5 t6 t7 ()1.802 12 dBnj 27 dB 28 dl~n~' 1.50 / 0. 0 0 .0 3 0 4 0 ,.,time2.u. (.C s ) ~ 1R 90 12 dB n (a)  17 dB  0.14 dB 1.50 1.10 1 Ou 2.0lu 3. mre ( s) 3: (1 4Y 10/m) e: undefined 17 dB 4 Olu A 3. 18Bd9u 1./310/) AB: (3. 1B309u 1.23998) in 1.80 12 dBn 0.18 dB 1.50 1.20Z 1 Ou 2.lu t~ime ( s 3 0 4 Olu A 3. 1821u 1 73222) B: (3.1B31u 1 24255) delt@; slope: (ln~ 489I668m) 4B9.668M ~12 dBn 27 dB 1.90 0.34 dB 1.50 S 1.10 3.0 4 Ou Error = 0.35 dB A; (3.18326u 1.72815) B: 3. 1B512u 1.24822) delta; (1.86115n 479.942rn) slope: 257.873M Figure 533. Transient simulation results of the AGC circuit for sine wave signal with final gain of (a) 15 dB, (b) 20 dB, (c) 23 dB and (d) 28 dB 1= 5 dB . ../Error 20 dB~ )Error 23 dB 