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New Modulation Technique to Improve Supply Ripple Rejection of a Digital Pulse Width Modulator

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Title:
New Modulation Technique to Improve Supply Ripple Rejection of a Digital Pulse Width Modulator
Creator:
BULLARD, JASON MARK ( Author, Primary )
Copyright Date:
2008

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Subjects / Keywords:
Acoustic data ( jstor )
Amplifiers ( jstor )
Bandwidth ( jstor )
Circuit boards ( jstor )
Circuit diagrams ( jstor )
Comparators ( jstor )
Computer programming ( jstor )
Control loops ( jstor )
Signals ( jstor )
Simulations ( jstor )

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Source Institution:
University of Florida
Holding Location:
University of Florida
Rights Management:
Copyright Jason Mark Bullard. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Embargo Date:
6/30/2007
Resource Identifier:
436098614 ( OCLC )

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NEW MODULATION TECHNIQUE TO IM PROVE SUPPLY RIPPLE REJECTION OF A DIGITAL PULSE WIDTH MODULATOR By JASON MARK BULLARD A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE UNIVERSITY OF FLORIDA 2004

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Copyright 2004 by Jason Mark Bullard

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This thesis is dedicated to my father, Frank Cyril Bullard.

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ACKNOWLEDGMENTS I would like to pay special thanks to Dr. Khai D. T. Ngo for support and guidance on this thesis. Without his input, the project would never have reached the this conclusion. I thank Dr. William R. Eisenstadt and Dr. Robert M. Fox for their key suggestions and for being on my supervisory committee. I also thank the National Science Foundation, Texas Instruments, Coilcraft, and Intersil for funding such projects and for donating parts. I would also like to personally thank Justin Bullard, Margie Bullard, Marcy Bryant, Evelyn Gonzalez, Clark Harju, Santanu Mishra, Mark Sullivan, and Jeff Strang. Without the support of these individuals, this work would never have been possible. iv

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TABLE OF CONTENTS page ACKNOWLEDGMENTS.................................................................................................iv LIST OF TABLES...........................................................................................................viii LIST OF FIGURES...........................................................................................................ix ABSTRACT....................................................................................................................xvii CHAPTER 1 INTRODUCTION........................................................................................................1 1.1 Motivation...............................................................................................................1 1.2 Background.............................................................................................................1 1.3 Basic Class D Amplifier or DC/AC Inverter..........................................................3 1.4 Cycle by Cycle Control..........................................................................................4 1.5 Pulse Edge Delay Error Correction (PEDEC)........................................................6 1.6 Bi-directional Sawtooth Error Correction (BSEC).................................................7 2 SYSTEM MODELING APPROACH..........................................................................9 2.1 System Overview....................................................................................................9 2.2 Comparator Linear Model....................................................................................10 2.3 Transfer Function and Loop Gain.........................................................................14 3 SYSTEM DESIGN.....................................................................................................16 3.1 Insights from Loop Gain Equation.......................................................................16 3.2 Design to Meet Requirements and Stability.........................................................17 3.2.1 Design of LPF.............................................................................................17 3.2.2 Design of HLPF............................................................................................19 3.2.3 Design of HM..............................................................................................20 3.2.4 Design of HE...............................................................................................23 3.2.5 Design of HC...............................................................................................25 3.3 Loop Stability.......................................................................................................28 3.4 Power Supply Ripple Rejection (PSRR)..............................................................31 3.5 System Frequency Response................................................................................32 v

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4 SYSTEM VERIFICATION........................................................................................33 4.1 Comparator System Verification..........................................................................34 4.1.1 Simulation Data to Verify HC Model.........................................................34 4.1.2 Analysis of Simulation Data to Verify HC Model......................................36 4.2 Behavioral Simulation of Control System............................................................36 4.2.1 Power Supply Rejection.............................................................................37 4.2.1.1 Simulation data for power supply rejection.....................................37 4.2.1.2 Analysis of simulation data for power supply rejection...................39 4.2.2.1 Simulation data for stable switching frequency...............................40 4.2.2.2 Analysis of simulated data for stable switching frequency..............41 4.2.3 Continuous Error Signal.............................................................................41 4.2.3.1 Simulation data for continuous error signal.....................................41 4.2.3.2 Analysis of simulated data for continuous error signal....................41 5 EXPERIMENTAL DATA AND ANALYSIS...........................................................43 5.1 Description of Test Setup.....................................................................................43 5.2 Filter Verification.................................................................................................49 5.2.1 Verification of LPF Filter...........................................................................49 5.2.2 Verification of HLPF Filter..........................................................................51 5.2.3 Verification of HM Filter.............................................................................52 5.2.4 Verification of HE Filter.............................................................................54 5.2.5 Verification of HC Block............................................................................55 5.3 Key Waveforms....................................................................................................56 5.3.1 Laboratory Power Supply Rejection Data..................................................56 5.3.2 Laboratory Phase Node Data......................................................................58 5.3.3 Laboratory Error Signal..............................................................................59 5.4 System Response..................................................................................................60 5.5 Power Supply Ripple Rejection Measurement.....................................................61 5.5.1 Analysis of Differential Power Supply Ripple Rejection Data..................64 5.5.2 Analysis of Common Mode Power Supply Ripple Rejection Data...........64 5.6 Single Tone Test (FFT Analysis).........................................................................65 5.6.1 Laboratory Unit Output Single Tone Test Data.........................................66 5.6.2 Analysis of Unit Output Single Tone Test Data.........................................70 5.6.3 Laboratory Maximum Output Single Tone Test Data................................71 5.6.4 Analysis of Maximum Output Single Tone Test Data...............................76 5.6.5 Laboratory Unit Output Single Tone Test with Supply Ripple Data.........76 5.6.6 Analysis of Unit Output Single Tone Test with Supply Ripple Data.........81 5.6.7 Laboratory Maximum Output Single Tone Test with Supply Ripple Data..................................................................................................................81 5.6.8 Analysis of Maximum Output Single Tone Test Data with Supply Ripple Data..................................................................................................................86 5.7 Two Tone Test (FFT Analysis)............................................................................86 5.7.1 Laboratory Two Tone Test with Unit Output Data....................................86 5.7.2 Analysis of Two Tone Test with Unit Output Data...................................86 5.7.3 Laboratory Two Tone Test with Maximum Output Data..........................93 vi

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5.7.4 Analysis of Two Tone Test with Maximum Output Data..........................99 5.7.5 Laboratory Two Tone Test with Unit Output and Ripple on Supply Data..................................................................................................................99 5.7.6 Analysis of Two Tone Test with Unit Output and Ripple on Supply Data..................................................................................................................99 5.7.7 Laboratory Two Tone Test with Maximum Output and Ripple on Supply Data................................................................................................................105 5.7.8 Analysis of Two Tone Test with Maximum Output and Ripple on Supply Data................................................................................................................111 6 CONCLUSION.........................................................................................................112 APPENDIX A MATHCAD WORKSHEET....................................................................................114 B DERIVATION OF DESIGN EQUATIONS FOR DUAL FEEDBACK SECOND ORDER ACTIVE FILTER.......................................................................................122 C MATLAB CODE......................................................................................................125 C.1 Code for Thesis.m..............................................................................................125 C.2 Code for PlotLog.m............................................................................................126 C.3 Code for PlotLog2.m..........................................................................................128 C.4 Code for IsHarmonic.m......................................................................................129 C.5 Code for THD.m................................................................................................129 C.6 Code for THDN.m.............................................................................................130 C.7 Code for MakeWave.m......................................................................................130 C.8 Code for Nyquist_Bode.m.................................................................................130 C.9 Code for NetworkAnalyzer.m............................................................................133 C.10 Code for NetworAnalyzer2.m..........................................................................135 C.11 Code for Scope.m.............................................................................................135 C.12 Code for Scope2.m...........................................................................................136 C.13 Code for Saber.m.............................................................................................136 D LOOP BACK EVALUTION OF SOUNDCARD AND MATLAB CODE............139 E BUFFER CIRCUIT SCHEMATIC AND LAYOUT...............................................143 LIST OF REFERENCES.................................................................................................146 BIOGRAPHICAL SKETCH...........................................................................................148 vii

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LIST OF TABLES Table page 3-1 Values for LPF.......................................................................................................18 3-2 Values for HLPF......................................................................................................20 3-3 Values for HM........................................................................................................23 3-4 Values for HE.........................................................................................................25 3-5 Values for HC.........................................................................................................27 viii

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LIST OF FIGURES Figure page 1-1 Basic Class D amplifier...........................................................................................4 2-1 Block Diagram of Control Scheme..........................................................................9 2-2 Basic Schematic of NSPWM Generator................................................................10 2-3 AC Input Signal.....................................................................................................11 2-4 AC NSPWM Signal...............................................................................................11 2-5 DC Input Signal.....................................................................................................12 2-6 DC NSPWM Signal...............................................................................................12 2-7 Timing Diagram for NSPWM Signal....................................................................13 2-8 Block Diagram of Control Scheme with Loops Labeled.......................................15 3-1 Basic Loop Gain Plot.............................................................................................16 3-2 Block Diagram for LPF.........................................................................................17 3-3 Schematic for LPF.................................................................................................18 3-4 Magnitude Plot of LPF...........................................................................................18 3-5 Phase Plot of LPF...................................................................................................19 3-6 Schematic for HLPF.................................................................................................20 3-7 Block Diagram for HLPF.........................................................................................20 3-8 Magnitude Plot of HLPF..........................................................................................21 3-9 Magnitude Plot of HLPF..........................................................................................22 3-10 Schematic for HM...................................................................................................22 3-11 Block Diagram for HM...........................................................................................22 ix

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3-12 Magnitude Plot of HM............................................................................................23 3-13 Phase Plot of HM....................................................................................................24 3-14 Schematic of HE.....................................................................................................24 3-15 Block Diagram of HE.............................................................................................24 3-16 Magnitude Plot of HE.............................................................................................25 3-17 Phase Plot of HE.....................................................................................................26 3-18 Schematic for HC....................................................................................................26 3-19 Block Diagram for HC............................................................................................27 3-20 Magnitude Plot of HC.............................................................................................27 3-21 Phase Plot of HC.....................................................................................................28 3-22 Complete Block Diagram for Control Scheme......................................................28 3-23 Magnitude Plot of Loop Gain................................................................................29 3-24 Phase Plot of Loop Gain........................................................................................29 3-25 Nyquist Plot of the Designed Loop Gain...............................................................30 3-26 Zoomed-in Nyquist Plot of the Designed Loop Gain............................................30 3-27 Hand Calculation of PSRR of System...................................................................31 3-28 Hand Calculation of System Response..................................................................32 4-1 Saber Schematic.....................................................................................................33 4-2 Nyquist Plot of Stable System for Model Verification..........................................34 4-3 Nyquist Plot of Unstable System for Model Verification......................................35 4-4 Output of Predicted Stable System for Model Verification...................................35 4-5 Output of Predicted Unstable System for Model Verification...............................36 4-6 Output and Supply Rails with 4 kHz Supply Ripple using Control Circuit..........37 4-7 Output and Supply Rails with 4 kHz Supply Ripple not using Control Circuit....38 4-8 FFT of the Output Voltage using Control Circuit..................................................38 x

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4-9 FFT of the Output Voltage not using Control Circuit............................................39 4-10 Simulated Phase Node...........................................................................................40 4-11 Simulated Error Signal...........................................................................................42 5-1 Schematic of Circuit Board, PWM Signal Generation..........................................43 5-2 Schematic of Circuit Board, HM Filter...................................................................44 5-3 Schematic of Circuit Board, HLPF Filter................................................................44 5-4 Schematic of Circuit Board, HE Filter...................................................................45 5-5 Schematic of Circuit Board, HC Block..................................................................45 5-6 Schematic of Circuit Board, LPF filter..................................................................46 5-7 Schematic of Circuit Board, Bypass Capacitors....................................................46 5-8 Top Layer of Layout of Circuit Board...................................................................47 5-9 Bottom Layer of Layout of Circuit Board.............................................................47 5-10 Laboratory Setup A................................................................................................48 5-11 Laboratory Setup B................................................................................................48 5-12 Magnitude plot of LPF Filter.................................................................................49 5-13 Phase plot of LPF Filter.........................................................................................50 5-14 Magnitude plot of HLPF Filter................................................................................51 5-15 Phase plot of HLPF Filter........................................................................................51 5-16 Magnitude plot of HM Filter...................................................................................52 5-17 Phase plot of HM Filter...........................................................................................53 5-18 Magnitude plot of HE Filter...................................................................................54 5-19 Phase plot of HE Filter...........................................................................................54 5-20 Magnitude plot of HC Block..................................................................................55 5-21 Phase plot of HC Block..........................................................................................56 5-22 Supply Rails and Output with Control Circuit.......................................................57 xi

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5-23 Supply Rails and Output without Control Circuit..................................................57 5-24 Laboratory Phase Node Plot..................................................................................58 5-25 Laboratory Error Signal.........................................................................................59 5-26 Laboratory System Response Data........................................................................60 5-27 Zoomed Laboratory System Response Data..........................................................61 5-28 Differential Ripple Rejection with Control Circuit...............................................62 5-29 Differential Ripple Rejection without Control Circuit..........................................62 5-30 Common Mode Ripple Rejection with Control Circuit.........................................63 5-31 Common Mode Ripple Rejection without Control Circuit....................................63 5-32 Output Signal from 20 Hz Single Tone Test Open Loop......................................66 5-33 Output Signal from 20 Hz Single Tone Test.........................................................66 5-34 Ref Signal from 20 Hz Single Tone Test...............................................................67 5-35 Output Signal from 1 kHz Single Tone Test Open Loop......................................67 5-36 Output Signal from 1 kHz Single Tone Test.........................................................68 5-37 Ref Signal from 1 kHz Single Tone Test...............................................................68 5-38 Output Signal from 20 kHz Single Tone Test Open Loop....................................69 5-39 Output Signal from 20 kHz Single Tone Test.......................................................69 5-40 Ref Signal from 20 kHz Single Tone Test.............................................................70 5-41 Maximum Output Signal from 20 Hz Single Tone Test Open Loop.....................71 5-42 Maximum Output Signal from 20 Hz Single Tone Test........................................72 5-43 Maximum Ref Signal from 20 Hz Single Tone Test.............................................72 5-44 Maximum Output Signal from 1 kHz Single Tone Test Open Loop.....................73 5-45 Maximum Output Signal from 1 kHz Single Tone Test........................................73 5-46 Maximum Ref Signal from 1 kHz Single Tone Test.............................................74 5-47 Maximum Output Signal from 20 kHz Single Tone Test Open Loop...................74 xii

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5-48 Maximum Output Signal from 20 kHz Single Tone Test......................................75 5-49 Maximum Ref Signal from 20 kHz Single Tone Test...........................................75 5-50 Output Signal from 20 Hz Single Tone Test Open Loop with Supply Ripple......76 5-51 Output Signal from 20 Hz Single Tone Test with Supply Ripple.........................77 5-52 Ref Signal from 20 Hz Single Tone Test with Supply Ripple...............................77 5-53 Output Signal from 1 kHz Single Tone Test Open Loop with Supply Ripple......78 5-54 Output Signal from 1 kHz Single Tone Test with Supply Ripple.........................78 5-55 Ref Signal from 1 kHz Single Tone Test with Supply Ripple...............................79 5-56 Output Signal from 20 kHz Single Tone Test Open Loop with Supply Ripple....79 5-57 Output Signal from 20 kHz Single Tone Test with Supply Ripple.......................80 5-58 Ref Signal from 20 kHz Single Tone Test with Supply Ripple.............................80 5-59 Maximum Output Signal from 20 Hz Single Tone Test Open Loop with Supply Ripple.....................................................................................................................81 5-60 Maximum Output Signal from 20 Hz Single Tone Test with Supply Ripple........82 5-61 Maximum Ref Signal from 20 Hz Single Tone Test with Supply Ripple.............82 5-62 Maximum Output Signal from 1 kHz Single Tone Test Open Loop with Supply Ripple.....................................................................................................................83 5-63 Maximum Output Signal from 1 kHz Single Tone Test with Supply Ripple........83 5-64 Maximum Ref Signal from 1 kHz Single Tone Test with Supply Ripple.............84 5-65 Maximum Output Signal from 20 kHz Single Tone Test Open Loop with Supply Ripple.....................................................................................................................84 5-66 Maximum Output Signal from 20 kHz Single Tone Test with Supply Ripple......85 5-67 Maximum Ref Signal from 20 kHz Single Tone Test with Supply Ripple...........85 5-68 Output Signal from 60 Hz and 7 kHz SMPTE Open Loop...................................87 5-69 Output Signal from 60 Hz and 7 kHz SMPTE......................................................87 5-70 Ref Signal from 60 Hz and 7 kHz SMPTE............................................................88 xiii

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5-71 Output Signal from 250 Hz and 8 kHz SMPTE Open Loop.................................88 5-72 Output Signal from 250 Hz and 8 kHz SMPTE....................................................89 5-73 Ref Signal from 250 Hz and 8 kHz SMPTE..........................................................89 5-74 Output Signal from 13 kHz and 14 kHz IMD-ITU-R Open Loop........................90 5-75 Output Signal from 13 kHz and 14 kHz IMD-ITU-R............................................90 5-76 Ref Signal from 13 kHz and 14 kHz IMD-ITU-R.................................................91 5-77 Output Signal from 19 kHz and 20 kHz IMD-ITU-R Open Loop........................91 5-78 Output Signal from 19 kHz and 20 kHz IMD-ITU-R............................................92 5-79 Ref Signal from 19 kHz and 20 kHz IMD-ITU-R.................................................92 5-80 Maximum Output Signal from 60 Hz and 7 kHz SMPTE Open Loop..................93 5-81 Maximum Output Signal from 60 Hz and 7 kHz SMPTE.....................................93 5-82 Maximum Ref Signal from 60 Hz and 7 kHz SMPTE..........................................94 5-83 Maximum Output Signal from 250 Hz and 8 kHz SMPTE Open Loop................94 5-84 Maximum Output Signal from 250 Hz and 8 kHz SMPTE...................................95 5-85 Maximum Ref Signal from 250 Hz and 8 kHz SMPTE........................................95 5-86 Maximum Output Signal from 13 kHz and 14 kHz IMD-ITU-R Open Loop.......96 5-87 Maximum Output Signal from 13 kHz and 14 kHz IMD-ITU-R..........................96 5-88 Maximum Ref Signal from 13 kHz and 14 kHz IMD-ITU-R...............................97 5-89 Maximum Output Signal from 19 kHz and 20 kHz IMD-ITU-R Open Loop.......97 5-90 Maximum Output Signal from 19 kHz and 20 kHz IMD-ITU-R..........................98 5-91 Maximum Ref Signal from 19 kHz and 20 kHz IMD-ITU-R...............................98 5-92 Output Signal from 60 Hz and 7 kHz SMPTE Open Loop with Supply Ripple...99 5-93 Output Signal from 60 Hz and 7 kHz SMPTE with Supply Ripple....................100 5-94 Ref Signal from 60 Hz and 7 kHz SMPTE with Supply Ripple..........................100 5-95 Output Signal from 250 Hz and 8 kHz SMPTE Open Loop with Supply Ripple...................................................................................................................101 xiv

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5-96 Output Signal from 250 Hz and 8 kHz SMPTE with Supply Ripple..................101 5-97 Ref Signal from 250 Hz and 8 kHz SMPTE with Supply Ripple........................102 5-98 Output Signal from 13 kHz and 14 kHz IMD-ITU-R Open Loop with Supply Ripple...................................................................................................................102 5-99 Output Signal from 13 kHz and 14 kHz IMD-ITU-R with Supply Ripple.........103 5-100 Ref Signal from 13 kHz and 14 kHz IMD-ITU-R with Supply Ripple...............103 5-101 Output Signal from 19 kHz and 20 kHz IMD-ITU-R Open Loop with Supply Ripple...................................................................................................................104 5-102 Output Signal from 19 kHz and 20 kHz IMD-ITU-R with Supply Ripple.........104 5-103 Ref Signal from 19 kHz and 20 kHz IMD-ITU-R with Supply Ripple...............105 5-104 Maximum Output Signal from 60 Hz and 7 kHz SMPTE Open Loop with Supply Ripple...................................................................................................................105 5-105 Maximum Output Signal from 60 Hz and 7 kHz SMPTE with Supply Ripple...106 5-106 Maximum Ref Signal from 60 Hz and 7 kHz SMPTE with Supply Ripple........106 5-107 Maximum Output Signal from 250 Hz and 8 kHz SMPTE Open Loop with Supply Ripple.......................................................................................................107 5-108 Maximum Output Signal from 250 Hz and 8 kHz SMPTE with Supply Ripple...................................................................................................................107 5-109 Maximum Ref Signal from 250 Hz and 8 kHz SMPTE with Supply Ripple......108 5-110 Maximum Output Signal from 13 kHz and 14 kHz IMD-ITU-R Open Loop with Supply Ripple.......................................................................................................108 5-111 Maximum Output Signal from 13 kHz and 14 kHz IMD-ITU-R with Supply Ripple...................................................................................................................109 5-112 Maximum Ref Signal from 13 kHz and 14 kHz IMD-ITU-R with Supply Ripple...................................................................................................................109 5-113 Maximum Output Signal from 19 kHz and 20 kHz IMD-ITU-R Open Loop with Supply Ripple.......................................................................................................110 5-114 Maximum Output Signal from 19 kHz and 20 kHz IMD-ITU-R with Supply Ripple...................................................................................................................110 xv

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5-115 Maximum Ref Signal from 19 kHz and 20 kHz IMD-ITU-R with Supply Ripple...................................................................................................................111 B-1 Schematic of Filter...............................................................................................122 B-2 Schematic of Filter with Two Input.....................................................................124 D-1 Loop Back Response for 20 Hz Single Tone.......................................................139 D-2 Loop Back Response for 1 kHz Single Tone.......................................................140 D-3 Loop Back Response for 20 kHz Single Tone.....................................................140 D-4 Loop Back Response for 60 Hz and 7 kHz SMPTE............................................141 D-5 Loop Back Response for 250 Hz and 8 kHz SMPTE..........................................141 D-6 Loop Back Response for 13 kHz and 14 kHz IMD-ITU-R.................................142 D-7 Loop Back Response for 19 kHz and 20 kHz IMD-ITU-R.................................142 E-1 Buffer Amplifier Schematic A.............................................................................143 E-2 Buffer Amplifier Schematic B.............................................................................144 E-3 Buffer Amplifier Top Layer Layout....................................................................144 E-4 Buffer Amplifier Bottom Layer Layout...............................................................145 xvi

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Abstract of Thesis Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Master of Science NEW MODULATION TECHNIQUE TO IMPROVE SUPPLY RIPPLE REJECTION OF A DIGITAL PULSE WIDTH MODULATOR By Jason Mark Bullard December 2004 Chair: Khai D. T. Ngo Major Department: Electrical and Computer Engineering We developed a new modulation technique to improve supply ripple rejection of a digital pulse width modulator. This control scheme uses two feedback points (the switching node and the output) to enable a high gain and high bandwidth loop gain at relatively low switching frequencies. This enables a high loop gain for the amplifier, allowing large power supply rejection ratio values, in the order of 65 dB attenuation. This method shows promise for power supply rejection ratio measurements. With future investigation of the linearity performance (signal to noise, total harmonic distortion, and total harmonic distortion and noise), this technique could be used for high fidelity audio power amplifiers. xvii

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CHAPTER 1 INTRODUCTION 1.1 Motivation Class D amplifiers are popular for motor drive and uninterruptible power supplies applications because of their high efficiency [1]. Class D amplifiers are slowly gaining favor in audio amplifiers for the same reason. Although more efficient than Class A, AB, B, or C amplifiers, Class D amplifiers are plagued by high distortion levels and low bandwidth [2]. These limitations in performance are considered acceptable for low frequency audio applications, such as subwoofer power amplifiers, but unacceptable for full bandwidth audio applications. In small battery-powered electronics, power dissipation and power amplifier efficiency are becoming critical design constraints. Of late, Class D amplifiers are being researched and designed for full-bandwidth audio power amplifiers [2-13] to meet these design constraints. In these new designs for power amplifiers, the designs are focusing on improving the bandwidth, linearity, and overall fidelity of the Class D amplifiers by using different control schemes [2-13]. 1.2 Background In many of the systems that would use these Class D amplifiers, the input signal is available as a digital Pulse Code Modulated (PCM) signal. All Class D amplifiers need a Pulse Width Modulated (PWM) signal to operate properly. In early designs, this PWM signal was generated by comparing an analog carrier function with an analog input [4, 6, 10, 12]. The carrier function could be either a ramp function or a triangular waveform. 1

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2 The input would be generated by using a high-resolution Digital to Analog Converter (DAC) to convert the digital PCM to an analog signal. In this solution, the need for both a high resolution DAC and a high-speed analog comparator is a costly solution. Both of these blocks tend to be large and inefficient to implement on silicon. Researchers have developed many ways of converting the digital PCM data directly to a PWM signal to make designs more scalable and efficient. [3, 5, 7, 10, 13]. There are many approaches to solving the PCM to PWM engineering dilemma. The Natural Sampling PWM (NSPWM) method [3, 10], Sigma Delta converter approach [7], and nonlinear techniques [10] are used to obtain a PWM signal that has an equivalent 16Bit resolution in the audio bandwidth. Although many designs convert digital 16Bit PCM data to a PWM signal, few designs address the output stage’s nonlinearity. However, designs that correct for the output stage’s nonlinearity do exist. Most of these designs are able to meet the bandwidth requirements for power amplifiers and only meet the Total Harmonic Distortion and Noise (THD+N) requirements. Many of the designs do not meet the THD+N and linearity specifications over the total bandwidth of the amplifier, given crosstalk through the DC supply for the amplifier. These amplifiers fail to meet these specifications since the loop gain is not large enough over the complete bandwidth of the amplifier [14]. Many of these designs are limited to a second-order system, for stability reasons [15]. This limitation causes a theoretical maximum for the loop gain for a given bandwidth and carrier frequency. Increasing the loop gain to meet the THD+N and linearity requirements for audio amplifiers would cause the carrier frequency to become

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3 unrealizable. The Class D amplifier in our study uses a dual-loop feedback control scheme to overcome this limitation. This allows THD+N and linear requirements to be met with a realistic carrier frequency. One loop is a high-speed loop used to stabilize the system. This loop is confined to a second order, for stability reasons. The other loop is used for bandwidth gain, and it is not responsible for the stability of the system. This allows the second loop to be higher than a second-order loop. 1.3 Basic Class D Amplifier or DC/AC Inverter Figure 1-1 shows the basic complete Class D amplifier [11], which is structured like a buck converter. In this half bridge example there are positive and negative supply rails (+Vg and –Vg), also referred to as +Vpower and –Vpower. The supply rails are fed into a power stage that is connected to a low pass filter (LPF). The node that connects both power switches and the inductor is commonly called the phase node (VP). The output of the Class D amplifier along with the input (Vref) is then fed into a compensation network, C(s). The output of the compensation network is then compared to a triangular waveform, CLK, with the use of a comparator. Finally, the output of the comparator is used to drive the power stage, thus closing the loop. The block C(s) and comparator act together as the error amplifier for this system. The typical input to this system is a pure sinusoidal waveform that can vary its frequency of the audio bandwidth, from 20 Hz to 20 kHz. The output waveform is trying to track the input, and therefore has the same basic shape as the input signal with the addition of a ripple from the switching frequency. Both signals are fed into the C(s) block, where a difference signal is generated. This difference signal is then compared to a triangular waveform. The triangular waveform has a fixed amplitude and frequency. A frequency from 350 kHz to 1 MHz is typically selected as the operating frequency. The amplitude

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4 of the triangular waveform sets up the DC gain of the system, and is selected to be large enough so that noise in the system will not be an issue [11]. The gain of these two blocks working together is the product of the C(s)’s Laplace equation and inverse of twice the amplitude, Vamp, of the triangular waveform. Figure 1-1. Basic Class D amplifier +Vpower The overall loop gain for this system is given in Equation 1-1. The loop gain equation had the LPF(s) block inside it. This creates a stability issue, and Type 2 or Type 3 compensation needs to be used to achieve good DC gain and stability [11]. This type of compensation is a gain and bandwidth tradeoff. To increase one, the other must be decreased. It is for this reason that the following works were devised to extend the bandwidth and the loop gain of Class D amplifiers. !"!" 2AMPLPFsCsV## Equation 1-1 1.4 Cycle by Cycle Control Lai et al. [11] proposed a system for Class D audio amplifiers with full audio bandwidth. The system is simple and elegant. All the non-linearities of the output power MOSFETs (turn-on time, turn-off time, dead time, resistance, rise time, and fall time ) are accounted for and adjusted in each cycle. This is achieved by feeding back the power + C(s) LPF(s) Input + Output Op-Amp -Vpower Com p arato r Power CLK Switch Phase node

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5 switching node before the output filter instead of the final output after the filter. None of the above non-linear problems are able to distort the output signal which causes for lower THD measurements. This greatly reduces the engineering effort in the power MOSFETs and the drive circuitry for the MOSFETs. The system uses a first order filter, an integrator, as an error amplifier. The input to the error amplifier is the analog reference. The system is guaranteed stable because the system is confined to a first order loop. A 95 W power Class D amplifier using this control scheme is build to test the performance. The performance of the amplifier is encouraging. The amplifier has a THD+N figure of 0.07% and a CCIF intermodulation distortion below 0.008%. Power Supply Rejection Ratio (PSRR) measurements are also taken. The amplifier has a PSRR of greater than 63 dB at 120 Hz. There are no data given on the THD+N or the CCIF intermodulation distortion given a ripple on the supply. Also no data are given about PSRR of the amplifier at 20 kHz. This system has the drawback of requiring a high precision ADC for the analog reference, and the loop gain bandwidth is fixed by the switching frequency. The ADC adds complexity and power losses to the system. While the system has a large PSRR at 120 Hz, it is not a real concern in a battery powered system or systems that have a front-end AC to DC converter. A larger concern would be crosstalk between channels through the power supply. It is important that the amplifier have high ripple rejection over the full audio bandwidth. This system would approximately have 22 dB of rejection at 20 kHz, according to the loop gain. In order to achieve approximately 62 dB of ripple rejection at 20 kHz the switching frequency would have to increase by two decades, 25 MHz, much to fast for

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6 practical Class D output stages. This lack of loop gain in battery powered systems would mean the addition of a front-end regulator to guarantee performance. In battery powered systems or AC powered systems, the front-end DC regulator needs to have a high gain over the full bandwidth to guarantee acceptable THD+N and intermodulation distortion levels for the Class D amplifier. 1.5 Pulse Edge Delay Error Correction (PEDEC) Lai et al. [13] presents a Class D amplifier that also addresses the non-linearities of the output stage as in [11]. The input to this amplifier is a pseudo-digital PWM signal; the high and low levels have a constant analog voltage. This simplifies the overall system by eliminating the need for a precision DAC for the reference. However, the amplifier requires the system to have a PCM to PWM converter. A PCM to PWM converter can be implemented in digital circuitry. This would allow it to scale with new smaller semiconductor processes and be more efficient than the analog circuits. Lai et al. [13] presents an elegant solution to the modulation scheme and constant switching frequency problem. Nielsen devised a method to enable a double edge modulation scheme and constant switching frequency by simply slowing the slew rate of the input pseudo digital waveform edges. Nielsen’s new waveform is referenced as VPEDEC in this paper. The controller can operate properly with both a positive and a negative error signal. The modulation scheme also has the ability to modulate both edges of the PWM signal. The PEDEC has limitations that may prevent implementation for some applications. Both the minimum and maximum PWM input signal must allow for the PEDEC signal to clamp out in order for the PEDEC control scheme to work properly. If this does not occur, then the control scheme is violated and stability of the system cannot

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7 be guaranteed. This restriction also limits the loop gain. Another limitation is that the slew time for the PEDEC signal must be limited to enable the amplifier to work over a wide modulation factor. The gain of the amplifier is proportional to the allowable slew time. Widening the modulation factor input therefore causes the gain to decrease [13]. 1.6 Bi-directional Sawtooth Error Correction (BSEC) Lai et al. [5, 15] improves on the design of the PEDEC controller. The control scheme is the same as that for the PEDEC with the exception of the error correcting technique. In this scheme the pseudo digital input signal is used to generate a bi-directional ramp function, thus enabling the control scheme to be valid for any input modulation factor and also increasing the loop gain of the amplifier. The BSEC control scheme works for either a positive or a negative error voltage. The loop gain is much higher in the BSEC system because the ramp amplitude has been reduced. While the system has a larger gain due to the bi-directional ramp, loses some of the usefulness of the PEDEC control scheme. Non-linear effects of the amplifier (turn-on delay, turn-off delay, and finite rise and fall times) need both edges to be modulated to correct for errors. The BSEC scheme does not allow for dual edge modulation. Only one edge is modulated, given the polarity of the error signal. This system will have to delay correcting such errors until the next clock cycle. The overall BSEC amplifier was unable to get better THD+N performance than the Cycle by Cycle amplifier [11]. Loop gain is limited by the compensation filter order, amplifier bandwidth, and switching frequency for all the discussed control schemes. At best case, the compensating filter for stability reasons is second order, 40 dB/decade. The amplifier’s bandwidth must be fixed at 20 kHz because of its applications. Stability reasons require that the loop gain be equal to or less than one at half the switching frequency, typically

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8 one-fourth of the switching frequency. This leaves only the switching frequency or the loop gain for the amplifier’s variable. For example, a loop gain of 40 dB, the switching frequency would have to be 400 kHz or for a switching frequency of 4 MHz, the maximum allowable loop gain would be 80 dB.

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CHAPTER 2 SYSTEM MODELING APPROACH 2.1 System Overview The control scheme for the Class D audio amplifier used in our study is shown in Figure 2-1. The system is comprised of two feedback paths, three active filters (designated by HX(s)), one passive filter (designated by X(s)), and one comparator block. As with all of the examples in Chapter 1 [5, 11, 13], this control scheme has a feedback point at the switching node of the power stage. The second feedback point, the final output voltage, is added to insure that any non-linear effects of the output filter could be accounted and corrected. The block HLPF is added for matching reasons and HE added for stability reasons. The comparator block lumps the Power MOSFETs and analog comparator as one. The system is inherently non-linear, but it can be modeled linearly. Using the assumption that the filters operate in their linear range of operation, the comparator is the only non-linear block. Developing a linear model for the comparator will allow the system to be described by a linear transform function. Figure 2-1. Block Diagram of Control Scheme HM(s) + Input Output + LPF(s) HLPF(s) HE(s) + 9

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10 2.2 Comparator Linear Model To better understand and devise a modeling approach for the comparator, it is important to investigate the ideal Natural Sampled PWM (NSPWM) signal. An ideal NSPWM signal can be generated using the circuit shown in Figure 2-2 [10]. The waveforms for the circuit are shown in Figure 2-3 [10]. The slow base band input signal is compared with the triangular carrier waveform to generate an NSPWM signal Figure 2-2. Basic Schematic of NSPWM Generator Figure 2-4 shows that the NSPWM signal contains information about both waveforms [10]. Recovering the base band information from the NSPWM signal is well understood. It is typically done by passing the NSPWM signal through a low pass filter [9]. To devise a model for the comparator, the high frequency information must also be well understood because it is this determining factor for the comparator’s gain. The base band signal is allowed to go to zero amplitude to better understand the high frequency information. Now all the information in the output must describe the triangular waveform only (see Figure 2-5 and Figure 2-6). The NSPWM signal is a 50% duty cycle square wave. The NSPWM signal must be integrated and scaled to recover the input signal and triangular waveform [9].

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11 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5x 10-6 -1.5 -1 -0.5 0 0.5 1 1.5 Time(s)Voltage (V) Figure 2-3. AC Input Signal 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5x 10-6 -1.5 -1 -0.5 0 0.5 1 1.5 Time(s)Voltage (V) Figure 2-4. AC NSPWM Signal

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12 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5x 10-6 -1.5 -1 -0.5 0 0.5 1 1.5 Time(s)Voltage (V) Figure 2-5. DC Input Signal 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5x 10-6 -1.5 -1 -0.5 0 0.5 1 1.5 Time(s)Voltage (V) Figure 2-6. DC NSPWM Signal

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13 With methods established to recover both base band and carrier information from an NSPWM, it is possible to devise a linear model for the comparator inside this control scheme. The amplifier is expected to receive a digital NSPWM signal as the input [4, 6, 10, 12]. For discussion reasons, it will be assumed that the system is devised so that both waveforms are recovered and presented at the input to the comparator. Therefore, Figure 2-7 could be valid inputs and outputs to the comparator. ST 2ST AMPV AMPV$ INPUTV CARRIERV A B Figure 2-7. Timing Diagram for NSPWM Signal Equation 2-1 describes the duty cycle in terms of A and B. Points A and B are defined in Equation 2-2 and Equation 2-3 respectively. Equation 2-4 is formed by substituting Equation 2-2 and Equation 2-3 into Equation 2-1. Now that the duty cycle, D, is defined in terms of carrier’s amplitude, VAMP and VINPUT, the gain of the comparator can be found by taking the partial derivative of Equation 2-4 forming Equation 2-5 [1].

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14 ABTDS$%# Equation 2-1 !INPUTAMPAMPSVVVTA$##%22 " Equation 2-2 ! " 222SINPUTAMPAMPSTVVVTB&&##% Equation 2-3 212&#%AMPINPUTVVD Equation 2-4 AMPCVVD#%''21 Equation 2-5 To complete the linear model for the comparator, any delay (tD) from input to output must be accounted with the delay function [14]. Equation 2-6 shows the final linear model for the comparator, HC. The numerical gain for the comparator cannot be found until the value of VAMP can be found. VAMP is dependant on the loop gain of the control scheme. !" AMPtsCVesHD#%#$2 Equation 2-6 2.3 Transfer Function and Loop Gain Having assigned linear models to all the control blocks, it is possible to derive a transfer function for the control scheme. Figure 2-8 shows the complete block diagram for the control scheme. Using linear algebra, it is possible to derive the loop gain, ! "s T, of such a system in Equation 2-7 [16]. From Equation 2-7, it is possible to find the loop gain in Equation 2-8 by inspection [15]. With the loop gain defined, it is possible to complete the model for HC in Equation 2-9. Equation 2-10 to Equation 2-12 define terms

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15 so that the complete and final transfer function can be given in a compact form in Equation 2-13. The final loop gain is expressed in Equation 2-14. Figure 2-8. Block Diagram of Control Scheme with Loops Labeled LM ( s ) HM(s) + Input Output + HC(s) LPF(s) HLPF(s) HE(s) + L`E ( s ) LE ( s ) !"!" ! " ! " ! "!"!"!"!"! " !"sLPFsHsHsHHsLPFsHsHHsInputsOutputLPFEMCEMC##&#& # & #%1 Equation 2-7 !"!" ! " ! "!sHsHsHHsTLPFEMC " # &#% Equation 2-8 !"!"!"! " SLPFSESMtsCjHjHjHesHD(((###&##%#$2 Equation 2-9 !" ! "!"!"! " SLPFSESMMtsMjHjHjHsHesLD(((###&###%#$2 Equation 2-10 !" ! " ! "!"!"! " SLPFSESMLPFEtsEjHjHjHsHsHesLD(((###&####%#$2' Equation 2-11 !" ! " ! "!"!"! " SLPFSESMEtsEjHjHjHsLPFsHesLD(((###&####%#$2 Equation 2-12 !"!" !" ! "!"!" !"sLPFsLsLsLsLsInputsOutputEMEM#&&&%1' Equation 2-13 !"!"!"sLsLsTEM&% Equation 2-14

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CHAPTER 3 SYSTEM DESIGN 3.1 Insights from Loop Gain Equation In Chapter 2, the modeling of the control scheme for a Class D amplifier was investigated and equations for the transfer function and loop gain were expressed. The model for the comparator is based on the idea that the system must behave as an integrator at and beyond the switching frequency. So for the equations for loop gain and the transfer function to be valid they also need to have this integrator requirement. Below the switching frequency, there is no restriction on the system’s behavior due to the modeling procedure. LE(s) LM(s) LM(s) dominates T(s) T(s) fS fBW LE(s) dominates T(s) Figure 3-1. Basic Loop Gain Plot The loop gain equation is composed of two terms added together. It is possible to have one term dominate the loop gain equation while the other has a negligible effect. Figure 3-1 shows a system designed to meet the modeling requirements and still maintain a high loop gain. For this LE(s) is chosen to dominate the loop gain in the amplifier’s bandwidth. LM(s), a lower order, dominates at and beyond the switching frequency. 16

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17 Also LM(s) must be designed to resemble an integrator while the signal is above the switching frequency so that the modeling approach for the comparator is still valid. 3.2 Design to Meet Requirements and Stability High fidelity amplifiers need high linearity in the pass band of the amplifier; Class D amplifiers are inherently non-linear. To overcome the non-linearity of this type of amplifier, the loop gain must be high to correct for any non-linear effects. In the next sections of this chapter, each block in the control scheme is designed such that the overall amplifier will have a loop gain of greater that 75dB at and below the bandwidth requirement of 20 kHz. 3.2.1 Design of LPF The amplifier’s power bandwidth is directly affected by LPF(s). For the amplifier to meet the overall power bandwidth requirement, the LPF(s) block needs to be flat and have unity gain near the power bandwidth requirement. The LPF(s) is a second order inductor, capacitor, and resistor passive filter. The LPF block is designed to have a corner frequency at the power bandwidth requirement and a quality factor, Q, of one. Figure 3-2 shows the schematic for the block LPF. Figure 3-3 shows the equivalent block diagram for the schematic shown in Figure 3-2. The values for the elements in the schematic are given in Table 3-1. Finally, the theoretical response of the block is given in Figure 3-4 and Figure 3-5. In LPF Out LPF LPF Figure 3-2. Block Diagram for LPF

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18 LLPF Figure 3-3. Schematic for LPF Table 3-1. Values for LPF Element Name Element Value RLPF 16 ! LLPF 120 H CLPF 0.57 F 101 102 103 104 105 106 -80 -60 -40 -20 0 20 Frequency (Hz)Magnitude (dB) Figure 3-4. Magnitude Plot of LPF In LPF Out LPF RLPF CLPF

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19 101 102 103 104 105 106 -180 -135 -90 -45 0 Frequency (Hz)Phase (degree) Figure 3-5. Phase Plot of LPF 3.2.2 Design of HLPF To keep internal signals to a minimal, the HLPF block is designed to match the LPF block. It is not necessary for the filters to perfectly match given tolerances of the elements, but the design of the filters should match. Therefore, the HLPF filter will have the same corner filter and Q of the LPF block. To achieve greater matching between the blocks, the parasitic zero from the capacitor in the LPF block is accounted for and added to the HLPF block. Figure 3-6 shows the schematic for the block HLPF. Figure 3-7 shows the equivalent block diagram for the schematic shown in Figure 3-6. The values for the elements in the schematic are given in Table 3-2. Finally, the response of the block is given in Figure 3-8 and Figure 3-9.

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20 RfLPF In HLPF R1LPF CfLPF R2LPF Out HLPF C2LPF + Op-Amp HLPF RC2LPF Figure 3-6. Schematic for HLPF In HLPF -HLPF Out HLPF Figure 3-7. Block Diagram for HLPF Table 3-2. Values for HLPF Element Name Element Value RfLPF 1.6 k! R1LPF 1.8 k! R2LPF 12.4 k! RC2LPF 0.47 ! C1LPF 10 nF C2LPF 330 pF Op-Amp HLPF OPA627U 3.2.3 Design of HM The HM(s) directly affects the DC loop gain. The amplitude of HM(s) at the switching frequency is the dominant factor for the DC loop gain. HM(s) must also act as an integrator in the area of the switching frequency. Constructing HM(s) as a double pole single zero filter type achieves this goal. The zero location is a balance between DC loop

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21 gain and phase error at the switching frequency. The pole location is used to determine DC loop gain and L(s)’s transition region. Figure 3-10 shows the schematic for the block HM. Figure 3-11 shows the equivalent block diagram for the schematic shown in Figure 3-10. The values for the elements in the schematic are given in Table 3-3. Finally, the response of the block is given in Figure 3-12 and Figure 3-13. 101 102 103 104 105 106 -80 -60 -40 -20 0 20 Frequency (Hz)Magnitude (dB) Figure 3-8. Magnitude Plot of HLPF

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22 101 102 103 104 105 106 0 45 90 135 180 Frequency (Hz)Phase (degree) Figure 3-9. Magnitude Plot of HLPF R1aM Figure 3-10. Schematic for HM Figure 3-11. Block Diagram for HM -HM In A HM In B HM Out HM + + RfM In A HM CfM In B HM R1bM R2M Out HM C2M + Op-Amp HM RC2M

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23 Table 3-3. Values for HM Element Name Element Value RfM 7.87 k! R1M 787 ! R2M 2.61 k! RC2M 10.2 ! C1M 47 nF C2M 1000 pF Op-Amp HM OPA657U 3.2.4 Design of HE For stability reasons the HE(s) filter type is chosen to be the same filter type as HM(s) with the zero location of HE(s) the same as HM(s). The pole location of HE(s) is set to the bandwidth to insure that the loop gain is high enough to meet the linearity requirements of the amplifier. The Q of the HE(s) filter is set to one in order to improve the loop gain at the bandwidth frequency. 101 102 103 104 105 106 -80 -60 -40 -20 0 20 40 Frequency (Hz)Magnitude (dB) Figure 3-12. Magnitude Plot of HM

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24 101 102 103 104 105 106 0 45 90 135 180 Frequency (Hz)Phase (degree) Figure 3-13. Phase Plot of HM Figure 3-14 shows the schematic for the block HE. Figure 3-15 shows the equivalent block diagram for the schematic shown in Figure 3-14. The values for the elements in the schematic are given in Table 3-4. Finally, the response of the block is given in Figure 3-16 and Figure 3-17. R1aE Figure 3-14. Schematic of HE Figure 3-15. Block Diagram of HE -HE In A HE In B HE Out HE + + RfE In A HE CfE R1bE In B HE R2E Out HE C2E + Op-Amp HE RC2E

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25 Table 3-4. Values for HE Element Name Element Value RfE 8.2 k! R1E 820 ! R2E 1.21 k! RC2E 18.2 ! C1E 27 nF C2E 220 pF Op-Amp HE OPA 657U 3.2.5 Design of HC For stability reasons the delay of the HC(s) block will be keep to a minimal. If the block introduces too much delay, the overall system may become unstable. In the test circuit, the delay has been limited to less than 10% of the switching frequency period. If the total delay of the comparator, power switch, and op-amp are too great, the system will not be stable. 101 102 103 104 105 106 -40 -20 0 20 40 Frequency (Hz)Magnitude (dB) Figure 3-16. Magnitude Plot of HE

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26 101 102 103 104 105 106 0 45 90 135 180 Frequency (Hz)Phase (degree) Figure 3-17. Phase Plot of HE Figure 3-18 shows the schematic for the block HC. Figure 3-19 shows the equivalent block diagram for the schematic shown in Figure 3-18. The values for the elements in the schematic are given in Table 3-5. Finally, the response of the block is given in Figure 3-20 and Figure 3-21. Figure 3-18. Schematic for HC RfC R1aC In A HC +Vpower R1bC In B HC + + Out HC Op-Amp HC Comparator HC -Vpower Power Switch

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27 In A HC + HC Out HC + In B HC Figure 3-19. Block Diagram for HC Table 3-5. Values for HC Element Name Element Value RfC 10 k! R1aC 1 k! R1bC 1 k! Op-Amp HC OPA 657U Comparator HC TL3016 Power Switch EL7457 C 101 102 103 104 105 106 0 20 40 Frequency (Hz)Magnitude (dB) Figure 3-20. Magnitude Plot of HC

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28 101 102 103 104 105 106 0 45 90 135 180 Frequency (Hz)Phase (degree) Figure 3-21. Phase Plot of HC 3.3 Loop Stability With each block designed and equivalent block diagrams given, it is possible to analyze the overall system for loop gain and stability. The complete block diagram is given in Figure 3-22. The gain and phase plots are given in Figure 3-23 and Figure 3-24 with the Nyquist plot in Figure 3-25 and a zoomed-in Nyquist plot in Figure 3-26. + -H M + + In H C LFP Out + -H LFP + -HE + Figure 3-22. Complete Block Diagram for Control Scheme

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29 101 102 103 104 105 106 -20 0 20 40 60 80 100 Frequency (Hz)Magnitude (dB) Figure 3-23. Magnitude Plot of Loop Gain 101 102 103 104 105 106 -270 -225 -180 -135 -90 -45 0 Frequency (Hz)Phase (degree) Figure 3-24. Phase Plot of Loop Gain

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30 -8000 -6000 Nyquist Plot of Loop Gain, T(s) -4000 -2000 0 2000 4000 6000 8000 10000 12000 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1x 104 Real AxisImaginary Axis Figure 3-25. Nyquist Plot of the Designed Loop Gain -12 -10 -8 -6 -4 -2 0 2 -20 -15 -10 -5 0 5 10 15 20 Nyquist Plot of Loop Gain, T(s)Real AxisImaginary Axis Figure 3-26. Zoomed-in Nyquist Plot of the Designed Loop Gain

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31 From the gain and phase plots in Figure 3.32, the system looks conditionally stable. This system could become unstable if the gain of the system is lowered enough to cause the phase margin to go to zero [14]. This is not the case in this system. The gain is fixed because it is a function of the poles and zeros of the control loops and not a function of the gain of any one individual op-amp. With precision passive components, the loop gain can be guaranteed to match the design shown in Figure 3-23 through Figure 3-26 guaranteeing stability. At first glance, the Nyquist plots of the loop gain may appear to encircle the point (-1, 0) [14]. If care is taken tracing the curve, it will be seen that it is not encircled. 3.4 Power Supply Ripple Rejection (PSRR) Given that the loop gain has been determined, it is now possible to determine the PSRR for the system [14]. Equation 3-1 gives the Equation for the PSRR of the system. Figure 3-27 is a plot of the PSRR of the System versus frequency. !"!"!" sTsLPFsPSRR&%1 Equation 3-1 101 102 103 104 105 106 -100 -80 -60 -40 -20 0 Frequency (Hz)Magnitude (dB) Figure 3-27. Hand Calculation of PSRR of System

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32 3.5 System Frequency Response Along with the PSRR, the System Frequency Response (SFR) can be found once the loop gain on the control scheme is found [14]. Equation 3-2 gives the equation for the SFR. Figure 3-28 is a plot of the SFR versus frequency. !"!"!" !"sLPFsTsTsPSRR#&%1 Equation 3-2 101 102 103 104 105 106 -80 -60 -40 -20 0 20 Frequency (Hz)Magnitude (dB) Figure 3-28. Hand Calculation of System Response

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CHAPTER 4 SYSTEM VERIFICATION In this chapter, verification of the linearized model of the comparator along with system verification will be investigated using saber simulation data. Simulation data are taken from the system that was discussed and designed in Chapter 3, with the exception of the verification of the comparator model. All simulations use the schematic found in Figure 4-1, varying just the resistor, capacitor, and input amplitude values. in enbl.06u duty_a p2p12 PositionSwitchDriver posd duty_a VDD C L v5 VDD 0.5ripple p2p1 VD 2 PositionSwitchDriver posd Dref input*520koffset:0 Dref R RfLPF ref R2LPF R1LPF C2LPF Dref_n enbl SABERripple:4kinput:0 v-5 Vss SABERC:.497uC1LPF:10nC2LPF:1000pL:127.324uR:16R1LPF:1.816kR2LPF:3.485kRc2LPF:1.326mRc1LPF:.531RfLPF:1.816kESR:10.667m C1LPF C2E C1E R1E RFE R2E error 0.5ripple VS VS Vss veevccop1 p2p1 veevccop1 R1M veevccop1 C1M R2M RFM C2M R1E R1M veevccop1 1k 1k 1k C L R L R C p2p1 Rc1E Rc1M Rc1LPF SABERC1M:82nC2M:1000pR1M:1.509kR2M:54.312kRFM:1.509kRc1M:5.882Rc2M:1.608m SABERC1E:27nC2E:220pR1E:912.137R2E:11.022kRFE:912.137Rc1E:17.863Rc2E:.7307m SABERC1M:82nC2M:1000pR1M:1.471kR2M:52.937kRFM:1.471kRc1M:5.882Rc2M:1.608m Figure 4-1. Saber Schematic 33

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34 4.1 Comparator System Verification It is impossible to validate the comparator model outside the system. The model is validated by therefore establishing the region of stability using the loop gain equation. To accomplish this test, two systems are designed very close to this region; one system is stable and the other unstable [14]. If the systems match the predicted stability, the model is assumed to be accurate. 4.1.1 Simulation Data to Verify HC Model -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Real AxisImaginary Axis Figure 4-2 and Figure 4-3 shows the Nyquist plots of the stable and unstable systems respectively. These systems are then simulated in Saber. The only difference between the two systems is the corner frequency of the HM active filter. Figure 4-4 shows the output for the stable system while Figure 4-5 shows the output for the unstable system. Nyquist Plot of Loop Gain, T(s) Figure 4-2. Nyquist Plot of Stable System for Model Verification

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35 -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Real AxisImaginary Axis Nyquist Plot of Loop Gain, T(s) Figure 4-3. Nyquist Plot of Unstable System for Model Verification 0 0.5 1 1.5 2 2.5x 10-3 -4 -3 -2 -1 0 1 2 3 4 5 6x 10-3 Time(s)Voltage (V)Stable Ouput of Amplifier Figure 4-4. Output of Predicted Stable System for Model Verification

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36 Unstable Ouput of Amplifier 0 0.5 1 1.5 2 2.5x 10-3 -8 -6 -4 -2 0 2 4 6 8 Time(s)Voltage (V) Figure 4-5. Output of Predicted Unstable System for Model Verification 4.1.2 Analysis of Simulation Data to Verify HC Model From the output seen in Figure 4-4 and Figure 4-5, it is clear that the systems match the predicted stability using the loop gain equation. The model for the comparator must therefore be valid and applicable to such systems. 4.2 Behavioral Simulation of Control System All behavioral simulations were performed using the system that was designed in Chapter 3 with the Saber simulation engine. Figure 4.2-1 shows the schematic used for the simulations. The main purpose of the behavioral simulations is to verify the linear models, system performance, and system stability.

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37 4.2.1 Power Supply Rejection Simulations validated the use of the circuit to reduce the effects of ripple present at the supply on the output voltage. The ripple was set to 10% of the DC value of the supply of the output stage at a frequency of 4 kHz. Data were collected with and without the control circuit. The input to the system was a 20 kHz signal. 4.2.1.1 Simulation data for power supply rejection Figure 4-6 and Figure 4-7 show the output voltage with and without the use of the control circuit, respectively. Figure 4-8 and Figure 4-9 show the Fast Fourier Transform (FFT) of the output voltage with and without the control circuit respectively. 0 2 4 6 8x 10-4 -6 -4 -2 0 2 4 6 Time(s)Voltage (V)Ouput of Amplifier with Control Circuit and 4kHz Ripple on Supply Figure 4-6. Output and Supply Rails with 4 kHz Supply Ripple using Control Circuit

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38 0 2 4 6 8x 10-4 -6 -4 -2 0 2 4 6 Time(s)Voltage (V)Ouput of Amplifier without Control Circuit and 4kHz Ripple on Supply Figure 4-7. Output and Supply Rails with 4 kHz Supply Ripple not using Control Circuit 103 104 -160 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Voltage (dB)FFT of Ouput of Amplifier with Control Circuit and 4kHz Ripple on Supply Figure 4-8. FFT of the Output Voltage using Control Circuit

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39 103 104 -160 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Voltage (dB)FFT of Ouput of Amplifier without Control Circuit and 4kHz Ripple on Supply Figure 4-9. FFT of the Output Voltage not using Control Circuit 4.2.1.2 Analysis of simulation data for power supply rejection In Figure 4-6 and Figure 4-7, it is clear that the circuit achieves the goal of ripple reduction. However, it is unclear how much the ripple is reduced until the FFT data are investigated. In Figure 4-8 and Figure 4-9, the 4 kHz ripple mixes with the input signal’s frequency of 20 kHz to generate signals at 16 kHz and 24 kHz. There is about 65 dB of attenuation of the 16 kHz signal from the output without the circuit and the output that used the control circuit. This 65 dB attenuation does not match the hand calculation of a predicted ripple rejection of nearly 80 dB. This discrepancy is believed to be in the modeling of the hysteresis of the comparator, causing the cancellation of the ripple not to be as high as the hand calculations. 4.2.2 Stable Switching Frequency

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40 From Section 4.2.1, it is clear that the output is stable and able to accurately reproduce the base band input signal. The other signal of concern is the switching frequency of the amplifier. The switching frequency of the output stage must also be stable for maximum performance, stability, and Electro-Magnetic Interference (EMI) reasons. The same simulation was run, as in Section 4.2.1, to determine if the switching frequency of the output stage is fixed and stable. 4.2.2.1 Simulation data for stable switching frequency Figure 4-10 is a plot of the switching node, phase, of the output stage of the amplifier. 1.5 1.505 1.51 1.515 1.52 1.525 1.53 1.535 1.54 1.545 1.55x 10-4 -5 -4 -3 -2 -1 0 1 2 3 4 5 Time(s)Voltage (V)Phase Node with Control Circuit and 4kHz Ripple on Supply Figure 4-10. Simulated Phase Node

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41 4.2.2.2 Analysis of simulated data for stable switching frequency In Figure 4-10, the switching frequency of the phase node is fixed and stable. 4.2.3 Continuous Error Signal In all the analyses and hand calculations, the error signal is assumed to be continuous. If at any time the error signal becomes discontinuous due to circuit electronics, the control scheme will lose performance and may even become unstable. The error signal is a function of the loop gain of the system and the errors that are seen by the system. In order to validate the system, the same simulation described in Section 4.2.1 is used. 4.2.3.1 Simulation data for continuous error signal In Figure 4-11, the error signal plot shows the system is able to accurately reproduce the input signal at the output even with the presence of a 10% ripple on the supply of the output stage. 4.2.3.2 Analysis of simulated data for continuous error signal Figure 4-11 shows that the error signal is continuous and valid for circuit operation though that the system does not have an ideal supply for the output stage of the amplifier. The error signal is bounded and less than the supply voltage for the HC block, so there is no need to scale the signal.

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42 4.6 4.65 4.7 4.75 4.8 4.85 4.9 4.95 5x 10-5 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 Time(s)Voltage (V)Error Signal With Control Circuit and 4kHz Ripple on Supply Figure 4-11. Simulated Error Signal

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43 CHAPTER 5 EXPERIMENTAL DATA AND ANALYSIS 5.1 Description of Test Setup Figure 5-1 to Figure 5-7 show the final schematic that was used in evaluating the performance of the control scheme. Figure 5-8 and Figure 5-9 show the layout for the top layer and the bottom layer of the Printed Circuit Board (PCB) that was used to evaluate the system. The layouts for the top and bottom layers do not match the schematic perfectly due to some modifications that had to be made for the system to work properly. The schematic is updated and matches what was used in the laboratory to make measurements. IN IN GND IN_PWM GND -5V IN_PWM 50R1 CLK GND GND 1KR6 11 22 33 XLR1 +5V CLK -5V PHASE +5V PHASE +5V IN_PWM GND conn gnd BNC1 +5V IN_PWM 50R3 -5V GND IND INC GND VL OE INA NC INB VSOUTD VH NC OUTA VS+ OUTC OUTB EL7457CU3 inin+ gnd VccVdd Ltch out out U1TL3016 Figure 5-1. Schematic of Circuit Board, PWM Signal Generation

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44 10.2R11 R8787 -5V GND +5V T1 GND R7787 R97.87k T2 HM PHASE PHASE_PWR 50R12 47nC1CAP0603 2.61kR10 T3 1000pC2 inin+ gnd Vdd out U4OPA657U Figure 5-2. Schematic of Circuit Board, HM Filter GND 1.8kR13 10nC3CAP0603 GND 1.6kR14 HLPF T5 0.47R16 inin+ gnd Vdd out U5OPA627U T4 PHASE 12.4kR15 C4330p +15V -15V Figure 5-3. Schematic of Circuit Board, HLPF Filter

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45 R17820 R198.2k -5V +5V HE T8 R18820 R17A820 GND 220pC6 R201.21k HLPF GND 18.2kR21 OUT T6 T7 50R22 27nC5 inin+ gnd Vdd out U8OPA657U Figure 5-4. Schematic of Circuit Board, HE Filter HE HM HC PHASE_PWR PHASE_PWR +PWR PHASE_PWR +5V -5V +5V GND 10kR25 T9 50R26 T13 +5V -5V GND GND -5V PHASE_PWR -PWR 1kR27 +5V -PWR T11 T10 T12 GND R231k T14 GND inin+ gnd VccVdd Ltch out out U6TL3016 1kR24 inin+ gnd Vdd out U9OPA657U +PWR IND INC GND VL OE INA NC INB VSOUTD VH NC OUTA VS+ OUTC OUTB EL7457CU7 OUT_DIGITAL_PWR OUT_DIGITAL_PWR OUT_DIGITAL_PWR OUT_DIGITAL_PWR OUT_DIGITAL_PWR Figure 5-5. Schematic of Circuit Board, HC Block

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46 L1120u GND 0.47uC7 11 22 33 XLR3 POWERRES16R28 OUT PHASE_PWR GND 0.1uC8 Figure 5-6. Schematic of Circuit Board, LPF filter 0.1uC_U6_A 0.1uC_U6_A 0.1uC_U1_A 0.1uC_U1_A GND B1 10uC_U6_B 10uC_U6_B 10uC_U1_B 10uC_U1_B GND +5V B3 GND -PWR -5V +PWR +5V -5V +5V MOUNT MOUNT 0.1uC_U8_A +5V -5V 0.1uC_U3_A CAP0805 +5V 0.1uC_U3_ACAP0805 MOUNT MOUNT GND -5V 10uC_U9_B +5V -5V 10uC_U4_B +5V 10uC_U4_B GND GND -5V +5V -15V 0.1uC_U5_A +15V 0.1uC_U5_A GND GND 0.1uC_U8_A MOUNT MOUNT 10uC_U9_B GND GND GND 0.1uC_U3_C 0.1uC_U3_C GND GND -5V B2 -5V GND -5V +5V -5V 10uC_U2_B 0.1uC_U2_A +5V 10uC_U2_B 0.1uC_U2_A 0.1uC_U9_A 10uC_U5_B 0.1uC_U4_A 10uC_U5_B 0.1uC_U4_A GND GND 10uC_U7_B 10uC_U7_B GND 0.1uC_U7_A 0.1uC_U7_A GND GND GND GND 10uC_U7_C 10uC_U7_C 0.1uC_U9_A 10uC_U8_B 10uC_U3_B 10uC_U3_B 10uC_U8_B Figure 5-7. Schematic of Circuit Board, Bypass Capacitors Figure 5-10 and Figure 5-11 show the two separate laboratory setups used to do all the measurements. The block labeled “System Under Test” is the circuit board that was given in the previous figures. The only other block that was not a standard piece of test equipment was the Buffer Amplifier. All key information about the buffer board is given in Appendix E.

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47 Figure 5-8. Top Layer of Layout of Circuit Board Figure 5-9. Bottom Layer of Layout of Circuit Board

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48 Oscilloscope: Power Supply: +/-5V HP6236B Power Supply: +/-15V HP6236B Tektronix DTS-460A Ch1-4 +/-5V Buffer Amplifier: +/-15V Network Analyzer: System OPA 541 Ref PC and Under ChA-B AP Instruments Test Power Stage Supply Ripple Frequency Model 200 Function Generator and Audio Capture: Function Generator: Input Philips PM 5192 PC and Lynx L22 Soundcard Function Generator: Output PM 5132 Carrier Frequency Figure 5-10. Laboratory Setup A Oscilloscope: Power Supply: +/-5V HP6236B Power Supply: +/-15V HP6236B Tektronix DTS-460A Ch1-4 +/-5V Buffer Amplifier: +/-15V System OPA 541 Under Power Stage Supply Test Ref Network Analyzer: ChA-B PC and Function Generator and Audio Capture: Input AP Instruments Model 200 PC and Lynx L22 Soundcard Output Function Generator: PM 5132 Carrier Frequency Figure 5-11. Laboratory Setup B

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49 5.2 Filter Verification This section includes testing all the active and passive filters. To obtain this data, the circuit board is modified from its intended use in such a way that the input and output of each block are isolated and can be measured using the AP model 200. 5.2.1 Verification of LPF Filter For the LPF filter verification, laboratory setup B was used. This allows for the reference signal from the network to drive a larger load than the network analyzer was designed to handle. 101 102 103 104 105 106 -80 -60 -40 -20 0 20 Frequency (Hz)Magnitude (dB) Figure 5-12. Magnitude plot of LPF Filter

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50 101 102 103 104 105 106 -180 -135 -90 -45 0 Frequency (Hz)Phase (degree) Figure 5-13. Phase plot of LPF Filter The main difference between the theoretical data from Chapter 3 and data in Section 5.2.1 is at the high frequency response of the LPF filter. This difference is believed to come from the performance of the Buffer Amplifier above 100 kHz. Any decoupling capacitors for the output stage had to be removed so that the Buffer Amplifier would not see such a heavy load at the higher frequencies (above 100 kHz). With the decoupling capacitors removed, the data looked as expected. But the data above 250 kHz should still not be considered reliable data, which is why there is such a difference in the filter response above 250 kHz.

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51 5.2.2 Verification of HLPF Filter Laboratory setup A was used to verification of HLPF filter. The network analyzer sweeps the reference’s frequency from 10 Hz to 1 MHz and measure input and the output to determine the transfer function of the filter. 101 102 103 104 105 106 -80 -60 -40 -20 0 20 Frequency (Hz)Magnitude (dB) Figure 5-14. Magnitude plot of HLPF Filter 101 102 103 104 105 106 0 45 90 135 180 Frequency (Hz)Phase (degree) Figure 5-15. Phase plot of HLPF Filter

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52 The theoretical data from Chapter 3 matches data in Section 5.2.2 with the exception of the phase response of the filter in the neighborhood of 1 MHz. This variation in phase response is attributed to circuit board parasitics, such as via resistance and trace resistance. The design called for a resistance of 0.47! for RC2LPF. The parasitics could cause this value to be larger shifting the zero to a lower frequency, causing the phase error that is observed. 5.2.3 Verification of HM Filter Laboratory setup A was used to verification of HM filter. The network analyzer sweeps the reference’s frequency from 10 Hz to 1 MHz and measure input and the output to determine the transfer function of the filter. 101 102 103 104 105 106 -80 -60 -40 -20 0 20 40 Frequency (Hz)Magnitude (dB) Figure 5-16. Magnitude plot of HM Filter

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53 101 102 103 104 105 106 0 45 90 135 180 Frequency (Hz)Phase (degree) Figure 5-17. Phase plot of HM Filter The theoretical data from Chapter 3 matches data in Section 5.2.3 with the exception of the DC gain of the filter and the final attenuation at 1 MHz. The DC gain variation is probably due to resistor tolerance but with circuit board parasitics also playing a role. The final attenuation variation at 1 MHz is probably due to slight shifts in the poles and zero of the filter due to resistor and capacitor tolerances, also circuit board parasitics.

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54 5.2.4 Verification of HE Filter Laboratory setup A was used to verification of HE filter. The network analyzer sweeps the reference’s frequency from 10 Hz to 1 MHz and measure input and the output to determine the transfer function of the filter. 101 102 103 104 105 106 -40 -20 0 20 40 Frequency (Hz)Magnitude (dB) Figure 5-18. Magnitude plot of HE Filter 101 102 103 104 105 106 0 45 90 135 180 Frequency (Hz)Phase (degree) Figure 5-19. Phase plot of HE Filter

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55 There are no noticeable differences between theoretical data from Chapter 3 and data in Section 5.2.4. 5.2.5 Verification of HC Block Laboratory setup A was used to verification of HC filter. The network analyzer sweeps the reference’s frequency from 10 Hz to 1 MHz and measure input and the output to determine the transfer function of the filter. 101 102 103 104 105 106 0 20 40 Frequency (Hz)Magnitude (dB) Figure 5-20. Magnitude plot of HC Block The data from Section 5.2.5 match the theoretical data from Chapter 3 with the exception of the phase. This discrepancy is because the delay due to the comparator was unable to be accounted for in these data. If it were able to be accounted for, there would

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56 be a phase shift at higher frequencies and the data would more resemble the theoretical data from Chapter 3. 101 102 103 104 105 106 0 45 90 135 180 Frequency (Hz)Phase (degree) Figure 5-21. Phase plot of HC Block 5.3 Key Waveforms 5.3.1 Laboratory Power Supply Rejection Data Laboratory measurements were conducted using laboratory setup A to validate the use of the circuit to reduce the effects of ripple present at the supply on the output voltage. The ripple was set to 10% of the DC value of the supply of the output stage at a frequency of 4 kHz. Data were collected with and without the control circuit. The input to the system was a 1 kHz signal.

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57 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1x 10-3 -6 -4 -2 0 2 4 6 Time(s)Voltage (V) Figure 5-22. Supply Rails and Output with Control Circuit -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1x 10-3 -6 -4 -2 0 2 4 6 Time(s)Voltage (V) Figure 5-23. Supply Rails and Output without Control Circuit

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58 Figure 5-22 shows that the circuit achieves the goal of ripple rejection, just as in the simulation data. The figure also shows that the output of the system is stable. Figure 5-23 shows the output without the use of the circuit, resulting in the ripple having a non-linear effect on the output. 5.3.2 Laboratory Phase Node Data Laboratory measurements were conducted using laboratory setup A to validate the switching frequency of the output stage. The ripple was set to 10% of the DC value of the supply of the output stage at a frequency of 4 kHz. The input to the system was a 1 kHz signal. The phase node was captured using the oscilloscope. -2 -1.5 -1 -0.5 0 0.5 1 1.5 2x 10-6 -6 -4 -2 0 2 4 6 Time(s)Voltage (V) Figure 5-24. Laboratory Phase Node Plot

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59 In Figure 5-24, the switching frequency of the phase node is fixed at 1 MHz. This figure shows that both the output and the switching frequency for the amplifier are stable. This allows for the proper design of a passive filter for EMI and switching frequency attenuation. 5.3.3 Laboratory Error Signal Laboratory measurements were conducted using laboratory setup A to validate that the error signal is continuous and does not have any discontinuities due to circuit electronics. The ripple was set to 10% of the DC value of the supply of the output stage at a frequency of 4 kHz. The input to the system was a 1 kHz signal. The error signal was captured using the oscilloscope. -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5x 10-6 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 Time(s)Voltage (V) Figure 5-25. Laboratory Error Signal

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60 Figure 5-25 shows that the error signal is continuous and that no information is being lost due to circuit electronics. There is a general agreement with base shape and amplitude of the error signal between the data from the laboratory and the simulated data. 5.4 System Response With the system verified and working as expected, more data can be taken to determine the performance of the system. Using laboratory setup A, the network analyzer obtained frequency response of the system. 101 102 103 104 105 106 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 Frequency (Hz)Voltage (dB) Figure 5-26. Laboratory System Response Data Figure 5-26 shows that the system would meet the requirements for bandwidth, and Figure 5-27 shows the system meets the flatness required for audio applications. When comparing the laboratory data and the theoretical data, there is a large agreement in the

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61 basic shape of the system response. Any variations can be mostly attributed to the LPF filter. 101 102 103 104 105 -9 -6 -3 0 3 6 9 Frequency (Hz)Voltage (dB) Figure 5-27. Zoomed Laboratory System Response Data 5.5 Power Supply Ripple Rejection Measurement Laboratory measurements were conducted using laboratory setup B to obtain the PSRR data for both common mode and differential ripple. The reference signal’s amplitude is set to 10% of the DC value of the supply for the output stage. If the supply ripple is a differential signal, the ripple mixes with the input frequency to the system. That is why no input signal is supplied. The data were taken using the network analyzer.

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62 101 102 103 104 105 106 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Rejection (dB) Figure 5-28. Differential Ripple Rejection with Control Circuit 101 102 103 104 105 106 -60 -55 -50 -45 -40 -35 -30 -25 -20 Frequency (Hz)Output Rejection (dB) Figure 5-29. Differential Ripple Rejection without Control Circuit

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63 101 102 103 104 105 106 -70 -60 -50 -40 -30 -20 -10 0 Frequency (Hz)Output Rejection (dB) Figure 5-30. Common Mode Ripple Rejection with Control Circuit 101 102 103 104 105 106 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 Frequency (Hz)Output Rejection (dB) Figure 5-31. Common Mode Ripple Rejection without Control Circuit

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64 5.5.1 Analysis of Differential Power Supply Ripple Rejection Data Figure 5-28 shows that the differential ripple does not quite match the expected 83 dB. The laboratory data are approximately 65 dB of attenuation, which is close to the simulated power supply ripple rejection ratio performance. The performance is not as good as predicted but does prove the system is working. These variations in PSRR can be caused by a lower loop gain than expected. The main factor in determining the loop gain is the attenuation of the HM filter at the switching frequency. Laboratory measurements were less than expected. Figure 5-29 shows the differential ripple rejection of the system without the use of a control circuit. There is some level rejection due to the fact that the ripple is a differential ripple and the operation of a Class D amplifier. 5.5.2 Analysis of Common Mode Power Supply Ripple Rejection Data Figure 5-30 shows that the common mode ripple does not match what was expected from the theoretical data of nearly 83 dB. The laboratory data are more on the order of 60 dB of attenuation, which is once again on the order of what would be expected from simulation data. The fact that the signal does not mix with the input signal means that the energy of the ripple is not divided between two frequencies, resulting in 6 dB less of attenuation. The common mode PSRR performance desegregation is attributed to the same reasons the differential case. Figure 5-31 shows the common mode ripple rejection of the system without the use the of control circuit. In this case, the only rejection comes from the LPF filter. The data above 100 kHz are not reliable data since the bypass capacitors could not be removed and the Buffer Amplifier did not accurately amplify signals above 100 kHz.

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65 5.6 Single Tone Test (FFT Analysis) The last area to investigate is the non-linearity of the amplifier from input to output. Laboratory measurements were conducted using laboratory setup A. To do these tests, a highly linear signal is needed as the input for the system and the output needs to be measured using a highly sensitive digitizer which is accomplished through the Lynx L22 soundcard. Once the information has been digitized, the data are manipulated in MatLab to obtain the data for these graphs. The complete MatLab files can be found in Appendix C. The amplifier’s linearity is checked using a single tone test. While performing the single tone test, the amplitude of the output is set to 0.775 VRMS and the maximum output voltage. Three test frequencies were used to judge the performance of the amplifier: 20 Hz, 1 kHz, and 20 kHz. These single tone tests were also done with and without a ripple injected onto the supply rails. The ripple injected was 4 kHz with amplitude of 10% of the DC voltage of the supply. Along with the output signal, the Ref signal was captured and is included in the figures. Inside of each graph, the S/N, THD, and THD+N (Bandwidth of 80 kHz, A-weighted, B-weighted, C-weighted, and ITU-R 468 weighted) are given. The signal to Noise ration (S/N) is the Root Mean Square (RMS) ration of the power spectrum of the signal information including the harmonics divided by the RMS power spectrum of noise. Total Harmonic Distortion (THD) is the RMS of the harmonic power spectrum. Total Harmonic Noise and Distortion (THD+N) is the RMS of the power spectrum minus the RMS power at the fundamental frequency. The mathematical calculations of S/N, THD, THD+N are given in Appendix C.

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66 5.6.1 Laboratory Unit Output Single Tone Test Data The data is grouped by frequency of the test performed and includes Figure-32 through Figure-40. 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N47dBTHD-47dBTHD+N-47dBTHD+N-57dBATHD+N-50dBBTHD+N-47dBCTHD+N-59dB468 Figure 5-32. Output Signal from 20 Hz Single Tone Test Open Loop 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N52dBTHD-52dBTHD+N-52dBTHD+N-66dBATHD+N-58dBBTHD+N-53dBCTHD+N-65dB468 Figure 5-33. Output Signal from 20 Hz Single Tone Test

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67 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N52dBTHD-52dBTHD+N-52dBTHD+N-67dBATHD+N-58dBBTHD+N-52dBCTHD+N-66dB468 Figure 5-34. Ref Signal from 20 Hz Single Tone Test 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N45dBTHD-47dBTHD+N-45dBTHD+N-48dBATHD+N-49dBBTHD+N-49dBCTHD+N-38dB468 Figure 5-35. Output Signal from 1 kHz Single Tone Test Open Loop

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68 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N64dBTHD-64dBTHD+N-64dBTHD+N-63dBATHD+N-65dBBTHD+N-65dBCTHD+N-54dB468 Figure 5-36. Output Signal from 1 kHz Single Tone Test 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N63dBTHD-63dBTHD+N-63dBTHD+N-62dBATHD+N-64dBBTHD+N-64dBCTHD+N-55dB468 Figure 5-37. Ref Signal from 1 kHz Single Tone Test

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69 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N45dBTHD-54dBTHD+N-46dBTHD+N-60dBATHD+N-61dBBTHD+N-59dBCTHD+N-52dB468 Figure 5-38. Output Signal from 20 kHz Single Tone Test Open Loop 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N51dBTHD-55dBTHD+N-52dBTHD+N-65dBATHD+N-67dBBTHD+N-66dBCTHD+N-53dB468 Figure 5-39. Output Signal from 20 kHz Single Tone Test

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70 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N68dBTHD-71dBTHD+N-66dBTHD+N-72dBATHD+N-74dBBTHD+N-74dBCTHD+N-61dB468 Figure 5-40. Ref Signal from 20 kHz Single Tone Test 5.6.2 Analysis of Unit Output Single Tone Test Data In Figure 5-32 through Figure 5-40, the system response is seen without the use of the control circuit. These plots show there is harmonic distortion and a noise floor that starts about -60 dB with a slope of -20 dB per decade. Figure 5-30 through Figure 5-32 show the performance of system using the control circuit. Data show the noise floor to be down around -120 dB and flat until the corner frequency of the LPF filter is reached, where it has a 40 dB per decade drop off. There also seems to be a spike of noise at 60 Hz and 120 Hz, the frequency of the AC line. When comparing the noise floor of the two systems, the system that uses the control circuit has a clear advantage over the system that does not use the control circuit.

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71 There is also the harmonic distortion that is present in both the open loop data and the data using the control circuit. The fact that the harmonic distortion is present in both systems would point to one of two conclusions: the output stage is generating the harmonic distortion or the input contains this harmonic distortion. Upon further investigation, the Ref signal is also observed. The same harmonic noise is also present on the Ref signal. So it may turn out that the harmonic distortion is not generated at the output stage, but rather in the step that generates the PWM signal. The source of harmonic distortion has yet to be verified due to the lack of test equipment capable of measuring this signal. 5.6.3 Laboratory Maximum Output Single Tone Test Data The data is grouped by frequency of the test performed and includes Figure-41 through Figure-49. 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N37dBTHD-28dBTHD+N-28dBTHD+N-38dBATHD+N-35dBBTHD+N-29dBCTHD+N-34dB468 Figure 5-41. Maximum Output Signal from 20 Hz Single Tone Test Open Loop

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72 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N43dBTHD-31dBTHD+N-31dBTHD+N-51dBATHD+N-39dBBTHD+N-32dBCTHD+N-50dB468 Figure 5-42. Maximum Output Signal from 20 Hz Single Tone Test 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N44dBTHD-33dBTHD+N-33dBTHD+N-51dBATHD+N-40dBBTHD+N-33dBCTHD+N-51dB468 Figure 5-43. Maximum Ref Signal from 20 Hz Single Tone Test

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73 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N39dBTHD-30dBTHD+N-30dBTHD+N-29dBATHD+N-31dBBTHD+N-31dBCTHD+N-23dB468 Figure 5-44. Maximum Output Signal from 1 kHz Single Tone Test Open Loop 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N47dBTHD-36dBTHD+N-36dBTHD+N-35dBATHD+N-37dBBTHD+N-37dBCTHD+N-27dB468 Figure 5-45. Maximum Output Signal from 1 kHz Single Tone Test

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74 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N48dBTHD-37dBTHD+N-37dBTHD+N-36dBATHD+N-38dBBTHD+N-38dBCTHD+N-28dB468 Figure 5-46. Maximum Ref Signal from 1 kHz Single Tone Test 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N15dBTHD-5dBTHD+N-1dBTHD+N-14dBATHD+N-15dBBTHD+N-15dBCTHD+N-2dB468 Figure 5-47. Maximum Output Signal from 20 kHz Single Tone Test Open Loop

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75 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N37dBTHD-36dBTHD+N-31dBTHD+N-42dBATHD+N-43dBBTHD+N-43dBCTHD+N-29dB468 Figure 5-48. Maximum Output Signal from 20 kHz Single Tone Test 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N60dBTHD-63dBTHD+N-52dBTHD+N-54dBATHD+N-56dBBTHD+N-56dBCTHD+N-43dB468 Figure 5-49. Maximum Ref Signal from 20 kHz Single Tone Test

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76 5.6.4 Analysis of Maximum Output Single Tone Test Data The data in this section reflects the same analysis from Section 5.6.2. The reader should refer to Section 5.6.2 for the analysis. The reader should also be aware of the different figure numbering between Section 5.6.3 and Section 5.6.1. These differences should be updated as to apply the analysis given in Section 5.6.2 for the data in Section 5.6.4. 5.6.5 Laboratory Unit Output Single Tone Test with Supply Ripple Data The data is grouped by frequency of the test performed and includes Figure-50 through Figure-58. 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N35dBTHD-35dBTHD+N-35dBTHD+N-34dBATHD+N-36dBBTHD+N-36dBCTHD+N-25dB468 Figure 5-50. Output Signal from 20 Hz Single Tone Test Open Loop with Supply Ripple

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77 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N53dBTHD-53dBTHD+N-53dBTHD+N-66dBATHD+N-58dBBTHD+N-53dBCTHD+N-64dB468 Figure 5-51. Output Signal from 20 Hz Single Tone Test with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N51dBTHD-51dBTHD+N-51dBTHD+N-67dBATHD+N-58dBBTHD+N-52dBCTHD+N-65dB468 Figure 5-52. Ref Signal from 20 Hz Single Tone Test with Supply Ripple

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78 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N34dBTHD-34dBTHD+N-34dBTHD+N-34dBATHD+N-35dBBTHD+N-36dBCTHD+N-24dB468 Figure 5-53. Output Signal from 1 kHz Single Tone Test Open Loop with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N65dBTHD-65dBTHD+N-65dBTHD+N-65dBATHD+N-66dBBTHD+N-66dBCTHD+N-55dB468 Figure 5-54. Output Signal from 1 kHz Single Tone Test with Supply Ripple

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79 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N63dBTHD-63dBTHD+N-63dBTHD+N-62dBATHD+N-64dBBTHD+N-64dBCTHD+N-54dB468 Figure 5-55. Ref Signal from 1 kHz Single Tone Test with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N34dBTHD-54dBTHD+N-34dBTHD+N-38dBATHD+N-40dBBTHD+N-40dBCTHD+N-30dB468 Figure 5-56. Output Signal from 20 kHz Single Tone Test Open Loop with Supply Ripple

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80 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N51dBTHD-55dBTHD+N-52dBTHD+N-65dBATHD+N-66dBBTHD+N-66dBCTHD+N-53dB468 Figure 5-57. Output Signal from 20 kHz Single Tone Test with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N69dBTHD-72dBTHD+N-67dBTHD+N-73dBATHD+N-75dBBTHD+N-74dBCTHD+N-62dB468 Figure 5-58. Ref Signal from 20 kHz Single Tone Test with Supply Ripple

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81 5.6.6 Analysis of Unit Output Single Tone Test with Supply Ripple Data The advantages of the control circuit for ripple rejection are easily seen in the figure that use the 20 Hz input signal. In the other figures, the advantages are not so easily seen because the 4 kHz ripple signal is lost in the harmonic noise. The analysis from Section 5.6.2 also applies to these data also. 5.6.7 Laboratory Maximum Output Single Tone Test with Supply Ripple Data The data is grouped by frequency of the test performed and includes Figure-59 through Figure-67. 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N33dBTHD-24dBTHD+N-24dBTHD+N-26dBATHD+N-27dBBTHD+N-25dBCTHD+N-17dB468 Figure 5-59. Maximum Output Signal from 20 Hz Single Tone Test Open Loop with Supply Ripple

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82 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N56dBTHD-45dBTHD+N-45dBTHD+N-52dBATHD+N-50dBBTHD+N-46dBCTHD+N-46dB468 Figure 5-60. Maximum Output Signal from 20 Hz Single Tone Test with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N55dBTHD-44dBTHD+N-44dBTHD+N-53dBATHD+N-51dBBTHD+N-45dBCTHD+N-47dB468 Figure 5-61. Maximum Ref Signal from 20 Hz Single Tone Test with Supply Ripple

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83 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N35dBTHD-26dBTHD+N-26dBTHD+N-25dBATHD+N-27dBBTHD+N-27dBCTHD+N-16dB468 Figure 5-62. Maximum Output Signal from 1 kHz Single Tone Test Open Loop with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N43dBTHD-31dBTHD+N-31dBTHD+N-30dBATHD+N-32dBBTHD+N-32dBCTHD+N-21dB468 Figure 5-63. Maximum Output Signal from 1 kHz Single Tone Test with Supply Ripple

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84 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N43dBTHD-32dBTHD+N-32dBTHD+N-31dBATHD+N-32dBBTHD+N-32dBCTHD+N-22dB468 Figure 5-64. Maximum Ref Signal from 1 kHz Single Tone Test with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N27dBTHD-28dBTHD+N-20dBTHD+N-27dBATHD+N-29dBBTHD+N-29dBCTHD+N-19dB468 Figure 5-65. Maximum Output Signal from 20 kHz Single Tone Test Open Loop with Supply Ripple

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85 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N38dBTHD-36dBTHD+N-32dBTHD+N-41dBATHD+N-43dBBTHD+N-43dBCTHD+N-29dB468 Figure 5-66. Maximum Output Signal from 20 kHz Single Tone Test with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N61dBTHD-63dBTHD+N-53dBTHD+N-55dBATHD+N-57dBBTHD+N-57dBCTHD+N-44dB468 Figure 5-67. Maximum Ref Signal from 20 kHz Single Tone Test with Supply Ripple

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86 5.6.8 Analysis of Maximum Output Single Tone Test Data with Supply Ripple Data The data in this section reflects the same analysis from Section 5.6.6. The reader should refer to Section 5.6.6 for the analysis. 5.7 Two Tone Test (FFT Analysis) The linearity of the amplifier can also be tested with a two tone test, SMPTE and the IMD-ITU-R. The SMPTE normally is tested with a 60 Hz and 7 kHz signal. The SMPTE test can also be conducted with a combination of 250 Hz and 8 kHz signal; both set of data are given. The IMD-ITU-R test also can have two different combinations of frequencies: 13 kHz matched with 14 kHz and also 19 kHz matched with 20 kHz. Again, both signals are given. As with the single tone test, the amplitude of the signals are tested under unity and maximum output, with and without the same supply ripple. Inside of each graph, the S/N, THD, and THD+N (Bandwidth of 80 kHz, A-weighted, B-weighted, C-weighted, and ITU-R 468 weighted) are also given. Laboratory measurements were conducted using laboratory setup A. 5.7.1 Laboratory Two Tone Test with Unit Output Data The data is grouped by frequency of the test performed and includes Figure-68 through Figure-79. 5.7.2 Analysis of Two Tone Test with Unit Output Data Without the knowledge of where the harmonic distortion is being generated, it is impossible to draw any more conclusions on the performance of the amplifier using the two tone test. The rest of the data will be presented, but as with this section, the data have lost any meaning until it is discovered where the harmonic distortion is being generated.

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87 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N44dBTHD-54dBTHD+N-48dBTHD+N-52dBATHD+N-53dBBTHD+N-52dBCTHD+N-42dB468 Figure 5-68. Output Signal from 60 Hz and 7 kHz SMPTE Open Loop 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N57dBTHD-60dBTHD+N-59dBTHD+N-65dBATHD+N-63dBBTHD+N-60dBCTHD+N-56dB468 Figure 5-69. Output Signal from 60 Hz and 7 kHz SMPTE

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88 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N57dBTHD-61dBTHD+N-60dBTHD+N-66dBATHD+N-63dBBTHD+N-61dBCTHD+N-56dB468 Figure 5-70. Ref Signal from 60 Hz and 7 kHz SMPTE 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N45dBTHD-49dBTHD+N-49dBTHD+N-51dBATHD+N-52dBBTHD+N-52dBCTHD+N-41dB468 Figure 5-71. Output Signal from 250 Hz and 8 kHz SMPTE Open Loop

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89 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N57dBTHD-59dBTHD+N-59dBTHD+N-62dBATHD+N-62dBBTHD+N-62dBCTHD+N-52dB468 Figure 5-72. Output Signal from 250 Hz and 8 kHz SMPTE 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N62dBTHD-66dBTHD+N-65dBTHD+N-67dBATHD+N-67dBBTHD+N-67dBCTHD+N-57dB468 Figure 5-73. Ref Signal from 250 Hz and 8 kHz SMPTE

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90 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N43dBTHD-44dBTHD+N-42dBTHD+N-51dBATHD+N-52dBBTHD+N-52dBCTHD+N-43dB468 Figure 5-74. Output Signal from 13 kHz and 14 kHz IMD-ITU-R Open Loop 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N40dBTHD-44dBTHD+N-44dBTHD+N-49dBATHD+N-51dBBTHD+N-51dBCTHD+N-45dB468 Figure 5-75. Output Signal from 13 kHz and 14 kHz IMD-ITU-R

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91 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N61dBTHD-68dBTHD+N-67dBTHD+N-71dBATHD+N-72dBBTHD+N-72dBCTHD+N-64dB468 Figure 5-76. Ref Signal from 13 kHz and 14 kHz IMD-ITU-R 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N42dBTHD-47dBTHD+N-45dBTHD+N-53dBATHD+N-54dBBTHD+N-54dBCTHD+N-48dB468 Figure 5-77. Output Signal from 19 kHz and 20 kHz IMD-ITU-R Open Loop

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92 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N40dBTHD-44dBTHD+N-44dBTHD+N-52dBATHD+N-54dBBTHD+N-54dBCTHD+N-55dB468 Figure 5-78. Output Signal from 19 kHz and 20 kHz IMD-ITU-R 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N56dBTHD-59dBTHD+N-59dBTHD+N-67dBATHD+N-69dBBTHD+N-69dBCTHD+N-63dB468 Figure 5-79. Ref Signal from 19 kHz and 20 kHz IMD-ITU-R

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93 5.7.3 Laboratory Two Tone Test with Maximum Output Data The data is grouped by frequency of the test performed and includes Figure-80 through Figure-91. 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N35dBTHD-30dBTHD+N-28dBTHD+N-33dBATHD+N-32dBBTHD+N-30dBCTHD+N-21dB468 Figure 5-80. Maximum Output Signal from 60 Hz and 7 kHz SMPTE Open Loop 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N42dBTHD-47dBTHD+N-33dBTHD+N-35dBATHD+N-37dBBTHD+N-37dBCTHD+N-24dB468 Figure 5-81. Maximum Output Signal from 60 Hz and 7 kHz SMPTE

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94 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N55dBTHD-53dBTHD+N-46dBTHD+N-49dBATHD+N-50dBBTHD+N-50dBCTHD+N-37dB468 Figure 5-82. Maximum Ref Signal from 60 Hz and 7 kHz SMPTE 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N36dBTHD-29dBTHD+N-29dBTHD+N-31dBATHD+N-31dBBTHD+N-31dBCTHD+N-21dB468 Figure 5-83. Maximum Output Signal from 250 Hz and 8 kHz SMPTE Open Loop

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95 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N38dBTHD-28dBTHD+N-28dBTHD+N-31dBATHD+N-33dBBTHD+N-33dBCTHD+N-20dB468 Figure 5-84. Maximum Output Signal from 250 Hz and 8 kHz SMPTE 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N51dBTHD-41dBTHD+N-41dBTHD+N-43dBATHD+N-44dBBTHD+N-44dBCTHD+N-32dB468 Figure 5-85. Maximum Ref Signal from 250 Hz and 8 kHz SMPTE

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96 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N28dBTHD-21dBTHD+N-21dBTHD+N-27dBATHD+N-29dBBTHD+N-29dBCTHD+N-24dB468 Figure 5-86. Maximum Output Signal from 13 kHz and 14 kHz IMD-ITU-R Open Loop 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N30dBTHD-25dBTHD+N-24dBTHD+N-31dBATHD+N-32dBBTHD+N-33dBCTHD+N-27dB468 Figure 5-87. Maximum Output Signal from 13 kHz and 14 kHz IMD-ITU-R

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97 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N58dBTHD-54dBTHD+N-54dBTHD+N-59dBATHD+N-61dBBTHD+N-61dBCTHD+N-55dB468 Figure 5-88. Maximum Ref Signal from 13 kHz and 14 kHz IMD-ITU-R 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N23dBTHD-20dBTHD+N-19dBTHD+N-27dBATHD+N-28dBBTHD+N-28dBCTHD+N-24dB468 Figure 5-89. Maximum Output Signal from 19 kHz and 20 kHz IMD-ITU-R Open Loop

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98 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N41dBTHD-40dBTHD+N-39dBTHD+N-48dBATHD+N-50dBBTHD+N-50dBCTHD+N-46dB468 Figure 5-90. Maximum Output Signal from 19 kHz and 20 kHz IMD-ITU-R 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N60dBTHD-63dBTHD+N-52dBTHD+N-54dBATHD+N-56dBBTHD+N-56dBCTHD+N-43dB468 Figure 5-91. Maximum Ref Signal from 19 kHz and 20 kHz IMD-ITU-R

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99 5.7.4 Analysis of Two Tone Test with Maximum Output Data The data in this section reflects the same analysis from Section 5.7.2. The reader should refer to Section 5.7.2 for the analysis. 5.7.5 Laboratory Two Tone Test with Unit Output and Ripple on Supply Data The data is grouped by frequency of the test performed and includes Figure 5-92 through Figure 5-103. 5.7.6 Analysis of Two Tone Test with Unit Output and Ripple on Supply Data The data in this section reflects the same analysis from Section 5.7.2. The reader should refer to Section 5.7.2 for the analysis. 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N35dBTHD-46dBTHD+N-35dBTHD+N-35dBATHD+N-36dBBTHD+N-36dBCTHD+N-25dB468 Figure 5-92. Output Signal from 60 Hz and 7 kHz SMPTE Open Loop with Supply Ripple

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100 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N57dBTHD-60dBTHD+N-59dBTHD+N-65dBATHD+N-62dBBTHD+N-60dBCTHD+N-55dB468 Figure 5-93. Output Signal from 60 Hz and 7 kHz SMPTE with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N57dBTHD-60dBTHD+N-60dBTHD+N-66dBATHD+N-62dBBTHD+N-60dBCTHD+N-55dB468 Figure 5-94. Ref Signal from 60 Hz and 7 kHz SMPTE with Supply Ripple

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101 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N34dBTHD-35dBTHD+N-35dBTHD+N-35dBATHD+N-36dBBTHD+N-36dBCTHD+N-25dB468 Figure 5-95. Output Signal from 250 Hz and 8 kHz SMPTE Open Loop with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N58dBTHD-60dBTHD+N-60dBTHD+N-63dBATHD+N-63dBBTHD+N-63dBCTHD+N-55dB468 Figure 5-96. Output Signal from 250 Hz and 8 kHz SMPTE with Supply Ripple

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102 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N61dBTHD-64dBTHD+N-64dBTHD+N-65dBATHD+N-65dBBTHD+N-65dBCTHD+N-57dB468 Figure 5-97. Ref Signal from 250 Hz and 8 kHz SMPTE with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N36dBTHD-36dBTHD+N-36dBTHD+N-39dBATHD+N-40dBBTHD+N-40dBCTHD+N-28dB468 Figure 5-98. Output Signal from 13 kHz and 14 kHz IMD-ITU-R Open Loop with Supply Ripple

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103 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N40dBTHD-44dBTHD+N-44dBTHD+N-49dBATHD+N-51dBBTHD+N-51dBCTHD+N-45dB468 Figure 5-99. Output Signal from 13 kHz and 14 kHz IMD-ITU-R with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N62dBTHD-69dBTHD+N-68dBTHD+N-71dBATHD+N-72dBBTHD+N-72dBCTHD+N-64dB468 Figure 5-100. Ref Signal from 13 kHz and 14 kHz IMD-ITU-R with Supply Ripple

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104 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N33dBTHD-36dBTHD+N-35dBTHD+N-42dBATHD+N-43dBBTHD+N-43dBCTHD+N-38dB468 Figure 5-101. Output Signal from 19 kHz and 20 kHz IMD-ITU-R Open Loop with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N40dBTHD-44dBTHD+N-44dBTHD+N-52dBATHD+N-54dBBTHD+N-54dBCTHD+N-55dB468 Figure 5-102. Output Signal from 19 kHz and 20 kHz IMD-ITU-R with Supply Ripple

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105 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N56dBTHD-59dBTHD+N-58dBTHD+N-67dBATHD+N-68dBBTHD+N-68dBCTHD+N-64dB468 Figure 5-103. Ref Signal from 19 kHz and 20 kHz IMD-ITU-R with Supply Ripple 5.7.7 Laboratory Two Tone Test with Maximum Output and Ripple on Supply Data The data is grouped by frequency of the test performed and includes Figure 5-104 through Figure 5-115. 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N33dBTHD-30dBTHD+N-26dBTHD+N-27dBATHD+N-28dBBTHD+N-27dBCTHD+N-16dB468 Figure 5-104. Maximum Output Signal from 60 Hz and 7 kHz SMPTE Open Loop with Supply Ripple

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106 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N40dBTHD-39dBTHD+N-29dBTHD+N-32dBATHD+N-34dBBTHD+N-33dBCTHD+N-21dB468 Figure 5-105. Maximum Output Signal from 60 Hz and 7 kHz SMPTE with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N47dBTHD-42dBTHD+N-37dBTHD+N-40dBATHD+N-40dBBTHD+N-39dBCTHD+N-28dB468 Figure 5-106. Maximum Ref Signal from 60 Hz and 7 kHz SMPTE with Supply Ripple

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107 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N32dBTHD-25dBTHD+N-25dBTHD+N-25dBATHD+N-26dBBTHD+N-26dBCTHD+N-15dB468 Figure 5-107. Maximum Output Signal from 250 Hz and 8 kHz SMPTE Open Loop with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N40dBTHD-30dBTHD+N-30dBTHD+N-32dBATHD+N-34dBBTHD+N-34dBCTHD+N-21dB468 Figure 5-108. Maximum Output Signal from 250 Hz and 8 kHz SMPTE with Supply Ripple

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108 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N54dBTHD-45dBTHD+N-45dBTHD+N-47dBATHD+N-48dBBTHD+N-48dBCTHD+N-36dB468 Figure 5-109. Maximum Ref Signal from 250 Hz and 8 kHz SMPTE with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N18dBTHD-10dBTHD+N-10dBTHD+N-16dBATHD+N-18dBBTHD+N-18dBCTHD+N-12dB468 Figure 5-110. Maximum Output Signal from 13 kHz and 14 kHz IMD-ITU-R Open Loop with Supply Ripple

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109 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N38dBTHD-35dBTHD+N-34dBTHD+N-42dBATHD+N-44dBBTHD+N-44dBCTHD+N-38dB468 Figure 5-111. Maximum Output Signal from 13 kHz and 14 kHz IMD-ITU-R with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N57dBTHD-55dBTHD+N-55dBTHD+N-60dBATHD+N-62dBBTHD+N-62dBCTHD+N-55dB468 Figure 5-112. Maximum Ref Signal from 13 kHz and 14 kHz IMD-ITU-R with Supply Ripple

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110 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N32dBTHD-30dBTHD+N-30dBTHD+N-37dBATHD+N-39dBBTHD+N-39dBCTHD+N-36dB468 Figure 5-113. Maximum Output Signal from 19 kHz and 20 kHz IMD-ITU-R Open Loop with Supply Ripple 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N35dBTHD-32dBTHD+N-32dBTHD+N-40dBATHD+N-42dBBTHD+N-42dBCTHD+N-39dB468 Figure 5-114. Maximum Output Signal from 19 kHz and 20 kHz IMD-ITU-R with Supply Ripple

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111 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N53dBTHD-48dBTHD+N-48dBTHD+N-56dBATHD+N-58dBBTHD+N-58dBCTHD+N-53dB468 Figure 5-115. Maximum Ref Signal from 19 kHz and 20 kHz IMD-ITU-R with Supply Ripple 5.7.8 Analysis of Two Tone Test with Maximum Output and Ripple on Supply Data The data in this section reflects the same analysis from Section 5.7.2. The reader should refer to Section 5.7.2 for the analysis.

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CHAPTER 6 CONCLUSION The data from the laboratory measurements, simulations, and hand calculations show a level of consistency. Although some of the filters do not match perfectly, they tend to have consistent performances. The passive low pass filter did not match the design and that is why the System Frequency Response (SFR) differed from hand calculations to the lab measurements. When comparing the rough signal captured by the oscilloscope, the signal very much resembled the shape of the simulated data. Even when comparing the Power Supply Rejection Ratio (PSRR) from simulated data and from lab measurements, there was a level of correlation although the hand calculations did not match. Further investigation needs to be done in order to find the source of the discrepancy. There was no evidence of instability or the system not behaving roughly as expected. The major area where the amplifier did not meet the requirements was in the test that looked at the linearity of the amplifier from input to output. The amplifier’s distortion was too large for audio applications. Further investigation into the source of these harmonic distortions needs to be completed. When in a lab, several different op-amps were used for the HLPF block trying to find an amplifier that would not create so much harmonic distortion on the Ref signal. It still is not clear if the distortion was coming from the Pulse Width Modulation (PWM) input signal or circuit elements. If the harmonic distortion is found to be coming from the circuit elements, then it may be advantageous to try to implement the system with digital filters instead of analog. 112

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113 When more of the system is understood, this control scheme could be a viable solution to dealing with the issue of unclean supplies for the output stage of Class D amplifiers where high levels of linearity are needed with low switching frequency to bandwidth ratio.

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114 APPENDIX A MATHCAD WORKSHEET j1$ ) ns109$sec#) m*103$*#) +s106$sec#) k1000) ,x()argx()180#.% ) Marginx()180,x(&.% dBx()20logx ! " # .% gainx()10x20 .% datapoints200.% x1datapoints//.% fstartfb2000 .% fendfs1#.% declogfendfstart 0 1 2 3 5 .% fx10decx#datapoints fstart#.% (xfx2# #.% 61) fb20kH z #) fzM350kH z #) fs1MHz # ) fzE350kHz # ) fzLPF40MH z # ) (b2-#fb#) (zM2-#fz M #) (s2-#fs#) (zE2-#fzE#) (zLPF2-#fzLPF#) fpM5kHz#) fpE20kHz # ) fpLPF20kH z # ) (pM2-#fpM#) (pE2-#f pE #) (pLPF2-#fpLPF#) QM0.5) QE1 ) QLPF1 ) td60ns#) Rout16*#) HMs()s(zM 1&s(pM 0 1 2 3 5 2s(pMQM# &1& .% ZMs()es$td ! " #.%

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HLPFs()s(zLPF 1&s(pLPF 0 1 2 3 5 2s(pLPFQLPF# &1& .% HEs()s(zE 1&s(pE 0 1 2 3 5 2s(pEQE# &1& .% ZEs()es$td ! " #.% LMs()HMs()ZMs()#.% LEs()ZEs()HLPFs()HEs() # ! " # .% Ls()LMs()LEs()&2LMj(s#!"LEj(s#!"& # .% TFs()HLPFs()Ls() # 1Ls()& .% RRs()HLPFs()1Ls()& .% dBRRj(b#0.02#!"!"82.434$% dBRRj(b# ! " ! "76.912$% dBRRj(b#1.5#!"!"$% 70.587 1001020406080100 /1031/1041/1051/106 Lj(x#!"!"3.6 dBLfx j(x#!"!" Margin gainM20.% C1M47nF#.% Rc1M1(zMC1M# .% Rc1M9.675*% Rc1M10.2*#.% 115

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(zM'1Rc1MC1M# .% (zM'2-# 331.988kHz% C2M1000pF#.% AgainM2C2MC1M(zM'#!"# 7 8 9 : #1gainM&!" .% BgainMC1M(zM'# ! "#1gainM&!" 1QM!"(pM# 1(zM' $7 ; 8 9 < :# 7 ; ; 8 9 < < :$.% C(zM'(pM2 1QM!"(pM# 1(zM' $7 ; 89 < :$7 ; ; 89 < < :.% R1MB$B24A#C#$ $2A# .% RfMR1Mgain M #.% RfM7.952k*% RfM7.87k*#.% 2R1M#0.795k*% R1M.787k*2 .% gainM'RfM2R1M# .% gainM'10 % R2M1QM!"(pM# 1(zM' $C2M R1MgainM#$1gainM&!" .% R2M2.634k*% R2M2.61k*#.% (pM'1R2MRfMR2MR1M&R1M #&0 1 235C2M#7 ; 89 < :RfM1RfMR1M &RfMR2M & C1M#1(zM' &0 1 1 1 2 34 5 # .% (pM'2-# 5.044kHz% QM'1R2MRfMR2MR1M&R1M #&0 1 2 3 5 C2M#1(zM' &7 ; 89 < :(pM'# .% QM'0.5% 116

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HM's()s(zM' 1& 0 1 2 3 5s(pM' 0 1 2 3 5 2s(pM'QM'# &1& gainM ' #.% ) LM's()HM's()ZMs( # .% ZMs()es$td ! " #.% gainE20.% C1E27nF#.% Rc1E1(zEC1 E # .% Rc1E16.842*% Rc1E18.2*#.% (zE'1Rc1EC1 E # .% (zE'2-# 323.881KH z % C2E220pF#.% AgainE2C2EC1E(zE'#!"# 7 8 9 : #1gainE&!" .% BgainEC1E(zE'# ! "#1gainE&!" 1QE!"(pE# 1(zE' $7 ; 8 9 < :# 7 ; ; 8 9 < < :$.% C(zE'(pE2 1QE(pE# 1(zE' $0 1 235$7 ; ; 89 < < :.% R1EB$B24A#C#$ $2A# .% RfEgainER1E#.% RfE8.192k*% RfE8.2k*#.% 2R1E0.819k*% R1E.82k*#2 .% gainE'RfE2R1 E # .% gainE'10% R2E1QE(pE# 1(zE' $C2E gainER1 E #$1gainE& .% R2E1.226k*% R2E1.21k*.% 117

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(pE'1R2ERfER2ER1E&R1E #&0 1 235C2E#7 ; 89 < :RfE1RfER1E &RfER2E & C1E#1(zE' &0 1 1 1 2 34 5 # .% (pE'2-# 20.12kHz% QE'1R2ERfER2ER1E&R1E #&0 1 2 3 5 C2E#1(zE' &7 ; 89 < :(pE'# .% QE'1.003 % HE's()s(zE' 1& 0 1 2 3 5s(pE' 0 1 2 3 5 2s(pE'QE'# &1& gainE#.% LLPFRoutQLPF( p LPF# .% LLPF127.324+H% LLPF120+ H #.% CLPF1LLPF(pLPF2# .% CLPF0.528+F% CLPF.57+F.% Rc1CLPF(zLPF# .% Rc6.98m*% Rc6.5m*#.% Rsw3.54 *#.% RL.8*#.% (pLPF'1LLPFCLPF# .% (pLPF'2-# 19.244kHz% (zLPF'1CLPFRc# .% (zLPF'2-# 42.957MHz% QLPF'LLPFRout CLPFRLRsw&!"#&7 ; 89 < :1$(pLPF .% QLPF'0.941 % gainLPF'RoutRoutRL&Rsw& .% gainLPF'0.905 % 118

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LPFs()s(zLPF' 1& 0 1 2 3 5s(pLPF' 0 1 2 3 5 2s(pLPF'QLPF'# &1&7 ; 89 < : gainLPF'#.% C1LPF10nF#.% Rc1LPF1(zLPF'C1LPF# .% Rc1LPF0.371*% Rc1LPF.47*#.% (zLPF'1Rc1LPFC1LPF# .% (zLPF'2-# 33.863MHz% C2LPF330pF#.% AgainLPF'2C2LPFC1LPF(zLPF'#!"# 7 8 9 : #1gainLPF'&() .% BgainLPF'()C1LPF(zLPF'#!"#1gainLPF'&() 1QLPF'()(pLPF'# 1(zLPF' $7 ; 8 9 < :#7 ; ; 89 < < :$.% C(zLPF'(pLPF'2 1QLPF'()(pLPF'# 1(zLPF' $7 ; 89 < :$7 ; ; 89 < < :.% R1LPFB$B24A#C#$ $2A# .% R1LPF1.741k*% R1LPF1.8k*#.% RfLPFR1LPFgainLPF'#.% RfLPF1.629k*% RfLPF1.6k*# gainLPF'RfLPFR1LPF .% gainLPF'0.905 % R2LPF1QLPF'(pLPF'# 1(zLPF' $C2LPF gainLPF'R1LPF#$1gainLPF'&!" .% R2LPF13.113k*% R2LPF12.4k*# 119

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(pLPF'1R2LPFRfLPFR2LPFR1LPF&R1LPF #&0 1 235C2LPF#7 ; 89 < :RfLPF1RfLPFR1LPF &RfLPFR2LPF & C1LPF#1(zLPF' &0 1 1 1 2 34 5 # .% (pLPF'2-# 18.948KH z % (pLPF'2-# 19.244KHz% QLPF'1R2LPFRfLPFR2LPFR1LPF&R1LPF #&0 1 2 3 5 C2LPF#1(zLPF' &7 ; 89 < :( p LPF'# .% QLPF'0.956% QLPF'0.941% HLPF's()s(zLPF' 1& 0 1 2 3 5s(pLPF' 0 1 2 3 5 2s(pLPF'QLPF'# &1&7 ; ; 89 < < : gainLPF ' #.% LM's()HM's()ZMs(#.% ) LE's()ZEs()LPFs()HE's() # ! " # .% L's()LM's()LE's()&2LM'j(s#!"LE'j(s#!"& # .% TFs()LPFs()L's() # 1L's()& .% RRs()LPFs()1L's()& .% dBRRj(b#0.005#!"!"82.345$% dBRRj(b# ! " ! "76.502$% dBRRj(b#1.5# ! " ! "70.121$% 120

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101001/1031/1041/1051/106 40 20020406080100 MarginLj(x#!"!"3.6 MarginL'j(x#!"!"3.6 dBLj(x#!"!"dBL'j(x#!"!"fx 121

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APPENDIX B DERIVATION OF DESIGN EQUATIONS FOR DUAL FEEDBACK SECOND ORDER ACTIVE FILTER The N-extra element theorem (NEET) is used to drive the transfer function for the active circuit. The reader should refer to [18] for an explanation of the procedure to use the NEET. The notation is as follows: represents the impedance seen at port 1 when using the null double injection. represents the impedance seen at port 1 when using the null double injection and port 2 in inverted from the initial state. represents the impedance seen at port 1 when the input is grounded. represents the impedance seen at port 1 when the input is grounded and port 2 is inverted from the initial state. NR1 21NR DR1 21DR Figure B-1 show the schematic of the dual feedback second order active filter. Equation B-1 to Equation B-8 describes the transfer function of the circuit when applying the NEET. Rf In H(s) R1 C2 R2 Out H(s) C1 + RC Op-Amp H(s) Figure B-1. Schematic of Filter 122

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123 !"!" ! "!"! " 2212112211221211221111sCRCRsCRCRsCRCRsCRCRHsHDDDDNNNNO####&##&#&####&##&#&#% Equation B-1 1RRHfO% Equation B-2 CNRR%1 Equation B-3 02%NR Equation B-4 012%NR Equation B-5 RcRD%1 Equation B-6 !12122RRRRRRfD&#&% "" Equation B-7 !11211112$$$$&&%RRRRfD Equation B-8 With the transfer function of the circuit understood, it is possible to select the resistors and capacitors to achieve the specific transfer function. The capacitor values should be selected first because of the limited standard values available. With C1 and C2 chosen arbitrarily the resistors can be designed for the desired transfer function. Equation B-9 gives the symbolic transfer function that the circuit to achieve. Equation B-10 to Equation B-16 are used to solve for the resistor values. !" 21144531120&#&&#%PPZsQssgainsH((( Equation B-9 ZCCR(#%11 Equation B-10 123

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124 !"ZCCgaingainA(###&%121 Equation B-11 !" 44531120$####&$%ZpMZQCgaingainB(((1111 Equation B-12 44531120$#$%ZppZQC((((112 Equation B-13 ACABBR###$$$%2421 Equation B-14 gainRRf#%1 Equation B-15 gaingainRCCQRzp&#$#$##%1111222(( Equation B-16 Figure B-2 shows the schematic of the dual feedback second order active filter with two inputs. In this system the gain for each input is the same therefore the R1A and R1B resistors must be the same value. The same equations, Equation B1 to Equation B-16, can be used because the gain is set to twice the desired value and R1A and R1B will be twice the value of R1. R1A Rf InA H(s) C2 InB H(s) R1B R2 Out H(s) C1 + RC Op-Amp H(s) Figure B-2. Schematic of Filter with Two Input 124

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APPENDIX C MATLAB CODE C.1 Code for Thesis.m function []=thesis(rootDIR,fs,fbin,os,ch) window=3.0081e-7*10;j=(-1)^0.5;s=(0:80000)*2*pi*j; Aw=(s.^4)./(((s+129.4).^2).*(s+676.7).*(s+4636).*((s+76655).^2)); Aw=Aw'*Aw(1001)^-1;dBA=20*log10(abs(Aw)); Bw=(s.^3)./(((s+129.4).^2).*(s+995.9).*((s+76655).^2)); Bw=Bw'*Bw(1001)^-1;dBB=20*log10(abs(Bw)); Cw=(s.^2)./(((s+129.4).^2).*((s+76655).^2)); Cw=Cw'*Cw(1001)^-1;dBC=20*log10(abs(Cw)); ITU468w=1./(1+(4.118e-5).*s+(9.39e-10).*s.^2+(8.675e-15).*s.^3)) ITU468w=ITU468w.*(1.843).*(s.*4.64e-5); ITU468w=ITU468w./(1+(4.803e-5).*s+(5.801e-10).*s.^2+(9.187e-15).*s.^3); ITU468w=ITU468w'/ITU468w(1001);dB468=20*log10(abs(ITU468w)); directory=dir(rootDIR);j=1; for i=1:size(directory) if getfield(directory(i),'isdir')&((getfield(directory(i),'name')~=('.'))|(getfield(directory(i),'name')~=('..'))) tempDIR(j,:)=directory(i);j=j+1;end;end directory=[];directory=tempDIR;j=[]; for i=1:size(directory); files=dir([rootDIR '\' getfield(directory(i),'name')]); for j=1:size(files) if ~getfield(files(j),'isdir') file=getfield(files(j),'name'); filename=[rootDIR '\' getfield(directory(i),'name') '\' file]; r=find(file=='r'); underscore=find(file=='_'); if isempty(underscore) f1=(file(1:(r-1))); f2=[]; f1=str2num(f1); else f1=(file(1:(underscore-1))); f2=(file((underscore+1):(r-1))); f1=str2num(f1); f2=str2num(f2); end 125

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[FFTdata1,FFTdB1,TIMEdata1,FFTdata2,FFTdB2,TIMEdata2,NF]=windowFFT(window,fs,os,filename); [THDN1]=ceil(THDN(FFTdata1(1:80001),f1,f2)); [THD1]=ceil(THD(FFTdata1(1:80001),FFTdB1(1:80001),f1,f2,NF)) [S2N1]=ceil(S2N(FFTdata1(1:80001),THDN1,f1,f2,THD1)) FFTdata1A=FFTdata1(1:80001).*Aw; FFTdata1B=FFTdata1(1:80001).*Bw; FFTdata1C=FFTdata1(1:80001).*Cw; FFTdata1468=FFTdata1(1:80001).*ITU468w; [THDN1A]=ceil(THDN(FFTdata1A(1:80001),f1,f2)); [THDN1B]=ceil(THDN(FFTdata1B(1:80001),f1,f2)); [THDN1C]=ceil(THDN(FFTdata1C(1:80001),f1,f2)); [THDN1468]=ceil(THDN(FFTdata1468(1:80001),f1,f2)); [THDN2]=ceil(THDN(FFTdata2(1:80001),f1,f2)); [THD2]=ceil(THD(FFTdata2(1:80001),FFTdB2(1:80001),f1,f2,NF)); [S2N2]=ceil(S2N(FFTdata2(1:80001),THDN2,f1,f2,THD2)); FFTdata2A=FFTdata2(1:80001).*Aw; FFTdata2B=FFTdata2(1:80001).*Bw; FFTdata2C=FFTdata2(1:80001).*Cw; FFTdata2468=FFTdata2(1:80001).*ITU468w; [THDN2A]=ceil(THDN(FFTdata2A(1:80001),f1,f2)); [THDN2B]=ceil(THDN(FFTdata2B(1:80001),f1,f2)); [THDN2C]=ceil(THDN(FFTdata2C(1:80001),f1,f2)); [THDN2468]=ceil(THDN(FFTdata2468(1:80001),f1,f2)); if ch==1 potlog(FFTdB1(1:80001),S2N1,THD1,THDN1,THDN1A,THDN1B,THDN1C,THDN1468,f1,f2,filename) else plotlog2(FFTdB1(1:80001),S2N1,THD1,THDN1,THDN1A,THDN1B,THDN1C,THDN1468,FFTdB2(1:80001),S2N2,THD2,THDN2,THDN2A,THDN2B,THDN2C,THDN2468,f1,f2,filename) end end end end C.2 Code for PlotLog.m function []=plotlog(fftdB,S2N,THD,THDN,THDNA,THDNB,THDNC,THDN468,f1,f2,filename) HA='HorizontalAlignment';PPM='PaperPositionMode';m='manual'; PS='PaperSize';PP='PaperPosition';PSv=[8.5,11];PPv=[0.25 0.25 8 6.75]; TNR='Times New Roman';FS='FontSize';FN='FontName'; HA='HorizontalAlignment';set(gca,FN,TNR,FS,14); set(gcf,PPM,m,PS,PSv,PP,PPv); semilogx(fftdB,'k'); 126

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hold on;ylim([-160,20]);xlim([0,80000]);set(gca,'YTick',[-160:10:20]); set(gca,'YGrid','on');xlabel('Frequency (Hz)'); ylabel ('Output Energy 10*log(V ^2)'); text(1.2,16,['S/N'],FN,TNR,FS,14); text(7,16,num2str(S2N),FN,TNR,FS,14,HA,'right'); text(7.25,16,['dB'],FN,TNR,FS,14); text(1.2,6,['THD'],FN,TNR,FS,14); text(7,6,num2str(THD),FN,TNR,FS,14,HA,'right'); text(7.25,6,['dB'],FN,TNR,FS,14); text(1.2,-4,['THD+N'],FN,TNR,FS,14); text(7,-4,num2str(THDN),FN,TNR,FS,14,HA,'right'); text(7.25,-4,['dB'],FN,TNR,FS,14); text(1.2,-14,['THD+N'],FN,TNR,FS,14); text(7,-14,num2str(THDNA),FN,TNR,FS,14,HA,'right'); text(7.25,-15.25,['dB_A'],FN,TNR,FS,14); text(1.2,-24,['THD+N'],FN,TNR,FS,14); text(7,-24,num2str(THDNB),FN,TNR,FS,14,HA,'right'); text(7.25,-25.25,['dB_B'],FN,TNR,FS,14); text(1.2,-34,['THD+N'],FN,TNR,FS,14); text(7,-34,num2str(THDNC),FN,TNR,FS,14,HA,'right'); text(7.25,-35.25,['dB_C'],FN,TNR,FS,14); text(1.2,-44,['THD+N'],FN,TNR,FS,14); text(7,-44,num2str(THDN468),FN,TNR,FS,14,HA,'right'); text(7.25,-45.25,['dB_4_6_8'],FN,TNR,FS,14); T='Maximum Open Loop Output Power Spectrum with Input Tone of '; T2=['Hz' sprintf('\n') 'and a Supply Rippleof 10% at 4000Hz']; TITLE=[T,num2str(f1),T2]; TITLE2=[T,num2str(f1),'Hz and ',num2str(f2),T2]; if isempty(f2) title(TITLE,FN,TNR,FS,14) text((f1+1),fftdB(f1+1),['\leftarrow ' num2str(ceil(fftdB(f1+1))) 'dB'],... HA,'left',FN,TNR,FS,14) end if ~isempty(f2) abs(fftdB(f1+1)-fftdB(f2+1))<25 title(TITLE2,FN,TNR,FS,14) text((f1+1),fftdB(f1+1),[num2str(ceil(fftdB(f1+1))) 'dB ' '\rightarrow' ],... HA,'right',FN,TNR,FS,14) text((f2+1),fftdB(f2+1),['\leftarrow ' num2str(ceil(fftdB(f2+1))) 'dB'],... HA,'left',FN,TNR,FS,14) end extention=find(filename=='.');filename(extention+1:size(filename,2))='emf'; saveas(gca,filename,'emf');hold off; 127

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C.3 Code for PlotLog2.m function []=plotlog(fftdB,S2N,THD,THDN,THDNA,THDNB,THDNC,THDN468,fftdB2,S2N2,THD2,THDN2,THDNA2,THDNB2,THDNC2,THDN4682,f1,f2,filename) TNR='Times New Roman';FS='FontSize';FN='FontName'; HA='HorizontalAlignment';PPM='PaperPositionMode';m='manual'; PS='PaperSize';PP='PaperPosition';PSv=[8.5,14];PPv=[0.25 0.25 8 11]; set(gca,FN,TNR,FS,14)SUBPLOT(2,1,1);set(gca,FN,TNR,FS,14); set(gcf,PPM,m,PS,PSv,PP,PPv);semilogx(fftdB,'k'); set(gca,FN,TNR,FS,14);ylim([-140,20]);xlim([0,80000]); set(gca,'YTick',[-140:20:20]);set(gca,'YGrid','on'); xlabel('Frequency (Hz)');ylabel ('Output Energy 10*log(V ^2)'); text(1.2,16,['S/N'],FN,TNR,FS,14); text(7,16,num2str(S2N),FN,TNR,FS,14,HA,'right'); text(7.25,16,['dB'],FN,TNR,FS,14); text(1.2,6,['THD'],FN,TNR,FS,14); text(7,6,num2str(THD),FN,TNR,FS,14,HA,'right'); text(7.25,6,['dB'],FN,TNR,FS,14); text(1.2,-4,['THD+N'],FN,TNR,FS,14); text(7,-4,num2str(THDN),FN,TNR,FS,14,HA,'right'); text(7.25,-4,['dB'],FN,TNR,FS,14); text(1.2,-14,['THD+N'],FN,TNR,FS,14); text(7,-14,num2str(THDNA),FN,TNR,FS,14,HA,'right'); text(7.25,-15.25,['dB_A'],FN,TNR,FS,14); text(1.2,-24,['THD+N'],FN,TNR,FS,14); text(7,-24,num2str(THDNB),FN,TNR,FS,14,HA,'right'); text(7.25,-25.25,['dB_B'],FN,TNR,FS,14); text(1.2,-34,['THD+N'],FN,TNR,FS,14); text(7,-34,num2str(THDNC),FN,TNR,FS,14,HA,'right'); text(7.25,-35.25,['dB_C'],FN,TNR,FS,14); text(1.2,-44,['THD+N'],FN,TNR,FS,14); text(7,-44,num2str(THDN468),FN,TNR,FS,14,HA,'right'); text(7.25,-45.25,['dB_4_6_8'],FN,TNR,FS,14); T='Maximum Stable Output Power Spectrum Vs Frequency with Input Tone of '; if isempty(f2);title([T,num2str(f1),'Hz'],FN,TNR,FS,14); text((f1+1),fftdB(f1+1),['\leftarrow ' num2str(ceil(fftdB(f1+1))) 'dB'],... HA,'left',FN,TNR,FS,14);end if ~isempty(f2) title([T,num2str(f1),'Hz and ',num2str(f2),'Hz'],FN,TNR,FS,14) text((f1+1),fftdB(f1+1),[num2str(ceil(fftdB(f1+1))) 'dB ' '\rightarrow' ],... HA,'right',FN,TNR,FS,14) text((f2+1),fftdB(f2+1),['\leftarrow ' num2str(ceil(fftdB(f2+1))) 'dB'],... HA,'left',FN,TNR,FS,14);end SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(fftdB2,'k'); set(gca,FN,TNR,FS,14);ylim([-140,20]);xlim([0,80000]); set(gca,'YTick',[-140:20:20]);set(gca,'YGrid','on'); 128

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xlabel('Frequency (Hz)');ylabel ('Output Energy 10*log(V ^2)'); text(1.2,16,['S/N'],FN,TNR,FS,14); text(7,16,num2str(S2N2),FN,TNR,FS,14,HA,'right'); text(7.25,16,['dB'],FN,TNR,FS,14); text(1.2,6,['THD'],FN,TNR,FS,14); text(7,6,num2str(THD2),FN,TNR,FS,14,HA,'right') text(7.25,6,['dB'],FN,TNR,FS,14); text(1.2,-4,['THD+N'],FN,TNR,FS,14); text(7,-4,num2str(THDN2),FN,TNR,FS,14,HA,'right'); text(7.25,-4,['dB'],FN,TNR,FS,14); text(1.2,-14,['THD+N'],FN,TNR,FS,14); text(7,-14,num2str(THDNA2),FN,TNR,FS,14,HA,'right'); text(7.25,-15.25,['dB_A'],FN,TNR,FS,14); text(1.2,-24,['THD+N'],FN,TNR,FS,14); text(7,-24,num2str(THDNB2),FN,TNR,FS,14,HA,'right'); text(7.25,-25.25,['dB_B'],FN,TNR,FS,14); text(1.2,-34,['THD+N'],FN,TNR,FS,14); text(7,-34,num2str(THDNC2),FN,TNR,FS,14,HA,'right'); text(7.25,-35.25,['dB_C'],FN,TNR,FS,14); text(1.2,-44,['THD+N'],FN,TNR,FS,14); text(7,-44,num2str(THDN4682),FN,TNR,FS,14,HA,'right'); text(7.25,-45.25,['dB_4_6_8'],FN,TNR,FS,14); T2='Ref''s Power Spectrum vs Frequency with Input Tone of '; if isempty(f2) title([T2,num2str(f1),'Hz'],FN,TNR,FS,14); text((f1+1),fftdB2(f1+1),['\leftarrow ' num2str(ceil(fftdB2(f1+1))) 'dB'],... HA,'left',FN,TNR,FS,14);end if ~isempty(f2) title([T2,num2str(f1),'Hz and ',num2str(f2),'Hz'],FN,TNR,FS,14) text((f1+1),fftdB2(f1+1),[num2str(ceil(fftdB(f1+1))) 'dB ' '\rightarrow' ],... HA,'right',FN,TNR,FS,14) text((f2+1),fftdB2(f2+1),['\leftarrow ' num2str(ceil(fftdB2(f2+1))) 'dB'],... HA,'left',FN,TNR,FS,14);end extention=find(filename=='.'); filename(extention+1:size(filename,2))='emf'; saveas(gca,filename,'emf');hold off C.4 Code for IsHarmonic.m function [Harm]=IsHarmonic(Freq,f) Int=(Freq-1)/f; Harm=(~(Int-floor(Int))&(Int>0)); Harm=Freq(Harm); C.5 Code for THD.m function [THD]=THD(FFTdata,FFTdB,f1,f2,NF) Freq=find(FFTdB>NF);Harm=IsHarmonic(Freq,f1); Harm=[IsHarmonic(Freq-f1,f1);Harm]; 129

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if ~isempty(f2);Harm=[IsHarmonic(Freq,f2);Harm]; Harm=[IsHarmonic(Freq,(f1+f2));Harm]; Harm=[IsHarmonic(Freq,abs(f1-f2));Harm]; Harm=[IsHarmonic(Freq-f1,f2);Harm]; Harm=[IsHarmonic(Freq-f1,(f1+f2));Harm]; Harm=[IsHarmonic(Freq-f1,abs(f1-f2));Harm]; Harm=[IsHarmonic(Freq-f2,f1);Harm]; Harm=[IsHarmonic(Freq-f2,f2);Harm]; Harm=[IsHarmonic(Freq-f2,(f1+f2));Harm]; Harm=[IsHarmonic(Freq-f2,abs(f1-f2));Harm]; end Harm=sort(Harm);HarmT=Harm;HarmT(1,:)=[];HarmT(size(Harm))=Harm(1,1); HarmI=~(~(Harm-HarmT));HarmS=Harm(HarmI); signal=HarmS(find(HarmS==f1+1)); HarmS(find(HarmS==f1+1))=[]; if ~isempty(f2);signal(2)=HarmS(find(HarmS==f2+1)); HarmS(find(HarmS==f2+1))=[]; end THD=abs(FFTdata(HarmS)).*abs(FFTdata(HarmS));THD=sum(abs(THD)); THD=10*log10(THD); C.6 Code for THDN.m function [THDN]=THDN(FFTdata,f1,f2) index=2:size(FFTdata,1);index(find(index==(f1+1)))=[];signal=[f1+1]; if ~isempty(f2);index(find(index==(f2+1)))=[];signal=[signal,f2+1]; end; THDN=abs(FFTdata(index)).*abs(FFTdata(index));THDN=sum(THDN); THDN=10*log10(THDN); C.7 Code for MakeWave.m function []=makewav(f) fs=215000;usr=40; if size(f)<2; singleTone=1;else;f1=f(1);f2=f(2);singleTone=0;end t=1/fs:1/fs:1/fbin*usr; if singleTone==1;y=0.9*sin(2*pi*f*t); else;y=0.45*(sin(2*pi*f1*t)+sin(2*pi*f2*t));end; y=y';f=num2str(f);wavwrite(y,fs,16,['C:\print\',f,'2.wav']); C.8 Code for Nyquist_Bode.m f=logspace(1,8,701);wn=2*pi*f; Qm=0.5;fpm=5060;fzm=331988;wpm=fpm*2*pi;wzm=fzm*2*pi;gainm=-10; Hm=tf([wzm^-1 1]*gainm,[wpm^-2 1/Qm/wpm 1]);[MagHm PHm]=bode(Hm,wn); MagHm2=[];MagHm2(1,:)=MagHm(1,1,:);dBHm=20*log10(MagHm2);pHm=[]; pHm(1,:)=PHm(1,1,:);TNR='Times New Roman';FS='FontSize';FN='FontName'; 130

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PSv=[8.5,14];PPv=[0.25 0.25 8 11];PPM='PaperPositionMode';m='manual'; PS='PaperSize';PP='PaperPosition'; SUBPLOT(2,1,1);set(gca,FN,TNR,FS,14);set(gcf,PPM,m,PS,PSv,PP,PPv); semilogx(f,dBHm,'k');xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14); title('Magnitude of H_M(s) vs Frequency',FN,TNR,FS,14);grid; ylim([-80,40]);xlim([0,1000000]);set(gca,'YTick',[-80:20:40]); hold off; SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(f,pHm,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Phase (degree)',FN,TNR,FS,14) title('Phase of H_M(s) vs Frequency',FN,TNR,FS,14);grid;ylim([0,200]); xlim([0,1000000]);set(gca,'YTick',[0:45:180]);hold off; filename=[dir 'Hm.emf'];saveas(gca,filename,'emf'); %Active HE(s) Qe=1.003;fpe=20120;fze=323881;wpe=fpe*2*pi;wze=fze*2*pi;gaine=-10; He=tf([wze^-1 1]*gaine,[wpe^-2 1/Qe/wpe 1]);[MagHe PHe]=bode(He,wn); MagHe2=[];MagHe2(1,:)=MagHe(1,1,:);dBHe=20*log10(MagHe2);pHe=[]; pHe(1,:)=PHe(1,1,:);SUBPLOT(2,1,1);set(gca,FN,TNR,FS,14); set(gcf,PPM,m,PS,PSv,PP,PPv);semilogx(f,dBHe,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14); title('Magnitude of H_E(s) vs Frequency',FN,TNR,FS,14);grid; ylim([-40,40]);xlim([0,1000000]);set(gca,'YTick',[-40:20:40]); hold off;SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(f,pHe,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Phase (degree)',FN,TNR,FS,14); title('Phase of H_E(s) vs Frequency',FN,TNR,FS,14);grid;ylim([0,200]); xlim([0,1000000]);set(gca,'YTick',[0:45:180]);hold off; filename=[dir 'He.emf'];saveas(gca,filename,'emf'); % Active Hlpf(s) Qlpf=.98;fplpf=19664;fzlpf=33863000;wplpf=fplpf*2*pi;wzlpf=fzlpf*2*pi; gainlpf=-1.6/1.8; Hlpf=tf([wzlpf^-1 1]*gainlpf,[wplpf^-2 1/Qlpf/wplpf 1]); [MagHlpf PHlpf]=bode(Hlpf,wn);MagHlpf2=[]; MagHlpf2(1,:)=MagHlpf(1,1,:);dBHlpf=20*log10(MagHlpf2);pHlpf=[]; pHlpf(1,:)=PHlpf(1,1,:);SUBPLOT(2,1,1);set(gca,FN,TNR,FS,14); set(gcf,PPM,m,PS,PSv,PP,PPv); semilogx(f,dBHlpf,'k');xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14); title('Magnitude of H_L_P_F(s) vs Frequency',FN,TNR,FS,14);grid; ylim([-80,20]);xlim([0,1000000]);set(gca,'YTick',[-80:20:20]); hold off;SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(f,pHlpf,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Phase (degree)',FN,TNR,FS,14); T='Phase of H_L_P_F(s) vs Frequency'; 131

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title(T,FN,TNR,FS,14);grid;ylim([0,200]); xlim([0,1000000]);et(gca,'YTick',[0:45:180]);hold off; filename=[dir 'Hlpf.emf'];saveas(gca,filename,'emf'); %Passive HLPF QLPF=1.03;fpLPF=19244;fzLPF=27922000;wpLPF=fpLPF*2*pi; wzLPF=fzLPF*2*pi;gainLPF=0.905; HLPF=tf([wzLPF^-1 1]*gainLPF,[wpLPF^-2 1/QLPF/wpLPF 1]); [MagHLPF PHLPF]=bode(HLPF,wn);MagHLPF2=[]; MagHLPF2(1,:)=MagHLPF(1,1,:);dBHLPF=20*log10(MagHLPF2);pHLPF=[]; pHLPF(1,:)=PHLPF(1,1,:);SUBPLOT(2,1,1);set(gca,FN,TNR,FS,14); set(gcf,PPM,m,PS,PSv,PP,PPv); semilogx(f,dBHLPF,'k');xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14); title('Magnitude of LPF(s) vs Frequency',FN,TNR,FS,14);grid; ylim([-80,20]);xlim([0,1000000]);set(gca,'YTick',[-80:20:20]); hold off;SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(f,pHLPF,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Phase (degree)',FN,TNR,FS,14); title('Phase of LPF(s) vs Frequency',FN,TNR,FS,14);grid; ylim([-200,10]);xlim([0,1000000]);set(gca,'YTick',[-180:45:0]); hold off;filename=[dir 'LPF.emf'];saveas(gca,filename,'emf'); %Active Hc(s) gainc=-10;Hc=tf(1,[1],'Inputdelay',60e-9);[MagHc PHc]=bode(Hc,wn); MagHc2=[];MagHc2(1,:)=MagHc(1,1,:);dBHc=20*log10(MagHc2);pHc=[]; pHc(1,:)=PHc(1,1,:);SUBPLOT(2,1,1);set(gca,FN,TNR,FS,14); set(gcf,PPM,m,PS,PSv,PP,PPv);semilogx(f,dBHc,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14); title('Magnitude of H_C(s) vs Frequency',FN,TNR,FS,14);grid; ylim([0,40]);xlim([0,1000000]);set(gca,'YTick',[0:20:40]);hold off; SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(f,pHc,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Phase (degree)',FN,TNR,FS,14); title('Phase of H_C(s) vs Frequency',FN,TNR,FS,14);grid;ylim([0,200]); xlim([0,1000000]);set(gca,'YTick',[0:45:180]);hold off; filename=[dir 'Hc.emf'];saveas(gca,filename,'emf'); %Loop Gain equation HeLPF=series(He,HLPF);HmHeHLPF=parallel(Hm,HeLPF);L=(HmHeHLPF*Hc); L=L*-629.19;unit=tf([1],[1]);RR=((HLPF)/(unit+L/Hc)); [MagL PL]=bode(L,wn);MagL2=[];MagL2(1,:)=MagL(1,1,:); dBL=20*log10(MagL2);pL=[];pL(1,:)=PL(1,1,:);SUBPLOT(2,1,1); set(gca,FN,TNR,FS,14);set(gcf,PPM,m,PS,PSv,PP,PPv); semilogx(f,dBL,'k');xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14); title('Magnitude of T(s) vs Frequency',FN,TNR,FS,14);grid; ylim([-20,100]);xlim([0,1000000]);set(gca,'YTick',[-20:20:100]); 132

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hold off;SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(f,pL,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Phase (degree)',FN,TNR,FS,14); title('Phase of T(s) vs Frequency',FN,TNR,FS,14);grid; ylim([-300,10]);xlim([0,1000000]);set(gca,'YTick',[-270:45:0]); hold off;filename=[dir 'L.emf'];saveas(gca,filename,'emf'); %Nyquist Plot newplot;set(gca,FN,TNR,FS,14);Nyquist(L,'k');set(gca,FN,TNR,FS,14); xlabel('Real Axis',FN,TNR,FS,14); ylabel('Imaginary Axis',FN,TNR,FS,14); title('Nyquist Plot of Loop Gain, T(s)',FN,TNR,FS,14); filename=[dir 'Nyquist1.emf'];saveas(gca,filename,'emf'); ylim([-2000,2000]);xlim([-2400,300]);filename=[dir 'Nyquist2.emf']; saveas(gca,filename,'emf') ylim([-200,200]);xlim([-40,40]);filename=[dir 'Nyquist3.emf']; saveas(gca,filename,'emf'); ylim([-20,20]);xlim([-12,3]);filename=[dir 'Nyquist4.emf']; %Ripple Rejection saveas(gca,filename,'emf'); set(gca,FN,TNR,FS,14);[MagRR PRR]=bode(RR,wn); MagRR2=[];MagRR2(1,:)=MagRR(1,1,:);dBRR=20*log10(MagRR2); semilogx(f,dBRR,'k');set(gca,FN,TNR,FS,14); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14); title('System Response vs Frequency',FN,TNR,FS,14);grid; ylim([-100,00]);xlim([0,1000000]);set(gca,'YTick',[-100:20:0]); filename=[dir 'RR.emf'];saveas(gca,filename,'emf'); %System Response SFR=RR*L;set(gca,FN,TNR,FS,14);[MagSFR PSFR]=bode(SFR,wn);MagSFR2=[]; MagSFR2(1,:)=MagSFR(1,1,:);dBSFR=20*log10(MagSFR2); semilogx(f,dBSFR,'k');set(gca,FN,TNR,FS,14); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14); title('System Response vs Frequency',FN,TNR,FS,14);grid; ylim([-80,20]);xlim([0,1000000]);set(gca,'YTick',[-80:20:20]); filename=[dir 'SFR.emf'];saveas(gca,filename,'emf'); C.9 Code for NetworkAnalyzer.m dir='C:\Documents and Settings\Jason\My Documents\Thesis\Data\'; Hm=load([dir 'hm.dat']);dBHm=Hm(:,2)';pHm=Hm(:,3)';f=Hm(:,1)'; TNR='Times New Roman';FS='FontSize';FN='FontName'; PPM='PaperPositionMode';m='manual';PS='PaperSize';PP='PaperPosition'; SUBPLOT(2,1,1);set(gca,FN,TNR,FS,14);PSv=[8.5,14];PPv=[0.25 0.25 8 11]; set(gcf,PPM,m,PS,PSv,PP,PPv); semilogx(f,dBHm,'k');xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14);T='Magnitude of H_M(s) vs Frequency'; 133

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title(T,FN,TNR,FS,14);grid;ylim([-80,40]);xlim([0,1000000]); set(gca,'YTick',[-80:20:40]);hold off; SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(f,pHm,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14);ylabel('Phase (degree)',FN,TNR,FS,14); title('Phase of H_M(s) vs Frequency',FN,TNR,FS,14);grid;ylim([0,200]); xlim([0,1000000]);set(gca,'YTick',[0:45:180]);hold off;filename=[dir 'Hm.emf']; saveas(gca,filename,'emf'); %Active HE(s) He=load([dir 'he.dat']); dBHe=He(:,2)';pHe=He(:,3)';f=He(:,1)';SUBPLOT(2,1,1);set(gca,FN,TNR,FS,14); set(gcf,PPM,m,PS,PSv,PP,PPv);semilogx(f,dBHe,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14);ylabel('Magnitude (dB)',FN,TNR,FS,14); title('Magnitude of H_E(s) vs Frequency',FN,TNR,FS,14);grid;ylim([-40,40]); xlim([0,1000000]);set(gca,'YTick',[-40:20:40]);hold off SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(f,pHe,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14);ylabel('Phase (degree)',FN,TNR,FS,14); title('Phase of H_E(s) vs Frequency',FN,TNR,FS,14);grid;ylim([0,200]); xlim([0,1000000]);set(gca,'YTick',[0:45:180]);hold off;filename=[dir 'He.emf']; saveas(gca,filename,'emf'); % Active Hlpf(s) Hlpf=load([dir 'hlpf.dat']);dBHlpf=Hlpf(:,2)';pHlpf=Hlpf(:,3)';f=Hlpf(:,1)'; SUBPLOT(2,1,1);set(gca,FN,TNR,FS,14);set(gcf,PPM,m,PS,PSv,PP,PPv); semilogx(f,dBHlpf,'k');xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14);T='Magnitude of H_L_P_F(s) vs Frequency'; title(T,FN,TNR,FS,14);grid;ylim([-80,20]);xlim([0,1000000]); set(gca,'YTick',[-80:20:20]);hold off; SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(f,pHlpf,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14);ylabel('Phase (degree)',FN,TNR,FS,14); title('Phase of H_L_P_F(s) vs Frequency',FN,TNR,FS,14);grid;ylim([0,200]); xlim([0,1000000]);set(gca,'YTick',[0:45:180]);hold off;filename=[dir 'Hlpf.emf']; saveas(gca,filename,'emf'); %Passive HLPF HLPF=load([dir 'LPF3.dat']);dBHLPF=HLPF(:,2)';pHLPF=HLPF(:,3)'; f=HLPF(:,1)';SUBPLOT(2,1,1);set(gca,FN,TNR,FS,14); set(gcf,PPM,m,PS,PSv,PP,PPv);semilogx(f,dBHLPF,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14); title('Magnitude of LPF(s) vs Frequency',FN,TNR,FS,14);grid; ylim([-80,20]);xlim([0,1000000]);set(gca,'YTick',[-80:20:20]); hold off; SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(f,pHLPF,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Phase (degree)',FN,TNR,FS,14); title('Phase of LPF(s) vs Frequency',FN,TNR,FS,14);grid; ylim([-200,10]);xlim([0,1000000]);set(gca,'YTick',[-180:45:0]); hold off;filename=[dir 'LPF.emf'];saveas(gca,filename,'emf'); 134

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%Active Hc(s) Hc=load([dir 'hc.dat']);dBHc=Hc(:,2)';pHc=Hc(:,3)';f=Hc(:,1)'; SUBPLOT(2,1,1);set(gca,FN,TNR,FS,14);set(gcf,PPM,m,PS,PSv,PP,PPv); semilogx(f,dBHc,'k');xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Magnitude (dB)',FN,TNR,FS,14); title('Magnitude of H_C(s) vs Frequency',FN,TNR,FS,14);grid; ylim([0,40]);xlim([0,1000000]);set(gca,'YTick',[0:20:40]); hold off;SUBPLOT(2,1,2);set(gca,FN,TNR,FS,14);semilogx(f,pHc,'k'); xlabel('Frequency (Hz)',FN,TNR,FS,14); ylabel('Phase (degree)',FN,TNR,FS,14); title('Phase of H_C(s) vs Frequency',FN,TNR,FS,14);grid; ylim([0,200]);xlim([0,1000000]);set(gca,'YTick',[0:45:180]);hold off; filename=[dir 'Hc.emf'];saveas(gca,filename,'emf'); C.10 Code for NetworAnalyzer2.m dir='C:\Documents and Settings\Jason\My Documents\Thesis\Data\Final\network\' psrr_c=load([dir 'psrr_c.dat']);psrr_d=load([dir 'psrr_d.dat']); fr=load([dir 'fr.dat');TNR='Times New Roman';FS='FontSize'; FN='FontName'; semilogx(psrr_c(:,1)',psrr_c(:,2)','k-'); set(gca,FN,TNR,FS,12);xlabel('Frequency (Hz)',FN,TNR,FS,12) ylabel('Output Rejection (dB)',FN,TNR,FS,12); T='Power Supply Rejection Ratio With Common Mode Ripple on Supplies'; title(T,FN,TNR,FS,12);grid;filename=[dir 'psrr_c.emf']; saveas(gca,filename,'emf') semilogx(psrr_d(:,1)',psrr_d(:,2)','k-'); set(gca,FN,TNR,FS,12); xlabel('Frequency (Hz)',FN,TNR,FS,12); ylabel('Output Rejection (dB)',FN,TNR,FS,12); title(T,FN,TNR,FS,12);grid;filename=[dir 'psrr_d.emf']; saveas(gca,filename,'emf') semilogx(fr(:,1)',fr(:,2)','k-'); set(gca,FN,TNR,FS,12);xlabel('Frequency (Hz)',FN,TNR,FS,12) ylabel('Voltage (dB)',FN,TNR,FS,12); title('System Response',FN,TNR,FS,12) grid; filename=[dir 'fr.emf'];saveas(gca,filename,'emf') ylim([-9 9]);set(gca,'YTick',[-9:3:9]);filename=[dir 'frZoom.emf']; saveas(gca,filename,'emf'); C.11 Code for Scope.m dir='C:\Documents and Settings\Jason\My Documents\Thesis\Data\Final\dataScope\'; vd=load([dir 'vd.dat']);vs=load([dir 'vs.dat']); out=load([dir 'out.dat']);error=load([dir 'error.dat']); phase=load([dir 'phase.dat']);TNR='Times New Roman';FS='FontSize'; FN='FontName';set(gca,FN,TNR,FS,12); plot(vd(:,1)',vd(:,2)','k:',vs(:,1)',vs(:,2)','k-.',out(:,1)',out(:,2)','k-'); 135

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set(gca,FN,TNR,FS,12);xlabel('Time(s)',FN,TNR,FS,12); ylabel('Voltage (V)',FN,TNR,FS,12); T='Ouput of Amplifier With Control Circuit and 4kHz Ripple on Supply'; title(T,FN,TNR,FS,12);grid;filename=[dir 'out.emf']; saveas(gca,filename,'emf'); plot(error(:,1)',error(:,2)','k-');set(gca,FN,TNR,FS,12); xlabel('Time(s)',FN,TNR,FS,12);ylabel('Voltage (V)',FN,TNR,FS,12); T='Error Signal With Control Circuit and 4kHz Ripple on Supply'; title(T,FN,TNR,FS,12); grid;filename=[dir 'error.emf'];saveas(gca,filename,'emf'); plot(phase(:,1)',phase(:,2)','k-');set(gca,FN,TNR,FS,12); xlabel('Time(s)',FN,TNR,FS,12);ylabel('Voltage (V)',FN,TNR,FS,12); T='Phase Node With Control Circuit and 4kHz Ripple on Supply'; title(T,FN,TNR,FS,12);grid;xlim([-2e-6,2e-6]); filename=[dir 'phase.emf'];saveas(gca,filename,'emf'); C.12 Code for Scope2.m dir='C:\Documents and Settings\Jason\My Documents\Thesis\New data\'; vd=load([dir 'vd.dat']);vs=load([dir 'vs.dat']); out=load([dir 'outwo.dat']);error=load([dir 'error.txt']); phase=load([dir 'phase.txt']); TNR='Times New Roman';FS='FontSize'; FN='FontName';set(gca,FN,TNR,FS,12); plot(vd(:,1)',vd(:,2)','k:',vs(:,1)',vs(:,2)','k-.',out(:,1)',out(:,2)','k-'); set(gca,FN,TNR,FS,12);xlabel('Time(s)',FN,TNR,FS,12); ylabel('Voltage (V)',FN,TNR,FS,12); T='Open Loop Ouput of Amplifier With 4kHz Ripple on Supply'; title(T,FN,TNR,FS,12);grid filename=[dir 'outwo.emf'];saveas(gca,filename,'emf') plot(error(:,1)',error(:,2)','k-');set(gca,FN,TNR,FS,12); xlabel('Time(s)',FN,TNR,FS,12);ylabel('Voltage (V)',FN,TNR,FS,12); T='Error Signal With Control Circuit and 4kHz Ripple on Supply'; title(T,FN,TNR,FS,12);grid;xlim([46e-6,50e-6]); filename=[dir 'error.emf'];saveas(gca,filename,'emf'); plot(phase(:,1)',phase(:,2)','k-');set(gca,FN,TNR,FS,12); xlabel('Time(s)',FN,TNR,FS,12);ylabel('Voltage (V)',FN,TNR,FS,12); T='Phase Node With Control Circuit and 4kHz Ripple on Supply'; title(T,FN,TNR,FS,12); grid;xlim([46e-6,50e-6]);filename=[dir 'phase.emf']; saveas(gca,filename,'emf'); C.13 Code for Saber.m dir='C:\Documents and Settings\Jason\My Documents\Thesis\Data\Final\saber\'; TNR='Times New Roman';FS='FontSize';FN='FontName';xl='Frequency (Hz)'; error=load([dir 'error.txt']);he=load([dir 'he.txt']); 136

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hm=load([dir 'hm.txt']);out=load([dir 'out.txt']); outDigitalFFT=load([dir 'outDigitalFFT.txt']); outFFT=load([dir 'outFFT.txt']);outwo=load([dir 'outwo.txt']); outwoFFT=load([dir 'outwoFFT.txt']);phase=load([dir 'phase.txt']); phaseFFT=load([dir 'phaseFFT.txt']);vd=load([dir 'vdd.txt']); vs=load([dir 'vs.txt']);set(gca,FN,TNR,FS,12); plot(vd(:,1)',vd(:,2)','k:',vs(:,1)',vs(:,2)','k-.',out(:,1)',out(:,2)','k-'); set(gca,FN,TNR,FS,12);xlabel('Time(s)',FN,TNR,FS,12); ylabel('Voltage (V)',FN,TNR,FS,12); T='Ouput of Amplifier With Control Circuit and 4kHz Ripple on Supply'; title(T,FN,TNR,FS,12);grid;filename=[dir 'out.emf']; saveas(gca,filename,'emf'); plot(vd(:,1)',vd(:,2)','k:',vs(:,1)',vs(:,2)','k-.',outwo(:,1)',outwo(:,2)','k-'); set(gca,FN,TNR,FS,12);xlabel('Time(s)',FN,TNR,FS,12); ylabel('Voltage (V)',FN,TNR,FS,12) T2='Ouput of Amplifier Without Control Circuit and 4kHz Ripple on Supply'; title(T2,FN,TNR,FS,12);grid;filename=[dir 'outwo.emf']; saveas(gca,filename,'emf'); semilogx(outFFT(:,1)',20*log10(abs(outFFT(:,2)')),'k'); set(gca,FN,TNR,FS,12)' xlabel(xl,FN,TNR,FS,12); ylabel('Voltage (dB)',FN,TNR,FS,12); T3='FFT of Ouput of Amplifier With Control Circuit and 4kHz Ripple on Supply'; title(T3,FN,TNR,FS,12);grid;xlim([250,80000]);ylim([-160,20]); filename=[dir 'outFFT.emf'];saveas(gca,filename,'emf'); semilogx(outwoFFT(:,1)',20*log10(abs(outwoFFT(:,2)')),'k'); set(gca,FN,TNR,FS,12); xlabel(xl,FN,TNR,FS,12);ylabel('Voltage (dB)',FN,TNR,FS,12); T4='FFT of Ouput of Amplifier Without Control Circuit and 4kHz Ripple on Supply'; title(T4,FN,TNR,FS,12);grid;xlim([250,80000]);ylim([-160,20]); filename=[dir 'outwoFFT.emf'];saveas(gca,filename,'emf'); plot(phase(:,1)',phase(:,2)','k');set(gca,FN,TNR,FS,12); xlabel('Time(s)',FN,TNR,FS,12);ylabel('Voltage (V)',FN,TNR,FS,12); T5='Ouput of Amplifier Without Control Circuit and 4kHz Ripple on Supply'; title(T5,FN,TNR,FS,12);grid;filename=[dir 'phase.emf']; saveas(gca,filename,'emf'); plot(phaseFFT(:,1)',20*log10(abs(phaseFFT(:,2)')),'k'); set(gca,FN,TNR,FS,12); xlabel(xl,FN,TNR,FS,12);ylabel('Voltage (dB)',FN,TNR,FS,12); T6='FFT of Ouput of Amplifier With Control Circuit and 4kHz Ripple on Supply'; title(T6,FN,TNR,FS,12);grid;ylim([-60,20]); filename=[dir 'phaseFFT.emf']; saveas(gca,filename,'emf'); plot(hm(:,1)',hm(:,2)','k:',he(:,1)',he(:,2)','k-'); set(gca,FN,TNR,FS,12); xlabel('Time(s)',FN,TNR,FS,12);ylabel('Voltage (V)',FN,TNR,FS,12); 137

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title('Control Signals with 4kHz Ripple on Supply',FN,TNR,FS,12);grid; filename=[dir 'Loop.emf'];saveas(gca,filename,'emf'); plot(error(:,2)','k-');set(gca,FN,TNR,FS,12); xlabel('Time(s)',FN,TNR,FS,12);ylabel('Voltage (V)',FN,TNR,FS,12); T7='Ouput of Amplifier Without Control Circuit and 4kHz Ripple on Supply'; title(T7,FN,TNR,FS,12);grid;filename=[dir 'error.emf']; saveas(gca,filename,'emf'); 138

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APPENDIX D LOOP BACK EVALUTION OF SOUNDCARD AND MATLAB CODE The following graphs prove that the system of signal generation and signal digitations used is valid for the measurement need to be taken in this system. Figure D-1 to Figure D-7 show all the input signals used in the measurement process being looped back directly into the digitization input channel. 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N94dBTHD-107dBTHD+N-98dBTHD+N-104dBATHD+N-104dBBTHD+N-102dBCTHD+N-95dB468 Figure D-1. Loop Back Response for 20 Hz Single Tone 139

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140 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N93dBTHD-113dBTHD+N-98dBTHD+N-104dBATHD+N-103dBBTHD+N-101dBCTHD+N-95dB468 Figure D-2. Loop Back Response for 1 kHz Single Tone 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N91dBTHD-112dBTHD+N-97dBTHD+N-104dBATHD+N-103dBBTHD+N-101dBCTHD+N-95dB468 Figure D-3. Loop Back Response for 20 kHz Single Tone

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141 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N86dBTHD-122dBTHD+N-98dBTHD+N-104dBATHD+N-104dBBTHD+N-103dBCTHD+N-95dB468 Figure D-4. Loop Back Response for 60 Hz and 7 kHz SMPTE 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N102dBTHD-93dBTHD+N-90dBTHD+N-93dBATHD+N-95dBBTHD+N-95dBCTHD+N-83dB468 Figure D-5. Loop Back Response for 250 Hz and 8 kHz SMPTE

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142 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N89dBTHD-112dBTHD+N-98dBTHD+N-104dBATHD+N-103dBBTHD+N-102dBCTHD+N-95dB468 Figure D-6. Loop Back Response for 13 kHz and 14 kHz IMD-ITU-R 100 101 102 103 104 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency (Hz)Output Energy 10*log(V 2)S/N88dBTHD-109dBTHD+N-97dBTHD+N-104dBATHD+N-103dBBTHD+N-101dBCTHD+N-95dB468 Figure D-7. Loop Back Response for 19 kHz and 20 kHz IMD-ITU-R

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APPENDIX E BUFFER CIRCUIT SCHEMATIC AND LAYOUT Figure E-1 and Figure E-2 show the schematic for the buffer board. Figure E-3 and Figure E-4 show the layout for the top and bottom on the buffer board. AGND AGND AGND 50R4 0.1uC1CAP0805 AGND AGND 1 2 1 2 1 2 10uC2CAP1206 AGND R350k +15 AGND conn BANNANA -15 AGND AGND 50R1 -15 +15 3 7 5 4 6 1 4OPA541 +15 R550k gnd conn U3BNC R250k gnd conn U1BNC AGND -15 conn BANNANA 0.1uC3CAP0805 10uC4CAP1206 conn BANNANA 50kR6 conn BANNANA Figure E-1. Buffer Amplifier Schematic A 143

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144 AGND R1150k AGND -15 -15 50kR12 +15 gnd conn U6BNC gnd conn U8BNC R850k AGND R950k 0.1uC7CAP0805 AGND AGND 1 2 AGND +15 50R7 1 2 AGND AGND AGND 3 7 5 4 6 1 6OPA541 50R10 1 2 0.1uC5CAP0805 10uC6CAP1206 conn BANNANA 10uC8CAP1206 Figure E-2. Buffer Amplifier Schematic B Figure E-3. Buffer Amplifier Top Layer Layout

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145 Figure E-4. Buffer Amplifier Bottom Layer Layout

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LIST OF REFERENCES 1. Mohan, N., Robbins, W. P., Underland, T. M., Power Electronics: Converters applications and Design Second Edition , John Wiley & Sons, Inc; New York, 1995. 2. Lee, The Design of CMOS Radio Frequency Intergrated Circuits , Cambridge University Press, Cambridge, UK, 2002. 3. Chang, J.S., Li, B.H.G., “A digital Class D amplifier design embodying a novel sampling process and pulse generator.” The 2001 IEEE International Symposium on Circuits and Systems, May 2001, vol. 4, pp. 826-829. 4. Chang, J.S., Li, B.H.G., Lon, Y. S., Tan, M. T., “A novel low-power low-voltage Class D amplifier with feedback for improving THD, power efficiency and gain linearity.” The 2001 IEEE International Symposium on Circuits and Systems, May 2001, vol. 1, pp. 635-638. 5. Cho, B.H., Jeong, J,-H., Park, J,-H., Kim, C.G., “A novel controller for switching audio power amplifier with digital input,” IEEE 33rd Annual Power Electronics Specialists Conference, June 2002, vol. 1, pp. 39-44. 6. Dondon, P., Micouleau, J.M., “An original approach for the design of a Class D power switching amplifier-an audio application.” The 6th IEEE International Conference on Electronics, Circuits and Systems, 1999, vol. 1 Sept. 1999, pp. 161-164. 7. Fedyczak, Z ., Soza"ski, K., Strzelecki, R., “Digital Control Circuit for Class-D Audio Power Amplifier,” Power Electronics Specialists Conference, PESC'2001, Vancouver, BC, 2001, pp. 1245-1250. 8. Hawksford, M.O.J., Logan, S.,“Linearization of Class D output stages for high-performance audio power amplifiers,” Second International Conference on Advanced A-D and D-A Conversion Techniques and Their Applications, June 1994, pp. 136-141. 9. Kim, S., Lee, G.-S., Lee, J.-S., Lee, J.-W., “A 2 W BTL single-chip Class-D power amplifier with very high efficiency for audio applications,” The 2000 IEEE International Symposium on Circuits and Systems, 2000. May 2000, vol. 5, pp. 493-496. 146

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147 10. Krein, P.T., Midya, P., Pascual, C., Roeckner, W.J., Song, Z., Sarwate, D.V., “High-fidelity PWM inverter for digital audio amplification: Spectral analysis, real-time DSP implementation, and results,” IEEE Transactions on Power Electronics, vol. 18, Issue 1, Jan. 2003, pp. 473. 11. Lai, Z., Smedley, K.M., Smith, K.M., Jr., “A new PWM controller with one-cycle response,” IEEE Transactions on Power Electronics, Jan. 1999, vol. 14, issue 1, pp. 142. 12. Lin, C. Zhu, S., “Reducing distortion of audio class D (PWM) power amplifier by using feed-forward techniques,” The 2000 IEEE Asia-Pacific Conference on Circuits and Systems, Dec. 2000, pp. 630. 13. Nielsen, K., “PEDEC-a novel pulse referenced control method for high quality digital PWM switching power amplification,” PESC 98 Record. 29th Annual IEEE Power Electronics Specialists Conference, May 1998, vol. 1, pp. 200-207. 14. Bishop, R. H. Dorf, R. C., Modern Control Systems 7th ed. , Addison-Wesley Publishing Company, Reading, MA, 1995. 15. Gray, P. R., Hurst, P. J., Lewis, S. H., Meyer, R. G., Analysis and Design of Analog Integrated Circuits 4th ed. , John Wiley & Sons, Inc, New York; 2001. 16. Cho, B. H., Lee, F. C., “Measurement of Loop Gain with the Digital Modulator,” IEEE Power Electronics Specialists Conference, 1984 Record, pp. 363-373. 17. Sedra, A. S., Smith, K. C., Microelectronic Circuits , Oxford University Press, New York, 1991. 18. Vorprian, V., Fast Analytical Techniques for Electrical and Electronic Circuits, Cambridge University. Press, 2002.

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BIOGRAPHICAL SKETCH Jason Bullard received his Bachelor of Science degree in electrical and computer engineering from the University of Florida, Gainesville, FL, in 1997. He began his career with Texas Instruments in Dallas, developing integrated circuits for the wireless handset market. In 2001, Jason returned to the University of Florida to pursue sis Master of Science degree in electrical engineering. His interests are integrated circuit design, power electronics, and audio power amplifiers. 148