Citation
Design and Implementation of Mixed Mode Digital Pulse Width Modulator for a DC-DC Converter

Material Information

Title:
Design and Implementation of Mixed Mode Digital Pulse Width Modulator for a DC-DC Converter
Creator:
KANNAN, BHARATH BALAJI ( Author, Primary )
Copyright Date:
2008

Subjects

Subjects / Keywords:
Capacitors ( jstor )
Circuit diagrams ( jstor )
Circuit switching ( jstor )
Comparators ( jstor )
Electric potential ( jstor )
Latches ( jstor )
Modulated signal processing ( jstor )
Modulators ( jstor )
Pulse duration ( jstor )
Signals ( jstor )

Record Information

Source Institution:
University of Florida
Holding Location:
University of Florida
Rights Management:
Copyright Bharath Balaji Kannan. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Embargo Date:
6/1/2004
Resource Identifier:
53207050 ( OCLC )

Downloads

This item is only available as the following downloads:


Full Text

PAGE 1

DESIGN AND IMPLEMENTATION OF MI XED MODE DIGITAL PULSE WIDTH MODULATOR FOR A DC-DC CONVERTER By BHARATH BALAJI KANNAN A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE UNIVERSITY OF FLORIDA 2003

PAGE 2

Copyright 2003 by Bharath Balaji Kannan

PAGE 3

This document is dedicated to the Almighty God.

PAGE 4

ACKNOWLEDGMENTS I would like to thank my advisor, Dr. Khai D.T. Ngo for his constant encouragement and though provoking ideas that had helped me in this thesis work. I would also like to thank Dr. William R. Eisenstadt and Dr. Robert M. Fox for their suggestions and for being on my thesis committee. I take this opportunity to express my gratitude and appreciation to the College of Engineering, Anna University, India, for providing an ambient environment to study and learn. I would also like to thank my parents and friends for giving me the necessary impetus towards the development of this thesis work. iv

PAGE 5

TABLE OF CONTENTS Page ACKNOWLEDGMENTS.................................................................................................iv LIST OF TABLES...........................................................................................................viii LIST OF FIGURES...........................................................................................................ix ABSTRACT.....................................................................................................................xiv CHAPTER 1 INTRODUCTION........................................................................................................1 1.1 DC-DC Converter...................................................................................................1 1.1.1 Theory and Operation...................................................................................1 1.1.2 Types and Configuration..............................................................................3 1.2. Controller for DC-DC converter............................................................................5 1.3. Thesis Chapter Synopses.......................................................................................6 2 PWM CONTROLLERS...............................................................................................8 2.1. Ramp Based PWM Controller...............................................................................8 2.2. Digital PWM Controllers.....................................................................................10 2.2.1 Fast-Clocked Counter-Comparator Scheme...............................................10 2.2.2 Tapped Delay Line Based PWM................................................................12 2.2.3 Hybrid Fast-Clock-Counter/Tapped Delay Line........................................13 2.2.4 Digital PWM Control Using DSP..............................................................14 3 MIXED MODE DIGITAL PULSE WIDTH MODULATOR...................................16 3.1. Architecture of MMDPWM................................................................................16 3.1.1 Switching Time Period Range and Count Determination..........................19 3.1.2 Generation of Unit Timed Signal-tu...........................................................20 3.1.3 Generation of Ton Using Fast-Clock Approach..........................................23 3.2 Algorithm for Ton Generation...............................................................................24 4 HARDWARE IMPLEMENTATION OF MIXED MODE DIGITAL PULSE WIDTH MODULATOR............................................................................................27 4.1. Architectural Implementation..............................................................................27 v

PAGE 6

4.1.1 Current Source Selection Based on Switching Period...............................29 4.1.2 Count Generation Circuit Based on Switching Period...............................30 4.1.3 Current Sources for Generating Voltage Reference Levels.......................32 4.1.4 Triangle Wave Generator...........................................................................36 4.1.4.a Fully Differential Comparator..........................................................36 4.1.4.b S-R Latch..........................................................................................40 4.1.4.c Current Source Selection for the Capacitor Charging Circuit..........41 4.1.5 PWM Pulse Generation Circuit..................................................................49 4.2 Advantages of the Proposed Approach.................................................................62 5 TESTING AND ANALYSIS.....................................................................................63 5.1 Fabrication and Packaging of Triangle Wave Generator.....................................63 5.1.1 Inputs to the Triangle Wave Generator......................................................65 5.1.2 Outputs of the Triangle Wave generator....................................................65 5.2. Printed Circuit Board Design and Layout...........................................................65 5.3. Testing Procedures and Measured Outputs.........................................................66 5.3.1 Switching Period Range Selector...............................................................67 5.3.2 Set-Reset Latch...........................................................................................70 5.3.3 Fully Differential Comparator....................................................................72 5.3.4 Unit Time Signal Generation Circuit.........................................................73 5.4 Analysis of Test Results.......................................................................................81 5.4.1 Performance Analysis.................................................................................81 5.4.2 Power Consumption Analysis..................................................................102 6 CONCLUSION.........................................................................................................106 6.1 Summary.............................................................................................................106 6.2 Future Work........................................................................................................106 APPENDIX A LAYOUT AND PACKAGE SPECIFICATIONS....................................................108 Layouts.....................................................................................................................108 Switching Period Range Selector......................................................................108 Set –Reset Latch................................................................................................110 Fully Differential Comparator...........................................................................110 Capacitor Layout...............................................................................................112 Current Sources for Charging/Discharging the Capacitor.................................113 Unit-Time Signal Generation Circuit................................................................115 Package Specifications.............................................................................................116 B TEST BOARD LAYOUT AND SOFTWARE MODULES....................................118 Printed Circuit Board Layout....................................................................................118 Matlab Program Module for On-Time Algorithm....................................................119 vi

PAGE 7

LIST OF REFERENCES.................................................................................................122 BIOGRAPHICAL SKETCH...........................................................................................125 vii

PAGE 8

LIST OF TABLES Table page 3-1 Time period range and count selection....................................................................20 3-2 Binary current sources used in reference voltage level generation..........................21 3-3 Charging/discharging current for generating the unit timed signal corresponding to VPP......................................................................................................................22 3-4 Comparison of the various approaches for PWM signal generation........................26 4-1 Binary equivalent of NCOUNT corresponding to the selection inputs.........................30 4-2 Comparator outputs based on capacitor charging/discharging cycle.......................45 5-1 Wafer and package information...............................................................................63 5-2 Unit-time for various switching period ranges.........................................................81 5-3 Unit-time for various switching period ranges corresponding to charging of capacitor from VLOW to VHIGH...........................................................................82 5-4 Unit-time for various switching period ranges corresponding to discharging of capacitor from VHIGH to VLOW...........................................................................83 5-5 Unit-time for various switching period ranges from the S-input of the S-R latch (fabricated chip test results).....................................................................................84 5-6 Unit-time for various switching period ranges from the R-input of the S-R latch...85 5-7 Unit-time generated for various VPP using the modified circuit.............................97 5-8 Supply current for various switching period ranges...............................................103 A-1 Electrical characteristics of the 40-pin DIP............................................................117 B-1 OPA656 specifications...........................................................................................119 viii

PAGE 9

LIST OF FIGURES Figure page 1-1 DC-DC converter configuration with control circuitry..............................................2 1-2 The basic circuit of a Buck type DC-DC converter...................................................4 2-1 Pulse width modulator circuit....................................................................................8 2-2 Typical waveforms obtained using ramp based pulse width modulator....................9 2-3 Architecture of fast-clocked counter-comparator circuit.........................................11 2-4 Architecture of tapped delay-line PWM generation................................................12 2-5 Architecture of hybrid fast-clocked counter and tapped delay line PWM...............13 2-6 Architecture of digital PWM using digital signal processor....................................14 3-1 On-time generation for the PWM pulse signal.........................................................17 3-2 Block diagram of mixed mode digital pulse width modulator.................................18 3-3 Block diagram showing the major internal components of the mixed mode digital pulse width modulator .............................................................................................19 3-4 Block diagram of the current source selection circuit..............................................23 3-5 Triangle wave form and schematic representation of Ton generation......................24 4-1 Block diagram of the mixed mode digital pulse width modulator...........................28 4-2 Schematic of 4*16 decoder for the selection of current source (Ic) based on switching period range.............................................................................................29 4-3 Combinational logic circuit used in the generation of (NCOUNT)2............................31 4-4 Count generator output waveforms for various input combinations........................32 4-5 Schematic of binary weighted current sources for 512A to 32A.........................33 4-6 Schematic showing the binary current sources from 16A to 1A.........................34 ix

PAGE 10

4-7 VHIGH and VLOW voltage levels for a duty ratio of 46.875%..............................36 4-8 Schematic of the fully differential comparator........................................................38 4-9 Propagation delay (response time) of the fully differential comparator in comparing VHIGH with the voltage on the capacitor..............................................39 4-10 Propagation delay (response time) of the fully differential comparator in comparing VLOW with the voltage on the capacitor...............................................40 4-11 Set-reset latch using NAND gates............................................................................41 4-12 Schematic of charging/discharging current selection circuit...................................42 4-13 Schematic of the current source generation circuit for various switching period ranges with control inputs........................................................................................43 4-14 Schematic of the control circuit for triangle wave generator...................................44 4-15 Capacitor charge/discharge circuit...........................................................................45 4-16 Triangle wave with the various zones during charging/ discharging cycle.............46 4-17 Triangle wave generator output for d=46.875%......................................................47 4-18 Lower /upper comparator outputs and the charge/discharge signal.........................48 4-19 Block diagram of a 8*6 Baugh Wooley multiplier..................................................50 4-20 Schematic of CELL 2 used in Baugh-Wooley mulitplier........................................51 4-21 Schematic of CELL 3 used in Baugh Wooley multiplier.........................................51 4-22 Schematic of CELL 4 used in Baugh-Wooley multiplier........................................52 4-23 Schematic of CELL 5 used in Baugh-Wooley multiplier........................................52 4-24 Schematic of full adder used in Baugh-Wooley multiplier......................................53 4-25 Output of the 8*6 Baugh Wooley multiplier for a switching period of 2s and duty ratio of 46.875%...............................................................................................54 4-26 Fast clock generated for a duty cycle of d=46.875% and switching period of 2s.56 4-27 Block diagram of the four stages of a 10-bit counter...............................................57 4-28 Block diagram of the three stages of a 10-bit digital comparator............................59 x

PAGE 11

4-29 10-bit counter output for a switching frequency of 500 kHz and duty ratio d =46.875%..............................................................................................................60 4-30 PWM pulse signal from the mixed mode digital pulse width modulator.................61 5-1 Floor plan of the triangle wave generator................................................................64 5-2 Printed circuit board for testing the triangle wave generator...................................66 5-3 Cadence simulation results for the switching period range selector........................68 5-4 Switching period range selector outputs-DECF0 and DECF1.................................69 5-5 Switching period range selector outputs-DECF3 and DECF2.................................69 5-6 Switching period range selector output-DECF4......................................................70 5-7 Set-reset latch outputs..............................................................................................71 5-8 Set-reset latch outputs..............................................................................................71 5-9 Fully differential comparator response time............................................................72 5-10 Comparator response time........................................................................................73 5-11 Triangle wave generator output –unit-timed signal generation...............................74 5-12 VPP obtained for 96.875%.......................................................................................74 5-13 Unit-time obtained during the charging interval from VLOW to VHIGH..............75 5-14 Unit-time obtained during the charging interval from VHIGH to VLOW..............75 5-15 Test results for VPP = 256mV.................................................................................76 5-16 Test results for VPP = 296mV.................................................................................77 5-17 Test results for VPP = 356mV.................................................................................78 5-18 Test results for VPP = 396mV.................................................................................78 5-19 Test results for VPP = 560mV.................................................................................79 5-20 Test results for VPP = 600mV.................................................................................80 5-21 Test results for VPP = 712mV.................................................................................80 xi

PAGE 12

5-22 Plot of unit-time (rise time-VLOW to VHIGH) obtained from equation 3.3, cadence simulation and chip test results measurement for various duty ratios corresponding to the switching period of 1s-10s.................................................86 5-23 Plot of unit-time (rise time-VLOW to VHIGH) obtained from equation 3.3, cadence simulation and chip test results measurement for various duty ratios corresponding to the switching period of 11s-20s...............................................87 5-24 Plot of unit-time (rise time-VLOW to VHIGH) obtained from equation 3.3, cadence simulation and chip test results measurement for various duty ratios corresponding to the switching period of 21s-30s...............................................88 5-25 Plot of unit-time (rise time-VLOW to VHIGH) obtained from equation 3.3, cadence simulation and chip test results measurement for various duty ratios corresponding to the switching period of 31s-40s...............................................89 5-26 Plot of unit-time (rise time-VLOW to VHIGH) obtained from equation 3.3, cadence simulation and chip test results measurement for various duty ratios corresponding to the switching period of 41s-50s...............................................90 5-27 Plot of error factor between simulated and computed unit-time values for various duty ratios.................................................................................................................91 5-28 Plot of error factor between measured and computed unit-time values for various duty ratios.................................................................................................................92 5-25 Constant-transconductance bias circuit with wide swing cascode current mirrors..94 5-26 Schematic showing the generation of current sources (100A-60A)....................95 5-27 Schematic showing the modified capacitor charging/discharging circuit................96 5-28 Unit-time generated for VPP=256mV using the modified current source and bias circuitry....................................................................................................................97 5-29 Plot of unit-time for various VPP using the modified circuit (1s 10s)..............98 5-30 Plot of unit-time for various VPP using the modified circuit (11s 20s)............99 5-31 Plot of unit-time for various VPP using the modified circuit (21s 30s)..........100 5-32 Plot of error factor in unit-time for various VPP (1s 10s: 11s 20s)..........101 5-32 Plot of error factor in unit-time for various VPP (21s 30s: 31s 40s)........102 5-33 Plot of supply current Vs VPP for various switching period ranges (solid line-simulation results, dashed line – chip test results).................................................103 xii

PAGE 13

6-1 Modified architecture of mixed mode digital pulse width modulator to eliminate the external clock input of switching frequency....................................................107 A-1 Layout of 3*8 decoder............................................................................................109 A-2 Layout of the set-reset latch...................................................................................110 A-3 Layout of fully differential comparator..................................................................111 A-4 Layout of the capacitor used in charging/discharging circuit................................113 A-5 Layout of the various current sources used in capacitor charging/discharging ....114 A-6 Layout of the triangle wave generator along with the bonding pads.....................115 A-7 Bonding diagram of the 40-pin DIP from MOSIS.................................................116 A-8 Equivalent circuit of the package trace..................................................................117 B-1 Printed circuit board layout for testing the triangle wave generator......................118 xiii

PAGE 14

Abstract of Thesis Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Master of Science DESIGN AND IMPLEMENTATION OF MIXED MODE DIGITAL PULSE WIDTH MODULATOR FOR A DC-DC CONVERTER By Bharath Balaji Kannan August 2003 Chair: Dr.Khai D.T Ngo Cochair: Dr. William R Eisenstadt Major Department: Electrical and Computer Engineering Switched mode power supplies have become one of the vital components in most of the commercial and industrial applications. Digital control of switched mode power supplies has gained popularity owing to its benefits of lower sensitivity to process and mismatch variations, programmability and the reduction of passive components used in tuning. Digital control based on pulse width modulation (PWM) techniques is employed in most of the converter configurations. The conventional digital approach of generating PWM pulse signal uses a fast clock method, while other methods of PWM generation using tapped-delay lines and digital signal processors also have been developed. These pulse width modulation schemes operate with a particular switching frequency limited by the resolution of the digital PWM, requires larger area and consume more power. The proposed Mixed Mode Digital Pulse Width Modulator provides a wide switching frequency range which is also programmable. In this approach a timing xiv

PAGE 15

generator produces a signal of certain duration whose period is based on the duty cycle input. The signal obtained from the timing generator is replicated over a certain number of times to obtain the on-time of the PWM signal. The timed signal depends on the duty cycle and the switching period range. The number of times the timed signal has to be replicated is decided by which is determined internally based on the switching period. COUNTN The main contributions in the design which addresses the problems found in other approaches are as follows: The architecture offers programmable switching period which enables it use in a variety of applications. The digital PWM resolution is independent of the clock frequency when compared to that of the fast-clock approach. The clocking signal and the unit-delay generated by charging/discharging can be disabled once the on-time is generated which reduces the effective frequency of the clock. This also reduces any power loss associated with the switching activity of the clock. The thesis focuses on the timing generator used in the pulse width modulator. The timing generator was fabricated using AMI 0.6m process and tested with a printed circuit board developed using Protel 99 SE. The test results indicated that the timing generator (triangle wave generator) works conceptually but due to parasitics involved with the package and the mismatches associated with the generation of current sources, introduced more delay than what is desired. The architecture also lends itself for further exploration with focus on reducing the switching activity associated with the internal clock. The thesis also concludes with a note on enhancing the design by eliminating the external clock which operates at the switching frequency. xv

PAGE 16

CHAPTER 1 INTRODUCTION Power control schemes have been revolutionized over the past few decades. The advancements in the semiconductor industry have helped in the easier implementation of these control strategies. In commercial applications it is required to maintain tight voltage regulation and high efficiency over a wide range of loads. The current trends in microprocessor design which necessitate increasing current demands and lower operating voltages also adds up to the requirements of power control schemes. It is predicted that the future microprocessors might require 30-60A of static current and impose dtdi requirements on the order of 5 nsA [1]. Such constraints bound to increase the additional toll on the power converters. 1.1 DC-DC Converter DC-DC converter is a device that accepts a DC input voltage and produces a DC output voltage. Generally the output produced is at a different voltage level than the input voltage. DC-DC converters are also used to provide noise isolation, power bus regulation etc. The DC-DC converter also considered as the DC equivalent of a transformer can be used to either step up or step down the voltage based on the configuration employed. 1.1.1 Theory and Operation DC-DC converters store energy in inductors, capacitor or both during their operation. This energy is then distributed to the load over a time period. This distribution of the stored energy is efficiently accomplished by varying the charging time for the 1

PAGE 17

2 energy storage device depending on the load, for every time period. This phenomenon is known as Pulse Width Modulation (PWM). In this mechanism the charging time period changes with respect to the load. The charging time period corresponds to the switching action of the power converter which is controlled by an external circuitry. The DC voltage across the load is to be maintained at the desired level irrespective of the loading conditions and the changes in the input voltage. The output voltage is monitored using a control circuit and maintained at the desired level using a switching circuitry. The basic configuration of a DC-DC converter employing Pulse Width Modulation technique for controlling the switching action is shown in Figure 1-1. The error voltage is determined by comparing the output voltage to the reference voltage and is amplified by the gain circuit. This error voltage is then digitized using an A/D converter. Load 0VinVModulator Width Pulse Digital(H)Gain Converter Switching -DA/ DAN/ dratioDuty circuitry control and nComputatio Figure 1-1. DC-DC converter configuration with control circuitry.

PAGE 18

3 The control circuitry manipulates the N-bit A/D output to produce the N-bit duty ratio input for the Pulse Width Modulator. The Pulse Width Modulator accepts the output from the computational unit and generates a square wave with duty ratio () at the switching frequency (fs) of the converter. d 1.1.2 Types and Configuration Converters are classified based on the operation performed. The five main types of converters are as follows: Boost Converter is used to step-up the voltage Buck Converter is used to step-down the voltage Buck-Boost is used to step-up or step-down the voltage. They are mainly used as voltage polarity reversers or inverters. Cuk converter is also used to step-up or step-down the voltage as that of a buck-boost converter. Charge-pump converters are used in low power applications for either voltage step up or voltage inversion. The circuit configuration used in buck type of DC-DC converter is shown in Figure 1-2. The major components include the switching power MOSFET Q1, flywheel diode D1, inductor L and the output filter capacitor C1. The control circuit monitors the output voltage and maintains it at the desired voltage reference level by switching the power MOSFET Q1.

PAGE 19

4 Q1D1LC1Load0Vcircuit Control Switching inV VREF Figure 1-2. The basic circuit of a Buck type DC-DC converter. In this type of converter the output voltage is related to the input voltage by the duty ratio () and is given by d dVVinout (1.1) where TTon d is the duty cycle and T is the duration over which the power MOSFET switches are on. This indicates that the output voltage can be controlled as a function of the on-time of the MOSFET switches. on In a boost type converter, the output voltage is governed by the following equation. dVVinout11 (1.2) This ratio indicates that the output voltage is greater than the input voltage and is related to the duration over which the MOSFET switches are off. Hence the switching action in a power converter is obtained by any one of the following mechanisms [2].

PAGE 20

5 1. Duty ratio adjustment-The boost and buck type converters which operate by adjusting the duty ratio of their switches exhibit pulse width modulation (PWM) action. This is the most widely used control technique. 2. Frequency adjustment-This kind of control is not usually employed owing to the reason that the need to provide matching frequency components of voltage and current in a given source or load places tight constraints on the switching (operating) frequencies. 3. Timing adjustment-The idea of adjusting the switching action in time is called as phase control. The converters which employ these mechanisms vary the phase leading to phase modulation 1.2. Controller for DC-DC converter The traditional approaches for the controller of DC-DC converters based on duty ratio adjustment have relied on analog implementation schemes. The above mentioned control strategies based on analog techniques which offer robust control suffer from serious limitations due to the sensitivity to noise of the passive components used in the architecture. Hence this trend has moved towards digital control schemes which offer multitudinous benefits. The advantages offered by digital control include low power consumption, immunity to analog component variations, ease of implementing sophisticated control schemes and least susceptibility to noise. The traditional approach of PWM generation using ramp based controller exhibits poor noise immunity [3-5]. The PWM controller based on fast clock approach involves larger power consumption, requires high resolution to avoid limit cycle oscillation [6-10] and requires an external clock, while the PWM controller using tapped delay line scheme [11-13] consumes larger area for its implementation. This thesis work focuses on the design of the digital pulse width modulator shown in Figure 1-1 which is used in the switching action of converters. The modulator accepts the duty ratio as an input and generates the switching signal for the MOSFET switches in

PAGE 21

6 the converter with an on-time (Ton) at the switching frequency. Some of the major contributions in this thesis work which addresses the problems dealt in other methods of PWM signal generation are: The architecture offers programmable switching period which enables its use in a variety of applications. The architecture also provides easier programmability of the inputs at the user level, enabling its integration with other digital systems. The digital PWM resolution is independent of the clock frequency when compared to that of the fast-clock approach. The clocking signal and the unit-delay generated by charging/discharging can be disabled once the on-time is generated which reduces the effective frequency of the clock. This also reduces any power loss associated with the switching activity of the clock. The inherent limitations in digital controllers based on PWM techniques have been studied and an effort to overcome these limitations was carried out in the design of the digital pulse width modulator. 1.3. Thesis Chapter Synopses Chapter 2 focuses on PWM based controllers for DC-DC converter. It explains the various control strategies involved in PWM based control. It also brings in the advantages and disadvantages of the various approaches dealt in PWM based control. Chapter 3 focuses on the Architecture of the proposed Mixed Mode Digital Pulse Width Modulator for DC-DC converters. It explains the algorithm involved in the implementation of this module using an example. Chapter 4 focuses on the block level and circuit level implementation of the proposed architecture. It also outlines the simulation results of each block of the architecture obtained using Cadence simulation software.

PAGE 22

7 Chapter 5 discuses the testing procedures involved in the board level testing of the proposed architecture fabricated using the AMI 0.6m process. It compares the simulation results obtained using Cadence with that of the real-time testing hardware. It also gives a detailed study on the analysis performed on each sub-block used in the architecture. It also suggests mechanisms for future exploration of the proposed architecture.

PAGE 23

CHAPTER 2 PWM CONTROLLERS Pulse Width Modulation controllers are implemented using both analog and digital control schemes. Pulse width modulator produces a logic signal, which is periodic with frequency and has duty cycle. The signal is used to control the duration over which power transistor in the converter are switched on. The input to the digital pulse width modulator is an N-bit digital command word obtained from a DSP/microprocessor unit. The modulator manipulates N-bit digital command word to produce the duty cycle in proportion to it. )(tP sf d )(tP 2.1. Ramp Based PWM Controller The signal used for in the switching action of the converter is generated using various techniques. The traditional approach is based on comparing a saw toothed waveform with the analog control voltage [3-5]. The peak-to-peak amplitude of is Vmax. The switching frequency of the converter () is equal to that ofv. This approach is shown in Figure 2-1. )(tP )(tvsaw )(tvsaw sf )(tsaw )(tvsaw)(tvc)(tPVDDVSSgenerator aveSawtooth WInput AnalogComparator WaveformPWM Figure 2-1. Pulse width modulator circuit 8

PAGE 24

9 The signal is generated by an analog comparator which compares the analog control voltage v with that of.The logic level of the signal is high whenever is greater thanv. The PWM waveform obtained using the above approach is illustrated in Figure 2-2. )(tP)(tcsaw )(tvsaw )(tvc )(t )(tcv)(tsawv maxVsdT0t)(tP0sTsT2 Figure 2-2. Typical waveforms obtained using ramp based pulse width modulator The analog input signal is a continuous function of time. This analog signal is sampled at a rate equal to that of the switching frequency in order to have one discrete value of the duty cycle every switching period. This sampling restricts the useful frequencies of the ac variations to frequencies much less than the switching frequency. Hence these pulse width modulators exhibit poor noise immunity when v contains significant components at frequencies equal to or greater that switching frequency. The inherent limitations of analog controllers like tuning, sensitivity to noise, process and component variations paved way for digital controllers. )(tvc )(tc

PAGE 25

10 Digital control of converters allows for the implementation of more functional control schemes. Digital controllers offer the benefits of programmability, immunity to noise and component variations. 2.2. Digital PWM Controllers Digital pulse width modulator (DPWM) generates a discrete set of duty ratio values. This leads to the output voltage having only discrete set of values during steady state condition. Under this condition if the required output voltage doesn’t fall under one of the discrete set of values, the feedback controller switches among two or more discrete values of the duty ratio. This leads to a phenomenon called as limit-cycle oscillation [6] [7]. This problem arises due to the resolution of the DPWM being too low to accommodate for the intermediate values of voltages. Hence a high resolution DPWM is desired in the design of these controllers. The various approaches employed in the design of digital pulse width modulator are: Fast-Clocked Counter-comparator scheme Tapped delay line scheme Hybrid fast-clock-counter/tapped delay line Microprocessor and DSP based approach 2.2.1 Fast-Clocked Counter-Comparator Scheme This approach uses an external fast clock to generate the PWM waveform. The output of the voltage sensor in the basic converter configuration is fed as input to an A/D converter. The A/D converter produces an N-bit binary number which represents the duty cycle. This binary number is loaded into a register and compared with the output from a counter clocked at using a digital comparator. This scheme requires the counter rate to be 2N times higher than the switching rate (N = resolution of the digital PWM in clkf clkf

PAGE 26

11 number of bits). An R-S latch is set at the instant when the number is loaded into the register. The R-S latch is reset once the counter has reaches zero from the loaded count. The on-time of the PWM wave is proportional to the count [1, 8]. This control scheme consumes larger die area and requires an external clock for the counter-compare circuit. In a multi-phase application, the PWM generation circuitry cannot be shared among phases. This necessitates an independent counter-compare circuit for each of the phases leading to increased die area and power. The architecture of the fast-clocked counter is shown in Figure 2-3. Data LoadDataDownCount swFbit-NData DigitalclkFCounterdetector ZeroDQ RSLatch R-SOutput PWM Figure 2-3. Architecture of fast-clocked counter-comparator circuit This architecture requires restructuring to accommodate for change in the switching frequency. In this approach the switching frequency is constrained by the resolution (N-bits) and the clock frequency () [9, 10]. This relationship is stated below: clkf )12(Nclkswff (2.1) For an 8-bit system with a 50 MHz clock, the duty cycle ranges from 1/257 to 256/257 and the switching frequency is 194.55 kHz.

PAGE 27

12 2.2.2 Tapped Delay Line Based PWM In this PWM generation strategy the switching frequency of the converter is used rather than a fast clock which consumes more power. The essential components of the tapped delay-line approach are a sequence of delay lines and a multiplexer [8, 11-13].A pulse from a reference clock initiates the cycle and sets the PWM signal to logic high level. This reference pulse is then propagated along a sequence of delay lines and when it reaches the output selected by the multiplexer, it sets the PWM signal to logic low level. The total delay of the delay line is adjusted to be equal to that of the reference clock period. Additionally feedback is used to provide a delay locked loop (DLL) which locks to the period of the input clock. This technique can also be utilized to generate multiple PWM signals by adding multiplexers to a single delay line. The architecture of tapped delay-line scheme is shown in Figure 2-4. rMultiplexe 1 to2N network MatchingDelay Clock Referenceinput digitalcycleDuty RSQOutput PWM Figure 2-4. Architecture of tapped delay-line PWM generation This configuration also uses starvation buffers to control the total delay of the delay line. The current available to switch the buffer outputs is limited by inserting a series

PAGE 28

13 MOS device in the sub threshold or linear region. Though this PWM pulse generation approach is power efficient it suffers from other disadvantages like, it requires larger implementation area due to numerous delay lines and multiplexer. 2.2.3 Hybrid Fast-Clock-Counter/Tapped Delay Line This hybrid approach combines the advantages of both the fast-clock counter and the tapped delay line schemes [8, 14]. In this approach a 32 stage delay line is configured as a ring oscillator and is phase locked to a reference clock. The ring oscillator frequency is set in such a way that it is 2 to 32 times faster than the reference frequency using a divider. The input clock period is divided into equal increments using the tapped delay line. The taps of the delay line are connected to two 32 1 multiplexers. The rising edge of the PWM signal is set by the reference clock and is reset when the pulse after propagating along the delay line is sensed by the multiplexer. This architecture is illustrated in Figure 2-5. Figure 2-5. Architecture of hybrid fast-clocked counter and tapped delay line PWM [8].

PAGE 29

14 2.2.4 Digital PWM Control Using DSP With the recent advances in the semi-conductor industry, microprocessors and DSP processors are used in producing digital PWM. A PWM controller using DSP processor is shown in Matsuo et al. [15]. In this control scheme the parameters of interest like the output voltage, input voltage and current are fed into a set of preamplifiers and digitized using an A/D converter. These parameters are manipulated suitably in the digital signal processor where the required numerical values namely corresponding to switching period, on-time for the converter switches and start time for the A/D signal conversion are generated. The calculations of these values are based on a set of gain equations. The architecture of this approach is shown in Figure 2-6. ADTonTsNNN,, ParametersinVinIoVcircuitamplifierPreconvertersignal A/DQ2for drive GateQ1for drive GateOSCgenerator signal Drivedon2on1sNT NT NT NTclkfCK1oininNV ,NI,NV(DSP)Processor Signal DigitaldonsTTT Figure 2-6. Architecture of digital PWM using digital signal processor This approach requires the usage of a digital signal processor. This can prove to be inefficient if all the functions of the processor are not utilized. This can also increase the power consumption and the cost involved in the implementation of such controllers. In microprocessor-based PWM converters [16-21], resolution limitation is caused due to the

PAGE 30

15 minimum timing cycle of the hardware timer used in generation of PWM waveform. This resolution limitation is discussed in Peng et al. [19]. In most of these controllers the switching frequency is either fixed or limited by the architectural approach. These controllers also necessitate an external fast clock and larger silicon area for implementation. An efficient design strategy calls for programmability at the switching level and less usage of external discrete components. This can be obtained by combining the major advantages of afore mentioned approaches. Hence a mixed mode design technique is adopted to offer high programmability and to reduce external discrete components along with the cost involved.

PAGE 31

CHAPTER 3 MIXED MODE DIGITAL PULSE WIDTH MODULATOR Mixed mode digital pulse width modulator (MMDPWM) generates a PWM pulse signal corresponding to the duty cycle for various switching frequencies. This PWM generator can be programmed to operate in the switching frequency range of 10 kHz to 1MHz. A digital PWM controller which allows for four discrete switching frequencies with a maximum value of 700 kHz is discussed in Chow [21]. MMDPWM also has a 10-bit resolution to meet the static voltage specifications and to prevent undesirable limit-cycle oscillation. 3.1. Architecture of MMDPWM Mixed Mode digital pulse width modulator uses a modified scheme of the fast-clock counter approach of generating a PWM waveform while eliminating the need for an external fast clock. In this architecture the on-time T corresponding to the duty cycle is generated as a multiple of and T times a unit timed signal (t). The expression describing the on-time is shown below: on COUNTN sn u snCOUNTuonTNtT (3.1) where is a number which is constant for a particular switching period range. In the above equation T denotes the normalized value of the switching period. For example a switching period of 50s denotes a T value of 50. The unit timed signal is derived from a triangle wave which is generated based on the duty cycle (d) and the COUNTN sn sn 16

PAGE 32

17 switching frequency () range selected. The expression for on-time from DC-DC converter fundamentals is given below: sf ut on sonTdT (3.2) In comparing equation 3.1 and 3.2 it is evident that the unit timed signal plays the role of duty cycle (d) which is scaled by. The conceptual generation of on-time of the PWM pulse signal using the Mixed Mode Digital Pulse Width Modulator is indicated in Figure 3-1. COUNTN Cv sT onT offTsTNtTsCOUNTu6101)(tP Figure 3-1. On-time generation for the PWM pulse signal. MMDPWM accepts four frequency selection bits which are used in determining the switching period range and a 10-bit duty cycle input. The switching time period is also

PAGE 33

18 given as a 7-bit digital input along with an external clock corresponding to the switching frequency (). The original idea in developing the Mixed Mode Digital Pulse Width Modulator rested on a model without any external clock and using only programmable digital inputs. Due to timing constraints this requirement was resorted for future study and an external clock corresponding to the switching frequency was included in the architecture. The block diagram of the Mixed Mode Digital Pulse Width Modulator showing the inputs and outputs is indicated in Figure 3-2. MMDPWM offers ten different switching frequency ranges. The architecture for T generation evolves by generating a unit timed signal from the duty cycle and replicating this timed signal for a specified number of times. The total number of times the timed signal has to replicated depends on the numerical value of the switching period and the value of determined from the particular switching period range. swf on )(ut COUNTN VDDGNDModulator Width PulseDigital Mode Mixed FR3FR2FR1FR0TP6TP5TP4TP3TP2TP1TP00123456789ddddddddddSWfsignalpulse PWMPeriodTime Switching Figure 3-2. Block diagram of mixed mode digital pulse width modulator.

PAGE 34

19 The architecture of MMDPWM is composed of the following major components. 1. Switching time period range selection and count determination 2. Unit-time signal generation 3. generation using fast-clock and digital comparator approach onT The internal blocks involved in the architecture of the Mixed Mode Digital Pulse Width Modulator and the interconnections between them are illustrated in Figure 3-3. selection rangePeriod SwitchingFR3FR2FR1FR0 selection Source/Current generation VPPGenerationDelay Unit 0123456789 dddddddddd iondeterminat COUNTN )Comparator Digitalr/Counter/(MultiplieGeneration )(T time-On on ut signal PWM onT TP0 TP1 TP2 TP3 TP4 TP5 TP6chip-on Fabricated fsw Figure 3-3 Block diagram showing the major internal components of the mixed mode digital pulse width modulator (dashed line indicates the components fabricated on chip) 3.1.1 Switching Time Period Range and Count Determination MMDPWM provides ten different switching time period ranges. The switching time period is selected based on the application using four selection bits (FR3 FR2 FR1

PAGE 35

20 FR0). The time period ranges offered by MMDPWM and the corresponding selection bits are listed in Table 3.1. The selected time period range is also used in determining the total count used in generation. COUNTN onT Table 3-1. Time period range and count selection S.NO Selection bits FR3 FR2 FR1 FR0 Switching Period Range (s) COUNTN 1 0 0 0 0 1-10 20 2 0 0 0 1 11-20 18 3 0 0 1 0 21-30 16 4 0 0 1 1 31-40 14 5 0 1 0 0 41-50 12 6 0 1 0 1 51-60 10 7 0 1 1 0 61-70 8 8 0 1 1 1 71-80 6 9 1 0 0 0 81-90 4 10 1 0 0 1 91-100 2 3.1.2 Generation of Unit Timed Signal-t u This component uses the 10-bit duty cycle input and the selection bits for unit timed signal generation. The unit timed signal to be generated for the on-time of the PWM pulse signal is given by the following equation: cuIVPPCt ns (3.3) The voltage equivalent of the duty cycle is obtained as follows: (3.4) mV 1024dVPP In order to achieve the requiredVPP, the two reference voltage levels VHIGH and VLOW are generated around the midpoint of the power supply. This is obtained by the voltage drop across a resistor obtained by the flow of appropriate binary weighted current. The reference voltage levels are described by the following equation.

PAGE 36

21 )500(2binIVDDVHIGH (3.5) )500(2binIVDDVLOW (3.6) VLOWVHIGHVPP (3.7) where is the binary weighted current corresponding to the duty cycle. The various current sources used in the generation of the reference voltage levels are listed in Table 3-2. The following table shows the bit pattern for some of the duty ratios, while the bits can be appropriately programmed to obtain other duty ratios. binI Table 3-2 Binary current sources used in reference voltage level generation S.NO Duty Cycle Input (d) d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Binary weighted current Source binI (A) 1 0 0 0 0 0 0 0 0 0 1 1 2 0 0 0 0 0 0 0 0 1 0 2 3 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 1 0 0 0 8 5 0 0 0 0 0 1 0 0 0 0 16 6 0 0 0 0 1 0 0 0 0 0 32 7 0 0 0 1 0 0 0 0 0 0 64 8 0 0 1 0 0 0 0 0 0 0 128 9 0 1 0 0 0 0 0 0 0 0 256 10 1 0 0 0 0 0 0 0 0 0 512 For example to obtain a duty ratio of 48.4375% the bit pattern is determined as follows: Duty ratio of 48.4375% corresponds to VPP of 496mV as from equation 3.4. This voltage of 496mV is generated by a current of 496A flowing through a 1k resistor. The values of VHIGHand VLOW for this duty cycle is 1.898V and 1.402V respectively. The bit pattern of (0111110000)2 is used to generate the binary weighted current of 496A, which corresponds to a duty cycle of 48.4375%.

PAGE 37

22 This VPP is appropriately converted into a unit timed signal using a triangle wave, which is obtained by charging and discharging a capacitor with a current source (). The time delay associated with charging the capacitor fromVLOW toVHIGH represents the unit-time required for T generation. The upper and lower limit of the triangle wave is set by VHIGHandVLOW voltage reference levels generated previously. The charging and discharging current () is distinct for each of the ten switching period ranges offered by MMDPWM. The time period (frequency) range selection bits are also used in selecting the current () required for charging and discharging the capacitor, from a set of ten different current sources. The various current sources used in charging the capacitor are listed in Table 3-3 CI onCI CI Table 3-3 Charging/discharging current for generating the unit timed signal corresponding to VPP S.NO Selection bits FR3 FR2 FR1 FR0 Charging/discharging current source (A) CI 1 0 0 0 0 100 2 0 0 0 1 90 3 0 0 1 0 80 4 0 0 1 1 70 5 0 1 0 0 60 6 0 1 0 1 50 7 0 1 1 0 40 8 0 1 1 1 30 9 1 0 0 0 20 10 1 0 0 1 10 The block diagram of the current source selection circuit based on the switching period range selection bits is illustrated in Figure 3-4.

PAGE 38

23 A 100 A 90 A 80 A 20 A 10FR0FR1FR2FR3SEL0SEL1Selector SourceCurrent SEL2SEL8SEL9SEL0SEL1SEL2SEL7SEL8SEL9SEL3 Figure 3-4 Block diagram of the current source selection circuit. The value of the capacitance used in t is 4.88pF. This value is determined using Matlab by iteration. u 3.1.3 Generation ofTUsing Fast-Clock Approach on The T representing the on-time of the PWM waveform is obtained as a multiple times the unit timed signal (t) and the switching time period as given in equation 3.1. The value of is determined using Table 3-1 based on the switching period range selected. The block diagram of Tgeneration is shown in Figure 3-5. on COUNTN u COUNTN on

PAGE 39

24 Cv Cv utonsCOUNTTTN610cIswitch cycle Chargeswitchcycle Discharge Figure 3-5 Triangle wave form and schematic representation of Tgeneration on From equation 3.1 it is evident that T can be generated by replicating the unit timed signal for number of times. The replication of the unit timed signal is accomplished using the fast-clock and digital comparator approach. on COUNTsNT610 3.2 Algorithm for TGeneration on This section describes the algorithm behind the on-time generation of the PWM waveform. This algorithm is applicable to all switching time period in the range of 1s to 100s. The Matlab code describing the determination of the capacitor value, charging current and is shown in Appendix B. COUNTN

PAGE 40

25 The algorithm can be explained by an example for a duty ratio of 25% and switching period of 22s. From the Table 3.1 it is evident that switching period of 22s corresponds to a switching period range selection bit pattern of (0010)2 and value of 16. Duty ratio of 25% indicates a VPPof 256mV using equation 3.4. The charging current associated with this time period range is 80A as from Table 3.3. COUNTN Hence the unit-time tassociated with this configuration is given as: u 63121080102561088.4 ut (3.8) (3.9) stu910616.15 The on-time for the given duty cycle is computed as shown below using equation 3.1. (3.10) sTon 162210616.159 sTon 496.5 (3.11) This can be verified by using the basic equation for T as given in equation 3.2. For the given example it is found to be equal to 5.5s.Thus this algorithm can be used to compute the on-time for the PWM waveform corresponding to the duty cycle for various switching frequencies. This approach also benefits from the fact that it does not require an external fast clock unlike the traditional fast-clock counter and digital comparator approach. The clock required for the counter circuit used in replicating the unit-time is generated internally using the triangle wave. on This approach also has the advantage of operating at various switching frequencies and provides high programmability. The architecture also doesn’t necessitate any external passive components for its operation thereby reducing the implications of component

PAGE 41

26 variations. The various approaches involved in PWM signal generation are summarized in Table 3-4 along with the features involved in each method. Table 3-4 Comparison of the various approaches for PWM signal generation Comparison features PWM Generation approach Switching frequency programmability Power Consumption Area Mixed Mode Digital Pulse Width Modulator (proposed approach) Ten different ranges 5mW (triangle wave generator) mm 183211 Fast clock approach N/A 30mW [14] mmmm11 Tapped Delay Line scheme N/A 10W [13] mmmm2.175.0 Hybrid Fast-clock/Tapped delay line scheme N/A 300W (32X reduction with respect to fast clock [8] ) mmmm125.0

PAGE 42

CHAPTER 4 HARDWARE IMPLEMENTATION OF MIXED MODE DIGITAL PULSE WIDTH MODULATOR The transistor level implementation of Mixed Mode Digital Pulse width modulator was done using the AMI 0.6m CMOS (Complementary Metal Oxide Semi-conductor) process. The circuit operates with a supply voltage of 3.3V. The digital logic high level is represented as 3.3V and digital logic low level is represented as 0V.The circuit was constructed and simulated using Analog artist environment provided by Cadence simulation software. The circuit was laid out using the Virtuoso tool of Cadence. 4.1. Architectural Implementation The architecture of MMDPWM in hardware comprises of the following major components: 1. Current source selection based on switching period. 2. Count generation circuit based on switching period. 3. Current sources for generating the reference voltage levels and charging the capacitor used intgeneration. u 4. Triangle wave generator. 5. PWM pulse generation circuit. The block diagram of the entire architecture is shown in Figure 4-1. In the block diagram the duty cycle is given as a 10-bit digital inputand the time period (TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0) is given as an 8-bit input. Using Table 3.1 the appropriate binary bit pattern (FR3 FR2 FR1 FR0) corresponding to the switching period is also given as input to the mixed mode digital pulse width modulator. d )(0123456789dddddddddd 27

PAGE 43

28 VDDVSSComparatorUpperComparatorLowerSignalchargeCharge/DisVDDVSSVHIGHVLOWVCAPcircuit generationVHIGH/VLOWVLVH SR decoder range period Switching FR3FR2FR1FR0Decoder 164 DECF9DECF8DECF7DECF6DECF5DECF4DECF3DECF2DECF1DECF0circuitselection current ischargingCharging/DcI N4N3N2N1N0P4P3P2P1P0cI period switchingon based sourceCurrent VCAP 4.88pFC clkfClock Multiplierey Baugh Wool 68 TP8 TP6 TP5 TP4 TP3 TP2 TP1 TP0 generator COUNTNFR3 FR2 FR1 FR0 012345CCCCCC Counterbit -10 Comparator Digitalbit -10 SRQ Q SRQ Q signalResetting DQRST VDD sfOutput PWM0123456789 dddddddddd chipon Fabricated Figure 4-1.Block diagram of the mixed mode digital pulse width modulator (dashed line indicates the timing generator that was fabricated on chip) The block diagram also highlights the major components making up the timing generator that were fabricated using the AMI 0.6m process.

PAGE 44

29 4.1.1 Current Source Selection Based on Switching Period The 4-bit binary input (FR3 FR2 FR1 FR0) corresponding to the switching period is determined from the bit patterns shown in Table 3-1. This pattern is decoded using a binary decoder to provide the selection inputs for the current selection circuit. The circuit is constructed using AND gates. The widths and lengths of transistors used for the implementation of digital gates are 4.95m and 1.05m respectively. The circuit schematic is shown in Figure 4-2. 164 0FR 1FR 2FR 3FR 0F 0FR 1FR 2FR 1F 1FR 2 F 3F 2FR 4 F 5F 6F 7F 2FR3FR 8F 3FR 9F 0FR1FR 2FR3FR 10F 0FR1FR 2FR3FR 11 F 2FR3FR 12 F 13F 0FR1FR2FR3FR 14F 0FR1FR2FR3FR 15F 3FR 0FR 2FR 3FR 2FR 3FR1FR0FR 0FR 1FR 0FR 1FR 3FR0FR 1FR2FR 3FR 3FR2FR1FR 0FR 3FR1FR0FR2FR0FR 1FR2FR3FR 0FR 1FR0FR 1FR 2FR Figure 4-2. Schematic of decoder for the selection of current source (Ic) based on switching period range. 164

PAGE 45

30 The 4 bit input is decoded and one of the output pins namely P0, P1, P2, P3,, P15 is set to logic high level. These output pins serve as the selection inputs for the current selection circuit used in generation circuit. Since the MMDPWM allows for ten different switching period ranges, only the binary bit patterns shown in Table 3-1 are considered as valid inputs. Hence only the output on pins P0 to P9 is considered as valid output. ut 4.1.2 Count Generation Circuit Based on Switching Period This component is used to generate the binary value of. The binary value of is obtained using a combinational logic circuit. The 4-bit input used in current selection is used as input for the count generation circuit. The combinational logic circuit is constructed for each of the output variables C4, C3, C2, C1, C0 using the selection bits as input variables and employing Karnaugh map logic reduction scheme. COUNTN COUNTN Table 4-1. Binary equivalent of corresponding to the selection inputs COUNTN S.No Selection bits FR3 FR2 FR1 FR0 COUNTN (C4 C3 C2 C1 C0)2 1 0 0 0 0 1 0 1 0 0 2 0 0 0 1 1 0 0 1 0 3 0 0 1 0 1 0 0 0 0 4 0 0 1 1 0 1 1 1 0 5 0 1 0 0 0 1 1 0 0 6 0 1 0 1 0 1 0 1 0 7 0 1 1 0 0 1 0 0 0 8 0 1 1 1 0 0 1 1 0 9 1 0 0 0 0 0 1 0 0 10 1 0 0 1 0 0 0 1 0 From K-map reduction scheme, the combinational logic equation obtained for each of the output variables is indicated below: )01(234FRFRFRFRC (4.1)

PAGE 46

31 2 )10(3FRFRFRC (4.2) )10(2FRFRC (4.3) 01FRC (4.4) 0 0 C (4.5) The schematic representation of the logic used in determining the output variables is shown in Figure 4-3. Figure 4-3. Combinational logic circuit used in the generation of ()2 COUNTN

PAGE 47

32 The output of the count generation circuit for various input combinations is illustrated in Figure 4-4. The outputs of ()2 namely C4, C3, C2 are shown in the following waveforms, while C1 is equal to the input FR0 and C0 is equal to 0. COUNTN Figure 4-4. Count generator output waveforms for various input combinations 4.1.3 Current Sources for Generating Voltage Reference Levels The VHIGH and VLOW voltage reference levels required in VPPgeneration are obtained by the virtue of the voltage drop across a resistor caused due to the flow of a binary weighted current source. The binary equivalent of the duty cycle is used in selecting the binary weighted current sources. The 10-bit binary bit pattern corresponding to the duty cycle is determined using equation 3.1 and Table 3-2. The binary weighted current sources are obtained using current mirrors. The schematic of the binary weighted

PAGE 48

33 current sources from 32A to 512A is shown in Figure 4-5 and the binary weighted current sources from 16A to 1A are shown in Figure 4-6. VDDVSS 05.105.52 05.105.4 05.14.26 05.13.48 05.135.25 05.18.49d8d5dVDDVDDVDDVSSVSSVSS AI 512AI 256 AI 32 kR1 kR1 kR1 kR1 AI 512AI 256 AI 32 VHIGHVLOW 9d 8d 5d 05.148 95.12.28 05.148 05.105.52 05.14.26 05.105.4 05.13.48 05.135.25 05.18.41 M 2 M 3M Figure 4-5. Schematic of binary weighted current sources for 512A to 32A The design of the current source circuit involves the transistor parameters namelyV, V and assumesV Vtn748.0 Vtp695.0 VDsat2.0 . In Figure 4-5 the (W/L) ratio of transistors are determined as follows: Using the square law model to get an initial estimate for the width and length of transistors, 222)(DsatNDVKILW (4.6) 2662)2.0(1017.40105122)(LW (4.7)

PAGE 49

34 24.25)(2LW (4.8) Similarly 4.43)(1LW using 259.13VAKP . The minimum length of the transistor allowable in this technology is 0.6m. Hence using a length of 1.05m the width of the transistors are suitably tweaked to produce the desired currents in the various branches. The transistor M3 operates in the linear region and is modeled as a resistor. The resistor value is determined as shown below. Using KVL, 21GSGSVIRVVDD (4.9) IVVVDDRGSGS)(21 (4.10) For AI 512 the value of kR845.2 . The width of M3 is adjusted suitably to attain this resistance value. VDDVSS 05.17.20 05.13 05.195.10 05.145.12 05.15.49d8d5dVDDVDDVDDVSSVSSVSS AI 16AI 8 AI 1 kR1 kR1 kR1 kR1 AI 16AI 8 AI 1 VHIGHVLOW 9d 8d 5d 05.121 95.195.1 05.121 05.13 05.14.20 05.145.12 05.15.4 95.195.1 95.195.1 05.17.20 05.195.10 05.14.20 M2 M1 Figure 4-6 Schematic showing the binary current sources from 16A to 1A.

PAGE 50

35 The (W/L) ratio of transistors M1 and M2 in Figure 4-6 are determined as follows: 212)(DsatNDVKILW (4.11) For a current of 300A in the branch consisting of M1 and M2 and to supply for the various current sources, 2661)2.0(1017.40103002)(LW (4.12) 32.19)(1LW (4.13) The (W/L) ratios of other transistors are suitably modified to have the required currents in the respective branches. The VHIGHandVLOWvoltage levels generated for a duty ratio of 46.875% corresponding to a VPPof 480mV is shown in Figure 4-7.The binary weighted 480A current required for VPP generation is also indicated in the figure. The duty cycle input for this configuration is (0111100000)2, based on Table 3-2.

PAGE 51

36 Figure 4-7. VHIGHandVLOWvoltage levels for a duty ratio of 46.875% 4.1.4 Triangle Wave Generator The triangle wave is generated by linearly charging and discharging a capacitor between two reference voltage levels. The voltage on the capacitor is compared with theVHIGHand VLOWreference levels using a fully-differential comparator. The triangle wave generator comprises of the following major components: Fully differential comparator S-R Latch Current sources for the capacitor charging/discharging circuit 4.1.4.a Fully Differential Comparator Fully differential comparator uses positive feedback for its operation. The actual design comprises of the pre-amplifier stage and the track-and-latch stage. Such latched

PAGE 52

37 comparators are used in analog/digital converters [23-25]. In analog/digital converters the comparison is performed only at a particular instant. The triangle wave generator requires continuous comparison of the reference voltage with the voltage on the capacitor. Hence the basic design from Norsworthy et al. [23] is modified in such a way that the comparator is used for continuous comparison. The input differential stage is coupled to two current mirror stages. These are in turn coupled using a positive feedback. The gain is provided by the input common source stage. The input preamplifier stage is used to obtain a higher resolution and to reduce the effects of kickback [26]. The positive feedback is used in regenerating the analog signal into a full-scale digital signal. The schematic of the comparator is shown in Figure 4-8. The widths of the transistors are indicated in the figure, while a length of 1.05m was used in all the transistors. In Figure 4-8 the (W/L) ratio of transistor M3 is determined for a bias current of 300A. The design procedure is shown below: Using the square law model to get an initial estimate for the width and length of transistors, 232)(DsatNDVKILW (4.14) 2663)2.0(1017.40103002)(LW (4.15) 32.19)(3LW (4.16) The (W/L) ratio of the transistors M1 and M2 are designed in such a way that each leg carries one-half of the bias current 300A.

PAGE 53

38 M1 M2 M3 Figure 4-8 Schematic of the fully differential comparator The propagation delay through the comparator when comparing the voltage across the capacitor (triangle wave) against the VHIGH and VLOW reference levels of 2.146V and 1.154V corresponding to a VPP value of 992mV is shown in Figure 4-9 and Figure 4-10 respectively. The delay involved during the comparison of VHIGH with voltage on the capacitor was determined to be around 6.73ns from simulation results. The delay involved during the comparison of VLOW with the voltage on the capacitor was determined to be 14.73ns. This indicates an asymmetrical delay in the comparator switching.

PAGE 54

39 R-Input S-Input VHIGH Figure 4-9. Propagation delay (response time) of the fully differential comparator in comparing VHIGH with the voltage on the capacitor.

PAGE 55

40 S-Input R-Input VLOW Figure 4-10. Propagation delay (response time) of the fully differential comparator in comparing VLOW with the voltage on the capacitor. 4.1.4.b S-R Latch An S-R latch is realized using NAND gates. The enable signal C is pulled to logic high level to enable the latch permanently. The schematic representation of the S-R latch is shown in Figure 4-11.

PAGE 56

41 Figure 4-11. Set-reset latch using NAND gates 4.1.4.c Current Source Selection for the Capacitor Charging Circuit The output of the decoder is used in selecting the current source required for charging the capacitor. The various current sources corresponding to the switching period range are listed in Table 3-2. The schematic of the current selection circuit is shown in Figure 4-12.The current source selection circuit uses transmission gate switches to select the required current sources. This component uses the 164 164 decoder outputs (DECF0, DECF1, DECF2,, DECF8, DECF9) in selecting the appropriate current sources based on switching period range. The following schematic shows the selection switches for three different current sources. The upper set of transmission gate switch outputs (P0, P1, P2) are used in selecting the PMOS transistors during the charging phase and the lower set of switch outputs (N0, N1, N2) are used in selecting the NMOS transistors during the

PAGE 57

42 discharging phase. The output of the S-R latch ( discharge chargesignal) is connected to the current source selected through the transmission gate. The switches are configured in such a way that the appropriate current source is selected and the PMOS transistor is enabled during the charging phase while the NMOS transistor is enabled during the discharging phase. GATEONTRANSMISSI GATEONTRANSMISSI 0P VDD /Discharge ChargeDECF0 DECF0 DECF0 GATEONTRANSMISSI GATEONTRANSMISSI 1 P DECF1 DECF1 DECF1 GATEONTRANSMISSI GATEONTRANSMISSI 2 P DECF2 DECF2 DECF2 GATEONTRANSMISSI GATEONTRANSMISSI 0N VSS /Discharge ChargeDECF0 DECF0 DECF0 GATEONTRANSMISSI GATEONTRANSMISSI 1N DECF1 DECF1 DECF1 GATEONTRANSMISSI GATEONTRANSMISSI 2N DECF2 DECF2 DECF2 Figure 4-12. Schematic of charging/discharging current selection circuit.

PAGE 58

43 The outputs of the current selection circuit (P0, P1, P2,, P9, N0, N1, N2,, N9) are fed as input to the current source circuit. The schematic of the various current sources generated for each switching period is shown in Figure 4-13. The schematic shows five different current sources generated corresponding to the switching period ranging from 1s-50s. The current sources corresponding to the switching period ranging from 51s-100s is generated in a similar manner. VDDVSS 6.005.10 6.09 0N1NVDDVDDVSSVSS AI 100AI 90 AI 100AI 90 0P1 P 05.105.40 05.105.40 6.055.8 6.095.7 05.14 6.005.10 6.09 6.055.8 6.095.7 6.01.8 6.02.72NVDDVSS AI 80 AI 80 2 P 6.01.8 6.02.7 6.03.6 6.064NVDDVSS AI 60AI 604 P 6.03.6 6.06 pFC88.4 Figure 4-13 Schematic of the current source generation circuit for various switching period ranges with control inputs Two comparators are used in triangle wave generator. The voltage across the capacitor is applied to the V and Vpins of the lower and upper comparator respectively. The reference voltage levels VHIGHandVLOWare applied to Vand pins of the upper and lower comparator respectively. The output of the upper comparator is connected to the S-input of the S-R latch and the output of the lower V

PAGE 59

44 comparator to the R-input of the S-R latch. This configuration is illustrated in Figure 4-14. VDDVSS SignalDischarge/ ChargeVDDVSSVHIGHVLOWVCAP RS QQComparatorUpper ComparatorLower Figure 4-14 Schematic of the control circuit for triangle wave generator The operation of the control circuit for the triangle wave generator is as follows. The capacitor charges from 0V to VLOWinitially (Zone 3) through a PMOS transistor as switch. The output of the lower comparator stays high making the discharge charge signal to go to logic low level. When the capacitor voltage increases above VLOW the lower comparator output switches to logic low level, while the discharge charge signal maintains the previous state. Hence the capacitor continues to charge to VHIGH (Zone 2). As soon as the capacitor voltage increases above VHIGH the upper comparator switches to logic high level (Zone 1). This sets the S-R latch output to logic high level and starts the discharging cycle. The capacitor discharges linearly to VLOW through a NMOS transistor as switch using the same current. The S-R latch output goes low once

PAGE 60

45 the capacitor voltage falls below VLOWand starts the charging cycle. The various zones corresponding to the comparator outputs are outlined in Table 4-2. u Table 4-2. Comparator outputs based on capacitor charging/discharging cycle Zone Set Input Reset Input )Q( signal DischargeCharge 1 1 0 1 2 0 0 QQ 3 0 1 0 The schematic representation of the triangle wave generation capacitor charging/discharging circuit and the associated waveforms are illustrated in Figure 4-15 and 4-16 respectively. The unit-time tis generated by the capacitor charging from to VHIGHand also during the discharge cycle from VHIGHtoVLOW. VLOW cIcICVCAP VDDVDDVSSVSS Signal/DischargeCharge VDD Figure 4-15 Capacitor charge/discharge circuit

PAGE 61

46 VCAP VHIGHVLOW1Zone2Zone3Zone t Figure 4-16 Triangle wave with the various zones during charging/ discharging cycle The triangle wave generator output for a duty cycle of 46.875% and switching period of 2s (500 kHz) is shown in Figure 4-17. The unit-time corresponding to this configuration is determined as follows: VPPICtcu (4.17) VPPcIut 121088.4 (4.18) 310480610100121088.4 ut (4.19) nsut424.23 (4.20) From the waveform it is evident that the unit-time generated was equal to 24.599ns. This gives 5% error, which is within the allowable tolerance level.

PAGE 62

47 Figure 4-17 Triangle wave generator output for %875.46 d

PAGE 63

48 The upper and lower comparator outputs and the discharge chargesignal are shown in Figure 4-18. From the output waveforms it is evident that the S and R inputs to the S-R latch from the upper and lower comparators, switch at one half the frequency corresponding to a unit timed signal period of ns. ut Figure 4-18. Lower /upper comparator outputs and the discharge chargesignal

PAGE 64

49 4.1.5 PWM Pulse Generation Circuit The PWM pulse signal is obtained by using the fast clock and digital comparator approach. This component generates the fast-clock internally for each of the duty cycles. The unit-timed signal t generated using the triangle wave generator is used in the generation of the PWM pulse signal. u This component of the circuit multiplies the count value ()2 with the number associated with the switching period. This product gives the total count up to which the unit-time has to be replicated, in order to generate the T of the PWM pulse signal. It uses a Baugh Wooley multiplier [27-28] to multiply the ()2 with the switching period. Since the switching period range offered by MMDPWM is from 1s to 100s, the time period is represented using 7-bits (Maximum value: (100)10 = (1100100)2). The count is represented using 5-bits (Maximum value: (20)10= (10100)2). The 8Baugh Wooley multiplier is chosen instead of COUNTNon 68 COUNTN 6 57 to eliminate signed number multiplication. The MSB of both the digital inputs to the multiplier is set to 0. If the maximum allowed value occurs in either of the inputs when using a configuration, incorrect multiplication can result due to the circuit assuming that one of the inputs is a negative number. Hence a 8configuration is desired. The block diagram of a 8 5 7 6 6 Baugh Wooley multiplier is shown in Figure 4-19.

PAGE 65

50 0C1C2C3C4C 0TP 05C 3 CELL 3 CELL 2 CELL 2 CELL 2 CELL 2 CELL 2 CELL 1T P 3 CELL 2 CELL 2 CELL 2 CELL 2 CELL 2 CELL 2T P 0D1D2D 3 CELL 2 CELL 2 CELL 2 CELL 2 CELL 2 CELL 6TP 4 CELL 4 CELL 4 CELL 4 CELL 4 CELL 5 CELL 0 7TP 6D ADDERFULL 7TP5C ADDERFULL ADDERFULL ADDERFULL ADDERFULL ADDERFULL ADDERFULL 1 7D 8D9D10D11D12D13D 14D Figure 4-19 Block diagram of a 8 6 Baugh Wooley multiplier The schematic of the cells used in the Baugh-Wooley multiplier namely cell 2, cell 3, cell 4, cell 5 and the full adder are shown in Figure 4-20 ,4-21, 4-22, 4-23 and 4-24 respectively [27-28].

PAGE 66

51 Figure 4-20 Schematic of CELL 2 used in Baugh-Wooley mulitplier Figure 4-21 Schematic of CELL 3 used in Baugh Wooley multiplier

PAGE 67

52 Figure 4-22 Schematic of CELL 4 used in Baugh-Wooley multiplier Figure 4-23 Schematic of CELL 5 used in Baugh-Wooley multiplier

PAGE 68

53 Figure 4-24 Schematic of full adder used in Baugh-Wooley multiplier The multiplier output corresponding to a switching frequency of 500 kHz and a duty ratio of 46.875% is shown in Figure 4-25. Here the switching period of 2s falls in the range of 1s-10s leading to a value of 20. The binary value of the switching period (00000010)2 is multiplied with the binary value of, namely (00010100)2 to get the final count. COUNTN COUNTN

PAGE 69

54 Figure 4-25 Output of the Baugh Wooley multiplier for a switching period of 2s and duty ratio of 46.875% 68

PAGE 70

55 In Figure 4-25, D0, D1, D2, D3,, D13 represent the output bits of the multiplier. The value of (D13 D12 D11,, D2 D1 D0)2 is (00000000101000)2 representing the multiplication 68 40202 . The product obtained from the multiplier is compared using a digital comparator with that of a 10-bit counter output. The clock required to drive the counter is obtained from the triangle wave generator circuit. The S and R inputs to the S-R latch switch to logic high level every ns. Hence the outputs of the upper and lower comparator are combined using an OR digital gate function. This generates a clock () that runs with a time period corresponding to seconds. A fast clock generated for a switching period () of 2s and duty ratio of 46.875% is illustrated in the schematic shown in Figure 4-26. ut2 clkf ut sT As seen in the output waveform of the fast clock generator the time period of the fast-clock is 23.424ns which is approximately equal to the unit-time computed using equation 4.6.

PAGE 71

56 Figure 4-26 Fast clock generated for a duty cycle of d=46.875% and switching period of 2s

PAGE 72

57 Hence by clocking the 10-bit counter using and by performing a count operation up to the final count provided by the multiplier, the T of the PWM pulse signal is obtained. This operation is repeated for every s, namely the switching period of the DC-DC converter. The block diagram of the four stages of a 10-bit counter [29] is shown in Figure 4-27. clkf on sT Figure 4-27. Block diagram of the four stages of a 10-bit counter. By adding subsequent stages a 10-bit counter can be realized. The counter used is a 10-bit synchronous binary counter. The counter is realized using flip flops, OR and AND

PAGE 73

58 gates. In this counter the flip flop in the least significant bit position is complemented every clock pulse. The flip flop in any other position is complemented if all the bits in the lower significant bit position are at logic high level. The counting operation is controlled using the count enable () and reset () signals of the counter. When the required count has reached, the reset signal goes low pulling all the outputs to zero. The count enable signal is also pulled low to disable the count operation and the counting begins during the start of the next switching cycle. The count generated by the counter at each fast-clock cycle is compared with the product generated by the multiplier using the digital comparator. The block diagram of a digital comparator [1] is shown in Figure 4-28. ENCT_ RST The digital comparator monitors the output of the counter and sets a signal to logic high level once the final count has reached. This signal is used in resetting the counter and in the generation of the Tsignal. on The 10-bit counter output for a switching frequency of 500 kHz and duty cycle of 46.875% is shown in Figure 4-29. The counter output at the instant before it resets to zero is given by the following equation: (4.18) 1 )10(6sCOUNTTNueCounterVal As the counter is reset to zero during every switching period the total count obtained is the desired value. The counter output waveform shows that it is reset to zero when the count reaches (39)10= (100111)2. An S-R latch is set during the start of every switching period and is reset once the counter has reached the final count value for obtaining the Tsignal. The final PWM waveform for the switching period of 2s and duty ratio of 46.875% is indicated in Figure 4-30. on

PAGE 74

1Q 1D 0Q 0D 2Q 2D 3Q 3D CMP_OUT 59 Figure 4-28 Block diagram of the three stages of a 10-bit digital comparator

PAGE 75

60 Figure 4-29 10-bit counter output for a switching frequency of 500 kHz and duty ratio d =46.875%

PAGE 76

61 Figure 4-30 PWM pulse signal from the mixed mode digital pulse width modulator

PAGE 77

62 From Figure 4-30 it is seen that the PWM wave has an on-time (T) of 1.0009s which is approximately equal to the theoretical value of 0.9375s computed using equation 3.11 as follows: on sondTT (4.19) (4.20) 610246875.0onT sTon 9375.0 (4.21) 4.2 Advantages of the Proposed Approach The Mixed Mode Digital Pulse Width Modulator combines the advantages of both the analog and digital approaches of PWM signal generation. The timing required for the on-time is generated by charging and discharging a capacitor. This unit-time is replicated using a counter and a digital comparator. This architecture offers the benefit of programming the switching frequency based on the loading condition. The clocking signal and the unit-timed signal generated by charging/discharging the capacitor can be disabled once the on-time is generated which reduces the effective frequency of the clock. This also reduces any power loss associated with the switching activity of the clock. In typical applications, during standby operation the load might require very less value of current. Under such circumstances the converter can operate at a lower switching frequency to supply the load. The architecture allows for easy change in the switching frequency by changing the bit pattern corresponding to the desired switching frequency.

PAGE 78

CHAPTER 5 TESTING AND ANALYSIS Mixed Mode Digital Pulse Width Modulator was designed and simulated in Cadence, with AMI 0.6m process used for modeling and layout. The integral part of the MMDPWM, namely the triangle wave generator was fabricated using AMI 0.6m process on a 40-pin DIP package through MOSIS. A set of testing procedures was framed and the triangle wave generator was tested using a printed circuit board laid out using Protel 99 SE [30]. 5.1 Fabrication and Packaging of Triangle Wave Generator The triangle wave generator was fabricated using the C5F/N process with 0.5m feature size. The C5F/N is a non-silicided CMOS process with 3 layers of metal and 2 layers of polysilicon. The following table outlines the process wafer and packaging information: Table 5-1 Wafer and package information S.NO Property Value 1 Wafer Size 8"(inches) 2 Reticle Size 2121 mm2 3 Die thickness 250m 4 Wafer thickness 760m 5 Package type DIP 6 Number of pins 40 The bonding diagram of the pads is illustrated in Appendix A. The floor plan of the triangle wave generator is shown in Figure 5-1. 63

PAGE 79

64 Figure 5-1. Floor plan of the triangle wave generator The floor plan shows the major blocks involved in the triangle wave generator circuit of the Mixed Mode Digital Pulse Width Modulator. The circuit has been laid out in a modular fashion so that each separate block can be tested for its operation. The layout of each block is shown in Appendix A. The circuit supports an on chip poly (electrode) to poly capacitor of 4.88pF. The computation of the layout area for the capacitor is shown in Appendix A. The triangle wave generator circuit uses 29 pins for the various inputs and outputs.

PAGE 80

65 5.1.1 Inputs to the Triangle Wave Generator 3-bit switching period range selection inputs (FR2 FR1 FR0) Voltage reference levels based on duty cycle-(VHIGH, VLOW) Voltage bias for the comparator-VBIAS Supply Voltage and ground-(VDD, GND) 5.1.2 Outputs of the Triangle Wave generator Switching period (frequency) decoder outputs-(DECF4, DECF3, DECF2, DECF1, DECF0) 83 Current source selection circuit outputs-(P4, P3, P2, P1, P0, N4, N3, N2, N1, N0) Upper and Lower comparator outputs-(S, R, V01-, V02-) Set-Reset latch output (charge/discharge signal)-SWITCH Triangle wave output-VCAP 5.2. Printed Circuit Board Design and Layout The printed circuit board (PCB) was laid out in Protel 99 and built using Quick circuit system [31] from T-Tech Corporation. The triangle wave generator is used to provide the unit-time (t) required in PWM signal generation. This component of MMDPWM accepts the duty cycle and switching period as inputs to generate the unit timed signal. The duty cycle is required for determining VHIGHand VLOWvoltage reference levels. The binary bit pattern corresponding to the switching period is given as input. The fabricated triangle wave generator allows for five different switching time period ranges and requires pre-computed VHIGHand VLOWvalues for its operation. Hence the various VHIGHand VLOWvalues are generated using a set of potentiometers. The triangle wave output is probed through a buffer to account for the input impedance of the oscilloscope. A FET input, unity gain stable operational amplifier (OPA656) from u

PAGE 81

66 Texas Instruments was used to drive the 1M || 10pF input impedance of the oscilloscope. The specifications of the operational amplifier are given in Appendix B. The necessary voltage values were generated using surface mount resistors and potentiometers. The photograph of the printed circuit board is shown in Figure 5-2. The gerber file layout used in the milling of the printed circuit board is shown in Appendix B. Figure 5-2. Printed circuit board for testing the triangle wave generator. 5.3. Testing Procedures and Measured Outputs The modular design enables testing of the triangle wave generator at the block level. The testing involves the modular testing of each of the following blocks:

PAGE 82

67 1. Switching period range selector 2. Set-Reset Latch 3. Fully differential comparator 4. Unit-time signal generation circuit The testing procedures for the above components are detailed below: 5.3.1 Switching Period Range Selector This component is tested by giving the binary bit pattern corresponding to the switching period based on Table 3.1. This component selects one of the five available current sources used in tgeneration. u // Test Function: Switching Period range selector Truth Table // Measure the decoder outputs DECF0-DECF4 ///////////////////////////////////// // Test conditions // VDD 3.3V // GND 0V // Apply a square wave of amplitude 3.3V to the FR0 input pin // with frequency 10 kHz // Apply a square wave of amplitude 3.3V to the FR1 input pin // with frequency 5 kHz // Apply a square wave of amplitude 3.3V to the FR2 input pin // with frequency 2.5 kHz // Monitor the DECF0, DECF1, DECF2, DECF3, DECF4 output pins The Cadence simulation results for the above testing procedure are indicated in Figure 5-3.

PAGE 83

68 Figure 5-3. Cadence simulation results for the switching period range selector The switching period range selector output from the fabricated chip is shown in the following figures. The inputs FR0 and FR1 are shown in channel 1 (CH1) and 2 (CH2) respectively (decoder input FR2 is held at logic 0) of Figure 5-4. The decoder outputs DECF0 and DECF1 are shown in channel 3 (CH3) and channel 4 (CH4) respectively.

PAGE 84

69 Figure 5-4 Switching period range selector outputs-DECF0 and DECF1 The decoder outputs DECF2 and DECF3 are shown below in channel 4 and 3 respectively of Figure 5-5. The inputs FR0 and FR1 are shown in channel 1 (CH1) and 2 (CH2) respectively (decoder input FR2 is held at logic 0). Figure 5-5 Switching period range selector outputs-DECF3 and DECF2

PAGE 85

70 The decoder output DECF4 is shown below in channel 4 of Figure 5-6. The inputs FR0 and FR1 are shown in channel 1 (CH1) and 2 (CH2) respectively. The decoder input FR2 is held at logic 1 and shown in channel 3 (CH3). Figure 5-6 Switching period range selector output-DECF4 5.3.2 Set-Reset Latch The test procedure for the S-R latch is illustrated below: // Test Function: Set-Reset Latch Truth Table // Measure the Switch output of the S-R latch for various combinations of S and R // digital inputs ///////////////////////////////////// // Test conditions // VDD 3.3V // GND 0V // Apply a square wave of amplitude 3.3V to the S input pin with frequency 50 kHz // Apply a square wave phase shifted with respect to the S-input of amplitude 3.3V // to R input pin at frequency 25 kHz // Measure the output waveform at the SWITCH pin The R-S latch outputs obtained using cadence simulation is shown in Figure 5-7.

PAGE 86

71 Figure 5-7. Set-reset latch outputs The R-S latch in the triangle wave generator is tested by applying pulse inputs to the R and S pin of the chip. The output of the latch through a buffer (OPA656 from Texas Instruments) is indicated in Figure 5-8. Figure 5-8. Set-reset latch outputs

PAGE 87

72 5.3.3 Fully Differential Comparator The comparator is tested for the response time measurement. The test procedure is given below: // Test Function: Comparator response time // Measure the propagation delay between the input and output // for the lower comparator ///////////////////////////////////////////// // Test conditions // VDD 3.3V // GND 0V // VBIAS 1.95V // VCAP 1.522V // VLOW AWG 3 to 0 V triangle wave // AWG frequency 10 kHz The cadence simulation results are shown in Figure 5-9. Figure 5-9. Fully differential comparator response time

PAGE 88

73 The results obtained using the fabricated chip by applying the above test procedure is shown in Figure 5-10. Figure 5-10. Comparator response time 5.3.4 Unit Time Signal Generation Circuit The test procedure for generating the unit-time based on the selected switching period and duty cycle is outlined below: // Test Function: Triangle wave generator // Measure the triangle waveform at the VCAP pin for duty cycle of 96.875% // VPP: = 992mV ///////////////////////////////////// // Test conditions // VDD 3.3V // GND 0V // VBIAS 1.95 V // VHIGH 2.146 V // VLOW 1.154 V // Set FR0 to 0V, FR1 to 0V and FR2 to 0V for switching // period range of 1s-10s range // Measure the triangle waveform at the VCAP output pin The cadence simulation result for the triangle wave generator is indicated in Figure 5-11.

PAGE 89

74 Figure 5-11. Triangle wave generator output –unit-timed signal generation VPP and unit-time obtained from the IC is shown in Figure 5-12 5-13 and 5-14. Figure 5-12. VPP obtained for 96.875%

PAGE 90

75 The VPP generated is found to be 1.35V against the required 992mV.The unit-time generated during the rise time of the triangle wave is found to be 520ns and during the fall time the delay is determined to be 690ns. Figure 5-13. Unit-time obtained during the charging interval from VLOW to VHIGH Figure 5-14 Unit-time obtained during the charging interval from VHIGH to VLOW

PAGE 91

76 The fabricated chip was also tested for other values of VPP to determine the discrepancy in the unit-time generated and to determine the source which causes this error. The above test procedure was repeated for VPP values like 256, 296, 356, 396, 560, 600 and 712mV. The waveform corresponding to these VPP values are shown in Figure 5-15, 5-16, 5-17, 5-18, 5-19, 5-20 and 5-21 respectively. A B C Figure 5-15 Test results for VPP = 256mV. A) measured VPP value of 535mV, B) measured unit-time from the rise time, C) measured unit-time from the fall time

PAGE 92

77 A B C Figure 5-16 Test results for VPP = 296mV. A) measured VPP value of 560mV, B) measured unit-time of 410ns from fall time, C) measured unit-time of 355ns from rise time

PAGE 93

78 A B C Figure 5-17 Test results for VPP = 356mV. A) measured VPP value of 365mV, B) measured unit-time of 295ns from rise time, C) measured unit-time of 385ns from fall time A C B Figure 5-18 Test results for VPP = 396mV. A) measured VPP value of 470mV, B) measured unit-time of 310ns from rise time, C) measured unit-time of 300ns from fall time

PAGE 94

79 A B C Figure 5-19 Test results for VPP = 560mV. A) measured VPP value of 820mV, B) measured unit-time of 400ns from rise time, C) measured unit-time of 570ns from fall time

PAGE 95

80 A B C Figure 5-20 Test results for VPP = 600mV. A) measured VPP value of 880mV, B) measured unit-time of 420ns from rise time, C) measured unit-time of 580ns from fall time A B C Figure 5-21 Test results for VPP = 712mV. A) measured VPP value of 930mV, B) measured unit-time of 450ns from rise time, C) measured unit-time of 630ns from fall time

PAGE 96

81 The above test results also indicate that the unit-time generated and the measured VPP value show much variation from the expected value. 5.4 Analysis of Test Results 5.4.1 Performance Analysis The unit-time values for various switching period ranges and duty ratio computed using equation 3.3 is indicated in Table 5-2. Table 5-2 Unit-time for various switching period ranges using equation 3.3 Unit-time values computed using equation (ns) S.NO Duty ratio (%) VPP (V) 100A 90A 80A 70A 60A 1 4.8828 0.05 2.44 2.71 3.05 3.49 4.07 2 7.2266 0.074 3.61 4.01 4.51 5.16 6.02 3 9.9609 0.102 4.98 5.53 6.22 7.11 8.3 4 12.305 0.126 6.15 6.83 7.69 8.78 10.2 5 14.258 0.146 7.12 7.92 8.91 10.2 11.9 6 15.82 0.162 7.91 8.78 9.88 11.3 13.2 7 19.336 0.198 9.66 10.7 12.1 13.8 16.1 8 22.07 0.226 11 12.3 13.8 15.8 18.4 9 25 0.256 12.5 13.9 15.6 17.8 20.8 10 28.906 0.296 14.4 16.1 18.1 20.6 24.1 11 31.25 0.32 15.6 17.4 19.5 22.3 26 12 34.766 0.356 17.4 19.3 21.7 24.8 29 13 38.672 0.396 19.3 21.5 24.2 27.6 32.2 14 41.602 0.426 20.8 23.1 23.1 29.7 34.6 15 44.531 0.456 22.3 24.7 27.8 31.8 37.1 16 46.875 0.48 23.4 26 29.3 33.5 39 17 50 0.512 25 27.8 31.2 35.7 41.6 18 53.125 0.544 26.5 29.5 33.2 37.9 44.2 19 57.031 0.584 28.5 31.7 35.6 40.7 47.5 20 60.938 0.624 30.5 33.8 38.1 43.5 50.8 21 64.844 0.664 32.4 36 40.5 46.3 54 22 70.313 0.72 35.1 39 43.9 50.2 58.6 23 74.219 0.76 37.1 41.2 46.4 53 61.8 24 80.469 0.824 40.2 44.7 50.3 57.4 67 25 84.375 0.864 42.2 46.8 52.7 60.2 70.3 26 96.875 0.992 48.4 53.8 60.5 69.2 80.7 27 100 1.024 50 55.5 62.5 71.4 83.3

PAGE 97

82 The triangle wave generator was simulated in Cadence for the above duty ratios and the unit-time obtained corresponding to the charging of capacitor from VLOW to VHIGH and the discharging of capacitor corresponding to VHIGH to VLOW are listed in Table 5-3 and Table 5-4 respectively. Table 5-3 Unit-time for various switching period ranges corresponding to charging of capacitor from VLOW to VHIGH (rise time) (cadence simulation results) Unit-time from charging of capacitor (rise time) obtained from Cadence (ns) S.NO Duty ratio (%) VPP (V) 100A 90A 80A 70A 60A 1 4.8828 0.05 20.86 21.66 22.49 23.456 25.216 2 7.2266 0.074 21.785 23.065 23.764 25.133 27.113 3 9.9609 0.102 22.984 24.233 25.239 26.64 28.766 4 12.305 0.126 24.175 25.561 26.757 28.54 29.706 5 14.258 0.146 25.456 26.11 27.952 29.489 32.5408 6 15.82 0.162 26.304 26.702 28 30.242 33.0156 7 19.336 0.198 27.04 28.109 30.094 31.583 35.962 8 22.07 0.226 28.224 30.7608 32.371 34.527 37.551 9 25 0.256 30.182 31.051 34.21 36.33 39.93 10 28.906 0.296 30.456 32.33 36.49 39.118 42.44 11 31.25 0.32 31.727 34.133 36.655 40.34 43.86 12 34.766 0.356 33.88 35.998 38.72 41.85 47.275 13 38.672 0.396 35.424 38.2 40.43 44.42 50.18 14 41.602 0.426 37.094 39.51 42.98 46 52.18 15 44.531 0.456 37.74 41.312 43.94 48.67 53.22 16 46.875 0.48 39.62 41.56 44.64 49.226 54.824 17 50 0.512 40.473 44.61 46.65 51.93 57.72 18 53.125 0.544 41.163 45.58 50.48 55.11 60.274 19 57.031 0.584 43.48 48.146 51.33 56.43 63.09 20 60.938 0.624 45.57 50.18 53.56 57.793 65.78 21 64.844 0.664 47.28 51.24 55.5 62.35 68.36 22 70.313 0.72 49.67 54.4 59.47 63.71 73.52 23 74.219 0.76 51.88 55.615 62.54 68.05 76.92 24 80.469 0.824 54.8 59.85 65.036 72.24 81.622 25 84.375 0.864 56.79 62.37 67.52 73.88 85.42 26 96.875 0.992 63.86 70.23 76.67 83.87 95.54 27 100 1.024 66.85 72.12 79.38 87.06 97.93

PAGE 98

83 Table 5-4 Unit-time for various switching period ranges corresponding to discharging of capacitor from VHIGH to VLOW (fall time) (cadence simulation results) Unit-time from discharging of capacitor (fall time) obtained from Cadence (ns) S.NO Duty ratio (%) VPP (V) 100A 90A 80A 70A 60A 1 4.8828 0.05 23.75 24.6 25.935 27.29 28.32 2 7.2266 0.074 25.048 25.836 27.389 28.727 30.28 3 9.9609 0.102 26.563 27.357 29.138 30.787 32.84 4 12.305 0.126 27.519 28.371 30.336 32.054 34.427 5 14.258 0.146 27.915 29.866 32.085 33.707 35.464 6 15.82 0.162 29.061 30.329 33.261 35.05 37.393 7 19.336 0.198 31.00 32.795 35.9 37.639 39.8 8 22.07 0.226 32.169 33.308 36.65 38.961 43.16 9 25 0.256 33.562 35.32 38.11 40.23 44.705 10 28.906 0.296 35.96 38.85 40.36 43.65 48.269 11 31.25 0.32 37.819 39.05 43.18 45.57 51.15 12 34.766 0.356 38.42 41.276 44.71 48.02 52.54 13 38.672 0.396 41.066 43 47.906 51.73 55.78 14 41.602 0.426 41.86 44.045 48.81 53.96 58.33 15 44.531 0.456 44.053 46.374 51.38 55.45 61.58 16 46.875 0.48 44.44 48.42 53.55 57.93 64.08 17 50 0.512 47.198 49.18 55.37 59.97 66.61 18 53.125 0.544 48.84 51.98 56.11 60.93 68.57 19 57.031 0.584 50.62 52.44 59.67 64.73 71.99 20 60.938 0.624 52.21 55.3 61.95 68.29 75.55 21 64.844 0.664 54.58 58.63 64.82 70.41 79.35 22 70.313 0.72 57.3 62.23 67.06 74.89 83.06 23 74.219 0.76 59.93 64.8 70.34 77.48 86.2 24 80.469 0.824 63.6 68.52 75.51 82.83 92.45 25 84.375 0.864 65.26 69.8 78.29 86.81 94.92 26 96.875 0.992 74.69 79.2 86.97 96.59 106.94 27 100 1.024 76.63 82.02 88.55 98.49 111.18 The impact of the parasitics on the unit-time generated is analyzed individually. The loading effect on the capacitor of 4.88pF due to the parasitics associated with the bond wire and package can be reduced by removing the bonding wire between the pad connected to the top plate of the on-chip capacitor and the pin of the package. This removes the loading effect due to the package, but the voltage on the capacitor cannot be measured. Hence the unit-time generated is measured indirectly by probing the

PAGE 99

84 comparator outputs which switch logic high level every ut 2 seconds. The unit-time generated for various switching period ranges is measured from the fabricated triangle wave generator. The unit-time obtained from the time period of S and R inputs of the S-R latch are listed in Table 5-5 and Table 5-6. Table 5-5 Unit-time for various switching period ranges from the S-input of the S-R latch (fabricated chip test results) Unit-time from SInput of the S-R latch (ns) S.NO Duty ratio (%) VPP (V) 100A 90A 80A 70A 60A 1 4.8828 0.05 267 280 310 326 350 2 7.2266 0.074 270 283 313 330 365 3 9.9609 0.102 275 287 319 335 371 4 12.305 0.126 276 293 321 339 376 5 14.258 0.146 276 294 325 343 378 6 15.82 0.162 278 297 330 345 383 7 19.336 0.198 284 298 333 353 385 8 22.07 0.226 288 302 336 357 391 9 25 0.256 290 307 341 362 398 10 28.906 0.296 295 309 349 368 405 11 31.25 0.32 297 314 353 373 408 12 34.766 0.356 303 318 355 375 415 13 38.672 0.396 310 324 363 384 423 14 41.602 0.426 312 329 368 390 430 15 44.531 0.456 315 333 372 395 434 16 46.875 0.48 318 334 378 399 439 17 50 0.512 321 339 385 407 447 18 53.125 0.544 330 339 389 413 450 19 57.031 0.584 335 347 394 420 460 20 60.938 0.624 340 355 398 428 470 21 64.844 0.664 350 362 413 438 476 22 70.313 0.72 357 372 422 450 498 23 74.219 0.76 364 383 428 455 508 24 80.469 0.824 382 389 440 475 625 25 84.375 0.864 448 468 525 570 635 26 96.875 0.992 497 515 570 613 689 27 100 1.024 505 518 585 625 710

PAGE 100

85 Table 5-6 Unit-time for various switching period ranges from the R-input of the S-R latch (fabricated chip test results) Unit-time from RInput of the S-R latch S.NO Duty ratio (%) VPP (V) 100A 90A 80A 70A 60A 1 4.8828 0.05 280 281 312 325 352 2 7.2266 0.074 270 283 312 330 367 3 9.9609 0.102 275 285 320 335 372 4 12.305 0.126 278 290 322 345 375 5 14.258 0.146 275 293 327 345 379 6 15.82 0.162 281 295 328 345 382 7 19.336 0.198 286 295 335 350 390 8 22.07 0.226 289 300 338 354 397 9 25 0.256 293 305 340 360 399 10 28.906 0.296 293 312 345 369 406 11 31.25 0.32 299 313 350 370 410 12 34.766 0.356 302 317 354 375 414 13 38.672 0.396 307 324 361 385 424 14 41.602 0.426 312 325 369 394 427 15 44.531 0.456 315 331 374 394 435 16 46.875 0.48 319 335 377 399 435 17 50 0.512 322 337 382 406 445 18 53.125 0.544 326 343 389 411 451 19 57.031 0.584 334 350 395 421 463 20 60.938 0.624 336 355 401 428 473 21 64.844 0.664 346 363 410 437 481 22 70.313 0.72 359 374 419 448 495 23 74.219 0.76 362 380 428 460 508 24 80.469 0.824 380 397 443 474 630 25 84.375 0.864 449 472 525 564 643 26 96.875 0.992 498 515 568 610 690 27 100 1.024 510 528 584 620 703 From Table 5-5 and Table 5-6 it is inferred that the error in the unit-time has been reduced by 30-40ns with the removal of the bonding wire between the capacitor and the package. These data are compared with the computed unit-time values given in Table 5-3 and the simulated unit-time values given in Table 5-4 and Table 5-5. The unit-time values corresponding to the rise time or the charging of capacitor from VLOW to VHIGH obtained using equation 3.3, from Cadence simulation and using

PAGE 101

86 the fabricated chip for the currents 100A, 90A, 80A, 70A, 60A are compared and illustrated in Figure 5-22, 5-23, 5-24, 5-25, 5-26 respectively. Figure 5-22 Plot of unit-time (rise time-VLOW to VHIGH) obtained from equation 3.3, cadence simulation and chip test results measurement for various duty ratios corresponding to the switching period of 1s-10s

PAGE 102

87 Figure 5-23 Plot of unit-time (rise time-VLOW to VHIGH) obtained from equation 3.3, cadence simulation and chip test results measurement for various duty ratios corresponding to the switching period of 11s-20s

PAGE 103

88 Figure 5-24 Plot of unit-time (rise time-VLOW to VHIGH) obtained from equation 3.3, cadence simulation and chip test results measurement for various duty ratios corresponding to the switching period of 21s-30s

PAGE 104

89 Figure 5-25 Plot of unit-time (rise time-VLOW to VHIGH) obtained from equation 3.3, cadence simulation and chip test results measurement for various duty ratios corresponding to the switching period of 31s-40s

PAGE 105

90 Figure 5-26 Plot of unit-time (rise time-VLOW to VHIGH) obtained from equation 3.3, cadence simulation and chip test results measurement for various duty ratios corresponding to the switching period of 41s-50s The data from Table 5-2, 5-3, 5-4, 5-5 and 5-6 are used to determine the error factor between the measured/simulated unit-time values against the theoretical computed unit-time values. The error factor plot between the simulated and computed unit-time values for various duty ratios is shown in Figure 5-27. The error factor between the measured and computed unit-time values for various duty ratios is shown in Figure 5-28.

PAGE 106

91 Figure 5-27 Plot of error factor between simulated and computed unit-time values for various duty ratios From the above figure it is evident that the error factor approaches unity for increasing values of VPP. The deviation between the simulated and computed unit-time values can be attributed to the delay involved in the asymmetrical switching of the comparator and the delay through the S-R latch.

PAGE 107

92 Figure 5-28 Plot of error factor between measured and computed unit-time values for various duty ratios From the above figure it is evident that the error factor decreases for increasing values of VPP. The discrepancy in the unit-time generated can be attributed to the inherent delay in the switching of the comparator, the delay caused due to the parasitic capacitance and inductance associated with the bonding wires and package. The error factor being less for larger values of VPP can be explained with reference to the resolving capability of the comparator. The comparator is able to resolve larger values of voltages due to which its output switches much sooner leading to lesser discrepancy between the actual unit-time and the theoretical unit-time. The currents required for charging and discharging the capacitor is generated using a single current reference whose value is highly sensitive to power supply variations. The

PAGE 108

93 current generated is also bound to vary due to mismatches in the width and length of the transistors. The capacitor used in generating the unit-time sees the drain capacitance of the various NMOS and PMOS transistor switches. This capacitance also contributes to the discrepancy in the unit-time generated. The parasitic resistance, capacitance and inductance associated with the package are given in Appendix A. Some of the factors which contribute to the discrepancy in the unit-time can be averted by designing supply independent current sources to avoid errors arising from mismatches in the dimensions and the variation in the VGS (gate-source voltage) of transistors. It can also be seen from Figure 4-11 that the drain capacitance of the various transistors (10 transistors since there are NMOS and PMOS switches) used as switches comes in parallel with that of the capacitor of value 4.88pF. This design can be modified in such a way that the capacitor sees only the drain capacitance of a single NMOS and PMOS transistor. This is achieved by generating a current source which is insensitive to supply variations (better PSRR – power supply rejection ratio) and the required current source is selected whose current is mirrored to charging/discharging network. The generation of the current source and the modified capacitor charging/discharging network is shown in Figure 5-25, 5-26 and 5-27.

PAGE 109

94 VDD5k 05.195.19 05.195.19 05.195.19 05.195.19 65.105.10 65.105.10 05.105.40 05.105.10 05.195.19 65.195.19 65.13 65.195.4 65.105.10 05.105.10 05.105.10 05.105.10 95.1995.1 05.105.10 P-VBIAS P-VCASCN-VBIASN-VCASC Figure 5-25 Constant-transconductance bias circuit with wide swing cascode current mirrors [26] The schematic shown in Figure 5-25 incorporates three main stages namely the bias loop, the cascode bias network and the circuit for start-up. This circuit uses bootstrap bias technique to reduce any power supply variations [32]. In this circuit the connection of a current source and a current mirror forms a positive feedback loop and the gain around the loop is equal to the gain of the current source. The gain around the loop is made to be less than unity. The circuit also uses a start-up circuit to avoid an initial unstable operating point. The intermediate voltages generated namely VBIAS-P, VCASC-P, VBIAS-N and VCASC-N can also be used to bias other cascode stages. The current sources generated using this circuit is shown in Figure 5-26. The decoder output is used in selecting the appropriate current based on switching period range.

PAGE 110

95 P-VBIASP-VCASC 65.1168 65.1168 65.1168 65.105.151 65.105.151 65.105.151 65.1135 65.1135 65.1135 65.105.118 65.105.118 65.105.118 65.11.101 65.11.101 65.11.101 DECF0DECF1DECF2DECF3DECF4 swIVDDA 100A 90A 80A 70A 60 Figure 5-26 Schematic showing the generation of current sources (100A-60A) The schematic shown in Figure 5-26 enables the selection of one of the current sources and sets the value of to the selected current. This current is mirrored into the capacitor charging/discharging network. The schematic illustrating the above mechanism is shown in Figure 5-27. The advantage of this circuit is that the effective drain capacitance seen by the capacitor 4.88pF is reduced when compared to Figure 4-11. This circuit also ensures that the generated triangle wave is symmetric since it derives it current from a single current source unlike Figure 4-11 which generated a separate current for the NMOS branch and the PMOS branch. SWI

PAGE 111

96 SWI /DischargeCharge pFC88.4 95.195.79 95.195.79 95.195.79 95.195.79 95.195.79 95.105.79 95.105.79 95.11.77 95.11.77VDD Figure 5-27 Schematic showing the modified capacitor charging/discharging circuit The triangle wave generator circuit was modified with the above current sources and charging/discharging circuitry. The unit-time generated for a VPP of 256mV and a switching period range of 1s-10s is shown in Figure 5-28. It is evident from the figure that the error between the computed and simulated unit-time has reduced by 10ns when compared to the previous circuit. The unit-time values generated for various VPP using the modified circuit is given in Table 5-7. The plot of computed, previous circuit simulated unit-time and the modified circuit simulated unit-time for various VPP values is shown in Figure 5-29, 5-30, 5-31. The error factor plot between the computed and simulated unit-time employing the circuit shown in Figure 5-25, 5-26 and 5-27 for various VPP over the different switching period ranges is shown in Figure 5-32 and 5-33.

PAGE 112

97 Figure 5-28 Unit-time generated for VPP=256mV using the modified current source and bias circuitry Table 5-7 Unit-time generated for various VPP using the modified circuit Unit-time obtained using the modified circuit (ns) S.NO Duty ratio (%) VPP (V) 100A 90A 80A 70A 60A 1 9.9609 0.102 14.79 15.02 15.21 15.87 15.93 2 15.82 0.162 17.49 18.54 19.21 19.604 20.65 3 25 0.256 22.89 24.12 25.079 27.10 29.72 4 34.766 0.356 27.22 29.10 30.47 33.26 36.51 5 44.531 0.456 31.8 34.06 36.01 40.27 44.84 6 50 0.512 34.62 37.44 40.13 44.42 49.19 7 60.938 0.624 40.03 43.38 46.38 50.83 55.41 8 70.313 0.72 45.09 48.65 52.5 55.52 66.11 9 80.469 0.824 49.82 53.75 58.94 66.05 74.267 10 100 1.024 61.88 66.54 71.95 79.35 89.9

PAGE 113

98 Figure 5-29 Plot of unit-time for various VPP using the modified circuit (1s 10s)

PAGE 114

99 Figure 5-30 Plot of unit-time for various VPP using the modified circuit (11s 20s)

PAGE 115

100 Figure 5-31 Plot of unit-time for various VPP using the modified circuit (21s 30s)

PAGE 116

101 Figure 5-32 Plot of error factor in unit-time for various VPP (1s 10s: 11s 20s)

PAGE 117

102 Figure 5-32 Plot of error factor in unit-time for various VPP (21s 30s: 31s 40s) From figure 5-31 and 5-32 it is evident that the error factor has been reduced by a factor of 2 by employing the modified circuit. The error factor can be reduced further by using a high speed comparator in the triangle wave generation circuit. The delay involved during the comparator switching when comparing the capacitor voltage with the VHIGH and VLOW reference levels should be reduced to around 1ns against the current value of 6ns. This reduction in the propagation delay can drastically reduce the error factor between the computed and actual unit-time. 5.4.2 Power Consumption Analysis The power consumption of the fabricated chip was analyzed. The average power consumption was found be 5.6mW. The current drawn by the triangle wave generator for various VPP values in each of the switching period range is indicated in Table 5-8.

PAGE 118

103 Table 5-8 Supply current for various switching period ranges Supply Current IDD for various switching period range (mA) VPP (mV) AIc 100 AIc 90 AIC 80 AIc 70 AIc 60 256 2.10 2.00 2.00 1.90 1.90 296 2.10 1.90 1.90 1.90 1.90 356 2.00 1.90 1.80 1.80 1.80 480 2.00 1.90 1.80 1.80 1.80 512 2.00 1.90 1.80 1.80 1.80 712 1.80 1.70 1.70 1.60 1.60 800 1.60 1.60 1.60 1.50 1.50 880 1.50 1.50 1.40 1.40 1.40 992 1.50 1.50 1.40 1.40 1.40 1024 1.40 1.50 1.30 1.30 1.30 The plot of the supply current for various VPP values is shown in Figure 5-33. Figure 5-33. Plot of supply current Vs VPP for various switching period ranges (solid line-simulation results, dashed line – chip test results) The power loss associated with the switching activity of the clock can be reduced if the frequency of the clock is reduced, if the capacitor is charged with a lesser value of

PAGE 119

104 current and the charging/discharging circuitry is disabled once the required count has been reached. From the equation forT, on snCOUNTuonTNtT (5.1) csnCOUNTonITNVPPCT (5.2) The ratio COUNTcNICOUNT is determined to be 5 for all the switching period ranges and the respective values. This indicates that unit-time can be generated by a constant current source of 5A and this unit-time can be replicated by T number of times to obtain the on-time of the PWM signal. This reduces the frequency of the clock that drives the 10-bit counter and also the current drawn from the power supply. Since the frequency of the clock driving the counter is reduced the loss associated with the switching activity of the clock is reduced. N sn From Figure 5-33 it is evident that the current drawn by the circuit is less when compared to that obtained by simulation. This can be explained as follows. If it is assumed that the current generated by the current source shown in Figure 4-11 differ from their actual values due to mismatch effects, power supply variations and temperature variations then the actual current drawn by the circuit is less when compared with the simulation values. In the above case it is assumed that the digital circuits draw the required current for their operation. This is reinforced by the fact that the unit-time generated is very high when compared to the desired value. If the following equation is considered, in which the unit-time generated is inversely proportional to the current then the reduced current value can increase the unit-time.

PAGE 120

105 cuIVPPCt (5.1) Hence to minimize such effects the circuit schematic shown in Figure 5-25 and 5-26 should be used to generate the required current source. The transistors should have comparable widths to account for mismatch effects. With respect to layout considerations, when laying out transistors for analog circuits the following design guidelines should be followed [33]. The gate length of transistors must be several times larger than the technology’s minimum allowed gate length. This reduces effects and improves matching. Multiple drain/source contacts along the width of the transistor to reduce parasitic resistance and to produces evenly distributed current through the device. Interdigitization of large aspect ratio devices to reduce source/drain capacitance. Usage of even number (n) of gate fingers to reduce and by one half or ( dbC sbC nn2)2( depending on source/drain designation. Usage of dummy poly strips to minimize mismatch induced by etch undercutting during fab.

PAGE 121

CHAPTER 6 CONCLUSION 6.1 Summary The Mixed Mode Digital Pulse Width Modulator was developed to offer high programmability at the user level. The ability of the MMDPWM to operate at various switching frequencies enables its use in various applications like VRM modules, variable-speed motor drives, off-line power supplies of computers etc. This architecture also eliminates the need for an external fast clock used in PWM generation. The architecture evolves by generating a unit-time corresponding to the duty cycle and replicates this unit-time to generate the on-time of the PWM pulse signal. The duty cycle is accepted as a 10-bit binary input providing enough resolution to reduce the effects of limit cycle oscillation. 6.2 Future Work The Mixed Mode Digital Pulse Width Modulator accepts both the duty cycle and the switching frequency as an external clock for the on-time of the PWM pulse signal. The architecture can be modified to accept only the duty cycle and the switching frequency as binary numbers to generate the T of the PWM wave. on The MMDPWM incorporates the internal timing generator, which replicates the unit-time and generates the on-time. The internal timing generator can be programmed in such a way that it accepts the duty cycle () for T generation and the complement of duty cycle () for T generation. This in effect brings in the switching period by virtue d on 'd off 106

PAGE 122

107 of generating both the Tand of the PWM signal. The modified version of the Mixed Mode Digital Pulse Width Modulator accepts the switching frequency and the duty cycle as binary inputs which eliminates the need for having an external clock for the switching frequency. The modified architecture is shown in Figure 6-1. on offT VDDGND32106543210 Pu onT Modulator Width lseDigital Mode MixedFRFRFRFRTPTPTPTPTPTPTPsignalpulse PWM d'doffT Figure 6-1. Modified architecture of mixed mode digital pulse width modulator to eliminate the external clock input of switching frequency

PAGE 123

APPENDIX A LAYOUT AND PACKAGE SPECIFICATIONS The layout of the various components used in the triangle wave generator were developed using the AMI 0.6m process. The AMI 0.6m process has three layers of metal and two layers of non-silicided poly. Layouts The layout for the triangle wave generator comprises of the following major components. 5. Switching period range selector 6. Set-Reset Latch 7. Fully differential comparator 8. Current sources () cI 9. Unit-time signal generation circuit 10. Pad layout Switching Period Range Selector This component is implemented with a 83 decoder. The layout of the decoder is shown in Figure A-1. 108

PAGE 124

109 Figure A-1. Layout of decoder 83

PAGE 125

110 Set –Reset Latch The layout of S-R latch is shown in Figure A-2. Figure A-2. Layout of the set-reset latch Fully Differential Comparator The layout is shown in Figure A-3.

PAGE 126

111 Figure A-3. Layout of fully differential comparator

PAGE 127

112 Capacitor Layout The capacitor used in the charging/discharging circuit is realized using a polysilicon to poly2 (electrode) capacitor. The MOSIS parametric test results were used in the calculation of the area required for realizing the capacitor. Capacitance to be realized = 4.88pF Poly to Poly2 (electrode) capacitance = 876 aF/m2 Area required to realize the required capacitance = 21812108761088.4m = 5570.77 2m This capacitance is realized using a square structure. Hence the length and width of the polysilicon used is found to be 74.64m. The capacitor layout is shown in Figure A-4.

PAGE 128

113 Figure A-4. Layout of the capacitor used in charging/discharging circuit Current Sources for Charging/Discharging the Capacitor The layout of the current source used in charging/discharging phase is shown in Figure A-5. The various current sources are obtained by varying the width of the MOSFET transistors.

PAGE 129

114 Figure A-5. Layout of the various current sources used in capacitor charging/discharging circuit

PAGE 130

115 Unit-Time Signal Generation Circuit The layout of the unit-time signal generation circuit is shown in Figure A-6. The layout shows the entire components used in triangle wave generation along with the connection of the various outputs the bonding pads. In the layout the digital inputs and outputs are connected to PadIO and analog inputs and outputs are connected to PadARef. Figure A-6. Layout of the triangle wave generator along with the bonding pads

PAGE 131

116 Package Specifications The triangle wave generator was packaged on a 40-pin dual in-line package (DIP). The cavity size of the ceramic package is 300mils. The bonding diagram of the pads is shown in Figure A-7. Figure A-7. Bonding diagram of the 40-pin DIP from MOSIS The parasitics associated with the package are listed in Table A-1. The equivalent circuit of the package trace is shown in Figure A-8.

PAGE 132

117 Figure A-8. Equivalent circuit of the package trace Table A-1. Electrical characteristics of the 40-pin DIP Pins R () L (nH) C (pF) 1, 20, 21, 40 0.217 8.18 5.32 2, 19, 22, 39 0.177 7.92 4.39 3, 18, 23, 38 0.154 7.34 3.37 4, 17, 24, 37 0.110 6.48 2.34 5, 16, 25, 36 0.103 5.69 2.16 6, 15, 26, 35 0.0661 4.37 1.43 7, 14, 27, 34 0.0646 4.54 1.48 8, 13, 28, 33 0.0498 3.69 1.05 9, 12, 29, 32 0.0378 3.54 0.863 10, 11, 30, 31 0.0247 3.15 0.660

PAGE 133

APPENDIX B TEST BOARD LAYOUT AND SOFTWARE MODULES Printed Circuit Board Layout The triangle wave generator was tested on a printed circuit board developed using Protel 99 SE. The gerber file layout of the test circuit is shown in Figure B-1. Figure B-1. Printed circuit board layout for testing the triangle wave generator 118

PAGE 134

119 The board is milled using the Quick circuit system from T-Tech Inc. The gerber files produced by Protel 99 SE are converted into quick cam files using IsoPro 2.5 software. The various outputs are probed through an operational amplifier configured as a unity gain buffer. OPA656 operational amplifier from Texas Instruments is used as a unity gain buffer. The specifications of the FET input OPA656 is indicated in Table B-1. Table B-1. OPA656 specifications S.NO Property Value 1 Unity Gain Bandwidth 500MHz 2 Input bias current 2pA 3 Output Current 70mA 4 Input Noise Voltage 7nV/Hz 5 Rise and Fall time with 0.2V step 1.5ns 6 Input impedance(Differential) 1012 || 0.7 pF 7 Input impedance(Common-mode) 1012 || 2.8 pF Matlab Program Module for On-Time Algorithm The algorithm for T is developed based on the concept of generating a unit-time corresponding to the duty cycle and replicating the unit-time based on the switching frequency. This is accomplished using a Matlab program by varying each of the parameters in the following equations. on cuIVPPCt (B.1) sonTTd (B.2) 1024 dVPP (B.3) (B.4) ) 101()(6suCOUNTonTtNT csCOUNTonITVPPCNT6101 (B.5)

PAGE 135

120 In equation B.5 the value of C, and are varied with reasonable limits and compared with the actual on-time generated using equation B.2. This is determined for each of the ten different frequency ranges. The Matlab program module is indicated below. COUNTN cI % Matlab code to determine the charging current, capacitor value and Ncount Ts=25e-6; % Switching Frequency 40 kHz Ichar_ct=80e-6; % Charging Current Ic for i= 1:10, duty_ratio(i)=0.1*i; end for k= 1:10, actual_ton(k)=duty_ratio(k)*Ts; % Ton (On time) using the duty ratio equation vpp(k)=duty_ratio(k)*1.024; % VPP values for various duty cycle end for e=1:10, ton_eg=actual_ton(e); vpp_eg=vpp(e); r=1; u=1; for n=20:-1:1, % Ncount decremented from 20 nc(u)=n; % N Count cap=3; while cap < 5 % Maximum value of capacitor is assumed to be 5pF

PAGE 136

121 cton(r,u)=((nc(u)*(cap*1e-12)*vpp_eg*Ts*1e6)/Ichar_ct); if (((ton_eg cton(r,u))/ton_eg)*100) <= 0.1 % Error percentage between actual and computed value allowed is 10% flag =1; cap_value(e)=cap; % Estimated value of Capacitance count_value(e)=nc(u); % Estimated Ncount value break; else cap=cap+0.01; r=r+1; end end u=u+1; end end

PAGE 137

LIST OF REFERENCES [1] A.M. Wu, J.X. Xiao, D. Markovic, S.R. Sanders, “Digital PWM Control: Application in Voltage Regulation Modules,”IEEE PESC 99, vol.1, 1999, pp. 77-83. [2] P.T. Krein, Elements of Power Electronics. New York: Oxford University Press, 1998. [3] G.M. Cooley, T.S. Fiez, B. Buchanan, “PWM and PCM Techniques for Control of Digitally Programmable Switching Power Supplies,”IEEE ISCAS 1995, vol. 2, 1995, pp. 1114-1117. [4] R.W. Erickson, Fundamentals of Power Electronics. New York: Chapman & Hall, 1997. [5] E. Alarcon, G. Villar, E. Vidal, H. Martinez, A. Poveda, “General-Purpose One-Cycle Controller for Switching Power Converters: A High-Speed Current-Mode CMOS VLSI Implementation,”IEEE MWSCAS 2001, vol. 1, 2001, pp. 290-293. [6] A. Prodic, D. Maksimovic, R.W. Ericson, “Design and Implementation of a Digital PWM Controller for a High-Frequency Switching DC-DC Power Converter,”IEEE IECON 2001, vol. 2, 2001, pp. 893-898. [7] A.V. Peterchev, S.R. Sanders, “Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters,” IEEE Trans. Power Electron., vol. 18, pp 301-308, January 2003. [8] A. Dancy, A. Chandrakasan, “A Reconfigurable Dual Output Low Power Digital PWM Power Converter,” IEEE International Symposium on Low Power Electronics and Design, pp. 191-196, 1998. [9] C.H. Tso, J.C. Wu, “An Integrated Digital PWM DC/DC Converter,”IEEE ICECS 2000, vol. 1, 2000, pp. 104-107. [10] C.H. Tso, J.C. Wu, “An Integrated Digital PWM DC/DC Converter Using Proportional Current Feedback,”IEEE ISCAS 2001, vol. 2, 2001, pp. 65-68. [11] B.J Patella, A. Prodic, A. Zirger, D. Maksimovic, “High Frequency Digital Controller IC for DC/DC Converters,”IEEE APEC 2002, vol. 1, 2002, pp. 374-380. 122

PAGE 138

123 [12] J.X. Xiao, A.V. Peterchev, S.R. Sanders, “Architecture and IC Implementation of a Digital VRM Controller,”IEEE PESC 2001, vol. 1, 2001, pp. 38-47. [13] A. Dancy, A. Chandrakasan, “Ultra Low Power Control Circuits for PWM Converters,”IEEE PESC 1997, vol. 1, 1997, pp. 21-27. [14] A.P. Dancy, R. Amirtharajah, A.P. Chandrakasan, “High-Efficiency Multiple-Output DC-DC Conversion,”IEEE Trans. VLSI Syst., vol. 8, no. 3, pp. 252-263, June 2000. [15] H. Matsuo, F. Kurokawa, Z. Luo, Y. Makino, Y. Ishizuka, T. Oshikata, “Partially Resonant Acitve Filter Using the Digital PWM Control Circuit with the DSP,” IEEE TELESCON 2000, pp. 307-311. [16] C. Hattrup, H.W. van der Broeck, M. Ossmann, “Fast Estimation Techniques for Digital Control of Resonant Converters,”IEEE Trans. Power Electron., vol. 18, pp 365-372, January 2003. [17] A. Prodic, D. Maksimovic, “Digital PWM Controller and Current Estimator for a Low-Power Switching Converter,”IEEE COMPEL 2000, pp. 123-128. [18] Y.Y. Tzou, “DSP-Based Fully Digital Control of a PWM DC-AC Converter for AC Voltage Regulation,”IEEE PESC 1995, vol. 1, 1995, pp. 138-144. [19] L. Peng, X. Kong, Y. Kang, J. Chen, “A Novel PWM Technique in Digital Control and Its Application to an Improved DC/DC Converter,”IEEE PESC 2001, vol. 1, 2001, pp. 254-259. [20] A. Consoli, A. Testa, G. Giannetto, F. Gennaro, “A New VRM Topology for Next Generation Microprocessors,”IEEE PESC 2001, vol. 1, 2001, pp. 339-344. [21] H.C Chow, “Duty Cycle Control Circuit and Applications to Frequency Dividers,”IEEE ICECS 1999, vol. 3, 1999, pp. 1619-1622. [22] A. Prodic, D. Maksimovic, R.W. Erickson, “Digital Controller Chip Set for Isolated DC Power Supplies,”IEEE APEC 2003, vol. 2, 2003, pp. 866-872. [23] S.R. Norsworthy, I.G. Post, H.S. Fetterman, “A 14-Bit 80 kHz Sigma –Delta A/D Converter: Modelling, Design and Performance Evaluation,”IEEE J. Solid-State Circuits, vol. SC-24, no. 2, 1989, pp. 256-266. [24] B.J. McCarroll, C.G. Sodini, H.S. Lee, “A High-Speed CMOS Comparator for Use in an ADC,”IEEE J. Solid-State Circuits, vol. SC-23, no. 1, 1999, pp. 159-165. [25] P. Amaral, J. Goes, N. Paulino, A. Steiger-Garo, “An Improved Low-Voltage Low-Power CMOS Comparator to be used in High–Speed Pipeline ADCs,”IEEE ISCAS 2002, vol. 5, 2002, pp. 141-145.

PAGE 139

124 [26] D.A. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons, 1997. [27] W.R. Eisenstadt, Course Handouts for EEL6323, Advanced VLSI Design, University of Florida at Gainesville, spring semester, 2002. [28] N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2nd ed. New York: Addison Wesley, 1992. [29] M. Morris Mano, Digital Design. 3rd ed. New York: Pearson Education, 2001. [30] Protel 99 SE: Designers Handbook. New York. Protel International Limited, 2000. [31] Quick Circuit Training Video: Quick Circuit, Dispensing and ISOPRO. Atlanta T-Tech, Inc., 1997. [32] P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: John Wiley & Sons, 2001. [33] A. Hastings, R.A. Hastings, Art of Analog Layout. New York: Pearson Education, 2000.

PAGE 140

BIOGRAPHICAL SKETCH Bharath Balaji Kannan was born on February 18, 1980, in Chennai, India. He did his schooling in SBOA School and Junior College and D.A.V Matriculation Higher Secondary School. He received his bachelor’s degree in electrical engineering from College of Engineering, Anna University, Guindy. He has been pursuing an MS in electrical and computer engineering at the University of Florida since August 2001. His research interests include analog and digital VLSI design with a focus on low power design. He is also interested in the field of digital signal processing and computer networks. His hobbies include listening to music, drawing and painting. 125