Citation
Modeling and characterization of advanced bipolar transistors and interconnects for circuit simulation

Material Information

Title:
Modeling and characterization of advanced bipolar transistors and interconnects for circuit simulation
Creator:
Yuan, Jiann-Shiun, 1957- ( Dissertant )
Eisenstadt, William R. ( Thesis advisor )
Li, Sheng S. ( Reviewer )
Neugroschel, Arnost ( Reviewer )
Bosman, Gijs ( Reviewer )
Hsieh, C. K. ( Reviewer )
Place of Publication:
Gainesville, Fla.
Publisher:
University of Florida
Publication Date:
Copyright Date:
1988
Language:
English
Physical Description:
xvi, 188 leaves : ill. ; 28 cm.

Subjects

Subjects / Keywords:
Bipolar transistors ( jstor )
Crowding ( jstor )
Electric current ( jstor )
Electrical polarity ( jstor )
Electrons ( jstor )
Modeling ( jstor )
Narrative devices ( jstor )
Signals ( jstor )
Simulations ( jstor )
Two dimensional modeling ( jstor )
Bipolar transistors ( lcsh )
Dissertations, Academic -- Electrical Engineering -- UF
Electrical Engineering thesis Ph. D
Integrated circuits -- Computer simulation ( lcsh )
Genre:
bibliography ( marcgt )
theses ( marcgt )
non-fiction ( marcgt )

Notes

Abstract:
This dissertation discusses the modeling of two-dimensional effects in advanced bipolar transistors (BJT's) and interconnects. The goal is to develop accurate and compact models for SPICE circuit simulation of advanced bipolar technologies. After reviewing base pushout mechanism in the bipolar transistor, the collector current spreading effects in quasi-saturation have been presented. A two-dimensional circuit model including collector spreading effects in the epitaxial collector is developed based on the physical insights gained from PISCES device simulations. Illustrative measurements and simulations demonstrate the bipolar circuit modeling accuracy. Then a physics-based current-dependent base resistance model for circuit simulation is developed. Physical mechanisms such as base width modulation, base conductivity modulation, emitter crowding, and base pushout are accounted for in the comprehensive current -dependent base resistance "model. Comparisons of the model predictions with measurements and device simulations show excellent agreement. Two-dimensional circuit modeling is developed for the nonuniform current and charge distribution effects at the emitter-base sidewall and under the emitter during switch-on transients. The charge and current partitioning implemented in the bipolar transistor model treats the transient emitter crowding and current -dependent base resistance in a unified manner. Good agreement is obtained between model predictions and experimental results and transient device simulations. In parallel to the work on fast BJT digital transients, the bipolar transistor high-frequency small-signal s-parameter prediction using a physical device simulator is developed. This is a novel result which includes the effects of the Intrinsic bipolar response as well as the parasitics of interconnects, discontinuities, and bonding pads. This modeling technique can be used for sophisticated three-port or four-port network characterization and for predicting the high-frequency small-signal parameters other types of transistors. The dissertation examines the improvement of IC interconnect models. Interconnect models including losses and dispersion are developed for advanced BJT IC doping profiles. In addition, signal crosstalk between adjacent interconnects is discussed. An ECL ring oscillator with interconnection line in mixed-mode circuit simulation demonstrates the utility and necessity of accurate interconnect modeling. In summary, the dissertation provides a comprehensive two-dimensional circuit and interconnect modeling for advanced bipolar IC techniques useful in computer-aided device and circuit design.
Thesis:
Thesis (Ph. D.)--University of Florida, 1988.
Bibliography:
Includes bibliographical references.
General Note:
Typescript.
General Note:
Vita.
Statement of Responsibility:
by Jiann-Shiun Yuan.

Record Information

Source Institution:
University of Florida
Holding Location:
University of Florida
Rights Management:
Copyright [name of dissertation author]. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Resource Identifier:
024554494 ( AlephBibNum )
19989966 ( OCLC )
AFL2506 ( NOTIS )

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Full Text











MODELING AND CHARACTERIZATION OF ADVANCED BIPOLAR
TRANSISTORS AND INTERCONNECTS FOR CIRCUIT SIMULATION
















BY

JIANN-SHIUN YUAN


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN
PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF DOCTOR OF PHILOSOPHY


UNIVERSITY OF FLORIDA

1988


1U OF F LIBRARIES
















ACKNOWLEDGMENTS

I wish to express my sincere appreciation to the chairman of my

supervisory committee, Professor William R. Eisenstadt, for his

guidance and encouragement during the course of this study. I also

thank Professors Sheng S. Li, Arnost Neugroschel, Gijs Bosman, and C.

K. Hsieh for their valuable comments and participation on my

supervisory committee.

I am grateful to my colleagues, Dr. S. Y. Yung, Mr. H. Jeong for

their helpful discussions, J. Atwater, G. Riddle for photoconductive

switch measurements and sample preparation. Special thanks are extend

to Dr. Juin J. Liou; his participation on the qualifying exam and on

the final defense merits a note of gratitude.

I am greatly indebted to my wife, Hui-Li, my parents and parents-

in-law for their love, patience, and encouragement.

The financial support of the Semiconductor Research Corporation

and the National Science Foundation is acknowledged.
















TABLE OF CONTENTS


Page



ACKNOWLEDGMENTS ................. ..................... .................. ii

LIST OF SYMBOLS ............. ..... ................................. vi

ABSTRACT ............ ..... .......................... ............. xiv

CHAPTER

ONE INTRODUCTION.... ................. ...... ...............1

TWO TWO-DIMENSIONAL COLLECTOR CURRENT SPREADING EFFECTS
IN QUASI-SATURATION ............ ......................... 5

2.1 Introduction. .............. ....... ...................... 5
2.2 Multidimensional Collector Current Spreading............7
2.3 SPICE Modeling Including Collector Spreading Effects...17
2.4 Model Verification with Experiments and Device
Simulations ................ .. ......... ........ ......21
2.5 Conclusions ............................ ............... 27

THREE PHYSICS-BASED CURRENT-DEPENDENT BASE RESISTANCE.............30

3.1 Introduction................................. ........... 30
3.2 Physical Mechanisms for Current Dependency .............31
3.2.1 Base Width Modulation .......................... 32
3.2.2 Base Conductivity Modulation.....................35
3.2.3 Emitter Current Crowding ........................37
3.2.4 Base Pushout....................................44
3.2.4 The Coupling Effects ................ ...........47
3.3 The Nonlinear Base Resistance Model.................... 48
3.4 Model Verification with Experiments.................... 49
3.5 Application. ............. ..... ......................... 52
3.6 Summary and Discussion .................. .............. 52

FOUR CIRCUIT MODELING FOR TRANSIENT EMITTER CROWDING AND TWO-
DIMENSIONAL CURRENT AND CHARGE DISTRIBUTION EFFECTS.......55

4.1 Introduction ................ ......... ........... .... 55


iii









4.2 Model Development..................... .............56
4.2.1 Transient Emitter Crowding......................56
4.2.2 Sidewall Injection Current and Junction Charge
Storage Effects...............................61
4.3 Model Verification with Experiments and Transient
Device Simulation....................................67
4.4 Summary and Discussion.................... .............72

FIVE S-PARAMETER MEASUREMENT PREDICTION USING A PHYSICAL DEVICE
SIMULATOR................................................. 75

5.1 Introduction........................................... 75
5.2 Bipolar Test Structure Modeling........................ 77
5.3 Bipolar Test Structure S-Parameter Response............90
5.4 Conclusions .......................................... 98

SIX INTEGRATED CIRCUITS INTERCONNECT MODEL FOR SPICE...........102

6.1 Introduction.......................................... 102
6.2 Interconnect Modeling Topology Development ............103
6.3 Advanced IC Interconnect Cross-section Analysis........111
6.4 Interconnect Model Verification.......................115
6.5 Mixed-Mode Circuit Simulation.........................118
6.6 Summary and Discussion................................128

SEVEN MODELING FOR COUPLED INTERCONNECT LINES....................129

7.1 Introduction........................................ 129
7.2 Even Mode and Odd Mode Analyses for Two Parallel
Lines ................................................130
7.3 Signal Dispersion, Loss and Coupling for Coupled
Transmission Lines ...................................136
7.4 Mode Transition in Photonic Picosecond Measurement....145
7.5 Equivalent Circuit Model for SPICE.....................148
7.6 SPICE simulations and Discussions .....................152
7.7 Conclusions ........................................... 154

EIGHT SUMMARY AND DISCUSSIONS .................................... 161

APPENDICES

A TWO-DIMENSIONAL NUMERICAL SIMULATION WITH PISCES...........164

A.1 Introduction..........................................164
A.2 Physical Mechanisms in PISCES II....................164
A.3 Discussion...........................................166

B BIPOLAR TRANSISTOR MODELING IMPLEMENTATION TECHNIQUES
IN SLICE/SPICE..............................................168

B.1 Introduction..........................................168
B.2 User-Defined-Controlled-Sources.......................168










B.3 UDCS Implementation of the BJT Model. ................. 173
B.4 Conclusions ............. ... ...........................175



REFERENCES ............ ............................. ............... 178

BIOGRAPHICAL SKETCH ........................ ......... .... .......... 188




























































v















LIST OF SYMBOLS


AC collector area

AE emitter area

AEeff effective emitter area

a emitter-base junction gradient

CC Coupling coefficient for signal crosstalk

CjC collector-base junction capacitance

CJCO collector-base junction capacitance at VBE = 0 V

CJE emitter-base junction capacitance

CJEX extrinsic emitter-base junction capacitance

C'JE derivative of emitter-base junction capacitance

CJEO emitter-base junction capacitance at VBE = 0 V

CSCR space-charge region capacitance

CSiO2 Si02 capacitance

Ce even mode capacitance for coupled transmission lines

Cea even mode capacitance for coupled transmission lines
without dielectric interface

Cf fringing capacitance

Cf' modified fringing capacitance

Cgt gate capacitance due to finite metal thickness

Co odd mode capacitance for coupled transmission lines

Coa odd mode capacitance for coupled transmission lines
without dielectric interface

Cp plate capacitance









Csub substrate capacitance

C2 forward low current nonideal base current coefficient

C4 reverse low current nonideal base current coefficient

c speed of light

cn Auger coefficient for electron in heavy doping effects

Cp Auger coefficient for hole in heavy doping effects

EFN electron quasi-Fermi level

EFP hole quasi-Fermi level

Ei intrinsic Fermi level

Et trap energy level

f frequency

fBWM base width modulation factor

fC critical frequency in frequency-dependent permittivity

fCR(t) time-dependent emitter crowding factor

fCM base conductivity modulation factor

fCROWDING emitter crowding factor without the coupling effects

f'CROWDING emitter crowding factor with the coupling effects

fc parameter incorporating the second order effects in
the emitter crowding mechanism

fD critical frequency for frequency-dependent permittivity
of coupled transmission lines

fPUSHOUT base pushout factor

fT bipolar transistor cut-off frequency

Gn+ conductance of n+ buried layer

hI height of the SiO2 layer

h2 height of the substrate

IB base current


vii









IBideal ideal base current with ohmic drops in the base and
emitter regions

IBj base current in the partitioned region j

IC collector current

ICQNB collector current in the base quasi-neutral region

ICQNR collector current in the collector quasi-neutral region

ICSCR collector current in the collector space-charge region

IE emitter current

IEj emitter current in the partitioned region j

ILQNR lateral diffusion current in the collector quasi-neutral
region

ILSCR lateral diffusion current in the collector space-charge
region

IK knee current

IKR reverse knee current

IS collector current at VBE = 0 V

ISB pre-exponential base current

ISE emitter current at VBE = 0 V

LE emitter length

JC collector current density

JE(x) position-dependent emitter current density

Jn electron current density

JO onset of the collector current density for base pushout

k Boltzmann's constant

LE emitter length

1 transmission line length

mc collector-base junction gradient coefficient

me emitter-base junction gradient coefficient

viii








NA acceptor doping density of p-type Si

Ng(x) base doping density at depth x

NBeff effective base doping density

ND donor doping density of n-type Si

NEPI epitaxial layer doping density

n nonideal base coefficient

nc nonideal collector-base emission coefficient

ne nonideal emitter-base emission coefficient

ni intrinsic carrier density

nie effective intrinsic carrier density

no electron concentration normalized by Ng(0)

An excess electron density

PE emitter perimeter

p(x,y) position dependent hole mobility

p average excess hole density

QBC base-collector charge

QBCX extrinsic base-collector junction charge

QBCj base-collector charge in the partitioned region j

QBE base-emitter charge

QBEX base-emitter sidewall junction charge

QBEj base-emitter charge in the partitioned region j

QBO intrinsic base charge at VBE = 0 V

QQNR charge in the collector quasi-neutral region

QSCR charge in the collector space-charge region

AQB incremental intrinsic base charge due to base width
modulation









6QB incremental intrinsic base charge due to base
conductivity modulation

q electron charge

qb normalized base charge

RB base resistance

RBI intrinsic base resistance

RBIO intrinsic base resistance at VBE = 0 V

RBj base series resistance in the partitioned region j

RBX extrinsic base resistance

RC collector resistance

RCON base contact resistance

RE emitter resistance

REj emitter series resistance in the partitioned region j

R'EPI current-dependent epi-layer resistance

T absolute temperature

t' interconnect line thickness

t time

tI height of the Si02 layer

t2 height of the Si buried layer

t3 height of the Si substrate

VA Early voltage

VB "late" voltage

VBC applied base-collector voltage

VBC' base-collector junction voltage

VBCI base-collector voltage at the moving boundary between
the collector quasi-neutral region and the collector
space-charge region

VBCj base-collector charge in the partitioned region j

x









VBCO base-collector voltage at the metallurgical base-
collector region

VBE applied base-emitter voltage

VBEj base-emitter junction voltage in the partitioned region j

VBE' base-emitter junction voltage

Vbi junction built-in voltage

VCB applied collector-base voltage

VCE applied collector-emitter voltage

VDQNR lateral diffusion velocity in the collector quasi-neutral
region

VDSCR lateral diffusion velocity in the collector space-charge
region

VT thermal voltage kT/q

V* effective junction built-in voltage

AV ohmic drops in the emitter and base regions

Vpe even-mode phase velocity of propagated signal in
coupled transmission lines

Vpo odd-mode phase velocity of propagated signal in
coupled transmission lines

vs electron saturation velocity

WE emitter width

WQNR collector quasi-neutral region width

WSCR collector space-charge region width

WEPI epitaxial collector width

XB base width

XEPI epitaxial layer depth

XJB base junction depth

XJE emitter junction depth










AXB current induced incremental base width due to base
pushout

w interconnect width

We effective interconnect width (TEM mode)

weff(f) frequency-dependent effective interconnect width

Z transmission line impedance

ZOe even-mode characteristic impedance of coupled
transmission line

Zo0 odd-mode characteristic impedance of coupled transmission
line

Zoe(f) frequency-dependent even-mode characteristic impedance
of coupled transmission line

Zo0(f) frequency-dependent odd-mode characteristic impedance
of coupled transmission line

a interconnect attenuation constant

ac interconnect conductor loss

ace conductor loss of coupled transmission lines in even mode

aco conductor loss of coupled transmission lines in odd mode

ad interconnect dielectric loss

ade dielectric loss of coupled transmission lines in even
mode

ado dielectric loss of coupled transmission lines in odd mode

f bipolar transistor current gain

PF maximum forward current gain

PR maximum reverse current gain

Op phase constant

y propagation constant

e permittivity of silicon

eSi relative permittivity of silicon


xii










ESiO2 relative permittivity of silicon dioxide

Er relative permittivity

Ere effective relative permittivity

eree effective permittivity of coupled transmission lines in
even mode

creo effective permittivity of coupled transmission lines in
odd mode

C0 permittivity of free space

Oc collector-base junction potential

Oe emitter-base junction potential

r effective base doping gradient

rF bipolar transistor forward transit time

rn doping-dependent electron recombination lifetime

Tn0 electron recombination lifetime at low doping

7p doping-dependent hole recombination lifetime

Tp0 hole recombination lifetime at low doping

rQNR injection-level-dependent hole recombination lifetime in
the collector quasi-neutral region

TR bipolar transistor reverse transit time

PnO electron mobility

Pp(xy) position-dependent hole mobility

P~ permeability of free space

p resistivity of the conducting microstrip

Pb intrinsic base sheet resistivity at VBE 0 V

UMETAL conductivity of metal line

aSi conductivity of silicon

Osub conductivity of substrate


xiii
















Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

MODELING AND CHARACTERIZATION OF ADVANCED BIPOLAR
TRANSISTORS AND INTERCONNECTS FOR CIRCUIT SIMULATION



BY



JIANN-SHIUN YUAN



December 1988



Chairman: William R. Eisenstadt
Major Department: Electrical Engineering

This dissertation discusses the modeling of two-dimensional

effects in advanced bipolar transistors (BJT's) and interconnects. The

goal is to develop accurate and compact models for SPICE circuit

simulation of advanced bipolar technologies. After reviewing base

pushout mechanism in the bipolar transistor, the collector current

spreading effects in quasi-saturation have been presented. A two-

dimensional circuit model including collector spreading effects in the

epitaxial collector is developed based on the physical insights gained

from PISCES device simulations. Illustrative measurements and

simulations demonstrate the bipolar circuit modeling accuracy.


xiv










Then a physics-based current-dependent base resistance model for

circuit simulation is developed. Physical mechanisms such as base width

modulation, base conductivity modulation, emitter crowding, and base

pushout are accounted for in the comprehensive current-dependent base

resistance model. Comparisons of the model predictions with

measurements and device simulations show excellent agreement.

Two-dimensional circuit modeling is developed for the nonuniform

current and charge distribution effects at the emitter-base sidewall

and under the emitter during switch-on transients. The charge and

current partitioning implemented in the bipolar transistor model treats

the transient emitter crowding and current-dependent base resistance in

a unified manner. Good agreement is obtained between model predictions

and experimental results and transient device simulations.

In parallel to the work on fast BJT digital transients, the

bipolar transistor high-frequency small-signal s-parameter prediction

using a physical device simulator is developed. This is a novel result

which includes the effects of the intrinsic bipolar response as well as

the parasitics of interconnects, discontinuities, and bonding pads.

This modeling technique can be used for sophisticated three-port or

four-port network characterization and for predicting the high-

frequency small-signal parameters other types of transistors.

The dissertation examines the improvement of IC interconnect

models. Interconnect models including losses and dispersion are

developed for advanced BJT IC doping profiles. In addition, signal

crosstalk between adjacent interconnects is discussed. An ECL ring

oscillator with interconnection line in mixed-mode circuit simulation









demonstrates the utility and necessity of accurate interconnect

modeling.

In summary, the dissertation provides a comprehensive two-

dimensional circuit and interconnect modeling for advanced bipolar IC

techniques useful in computer-aided device and circuit design.
















CHAPTER ONE
INTRODUCTION

The bipolar transistor (BJT) circuit model implemented in SPICE

(the Gummel-Poon model) is derived based on one-dimensional device

physics. Recently, the bipolar transistor has been scaled down to one

micrometer emitter width. It exhibits the multidimensional current

flow, especially when operated in high current transients rendering

one-dimensional analysis inadequate. Thus, accurate device

characterization and optimal integrated circuit (IC) fabrication

process enhancement, through device and circuit simulations require

better modeling of the advanced bipolar transistor. In addition, the

interconnect delay in the submicrometer integrated circuits becomes

increasing important during high speed transients. To precisely predict

the BJT circuit performance, an accurate modeling of interconnect is

essential. These facts motivate this study.

The general topology of this study is, first, to explore the

importance of the multidimensional current flow by investigating the

physical insight into the two-dimensional device simulations, and,

second, to develop a representative two-dimensional circuit model for

circuit simulation. The model developed describes the nonuniform

current and charge distribution in the quasi-neutral base, the emitter-

base sidewall, and the collector. The model shows good agreement when

compared with measurements and device simulations.









2

Then, an interconnect model is developed based upon the first-

order approximation and physical device simulation. The BJT circuit

model and the IC interconnect model are integrated together for digital

circuit simulation. The results of this study are directly applicable

to advanced bipolar transistors and BiCMOS devices.

In Chapter Two, we developed a circuit model of the collector

current spreading effects in quasi-saturation for advanced bipolar

transistors. The discussion in this chapter reveals the importance of

lateral current spreading in the epitaxial collector when base pushout

occurs. The lateral diffusion currents ameliorates the quasi-saturation

effects compared to one dimensional BJT model. Physical insight into

the charge dynamics in the collector is shown by examining the current

gain and hole concentration plots in PISCES simulations for 1-D-

collector and 2-D-collector BJT's. Also, dc and transient circuit

simulations at high currents are compared with measurements to

demonstrate the model utility and accuracy.

Chapter Three presents a physics-based current-dependent base

resistance model for all levels of injection. The model includes the 1-

D and 2-D physical mechanisms of base width modulation, base

conductivity modulation, emitter current crowding, and base pushout; it

describes a current and voltage-dependent base resistance. Various

measurement results and device simulation data are compared with the

model predictions to demonstrate the model accuracy. For an emitter-

coupled logic circuit, the BJT with a current-dependent Rg model

results in a more realistic transient response compared with a BJT with

constant base resistance model.









3

In Chapter Four, the author develops a partitioned circuit model

taking into account the emitter crowding, sidewall current injection,

and current-dependent base resistance in a unified manner. The model

describes a nonuniform transient current and charge distribution under

the emitter and at the emitter-base sidewall. This current and charge

partitioning accurately represents the charge dynamics of the BJT

during switch-on transient. The model predictions shows good agreement

when compared with measurements and transient device simulations.

Chapter Five describes the s-parameter measurement prediction

using a physical device simulator for advanced bipolar transistors. The

prediction not only includes the intrinsic BJT small signal responses,

but also accounts for the parasitic effects resulting from the

interconnects, bends and pads. The intrinsic BJT small signal s-

parameters are converted from y-parameters simulated in PISCES. The

terminal responses are obtained by multiplying the cascaded T-matrix

components representing the intrinsic BJT and extrinsic layout

parasitic effects. Two interconnect cross-sections are compared to

evaluate which is a superior test structure that introduces less signal

attenuation and phase. In general, this technique can be used for three

or four port network analysis and for the devices other than the BJT,

such as GaAs heterojunction bipolar transistors in high frequency

characterization.

In Chapter Six, the conventional interconnect model is improved.

A new interconnect model which accounts for signal loss and dispersion

is introduced for advanced IC cross-section profiles. An inverse

Fourier transform is used for modeling transients. The prediction of









4

the interconnect model shows good agreement when compared with

measurement. The model is implemented in SLICE/SPICE for mixed-mode

circuit simulation. The utility of the interconnect model is

demonstrated in a five-stage ECL ring oscillator transient simulation.

In Chapter Seven, the single interconnect model is extended to

include crosstalk for coupled interconnect lines in close proximity.

Signal crosstalk is important in digital switching. The model is

developed from even mode and odd mode interconnect capacitance

analysis. The picosecond transient measurement of photoconductive

circuit element technique has been used to demonstrate the even mode

and odd mode pulse splitting. An equivalent distributed, lumped circuit

model for coupled interconnect lines is also developed. Circuit

simulations employing the coupled transmission lines in digital

switching have been used to demonstrate the signal crosstalk between

interconnects. The discussion in this chapter supplements Chapter 6,

thus providing a more complete interconnect modeling analysis.

Chapter Eight summarizes the contributions of this dissertation

and presents recommendations for extension of this study.
















CHAPTER TWO
TWO-DIMENSIONAL COLLECTOR CURRENT SPREADING EFFECTS IN QUASI-SATURATION

2.1 Introduction

Advanced self-aligned bipolar transistors based on a double

polysilicon technology show multidimensional current flow in the

collector, especially when operated at high currents. The

multidimensional current flow effects are not included in existing

bipolar circuit-simulator models such as the Gummel-Poon model in

SPICE2 [1]. Recently, a novel 3-D BJT circuit model has been developed

by using a 2-D device simulator [2]; however, the details of the

collector spreading physical mechanism and the implementation in the

equivalent circuit model have not been treated.

The quasi-saturation effects have been investigated by numerous

authors for the past twenty years [3-8]. In general, two distinct

models (one-dimensional and two-dimensional) have been developed. In

the 1-D model, base push-out or quasi-saturation effect occurs when the

current density is high enough that the intrinsic base-collector

metallurgical junction becomes forward biased. Then carriers are

injected into the epitaxial collector [3], [8].

In the two-dimensional model, there is a maximum current density,

called space-charge-limited current flow, and any further increase in

collector current results in a 2-D base spreading [4], [5]. Detailed

explanations for the operating regions of each mechanism are shown in

[6-8].









6

For the standard advanced BJT process, however, the heavily doped

extrinsic base resulting from the double polysilicon technology makes

base spreading negligible. In contrast, the base push-out due to high

current in the collector is two-dimensional and results in lateral

collector current spreading in the epitaxial collector [9], [10]. This

collector current spreading, which is different from base spreading,

has not previously been modeled.

Recently, Kull et al. [11] extended the Gummel-Poon model to

include quasi-saturation, or base push-out in the BJT circuit model

formulation. Kull's compact extension was modified by Jeong and Fossum

[12] [13] to account for the possible existence of a current-induced

space-charge region in the epitaxial collector. The modeling in [11]

[12] is based a one-dimensional derivation and does not represent the

two-dimensional currents in the collector. Thus, this modeling can

overestimate quasi-saturation effects [9], [10].

In this chapter, the model in [12] is extended to take into

account the multidimensional collector-current-spreading mechanism that

occurs in quasi-saturation. The extension is facilitated by using the

two-dimensional device simulator PISCES [14) to perform simulations of

the advanced BJT's (Sec. 2.2). The PISCES simulations reveal the

physical mechanism producing 2-D collector spreading. The mechanism was

not reported in the previous BJT simulations [9], [15]. The modeling of

collector transport in [12] [13] is modified to account for the lateral

diffusion currents in the epitaxial collector region. The development

of this modeling is described in Sec. 2.3. Comparisons of the model

performance with measurements and device simulations are presented in









7

Sec. 2.4. Excellent agreement in dc and transient behavior is observed

over a wide range of operating conditions.



2.2 Multidimensional Collector Current Spreading

An analysis of PISCES simulations of the advanced bipolar

transistor was undertaken to identify the physical origin of the

collector current spreading in the epitaxial collector. The BJT

simulations with PISCES include heavy-doping effects (bandgap

narrowing, Auger recombination), doping and field dependent carrier

mobilities, and Shockley-Read-Hall (SRH) recombination. A generic

advanced BJT cross-section was constructed by incorporating common

features of many state-of-the-art transistors reported in the

literature [16], [17].

The advanced bipolar transistor is illustrated in Fig. 2.1, where

only half cross-section and doping profile need to be simulated due to

the cross-section's symmetry. The emitter and base doping profiles and

the emitter-base spacing were designed to avoid sidewall tunneling and

perimeter punchthrough in the BJT [18]. Polysilicon contacts are

simulated for the emitter and the base by using an effective surface

recombination velocity of 3 x 104 cm/s [19]. The substrate contact is

situated at the bottom of the buried collector. It is found that only a

negligible perturbation on the lateral current flow in the lightly

doped epitaxial collector results when a side-collector contact is

used; this is discussed later in the paper.

A PISCES simulation predicted the multidimensional current flow in

the collector and this is shown in Fig. 2.2. This diagram displays the














E

(0,0)


(0,1.0)


Figure 2.1.1


A right half cross-section of an advanced bipolar
transistor used for multidimensional current studies.
Dimensions of the cross-section are indicated in
micrometer.


(0.5,0)


n+

p+





n
(EPITAXIAL LAYER)










n*


I (1.0,0)


(1.0,1.0)

















1x1021

S1x1020
E
S1x1019 -
Z ,-EXTRINSIC BASE
O p PROFILE

S1x1018 -
S 170 -
O
Z 1x1016- \

0.

o 614
o lxlO10
l 1x1014 I

1x1013 -1 11 -
0.0 0.2 0.4 0.6 0.8 1.0
DEPTH INTO SILICON (gm)



Figure 2.1.2 The doping profiles of the bipolar transistor shown in
Figure 2.1.1. The solid line is the doping profile at
the center of the emitter and the dashed line is the
doping profile below the extrinsic base region.














E

(0,0)


(0,1.0)


B

I (1.


(0.5,0)


(1.0,


),0)























1.0)


Figure 2.2 Plot of electron current vectors in the advanced BJT
shown in Figure 2.1. In this PISCES simulation the
collector contact is at the bottom of the buried
collector at VCE 2.0 V and VBE 0.9 V.


Jr Jr r r \\V \ I \ \ \ \ +
--- < -- t - '- -t*











Jr Jr Jr \\\\\\' \JrI \ \ \ \ \

SI Jr r \\\\\\VIAI \ \ \ \ \ Jr
S t 4 4 "
t t t I I At" I
t t t tt" *














i i I I 1111~11141 1 1 1 1 I I
I( t I t I 1tt111 1 1 1 I I
-i t 1 1) )1 nniu \ : .


I I I \ \ \~!II \ \\\\ \










11

PISCES simulation of the electron-current-density-vector plot, Jn, of

the advanced BJT biased at applied collector-emitter voltage, VCE = 2.0

V and applied base-emitter voltage, VBE = 0.9 V (IC = 0.5 mA/pm). In

the quasi-saturation region depicted in Fig. 2.2, excess carriers are

injected into the epitaxial collector (base push-out). These excess

electrons diffuse laterally in the epitaxial collector region under the

extrinsic base due to the high carrier concentration gradient in the

horizontal direction. Collector current spreading is indicated by the

horizontal component of current-density vectors underneath the

extrinsic base.

Note that Fig. 2.2 qualitatively shows where the multidimensional

collector currents occur, but it does not lend itself to a quantitative

estimation of the magnitude of these currents. The grid in Fig. 2.2 is

nonuniform (for better simulation accuracy and convergence) and dense

at emitter, base, and emitter-base junction because of the position-

dependent doping density at these regions. The magnitudes of the

current-density vectors at the grid points which are sparsely located

are enhanced when compared to those of dense grid points.

The effect of electric field in the buried collector on the

current distribution in the epitaxial collector can be seen by shifting

the collector contact to the right-side of the BJT. Figure 2.3 shows a

BJT simulation from PISCES of the current-density vectors for a right-

side-collector contact, with VCE 2.0 V and VBE = 0.9 V, the same bias

as that of Fig. 2.2. Although there is a great difference in the

current vectors in the buried collector (due to lateral ohmic drop),

all the currents in the intrinsic BJT remain virtually the same. The














E

(0,0) I


(0,1.0)


(0.5,0)


B

S(1.0,0o)


(1.0,1.0)


Figure 2.3 Plot of electron current vectors in the advanced BJT
shown in Figure 2.1. In this PISCES simulation the
collector contact is at the side of the buried collector
at VCE 2.0 V and VBE 0.9 V.


: ii,,,-,,::
t t f t tfr *t*
S ttt
4 4 4 4 4 *444*4*44
t ,4 + 4 4 t tt4 '4
; I n, s'mI :iiii *
-- t J \ i ;\ 15515; +




l i n m11\\ \ \ \ \ '




J r i, l l\\\\\\w\ \ \ \ \ ,

\ 4 \ \ \\\\\4\\\\ \ \ \ \ \
1 \ \ \ \\\ \\1 \ \ \ \ \

S \ \\\ \\4\\ \ \ \ \'
\ \ \ \\ VS\\ ^ *- -O










13

magnitudes of the vertical and lateral current-density vectors in Fig.

2.2 and Fig. 2.3 are typically within 0.5% of each other. This

indicates that the electric field from the right-side collector contact

only controls the current flow in the buried-collector region, and that

it does not significantly affect the lateral flow. Thus, there is no

significant drift component in the collector spreading mechanism.

A 1-D-collector transistor was simulated in order to isolate the

effects of collector spreading in the advanced BJT operation. This 1-D-

collector BJT, shown in Fig. 2.4, has the same emitter and base regions

as the 2-D BJT in Fig. 2.1; however, below the extrinsic base region of

the 1-D-collector transistor, the epitaxial and buried-collector

regions are replaced with SiO2. This forces the collector current to

flow solely in the vertical direction below the intrinsic base, hence

the name l-D-collector transistor.

Comparing the current gain, f and cut-off frequency, fT of the 2-D

BJT to those of the 1-D-collector BJT at high currents is one of the

keys to understanding the role of collector current-spreading. The 2-D

BJT exhibits a larger p (see Fig. 2.5) and fT than the 1-D-collector

BJT as both transistors are driven further into saturation [10].

Figure 2.6 indicates how quasi-saturation is ameliorated by

lateral diffusion in the collector. This figure displays a hole

concentration plot for a vertical slice along the center of the emitter

of both the 2-D BJT and l-D-collector BJT. This simulation is performed

for BJT's with emitter width, WE 1 pm, VBE = 0.9 V, and VCE 2.0 V.

The base in the 1-D BJT displays significantly more base widening than

the 2-D-collector BJT, which results in an enhanced 2-D-BJT P, and fT
















E

(0,0) I


B

I (1.0,0)


(0.5,0)


(0,1.0o)

C


(1.0,1.0)


Figure 2.4 An advanced bipolar transistor cross-section designed
with a 1-D-collector. This transistor is used to isolate
the 2-D collector spreading effects.


n+

P+
p






n


Si02






n+




















300







z 200




u


100-








0.4 0.5 0.6 0.7 0.8 0.9
VBE (V)






Figure 2.5 Plot of the current gain versus VBE. The solid line
represents the 2-D BJT and the dashed line represents
the 1-D-collector BJT.

























E 20
E.1 0 -
z
O -

10 -
F




0 10\


0 4
=1014
0 0.2 0.4 0.6 0.8 1.0
DEPTH (grm)







Figure 2.6 Plot of hole concentration from the center of the emitter
to the collector at VCE 2.0 V and VBE 0.9 V. The
solid line represents the 2-D BJT and the dashed line
represents the l-D-collector BJT.












at high currents. The reduced quasi-saturation effects in 2-D-BJT are

due to the lateral diffusion current which results from the high

carrier concentration gradient in the horizontal direction. Further

simulation of current spreading at different emitter widths, with the

same doping profiles and boundary conditions as in Fig. 2.2, indicates

that the lateral diffusion current is not a function of WE, but a

function of normalized charge Q(IC,VCE,WE)/WE or the charge below the

emitter periphery.



2.3 SPICE Modeling Including Collector Spreading Effects

A semi-empirical model was developed using PISCES simulation to

suggest analytical approximations that would predict collector current

spreading. This modeling of the collector spreading effect was

incorporated into an existing charge-based 1-D BJT model [12] to yield

a quasi-2-D model. The 1-D BJT model accounts for quasi-saturation

ohmicc and non-ohmic) by describing the collector current in terms of

the quasi-Fermi potentials at the boundaries of the epitaxial collector

which, in conjunction with the base transport, characterizes

IC(VBE,VBC). Since this charge-based 1-D model correctly accounts for

the 1-D BJT physics [12] it can be modified to incorporate the

multidimensional current effects in the advanced BJT.

In the formulation of the 2-D model, we estimate the lateral

diffusion currents in the collector quasi-neutral region and the

collector space-charge region (ILQNR and ILSCR) as a function of the

normalized 1-D-collector quasi-neutral region charge and space-charge

region charge (QQNR/AE and QSCR/AE, AE is the emitter area). These








18

normalized excess charges are the sources of the lateral diffusion

currents. Empirical lateral diffusion velocities (VDQNR and VDSCR) are

estimated from the collector lateral current flow predicted by PISCES

BJT simulation. These lateral diffusion velocities multiplied by the

respective normalized charges and emitter perimeter, PE form the

lateral diffusion currents. The current and voltage dependence of the

lateral diffusion currents are implicitly accounted for in the model by

the collector charges QQNR(IC,VCE) and QSCR(IC,VCE). Figure 2.7 shows

the base transport current, ICQNB in the quasi-neutral base, collector

transport currents, ICQNB and ILQNB in the collector quasi-neutral

region, and ICSCR and ILSCR in the collector space-charge region. In

Fig. 2.7 a moving boundary between collector quasi-neutral region and

collector space-charge region defines the collector quasi-neutral

region width, WQNR and the collector space-charge region width, WSCR

(WSCR WEPI-WQNR, and WEPI is the epitaxial collector width).

The following equations incorporate the collector-spreading

mechanism into the 1-D model and make it a 2-D model:


ICQNB = ICQNR + ILQNR (2.1)


ICQNR ICSCR + ILSCR (2.2)


ICQNB = IS/qb [exp(VBE'/VT) exp(VBCO/VT)]

+ C21S exp[VBE'/(neVT)] (2.3)


VT 1+F(VBCO) VBCO-VBCI
ICQNR -- F(VBCO) F(VBCI) In[-] + )
R'EPI 1+F(VBCI) VT (2.4)


ICSCR q AE (NEPI + An) v,


(2.5)






















1/2 R 1/2 SCR
L L


E O---- I --- C
IQNB QNR ISCR
C C C


0 WONR WEPI

QNR SCR
B 1/2 IL 1/2 1



Figure 2.7 Regional BJT schematic used to show the transport
currents associated with their regions and boundaries.











ILQNR VDQNR (QQNR/AE) PE (2.6)


ILSCR VDSCR (QSCR/AE) PE (2.7)


where R'EPI QQNR/(nONEPIAE), F(V) [1 + aexp(V/VT)]1/2,


VBCO [EFN(0)-EFP]/q, a 4ni2/NEPI2


VBCI [EFN(WQNR)-EFp]/q, VT kT/q,


QQNR, QSCR, WQNR, and An are defined in [12].


The notation used in the equations above is as follows: NEPI is the

epitaxial collector doping concentration, ni is the intrinsic carrier

concentration, vs is the saturation velocity, PnO is the electron

mobility, EFN is the electron quasi-Fermi level, EFP is the hole quasi-

Fermi level, VBE' is the base-emitter junction voltage, and IS, qb, C2,

and ne retain their meanings given in the Gummel-Poon model [1].

Figure 2.8 displays the overall SPICE model topology of the 2-D

model for collector spreading. Two new current sources which are

highlighted in the figure have been added to the 1-D-BJT model [12] to

account for the lateral diffusion currents in the epitaxial collector.

Note that, since the 2-D model modifies the 1-D BJT quasi-static charge

in the collector region, the transient currents dQQNR/dt and dQSCR/dt

are effectively refined in terms of this new quasi-static charge

distribution as Eqs. (2.1)-(2.7) are solved simultaneously. A l-D BJT

model can not represent this collector charge redistribution [12] and

gives erroneous estimates of the BJT transient performance [10]. In

contrast, the 2-D BJT circuit model correctly accounts for the charge










21

dynamics in the collector and the moving boundary between the quasi-

neutral region and the space-charge region in the epitaxial collector.

In addition, collector conductivity modulation, which makes the

collector resistance small, is accounted for in the modified R'EPI that

is a function of the varying quasi-neutral collector width,

WQNR(IC,VCE). A component of base recombination current, QQNR/rQNR due

to a finite recombination lifetime, rQNR in the collector quasi-neutral

region [20] is also included in the base current, IB. The injection-

level-dependent lifetime (TQNR) can be modeled as [21]:


p
'QNR rpO + 'nO (2.8)

p+ NEPI


QQNR
p (2.9)
q AE WQNR


where rnO is the electron recombination lifetime, and rp0 is

the hole recombination lifetime in SRH recombination model.



2.4 Model Verification with Experiments and Device Simulations

The circuit model which includes collector current spreading was

implemented in the user-defined controlled-sources (UDCS's) available

in SLICE, the Harris Corporation enhanced version of SPICE. In the

SPICE circuit analysis, UDCS's are user-defined subroutines that use

the implicit nonlinear model equations to compute both charging current

(dQ/dt) and transport (I) currents [22] (see Appendix B) in the model

as depicted in Fig. 2.8. The underlying transport currents in Sec. 2.3
















dQQNR/dt




B R dQB/dt RC
*--Ar- -- -|-n-- -


SCR C

QNR
'B L lQNR dQscR/dt
dQBE/dt


I QNB
Co,).






RE

*E




Figure 2.8 Network representation of the circuit model including
collector current spreading effects. The bold lines are
lateral diffusion currents in the collector.









23

are solved simultaneously to account for the correct charge dynamics in

the collector. The time derivatives of the quasi-static stored charges

thus properly represent the distributed charging currents. Also the

inherent nonreciprocal transcapacitance of the BJT are simulated

directly, without the use of equivalent-circuit capacitors [23].

Test devices representative of the advanced BJT were used to

verify the model and to define a parameter-extraction scheme [24). Some

of the parameters can be defaulted directly from geometrical and

process information such as AE, PE, NEPI, and WEpI. Empirical

parameters of RE, RB, IS, F, PR, VA, VB, C2, C4, ne, nc, CJEO, CJCO,

me, mc, e, Oc, TF, rR are measured by standard methods [1]. Other

parameters which related to device physics are known in [25] (ni, PnO,

vs), by fitting measured and simulated IB (rnO, rpO), by estimating

PISCES results (VQNR, VDSCR).

The physical parameters of the lateral diffusion velocities

calculated from the collector lateral flow in PISCES 2-D simulation (WE

SLE) are:



AWE [Jn(x,y=O) + Jn(x,y-WE)] dx
AE ILQ(R 0
VDQNR = (2.10)


PE QQNR






AE ILSCR
VDSCR
PE QSCR


FWE[WQNR
2 WE q[n(x,y) NEPI] dxdy
Jo Jo


EPI
WE [Jn(x,y=O) + Jn(x,y-WE)] dx
JWQNR

[WE WEPI
2 JE q[n(x,y) NEPI] dxdy
J0 JWQNR


(2.11)









24

where n is the position-dependent electron carrier concentration, the x

axis is in the vertical direction, the y axis is in the horizontal

direction, y 0 stands for the left-side emitter edge, and y WE

stands for the right-side emitter edge.

The lateral diffusion velocities are in the range of 3 x 106 cm/s

to 5 x 106 cm/s due to the error introduced in the double integration

of discrete data. A fine tune-up of these parameters can be done by

optimizing (or fitting) the measured and simulated results at high IC,

and low VCE.

The simulation results of the collector current versus VCE at

different base currents from 1-D [12] and 2-D models are compared with

measurements in Fig. 2.9. In this figure, the solid line represents

measurements, the symbol x's represent 2-D model simulations, and the

circles represent l-D model simulations. It is clear that 1-D model

overestimates quasi-saturation effects. This is seen in Fig. 2.9 at

high IC and low VCE, where non-ohmic quasi-saturation dominates. The

test device measured in Fig. 2.9 has the drawn dimension WE = 2 pm, LE

- 4 pm and the approximate active emitter area AE = 1.2 x 3.2 pm2 due

to its "boot-shaped" sidewall spacer technology [26]. In order to

demonstrate the model's lateral scalability, a test device with active

emitter area AE = 0.7 x 3.2 pm2 was measured and compared with model

simulations in Fig. 2.10. Note that the lateral diffusion velocities

(VDQNR, VDSCR) used in these simulations are the same as in the

previous ones. The predictions of the present model show good agreement

when compared with the experimental results on these two different

emitter size BJT's. However, the 1-D model simulation results differ


















3.0 IB = 35 A



2.4

IB = 20 mA

< 1.8-

- 0

1.2


IB = 5 MA
0.6


0,,. 1 -- ----- --

0 0.2 0.4 0.6 0.8
VCE (V)




Figure 2.9 Plot of collector current IC versus VCE at different
IB with test device AE = 1.2 x 3.2 pm. The solid line
represents measurements, "x" represents 2-D model
simulations, and "0" represents 1-D model simulations.













































VCE (V)


Plot of collector current IC versus VCE at different
IB with test device AE = 0.7 x 3.2 pm. The solid line
represents measurements, "x" represents 2-D model
simulations, and "0" represents l-D model simulations.


Figure 2.10












significantly from measurements in quasi-saturation, especially with

the small emitter size BJT.

The 2-D and 1-D models are used to simulate a BJT (AE 1.2 x 3.2

pm2) inverter with 1.6 KQ load resistor. The input pulse waveform

consists of a 0.9 V, 50 ps ramp followed by a flat pulse of 950 ps

duration and then a falling 0.9 V ramp of 50 ps. The circuit responses

to the input pulse of the 2-D and 1-D BJT models are shown in Fig.

2.11. Both transistor models yield the same initial delay and falling

waveform for the first 100 ps. After that the 2-D BJT model predicts a

faster falling waveform that goes to a lower asymptote on the output

pulse due to higher IC, lower dQQNR/dt and dQSCR/dt. To verify model

prediction in transient operation, transient device simulation is used

for comparison. Transient measurement of a ring oscillator introduces

an extra propagation delay from the interconnect between the first and

last stages of the ring oscillator and the I/O pad capacitances which

lead to the difficulty in measuring the actual transient switching

responses [27]. The 2-D model simulations of an inverter show good

agreement with PISCES numerical results (circles in Fig. 2.10) in

transient operation which indicates that 2-D BJT model correctly

accounts for the charge dynamics and the time derivatives of the quasi-

static stored charges in the collector.



2.5 Conclusions

A circuit model for the advanced bipolar transistor including

collector current spreading effects in quasi-saturation has been

developed. The model is defined implicitly by a system of nonlinear





























2 t3=l2o0psec
I- 1.2 t2=1000psec
0


0.8



0.4 -


0 III I I I
0 0.3 0.6 0.9 1.2
TIME (x 10-9s)





Figure 2.11 Plot of the simulated transient responses of a BJT
inverter (AE = 1.2 x 3.2 pm) with load resistance 1.6 KO
for 2-D model (solid line), 1-D model (dashed line), and
PISCES simulation (circles).












equations describing base and collector transport. Two lateral

diffusion current sources were added to the l-D physical model to

account for the multidimensional currents in the collector. The lateral

diffusion currents due to a carrier concentration gradient between the

collector area under the emitter and the collector area under the

extrinsic base were investigated. It was found that the collector

current spreading mechanism, which is entirely different from the base

spreading mechanism, is independent of the drift component in the

collector, and ameliorates quasi-saturation effects in terms of current

gain and transient response. The collector spreading effect is

significant when the BJT is operated at high IC and low VCE, with low

epitaxial collector concentration, large epitaxial collector depth, or

small emitter width. SPICE simulations employing the collector

spreading model are in good agreement with the experimental results and

device simulations. The present model correctly accounts for the charge

dynamics in the collector and is scalable to small geometry BJT

resulting lateral scaling.















CHAPTER THREE
PHYSICS-BASED CURRENT-DEPENDENT BASE RESISTANCE

3.1 Introduction

The base resistance RB plays a significant role in the switching

speed and frequency response of the bipolar transistors [28] [29]. In

BJT circuit simulator models such as the Gummel-Poon model in SPICE, RB

is treated as constant with respect to applied bias [1], which in

modern BJT's is inadequate because base resistance is current

dependent.

The characterization and modeling of the BJT base resistance is a

difficult task. For the past twenty years, various methods for deriving

RB have been reported [30-34] Recently, Ning and Tang [33] developed an

elegant dc method for measuring the base and emitter resistances.

However, the accuracy of this method depends on having the intrinsic

base resistance RBI linearly proportional to the forward current gain,

3 at high currents. This method may not be applicable to modern

advanced bipolar transistors [35]. Neugroschel [34] presented an ac

method for determining RB at low currents. By varying the base-emitter

voltages, the current-dependent base resistance was characterized at

low currents. However, this ac technique can be sensitive to the

picofarad parasitic capacitances associated with probed measurements on

the integrated circuits and requires skilled experimental techniques.

In this chapter, we propose a physics-based base resistance model

taking into account a wide range of injection levels. This model, which

30










31

is discussed in Secs. 3.2 and 3.3, includes the physical effects of

base width modulation, base conductivity modulation, emitter crowding,

and base pushout. Good agreement is obtained when the new RB model is

compared with BJT measurements and a 2-D device simulations (Sec. 3.4).

In order to illustrate its usefulness, the RB model is also implemented

in the user-defined subroutines in SLICE. Then transient responses are

simulated for an ECL circuit by performing circuit simulation with the

current RB model versus the constant RB model (Sec. 3.5). Conclusions

are given in Sec. 3.6.



3.2 Physical Mechanisms for Current Dependency

In this section, the various physical mechanisms (1-D and 2-D)

that are involved in the RB determination are treated separately and

then a simple method of estimating their coupled effects is proposed.

The total base resistance of a bipolar transistor, RB is composed

of the following


RB = RBI + RBO + RCON (3.1)


where RBI is the intrinsic base resistance, RB0 is the extrinsic base

resistance, and RCON is the base contact resistance. The intrinsic base

resistance occurs in the base region between the emitter and collector,

the extrinsic base resistance occurs in the lateral extension of the

base from its intrinsic region to the base contact, and the base

contact resistance results from the ohmic contact between IC

interconnect and the base. Generally, RCON < RBI and RCON < RBO. Thus,

RCON will be neglected in this study. In addition, the RBO of a BJT is









32

almost excitation independent [36]. Thus the only current dependent

term in the right hand side of Eq. 1 is RBI. Methods for characterizing

ohmic base resistance behavior (RB0) in the BJT are presented in the

literature [33-36]. Therefore, the focus of this chapter will be on

estimating RBI from the physical mechanisms in the active base region.



3.2.1 Base Width Modulation

Figure 3.1 shows a simplified structure of n+-p-n-n+ bipolar

transistor. Using conventional terminology, the base width, Xg is the

vertical dimension between the emitter-base space-charge region (SCR)

and the collector-base space-charge region. The emitter length, LE is

defined as the dimension pointing into the figure. The cross-sectional

area of the base (perpendicular to the base current path) is determined

by the product of the quasi-neutral base width, XB and LE.

Since RBI is inversely proportional to the cross-sectional area

of the base, the modulation of the emitter-base or the collector-base

space-charge region will change the magnitude of RgB. For example,

assume that the emitter-base junction is forward-biased and there is a

constant collector-base applied voltage, VCB. Then XB is modulated by

the moving edge of the emitter-base space-charge region when VBE

changes. As VBE increases, the emitter-base space-charge region

contracts, and Xg expands. This reduces RBI because the base cross-

sectional area, XB x LE increases resulting in a larger base charge and

a larger effective Gummel number.

The variation in quasi-neutral base charge can be modeled as

QBO/(QBO+AQB) where QBO is the zero-biased intrinsic base charge


















.- BASE EMITTER
CONTACT CONTACT




SI02 P P P S 0



-1i
n .

n '
/ /











Figure 3.1 Schematic of an advanced bipolar transistor structure.
The dashed lines represent the edges of the space-charge
region.








34

(QBO AEJNB(X) dx), and AQg is the incremental base charge resulting

from base width modulation effect (AQg AEJCJE(V) dV). AE is the

emitter area, and VBE' is the base-emitter junction voltage (VBE'= the

quasi-Fermi level separation between the edges of the emitter-base

space-charge region).

To find AQB, a recently reported comprehensive l-D model for the

emitter-base junction capacitance, CJE is employed [37]:


CJE(VBE') [qe2a/12(V*-VBE')]1/3 for qNB3/(a2 (V*-VBE')] > 0.1

= [qeNB/2(V*-VBE')]1/2 for qNB3/(a2E(V*-VBE')] < 0.1

for VBE' < Vbi 0.3 (3.2)


CJE(VBE') (2qeni/VT)1/2 exp(VBE'/4VT)

for Vbi 7VT S VBE' < Vbi 5VT (3.3)


CJE(VBE') = (2qeni/VT)1/2 exp[-(VBE'-2Vbi+10VT)/4VT]

for VBE' > Vbi 5VT (3.4)


where q is the electron charge, ni is the intrinsic carrier

concentration, e is the dielectric permittivity of silicon, "a" is the

emitter-base junction impurity gradient, Vbi is the built-in junction

voltage, NBeff is the effective base doping density (NBeff -

JN(x)dx/Xg, XB is the base width), C'JE is the derivative of the

junction capacitance, V* is the effective junction built-in voltage.

For a linearly-graded junction V* (2kT/3q)/n(ckTa2/8q2ni3) [37].

The model defines parameters V1 m Vbi 0.3 and V2 Vbi 7VT. A

polynomial fit calculates the capacitance using (3.2), (3.3) and the

derivative of the capacitance (C'JE) in the region between Vbi 0.3 <










VBE' < Vbi 7VT [37].


CJE(VBE') = CJE(V1) [1-2(VBE'-Vl)/(Vl-V2)] [(VBE'-V2)/(Vl-V2)12

+ CJE(V2) [1-2(VBE'-V2)/(V2-Vl)] [(VBE'-Vl)/(V2-Vl)]2

+ C'JE(V1) (VBE'-Vl) [(VBE'-V2)/(Vl-V2)]2

+ C'JE(V2) (VBE'-V2) [(VBE'-Vl)/(V2-Vl)12

for Vbi 0.3 VI < VBE' < Vbi 7VT = V2 (3.5)


Figure 3.2 shows a plot of a base-width modulation QBO/(QBO+AQB)

versus VBE'. We define a base-width modulation factor, fBWM "

QBO/(QBO+AQB) as the vertical axis of the plot in Fig. 3.3. In general,

VBE' < VBE because of ohmic drop in the quasi-neutral region [38]. The

monotonic decrease of fBWM at low VBE' is due to the contraction of the

emitter-base SCR width shrinking. For VBE' above 0.8 V, the fBWM slope

is zero because the emitter-base SCR width can not contract further.

The base width modulation due to the base-collector SCR edge variation

in the base is neglected because modern BJT's have base doping density

much higher than their epi-layer doping density, Nepi. This results in

the SCR edge variation occurring in the epitaxial collector.



3.2.2 Base Conductivity Modulation

When a bipolar transistor (n-p-n) is in high current operation,

the hole concentration (including the excess carrier concentration) in

the base will exceed the acceptor dopantt) concentration to maintain

charge neutrality. As a result, the base sheet resistance under the

emitter decreases as the hole injection level increases. An excess base

charge, 6QB that results from this effect is given as [39]








































0 0.2 0.4 0.6 0.8


VB (v)


Figure 3.2 Plot of the base-width-modulation factor, fBWM versus the
base-emitter junction voltage, VBE'.










(2+Al+no)A2n0
6QB QBO (3.6)
(2+AI)A2/A3+n0


where A1=2[exp(r)-l]/[rexp(r)], A2-1/A1, A3-exp[(r-l)exp(r)+l]/[exp(r)-

1]2, r is the effective base doping gradient (r In[N(O)/N(XB)]), and

no is the electron concentration normalized by base doping N(O) at the

base edge of the emitter-base space-charge region. Note that no is

determined by no(l+no)-ni2/N2(0)exp(VBE'/VT)

The simulated result of base-conductivity modulation versus VBE'

is shown in Fig. 3.3. We define a base-conductivity-modulation factor,

fCM QBO/(QBO + 6QB) as the vertical axis of the plot in Fig. 3.3. The

factor, fCM stays constant at low voltages (low injection) and drops

sharply for VBE' > 0.75 V due to the presence of numerous excess

carriers (high injection) in the quasi-neutral region.



3.2.3 Emitter Current Crowding

As the base current flows through the active base region, a

potential drop in the horizontal direction causes a progressive lateral

reduction of de bias along the emitter-base junction. Consequently, the

emitter current crowding occurs at the peripheral emitter edges. Figure

3.4 shows emitter current crowding across the active base region in a

plot of the electron current density. This plot is drawn horizontally

from the middle of the emitter (x 0) to the left side emitter edge (x

- WE/2) using the two-dimensional device simulator PISCES [14]. In the

PISCES simulations, the physical features of the transistor include a 2

pm emitter width (WE/2 1 pm), a 0.1 pm emitter junction depth, XJE, a

0.2 pm base junction depth, XJB, and a 0.7 pm epi-layer depth, XEpI.










































0.2 0.4 0.6 0.8


VBE (v)


Figure 3.3 Plot of the base-conductivity-modulation factor, fCM
versus the base-emitter junction voltage, VBE'.


























20 x 104

18 x 104
16 x 10'

14 x 104
N 12 x 104
10 x 104
8 x 104 VBE=0.91V
6 6x10'

4x 104 VBE= 0.87V
2 x 104 WE/2

0 0.5 1.0 1.5



X (pm)










Figure 3.4 PISCES simulation of electron current density horizon-
tally along the emitter-base junction. In this figure,
x 0 represents the center of the emitter; the
increasing x is closer to the base contact.









40

The doping profiles are assumed Gaussian for the emitter, Gaussian for

the base, and uniform for the epi-layer. The peak dopings are 2 x 1020

cm-3, 8 x 1017 cm-3, and 2 x 1016 cm-3 in the emitter, intrinsic base,

and epi-layer, respectively. The non-uniform emitter current

distribution (Fig. 3.4) makes the effective emitter width smaller [40-

42]. Hence, emitter current crowding reduces the magnitude of RBI.

In order to analytically represent the effects of emitter

crowding, a variable named the emitter crowding factor, fCROWDING is

employed. The emitter crowding factor is defined as the ratio of the

emitter current with emitter crowding to the emitter current without

emitter crowding [40], [41], [43]:


fCROWDING IE with emitter crowding/IE without emitter crowding

WE
JE(x) dx

(3.7)

JE(0) dx



where JE(0) is the emitter current density at the emitter edge.

In general, the integration of JE(x), the non-uniform emitter

current caused by lateral ohmic drops, can not be solved analytically

[40-42], [44]. Equation (3.7) is solved numerically by using Simpson's

integration method applied to a circuit network.

The circuit network in Fig. 3.5 is used to model the current

densities at various partitioned regions. The emitter-current density

at the different emitter sections including the ohmic drops in the

quasi-neutral base and emitter region are:
























EMITTE





Bo-

BASE


COLLECT


R IR T RE1 T RE2 T RE3 T RE4 T
IEO IEi E2 E3 lE4l

---------- ------- -------
REo I R1 RB RB3 RB4


Io 1 I8 182 183 IB4
---------------------------




TOR





L

I Ic
C


Figure 3.5 Equivalent circuit representing the ohmic drops in the
quasi-neutral base and emitter regions.








42

IEO ISE/5 exp[(VBE-IBORBO-IEOREO)/VT] (3.8)


IE1 ISE/5 exp[(VBE-IBBORBO-IBRBl-IElREl)/VT] (3.9)


IE2 = ISE/5 exp[(VBE-IBORBO-IBlRB1-IB2RB2-IE2RE2)/VT] (3.10)


IE3 ISE/5 exp[(VBE-IBORB0-1BIRBl-IB2RB2-IB3RB3-1E3RE3)/VT]
(3.11)

IE4 ISE/5 exp[(VBE-IBORBO-IBIRB1-IB2RB2-IB3RB3-IB4RB4

-IE4RE4)/VT] (3.12)


where ISE is the emitter current at VBE VBE' 0 V, RBj, REj are the

emitter, base series resistances in the partitioned region j. As a

first order approximation, RBO = RBX, RBj(j-1,2,3,4) = RBI/4,

REj(j-0,1,2,3,4) 5 RE. The base currents (IBO, IB, IB2, IB3, IB4)

can also be calculated by using (3.8)-(3.12) provided ISE/5 is replaced

by ISE/(5(PF+1)]. PF is the maximum forward current gain.

Using the Simpson's integration method, the total emitter current

IE = (IE0+4El1+2IE2+41E3+IE4)/12 is calculated for a single-base-

contact BJT. The method also applies to a double-base-contact BJT in

which the equations for IE3 and IE4 should be replaced by those of IE1

and IEO due to a symmetry current crowding in the left and right halves

of the BJT. Note that the accuracy can be improved if the structure in

Fig. 3.5 is divided into more sections, but there is a trade-off in

terms of the increased CPU time. The calculated fCROWDING versus VBE is

shown in Fig. 3.6. The solid line represents the emitter crowding

factor without conductivity modulation. The dashed line represents the

emitter crowding factor with conductivity modulation. This second order

effect lessens the level of emitter current crowding and will be



































0.4



0.2



0
0









Figure 3.6


S0.2 0.4 0.6 0.8


VBE (V)


Plot of the emitter crowding factor, fCROWDING versus the
base-emitter applied voltage, VBE with RRI 480 0, RE -
20 0, ISE 10 x 10-18 A, ISB 6 x 10-22 A for a single-
base-contact BJT. The solid line represents the emitter
crowding without base-conductivity modulation and the
dashed line represents the emitter crowding with base
conductivity modulation.









44

discussed later. The emitter current crowding becomes important when

VBE > 0.85 V. In general, emitter crowding is more pronounced at high

currents (see Fig. 3.4) and for devices with large emitter width and

high intrinsic base sheet resistance.



3.2.4 Base Pushout

For bipolar transistors operating at high currents, base pushout

can occur [3]. Based on PISCES simulations, Fig. 3.7 shows hole

concentrations of a n+-p-n-n+ BJT at the emitter-collector applied

voltage, VCE 2.0 V and VBE 0.87 V, 0.91 V, and 0.95 V. Base pushout

initiates when VBE is greater than 0.87 V for the doping profile used

in Sec. 3.2.

The current-induced incremental base width, 6XB is [25]


(JO qsNEPI)/2
6XB = WEPI (1 C q ) ) for JC > J0 (3.13)
(Jc qVsNEpl)I/2


where WEPI is the epitaxial-collector width between the base-collector

junction and collector high-low junction, vs is the saturation

velocity, JC is the collector current density, and JO is the onset

collector current density for base pushout (JO

qvs(Nepi+2VcB/qWEPI2)).

The variation of base resistance due to base-widening is shown in

the plot in Fig. 3.8. We define a base-pushout factor, fPUSHOUT as the

ratio of base width, XB without base widening to base width with base

widening (XB + AXB). Thus,










































1014


DEPTH (m)


PISCES simulation of hole concentration plot along the
vertical direction at VCE 2 V, VBE 0.87 V, 0.91 V,
and 0.95 V (dashed lines). The solid line is the doping
profile from emitter to collector. Depth zero stands for
emitter surface.


Figure 3.7

















1.2



1.0
\\ \\


\\
0.8
\ \

0
'n! 0.6
0a


0.4



0.2



0 T, I -I-T- I I I I I --!-1-1-

103 104 10s



Jc (A/cm2)





Figure 3.8 Plot of the base pushout factor, fpUSHOUT versus the
collector current density, JC (A/cm ). The solid line
represents the epi-layer doping density, Nepi 2 x 1016
cm, the epitaxial collector thickness, Wepi 0.5 pm,
and the collector-base applied voltage VCB 2.0 V, the
dashed line represents Nepi 0.8 x 1016 cm3, Wepi 0.5
pm, and VCB 2.0 V, and the dotted and dashed line
represents Nepi 2 x 1016 cm3, Wepi 0.5 pm, and VCB -
3.0 V.











fFUSHOUT 1 for JC < JO,

WEPI (JO qvsNEPI)1/2
(1 + -- [1 --/2-1 for JC > JO. (3.14)
XB (JC sNEPI)1/2


Figure 3.8 shows a plot of fPUSHOUT versus JC. In Fig. 3.8, the

solid line represents BJT pushout for a collector with NEPI = 2 x 1016

cm-3, WEPI 0.5 pm, and VCB 2.0 V, the dashed line represents BJT

base pushout with NEPI 0.8 x 1016 cm-3, WEPI 0.5 pm, and VCB = 2.0

V, and the dotted and dashed line represents BJT base pushout with NEPI

- 2 x 1016 cm-3, WEPI = 0.5 pm, and VCB = 3.0 V. The base widening is

more significant when the epi-layer doping density is low, the width of

the epitaxial collector is large, or the collector-base applied voltage

is small. The base-widening increases dramatically for BJT operated at

high current densities and results in a very low fPUSHOUT-



3.2.4 The Coupling Effects

The emitter-crowding factor taking into account the conductivity

modulation, base width modulation, and base pushout in the emitter

crowding mechanism is discussed in this section. In general, the high

conductivity from high injection reduces the emitter current crowding

(see dotted line in Fig. 3.6). Also, the base width modulation and base

pushout effects result in a smaller effective base resistance. These

effects lessens the level of emitter current crowding.

To model a better emitter-crowding factor, f'CROWDING which

accounts for the second order effects (base conductivity modulation,

base width modulation, and base pushout) in the emitter crowding

mechanism, a parameter fc (fc, fBWM x fCM x fPUSHOUT) is incorporated








48

into (3.8)-(3.12). The parameter fc modifies the base resistance in

each partitioned region of the intrinsic base. Thus if base resistance

is lower due to base conductivity modulation, base width modulation, or

base pushout, the IBRBI drop due to intrinsic base resistance is

reduced in the current crowding calculation.


IEO 1SE/5 exp[(VBE-IBORBO-IEOREO)/VT] (3.15)


IEl ISE/5 exp[(VBE-IBORBO-IBlRBlfc-IE1RE1)/VT] (3.16)


IE2 ISE/5 exp[(VBE-IBORBO-BIlRBlfc-IB2RB2fc-IE2RE2)/VT] (3.17)


IE3 ISE/5 exp[(VBE-IBORBO^BlRBfc^-B2RB2fc-B3RB3fc

-IE3RE3)/VT] (3.18)


IE4 = ISE/5 exp[(VBE-IBORBO-1BlRBlfc-IB2RB2fc-B3RB3f

-IB4RB4fc-IE4RE4)/VT] (3.19)


Using (3.7), (3.15)-(3.19) together with the Simpson's method,

f'CROWDING can be calculated numerically.



3.3 The Nonlinear Base Resistance Model

The physical mechanisms for modeling the current-dependent base

resistance have been discussed in Sec. 3.2. A simple method of

estimating the combined effects of all the contributing factors in the

base resistance is to multiply then together in a liner fashion. In

fact, the multiplication of those physical factors produces a very

acceptable first order model of the current-dependent base resistance

that agrees with experiments. Thus,










49

RBI RBIO x fBM x fCM x f'CROWDING x fPUSHOUT (3.20)


where RBIO is the intrinsic base resistance at VBE 0 V. RBIO equals

WEPb/12LE for a rectangular emitter with base contact on two sides, and

WEPb/3LE for a rectangular emitter with single base contact [45]. pb is

the intrinsic base sheet resistivity at VBE 0 V.

The solid line in Fig. 3.9 represents Rg (RB = RBI + RBO)

calculated from the present model, where RB0 can be obtained through

measurements [33], [34], circuit simulation [36), or device

simulations. The gradual reduction of RB at low VBE is caused by the

emitter-base space-charge region shrinkage. The sharp decrease of RB at

high VBE is due to base conductivity modulation, base pushout, and

emitter current crowding effects.



3.4. Model Verification with Experiments

A method is developed in this section for obtaining RB at high

voltages. An ideal base current, IBideal without ohmic drops in the

quasi-neutral base and emitter regions can be defined


IBideal ISB exp(qVBE/nkT) (3.21)


where ISB is the pre-exponential base current (ISB ISE/(F+1)),

n is the nonideal base coefficient. n = 1 for metal emitter contact,

and n > 1 for a polysilicon contact BJT in the current technologies

[35].

The actual base current from measurement is [1]


IB ISB exp[q(VBE-AV)/nkT]


(3.22)

















600



500 O



400



" 300
r0


200



100



0
0 -------------------------------
0 0.2 0.4 0.6 0.8 1.0 1.2



VBE (V)





Figure 3.9 Plot of the base resistance, RB versus the base-emitter
applied voltage, VBE. The solid line represents the
simulation result from the present RB model, squares
represent PISCES simulation data, triangle represents
Ning and Tang's method data, and circles represent DC
measurement data at high currents.









51

From (3.21), (3.22) the ohmic drop AV (AV IERE + IBRB) is


AV (nkT/q)[ln(IBideal/IB)] (3.23)


1 nkT IBideal
thus RB(VBE) = (-- ln(-- ) IERE) (3.24)
IB q IB


Since Ig, ISB, and IE are known from measurement directly, n is

extracted in the intermediate current level (prior to ohmic drop

region) by (3.21), RE can be extracted from open collector method [46]

or ac method [34], and IBideal can be calculated from (3.21), the

excitation-dependent base resistance RB can be computed from (3.24).

When emitter current crowding occurs, however, the emitter resistance

RE increases due to a smaller effective emitter area. Thus, emitter-

crowding factor, f'CROWDING must be included in the RE term in (3.24)

to obtain a more accurate Rg:


1 nkT IBideal IERE
RB(VBE) - (-- ln(--- ) ) (3.25)
IB q IB f'CROWDING


The low current base resistance value, on the other hand, is

extracted from device simulations because AV is negligible compared to

VBE in low current and difficult to measure. RBI in low currents is

computed as WE2/mLE S qpp(x,y)p(x,y)dxdy where the position-dependent

hole mobility pp(x,y) and hole concentration are known from PISCES

simulations. Here, m 3 for a rectangular emitter with one base

contact, and m = 12 for a rectangular emitter with two base contacts.

Combining the above methods for RB characterization and a dc

method [33], the base resistance is obtained (Fig. 3.9). The results









52

from the present model are in good agreement with measurements. A small

derivation is present at low VBE and this is due to the fuzzy

boundaries of the moving space-charge-region edges in the PISCES

simulations.



3.5 Application

In order to demonstrate the utility of the current-dependent base

resistance model, the present model was implemented in SLICE using

user-defined subroutines [10]. Transient simulations from Gummel-Poon

model with current-dependent base resistance for an ECL circuit are

illustrated in Fig. 3.10. The ECL gate has the load resistances, RL1 -

270 0, RL2 290 0, and the current source resistance, RI = 1.24 Kn.

The input pulse waveform has logic swing from -1.55 V to -0.75 V with

20 ps ramp followed by a flat pulse of 400 ps, and then a falling ramp

of 20 ps from -0.75 to -1.55 V. Figure 3.10 indicates that the constant

base resistance chosen at low injection (dashed line) overestimates the

propagation delay of ECL logic and that the nonlinear base resistance

model (solid line) yields a more realistic switching transient in which

the base resistance changes drastically during the large-signal

transition. These simulations indicate that the existing constant RB

model is inadequate for predicting the transient performance of

advanced bipolar technologies and the current-dependent base resistance

model is superior for BJT predicting transients.





















-0.9


-1.0 RLI1 R2
-0 \ 270S 290S

-1.1 VIN (v) \ VI 1.15V
1.1 5V
/ -0.75 VOUT

-1.2 \ Ri RI=
-1.55 1.24K1 1.24K6
/ t- t2 t \t

-1.3 /t = 20 PS \ 5.2V
/ t2= 420 PS \
t3= 440 PS \
-1.4 \
/ \
/ \
/ \
-1.5 / \

1 \
-1.6 / \


-1.7
0 1 2 3 4 5 6 7 8


TIME ( x 10-s)


Figure 3.10


Transient responses from Gummel-Poon model with constant
base resistance model (dashed line) and current-depend-
ent base resistance model (solid line) for an emitter-
coupled logic inverter with an emitter follower.









54

3.6 Summary and Discussion

A physics-based current-dependent base resistance model of

bipolar junction transistors has been presented. The model is

applicable for all injection levels and accounts for the effects of

base width modulation, base conductivity modulation, base pushout, and

emitter crowding. Interactions among these effects are also treated.

The results obtained from the present model, from the two-dimensional

device simulator PISCES, and from measurement data show excellent

agreement.

We have implemented this physics-based base resistance model in

SLICE/SPICE using user-defined subroutines. For an emitter-coupled

logic circuit, the Gummel-Poon model with the present Rg model results

in a more realistic transient response compared with that of the

constant base resistance model. It is anticipated that the present

model is useful for accurate bipolar integrated-circuit simulation in

advanced IC technologies.















CHAPTER FOUR
CIRCUIT MODELING FOR TRANSIENT EMITTER CROWDING AND
TWO-DIMENSIONAL CURRENT AND CHARGE DISTRIBUTION EFFECTS

4.1 Introduction

Today's advanced bipolar transistors, resulting from double

polysilicon self-aligned technology, have been scaled down to

submicrometer emitter widths and exhibit multidimensional current flow,

especially when operated during high current transients. The one-

dimensional BJT model [12] has been extended into a quasi-2-D model,

useful for quasi-saturation, to account for the two-dimensional

collector current spreading effects. In forward active mode the emitter

current crowding will be significant if the base resistance is large

and the collector current is high. In addition, this current crowding

is enhanced during the BJT switch-on transient.

The emitter current crowding and sidewall injection effects have

been investigated by numerous authors [40-45], [47-55]. Analytical

solutions for emitter crowding were derived to formulate a distributed

circuit model [42]. The assumption of a negligible emitter ohmic drop,

IERE in [42] is not generally valid for the polysilicon bipolar

transistors since IERE can be non-negligible compared to the base ohmic

drop, IBRB. It is the author's experience that neither the distributed

model [42] nor the two-lump empirical models [48] [49] are optimal for

parameter extraction and circuit simulation in terms of CPU time. In

addition, emitter-base sidewall injection and its junction charge









56

storage effects, usually neglected in the lumped circuit models, can be

quite significant in small emitter-width VLSI BJT's.

In this chapter, an improved circuit model including nonuniform

transient current and charge distribution effects is developed. The

details of the model formulation are described in Section 4.2. In

Section 4.3 the model is verified by measurements and transient device

simulations. Conclusions are given in Section 4.4.



4.2. Model Development

A circuit model for the nonuniform current and charge

distribution resulting from transient emitter crowding and emitter-base

sidewall injection effects is discussed in this section.



4.2.1. Transient emitter crowding

As the base current flows through the active base region, a

potential drop in the horizontal direction causes a progressive lateral

reduction of dc bias along the emitter-base junction. Consequently,

emitter current crowding occurs at the peripheral emitter edges. This

nonuniform current distribution effect is enhanced in transient

operation [55], in which the base resistance and junction capacitance

contribute finite RC time constant (delay) in the base region. Thus the

emitter edge of a BJT turns on earlier than the emitter center during a

switch-on transient. Also, the charge (QBE) at the emitter edge is

larger than at the center during switching.

In order to analytically represent the emitter crowding effect, a

variable, emitter crowding factor fCR, was defined as the ratio of the








57

emitter current with emitter crowding to the emitter current without

emitter crowding (see Cahpter 3). In this Chapter, fCR is treated as

time-dependent for transient as well as steady state operation:



JE[V(x,t)]dx

fCR(t) (4.1)
JWE
0EJE[V(0,t)]dx


where JE is the position and time-dependent emitter current density, x

is the horizontal direction (x 0 is the emitter edge), t is time, and

V is the position and time-dependent junction voltage.

In general, JE(x,t), the nonuniform transient emitter current,

can not be integrated analytically [41] [46]. Equation (4.1) is solved

numerically using Simpson's integration method as


WE n/2 n/2-1
--JE(0,t)+JE(WE,t)+4 X JE[(2j-l)WE/n,t]+2 X JE(2jWE/n,t))
3n j-1 j=1
fCR -
JE(0,t)WE
(4.2)


A circuit network is used to model the current densities at

various partitioned boundaries in a three-dimensional bipolar structure

shown in Fig. 3.1. The concept of charge-based model was developed by

Jeong and Fossum [12]. This work extends the development of Chapter 3

using this charge-based concept for regional BJT partitioning. The

time-dependent lateral voltage drop, IBI(t)RBI in the intrinsic base

region is calculated using the partitioned intrinsic base series

resistance, RBj, base current, IBIj(t), and charging currents,








58

dQBEj(t)/dt and dQBCj/dt at the partioned region j.

The regional intrinsic base current IBgj(t) can be written as


IS VBEj(t) C21S VBEj(t)
IBIj [exp( )-1] + [exp( )-1]
(n+l)BF VT (n+l) VT

IS VBCj(t) C41S VBCj(t)
+ -- [exp( )-l] + [exp( )-l]
(n+l)>R VT (n+l) VT (4.3)



VBEj(t) VBE(t) IB(t)RBX IE(t)RE IBI(k-1)(t)RBk (4.4)
k=l



VBCj(t) VBC(t) IB(t)RBX IC(t)RC IBI(k-1)(t)RBk (4.5)
k=l


where RBX is the extrinsic base resistance, RBk is the regional

intrinsic base resistance (RBk 1/n RBIO x fBWM x fCM), VT is the

thermal voltage kT/q, and IS, IB, IE, IC, OF, R, RC, RE, ne, nc, C2,

and C4 retain their usual meanings in the Gummel-Poon model.

The regional base-emitter charging (transient) current is


dQBEj(t) 1 d VBEj(t)
-- (rFIs[exp( )-1] + AEfCJE[VBEj(t)]dV)
dt n+l dt VT
(4.6)


where CJE is the voltage-dependent emitter-base junction capacitance,

AE is the emitter area, and TF is the forward transit time. Similarly,

the regional base-collector charging current, dQBCj(t)/dt can be found.

The junction capacitance model in SPICE2 is based on the

depletion approximation. This simple model holds for CJC, the

collector-base junction capacitance, in which the collector-base









59

junction is reverse-biased when the BJT is at the forward active mode.

When emitter crowding occurs, however, the junction voltage across the

emitter-base space-charge region is usually high enough to invalidate

the depletion approximation for finding the emitter-base junction

capacitance. A recently developed junction capacitance model [37] which

takes into account the free carrier charges in the space-charge region

in high forward bias is therefore used in this circuit model to

determine emitter-base charging currents. The biased-dependent CJE

model can be found in Section 3.2.1.

Through the regional voltage drops which define the position and

time-dependent junction voltages, the nonuniform currents and charges

under the emitter are determined. For example, the nonuniform quasi-

static charges under the emitter are described by the position and

time-dependent regional charge, Qj(x,t) which is a function of its

junction voltage, V (x,t).

Figure 4.1 shows a partitioned circuit model including the

transient crowding effects using charge-based circuit modeling approach

[12] [23]. In Fig. 4.1 the collector current under the emitter is the

product of the current crowding factor fCR and the collector current

without emitter current crowding. The current crowding factor is

equivalent to the effective emitter area ratio (AEeff/AE) in [40] [41]

[45]. Applying (4.1)-(4.2) to the partitioned model for n = 2 yields


VBE(t)-IB(t)RBX-IE(t)RE
IC = fCR {ISexp[]
VT

VBE(t)-IB(t)RBX-IE(t)RE
+ C21Sexp[ ]) (4.7)
neVT































dOBC2 V = VBO- V
di VBE1 = VB;. VE
RB RB 81 RB2 B VBE2=VB2-VE


dOBEx dE dOBO dC3El d02
di bb 1 d o i c
'Ax -r o iY '62 Ic (VBEO VBE1 VBE2)


E'

RE

E




Figure 4.1 Network representation of the charge-based bipolar model
including the nonuniform transient current and charge
distribution effects.









61

exp[VBEO(t)]+4exp[VBEl(t)]+exp[VBE2(t)]
fCR (4.8)
6exp(VBEO(t))


where VBEO, VBEl, and VBE2 are the position and time-dependent base-

emitter junction voltages at the emitter edges (VBEO, VBE2) and emitter

center (VBEI). Note that the present model takes into account both dc

and transient emitter crowding and it can be easily reduced to a dc

model by removing the transient current sources in Fig. 4.2. In

addition, the equivalent distributed two-dimensional circuit model

avoids the convergence, grid, and cost problems associated with

transient numerical device simulations while still providing an

accurate prediction of transient current crowding (see Fig. 4.7) with

much less CPU time.



4.2.2. Sidewall Iniection Current and Junction Charge Storage Effects

When the lateral dimensions of the emitter are in the same order

of magnitude as the emitter width, the emitter-base sidewall plays a

significant role in the performance of the bipolar transistor [52]. To

accurately model the nonuniform current and charge distribution in the

advanced BJT, the emitter-base sidewall injection current and its

associated junction stored charge should be modeled. An analysis of a

PISCES simulation of an advanced bipolar transistor is performed to

identify multidimensional currents. In PISCES simulations, the BJT has

a 1.2 pm emitter width, a 0.1 pm emitter junction depth, a 0.25 pm base

junction depth, and a 0.7 pm epi-layer depth. The doping profiles are

assumed Gaussian for the emitter, Gaussian for the base, and uniform

for the epi-layer. The emitter dopant lateral straggles are assumed 75%









62

of the vertical straggles for the emitter sidewall lateral diffusion

[18]. The peak dopings are 2 x 1020 cm-3, 8 x 1017 cm-3, and 2 x 1016

cm-3 in the emitter, intrinsic base, and epi-layer, respectively. The

physical mechanisms used in PISCES simulations include Shockley-Read-

Hall recombination, Auger recombination, bandgap narrowing, and doping

and field-dependent mobility.

PISCES 2-D simulation readily shows the multidimensional current

paths as illustrated in Fig. 4.2. The figure displays the electron-

current-density and hole-current-density vector plots of the advanced

BJT biased at VBE 0.85 V and VCE 3.0 V. The current vectors suggest

that the sidewall injection contributes an important component of the

base current. A quantitative measure of the sidewall current is given

by integrating the electron current density and hole current density

along the emitter-base junction sidewall. Simulation of the current

gain versus emitter width also indicates the significance of the

sidewall injection current and the emitter-width size effect on the

current gain.

Figure 4.3 shows the f plots of three advanced BJT's with

different emitter widths. The peak P of the BJT with the 1.5 pm emitter

width is the highest followed by the peak P of the 1.0 pm emitter, and

then the peak P of the 0.5 pm emitter. The PISCES 2-D-BJT simulations

indicate the peak-current gains of the submicrometer advanced BJT's

will be reduced significantly with scaling. Since the normalized

collector currents (IC/WE) are approximately the same in these three

structures, the primary reason for peak P reduction is the emitter-base

sidewall injection current, which makes Ig not scalable. The f falloff















E B




+ n+ +
#* 4 *
+ 4 4, +1,


+ +, 4 4 4 -



4, + 4 + 4 4,


4 4, 4, 4, 4, .4, 4' 4








C
P ~*)*+Cc


Figure 4.2.1 PISCES electron-current-density vector plot at VBE -
0.85 V and VCE 3.0 V.

















E B



t t t- --
S i-
P p -- p+





n
















C


Figure 4.2.2 PISCES hole-current-density vector plot at VBE 0.85 V
and VCE 3.0 V.


















300







Z 200
< / /*'' ~"--- ^.
-, ,,

I-









0 I I I I
S100 -l i







0.4 0.5 0.6 0.7 0.8
VBE (V)






Figure 4.3 Plot of current gain versus VBE at different emitter
width, WE. The solid line represents WE 0.5 Am, the
dashed line represents WE 1.0 Am, and the dashed and
dotted line represents WE 1.5 pm.









66

at the intermediate current level before high injection occurs is due

to base-width modulation at the emitter-base junction; this effect is

significant in narrow-base BJT's [56].

Based on device simulation and analytical approximation [52]

[53], the emitter-base sidewall base current, IBX is modeled using the

ratio of the emitter perimeter to the emitter area:


PE XJE IS VBE(t)-IB(t)RBX VBE(t)-IB(t)RBX
IBX- (-exp[ ] + C21Sexp[ ])
AE F VT VT
(4.9)


where PE is the emitter perimeter and XJE is the emitter junction

depth. Note that the lateral voltage drop under the emitter is defined

as IBIRBI in the emitter crowding mechanism. The use of voltage drop

IBRBI in emitter crowding would overestimate the level of current

crowding since the base current under the emitter (IBI) can be quite

different than the base terminal current (Ig) if the base sidewall

current (IBX = IB-IBI) is significant.

As a first-order approximation, the collector current flow out of

the emitter-base sidewall can be neglected [52]. Thus the charge stored

at the emitter-base junction sidewall, QBEX is determined by the

sidewall junction capacitance, CjEX so that QBEX = PEXJEGCjEX(V)dV.

CJEX is the same as Eqs. (3.2)-(3.5) providing different values for the

junction gradient "a" and the effective junction built-in voltage V*.

Similarly, the extrinsic base-collector junction charge, QBCX

associated with the collector-base junction outside the intrinsic

emitter region is (AC-AE)fCjC(V)dV because the collector current flows

mainly in the intrinsic emitter region (see Fig. 4.3.1).








67

By combining the modeling methodologies in Secs. 4.2.1 and 4.2.2,

the nonuniform transient currents and charges in an advanced BJT can be

determined.



4.3. Model Verification with Experiments and Transient
Device Simulations

The circuit model which includes the emitter crowding (dc and

transient) and sidewall injection effects was implemented as user-

defined-controlled-sources in SLICE. In SLICE/SPICE circuit analysis,

UDCS's are user-defined subroutines (see Appendix B) that use the

implicit nonlinear model equations to compute both charging current

(dQ/dt) and transport current (I) in the model depicted in Fig. 4.1.

The time derivatives of the quasi-static stored charges in the base

thus properly represent the charge dynamics in the BJT. The lateral

voltage drops (VBE2(t) < VBEl(t) < VBEO(t) < VBE(t)) are given as the

system of model equations (I and dQ/dt) are solved simultaneously.

Transient current crowding is then accounted for in the collector

current by fcR(VBEO(t),VBEI(t),VBE2(t)).

Test devices representative of advanced BJT's were used to verify

the model and to define a parameter-extraction scheme. The devices have

drawn emitter width WE = 2 pm, emitter length LE = 8 pm and the

approximate active emitter area is AE 1.2 x 7.2 pm2 due to sidewall

spacer technology. The intrinsic and extrinsic base resistances are

obtained by Ning and Tang's method [33]. The Gummel-Poon model

parameters IS, PF, fR, 'F, rR, ne, nc, C2, C4, RE, and RC are extracted

by the methods in [1]. Some of the physical parameters are determined

from the process information (AE, PE, WE, XJE, and NB) and from [25]












(ni, V*).

The BJT is measured from VBE 0.6 V to VBE 1.0 V with VCE 3

V to keep the transistor out of quasi-saturation. The simulated results

from the present model and the Gummel-Poon model show excellent

agreement with the experimental data at low currents; however, the

simulated results from the Gummel-Poon model deviate significantly from

measurements at high currents (see Fig. 4.4). The discrepancy would be

exaggerated if Fig. 4.4 were shown on a linear scale.

Transient measurement of a ring oscillator introduces an extra

propagation delay due to the interconnect between the first and last

stages of the ring oscillator and the I/O pad capacitances which

complicate measurement of the real inverter transient response [27].

Thus, to demonstrate the model utility in transient operation, the

emitter crowding factor and pulse response of an inverter are simulated

using the present model and compared with transient device simulation

using PISCES. Figure 4.5 shows the emitter current density horizontally

along the emitter-base junction at various times in the PISCES

transient simulation. In Fig. 4.5 emitter crowding is very significant

during the initial turn-on transient. The transient crowding factors

obtained from PISCES and the present model are compared in Fig. 4.6.

The model predictions show close agreement with PISCES transient

simulations. This indicates that the lumped model in Fig. 4.1 correctly

accounts for the nonuniform transient current and charge distribution

effects. SLICE implementation employing the present model, which

includes the transient crowding effects, is used to simulate a BJT

inverter with 1.2 KD load resistor. The input pulse waveform consists















10-2


10"3 IC


10-4


10-5


10-6


10- 6


10.8


108
10-9 I \ -I \ I I
0.6 0.7 0.8 0.9 1.
VBE (V)




Figure 4.4 Log I versus base-emitter applied voltage, VBE. The solid
line represents the present model simulation, the dashed
line represents the Gummel-Poon model simulation, and the
circles represents the measurement.
















1.2



1.0-


t=940 PS

0.8
St=227 PS

0.6

t=126 PS

0.4

t=89 PS

0.2

t=62 PS

o f I jI i I i
0 1.0 2.0 3.0
x (gim)




Figure 4.5 Electron current density distribution horizontally along
the emitter-base junction at various times in PISCES
transient simulation.
















1.0



0.8




0.6



0.4




0.2 -





0 0.2 0.4 0.6 0.8

TIME (x109S)





Figure 4.6 Plot of the emitter crowding factor versus time. The
solid line represents SPICE simulation employing the
present model, and the circles represent PISCES
simulation.










72

of a 0.85 V, 50 ps ramp followed by a flat pulse of 1200 ps duration

and then a falling 0.85 V ramp of 50 ps. Figure 4.7 shows the inverter

transient responses from SPICE/SLICE (using the Gummel-Poon model and

the present model) and PISCES. The predictions of the present model are

in good agreement with PISCES results; however, the Gummel-Poon model

shows a slower turn-on transient and a large propagation delay. The

discrepancy between the Gummel-Poon and PISCES results is due to the

nonuniform transient current and charge distribution in PISCES

simulation which lowers the magnitude of the base impedance during

switching. The use of a lumped base resistance measured at steady-state

in the Gummel-Poon model predicts more delay than is actually observed.



4.4 Summary and Discussion

A new circuit model for the advanced bipolar transistor including

nonuniform transient current and charge distribution effects has been

developed. The model takes into account the transient emitter crowding

mechanism, emitter-base sidewall injection, and extrinsic junction

charge storage effects. The spatially partitioned model is developed

based on physical insight gained from device simulations (dc and

transient). Although the partitioning technique itself is

straightforward, the present model represents the nonuniform current

and charge distribution at the emitter-base sidewall and under the

emitter in a unified manner. Furthermore, second order effects such as

base-width modulation and base conductivity modulation, which decrease

the intrinsic base resistance and emitter crowding are easily modeled

in the equivalent circuit through a correction factor for the effective














3.5


Vc = 3V

VIN
3.0 0.85V R L= 1.2 Kf2
0.85V
0 t t VIN VOUT


-\ t = 50 ps
S2.5- \ t2= 1250 ps
S\ t3= 1300 ps
>O



2.0 -





1 .5 I I I I I I II I I
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
TIME (xlO 9S)





Figure 4.7 Simulated transient responses for a single-transistor
inverter. The solid line represents the present model
simulation, the dashed line represents the Gummel-Poon
model simulation, and the circles represents PISCES
transient simulation.









74

base charge. SLICE simulations employing the present model show

excellent agreement with measurements and device simulations. Since the

model correctly represents the charge dynamics of the BJT in transient

operation, it is anticipated that the present model can be useful in

advanced bipolar (or BiCMOS) modeling in technology computer-aided

circuit design and process sensitivity diagnosis.















CHAPTER FIVE
S-PARAMETER MEASUREMENT PREDICTION USING A PHYSICAL
DEVICE SIMULATOR

5.1 Introduction

Submicrometer emitter bipolar transistors produce small signal

responses that are difficult to characterize with existing s-parameter

equipment. State of the art probes, and proper calibration technique

have proven essential in the measurement of s-parameters of single BJT

test structure [57]. However, s-parameter measurements cannot predict

the test-structure response of new BJT technologies in the "on paper"

development stage.

A new method of predicting s-parameter test structure response

from physical device simulator output has been developed. This

predicted s-parameter response is particularly useful for examining the

performance of conceptual designs of submicron BJT technologies.

Submicrometer BJT's have significant dc, transient and small-signal

multidimensional effects which include collector current spreading,

emitter crowding, and emitter-base sidewall injection; these effects

have been evaluated by a 2-D physical device simulator previously [58]

[59] and are discussed in Chapters 2, 3, and 4. The new method of

predicting s-parameter response provides a direct comparison between 2-

D BJT simulations and measurement data from BJT test structures.

Important uses of this simulated s-parameter response also

include verifying BJT test structure s-parameter measurements and










76

previous BJT characterizations. The derived BJT test structure response

can be used to confirm the accuracy of existing test structures

measurements, potentially reducing the total number of test structures,

measurements, and cost necessary to characterize a BJT technology.

In order to get a complete characterization of a 3-port BJT,

three sets of 2-port measurements must be taken, generally requiring 3

separate test structures. Since the 3-port measurement is time

consuming and IC layout area intensive, often only a single 2-port BJT

measurement is made. The s-parameter prediction technique can

supplement an existing 2-port test structure measurement so that a

complete 3-port BJT characterization is possible. The simulated s-

parameter response also can be extended beyond s-parameter

instrumentation frequency ranges.

This modeling technique is demonstrated using submicrometer BJT

simulations from the PISCES 2-D physical device simulator [60]. Other

small-signal device simulations or characterizations [61) could be

substituted for the PISCES data. Simulated small-signal BJT y-parameter

measurements are converted (via software) to s-parameters. S-parameter

measurements are preferred for high-frequency characterizations and

have been demonstrated on-chip at frequencies up to 50 GHz [62]. In

addition, s-parameter best represent a distributed circuit with high

frequency discontinuities [63], such as a BJT IC test structure

measured at microwave frequencies. The BJT s-parameter response is

incorporated into a BJT test structure model which includes the effects

of IC interconnects, discontinuities and bond pads. The predicted s-

parameter response for the BJT test structure is then calculated and









77

plots of the BJT test structure responses are presented. This modeling

technique proves extremely useful for evaluating IC test structure

characteristics.

This is the first time that the high frequency BJT test structure

circuit modeling has been combined with a 2-D device simulation output

in order to predict test structure s-parameter response. In addition, a

novel two-layer metal-based BJT test structure with low attenuation is

examined using this modeling. The modeling algorithms presented here

may be applied in inverse fashion to extract accurate BJT small signal

characteristics from s-parameter measurements or evaluate the accuracy

of s-parameter calibration algorithms.



5.2 Bipolar Test Structure Modeling

In order to demonstrate the utility of the bipolar test structure

modeling, an n-p-n BJT small-signal response was simulated using the

PISCES program. The physical features of the BJT include a 1 pm emitter

width (WE 0.5 pm), a 0.1 pm emitter-depth, a 0.2 pm base-depth, and a

0.8 pm epitaxial collector-depth shown in Fig. 2.1.1. The doping

profiles are shown in Fig. 2.1.2. Small-signal parameters from l-D, 2-

D, or 3-D simulator may be used for input in this test structure

modeling technique.

A 2-D simulation typically provides BJT y-parameter response up

to the emitter contact, base contact, and collector contact. During y-

parameter simulations the BJT is biased at VBE = 0.8 V. and VCE = 2.0 V

and the frequency is varied from 10 MHz to 7 GHz. The y-parameters are

normalized by the distributed circuit admittance (frequency dependent









78

interconnect admittance) and then converted to s-parameters. The y-

parameter to s-parameter conversion equations are [64]:


(1-yll)(1+y22) + Y12Y21
S11 (5.1)
(I+yll)(+y22) Y12Y21


-2y12
s12 (5.2)
(1+yll)(l+y22) Y12Y21


-2y21
s21 (5.3)
(1+Yll)(I+Y22) Y12Y21


(1+yll)(1-y22) + Y12Y21
s22 = (5.4)
(1+yll)(l+y22) Y12Y21


In order to predict the s-parameter response of a specific BJT

test structure layout, an equivalent high frequency circuit must be

constructed. An example BJT test structure layout which is frequently

used for s-parameter measurements is presented in Fig. 5.1. Here, the

BJT is positioned between three bond pads that are connected to the

transistor by IC interconnect. The bond pads are 100 pm by 100 pm and a

bend is added to the IC interconnect between the base terminal and the

base bond pad. The interconnect, the bond pads and the bend exhibit

parasitic responses at microwave frequencies.

A flow chart which outlines the calculation of the BJT test

structure response is shown in Fig. 5.2. The physical dimensions and

doping profiles of the submicron BJT are entered into the device

simulator program and dc and ac simulations are performed in order to

predict y-parameters. These y-parameters are converted to s-parameters




























































Figure 5.1 BJT test structure layout typically used for s-parameter
measurement.












ADVANCED BIPOLAR
TRANSISTOR DESCRIPTION



PIECES DC & AC SIMULATIONS

Y PARAMETERS

CONVERT TO S PARAMETERS
NORMALIZE TO INTERCONNECT IMPEDANCE



CASCADE TEST STRUCTURE LAYOUT DISCONTINUITY
EFFECTS WITH INTRINSIC BJT RESPONSE MODELS



NORMALIZE TO 50Q S PARAMETER
MEASUREMENT ENVIRONMENT



S11 S12

2, S22


Figure 5.2 Flow chart outlining the calculation of the BJT test
structure measurement.









81

after normalization by the on-chip interconnect admittance. Then the

BJT s-parameters are cascaded with the s-parameter responses of the BJT

layout elements (interconnect, bond pads and a bend in interconnect).

Figure 5.3 is a block diagram showing the order in which the

matrix models of the interconnect, bend in interconnect and bond pads

are cascaded. The BJT simulation (shown in the middle of the cascaded

matrices) is multiplied by the surrounding component matrices. In order

to do this, the s-parameter data in each component matrix are converted

to readily cascaded high frequency T-parameters which are similar to

low frequency ABCD parameters [63]. The cascaded T-parameter matrices

are multiplied in order to model the BJT test structure response at the

bond pads and the result is converted back to s-parameters.

The s-parameters at the bond pads, which are normalized by the

on-chip interconnect admittance, are converted to a 50 0 system

impedance that is common to s-parameter instrumentation. This

conversion employs the following equations [63]:


(Z2 Z02) sinhyl
Sll = S22 = (5.5)
2ZZOcoshyl + (Z2+Z02)sinhyl



2ZZO
S21 = S21 = (5.6)
2ZZ0coshyl + (Z2+Z02)sinhTl


In these equations, Z is the transmission line impedance, ZO is the

system impedance (50 0), is the propagation constant (v a + jip), a

is the attenuation constant, 9p is the phase constant, and 1 is the

transmission line length.



















































Figure 5.3 Cascade of the BJT test structure components and PISCES
simulations for calculating s-parameter response.









83

Analytical circuit models from the microwave literature are used

to represent the effects of IC interconnect and bends. The bond pads

are treated as a section of wide lumped admittance since a probe or

ball bond touches most of the bond pad area. The value of the bond pad

admittance was estimated by calculating the lumped admittance of a

short section of interconnect of the same dimensions as the bond pad.

The microwave model for the bend in the interconnect was taken from the

literature [63].

An IC interconnect cross-section with microstrip metal over Si02

over the Si substrate is used for the BJT test structure layout. Then a

novel two-layer-metal IC interconnect is examined as a superior

interconnect alternate. Fig. 5.4 displays a cross-section of a metal-

SiO2-Si microstrip interconnect cross-section. In Fig. 5.4 the width of

the metal line is 20 pm, the thickness of the metal line is 1 pm, the

thickness of the Si02 layer is 1 pm, the thickness of the Si substrate

is 300 pm, and the resistivity of the Si substrate is 1 0-cm.

The transmission-line model for this interconnect system has a

series impedance per unit length and a parallel admittance per unit

length as shown in Fig. 5.5. The series impedance, Z is composed of R,

the interconnect-line resistance plus L, the interconnect-line

inductance. The parallel admittance of the transmission line includes

the SiO2 capacitance, C1, in series with the parallel combination of

the Si capacitance, C2, and the Si conductance, G2. The IC interconnect

equations presented below are valid when the Si substrate layer is

moderately to lightly doped [65] [66]:


L ~o F(hl+h2)


(5.7)




Full Text

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MODELING AND CHARACTERIZATION OF ADVANCED BIPOLAR TRANSISTORS AND INTERCONNECTS FOR CIRCUIT SIMULATION BY JIANN-SHIUN YUAN A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 1988 U OF F LIBRARIES

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UNIVERSITY OF FLORIDA 3 1262 08552 3446

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ACKNOWLEDGMENTS I wish to express my sincere appreciation to the chairman of my supervisory committee, Professor William R. Eisenstadt, for his guidance and encouragement during the course of this study. I also thank Professors Sheng S. Li, Arnost Neugroschel, Gijs Bosman, and C. K. Hsieh for their valuable comments and participation on my supervisory committee. I am grateful to my colleagues, Dr. S. Y. Yung, Mr. H. Jeong for their helpful discussions, J. Atwater, G. Riddle for photoconductive switch measurements and sample preparation. Special thanks are extend to Dr. Juin J. Liou; his participation on the qualifying exam and on the final defense merits a note of gratitude. I am greatly indebted to my wife, Hui-Li, my parents and parentsin-law for their love, patience, and encouragement. The financial support of the Semiconductor Research Corporation and the National Science Foundation is acknowledged.

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TABLE OF CONTENTS Page ACKNOWLEDGMENTS ii LIST OF SYMBOLS vi ABSTRACT xiv CHAPTER ONE INTRODUCTION 1 TWO TWO-DIMENSIONAL COLLECTOR CURRENT SPREADING EFFECTS IN QUASI -SATURATION 5 2 . 1 Introduction 5 2.2 Multidimensional Collector Current Spreading 7 2.3 SPICE Modeling Including Collector Spreading Effects... 17 2.4 Model Verification with Experiments and Device Simulations 21 2 . 5 Conclusions 27 THREE PHYSICS-BASED CURRENT -DEPENDENT BASE RESISTANCE 30 3 . 1 Introduction 30 3.2 Physical Mechanisms for Current Dependency 31 3.2.1 Base Width Modulation 32 3.2.2 Base Conductivity Modulation 35 3.2.3 Emitter Current Crowding 37 3.2.4 Base Pushout 44 3.2.4 The Coupling Effects 47 3.3 The Nonlinear Base Resistance Model 48 3.4 Model Verification with Experiments 49 3.5 Application 52 3.6 Summary and Discussion 52 FOUR CIRCUIT MODELING FOR TRANSIENT EMITTER CROWDING AND TWODIMENSIONAL CURRENT AND CHARGE DISTRIBUTION EFFECTS 55 4 . 1 Introduction 55 111

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4 . 2 Model Development 56 4.2.1 Transient Emitter Crowding 56 4.2.2 Sidewall Injection Current and Junction Charge Storage Effects 61 4.3 Model Verification with Experiments and Transient Device Simulation 67 4.4 Summary and Discussion 72 FIVE SPARAMETER MEASUREMENT PREDICTION USING A PHYSICAL DEVICE SIMULATOR 75 5 . 1 Introduction 75 5 . 2 Bipolar Test Structure Modeling 77 5.3 Bipolar Test Structure SParameter Response 90 5 .4 Conclusions 98 SIX INTEGRATED CIRCUITS INTERCONNECT MODEL FOR SPICE 102 6 . 1 Introduction 102 6.2 Interconnect Modeling Topology Development 103 6.3 Advanced IC Interconnect Cross-section Analysis Ill 6.4 Interconnect Model Verification 115 6 . 5 Mixed-Mode Circuit Simulation 118 6 . 6 Svimmary and Discussion 128 SEVEN MODELING FOR COUPLED INTERCONNECT LINES 129 7 . 1 Introduction 129 7.2 Even Mode and Odd Mode Analyses for Two Parallel Lines 130 7.3 Signal Dispersion, Loss and Coupling for Coupled Transmission Lines 136 7.4 Mode Transition in Photonic Picosecond Measurement .... 145 7 . 5 Equivalent Circuit Model for SPICE 148 7 . 6 SPICE simulations and Discussions 152 7 . 7 Conclusions 154 EIGHT SUMMARY AND DISCUSSIONS 161 APPENDICES A TWO-DIMENSIONAL NUMERICAL SIMULATION WITH PISCES 164 A. 1 Introduction 164 A. 2 Physical Mechanisms in PISCES II 164 A. 3 Discussion 166 B BIPOLAR TRANSISTOR MODELING IMPLEMENTATION TECHNIQUES IN SLICE/SPICE 168 B.l Introduction 168 B.2 User-Def ined-Controlled-Sources 168

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B.3 UDCS Implementation of the BJT Model 173 B.4 Conclusions 175 REFERENCES 178 BIOGRAPHICAL SKETCH 188

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LIST OF SYMBOLS Aq collector area Ag emitter area Aggff effective emitter area a emitter-base junction gradient CC Coupling coefficient for signal crosstalk CjQ collector-base junction capacitance Cjco collector-base junction capacitance at Vgg = V Cjg emitter-base junction capacitance Cj£x extrinsic emitter-base junction capacitance C'jg derivative of emitter-base junction capacitance Cjgo emitter-base junction capacitance at Vgg = V CgcR space -charge region capacitance Csj^02 Si02 capacitance Cg even mode capacitance for coupled transmission lines Cg^ even mode capacitance for coupled transmission lines without dielectric interface Cf fringing capacitance Cf' modified fringing capacitance C„^gate capacitance due to finite metal thickness Cq odd mode capacitance for coupled transmission lines Cq^ odd mode capacitance for coupled transmission lines without dielectric interface Cp plate capacitance

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•^sub C2 C4 Efn Epp Ei Et f fBWM fc fCR(t) fCM ^CROWDING f CROWDING fc fD fpUSHOUT fx h2 Ib substrate capacitance forward low current nonideal base current coefficient reverse low current nonideal base current coefficient speed of light Auger coefficient for electron in heavy doping effects Auger coefficient for hole in heavy doping effects electron quasi-Fermi level hole quasi-Fermi level intrinsic Fermi level trap energy level frequency base width modulation factor critical frequency in frequency -dependent permittivity time -dependent emitter crowding factor base conductivity modulation factor emitter crowding factor without the coupling effects emitter crowding factor with the coupling effects parameter incorporating the second order effects in the emitter crowding mechanism critical frequency for frequency-dependent permittivity of coupled transmission lines base pushout factor bipolar transistor cut-off frequency conductance of n"^ buried layer height of the Si02 layer height of the substrate base current

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^Bideal ideal base current with ohmic drops in the base and emitter regions Igj base current in the partitioned region j 1q collector current ic collector current in the base quasi-neutral region Iq collector current in the collector quasi -neutral region Iq^^^ collector current in the collector space-charge region Ig emitter current Ig^ emitter current in the partitioned region j II lateral diffusion current in the collector quasi-neutral region j^SCR lateral diffusion current in the collector space-charge region Ij^ knee current Ij^ reverse knee current Ig collector current at Vgg = V Igg pre -exponential base current Igg emitter current at Vgg = V Lg emitter length Jq collector current density Jg(x) position-dependent emitter current density Jjj electron current density Jq onset of the collector current density for base pushout k Boltzmann's constant Lg emitter length 1 transmission line length nig collector-base junction gradient coefficient nig emitter-base junction gradient coefficient

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N^ acceptor doping density of p-type Si Ng(x) base doping density at depth x Ngeff effective base doping density Nj) donor doping density of n-type Si Ngpi epitaxial layer doping density n nonideal base coefficient n^ nonideal collector-base emission coefficient Uq nonideal emitter-base emission coefficient nj[ intrinsic carrier density nj^e effective intrinsic carrier density no electron concentration normalized by NgCO) An excess electron density Pg emitter perimeter p(x,y) position dependent hole mobility p average excess hole density Qg(-; base-collector charge QgQX extrinsic base-collector junction charge QgQ^ base-collector charge in the partitioned region j Qgg base -emitter charge QggX base -emitter sidewall junction charge Qgg^ base-emitter charge in the partitioned region j QgO intrinsic base charge at Vgg = V Qqjjj^ charge in the collector quasi -neutral region QgQg^ charge in the collector space-charge region AQg incremental intrinsic base charge due to base width modulation ix

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5Qb incremental intrinsic base charge due to base conductivity modulation q electron charge q]5 normalized base charge Rg base resistance Rgj intrinsic base resistance RgjO intrinsic base resistance at Vgg = V RB4 base series resistance in the partitioned region j RgX extrinsic base resistance R^ collector resistance R(;;ON base contact resistance R£ emitter resistance Rg4 emitter series resistance in the partitioned region j R'gpj currentdependent epi-layer resistance T absolute temperature t' interconnect line thickness t time tj^ height of the Si02 layer t2 height of the Si buried layer t3 height of the Si substrate V^ Early voltage Vg "late" voltage Vgc applied base-collector voltage Vgc' base-collector junction voltage VgQj base -collector voltage at the moving boundary between the collector quasi -neutral region and the collector space -charge region Vgcj base-collector charge in the partitioned region j

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Vgco base-collector voltage at the metallurgical basecollector region Vgg applied base-emitter voltage VgE^ base-emitter junction voltage in the partitioned region j Vgg' base -emitter junction voltage V^j^ junction built-in voltage VQg applied collector-base voltage VcE applied collector-emitter voltage Y^QNR lateral diffusion velocity in the collector quasi-neutral region Vj)^^^ lateral diffusion velocity in the collector space-charge region Vf thermal voltage kT/q V* effective junction built-in voltage AV ohmic drops in the emitter and base regions Vp® even-mode phase velocity of propagated signal in coupled transmission lines Vp° odd-mode phase velocity of propagated signal in coupled transmission lines Vg electron saturation velocity Wg emitter width Wqnr collector quasi-neutral region width WgcR collector space-charge region width Wgpj epitaxial collector width Xg base width Xepi epitaxial layer depth XjB base junction depth XjE emitter junction depth xi

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^e

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csi02 relative permittivity of silicon dioxide €r relative permittivity £re effective relative permittivity c^g® effective permittivity of coupled transmission lines in even mode £^6° effective permittivity of coupled transmission lines in odd mode eg permittivity of free space (^(, collector-base junction potential (^g emitter-base junction potential r effective base doping gradient rp bipolar transistor forward transit time T^ doping-dependent electron recombination lifetime T-^Q electron recombination lifetime at low doping fp doping-dependent hole recombination lifetime TpO hole recombination lifetime at low doping fQjj^ injectionlevel -dependent hole recombination lifetime in the collector quasi-neutral region TR bipolar transistor reverse transit time /ijjQ electron mobility /ip(x,y) position-dependent hole mobility fiQ permeability of free space p resistivity of the conducting microstrip p^ intrinsic base sheet resistivity at Vgg = V '^METAL conductivity of metal line ag£ conductivity of silicon agulj conductivity of substrate xiii

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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy MODELING AND CHARACTERIZATION OF ADVANCED BIPOLAR TRANSISTORS AND INTERCONNECTS FOR CIRCUIT SIMULATION BY JIANN-SHIUN YUAN December 1988 Chairman: William R. Eisenstadt Major Department: Electrical Engineering This dissertation discusses the modeling of two-dimensional effects in advanced bipolar transistors (BJT's) and interconnects. The goal is to develop accurate and compact models for SPICE circuit simulation of advanced bipolar technologies. After reviewing base pushout mechanism in the bipolar transistor, the collector current spreading effects in quasi-saturation have been presented. A twodimensional circuit model including collector spreading effects in the epitaxial collector is developed based on the physical insights gained from PISCES device simulations. Illustrative measurements and simulations demonstrate the bipolar circuit modeling accuracy.

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Then a physics-based current-dependent base resistance model for circuit simulation is developed. Physical mechanisms such as base width modulation, base conductivity modulation, emitter crowding, and base pushout are accounted for in the comprehensive current -dependent base resistance "model. Comparisons of the model predictions with measurements and device simulations show excellent agreement. Two-dimensional circuit modeling is developed for the nonuniform current and charge distribution effects at the emitter-base sidewall and under the emitter during switch-on transients. The charge and current partitioning implemented in the bipolar transistor model treats the transient emitter crowding and current -dependent base resistance in a unified manner. Good agreement is obtained between model predictions and experimental results and transient device simulations. In parallel to the work on fast BJT digital transients, the bipolar transistor high-frequency small-signal s-parameter prediction using a physical device simulator is developed. This is a novel result which includes the effects of the Intrinsic bipolar response as well as the parasitics of interconnects, discontinuities, and bonding pads. This modeling technique can be used for sophisticated three-port or four-port network characterization and for predicting the highfrequency small-signal parameters other types of transistors. The dissertation examines the improvement of IC interconnect models. Interconnect models including losses and dispersion are developed for advanced BJT IC doping profiles. In addition, signal crosstalk between adjacent interconnects is discussed. An ECL ring oscillator with interconnection line in mixed-mode circuit simulation

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demonstrates the utility and necessity of accurate interconnect modeling. In summary, the dissertation provides a comprehensive twodimensional circuit and interconnect modeling for advanced bipolar IC techniques useful in computer-aided device and circuit design. xvi

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CHAPTER ONE INTRODUCTION The bipolar transistor (BJT) circuit model implemented in SPICE (the Gummel-Poon model) is derived based on one -dimensional device physics. Recently, the bipolar transistor has been scaled down to one micrometer emitter width. It exhibits the multidimensional current flow, especially when operated in high current transients rendering onedimensional analysis inadequate. Thus, accurate device characterization and optimal integrated circuit (IC) fabrication process enhancement, through device and circuit simulations require better modeling of the advanced bipolar transistor. In addition, the interconnect delay in the submicrometer integrated circuits becomes increasing important during high speed transients. To precisely predict the BJT circuit performance, an accurate modeling of interconnect is essential. These facts motivate this study. The general topology of this study is, first, to explore the importance of the multidimensional current flow by investigating the physical insight into the two-dimensional device simulations, and, second, to develop a representative two-dimensional circuit model for circuit simulation. The model developed describes the nonuniform current and charge distribution in the quasi-neutral base, the emitterbase sidewall, and the collector. The model shows good agreement when compared with measurements and device simulations.

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2 Then, an interconnect model is developed based upon the firstorder approximation and physical device simulation. The BJT circuit model and the IC interconnect model are integrated together for digital circuit simulation. The results of this study are directly applicable to advanced bipolar transistors and BiCMOS devices. In Chapter Two, we developed a circuit model of the collector current spreading effects in quasi -saturation for advanced bipolar transistors. The discussion in this chapter reveals the importance of lateral current spreading in the epitaxial collector when base pushout occurs. The lateral diffusion currents ameliorates the quasi-saturation effects compared to one dimensional BJT model. Physical insight into the charge dynamics in the collector is shown by examining the current gain and hole concentration plots in PISCES simulations for 1-Dcollector and 2-D-collector BJT's. Also, dc and transient circuit simulations at high currents are compared with measurements to demonstrate the model utility and accuracy. Chapter Three presents a physics-based currentdependent base resistance model for all levels of injection. The model includes the 1D and 2-D physical mechanisms of base width modulation, base conductivity modulation, emitter current crowding, and base pushout; it describes a current and voltage -dependent base resistance. Various measurement results and device simulation data are compared with the model predictions to demonstrate the model accuracy. For an emittercoupled logic circuit, the BJT with a current -dependent Rg model results in a more realistic transient response compared with a BJT with constant base resistance model.

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3 In Chapter Four, the author develops a partitioned circuit model taking into account the emitter crowding, sidewall current injection, and current -dependent base resistance in a unified manner. The model describes a nonuniform transient current and charge distribution under the emitter and at the emitter-base sidewall. This current and charge partitioning accurately represents the charge dynamics of the BJT during switchon transient. The model predictions shows good agreement when compared with measurements and transient device simulations. Chapter Five describes the s -parameter measurement prediction using a physical device simulator for advanced bipolar transistors. The prediction not only includes the intrinsic BJT small signal responses, but also accounts for the parasitic effects resulting from the interconnects, bends and pads. The intrinsic BJT small signal sparameters are converted from y-parameters simulated in PISCES. The terminal responses are obtained by multiplying the cascaded T-matrix components representing the intrinsic BJT and extrinsic layout parasitic effects. Two interconnect cross-sections are compared to evaluate which is a superior test structure that introduces less signal attenuation and phase. In general, this technique can be used for three or four port network analysis and for the devices other than the BJT, such as GaAs heterojunction bipolar transistors in high frequency characterization. In Chapter Six, the conventional interconnect model is improved. A new interconnect model which accounts for signal loss and dispersion is introduced for advanced IC cross -section profiles. An inverse Fourier transform is used for modeling transients. The prediction of

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4 the interconnect model shows good agreement when compared with measurement. The model is implemented in SLICE/SPICE for mixed-mode circuit simulation. The utility of the interconnect model is demonstrated in a five -stage ECL ring oscillator transient simulation. In Chapter Seven, the single interconnect model is extended to include crosstalk for coupled interconnect lines in close proximity. Signal crosstalk is important in digital switching. The model is developed from even mode and odd mode interconnect capacitance analysis. The picosecond transient measurement of photoconductive circuit element technique has been used to demonstrate the even mode and odd mode pulse splitting. An equivalent distributed, lumped circuit model for coupled interconnect lines is also developed. Circuit simulations employing the coupled transmission lines in digital switching have been used to demonstrate the signal crosstalk between interconnects. The discussion in this chapter supplements Chapter 6, thus providing a more complete interconnect modeling analysis. Chapter Eight siommarizes the contributions of this dissertation and presents recommendations for extension of this study.

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CHAPTER TWO TWO-DIMENSIONAL COLLECTOR CURRENT SPREADING EFFECTS IN QUASI -SATURATION 2 . 1 Introduction Advanced self-aligned bipolar transistors based on a double polysilicon technology show multidimensional current flow in the collector, especially when operated at high currents. The multidimensional current flow effects are not included in existing bipolar circuit-simulator models such as the Gummel-Poon model in SPICE2 [1]. Recently, a novel 3-D BJT circuit model has been developed by using a 2-D device simulator [2]; however, the details of the collector spreading physical mechanism and the implementation in the equivalent circuit model have not been treated. The quasi-saturation effects have been investigated by numerous authors for the past twenty years [3-8]. In general, two distinct models (one -dimensional and two-dimensional) have been developed. In the 1-D model, base push-out or quasi-saturation effect occurs when the current density is high enough that the intrinsic base-collector metallurgical junction becomes forward biased. Then carriers are injected into the epitaxial collector [3], [8]. In the two-dimensional model, there is a maximum current density, called space -charge -limited current flow, and any further increase in collector current results in a 2-D base spreading [4] , [5] . Detailed explanations for the operating regions of each mechanism are shown in [6-8]. 5

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6 For the standard advanced BJT process, however, the heavily doped extrinsic base resulting from the double polysilicon technology makes base spreading negligible. In contrast, the base push-out due to high current in the collector is two-dimensional and results in lateral collector current spreading in the epitaxial collector [9], [10]. This collector current spreading, which is different from base spreading, has not previously been modeled. Recently, Kull et al . [11] extended the Gummel-Poon model to include quasi-saturation, or base push-out in the BJT circuit model formulation. Kull's compact extension was modified by Jeong and Fossum [12] [13] to account for the possible existence of a current -induced space -charge region in the epitaxial collector. The modeling in [11] [12] is based a one -dimensional derivation and does not represent the two-dimensional currents in the collector. Thus, this modeling can overestimate quasi-saturation effects [9], [10]. In this chapter, the model in [12] is extended to take into account the multidimensional collector-current-spreading mechanism that occurs in quasi-saturation. The extension is facilitated by using the two-dimensional device simulator PISCES [14] to perform simulations of the advanced BJT's (Sec. 2.2). The PISCES simulations reveal the physical mechanism producing 2-D collector spreading. The mechanism was not reported in the previous BJT simulations [9], [15]. The modeling of collector transport in [12] [13] is modified to account for the lateral diffusion currents in the epitaxial collector region. The development of this modeling is described in Sec. 2.3. Comparisons of the model performance with measurements and device simulations are presented in

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7 Sec. 2.4. Excellent agreement in dc and transient behavior is observed over a wide range of operating conditions. 2. 2 Multidimensional Collector Current Spreading An analysis of PISCES simulations of the advanced bipolar transistor was undertaken to identify the physical origin of the collector current spreading in the epitaxial collector. The BJT simulations with PISCES include heavy-doping effects (bandgap narrowing, Auger recombination), doping and field dependent carrier mobilities, and Shockley-Read-Hall (SRH) recombination. A generic advanced BJT cross -section was constructed by incorporating common features of many state-of-the-art transistors reported in the literature [16] , [17] . The advanced bipolar transistor is illustrated in Fig. 2.1, where only half cross-section and doping profile need to be simulated due to the cross-section's symmetry. The emitter and base doping profiles and the emitter-base spacing were designed to avoid sidewall tunneling and perimeter punchthrough in the BJT [18] . Polysilicon contacts are simulated for the emitter and the base by using an effective surface recombination velocity of 3 x 10^ cm/s [19]. The substrate contact is situated at the bottom of the buried collector. It is found that only a negligible perturbation on the lateral current flow in the lightly doped epitaxial collector results when a side-collector contact is used; this is discussed later in the paper. A PISCES simulation predicted the multidimensional current flow in the collector and this is shown in Fig. 2.2. This diagram displays the

PAGE 25

(0,0) (1.0,0) (0,1.0) (1.0,1.0) Figure 2.1.1 A right half cross-section of an advanced bipolar transistor used for multidimensional current studies, Dimensions of the cross -section are indicated in micrometer.

PAGE 26

1x10' EXTRINSIC BASE PROFILE I L 0.2 0.4 0.6 0.8 DEPTH INTO SILICON (iim) 1.0 Figure 2.1.2 The doping profiles of the bipolar transistor shown in Figure 2.1.1. The solid line is the doping profile at the center of the emitter and the dashed line is the doping profile below the extrinsic base region.

PAGE 27

10 (0,0) (0,1.0) 1 B (0.5,0) 1^ I If 1 Hii 1 imuiii ! ! ! 1 iminii I 11*1 uuv\ut V i 1 i i 1 1 i I Mi i I i I I I I I I I I 1 I I I I I iuwuu lUWUU UWUll 1 1 1 \\\\\\\ \ \ \\\\\\\\\ \ \ \ \u\\\w \ \ \ wwwu \ \ wwwu \ \ \ \ \ \ \ \ lUUUli \ I WUIHU i — r I I i I I (1.0,0) \ \ J (1.0,1.0) Figure 2.2 Plot of electron current vectors in the advanced BJT shown in Figure 2.1. In this PISCES simulation the collector contact is at the bottom of the buried collector at Vq^ 2.0 V and VgE 0.9 V.

PAGE 28

11 PISCES simulation of the electron-current-density-vector plot, J-^, of the advanced BJT biased at applied collector-emitter voltage, V^g = 2.0 V and applied base -emitter voltage, Vgg = 0.9 V (I^ 0.5 mA//im) . In the quasi -saturation region depicted in Fig. 2.2, excess carriers are injected into the epitaxial collector (base pushout) . These excess electrons diffuse laterally in the epitaxial collector region under the extrinsic base due to the high carrier concentration gradient in the horizontal direction. Collector current spreading is indicated by the horizontal component of current -density vectors underneath the extrinsic base. Note that Fig. 2.2 qualitatively shows where the multidimensional collector currents occur, but it does not lend itself to a quantitative estimation of the magnitude of these currents. The grid in Fig. 2.2 is nonuniform (for better simulation accuracy and convergence) and dense at emitter, base, and emitter-base junction because of the positiondependent doping density at these regions. The magnitudes of the current -density vectors at the grid points which are sparsely located are enhanced when compared to those of dense grid points. The effect of electric field in the buried collector on the current distribution in the epitaxial collector can be seen by shifting the collector contact to the right-side of the BJT. Figure 2.3 shows a BJT simulation from PISCES of the current-density vectors for a rightside-collector contact, with Vq£ = 2.0 V and Vgg = 0.9 V, the same bias as that of Fig. 2.2. Although there is a great difference in the current vectors in the buried collector (due to lateral ohmic drop) , all the currents in the intrinsic BJT remain virtually the same. The

PAGE 29

12 (0,0) (0,1.0) \ \ 1 *\ \ i I 1 I 1 I i I I 1 (0.5,0) i UUUUi \ iUUUU I iUUUU I imuui i 1 1 umii \uuuui \\\\\m \\\\\\\iu i \ 1 I M 1 1 \ \ WWUllll \ \ \ \ \ ^ 1 — I I I uuim — r T \ * I V ^ \ ^ ^ ^ (1.0,0) 1 — } — ^ — r ^ XX (1.0,1.0) Figure 2 . 3 Plot of electron current vectors in the advanced BJT shown in Figure 2.1. In this PISCES simulation the collector contact is at the side of the buried collector at VcE 2.0 V and VgE 0.9 V.

PAGE 30

13 magnitudes of the vertical and lateral current -density vectors in Fig. 2.2 and Fig. 2.3 are typically within 0.5% of each other. This indicates that the electric field from the right-side collector contact only controls the current flow in the buriedcollector region, and that it does not significantly affect the lateral flow. Thus, there is no significant drift component in the collector spreading mechanism. A 1-D-collector transistor was simulated in order to isolate the effects of collector spreading in the advanced BJT operation. This 1-Dcollector BJT, shown in Fig. 2.4, has the same emitter and base regions as the 2-D BJT in Fig. 2.1; however, below the extrinsic base region of the 1-D-collector transistor, the epitaxial and buried-collector regions are replaced with Si02. This forces the collector current to flow solely in the vertical direction below the intrinsic base, hence the name 1-D-collector transistor. Comparing the current gain, P and cut-off frequency, fj of the 2-D BJT to those of the 1-D-collector BJT at high currents is one of the keys to understanding the role of collector current -spreading. The 2-D BJT exhibits a larger /9 (see Fig. 2.5) and f^ than the 1-D-collector BJT as both transistors are driven further into saturation [10]. Figure 2.6 indicates how quasi-saturation is ameliorated by lateral diffusion in the collector. This figure displays a hole concentration plot for a vertical slice along the center of the emitter of both the 2-D BJT and 1-D-collector BJT. This simulation is performed for BJT's with emitter width, Wg = 1 /xm, Vgg = 0.9 V, and V^g; = 2.0 V. The base in the 1-D BJT displays significantly more base widening than the 2-D-collector BJT, which results in an enhanced 2-D-BJT ji , and fj

PAGE 31

14 (0.5,0) (1.0,0) P* SiO, (1.0,1.0) Figure 2.4 An advanced bipolar transistor cross-section designed with a 1-D-collector . This transistor is used to isolate the 2-D collector spreading effects.

PAGE 32

15 o u u

PAGE 33

16 0.4 0.6 DEPTH {[im) 1.0 Figure 2.6 Plot of hole concentration from the center of the emitter to the collector at Vqe 2.0 V and VgE 0.9 V. The solid line represents the 2-D BJT and the dashed line represents the 1-D-collector BJT.

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17 at high currents. The reduced quasisaturation effects in 2-D-BJT are due to the lateral diffusion current which results from the high carrier concentration gradient in the horizontal direction. Further simulation of current spreading at different emitter widths, with the same doping profiles and boundary conditions as in Fig. 2.2, indicates that the lateral diffusion current is not a function of Wg, but a function of normalized charge Q(Ic.VcE>%)/^E °^ ^^^ charge below the emitter periphery. 2.3 SPICE Modeling Including Collector Spreading Effects A semi-empirical model was developed using PISCES simulation to suggest analytical approximations that would predict collector current spreading. This modeling of the collector spreading effect was incorporated into an existing charge-based 1-D BJT model [12] to yield a quasi-2-D model. The 1-D BJT model accounts for quasi-saturation (ohmic and non-ohmic) by describing the collector current in terms of the quasi-Fermi potentials at the boundaries of the epitaxial collector which, in conjunction with the base transport, characterizes Iq(Vbe,Vbq). Since this charge-based 1-D model correctly accounts for the 1-D BJT physics [12] it can be modified to incorporate the multidimensional current effects in the advanced BJT. In the formulation of the 2-D model, we estimate the lateral diffusion currents in the collector quasi-neutral region and the collector space -charge region (II^^^^ and II^^^) as a function of the normalized 1-D-collector quasi-neutral region charge and space-charge region charge (Qqnr/Ae ^"^ QsCrAe> ^E ^^ ^he emitter area). These

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18 normalized excess charges are the sources of the lateral diffusion currents. Empirical lateral diffusion velocities (V])^ and V^^^^) are estimated from the collector lateral current flow predicted by PISCES BJT simulation. These lateral diffusion velocities multiplied by the respective normalized charges and emitter perimeter, Pg form the lateral diffusion currents. The current and voltage dependence of the lateral diffusion currents are implicitly accounted for in the model by the collector charges Qqnr(IC'^CE) ^"^ QsCR(^C'^CE) • Figure 2.7 shows the base transport current, IqQNB ^^ ^j^g quasi-neutral base, collector transport currents, I^Q^^ and 1^^^^ in the collector quasi-neutral region, and Iq and II ^^ the collector space-charge region. In Fig. 2.7 a moving boundary between collector quasi -neutral region and collector space-charge region defines the collector quasi-neutral region width, Wqfjj^ and the collector space-charge region width, WgQj^ (^SCR ~ ^EPI'^QNR' ^^'^ ^EPI i^ the epitaxial collector width). The following equations incorporate the collectorspreading mechanism into the 1-D model and make it a 2-D model: I^QNB =. i^QNR + i^QNR (2.i) I^QNR = i^SCR + i^SCR (2.2) IC^"^ = Is/qb [exp(VBE'AT) " expCVgco/VT) 1 + C2ls exp[VBE'/(neVT)] (2.3) Vt 1+F(Vbco) ^bco-'^bci I^QNR {F(Vbco) F(Vbci) ln[ ] + } R'ePI 1+F(Vbci) Vx (2.4) IC^C^ q Ae (Nepi + An) Vg (2.5)

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19 1/2 1°^" 1/2 if^" EO QNB 6 B QNR iSCR W. QNR 1/2 1°^" 1/2 II Wepi SCR -OC Figure 2.7 Regional BJT schematic used to show the transport currents associated with their regions and boundaries,

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20 IlQNR VdQNR (Qqnr/Ae) Pe (2.6) II^^^ Vd^^^ (Qscr/Ae) Pe (2-7) where R'epi QQNR/(MnONEPlAE) . F(V) [1 + aexpCVAx) ] ^/^ . VbCO = [EFN(0)-EFp]/q, a = 4ni2/NEpi2, ^BCI = [EFN(WQNR)-EFp]/q. ^T = l^^Vq. QqNR' QsCR' ''^QNR' ^^^ ^^ ^^^ defined in [12]. The notation used in the equations above is as follows: Nepi is the epitaxial collector doping concentration, nj^ is the intrinsic carrier concentration, Vg is the saturation velocity, h-^q is the electron mobility, Epjq is the electron quasi-Fermi level, Epp is the hole quasiFermi level, VgE* Is the base-emitter junction voltage, and Ig, q^, C2 , and ng retain their meanings given in the Gummel-Poon model [1]. Figure 2.8 displays the overall SPICE model topology of the 2-D model for collector spreading. Two new current sources which are highlighted in the figure have been added to the 1-D-BJT model [12] to account for the lateral diffusion currents in the epitaxial collector. Note that, since the 2-D model modifies the 1-D BJT quasi-static charge in the collector region, the transient currents dQgf^j^/dt and dQgcp^/dt are effectively refined in terms of this new quasi-static charge distribution as Eqs . (2.1) -(2. 7) are solved simultaneously. A 1-D BJT model can not represent this collector charge redistribution [12] and gives erroneous estimates of the BJT transient performance [10]. In contrast, the 2-D BJT circuit model correctly accounts for the charge

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21 dynamics in the collector and the moving boundary between the quasi neutral region and the space-charge region in the epitaxial collector. In addition, collector conductivity modulation, which makes the collector resistance small, is accounted for in the modified R'gpj that is a function of the varying quasi-neutral collector width, ^QNR(-'-C'^CE) • ^ component of base recombination current, Qqnr/^QNR ^^^ to a finite recombination lifetime, rqNR in the collector quasi-neutral region [20] is also included in the base current, Ig. The injectionlevel -dependent lifetime (tq^jr) can be modeled as [21] : P '"QNR = '"pO + ''nO (2.8) P + Nepi Qqnr q A-E Wqnr (2.9) where t-^q is the electron recombination lifetime, and t^q is the hole recombination lifetime in SRH recombination model. 2.4 Model Verification with Experiments and Device Simulations The circuit model which includes collector current spreading was implemented in the user-defined controlled-sources (UDCS's) available in SLICE, the Harris Corporation enhanced version of SPICE. In the SPICE circuit analysis, UDCS's are user-defined subroutines that use the implicit nonlinear model equations to compute both charging current (dQ/dt) and transport (I) currents [22] (see Appendix B) in the model as depicted in Fig. 2.8. The underlying transport currents in Sec. 2.3

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22 dQQNR/dt Rb tWAt dQec'tlt 'b® (t) ^ dOsE^dt (!) (i)sc. (?)' L QNR (^,QNR (t) dQscR/dt (t) SCR C QNB "C *E Figure 2.8 Network representation of the circuit model including collector current spreading effects. The bold lines are lateral diffusion currents in the collector.

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23 are solved simultaneously to account for the correct charge dynamics in the collector. The time derivatives of the quasi-static stored charges thus properly represent the distributed charging currents. Also the inherent nonreciprocal transcapacitance of the BJT are simulated directly, without the use of equivalent-circuit capacitors [23]. Test devices representative of the advanced BJT were used to verify the model and to define a parameter-extraction scheme [24]. Some of the parameters can be defaulted directly from geometrical and process information such as Ag, Pg, Ngpj , and Wgpj . Empirical parameters of Rg, Rb. IsPF' ^R' ^A' '^B^2' ^4, i^e , n^ , Cjeq. Cjcq , mg, m^,, 4>Q, (f)^, rp, rj^ are measured by standard methods [1]. Other parameters which related to device physics are known in [25] (n^, /inO> ^s) . by fitting measured and simulated Ig (''nO' ''pO) > ^Y estimating PISCES results {V^P^^ , Vp^CR) . The physical parameters of the lateral diffusion velocities calculated from the collector lateral flow in PISCES 2-D simulation (Wg < Lg) are: Vd QNR ^ Pe Qqnr We QNR [Jn(x,y=0) + Jn(x,y=WE)] dx "'QNR q[n(x,y) Ngpj] dxdy (2.10) Vd SCR Ae II SCR We Wepi [Jn(x,y=0) + Jn(x,y=WE)] dx ^QNR Pe Qscr Wepi q[n(x,y) Nepi ] dxdy ''QNR (2.11)

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24 where n is the position-dependent electron carrier concentration, the x axis is in the vertical direction, the y axis is in the horizontal direction, y stands for the left-side emitter edge, and y Wg stands for the right-side emitter edge. The lateral diffusion velocities are in the range of 3 x 10" cm/s to 5 X 10° cm/s due to the error introduced in the double integration of discrete data. A fine tune -up of these parameters can be done by optimizing (or fitting) the measured and simulated results at high 1q, and low V^g . The simulation results of the collector current versus V^g at different base currents from 1-D [12] and 2-D models are compared with measurements in Fig. 2.9. In this figure, the solid line represents measurements, the symbol x's represent 2-D model simulations, and the circles represent 1-D model simulations. It is clear that 1-D model overestimates quasi -saturation effects. This is seen in Fig. 2.9 at high 1q and low V^g, where non-ohmic quasi -saturation dominates. The test device measured in Fig. 2.9 has the drawn dimension Wg = 2 /xm, Lg = 4 ^m and the approximate active emitter area Ag 1.2 x 3.2 /xm due to its "boot-shaped" sidewall spacer technology [26]. In order to demonstrate the model's lateral scalability, a test device with active emitter area Ag 0.7 x 3.2 pm^ was measured and compared with model simulations in Fig. 2.10. Note that the lateral diffusion velocities (^D ' ^D ) used in these simulations are the same as in the previous ones. The predictions of the present model show good agreement when compared with the experimental results on these two different emitter size BJT's. However, the 1-D model simulation results differ

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25 3.0 2.4 ei.8 E o 1.2 0.6 Ir = 35 ^^A Figure 2.9 Plot of collector current I^ versus V^g at different Ig with test device Ag ~ 1.2 x 3.2 /im. The solid line represents measurements, "x" represents 2-D model simulations, and "0" represents 1-D model simulations.

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26 1.5 1.2 ^ 0.9 E o 0.6 0.3 OSh Ib = 5 M-4 ^ g & 8 8 0.4 0.6 Vce(V) 1.0 Figure 2.10 Plot of collector current I^ versus V^g at different Ig with test device A^ = 0.7 x 3.2 fxm. The solid line represents measurements, "x" represents 2-D model simulations, and "0" represents 1-D model simulations.

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27 significantly from measurements in quasisaturation, especially with the small emitter size BJT. The 2-D and 1-D models are used to simulate a BJT (Ag = 1.2 x 3.2 /xm^) inverter with 1.6 Kfl load resistor. The input pulse waveform consists of a 0.9 V, 50 ps ramp followed by a flat pulse of 950 ps duration and then a falling 0.9 V ramp of 50 ps. The circuit responses to the input pulse of the 2-D and 1-D BJT models are shown in Fig. 2.11. Both transistor models yield the same initial delay and falling waveform for the first 100 ps. After that the 2-D BJT model predicts a faster falling waveform that goes to a lower asymptote on the output pulse due to higher Iq, lower dQoNR/dt and dQgcg^/dt. To verify model prediction in transient operation, transient device simulation is used for comparison. Transient measurement of a ring oscillator introduces an extra propagation delay from the interconnect between the first and last stages of the ring oscillator and the I/O pad capacitances which lead to the difficulty in measuring the actual transient switching responses [27]. The 2-D model simulations of an inverter show good agreement with PISCES numerical results (circles in Fig. 2.10) in transient operation which indicates that 2-D BJT model correctly accounts for the charge dynamics and the time derivatives of the quasi static stored charges in the collector. 2 . 5 Conclusions A circuit model for the advanced bipolar transistor including collector current spreading effects in quasi-saturation has been developed. The model is defined implicitly by a system of nonlinear

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28 2.4 Vcc = + 2V r (O-O-O-OO J L 0.3 0.6 TIME (X 10"^s) 0.9 1.2 Figure 2.11 Plot of the simulated transient responses of a BJT inverter (Ag ~ 1.2 x 3.2 /im) with load resistance 1 . 6 Kfl for 2-D model (solid line), 1-D model (dashed line), and PISCES simulation (circles) .

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29 equations describing base and collector transport. Two lateral diffusion current sources were added to the 1-D physical model to account for the multidimensional currents in the collector. The lateral diffusion currents due to a carrier concentration gradient between the collector area under the emitter and the collector area under the extrinsic base were investigated. It was found that the collector current spreading mechanism, which is entirely different from the base spreading mechanism, is independent of the drift component in the collector, and ameliorates quasi -saturation effects in terms of current gain and transient response. The collector spreading effect is significant when the BJT is operated at high I^ and low V^g, with low epitaxial collector concentration, large epitaxial collector depth, or small emitter width. SPICE simulations employing the collector spreading model are in good agreement with the experimental results and device simulations. The present model correctly accounts for the charge dynamics in the collector and is scalable to small geometry BJT resulting lateral scaling.

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CHAPTER THREE PHYSICS -BASED CURRENT -DEPENDENT BASE RESISTANCE 3 .1 Introduction The base resistance Rg plays a significant role in the switching speed and frequency response of the bipolar transistors [28] [29] . In BJT circuit simulator models such as the Gummel-Poon model in SPICE, Rg is treated as constant with respect to applied bias [1], which in modern BJT's is inadequate because base resistance is current dependent . The characterization and modeling of the BJT base resistance is a difficult task. For the past twenty years, various methods for deriving Rg have been reported [30-34] Recently, Ning and Tang [33] developed an elegant dc method for measuring the base and emitter resistances. However, the accuracy of this method depends on having the intrinsic base resistance Rgj linearly proportional to the forward current gain, P at high currents. This method may not be applicable to modern advanced bipolar transistors [35]. Neugroschel [34] presented an ac method for determining Rg at low currents. By varying the base-emitter voltages, the current-dependent base resistance was characterized at low currents. However, this ac technique can be sensitive to the picofarad parasitic capacitances associated with probed measurements on the integrated circuits and requires skilled experimental techniques. In this chapter, we propose a physics-based base resistance model taking into account a wide range of injection levels. This model, which 30

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31 is discussed in Sees. 3.2 and 3.3, includes the physical effects of base width modulation, base conductivity modulation, emitter crowding, and base pushout. Good agreement is obtained when the new Rg model is compared with BJT measurements and a 2-D device simulations (Sec. 3.4). In order to illustrate its usefulness, the Rg model is also implemented in the user-defined subroutines in SLICE. Then transient responses are simulated for an ECL circuit by performing circuit simulation with the current Rg model versus the constant Rg model (Sec. 3.5). Conclusions are given in Sec. 3.6. 3 . 2 Physical Mechanisms for Current Dependency In this section, the various physical mechanisms (1-D and 2-D) that are involved in the Rg determination are treated separately and then a simple method of estimating their coupled effects is proposed. The total base resistance of a bipolar transistor, Rg is composed of the following Rg = Rbi + RbO + RCON (3.1) where Rgj is the intrinsic base resistance, Rgg is the extrinsic base resistance, and Rcqn ^^ ^^^ base contact resistance. The intrinsic base resistance occurs in the base region between the emitter and collector, the extrinsic base resistance occurs in the lateral extension of the base from its intrinsic region to the base contact, and the base contact resistance results from the ohmic contact between IC interconnect and the base. Generally, RcoN ^ ^BI ^^^ ^CON ^ ^BO • Thus, RqON will be neglected in this study. In addition, the Rgg of a BJT is

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32 almost excitation independent [36]. Thus the only current dependent term in the right hand side of Eq. 1 is Rgj . Methods for characterizing ohmic base resistance behavior (Rgo) ^" ^^^ ^^ ^^® presented in the literature [33-36]. Therefore, the focus of this chapter will be on estimating Rgj from the physical mechanisms in the active base region. 3.2.1 Base Width Modulation Figure 3.1 shows a simplified structure of n'^-p-n-n'^ bipolar transistor. Using conventional terminology, the base width, Xg is the vertical dimension between the emitter-base space-charge region (SCR) and the collector-base space-charge region. The emitter length, Lg is defined as the dimension pointing into the figure. The cross-sectional area of the base (perpendicular to the base current path) is determined by the product of the quasi-neutral base width, Xg and Lg. Since Rgj is inversely proportional to the cross -sectional area of the base, the modulation of the emitter-base or the collector-base space-charge region will change the magnitude of Rgj . For example, assume that the emitter-base junction is forward-biased and there is a constant collector-base applied voltage, V(]g. Then Xg is modulated by the moving edge of the emitter-base space-charge region when Vgg changes. As Vgg increases, the emitter-base space-charge region contracts, and Xg expands. This reduces Rgj because the base crosssectional area, Xg x Lg increases resulting in a larger base charge and a larger effective Gummel number. The variation in quasi-neutral base charge can be modeled as QgO/(Qgo+^QB) where Qgg is the zero-biased intrinsic base charge

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33 Figure 3.1 Schematic of an advanced bipolar transistor structure. The dashed lines represent the edges of the space-charge region.

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34 (QbO " AeJNb(x) dx) , and AQg is the incremental base charge resulting from base width modulation effect (AQg = AgJCjECV) dV) . Ag is the emitter area, and Vgj;' is the base-emitter junction voltage (Vg£'= the quasi-Fermi level separation between the edges of the emitter-base space-charge region). To find AQg, a recently reported comprehensive 1-D model for the emitter-base junction capacitance, Cjg is employed [37]: Cje(Vbe') = [qe2a/12(V*-VgE')]V3 for qNgVCa^e (V*-VgE' ) ] > 0.1 = [q€Ng/2(V*-VgE')]V2 for qNgVCa^e (V*-VgE' ) ] < 0.1 for Vgg' < Vbi 0.3 (3.2) Cje(Vbe') = (2q£ni/VT)V2 expCVgE'/^Vi) for Vbi 7Vx < VgE' < Vbi SVj (3.3) Cje(Vbe') = (2q£niAT)^/^ exp[ (VgE' -2Vbi+10Vx)/4VT] for VgE' > Vbi 5Vx (3.4) where q is the electron charge, ni is the intrinsic carrier concentration, e is the dielectric permittivity of silicon, "a" is the emitter-base junction impurity gradient, Vbi ^^ the built-in junction voltage, Nggff is the effective base doping density (Nggff jN(x)dx/Xg, Xg is the base width), C'je is the derivative of the junction capacitance, V is the effective junction built-in voltage. For a linearlygraded junction V* = (2kT/3q)ln(£kTa2/8q2ni3) [37]. The model defines parameters Vi = Vbi " ^-^ and V2 = Vbi " ^V^. A polynomial fit calculates the capacitance using (3.2), (3.3) and the derivative of the capacitance (C'je) in the region between Vbi 0.3 <

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35 Vbe' < Vbi 7Vt [37]. Cje(Vbe') = Cje(Vi) [1-2(Vbe'-Vi)/(Vi-V2)] [ (Vbe' -V2)/(Vi-V2) ] ^ + Cje(V2) [1-2(Vbe'-V2)/(V2-Vi)] [ (Vbe' -Vi)/(V2-Vi) ] 2 + C'je(Vi) (Vbe'-Vi) [(Vbe'-V2)/(Vi-V2)]2 + C'je(V2) (Vbe'-V2) [(Vbe'-Vi)/(V2-Vi)]2 for Vbi 0.3 Vi < Vbe' < Vbi 7Vx V2 (3.5) Figure 3.2 shows a plot of a base-width modulation Qbo/(QbO"''^Qb) versus Vbe' • ^^ define a base -width modulation factor, fBWM = Qbo/(QbO'^^Qb) ^^ ^^^ vertical axis of the plot in Fig. 3.3. In general, Vbe' "^ ^BE because of ohmic drop in the quasi-neutral region [38]. The mono tonic decrease of fBWM ^^ '-°^ ^BE' ^^ ^'^^ ^° ^^^ contraction of the emitter-base SCR width shrinking. For Vbe' above 0.8 V, the fBWM slope is zero because the emitter-base SCR width can not contract further. The base width modulation due to the base -collector SCR edge variation in the base is neglected because modern BJT's have base doping density much higher than their epilayer doping density, Ngpj^. This results in the SCR edge variation occurring in the epitaxial collector. 3.2.2 Base Conductivity Modulation When a bipolar transistor (n-p-n) is in high current operation, the hole concentration (including the excess carrier concentration) in the base will exceed the acceptor (dopant) concentration to maintain charge neutrality. As a result, the base sheet resistance under the emitter decreases as the hole injection level increases. An excess base charge, 6Qb that results from this effect is given as [39]

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36 V„P (v) Figure 3.2 Plot of the base -width-modulation factor, fgWM versus the base-emitter junction voltage, Vgg' .

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37 (2+Ai+no)A2no SQb = QbO (3.6) (2+Ai)A2/A3+no where A;l==2 [exp(r ) -l]/[r exp(r ) ] , A2=l/A]^, A3=exp[ (t l)exp(r)+l]/[exp(r ) o 1]^, r is the effective base doping gradient (r = ln[N(0)/N(Xg) ] ) , and nQ is the electron concentration normalized by base doping N(0) at the base edge of the emitter-base space-charge region. Note that ng is determined by no(l+no)=n£^/N^(0)exp(Vgg'/V'j') . The simulated result of base -conductivity modulation versus Vgg' is shown in Fig. 3.3. We define a base-conductivity-modulation factor, ^CM ^ Qbo/(QbO "^ *Qb) ^^ t^^ vertical axis of the plot in Fig. 3.3. The factor, fcj^ stays constant at low voltages (low injection) and drops sharply for Vgg' > 0.75 V due to the presence of numerous excess carriers (high injection) in the quasi-neutral region. 3.2.3 Emitter Current Crowding As the base current flows through the active base region, a potential drop in the horizontal direction causes a progressive lateral reduction of dc bias along the emitter-base junction. Consequently, the emitter current crowding occurs at the peripheral emitter edges. Figure 3.4 shows emitter current crowding across the active base region in a plot of the electron current density. This plot is drawn horizontally from the middle of the emitter (x = 0) to the left side emitter edge (x = Wg/2) using the two-dimensional device simulator PISCES [14]. In the PISCES simulations, the physical features of the transistor include a 2 /im emitter width (Wg;/2 = 1 /im) , a 0.1 /^m emitter junction depth, Xjg, a 0.2 pm base junction depth, Xjg, and a 0.7 /im epi-layer depth, Xgpj .

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38 1.0 V„P (v) 'BE Figure 3.3 Plot of the base-conductivity-modulation factor, fc^ versus the base -emitter junction voltage, Vgg' .

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39

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40 The doping profiles are assumed Gaussian for the emitter, Gaussian for the base, and uniform for the epilayer. The peak dopings are 2 x lO'^" cm'-^, 8 X lO-*-' cm"-^, and 2 x lO-*-" cm"^ in the emitter, intrinsic base, and epi -layer, respectively. The non-uniform emitter current distribution (Fig. 3.4) makes the effective emitter width smaller [4042]. Hence, emitter current crowding reduces the magnitude of Rgx • In order to analytically represent the effects of emitter crowding, a variable named the emitter crowding factor, f CROWDING ^^ employed. The emitter crowding factor is defined as the ratio of the emitter current with emitter crowding to the emitter current without emitter crowding [40] , [41] , [43] : ^CROWDING ^ ^E with emitter crowding/^E without emitter crowding We Je(x) dx (3.7) PWe Je(0) dx where Je(0) is the emitter current density at the emitter edge. In general, the integration of Je(x) , the non-uniform emitter current caused by lateral ohmic drops, can not be solved analytically [40-42], [44]. Equation (3.7) is solved numerically by using Simpson's integration method applied to a circuit network. The circuit network in Fig. 3.5 is used to model the current densities at various partitioned regions. The emitter-current density at the different emitter sections including the ohmic drops in the quasi-neutral base and emitter region are:

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41 EMITTER Rbo B o ^A/ BASE Ibo f |ReqJ^ REii^ "£2^^ Re3^^ Re4^ COLLECTOR 'EO »B1 A/V'B1 -A/V'E2 'B3 .JWAA/'B4 Figure 3.5 Equivalent circuit representing the ohmic drops in the quasi-neutral base and emitter regions.

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42 IeO =Ise/5 exp[(VBE-lBoRBO-lEOREO)AT] (3-8) IeI = Ise/5 exp[(VBE-lBORBO-lBlRBl-lElREl)AT] (3-9) Ie2 = Ise/5 exp[(VBE-lB0RB0-lBlRBl-lB2RB2-lE2RE2)AT] (3.10) Ie3 = IsE/5 exp[(VBE-lB0RB0-lBlRBl-lB2RB2-lB3RB3-lE3RE3)AT] (3.11) Ie4 = Ise/5 exp[(VBE-lBoRBO-lBlRBl-lB2%2-lB3RB3-lB4RB4 -IE4Re4)/VT] (3.12) where I^e is the emitter current at Vbe = ^BE' = V, Rbi , Ret ^^^ the emitter, base series resistances in the partitioned region j . As a first order approximation, Rbq = RbX' Rbi (J^-'> ^ . 3 ,4) = Rbi/4 , Rej(J=0,1,2,3,4) = 5 Rg. The base currents (Ibq, IbI . Ib2 . Ib3 . Ib4) can also be calculated by using (3. 8) -(3. 12) provided Ise/^ ^^ replaced by Ise/(5(^p+1) ] . ^p ^^ ^^^ maximum forward current gain. Using the Simpson's integration method, the total emitter current Ie = (Ieo+'^Ie1''"2Ie2''"^-'-E3'*"-^E4)/-'-2 ^^ calculated for a single-basecontact BJT. The method also applies to a double -base -contact BJT in which the equations for Ie3 and Ie4 should be replaced by those of Iei and Ieo due to a symmetry current crowding in the left and right halves of the BJT. Note that the accuracy can be improved if the structure in Fig. 3.5 is divided into more sections, but there is a trade-off in terms of the increased CPU time. The calculated fcROWDING versus Vbe ^^ shown in Fig. 3.6. The solid line represents the emitter crowding factor without conductivity modulation. The dashed line represents the emitter crowding factor with conductivity modulation. This second order effect lessens the level of emitter current crowding and will be

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43 0.8 a z Q $ O (T O Vbf. (v) Figure 3.6 Plot of the emitter crowding factor, fcROWDING versus the base-emitter applied voltage, Vgg with Rrj 480 fi, R-g 20 n, IsE 10 X 10"^^ A, IsB 6 X 10"2"^A for a singlebase-contact BJT. The solid line represents the emitter crowding without base-conductivity modulation and the dashed line represents the emitter crowding with base conductivity modulation.

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44 discussed later. The emitter current crowding becomes important when Vgg > 0.85 V. In general, emitter crowding is more pronounced at high currents (see Fig. 3.4) and for devices with large emitter width and high intrinsic base sheet resistance. 3.2.4 Base Pushout For bipolar transistors operating at high currents, base pushout can occur [3]. Based on PISCES simulations. Fig. 3.7 shows hole concentrations of a n"'"-p-n-n"*' BJT at the emitter-collector applied voltage, VcE 2.0 V and VgE = 0.87 V, 0.91 V, and 0.95 V. Base pushout initiates when Vgg is greater than 0.87 V for the doping profile used in Sec. 3.2. The current -induced incremental base width, 5Xg is [25] (Jo qVsNEPi)V2 5Xb = Wepi {1 -—) for Jc > Jo (3.13) (Jc qvsNEPi)^/^ where Wepx is the epitaxial-collector width between the base-collector junction and collector highlow junction, Vg is the saturation velocity, J^ is the collector current density, and Jq is the onset collector current density for base pushout (Jo = qVs(Nepi+2VcB/qWEPI^))The variation of base resistance due to base-widening is shown in the plot in Fig. 3.8. We define a base-pushout factor, fpuSHOUT ^^ ^^^ ratio of base width, Xg without base widening to base width with base widening (Xg + AXg) . Thus,

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45 \ \ '\ Vbe=0.87V \Vbe=0.9\iV Vbe=0.95V \ \ \ 0.2 0.4 0.6 0.8 1.0 DEPTH (fxm) Figure 3.7 PISCES simulation of hole concentration plot along the vertical direction at Vcg 2 V, VgE 0.87 V, 0.91 V, and 0.95 V (dashed lines). The solid line is the doping profile from emitter to collector. Depth zero stands for emitter surface.

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46 1.2 1.0 0.8 0.6 0.4 0.2 J I I I I I L_l_ 10^ 10^ 10= Jc(A/cm^) Figure 3.8 Plot of the base pushout factor, fpuSHOUT versus the collector current density, J^ (A/cm^) . The solid line represents the epi-layer doping density, N epi cm"-', the epitaxial collector thickness, Wgpi and the collector-base applied voltage, V^g dashed line represents Ngpi 0.8 x lO-*-" cm'-^ ~ V, and " 2 X 10 16 2 X 10 0.5 urn, 2.0 V, the W, epi 0.5 um, and V(-n 2.0 V, and the dotted and dashed line ^16 cm-3, represents 3.0 V. N epi W, epi 0-5 Mm> and Vq^ -

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47 fpUSHOUT " 1 f°^ Jc < -JQ' Wepi (>Jo qvsNEPi)-'"/^ , = {1 + [1 ])-! for Jc > Jo(3.14) Xfi (Jc qvsNEPi)^/^ Figure 3.8 shows a plot of fpuSHOUT versus J^. In Fig. 3.8, the solid line represents BJT pushout for a collector with Ngpj = 2 x 10-'-° cm'^, Wgpj = 0.5 /im, and V^g = 2.0 V, the dashed line represents BJT base pushout with Ngpj = 0.8 x lO-'-^ cra"-^, Wgpj = 0.5 /im, and V^g = 2.0 V, and the dotted and dashed line represents BJT base pushout with Ngpj = 2 X 10^^ cm"^, Wepi = 0.5 /im, and V^g = 3.0 V. The base widening is more significant when the epi-layer doping density is low, the width of the epitaxial collector is large, or the collector-base applied voltage is small. The base-widening increases dramatically for BJT operated at high current densities and results in a very low fpuSHOUT3.2.4 The Coupling Effects The emitter-crowding factor taking into account the conductivity modulation, base width modulation, and base pushout in the emitter crowding mechanism is discussed in this section. In general, the high conductivity from high injection reduces the emitter current crowding (see dotted line in Fig. 3.6). Also, the base width modulation and base pushout effects result in a smaller effective base resistance. These effects lessens the level of emitter current crowding. To model a better emitter-crowding factor, f CROWDING which accounts for the second order effects (base conductivity modulation, base width modulation, and base pushout) in the emitter crowding mechanism, a parameter f^ (fc = ^BWM ^ ^CM -^ ^PUSHOUT) ^^ incorporated

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48 into (3 . 8) (3 . 12) . The parameter fc modifies the base resistance in each partitioned region of the intrinsic base. Thus if base resistance is lower due to base conductivity modulation, base width modulation, or base pushout, the Ib^BI drop due to intrinsic base resistance is reduced in the current crowding calculation. IeO = Ise/5 exp[(VBE-lBORBO-lEOREO)AT] (3.15) lEl Ise/5 exp[(VBE-lBORBO-lBlRBlfc-lElREl)/VT] (3-16) Ie2 = Ise/5 exp[(VBE-lB0RB0-lBlRBlfc-lB2RB2fc-lE2RE2)AT] (3.17) Ie3 = IsE/5 exp[(VBE-lB0RB0-lBlRBlfc-lB2RB2fc-lB3RB3fc -Ie3Re3)At] (3.18) Ie4 = Ise/5 exp[(VBE-lB0RB0-lBlRBlfc-lB2RB2fc-lB3RB3fc -lB4RB4fc-lE4RE4)AT] (3.19) Using (3.7), (3 . 15) (3 . 19) together with the Simpson's method, ^'crowding ^^^ ^^ calculated numerically. 3.3 The Nonlinear Base Resistance Model The physical mechanisms for modeling the current -dependent base resistance have been discussed in Sec. 3.2. A simple method of estimating the combined effects of all the contributing factors in the base resistance is to multiply then together in a liner fashion. In fact, the multiplication of those physical factors produces a very acceptable first order model of the current -dependent base resistance that agrees with experiments. Thus,

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49 ^BI = f^BlO ^ fRWM ^ fcM ^ f CROWDING ^ ^PUSHOUT (3.20) where RgxO ^'^ ^^^ intrinsic base resistance at Vgg = V. Rgjo equals W£pb/12Lg for a rectangular emitter with base contact on two sides, and W£p]-,/3Lg for a rectangular emitter with single base contact [45]. p^ is the intrinsic base sheet resistivity at Vgg = V. The solid line in Fig. 3.9 represents Rg (Rg = Rgj + Rgo) calculated from the present model , where Rgg can be obtained through measurements [33], [34], circuit simulation [36], or device simulations. The gradual reduction of Rg at low Vgg is caused by the emitter-base space-charge region shrinkage. The sharp decrease of Rg at high Vg£ is due to base conductivity modulation, base pushout, and emitter current crowding effects. 3.4. Model Verification with Experiments A method is developed in this section for obtaining Rg at high voltages. An ideal base current, Isideal without ohmic drops in the quasi -neutral base and emitter regions can be defined iBideal = ISB expCqVgg/nkT) (3.21) where Igg is the pre -exponential base current (Igg = Ise/(^p+1)), n is the nonideal base coefficient, n = 1 for metal emitter contact, and n > 1 for a polysilicon contact BJT in the current technologies [35]. The actual base current from measurement is [1] Ig = Isg exp[q(VgE-AV)/nkT] (3.22)

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50 a 600 500 400 300 200 100 0.2 0.4 0.6 0.8 1.0 1.2 Vb^ (v) Figure 3.9 Plot of the base resistance, Rg versus the base-emitter applied voltage, VgEThe solid line represents the simulation result from the present Rg model, squares represent PISCES simulation data, triangle represents Ning and Tang's method data, and circles represent DC measurement data at high currents .

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51 From (3.21), (3.22) the ohmic drop AV (AV = I^Re + Ib^b) is AV = (nkT/q)[ln(lBicleal/lB)] (3-23) 1 nkT Ifiideal thus Rb(Vbe) = — { ln( ) IeRe) (3.24) Ib q Ib Since Ig, IgB^^^ ^E ^^^ known from measurement directly, n is extracted in the intermediate current level (prior to ohmic drop region) by (3.21), Rg can be extracted from open collector method [46] or ac method [34], and Igideal ^^'^ ^^ calculated from (3.21), the excitation-dependent base resistance Rg can be computed from (3.24). When emitter current crowding occurs, however, the emitter resistance Rg increases due to a smaller effective emitter area. Thus, emittercrowding factor, f CROWDING •""^st be included in the Rg term in (3.24) to obtain a more accurate Rg: 1 nkT Ifiideal Ie^E Rb(Vbe) ( ln( ) } (3.25) ifi q ^b f crowding The low current base resistance value, on the other hand, is extracted from device simulations because AV is negligible compared to Vbe in low current and difficult to measure. Rbi in low currents is computed as WE^/mLgl lq/ip(x,y)p(x,y)dxdy where the position-dependent hole mobility /ip(x,y) and hole concentration are known from PISCES simulations. Here, m = 3 for a rectangular emitter with one base contact, and m =12 for a rectangular emitter with two base contacts. Combining the above methods for Rq characterization and a dc method [33], the base resistance is obtained (Fig. 3.9). The results

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52 from the present model are in good agreement with measurements. A small derivation is present at low Vgg and this is due to the fuzzy boundaries of the moving space -charge -region edges in the PISCES simulations . 3 . 5 Application In order to demonstrate the utility of the current -dependent base resistance model, the present model was implemented in SLICE using user-defined subroutines [10] . Transient simulations from Gummel-Poon model with current -dependent base resistance for an ECL circuit are illustrated in Fig. 3.10. The ECL gate has the load resistances, Rl^^ = 270 n, Rl2 = 290 Q, and the current source resistance, Rj = 1.24 KO. The input pulse waveform has logic swing from -1.55 V to -0.75 V with 20 ps ramp followed by a flat pulse of 400 ps , and then a falling ramp of 20 ps from -0.75 to -1.55 V. Figure 3.10 indicates that the constant base resistance chosen at low injection (dashed line) overestimates the propagation delay of ECL logic and that the nonlinear base resistance model (solid line) yields a more realistic switching transient in which the base resistance changes drastically during the large-signal transition. These simulations indicate that the existing constant Rg model is inadequate for predicting the transient performance of advanced bipolar technologies and the current -dependent base resistance model is superior for BJT predicting transients.

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53 -0.9 -1.0 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7

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54 3 . 6 Sununary and Discussion A physics-based current -dependent base resistance model of bipolar junction transistors has been presented. The model is applicable for all injection levels and accounts for the effects of base width modulation, base conductivity modulation, base pushout, and emitter crowding. Interactions among these effects are also treated. The results obtained from the present model, from the two-dimensional device simulator PISCES, and from measurement data show excellent agreement . We have implemented this physics -based base resistance model in SLICE/SPICE using user-defined subroutines. For an emitter-coupled logic circuit, the Gummel-Poon model with the present Rg model results in a more realistic transient response compared with that of the constant base resistance model. It is anticipated that the present model is useful for accurate bipolar integrated-circuit simulation in advanced IC technologies.

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CHAPTER FOUR CIRCUIT MODELING FOR TRANSIENT EMITTER CROWDING AND TWO-DIMENSIONAL CURRENT AND CHARGE DISTRIBUTION EFFECTS 4. 1 Introduction Today's advanced bipolar transistors, resulting from double polyslllcon self-aligned technology, have been scaled down to submicrometer emitter widths and exhibit multidimensional current flow, especially when operated during high current transients. The onedimensional BJT model [12] has been extended into a quasi2 -D model, useful for quasi -saturation, to account for the two-dimensional collector current spreading effects. In forward active mode the emitter current crowding will be significant if the base resistance is large and the collector current is high. In addition, this current crowding is enhanced during the BJT switch-on transient. The emitter current crowding and sidewall injection effects have been investigated by numerous authors [40-45], [47-55]. Analytical solutions for emitter crowding were derived to formulate a distributed circuit model [42]. The assumption of a negligible emitter ohmic drop, IgRg in [42] is not generally valid for the polysilicon bipolar transistors since IgRg can be non-negligible compared to the base ohmic drop, IgRg. It is the author's experience that neither the distributed model [42] nor the two-lump empirical models [48] [49] are optimal for parameter extraction and circuit simulation in terms of CPU time. In addition, emitter-base sidewall injection and its junction charge 55

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56 storage effects, usually neglected in the lumped circuit models, can be quite significant in small emitter-width VLSI BJT's. In this chapter, an improved circuit model including nonuniform transient current and charge distribution effects is developed. The details of the model formulation are described in Section 4.2. In Section 4.3 the model is verified by measurements and transient device simulations. Conclusions are given in Section 4.4. 4.2. Model Development A circuit model for the nonuniform current and charge distribution resulting from transient emitter crowding and emitter-base sidewall injection effects is discussed in this section. 4.2.1. Transient emitter crowding As the base current flows through the active base region, a potential drop in the horizontal direction causes a progressive lateral reduction of dc bias along the emitter-base junction. Consequently, emitter current crowding occurs at the peripheral emitter edges. This nonuniform current distribution effect is enhanced in transient operation [55], in which the base resistance and junction capacitance contribute finite RC time constant (delay) in the base region. Thus the emitter edge of a BJT turns on earlier than the emitter center during a switch-on transient. Also, the charge (Qbe) ^^ ^^® emitter edge is larger than at the center during switching. In order to analytically represent the emitter crowding effect, a variable, emitter crowding factor fcR, was defined as the ratio of the

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57 emitter current with emitter crowding to the emitter current without emitter crowding (see Cahpter 3). In this Chapter, f^^ is treated as time -dependent for transient as well as steady state operation: "We JE[V(x,t)]dx fCR(t) (4.1) 'We JE[V(0,t)]dx Jo where Je is the position and time -dependent emitter current density, x is the horizontal direction (x = is the emitter edge), t is time, and V is the position and time -dependent junction voltage. In general, JE(x,t), the nonuniform transient emitter current, can not be integrated analytically [41] [46]. Equation (4.1) is solved numerically using Simpson's integration method as We n/2 n/2-1 — {JE(0,t)+JE(WE,t)+4 I JE[(2j-l)WE/n,t]+2 I JE(2jWE/n, t) ) 3n j=l j=l -CR = JE(0.t)WE (4.2) A circuit network is used to model the current densities at various partitioned boundaries in a three-dimensional bipolar structure shown in Fig. 3.1. The concept of charge -based model was developed by Jeong and Fossum [12]. This work extends the development of Chapter 3 using this charge-based concept for regional BJT partitioning. The time -dependent lateral voltage drop, lBl(t)RBI ^^ ^^® intrinsic base region is calculated using the partitioned intrinsic base series resistance, Rbi • base current, IbIi^^)' ^^'^ charging currents.

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58 dQBE^(t)/dt and dQgci/dt at the partioned region j. The regional intrinsic base current IbijC^) can be written as Is VBEj(t) C2ls VBEj(t) iBIi [exp( )-l] + [exp( )-l] (n+l);9F ^T (n+1) Vx Is VBCi(t) C4IS VBCi(t) [exp( )-l] + [exp( )-l] (n+l)^R Vx (n+1) Vj (4.3) J VBEi(t) = VBE(t) lB(t)RBX " lE(t)RE " 1 iBI(k-l) ( ORfik C^-^) k=l J VBCi(t) = VBc(t) lB(t)RBX Ic(t)Rc " I IbI (k-1) (t)RBk (^-5) k=l where Rbx is the extrinsic base resistance, Rbi^ is the regional intrinsic base resistance (RBk " I/^ ^BIO ^ ^BWM ^ ^CM) > ^T is the thermal voltage kT/q, and Ig, Ib, Ie. Ic^F > PR' ^C^E"e "^c ^2' and C4 retain their usual meanings in the Gummel-Poon model. The regional base-emitter charging (transient) current is dQBEi(t) 1 d VBEi(t) {rFls[exp( )-l] + AeJCje[Vbej (t) ]dV) dt n+1 dt Vj (4.6) where Cje is the voltage-dependent emitter-base junction capacitance, Ae is the emitter area, and rp is the forward transit time. Similarly, the regional base-collector charging current, dQBCj(t)/dt can be found. The junction capacitance model in SPICE2 is based on the depletion approximation. This simple model holds for Cjq, the collector-base junction capacitance, in which the collector-base

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59 junction is reverse-biased when the BJT is at the forward active mode. When emitter crowding occurs, however, the junction voltage across the emitter-base space-charge region is usually high enough to invalidate the depletion approximation for finding the emitter-base junction capacitance. A recently developed junction capacitance model [37] which takes into account the free carrier charges in the space -charge region in high forward bias is therefore used in this circuit model to determine emitter-base charging currents. The biaseddependent Cjg model can be found in Section 3.2.1. Through the regional voltage drops which define the position and time -dependent junction voltages, the nonuniform currents and charges under the emitter are determined. For example, the nonuniform quasistatic charges under the emitter are described by the position and time -dependent regional charge, Q^(x,t) which is a function of its junction voltage, V.j(x,t). Figure 4.1 shows a partitioned circuit model including the transient crowding effects using charge-based circuit modeling approach [12] [23]. In Fig. 4.1 the collector current under the emitter is the product of the current crowding factor f^R and the collector current without emitter current crowding. The current crowding factor is equivalent to the effective emitter area ratio (Aggff/Ag) in [40] [41] [45]. Applying (4.1)-(4.2) to the partitioned model for n = 2 yields VBE(t)-lB(t)RBX-lE(t)RE IC fCR {Isexp[ ] VBE(t)-lB(t)RBX-lE(t)RE + C2lsexp[ ]) (4.7) neVx

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60 R. BD-vVvV -^ "B1 B dOBEO ®®" ®®"' ,®®"',Q)Q)"' (p — &" R B2 B, -vVW -ec Vbeo = Vbo Ve VBE1=VBi-VE VbE2 = Vb2-Ve (VbeO.V8E1.VbE2) 'E' Rr Figure 4.1 Network representation of the charge -based bipolar model including the nonuniform transient current and charge distribution effects.

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61 exp[VBE0(t)]+4exp[VBEl(t)]+exp[VBE2(t)] :CR (4.8) 6exp(VBE0(t)) where VgEO > ^BE1> ^^^ ^BE2 ^^^ ^^® position and time -dependent baseemitter junction voltages at the emitter edges (VgEO> ^BE2) ^^'^ emitter center (VgE]^) . Note that the present model takes into account both dc and transient emitter crowding and it can be easily reduced to a dc model by removing the transient current sources in Fig. 4.2. In addition, the equivalent distributed two-dimensional circuit model avoids the convergence, grid, and cost problems associated with transient numerical device simulations while still providing an accurate prediction of transient current crowding (see Fig. 4.7) with much less CPU time. 4.2.2. Sidewall Injection Current and Junction Charge Storage Effects When the lateral dimensions of the emitter are in the same order of magnitude as the emitter width, the emitter-base sidewall plays a significant role in the performance of the bipolar transistor [52]. To accurately model the nonuniform current and charge distribution in the advanced BJT, the emitter-base sidewall injection current and its associated junction stored charge should be modeled. An analysis of a PISCES simulation of an advanced bipolar transistor is performed to identify multidimensional currents. In PISCES simulations, the BJT has a 1.2 fj,m emitter width, a 0.1 /xm emitter junction depth, a 0.25 /im base junction depth, and a 0.7 /im epilayer depth. The doping profiles are assumed Gaussian for the emitter, Gaussian for the base, and uniform for the epi -layer. The emitter dopant lateral straggles are assumed 75%

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62 of the vertical straggles for the emitter sidewall lateral diffusion [18]. The peak dopings are 2 x 10^0 cm"^, 8 x 10^^ cm"^, and 2 x 10^^ cm'-^ in the emitter, intrinsic base, and epi-layer, respectively. The physical mechanisms used in PISCES simulations include Shockley-ReadHall recombination. Auger recombination, bandgap narrowing, and doping and fielddependent mobility. PISCES 2-D simulation readily shows the multidimensional current paths as illustrated in Fig. 4.2. The figure displays the electroncurrent -density and hole -current -density vector plots of the advanced BJT biased at Vgg 0.85 V and V^g = 3.0 V. The current vectors suggest that the sidewall injection contributes an important component of the base current. A quantitative measure of the sidewall current is given by integrating the electron current density and hole current density along the emitter-base junction sidewall. Simulation of the current gain versus emitter width also indicates the significance of the sidewall injection current and the emitter-width size effect on the current gain. Figure 4.3 shows the ^ plots of three advanced BJT's with different emitter widths. The peak ^ of the BJT with the 1 . 5 /jm emitter width is the highest followed by the peak y9 of the 1.0 fixa emitter, and then the peak P of the 0.5 /im emitter. The PISCES 2-D-BJT simulations indicate the peak-current gains of the submicrometer advanced BJT's will be reduced significantly with scaling. Since the normalized collector currents (I^/Wg) are approximately the same in these three structures, the primary reason for peak /9 reduction is the emitter-base sidewall injection current, which makes Ig not scalable. The ^ falloff

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63

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64

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65 300 Figure 4.3 Plot of current gain versus Vgg at different emitter width, Wg. The solid line represents Wg 0.5 fim, the dashed line represents Wg 1.0 /im, and the dashed and dotted line represents Wg 1.5 ^m.

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66 at the intermediate current level before high injection occurs is due to base-width modulation at the emitter-base junction; this effect is significant in narrow-base BJT's [56]. Based on device simulation and analytical approximation [52] [53], the emitter-base sidewall base current, Igx ^^ modeled using the ratio of the emitter perimeter to the emitter area: Pe XjE Is VBE(t)-lB(t)RBX VgECt) -lB(t)RBX Ibx {— exp[ ] + C2lsexp[ ]) Ae /9f Vx Vt (4.9) where Pg is the emitter perimeter and Xje is the emitter junction depth. Note that the lateral voltage drop under the emitter is defined as IbiRbI ^^ ^^^ emitter crowding mechanism. The use of voltage drop IbRbi in emitter crowding would overestimate the level of current crowding since the base current under the emitter (Ibi) can be quite different than the base terminal current (Ig) if the base sidewall current (Ibx °" ^B'^Bl) ^^ significant. As a first-order approximation, the collector current flow out of the emitter-base sidewall can be neglected [52]. Thus the charge stored at the emitter-base junction sidewall, QbeX ^^ determined by the sidewall junction capacitance, Cjex so that QbeX ^ Pe^JeJ*-'JEX(^)^^CjEX is the same as Eqs . (3. 2) -(3. 5) providing different values for the junction gradient "a" and the effective junction built-in voltage V . Similarly, the extrinsic base-collector junction charge, QfiCX associated with the collector-base junction outside the intrinsic emitter region is (Ac-AE)JCjc(V)dV because the collector current flows mainly in the intrinsic emitter region (see Fig. A. 3.1).

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67 By combining the modeling methodologies in Sees. 4.2.1 and h.1.2, the nonuniform transient currents and charges in an advanced BJT can be determined. 4.3. Model Verification with Experiments and Transient Device Simulations The circuit model which includes the emitter crowding (dc and transient) and sidewall injection effects was implemented as userdefined-controlled-sources in SLICE. In SLICE/SPICE circuit analysis, UDCS's are user-defined subroutines (see Appendix B) that use the implicit nonlinear model equations to compute both charging current (dQ/dt) and transport current (I) in the model depicted in Fig. 4.1. The time derivatives of the quasi-static stored charges in the base thus properly represent the charge dynamics in the BJT. The lateral voltage drops {V^Y.l'^t) < Vfigj^Ct) < VgEOCt) < VegCt)) are given as the system of model equations (I and dQ/dt) are solved simultaneously. Transient current crowding is then accounted for in the collector current by fcR(VBEO(t) , VgElCt) ,VBE2(t) ) • Test devices representative of advanced BJT's were used to verify the model and to define a parameter-extraction scheme. The devices have drawn emitter width Wg = 2 /xm , emitter length Lg = 8 /zm and the approximate active emitter area is Ag = 1.2 x 7.2 ^im^ due to sidewall spacer technology. The intrinsic and extrinsic base resistances are obtained by Ning and Tang's method [33]. The Gummel-Poon model parameters Ig, ^p, ^^, rp, t^, n^, n^, , C2 , C4, Rp, and R^ are extracted by the methods in [1]. Some of the physical parameters are determined from the process information (Ap, Pp, Wp, Xjp, and Ng) and from [25]

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68 (ni, V*). The BJT is measured from Vgg 0.6 V to Vgg = 1.0 V with Vcg = 3 V to keep the transistor out of quasi-saturation. The simulated results from the present model and the Gummel-Poon model show excellent agreement with the experimental data at low currents; however, the simulated results from the Gummel-Poon model deviate significantly from measurements at high currents (see Fig. 4.4). The discrepancy would be exaggerated if Fig. 4.4 were shown on a linear scale. Transient measurement of a ring oscillator introduces an extra propagation delay due to the interconnect between the first and last stages of the ring oscillator and the I/O pad capacitances which complicate measurement of the real inverter transient response [27]. Thus, to demonstrate the model utility in transient operation, the emitter crowding factor and pulse response of an inverter are simulated using the present model and compared with transient device simulation using PISCES. Figure 4.5 shows the emitter current density horizontally along the emitter-base junction at various times in the PISCES transient simulation. In Fig. 4.5 emitter crowding is very significant during the initial turn-on transient. The transient crowding factors obtained from PISCES and the present model are compared in Fig. 4.6. The model predictions show close agreement with PISCES transient simulations. This indicates that the lumped model in Fig. 4.1 correctly accounts for the nonuniform transient current and charge distribution effects. SLICE implementation employing the present model, which includes the transient crowding effects, is used to simulate a BJT inverter with 1.2 Kfl load resistor. The input pulse waveform consists

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69 Figure 4.4 Log I versus base-emitter applied voltage, Vgg. The solid line represents the present model simulation, the dashed line represents the Gummel-Poon model simulation, and the circles represents the measurement.

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70 1.2 1.0 •^ 0.8 u < '%D 0.6 c 0.4 0.2 -

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71 1.0 0.8 _ 0.6 o 0.4 0.2 TIME (x10"^S) Figure 4.6 Plot of the emitter crowding factor versus time. The solid line represents SPICE simulation employing the present model, and the circles represent PISCES simulation.

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72 of a 0.85 V, 50 ps ramp followed by a flat pulse of 1200 ps duration and then a falling 0.85 V ramp of 50 ps . Figure 4.7 shows the inverter transient responses from SPICE/SLICE (using the Gummel-Poon model and the present model) and PISCES. The predictions of the present model are in good agreement with PISCES results; however, the Gummel-Poon model shows a slower turn-on transient and a large propagation delay. The discrepancy between the Gummel-Poon and PISCES results is due to the nonuniform transient current and charge distribution in PISCES simulation which lowers the magnitude of the base impedance during switching. The use of a lumped base resistance measured at steady-state in the Gummel-Poon model predicts more delay than is actually observed. 4.4 Summary and Discussion A new circuit model for the advanced bipolar transistor including nonuniform transient current and charge distribution effects has been developed. The model takes into account the transient emitter crowding mechanism, emitter-base sidewall injection, and extrinsic junction charge storage effects. The spatially partitioned model is developed based on physical insight gained from device simulations (dc and transient) . Although the partitioning technique itself is straightforward, the present model represents the nonuniform current and charge distribution at the emitter-base sidewall and under the emitter in a unified manner. Furthermore, second order effects such as base-width modulation and base conductivity modulation, which decrease the intrinsic base resistance and emitter crowding are easily modeled in the equivalent circuit through a correction factor for the effective

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73 3.5 3.0 2.5 2.0 TIME (x10"^S) Figure 4.7 Simulated transient responses for a single-transistor inverter. The solid line represents the present model simulation, the dashed line represents the Gummel-Poon model simulation, and the circles represents PISCES transient simulation.

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74 base charge. SLICE simulations employing the present model show excellent agreement with measurements and device simulations. Since the model correctly represents the charge dynamics of the BJT in transient operation, it is anticipated that the present model can be useful in advanced bipolar (or BiCMOS) modeling in technology computer-aided circuit design and process sensitivity diagnosis.

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CHAPTER FIVE SPARAMETER MEASUREMENT PREDICTION USING A PHYSICAL DEVICE SIMULATOR 5 . 1 Introduction Submicrometer emitter bipolar transistors produce small signal responses that are difficult to characterize with existing s -parameter equipment. State of the art probes, and proper calibration technique have proven essential in the measurement of s -parameters of single BJT test structure [57]. However, s-parameter measurements cannot predict the test-structure response of new BJT technologies in the "on paper" development stage. A new method of predicting s-parameter test structure response from physical device simulator output has been developed. This predicted s-parameter response is particularly useful for examining the performance of conceptual designs of submicron BJT technologies. Submicrometer BJT's have significant dc, transient and small -signal multidimensional effects which include collector current spreading, emitter crowding, and emitter-base sidewall injection; these effects have been evaluated by a 2-D physical device simulator previously [58] [59] and are discussed in Chapters 2, 3, and 4. The new method of predicting s-parameter response provides a direct comparison between 2D BJT simulations and measurement data from BJT test structures. Important uses of this simulated s-parameter response also include verifying BJT test structure s-parameter measurements and 75

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76 previous BJT characterizations. The derived BJT test structure response can be used to confirm the accuracy of existing test structures measurements, potentially reducing the total number of test structures, measurements, and cost necessary to characterize a BJT technology. In order to get a complete characterization of a 3 -port BJT, three sets of 2 -port measurements must be taken, generally requiring 3 separate test structures. Since the 3-port measurement is time consuming and IC layout area intensive, often only a single 2-port BJT measurement is made. The s -parameter prediction technique can supplement an existing 2-port test structure measurement so that a complete 3-port BJT characterization is possible. The simulated sparameter response also can be extended beyond s-parameter instrumentation frequency ranges. This modeling technique is demonstrated using submicrometer BJT simulations from the PISCES 2-D physical device simulator [60] . Other small-signal device simulations or characterizations [61] could be substituted for the PISCES data. Simulated small-signal BJT y-parameter measurements are converted (via software) to s-parameters . S-parameter measurements are preferred for high-frequency characterizations and have been demonstrated on-chip at frequencies up to 50 GHz [62]. In addition, s-parameter best represent a distributed circuit with high frequency discontinuities [63], such as a BJT IC test structure measured at microwave frequencies. The BJT s-parameter response is incorporated into a BJT test structure model which includes the effects of IC interconnects, discontinuities and bond pads. The predicted sparameter response for the BJT test structure is then calculated and

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77 plots of the BJT test structure responses are presented. This modeling technique proves extremely useful for evaluating IC test structure characteristics . This is the first time that the high frequency BJT test structure circuit modeling has been combined with a 2-D device simulation output in order to predict test structure s-parameter response. In addition, a novel two-layer metal-based BJT test structure with low attenuation is examined using this modeling. The modeling algorithms presented here may be applied in inverse fashion to extract accurate BJT small signal characteristics from s-parameter measurements or evaluate the accuracy of s-parameter calibration algorithms. 5 . 2 Bipolar Test Structure Modeling In order to demonstrate the utility of the bipolar test structure modeling, an n-p-n BJT small-signal response was simulated using the PISCES program. The physical features of the BJT include a 1 /im emitter width (Wg =0.5 ^m) , a 0.1 ^m emitterdepth, a 0.2 urn base -depth, and a 0.8 urn epitaxial collector-depth shown in Fig. 2.1.1. The doping profiles are shown in Fig. 2.1.2. Small-signal parameters from 1-D, 2D, or 3-D simulator may be used for input in this test structure modeling technique. A 2-D simulation typically provides BJT y-parameter response up to the emitter contact, base contact, and collector contact. During yparameter simulations the BJT is biased at Vgg = 0.8 V. and V^g = 2.0 V and the frequency is varied from 10 MHz to 7 GHz. The y-parameters are normalized by the distributed circuit admittance (frequency dependent

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78 interconnect admittance) and then converted to s -parameters . The yparameter to s -parameter conversion equations are [64] : (1-yii) (1+722) + yiiyii sii (5.1) (1+yil) (1+722) 712721 -2712 !12 (5.2) (1+711) (1+722) 712721 -2721 S21 (5.3) (1+711) (1+722) 712721 (1+711) (1-722) + 712721 S22 (5.4) (1+711) (1+722) 712721 In order to predict the s-parameter response of a specific BJT test structure layout, an equivalent high frequency circuit must be constructed. An example BJT test structure layout which is frequently used for s-parameter measurements is presented in Fig. 5.1. Here, the BJT is positioned between three bond pads that are connected to the transistor by IC interconnect. The bond pads are 100 ^m by 100 /im and a bend is added to the IC interconnect between the base terminal and the base bond pad. The interconnect, the bond pads and the bend exhibit parasitic responses at microwave frequencies. A flow chart which outlines the calculation of the BJT test structure response is shown in Fig. 5.2. The physical dimensions and doping profiles of the submicron BJT are entered into the device simulator program and dc and ac simulations are performed in order to predict y-parameters . These y-parameters are converted to s-parameters

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79 Figure 5.1 BJT test structure layout typically used for s -parameter measurement .

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80 INTERCONNECT MODELS ADVANCED BIPOLAR TRANSISTOR DESCRIPTION PISCES DC & AC SIMULATIONS Y PARAMETERS CONVERT TO S PARAMETERS NORMALIZE TO INTERCONNECT IMPEDANCE CASCADE TEST STRUCTURE LAYOUT EFFECTS WITH INTRINSIC BJT RESPONSE NORMALIZE TO 50Q S PARAMETER

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81 after normalization by the on-chip interconnect admittance. Then the BJT s -parameters are cascaded with the s -parameter responses of the BJT layout elements (interconnect, bond pads and a bend in interconnect). Figure 5.3 is a block diagram showing the order in which the matrix models of the interconnect, bend in interconnect and bond pads are cascaded. The BJT simulation (shown in the middle of the cascaded matrices) is multiplied by the surrounding component matrices. In order to do this, the s -parameter data in each component matrix are converted to readily cascaded high frequency T-parameters which are similar to low frequency ABCD parameters [63] . The cascaded T-parameter matrices are multiplied in order to model the BJT test structure response at the bond pads and the result is converted back to s -parameters . The s -parameters at the bond pads, which are normalized by the on-chip interconnect admittance, are converted to a 50 fl system impedance that is common to s -parameter instrumentation. This conversion employs the following equations [63]: (z2 Zq^) sinh7l sil = S22 = (5.5) 2ZZocosh7l + (Z^+Zo'^)sinh7l 2ZZo S21 = S21 = (5.6) 2ZZocosh7l + (Z^+Zo'^)sinh7l In these equations, Z is the transmission line impedance, Zq is the system impedance (50 fi) , 7 is the propagation constant (7=0+ j^p) , a is the attenuation constant, ^„ is the phase constant, and 1 is the transmission line length.

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82 50Q CO CL D C o m o a. CQ "D (0 Q. 50Q Figure 5.3 Cascade of the BJT test structure components and PISCES simulations for calculating s-parameter response.

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83 Analytical circuit models from the microwave literature are used to represent the effects of IC interconnect and bends. The bond pads are treated as a section of wide lumped admittance since a probe or ball bond touches most of the bond pad area. The value of the bond pad admittance was estimated by calculating the lumped admittance of a short section of interconnect of the same dimensions as the bond pad. The microwave model for the bend in the interconnect was taken from the literature [63] . An IC interconnect cross-section with microstrip metal over Si02 over the Si substrate is used for the BJT test structure layout. Then a novel two-layer-metal IC interconnect is examined as a superior interconnect alternate. Fig. 5.4 displays a cross-section of a metalSi02-Si microstrip interconnect cross-section. In Fig. 5.4 the width of the metal line is 20 /im, the thickness of the metal line is 1 fim, the thickness of the Si02 layer is 1 /xm, the thickness of the Si substrate is 300 ^J.m, and the resistivity of the Si substrate is 1 fl-cm. The transmissionline model for this interconnect system has a series impedance per unit length and a parallel admittance per unit length as shown in Fig. 5.5. The series impedance, Z is composed of R, the interconnectline resistance plus L, the interconnectline inductance. The parallel admittance of the transmission line includes the Si02 capacitance, C]^ , in series with the parallel combination of the Si capacitance, C2, and the Si conductance, G2 . The IC interconnect equations presented below are valid when the Si substrate layer is moderately to lightly doped [65] [66] : L = MO F(hi+h2) (5.7)

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84 W w i Metal I t' SiOo f Si ia-cm Metal (Ground Plane) Figure 5.4 Cross-section of a metal-Si02-Si system, w 20 /xm, t' 1 /im, h]^ 1 /im, and h2 300 /xm.

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85 R L =7=c. Figure 5.5 Transmission line circuit model for interconnect over metal-Si02-Si.

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86 1 R (5.8) "^METAL w t' Ci (5.9) F(hi) «0 Fl(«Si. 1^2) C2 (5.10) F(h2) PSi [l+(l+10h2/w)-V2] 2 F(h2) w/h +2.42 0.44h/w + (l-h/w)^ (5.11) 1 8h w F(h) = — ln(— + — ) for h/w > 1 (5.12) 27r w 4h for h/w < 1 (5.13) £ + 1 £ I Fi(€, h) + . (5.14) 2 (l+10h/w)l/2 In these expressions, eg ^^ the permittivity of free space, e^^ is the relative permittivity of Si, €§£02 ^^ ^he relative permittivity of Si02, and /ig is the permeability of free space. The variable t' , represents the interconnect thickness, w is the interconnect width, hi is the height of the Si02 layer, h2 is the height of the Si substrate, o^l is the conductivity of the Si layer, and c^mETAL ^^ ^^^ conductivity of the metal interconnect. This interconnect model neglects the effect of skin-effect loss, Qq in the interconnect center conductor. The skineffect loss may be

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87 approximately modeled assuming that the phase constant, /3p is much greater than the attenuation of the transmission line. First the above equations are used to calculate a + jy9p = (ZY)-'-/^. The corrected propagation constant, 7 is estimated from the following relationship, 7 = a + ttf, + j/3p for low loss interconnect. The low loss condition implies that the addition of the skin-effect loss to the interconnect model has a negligible effect on the transmission line ^p . The equations governing the conductor skin-effect losses are [63] [67] : 1.38 Ci Rg [32-(We/h)2] w ^c = for < 1 h Zq [32+(We/h)2] h 6.1x10"^ Ci Rs Zq Cj-e ^e 0.667 Wg/h w [ — + ] for > 1 (5.15) h h We/h + 1.444 h We 1 2C2 where C^ = 1 + — [1 + -In ] h TT t Rs = (TTf^oP)^/^ w 1 C2 = h for > — , h 2n w 1 = 27rw for — < — . h 27r In these expressions, p is the resistivity of the conducting raicrostrip and Wg is the effective conductor width which is a function of microstrip dimensions [63] [68] [69]:

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88 (Tg w Aw + — (5.16) h h h Aw 1 . 2 5 1 ' 47rw w 1 where — [1 + In ] for — < — , h Trh t' h 2jr 1.25t' 2h w 1 [1 + In — ] for > — . Trh t' h 27r The novel double -layer metal interconnect cross -section we proposed for the BJT s-parameter test structure layout (see Fig. 5.1) is shown in Fig. 5.6. This interconnect has a 20 fim wide line in metal 2 separated from a metal -1 ground plane by 1 ^m of insulating dielectric (Si02) . This interconnect is integrated on the silicon substrate but the effects of the substrate are blocked by the metal -1 ground plane. This interconnect has a lower attenuation for the same physical geometry than the metal-Si02 interconnect since there are no substrate losses. The metalinsulator-metal transmission-line equations are reported in the literature [70]: 120 TT h Z0(f) = — (5.17) weff(f) £r(f)^/^ Weff(O) wi weff(f) = wi + — — (5.18) 1 + f^/fT^^ «r(0) «eff 6r(f) ^1.(0) — (5.19) 1 + f^/fx^ Here, tgff is the effective permittivity of the insulator, €j-(0) is the

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89 Metal-2 | t' t Metal-1 Figure 5.6 Cross -section of a metal -insulator-metal interconnect system, v^ 20 fim, t' 1 /im, and ^r " ^-

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90 relative permittivity of the insulator at f (dc) , eq is the permittivity of free space, c is the speed of light, f is frequency, Wgff(O) is the effective metal width at f = 0, h is the height of the dielectric, and W]^ is the width of the metal interconnect. The conductor losses are added to the model by using (5.14) and (5.15). The results of this modeling are shown in the next section. 5.3. Bipolar Test Structure S -parameter Response The BJT test structure s -parameter response using the layout in Fig. 5.1 is predicted for BJT simulations. The BJT test structure response with microstrip interconnect (metal-Si02-Si substrate) and the double-layer metal interconnect (raetal-Si02-metal) test structure response are both calculated. In order to investigate the relative contributions of the BJT test structure parasitic elements, simulations of: 1) the intrinsic BJT s-parameter response, 2) the s-parameter response of BJT transistor plus 200 /im of interconnect on each terminal, and 3) the response of the full BJT test structure are performed. Figure 5.7 shows a pair of polar graphs of S]^]^ and S21 simulated measurements for the BJT test structure with the metal-Si02-Si crosssection shown in Fig. 5.4. The curves labeled a and x display the BJT S11 and S21 response calculated from y-parameters . The curves labeled b, and c plot the Sii representation of 1) the BJT with 200 nm of interconnect on each terminal and 2) the BJT plus 200 /xm of interconnect, bond pads, and an interconnect bend, respectively, the curves labeled y and z show the S21 response of the BJT test structure.

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91 +150 Figure 5.7.1 A polar graph of Sn for the metal -Si02Si system shown in Fig. 5.4; curve a is a PISCES BJT simulation. Curves b and c show the BJT simulation plus the effects of 200 /im interconnect, and the BJT test structure layout (200 /im of interconnect bond pads and a bend), respectively.

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92 1.3 Figure 5.7.2 A polar graph of S21 for the metal-Si02-Si system shown in Figure 5.4. Curves x, y, and z correspond to curves a , b and c in Figure 5.7.1.

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93 These s -parameter plots go from 10 MHz to 7 GHz and have markers at 1 GHz, 3 GHz, 5 GHz, and 7 GHz. The curves in Fig. 5.7 show that interconnect on the order of 200 fixn significantly influences phase and gain of the s -parameter response simulation; bond pads and bend add additional parasitics effects to the s -parameter measurement. Figure 5.8 displays the differences between the simulation of the BJT s -parameter response and the S21 magnitude (Fig. 5.8.1) and phase (Fig. 5.8.2) simulations of the BJT test structure. Figure 5.8.1 shows that the metal -Si02Si BJT test structure has about 3 dB magnitude loss at 7 GHz and just 200 ^m of interconnect will have 1 dB loss at 7 GHz. These losses will become large at frequencies above 10 GHz. There are significant differences in phase between the BJT sparameter response and the BJT test structure response at lower frequencies. A phase error of 10° is present for the BJT test structure at 1 GHz and just 200 /^m of interconnect will add 10° phase error at 2 GHz. This phase error becomes larger than 58° for s -parameter measurements above 7 GHz for the BJT test structure. Figure 5.9 displays a pair of polar graphs of Sn and S21 for the BJT test structure built on the novel metalinsulator-metal test structure. Again there are response differences between the BJT sparameters of curve a, the BJT with 200 /im of interconnect (curve b) , and the full BJT test structure (curve c) . The s-parameter response curves for the metalinsulator-metal-based BJT test structure are closer on the polar graph than the response curves for the metal -Si02Si interconnect-based BJT test structure (see Fig. 5.7). This indicates that the double-layer metal test structure has less parasitic effects.

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94 ^ m T3 CO -CM CO O o 2 -4 -

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95 10 ^^

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96 +i50 -j50 Figure 5.9.1 A polar graph of S-^i for the metal -insulator-metal system shown in Figure 5.6; curve a is a PISCES BJT simulation. Curves b and c show the BJT simulation plus the effects of 200 |im interconnect, and the BJT test structure layout (200 /im of interconnect, bond pads and a bend), respectively.

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97 Figure 5.9.2 A polar graph of S21 for the metal -insulator metal system shown in Figure 5.6. Curves x, y and z correspond to curves a, b and c in Figure 5.9.1.

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98 Figure 5.10 displays the differences in S21 magnitude (Fig. 5.10.1) and S21 phase (Fig. 5.10.2) between the BJT s-parameter response, the BJT test structure s-parameter response, and the sparameter response of the BJT with 200 /im of metal -insulator-metal interconnect. Here, there is a 1.6 dB loss in S21 magnitude for the BJT test structure at 7 GHz, indicating a much improved measurement environment. This interconnect system also exhibits better phase agreement with the PISCES simulated s-parameter response than the metal-Si02-Si-based BJT test structure as shown by an 18° reduction in phase error at 7 GHz . 5 .4 Conclusions In general, the simulations produced by a 2-D device simulator do not incorporate test structure layout topology effects into account. We have demonstrated modeling techniques necessary to predict s-parameter response from 2-D simulations for a given BJT test structure layout. Thus, s-parameter simulations give insights into changes in BJT behavior with variations in doping profiles, and physical dimensions can be compared directly to measurements. This modeling technique also can be used to produce 3 -port s-parameter characterizations and supplement existing 2-port device BJT s-parameter measurements. Moreover, the modeling can be applied to high frequency test structure modeling for transistor other than the BJT, such as GaAs heterojunction bipolar transistors. The simulations presented in the paper [71] show that significant high frequency parasitics are present in a typical BJT test structure,

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99 ^ m •a CO CO D) O o CM r" -2 -4 -6 -

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100 1 u

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101 especially above 1 GHz. for example, the addition of 200 /jm of interconnect on each terminal and bond pads will introduce a S21 magnitude error of 3.0 dB and S21 phase error of 58° at 7 GHz on a metal -Si02Si interconnect system. The simulations also show that a metalinsulator-metal system with the same interconnect dimensions will be superior to the metal-Si02-Si system for BJT test structure layout across the frequency range of simulation.

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CHAPTER SIX INTEGRATED CIRCUITS INTERCONNECT MODEL FOR SPICE 6 . 1 Introduction With the design of fast devices having switching times in the picosecond range, transmitting data at high speed rate has becomes very commonplace in digital integrated circuit systems. Signal delays and rise times are more and more limited by interconnection lengths rather than intrinsic device speed in submicrometer VLSI technology [72]. Accurate modeling and analysis of the interconnect structure is thus essential to the realization of the next generation of high performance IC's. Careful modeling of IC interconnect and associated parasitics is required to push the performance of both digital and analog advanced bipolar circuits into the GHz frequency range. SPICE transmission line modeling (lossless and nondispersive) very poorly describes the behavior of signals on IC interconnect of advanced IC technologies (lossy and dispersive) . Existing interconnect circuit models for the silicon integrated circuit describe the transmission properties of a metal interconnect line on a dielectric substrate or on a Si02 layer of constant thickness over a substrate with constant doping. A model for this case is presented in Chapter 5. However, this existing interconnect circuit modeling neglects the effects of buried layers, epi-layers, and p-n junction space-charge capacitance that may occur in modern integrated 102

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103 circuit technologies [73]. A method of modeling first-level metal interconnect signal transmission on silicon substrate with arbitrary doping profiles is presented in this chapter. Analytical modeling and the output of a 2-D device simulator are used to predict and verify the small-signal admittance per unit length of silicon IC interconnect. Then accurate analytical models of interconnect signal transmission are derived by combining the admittance information and existing modeling of interconnect series impedance per unit length. The model prediction in SPICE simulation is verified by experiments. An ECL ring oscillator transient analysis is used to study the practical utility of the interconnect circuit model. Finally, a conclusion section ends the chapter. 6 . 2 Interconnect Modeling Topology Development An interconnect system tends to require complex modeling because the conductor material is not lossless and the lines can be coupled both capacitively and inductively. The finite conductivity of the conductor results in a variation of the current density distribution in the conductor. Skin effect loss (conductor loss) and dielectric loss as well as different signal phase velocities at high frequency make the interconnect resistance and capacitance frequency dependent. Thus, linear distributed interconnect models which are commonly used in CAD packages (such as SPICE and Touchstone) do not readily represent the interconnect dispersive and lossy characteristics. In this section, a nonlinear interconnect circuit modeling technique will be developed

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104 that takes into account signal dispersion and signal loss. First, a simplified interconnection line and its equivalent circuit model per unit length of the structure for frequency -dependency analysis are shown in Fig. 6.1. In Fig. 6.1.2, R represents the interconnection line series resistance, L is the interconnect line inductance resulting from the propagating electromagnetic field, G is the substrate shunt conductance, and C is the substrate capacitance. The circuit elements above are written in terms of the metal width w, thickness t' , and substrate height h as follows [63] [66]: TT /iQ f R(f) = ( )l/2 (6.1) '^METAL w t' L MO F(w,h) (6.2) '^sub [l+(l+10h/w)-V2] (6.3) F(w,h) fO «eff(f) C(f) . (6.4) F(w,h) 1 8h w F(w,h) ln[— + — ] , for h/w > 1 2ir w 4h w/h +2.420.44h/w+(l-h/w)^ , for h/w < 1 (6.5) where a^^i, is the dielectric substrate conductivity. The nonlinear characteristics of the circuit elements above is implicitly accounted for in the frequencydependent permittivity.

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105 Figure 6.1.1 A metal-Si-metal interconnect line,

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106 R L Figure 6.1.2 The equivalent circuit model per unit length of the interconnect shown in Figure 6.1.1.

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107 Bgff (f ) . The effective permittivity starts to increase to its maximum value (cgff -* e) when the frequency is above the critical frequency, f^ [70]. ^eff(f) = ^ (6.6) 1 + (f2/fc^) e+1 €-1 + (6.7) 2 2(l+10h/w)V2 c2 eo Zo e^/2 fc -— (6.8) 2 h €'^/2 120 TT F(w,h) '« ° .,1/2 <'" Using Eqs. (6.1) -(6. 9), the frequencydependent propagation coefficient 7 is given as 7(f) = [Z(f) Y(f)]V2 (6.10) where Z(f) = R(f) + jwL(f), and Y(f) = G(f) + ja;C(f ) . Time -domain simulations of pulse propagation can be performed using this interconnect model [74] . A Gaussian pulse is divided into frequency -domain components via the Fourier transform and these components are propagated along the IC interconnect using the wave equation. The frequency-domain components experience different wavespeeds and loss as they propagate. Applying the inverse Fourier transform to the input signal and the frequencydependent propagation coefficient in Eq. (6.10), the pulse shape at any particular point on

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108 the interconnect can be calculated [75-77]: 1 V(l,t) 1-K jwt -7I V(0,x) e e dx (6.11) where 1 is the interconnection length, w is the radian frequency (oj = 2wf ) , and t is time. A flow chart of this topology is shown in Fig. 6.2. To demonstrate the necessity of the frequency -dependent components and the modeling utility, a Gaussian pulse propagating along an interconnect is simulated. In this simulation, 1 = 0.9 cm, t' = 0.0005 cm, w = 0.051 cm, h = 0.064 cm, e = 10.2, aj^ETAL = 3.7 x 10^, o CTsub = 1 >< 10' . The dashed line in Fig. 6.3 is the propagating pulse computed from the interconnect model without frequency -dependent permittivity (^eff °° ^') while the solid line is from the interconnect model with frequency -dependent ^eff(^)'•'^ ^^® semiconducting substrate, wave propagation is dispersive due to slow-wave propagation and mode transition [78]. Owing to this, propagation delay and rise time of high speed pulses are deteriorated in the semiconducting substrate. Therefore, the frequency -dependent permittivity used in nonlinear circuit elements formulation is necessary to represent signal dispersion. To verify the interconnect model, we compare the model simulations with the published data [76]. The circles in Fig. 6.3 [76] show excellent agreement with the model prediction (solid line) ; however, the frequencyindependent circuit elements response has a large discrepancy (dashed line) with the dispersive signal. Therefore, the equivalent circuit modeling topology here is more accurate than the

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109 Interconnect Circuit Model (R,L,G,C/length) Compute Interconnect Propagation Constant Y = Yz^T Input Transient Pulse e.g. , V,n(o,t) = Ae'^'^' Time to Frequency Domain Conversion V,„ (0,00,= AVE e -0) 4a' Inverse Fourier Transform Vout( I ^) =irJrVln (o,co)eJO)te-Y I dco Propagated Transient Response Figure 6.2 Calculation of pulse propagation using Fourier transforms and inverse Fourier transforms.

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110 1.0 0.6 >° 0.2 •0.2 -

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Ill linear circuit elements model in [65] [66]. Note that even though the mathematical modeling technique in [76] is adequate for finding signal transmission for a single circuit element, equivalent circuit modeling is more suitable for SPICE circuit simulation. 6 . 3 Advanced IC Interconnect Cross -Section Analysis The interconnect circuit model in Section 6.2 is extended for advanced IC technologies. First, the IC interconnect cross -section is partitioned into the relevant doping regions (oxide, epi-layer, buriedlayer, substrate, etc.). Analytical expressions provide the conductance and capacitance of each region. Parallel admittance per unit length of the interconnect cross -section (Y) is modeled by stacking the circuit elements (G's and C's per unit length) into a series of admittances representing each of the doping regions. Space charge capacitances are placed between p region and n region. The 2-D device simulator is used to verified the validity of the overall analytical expressions for a particular IC interconnect cross-section. Figure 6.4 shows a segment of the representative distributed circuit model (Fig. 6.4.2) for signal propagation on the interconnect integrated on an Si02 substrate over an n-type buried layer on a p-type substrate (Fig. 6.4.1). The parallel admittance elements of the interconnect circuit are the field oxide capacitance (Csi02) > the buried layer conductance (G^+) , the buried layer capacitance (Cn+) , the junction space-charge region capacitance (Cscr) ^^^ substrate conductance (Ggub) • ^"^ ^^^ substrate capacitance (Cg^^) • Extensions of existing analytical modeling are used to calculate the values of these

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112 Figure 6.4.1 An interconnect line for advanced bipolar IC cross section profile. The interconnect is integrated on an Si02 substrate over an n-type buried layer on a p-type substrate .

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113 R L CS102 Cn* CsCR 'Sub' Csub O Figure 6.4.2 The equivalent circuit model per unit length of the interconnect shown in Figure 6.4.1.

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114 parallel admittances as below: «0 «eff(f) Csi02 (6.12) F(w,ti) an+ [l+(l+10t2/w)-V2] Gn+ (6.13) 2F(w,t2) «0 «eff(f) Cn+ (6.14) F(w,t2) «0 «eff(f) w CsCR = (6.15) [2€0feff(f)(NA+ND)(Vbi-2VT)/(qNAND)]^/2 '^sub [l+(l+10t3/w)-V2] Gsub (6.16) 2F(w,t3) ^0 feff(f) Csub (6.17) F(w,t3) where N^ is the acceptor doping concentration for p-type Si substrate, Nj) is the donor doping concentration for n"^-type Si layer, '^^+ is the n"*" silicon conductivity. The variables t^, t2, and t3 are the oxide height, the Si buried layer height, and the silicon substrate height, respectively. Among the capacitances of Csj^o2> '^n"'"' '-'SCR^^^ '-'sub' ^^^ substrate capacitance Cg^^ shows the strongest frequencydependent behavior due to a large thickness and the small critical frequency f^ (see Eqs. (6.6) (6.9)).

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115 The series Impedance elements (R and L) are determined by (6.1) and (6.2) providing h in (6.2) is replaced by t]^ + t2 + t3. To verify the new cross -section modeling, the transient response of this IC interconnect cross-section admittance is simulated using PISCES-II. A pulse is applied to the cross-section with a 100 ps risetime ramp. The SPICE circuit simulation program simulated the interconnect circuit model transient response (parallel admittance elements only) to an identical pulse. These results are plotted in Fig. 6.5. The agreement between the PISCES cross -section transient simulation and SPICE interconnect circuit model transient simulation is excellent. This indicates that the circuit modeling of the interconnect parallel admittance is correct. 6 .4 Interconnect Model Verification The interconnect cross -section model in Sec. 6.3 plus the impedance model (R and L) in Sec. 6.2 give an advanced IC interconnect model. To verify the model accuracy, test structures representative of the interconnect lines are fabricated in Texas Instruments Inc. The interconnect dimensions and profiles where established from the fabrication process. Transient measurements were performed using the Tektronix 7854 sampling oscilloscope and 7S12 time domain reflectometry (TDR) sampler. TDR 7S12 generates fast transient pulse with amplitude 250 raV and rise time less than 35 ps. The fast switching-on transient enables characterization of signal dispersion. A measured transient response with signal delay, loss, and dispersion is displayed in Fig. 6.6.

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116 6 < 1^ 3 X :=2 1 -1 c

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117 0.3 cr 0.2 LU o < o > 0.1 TIME (X10"^S) Figure 6.6 Step response of a 5 cm interconnect line. The solid line represents the step input, the dashed line represents the model simulation, and the circles represent measurement data.

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118 To demonstrate interconnect model utility in SPICE circuit simulation, the interconnect circuit model is constructed as an nsectional miniaturize network representing a distributed circuit. SPICE simulation employing the present nonlinear interconnect model is simulated by a input pulse with 35 ps ramp from to 250 mV followed by a flat pulse. In the SPICE simulation, the equivalent circuit elements are determined to have a bandwidth defined by f cutoff ^ l/C^f^rise) • Frequency variations in circuit elements can not be computed in transient simulation in SPICE [79]. However, by examining the characteristics of the frequency -dependent dielectric constant (see Fig. 6.7), the author determined that the capacitance's frequencydependency behavior can be neglected if the signal frequency is below 30 Ghz . Therefore, for a 35 ps risetime ramp the frequencyindependent circuit elements in SPICE simulation will be fairly accurate. Nevertheless, the use of f = l/ilirr-^i^^) for computing circuit elements is much better than the use of f = ". The simulated transient waveform is compared with the experimental result in Fig. 6.5. Good agreement is obtained between measurement and model prediction. This confirms the present interconnect circuit model utility and accuracy. 6 . 5 Mixed-Mode Circuit Simulation The steady increases in chip complexity brought about by continuing improvements in lithographic resolution have created the economic incentive to implement subsystems containing both analog and digital functions on a single integrated circuit. In circuit design, mixed-mode circuits mean the combination of analog and digital circuits

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119 1 £.

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120 integrated in a single chip. In circuit simulation, however, mixedmode simulation combines the level of device simulation and circuit simulation in circuit analysis, such as MEDUSA [80]. The "mixed-mode" circuit simulation described here includes bipolar transistors and interconnects. Since the bipolar circuit models in this work are derived from the physical insights of device simulations, the physical model contains a lot of information of device layout (emitter width, emitter length, emitter perimeter, etc.), device doping (base doping and epitaxial collector doping) , and physical device parameters (lateral diffusion velocities) in circuit simulation. Therefore, the circuit simulator inputs have not only circuit parameters from measurements, but also physical parameters in device make up. In addition, the parasitics such as interconnects which are also process cross-section dependent are included in our circuit simulation. We then call it mixed-mode circuit simulation. To demonstrate the interconnect model utility and necessity in mixed-mode circuit simulation, a ring oscillator with an interconnect feedback path between its last and first stages (see Fig. 6.8) is simulated in transient operation. The ring oscillator has a NOR gate as a stimulus input source and an inverter followed by four ECL inverters. The ECL circuits in Fig. 6.9 have Rd 500 Q, Rc2 = 500 fi, Rg 640 Q, Vg -4.0 V, Vqs -2.5 V, and V^gp -1.11 V. The input source used to trigger the NOR gate has a logic swing from -0.86 V to -1.36 V with 70 ps ramp and then stays at -1.36 V. The transient simulation of the ring oscillator with 0.5 mm interconnect (the equivalent interconnect circuit is in Fig. 6.1) is

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121 INTERCONNECT NOR INV1 INV2 INV3 INV4 Figure 6.8 A five-stage ring oscillator with an interconnect feedback path between its last and first stages.

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122 1C1 Vm oGND o Vcs -o VOUT — o 'i Figure 6.9 An ECL inverter circuit configuration.

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123 •0.8 TIME (x10-^s) Figure 6.10 Transient response of a five-stage ring oscillator. In this figure, curve 1 is the output of INV 1, curve 2 is the output of INV 2 , and curve 3 is the input of NOR gate.

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124 shown in Fig. 6.10. In Fig. 6.10 curves 1, 2, and 3 represent the transient responses probed from the output of INV 1, INV 2, and the input of NOR, respectively. Curve 2 is the inverse of curve 1 providing a small finite time delay and curve 3 has the same polarity with curve 1 providing a larger finite delay due to delays in INV3 , INV4, and interconnect. To demonstrate the model utility, the transient simulation of the same oscillator without interconnect has been performed in Fig. 6.11. In Fig. 6.11 curves 1, 2, and 3 correspond to curves with the same numbers as those in Fig. 6.10. In general, the transient response in Fig. 6.11 is faster in Fig. 6.10. For a better comparison, the inputs of the NOR gate, which are the output of the interconnect (solid line) and the output of the INV 4 without interconnect (dashed line), are plotted in Fig. 6.12. It is clear that the oscillator with interconnect has a wider delay time between 50% turnon and 50% turn-off (=700 ps) in logic ringing compared with the oscillator without interconnect (=650 ps). The difference is due to the interconnect delay and the loading effects for INV 4. The interconnect contributes capacitance, resistance, and inductance effects which degrade the transient response of the ring oscillator. Thus, for a polysilicon interconnect, the difference in the delay time will be significantly enhanced due to a big polysilicon line resistance. In order to further probe the origin of the difference, the input and output from the "input transistor" (Vjfj connects BJT's base in Fig. 6.9) and the "level shifting transistor" (Vqut connects BJT's emitter in Fig. 6.9) of INV 4 have been shown in Fig. 6.13. It is interesting to note in Fig. 6.13 that the delay of the ECL gate comes mainly from

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125 •0.8 TIME (x10"^s) Figure 6.11 Transient response of a five-stage ring oscillator with an interconnect feed path between its first and last stages. In this figure, curve 1 is the output of INV 1, curve 2 is the output of INV 2, and curve 3 is the input of NOR gate .

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126 0.8 ^ -1 > LLI O < o > 1.2 -1.4

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127 TIME (x10"^s) Figure 6.13 Internal transient response of INV 4. In this figure, curve 1 is the input pulse of INV 4, curve 2 is the output signal at the cllector side of the input transistor in INV 4, and the curve 3 is the output signal of the level shifting transistor in INV 4.

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128 the input stage transistor (see curves 2 and 1 in Fig. 6.13). The level shifting transistor does not contributes much switching delay (see curves 3 and 2) . The loading effects for the level shifting transistor in inverter 4 degrade the transient response (delay time between 50% turn-on and 50% turn-off in curve 3). Since this 50% turn-on and 50% turn-off delay divided by the number of gates in the ring oscillator is used for evaluating the gate propagation delay (r^) in measurement, t^ will be underestimated if the effects of interconnect are not considered. 6 . 6 Summary and Discussion A flexible technique for developing IC interconnect circuit models and verifying their properties through simulation is presented. The effects of dispersion and attenuation on pulse propagation on the IC interconnect of an advanced bipolar technology is demonstrated. The interconnect model is easily implemented on SPICE circuit simulation using an approximation of a distributed subcircuit. The agreement between model prediction and measurement is excellent. This interconnect modeling is of importance for mixed-mode circuit simulation environment of cascaded logic gates connected by long sections of interconnection. For VLSI signal crosstalk between adjacent lines may be significant to distort the circuit response, a subject of the next chapter.

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CHAPTER SEVEN MODELING FOR COUPLED INTERCONNECTION LINES 7.1. Introduction As the speed of logic device increase, designers are confronted with limitations imposed by the packing and interconnect systems which could potentially degrade the electrical performance of the system [81]. Thus, in a high-speed digital integrated circuit, it is important to know the effects of signal coupling between different parallel interconnection lines. Coupled transmission lines have received extensive amounts of modeling in the literature [82-92]. Based on the solution of the coupled transmission line equations, accurate models have been derived primarily for the coupled pairs of symmetric lines. These models provide an analysis of the pulse propagation characteristics of the interconnections in digital as well as microwave circuits. In this chapter, a comprehensive study of coupled interconnect lines will be given. Even mode and odd mode capacitances which determine the phase delay and the coupling between two lines are discussed in Section 7.2. Signal losses, dispersion and crosstalk are presented in Section 7.3. In Section 7.4 the mode transition for a very fast signal propagation in picosecond photoconductor measurements is shown. An equivalent circuit model for coupled transmission lines in SPICE is demonstrated in Section 7.5. The model can be easily incorporated in the form of subcircuits making the coupled line 2n-port 129

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130 a standard circuit element for computer-aided circuit design and analysis. The simulated results and discussions are presented in Section 7.6. Conclusions are given in Section 7.7. 7.2. Even Mode and Odd Mode Analysis for Two Parallel Lines In order to properly analyze a periodic array of interconnect lines which have distributed characteristics, the interconnect system can be viewed as a coupled microstrip structure (Fig. 7.1). This structure consists of two adjacent lines which can support two different modes of propagation with different characteristic impedances and phase velocities. If the lines are symmetric, the propagation can be divided into even and odd modes corresponding to an even and odd synunetry about a plane which can be replaced by a magnetic or electric wall for the purpose of analysis. In Figs. 7.2 and 7.3 the solid line arrows represent the electric field lines, and the dashed line arrows represent the magnetic field lines. From the distribution of the fields in different modes, the capacitances in even and odd modes can be determined. The even mode capacitance, Cg is simply the sununation of the plate capacitance, Cp , the fringing capacitance, Cf, and a modified fringing capacitance, Cf' due to the influence of the magnetic wall [63] [93] [94]: Ce = Cp + Cf + Cf ' (7.1) w (7.2)

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131 '///////// / ///////T7. Figure 7 . 1 A coupled microstrip lines configuration. These interconnect lines have the same width and thickness,

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132 f-T-^Py '-f-r-j-^f -p-Cp^J^f Cf Cf Figure 7.2 A coupled transmission lines cross-section and break-up of capacitances for even mode. The solid line arrows are electrical field lines and the dashed line arrows are magnetic field lines.

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133 Figure 7.3 A coupled transmission lines cross-section and break-up of capacitances for odd mode. The solid line arrows are electrical field lines and the dashed line arrows are magnetic field lines.

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134 (^re)^/^ Cp Cf (7.3) 2 c Zq 2 Cf Cf' (7.4) 1 + Ki(h/s)tanh(10s/h) where the characteristic impedance Zq, the effective dielectric constant e^e' ^^'^ ^ constant K]^ in Eqs . (7.3) and (7.4) are: 60 8h We Zq = — ln(— + 0.25— ) (7.5) (6re)^/2 We h ^r2 + 1 fr2 1 ^ , ,^ + (1 + 10 -)-l/^ (7.6) 2 2 w Ki = exp[-0.1 exp(2.33 2.53 — )]. (7.7) h Similarly, the odd mode capacitance, Cq can be written as Co = Cp + Cf + Cgi + Cg2 + Cgf (7.8) In Eq. (7.8) the capacitances C„]^ and C„2 ^^e given as follows [63] [94]: £0«rl Wk' Cgi ln[2 ] for < k < 1/72 (7.9) n 1-yk' 7r€0€rl for 1/72 < k < 1 (7.10) l+7k ln( ) l-7k

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135 €0«r2 'fs 0.02 1 Cg2 = ln[coth(— ) + 0.65Cf + [ (€r2)''"^^ + (1 )] K Ah s/h f re (7.11) s/h where k = , s/h+2w/h k' = (l-k2)V2_ and the gate capacitance, C„^ due to a finite metal thickness is Cgt = • (7.12) s Effective dielectric constants e-^^^ and ej-e° ^°^ even mode and odd mode can be obtained by the equations below: Ce (7.13) -"o o _ _ ^re ° ^ (7.14) ^o where Cg^ and Cq^ are even and odd mode capacitances when there is no dielectric interface between regions 1 and 2 (e^l ^ ^r2 ^ ^q) The even mode and odd mode phase velocities, Vp® and Vp° and characteristic impedances describing the coupled transmission line behavior are (this assumes /ij= 1) : ^p® (7.15) ' (ere^)^/2

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136 /p° (7.16) Zo-TTX (7.17) Zo° — — . (7.18) c (CoCo^)^/2 where c is the speed light. The equations here will be used to investigate the signal crosstalk and mode transition in fast transient measurement in the next few sections. 7.3. Signal Dispersion. Loss and Coupling for Coupled Transmission Lines For the development of high speed large scale integrated circuits, it is necessary to characterize: 1) signal distortion due to losses (in the conductor and the substrate); 2) impedance discontinuities (at the line termination) ; 3) coupling effects between adjacent lines; and 4) dispersion caused by changing of the effective dielectric constant with frequency. The dispersive behavior of coupled microstrip lines describes frequency -dependent dielectric constants for different modes [63]: fr «re^ «re^(f) ^r T (7-19) 1 + G (f/fD)2 f r 're «re°(f) ^r 1 (7-20) 1 + G (f/fD)2

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137 where G 0.6 + 0.0045 Zq® for even mode 0.6 + 0.018 Zo° for odd mode zo" fj) •= for even mode 4/ioh zo° 4/ioh for odd mode . The above equations are better for CAD modeling than empirical fitting equations [95]. The dispersion concepts apply to the characteristics impedances yield [63]: Zo^s Zo^(O) Zo«(f) " Zo^ -— (7.21) 1 + G (f/fo)^-^ ZOos ZOo(O) Zo°(f) = Zo° — (7.22) 1 + G (f/fo)^-^ where Zo^(O) and Zo°(0) are the zero -frequency characteristic impedances given by Eqs. (7.17), (7.18), and 30 Wke' Zq®^ ln(2 ) for < ke < 1/72 30;r2 l+Vkg [ln(2 )]-^ for 1/72 < ke < 1 7er l-7ke 30 l+7ko' Zo°^ ln(2 ) for < kg < 1/72 7€r l-7ko' 30^2 l+7ko [ln(2 )]-! for 1/72 < kg < 1 7c r l-7ko

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138 JT w n w+s ke tanh( ) tanh( ), ke' (l-kg^)^/'^ 2 2h 2 2h WW JT W+S ko tanh( ) tanh( ), ko' =(l-ko^)^/^. 2 2h 2 2h Figures 7.4 and 7.5 show an example of frequency -dependent characteristics impedances and dielectric constants for even mode and odd mode, respectively where the coplanar line system is assumed symmetry. In Fig. 7.4 the even mode permittivity is larger than the odd mode permittivity due to a lower phase velocity. In high frequency Cj^g^ and Zq^ increase more rapidly than e^e^ ^'^^ ^0° because of the smaller fj) for even mode propagation. The parameter normally representing the signal crosstalk between two interconnect lines is the coupling coefficient [63] [96] [97]. From the even mode and odd mode characteristic impedances, the coupling coefficient CC is defined as zo^ Zo° CC . (7.23) Zo^ + Zo° To investigate the relationships of the coupling coefficient with the interconnect line width, substrate thickness, and interconnect lines spacing, CC versus w, s, and h are plotted in Figs. 7.6 and 7.7. When the substrate thickness is large, the interconnect cross coupling becomes smaller. Also, the narrower the interconnect spacing is, the larger is the signal coupling. This can limit VLSI packing density when high speed signal propagation is required. Applying the frequencydependent characteristic impedances in Eqs . (7.21) and (7.22), the

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139 180 130 a N FREQUENCY (Hz) Figure 7.4 Plot of the frequencydependent even-mode impedance, Zq® and odd-mode impedance, Zq°.

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140 FREQUENCY (Hz) Figure 7.5 Plot of the frequency -dependent even-mode permittivity, €j-^ arid odd-mode permittivity, ej.°.

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141 H Z o LU U. LU o o o z — i Q. o o U. JJ

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142 h-

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143 coupling coefficient versus frequency is obtained in Fig. 7.8. Since Zq^ increases more rapidly than Zo° at high frequencies, the coupling coefficient increases with frequency. This indicates that fast digital switching pulses have a higher cross coupling than steadystate signals . Coupled microstrip lines have primarily two types of losses: conductor (ohmic) loss and dielectric loss. The conductor loss results from a finite conductivity in the interconnect line and the dielectric loss is from conductivity in the substrate. The attenuation due to conductor loss for even mode propagation and odd mode propagation are [631: . 686 Rg 2 1 ZCe^ w ZCg^ s [ (1 + 5 — ) (15 — ) 240 TT Zq^ h c (Ce^)2 Z(w/h) 2h Z(s/h) 2h ZCg^ t + (1 + 5 — )] (7.24) Z(t/h) 2h .686 Rg 2 1 ZCq^ w ZCq^ s [ (1 + 5 — ) (15 — ) 240 TT Zo° h c (Co^)2 Z(w/h) 2h Z(s/h) 2h ZCq^ t + (1 + 5 — )] (7.25) Z(t/h) 2h and the attenuation due to dielectric loss are: €j^re^ tanS ad® = 27.3 (7.26) €j. fre° tanS = 27.3 (7.27) (^re°)^/^ «r "1 ^0

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0.6 144 Iz UJ o Li. U. LU o o o 0.5 Q. Z) o o 0.4 0.3 10^ J I I I I I I I 10 1 J ! I ' ' ' I 1 1 1 FREQUENCY (Hz) Figure 7.8 Plot of the coupling coefficient versus frequency.

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145 where tanS is the loss tangent of the dielectric substrate, and kg is the free space wavelength. 7.4. Mode Transition in Photonic Picosecond Measurement The signal propagation in even mode and odd mode can be investigated in picosecond time domain measurements by employing photoconductive circuit elements (PCE's). The test structures used in many of the PCE measurements are coupled transmission lines fabricated on a dielectric substrate. The PCE in this research is basically a thin film photoconductor on a silicon substrate [98]. Standard IC fabrication techniques followed by ion-beam irradiation are used to create the photoconductors with picosecond switching speeds [99]. The high recombination rates in the radiationdamaged PCE lead to a fast turnoff when the laser light ceases. This provides picosecond electrical switch. In general, two PCE's are fabricated with the coupled transmission lines on the same substrate for on-chip fast transient characterization as shown in Fig. 7.9. The first (pulse) PCE is stimulated by a colliding-pulse model-locked (CPM) laser in order to cause rapid conduction. Laser interaction with the PCE gap in microstrip conducts for a short period of time. The second (sampler) PCE samples the charge from the output waveform of a device under test. This sample of charge is produced at a constant difference in time of switching between the pulser PCE and sampler PCE. By varying the difference in the CPM laser beam path length, the entire transient response can be reconstructed. Figure 7.10 shows a coupled transmission

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146 w IE Pulser PCE Sampler PCE Figure 7.9 Coupled transmission lines layout used for PCE measurement. The left side photoconductor is a pulser PCE and the right side photoconductor is a sampler PCE.

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147 2.40E-01 2.20E-01 2.00E-01 1.80E-01 1.60E-01 C-1.40E-01 c ^1.20E-01 z a 1.00E-01 X D "8.00E-02 6.00E-02 4.00E-02 2.00E-02 O.OOE+00 -2.00E-02

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148 line picosecond photoconductive measurement response [100]. In Fig. 7.10 the measured PCE response for coupled transmission lines shows two switching peaks due to even mode to odd mode transition. Applying the frequency -dependent permittivities to Eq. (6.11), the pulse responses for even mode and odd mode can be simulated. The odd mode propagation response for a Gaussian input is faster than that of the even mode due to a higher phase velocity. If the mode splitting occurs during the signal transmission, two-peak pulse response can be obtained, as shown in Fig. 7.11. This pulse splitting is consistent with the PCE measurement above. The details of physical reasoning for mode splitting deserve a further research. 7.5. Equivalent Circuit Model for SPICE The equivalent circuit model for coupled transmission lines in SPICE simulation is developed in this section. The even mode and odd mode capacitances shown in Sec. 7.2 are used to determine the self capacitances (Cn and C22) . mutual capacitance (C]^2) > self inductance (hii and 1.22)1 ^rid mutual inductance (L]^2) ^"^ Fig7.12 as: 1 Cll = (Ci^ + Ci°) (7.28) 2 1 C22 = (C2^ + C2°) (7.29) 2 1 C12 (Cl° Ci^) (7.30) 2

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149 200 TIME (x10"''^s) Figure 7.11 Simulated signal propagation on a coupled interconnect lines for even mode and odd mode splitting.

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150 Rl 1 Ml Line 1 o \Y ^^W^ \ \ Line 2 o1 2 R22 >L22 C12 '1 1 C22 Figure 7.12 Equivalent circuit model per unit length for coupled transmission lines.

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151 Lii ( + ) (7.31) L22 ( + ) (7.32) 2 C2°^ C2®^ Li2 ( ) (7.33) 2 Ci^^ Ci°^ where C]^^ is the even mode capacitance for interconnect 1, C]^° is the odd mode capacitance for interconnect 2, C2^ is the even mode capacitance for interconnect 2, C2° is the odd mode capacitance for interconnect 2. The interconnect line resistances are given as: Rll = (7.34) '^liwiltii R22 = (7-35) a22W22^22 where oii is metal 1 resistivity, wn is the metal 1 width, t^i is the metal 1 thickness, ^22 ^^ ^^^ metal 2 resistivity, W22 is the metal 2 width, and t22 is the metal 2 thickness. The interconnect circuit elements above can be used for SPICE/SLICE circuit simulation in a distributed circuit network. The use of frequency -dependent circuit elements is neglected here, but can be added to the simulation using the modeling topology developed in Chapter 6 (e.g., eeff(f)). The voltages and currents on coupled transmission lines are described by

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152 the differential equations below: dVi ail 3l2 Rllll Lii Li2 (7.36) ax at at av2 ai2 ail -R22I2 L22— L12 (7.37) ax at at ail dvi dxi Cii + CI2 (7.38) ax at at ai2 av2 av2 C22 + C12 • (7.39) ax at at Those equations above can be solved in a straightforward fashion in the SPICE/SLICE circuit analysis presented in the next section. 7.5. SPICE Simulations and Discussions The interconnect circuit model developed in Section 7.4 was implemented in SPICE/SLICE for transient response. Figure 7.13 shows three interconnect lines transient response in which curve 1 is from the end point of an active interconnect line and curves 2 and 3 are from the end point of inactive interconnect lines 2 and 3, respectively. It is interesting to note that during switching the inactive interconnect lines (curve 2 and curve 3) are activated by the active interconnect signal line, especially for the nearest neighbor line. The signal coupling results from the coupled electric field and magnetic field effects between interconnect lines. This is represented by the mutual capacitance and mutual inductance in the equivalent

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153 Lll o < Io > 1.1 0.80.5 0.2 •0.1 1.2 1.6 TIME (xlO'^s) Figure 7.13 Step response of 5 cm coupled interconnect lines. In this plot, curve 1 is a step input, curve 2 is the step response on the active (signal) line, curve 3 and 4 are the signal crosstalk on the inactive lines with 50 Q load resistances on each side.

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154 circuit model. Since the capacitance and inductance play an important role in signal transmission and crosstalk, Cii, C]^2> Ml' ^^^ ^12 versus w and s are presented in Figs. 7.14, 7.15, 7.16, and 7.17, respectively. In those figures Cii and €^^2 increase with w due to normal capacitance effects (C aw), but decrease with s. L]^]^ and L]^2 decrease with w and s. The inverse proportionality of C2^2 ^^'^ ^,2^2 with s (Figs. 7.15 and 7.17) happens because the signal crosstalk is reduced when the space between conductors increases . By varying 2% value of the circuit elements individually in SPICE simulation, the circuit elements sensitivities are obtained. The most sensitivity component in the equivalent circuit is C]^2 which describes the significance of electric coupling. Further simulation of the coupled interconnect end resistance (see Fig. 7.18) indicates that when the neighbor interconnect is floating (Rl '») , the signal crosstalk becomes larger due to an increase in mutual coupling. In general, the signal crosstalk can be reduced by using adjacent shielding ground lines [97], a second ground plane over the interconnects [96], a larger substrate thickness, or a wide interconnect spacing. 7 . 6 Conclusions The coupled interconnect lines for even mode and odd mode analyses have been studied. Signal loss, dispersion, and crosstalk are discussed. From the even mode and odd mode capacitances, the equivalent circuit model for coupled transmission lines in SPICE simulation is constructed. The space between interconnect lines, the substrate

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155 3.1 2.6 E o CL O 2.1 -: 1.6

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156 E o LL Q. O u.o

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157 4.9 4.3E o X c 3.1 3.7 W (x10-^cm) Figure 7.16 Plot of Lii versus the interconnect line width, w at different coupled interconnect line spacing, s.

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158 1 .D 1.4

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159

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160 thickness, and the interconnect width are important for signal coupling. For a set of coupled lines, the induced signal on the inactivated lines depends on the coupling coefficients and the slew rate of the propagating signal. This coupling becomes stronger for very high frequency. In the equivalent circuit model, the mutual capacitance is the most significant component describing signal crosstalk. This capacitive cross coupling causes pickup of any signal carried on a nearby conductor track.

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CHAPTER EIGHT SUMMARY AND CONCLUSIONS The modeling and characterization of bipolar transistors and interconnects for circuit simulation has been presented in earlier chapters. This work provides a comprehensive two-dimensional circuit and interconnect modeling for advanced bipolar IC techniques useful in computer-aided device and circuit design. Illustrative measurements and simulations demonstrate the modeling accuracy. The major accomplishments of this study are: first, implemented the user-def ined-controlled-sources techniques for new circuit model development. By using the voltage -controlled current sources, newly developed circuit model equations are inserted in UDCSs which are compiled with original SPICE circuit matrix programs for model implementation. Thus, physical mechanisms such as collector current spreading, emitter crowding, and sidewall injection can be included, second, explored the two-dimensional collector current spreading mechanism in quasi-saturation. The collector current spreading ameliorates base pushout to increase the BJT's current gain and cutoff frequency, third, developed a quasi-2-D circuit model for collector current spreading effects. The model refines the previous 1-D physical model for high current transients, fourth, developed a physics -based current -dependent base resistance model for all injection levels. The base resistance model accounts for the physical effects of base width modulation, base conductivity modulation, emitter current crowding, and 161

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162 base pushout, fifth, developed a circuit model for transient emitter crowding, sidewall injection effects. The model represents the nonuniform current and charge distribution under the emitter and at the emitter-base sidewall and the current -dependent base resistance in a unified manner, sixth, predicted s -parameter measurement responses using a physical device simulator and newly developed software. The parasitics effects of the test structures are included in the modeling package, seventh, improved the single interconnect model for advanced IC cross-section profiles. The model includes the effects of conductor loss, dielectric loss, and dispersion, eighth, refined the coupled interconnect model for signal coupling and crosstalk. Finally, implemented the mixed-mode circuit simulation including the bipolar transistors and interconnects. The author suggests the following research based on the methods and approaches of the present study: 1) explore the physics details about the transient collector spreading mechanism. One can start this by probing the transient device simulations in quasi-saturation; 2) investigate the three-dimensional behavior of collector spreading, emitter crowding, and sidewall injection by investigating the 3-D device simulation or strategical designed test structures for different emitter widths, emitter lengths, shapes of emitter area; 3) develop a comprehensive circuit model for the coupling effects of collector current spreading and emitter current crowding; 4) explore the timedependent base resistance model in digital switching form the physical insight of transient device simulation ; 5) include more experimental studies for s-parameter terminal responses; 6) explore more

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163 experimental evaluations for current spreading and transient crowding based on strategical test structures; 7) investigate the on-chip fast transient measurement of the advanced bipolar transistors by photoconductive circuit element techniques; 8) develop the multilevel interconnect model from 3-D capacitance solver for process diagnosis and circuit simulation; 9) include the frequency -dependent circuit elements in SPICE transient simulation for signal dispersion in very fast switching transient; 10) extend the mixed-mode circuit simulation for various regions of BJT operation in which the collector current spreading or emitter current crowding or both are significant.

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APPENDIX A TWO-DIMENSIONAL NUMERICAL SIMULATION WITH PISCES A. 1 Introduction The two-dimensional bipolar transistor models, physics-based current -dependent base resistance, and s-parameter measurement prediction for advanced bipolar transistors in Chapters 2, 3, 4, and 5 are developed using the physical insights gained from PISCES based twodimensional device simulations. Since the physical parameters internal to device simulators are critical to the accuracy of the device simulation, the physical modeling in PISCES is discussed in this Appendix. Also, some controversial parameters for heavy doping effects are addressed here in order to correctly interpret the simulation results . A. 2 Physical Mechanisms in PISCES II PISCES is a two-dimensional, two-carrier semiconductor device simulator which predicts transistor (e.g., BJT, NMOS , CMOS, SOIMOSFET, power device, etc) electrical behavior under steadystate , transient, and small -signal excitations. In general, device simulators solve the partial differential Poisson equation (eV'^V = -qCp-n+Np -N^' )-pp) and continuity equations (Sn/St = 1/q VJ^^-U^^, dp/dt = -1/q VJpUp) by finite element methods (PISCES) or finite difference methods (SEDAN, BAMBI). 164

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165 In the continuity equations above, the recombination models supported in PISCES are the Shockley-Read-Hall (SRH) model and Auger recombination model: Pn "ie^ UsRH (A.l) EfEi Ei-Et rp[n+nieexp( )] + rn[p+nieexp( )] kT kT UAuger " CnCpn^-nnie^) + Cp(np2-pnie^) (A. 2) where E^ is the intrinsic Fermi energy, Ejis the trap energy level, ^ie ^s t^® effective intrinsic concentration including the bandgap narrowing effects [101] 9x10"^ N(x,y) N(x,y) 1 nie(x.y) niexp{ {In + [(In )2 + -]l/2))_ (a. 3) 2kT/q 10^7 10^7 2 T^ and Tp are the electron and hole lifetimes which are concentration dependent : ''nO rn(x,y) (A. 4) l+N(x,y)/NsRH-n »"pO 'pCx.y) , (A. 5) l+N(x,y)/NsRH-p and c^ and Cp are Auger coefficients for n"*" and p"^ materials. The default parameters for NsRH-n> ^sRH-p. Cj^, and Cp in PISCES are 5 x lO^^, 5 x 10^^, 2.8 x lO^^^, and 9.9 x lO^^^^ respectively. Note that the notation for c^ and Cp is different than the conventional

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166 one which defines Cj^ for electron recombination in p"*"-type silicon and Cp for hole recombination in n"''-type silicon. Due to the difficulty in characterization of heavy doping effects, the controversial physical parameter c^ is in the range of 1 x 10'^^ to 3 x 10"^^ [102] [103]. Different values for c^ are used in various device simulators (0.5 x 10-3^ in [104], 1.0 X 10-31 [105], 1.5 x lO'^^ [106], and 2.8 x lO'^l [107]). Another controversial issue is the mobility model in PISCES. Due to a different scattering mechanism and Coulomb force on electrons (repulse force) and holes (attract force) in the heavily doped n"*" material, the majority carrier mobility and minority carrier mobility can be significantly different. Models for explaining the physical origin of the difference are presented in [108-110] . Even though the physical mechanisms are not clearly understood, the difference between the majority and the minority carrier mobilities is clearly established and it is enhanced in the highly doped region [111-113]. This difference is not accounted for at all in PISCES -II and deserves consideration in PISCES simulation interpretation. A. 3 Discussion The self-aligned polysilicon-emitter transistor has become the predominant device structure for today's high-performance bipolar VLSI circuits due to its low base current or high /9. This high current gain is usually traded for a low base resistance (high base doping) to increase f'p [114] [115]; however, the polysilicon and monosilicon interface is not readily controllable which results in a process-

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167 dependent surface recombination at the polysilicon contact. The process variation and the uncertainties in the polysilicon heavy doping parameters make it difficult to match simulation results with measurements . In order to get the representative simulation results, we model the polysilicon contact by an effective surface recombination velocity Sp in the range of 1 X 10^ to 5 X 10^ cm/s [19]. By adjusting Sp, c^, mobilities, and carrier lifetimes to match dc measurements, reasonable simulation can be obtained. In addition, The uncertainties caused by the heavy doping effects and the polysilicon interface are critical in the emitter design, but are less significant for analysis of collector (collector spreading in Chapter 2) , and analysis of the base (base resistance in Chapter 3, emitter crowding in Chapter 4). In fact, the author suggests that the circuit designers look at both the physical insight from device simulations and quantitative terminal responses from device measurements. The modeling implementation techniques for new circuit model development is presented in Appendix B.

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APPENDIX B BIPOLAR TRANSISTOR MODELING IMPLEMENTATION TECHNIQUES ON SLICE/SPICE B. 1 Introduction The multidimensional current effects developed in chapters 2, 3, and 4 are not properly accounted for in the existing models built into the common circuit simulator SPICE. A flexible set of subroutines has therefore been developed which enable one to implement the novel bipolar transistor model into the SLICE, a Harris Corporation derivation of the SPICE program. The use of user-defined controlled sources for SOI MOSFET modeling was first investigated by S. Veeraraghavan et al . [23]. The methodology for implementing dc , transient, and small-signal models in the form of flexible subroutines for advanced bipolar transistor into SLICE is presented here. B. 2 User-DefinedControlledSources The flexible modeling subroutines, user-defined-controlledsources (UDCS's), in the SLICE circuit simulator are typically used for new circuit model development. UDCS's include 1) voltage-controlled voltage sources, 2) voltage-controlled current sources, 3) currentcontrolled voltage sources, and 4) current-controlled current sources. The UDCS's nodes are automatically incorporated by the SLICE program [115] into a circuit simulation matrix during the computer simulation of a circuit. When using a UDCS form of the model equations, one can modify the transistor behavior and not be concerned with the matrix 168

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169 operation, memory management, and data structures of the SPICE circuit simulator. The formulation of UDCS subroutines requires 1) a device parametric description, 2) conservation of numerical overflow, 3) modeling the device current -voltage relations, and 4) evaluating the device charging currents. Figure B.l is a flow chart outlining the steps necessary to write a UDCS subroutine. At the top of the UDCS subroutine, one must define the device model parameters and the model control nodes. Then the SPICE subroutine PNJLIM is called in order to prevent numerical overflow [117] . Next, the presentation of the device's currents as a function of node voltages is added to the subroutine. At this point the dc UDCS subroutine has been completed. Small-signal capability may be added to the UDCS subroutine by calculating the device's small-signal components in terms of dc bias and inserting the information in the UDCS subroutine. Transient capability and charge -control modeling can also be added to the UDCS subroutine. First the SPICE COMMON block STATUS must be inserted into the subroutine and then device model parameters and transient model control nodes are defined. An initialization of the transient model values is performed at time equals zero. Numerical overflow must be prevented as in the dc UDCS subroutine. Finally, transient current and transient conductance representations are appended to the UDCS subroutine. Note, that the current-voltage relations and transient current derivations entered into the UDCS subroutine are based on the relevant analytical device model.

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170

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171 small sior^ Calc^ate small signal components, C=5Q/av, g=3I/aV in terns of IX bias condition Insert small signal elements to UDCS subroutine DC transient

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172 The transient current, dQ/dt, and transconductance , dl/dV, at different time points are calculated as follows: dQ 2Q[Vn,.i(t)] 2Q(t) dQ(t) — [Vm(t)] [ + ] (B.l) dt dt dt dt 2 dQ gm [Vm-l(t)] (B.2) dt dV where m and m-1 are the present and previous time points, respectively. The numerical integration methods, such as 1) the implicit second-order trapezoidal rule or 2) the Gear-2 method, are available for the SPICE transient calculation. It is necessary to control the local truncation error using the time step, in order to obtain reasonable solution accuracy and stability in the transient simulation [118]. Since the bipolar transistor model has exponential voltagecontrolled current source terms, it is possible to produce an unbounded solution point during the Newton-Raphson iterations. This numerical overflow problem should be avoided by setting the critical voltage as [118] [119] kT kT Vcritical = — ln( ). (B.3) q 72 q Is Then, change the voltage increments during the Newton-Raphson iterations smoothly as [119] kT qAVi AVi ln(l + ). (B.4) q kT

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173 The subroutine PNJLIM is SPICE is called in the UDCS subroutines to prevent the overflow problems. In addition, some of the built-in parameters in SLICE, such as the absolute tolerance, e^, the relative tolerance, e,., and the charge tolerance, «(,> ^^^i be modified to avoid divergence. This is especially important when the circuit is illconditioned (i.e. the nodal capacitance is very small and the nodal inductance is large) . B.3 UDCS Implementation of the BJT model The UDCS implementation of SPICE Gummel-Poon model is presented in this section in order to demonstrate flexible user-defined subroutines. The standard SPICE Gummel-poon implementation uses the following collector and base current equations [120]: Is qVfiE' q^Bc' Is q^Bc' Ic [exp( ) exp( )] — [exp( ) 1] qb kT kT ^R kT Is qVfic' q^Bc' [exp( ) 1] C4lsexp( ) 1] (B.5) pR kT n^kT Is q^BE' Is qVfic' Ib = — [exp( ) 1] + — [exp( ) 1] ^F kT ^R kT q^BE' q^Bc' + C2ls[exp( ) 1] + C4ls[exp(— ) 1] (B.6) n^kT n„kT "^1 "^19 1/9 where qt, = — + [( — ) + q2] ' . 2 2

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174 qi 1 + + Is qVfiE' Is q^Bc' q2 [exp( ) 1] + [exp( ) 1] Ik kT Ikr kT Transient modeling of bipolar transistor behavior is essential for simulating high-speed bipolar switching circuits. Modern digital bipolar circuit models must be able to predict the behavior of ECL, and other logic family designs. During the bipolar transistor transient operation, it is necessary to consider the time-varying base-emitter and base -collector junction charging currents. The charge, Qbe> associated with the base-emitter junction includes the neutralized charge (mobile carrier charge) and the unneutralized charge (deletion charge) which can be represented as: q^BE' QbE IST [exp( ) 1] + CjEo kT Vbe' V (1 )-"'e dV. 4>^ (B.7) Similarly, the charge, Qbc> associated with the base-collector junction is given as : qVBc' QbC = IS'"R [exp( ) 1] + Cjco kT Vbc' V (1 )-'"^ dV. (B.8)
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175 Is q^BE' qVfic' Is qVgc' — [exp( ) exp( )] — [exp( ) 1] qb kT kT ^R kT Is q^Bc' q^Bc' ^Qbc [exp( ) 1] C4lsexp( ) -1] (B.9) ^R kT iickT dt Is q^BE' Is q^Bc' Ib [exp( ) 1] + — [exp( ) -1] ^F l^T ^R kT q^BE' q^Bc' ^Qbc ^Qbe + C2ls[exp( ) 1] + C4ls[exp( ) 1] + + kT kT dt dt (B.IO) The charge control circuit model implemented in the UDCS subroutines is shown in Fig. B.2. Each voltage -controlled current source in Fig. B.2 is one UDCS subroutine in the SPICE subcircuit. The UDCS subroutines calculate the collector, base, emitter-base transient, and collector-base transient currents as (B.5)-(B.8), respectively. For the UDCS bipolar modeling, a controlled subroutine calls the transient UDCS subroutines in coordination with dc UDCS subroutines in response to a transient stimulus. The resistance R^, Rg, and Rg are incorporated into the subcircuit file. B.4 Conclusions The Gummel-Poon bipolar transistor modeling using UDCS subroutines has been described. The UDCS approach is an efficient, flexible way to incorporate new device models into the SPICE/SLICE circuit simulator. The UDCS approach works independently of the matrix operations, the memory management, and the various nvimerical solution

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176 BO VvVFigure B.2 Network representation of the Gummel-Poon model for UDCS implementation.

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177 techniques Implemented Into the SPICE/SLICE program. The use of UDCS approach greatly reduces the time for inserting new model equations into the SPICE/SLICE program. In addition, the UDCS subroutine provides a method for simulating device behavior which can not be described in a closedform analytic solution.

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REFERENCES 1. I.E. Getreu, Modeling the Bipolar Transistor . New York: Elsvier, 1978. 2. F.-Y Chang and L. F. Wagner, "The generation of threedimensional bipolar transistor models for circuit analysis," IBM J. Res. Develop. . vol. 29, pp. 252-262, May 1985. 3. C. K. Kirk, "A theory of transistor cutoff frequency (fi;) falloff at high current density," IEEE Trans. Electron Devices , vol. ED-9, p. 164 1962. 4. A. van der Ziel and D. Agouridis, "The cutoff frequency falloff in UHF transistors at high currents," Proc . IEEE , vol. 54, pp. 411-412, Mar. 1966. 5. R. J. Whitter and D. A. Tremere, "Current gain and cutoff frequency falloff at high currents , " IEEE Trans. Electron Devices , vol. ED-16, pp. 3957, Jan. 1969. 6. H. C. de Graaff, "Collector models for bipolar transistors," Solid-state Electron. , vol. 16, pp. 587-600, 1973. 7. D. L. Bowler and F. A. Lindholm, "High current regimes in transistor collector regions," IEEE Trans. Electron Devices , vol. ED-20, pp. 257-263, Mar. 1973. 8. G. Rey, F. Dupuy, and J. P. Bailbe, "A unified approach to the base widening mechanisms in bipolar transistors," Solid-State Electron. . vol. 18, pp. 863-866, 1975. 9. J. W. Slotboom, "Computer-aided two-dimensional analysis of bipolar transistors," IEEE Trans. Electron Devices , vol. ED-20, pp. 669-679, Aug. 1973. 10. J.-S. Yuan, W. R. Eisenstadt, and J. G. Fossum, "Multidimensional current modeling in advanced bipolar transistors," presented at the SRC Topical Res. Conf . : Bipolar Device Modeling, May 1987. 11. G. M. Kull, L. W. Nagel, S.-W. Lee, P. Lloyd, E. J. Prendergast, and H. Dirks, "A unified circuit model for bipolar transistors including quasi-saturation effects," IEEE Trans. Electron Devices , vol. ED-32, pp. 1103-1113, June 1985. 178

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179 12. H. Jeong and J. G. Fossum, "Physical modeling of high-current transients for bipolar transistor circuit simulation," IEEE Trans. Electron Devices , vol. ED-43, pp. 898-905, April 1987. 13. J. G. Fossum, H. Jeong, J. S. Yuan, and W. R. Eisenstadt, "Steadystate and transient SPICE2 modeling of high current phenomena in ECL BJT's," SRC Topical Res. Conf . , April 1986. 14. M. R. Pinto, C. S. Rafferty, and R. W. Dutton, PISCES-II User Manual, Stanford Electronics Lab., Stanford Univ., 1984. 15. H.-M. Rein, H. StUbing, and M. Schroter, "Verification of the integral charge -control relation for high-speed bipolar transistors at high current densities," IEEE Trans. Electron Devices , vol. ED-33, pp. 1070-1076, June 1985. 16. S. Konaka, Y. Yamamoto, and T. Sakai, "A 30-ps Si bipolar IC using super self -aligned process technology," IEEE Trans. Electron Devices , vol. ED-33, pp. 526-531, April 1986. 17. D. D. Tang et al . , "Design considerations of high-performance narrowemitter bipolar transistors," IEEE Electron Device Lett. . vol. EDL-8, pp. 174-175, April 1987. 18. C. T. Chuang, D. D. Tang, G. P. Li, and E. Hackbarth, "On the punchthrough characteristics of advanced selfaligned bipolar transistors," IEEE Trans. Electron Devices , vol. ED34, pp. 15191524, July 1987. 19. A. Neugroschel, M. Arienzo, Y. Komem, and R. D. Isaac, "Experimental study of the minority-carrier transport at the polysilicon interface," IEEE Trans. Electron Devices . vol.ED-32, pp. 807-816, April, 1985. 20. K. N. Bhat, M. J. Kumar, V. Ramasubramanian, and P. George, "The effects of collector lifetime on the characteristics of high-voltage power transistors operating in the quasi -saturation region," IEEE Trans. Electron Devices , vol. ED-34, pp. 11631169, May 1987. 21. P. Spirito and G. Cocorullo, "A measurement technique to obtain the recombination lifetime profile in epi layers at any injection level," IEEE Trans. Electron Devices , vol. ED-35, pp. 2546-2554, Dec. 1987. 22. J.-S. Yuan and W. R. Eisenstadt, "Flexible bipolar transistor modeling subroutines implemented on the SLICE/SPICE circuit simulator," Technical Report lEG 87-001, Integrated Electronics Center, Univ. of Florida, Feb. 1987.

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180 23. S. Veeraraghvan, J. G. Fossum, and W. R. Eisenstadt, "SPICE simulation of SOI MOSFET integrated circuits," IEEE Trans. CAD /I CAS . vol. 5, p. 653, Oct. 1986. 24. P. J. Zdebel, R. J. Balda, B.-Y. Hwang, V. d. 1. Torre, and A. Wagner, "Mosaic III -A high-performance bipolar technology with advanced self -aligned devices," in Proc . of IEEE Bipolar Circuits and Technol. Meeting . Sept. 1987. 25. S. M. Sze, Physics of Semiconductor Devices . New York: WileyInterscience, 1981. 26. B.-Y. Hwang, P. J. Zdebel, R. J. Balda, G. G. Sweeney, and V. d. 1. Torre, "Lateral scaling effects of double-poly-silicon advanced self -aligned bipolar npn transistors," in Proc. of IEEE Bipolar Circuits and Technol. Meeting . Sept. 1987. 27. P. May, J.-M Halbout, C. T. Chuang, and G. P. Li, "Waveform measurements in high-speed silicon bipolar circuits using a picosecond photoelectron scanning electron microscope," IEEE Trans. Electron Devices , vol. ED-35, pp. 1126-1129, July 1988. 28. D. D. Tang and P. M. Soloman, "Bipolar transistor design for optimized power-delay logic circuits, " IEEE J. Solid-State Circuits , vol. SC-14, pp. 659-684, August 1979. 29. M. H. White and M. 0. Thurston, "Characterization of microwave transistors," Solid-State Electron. . vol. SC-13, pp. 523-542, 1970. 30. W. M. C. Sansen and R. G. Meyer, "Characterization and measurement of the base and emitter resistances of bipolar transistors," Solid-State Electron. . vol. SC-13, pp. 533-542, 1970. 31. S. T. Hsu, "Noise in high-gain transistors and its application to the measurement of certain transistor parameters," IEEE Trans. Electron Devices , vol. ED-18, pp. 425-431, July 1971. 32. E. A. Valsamakis, "Power dissipation calculation of the base spreading and contact resistance of transistors at low currents and low frequencies," IEEE Trans. Electron Devices , vol. ED31, pp. 409-412, April 1984. 33. T. H. , Ning and D. D. Tang, Method for determining the emitter and base series resistances of bipolar transistors," IEEE Trans. Electron Devices , vol. ED-31, pp. 409-412, April 1984. 34. A. Neugroschel, "Measurement of the low-current base and emitter resistances of bipolar transistors," IEEE Trans. Electron Devices , vol. ED-34, pp. 817-822, April 1987.

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181 35. H. C. de Graaff and J. G. Groot, "The SIS tunnel emitter: A theory for emitter with thin interface layers," IEEE Trans. Electron Devices , vol. ED-26, pp. 1771-1776, Nov. 1979. 36. J. Luo and S. Graham, "A quasi 3-D base resistance RBI simulator for non-walled emitter transistors," in Proc . of IEEE Bipolar Circuits and Technol. Meeting . Sept. 1987. 37. J.J. Liou, F. A. Lindholm, and J. S. Park, "Forward-voltage capacitance and thickness of p-n junction space-charge regions," IEEE Trans. Electron Devices , vol. ED-34, pp. 1571-1579, July 1987. 38. A. H. Marshak and C. M. Van Vliet, "Electrical current and carrier density ion degenerate materials with non-uniform band structures," Proc. IEEE , vol. 72, pp. 148-164, Jan. 1984. 39. H. C. de Graaff and W. J. Kloosterman, "New formulation of the current and charge relations in bipolar transistor modeling for CACD purposes," IEEE Trans. Electron Devices , vol. ED-32, pp. 2415-2419, Nov. 1985. 40. R. M. Burgerand and R. P. Donovan, Fundamental of Silicon Integrated Device Technology , vol. II, Englewood Cliffs, NJ : Prentice Hall, 1968. 41. J. R. Hauser, "The effects of distributed base potential on emitter-current injection density and effective base resistance for strip transistor geometries," IEEE Trans. Electron Devices , vol. ED-11, pp. 238-242, 1964. 42. H. N. Ghosh, "A distributed model of the junction transistor and its application in the prediction of the emitter-base diode characteristics, base impedance, and pulse response of the device," IEEE Trans. Electron Devices , vol. ED-11, pp. 513-531, Oct. 1965. 43. H. H. Berger, "Models for contacts to planar device," Solid-State Electron. . vol. 5, pp. 145-158, 1971. 44. J. E. Lary and R. L. Anderson, "Effective base resistance of bipolar transistors," IEEE Trans. Electron Devices , vol. ED-32, pp. 2503-2505, Nov. 1985. 45. A. B. Philips, Transistor Engineering . New York: McGraw Hill, 1962. 46. W. Filensky and H. Beneking, "New technique for determination of static emitter and collector series resistances of bipolar transistors," Electron. Lett. . vol. 17, pp. 503-504, 1981.

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182 47. P. Hower and W. G. Einthoven, IEEE Trans. Electron Devices , vol. ED-25, pp. 465-471, April 1978. 48. L. C. McBride, "Large-signal modeling of bipolar transistors for computer-aided circuit analysis," Technical Report 4825-6, Stanford Electronics Lab., Stanford Univ., 1971. 49. D.A. Divekar and R. W. Dutton, IEEE J. Solid-State Circuits , vol. SC-11, p. 726, May 1976. 50. J.-S. Yuan and W. R. Eisenstadt, "Two-dimensional modeling of advanced bipolar transistors and interconnects for mixed-mode circuit simulation," SRC Bipolar Contract Review Meeting and BiCMOS roadmap . April 1988. 51. J.J. Liou, J.-S. Yuan, and W. R. Eisenstadt, "two-dimensional emitter-base junction capacitance for bipolar circuit simulation, " in Proc . of IEEE Workshop on Numerical Process and Device Modeling for Integrated Circuits . NUPAD-II, May 1988. 52. G. A. M. Hurkx, "On the sidewall effects in submicrometer bipolar transistors," IEEE Trans. Electron Devices , vol. ED-34, pp. 19391946, Sept. 1987. 53. D. P. Verret and J. E. Brighton, "Two-dimensional effects in the bipolar polysilicon self -aligned transistor," IEEE Trans . Electron Devices , vol. ED-34, pp. 2297-2303, Nov. 1987. 54. H. M. Rein and M. Schroter, "A compact physical large -signal model for high-speed bipolar transistors at high current densities part II: two-dimensional model and experimental results," IEEE Trans. Electron Devices , vol. ED-34, pp. 17521761, Aug. 1987. 55. D. D. Tang, "Switch-on transient of shallow-profile bipolar transistors," IEEE Trans. Electron Devices , vol. ED-32, pp. 22242227, Nov. 1985. 56. K. Sukulal and K. N. Bhat, "Current gain of narrow-base transistors," Solid-State Electron. . vol. 29, pp. 311-316, 1986. 57. P. van Wingen and E. Wolsheimer, "A new straightforward calibration and correction procedure for "on wafer" highfrequency s-parameter measurements (45MHz-18GHz) , " in Proc. IEEE Bipolar Circuits and Technol. Meeting . Sept. 1987. 58. J.-S. Yuan and W. R. Eisenstadt, "Circuit modeling of collector current spreading effects in quasi-saturation for advanced bipolar transistors," Solid-State Electron. . to be published.

PAGE 200

183 59. J.-S. Yuan, J. J. Liou, and W. R. Eisenstadt, "A physics -based current -dependent base resistance model for advanced bipolar transistors," IEEE Trans. Electron Devices , vol. ED-35, pp. 10551062, July 1988. 60. J.-S. Yuan and W. R. Eisenstadt, "S-parameter measurement prediction for bipolar transistors using a physical device simulator," in Proc. of IEEE Bipolar Circuits and Technol. Meeting . Sept. 1987. 61. M.-S. Jo, D. E. Burk, J.-S. Yuan, and W. R. Eisenstadt, "Improved SLICE simulation of digital bipolar transistors using s-parameter data, "s-parameter data, in Proc. of IEEE Bipolar Circuits and Technol. Meeting . Sept. 1986. 62. E. Strid, "Wideband probing techniques for planar devices," in Proc. of SPIE Meeting . May 1987. 63. K. C. Gupta, R. Garg, and R. Chadha, Computer-Aided-Design of Microwave Integrated Circuits . Dedham, MA: Artech House, 1981. 64. S. F. Adams, Microwave Theory and Applications . Englewood Cliffs, NJ: Prentice-Hall, 1969. 65. H. Hasegawa, M. Furukawa, and H. Yanai, "Properties of microstrip lines on Si-Si02 system," IEEE Trans . Microwave Theory and Techniques , vol. MTT-19, pp. 869-881, Nov. 1971. 66. R. A. Lawton, N. S. Nahman, J. M. Biegelow, "A solid-state reference waveform standard," IEEE Trans. Instruments and Measurements . " vol. 33, pp. 201-205, Sept. 1984. 67. R. A. Pucel, D. J. Masse, and C. P. Hartwig, "Losses in microstrip," IEEE Trans. Microwave Theory and Techniques , vol. MTT-20, pp. 342-350, June 1968. 68. H. A. Wheeler, "Transmission line properties of a strip on a dielectric sheet on a plane," IEEE Trans . Microwave Theory and Techniques , vol. MTT-25, pp. 631-647, Aug. 1977. 69. M. V. Schnider, "Microstrip line for microwave integrated circuits," Bell Svst. Tech. J. . vol. 48, pp. 1421-1422, 1969. 70. P. Pramanick and P.Bhartia, "An accurate description of dispersion in microstrip," Microwave J . . vol. 26, pp. 89-93, Dec. 1983. 71. J.-S. Yuan and W. R. Eisenstadt, "S-parameter measurement predciton of bipolar transistor using a physical device simulator," IEEE Trans. Electron Devices , vol. ED-35, pp. 16331639. Oct. 1988.

PAGE 201

184 72. C. J. Stanghan and B. M. McDonald, "Electrical characterization of packages for high-speed integrated circuits," IEEE Trans. Components. Hybrid, and Manufac. Technol. . vol. CHMT-8, pp. 468473, Dec. 1985. 73. W. R. Eisenstadt and J.-S. Yuan, "Interconnect circuit model development based on 2-D device simulation," IEEE Workshop on Numerical Process and Device Modeling for Integrated Circuits . NUPAD-II, May 1988. 74. W. R. Eisenstadt and J.-S. Yuan, "Interconnect circuit model development for SPICE," SCR Technol. Fair . Oct. 1988. 75. K. K. Li, G. Arjavalingam, A. Dienes, and J. R. Whinnery, "Propagation of picosecond pulses on microwave striplines," IEEE Trans. Microwave Theory and Techniques , vol. MTT-30, Aug. 1982. 76. R. L. Veghte and C. A. Balanis , "Dispersion of transient signals in microstrip transmission lines," IEEE Trans. Microwave Theory and Techniques , vol. MTT-34, pp. 1427-1436, Dec. 1986. 77. J. F. Whitaker, T. B. Norris, G. Mourou, and T. Y. Hsiang, "Pulse dispersion and shaping in microwave lines," IEEE Trans. Microwave and Techniques , vol. MTT-35, pp. 41-47, Jan. 1987. 78. G. W. Hugnes and R. M. White, "Microwave properties of nonlinear MIS and schottky-barrier microstrip," IEEE Trans. Electron Devices , vol. ED-22, pp. 945-955, Oct. 1975. 79. A. R. Djordjevic, T. K. Sarkar, and R. F. Harrington, "Timedomain response of multiconductor transmission lines," Proc . IEEE , vol. 75, pp. 743-764, June 1987. 80. W. L. Engl, R. Laur, and H. K. Dirks, " MEDUSA a simulator for modular circuits," IEEE Trans. CAD/ICAS . vol. CAD-1, pp. 85-93, April 1982. 81. R. Kamikawai , M. Nishi, K. Nakanishi, and A. Masaki, "Electrical parameter analysis from three-dimensional interconnection geometry," IEEE Trans. Components. Hybrids, and Manufac. Technol. . vol. CHMT-8, pp. 269-274, June 1985. 82. A. J. Gruodis and C. S. Chang, "Coupled lossy transmission line characterization and simulation," IBM J. Res. Develop. , vol. 25, pp. 25-41, Jan. 1981. 83. Y. Fukuoka, Q. Zhang, D. P. Neikirk, and T. Itoh, "Analysis of multilayer interconnection lines for a high-speed digital integrated circuit," IEEE Trans. Microwave Theory and Techniques . vol. MTT-33, pp. 527-532, June 1985.

PAGE 202

185 84. C. W. Ho, "Theory and computer-aided analysis of lossless transmission lines," IBM J. Res. Develop. . vol. 27, pp. 249-255, May 1983. 85. S. M. Perlow and A. Presser, "The interdigitated three-strip coupler," IEEE Trans. Microwave Theory and Techniques , vol. MTT32, pp. 1418-1422, Oct. 1984. 86. P. N. Venkatachalam, "Pulse propagation properties of multilayer ceremic multichip modules for VLSI Circuits," IEEE Trans . Components . Hybrids . and Manuf ac . Technol . . vol. CHMT-6, pp. 480484, Dec. 1984. 87. C. J. Stanghan and B. M. McDonald, "Electrical characterization of packages for high-speed integrated circuits," IEEE Trans. Components. Hybrids, and Manuf ac . Technol. . vol. CHMT-8, pp. 468473, Dec. 1985. 88. T. A. Lane, J. Belcourt, and R. Jensen, "Electrical characteristics of copper/polyimide thinfilm multilayer interconnects , " IEEE Trans. Components. Hybrids, and Manuf ac . Technol. . vol. CHMT-12, pp. 577-585, Dec. 1987. 89. R. Senthinathan, J. L. Prince, and M. R. Scheinfein, "Characteristics of coupled buried microstrip lines by modeling and simulation," IEEE Trans. Components. Hybrids, and Manuf ac . Technol . . vol. CHMT-12, p. 604, Dec. 1987. 90. 0. A. Palusinski, J. C. Liao , P. E. Teschan, J. L. Prince, and F. Quintero, "Electrical modeling of interconnects in multilayer packing structures," IEEE Trans. Components. Hybrids, and Manuf ac . Technol . . vol. CHMT-10, pp. 217-223, June 1987. 91. M. R. Scheinfein, J. C. Liao, A. Palusinski, J. L. Prince, "Electrical performance of high-speed interconnect systems," IEEE Trans. Components. Hybrids, and Manuf ac . Technol. . vol. CHMT-10, pp. 303-310, Sept. 1987. 92. V. K. Tripathi and R. J. Bucolo, "Analysis and modeling of multilevel parallel and crossing interconnect lines," IEEE Trans. Electron Devices , vol. ED-34, pp. 650-658, March 1987. 93. K. C. Gupta. R. Garg, and I. J. Bahl, Microstrip Lines and Slotlines . Dedham, MA: Artech House, 1979. 94. T. C. Edwards, Foundations for Microstrip Circuit Design . New York: John Wiley & Sons, 1981. 95. M. Kirschning and R. H. Jansen, "Accurate wide -range design equations for the frequency-dependent characteristic of parallel coupled microstrip lines," IEEE Trans. Microwave Theory and Techniques , vol. MTT-32, pp. 83-90, Jan. 1984.

PAGE 203

186 96. J. Chill and T. Arnaud, "Coupling effects In the time domain for an Interconnecting bus in high-speed GaAs logic circuits," IEEE Trans. Electron Devices , vol. ED-31, pp. 347-352, Mar. 1984. 97. S. Seki and H. Hasegawa, "Analysis of crosstalk in very highspeed LSI/VLSI 's using a coupled multiconductor MIS microstrip line model," IEEE Trans. Electron Devices , vol. ED-31, pp. 19481953, Dec. 1984. 98. D. H. Auston, "Picosecond optoelectric switching and gating in silicon," Applied Physics Lett. , vol. 25, pp. 101-103, Feb. 1975. 99. W. R. Eisenstadt, R. B. Hammond, and R. B. Dutton, "On-chip picosecond time-domain measurements for VLSI and interconnect testing using photoconductors , " IEEE Trans. Electron Devices , vol. ED-32, pp. 364-369, Feb. 1985. 100. R. J. Atwaters , "High speed transient measurement of coplanar transmission lines utilizing picosecond photoconductors fabricated on an SOS substrate," Master's thesis. University of Florida, Aug. 1988. 101. J. W. Slotboom and H. C. de Graaff, "Measurements of bandgap narrowing in Si bipolar transistors," Solid-State Electron. . vol. 19, pp. 857-862, 1976. 102. J. Dzlewior and W. Schmid, "Auger coefficients for highly doped and highly excited silicon," Applied Physics Lett. . vol. 31, pp. 346-348, Sept. 1977. 103. J. G.Fossuro, R. P. Mertens , D. S. Lee, and J . F. Nijs, "Carrier recombination and lifetime in highly doped silicon," Solid-State Electron. . vol. 26, pp. 569-576, 1983. 104. Zhiping Yu, Bruno Ricco, and Robert W. Dutton, "A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors," IEEE Trans. Electron Devices , vol. ED-31, pp. 773-784, June 1984. 105. Shuy-Young Yung, "The modeling and design optimization of polysilicon-emltter transistors, including experimental verification," Ph.D. dissertation. University of Florida, Dec. 1987. 106. S. P. Gaur, P. A. Habitz, Y.-J. Park, R. K. Cook, Y.-S. Huang, and L. F. Wagner, "Two-dimensional device simulation program: 2DP," IBM J. Res. Develop. . vol. 29, pp. 242-251, May 1985. 107. W. Fichtner, D. J. Rose, and R. E. Bank, "Semiconductor device simulation," IEEE Trans. Electorn Devices , vol. ED-30. pp. 10181030, Sept. 1983.

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BIOGRAPHICAL SKETCH Jiann-Shiun Yuan was born in Kaohsiung, Taiwan, Republic of China, on August 7, 1957. He received the B.S. degree from the National Taiwan College of Marine Science and Technology, Taiwan in 1980 and the M.S. degree in electrical engineering from the University of Florida in 1984. Since 1984 he has been working towards the Ph.D. degree at the University of Florida in the field of semiconductor device modeling and characterization. His area of interest includes bipolar and MOSFET transistor modeling, computer-aided device and circuit design, high speed device measurement, and interconnect modeling and characterization. 188

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I certify that I have read this study and that in my opinion it confirms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. William R. Eisenstadt, Chair Assistant Professor of Electrical Engineering I certify that I have read this study and that in my opinion it confirms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. ^fi^-'U^ Sheng S. Li Professor of Electrical Engineering I certify that I have read this study and that in my opinion it confirms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Arnost Neugroschel ^ Professor of Electrical Engineering I certify that I have read this study and that in my opinion it confirms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Gijs . 'Bosman Associate Professor of Electrical Engineering I certify that I have read this study and that in my opinion it confirms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a d^ssertapioj^ for the degree of Doctor of Philosophy. C. K. Hsieh Professor of Mechanical Engineering

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This dissertation was submitted to the Graduate Faculty of the College of Engineering and to the Graduate School and was accepted as partial fulfillment of the requirements for the degree of Doctor of Philosophy. December 1988 Dean, Graduate School

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