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Study of the optimum charge-transfer image sensor

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Study of the optimum charge-transfer image sensor
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Tseng, Hsin-Fu, 1940-
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vi, 168 leaves : ill. ; 28 cm.

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Capacitance ( jstor )
Charge transfer ( jstor )
Diodes ( jstor )
Drains ( jstor )
Electric potential ( jstor )
Sensors ( jstor )
Shift registers ( jstor )
Signals ( jstor )
Tetrodes ( jstor )
Transistors ( jstor )
Dissertations, Academic -- Electrical Engineering -- UF
Electrical Engineering thesis Ph. D
Optoelectronic devices ( lcsh )
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bibliography ( marcgt )
non-fiction ( marcgt )

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Thesis:
Thesis--University of Florida.
Bibliography:
Bibliography: leaves 164-167.
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Typescript.
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Vita.
Statement of Responsibility:
by Hsin-Fu Tseng.

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University of Florida
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Copyright Hsin-Fu Tseng. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
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STUDY OF THE OPTIMUM CHARGE-TRANSFER
IMAGE SENSOR








By

Hsin-Fu Tseng


A DISSERTATION PRESENTED TO THE GRADUATE COUNCIL OF
THE UNIVERSITY OF FLORIDA
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE
DEGREE OF DOCTOR OF PHILOSOPHY














UNIVERSITY OF FLORIDA


1979
























ACKNOWLEDGEMENTS


I would like to express my deepest gratitude to Professor S.S. Li for his guidance and encouragement throughout the research and preparation of this dissertation. Also, I give thanks to Professors E. R. Chenette, F. A. Lindholm, D. R. MacQuigg, J. K. Watson, and K. Y. Chen for their advice and support. In addition, I would like to acknowledge the many helpful discussions with Mr. G. P. Weckler, and Dr. R. W. Brodensen at Reticon Corporation.

Thanks are also due to Mr. Ed Webb for carefully proofreading the

manuscript, and Reticon Corporation for financial support and fabrication of the devices used in this study.
















TABLE OF CONTENTS

Page

ACKNO14LEDGEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . ii

ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

CHAPTER

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . 1

2 OPTIMIZATION OF A SOLID-STATE IMAGE SENSOR . . . . . . . . . 5

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . 5
2.2 The Architecture of A Solid-State Image Sensor. . . . . 5 2.3 Device Structure to Realize the Optimum Architecture. . 17

2.3.1 Device Structure . . . . . . . . . . . . . . . . 18
2,3.2 Device Operation . . . . . . . . . . . . . . . . 26

3 ANALYSIS OF THE BUCKET-BRIGADE SHIFT REGISTER . . . . . . . . 31

3.1 Introduction . . . . . . . . . . . . . . . . . . 31
3.2 Device Structure and Opera ion . . . . . . . . . . . . . 35

3.2.1 Device Structure . . . . . . . . . . . . . . . . 35
3.2.2 Device Operation . . . . . . . . . . . . . . . . 38
3.2.3 Input and Output Structures . . . . . . . . . . 0

3.3 Performance Limitations . . . . . . . . . . . . . . . . 43
3.4 Tetrode Structure Bucket-Brigade Device . . . . . . . . 46 3.5 Derivation of Transfer Inefficiency Model . . . . . . . 51

3.5.1 Intrinsic Transfer Rate . . . . . . . . . . . . . 52
3.5.2 Transfer Inefficiency Due to Subthreshold
Leakage of the IGFETS . . . . . . . . . . . . . . 61
3.5.3 Transfer Inefficiency Due to Barrier-Height
Modulation . . . . . . . . . . . . . . . . . . . 73

4 ANALYSIS OF THE OPERATING MECHANISMS AND NOISE LIMITATIONS
OF THE OPTIMUM IMAGE SENSOR . . . . . . . . . . . . . . . . . 84

4.1 Charge-Storage Operation of a Photodiode . . . . . . . . 84
4.2 Sensing Diode to BBD Analog Register Charge-Transfer
Mechanism . . . . . . . . . . . . . . . . . . . . . . . 88










Page

4.3 Anti.-Blooming Mechanism . . . . . . . . . . . . . . . . 96
I
4.4 Noise Analysis . . . . . . . . . . . . . . . . . . . . 101

4.4.1 Noise Sources Associated with the Sensing
Diodes . . . . . . . . . . . . . . . . . . . . . 101
4.4.2 Noise Sources Associated wi th the Common
Video Lines . . . . . . . . . . . . . . . . . . 103
4.4.3 Noise Sources Associated with the BBD Shift
Register . . . . . . . . . . . . . . . . . . . . 104

5 DEVICE FABRICATION AND MEASUREMENT METHODS . . . . . . . . . 108

5.1 Device Fabrication . . . . . . . . . . . . . . . . . . 108
5.2 Measurements . . . . . . . . . . . . . . . . . . . . . 109

5.2.1 Barrier-Height Modulation Measurement . . . . . 110
5.2.2 Bucket-Brigade Shift Register Transfer
Inefficiency Measurement . . . . . . . . . . . . 110
5.2.3 Optical-to-Electrical Transfer Characteristics
Measurement . . . . . . . . . . . . . . . . . . 115
5.2.4 Saturation Charge Measurement . . . . . . . . . 115

6 EXPERIMENTAL RESULTS AND DISCUSSION . . . . . . . . . . . . 119

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . 119
6.2 Experimental Results of the Bucket-Brigade Shift
Reo ister . . . . . . . . . . . . . . . . . . . . . . . 119
C7

6.2.1 Experimental Verification of the Barrier-Height
Modulation Model . . . . . . . . . . . . . . . . 120
6.2.2 Experimental Verification of the Intrinsic
Transfer Rate Model . . . . . . . . . . . . . . 129
6.2.3 Improvement of Transfer Efficiency by Using
Selective Ion Implantation . . . . . . . . . . . 131
6.2.4 A Proposed BBD Structure with Improved Performance . . . . . . . . . . . . . . . . . . . . . 139

6.3 Experimental Results of the Image Sensor Performance . 140

6.3.1 BBD Analog Shift Register . . . . . . . . . . . 140
6.3.2 Image Test . . . . . . . . . . . . . . . . . . . 144
6.3.3 Transfer Characteristics . . . . . . . . . . . . 149
6.3.4 Saturation Signal and Dark Current . . . . . . . 151 6.3.5 Blooming Characteristic . . . . . . . . . . . . 154
6.3.6 Noise Performance and Dynamic Range . . . . . . 157

7 CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . 162

REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

BIOGRAPHICAL SKETCH . . . . . . . . . . . . . . . . . . . . . . . 168










Abstract of Dissertation Presented to the Graduate Council
of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy



STUDY OF THE OPTIMUM CHARGE-TRANSFER IMAGE SENSOR


By


llsin-Fu Tseng

March 1979

Chairman: Sheng-San Li
Major Department: Electrical Engineering

This research deals with an investigation into the optimum structure for a solid-state image sensor. This optimum structure consists of diffused diodes for photosensing, and either a bucket-brigade or charge-coupled transfer register for signal readout. The photodiode sensors offer the advantages of full, smooth spectral response and high quantum efficiency, while the charge-transfer register provides a low noise self-scanned video output. A matrix array with two tetrode bucket-brigade readout registers is fabricated and studied. This array consists of 10,000 photodiodes arranged in 100 columns and 100 rows. Each row of diodes is selected in sequence by a digital scanning register, and the resulting signal charges are transferred in parallel to two 50 stage odd and even bucket-brigade registers by means o f video lines and transfer gates common to all diodes in a column. The outputs of the two 50 stage registers are then multiplexed to obtain a single 100 stage video signal.

Models describing the operating mechanisms of the bucket-brigade and

image sensor devices are developed. It is shown that for a tetrode bucketbrigade device the high frequency operation is limited by the intrinsic










transfer rate of the tetrode gate, while the transfer inefficiency at low frequencies is mainly determined by the barrier-height modulation of the transfer gate. To improve the performance of the bucket-brigade, the regions under the tetrode and transfer gates are implanted to increase the effective substrate concentration; this reduces the barrier-height modulation and significantly improves the bucket-brigade's performance. The merits and disadvantages of the implanted device are discussed, which leads to a proposed new bucket-brigade structure. It is shown that the charge-transfer efficiency between the sensing diode and analog shift register degrades sharply with decreasing light level due to the subthreshold leakage current of the transfer gates. By using a unique method to provide a background or fat-zero charge, this transfer inefficiency is eliminated, and the image sensor exhibits a linear photo-response with a dynamic range of more than 600 to 1 at operating frequencies up to

10 1ARZ.
















CHAPTER 1

INTRODUCTION



Electronic imaging devices perform the task of converting a pattern of incident radiation falling upon the surface of the sensor into an electrical signal which is an ordered, sequential reproduction of the radiation pattern. The basic architecture of an image sensor, therefore, can be reduced to two basic functions, namely, the detection of photogenerated carriers and the readout of information gained thereby. For some time the successful development of solid-state image sensors has been regarded as a highly desirable goal, since solid-state sensors are superior in performance and could be cheaper than electron beam scanned camera tubes due to their small size, low power consumption, high reliability, and long life. In addition, their expected ruggedness and immunity to shock, vibration, and electromagnetic field provide attractive features for such devices. However, until recently, the state of development of solid-state image sensors was still far from satisfactory.

The development of solid-state image sensors began in the early 60's and with the rapid advancement of semiconductor technology, several types of imaae sensors were developed. They are referred to as self-scanned photodiode arrays [1-3], charge injection image arrays [4-6], and chargecoupled image arrays [7-171. Each type of array uses a different architecture to perform the photo-detection and the signal readout functions. As a result, each type of device possesses certain advantages and drawbacks which limit its performance.










IRecently a new structure which combines the advantages of each of

these image sensors has been reported by Tseng and Weckler [18-20]. This new structure employs photodiodes for signal detection and a low noise charge-transfer analog shift register for readout. This combination together with a built-in anti-blooming structure results in an optimum image sensor. The optimum sensor possesses all the desired characteristics such as minimum fixed-pattern noise, high dynamic range, smooth and broad spectral response, high quantum efficiency, uniform sensitivity, immunity to overload blooming, and versatility of operation. It is important and highly desirable that such a solid-state image sensor be developed and studied.

In this dissertation, the operating mechanism and performance limitations of a matrix charge-transfer image sensor having optimal characteristics are investigated. This image sensor consists of 10,000 photodiodes arranged in 100 columns and 100 rows. Each row of diodes is selected in sequence by a scanning digital register, and the signal charges are transferred in parallel into two tetrode bucket-brigade analog registers [21-27] for readout. Since the analog shift register constitutes a very important part of the imaging device, a large segment of this research effort was devoted to the modeling and study of the BBD analog register.

In Chapter 2, the building blocks of the common image sensors are reviewed, and the new architecture which results in the optimal solidstate image sensor is discussed in detail. The organization and operation of the matrix array which realizes the optimal architecture is described.

In Chapter 3, the operation and performance limitations of the basic and improved tetrode bucket-brigade devices are analyzed, and models





-3-


describing the mechanisms which govern the transfer efficiency and operating speed of the BBD are developed. The barrier-height modulation model developed to explain the low frequency transfer inefficiency of the BBD is an improved version of Yau's [28] and Taylor's [29] shortchannel models. In this model, the effects of drain potential and the gate-electrode fringing field in the drain depletion region [301 are taken into account in deriving the threshold voltage of the MOS transistor. This model is very useful for MOS circuit simulation, and can be implemented easily into the simulation program.

Chapter 4 contains the analysis of the operating mechanisms and design formulations for the optimal matrix array. A unique "fill and spill" technique [31] used to eliminate the charge transfer inefficiency between the sensing diode and the BBD register is discussed in detail. The limitations of the anti-blooming structure for minimizing the signal degradation due to saturation are also presented.

In Chapter 5, device fabrication and measurement procedures are described. The fabrication process used was n-channel, double-layer silicon-gate technology. The substrate concentrations used in this study were 6 x 10 14 and 1.7 x 10 15 cm -3 .

Chapter 6 presents the experimental results. It was concluded that while high frequency operation of the BBD register is limited by its intrinsic transfer rate, the transfer inefficiency at low frequencies is mainly determined by the barrier-height modulation of the transfer gate. To obtain a BBD register with good transfer efficiency and reasonable speed, the substrate concentration must be much higher than 1.7 x 10 15
-3
cm . However, if a low resistivity substrate is used for fabricating the BBD register, the body effect [321 of the high substrate concentration











will make the peripheral circuits inoperable. To solve this dilemma, a selective ion implant technique [33] was employed in which only the regions under the BBD gates were implanted to minimize the barrier-height modulation. This technique resulted in a high performance BBD register. The limitations of the high performance BBD are discussed, which lead to a proposed new BBD structure. Finally, the experimental results of the optimal matrix array which incorporated the high performance BBD register are reported. The optical-to-electrical transfer characteristics with and without using the "f ill and spill" technique are compared, and the noise performanc e is presented.

Chapter 7 contains the conclusions of this work.
















CHAPTER 2

OPTIMIZATION OF A SOLID-STATE IMAGE SENSOR



2.1 Introduction


Evolution has produced several solid-state image sensors, each possessing different architectures. Most of these can be broken down into combinations of four basic building blocks. This chapter will present a review of these building blocks and discuss in detail a new architecture which results in the optimal solid-state image sensor.



2.2 The Architecture of A Solid-State Image Sensor


The solid-state image sensor takes advantage of the highly developed silicon integrated circuit technology. The mechanism of detection is based on the absorption by silicon of photons within an energy range of 1.1 eV to about 6 eV; this corresponds to a wavelength range of 1.1 pm to 0.2 pm as shown in Figure 2.1 by a typical spectral response curve. When a photon is absorbed, it generates an electron-hole pair. If we are to detect this electron-hole pair, the components must be separated. This is normally accomplished by the depletion region of a p-n junction or the depletion region induced by applying the appropriate voltage to an MOS capacitor. This is also referred to as a potential well. In either case, the electron and hole are separated and the charge equivalent to one electron will then appear on the depletion region capacitance.













1.0



0.8

U)
z
0
Oj 0.6w


ct
>
.1
w


0.2


I I I I I I I I I
200 300 400 500 600 700 800 900 1000 1100 WAVELENGTH (nm)


Figure 2.1 Typical spectral response of a diffused diode.











Let us briefly compare these two basic detection mechanisms. The internal quantum efficiencies can for all practical purposes be assumed to be the same for both mechanisms, i.e., the efficiency of collecting photo-generated electron-hole pairs. The main difference is in the external quantum efficiency of the two mechanisms. Figure 2.2 shows the basic structure of these two detectors. The external quantum efficiency of the diffused photodiode suffers minimum losses due to only two interfaces between materials of different refractive indices, i.e., Air-SiO 2 interface and SiO 2-Si interface. The thickness of the SiO 2is such that the modulation of the spectral response of the diffused photodiode is negligible. It is apparent from Figure 2.2 that for the field induced detector an additional two interfaces are present to introduce losses [34]. Furthermore, the transparent electrode is not really transparent since it is usually polysilicon. Because silicon is absorptive, some of the incident photons are absorbed in this layer. This is particularly true for the short wavelength or the blue end of the spectrum. The use of exotic metallic materials [35] has resulted in field plates that are more transparent over the spectral range of interest than is polysilicon; however, these materials are foreign to standard integrated circuit technology.

Furthermore, the thickness of these films is subject to normal

processing variations. It is, therefore, difficult to insure reproducibility of sensitivity, uniformity, or spectral response. It is apparent that the diffused photodiode is a far superior detector, possessing the following advantages:

(1) external quantum efficiency approximately three times that of the quasi-transparent electrode employing polysilicon;





0I


iJhv


DIFFUSED PHOTODETECTOR


Inverted Surface Si


FIELD INDUCED PHOTODETECTOR


Figure 2.2 Two basic photodetector structures.





-9-


(2) full spectral response extending from 0.2 pm to 1.1 pm; and (3) a relatively smooth spectral response not subject to process variations.

Having now detected internally the absorption of a photon, it is necessary that this information be made available at a terminal. Here lies another of the principal differences in the design of solid-state image sensors. Figure 2.3 shows schematically two approaches used to interrogate and read out the individual picture elements of an image sensor. Each approach uses a shift register to read out the information stored on each individual photosensitive element or pixel. In the first case a digital shift register is used to sequentially access a transfer switch which connects individual pixels in turn to a common terminal. This approach has the definite advantage that digital shift registers and multiplex switches have been highly developed, use standard MOS processes and are relatively easy to implement. The performance of this readout technique is dependent on both the total number of multiplex switches and on the uniformity of the multiplexing function, i.e., ideally each multiplex switch and its drive should be identical. Non-uniform multiplexing results in a fixed-pattern modulation which is.superimposed on the video information from the pixels. Differential signal processing techniques have recently been incorporated which have reduced the fixedpattern component to a negligible level. The fixed pattern has been reduced to the point where the total number of multiplex switches is now of practical significance. The random noise depends directly on the size of the output capacitance which in turn is a function of the number of multiplex switches connected to the output line. In the majority of applications, particularly those for which the solid-state image sensor























CLOCK CLOCK

IA AALOG SHIFT REGISTERK[*VIDEO START DIGITAL SHIFT REGISTER OUTPUT READOUT I I

START LK T K VIE
READOUT VIDEO
READOUT'YOYUYPUT





PIXELS H


Figure 2.3 Techniques f or interrogating and reading-out picture elements.





_11-


serves as an input to a machine, random noise does not appear to be a practical problem. The level of the random noise, however, does set a basic limit to the minimum detectable illumination level that can be detected.

The second approach, shown in Figure 2.3, also employs a transfer

switch (really an adjustable barrier) for each pixel; however, all pixels are sampled simultaneously, thus transferring all the information in parallel into an analog shift register. This information is then clocked to an output terminal at the end of the analog shift register. The analog shift register has been highly developed over the past few years. Charge-transfer devices, both bucket-brigade [331 and charge-coupled [36], can now be made with transfer efficiencies exceeding 0.9999 at megahertz clocking rates; therefore, the initial problems of shading and loss of resolution are no longer a serious problem.

Figure 2.4 shows four architectures that may be implemented using the building blocks described above. Let us begin by examining each structure. The first structure to be discussed uses photodiodes as the detectors and a digital shift register to sequentially interrogate these diodes and is depicted in the figure as Combination A. This structure operates in the charge-storage mode [11 and is commonly referred to as " self-scanned photodiode array [2,3]. To obtain line storage requires " single multiplex switch connected to each photodiode, thus making possible high density linear arrays which possess all the advantages of the photodiode detector. To obtain frame storage in a matrix or twodimensional array requires that each photodiode have two multiplex switches associated with it. As a result, the size is limited since the minimum center-to-center spacing is about 75 pm [37]. For linear












CLOCK

START -DIGITAL READOU GITAL











hvEJ


SHIFT










A


CLOCK

VIDEO
REGISTER ANALOG SHIFT REGISTER OUTPUT

VIDEO START
) ) OUTPUT READOUT



4 INDIVIDUAL
PIXELS



B
C hv _Poly-Silicor


Inverted Surface


DIFFUSED PHOTODETECTOR


FIELD INDUCED PHOTODETECTOR


Figure 2.4 Four basic architectures of a solid-state image sensor.


0





-13-


arrays, this architecture is perfectly adequate for realizing long, high density arrays. Linear arrays approaching 2000 pixels in length with pixels as close as 15 pm centers have been available for some time [381. This architecture, however, has reportedly two serious shortcomings. The one most often referred to is the output capacitance, which.increases directly with the number of pixels. Its effect is to increase directly the thermodynamic or random noise of the system, thus limiting the minimum number of photons/pixel that can be detected. The other is referred to as fixed-pattern noise, which originates from the non-uniformity of the shift register and multiplex switches. This noise is discernible primarily at low levels of illumination. However, it can be eliminated by using differential signal processing techniques and is, therefore, much less of a problem now as compared to earlier arrays using this architecture.

The second architecture to be discussed is commonly referred as a charge-coupled device which uses the field-induced photo-detector as the pixel and the analog shift register to shift the information from the pixel to the output terminal and is depicted by Combination B. Two typical matrix structures are shown in Figure 2.5. These structures permit very high density with pixel spacings of 20 to 30 pm not uncommon [171. Depending on the particular criteria employed, the performance of these structures has ranged from adequate to excellent. As a result of the very low output capacitance and the elimination of sequential sampling with multiplex switches, both the thermodynamic and the fixed-pattern noise in the dark are exceptionally low. This, however, is offset by the resulting non-uniformity that prevails under illumination. This nonuniformity is a result of the variations in film thicknesses that occur











7E

E EF EF


FRAME/FIELD TRANSFER


SIF

E E
\ \\\1


INTERLINE
TRANSFER


Figure 2.5 Readout organization of CCD matrix array.


S7E




E N


\ \


~ i\~\~i\~:~\~\~ ~i\\\\\\\~:~~


\\\\\


L7U--*-





-15-


in fabricating the field-induced photo-detector added as well as those non-uniformities that are always present in the bulk silicon. Since the reflectivity as well as the absorption depends on the relative thicknesses of several films,.a compromise must be made between spectral response, quantum efficiency, and the non-uniformity [34]. Normal process variations make reproduction of consistent parameters over a period of time somewhat more difficult than for the simpler diffused diode structure. This problem is further aggravated by both the complexity of the required process and its developmental nature, i.e., most CCD processes are not high volume production processes; therefore, they lack the stability of a standard production process.

The third structure to be discussed, shown as C in the figure, combines the field-induced photo-detector with the digital shift register in an effort to obtain higher density with an existing technology. This structure is employed in charge injection array as shown in Figure 2.6. As initially conceived, this structure exhibited excessive uncontrolled blooming, less sensitivity than the photodiode, spectral variations, excessive non-uniformity, fixed patterns in the dark resulting from digital sampling, and an extremely large output capacitance. Most of these difficulties are now under control; however, the technology is no longer standard requiring an exotic metal/silicon gate MOS process on an expitaxial substance [4-6,35]. Furthermore, a double sampling technique must be used to process out the fixed-pattern noise resulting from the sequential sampling of multiplex switches and the thermodynamic noise associated with resetting the output capacitance. As a result of employing this more complicated signal processing technique, the inherent forms of signal contamination are eliminated, and good low level performance is obtained.





-16-


PHOTO CURRENT


(a) CHARGE INTEGRATION


M READOUT ENABLE


(c) INJECTION READOUT


Cross-section of X-Y addressable sensing cell of a charge injection array showing location of stored charge under (a) Integration, (b) Readout enable, (c) Injection conditions.


Figure 2.6





-17-


The final structure to be assembled from the set of building blocks is shown in the figure as D. This structure uses photodiodes with all their inherent advantages, i.e., spectral purity, high-external quantum efficiency, combined with an analog shift register for readout. This combination possesses all the advantages of the photodiode detector with those of the analog shift register readout. In the following section we will describe the practical realization of array employing this architecture. For lack of a more descriptive acronym, let us refer to this architecture as the optimum solid-state image sensor.



2.3 Device Structure to Realize the Optimum Architecture


Solid-state image sensors can be divided into two groups: linear

image sensors and area image sensors. Linear sensors consist of a single row of photosensitive elements and thus can be used to monitor a one- . dimensional variable. In order to obtain a two-dimensional picture fro-m a line sensor, the other dimension has to be scanned mechanically. For high speed scanning of a two-dimensional picture such as standard broadcast television, an electronically scanned area array which contains rows and columns of photosensitive elements must be used. In the present study, only a 100 by 100 area array image sensor will be fabricated and investigated, since, in principle, the linear array is a simplified form of a matrix array. Any results obtained from this study then will also be applicable to the linear image sensor.





-18-


2.3.1 Device Structure

i
The 100 x 100 diode matrix array to be fabricated and studied consists of six functional elements as shown in the schematic diagram of Figure 2.7. These elements are:

(1) A 100 x 100 diode array matrix, schematically indicated by the columns and rows of individual photodiodes. The diodes in each column are connected one at a time through multiplex switches to a video line which is common to all the diodes in that column. Parallel connection of the multiplex switches simultaneously selects one diode from each column. The diodes are operated in the charge storage mode [1]. When a diode is selected by the multiplex switch, the potential of the diode will be reset to a value of (V Gm7VTM ), where V GM and V T111 represent the clock high voltage and threshold voltage of the multiplex switch, respectively. The signal charge removed from the selected diode will be transferred into an analog shift register through the common video line for readout. After the multiplex switch is turned off, the diode starts to integrate the photon-generated charge and its potential decays. The total integration time of each diode is the time between two consecutive readouts of the same diode. Figure 2.8 shows the potential diagram of a diode before and after selection by the multiplex switch. This unique structure makes possible a matrix array of photodiodes, each having only a single multiplex switch, which provides frame storage. Furthermore, the output capacitance is a single line and not the total number of pixels.

(2) A two-phase (2 0) dynamic shift register which controls the multiplex switches. It turns on each row of diodes in sequence and dumps the corresponding signal charge into the appropriate analog shift register through each common video line, thus loading a complete





-19-


Figure 2.7 Schematic diagram of the 100 x 100 photodiode
charge-transfer array.





-20-


SUBSTRATE POTENTIAL
































DIODE


MULTIPLEX SWITCH
k LOW


N)

HIGH


SIGNAL CHARGE TRANSFERRED INTO COMMON VIDEO LINE






VIDEO
LINE POTENTIAL


Figure 2.8 Potential diagram of a diode before and
after being selected.





-21-


line of information at one time. The dynamic shift register is driven by a two-phase clock denoted by 0 and 0 in Figure 2.7. It can be Yl Y2

self-loaded for sequencing or controlled by an external start pulse. These functions are performed by the "NOR" circuit. Tied to each output of the shift register (except for the 100th position) are inputs to the "NOR" circuit which control the loading of the shift register. When there is an output from any of the 99 output positions, the "NOR" circuit keeps the shift register from loading. Once the bit occupies the last position, the "NOR" circuit's output goes high and another bit is loaded into the shift re-ister. Note that Y is also connected to
0 START

the "NOR" gate. It can be used to inhibit the register from loading by pulling Y START to a high potential.

(3) Two tetrode gate bucket-brigade shift registers [26,27] with a gated charge-integrator output. As shown in Figure 2.7, there are two bucket-brigade analog shift registers located on either side of the device. These are the odd and even transport registers which accept the pixel information in parallel from their respective odd and even video diode columns, and shift the pixel information sequentially to the output amplifier. Each shift register is driven by a two-phase clock denoted by 0 X11 OX2 in Figure.2.7, and is also provided with a "fat zero" input port to improve the transfer efficiency as well as to check the performance of the register. The outputs from both shift registers are multiplexed off-chip to obtain one line of combined video information. The advantages of this multiplexing approach are manifold. It increases the density of the array, especially for the linear array in which the center-to-center distance of the sensing diodes is limited by the bit length of the analog shift register; it increases the pixel rate to two





-22-


times the transport clock frequency, and generates a full-wave sampleand-hold output; it also halves the number of charge transfers. This is very important in realizing long arrays when the total amount of charge loss and transfer noise limits the performance of the device.

As will be discussed in Chapter 3, the bucket-brigade device offers certain advantages over the charge-coupled device, such as greater compatibility with standard 140S technology and ease of interfacing with the peripheral circuitry. However, the bucket-brigade shift register has received much less attention than the charge-coupled device. In an attempt to remedy this, the BBD shift register instead of the CCD register is discussed in this study. It is hoped that a better understanding of the performance limitations of the BBD shift register can be obtained, and a design formulation can be established.

(4) A video line reset switch LR, a transfer switch LT and a buffer gate V buff* The reset switch LR provides a reference bias for all the video lines while all the sensor diodes are integrating signal charges. All the charges collected on stray capacitances along the video lines and all the excess signal charges leaked from the sensor diodes are drained into the sink voltage V DD through operation of the LR gate. Therefore, LR functions as an anti-blooming and anti-crosstalk gate. Prior to the moment when the dynamic register is to select another row of diodes, the LR gate is turned off and the transfer gate is turned on to the same reference level set by LR. This makes conditions ready for the signal charge from the next row to be transferred into the BBD registers. The LR and LT control clocks are complements of one another. Note also that, just prior to transfer, the BBD is empty of signal charges, it contains only fat-zero reference charges so that the new





-23-


transfer is unaffected by prior data.

Ideally when the signal charge is transferred from the common video line into the BBD shift register, the transfer gate LT should be turned on to the same reference level set by LR. However, due to normal process parameter variations at device fabrication, such as surface-state density, gate-oxide thickness, and substrate concentration, there will be a threshold voltage variation between transistors even though they are very close together on the same integrated-circuit chip. This threshold voltage variation will cause two problems in the operation of the device. Firstly, with different threshold voltages, the level set by the LR and LT switches will be different, even though they have the same gate voltage. If the reference potential level set by the LR switch is higher than that of LT, which corresponds to V TLR

Qf= [(VL- V L) - (VTL - V TL)1 CS (2.1)


=(VG AV T) C


VLR ad V LT are the gate potentials of the LR and LT gates respectively, and C sis the capacitance of the video line. To prevent this fixed














LR LOW L O


SIGNAL CHARGE DRAINED TO VDD






VDD SINK


SINA CHARG


TRANSFERRED INTO BBD BBD SHIFT REGISTER


BACK GROUND CHARGE


Figure 2.9


Loss of signal charge due to threshold voltage difference of LT and LR gates, V T > V T





-25-


charge Q f from saturating the analog shift register, it must be minimized by either minimizing AV G or C s .

The second problem caused by the threshold variation is the introduction of fixed-pattern noise due to a different AV T for each video line. As can be seen.from equation (2.2), with a different AV T for each video line, there will be a different Qf2 which results in a fixed-pattern noise on the output signal.

To minimize both the Q f and the fixed-pattern noise, a buffer gate V buff is introduced in front of the LR and LT switches. This buffer gate is biased at a DC potential below the LR and LT "high" potential. The function of this buffer gate is to isolate the video line capacitance C s from being affected by the AV G and AV T shown in equation (2.2), and to minimize Q f as well as the fixed-pattern noise. Its effect is very similar to that of the tetrode gate in the BBD shift register to be discussed in the following chapter. With the introduction of this buffer gate, equation (2.2) is revised to


Qf (AV G - AV T ) C (2.3)


where C. is the junction capacitance of the N + diffusion between the LR and LT switches. This C i is much smaller than C s and results in a great reduction of Q f and fixed-pattern noise.

(5) Interlacing switches denoted as LO and LE gates. These gates allow the device to operate in an interlacing mode when driven by a set of two-phase clocks running at the field rate. For the non-interlacing mode, these gates are tied to a fixed voltage, and the rows are accessed sequentially, with each odd line followed by an even line. For the





-26-


interlacing mode, odd rows are first all accessed to form an odd field, followed by even rows to form an even field.

(6) Frame reset FR. This switch provides an access to the multiplex switches of all the diodes in the matrix and allows the entire frame to be reset instantaneously. Since the diodes in each line are automatically reset when the line is accessed, the frame reset switch is normally not used and is held low. However, when a particular exposure is desired, this control may be used to clear the diodes to start a fresh integration cycle by taking FR terminal to V DD . Men this mode is used, a shutter or pulsed light input is required because the diodes are sequentially accessed and will thus differ in exposure time if light input is continued during the readout sequence.



2.3.2 Device Operation


Figure 2.10 shows the timing diagram for the array when operated in the non-interlace mode. It consists of three sets of complementary clocks for the dynamic shift register, the BBD analog register, and the line reset and transfer gates. The rising edge of the LT pulse should lead the rising (or falling) edge of the 0 Y clock by approximately 30 ns or more to insure that no useful signal charge is drained into V DD . The width of the IT pulse should be minimized to the time required for the Complete transfer of charge into the BBD register. During the transfer gate "ON" time, the charge collected at the stray capacitance along the video line and the excess signal charge leaked from other sensor diodes not selected also go into the BBD shift register, with the possibility of causing interline crosstalk and blooming. The theoretical considerations of the anti-blooming mechanism, speed limitations of the charge


















OY= I a50 OR MORE CLOCK PERIODS
c~X2~X TnJ LFLJLF _ FTLFLFnh--LFLFLn
X 2 0X 1
LT =LR _1] T d f c





Figure 2.10 Timing diagram for continuous-scan mode.





-28-


transfer into the BBD register, as well as ways to speed up the charge transfer process will be discussed in detail in Chapter 4.

During the time when the signal charge is being transferred into

the BBD register, the clock driving the register must stop with the clock at high potential on the buckets receiving charge from the video line. This will cause a deep potential well for the signal charge to flow into. As evident from Figures 2.7 and 2.10, the buckets receiving charge for both the odd and even transport registers are driven by 0 X2' and the charge transfer takes place simultaneously for both registers during the time 0 X2 is held high. However, on the readout, the odd BBD register produces the first pixel, since it reads out on the first low-going 0 X2 clock just after the transfer period. The second pixel is produced by the even BBD register; and since this pixel must transfer through an extra half-stage which is controlled by the 0 X1 clock, this even pixel is produced when 0 X1 goes low. This provides an easily multiplexed signal by means of-a simple external adder amplifier. The output charge integrators of the shift registers are connected as a source follower with an external load resistor tied between the video output terminal and ground. The reset switch of the charge integrator VR1 and VR2 are connected to the appropriate clocks driving the shift register to remove the signal charges after they have been sensed. Because there are fifty buckets of signal in each transport register, it requires at least 50 clocks to transfer all the signal charge into the output amplifier as shown in Figure 2.10.

The timing diagram for the interlace mode is shown in Figure 2.11. It generally is somewhat similar to that for the non-interlace mode; however, the dynamic shift register clock 0 Y must run at twice the
















I
ODD FIELD EVEN FIELD
oY1= -Y2 I
50 OR MORE CLOCK PERIODS

OX2 X1 LINE
TRANSFER, LT _- - "
LINE -L
RESET, LR =LT
50 OR MORE CLOCK PERIODS


LO~ TEE EVEN FIELD
LO = EIEL
ODD FIELD


Figure 2.11 Timing diagram for interlace mode.





-30




relative former rate, while the interlace gates LO, LE confine the row selection to alternate lines, odd or even as appropriate for the field. Thus, there is no change either in integration period or in overall frame rate; the picture is merely assembled in two interlaced fields instead of one sequential scan. Slight changes are required in the LT and LR clocks to accommodate the new pattern.

















CHAPTER 3

ANALYSIS OF THE BUCKET-BRIGADE SHIFT REGISTER



3.1 Introduction


The basic structure of the bucket-brigade device (BBD) is shown in Figure 3.1. This device in its integrated form was invented by Sangster [21,221 in 1968. There was much interest [23-25] in this device since it offered the first glimpse of a practical way of implementing an analog delay. However, the initial device had many shortcomings, with the major one being very poor transfer efficiency. Potential variations during the charge-transfer period introduced excessive channel-length and barrierheight modulation, and consequent transfer inefficiency. As a result, the device was limited to a small number of stages and low-frequency applications.

The first major advance made in improving the transfer efficiency was also made by Sangster and his co-workers [26,27]. It came from the introduction of an isolation or tetrode structure, with a DC biased gate, separating each clocked element from its neighbor, as in Figure

3.2. Devices fabricated employing this tetrode structure were found to perform reasonably well, but transfer efficiencies were still less than one could wish; furthermore, stability was erratic and the devices were sensitive to clock shapes, particularly the transition edges. Before these problems could be solved, charge-coupled devices (CCD) [391 were


-31-





-32-


INPUT


Ici


Figure 3.1 Basic bucket-brigade structure.





-33-


I


Figure 3.2 Improved bucket-brigade structure with tetrode
isolation.





-34-


introduced which showed promise of improved transfer efficiency, higher clocking frequencies and higher density; therefore, most of the work switched from bucket-brigade devices to charge-coupled devices. The charge-coupled device appeared to be a very simple structure, requiring only simple processing. However, despite the theoretical improvement, it produced devices with not much better performance than the bucketbrigade. It took five years and a tremendous amount of effort to develop the understanding and technology to the point which allowed the advantages of CCD to be truly realized.

With the development of CCD and modern MOS technology, such as

multiple-layer silicon gates to increase the density, self-aligned structures to reduce the parasitic capacitance, and threshold voltage control by selective ion implantation to minimize channel-length and barrier modulation, it is now possible without any difficulty to fabricate a bucket-brigade device with transfer inefficiency less than 10-4 and operating frequency higher than 5 MHz [19,331. The bucket-brigade device possesses certain advantages over the charge-coupled device, which makes it very attractive in some signal processing and image sensing applications. The most important advantage of the bucket7brigade device is the simplicity [33] and flexibility [401 of tapping the signal along the shift register. This is very desirable in correlator and transversal filter applications, as well as in interfacing with peripheral circuitry. Another advantage of the bucket-brigade device is its compatibility with existing MOS processes; as a result, a wealth of circuitry used in making digital memories and microprocessors can be integrated on the same chip.

In this chapter, the operation of the bucket-brigade device will be presented, and its performance limitations will be discussed. Analytical





-35-


equations will be formulated to analyze the transfer efficiency quantitatively, which will allow one to see the effects of each device parameter on its performance.



3.2 Device Structure and Operation


3.2.1 Device Structure


Figure 3.3a shows the integrated circuit version of an N-channel

IGFET bucket-brigade shift register. It can be fabricated using a standard two-layer polysilicon gate process. The substrate is p-type material and the transfer channel is confined by channel-stop ion implantation an d field oxide. After the gate oxide is grown, the first poly layer is deposited and defined to form the FET switch. The channel region under the FET gate can be selectively implanted before the gate deposition to increase the effective substrate concentration for minimization of, channel-length and barrier-height modulation. The oxide between the switches is then etched away. An N island is then formed between the switches either by a light diffusion or by ion implantation. A second oxidation step regrows the gate oxide on top of the N island as well as the insulation oxide on the first poly. A second layer of poly is then deposited and defined on top of the N island to form the capacitor. Figure 3.3b shows the equivalent circuit. C represents the gate capacitance between the N island and the second poly. C i represents the junction capacitance of the N island to the p-substrate.




























Figure 3.3 (a) Integrated-circuit version of an N-channel IGFET
bucket-brigade shift register.

(b) Equivalent circuit and two output sensing schemes.










02 c1


2nd Poly


SiO2 INPUT S

N+ /
N,- 1st Poly
P-SUBSTRATE

(3a)


S(2 01 #2 VOG r VDD


C C C C
INPUT VI C 1 C. VDD B
NODE I UTPURT

OUTPUT
A


(3b)





-38-


3.2.2 Device Operation


The bucket-brigade device can be operated by either a two-phase complementary, or non-overlapping clock. For simplicity, a two-phase complementary clock changing from 0 V to V G will be used to describe the charge transfer from stage to stage. To begin, it is assumed that several cycles of the clock voltage have been applied. Referring to Figure 3.4, at t = t 1 when the clock transition has just finished, the 0 1 switch will be turned off while the 0 2 switch will be turned on. Node B will be bootstrapped by the 0 2 clock to a most positive reference-potential of V and become the drain of the 0 2 switch. Node A will be lowered to a potential of V s by the capacitive coupling of the 0 1 clock. The magnitude of V s will depend upon the amount of the signal cha rge. Node A now becomes the source of the 0 2 switch and the signal electrons will flow through the 0 2 channel into the drain node. As a result, the source potential rises and the drain potential falls. Electron flow continues until the source potential rises to (V G - V T ) where V G is the most positive voltage of the 0 2 clock and V T is the threshold voltage of the IGFET devices. At this point, the potential of the source is no longer negative enough to inject electrons into the surface inversion layer, and charge transfer ceases. The drain will maintain a potential of [V c - QS /(C + C where Q s is the signal charge. This is depicted in Figure 3.4 as t t
2'
At t = t 32 the potentials of the clock lines are now reversed, and the sources and drains reverse their roles. The new potentials differ from the old ones by (V X C The factor C represents the
G C + C. C + C,
J J
voltage division of the clock voltage by the two series capacitances. Therefore, the reference voltage V C can be expressed as






















Figure 3.4 Operation of BBD shift register:

(a) Equivalent circuit of one-andone-half-stage shift register.

(b) Clocks to drive the shift register.

(c) Potential of each node at different
time cycles.




-40-


1 A2 03




NODE A 1Cj NODE B Cj NODE C 1Cj

(4a)



I I I
I/~i K


I I
t1 t2


t3 t4


(4 b)





t tj t t2 t t3 t t4


QS
C+ )=(Vcj


Qs
c


OS (VC VC


(4 c)





-42-


VC = VG VT + VG X C +C.(31
J

= 2V I- V,.T (if C >> C.i) (3.2)


The potential V sat the source when the clock transition has just finished (t = t 1 or t 3 can be approximated by


V V Qs C (3.3)


~VG VT-QS(if C >>j (3.4)


The charge that was previously transferred into a drain now finds itself in another source, and so it again transfers one more stage toward the output. If the input source island potential is held significantly positie(hgertan" - V T), there will be no new charge injected at the


input, and any internal charge is swept toward the output. When the internal charge has all been removed, the N island potentials oscillate between (VG - VT) (source potential) and (2VG - VT) (drain potential).

In the above analysis, the overlap capacitance of the IGFET gate to the source island is assumed negligible. The formation of the N island by light diffusion or ion implantation is intended to minimize'this parasitic capacitance.

The largest quantity of charge that can be transferred in the channel is referred to as the charge handling capacity of the shift register. The charge handling capacity can be obtained from equation (3.4) by letting VS = 0 which leads to


Q s(Max) =C (V G - V T) (3.5)


A larger charge would make V negative and forward bias the N island

and p-substrate junction and inject the signal charge into the substrate.





-43-


3.2.3 Input and Output Structures


As shown in Figure 3.3b, the input structure consists of an source island which is the analog signal input terminal, a FET sampling switch which is driven by one phase of the shift register clocks, and an input capacitor C i' When the 0 2 switches are off and the 0 1 swit ches are on, node I will be charged to the input potential V . When the voltages on the 0 1 and 0 2 switches are reversed, the charge at the input capacitance will be transferred into the shift register, and node I will be discharged to (V G - V T ) by the 0 2 switch. The charge injected into the shift register is therefore


Qs = (V G - V T - V i ) C i (3.6)


The signal charge in the shift register channel can be detected by attaching the gate of a source follower to the channel, as depicted by output A in Figure 3.3b, or by using a gated charge integrator [361 at the end of the shift register as depicted by output B in Figure 3.3b. The disadvantage of the output A structure is that any noise on the driving clock will appear on the output signal. However, this means of detection is non-destructive which is an advantage over the charge integrator.



3.3 Performance Limitations


The most important aspect of a charge transfer device is its ability to maintain the integrity of the charge packets as they are transferred along the device. In the preceding section, it was assumed that the charge transfer at each stage is perfect. However, in actual operation, the transfer of charge from one stage to the next is neither instantaneous





-44-


nor complete. This puts some limitations on the speed of operation of the bucket-brigade devices and the total number of transfers that can be executed without objectional signal degradation. Incomplete transfer means that in each transfer a small amount of signal charge is left behind. This effect is cumulative and after many transfers the charge packets become significantly smeared together. The parameter used to describe the performance of the bucket-brigade device is called transfer inefficiency c. This is defined as the fraction of signal charge left behind after each transfer. This parameter multiplied by the number of transfers in a device is the transfer inefficiency product N 9 C, which determines the overall transfer performance of the whole device.

The mechanisms that introduce the transfer inefficiency can be classified according to the operating frequency of the bucket-brigade device. At high frequencies, it is the intrinsic transfer rate of the FET switch that limits the transfer efficiency. If not enough time is allowed for the charge to transfer through the switch before the switch is turned off, some of the signal charge will betrapped at the previous stage. As will be discussed later, the transfer inefficiency is proportional to the square of the clock frequency when the device is operated in this frequency range. At low frequencies, there is enough time for the charge to transfer through the FET switch, and therefore, the source potential will be discharged to (V G - V T ) as discussed in the previous section. However, the discharge current is not completely cut off due to thermal diffusion of the charge carriers. There is still some leakage current passing through the FET switch, which is referred to as the subthreshold leakage current, and the FET device is referred to as being operated in the subthreshold or weak inversion region [41-43]. This





-45-


subthreshold leakage current will be affected by the channel-length modulation [30,44] of the FET switch due to the different drain potential accompanying the various amounts of signal charge. Moreover, the threshold voltage of the FET switch is a function of the drain voltage due to the ion-sharing effect at the drain junction [28,29,45]. This effect is usually referred to as barrier-height modulation. As a result of these channel-length and barrier-height modulations, there is a frequencyindependent component of transfer inefficiency which dominates at low frequency.

While the intrinsic transfer rate and the channel-length and barrierheight modulate ions contribute to the transfer inefficiency and provide the major limitations to shift register performance, there are other performance limiting effects which should be mentioned. Of these, perhaps the most important one is that of interface state s. With present day technology, interface-state densities are so small that they are not normally considered to affect significantly IGFET operation. However, in the case of the bucket-brigade shift register, we are talking about transfer inefficiency in the order of 10-4 ; therefore even A small density of interface states can be important.

Only the interface states in the channel region of the IGFET can affect bucket-brigade operation. Their effects are two-fold: one is contributing generation current, and the other is trapping carriers during transfer and emitting them at some later time. Interface-state generation current, in combination with bulk generation current associated with the N island, will add to the signal charge in the storage capacitance. Given enough time, these generation currents will add enough charge to overdrive the register. As a consequence, a low frequency or minimum refresh time limitation will be introduced by the leakage current.





-46-


The trapping of carriers by interface states in the IGFET channel

and subsequent emission at a later time will result in charge left behind, and will effectively introduce another contribution to the transfer inefficiency. This transfer inefficiency can be minimized by using a certain amount of circulating charge, or "fat zero" in the device. The effect of the fat zero is to keep the interface states under the gates filled so that these states will not trap signal charge. As a result, each charge packet will receive about the same number of electrons from the preceding packets as it loses to the trailing packets. As will be discussed later, this circulating charge will also speed up the intrinsic transfer rate considerably, and improve the high-frequency performance of the device.

Another limitation to bucket-brigade operation that needs to be mentioned is the dynamic drain conductance effect. It is well known that drain potential modifies the current flow and gives rise to a non zero output conductance in the saturation region of the IGFET characteristic [30,44]. This effect is also caused by channel-length modulation as mentioned before. This dynamic drain conductance effect will introduce another component of transfer inefficiency in the high frequency operation range of the bucket-brigade device. However, this transfer inefficiency component can be reduced to a negligible level by using the tetrode gate structure.



3.4 Tetrode Structure Bucket-Brigade Device


The most-important improvement in the development of the bucketbrigade device, which makes the actual application of this device possible, is the introduction of the tetrode gate structure [26,27].





-47-


The tetrode structure improves the performance of the device by reducing the effects of channel-length and barrier-height modulation and meanwhile does not increase the complexity of the fabrication process. There are sone other device structures which can improve the performance, such as stepped electrode [46] and junction FET approaches [47]. However, these approaches require special fabrication processes which are not compatible with standard 1405 processes. As a consequence, most of the modern bucketbrigade devices use the tetrode structure.

Figure 3.5a shows the actual device structure, and Figure 3.5e shows the equivalent circuit. C represents the junction capacitance of the N island between the FET switch and tetrode gate. The function of the tetrode gate is to isolate the storage capacitance C from being affected by any channel-length and barrier-height modulations on the transfer gates. Therefore, for optimum operation, the tetrode gate should be biased near the higher clock driver voltage V G' In Figure 3.5b, the bias level of the tetrode gate is shown at its optimum level which is slightly below the phase driver voltage. The solid lines indicate the surface potential without any introduced signal charge for the condition of 0 2 high and 0 1 low. The shaded region is the bias charge always present in the N regions. The double crosshatching indicates the introduction of a half well of signal charge and the resultant barrier modulation. The arrow points out the loss of charge from the signal packet due to the barrier modulation. Since the capacitance of C yis very small, this loss is small. In Figure 3.5c, the tetrode gate is shown at a higher voltage than that applied to the phase drivers. As seen by the double crosshatching which extends across the tetrode gate, the loss due to the barrier modulation is much larger since the capacitance which is affected


























Figure 3. 5 Tetrode bucket-brigade device:

(a) Actual device structure in integrated-circuit
form.

(b) Tetrode gate correctly biased. The charge
loss due to barrier-height modulation is
minimized.

(c) Tetrode gate biased too high, no effect in
suppressing the barrier-height modulation.

(d) Tetrode gate biased too low, reducing the
speed and charge handling capacity.

(e) Equivalent circuit.




-49-


VBB 01


VBB 2


VBB


(5a)


(5b)


(5c)






-50-


LOWER gm RESULTS IN LOWER SPEED


(5d)


(5e)





-51-


by the modulation is much larger. The tetrode gate has no effect in suppressing the barrier modulation with this bias level. In Figure 3.5d, the tetrode gate is much lower than the phase driver voltage. This results in low signal-handling capacity and reduced operating speed.

Whlen the tetrode gate bias V BB is lower than the clock voltage V G9 the charge-handling capacity becomes


QS (Max) = C(V BB - V T) (3.7)


with V BB too low, the charge-handling capacity is greatly reduced. Since the capacitance C yis very small, the node voltage V will quickly discharge to a threshold below the gate voltage of 0 2. The limiting process for speed of the transfer is the discharge of the large storage capaci-tance C through the tetrode transistor T .t Lowering of V BBbias will effectively reduce the transconductance of the tetrode transistor and consequently decrease the operating speed. It is also apparent that the tetrode transistor will not suffer any barrier-height and channel-length modulation, since the potential of V will never be much different from a threshold below the 0 2 voltage when 0 2 clock is high. Therefore, the high-frequency component of transfer inefficiency due to dynamic drain conductance is negligible when the tetrode structure is used.



3.5 Derivation of Transfer Inefficiency Model


In this section, the three mechanisms, namely intrinsic transfer rate, channel-length modulation, and barrier-height modulation; which limit the performance of the bucket-brigade device, will be discussed in detail. Analytical equations will be formulated to allow one to






-52-


examine the effects of each device parameter on its performance, and, therefore, an optimum device can be designed for each specific application. In the following derivation, emphasis will be on the physical process involved as well as the simplification of the model, and, therefore, any model requiring two-dimensional numerical analysis will be avoided.



3.5.1 Intrinsic Transfer Rate


The intrinsic transfer rate of the basic bucket-brigade device will be first derived, and the result will be then extended to the tetrode gate structure. In Figure 3.6, a single IGFET is shown, which will serve as the basis for the modeling of charge transfer efficiency in the bucketbrigade device [23-251.

This FET is merely one-half of one stage of a BBD shift register. The junction capacitance C i between the N island and the p-substrate has been neglected. This makes the storage capacitance C linear which is not completely true, but is a good enough approximation for most of the practical devices.

In Section 3.2.2, it was pointed out that during charge transfer,

the source potential V s rises to (V G - V T ) as the excess electronic charge in the source transfer to the drain. At the same time, the rate of charge transfer must go to near zero. However, this charge transfer process requires a certain amount of time. If the bucket-brigade is to Operate at a clock frequency of f c , then the maximum time T allocated for each charge transfer is


T = 1 (3.8)
2f





-53-


Vso










Figure 3.6


I I 1 OVD'
C "







FET model for charge transfer efficiency behavior of a bucket-brigade device.






-54-


If Tr is not long enough to allow the charge transfer process to Complete, there will be always a finite quantity of charge left behind in the source due to this intrinsic transfer rate limitation.

As mentioned in Section 3.2.2, when the gate voltage is V Wthe drain voltage VD will be equal to (2VG - VT) when there is no signal charge. The drain voltage will decrease as the signal charge is transferred into the drain node. The minimum drain voltage occurs when there is a saturation charge in the channel. This drain voltage equals


V (Min) = 2V - V -Q (Mx
D G T C


= 2V - VT - (V,- V )(3.9) G T T


= VG


From equation (3.9), it is clear that the IGFET is always operated in the saturation region.

To derive the excess charge Q remaining in the source after time T, we use the usual saturated current-voltage relation for the IGFET:


I = . (VG V - VT) 2(3.10) with


L o (3.11)


where 11 n =electronic mobility in the inversion layer

C ox= channel gate-oxide capacitance per cm2

W = channel width

L = channel length





-55-


During the time the gate voltage is VG, the excess charge in the source is defined as


Q(t) = C[V S(t) - (VG - VT)] (3.12)


The source-to-drain current is

I= dQ(t) (3.13)
dt

combining equations (3.10), (3.12), and (3.13) gives

dQ(t) _ [Q(t) 2 (3.14)
dt 2 C c1

integrating (3.14) leads to


Q(t) = Qo (+ 22) (3.15)


where Q is the initial charge in the source. Combining (3.15) with (3.8) gives
-1

Q(T) = Q 1+ 2 (3.16)
4f C

The transfer inefficiency c is defined by

c(r) _ dQ(r) (3.17)
dQo

Differentiating equation (3.16) leads to NO -2

= (1+ 4fC (3.18)
c
It is convenient to perform a Taylor expansion in f of (3.18),
c

16C4f 2
= c (3.19)
Qo2 2





-56-


From (3.19) it is now obvious that the transfer inefficiency due to the intrinsic transfer rate is not only proportional to the square of the clock frequency, but also is inversely proportional to the square of the signal charge Q0. As the signal charge decreases, the transfer inefficiency increases sharply. A circulating charge Q C or "fat zero" is therefore needed not only to reduce the interface-state trapping, but also to improve the transfer inefficiency due to this transfer rate limitation.

The physical meaning of the speeding up of the apparent transfer rate by the circulating charge can be understood by examining equation (3.16), which has been plotted in Figure 3.7 for the following representative values:


= 3 x 10-5 AN 2


Q0 = 0.8 and 2.4 picocoulorib (PC) (3.20)


C = 0.44 pF


Figure 3.7 shows that for a clock frequency of 0.5 MHz approximately

0.012 PC or 0.5% of charge remains in the source for Q0 = 2.4 PC. This

0.5% transfer inefficiency is intolerable for any practical bucket-brigade device. However, the charge remaining in the source for Q. = 0.8 PC is very near to the value for the large initial charge. If this 0.8 PC is the circulating charge Qc and any change beyond this amount represents the signal information, then the actual signal charge trapped at each transfer will be the difference between the charges left behind for both of the initial charges of 0.8 and 2.4 PC. Hence, the apparent transfer efficiency is greatly improved. An accurate calculation of (3.16) using





-57-


0.1









0.01









0.1 1.0 10 100
fc (MHz)



Figure 3.7 Charge left behind as a function of clock frequency for two different initial charges, Q 0 , as described by equation (3.16).





-58-


the condition of (3.20) for fc 0.5 2MHz gives the signal charge left

behind of 0.0001 pc, which corresponds to 0.006% of the signal charge which is now (2.4 -0.8) =1.6 pc.

Equation (3.19) now can be modified to accommodate the introduction of the circulating charge and actual transfer efficiency measurement scheme which will be discussed in a later chapter. Equation (3.16) can be expanded in a binominal series valid for most cases of practical interest to get

4f C 2 16f 2C 42
Q(T)- for Q >> 4f C (3.21)
2 oo c

With a circulating charge of Q9 and a charge packet of 9 , the actual signal charge left behind will be


AQ = 1fc 2 )(3.22)


The average transfer inefficiency is then IAQ 0 16f C2 C4
() - c 2 Qoc (3.23)


Comparing (3.23) with (3.19), it can be seen that (3.19) is the small signal limit [24] of (3.23), which represents [AQ o/(Q - Q)] (9o- d9 .

From (3.23), it is also clear that the transfer inefficiency can be minimized when both Q 0and Q care made as large as possible and that through the clock frequency dependence of C(T) the intrinsic transfer rate will provide an upper limitation to the operation of the bucket-brigade device.

To extend the result of the transfer inefficiency derived above for the tetrode gate bucket-brigade structure, we use the model shown in Figure 3.8, which represents one half stage of the tetrode BBD. As mentioned in Section 3.4, the junction capacitance C yis much smaller than the





-59-


VBB
0



To


-C - - Cy
_ I


Figure 3.8


FET model for charge transfer efficiency behavior of a tetrode bucket-brigade device.


.VG





-60-


storage capacitance C, the limiting process for the speed of charge transfer is the discharge of the'large storage capacitance C through the tetrode transistor T .t This is because any small amount of charge accumulated in node y will lower V considerably and cause a sharp increase of the current passing through the switch transistor T to discharge the
0 rs

accumulated charge. Therefore, equation (3.23) has to be modified for the tetrode BBD with the parameter of the tetrode transistor T rtreplacing that of the switch transistor T r

In the derivation of equation (3.23), we assume that the switch

transistor T rsis always operated in the saturation region, which is always true as discussed previously. However, this is not exactly the case for the tetrode T rtin the tetrode BBD. During and right after the clock transition, the voltage at node y will be charged to a potential V y< (V BB- V T), and then quickly discharged to near (V0G - V T). Therefore, during the very early stage of the charge transfer process, the tetrode transistor T rtis operated in the linear region instead of the saturation region. However, a rigorous computer simulation using the ASPEG transient program shows that with a capacitor ratio of C/C y=20-30, and the same parameter for both the switch transistor T rsand the tetrode transistor T t, the time that the tetrode transistor operated in the linear region during the early stage of charge transfer process is around 2-3% of the total charge transfer time. The total charge transfer time here is defined as the time required for the transfer inefficiency due to the charge transfer rate limitation to drop to the low frequency limitation value due to channel-length and barrier-height modulation. Therefore, the error introduced by assuming that the tetrode transistor T rtis always operated in the saturation region is negligible.





-61-


3.5.2 Transfer Inefficiency Due to Subthreshold Leakage of the IGFETS


As discussed previously, at the end of a charge transfer the source will rise to a potential of nearly (V G - V T). However, due to thermal diffusion of the charge carriers from the source region into the drain region, the channel current of the IGFET does not suddenly drop to zero. Rather, it diminishes exponentially with decreasing gate-to-source voltage. The effect of this subthreshold leakage current on the transfer inefficiency of the BBD will be considered in this section.

Figure 3.9a shows the FET model to be used in the subthreshold leakage current analysis. C represents the capacitance at the source node. In the basic BBD structure, this is the storage capacitance; however,in the tetrode BBD, this is the junction capacitance of the N+island between the tetrode and switch gates which is depicted as C yin Figure 3.8. C D represents the capacitance at the drain node which is the storage capacitance for both the basic and tetrode structures. It is assumed that enough time has elapsed to allow the charge at the source node to transfer into the drain node and the source potential reaches (V G - V T) as shown in Figure 3.9b. Once this condition is reached, current enters the channel barrier region only by diffusion.

The objective of this analysis will be to find the amount of charge trapped on the left of the barrier at the end of the charge transfer cycle. The amount of this charge Q 1 will be found as a function of the charge transferred, Q0. The charge transfer inefficiency due to this subthreshold leakage current c D is then dQ 1/dQ 0as before.

To find this relationship, consider Figure 3.9b. Assuming the carrier concentration at the left edge of the barrier is n 0, then the diffusion current across the barrier can be expressed [41] as






















Figure 3.9 (a)


FET model for derivation of transfer inefficiency due to subthreshold leakage current.


(b) Surface potential of an ideal FET with
no subthreshold leakage current. Also
shown are the trapped and transferred
charges.

(c) Actual surface potential and charge
transfer during the part of the cycle
devoted to subthreshold leakage current.





-63-


VG


Trs -CD

VSo 1 T .~ OVD

Cs


(a)


CARRIER CONCENTRATION
no


TRAPPED
CHARGE -a










2U-'


TRAPPED /t CHARGE__.,


(VG -VT)


-H--


TRANSFERRED
CHARGE .














TRANSFERRED
CHARGE





-64-


qDn�LBW[
Ist o L(VD) 1 - exp (-Vq/kT) (3.24)


where
=Ks�okT

LB S 0 (3.25)
2NAq

is the extrinsic Debye length


and q = electron charge

D = electron diffusion constant

NA = substrate concentration

k = Boltzmann's constant

T = temperature in degrees Kelvin

VDS = drain-to-source potential

K = dielectric constant of silicon
s

C = permitivity of free space
0

L(V ) = effective channel-length as a function of the drain voltage due to channel-length modulation.



The equilibrium minority-carrier concentration n at the edge of

the source is a function of the surface potential at the source, and can be expressed [411 as

no =exp[(b - 1)UF] n. (3.26)

[2(Usx + bUF - 1)] 12 where

U = source-to-substrate voltage normalized by kT/q NA
UF = nn the bulk Fermi potential normalized by kT/q
1
US
b = ,--, the band-bending parameter (b = 2 at strong
UF inversion, b = 1 at weak inversion)





-65-


U9 = surface band-bending normalized by kT/q

n. = intrinsic carrier concentration of silicon.


If VDS >> kT/q which is the case in BBD operation, the term in the brackets of equation (3.24) equals 1, and (3.24) reduces to

qDno L BW
st - L(VD) (3.27)


As the current diffuses over the barrier into the drain, the potential energy level at the source node starts to drop below the (VG - VT) level as shown in Figure 3.9c. As a consequence, the carrier concentration at the source edge also drops, as does also the diffusion current. From equation (3.26), it can be seen that carrier concentration at the source edge will decrease exponentially with reducing surface potential, therefore


n (t) = 0eV(t)q/kT (3.28)


and

qDnoLBW -V(t)q/kT (3.29)
st L (VD)


The value of V gradually increases as current flows over the barrier according to

dV(t) _ I st(t) (3.30)
dt C
s
Eliminating I st (t) from (3.29) and (3.30), we obtain an equation which can be solved for V(t).

dV(t) qDnoLBW -V(t)q/kT
-e (3.31)
dt L(V D)C V





-66-


Solving equation (3.31) with the initial condition V = 0 at t = 0, we obtain


V(t) = T Zn 1 + q2Dn�okTL(V )Cs (3.32)
q kLVD )Cs

At the end of the charge transfer cycle, the charge trapped at the source node is
kC[

Q = -CsV(T) = - q sn 1 + kTL(D)Cs] (3.33)

kTC q2DnoLV 1

_ s n k 0L(V) (3.34)
q kTL (VD)C Cs


where T is defined by equation (3.8). The approximation of (3.34) from (3.33) is always true when the BBD is operated in the low frequency range. The minus sign in front of equation (3.33) indicates that in reality the charge is depleted instead of trapped.

The transfer inefficiency is then obtained by taking the derivative of Q with respect to the charge Q transferred,

dQ1 dQ1 dL(VD)
=DdQ dL(V) dQ (3.35)
0 DD


k 1 D(3.36)
q L(V) dQ

The transfer inefficiency in (3.36) depends only on how the channel length is modulated by the charge Q transferred into the drain node. The charge Qo is related to the drain voltage VD by Qo
V = 2V - V (3.37)
D G T CGD





-67-


This gives
kT C dL(VD)
ks 1I
SD q CD L(V ) dV D338)


Thelast multiplier term in (3.38) represents the channel-length modulation for different drain voltages.

As mentioned previously in this section, a circulating charge Qc is always present in the channel, and the actual signal charge is (Q - Qc)" The actual signal charge trapped at the source can be calculated from (3.34) which leads to

C kT L(VD
AQn (3.39)
sig q L(D


L(V Do) and L(V Dc) represent the effective channel lengths when a charge packet of Q and Q are respectively present at the drain node. The transfer inefficiency then can be expressed by

AQ.i C skT knL(V ) 3.0
D Qo- Qc q(Qo- Qc) n L(VDc



To complete the calculation of transfer inefficiency, the multiplier terms in (3.38) and (3.40) representing the channel-length modulation have to be evaluated. The channel-length modulation is generally attributed to the spreading of the depletion region near the drain which results in a reduction of the channel length. Ihantola [48], Reddi and Sah [44] calculated the extent of this spreading by describing the electric field distribution using step p-n junction theory. However, it was pointed out by Frohman-Bentchkowsky and Grove [30] that owing to the presence of the gate electrode, the electric field in the drain depletion region near the Si-SiO2 interface is greatly increased. A simple physical model was presented by them which takes into account this increase in the





-68-


electric field. Good agreement between the model and output conductance measurements throughout a very wide range of device parameters was observed; as a result, this model is widely adopted in many modern computer circuit simulation programs.

Although this model is developed for the IGFET under strong inversion to account for the dynamic drain conductance, it can be extended into the weak inversion region with a slight modification of the definition of the drain saturation voltage V Dst* According to conventional theory, an IGFET device operates in the saturation region when the drain voltage is increased to a value such that the inversion condition at the end of the channel near the drain can no longer be maintained by the applied gate voltage. The drain voltage at the onset of saturation is denoted by V Dst' and can be expressed in terms of device parameters and applied gate Voltage.


V =V - - 20 + s oA Il 1+ ox G F
Dsat G FB F C 2 KL KE oJN

(3.41)

where

V B= "flat-band" voltage of the IGFET

0 F= Fermi potential of the substrate.


Any further increase of drain voltage beyond this value is then pictured to result in the formation of a depleted region of length Z~dep between drain and channel as shown in Figure 3.10. This is equivalent to assuming that the voltage at the end of the channel which corresponds to the edge of the depletion is V Dsat' In weak inversion operation, there is

















VG >VT


Figure 3. 10


Cross-section of MOS transistor operating in saturation region.
0





-70-


no drift component in the channel current; therefore, the variation of surface potential along the channel is very small [42]. The current is mainly from diffusion of minority carriers due to the concentration gradient. Therefore, the end of the channel should be the point where the minority-carrier concentration equals zero. For simplicity, we define the end of the channel as the point where the semiconductor is intrinsic. The potential at this point is denoted by V t as distinguished from

conventional V .By definition V ' can be expressed by
Dsat* Dsat



V - = -V -0 +_ K sc N A- K/l2c x2VG -VFB)
Dsat G FB F C j 0q

(3.42)

Note that the only difference between (3.41) and (3.42) is the factor "2" in front of the Fermi potential 0 F*

The extent of the depleted region depends on the difference between the potential of the drain, V D2 and that at the end of the channel, V~t and on the average transverse electric field component near the Si-SiO2 interface, E T*Thus

V - V
Y.dep =- ETDa (3.43)


According to Frohman-Bentchkowsky and Grove's model [30], this average transverse field is-attributed to the superposition of three electric fields as shown in Figure 3.11. E 1 arises from acceptor ions within the drain depletion layer, E X2 is the X-axis component of fringing field E which arises from the drain-gate potential difference, and E X3is the X-axis component of fringing field E which arises from the gate to V
3 Dsat
difference. Thus






-71-


OX IDE - SEMICONDUCTOR
INTERFACE -,


Figure 3. 11


The electric field distribution for MOS device operation in saturation.





-72-


ET = E1 + EX2 + EX3 (3.44)


The field E1 can be obtained from the step junction approximation qN A(V(.5
72K (VD VDs
so
A rigorous calculation of the contributions of EX2 and EX3 requires a


solution of Poisson's equation in the depletion region near the Si-SiO2 interface. However, they can be given by the approximations [30]
K (VD -VG +V VF)
E K D G FB (3.46)
X2 K t
s ox
K (V-V -V V )
E X3 FB Dsat (3.47)
s ox

where K and t are the dielectric constant and thickness of the gate
o ox
oxide layer respectively, and a and a are the field-fringing factors which represent the extent to which the normal oxide field fringes in a transverse direction into the depleted region near the drain. Good agreement between theory and experiment was obtained over a wide range of device parameters and applied voltages for the values a = 0.2 and

0.6.

Combining equations (3.43)-(3.47), we obtain


kdep (V -Vs) [ (V+ -V ) (VDVG + VFB)
D Dsat [ D Dsat t


( (VG - VF - V ] )
(Ko (G - FB Dsat)
+
\s)


In the limiting case of high substrate concentration, the first term in the bracket of (3.48) will dominate, and the expression of Zdep reduces to





-73-


2K c
Zdep qN (VD V (3.49)


which corresponds to the results obtained by Ihantola [48] and by Reddi and Sah [44]. The effective channel length now can be expressed as


L(VD) = , - 2X. - kdep (3.50)


where LM is channel length defined by the gate mask, and X. represents the lateral underdiffusion from the source and drain. Differentiating (3.50) leads to
L(VD (FK) (V D V ) + (Ko/K t )( - a)(VG - VFB - V
DL( D ( k)sat o s ox G F s~
dVD 1 9 2 1-2t(V
D (-) (V - V + (Ko/Kst )-F + (2K/-KKsto)(V - V F
K D Dsat o s ox o o Dsa

(3.51)

2K
where K = s 0 (3.52)
qNA


F = a(VD -VG +VFB) + (VG VFB - V ~sat) (3.53)


With equations (3.36), (3.40), (3.48) and (3.51), the transfer inefficiency ED due to the subthreshold current can be calculated. In Figure

3.12 the theoretical values of tD are plotted as a function of the channel length L for different substrate concentrations NA



3.5.3 Transfer Inefficiency Due to Barrier-Height Modulation


Another mechanism that affects the transfer inefficiency at low frequencies is the barrier-height modulation due to variation of drain voltage with different signal charges. To analyze this mechanism we will not consider the effects of subthreshold leakage current which have been treated in the previous subsection. In addition, we assume the









I I I


Cs
CD


rj = 1.5Fm tox = 0.11 .m


=6 x 1014 1.7X 1015 x 1016


5 t I I I


8
CHANNEL


12
LENGTH i


(urm)


Figure 3.12


Theoretical transfer inefficiency due to subthreshold leakage current as a function of channel length for different substrate concentrations.


10-4


10-"


0






-75-


frequency is so low that the surface potential on the left of the barrier equals the potential of the barrier as shown in Figures 3.9a and 3.9b. These assumptions simplify the calculation because the amount of untransf erred charge is completely determined by the product of the barrier potential and the capacitance of the region to the left of the barrier. The objective then is to find the barrier potential as a function of transferred charge. The transfer inefficiency can then be found from

dQ 1 __d(V G - V T) dV T
6 B = dQ 0=Cs dQ 0 Cs dQ 0(.4


where Q1is the untransferred charge at the end of transfer, Q 0is the transferred charge. C sis the capacitance of the source node, and V T is the threshold voltage of the switch transistor T r

In conventional MOS theory, the threshold voltage of an IGFET is simply obtained by applying the charge conservation principle to the region bounded by the gate and bulk of the semiconductor and neglecting any two-dimensional edge effects at the source and drain ends. This may be written as [49]



+M + +F ' N B a (3.55)


where Qis the charge on the gate, QF includes the fixed charge in the Sio 21 QN is the charge due to the free carriers in the surface inversion layer, and Q B is the fixed charge due to the ionized impurities in the depletion region. For an N-channel IGEET, equation (3.55) may be expressed in terms of voltages as [49]


V G = VFB + 0 s- (Q + Q N)C (356


(3.56)






-76-


where 0 S is the surface potential with respect to the substrate. By using the commonly used criterion for surface inversion, the expression for the threshold voltage is [42,49]


V T = V FB + bO F - QB /C ox (3.57)


where 0 F is the bulk Fermi potential and b is the band-bending parameter which determines the degree of inversion. The effect of the bulk charge

in equation (3.57) is to increase the magnitude of the threshold voltage. However, due to the two-dimensional edge effect, the full effect of Q B on the threshold voltage is decreased when the channel length is reduced and becomes comparable to the junction depth of the source and drain. As the distance between the source and drain decreases, the influence of the source and drain on the electrostatic potential distribution under the gate increases. In contrast to the conventional long-channel theory, a large fraction of the field lines originating from the bulk charge under the gate are terminated on the source and drain islands, causing the threshold voltage to be lower than what is predicted by equation (3.57). This ion-sharing effect near the ends of the channel results in a dependence of threshold voltage on the channel length and on the drain voltage [28,29,45].

To analyze the dependence of threshold voltage on the channel length and drain voltage requires a two-dimensional numerical analysis of the IGFET [50,51]. However, many one-dimensional models which take into account the two-dimensional field distribution have been reported. Cheney and Kotch [52] first modified the threshold voltage expression for the case of a large substrate bias by including the effect of the depth of the source and drain diffusion. This results in a correction





-77-


at high backgate bias. To include the short-channel effect for low backgate bias, Lee [451 refined the model of Cheney and Kotch, and after a lengthy piecewise one-dimensional analysis, he obtained a very complicated closed-form expression for the threshold voltage as a function of channel length, drain voltage, and junction depth. By introducing two experimentally determined weighting factors, his theory And experiments appear to agree much better than that of Cheney and Kotch. Yau [28] used a simple geometrical approximation in conjunction with a charge conservation analysis to obtain a threshold voltage expression which has the advantage of a simple form and, at the same time, retains the physical insight of the original charge conservation approach. Although his theory is in excellent agreement with experiments, the expression is only applicable for the case of zero drain-to-source voltage. To take into account the effect of drain-to-source voltage, Taylor [29] modified Yau's mLodel. His theory was corroborated by experiments over a wide range of drain and gate voltages. In the following discussion, a simple model which is applicable to the operation of bucket-brigade devices will be presented. The approach taken is similar, in some respects, to the derivations of Yau and Taylor.

To include the edge-effects of bulk charge Q B in the expression of VT, we assume a source and drain junction with a cylindrical edge of radius, r., equal to the depth of the N+ islands as shown in Figure 3.13. Directly under the middle of the gate, the width of the bulk space charge is


W = K(0 +VS) (.8


(3.58)















































Figure 3.13


Model to calculate threshold voltage of an MOS transistor.






-79-


where K is defined by equation (3.52). Without going through a twodimensional analysis, the field lines arising from the bulk charge can be approximated as drawn in Figure 3.13. The field lines originating from the fixed charge inside the trapezoidal region are terminated within the effective channel length (L - idep), whereas the field lines from the fixed charge outside the trapezoidal region are terminated in the N+ islands. Based on this geometrical approximation, the total bulk charge inside the trapezoid is


Q (L - k~dep) qN AW (L+ L 2 dep) (3.59)


Q =qNW 14( dep) (3.60)


where Q represents the average charge per unit area in the effective channel length of (L - kdep), where 9kdep is defined by equation (3.48).

The threshold voltage V T at weak inversion (b = 1) now can be expressed as


VT VF + 0 + Fb x /A o(V t + 0F (3.61)
ox

with

F =(L + L -dep) (3.62)
b 2(L - kdep)


is the form factor for barrier modulation. In equation (3.61), the source potential has been replaced by V~st This is because at the end

of the charge transfer process, the subthreshold leakage current will decay twoard zero, and the source potential will reach (V G - VT) V Dsat.

From Figure 3.13, the form factor can be calculated by straightforward geometrical analysis:





-80-


L = L - L1 - L2 - Adep L = (r -W 2 - r. L = (r 2 2 W) - r. - dep r = r + /K(Vbi + V )
1 j bi Dsat

r2 = r. + K(Vbi + VD) W = /K(Vs + 0F)
Dsat F


(3.63) (3.64) (3.65)


(3.66) (3.67) (3.68)


where Vbi is the build-in voltage of the N+ junction. Combining (3.62)(3.68) we obtain


F = [1 b [L


L1 + L2 2(L - kdep)


(3.69)


L1 = 2


L2 = [ r
2 j


2rj /K(Vbi + V Ds ) + K(Vbi j bi Dsat bi


- 0F] 2-rj


+ 2r. /K(Vbi + VD) + K(VD + Vbi - V Dsat
S bi D D b Dsat


(3.70)


- 0F)]


(3.71)


- (rj + Rdep)


From equations (3.37), (3.54) and (3.61), the transfer inefficiency due

to barrier modulation B now can be expressed as

C 2qNAK E V
E = S x soX (V + O )
B CD 2 (Dsat F
ox


x 1


qNKsat c
+Fb 2
ox Dsat


dFb dVD


(3.72)


(L - Edep)


dL2 + L dde
dV 2 dV
(3.73)


2(L - Zdep)/


dFB
dVD





-81-


dLD 2 [r' + 2r. *K(Vbi + VD) + K(VD V Va
-d[VD 2 j + bi Dsat OF



x Kr + K dep (3.74)
V(Vbi + VD)

where ddep can be obtained from equation (3.50)-(3.51). The second
dVD
bracketed term in (3.72) represents the effect of the change of depletion width under the gate due to the source potential being modulated. This term is only important at high substrate concentration (CB > 1016Cm-3). For the simplified case of source and drain junction with vertical sides (or the equivalent condition r. >> IK(V ' + 0) equations (3.70), ( Dsat F
(3.71), and (3.73) reduces to the forms


L, = /K(Vbi + V Dsat) (3.75)

L2 = VK(Vbi + VD) - kdep (3.76)


dL2 1 1 K dkdep (377)
dVD 2 /K(Vb + VD) dVD


Again for the case of a circulating charge Q and signal charge of Qo - Qc)' the transfer inefficiency also can be obtained by
AVT. x Cs
= AV T C) (3.78)
B (Q 0- Q)

where AVT is the threshold voltage variation of the switch transistor when Qc and Q are present at the drain node. This threshold voltage variation AVT is obtained by calculating the variation of form factor AFb for different drain potentials, and multiplying by the two bracketed terms in (3.72).

For the model discussed in this section it is assumed that the






-82




substrate concentration is uniform, the one-sided junction approximation is valid, and that the channel length is long enough so that the source and drain depletion regions do not meet under the -ate. Any deviation from these assumptions will cause errors and affect the accuracy of this model. In Figure 3.14, the theoretical values of c B are plotted as a function of channel length for different substrate concentrations N A' In Chapter 6, the models discussed in this chapter will be compared with experimental results.











Cs CD


10-2


z


Li
z
ILl


z
-


rj = 1.5p m tox = 0.11 m







NA 6 x 1014

17x1015









3 x 1016 -


I I I I I


8
CHANNEL


16
I(jim)


Figure 3.14 Theoretical transfer inefficiency due to barrierheight modulation as a function of channel length
for different substrate concentrations.


-83-


10-1


10-4
0


12
LENGTH

















CHAPTER 4

ANALYSIS OF THE OPERATING MECHANISMS AND NOISE
LIMITATIONS OF THE OPTIMUM IMAGE SENSOR



4.1 Charge-Storage Operation of a'Photodiode


The photodiode used in a solid-state image sensor is operated in the charge-storage mode instead of the normal photoconductive or photovoltaic mode. In the normal photoconductive or photovoltaic mode, the output from a photodiode depends on the rate of photon absorption; however, as discussed in the previous chapter, the photodiodes in an image sensor are sampled in a periodic manner. Therefore, the active properties of the diode are used only during the time of sampling. To fully utilize the sensing diode during the total sensing period, the photon flux has to be integrated, which leads to the charge-storage mode of operation.

In the charge-storage mode of operation the photodiode is precharged first to a fixed reverse bias of a few volts, and the circuit is then opened so that the junction behaves like a capacitor which discharges smoothly under the influences of the illumination and the junction leakage current. While the photodiode integrates the light, it provides a means to evaluate the total irradiation energy received. The charge lost during the light integration period is proportional to the illumination energy received by the diode multiplied by the duration of light integration. Thus, by monitoring the charge required periodically to


-84-






-85-


re-establish the initial-voltage condition, one may obtain a signal proportional to the incident illumination. The advantages of this mode of operation are the improvement of responsivity resulting from integration of the incident illumination and the capacity to control the responsivity-by varying the-integration time.

The signal charge Q obtained from the sensing diode at each sampling time can be expressed as


Q=(I + I )T (4.1)
Qs p L i


where T.i is the total integration time, and I pand I L are the photocurrent and the leakage current respectively. The photocurrent I is related to
p
the incident power by


I = gAnAP (4.2)
p hc


where A is the sensing diode area in cm2

n is the quantum efficiency

X is the wavelength of the incident light

P is the incident power in watt/cm 2

h is the Planck's constant

c is the velocity of the incident light


It is obvious from equation (4.1) that if I 1>I' the signal charge QS will be proportional to the integration time T ., and, therefore, the sensitivity will increase by increasing T.i . However, at low light level the contribution of the leakage current is no longer negligible. This leakage current not only introduces shot noise, but also results in a fixed-pattern noise due to the dark current non-uniformity in each






-86-


sensing cell. In the very low light level limiting case where I >>I L .p'
the sensing diode will be saturated by the dark current; therefore, the dark current plays a very important role in the low light level applications of an image sensor. The leakage current is a strong function of temperature and can be written as [49]


1 n. (3
IL qoJ WiA 43


where Tis the effective lifetime within the reversebiased depletion region

W.i is the width of the depletion region

A. is the junction area.


The maximum amount of charge that a photodiode can store before it spills over the anti-blooming control gate is also important. This is commonly referred to as the saturation charge of photosensor. This saturation charge determines the maximum output level and, therefore, affects the useful dynamic range of the device. This saturation charge can be obtained by integrating C(V)dV from the initial vo .ltage V 0to the final voltage V Fwh ich is determined by the anti-blooming gate voltage. Assuming a one-sided step junction, the result can be given by



Qsat = (qK s c0N A) [(V + 0B;__- (v + O) 12 (4.4)


where 0 Bis the junction built-in potential. For a linearly graded junction, the result becomes



wher ~ ~at . [qaK s2E 2] 1/3 [(V0 + 0B2/3 -(F+B 2/3] 45

wher "a"is the impurity gradient in cm4 and can be approximated by [53]





-87-


NA No
a A 9,n 0(4.6)
X. x 0.7 %N A46


where X. is the junction depth and N is the surface concentration of
J 0

the N diffusion which is usually around 1020 cm-3

The voltage drop across the photodiode is also proportional to the total energy received. This voltage drop provides another way to sense the total incident radiation by connecting a MOS sensing gate to each diode. However, since the depletion layer capacitance varies with reverse bias, the relationship between irradiant energy and reverse bias voltage is nonlinear. Assuming that the photocurrent is predominant, the voltage across the junction as a function of time and photocurrent can be obtained by solving the following equation [1]


C(V) dV(t) -I (4.7)
dt p

which leads to


V(T) = [V - t (4.8)
0 A s 2qK s o NA)


for the one-sided step junction, and


V(t) = 2/3 _ 2_P () 1/3 t]3/2 (4.9)
0 3 A s (qaK s2o02)


for the linearly graded junction. As is the total sensing diode storage area. Other than the nonlinearity of the optical-to-electrical transfer characteristic, this voltage pick-up sensing method offers certain advantages such a low reset noise, nondestructive readout, and higher sensitivity.





-88-


4.2 Sensing Diode to BBD Analog Register Charge-Transfer Mechanism


The charge transfer mechanism from the sensing diode into the BBD register, for the optimum area image sensor described in Chapter 2, is very similar to that of the tetrode bucket-brigade device. Figure 4.1a shows the equivalent circuit of the charge transfer path. C represents, the storage capacitance of the sensing diode, 0 is the multiplex switch,
C, M

C vis the video line capacitance, and C.i is the junction capacitance of the N diffusion between the LR and LT switches. The line reset LR switch is not shown in the equivalent circuit since it is turned off during the charge transfer process. Figure 4.1b shows the potential at each node before the charge transfer. Since C vis much larger than both C sand C. the charge transfer seed will be limited by the discharge of C through the V bufgate.

Ideally, during the charge transfer process, the MOS switches should cut off when the potentials of each capacitor reach a value of (V G-VT), where V Gand V Tare the gate potential and threshold of the MOS switches. However, as discussed in Chapter 3, due to the subthreshold leakage behavior of the MOS switch, the current does not cut off sharply. Instead, it decays exponentially, and as a consequence, the potential at each capacitor will increase slowly beyond the (V G-VT) level with increasing time. Theoretically this leakage current never ceases, and the potential of the capacitor keeps increasing. However, in real applications, when the current reaches a negligible level, the MO S switch is considered to be in the off state.

To derive the equations for the charge transfer speed let us consider the worst case transfer efficiency of the buffer gate at very low light levels. Because the buffer gate is biased at a DC level of Vbuff'


























Figure 4. 1


(a) Equivalent circuit for charge transfer between the sensing diode
and BBD shift register.

(b) Potential at each node before charge transfer.









BBD REGISTER


#X2


C




SENSING DIODE
LEVEL


ox1


LT LOW


kM LOW
__-


PM
HIGH


Qs
b.
V(t)



/


Vbuff


(a)










(b)


-I


/-LT HIGH




BBD RECEIVING GATE


M
-1


LT


VB

/





-91-


after each charge transfer the potential of the common video line will increase with time which is depicted as V v(t) in Figure 4.1a. From Chapter 3, the subthreshold leakage current through the buffer gate can be expressed as
qDnoLBW -V(t/k
Is(t) = n e (4.10)
st L eff


where V(t) = V v(t) - (Vbuff - VTbuff)

Leff is the effective channel length of the buffer gate

VTbuff is the threshold voltage of the buffer gate.


V(t) is the video line potential below the (Vbuff - VTbuff) level as shown in Figure 4.1b. As the value of V(t) increases, the current decreases exponentially toward zero.

The small signal "ON" resistance of the buffer gate, operated in this subthreshold region, now can be obtained by


dV LeffkT V(t)q/kT(4.11)
RdI 2. e
st q2DnoLBW

From Chapter 3, the V(t) can be expressed by


V(t) = T 9n [1 + q2DnoLBW ,t (4.12)
q kTLeffC v

q 2q Dn L WI
ikT n o IB t (4.13)
q L kTL eff C v

where C is the video line capacitance. Substituting (4.13) into (4.11),
v

the small signal "ON" resistance now becomes


R = t (4.14)
C
v





-92-


It is clear from equation (4.14) that the subthreshold "ON" resistance is independent of the geometry of the MOS switch. Therefore, increasing the size of the MOS switch will not help the transfer speed. Multiplying both sides of equation (4.14) by C results in a small signal
0 v

RC time constant of "t." The worst case time is the total integration time. This worst case corresponds to the condition that only one diode in the common video line is under illumination, and the rest are in the dark.

In the above discussion, it is assumed that signal charge dumped into the video line is so small that it does not change the video line potential V v significantly. Under this low light level, the charge transfer time constant is so long that with a finite transfer time T t which corresponds to the pulse width of the LT clock, most of the signal charge will be trapped on the video line. However, at high light levels, the charge dumped into the video line is large enough to modulate the video line potential considerably. As a result, the initial charge transfer speed will increase greatly, and the percentage of signal charge trapped on the video line will become less important.

To calculate the charge trapped on the video line after a finite transfer time, Tt. at high light levels, let us assume that only one of the diodes in the video line is illuminated, and a signal charge of Q s is dumped into the video line when this diode is selected. The signal charge will lower the video line potential by an amount Q s /C V* Let us further assume that the g M of buffer gate is large enough that the video line potential will be discharged to (V buff - V Tbuff ) in a time which is negligible compared with the total transfer time T t* At the end of the transfer time, the video line potential will be





-93-


kT DL
V(Tt kB n + kTLB T (4.15)
t qkTL C. t

where n is the equivalent carrier concentration at the source end of
0

the buffer gate when Vv = (Vbuff - VTbuff). Before the illuminated diode is selected again, the video line potential will reach V(Ti), where T. is the integration time. The expression of V(Ti) is identical to equation (4.15) with T, replacing T . The signal charge lost now can be determined
1t
from


Q= C [V(Ti) - V(T )] (4.16)


With a typical integration time of 4 ms and transfer time of 4 1s, the charge loss calculated from equation (4.16) is about 30% even at a saturation charge level of 1.5 pc. This results from the video line capacitance, C , being about ten times larger than the sensing diode storage
v

capacitance C
s

For the low light level case, let us assume that after the video line potential has been lowered by a magnitude of Q s/Cv, its potential is still "V " below the (V buff - VTbuff) level. The video line potential then can be expressed by
q~inoWLBoqk

V(t) =.kT Pn ( LnoC B t + e Vo0kT (4.17)
q ( L effC v

In equation (4.17), the electronic diffusion constant D has been replaced by pn using Einstein's relationship, and the initial condition V = Vo at t = 0 also has been incorporated. The worst case charge transfer inefficiency now can be determined from

Cv [V(Tt) - Vo]
= (4.18)
C [V(Ti) - Vo]
vo





-94-


InqpnnWL Bx T \
Fq n no VLB T 1 4.9

no Bf ___eV __q1,




Examining equations (4.16) and (4.19) indicates that the ratio of T I T.i is important in determining the transfer inefficiency. To reduce this ratio, the V gate can be clocked instead of DC biased. It can
buff

be clocked with a pulse which is about the same width as the LT pulse. However, in order to have the anti-blooming circuit function properly, the rising edge of the Vbuff pulse should lead the rising edge of the LT pulse by his or more to allow the video line to be reset through the LR switch before charge transfer. Using this clocking scheme, T . in equations (4.16) and (4.19) can be replaced by T onwhich is the total buffer gate "ON" time duri ng. the total integration time T. In Figure

4.2, the transfer efficiency is plotted as a function of Q /C for a
5 V

T t= 2iis and T on 300iis. It is clear that the transfer efficiency is still very poor.

To increase the charge transfer speed, a background charge of Q

is needed. The function of this background charge is similar to the "fat zero" in the BBD reg ister. As discussed in Chapter 3, this background charge will speed up the apparent transfer rate considerably, since the charge lost will be the difference of the charges left behind when the initial charges are Q cand (Q C+ Q s). Using the result of Chapter 3, the low light level transfer inefficiency, which corresponds to 0 s t 0,

can be expressed as

4C4
C(T d 2v 22(4.20)
c t




Full Text
-55-
During the time the gate voltage is V the excess charge in the source
Ct
is defined as
Q(t) = C[Vg(t) (VG VT)]
(3.12)
The source-to-drain current is
I =
dQ(t)
dt
(3.13)
combining equations (3.10), (3.12), and (3.13) gives
dQ(t) = e [~Q(t)l2
dt 2 L C J
(3.14)
integrating (3.14) leads to
/ BQ t\ 1
Q where Qq is the initial charge in the source.
(3.8) gives
6<2
-1
Q(T) = Q 1+ IT?
c
The transfer inefficiency e is defined by
(3.15)
Combining (3.15) with
(3.16)
(t) = dQ(T-^
C } dQo
(3.17)
Differentiating equation (3.16) leads to
-2
e(x) = 1+
3Q,
4f C
c
(3.18)
It is convenient to perform a Taylor expansion in f of (3.18),
e(x) =
16C4f 2
c_
2 2
Qo B
(3.19)


-155-
T. = 47 ms
x
Vertical scale
= 0.1 V/div.
Horizontal scale
= 0.1 ms/div.
Figure 6.21
Dark current response of the image sensor
with two different integration times.


-86-
sensing cell. In the very low light level limiting case where IT>>I ,
L p
the sensing diode will be saturated by the dark current; therefore, the
dark current plays a very important role in the low light level applica
tions of an image sensor. The leakage current is a strong function of
temperature and can be written as [49]
1 n-
IT = q W.A (4.3)
L 2 ^ x_ 1
0 J
where Tq is the effective lifetime within the reverse-
biased depletion region
Wj is the width of the depletion region
A. is the junction area.
The maximum amount of charge that a photodiode can store before it
spills over the anti-blooming control gate is also important. This is
commonly referred to as the saturation charge of photosensor. This
saturation charge determines the maximum output level and, therefore,
affects the useful dynamic range of the device. This saturation charge
can be obtained by integrating C(V)dV from the initial voltage Vq to the
final voltage V^, which is determined by the anti-blooming gate voltage.
Assuming a one-sided step junction, the result can be given by
sat
= (qKs£oNA)2£(V + Kf2 (V* + 0n)']
(4.4)
where 0^ is the junction built-in potential. For a linearly graded junc
tion, the result becomes
3
sat
x, 2 2
qaK e
so
12
1/3
[(Vo + 0b)2/3 (VF + 0b)2/31 (4:5)
where "a" is the impurity gradient in cm and can be approximated by
[53]


-77-
at high backgate bias. To include the short-channel effect for low back-
gate bias, Lee [45] refined the model of Cheney and Kotch, and after a
lengthy piecewise one-dimensional analysis, he obtained a very complicated
closed-form expression for the threshold voltage as a function of channel
length, drain voltage, and junction depth. By introducing two experimen
tally determined weighting factors, his theory and experiments appear to
agree much better than that of Cheney and Kotch. Yau [28] used a simple
geometrical approximation in conjunction with a charge conservation analy
sis to obtain a threshold voltage expression which has the advantage of
a simple form and, at the same time, retains the physical insight of the
original charge conservation approach. Although his theory is in ex
cellent agreement with experiments, the expression is only applicable
for the case of zero drain-to-source voltage. To take into account the
effect of drain-to-source voltage, Taylor [29] modified Yau's model.
His theory was corroborated by experiments over a wide range of drain
and gate voltages. In the following discussion, a simple model which
is applicable to the operation of bucket-brigade devices will be pre
sented. The approach taken is similar, in some respects, to the
derivations of Yau and Taylor.
To include the edge-effects of bulk charge CL. in the expression of
V^, we assume a source and drain junction with a cylindrical edge of
radius, r equal to the depth of the N+ islands as shown in Figure 3.13.
Directly under the middle of the gate, the width of the bulk space charge
is
W = + V )
s s'
(3.58)


CHAPTER 1
INTRODUCTION
Electronic imaging devices perform the task of converting a pattern
of incident radiation falling upon the surface of the sensor into an
electrical signal which is an ordered, sequential reproduction of the ra
diation pattern. The basic architecture of an image sensor, therefore,
can be reduced to two basic functions, namely, the detection of photo
generated carriers and the readout of information gained thereby. For
some time the successful development of solid-state image sensors has
been regarded as a highly desirable goal, since solid-state sensors are
superior in performance and could be cheaper than electron beam scanned
camera tubes due to their small size, low power consumption, high reli
ability, and long life. In addition, their expected ruggedness and
immunity to shock, vibration, and electromagnetic field provide attractive
features for such devices. However, until recently, the state of develop
ment of solid-state image sensors was still far from satisfactory.
The development of solid-state image sensors began in the early 60's
and with the rapid advancement of semiconductor technology, several types
of image sensors were developed. They are referred to as self-scanned
photodiode arrays [1-3], charge injection image arrays [4-6], and charge-
coupled image arrays [7-17]. Each type of array uses a different
architecture to perform the photo-detection and the signal readout func
tions. As a result, each type of device possesses certain advantages and
drawbacks which limit its performance.
-1-


Q
N +
P-SUBSTRATE
Figure 3.13 Model to calculate threshold voltage of
an MOS transistor.


Table 1. Noise Source in the Optimum Image Sensor
N
n
DESIGNED VALUE OF N
n
SOURCE
Thermal Noise of Sensing
Diode Multiplex Switch
Shot Noise of Sensing
Diode Dark Current
Thermal Noise of Buffer Gate
200 C = 0.24 pF
s
270 Assume 1% dark signal
700 C = 3 pF
v
400 /C
pf
\ Ti
400 VC
pf
BBD "fat-zero" Generation
BBD Transfer Noise
BBD Output Sensing
Node Reset
MOSFET Amplifier
400 /C
pf
- (2m N kTC)?S
Q s
400 /c
pf
60 C
gate
AB \ /lOOO pmho\
5 MHz/ V 8mo )
310 C. = 0.6 pF
in
4400 N =100 C = 0.6 pF
g
280 C = 0.5 pF
out
22 AB = 5 MHz
g =1700 pmho
mo
C = 0.48 pF
gate
Total Equivalent Noise
4490
Fixed-Pattern Noise Due to
(VTLT-VTLR) VarIatl
c.
AV,
Tn
q
13,800 C^ = 0.11 pF
AV = 20 mv
In
m = 1
-106-


-60-
storage capacitance C, the limiting process for the speed of charge
transfer is the discharge of the large storage capacitance C through the
tetrode transistor T This is because any small amount of charge ac
cumulated in node y will lower considerably and cause a sharp increase
of the current passing through the switch transistor T to discharge the
ITS
accumulated charge. Therefore, equation (3.23) has to be modified for
the tetrode BBD with the parameter g of the tetrode transistor T re
placing that of the switch transistor Trg
In the derivation of equation (3.23), we assume that the switch
transistor T^g is always operated in the saturation region, which is al
ways true as discussed previously. However, this is not exactly the case
for the tetrode T in the tetrode BBD. During and right after the clock
transition, the voltage at node y will be charged to a potential
V < (V__ V_), and then quickly discharged to near (V V). There-
y BB l (j i
fore, during the very early stage of the charge transfer process, the
tetrode transistor T is operated in the linear region instead of the
saturation region. However, a rigorous computer simulation using the
ASPEC transient program shows that with a capacitor ratio of C/C^ = 20-30,
and the same 0 parameter for both the switch transistor T^g and the te
trode transistor T the time that the tetrode transistor operated in
rt
the linear region during the early stage of charge transfer process is
around 2-3% of the total charge transfer time. The total charge transfer
time here is defined as the time required for the transfer inefficiency
due to the charge transfer rate limitation to drop to the low frequency
limitation value due to channel-length and barrier-height modulation.
Therefore, the error introduced by assuming that the tetrode transistor
T is always operated in the saturation region is negligible.


CHAPTER 5
DEVICE FABRICATION AND MEASUREMENT METHODS
5.1 Device Fabrication
The test MOSFETs, bucket-brigade shift registers, and optimum image
sensor used in this study were fabricated using standard double-layer
polysilicon-gate MOS technology. The substrate materials were <100>
14
orientation, boron-doped p-type with doping concentrations of 6 x 10
15 -3
and 1.7 x 10 cm The fabrication process steps are summarized as
follows:
O
(1)
Initial oxidation: 4000A
(2)
First photoresist mask: definition of
(or channel stop) regions
field
(3)
Channel stop ion implant
(4)
Implant drive-in and field oxidation:
1 pm
(5)
Second photoresist mask: definition of
regions
active
(6)
Gate oxide growth: 750 1100A
(7)
Deposition and phosphorus doping of the
layer polysilicon
first-
(8)
O
First-layer polysilicon oxidation: 2000A
(9)
Third photoresist mask: definition of the
first-layer polysilicon gates for the MOSFETs
(10)
Gate oxide etching and light phosphorus
for the storage capacitor regions
doping
(11) Gate oxide growth for the storage capacitors
-108-


-94-
E =
. (. 'V..
In t1 + i/c x
\ erf v
V q/kT
e o
(qy n WL
1+-^x
eff v
V q/kT
e o
(4.19)
Examining equations (4.16) and (4.19) indicates that the ratio of
T /T^ is important in determining the transfer inefficiency. To reduce
this ratio, the V, .. gate can be clocked instead of DC biased. It can
buff
be clocked with a pulse which is about the same width as the LT pulse.
However, in order to have the anti-blooming circuit function properly,
the rising edge of the V, __ pulse should lead the rising edge of the
LT pulse by lys or more to allow the video line to be reset through the
LR switch before charge transfer. Using this clocking scheme, T_^ in
equations (4.16) and (4.19) can be replaced by TQn which is the total
buffer gate "ON" time during the total integration time T^,. In Figure
4.2, the transfer efficiency is plotted as a function of Qg/Qy fr a
T = 2ys and T = 300ys. It is clear that the transfer efficiency is
t on
still very poor.
To increase the charge transfer speed, a background charge of Qc
is needed. The function of this background charge is similar to the "fat
zero" in the BBD register. As discussed in Chapter 3, this background
charge will speed up the apparent transfer rate considerably, since the
charge lost will be the difference of the charges left behind when the
initial charges are and (Qc + Q ). Using the result of Chapter 3,
the low light level transfer inefficiency, which corresponds to Qg 0,
can be expressed as
e(Tt)
Q
4
V
(4.20)


142
Figure 6.12 Photograph of the 100 x 100 photodiode
charge-transfer image sensor. The chip
measures 279 x 282 mil^.
+


Abstract of Dissertation Presented to the Graduate Council
of the University of Florida in Partial Fulfillment of the Requirements
for the Degree of Doctor of Philosophy
STUDY OF THE OPTIMUM CHARGE-TRANSFER
IMAGE SENSOR
By
Hsin-Fu Tseng
March 1979

Chairman: Sheng-San Li
Major Department: Electrical Engineering
This research deals with an investigation into the optimum structure
for a solid-state image sensor. This optimum structure consists of dif
fused diodes for photosensing, and either a bucket-brigade or charge-coupled
transfer register for signal readout. The photodiode sensors offer the
advantages of full, smooth spectral response and high quantum efficiency,
while the charge-transfer register provides a low noise self-scanned video
output. A matrix array with two tetrode bucket-brigade readout registers
is fabricated and studied. This array consists of 10,000 photodiodes ar
ranged in 100 columns and 100 rows. Each row of diodes is selected in
sequence by a digital scanning register, and the resulting signal charges
are transferred in parallel to two 50 stage odd and even bucket-brigade
registers by means of video lines and transfer gates common to all diodes
in a column. The outputs of the two 50 stage registers are then multi
plexed to obtain a single 100 stage video signal.
Models describing the operating mechanisms of the bucket-brigade and
image sensor devices are developed. It is shown that for a tetrode bucket-
brigade device the high frequency operation is limited by the intrinsic
v


CHAPTER 3
ANALYSIS OF THE BUCKET-BRIGADE SHIFT REGISTER
3.1 Introduction
The basic structure of the bucket-brigade device (BBD) is shown in
Figure 3.1. This device in its integrated form was invented by Sangster
[21,22] in 1968. There was much interest [23-25] in this device since
it offered the first glimpse of a practical way of implementing an analog
delay. However, the initial device had many shortcomings, with the major
one being very poor transfer efficiency. Potential variations during the
charge-transfer period introduced excessive channel-length and barrier-
height modulation, and consequent transfer inefficiency. As a result,
the device was limited to a small number of stages and low-frequency
applications.
The first major advance made in improving the transfer efficiency
was also made by Sangster and his co-workers [26,27]. It came from the
introduction of an isolation or tetrode structure, with a DG biased
gate, separating each clocked element from its neighbor, as in Figure
3.2. Devices fabricated employing this tetrode structure were found to
perform reasonably well, but transfer efficiencies were still less than
one could wish; furthermore, stability was erratic and the devices were
sensitive to clock shapes, particularly the transition edges. Before
these problems could be solved, charge-coupled devices (CCD) [39] were
-31-


-87-
\
a
N. N
Hn
X. x 0.7 N
J A
(4.6)
where X. is the junction depth and Nq is the surface concentration of
+ 20 -3
the N diffusion which is usually around 10 cm
The voltage drop across the photodiode is also proportional to the
total energy received. This voltage drop provides another way to sense
the total incident radiation by connecting a MOS sensing gate to each
diode. However, since the depletion layer capacitance varies with re
verse bias, the relationship between irradiant energy and reverse bias
voltage is nonlinear. Assuming that the photocurrent is predominant,
the voltage across the junction as a function of time and photocurrent
can be obtained by solving the following equation [1]
C(V)
dV(t) =
dt
(4.7)
which leads to
vm- K'-MaN
for the one-sided step junction, and
2/3 2 Ip / 12_
V(t) =
1/3
V
3 A I 2 2
S \qaKs £o ,
3/2
(4.8)
(4.9)
for the linearly graded junction. A is the total sensing diode storage
area. Other than the nonlinearity of the optical-to-electrical transfer
characteristic, this voltage pick-up sensing method offers certain advan
tages such a low reset noise, nondestructive readout, and higher
sensitivity.


-114-
Figure 5.3
The output of a BBD shift register which
has transfer inefficiency charge loss,
with an input pulse five clock periods
long.


-104-
4.4.3 Noise Sources Associated With the BBD Shift Register
The noise sources associated with the shift register are fat-zero
generation noise, charge transfer noise, output floating diffusion reset
noise, and the output MOSFET noise. The fat-zero generation and floating
diffusion reset noise sources are kTC noise, their rms noise electron
value is determined by the input and output sensing node capacitances
respectively.
The charge transfer noise source is also kTC noise associated with
the resistance of the transfer switches. Assuming transfer inefficiency
£ = , and a transfer time much larger than the RC time constant of the
transfer switch resistance and storage capacitor, the rms noise electron
value can be expressed by [55]
with m
C
ox
= (2mN kTC)J$
q g
+ CD
C
ox
where C = (Cqx + C^) is the total storage capacitance
C is the gate oxide capacitance per
unit area
CD is the junction capacitance per
unit area
N is the number of transfers.
g
(4.27)
The noise source in the output MOSFET amplifier is the thermal
channel noise. This source will create fluctuations in the drain current
that can be referred back to the input as fluctuations in the number of
electrons on the input gate. It has been shown [54] that the rms carrier
fluctuation at the input can be expressed by


-116-
Figure 5.4
Amplitude attenuation of the transfer function
of a charge transfer device for different values
of the transfer inefficiency product N e.


CHAPTER 6
EXPERIMENTAL RESULTS AND DISCUSSION
6.1 Introduction
In this chapter, the experimental results of the optimum image sensor
will be presented. Since the bucket-brigade shift register constitutes a
very important part of the image sensor, a great deal of research effort
was undertaken to optimize its performance. The results of this research
were incorporated in the optimum device. In the following sections, the
experimental results of the BBD shift register and image sensor will be
discussed separately.
6.2 Experimental Results of the Bucket-Brigade Shift Register
In an effort to optimize the performance of the BBD register, the
validity of the transfer inefficiency model developed in Chapter 3 was
first proved experimentally. Based on the model, a selective ion implant
technique was then employed to improve the transfer efficiency which re
sulted in a high performance BBD register. The experimental data of this
high performance register will be analyzed, and its merits and disadvantages
will be discussed, as well as a proposed new BBD structure with improved
performance.
-119-


-54-
If T is not long enough to allow the charge transfer process to complete,
there will be always a finite quantity of charge left behind in the source
due to this intrinsic transfer rate limitation.
As mentioned in Section 3.2.2, when the gate voltage is V^, the
drain voltage V will be equal to (2V V ) when there is no signal
D (j i
charge. The drain voltage will decrease as the signal charge is trans
ferred into the drain node. The minimum drain voltage occurs when there
is a saturation charge in the channel. This drain voltage equals
Qg(Max)
VD (Min) = 2Vg VT -
(3.9)
2Vg VT -(VG VT)
G
From equation (3.9), it is clear that the IGFET is always operated in
the saturation region.
To derive the excess charge Q remaining in the source after time t,
we use the usual saturated current-voltage relation for the IGFET:
I = (V V V)2
2 ^ G s V
(3.10)
wi th
(3.11)
where p = electronic mobility in the inversion layer
n
Cqx = channel gate-oxide capacitance per cm'
W = channel width
L = channel length


-85-
re-establish the initial-voltage condition, one may obtain a signal
proportional to the incident illumination. The advantages of this mode
of operation are the improvement of responsivity resulting from integra
tion of the incident illumination and the capacity to control the
responsivity by varying the integration time.
The signal charge Qg obtained from the sensing diode at each sampling
time can be expressed as
Q
s
(I + I-)T.
p L i
(4.1)
where T^ is the total integration time, and I and 1^ are the photocurrent
and the leakage current respectively. The photocurrent I is related to
the incident power by
_ qApAP
p he
2
where A is the sensing diode area in cm
n is the quantum efficiency
X is the wavelength of the incident light
2
P is the incident power in watt/cm
h is the Plancks constant
c is the velocity of the incident light
(4.2)
It is obvious from equation (4.1) that if I >>IT, the signal charge
Qg will be proportional to the integration time T^, and, therefore, the
sensitivity will increase by increasing T^. However, at low light level
the contribution of the leakage current is no longer negligible. This
leakage current not only introduces shot noise, but also results in a
fixed-pattern noise due to the dark current non-uniformity in each


-99-
anti-blooming gate V in addition to the transfer gate 0 This anti-
cl D L
blooming gate is.biased at a DC potential which is below that of the
isolation barrier and transfer gate "low" barrier. When the signal
charge reaches the level set by the anti-blooming gate, the excess will
be sunk into the V j, thus preventing blooming. However, for an area
array, due to the limitation on center-to-center distance of the sensing
diodes, there is no space to implement the anti-blooming gate.
In this case, the anti-blooming function can be obtained by using
a video line reset switch LR as described in Chapter 2. The multiplex
switch 0_, "low" barrier is set below the isolation barrier between the
diodes; therefore, the excess signal charge will spill into the common
video line, instead of the adjacent diodes, and sink into the V ^ through
the line reset LR switch. Using the anti-blooming structure reduces the
blooming effect, but there are still two charge sources that will con
tribute to it. The first source is the variation of charge trapped on
the video line and sunk into V ^ through the LR switch after each "fill
and spill" process described in the previous section. With no excess
signal charge, the video line potential before and after the "fill and
spill" transfer process will be V(T.^ne) and V(Tfc) respectively, as ex
pressed by equation (4.15), where is one video line interval. The
charge lost from each transfer will be fixed amount, determined from
Qlt Cv IV(TUiie) V(Tt)] (4.21)
However, with excess signal charge leaking into the video line, the video
line potential before and after the "fill and spill" process will be
modulated. This will result in a reduction of the amount of charge lost,
which represents a gain of blooming signal at the output. In the extreme


-146-
Odd video
output
Even video
output
(a)
Combined video
output
Figure 6.15 Photograph of one line output. Vertical
scale 2 V/div., horizontal scale 20 ps/
div. .
(a) Video outputs from the odd and even
transport registers.
(b) Combined video output using a simple
adder.


I
H
4>
I
FRAME/FIELD INTERLINE
TRANSFER TRANSFER
Figure 2.5 Readout organization of CCD matrix
array.


-79-
where K is defined by equation (3.52). Without going through a two-
dimensional analysis, the field lines arising from the bulk charge can
be approximated as drawn in Figure 3.13. The field lines originating
from the fixed charge inside the trapezoidal region are terminated with
in the effective channel length (L £dep), whereas the field lines from
the fixed charge outside the trapezoidal region are terminated in the N+
islands. Based on this geometrical approximation, the total bulk charge
inside the trapezoid is
Q(L Jtdep) = qSA IL + L2 Met>
or = qN w
XB H A 2(L £aep)
(3.59)
(3.60)
where represents the average charge per unit area in the effective
B
channel length of (L £dep), where £dep is defined by equation (3.48).
The threshold voltage V at weak inversion (b = 1) now can be ex
pressed as
with
VT VFB + + Fb *
/ 2qN K e
/ A s o
(VDsat + 0F)
ox
_ (L + L £dep)
b 2(L £dep)
(3.61)
(3.62)
is the form factor for barrier modulation. In equation (3.61), the
source potential has been replaced by This is because at the end
of the charge transfer process, the subthreshold leakage current will de
cay twoard zero, and the source potential will reach (V^ V^) V
From Figure 3.13, the form factor can be calculated by straightfor
ward geometrical analysis:


^LT
<£y1
$ Y2
| I =gj k-TTO
*| HiTyp 30nsec *j tYL 30nsec 30nsec Figure 4.3 Optimum timing diagram to perform the "fill and spill"
function for improving the charge transfer efficiency
from the video line into the BBD shift register.


-128-
then during the clock transition there can be direct current injection
through the input capacitance into the first BBD bucket. This direct
current injection will cause nonlinearity as well as saturation in the
BBD channel. To prevent this, a separate narrow sampling pulse must be
used.
(2) The transfer inefficiency of a tetrode gate structure will be
reduced by a ratio of Cs/C^. For a high resistivity substrate, the source
capacitance Cg arises mainly from the overlap capacitances of the tetrode
gate and the transfer switch due to lateral diffusion. Therefore, the
C¡s/Cq ratio cannot be reduced by increasing the channel width, since
both Cs and will increase proportionally. To reduce the Cg/CD ratio,
the pitch distance of one shift register stage must be increased. This
is usually undesirable for high density integration.
(3) The boron sheet implant does not affect the performance of the
BBD register predicted by the barrier-height modulation model. This re
sults from the sheet implant representing a fixed surface charge Qgg which
does not enter into the expression of barrier-height modulation as shown
in equation (3.72).
(4) To obtain a BBD register with good transfer efficiency and
reasonable transfer speed, the substrate concentration must be much higher
113 3 16 3
than 1.7 x 101 cm It should be at least in the 10 cm range. How
ever, if such a low resistivity substrate is used for fabricating the BBD
register, the body effect [32] of the high substrate concentration will
make the peripheral circuits inoperable. Therefore, a selective ion- im
plant technique must be used in which only the regions under the tetrode
gates and transfer switches are implanted to minimize the barrier-height
modulation. Moreover, the implant must be driven into the silicon deep


-38-
3.2.2 Device Operation
The bucket-brigade device can be operated by either a two-phase
complementary, or non-overlapping clock. For simplicity, a two-phase
complementary clock changing from OV to V will be used to describe the
O
charge transfer from stage to stage. To begin, it is assumed that sev
eral cycles of the clock voltage have been applied. Referring to Figure
3.4, at t = t^ when the clock transition has just finished, the 0^ switch
will be turned off while the 0^ switch will be turned on. Node B will
be bootstrapped by the 0^ clock to a most positive reference potential
of V and become the drain of the 0. switch. Node A will be lowered to
c 2
a potential of Vg by the capacitive coupling of the 0^ clock. The mag
nitude of Vg will depend upon the amount of the signal charge. Node A
now becomes the source of the 0^ switch and the signal electrons will
flow through the 0£ channel into the drain node. As a result, the source
potential rises and the drain potential falls. Electron flow continues
until the source potential rises to (Vn V^) where V is the most pos-
itive voltage of the clock and is the threshold voltage of the
IGFET devices. At this point, the potential of the source is no longer
negative enough to inject electrons into the surface inversion layer,
and charge transfer ceases. The drain will maintain a potential of
[V -Q/(C+C.)] where Q is the signal charge. This is depicted in
c s j s
Figure 3.4 as t = t^.
At t = tj, the potentials of the clock lines are now reversed, and
the sources and drains reverse their roles. The new potentials differ
C C
from the old ones by (Vn x ;). The factor ( n ) represents the
o 0 t L. L t L #
3 3
voltage division of the clock voltage by the two series capacitances.
Therefore, the reference voltage can be expressed as


-42-
V
c
= V V + V X
G T G C + C.
= 2V_ V (if C C )
tr -I- J
(3.1)
(3.2)
The potential Vg at the source when the clock transition has just finished
(t = t^ or tg) can be approximated by
V = V
s c
s C
V x
C + C. G C +
C.
1
(3.3)
= V,
- vT-
(if C C.)
3
(3.4)
The charge that was previously transferred into a drain now finds itself
in another source, and so it again transfers one more stage toward the
output. If the input source island potential is held significantly posi
tive (higher than "V V ") there will be no new charge injected at the
input, and any internal charge is swept toward the output. When the
internal charge has all been removed, the N island potentials oscillate
between (V^ V^) (source potential) and (2V^ V^) (drain potential).
In the above analysis, the overlap capacitance of the IGFET gate to
the source island is assumed negligible. The formation of the N island
by light diffusion or ion implantation is intended to minimize this para
sitic capacitance.
The largest quantity of charge that can be transferred in the chan
nel is referred to as the charge handling capacity of the shift register.
The charge handling capacity can be obtained from equation (3.4) by
letting Vg = 0 which leads to
Qs (Max) = C (VG VT)
(3.5)
A larger charge would make Vg negative and forward bias the N island
and p-substrate junction and inject the signal charge into the substrate.


-75-
frequency is so low that the surface potential on the left of the barrier
equals the potential of the barrier as shown in Figures 3.9a and 3.9b.
These assumptions simplify the calculation because the amount of un
transferred charge is completely determined by the product of the barrier
potential and the capacitance of the region to the left of the barrier.
The objective then is to find the barrier potential as a function of
transferred charge. The transfer inefficiency can then be found from
^ _dn d(VG VT) dV,
'B dQ s dQ s dQ
(3.54)
where is the untransferred charge at the end of transfer, Qq is the
transferred charge. Cg is the capacitance of the source node, and
is the threshold voltage of the switch transistor T .
In conventional MOS theory, the threshold voltage of an IGFET is
simply obtained by applying the charge conservation principle to the
region bounded by the gate and bulk of the semiconductor and neglecting
any two-dimensional edge effects at the source and drain ends. This may
be written as [49]
% + qf + + 0 (3-55)
where is the charge on the gate, includes the fixed charge in the
SiC^, is the charge due to the free carriers in the surface inversion
layer, and QD is the fixed charge due to the ionized impurities in the
D
depletion region. For an N-channel IGFET, equation (3.55) may be ex
pressed in terms of voltages as [49]
VG VFB + S B +
/
(3.56)


BBD REGISTER
V,
buff
LT
I
o
I


-45-
subthreshold leakage current will be affected by the channel-length
modulation [30,44] of the FET switch due to the different drain potential
accompanying the various amounts of signal charge. Moreover, the thresh
old voltage of the FET switch is a function of the drain voltage due to
the ion-sharing effect at the drain junction [28,29,45]. This effect is
usually referred to as barrier-height modulation. As a result of these
channel-length and barrier-height modulations, there is a frequency-
independent component of transfer inefficiency which dominates at low
frequency.
While the intrinsic transfer rate and the channel-length and barrier-
height modulations contribute to the transfer inefficiency and provide the
major limitations to shift register performance, there are other perform
ance limiting effects which should be mentioned. Of these, perhaps the
most important one is that of interface states. With present day tech
nology, interface-state densities are so small that they are not normally
considered to affect significantly IGFET operation. However, in the case
of the bucket-brigade shift register, we are talking about transfer in-
-4
efficiency in the order of 10 ; therefore even a small density of interface
states can be important.
Only the interface states in the channel region of the IGFET can
affect bucket-brigade operation. Their effects are two-fold: one is
contributing generation current, and the other is trapping carriers dur
ing transfer and emitting them at some later time. Interface-state
generation current, in combination with bulk generation current associated
with the N island, will add to the signal charge in the storage capaci
tance. Given enough time, these generation currents will add enough
charge to overdrive the register. As a consequence, a low frequency or
minimum refresh time limitation will be introduced by the leakage current.


Vg>Vj
Figure 3.10 Cross-section of MOS transistor operating in saturation region.


-66-
Solving equation (3.31) with the initial condition V = 0 at t = 0, we
obtain
VT
V(t) = Jin
q
1 +
q Dn LgWt
kTL(VD)Cs
(3.32)
At the end of the charge transfer cycle, the charge trapped at the source
node is
kTC
Qi = -CV(0 f
£n
1 +
q Dn L Wt
M o B
kTL(Vn)C
D s
(3.33)
kTC
Jin
q Dn L Wt
H o B
kTLOOC
D s
(3.34)
where r is defined by equation (3.8). The approximation of (3.34) from
(3.33) is always true when the BBD is operated in the low frequency
range. The minus sign in front of equation (3.33) indicates that in
reality the charge is depleted instead of trapped.
The transfer inefficiency is then obtained by taking the derivative
of with respect to the charge Qq transferred,
dQ,
dQ
dQo dL(VD)
1 dL(V
X
dQ.
C kT
s
1 dL(V
q L(Vd) dQo
(3.35)
(3.36)
The transfer inefficiency in (3.36) depends only on how the channel length
is modulated by the charge Qq transferred into the drain node. The charge
Qq is related to the drain voltage by
V = 2V V
G x C
(3.37)


-136-
junctions, or they may be between these two types, depending on the sub
strate concentration, junction depth, and reverse-bias voltage [49,59].
It is found that the low frequency transfer inefficiency of the implanted
BBD register is in reasonable agreement with the barrier-height modulation
model if the linearly graded junction approximation is used in calculating
the depletion region depth. This observation is in agreement with Lees
model [45]. In this model a weighting factor is used in calculating the
lateral extension of the source and drain depletion region into the sub
strate at high substrate concentrations. This weighting factor corrects
for the deviation of the actual depletion profile from the one-sided
junction approximation. His experiments also show that the weighting
factor depends primarily on the substrate doping, and minimally on the
voltages. Therefore, it can be treated as a constant for a given sub
strate concentration.
Extensive numerical integration of Poisson's equation for diffused
junctions has been performed by Lawrence and Warner [59]. They obtained
a family of curves which describes the actual depletion profile of a dif
fused junction for various substrate dopings and junction depths. Wang
[60] used Laxvrence-Warner curves to determine a gradient constant for a
linearly graded junction and used this constant to calculate the depth
of the depletion region into the substrate, L due to reverse bias, V .
Wangs equation is
(6.1)
where the gradient constant, a, is expressed by equation (4.6). Using
this result and referring to figure 3.13, the parameters r^ and r^ can
be expressed by


-18-
2.3.1 Device Structure
The 100 x 100 diode matrix array to be fabricated and studied con
sists of six functional elements as shown in the schematic diagram of
Figure 2.7. These elements are:
(1) A 100 x 100 diode array matrix, schematically indicated by the
columns and rows of individual photodiodes. The diodes in each column
are connected one at a time through multiplex switches to a video line
which is common to all the diodes in that column. Parallel connection
of the multiplex switches simultaneously selects one diode from each
column. The diodes are operated in the charge storage mode [1]. When
a diode is selected by the multiplex switch, the potential of the diode
will be reset to a value of (V -V ), where V and represent the
clock high voltage and threshold voltage of the multiplex switch, re
spectively. The signal charge removed from the selected diode will be
transferred into an analog shift register through the common video line
for readout. After the multiplex switch is turned off, the diode starts
to integrate the photon-generated charge and its potential decays. The
total integration time of each diode is the time between two consecutive
readouts of the same diode. Figure 2.8 shows the potential diagram of
a diode before and after selection by the multiplex switch. This unique
structure makes possible a matrix array of photodiodes, each having only
a single multiplex switch, which provides frame storage. Furthermore,
the output capacitance is a single line and not the total number of pixels.
(2) A two-phase (2 0) dynamic shift register which controls the
multiplex switches. It turns on each row of diodes in sequence and
dumps the corresponding signal charge into the appropriate analog
shift register through each common video line, thus loading a complete


-63-
VG
Vd
(a)
CARRIER CONCENTRATION
TRANSFERRED
CHARGE
] L I*
(c)


-65-
Ug = surface band-bending normalized by kT/q
n. = intrinsic carrier concentration of silicon.
i
If Vpg >> kT/q which is the case in BBD operation, the term in the
brackets of equation (3.24) equals 1, and (3.24) reduces to
st
qDn L W
n o B
L(V )
(3.27)
As the current diffuses over the barrier into the drain, the potential
energy level at the source node starts to drop below the (V^ V^) level
as shown in Figure 3.9c. As a consequence, the carrier concentration at
the source edge also drops, as does also the diffusion current. From
equation (3.26), it can be seen that carrier concentration at the source
edge will decrease exponentially with reducing surface potential, there
fore
n (t) = n e
o o
-V(t)q/kT
(3.28)
and
TBt(t)
qDnoLBW V(t)q/kT
L(VD) e
(3.29)
The value of V gradually increases as current flows over the barrier ac
cording to
dV(t) = ^st^
dt C
(3.30)
Eliminating I (t) from (3.29) and (3.30), we obtain an equation which
can be solved for V(t).
dV(t) = qDnoLBW -V(t)q/kT n
dt l(vd)cs u


-91-
after each charge transfer the potential of the common video line will
increase with time which is depicted as V (t) in Figure 4.1a. From
Chapter 3, the subthreshold leakage current through the buffer gate can
be expressed as
qDn L W -V(t)q/
W* Tt- e
eff
(4.10)
where
V(t) = vv(t)
(V V )
v buff Tbuff'
L is the effective channel length of the buffer gate
eft
V __ is the threshold voltage of the buffer gate,
ibuf t
V(t) is the video line potential below the (V^ ^ ^buff^ level as
shown in Figure 4.1b. As the value of V(t) increases, the current de
creases exponentially toward zero.
The small signal "ON" resistance of the buffer gate, operated in
this subthreshold region, now can be obtained by
R =
dV LeffkT V(t)q/kT
= 0
dIst q^Dn L W
^ o B
(4.11)
From Chapter 3, the V(t) can be expressed by
2t
V(t) = In
q
kT n
- £n
q
1 +
q 'Dn L W
^ o B
kTL
eff v
q Dn L^W
t
kTL _.C
eff v J
(4.12)
(4.13)
where C is the video line capacitance. Substituting (4.13) into (4.11),
v
the small signal "ON" resistance now becomes
R =
t
C
v
(4.14)


-59-
Vbb vG
Figure 3.8
FET model for charge transfer efficiency
behavior of a tetrode bucket-brigade device.


-15-
in fabricating the field-induced photo-detector added as well as those
non-uniformities that are always present in the bulk silicon. Since the
reflectivity as well as the absorption depends on the relative thicknesses
of several films, a compromise must be made between spectral response,
quantum efficiency, and the non-uniformity [34], Normal process vari
ations make reproduction of consistent parameters over a period of time
somewhat more difficult than for the simpler diffused diode structure.
This problem is further aggravated by both the complexity of the required
process and its developmental nature, i.e., most CCD processes are not
high volume production processes; therefore, they lack the stability of
a standard production process.
The third structure to be discussed, shown as C in the figure, com
bines the field-induced photo-detector with the digital shift register
in an effort to obtain higher density with an existing technology. This
structure is employed in charge injection array as shown in Figure 2.6.
As initially conceived, this structure exhibited excessive uncontrolled
blooming, less sensitivity than the photodiode, spectral variations, ex
cessive non-uniformity, fixed patterns in the dark resulting from digital
sampling, and an extremely large output capacitance. Most of these dif
ficulties are now under control; however, the technology is no longer
standard requiring an exotic metal/silicon gate MOS process on an ex-
pitaxial substance [4-6,35]. Furthermore, a double sampling technique
must be used to process out the fixed-pattern noise resulting from the
sequential sampling of multiplex switches and the thermodynamic noise
associated with resetting the output capacitance. As a result of em
ploying this more complicated signal processing technique, the inherent
forms of signal contamination are eliminated, and good low level perform
ance is obtained.


-67-
This gives
e
D
kT 1_
q CD L(Vd)
dL(VD)
dV~
(3.38)
The last multiplier term in (3.38) represents the channel-length modula
tion for different drain voltages.
As mentioned previously in this section, a circulating charge is
always present in the channel, and the actual signal charge is (Q Qc)*
The actual signal charge trapped at the source can be calculated from
(3.34) which leads to
AQ .
sig
C kT
s
q
in
MVD )
(3.39)
c j
L(V ) and L(V ) represent the effective channel lengths when a charge
Do Dc
packet of Qq and are respectively present at the drain node. The
transfer inefficiency then can be expressed by
AQ
- = S1g =
D Q Q
C kT
s
q(Qo Qc>
Jin
L(Vd )
o
L(Vd )
(3.40)
L C J
To complete the calculation of transfer inefficiency, the multiplier
terms in (3.38) and (3.40) representing the channel-length modulation
have to be evaluated. The channel-length modulation is generally attrib
uted to the spreading of the depletion region near the drain which
results in a reduction of the channel length. Ihantola [48], Reddi and
Sah [44] calculated the extent of this spreading by describing the elec
tric field distribution using step p-n junction theory. However, it was
pointed out by Frohman-Bentchkowsky and Grove [30] that owing to the
presence of the gate electrode, the electric field in the drain depletion
region near the Si-SiO^ interface is greatly increased. A simple physical
model was presented by them which takes into account this increase in the


Page
4.3 Anti-Blooming Mechanism 96
4.4 Noise Analysis 101
4.4.1 Noise Sources Associated with the Sensing
Diodes 101
4.4.2 Noise Sources Associated with the Common
Video Lines 103
4.4.3 Noise Sources Associated with the BBD Shift
Register 104
5 DEVICE FABRICATION AND MEASUREMENT METHODS .... 108
5.1 Device Fabrication 108
5.2 Measurements 109
5.2.1 Barrier-Height Modulation Measurement 110
5.2.2 Bucket-Brigade Shift Register Transfer
Inefficiency Measurement 110
5.2.3 Optical-to-Electrical Transfer Characteristics
Measurement 115
5.2.4 Saturation Charge Measurement 115
6 EXPERIMENTAL RESULTS AND DISCUSSION 119
6.1 Introduction ..... 119
6.2 Experimental Results of the Bucket-Brigade Shift
Register 119
6.2.1 Experimental Verification of the Barrier-Height
Modulation Model 120
6.2.2 Experimental Verification of the Intrinsic
Transfer Rate Model 129
6.2.3 Improvement of Transfer Efficiency by Using
Selective Ion Implantation 131
6.2.4 A Proposed BBD Structure with Improved Perfor
mance 139
6.3 Experimental Results of the Image Sensor Performance 140
6.3.1 BBD Analog Shift Register 140
6.3.2 Image Test 144
6.3.3 Transfer Characteristics 149
6.3.4 Saturation Signal and Dark Current 151
6.3.5 Blooming Characteristic 154
6.3.6 Noise Performance and Dynamic Range 157
7 CONCLUSIONS 162
REFERENCES 164
BIOGRAPHICAL SKETCH
168


BIOGRAPHICAL SKETCH
Hsin-Fu Tseng was born in Hsinchu, Taiwan, in 1940. He received
the BSEE degree from Cheng-Kung University, Taiwan, in 1962, and MSEE
degree from the University of Florida, Gainesville, Florida, in 1970.
From 1971 to 1973, he worked towards his Ph.D. degree at the
University of Florida. From 1973 to 1975, he worked at Fairchild
Semiconductor Laboratories as a research engineer, and from 1975 to
1978, for Reticon Corporation as a device design engineer. In 1978,
he returned to the University of Florida to continue work on his
Ph.D. degree.
-168-


This dissertation was submitted to the Graduate Faculty of the College
of Engineering
fulfillment of
and to the Graduate Council, and was accepted as partial
the requirements for the degree of Doctor of.Philosophy.
March 1979
Dean, College of Engineering
Dean, Graduate School


Figure 2.7 Schematic diagram of the 100 x 100 photodiode
charge-transfer array.


-52-
examine the effects of each device parameter on its performance, and,
therefore, an optimum device can be designed for each specific applica
tion. In the following derivation, emphasis will be on the physical
process involved as well as the simplification of the model, and, there
fore, any model requiring two-dimensional numerical analysis will be
avoided.
3.5.1 Intrinsic Transfer Rate
The intrinsic transfer rate of the basic bucket-brigade device will
be first derived, and the result will be then extended to the tetrode gate
structure. In Figure 3.6, a single IGFET is shown, which will serve as
the basis for the modeling of charge transfer efficiency in the bucket-
brigade device [23-25].
This FET is merely one-half of one stage of a BBD shift register.
The junction capacitance (k between the N island and the p-substrate
has been neglected. This makes the storage capacitance C linear which
is not completely true, but is a good enough approximation for most of
the practical devices.
In Section 3.2.2, it was pointed out that during charge transfer,
the source potential V rises to (V VT) as the excess electronic charge
in the source transfer to the drain. At the same time, the rate of charge
transfer must go to near zero. However, this charge transfer process re
quires a certain amount of time. If the bucket-brigade is to operate at
a clock frequency of f^, then the maximum time x allocated for each charge
transfer is
t =
2f
(3.8)


TABLE OF CONTENTS
Page
ACKNOWLEDGEMENTS ii
ABSTRACT v
CHAPTER
1 INTRODUCTION 1
2 OPTIMIZATION OF A SOLID-STATE IMAGE SENSOR 5
2.1 Introduction 5
2.2 The Architecture of A Solid-State Image Sensor., .... 5
2.3 Device Structure to Realize the Optimum Architecture. 17
2.3.1 Device Structure 18
2.3.2 Device Operation 26
3 ANALYSIS OF THE BUCKET-BRIGADE SHIFT REGISTER. ....... 31
3.1 Introduction 31
3.2 Device Structure and Operation 35
3.2.1 Device Structure 35
3.2.2 Device Operation 38
3.2.3 Input and Output Structures. . 43
3.3 Performance Limitations 43
3.4 Tetrode Structure Bucket-Brigade Device 46
3.5 Derivation of Transfer Inefficiency Model 51
3.5.1 Intrinsic Transfer Rate 52
3.5.2 Transfer Inefficiency Due to Subthreshold
Leakage of the IGFETS 61
3.5.3 Transfer Inefficiency Due to Barrier-Height
Modulation 73
4 ANALYSIS OF THE OPERATING MECHANISMS AND NOISE LIMITATIONS
OF THE OPTIMUM IMAGE SENSOR 84
4.1 Charge-Storage Operation of a Photodiode 84
4.2 Sensing Diode to BBD Analog Register Charge-Transfer
Mechanism 88
iii


-163-
operation of the bucket-brigade device have been developed. The accuracy
of these models has been corroborated by experiments. Based on these
models, a selective ion implant technique has been employed to minimize
the barrier-height modulation of the transfer gate, and this resulted in
a high performance bucket-brigade register. To further improve the per
formance of the bucket-brigade register, a new structure has been proposed.


-76-
where 0g is the surface potential with respect to the substrate. By
using the commonly used criterion for surface inversion, the expression
for the threshold voltage is [42,49]
VT VFB + b|aF VCX (3-57>
where 0 is the bulk Fermi potential and b is the band-bending parameter
r
which determines the degree of inversion. The effect of the bulk charge
Q_ in equation (3.57) is to increase the magnitude of the threshold volt-
D
age. However, due to the two-dimensional edge effect, the full effect
of Q on the threshold voltage is decreased when the channel length is
reduced and becomes comparable to the junction depth of the source and
drain. As the distance between the source and drain decreases, the in
fluence of the source and drain on the electrostatic potential distribution
under the gate increases. In contrast to the conventional long-channel
theory, a large fraction of the field lines originating from the bulk
charge under the gate are terminated on the source and drain islands,
causing the threshold voltage to be lower than what is predicted by
equation (3.57). This ion-sharing effect near the ends of the channel
results in a dependence of threshold voltage on the channel length and
on the drain voltage [28,29,45].
To analyze the dependence of threshold voltage on the channel length
and drain voltage requires a two-dimensional numerical analysis of the
IGFET [50,51], However, many one-dimensional models which take into
account the two-dimensional field distribution have been reported.
Cheney and Kotch [52] first modified the threshold voltage expression
for the case of a large substrate bias by including the effect of the
depth of the source and drain diffusion. This results in a correction


(3b)


-58-
the condition of (3.20) for f = 0.5.MHz gives the signal charge left
behind of 0.0001 pc, which corresponds to 0.006% of the signal charge
which is now (2.A 0.8) = 1.6 pc.
Equation (3.19) now can be.modified to accommodate the introduction
of the circulating charge and actual transfer efficiency measurement
scheme which will be discussed in a later chapter. Equation (3.16) can
be expanded in a binominal series valid for most cases of practical in
terest to get
2 2 4
4f C 16f C
Q(t) = § $ for BQ 4f CT
3 B2Q o c
(3.21)
With a circulating charge of Qc and a charge packet of Qq, the actual
signal charge left behind will be
AQo -
2 4
16f C /,
c II
B
,Q Q
v c o
(3.22)
The average transfer inefficiency is then
e(-r) =
AQ
16f 2C4
Qo Qc B2Q Q
o c
(3.23)
Comparing (3.23) with (3.19), it can be seen that (3.19) is the small
signal limit [24] of (3.23), which represents [AQq/(Qo Qc)] (Qq -* Q£) .
From (3.23), it is also clear that the transfer inefficiency can be mini
mized when both Qq and Qc are made as large as possible and that through
the clock frequency dependence of c(t) the intrinsic transfer rate will
provide an upper limitation to the operation of the bucket-brigade device.
To extend the result of the transfer inefficiency derived above for
the tetrode gate bucket-brigade structure, we use the model shown in
Figure 3.8, which represents one half stage of the tetrode BBD. As men
tioned in Section 3.4, the junction capacitance is much smaller than the


-120-
6.2.1 Experimental Verification f the Barrier-Height Modulation Model
As discussed in Chapter 3, the mechanisms that cause transfer in
efficiency of BBD registers at low frequencies are subthreshold leakage
current and barrier-height modulation. Their theoretical contributions
to the transfer inefficiency are displayed in Figure 3.12 and 3.14. It is
obvious from these two figures that the transfer inefficiency due to the
subthreshold leakage current is negligible compared with that due to the
barrier-height modulation in the substrate concentration range of our
interest. Therefore, it is assumed that the low frequency transfer in
efficiency is mainly due to the barrier-height modulation, and the
experimental results will be compared with the model described in Section
3.5.3.
Test transistors of different channel lengths were first fabricated
14 15
on two substrates with carrier concentrations of 6 x 10 and 1.7 x 10
-3
cm Accompanying each group of test transistors, was a long channel
reference transistor with an effective channel length of 64 ym as shown
in Figure 6.1. The threshold variation due to short channel effects is
negligible for this reference transistor. The threshold variation of
the test transistor can then be accurately obtained by subtracting the
measured barrier potential of the reference transistor from that of the
test transistor, thus cancelling flat-band voltage variations due to
process fluctuations.
The agreement between the experimental data and the barrier-height
modulation model developed in Chapter 3 is quite good. Figures 6.2 and
6.3 display some of these results. Figure 6.2 shows the barrier-height
modulation of a test transistor with effective channel length of 8 ym.
14 -3
The substrate concentration was 6 x 10 cm and the junction radius


-22-
tines the transport clock frequency, and generates a full-wave sample-
and-hold output; it also halves the number of charge transfers. This is
very important in realizing long arrays when the total amount of charge
loss and transfer noise limits the performance of the device.
As will be discussed in Chapter 3, the bucket-brigade device offers
certain advantages over the charge-coupled device, such as greater com
patibility with standard MOS technology and ease of interfacing with
the peripheral circuitry. However, the bucket-brigade shift register
has received much less attention than the charge-coupled device. In an
attempt to remedy this, the BBD shift register instead of the CCD regis
ter is discussed in this study. It is hoped that a better understanding
of the performance limitations of the BBD shift register can be obtained,
and a design formulation can be established.
(4) A video line reset switch LR, a transfer switch LT and a buffer
gate The reset switch LR provides a reference bias for all the
video lines while all the sensor diodes are integrating signal charges.
All the charges collected on stray capacitances along the video lines
and all the excess signal charges leaked from the sensor diodes are
drained into the sink voltage V through operation of the LR gate.
Therefore, LR functions as an anti-blooming and anti-crosstalk gate.
Prior to the moment when the dynamic register is to select another row
of diodes, the LR gate is turned off and the transfer gate is turned on
to the same reference level set by LR. This makes conditions ready for
the signal charge from the next row to be transferred into the BBD re
gisters. The LR and LT control clocks are complements of one another.
Note also that, just prior to transfer, the BBD is empty of signal
charges, it contains only fat-zero reference charges so that the new


-82-
substrate concentration is uniform, the one-sided junction approximation
is valid, and that the channel length is long enough so that the source
and drain depletion regions do not meet under the gate. Any deviation
from these assumptions will cause errors and Affect the accuracy of this
model. In Figure 3.14, the theoretical values of are plotted as a
function of channel length for different substrate concentrations N^.
In Chapter 6, the models discussed in this chapter will be compared with
experimental results.


-71-
OXIDE -SEMICONDUCTOR
Figure 3.11 The electric field distribution for MOS
device operation in saturation.


PERCENT BLOOMING
Figure 6.22 Blooming characteristic of the
optimal image sensor.


-61-
3.5.2 Transfer Inefficiency Due to Subthreshold Leakage of the IGFETS
As discussed previously, at the end of a charge transfer the source
will rise to a potential of nearly (V V ). However, due to thermal
(j 1
diffusion of the charge carriers from the source region into the drain
region, the channel current of the IGFET does not suddenly drop to zero.
Rather, it diminishes exponentially with decreasing gate-to-source volt
age. The effect of this subthreshold leakage current on the transfer
inefficiency of the BBD will be considered in this section.
Figure 3.9a shows the FET model to be used in the subthreshold leak
age current analysis. Cg represents the capacitance at the source node.
In the basic BBD structure, this is the storage capacitance; however,in
the tetrode BBD, this is the junction capacitance of the N+ island between
the tetrode and switch gates which is depicted as in Figure 3.8.
represents the capacitance at the drain node which is the storage capac
itance for both the basic and tetrode structures. It is assumed that
enough time has elapsed to allow the charge at the source node to transfer
into the drain node and the source potential reaches (V^ V^) as shown
in Figure 3.9b. Once this condition is reached, current enters the channel
barrier region only by diffusion.
The objective of this analysis will be to find the amount of charge
trapped on the left of the barrier at the end of the charge transfer
cycle. The amount of this charge will be found as a function of the
charge transferred, Qq. The charge transfer inefficiency due to this
subthreshold leakage current is then dQ^/dQQ as before.
To find this relationship, consider Figure 3.9b. Assuming the
carrier concentration at the left edge of the barrier is nQ, then the
diffusion current across the barrier can be expressed [41] as


Q (t) pc
-57-
1
0.01
0.1
1.0
10
100
fc (MHz)
Figure 3.7
Charge left behind as a function of clock frequency
for two different initial charges, Q as described
by equation (3.16).


-161-
From the above noise measurement, it is obvious that without using
any signal-processing techniques, this image sensor can provide a useful
dynamic range of better than 600 to 1.


-50-
(jfc-l VBB <£2 VBB <£, VBB
I
p
C
p
c
>
c
p
c
>
o
Trs =
Lc
Trt
=c
-C _
1I
11 .
. 1l
. r~L_
p 11
, r~
=Cj
-Cy
:C)
-Cy -
=C]
(5e)


-158-
Figure
6.23 Fixed-pattern across one line in
the dark. Vertical scale 50 mV/
div., horizontal scale 2 ps/div.


Figure 4.1
(a) Equivalent circuit for charge transfer between the sensing diode
and BBD shift register.
(b) Potential at each node before charge transfer.


-9-
(2) full spectral response extending from 0.2 pm to 1.1 pm; and
(3) a relatively smooth spectral response not subject to process
variations.
Having now detected internally the absorption of a photon, it is
necessary that this information be made available at a terminal. Here
lies another of the principal differences in the design of solid-state
image sensors. Figure 2.3 shows schematically two approaches used to
interrogate and read out the individual picture elements of an image
sensor. Each approach uses a shift register to read out the information
stored on each individual photosensitive element or pixel. In the first
case a digital shift register is used to sequentially access a transfer
switch which connects individual pixels in turn to a common terminal.
This approach has the definite advantage that digital shift registers
and multiplex switches have been highly developed, use standard MOS pro
cesses and are relatively easy to implement. The performance of this
readout technique is dependent on both the total number of multiplex
switches and on the uniformity of the multiplexing function, i.e., ideally
each multiplex switch and its drive should be identical. Non-uniform
multiplexing results in a fixed-pattern modulation which is superimposed
on the video information from the pixels. Differential signal processing
techniques have recently been incorporated which have reduced the fixed-
pattern component to a negligible level. The fixed pattern has been re
duced to the point where the total number of multiplex switches is now
of practical significance. The random noise depends directly on the
size of the output capacitance which in turn is a function of the number
of multiplex switches connected to the output line. In the majority of
applications, particularly those for which the solid-state image sensor


TRANSFER INEFFICIENCY
Figure 3.12 Theoretical transfer inefficiency due to subthreshold leakage current
as a function of channel length for different substrate concentrations


STUDY OF THE OPTIMUM CHARGE-TRANSFER
IMAGE SENSOR
By
Hsin-Fu Tseng
A DISSERTATION PRESENTED TO THE GRADUATE COUNCIL OF
THE UNIVERSITY OF FLORIDA
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE
DEGREE OF DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA


-68-
electric field. Good agreement between the model and output conductance
measurements throughout a very wide range of device parameters was ob
served; as a result, this model is widely adopted in many modern computer
circuit simulation programs.
Although this model is developed for the IGFET under strong inversion
to account for the dynamic drain conductance, it can be extended into the
weak inversion region with a slight modification of the definition of the
drain saturation voltage V afc. According to conventional theory, an
IGFET device operates in the saturation region when the drain voltage is
increased to a value such that the inversion condition at the end of the
channel near the drain can no longer be maintained by the applied gate
voltage. The drain voltage at the onset of saturation is denoted by
^Dsat anC^ Can exPressed in terms of device parameters and applied
gate voltage.
= V - 20 +
Dsat G FB r
K e qN
s o A
ox
1 /I +
2C (V V^)
ox v G FB
K e qN.
s o^ A
(3.41)
where
V = "flat-band" voltage of the IGFET
r B
0 = Fermi potential of the substrate,
r
Any further increase of drain voltage beyond this value is then pictured
to result in the formation of a depleted region of length £dep between
drain and channel as shown in Figure 3.10. This is equivalent to assum
ing that the voltage at the end of the channel which corresponds to the
edge of the depletion is VDsat_. In weak inversion operation, there is


-102-
TRC
Figure 4.5 Johnson-Nyquist noise of RC circuit.


LOW FREQUENCY TRANSFER INEFFICIENCY
Figure 6.10 Low frequency transfer inefficiency as a function
of channel length for the implanted BBD. The
theoretical values were calculated using a linearly-
graded junction approximation.


-51-
by the modulation is much larger. The tetrode gate has no effect in
suppressing the barrier modulation with this bias level. In Figure 3.5d,
the tetrode gate is much lower than the phase driver voltage. This re
sults in low signal-handling capacity and reduced operating speed.
When the tetrode gate bias V__ is lower than the clock voltage Yn,
BB b
the charge-handling capacity becomes
Qs (Max) = C(VBB VT) (3.7)
with V too low, the charge-handling capacity is greatly reduced. Since
the capacitance C is very small, the node voltage will quickly dis
charge to a threshold below the gate voltage of 0^. The limiting process
for speed of the transfer is the discharge of the large storage capaci
tance C through the tetrode transistor T Lowering of VBB bias will
effectively reduce the transconductance of the tetrode transistor and
consequently decrease the operating speed. It is also apparent that the
tetrode transistor will not suffer any barrier-height and channel-length
modulation, since the potential of V will never be much different from
a threshold below the 0^ voltage when 0£ clock is high. Therefore, the
high-frequency component of transfer inefficiency due to dynamic drain
conductance is negligible when the tetrode structure is used.
3.5 Derivation of Transfer Inefficiency Model
In this section, the three mechanisms, namely intrinsic transfer
rate, channel-length modulation, and barrier-height modulation; which
limit the performance of the bucket-brigade device, will be discussed
in detail. Analytical equations will be formulated to allow one to


TRANSFER EFFICIENCY (%)
Os/Cv (V)
Figure 4.2 The worst-case charge transfer efficiency
between the sensing diode and BBD shift
register as a function of signal level.


-115-
out
A.
xn
exp [-N e(l cos 2 irf/f )]
g c
(5.4)
where f is the signal frequency and f is the clock frequency of the shift
register. Equation (5.4) is displayed in Figure 5.4 for various values
of the inefficiency product.
The amplitude attenuation at the output can be measured using the
Tektronix scope or the spectrum analyzer. However, if the spectrum analy
zer is used, the amplitude attenuation due to normal sin X/X sampling loss
[58] must be taken into account.
5.2.3 Optical-to-Electfical Transfer Characteristics Measurement
Figure 5.5 shows the test setup for measuring the optical-to-electrical
transfer characteristics of the image sensor. .The light source is a tung
sten lamp at a fixed temperature. The light intensity is adjusted using
neutral density filters. The incident light is passed through a beam
splitter. Half of the radiant energy falls on the image sensor under test
through a mask which creates the desired image pattern. The other half of
the radiant energy is directed into a calibrated PIN diode for measuring
the incident power. For spectral response measurement, the tungsten lamp
is replaced by a monochromator.
5.2.4 Saturation Charge Measurement
To measure the saturation charge of the image sensor, the device
under test is placed in complete darkness. The DC current flowing into
the reset drain terminal of the output charge integrator is measured.
This current represents the fat-zero charge and dark leakage current.


Figure 3.9 (a) FET model for derivation of transfer
inefficiency due to subthreshold leakag
current.
(b) Surface potential of an ideal FET with
no subthreshold leakage current. Also
shown are the trapped and transferred
charges.
(c) Actual surface potential and charge
transfer during the part of the cycle
devoted to subthreshold leakage current


-2-
Recently a new structure which combines the advantages of each of
these image sensors has been reported by Tseng and Weckler [18-20]. This
new structure employs photodiodes for signal detection and a low noise
charge-transfer analog shift register for readout. This combination to
gether with a built-in anti-blooming structure results in an optimum
image sensor. The optimum sensor possesses all the desired characteris
tics such as minimum fixed-pattern noise, high dynamic range, smooth and
broad spectral response, high quantum efficiency, uniform sensitivity,
immunity to overload blooming, and versatility of operation. It is im
portant and highly desirable that such a solid-state image sensor be
developed and studied.
In this dissertation, the operating mechanism and performance limi
tations of a matrix charge-transfer image sensor having optimal charac
teristics are investigated. This image sensor consists of 10,000
photodiodes arranged in 100 columns and 100 rows. Each row of diodes
is selected in sequence by a scanning digital register, and the signal
charges are transferred in parallel into two tetrode bucket-brigade
analog registers [21-27] for readout. Since the analog shift register
constitutes a very important part of the imaging device, a large segment
of this research effort was devoted to the modeling and study of the BBD
analog register.
In Chapter 2, the building blocks of the common image sensors are
reviewed, and the new architecture which results in the optimal solid-
state image sensor is discussed in detail. The organization and operation
of the matrix array which realizes the optimal architecture is described.
In Chapter 3, the operation and performance limitations of the basic
and improved tetrode bucket-brigade devices are analyzed, and models


Figure 3.3 (a) Integrated-circuit version of an N-channel IGFET
bucket-brigade shift register.
(b) Equivalent circuit and two output sensing schemes.


-124-
was 1.3 pm. The solid line represents the theoretical values, and the
circles and triangles are the measured values for two gate voltages of
6 V and 7.5 V respectively. Figure 6.3 shows the barrier-height modulation
of two test transistors fabricated on a substrate concentration of 1.7 x
15 -3
10 cm The junction radius was 1.5 pm. The two transistors were
biased at a fixed gate voltage of 9 V. Again, the solid line represents
the theoretical values, and the circles and triangles are the measured
values for the two transistors with effective channel lengths of 5 pm
and 7 pm respectively. It is evident that the fit between the measure
ments and calculations is very good.
Several test BBD shift registers were also fabricated on the two
substrates used for the test transistors. The shift registers fabricated
15-3
on the 1.7 x 10 cm substrate were 256 stages long with a gate oxide
o 14 -3
thickness of 1100A. The shift registers fabricated on the 6 x 10 cm
substrate were 64 stages long. There were two types of registers on the
low carrier-concentration substrate, one with a gate oxide thickness of
O O
750A, and the other with a gate oxide thickness of 1000A and a sheet
boron implant to adjust its threshold voltage. All of the registers had
a tetrode gate structure.
The experimental results of the low-frequency transfer inefficiency
for the test BBD registers are displayed in Figure 6.4, The theoretical
values calculated from the barrier-height modulation model are also shown
in the figure. It is clear that the fit between the theoretical and ex
perimental data is.very good. Although all the test registers had a
tetrode gate, the measured transfer inefficiency e is normalized to the
condition of Cg/CD = 1, which corresponds to the normal BBD structure
without the tetrode gate. This can be obtained by measuring the transfer


-25-
charge from saturating the analog shift register, it must be minimized
by either minimizing AV^ or C^.
The second problem caused by the threshold variation is the intro
duction of fixed-pattern noise due to a different AV^, for each video line.
As can be seen from equation (2.2), with a different AV^ for each video
line, there will be a different Q^, which results in a fixed-pattern
noise on the output signal.
To minimize both the and the fixed-pattern noise, a buffer gate
V, is introduced in front of the LR and LT switches. This buffer
buff
gate is biased at a DC potential below the LR. and LT "high" potential.
The function of this buffer gate is to isolate the video line capacitance
Cg from being affected by the AV^ and AV^ shown in equation (2.2), and to
minimize as well as the fixed-pattern noise. Its effect is very simi
lar to that of the tetrode gate in the BED shift register to be discussed
in the following chapter. With the introduction of this buffer gate,
equation (2.2) is revised to
Qf = (AVG AVt) (2.3)
where C_. is the junction capacitance of the N+ diffusion between the LR
and LT switches. This C. is much smaller than C and results in a great
3 s
reduction of and fixed-pattern noise.
(5) Interlacing switches denoted as LO and LE gates. These gates
allow the device to operate in an interlacing mode when driven by a set
of two-phase clocks running at the field rate. For the non-interlacing
mode, these gates are tied to a fixed voltage, and the rows are accessed
sequentially, with each odd line followed by an even line. For the


-101-
4.4 Noise Analysis
The noise sources in the optimum image sensor can be divided into
three groups according to their association with different functional
elements, namely those associated with the sensing diode, the common
video line, and the BBD shift register.
4.4.1 Noise Sources Associated With the Sensing Diodes
There are two noise sources associated with the sensing diodes.
One is the Johnson-Nyquist noise of the multiplex switches. An MOS
switch has a finite resistance to the flow of charge carriers. This
electrical resistance defines the fluctuation of charge across the
storage capacitance C. .To illustrate this effect we consider a series
RC circuit as shown in Figure 4.5 with an ideal switch, its equivalent
resistance R, and the noise voltage generator, V associated xvith it.
The noise voltage across the capacitor can be derived from [54]
V
2kTR
nc
f
dm
2 2 2
1 + w R C
kT
C
(4.23)
which at room temperature converts to a rms noise electron value of
N = (kTC)^ = 400 (C _)3s
n q pf
(4.24)
where C ^ is the capacitance of the storage capacitor in picofarads.
It is obvious from equation (4.24) that the rms noise electron value
depends only on the size of the capacitor and is independent of the re
sistance value. Therefore, it is often referred to as kTC noise in
charge-transer and image-sensing devices.
The other noise source in the sensing diode is the dark current shot
noise. The fluctuations in the generation of dark current are random,


-80-
L =
L, =
L =
r =
r =
L - by, £dep
(rx2 W2)% rj
(r*" VT) 2 r:. £dep
^ J
r. + A(y,. + vn \)
j bx Dsat
r. + /K(Vb. + Vc)
(3.63)
(3.64)
(3.65)
(3.66)
(3.67)
W /K(VDsat + V
(3.68)
where V, is the build-in voltage of the N+ junction. Combining (3.62)-
bi
(3.68) we obtain
-[
L! + l2
2(L £dep)
L = I r/ + 2r. /K(V. . + Vn ') + K(V, 0_)
1 I j j bi Dsat bi F
-IS
(3.69)
(3.70)
L2 =
r. + 2r. /VV + K(Vd + Vb - 0p) 2
- (r^ + £dep) (3.71)
From equations (3.37), (3.54) and (3.61), the transfer inefficiency due
to barrier modulation e now can be expressed as
B
X
2qNAK e
-s-- (V + 0 )
2 'Dsat V
ox
1 + F,
qN,K e
Aso
2C (Vn + 0V)
ox Dsat F
-1 dF
x
dVT
(3.72)
dVT
/t A ^2 T d£dep
(L £dep) + L
D D
2(L £dep)2
(3.73)


Figure 3.4 Operation of BBD shift register:
(a) Equivalent circuit of one-and-
one-half-stage shift register.
(b) Clocks to drive the shift register.
(c) Potential of each node at different
time cycles.


-64-
st
qDn L W
_ o B
L(V.
D
y- [l exp (-VDSq/kT)J
where
B
./
K e kT
s o
2NAq
is the extrinsic Debye length
(3.24)
(3.25)
and
q = electron charge
D = electron diffusion constant
N, = substrate concentration
A
k = Boltzmann's constant
T = temperature in degrees Kelvin
V = drain-to-source potential
K = dielectric constant of silicon
s
= permitivity of free space
L(V^) = effective channel-length as a function of the
drain voltage due to channel-length modulation.
The equilibrium minority-carrier concentration nQ at the edge of
the source is a function of the surface potential at the source, and can
be expressed [41] as
exp [ (b 1)U ] 1
n = n- (3.26)
[2(Ugx + bUF 1)]* 1
where
U = source-to-substrate voltage normalized by kT/q
SX Na
Up = Jin the bulk Fermi potential normalized by kT/q
i
Us
b = the band-bending parameter (b = 2 at strong
F inversion, b = 1 at weak inversion)


-122-
VD (V)
Figure 6.2 Barrier-height modulation as a function of
drain voltage for a test MOSFET.


Figure 3.5 Tetrode bucket-brigade device:
(a) Actual device structure in integrated-circuit
form.
(b) Tetrode gate correctly biased. The charge
loss due to barrier-height modulation is
minimized.
(c) Tetrode gate biased too high, no effect in
suppressing the barrier-height modulation.
(d) Tetrode gate biased too low, reducing the
speed and charge handling capacity.
(e) Equivalent circuit.


-149-
the entire frame was reset by pulsing the FR switch, the dynamic scan
register started to read out the video signal from the first line. Since
the integration time of each line increases linearly as the scan register
propagates through the entire frame, the output is a linear ramp. This
frame reset is intended to capture a pulsed image, such as encountered
in explosion studies.
6.3.3 Transfer Characteristics
The transfer characteristics of the array are determined by measur
ing the response to different irradiance levels. The light source is a
2870K tungsten lamp, measured using a detector with flat response and
a 370 to 1040 nm bandwidth. Array response usually follows the form
Y
V = KE where V is the output signal, K is a constant, and E is the
s s
input energy. When plotted on log-log paper, this equation becomes a
straight line with a slope of gamma (y).
Figure 6.18 shows a irregular transfer characteristic when the line
reset LR and line transfer LT gates were improperly clocked. This trans
fer characteristic was obtained under the following conditions:
0 to 15 V
V.
BB
14 V DC
V.
buff
12.5 V DC
LT
0 to 14.5 V
LR
0 to 14.7 V
Source followers R^
Integration time T^
Transfer time T
4 kfi
18 ms


-17-
The final structure to be assembled from the set of building blocks
is shown in the figure as D. This structure uses photodiodes with all
their inherent advantages, i.e., spectral purity, high-external quantum
efficiency, combined with an analog shift register for readout. This
combination possesses all the advantages of the photodiode detector with
those of the analog shift register readout. In the following section we
will describe the practical realization of array employing this architec
ture. For lack of a more descriptive acronym, let us refer to this
architecture as the optimum solid-state image sensor.
2.3 Device Structure to Realize the Optimum Architecture
Solid-state image sensors can be divided into two groups: linear
image sensors and area image sensors. Linear sensors consist of a single
row of photosensitive elements and thus can be used to monitor a one
dimensional variable. In order to obtain a two-dimensional picture from
a line sensor, the other dimension has to be scanned mechanically. For
high speed scanning of a two-dimensional picture such as standard broad
cast television, an electronically scanned area array which contains rows
and columns of photosensitive elements must be used. In the present
study, only a 100 by 100 area array image sensor will be fabricated and
investigated, since, in principle, the linear array is a simplified form
of a matrix array. Any results obtained from this study then will also
be applicable to the linear image sensor.


TRANSFER INEFFICIENCY
-130-
CLOCK FREQUENCY (Mz)
Figure 6.6 Transfer inefficiency as a function of
clock frequency for a BBD shift register
with C = 1.7 x 10-*-^ cm~3> tetrode gate
W/L = 18/15, transfer gate W/L = 18/7.


-157-
6.3.6 Noise Performance and Dynamic Range
The noise performance of the matrix array is displayed in Figures
6.23 and 6.24. Figure 6.23 shows the fixed-pattern noise across one line
in the dark. The device was running at a data rate of 5 MHz and an in
tegration time of near 2 ms. Therefore, the contribution to the
fixed-pattern noise due to the dark current is negligible. The vertical
scale is 50 mV per division. The measured fixed pattern is better than
5 mV which corresponds to a dynamic range of better than 600 to 1 with
a saturation voltage of 3 V.
Figure 6.24 shows the spectral response of the thermodynamic noise.
The clock rate of the transport analog register was 500 KHz. The com
bined output from the two analog registers was filtered before going into
the spectrum analyzer. The bandwidth of the filter and spectrum analyzer
were 200 KHz and 100 Hz respectively. The solid line on the top repre
sents a reference voltage of IV at the output. This voltage was obtained
by feeding a sinusoidal signal to the fat-zero input port of the analog
register. The attenuation at higher frequencies is due to the frequency
response of the low-pass filter. The noise output on the upper trace is
that of the device in the dark, while the bottom trace is that of the
measurement system.
The difference between the reference voltage and the device noise
is about 88 DB. This corresponds to a rms noise voltage of about 40 pV.
Using a noise bandwidth equal to the Nyquist frequency of the clock, and
saturation output of 3 V, this noise voltage converts to a dynamic range
of 1500 to 1. This result is very close to the theoretical limit of
2000 to 1.


-131-
Figure 6.13 shows the same measurement for a BBD register fabricated on
15 -3
a substrate also with a carrier concentration of 1.7 x 10 cm How
ever, the regions under the tetrode and switch transistor gates were
selectively implanted. This is the final shift register that was inte
grated into the image sensor. The details of this shift register will
be discussed later; however, it is clear that the fit between the
theoretical and experimental transfer rate is also excellent. This re
gister has a tetrode gate 6 parameter nearly two times that of the switch
transistor.
6.2.3 Improvement of Transfer Efficiency by Using Selective Ion
Implantation
The substrate concentration of the starting material used in this
15 -3
fabrication process was 1.7 x 10 cm The regions under the switch
transistors and tetrode gates were implanted with boron before the field
oxidation step. The rest of the process steps were similar to that of
the previous devices. The boron implant was driven-in during the sub
sequent high temperature process steps, i.e., field oxidation, gate-oxide
growth, and gettering etc. The final substrate concentration profile of
the boron implant was first calculated using a process simulation program
SUPREM developed by Stanford University, and then experimentally verified
by measuring the threshold voltage of a test transistor as a function of
substrate bias. The results are shown in Figures 6.7 and 6.8.
Figure 6.7 shows the computer plot of the calculated final substrate
concentration as a function of distance from the SiO^ Si interface.
The 0.0 on the vertical scale represents the interface. The negative and
positive directions from this interface represent the SO2 and Si


-140-
A BBD register employed these structures is displayed in Figure
6.11. The tetrode gate is formed by the first layer of polysilicon, while
the transfer switch uses the second layer which overlaps the tetrode gate.
The storage capacitance is formed by the two layers of polysilicon de
posited on top of the field oxide. The top plate of the storage capacitor
and the transfer gate are a continuous piece of polysilicon, and the bottom
plate of the capacitor is connected to the BBD channel by a butting contact.
The advantages of this proposed BBD structure are numerous:
(1) High transfer efficiency over a wide frequency range due to
the elimination of C .
s
(2) Low dark current due to the elimination of the p-n junction
underneath the MOS capacitance.
(3) Shorter length per stage due to the removal of the N*" island.
(4) Elimination of the disadvantages caused by ion implant as
discussed in the previous section.
6.3 Experimental Results of the Image Sensor Performance
Figure 6.12 shows a photograph of the optimum image sensor which
incorporates two implanted BBD shift registers. The chip measures 279 x
2
282 mil The test results of the image sensor performance are discussed
in the following paragraphs.
6.3.1 BBD Analog Shift Register
Figure 6.13 shows the characteristics of the BBD register which was
integrated on the image sensor device. Using the results of the study
discussed in the previous section, this register was optimized for high


-148-
Figure 6.17 Output of a frame using the frame reset,
FR, switch. The array was illuminated
with a continuous uniform light, there
fore, the output was a linear ramp.


-133-
yvSB + j6f Figure 6.8 Threshold voltage as a function of substrate bias
for the implanted transistor. Constant slope re
presents a uniform substrate concentration.


CLOCK
CLOCK
i
ro
I
Figure 2.4 Four basic architectures of a solid-state image sensor.


-23-
transfer is unaffected by prior data.
Ideally when the signal charge is transferred from the common video
line into the BED shift register, the transfer gate LT should be turned
on to the same reference level set by LR. However, due to normal process
parameter variations at device fabrication, such as surface-state density,
gate-oxide thickness, and substrate concentration, there will be a thres
hold voltage variation between transistors even though they are very close
together on the same integrated-circuit chip. This threshold voltage
variation will cause two problems in the operation of the device. Firstly,
with different threshold voltages, the level set by the LR and LT switches
will be different, even though they have the same gate voltage. If the
reference potential level set by the LR switch is higher than that of LT,
which corresponds to VT voltages of the LR and LT switches respectively, then some of the signal
charge xtfill be drained into the sink and cause nonlinearity in the
optical-to-electrical transfer characteristics. This is illustrated in
Figure 2.9. In order to avoid this possible loss of signal charge, the
voltage applied to the LR switch should be lower than that of LT. The
effect of these different gate potentials on LR and LT results in adding
a fixed amount of charge into the video signal at high light levels,
where
^VLR VLT't (VTI.R VTLT^' Cs (2.1)
" <4VG 4V Cs
V^p and are the gate potentials of the LR and LT gates respectively,
and Cg is the capacitance of the video line. To prevent this fixed



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-21-
line of information at one time. The dynamic shift register is driven
by a two-phase clock denoted by 0^-^ and 0^ i-n Figure 2.7. It can be
self-loaded for sequencing or controlled by an external start pulse.
These functions are performed by the "NOR" circuit. Tied to each output
of the shift register (except for the 100th position) are inputs to the
"NOR" circuit which control the loading of the shift register. When
there is an output from any of the 99 output positions, the "NOR" cir
cuit keeps the shift register from loading. Once the bit occupies the
last position, the "NOR" circuit's output goes high and another bit is
loaded into the shift register. Note that YArirn is also connected to
the "NOR" gate. It can be used to inhibit the register from loading by
pulling YgTART to a high potential.
(3) Two tetrode gate bucket-brigade shift registers [26,27] with
a gated charge-integrator output. As shown in Figure 2.7, there are two
bucket-brigade analog shift registers located on either side of the de
vice. These are the odd and even transport registers which accept the
pixel information in parallel from their respective odd and even video
diode columns, and shift the pixel information sequentially to the out
put amplifier. Each shift register is driven by a two-phase clock
denoted by 0 0 in Figure 2.7, and is also provided with a "fat zero"
input port to improve the transfer efficiency as well as to check the
performance of the register. The outputs from both shift registers are
multiplexed off-chip to obtain one line of combined video information.
The advantages of this multiplexing approach are manifold. It increases
the density of the array, especially for the linear array in which the
center-to-center distance of the sensing diodes is limited by the bit
length of the analog shift register; it increases the pixel rate to two


-13-
arrays, this architecture is perfectly adequate for realizing long, high
density arrays. Linear arrays approaching 2000 pixels in length with
pixels as close as 15 pm centers have been available for some time [38].
This architecture, however, has reportedly two serious shortcomings. The
one most often referred to is the output capacitance, which increases
directly with the number of pixels. Its effect is to increase directly
the thermodynamic or random noise of the system, thus limiting the mini
mum number of photons/pixel that can be detected. The other is referred
to as fixed-pattern noise, which originates from the non-uniformity of
the shift register and multiplex switches. This noise is discernible
primarily at low levels of illumination. However, it can be eliminated
by using differential signal processing techniques and is, therefore,
much less of a problem now as compared to earlier arrays using this
architecture.
The second architecture to be discussed is commonly referred as a
charge-coupled device which uses the field-induced photo-detector as the
pixel and the analog shift register to shift the information from the
pixel to the output terminal and is depicted by Combination B. Two
typical matrix structures are shown in Figure 2.5. These structures
permit very high density with pixel spacings of 20 to 30 pm not uncommon
[17]. Depending on the particular criteria employed, the performance of
these structures has ranged from adequate to excellent. As a result of
the very low output capacitance and the elimination of sequential sampl
ing with multiplex switches, both the thermodynamic and the fixed-pattern
noise in the dark are exceptionally low. This, however, is offset by the
resulting non-uniformity that prevails under illumination. This non
uniformity is a result of the variations in film thicknesses that occur


-4-
will make the peripheral circuits inoperable. To solve this dilemma, a
selective ion implant technique [33] was employed in which only the regions
under the BBD gates were implanted to minimize the barrier-height modula
tion. This technique resulted in a high performance BBD register. The
limitations of the high performance BBD are discussed, which lead to a
proposed new BBD structure. Finally, the experimental results of the
optimal matrix array which incorporated the high performance BBD register
are reported. The optical-to-electrical transfer characteristics with
and without using the "fill and spill" technique are compared, and the
noise performance is presented.
Chapter 7 contains the conclusions of this work.


-127-
Output
Input
(a)
Output
Input
(b)
Figure 6.5
Output of a
0.5 V/div.,
(a) Tetrode
(b) Tetrode
BBD shift register. Vertical scale
horizontal scale 50 ps/div.
gate properly biased,
gate biased too high.


-139-
1s due to the transfer noise being mainly determined by the magnitude of
the storage capacitance as discussed in Section 4.4.3. Therefore with
same magnitude of storage capacitance, a lower saturation charge will
result in a smaller dynamic range. A second disadvantage is the sen
sitivity of the threshold voltage of the implanted transistors due to
process fluctuations. This results from the fact that the effective
substrate concentration of the implanted transistors not only depends
on the ion implant process step, but also on each subsequent high tem
perature step used for drive-in. Any fluctuation in these subsequent
high temperature processes will result in a threshold voltage change,
and these changes will cause a fluctuation of the optimum DC bias point
for the input and output circuits from device to device.
6.2.4 A Proposed BBD Structure With Improved Performance
The low frequency transfer efficiency of a tetrode BBD can be im
proved by reducing the Cg/Cp ratio. This usually can only be achieved
by increasing C^, since there is a limitation on the minimum achievable
C However, higher C will result in a degradation of the high fre-
quency performance due to the intrinsic transfer rate limitation.
In modern multiple-layer silicon-gate technology, a transistor can
be fabricated by using either a first or a second layer silicon gate.
If the tetrode gates and switch transistors of a BBD use different layers
of polysilicon, the capacitance Cg can be completely eliminated by over
lapping the two gate layers. Moreover, the storage capacitance can
be obtained by using the overlapped capacitance between the two layers
of polysilicon instead of the usual MOS capacitance. This will greatly
reduce the dark current by eliminating the p-n junction underneath the
MOS capacitance.


Table 2. Design Parameters of the Optimum Image Sensor
PARAMETERS
DESIGNED VALUES
Sensing Diode:
Center-to-Center Distance X
60 ym
Center-to-Center Distance Y
60 ym
Saturation Charge
1.5 pc
/ w\
Multiplex Switch Size 1 1
6/10
Common Video Line:
Stray Capacitance C^
3 pF
Junction Capacitance of N+ between LT,
LR Switches
0.11 pF
Buffer Gate Size
106/8
/w\
LT Gate Size ( 1
22/10
LR Gate Size
22/10
Transfer Time into BBD Register
1 ys
BBD Shift Register:
Storage Capacitance
0.6 pF
/ w \
Transfer Gate Size 1 1
60/12
Tetrode Gate Size
60/8
Maximum Data Rate
10 MHz
Output Sensing Node Capacitance
0.5 pF
/ w\
Output Amplifier Size ^ j-1
160/10
Dynamic Range Due to Thermodynamic Noise
2000
Dynamic Range Due to Fixed-Pattern Noise
600


Poly-Sil icon
Field Plate
DIFFUSED PHOTODETECTOR FIELD INDUCED PHOTODETECTOR
Figure 2.2 Two basic photodetector structures.


-144-
speed and low transfer inefficiency. The effective channel length of the
tetrode transistor was 5 pm, providing high frequency operation, while
the switch transistor had an effective channel length of 9 ym for minimiz
ing barrier-height modulation. Both transistors were implanted. As can
be seen from Figure 6.13, this register is capable of operating up to 5
-4
MHz, and still has a transfer inefficiency of 2 x 10 Since the video
output is obtained from multiplexing the two registers, this is equiva
lent to a data rate of 10 MHz which translates to a frame rate of about
800 frame/sec. This high frame rate makes this image sensor very attrac
tive for applications in the field of high speed motion studies.
6.3.2 Image Test
Figure 6.14 shows an image taken with the matrix array. It was a
street scene looking from a window. The array output was displayed on
a CRT, and the face of the CRT was photographed directly using a Polaroid
camera. The clock frequency of the BBD register was 500 KHz, and the in
tegration time was about 11 ms. Except for the limited resolution (100
lines/frame), the picture is quite clear.
Figure 6.15a shows one line of video output from both the odd and
even registers. The video signals represent a bright spot at the center
of the array. Figure 6.15b shows the combined output using an adder on
the Tektronix scope. Without any sample-and-hold signal processing cir
cuits, a clean output can be obtained by using simple adder. The output
of a complete frame is shown in Figure 6.16.
Figure 6.17 shows the output of a frame using the frame reset, FR,
switch. The array was illuminated with a continuous uniform light. After


-126-
inefficiency e with the tetrode gate properly biased, and dividing the
measured e by the C /C ratio. The C /CL ratio can be determined either
s D s D
from calculation or from measurement.
To measure the C /C ratio, the transfer inefficiency e is first
s D
measured with the tetrode gate properly biased, and then with the tetrode
gate biased at several volts higher than the clock voltage. The ratio
of the two measured transfer inefficiencies represents the ratio of
C /C Once the C /C ratio is determined at a certain frequency, it can
S U S D
be used for the entire clock frequency range, since both Cg and are
independent of the clock frequency. Figure 6.5 is a photograph of the
output of a BBD shift register. Figure 6.5a is the output when the te
trode gate was properly biased. Figure 6,5b shows the output when the
tetrode gate was biased at about 1 V above the clock voltage. The im
provement in transfer efficiency is obvious. Figure 6.5a shows a total
charge loss of about 45% while the charge loss in Figure 6.5b is so
large that it cannot be measured accurately using this pulse input
method. Under this condition, the amplitude attenuation method described
in Chapter 5 must be used.
Based on the experimental results of the test BBD registers, the
following conclusions were reached:
(1) It was reported [33] that for a BBD register fabricated on a
low carrier-concentration substrate, the performance was very sensitive
to the clock wave shape. It was found during our experiments that the
sensitivity to the clock wave shape is caused by the input structure.
Usually the BBD register is driven by a set of complementary clocks, and
the input sampling gate is tied to one of the clocks. If the threshold
voltages of the transfer switch and the input sampling gate are too low,


VIDEO OUTPUT (V)
-152-
Figure 6.19 Nonlinear transfer characteristic of the
area image sensor due to subthreshold
leakage of the buffer gate which causes
a high transfer inefficiency between the
sensing diode and BBD register.


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-43-
3.2.3 Input and Output Structures
"f*
As shown in Figure 3.3b, the input structure consists of an N source
island which is the analog signal input terminal, a FET sampling switch
which is driven by one phase of the shift register clocks, and an input
capacitor C. When the 0£ switches are off and the 0^ switches are on,
node I will be charged to the input potential V_^. When the voltages on
the 0^ and 0£ switches are reversed, the charge at the input capacitance
will be transferred into the shift register, and node I will be discharged
to (V_ V) by the 0 switch. The charge injected into the shift reg-
ister is therefore
(VG VT V ci (3-6)
The signal charge in the shift register channel can be detected by atta
ching the gate of a source follower to the channel, as depicted by output
A in Figure 3.3b, or by using a gated charge integrator [36] at the end
of the shift register as depicted by output B in Figure 3.3b. The dis
advantage of the output A structure is that any noise on the driving
clock will appear on the output signal. However, this means of detection
is non-destructive which is an advantage over the charge integrator.
3.3 Performance Limitations
The most important aspect of a charge transfer device is its ability
to maintain the integrity of the charge packets as they are transferred
along the device. In the preceding section, it was assumed that the
charge transfer at each stage is perfect. However, in actual operation,
the transfer of charge from one stage to the next is neither instantaneous


-3-
describing the mechanisms which govern the transfer efficiency and
operating speed of the BBD are developed. The barrier-height modulation
model developed to explain the low frequency transfer inefficiency of
the BBD is an improved version of Yau's [28] and Taylor's [29] short-
channel models. In this model, the effects of drain potential and the
gate-electrode fringing field in the drain depletion region [30] are
taken into account in deriving the threshold voltage of the MOS transis
tor. This model is very useful for MOS circuit simulation, and can be
implemented easily into the simulation program.
Chapter 4 contains the analysis of the operating mechanisms and
design formulations for the optimal matrix array. A unique "fill and
spill" technique [31] used to eliminate the charge transfer inefficiency
between the sensing diode and the BBD register is discussed in detail.
The limitations of the anti-blooming structure for minimizing the signal
degradation due to saturation are also presented.
In Chapter 5, device fabrication and measurement procedures are
described. The fabrication process used was n-channel, double-layer
silicon-gate technology. The substrate concentrations used in this
study were 6 x 10^^ and 1.7 x 10^ cm
Chapter 6 presents the experimental results. It was concluded that
while high frequency operation of the BBD register is limited by its
intrinsic transfer rate, the transfer inefficiency at low frequencies is
mainly determined by the barrier-height modulation of the transfer gate.
To obtain a BBD register with good transfer efficiency and reasonable
speed, the substrate concentration must be much higher than 1.7 x 10^
_3
cm However, if a low resistivity substrate is used for fabricating
the BBD register, the body effect [32] of the high substrate concentration


TRANSFER INEFFICIENCY
-135-
fc (Hz)
Figure 6.9
Measured transfer inefficiency as a
function of clock frequency for the
implanted BBD shift register with
Tetrode gate W/L = 18/15, transfer
gate W/L = 18/7.


-41-
t = t4
Qs
C
)
(4c)


-40-


-154-
Another important characteristic of an image sensor is the dark
current. Figure 6.21 shows a photograph of the dark response of an array
with two different integration times. There is no discernable difference
between the two dark signals as the integration time was increased from
2 ms to 47 ms. At room temperature the dark current contributes less
than 1% of the saturation signal for integration times up to about 30 ms.
Low dark current is another advantage of this charge-transfer photodiode
technology.
6.3.5 Blooming Characteristic
The blooming characteristic is shown in Figure 6.22. The curve was
obtained by imaging a circular target with a diameter of approximately
10 diodes on the array, and measuring the output of a nonexposed diode
located 15 diodes away from the exposure center but sharing the same
common video line. Points on the horizontal axis represent multiples
of saturation exposure and points on the vertical axis represent the
output of the nonexposed diode normalized to the output voltage of a
saturated diode. The dashed line shows the contribution from the second
term of equation (4.22). The difference between the dashed line and
measured curve is the contribution from (AQ- /Q ) as shown in the same
It SEt
equation. The maximum value of this term is calculated to be Q, /Q =
It sat
10%. Agreement between calculations and measurements is reasonably good.
From this blooming characteristic, it is evident that although the bloom
ing control is not perfect, it is much better than typical CCD imagers
[15-17].


VIDEO OUTPUT (V)
EXPOSURE (pjoule/cm2)
Figure 6.20 Linear transfer characteristic of the
area image sensor obtained by using a
"fill and spill" technique to eliminate
the transfer inefficiency between the
sensing diode and BBD register.


-109-
(12)
Deposition of second-layer polysilicon
(13)
O
Second-layer polysilicon oxidation: 2000A
(14)
Fourth photoresist mask: definition of the
second-layer polysilicon gates for the storage
capacitances
(15)
Gate oxide etching and phosphorus doping for
the second-layer polysilicon, and source and
drain regions
(16)
O
Source and drain oxidation: 1000A
(17)
Deposition of pyroglass: 1.8 pm
(18)
N-gettering
(19)
Fifth photoresist mask: open contacts
(20)
Low temperature gettering
(21)
Aluminum evaporation
(22)
Sixth photoresist mask: definition of inter
connection metal
(23)
Aluminum alloy: 515C
(24)
Deposition of scratch protection pyrox
(25)
Seventh photoresist mask: open up aluminum
bonding pads
(26)
Backside gold evaporation
5.2 Measurements
In this section the experimental setups to measure the barrier-height
modulation of a MOSFET, transfer inefficiency of the bucket-brigade re
gister, optical-to-electrical transfer characteristics, and the saturation
charge of an image sensor, will be described.


-44-
nor complete. This puts some limitations on the speed of operation of
the bucket-brigade devices and the total number of transfers that can
be executed without objectional signal degradation. Incomplete transfer
means that in each transfer a small amount of signal charge is left be
hind. This effect is cumulative and after many transfers the charge
packets become significantly smeared together. The parameter used to
describe the performance of the bucket-brigade device is called transfer
inefficiency e. This is defined as the fraction of signal charge left
behind after each transfer. This parameter multiplied by the number of
transfers in a device is the transfer inefficiency product N^e, which
determines the overall transfer performance of the whole device.
The mechanisms that introduce the transfer inefficiency can be
classified according to the operating frequency of the bucket-brigade
device. At high frequencies, it is the intrinsic transfer rate of the
FET switch that limits the transfer efficiency. If not enough time is
allowed for the charge to transfer through the switch before the switch
is turned off, some of the signal charge will be trapped at the previous
stage. As will be discussed later, the transfer inefficiency is propor
tional to the square of the clock frequency when the device is operated
in this frequency range. At low frequencies, there is enough time for
the charge to transfer through the FET switch, and therefore, the source
potential will be discharged to (V V ) as discussed in the previous
section. However, the discharge current is not completely cut off due
to thermal diffusion of the charge carriers. There is still some leakage
current passing through the FET switch, which is referred to as the sub
threshold leakage current, and the FET device is referred to as being
operated in the subthreshold or weak inversion region [41-43]. This


-20-
SUBSTRATE
POTENTIAL
Figure 2.8 Potential diagram of a diode before and
after being selected.


CHAPTER 4
ANALYSIS OF THE OPERATING MECHANISMS AND NOISE
LIMITATIONS OF THE OPTIMUM IMAGE SENSOR
4.1 Charge-Storage Operation of a Photodiode
The photodiode used in a solid-state image sensor is operated in
the charge-storage mode instead of the normal photoconductive or photo
voltaic mode. In the normal photoconductive or photovoltaic mode, the
output from a photodiode depends on the rate of photon absorption;
however, as discussed in the previous chapter, the photodiodes in an
image sensor are sampled in a periodic manner. Therefore, the active
properties of the diode are used only during the time of sampling. To
fully utilize the sensing diode during the total sensing period, the
photon flux has to be integrated, which leads to the charge-storage mode
of operation.
In the charge-storage mode of operation the photodiode is precharged
first to a fixed reverse bias of a few volts, and the circuit is then
opened so that the junction behaves like a capacitor which discharges
smoothly under the influences of the illumination and the junction leak
age current. While the photodiode integrates the light, it provides a
means to evaluate the total irradiation energy received. The charge
lost during the light integration period is proportional to the illumin
ation energy received by the diode multiplied by the duration of light
integration. Thus, by monitoring the charge required periodically to
-84-


-72-
ET E1 + EX2 + EX3
(3.44)
The field E^ can be obtained from the step junction approximation
./
qNA
2 (y V )
2K e v D Dsat'
s o
(3.45)
A rigorous calculation of the contributions of and E^ requires a
solution of Poisson's equation in the depletion region near the Si-SiC^
interface. However, they can be given by the approximations [30]
Ko (VD VG + V
EX2 K t
s ox
"X3
K (V V V )
_£ G FB Dsat7
K t
s ox
(3.46)
(3.47)
where K and t are the dielectric constant and thickness of the gate
o ox
oxide layer respectively, and a and B are the field-fringing factors
which represent the extent to which the normal oxide field fringes in
a transverse direction into the depleted region near the drain. Good
agreement between theory and experiment was obtained over a wide range
of device parameters and applied voltages for the values a = 0.2 ana
B = 0.6.
Combining equations (3.43)-(3.47), we obtain
Jldep = (V V )
r D Dsat
2K e (VD ~ VDsat) + (k ,
so \ s/
(V V + V )
v D G FB
-1
ox
(3.48)
, r o
6 K)
In the limiting case of high substrate concentration, the first term in
the bracket of (3.48) will dominate, and the expression of i-dep reduces
to


transfer rate of the tetrode gate, while the transfer inefficiency at low
frequencies is mainly determined by the barrier-height modulation of the
transfer gate. To improve the performance of the bucket-brigade, the re
gions under the tetrode and transfer gates are implanted to increase the
effective substrate concentration; this reduces the barrier-height modu
lation and significantly improves the bucket-brigade's performance. The
merits and disadvantages of the implanted device are discussed, which
leads to a proposed new bucket-brigade structure. It is shown that the
charge-transfer efficiency between the sensing diode and analog shift
register degrades sharply with decreasing light level due to the subthresh
old leakage current of the transfer gates. By using a unique method to
provide a background or fat-zero charge, this transfer inefficiency is
eliminated, and the image sensor exhibits a linear photo-response with
a dynamic range of more than 600 to 1 at operating frequencies up to
10 MHz.
vi


-98-
ANTI-BLOOMING
GATE
VQb
VDD
TRANSFER GATE
1
I I TO ANALOG
* SHIFT REGISTER
SENSING
DIODE
(a)
(b)
Figure 4.4
(a) Schematic of linear array anti-blooming
structure.
(b) Potential diagram showing the anti-blooming
effect and charge transfer into the analog
shift register.


-30-
relative former rate, while the interlace gates LO, LE confine the row
selection to alternate lines, odd or even as appropriate for the field.
Thus, there is no change either in integration period or in overall
frame rate; the picture is merely assembled in two interlaced fields
instead of one sequential scan. Slight changes are required in the LT
and LR clocks to accommodate the new pattern.


-49-
(5a)
(5b)
(5c)


Figure 5.2 Test setup for measuring transfer inefficiency of a BBD shift
register.


Figure 6.14
Image taken with the matrix array.


TRANSFER INEFFICIENCY
-83-
Figure 3.14 Theoretical transfer inefficiency due to barrier-
height modulation as a function of channel length
for different substrate concentrations.


I certify that I have read this study and that in my opinion it
conforms to acceptable standards of scholarly presentation and is fully
adequate, in scope and quality, as a dissertation for the degree of
Doctor of Philosophy.
Sheng-San Li, /Chairman
Professor of Electrical Engineering
I certify that I have read this study and that in my opinion it
conforms to acceptable standards of scholarly presentation and is fully
adequate, in scope and quality, as a dissertation for the degree of
Doctor of Philosophy.
Eugene R. Chenette
Professor of Electrical Engineering
I certify that I have read this study and that in my opinion it
conforms to acceptable standards of scholarly presentation and is fully
adequate, in scope and quality, as a dissertation for the degree of
Doctor of Philosophy.
Kwan-Yu Chen
t
Professor of Physics and Astronomy


*£y1 = ^2 I ^ I W 1 *
50 OR MORE CLOCK PERIODS
, 7- M H
xz=4>xi TJTJ_TJTiA-nJTJ_lJTifUlJlJ_TJ^fUT_n
LT=LR n ;¡ n ;; T1
Figure 2.10 Timing diagram for continuous-scan mode.


-47-
The tetrode structure improves the performance of the device by reducing
the effects of channel-length and barrier-height modulation and meanwhile
does not increase the complexity of the fabrication process. There are
some other device structures which can improve the performance, such as
stepped electrode [46] and junction FET approaches [47]. However, these
approaches require special fabrication processes which are not compatible
with standard MOS processes. As a consequence, most of the modern bucket-
brigade devices use the tetrode structure.
Figure 3.5a shows the actual device structure, and Figure 3.5e shows
the equivalent circuit. represents the junction capacitance of the
+
N island between the FET switch and tetrode gate. The function of the
tetrode gate is to isolate the storage capacitance C from being affected
by any channel-length and barrier-height modulations on the transfer
gates. Therefore, for optimum operation, the tetrode gate should be
biased near the higher clock driver voltage V^. In Figure 3.5b, the
bias level of the tetrode gate is shown at its optimum level which is
slightly below the phase driver voltage. The solid lines indicate the
surface potential without any introduced signal charge for the condition
of 0£ high and 0^ low. The shaded region is the bias charge always pre
sent in the N regions. The double crosshatching indicates the introduction
of a half well of signal charge and the resultant barrier modulation. The
arrow points out the loss of charge from the signal packet due to the
barrier modulation. Since the capacitance of is very small, this
loss is small. In Figure 3.5c, the tetrode gate is shown at a higher
voltage than that applied to the phase drivers. As seen by the double
crosshatching which extends across the tetrode gate, the loss due to the
barrier modulation is much larger since the capacitance which is affected


-Ir
respectively. It is clear that the final gate oxide thickness is 1100A,
and the substrate concentration is fairly uniform within 1 ym from the
interface. The effective substrate concentration is about 4.5 x 10^
-3
cm Using this effective substrate concentration, the calculated
threshold voltage is about 3.15 V. This is higher than the actual meas
urements mad.e on test transistors, which were in the range of 2.0 to 2.5 V.
Figure 6.8 shows the plot of measured V versus vfy + 0_, where V__ is
I dd r Sij
the substrate bias voltage. The straight line relationship shows that
the substrate concentration was uniform within the depletion region.
The effective substrate concentration calculated from the slope of the
16 "3
straight line is 3 x 10 cm The discrepancy between the calculated
and measured effective substrate concentration may be due to the inac
curacy of boron segregation coefficient used in the program, or less
boron dosage in the actual implantation. In the following analysis a
16 -3
uniform substrate concentration of 3 x 10 cm will be used.
Figure 6.9 shows the measured transfer inefficiency as a function
of clock frequency for a device with the same geometry as the one shown
in Figure 6.6, except that the switch transistors and tetrode gates were
implanted. The high frequency transfer inefficiency is still in good
agreement with the intrinsic transfer rate model described in Chapter 3.
However, the measured low frequency transfer inefficiency is much better
than that predicted by the barrier-height modulation model. This dis
crepancy is due to the high carrier concentration of the implanted
substrate. This high substrate concentration resulted in a diffused, p-n
junction which no longer can be approximated by the one-sided step junc
tion used in deriving equation (3,72), Practical diffused p-n junctions
may be approximated by one-sided step junctions or linearly graded


TRANSFER INEFFICIENCY
-143-
Figure 6.13 Transfer inefficiency characteristic of the
high performance BBD shift register integrated
on the optimal image sensor. Both the tetrode
and transfer gates were implanted.


Figure 6.24 Spectral response of thermodynamic noise for the area image
sensor. The upper solid line represents a reference voltage
of 1 V at the output, the upper trace is the noise of the
device, and the lower trace is that of the measurement system.


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AUTHOR: Tseng, Hsin-Fu
TITLE: Study of the Optimum Charge-Transfer Image Sensor (record number:
87525)
PUBLICATION DATE: 1979
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CHAPTER 2
OPTIMIZATION OF A SOLID-STATE IMAGE SENSOR
2.1 Introduction
Evolution has produced several solid-state image sensors, each pos
sessing different architectures. Most of these can be broken down into
combinations of four basic building blocks. This chapter will present a
review of these building blocks and discuss in detail a new architecture
which results in the optimal solid-state image sensor.
2.2 The Architecture of A Solid-State Image Sensor
The solid-state image sensor takes advantage of the highly developed
silicon integrated circuit technology. The mechanism of detection is
based on the absorption by silicon of photons within an energy range of
1.1 eV to about 6 eV; this corresponds to a wavelength range of 1.1 pm
to 0.2 pm as shown in Figure 2.1 by a typical spectral response curve.
When a photon is absorbed, it generates an electron-hole pair. If we are
to detect this electron-hole pair, the components must be separated.
This is normally accomplished by the depletion region of a p-n junction
or the depletion region induced by applying the appropriate voltage to
an MOS capacitor. This is also referred to as a potential well. In
either case, the electron and hole are separated and the charge equiva
lent to one electron will then appear on the depletion region capacitance.
-5-


I
to
4>
I
Figure 2.9 Loss of signal charge due to threshold voltage difference of LT
and LR gates, > VTLR.


-16-
Figure 2.6 Cross-section of X-Y addressable sensing
cell of a charge injection array showing
location of stored charge under (a)
Integration, (b) Readout enable, (c)
Injection conditions.


-137-
r
1
r. +
1
2e K
o s
aq
1/3
(V.
bi
V )
Dsat
1/3
r
1
r. +
1
2 e K
o s
aq
1/3
(V.
bi
V
1/3
(6.2)
(6.3)
The channel length modulation Jldep also must be corrected using the
linearly graded junction approximation. Neglecting the fringing field
of the gate, the result is
/ O
,1/3
/ 2e K \ 1/3
*dep -Hr) (vd- w
(6.4)
From equations (6.2) (6.4), the form factor F^ as expressed by equation
(3.69) now can be calculated versus drain potential, from which the trans
fer inefficiency due to barrier-height modulation can be determined.
Figure 6.10 shows the low frequency transfer inefficiency of the
implanted BBD register as a function of channel length. The circles re
present the experimental results while the solid line represents the
theoretical calculation. The two are in reasonable agreement.
It is evident from Figures 6.9 and 6.10 that the low frequency trans
fer efficiency is greatly improved using this selective implant technique.
It is not difficult to fabricate a BBD register with transfer inefficiency
less than 10 ^ at clock frequencies up to 5 MHz. By reducing the ratio
of Cg/C^, the transfer efficiency at low frequencies can be further im
proved to the extent that a BBD register of several thousand stages can
be fabricated, with a very small N e product. However, there are two
§
disadvantages caused by the ion implant. One disadvantage is the very
high threshold voltage of the implanted transistors due to body effect.
This high threshold voltage reduces the charge handling capacity as de
scribed by equation (3.7), and results in smaller dynamic range. This


-73-
£dep =
/2K e
/ s o
qNA
(V V )
K D Dsat
(3.49)
which corresponds to the results obtained by Ihantola [48] and by Reddi
and Sah [44] The effective channel length now can be expressed as
L(V = hi 2XJ £dep
(3.50)
where is channel length defined by the gate mask, and represents
the lateral underdiffusion from the source and drain. Differentiating
(3.50) leads to
dLOy ihJl)(VD VDS-t)^ 4- (Kc/Kstox) (B a)(Tg VFB VDs't)^
D (I)(VD + + <2Ko/'/5CstoX,(VD ^Dsat^F
dV.
2K e
(3.51)
where K = - (3.52)
qNA
F c(VD VG + VFB) + 6(Tg VFB VDs't) (3.53)
With equations (3.36), (3.40), (3.48) and (3.51), the transfer ineffi
ciency due to the subthreshold current can be calculated. In Figure
3.12 the theoretical values of are plotted as a function of the
channel length L for different substrate concentrations NA*
3.5.3 Transfer Inefficiency Due to Barrier-Height Modulation
Another mechanism that affects the transfer inefficiency at low
frequencies is the barrier-height modulation due to variation of drain
voltage with different signal charges. To analyze this mechanism we
will not consider the effects of subthreshold leakage current which have
been treated in the previous subsection. In addition, we assume the


RELATIVE RESPONSE
Figure 2.1 Typical spectral response of a diffused diode.


rrnrni ir-urv i u
I |\UUUU.M t 111
C2
C2
hJ -
m
hi
vn .
ca
na
*-i -
vn
C3
I M
U
CS
7^
ZC
m
rxi
vn
ca
vn
ra
ra-
-j
vn
CU
ca
ca
ca
hJ
to
n
ra
hj
n
in
AMPLITUDE RESPONSE
i i i i i i
L0 iii *-4 m vn a:
ca ¡si E3 ca ea cs
-I j. 1 1 1-
IN DE
i i
id r-d
ca ca
I H
ca
i
s
H J
I
/
/
09T


-56-
From (3.19) it is now obvious that the transfer inefficiency due to the
intrinsic transfer rate is not only proportional to the square of the
clock frequency, but also is inversely proportional to the square of the
signal charge Qq. As the signal charge decreases, the transfer ineffi
ciency increases sharply. A circulating charge or "fat zero" is
therefore needed not only to reduce the interface-state trapping, but
also to improve the transfer inefficiency due to this transfer rate
limitation.
The physical meaning of the speeding up of the apparent transfer
rate by the circulating charge can be understood by examining equation
(3.16), which has been plotted in Figure 3.7 for the following represen
tative values:
3 = 3 x 10~5 A/V2
Qq = 0.8 and 2.4 picocoulomb (pc) (3.20)
C =0.44 pF
Figure 3.7 shows that for a clock frequency of 0.5 MHz approximately
0.012 pc or 0.5% of charge remains in the source for Qq = 2.4 pc. This
0.5% transfer inefficiency is intolerable for any practical bucket-brigade
device. However, the charge remaining in the source for = 0.8 pc is
very near to the value for the large initial charge. If this 0.8 pc is
the circulating charge Q^, and any change beyond this amount represents
the signal information, then the actual signal charge trapped at each
transfer will be the difference between the charges left behind for both
of the initial charges of 0.8 and 2.4 pc. Hence, the apparent transfer
efficiency is greatly improved. An accurate calculation of (3.16) using


-103-
similar to the thermal fluctuations of the Nyquist noise; however, the
probability density has a Poisson distribution. The noise electron value
due to this source can be expressed as [54]
where 1^ is the dark current, and T^ is the integration time.
This noise is only important in low light level imaging when the
integration time is long enough that the dark-current charge is sizable
compared with the saturation charge of the sensing diode.
Besides the shot noise, the dark current will also cause a fixed-
pattern noise due to the variation of the dark current between the sensing
cells.
4.4.2 Noise Sources Associated With the Common Video Lines
There are also two noise sources associated with the common video
lines. One is the kTC noise of the video line capacitance due to the
reset of the video line through the buffer gate. The other is a fixed-
pattern noise generated by the variation of V,^^) among the
video lines. Assuming a voltage variation of AV^, the fixed-pattern
noise electron value is expressed by
C.AV
N = Tn (4.26)
n q
+
where C_. is the junction capacitance of the N diffusion between the LT
and LR switches. AV,^ usually is around 10-20 mv. This fixed-pattern
noise can be cancelled out by using differential techniques, otherwise
it will be the limiting noise for low light level imaging.


-167-
46. C.N. Berglund and K.K. Thornber, "A Fundamental Comparison of Incom
plete Charge Transfer in Charge Transfer Devices," Bell Syst. Tech.
J. 52, 147-182 (1973).
47. M.B. Barron and W.J. Butler, "JFET Bucket-Brigade Circuit: Some Re
cent Experimental Results," Electronics Lett. 9, 603-604 (1973).
48. H.K. Ihantola, "Design Theory of A Surface Field-Effect Transistor,"
Stanford Electronics Labs., Stanford, C., Tech. Rept., (1961).
49. A.S. Grove, "Physics and Technology of Semiconductor Devices,"
John Wiley and Sons Inc. New York (1967).
50. M.B. Barron, "Computer Aided Analysis of Insulated Gate Field Effect
Transistors," Stanford Electronics Laboratories, Report No. 5501-1,
(1961).
51. R.H. Krambeck, T.F. Retajczyk and L.D. Yau, "Low Frequency Transfer
Efficiency of E-Beam Fabricated Conductively Connected Charge-
Coupled Device," IEEE J. Solid-State Circuits SC-11, 171-180 (1976).
52. G.T. Cheney and R.A. Kotch, "A Simple Theory for Threshold Voltage
Modulation in IGFET's," Proc. IEEE 56, 887-888 (1968).
53. F.S. Jenkins, E.R. Lane, W.W. Lattin and W.S. Richardson, "MOS-Device
Modeling for Computer Implementation," IEEE Trans. Circuit Theory
CT-20, 649-658 (1973).
54. J.E. Carnes and W.F. Kosonocky, "Noise Sources in Charge-Coupled De
vices," RCA Review 33, 327-343 (1972).
55. D.D. Buss, W.H. Bailey and W.L. Eversole, "Noise in MOS Bucket-Brigade
Devices," IEEE Trans. Electron Device ED-22, 977-981 (1975).
56. R.W. Broderson, D.D. Buss and A.F. Tasch, "Experimental Characteriza
tion of Transfer Efficiency in Charge-Coupled Devices," IEEE Trans.
Electron Devices ED-22, 40-46 (1975).
57. W.B. Joyce and W.J. Bertram, "Linearized Dispersion P^elation and
Green's Function for Discrete Charge Transfer Devices with Incomplete
Transfer," Bell Syst. Tech. J. 50, 1741-1759 (1971).
58. P.Z. Peebles, "Communication System Principles," Addison-Wesley Inc.
Massachusetts (1976).
59. H. Lawrence and R.M. Warner, Jr., "Diffused Junction Depletion Layer
Calculation," Bell Syst. Tech. J. 39, 389-403 (1960).
60. R. Wang, "4-Terminal MOS Analysis," Motorola Internal Rep. 8-30-1968.


-35-
equations will be formulated to analyze the transfer efficiency quantita
tively, which will allow one to see the effects of each device parameter
on its performance.
3.2 Device Structure and Operation
3.2.1 Device Structure
Figure 3.3a shows the integrated circuit version of an N-channel
IGFET bucket-brigade shift register. It can be fabricated using a stan
dard two-layer polysilicon gate process. The substrate is p-type material
and the transfer channel is confined by channel-stop ion implantation and
field oxide. After the gate oxide is grown, the first poly layer is
deposited and defined to form the FET switch. The channel region under
the FET gate can be selectively implanted before the gate deposition to
increase the effective substrate concentration for minimization of
channel-length and barrier-height modulation. The oxide between the
switches is then etched away. An N island is then formed between the
switches either by a light diffusion or by ion implantation. A second
oxidation step regrows the gate oxide on top of the N island as well
as the insulation oxide on the first poly. A second layer of poly is
then deposited and defined on top of the N island to form the capacitor.
Figure 3.3b shows the equivalent circuit. C represents the gate capaci
tance between the N island and the second poly. Ch represents the
junction capacitance of the N island to the p-substrate.


-129-
enough so that it results in an increase of effective substrate concen
tration and not a fixed surface charge of Q To assure this condition,
ss
the drive-in depth of the implant must be deeper than the depletion re
gion under the gate.
In section 6.2.3, the experimental results of the high performance
BBD registers fabricated using the selective implant technique will be
presented.
6.2.2 Experimental Verification of the Intrinsic Transfer Rate Model
In section 3.5.1, it was pointed out that the intrinsic transfer
rate of the BBD register is limited by the transconductance of the tetrode
transistor. Therefore, in determining the intrinsic rate, the B parameter
of the tetrode transistor, instead of the switch transistor, must be used.
To prove this conclusion, the intrinsic transfer rate of two BBD registers
were compared, one with a B parameter of the tetrode gate nearly one half
that of the switch transistor and the other with a B parameter of the te
trode gate nearly two times that of the switch transistor. The results
are shown in Figures 6.6 and 6.13.
Figure 6.6 shows the measured transfer inefficiency e as a function
of clock frequency for the BBD register fabricated on a substrate with a
15 -3
carrier concentration of 1.7 x 10 cm The B parameter of the tetrode
transistor is nearly one half that of the switch transistor as can be seen
from the W/L sizes displayed in the figure. At low frequencies, the e is
determined by the barrier-height modulation of the switch transistor. At
high frequencies, however, it is limited by the transfer rate of the te
trode gate. The agreement between theory and measurement is excellent.


-7-
Let us briefly compare these two basic detection mechanisms. The
internal quantum efficiencies can for all practical purposes be assumed
to be the same for both mechanisms, i.e., the efficiency of collecting
photo-generated electron-hole pairs. The main difference is in the ex
ternal quantum efficiency of the two mechanisms. Figure 2.2 shows the
basic structure of these two detectors. The external quantum efficiency
of the diffused photodiode suffers minimum losses due to only two inter
faces between materials of different refractive indices, i.e., Air-SiC^
interface and SiC^-Si interface. The thickness of the SiC^ is such that
the modulation of the spectral response of the diffused photodiode is
negligible. It is apparent from Figure 2.2 that for the field induced
detector an additional two interfaces are present to introduce losses
[34]. Furthermore, the transparent electrode is not really transparent
since it is usually polysilicon. Because silicon is absorptive, some of
the incident photons are absorbed in this layer. This is particularly
true for the short wavelength or the blue end of the spectrum. The use
of exotic metallic materials [35] has resulted in field plates that are
more transparent over the spectral range of interest than is polysilicon;
however, these materials are foreign to standard integrated circuit tech
nology.
Furthermore, the thickness of these films is subject to normal
processing variations. It is, therefore, difficult to insure reprodu
cibility of sensitivity, uniformity, or spectral response. It is
apparent that the diffused photodiode is a far superior detector, pos
sessing the following advantages:
(1) external quantum efficiency approximately three times that of
the quasi-transparent electrode employing polysilicon;


-151-
The output signal was measured directly from the source follower
at the end of the shift register. Since the LR "high" level was two
tenths of one volt above that of the LT, some of the signal charge will
be drained into V through the LR switch. The irregularity of the trans
fer characteristic is caused by a combination of this charge loss and poor
transfer efficiency due to subthreshold leakage current of the buffer gate
Figure 6.19 shows the transfer characteristic when the LT and LR
gates were properly clocked. The LT "high" level was 14.7 V and LR "high"
level was 14.5 V. The slope of the transfer curve is not constant. The
slope increases with decreasing light level. This is in agreement with
the result obtained in Section 4.2, which shows that charge transfer ef
ficiency into the BBD register degrades sharply with decreasing light
level. It was mentioned previously that transfer inefficiency, due to
subthreshold leakage current of the buffer gate, can be eliminated by a
background charge using a "fill and spill" technique. The result using
this technique is presented in Figure 6.20. The gamma (y) of this trans
fer curve is unity. This indicates that the background charge does
eliminate the transfer inefficiency and results in a linear photo-response
2
The responsivity calculated from the transfer curve is 13 V per yjoule/cm
6.3.4 Saturation Signal and Dark Current
In the image sensor, saturation is determined by imaging a target
on the chip and increasing the irradiance until the output signal begins
to level off. The signal level at this point is defined as the saturation
amplitude; the corresponding irradiance energy is the saturation exposure.
As can be seen from Figure 6.20, the saturation signal was about 3 V at an
2
exposure level of 0.25 yjoule/cm The saturation charge measured at the
reset drain is 1.6 pc.


-166-
30. D. Frohman-Bentchkowslcy and A.S. Grove, "Conductance of MOS Tran
sistors in Saturation," IEEE Trans. Electron Devices ED-16, 108-113
(1969).
31. C.H. Sequin and A.M. Mohson, "Linearity of Electrical Charge Injec
tion into Charge-Coupled Device," IEDM, Washington, D.C., Tech. Dig.,
229-232 (1974).
32. W.M. Penny and L. Lau, "MOS Integrated Circuits," VanNostrand
Reinhold Comp. New York (1972).
33. R.R. Buss and G.P. Weckler, "Bucket Brigade Devices," CCD76 Int.
Conf., Edinburgh, Proc,, 55-65 (1976).
34. C. Anagnostopoulos and G. Sadasiv, "Transmittance of Air/Si02/
Polysilicon/Si02/Si Structures," IEEE J. Solid-State Circuits SC-10,
177-179 (1975).
35. D.M. Brown, M. Ghezzo and M. Gartinkel, "Transparent Metal Oxide
Electrode CID Imager Array," ISSCC Dig. Tech. Papers, 34-35 (1975).
36. C.H. Sequin and M.F. Tompsett, "Charge Transfer Devices," Academic
Press, Inc. New York (1975).
37. E.H. Snow, "Solid State Image Sensors for Visual Protheses," IEEE
INTERCON, New York, Dig., Papers 37/2 (1973).
38. RL1872F Linear Photodiode Array, Reticon Corporation, Sunnyvale,
Ca.
39. W.S. Boyle and G.E. Smith, "Charge-Coupled Semiconductor Devices,"
Bell Syst. Tech. J. 49, 587-593 (1970).
40. G.P. Weckler, H.F. Tseng and R.W. Broderson, "Fully Integrated CTD
Filter with Output Sensing," ISSCC Dig. Tech. Paper, 84-85 (1978).
41. R.R. Troutman, "Subthreshold Slope for Insulated Gate Field-Effect
Transistors," IEEE Trans. Electron Devices ED-22, 1049-1051 (1975).
42. M.B. Barron, "Low Level Currents in Insulated Gate Field Effect
Transistors," Solid-State Electronics 15, 293-302 (1972).
43. R.M. Swanson and J.D. Meindl, "Ion-Implanted Complementary MOS Tran
sistors in Low-Voltage Circuits," IEEE J. Solid-State Circuits SC-7,
146-153 (1972).
44. V.G.K. Reddi and C.T. Sah, "Source to Drain Resistance Beyond Pinch-
Off in MOS Transistors," IEEE Trans. Electron Devices ED-12, 139-141
(1965).
45. H.S. Lee, "An Analysis of the Threshold Voltage for Short-Channel
IGFET's," Solid-State Electronics 16, 1407-1417 (1973).


Figure 6.11 A proposed BBD structure with improved
performance.
-141-


-28-
transfer into the BBD register, as well as ways to speed up the charge
transfer process will be discussed in detail in Chapter 4.
During the time when the signal charge is being transferred into
the BBD register, the clock driving the register must stop with the clock
at high potential on the buckets receiving charge from the video line.
This will cause a deep potential well for the signal charge to flow into.
As evident from Figures 2.7 and 2.10, the buckets receiving charge for
both the odd and even transport registers are driven by 0 0, and the
charge transfer takes place simultaneously for both registers during the
time 0 0 is held high. However, on the readout, the odd BBD register
produces the first pixel, since it reads out on the first low-going 0^
clock just after the transfer period. The second pixel is produced by
the even BBD register; and since this pixel must transfer through an
extra half-stage which is controlled by the 0^ clock, this even pixel
is produced when 0 .. goes low. This provides an easily multiplexed
signal by means of a simple external adder amplifier. The output charge
integrators of the shift registers are connected as a source follower
with an external load resistor tied between the video output terminal
and ground. The reset switch of the charge integrator VR1 and VR2 are
connected to the appropriate clocks driving the shift register to remove
the signal charges after they have been sensed. Because there are fifty
buckets of signal in each transport register, it requires at least 50
clocks to transfer all the signal charge into the output amplifier as
shown in Figure 2.10.
The timing diagram for the interlace mode is shown in Figure 2.11.
It generally is somewhat similar to that for the non-interlace mode;
however, the dynamic shift register clock 0^ must run at twice the


-11-
serves as an input to a machine, random noise does not appear to be a
practical problem. The level of the random noise, however, does set a
basic limit to the minimum detectable illumination level that can be
detected.
The second approach, shown in Figure 2.3, also employs a transfer
switch (really an adjustable barrier) for each pixel; however, all pixels
are sampled simultaneously, thus transferring all the information in
parallel into an analog shift register. This information is then clocked
to an output terminal at the end of the analog shift register. The ana
log shift register has been highly developed over the past few years.
Charge-transfer devices, both bucket-brigade [33] and charge-coupled [36],
can now be made with transfer efficiencies exceeding 0.9999 at megahertz
clocking rates; therefore, the initial problems of shading and loss of
resolution are no longer a serious problem.
Figure 2.4 shows four architectures that may be implemented using
the building blocks described above. Let us begin by examining each
structure. The first structure to be discussed uses photodiodes as the
detectors and a digital shift register to sequentially interrogate these
diodes and is depicted in the figure as Combination A. This structure
operates in the charge-storage mode [1] and is commonly referred to as
a self-scanned photodiode array [2,3]. To obtain line storage requires
a single multiplex switch connected to each photodiode, thus making pos
sible high density linear arrays which possess all the advantages of
the photodiode detector. To obtain frame storage in a matrix or two-
dimensional array requires that each photodiode have two multiplex
switches associated with it. As a result, the size is limited since
the minimum center-to-center spacing is about 75 pm [37]. For linear


-32-
<
INPUTo

2
3
1
Figure 3.1 Basic bucket-brigade structure.


-88-
4.2 Sensing Diode to BBD Analog F-egister Charge-Transfer Mechanism
The charge transfer mechanism from the sensing diode into the BBD
register, for the optimum area image sensor described in Chapter 2, is
very similar to that of the tetrode bucket-brigade device. Figure 4.1a
shows the equivalent circuit of the charge transfer path. Cg represents ,
the storage capacitance of the sensing diode, 0^ is the multiplex switch,
is the video line capacitance, and is the junction capacitance of
-f*
the N diffusion between the LR and LT switches. The line reset LR
switch is not shown in the equivalent circuit since it is turned off
during the charge transfer process. Figure 4.1b shows the potential at
each node before the charge transfer. Since is much larger than both
and Ck the charge transfer speed will be limited by the discharge of
Cy through the V ff gate.
Ideally, during the charge transfer process, the MOS switches should
cut off when the potentials of each capacitor reach a value of (V -V ),
where V and V are the gate potential and threshold of the MOS switches.
However, as discussed in Chapter 3, due to the subthreshold leakage be
havior of the MOS switch, the current does not cut off sharply. Instead,
it decays exponentially, and as a consequence, the potential at each
capacitor will increase slowly beyond the (V -V ) level with increasing
time. Theoretically this leakage current never ceases, and the potential
of the capacitor keeps increasing. However, in real applications, when
the current reaches a negligible level, the MOS switch is considered to
be in the off state.
To derive the equations for the charge transfer speed let us con
sider the worst case transfer efficiency of the buffer gate at very low
light levels. Because the buffer gate is biased at a DC level of V^uff


-147-
Figure 6.16
Output of a complete frame. Vertical
scale 2V/div., horizontal scale 1 ms/
div.


-132-
IStNG BORN IMPLAN!
BORON ION IMPLAN!
SltP -7 1MC = 0.5 MINUIES.
OEP!H
IUM)
-0.11
0.0
1.00
2.00
3.00
4.00
CDNCCMRA11 UN {LOO AlMS/CC)
4
15
10 17
10
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20
21
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1 1
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Figure 6.7 Calculated substrate concentration profile
of the implanted region using the process
simulation program SUPREM.


-26-
interlacing node, odd rows are first all accessed to form an odd field,
followed by even rows to form an even field.
(6) Frame reset FR. This switch provides an access to the multi
plex switches of all the diodes in the matrix and allows the entire
frame to be reset instantaneously. Since the diodes in each line are
automatically reset when the line is accessed, the frame reset switch
is normally not used and is held low. However, when a particular ex
posure is desired, this control may be used to clear the diodes to start
a fresh integration cycle by taking FR terminal to V^. When this mode
is used, a shutter or pulsed light input is required because the diodes
are sequentially accessed and will thus differ in exposure time if light
input is continued during the readout sequence.
2.3.2 Device Operation
Figure 2.10 shows the timing diagram for the array when operated in
the non-interlace mode. It consists of three sets of complementary
clocks for the dynamic shift register, the BBD analog register, and the
line reset and transfer gates. The rising edge of the LT pulse should
lead the rising (or falling) edge of the 0^ clock by approximately 30 ns
or more to insure that no useful signal charge is drained into V^. The
width of the LT pulse should be minimized to the time required for the
complete transfer of charge into the BBD register. During the transfer
gate "ON" time, the charge collected at the stray capacitance along the
video line and the excess signal charge leaked from other sensor diodes
not selected also go into the BBD shift register, with the possibility
of causing interline crosstalk and blooming. The theoretical considera
tions of the anti-blooming mechanism, speed limitations of the charge


ACKNOWLEDGEMENTS
I would like to express my deepest gratitude to Professor S.S. Li
for his guidance and encouragement throughout the research and prepara
tion of this dissertation. Also, I give thanks to Professors E. R.
Chenette, F. A. Lindholm, D. R. MacQuigg, J. K. Watson, and K. Y. Chen
for their advice and support. In addition, I would like to acknowledge
the many helpful discussions with Mr. G. P. Weckler, and Dr. R. W. Bro-
densen at Reticon Corporation.
Thanks are also due to Mr. Ed Webb for carefully proofreading the
manuscript, and Reticon Corporation for financial support and fabrication
of the devices used in this study.
ii


VIDEO OUTPUT (V)
-150-
T
1.0

0.1
0.011
0.001
e
e
e
09
0.01 0.1
EXPOSURE (fijoule/cm2)
Figure 6.18
Irregular transfer characteristic of the
area image sensor occurring when the
line reset LR and line transfer LT gates
were improperly clocked.
1.0


CHAPTER 7
CONCLUSIONS
The research described in this dissertation has led to the follow
ing conclusions:
(1) The optimum structure of a solid-state image sensor consists
of diffused junction diodes for photo-sensing and an analog charge-transfer
register for signal readout. The photodiode offers the advantages of high
quantum efficiency, and full and smooth spectral response, while the charge-
transfer register provides a low noise self-scanned video output.
(2) This optimum structure can be easily implemented in both linear
and matrix arrays. A matrix array, consisting of 100 by 100 photodiodes
and two tetrode bucket-brigade shift registers, has been realized and
studied. Evaluation of this image sensor has shown that it has a linear
photo-response, and can be operated up to a data rate of more than 10 MHz.
Without using any signal-processing technique, this device provides a
useful dynamic range of more than 600 to 1. Although the center-to-center
distance of the photodiodes used in this device was 60 pm, this distance
can be reduced to less than 40 pm by careful device layout. As a conse
quence, an array with higher resolution is achievable.
(3) A bucket-brigade device offers several advantages over a
charge-coupled device. These advantages are simplicity and flexibility
of tapping the signal along the shift register, compatibility with stand
ard MOS technology, and ease of operation. Models describing the
-162-


-53-
<
Figure 3.6
FET model for charge transfer efficiency
behavior of a bucket-brigade device.


-33-
INPUT
I
1
Figure 3.2
Improved bucket-brigade structure with tetrode
isolation.


-81-
dL
dV.
D
1
2
r+ 2r. M7+T) + K(V + V, V 0_) 2
j 2 bi D D bi Dsat F'
x
Kr.
+ K
VV
d&dep
dVD
(3.74)
where can be obtained from equation (3.50)-(3.51) The second
bracketed term in (3.72) represents the effect of the change of depletion
width under the gate due to the source potential being modulated. This
2. ^
term is only important at high substrate concentration (C^ >10 Cm ).
For the simplified case of source and drain junction with vertical sides
(or the equivalent condition r^ /K(V^s^+ 0^)), equations (3.70),
(3.71), and (3.73) reduces to the forms
L1 = /K(V, + Vn ')
1 bi Dsat
L2 = /K(Vb. + VD) £dep
dL
K
ddep
dVo 2 /K(V + vj dVD
(3.75)
(3.76)
(3.77)
Again for the case of a circulating charge Qc and signal charge of
(Q Qc), the transfer inefficiency also can be obtained by
AVT s
£b (Qc Qc)
(3.78)
where AV^ is the threshold voltage variation of the switch transistor
when Qc and Qq are present at the drain node. This threshold voltage
variation AV^ is obtained by calculating the variation of form factor
AF^ for different drain potentials, and multiplying by the two bracketed
terms in (3.72).
For the model discussed in this section it is assumed that the


-105-
N = 60 C
n
gate \5 MHz
AB
1000 ymho
mo
i.
(4.28)
where
C
gate
is the MOS gate capacitance in pF
8,
is the transconductance of the device
mo
AB
is the noise bandwidth
In the above noise analysis, the 1/f noise has been neglected, since
the image sensor is usually operated in a high frequency range where the
1/f noise can be ignored. Table 1 shows the noise sources considered,
the expression of N^, and finally the actual number for the rms fluctua
tions for the designed value of the parameter involved. It is evident
that while the charge transfer dominates the thermodynamic noise charac
teristic, the fixed-pattern noise will limit the low light level
performance if it is not eliminated by using differential signal process
ing techniques.
In Table 2, the design values of the parameters for the optimum
image sensor discussed in this chapter are summarized.


-92-
It is clear from equation (4.14) that the subthreshold "ON" resis
tance is independent of the geometry of the MOS switch. Therefore,
increasing the size of the MOS switch will not help the transfer speed.
Multiplying both sides of equation (4.14) by C results in a small signal
RC time constant of "t." The worst case time is the total integration
time. This worst case corresponds to the condition that only one diode
in the common video line is under illumination, and the rest are in the
dark.
In the above discussion, it is assumed that signal charge dumped
into the video line is so small that it does not change the video line
potential V significantly. Under this low light level, the charge
transfer time constant is so long that with a finite transfer time T ,
which corresponds to the pulse width of the LT clock, most of the signal
charge will be trapped on the video line. However, at high light levels,
the charge dumped into the video line is large enough to modulate the
video line potential considerably. As a result, the initial charge
transfer speed will increase greatly, and the percentage of signal charge
trapped on the video line will become less important.
To calculate the charge trapped on the video line after a finite
transfer time, T at high light levels, let us assume that only one of
the diodes in the video line is illuminated, and a signal charge of Qg
is dumped into the video line when this diode is selected. The signal
charge will lower the video line potential by an amount Qg/Cv. Let us
further assume that the g^ of buffer gate is large enough that the video
line potential will be discharged to O^uff in a time which
is negligible compared with the total transfer time T At the end of
the transfer time, the video line potential will be


REFERENCES
1. G.P. Weckler, "Operation of p-n Junction Photodetectors in a Photon
Flux Integrating Mode," IEEE J. Solid-State Circuits SC-2, 65-73
(1967).
2. R.H. Dyck and G.P. Weckler, "Integrated Array of Silicon Photodetec
tors for Image Sensing," IEEE Trans. Electron Devices ED-15, 196-201
(1968).
3. G.P. Weckler, "Solid-State Image Sensing With Photodiode Arrays,"
IEEE INTERCON, New York, Dig., Papers 1/2 (1973).
4. G.J. Michon and H.K. Burke, "Charge Injection Imaging," ISSCC Dig.
Tech. Papers, 138-139 (1973).
5. G.J. Michon and H.K. Burke, "Operational Characteristics of CID
Imager," ISSCC Dig. Tech. Papers, 26-27 (1974).
6. G.J. Michon and H.K. Burke, "Recent Developments in CID Imaging,"
Symposium on CCD Tech, for Scientific Imaging Applications,
Pasadena (1975).
7. M.F. Tompsett, G.F. Amelio, W.J. Bertram, R.R. Buckley, W.J. McNamara,
J.C. Mikklsen and D.A. Sealer, "Charge Coupled Image Devices: Experi
mental Results," IEEE Trans. Electron Devides ED-18, 992-996 (1971).
8. C.K. Kim and R.H. Dyck, "Low Light Level Imaging Device With Buried
Channel Charge Coupled Devices," Proc. IEEE 61, 1146-1147 (1973).
9. M.F. Tompsett, W.J. Bertram, D.A. Sealer and C.H. Sequin, "Charge-
Coupling Improves Its Image, Challenging Video Camera Tubes,"
Electronics 46, No. 2, 162-168 (1973).
10. C.H. Sequin, "Experimental Investigation of a Linear 500-Element 3
Phase Charge-Coupled Device," Bell Syst. Tech. J. 53, 581-610 (1974).
11. D.A. Sealer, C.H. Sequen and M.F. Tompsett, "High Resolution Charge
Coupled Image Sensors," IEEE INTERCON, New York, Dig., Papers 2/1
(1974).
12. C.K. Kim, "Two-Phase Charge Coupled Linear Imaging Devices With Self-
Aligned Barriers," IEDM, Washington, D.C., Tech. Dig., 55-58 (1974).
13. C.H. Sequin, "Interlacing in Charge Coupled Imaging Device," IEEE
Trans. Electron Devices ED-20, 535-541 (1973).
-164-


-70-
no drift component in the channel current; therefore, the variation of
surface potential along the channel is very small [42]. The current is
mainly from diffusion of minority carriers due to the concentration gra
dient. Therefore, the end of the channel should be the point where the
minority-carrier concentration equals zero. For simplicity, we define
the end of the channel as the point where the semiconductor is intrinsic.
The potential at this point is denoted by V as distinguished from
I/SEt
conventional V By definition V can be expressed by
JJScLu DSat
V = V V 0 +
Dsat G FB r
K e qN.
s o A
ox
1 / 1 +
2V, K e qN.
s o A
(3.42)
Note that the only difference between (3.41) and (3.42) is the factor
"2" in front of the Fermi potential 0^.
The extent of the depleted region depends on the difference between
the potential of the drain, V^, and that at the end of the channel,
V and on the average transverse electric field component near the
Dsat
Si-SiC^ interface, E^. Thus
£dep =
V V *
D Dsat
(3.43)
According to Frohman-Bentchkowsky and Grove's model [30], this average
transverse field is attributed to the superposition of three electric
fields as shown in Figure 3.11. arises from acceptor ions within
the drain depletion layer, E^ is the X-axis component of fringing field
E^ which arises from the drain-gate potential difference, and E^ is the
X-
-axis component of fringing field E^ which arises from the gate to
difference. Thus


-100-
case, when the excess signal charge is so large that the current spilling
into video line exceeds the subthreshold leakage current of the buffer
gate, then the video line will maintain a potential of (V, rr. Vm, rr.)
buff Tbuff
at all times. Under this high light level condition, a blooming signal
of represented by equation (4.21) will be present at the output.
The second source of blooming is due to the transfer gate "ON" time.
During this "ON" time, the current leaking into the video line from the
saturated diodes will go directly into the bucket-brigade register. This
blooming charge depends on the leakage current, which is determined by
the light level as well as the number of diodes under illumination. The
greater the number of diodes on the same video line that are over-saturated,
the greater the leakage current that will be drained into the register.
Combining the two blooming sources, the percentage blooming of an
unilluminated diode can be expressed as
AQ N x M x T \
%BLM = | + - I :x 100%, (M > 1)
sat
T.
i
(4.22)
where N_^ is the number of diodes illuminated on the same
video line
M is the exposure normalized to the saturation
light intensity
AQ^t is the reduction of the trapped charge.
The second term in the parenthesis of equation (4.22) represents
the leakage charge collected during the transfer gate "ON" time T The
expression is self explanatory. With N_^ diodes illuminated by a light
intensity of M times the saturation level, it will generate (N x M)
times saturation charge during the total integration time T.. The per-
centage of charge collected during time T is, therefore, determined by
the ratio of T /T..
t i


-46-
The trapping of carriers by interface states in the IGFET channel
and subsequent emission at a later time will result in charge left behind,
and will effectively introduce another contribution to the transfer in
efficiency. This transfer inefficiency can be minimized by using a
certain amount of circulating charge, or "fat zero" in the device. The
effect of the fat zero is to keep the interface states under the gates
filled so that these states will not trap signal charge. As a result,
each charge packet will receive about the same number of electrons from
the preceding packets as it loses to the trailing packets. As will be
discussed later, this circulating charge will also speed up the intrinsic
transfer rate considerably, and improve the high-frequency performance of
the device.
Another limitation to bucket-brigade operation that needs to be men
tioned is the dynamic drain conductance effect. It is well known that
drain potential modifies the current flow and gives rise to a non zero
output conductance in the saturation region of the IGFET characteristic
[30,44]. This effect is also caused by channel-length modulation as
mentioned before. This dynamic drain conductance effect will introduce
another component of transfer inefficiency in the high frequency opera
tion range of the bucket-brigade device. However, this transfer
inefficiency component can be reduced to a negligible level by using
the tetrode gate structure.
3.4 Tetrode Structure Bucket-3rigade Device
The most important improvement in the development of the bucket-
brigade device, which makes the actual application of this device
possible, is the introduction of the tetrode gate structure [26,27].


AVt (V)
-123-
vD (V)
Figure 6.3 Barrier-height modulation as a function of
drain voltage for two test MOSFETs with
different channel lengths.


-93-
kT / q Dllr,LT!W
V ' eff v
(4.15)
where nQ is the equivalent carrier concentration at the source end of
the buffer gate when V = (V, V_, ,.-). Before the illuminated diode
v buff Tbuff
is selected again, the video line potential will reach V(T^), where
is the integration time. The expression of V(T_^) is identical to equation
(4.15) with T_^ replacing T The signal charge lost now can be determined
from
Q1 = C [V(T.) V(Tt)]
(4.16)
With a typical integration time of 4 ms and transfer time of 4 ys, the
charge loss calculated from equation (4.16) is about 30% even at a satur
ation charge level of 1.5 pc. This results from the video line capaci
tance, C^, being about ten times larger than the sensing diode storage
capacitance Cg.
For the low light level case, let us assume that after the video
line potential has been lowered by a magnitude of Qs/Cv, its potential
is still "V below the (V, V__ rj.) level. The video line potential
o buff Tbuff
then can be expressed by
. kl,| <","oWLB , V>/kT
V(i) L c t + e
(4.17)
eff v
In equation (4.17), the electronic diffusion constant D has been replaced
by using Einsteins relationship, and the initial condition V = Vq at
t = 0 also has been incorporated. The worst case charge transfer inef
ficiency now can be determined from
c, [V(Tt) vj
Cv [V(T.) VQ]
e
(4.13)


Figure 5.1 Test setup for measuring barrier-height modulation of an
MOSFET.
-Ill-


START _
READOUT
CLOCK
CLOCK
Figure 2.3
Techniques for interrogating and reading-out picture elements.
VIDEO
OUTPUT


^Yl =
ODD FIELD
Y2
ib
ib
ib
50 OR MORE CLOCK PERIODS
H H
-i?-
EVEN FIELD
n
ib
<£x2= ^xi Jinjyuui/uinjYL^^
LINE
t-HNc. m
TRANSFER, LT 1 l #.
-ib
J1
LINE 1 r
RESET, LR = LT U
-ib
-ib
U
ib
-ib
-ib
ib
-ib
-ib
TL
U
-ib
-ib
-ib
JT
ib
U
50 OR MORE CLOCK PERIODS
<* N
<#>yi=^YsiJiAririJijiJirLrir
i a
i
I
LO = LE
ODD FIELD
EVEN FIELD.
U
ib
Figure 2.11 Timing diagram for interlace mode.


TUNGSTEN
LAMP
r\
MICROAMMETER
Figure 5.5 Test setup for measuring the optical-to-electrical
characteristics of the image sensor.
-IT-


-113-
The usual method of measuring the inefficiency parameter is presented
in Figure 5.3, which shows a train of uniform signal charges (five shown
here) in the midst of a long series of "fat-zero." This is obtained by
feeding a pulse signal into the shift register. is the difference be
tween the signal charge and the fat-zero charge. The differences A^, A^,
etc., are the amounts of charge missing from the first, second, etc.,
pixels in the train; and A^, A^, etc., are the amount of charge in excess
of the fat-zero charge which emerge in the first, second, etc., pixels
trailing the pulse train. The normalized total loss in the leading edge
(L^) is defined by
LL =
Z A.
. l
l
(5.1)
and the normalized total loss in the trailing edge (L^,) is defined by
LT
a:
(5.2)
It is shown [56] that the normalized loss is related to the transfer
inefficiency e by
U = Lm =
(N l)e
__g
1 e
N e
g
(5.3)
which is independent of signal amplitude. N represents the total number
g
of transfers. Using equation (5.3), the inefficiency parameter e can be
determined.
However, in the case of N e > 1, it is usually difficult to measure
g
the total charge loss accurately. Under this condition, it is easier to
feed a sinusoidal signal into the shift register and measure the output
signal amplitude attenuation as a function of the signal frequency. The
amplitude attenuation |A /A | is related to the total signal charge
loss by [57]


-118-
The device is then illuminated uniformly over the entire active area
with a saturation irradiation. The increase in current measured at the
reset drain terminal is the saturation photocurrent I The saturation
charge Q then can be determined from
S3t
I x T.
o = -E i
%at N .
pixel
(5.5)
where T^ is total integration time, and N is
total number of pixels
in the array.


-34-
introduced which showed promise of improved transfer efficiency, higher
clocking frequencies and higher density; therefore, most of the work
switched from bucket-brigade devices to charge-coupled devices. The
charge-coupled device appeared to be a very simple structure, requiring
only simple processing. However, despite the theoretical improvement,
it produced devices with not much better performance than the bucket-
brigade. It took five years and a tremendous amount of effort to develop
the understanding and technology to the point which allowed the advantages
of CCD to be truly realized.
With the development of CCD and modern MOS technology, such as
multiple-layer silicon gates to increase the density, self-aligned struc
tures to reduce the parasitic capacitance, and threshold voltage control
by selective ion implantation to minimize channel-length and barrier
modulation, it is now possible without any difficulty to fabricate a
-4
bucket-brigade device with transfer inefficiency less than 10 and
operating frequency higher than 5 MHz [19,33]. The bucket-brigade de
vice possesses certain advantages over the charge-coupled device, which
makes it very attractive in some signal processing and image sensing
applications. The most important advantage of the bucket-brigade device
is the simplicity [33] and flexibility [40] of tapping the signal along
the shift register. This is very desirable in correlator and transversal
filter applications, as well as in interfacing with peripheral circuitry.
Another advantage of the bucket-brigade device is its compatibility with
existing MOS processes; as a result, a wealth of circuitry used in making
digital memories and microprocessors can be integrated on the same chip.
In this chapter, the operation of the bucket-brigade device will be
presented, and its performance limitations will be discussed. Analytical


-165-
14. C.H. Sequin, F.J. Morris, T.A. Shankoff, M.F. Tompsett and E.J. Zimany,
"Charge-Coupled Area Image Using Three Levels of Polysilicon," IEEE
Trans. Electron Devices ED-21, 712-720 (1974).
15. R.L. Rogers, "A 512 x 320 Element Silicon Imaging Device," ISSCC
Dig. Tech. Papers, 188-189 (1975).
16. L. Walsh and R.H. Dyck, "A New Charge-Coupled Area Imaging Device,"
CCD Appl. Conf., San Diego, Proc., 21-22 (1973).
17. G.F. Amelio, "The Impact of Large CCD Image Sensing Area Arrays,"
CCD74 Int. Conf., Edinburgh, Proc., 133-152 (1974).
18. H.F. Tseng, "Interlaced Photodiode Array Employing Analog Shift
Registers," U.S. Patent No. 4,087,833 (1978).
19. H.F. Tseng and G.P. Weckler, "Optimization of a Solid State Image
Sensor," CCD76 Int. Conf., Edinburgh, Proc., 79-84 (1976),
20. H.F. Tseng and G.P. Weckler, "CCPD-The Optimum Solid State Linear
Scanner," NATO AGARD Symposium on CCD, Papers 4/3 (1977).
21. FiL.J. Sangster, "The Bucket-Brigade Delay Line, A Shift Register
for Analogue Signals," Phillips Tech. Review 31, 97-110 (1968),
22. F.L.J. Sangster and K. Teer, "Bucket-Brigade Electronics-New Possi
bilities for Delay, Time-axis Conversion and Scanning," IEEE J.
Solid-State Circuits SC-4, 131-136 (1969).
23. K.K. Thornber, "Incomplete Charge Transfer in IGFET Bucket-Brigade
Shift Registers," IEEE Trans. Electron Devices ED-18, 941-950 (1971).
24. C.N. Berglund, "Analog Performance Limitations of Charge-Transfer
Dynamic Shift Registers," IEEE J. Solid-State Circuits SC-6, 391-
394 (1971).
25. C.N. Berglund and H.J. Boll, "Performance Limitations of the IGFET
Bucket-Brigade Shift Register," IEEE Trans. Electron Devices ED-19,
852-860 (1972).
26. F.L.J. Sangster, "Integrated Bucket-Brigade Delay Line Using MOS
Tetrodes," Phillips Tech. Review 31, 266 (1971).
27. L. Boonstra and F.L.J. Sangster, "Progress on Bucket-Brigade Charge-
Transfer Devices," ISSCC Dig. Tech. Papers, 140-141 (1972),
28. L.D. Yau, "A Simple Theory to Predict the Threshold Voltage of '
Short-Channel IGFET's," Solid-State Electronics 17, 1059-1063 (1974).
29. G.W. Taylor, "Subthreshold Conduction in MOSFET's," IEEE Trans.
Electron Devices ED-25, 337-351 (1978).


LOW FREQUENCY TRANSFER INEFFICIENCY
-125-
Figure 6.4
Low frequency transfer inefficiency
as a function of channel length for
the test BBD shift registers.


-110-
5.2.1 Barrier-Height Modulation Measurement
The barrier-height modulation of an MOS transistor can be measured
using a setup as shown in Figure 5.1. The gate of the MOSFET is biased
at a fixed DC potential. The source potential is then measured as a
function of the drain voltage. A buffer stage is used between the source
node of the FET and the VTVM so that the source node is completely float
ing. The measured source potential variation is the barrier-height
modulation. It is obvious that this measurement setup is equivalent to
a bucket-brigade device operating at a very low frequency.
In the above measurement, the effect of subthreshold leakage current,
which will cause the source potential to drop below the barrier potential,
is neglected, since we are interested only in the modulation of the
barrier-height as a function of drain voltage, and not in the absolute
value of the threshold voltage. The error introduced by neglecting the
diffusion current is small, since the transfer inefficiency of the BBD
due to the subthreshold leakage current is negligible compared with that
due to the barrier-height modulation. This is evident by comparing the
theoretical values of the two transfer inefficiencies and s^ as dis
played in Figures 3.12 and 3.14.
5.2.2 Bucket-Brigade Shift Register Transfer Inefficiency Measurement
Figure 5.2 shows the block diagram of the test setup to measure the
transfer inefficiency of the BBD shift register. The signal from a signal
generator is fed into the shift register through a biasing and coupling
circuit. The output from the shift register is buffered before going
into a Tektronix scope or a spectrum analyzer.


-121-
Figure 6.1 Photograph of test transistors, the one
on the right is the long-channel reference
transistor.


-96-
Using the designed value of = 3 pF for the video line capacitance,
A 2
B = 4.5 x 10 A/V for the buffer gate, and a background charge of 1
pc, the time required to obtain a transfer inefficiency of 1% is 0.4 ps.
This is several orders of magnitude better than that without the back
ground charge.
To supply this background charge, a unique "fill and spill" scheme
is employed. During the charge transfer time when the LT switch is on,
the fat-zero charge in the bucket-brigade shift register is dumped into
the video line through the LT switch by pulsing 0^ low while 0^ is
still low. When the 0 clock goes high again, the fat-zero charge to-
gether with the signal charge will then spill back into the 0^ potential
well of the register. At the end of charge transfer, the charge left
behind on the video line will be a fixed amount and the apparent transfer
efficiency will be greatly improved as described by equation (4.20).
Figure 4.3 shows the timing diagram required to perform this "fill and
spill" function. Using this scheme, a linear optical-to-electrical
transfer characteristic can be obtained with a "spill" time of 1 ys.
4.3 Anti-Blooming Mechanism
When the signal charge collected by each sensing diode exceeds the
saturation level, the signal charge will spill over the isolation barrier
between the diodes and intersperse into the adjacent sensing cells. This
spill-over will add to the signals of the adjacent diodes and cause smear
ing or blooming of the output image. To prevent this, an anti-blooming
structure must be employed.
For a linear array, an anti-blooming structure may be easily imple
mented. As shown in Figure 4.4, each sensing diode is provided with an