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Effects of grain boundaries in polysilicon-on-insulator (SOI) MOSFETS

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Title:
Effects of grain boundaries in polysilicon-on-insulator (SOI) MOSFETS
Creator:
Ortiz-Conde, Adelmo, 1956-
Fossum, Jerry G. ( Thesis advisor )
Lindholm, Frederik ( Reviewer )
Li, Sheng S. ( Reviewer )
Burk, Dorothea E. ( Reviewer )
Varma, Arun K. ( Reviewer )
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English
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vii, 155 leaves : ill. ; 28 cm.

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Subjects / Keywords:
Charge density ( jstor )
Drains ( jstor )
Electric current ( jstor )
Electric potential ( jstor )
Electrons ( jstor )
Grain boundaries ( jstor )
Modeling ( jstor )
Narrative devices ( jstor )
Silicon ( jstor )
Threshold voltage ( jstor )
Dissertations, Academic -- Electrical Engineering -- UF
Electrical Engineering thesis Ph. D
Grain boundaries ( lcsh )
Metal oxide semiconductor field-effect transistors ( lcsh )
Genre:
bibliography ( marcgt )
non-fiction ( marcgt )

Notes

Abstract:
This dissertation presents physical models that describe the effects of grian boundaries on the steady-state current-voltage characteristics of large- and small-grain polysilicon (SOI: Si-on-SiO2) MOSFETS. These models, which are supported experimentally, reveal that the grain boundaries can control the drain current and hence the electrical properties of the MOSFET. Interpretations of measurements based on single-crystal MOSFET theory can therefore result in erroneous parameter evaluations and misconceptions regarding the underlying physics. The models developed herein enable proper interpretations of measurements and facilitate optimal design of the devices. The models for the large-grain polysilicon SOI MOSFET predict: (a) an effective turn-on characteristic in the linear-region, controlled by the grain boundaries, that occurs beyond the strong-inversion threshold voltage, and henceforth defines the "carrier mobility threshold voltage" and the effective field effect carrier mobility; (b) nearly exponential dependence on the (front) gate voltage, defined by the properties of the grain boundaries, for moderate-inversion conductance, and (c) that a grain boundary near the drain can control the conduction properties for all (week-to-strong) inversion conditions in all (linear-to-saturation) regions of operation. The models for the small-grain polysilicon SOI MOSFET predict: (a) the anomalous leakage current (OFF state), which is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain; (b) that the gate-voltage swing for the subthreshold drain current (ON state) depends strongly on the grain-boundary properties and weakly on the charge coupling between the front and back gates; (c) that the effective threshold voltage (ON state) depends strongly on grain-boundary properties and on the charge coupling between the front and back gates; and (d) the device design modifications to control and reduce the leakage current, the gate-voltage swing, and the effective threshold voltage.
Thesis:
Thesis (Ph. D.)--University of Florida, 1985.
Bibliography:
Bibliography: leaves 148-154.
General Note:
Typescript.
General Note:
Vita.
Statement of Responsibility:
by Adelmo Ortiz-Conde.

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University of Florida
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University of Florida
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Copyright Adelmo Ortiz-Conde. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
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AEH3691 ( NOTIS )

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EFFECTS OF GRAIN ROUNDARIES IN
POLYSILICON-ON-INSULATOR (SO) MOSFETS









By

ADELMO ORTIZ-CONDE


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN
PARTIAL FULFILLMENT OF THE REOIJIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA 1985



















TENGO EL INMENSO PLACER DE

DEDICAR ESTA TESIS A MIS PADRES



ALICIA CONDE-BRANDT DE ORTIZ ADELMO ORTIZ PINERO



















ACKNOWLEDGMENTS

I would like to thank all those who helped me in one way or another to make this work possible.

I wish to express my sincere gratitude to my guru, Dr. Jerry G. Fossum, for his invaluable guidance, encouragement and assistance in all

phases of this dissertation. It has been my privilege and my pleasure to have been his student. I am thankful to Professors Fredrik A.

Lindholm, Dorothea E. Burk, Sheng S. Li, and Arun K. Varma for their participation on my supervisory committee. I also thank Professor

Arnost Neugroschel for his help during the experimental part of this work and Professor Eugene R. Chenette for guiding my steps during the beginning of my graduate work.

I want to express my appreciation to Drs. Hon Wai Lam, Ravishankar Sundaresan, Hisashi Shichijo, and Sanjay Ranerjee of Texas Instruments, Inc., for technological support.

I would especially like to thank my friends Drs. Hyung-Kiu Lim and Ravishankar Sundaresan, former graduate students, for the many insightful discussions. My interaction with them has been a very gratifying learning experience. I would like to also thank my other colleagues and friends, Dr. Franklin Gonzalez, Bruce Rushing, Dr. HsingLiang Lu, Victor de la Torre, Tae-Wong Jung, Robert McDonald, Suy-Young Yung, Surya Veeraraghavan, Dr. Jean Andrian, Dr. Ganesh Kousik, Arthur











Van Rheenen, Dr. Saeid Tehrani-Nikoo, and Juin-Jei Liou for helpful comments and encouragements.

I am grateful to Ms. Carole Boone for her excellent work in editing and typing this dissertation.

I cannot in words express my thanks to my former professors at the Universidad Simn ?ollvar, Drs. Pierre Schmidt, Gustavo Roig, Paul Esqueda, and Francisco Garcia, for all they have done in support of my graduate work.

I am infinitely indebted to ny parents and family for their incredible support and encouragement throughout my graduate school career.

The financial support of The Consejo Nacional de Investigaciones Cientificas y Tecnologicas (CONICIT), Naval Research Laboratory (NRL), and the University of Florida Center-of-Excellence Program is gratefully acknowledged.



















TABLE OF CONTENTS



PAGE
ACKNOWLEDGMENTS . . . .iii

ABSTRACT . . .****** ********* *****.V vi1

CHAPTER

ONE INTRODUCTION . .01

TWO LINEAR-REGION CONDUCTANCE OF LARGE-GRAIN POLYSILICON MOSFETS.11
2.1 Introduction . . o. o. . 1
2.2 Linear-Region Conductance in Strong Inversion. 14
2.2.1 Intragrain Electron Distribution in Channel . 14 2.2.2 Grain-Boundary Potential Barrier in Channel.16 2.2.3 Channel Conductance. . .24
2.3 Linear-Region Conductance in Moderate Inversion.31 2.4 The Significance of Grain Boundary Orientation.35 2.5 Experimental Support and Discussion . 38
2.5.1 Support for the Strong Inversion Analysis . 39 2.5.2 Support for the Moderate Inversion Analysis.45
2.6 Summary . 46

THREE CURRENT-VOLTAGE CHARACTERISTICS OF LARGE-GRAIN POLYSILICON
MOSFETS. . . . . . . 49

3.1 Introduction . . 49
3.2 Analysis oo .o . o. -._ .5
3.2.1 Formalism. . . . . .53
3.2.2 Numerical Solution . . 59
3.3 Experimental Support and discussion .o. . 65 3.4 Summa ry . . . . . 67

FOUR ANOMALOUS LEAKAGE CURRENT OF SMALL-GRAIN POLYSILICON
MOSFETS. . . . 69

4.1 Introduction . . 69
4.2 Leakage Current Model . . 73 4.3 Summary . . 94













FIVE SUBTHRESHOLD BEHAVIOR OF THIN-FILM SMALL-GRAIN POLYSILICON
MOSFETS . *. .97 5.1 Introduction. . . 97
5.2 Analysis. , . . . . . . . . . . .,. 100
5.2.1 Formalism. . . . . .102
5.2.2 Numerical Solution. . -. . . . 108
5.3 Experimental Results and Discussion. . . 121 5.4 Summary. . o _ . . . . . .o. 125

SIX SUMMARY, CONCLUSIONS, AND RECOMMENDATIONS . . 128

6.1 Summary and Conclusions. 128 6.2 Recommendations for Further Research .131 APPENDICES

A THE CHARGE TRAPPED AT THE GRAIN BOUNDARY IN TERMS OF THE
OUASI-FERMI LEVEL . . . . . . . 134 B THE FOUNDATION OF A CHARGE-SHEET MODEL FOR THE THIN-FILM
MOSFET. . . o . 136 C FORTRAN COMPUTER PROGRAM TO CALCULATE THE CHARGE DENSITY IN A
THIN-FILM SMALL-GRAIN POLYSILICON MOSFET.

REFERENCES . . 148

BIOGRAPHICAL SKETCH. . . . 155


















Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy EFFECTS OF GRAIN BOUNDARIES IN
POLYSILICON-ON-INSULATOR (SOI) MOSFETS

Ry

ADELO ORTIZ-CONDE

August 1985

Chairman: Jerry G. Fossum
Major Department: Electrical Engineering

This dissertation presents physical models that describe the

effects of grain boundaries on the steady-state current-voltage characteristics of large- and small-grain polysilicon (SOI: Si-on-SiO2) MOSFETs. These models, which are supported experimentally, reveal that the grain boundaries can control the drain current and hence the electrical properties of the MOSFET. Interpretations of measurements based on single-crystal MOSFET theory can therefore result in erroneous parameter evaluations and misconceptions regarding the underlying physics. The models developed herein enable proper interpretations of measurements and facilitate optimal design of the devices.

The models for the large-grain polysilicon SOI MOSFET predict:

(a) an effective turn-on characteristic in the linear-region, controlled by the grain boundaries, that occurs beyond the strong-inversion

threshold voltage, and henceforth defines the "carrier mobility theshold












voltage" and the effective field effect carrier mobility; (b) a nearly

exponential dependence on the (front) gate voltage, defined by the properties of the grain boundaries, for moderate-inversion conductance, and (c) that a grain boundary near. the drain -can control the conduction properties for all (weak-to-strong) inversion conditions in all (linearto-saturation) regions of operation.

The models for the small-grain polysilicon SOl MOSFET predict:

(a) the anomalous leakage current (OFF state), which is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain; (b) that the gate-voltage swing for the

subthreshold drain current (ON state) depends strongly on the grainboundary properties and weakly on the charge coupling between the front and back gates; (c) that the effective threshold voltage (ON state) depends-strongly on grain-boundary properties and on the charge coupling between the front and back gates; and (d) the device design

modifications to control and reduce the leakage current, the gatevoltage .swing, and the effective threshold voltage.


viii



















CHAPTER ONE
INTRODUCTION

Because of the advantages of dielectric isolation and threedimensional (3-D) integration [GI80; LA82; MA85], there is much interest in SOI (silicon-on-insulator) MOSFETs. The advantages of these devices

compared with the single-crystal counterpart are [LA821: (a) increased circuit speed due to reduced parasitic capacitance; (b) superior hardness to transient radiation; and (c) elimination of'latch-up, which is of fundamental importance when the feature sizes in CMOS

(complementary metal-oxide-semiconductor) technology are scaled to smaller dimensions. Today, CMOS is the dominant technology for VLSI (very large scale integration) because of low power consumption,

superior noise margins, better compatibility with analog circuits, and reduced vulnerability to soft errors.

The most promising SOl technologies for VLSI are: SOl formed by high-dose ion implantation [HE841, SOI using porous silicon [BA841, silicon-on-sapphire (SOS) [SA84], beam recrystallization of polysiliconon-silicon dioxide FLASO], and as-deposited LPCVD (low-pressure chemical

vapor deposition) polysilicon-on-silicon dioxide [MA85i. The first two of these technologies yield dielectrically isolated single-crystal

silicon, but they have disadvantages. The SOl formed by high-dose ion implantation technology requires excessive capital costs for equipment, and the SOl formed by the porous silicon technology is not compatible













with the subsequent process [LA82]. The SOS technology also produces

dielectrically isolated single-crystal silicon, but it has not been widely accepted because of fundamental material limitations [LA82] thatimpede the realization of high-quality silicon-on-sapphire. The beamrecrystallization SOT technology, which yields large-grain polysilicon (> 1 um), is of practical interest because of the relatively good performance of the devices fabricated with it compared with that of the single-crystal counterpart [LASO; TS81; C083,84]. The as-deposited

LPCVD SOl technology, which produces small-grain polysilicon (< 0.1 um), is also of practical interest because of the circuit applications

[MA84,851 that do not require stringent performance of all the devices, e.g., CMOS memories, and because of the simplicity of the fabrication. Because of the practicality of the last two technologies, it is of primary importance to model the large- and small-grai.n polysilicon SOT

MnSFETs.

Most of the previous research and development of SOl has emphasized

either the technology, i.e., the recrystallization process [LARO; LE81; NG81; TSA81; N1831 or the grain-boundary passivation [KA80; SH84; MA851, or the recrystall ized silicon [GE82; MA82; SC831, i.e., its characteristic defects and grain boundaries. Little work [KA72;

DE80,82; LEV82; COV82,83,84] has been done on the characterization and modeling of devices in large- and small-grain polysilicon SOl films, which is essential if SOl integrated circuits are to be optimally developed.













Such characterization of the large- and small-grain polysilicon SOT MOSFET must include a description of the charge coupling between the front and back gates [LI83b,84a,84b], and must account for the influence of grain boundaries on the electrical characteristics, which is the subject of this dissertation.

The inversion-mode large-grain polysilicon SOl MOSFET, illustrated in Fig. 1.1, presents a relatively good performance compared with that of the single-crystal counterpart [LA80; TS81; C083, 841, but it has the disadvantage of requiring the additional recrystallization step. The accumulation-mode small-grain (as deposited) polysilicon SOl MOSFET, shown in Fig. 1.2, does not require the recrystallization step, but it is inferior to the single-crystal counterpart, especially because of anomalous high leakage current and exceptionally high gate-voltage swing FON82; SH841. To improve the performance of the small-grain SOT MOSFET, for applications that do not require single-crystal silicon device

characteristics (e.g. load elements for a dense static RAM), grainboundary passivation (e.g., via hydrogenation [KA80; SH841) has been successfully used rMA84; MA85]. Unlike the large-grain polysilicon

device, the small-grain polysilicon device can be designed to be operated in either the accumulation- or inversion-mode because the film body (grains) is completely depleted of free carriers, facilitated by grain-boundary trapping.

The purpose of this dissertation is to develop physical models for the effects of grain boundaries in large- and small-grain polysilicon SOT MOSFETs, which are useful for the prediction and optimization of





















VG f . Polysilicon or Metal SiO0


I U


I


Si Substrate


VG b


Fig. 1.1 Cross-section of the four terminal n-channel inversion-mode
heam-recrystallized (large-grain) polysilicon SOI MOSFET.
The -terminal voltages are referenced to the source-voltage
(vs 0 0).


Vs =0


rrnrrimi~~rrrrrni~


Polysilicon Film


.
. ! . . . . . . .
.
. S i.0 * :::::::: .
2:
. . . . . . . . . . . . . . . . .


V)'












































VGb


Pig. 1.2 Basic structure of the four-terminal p-channel accumulationmode LPCVD (small-grain) polysilicon SOl MOSFET.













device performance in SOl integrated circuits. Chapters Two and Three

concern the large-grain polysilicon device, and Chapters Four and Five concern the small-grain polysilicon device. The major contributions made in this dissertation are:

(1) the modeling of the effects of grain boundaries for all

regions of operation in large-grain polysilicon SOT MOSFETs;

(2) the physical characterization of the anomalous leakage

current (OFF state) in small-grain polysilicon SOl MOSFETs;

(3) the numerical modeling of the subthreshold drain current and

the threshold voltage (ON state) of thin-film small-grain

- polysilicon SOT MOSFETs;

(4) the development of the foundation of a charge-sheet model

[BR78,811 for the thin-film single-crystal SOT MOSFET;

(5) the experimental support for the developed models from

measurements of representative SOI MOSFETs.

We derive in Chapter Two a theoretical description of the linearregion drain current of the large-grain polysilicon SOl MOSFET, which is valid for all inversion levels and accounts for arbitrary orientation of the grain boundaries. The corresponding channel conductance shows an effective turn-on characteristic controlled by the grain boundaries that occurs beyond the strong-inversion threshold. Henceforth the carrier mobility threshold voltage, which exceeds the actual one, and the effective carrier mobility, which is typically higher than the actual

(intragrain) one, are defined. For sufficiently high gate voltage, the grain-boundary potential barrier is low enough that the channel













conductance is not significantly influenced by the boundaries. For gate voltages lower than the carrier mobility threshold voltage, the

conductance varies nearly exponentially with the gate voltage and depends strongly on the grain-boundary properties. Grain boundaries

perpendicular to the carrier flow in the channel produce the strongest effects on the conductance. To support this analysis and to stress its practicality, we compare model, predictions with measured currentvoltage-temperature characteristics of laser-recrystallized SOI MOSFETs fabricated at Texas Instruments FLA83]. The theoretical-experimental agreement is good, and in addition to indicating properties of the grain boundaries in these devices, it exemplifies how the mobility threshold voltage and the effective carrier mobility can be easily misinterpreted as the actual threshold voltage and mobility when conventional MOSFET theory is used as the basis for interpreting electrical measurements of SOI MOSFETs. Such misinterpretations can obscure essential criteria for achieving optimal designs of SOI devices and integrated circutis. For example, our physical analysis reveals that in particular cases grain boundaries can actually benefit the SOI MOSFET performance by producing

an unusually high transconductance. This suggests, in contrast to the general belief, that optimal designs may not require elimination of all grain boundaries.
We describe in Chapter Three a physical model for the currentvoltage characteristics of the large-grain polysilicon SOl MOSFET in all

regions of operation. The essence of this model is an accounting for sizable, position-dependent voltage drops across the grain boundaries













that-can occur when the device isdriven out of the linear-region. The carrier transport through the grain boundaries (viz., over potential

barriers-created by carrier trapping) is then nonlinear, and the channel conduction depends ;on how the grain boundaries are distributed between

the source and the drain. Although our model accounts for any number of grain boundaries in the channel, we apply it herein to the most likely case (in beam-recrystallized VLSI) of an SOI MOSFET with only one grain boundary. We emphasize the importance of the position of the grain boundary, as well as its electrical properties, in defining the currentvoltage characteristics. Model calculations, supported by limited experimental results, show that grain boundaries tend to decrease the drain current of large-grain polysilicon SOl MOSFETs, but can increase the transconductance.

We develop in Chapter Four a physical model for the anomalous leakage current (OFF state) in small-grain polysilicon SOl MOSFETs based

on field emission via grain-boundary traps. To support this model, we compare its predictions with measured data from p-channel accumulationmode and n-channel inversion-mode devices FSU84; SH85]. Good correlation is shown, and field emission at the back surface is

suggested as the mechanism underlying the minimization of the leakage current at relatively low values of front gate voltage. Insight

regarding the physics underlying the anomalously strong drain and gate voltage dependences is readily provided by the model, and implies design

criteria to control the leakage current in small-grain polysilicon MOSFETs.












We derive in Chapter. Five a theoretical description., of the. suhthreshold drain current and the threshold voltage (ON state) in the thin-film small- grain polysi.licon S(l. M(ISFET, --which reveals-,the physical.influence of grain boundaries in the channel, and the charge coupling between the front and back gates. The main results of this model, supported by experimental results, are: the gate-voltage swing depends strongly on grain-boundary properties and weakly on the charge-coupling effects; the threshold voltage depends strongly on grain-boundary

properties and charge-coupling effects; the charge-coupling effects decrease as the trap density, the thickness of the film, or the doping concentration increases.

We summarize in Chapter Six the main conclusions and accomplishments of this dissertation. We also suggest in this chapter further related research.
We show in Appendix A that the electron charge trapped at a grain boundary (in an n channel) can be expressed in terms Of the electron quasi-Fermi level for any grain-boundary voltage drop. This result, which was used in Chapter Three, indicates that a previous assumption rRA78aI, which establishes that the charge trapped at the grain boundary is independent of the grain-boundary voltage drop, is generally invalid. In Chapter Three, we have also avoided the use of another classical, but generally invalid assumption [MU61] that a (constant) fraction of the thermionically emitted electrons are captured by the grain-boundary traps.












As a first step towards the development of a practical model for integrated circuit design with SOI MOSFETs, we present in Appendix R the foundation of' a -charge-sheet model -[RR78,81] for the thin-film singlecrystal silicon MOSFET.

In Appendix C we include the computer program used in Chapter Five to calculate the subthreshold drain current and the threshold voltage (ON state) in the thin-film small-grain polysilicon MOSFET. The program is based on a "two-dimensional" bisection method [BU81i that we developed. Although this method is not as fast computationally as Newton-Raphson FBU81], we use it because it avoids the problems of convergence that typically occur when Newton-Raphson [BU81] is applied to complex problems.


















CHAPTER TWO
LINEAR-REGION CONDUCTANCE OF LARGE-GRAIN POLYSILICON MOSFETs



2.1 Introduction

We derive in this chapter a theoretical description of the linearregion drain current of the large-grain polysilicon SOI MOSFET, which reveals the physical influence of grain boundaries in the channel. The corresponding channel conductance is described in terms of the (front)

gate voltage, the device parameters, and the grain and grain-boundary properties. We restrict our analysis to cases in which the polysilicon film is not completely depleted between the front and back surfaces. We

initially assume in Section 2.2 strong inversion, and that the grain boundaries in the channel are perpendicular to the carrier flow; but we generalize the analysis in Sections 2.3 and 2.4 by removing these two as5umptions respectively.

The model comprises the following physics: (a) the quantummechanical description [HS79] of the carrier distribution in the

inversion layer, which implies an average carrier density and its dependence on the gate voltage that can be modeled based on the classical solution [C070; SZ11; (b) the two-dimensional potential

variation near a grain boundary in the channel, which when approximated

by coupled one-dimensional solutions of Poisson's equation defines the













grain-houndary barrier height resulting from carrier trapping [BA78a,b]; and (c) the description of the carrier transport through the grain boundary, assumed to be predominantly thermionic emission over the potential barrier rP1791. To obtain closed-form expressions for the channel conductance, which give physical insight and facilitate the development of SOl MOSFET models suitable for computer-aided circuit analysis, simplifying assumptions are made and justified.

The resulting strong-inversion channel-conductance model of Section 2.2 shows an effective turn-on characteristic controlled by the grain boundaries that occurs beyond the strong-inversion threshold. Henceforth the carrier mobility threshold voltage, which exceeds the actual one, and the effective carrier mobility, which is typically higher than the actual (intragrain) one, are defined. For sufficiently

high gate voltage, the grain-boundary potential barrier is low enough that the channel conductance is not significantly influenced by the boundaries. Thus the intragrain mobility, which can be affected by surface scattering [SU80, controls the conductance at high gate

voltages.

In Section 2.3 we extend the analysis to account for moderate- and weak-inversion levels. For gate voltages lower than the carrier

mobility threshold voltage, we find that the conductance varies nearly exponentially with the gate voltage, and that the gate-voltage swing needed to reduce the conductance by one order of magnitude is strongly dependent on the properties of the grain boundaries.













We account, in Section 2.4 for -arbitrary orientation -of the grain boundaries. This analysis is of interest because of the possibility of controlling [MA8Z; :TSA82; N183; SC83] the predominant -grain-boundary orientation in devices fabricated in recrystallized polysilicon. We

find that grain boundaries perpendicular to the carrier flow in the channel maximize the grain-boundary effects on the conductance. In

contrast, grain boundaries parallel to carrier flow in the channel do not affect the conductance.

To support the analysis and to stress its practicality, we compare in Section 2.5 model predictions with measured current-voltagetemperature characteristics of laser-recrystallized SOl _.MOSFETs fabricated at Texas Instruments FLA83i. The theoretical-experimental agreement is good, and in addition to indicating properties of the grain boundaries in these devices, it exemplifies how the mobility threshold voltage and the effecti-ve carrier mobility can be easily misinterpreted as the actual threshold voltage and mobility when conventional MOSFET theory is used as the basis for interpreting electrical measurements of SOl MOSFETs. Such misinterpretations can obscure essential criteria for achieving optimal designs of SOI devices and integrated circuits. For example, our physical analysis reveals that in particular cases grain boundaries can actually benefit the SOT MOSFET performance by producing an unusually high transconductance. This suggests, in contrast to the general belief, that optimal designs may not require elimination of all grain boundaries.













2.2 Linear-Region Conductance in Strong Inversion

We assume, based on studies [RA78a,b; P179] of majority-carrier transport through silicon grain boundaries at room temperature, that thermionic emission of carriers over the grain-boundary potential

barrier 'Ro underlies the predominant influence of the boundary on the channel conductance of SOI MOSFETs, and that TBo results from carrier

trapping at localized grain-boundary states. The trapping and TBo are characterized by a two-dimensional solution of Poisson's equation in the channel. Before we discuss this solution and the corresponding

thermionic-emission current, we must consider the intragrain carrier distribution in the channel and its dependence on the gate bias, which define 'Bo* We refer to the four-terminal n-channel inversion-mode large-grain polysilicon SOl MOSFET illustrated in Fig. 1.1, and we assume that the grain boundaries in the channel are perpendicular to the electron flow.


2.2.1 Intragrain Electron Distribution in Channel

Because the inversion layer thickness xi is very narrow (on the order of the electron de Broglie wavelength), the true electron

distribution n(x) in the channel (away from grain boundaries) must be described quantum-mechanically FHS791. This description follows from a self-consistent solution of the Schrodinger equation and Poisson's equation. The result differs markedly from the classical solution [C070, SZ81] based on Poisson's equation and Maxwell-Boltzmann statistics: xi is narrower and n(x) is more uniform FHS79]. However the inversion-layer areal charge density,













x.
-0 = q f n(x)dx (2.1)

n 0

where x = 0 represents the Si-SiO2 interface, is predicted well -by the classical solution.

The analyses suggest a simplification in the description of n(x) and its dependence on the (front) gate voltage VGf. We define an

average electron density R over the effective portion of the inversion layer, O x4 Xi(eff), as revealed by the quantum-mechanical solution, but we use the classical solution, ncl(x), to convey the VCf dependence. We find that Xi(eff) is described well by

Xi(eff) cl ocl
qf n (x)dx: -0.9 0 (2.2)
0 n


where Ocl is given by (2.1) with n(x) replaced by nCl(x); that

is, about 90% of the inversion-layer charge is contained within a region

in which n = and in which virtually all the channel current flows. Then we define R by

cl
qnxi(eff) = -0.9 0n (2.3)



Numerical evaluations of Xi(eff) reveal that it is not strongly dependent on VGf, that it decreases with increasing film doping density

NA, and that typically it is quite narrow. For example, when NA =

In16 cm-3, Xi (eff) = 120 A. Corresponding calculations of R defined by













(2.3) are plotted -versus (VGf -- V-rf) in Fig.2.1 for-different values of NA and for an oxide thickness tof of 600 A; VTf is the threshold voltage

: - - .-- .---3 that earrespotds, torthe_ -nset,,of strong- tnverstorIn-[l(o

NAT.- As -implied -by (2.3), Fig. -21 shows -that ff increases with increasing VGf and with increasing NA. We find that Xi(eff) and 5 as defined by (2.2) and (2.3) in terms of the classical solution [C070; SZ81] are generally consistent with the actual electron distribution

given by the quantum-mechanical solution rHS79J.



2.2.2 Grain-Roundary Potential Barrier in Channel

For strong-inversion _conditions_ within the grains, .electron

trapping at localized grain-boundary states produces potential barriers

that - affect the electron transport along the channel. The barrier formation is similar to that. at grain boundaries in bulk polysilicon [R A78b, - F08 21 except '-in the "channel- To is .influenced,. by_ VGf as

described by the two-dimensional form of Poisson's equation.

We consider the potential variation near a grain houndary in the

channel as shown in Fig. 2.2. We assume that away from the grain

boundary (y > yd) the electric field is vertical (in the x-direction), and, n(x) .is well approximated by n .over the effective inversion layer, o( x 4 Xi(eff), as discussed in the preceding subsection. In this

region (I), Poisson's equation simplifies to



x(2.4)

















4 x 1017 3S- x 1017 3 x 1017 2.5 x 1017


1.5 x . . 0.5S x.


VGf - VTf (V)


Fig. 2.1 Calculated average electron density in channel versus (front)
gate voltage for several film doping densities.
















Vs =0 i:
s G f V
!D
re












I-a0
N eff) L _V g +


n+ P








Grain Boundaries



Fig. 2.2 Cross-section of effective inversion layer showing typical
grain and grain boundaries, which are assumed to he
perpendicular to the electron flow.













where T is the electrostatic potential. In the vicinity of the grain

boundary (y < Yd), a horizontal (y-direction) component of the electric field is prdduced-by the electrons trapped at the grain boundary. We

assuine that the trapping nearly depletes this region (II) of free electrons; hence


+ 3 T q NA "(2.5)

ax ayIWe note that this depletion approximation [BA78b; P1791 is valid

provided TBo is sufficiently high: high enough in fact, we assume, that

the grain boundaries significantly affect the channel conductance. We

discuss the validity of this assumption in Subsection 2.2.3.

Assuming that, analogous to the gradual-channel approximation

FSZ81], the trapped electrons at the grain boundary typically create only a small perturbation on the x-component of electric field, we can write


<< (2.6)
a x I ax II ay II


where the partial derivatives are evaluated anywhere in the regions indicated. We justify this assumption by noting that the subsequent solution we obtain is consistent with it when (VGf - VTf) > TFo' which is usually true for strong-inversion conditions. Hence (2.6) implies an approximate solution to the two-dimensional problem defined by (2.4) and (2.5), which is obtained by coupling two one-dimensional solutions.













The corresponding approximation for TB derives combination of (2.4)-(2.6), which yields



SII s


with the boundary conditions


T(x'y = yd) :pl(x)


from the




(2.7)


(2.8)


and


(2.9)


In (2.8) T(x) is the intragrain (region I) potential variation in the channel, which is given by the one-dimensional solution -of Poisson's equation and the Schrodinger equation [HS791. We now identify Yd as the grain-boundary depletion-region width, and we note that our analysis applies only when the grains are not completely depleted. The solution to (2.7)-(2.9) is


T (x,y) II - (y-) + (x)


and hence

-2
qn5yd Ro = UI(x) - '(xO) II= Tn o
S


(2.10)


(2.11)


3T9 Y=Yd















To complete the description of Bo,' we must express yd in terms of known parameters. This expression is implied by the conservation of

charge in the vicinity of the grain boundary:


O :- 2q yd , (2.12)


which equates the areal density of charge trapped at the grain boundary, OGR, to the electron charge density removed to form the (two) adjacent depletion regions. In writing (2.12) we have implicitly assumed that the electrons are trapped within Xi(eff), which is commensurate with our previous assumptions. The trapped charge density depends on the

distribution in the energy gap of localized grain-boundary states

(acceptor-type since QGB < 0) [P1791. It is reasonable to approximate this. distribution by a delta function FBA78b; P179; F082; LUlI],

yielding NST states (traps) per unit area at an energy level ET. Then



0 = I ST_ (2.13)
GR 1 xlE T - E FY=.O
1 +2exp kT

where EF is the Fermi level and the factor of 1/2 reflects the (spin) degeneracy of the localized states. The position of EF relative to ET is defined by YRo and the electron density in region I, i.e., :



[ET E E +-T In( ) (2.14)
FE - Fy=O lT " il + q'Bo - q n-













where Ei is the intrinsic Fermi level (virtually at midgap) and ni is the intrinsic carrier density in silicon.

Thus (2.11)-(2.14) implicitly describe ThBo in terms of the grainboundary parameters NST and (ET - Ei), and of R, which depends on VGf and the MOSFET properties as described in Suhsection 2.2.1. Numerical calculations of TBo are plotted versus (VGf - VTf) in Fig. 2.3 for NA : 1016 cm"3, tof = 600 A , two representative values of NST, 'I011 and 1012 cm-2, and three positions of ET in the energy gap. In all cases, for VGf sufficiently high, TRo decreases with increasing Vrf. This can be explained by noting that under these conditions virtually all the grain-boundary states- (within Xi(eff)) -are filled, ,and hence OGR- :-qNST is independent of VGf. Therefore since R increases with VGf (see Fig. 2.1), Yd concomitantly decreases as described by (2.12), which implies through (2.11) that 'Ro also decreases:


qN T
RO S T (2.1 5)
Ss5


However when VGf is low,'Bo is nearly insensitive to VGf. This is

because the grain-boundary states are not completely filled, and hence EF is near ET, which virtually fixes T Bo as described by (2.14).

We note in Fig. 2.3 that for NST = 1011 cm'2, T8o is less than 10 mV when (VGf - VTf) exceeds about 0.1 V. Thus although our depletion approximation is invalid for these conditions, we surmise that 'Ro is low enough that the grain boundaries do not significantly affect the channel conductance. However for NST = 1012 cm"3, 'Po is high enough,



















































VCf - v.f (V)


Calculated grain boundary potential barrier versus (front) gate voltage for two representative grain-boundary trap
densities and three energy levels. WO note that the low values of 'Ro calculated for N1ST : I0 cm"2 are probably inaccurate because of the invalidity of the depletion approximation (2.5). Nevertheless the curve is useful because it indicates when T3o is low enough that the grainboundary effect on channel conduction is insignificant.


Fig. 2.3













even when (VGf - VTf) is relatively large, to validate the depletion approximation and to strongly influence the channel conductance as we describe in the next section.



2.2.3 Channel Conductance

The physical basis for the influence of grain boundaries on the channel conductance is the interaction between electrons flowing from source to drain and the potential barriers at the boundaries. Although

quantum-mechanical tunneling of electrons through the barrier may be significant at low temperatures FLU81] and diffusion of electrons is important when the barrier is low [C082, 83, 84], we assume (at room temperature) that thermionic emission of electrons over the barrier T co is the predominant grain boundary transport mechanism [P179). Then

if the drain voltage VD is low enough (linear region) that the voltage drop across a grain boundary Vgb is much smaller than 2kT/q, and if TRo > kT/q, the emitted current density is [BA78b]


qA*T exp( kT n V (2.16)
gb kNC e gb


where A* is the effective Richardson constant [SZ81] for electrons (- 250 A/cm2/K2) and NC is the effective density of states in the conduction band (- 2.9 x 1019 cm-3 at 300' K).

Since the current in the channel is continuous from source to

drain, the drain current ID can be expressed by the integral of (2.16) over the (effective) cross-sectional area of the channel:














I D :Z xi(eff) Jgb (2.17)


where Z is the channel width. The combination of (2.16) and (2.17)

gives ID as a function of Vgb. To obtain ID as a function of V we

simply equate the sum of the voltage drops along the channel to Vn. If we assume that the channel comprises N grains of equal length yg

separated by (Ng - 1) identical grain boundaries (see Fig. 2.2), then


VD =(Ng -l)Vgb + N V (2.18)
gb gg


where V is the voltage drop across a grain, which assuming that the carrier transport in the grain is by drift [SZ81] is


Vyq - yd (2.19)
Yg nY
Vg 31, ng 1Qn I ID(219


in the linear region. In (2.19) ung is the intragrain electron

mobility, the dependence of which on VGf and on device parameters can he

given empirically [SU80].
Combining (2.3) and (2.16)-(2.19), we obtain IF(VGf,VD) for the SOT MOSFET in the linear region (V < (Ng - 1) 2kT/q). If we assume that Yg " Yd, which is valid in typical recrystallized SOl MOSFETs, then our result simplifies to

Z
~ -J-qIlOnlVn
ID ng V (2.20)
1 + (Ng-) kN'n4nq exp Ro(V f) (2.20
0. 9LA*T kT 1















where L = Ngyg is the channel length. In (2.20) On is given by the

strong-inversion condition


-Qn Cof(VGf - VTf) , (2.21)



where Cof is the (front) gate oxide capacitance.

The influence of the grain boundaries on ID is reflected by the second term in the denominator of (2.20), which depends of VGf through

Bo[f(VGf - VTf)] as described in Subsections 2.2.1 (Fig. 2.1) and 2.2.2 (Fig. 2.3). If the number of grains N constituting the channel is one, vis-a-vis, if there are no grain boundaries in the channel, then (2.20) reduces to the corresponding result of conventional MOSFET theory FSZ81I. Furthermore if T'Bo is sufficiently low, because of low NST and/or high VGf (see Fig. 2.3), then the same result obtains. We note that (2.20), which because of the model assumptions is strictly valid only when TRo > kT/q, will correctly give the conventional current at high VGf only if the pre-exponential coefficient is much less than unity. With this insight then, (2.20) facilitates a self-consistency check for our model assumptions (2.5) and (2.16). We find that when the grain boundaries are influential, TBo is generally high enough that the assumptions are valid.

In deriving (2.20) we have neglected thermionic field emission (tunneling) through Ro, and we have ignored the possible existence of a significant grain-boundary scattering potential barrier [LU81 through













which the electrons must tunnel to traverse the boundary. The tunneling can be predominant at low temperatures, but at room temperature and above it is generally insignificant [P179; LU81]. We also neglected

diffusion of electrons through 'Bo, which is important only when 'Ro is low rC083]. When TBo is high enough that the grain boundaries significantly affect ID, the diffusion can be ignored.

To illustrate the grain-boundary effects described by (2.20), we

plot in Figs. 2.4 and. 2.5 calculations of the linear-region channel conductance (gA ID/V)) versus (VGf - VTf) for several values of Ng and NST. In Fig. 2.4 we let Ng vary from one to 200 grains, and we use typical-. values for the remaining parameters: NST = 101.2 cm2 .at ET = Ei; NA = 1016 cm-3, tof = 600A , Z = L = 40 um; we also specify a (front) fixed oxide charge density Off = q(1011 cm"2), which defines i ng and its dependence on VGf ISU80]. We see that as Ng increases, g decreases and the plots become inflected, in general accord with recent measurements of laser-annealed SOT MOSFETs [LE81; C0841. The plots show apparent threshold voltages that are higher than VTf and transconductances (gm m ID/'VGf = VP9g/ VGff) that imply effective electron mobilities (via the conventional MOSFET theory [SZ81]) which can differ from i ng. The apparent threshold voltage is actually a '.'carrier mobility threshold voltage" (V ) at which n becomes high enough that'TRo begins to diminish with increasing VGf (see

Fig. 2.3) as described by (2.15). For VGf >> V, Ro is too low to

significantly affect If); that is, theT 'Ro term in (2.20) is negligible, and gm is defined hyu ng. Note however in Fig. 2.4 that the plots for














































.0 1.5
VGI -VTf (V)


Fig. 2.4 Calculated linear-region channel conductance versus (front)
gate voltage for several numbers of grains constituting the channel. The broken portions of the curves for Ng=20, 100, and 200 are inaccurate because of the invalidity of (2.2n) as discussed in Subsection 2.2.3. The N 4 I curve is
inaccurate for VGf near VTf because of the invalidity of the
strong-inversion relationship (2.21).












9 x 10-5


8 x 10-5


7 x 10-9 6 x 10-5 ,5 x 10-5 4 x 10-5 3 x10-5



2xiO


10- 5




0


VGf - VTf (V)


Fig. 2.5 Calculated linear-region channel conductance versus (front)
gate voltage for several grain-boundary trap densities.













N very large become erroneous when VGf >> V because, as we discussed previously, the pre-exponential coefficient in (2.20) is not much less than unity. When V f > V , g is typically higher than that
11
corresponding tO u ng. We stress that the high effective electron mobility implied by gm is defined predominantly by the properties of the grain boundaries. Measured ID(VGf,VD) characteristics of SOl MOSFETs can thus be misleading because of the nonlinear effects of grain boundaries as we discuss in the next section.

Additional calculations reveal that V depends on NA and tof; it
11
decreases with increasing NA and it increases with increasing tof. These dependences reflect, for a given (VGf - VTf), the dependences of Fn, which controls Ro, on NA shown in Fig. 2.1 and on tof implied by -0n Cof.

The plots of g versus (VGf - VTf) in Fig. 2.5 for NST ranging from loll to 2 x 1012 cm"2 were calculated from (2.20) for the same device parameter values used to derive the plots in Fig. 2.4. We let Ng = 2 (one grain boundary) to simplify the physical interpretation of the results. The same type of inflection seen in Fig. 2.4 is noted in Fig. 2.5 for NST > l0l cm-2. For the device considered, if NST is much lower than 1012 cm- 2, the grain boundary is virtually ineffective; whereas if NST is higher than 1012 cm"2, the grain boundary severely affects (lowers) the channel conductance. Similar calculations have been made for different values of ET. In this case of the n-channel MOSFET, we find that as ET approaches the conduction-hand edge, T RO diminishes and the grain boundary becomes ineffective. As ET













moves towardmidgap and below, the grain-boundary effect materializes as indicated in Fig. 2.5. This dependence on ET reflects the electron

occupancy of the grain-boundary states, which has been described elsewhere FF082]. These results for a monoenergetic trap density could be used to infer corresponding results for different trap distributions in the energy gap.



2.3 Linear-Region Conductance in Moderate Inversion

To extend the analysis described in Section 2.2 to the moderate inversion region of operation, we must remove the strong-inversion approximation (2.21). If the polysilicon film is not completely depleted between the front and back surfaces, we can neglect the chargecoupling effects [BA8O; LI83b]. Then for all inversion conditions

[TSI82],



0n =0s -0b (2.22)



where

qP n 2 1/2
r T -A F-) (2.23)


is the (areal) charge density in the silicon and


- _qP f 1/2
0 : -0 r-- i (2.24)
r KT













is the depletion-region charge density. In (2.23) and (2.24), *sf is the front hand bending and Or = [2kTesNA]I/2 has been defined to make a compact notation. The relationship between 'sf and VGf is defined by


f - 05 qNsf
Gf VFR : - C C sf
o~f of

where V f is the front-gate flatband voltage [N182], which includes a
FR
contribution from fast surface states at the Si-SiO2 interface, the density Nsf (cm2eV-1) of which is assumed to be uniform in the energy gap. The On(VGf) dependence in (2.20) is now defined by (2.22)-(2.25).

.To illustrate the grain-boundary effects in moderate inversion described by (2.20) and (2.22)-(2.25), we plot in Fig. 2.6 and 2.7 calculations of the linear-region channel conductance versus VGf for several values of ET and Nsf. To facilitate a later comparison between

experimental and theoretical results (see Section 2.5.2), we set VTf 0, which defines Vf through (2.25). In Fig. 2.6 we let (ET-Ei) vary from 0 to 0.22 eV, and we use typical values for the remaining parameters: NA = 2xl016cm-3, which implies Xi(eff) = 80A, .1ng 380 cm2/v-sec, tof = 600 A , Z = L = 40 u m, NST = I012cm'2, and Ng = 50. We see that the conductance presents a nearly exponential dependence on

Vf for the lower-Vr~f(> 1).










1-4


0 .2 .4 .6 .8 1.0 1.2 1.4




Fig. 2.6 Measured (points) and calculated (curves) linear-region (VO
50 mV) conductance versus front-gate voltage of an n-channel SOI MOSFET in laser-recrystallized polysilicon at room temperature. The measurements were made with the hack gate biased at -40 V. The calculations were done for different grain-boundary trap energy levels as indicated and with the fast surface-state density at the front Si-SiO2 interface
equal to zero. Note that VTf = 0 V.


















































VG f (V)


Fig. 2.7


Measured (points) and calculated (curves) linear-region (VD : 50 mV) conductance versus front-gate voltage of an n-channel SOl MOSFET in laser-recrystallized polysilicon at room temperature. The measurements were made with the hack gate biased at -40 V. The calculations were done for different fast surface-state densities at the front Si-SiO2 interface as indicated and with the grain-boundary trap energy level at
0.2 eV above midgap.













The plots of g versus VGf in Fig. 2.7 for Nsf ranging from 0 to 5 x 10ll cm-2eV-1 were calculated for (ET-Ei) = 0.2 eV and the same remaining parameters values used to derive the plots" in-Fig. 2.6. We see that S is nearly independent of Nsf although g decreases as Nsf increases.

We conclude this subsection by stressing that the drain current in the lower-VGf, or "submobility-threshold" (VGf < V) regions of operation, presents a nearly exponential dependence with respect to VGf,

and that the gate-voltage swing needed to reduce ID by one order-ofmagnitude is strongly dependent on the properties of the grain

boundaries.



2.4 The Significance of Grain Boundary Orientation

The studies in Section 2.3 and 2.4 have been based on the assumption that the grain boundaries are perpendicular to the carrier flow in the channel. In this Section, we generalize the analysis to account for arbitrary orientation of the grain boundaries. This

generalization is of interest because of the possibility of controlling

IMA82; TSA82; N183; SC831 the predominant grain-boundary orientation in devices fabricated in recrystallized polysilicon.

We consider a (straight) grain boundary arbritrarily oriented in the channel as shown in Fig. 2.8. The drain current can be expressed, to first order, as


in = Ilf + I D(


(2.26)






















H L


grain boundary

























Fig. 2.8 Illustration of arbitrary grain-boundary orientation in
channel.













where IDf is the component that flows in the grain-boundary-free portion (Z-Zb) of the channel and IDh is the component that flows in the portion

(Zb) containing the grain boundary. Note in Fig. 2.8 that Zb is defined by Z and L, and a , the angle between the grain boundary and the z-direction. In the linear region (strong inversion),


(Z-Zb)
l ff L ngCof(VGf - Tf)VD "(2.27)


The characterization of I Ob depends on a complicated twodimensional electron transport problem. To derive a crude

approximation, we assixne that the electron current density Jgb through the grain boundary (via thermionic emission) is perpendicular to it. Then, analogous to (2.16),


qA*T e p Bn
gh exp(- kT (2.28)


where n = cos(0 )y - sin(e )z is the unit vector normal to the grain boundary. We further assume that away from the grain boundary the electrons flow predominantly in the y-direction. Then to ensure current continuity from source to drain, we must have



Zb (.9
flb =cos 6 Xi(eff) n * Jgh " (2.29)













Using (2.28) and (2.29) and following the derivation in Section 2.2, we obtai n

Zb
_ U n g C of (V Gf-VTf )V 0
Db + cxp . (2.30)
1 ep.9LA*T xc

The combination of (2.26), (2.27) and (2.30) then describes approximately, for strong-inversion conditions in the linear region, the significance of the grain-boundary orientation illustrated in Fig. 2.8. The cos(e) in (2.30), as well as the Zb(e) dependence, convey this significance. If e > 00, then Zb < Z and the grain-houndary effect

is ameliorated. If 6:= .90' (grain boundary parallel to electron flow), then Zh = 0 and the grain boundary does not affect the channel

conductance (although it may enhance source-drain leakage current via other mechanisms).



2.5 Experimental Support and Discussion

To support the analysis in this chapter and to identify critical aspects of it with regard to SOl device and integrated circuit design, we measured linear-region In(VGf,VD,T) characteristics of four-terminal SO1 MOSFETs (n-channel) fabricated at Texas Instruments [LAR3]. The

polysilicon film is 0.5 um thick and was laser-recrystallized after being deposited via LPCVD on a 1-um-thick layer of silicon-dioxide,

which had been thermally grown on a silicon substrate. The film was

doped by ion implantation of boron that yielded N A = 2 x 1016 cm3 near the front surface and NA~ 1015 cm-3 at the back surface [LAR3].













The front gate is n+ polysilicon and Cof = 5.8 x 10-8 F/cm2 Of
(tof = 600 A). Large devices (Z = L = 40 um) were selected to preclude small-geometry effects [AK82].

To avoid complications due to the charge coupling between the front and hack gates [LI83b], a high negative voltage (- 40 V) was applied to

the back gate to ensure accumulation at the back Si-SiO2 interface and to fix VTf. The Io(VGf) dependence was measured with VD := 50 mV at three temperatures (240 C, 70' C, and 1000 C).


2.5.1 Support for the Strong Inversion Analysis

The corresponding channel conductance characteristics g(V~f,T) of a

particular device, which typify the characteristics of identically processed devices, are plotted in Fig. 2.9. The basic shape of these plots is the same as that of the theoretical curves in Figs. 2.4 and 2.5, which implies qualitative support for our analysis. (The

experimental curves and Figs. 2.4 - 2.5 should not be compared quantitatively because the parameter values used in the calculations are not necessarily the actual values.)

The support for (2.20) is demonstrated by examination of the measured g(VGf,T) characteristics within particular ranges of Vrf. For high VGf (> V), g is defined by the numerator of (2.20); the grainboundary effect is negligible. Thus as in the case of conventional

MOSFETs [SZSII, the carrier mobility (Ing) follows from the slope of g(VG'f), i.e., from gm, and the threshold voltage (VTf) is given by the
























4 x 10-0 7 6
3 x 10-5



2 x 10- 5



10-



0
0 0.5 1 1.5 2 2.5
VG (VI


Fig. 2.9 Measured linear-region channel conductance. versus (front)
gate voltage of n-channel SOI MOSFET in laser-recrystallized polysilicon [LA83] at three temperatures. The threshold
voltage is fixed by the back-gate voltage [LI83b], which was
set at -40V to ensure accumulation at the back Si-SiO2
interface.













linear extrapolation of the characteristic to the VGf axis. From

Fig. 2.9 we thereby get VTf: 0.10 V and Ung 380 cm2/V-sec at 240 C.

This vaiue ofPng is low, and hence implies excessive scattering at the polysilicon surface, due possibly to high Off [SUSO]. The low Ung does

not reflect decreased transconductance due to a high surface electric field FSUSO, which we observed only at values of VGf higher than those

in Fig. 2.9. These interpretations are supported hy the temperature dependence of g in the high-VGf region. We see in Fig. 2.9 a weak

dependence of VTf on T and a negative temperature coefficient for png, which are consistent with the g(T) characteristics of conventional

silicon MOSFETs [LE81; GA75]. 7

We see from Fig. 2.9 that VTf is considerably less than the electron mobility threshold voltage V . Thus there is a significant range of VGf (VTf< VGf < ) in which the grain boundaries suppress

In. In this case the TBo term in (2.20) is much greater than unity, i.e., Vgb >> Vg, and hence g- exp(-OyBo/kT). As long as VGf < VU, TBo is high and does not vary significantly with VGf (see Fig. 2.3). The positive temperature coefficient for g thus predicted is consistent with the measured conductance plotted in Fig. 2.9 in this region.
When VGf > , 'Ro decreases with increasing VGf (see Fig. 2.3), and hence g increases. To analytically describe this increase and to estimate V we use the approximate T8o(n) dependence in (2.15) and the strong-inversion relationship (2.21). The cnmbination of (2.15), (2.20), and (2.21) yields a g(VGf) characteristic that exhibits an inflection point where gm is maximum. The theoretical and experimental













plots in Figs. 2.4, 2.5 and 2.9 imply that this maximum is broad. Therefore we approximate the actual characteristic by the linear function


Z C( (2.31)
g n(eff)Cof(VGf - V )


which is tangent to the actual g(VGf) curve af the inflection point. This function then analytically defines A/ and the effective fieldeffect electron mobility1ln(eff) due to the grain boundaries.

The value of VGf at the inflection point is defined by equating to zero the ,second derivative of (2.20) with respect to VGf, using (2.3), (2.15), and (2.21). We find that at this value, the denominator of (2.20) is two. Thus (2.31) describes the tangent to g(VGf) at the point where the TFRo term in the denominator of (2.20) is unity. This tangent yields (for Ng > 1.)
9 q3 x N2
q xi(eff) ST
8kTe sCo
V = V f+ 8 es Cof (2.32)
n 0.9A*TL
kNe ng (Ng-1)

and



ng { 2+1n 0.9A*TL ) (2.33)
Un(eff) 4 { +I kN &ng (Ng-Il



We note that the weak dependence of xi(eff) on VGf has been ignored in the derivation of (2.32) and (2.33). Thus Vu in (2.32) is evaluated by assuring a representative value for xi(eff), which depends on NA as













discussed in Subsection 2.2.1. We stress that (2.32) and (2.33), which are based on analytic simplifications of our more general analysis

described in Section 2.2, are merely estimates of V and pn(eff)"

However they are useful in describing the functional dependences of g and gm on device parameters and temperature, and hence will facilitate SOI MOSFET design and computer-aided SOI circuit analysis.

We see from (2.33) that the effective electron mobility is

typically higher than u ng depending on L, Ng. and T. The measured

g(VGf) characteristics plotted in Fig. 2.9 when interpreted using (2.31) yield p n(eff) 530 cm2/V-sec at 240 C, which is considerably higher than ung. The negative temperature. coefficient for in(eff) implied by the data in Fig. 2.9 is consistent with (2.33), which shows that the temperature dependence is defined primarily by that of ung" Using the

measured value of u n(eff) mentioned above and (2.33), we find that Ng 50 grains. Since L = 40 um, this implies a crude estimate of about 1 um for the average grain size (yg), which is not unreasonable for the laser-recrystallized polysilicon film rLA83]. We note finally that the dependence of u n(eff) on L suggested by (2.33) is consistent with measurements FNG81] of (effective) electron mobility in laserrecrystallized MOSFETs having different channel lengths. For a given Yg (=L/N with Ng > 1), un(eff) increases as L is reduced from many times yg toward yg.

The electron mobility threshold voltage as described in (2.32) is strongly dependent on NST and T, as well as on NA through VTf FLI83h]

and Xi(eff). The inverse dependence of Xi(eff) on NA described in













Subsection 2.2.1 implies that the difference between V,, and VTf

decreases as NA increases. The predicted direct dependence on NST is

consistent with observed decreases in the (apparent) threshold voltage of polysilicon MOSFETs resulting from hydrogenation [KA80], which is

known to reduce NST. The inverse dependence of V on T suggested by (2.32) is corrohorated by the measured g(VGf,T) data plotted in Fig. 2.9. At 240 C, the measurements when interpreted using (2.31) imply V = 0.55 V, whereas VTf 0.10 V. The difference between Vu and VTf, based on (2.32), indicates that NST: 1 x 1012 cm-2 (where the

traps are near midgap).

We conclude -this -subsection bY -stressing two significant conclusions drawn from it. First, because (2.31), which is of the same

form as the linear-region conductance expression for the conventional MOSFET FSZ81I, empirically describes well an appreciable region of the g(Vrf) characteristic for the SOI MOSFET, V. and un(eff) can be easily misinterpreted as VTf and Ung. Such misinterpretations, which evidently

have been made in some previous work., can lead to misconceptions regarding SOI and can impede the development of optimal SOI devices and integrated circuits. Second, even though grain boundaries are effective in defining the channel conductance of SOI MOSFETs, the transconductance

can be higher than that of the conventional counterpart; the grain boundaries are actually beneficial in this regard. Thus perhaps optimal

designs of SOl MOSFETs may not require complete elimination of grain boundaries.












14 t5$o'port for the Moderate Inversion Analysis

-In-.subsection 2.5.1 we estimated, for a typical device, that the

hr d voTtage- defi ne-d by the linear extrapolation-6f the measured'
14(V i 0 - liHn the grain boundaries are insignificant (VGf >> V ) is Tf 0. 1 V, and that the electron mobility defined by the slope of the extrapolation is p ng 380 cm /V-sec. From g(VGf) that is affected by

Ith-e �r~in boundaries (VGf > V ), we measured, based on our model, V = 0.5 V, NST= 1012 cm-2 (for ET assumed to be at midgap), and N 9-="50. -Note that typically Vf = VTf + nkT/q with n = 3-5 depending on NA and Cof [TS82b]. Thus our strong-inversion measurements imply Vf- which is consistent with calculations based on (2.22),- (2.25).

*We stress -that the difference between VT and Vjf can be ignored for the

strrng-in-Vrsion analysis because (VGf - VTf) >> kT/q.

" T4ep1bt in Fig. 2.6 the g(VGf) characteristic of a typical device mIea.sured--a.a room temperature. Note especially the lower-VGf (< V )
-'-data,iWich show a nearly exponential dependence on VGf. For comparison we also show in Fig. 2.6 theoretical g(VGf) curves that were numerically derived from (2.20) and (2.22) - (2.25) using the parameter values given

above -and NA = 2 x 1016 cm-3. We varied ET and let Nsf = 0, which

= -f-rom7f =) and (2.25) implies Vf =-1.9 V. The calculated g(VGf) .c.iiaa-teristics also are nearly exponential for low VGf, even though the

inversion level is not weak. (In weak inversion, the conductance of single-crystal MOSFETs is exponentially dependent on the gate voltage because On is [TS82h; S14721.) This dependence is due primarily to the exp(qTBo/kT) term in (2.20) as implied by the strong dependence of S













('i.e.-, the inverse slope) on ET. As ET moves from midgap (= Ei) toward the conduction band, S increases; when (ET-Ei) = 0.2 eV, the measured S is'-mo'deled Well. -Thus 'the energy level of the grain-boundary traps significantly affects the channel conductance below the electron mobility threshold (VGf < V )

We illustrate in Fig. 2.7 the effect of Nsf on the g(VGf)

characteristic. The theoretical curves plotted were derived using the same parameter values for Fig. 2.6 and (ET-Ei) = 0.2 eV. For each value of Nsf, VfB was calculated from (2.25) using VTf . Increasing Nf tends to suppress the conductance for intermediate values (_ V ) of VGf, but does not significantly affect S. By comparing the calculated curves with the measured data, we crudely estimate that Nsf 10 cm-2eV1.

Measurements at different temperatures (T = 240C, 70'C, and 100'C) indicate that, for intermediate VGf, both g(VGf) and S increase with increasing T. As T increases from 240C to 100'C, S increases from 0.25 V/decade to 0.34 V/decade and, at VGf = V = 0.5 V, g increases 1V
from 1.3 x 10-6 u to 4.5 x 10-6u . These changes.are consistent with (2.20) in which, for relatively low VGf, the exp(qiBO/kT) term defines the predominant dependence on temperature.



2.6 Summary

A physical model that describes the effects of grain boundaries on channel conductance in SOl MOSFETs has been developed and supported experimentally. These effects originate when electrons (n-channel MOSFET) are trapped at localized grain-boundary states, thereby creating













potential barriers that influence the flow of electrons from source to drain. The electron trapping depends on the degree of inversion in the channel and hence on the gate voltage. For sufficiently high Vf Bo is low enough that the grain boundaries are inconsequential with regard to g and gm" However for lower VGf, the grain boundaries can

predominantly control g and gm and can define: (a) an effective turn-on (linear-region) characteristic that occurs well beyond the stronginversion threshold as illustrated in Figs. 2.4 and 2.5; and (b) a nearly exponential dependence with gate voltage, as shown in Figs. 2.6 and 2.7, for moderate inversion conditions.
7 .The effective turn-on characteristic, described generally by (2.20) and approximated by (2.31), is actually a reflection of the "carrier mobility turn-on", which is controlled by the grain boundaries. it

defines the electron mobility threshold voltage V, which exceeds VTf, and the effective electron mobility l1n(eff), which is typical-y higher than the actual (intragrain) mobility ung. Evidently measurements of V. and un(eff) have been previously misinterpreted as determinations of VTf. and ung. Subsequent erroneous conclusions regarding SOT can inhibit the development of optimal SOl devices and integrated circuits, which, based on our analysis, possibly need not nor should not be completely void of grain boundaries.

For moderate-inversion conditions, the drain current, which is controlled by the grain boundaries, varies nearly exponentially with gate voltage and the gate-voltage swing needed to reduce the drain current by one order-of-magnitude depends strongly on the properties of













the grain boundaries, especially the grain-boundary trap level, and on the properties of the Si-SiO2 interface, i.e., the fast surface-state density.

Grain boundaries perpendicular to the carrier flow in the channel maximizes the grain-boundary effects on the conductance as described by (2.30). In contrast, grain boundaries parallel to carrier flow in the channel does not affect the conductance.(although it may enhance sourcedrain leakage current via other mechanisms).



















CHAPTER THREE
CURRENT-VOLTAGE CHARACTERISTICS OF
LARGE-GRAIN POLYSILICON MOSFETs



3.1 Introduction

In this. chapter, we describe extensions of our previous work that yield a physical model for the steady-state current-voltage characteristics of the large-grain polysilicon SOl MOSFETs in all

regions of operation. The essence of the extensions is an accounting for sizable, position-dependent voltage drops across the grain

boundaries that can occur when the device is driven out of the linear region. The carrier transport through the grain boundaries (viz., over potential barriers created by carrier trapping) is then nonlinear, and the channel conduction depends on how the grain boundaries are distributed between the source and the drain. Although our model

accounts for any number of grain boundaries in the channel, we apply it herein to the most likely case (in beam-recrystallized VLSI) of an SOI MOSFET with only one grain boundary. We emphasize the importance of the position of the grain boundary, as well as its electrical properties, in defining the current-voltage characteristics.

As in the previous chapter, we assume that thermionic-emission theory adequately describes the carrier transport over the grainboundary potential harriers. Unlike the previous chapter, the use of













the thermionic-emission theory is not well established because the applied voltage to the grain boundary is much greater than 2kT/q. The previous analyses [MU61; BA78b] of this problem for polysilicon resistors are based on assumptions which are generally invalid, e.g., that a (constant) fraction of the thermionically emitted electrons are captured by the grain boundary traps FMU61], or that the charge trapped

at the grain boundary is independent of the grain-boundary voltage drop [RA78a]. The former assumption is invalid because the rate of the bandto-trap recombination process is proportional [SZ81] to the concentration of unoccupied traps and not to the current. The latter assumption is -invalid because the charge trapped at the grain boundary can be expressed (see Appendix A) in terms of the electron quasi-Fermi level, and therefore, it depends on the grain-boundary voltage drop. We avoid the use of these invalid assumptions by using the physically reasonable approximation that the electron quasi-Fermi level is nearly flat on the emitting side of the grain boundary.

These potential barriers, which result from trapped inversion-layer charge, decrease with increasing inversion level, and hence are modulated by the gate voltage and vary along the channel when the drain voltage is high. Consequently grain boundaries near the drain, where the inversion level is weakest, are most influential. To properly

account for the inversion-level dependence, we necessarily base our

analysis on a MOSFET model [RR78, 81] that is applicable for all inversion levels.













Model calculations, supported by limited experimental results, show that grain boundaries generally tend to decrease the conductance (drain current) of SOl MOSFETs, but can increase the transconductance. Grain boundaries having a trap density comparable to that (~1012 cm-2)

estimated for typical high-angle boundaries in beam-recrystallized SOl can, when located near the drain, significantly affect the currentvoltage characteristics of the SOl MOSFET in all regions of operation. The grain-boundary effect is enhanced as the channel length is shortened.


. . .3.2 Analysis

We refer to the n-channel, enhancement-mode large-grain polysilicon SOl MOSFET illustrated in Fig. 1.1. To emphasize the grain-boundary

effects, we assume that the polysilicon film' is not completely depleted between the front and back surfaces so that charge-coupling effects FLI83b] can be ignored (vis-a-vis, the back gate is inconsequential).

We initially assume that the (front) channel comprises Ng grains separated by (Ng - 1) identical grain boundaries (surfaces) perpendicular to the carrier (electron) flow. Later we analyze the

likely case of a single grain boundary in the channel (Ng = 2), emphasizing the importance of its position. The energy-band diagram at the jth [1< j < (N - 1)1 grain boundary, counted from source to drain, is illustrated in Fig. 3.1 for the cases of zero drain voltage (VD) and of VD > 0. When VD = 0, electrons trapped at localized grain-boundary states produce the potential harrier 'Bo (at each grain boundary), which













q B


Ev







EC
EFn .


electron energy J~L4J30


EFn


, jth grain boundary





(a) VD=O t electron energy


(b) VD:-O


Fig. 3.1 Energy-hand diagram at jth grain boundary for drain voltage
equal to (a) and greater than (b) zero.







53




is determined by the inversion level, vis-a-vis, the I. (front) gate voltage VGf, as we described in the previous chapter. When VD > 0, a voltage Vgbj is -dropped- -across--the jth grain boundary, skewing the energy-hand diagram as illustrated. If Vghj is large enough, it

produces significant changes in the (areal) density of charge OCRj trapped at the grain boundary and in the inversion levels in the

adjacent grains.


3.2.1 Formalism

From Fig. 3.1, for VD > 0,



11 r
Vgbj =@ -j +Bj -Bj(.1



where Tj rnd i are the potential barriers on the left and right sides of the jth grain boundary, and l and j are the electron quasi-Fermi potentials in the left and right adjacent grains. The average electron densities in the adjacent inversion layers are



n niexp(qp /kT) (3.2)


Fr : niexp(qp r/kT) (3.3)



where ni is the intrinsic carrier density in silicon. The densities in (3.2) and (3.3) are related to the inversion layer (areal) charge densities On on the left and right by (2.3).












The electron transport is controlled by the gate and drain voltages through the dependence of On on VGf and VD. To characterize this

dependence, as well as the intragrain current, we use the charge-sheet model [rBR78, BR81], which is applicable for all levels of inversion. At an arbitrary (intragrain) point y in the channel,


0n(Y) = (Y) - b(Y) (3.4)


where

_rc sf (Y) n i2 ryS( VY]1/
0s(Y)- kT - I + (-rA)2expF.Fsf(y) V(y)]]}112 (3.5)


is the charge density in the silicon and c- sf(y) 1/2

Obh(Y) -Qr- kT 1] (3.6)


is the depletion-region charge density. In (3.5) and (3.6), Tisf is the
band bending (normal to the front surface), V is the difference between the electron and hole quasi-Fermi potentials [V(O) = 0, V(L) = V0 where L is the channel length], and Or = [2kThsNA]1/2. The band bending is related to VGf by


0s(Y) = -Cof[VGf - vf -f f(y) (3.7)













To complete the description of the energy-band diagram in Fig. 3.1, we ensure that charge is conserved in the vicinity of the grain boundary



S 2: IBj /2s Bj (3.8)


which equates the charge trapped at the jth grain boundary to the electron charge removed to form the adjacent depletion regions. (We

assume the regions are virtually depleted of free electrons.) Because the inversion layer is void of holes, the electron capture and emission

rates for the grain-boundary traps must be equal in the steady state, and hence OGj can be expressed in terms of the electron quasi-Fermi level EFnj at the jth grain boundary (see Appendix A):


0 ~-qN ST(39
OGBj 1 +1exp(ET-n . (3.9)
I +- 2 - )

In (3.9), (ET-EFni) depends on Vgbj as suggested by Fig. 3.1. This dependence is, in general, complicated and can be defined only when the

electron transport mechanism(s) is specified. Although many theories regarding carrier transport through grain boundaries have been purported

(e.g., thermionic emission, diffusion, thermionic field emission), none can be verified unequivocally because of the complex, variable nature of the grain boundaries. Thus to avoid undue model complexity, we assume, as in the previous chapter, that the predominant transport mechanism is thermionic emission over the potential barrier. This simplifying

assumption is physically reasonable at and above room temperature where













thermionic field emission is not probable, and for substantial (nontrivial) barrier heights, which render diffusion less significant. The thermionic-emission model, which in fact has functional dependences similar to the diffusion model, is further consistent with the depletion

approximation, and hence with it yields insightful results commensurate with the uncertain nature of the grain boundaries.

Referring to Fig. 3.1, we note that if there is a net left-to-right transport of electrons predominantly by thermionic emission, then EFn

can be assumed to be nearly flat on the left side of the grain boundary; Vgbj is dropped predominantly on the right side where the (net) emitted electrons drift away from the grain boundary. Thus in (3.9),. .



E E ) (E E1 +q1 (.0
T Fnj T Ei) - + Bj(3.10)


where (ET-Ei) gives generally the position of the traps in the energy gap. We stress that dEFn/dy at the grain boundary is not related to the current because of the assumptions that the carrier transport is

described by thermionic emission theory and not by diffusion theory.

We have now described, in (3.1) - (3.10), how the energy-band

diagram at a grain boundary changes to reflect the voltage drop Vgbj. Ry using physically reasonable approximations, we have avoided the use of a classical, but generally invalid assumption [MU61] that a (constant) fraction of the thermionically emitted electrons are captured by the grain-boundary traps. This commonly used assumption in fact

overly defines the grain-boundary transport problem because the rate of













the-band--to-trap recombination process is proportional [SZ81] to the concentration of unoccupied traps and not to the current. We have

furthermore- not used another common assumption [BA78a] that QGBj is independent of Vgbj, which is also generally invalid as indicated by


Our model for the steady-state current-voltage characteristics of

the large-grain polysilicon MOSFET is completed by: (a) equating the drain current I to the net thermionic-emission current defined by the perturbed energy-band diagram at each grain boundary; (b) equating In to the current defined by the charge-sheet model [BR78] applied to each 9rjatd-(c) summing all the grain-boundary and grain voltage drops to

VD.

The net thermionic-emission current density over the potential

harrier at the jth grain boundary (Fig. 3.1) is [BA78b]


1*T 1
. -.g b . . A*T2 I e - - njexp(- __ )]q (3.11)



where A* is the effective Richardson constant for electrons in silicon . 25 A/cm2-K2) and NC is the effective density of states in the .---onduction-band (- 2.9 x 1019 cm-3 at 300�K). Thus for all j,



I D = ZXi(eff) gbj (3.12)


where Z is the channel width. We assume xi(eff) (-i00 A) is constant, independent of position and bias; n reflects changes in the local












channel conductivity. With (2.3) and (3.1) - (3.10), (3.11) and (3.12) relate ID to Vgbj for the (Ng - 1) grain boundaries.

Using the charge-sheet model [BR78], we now express ID as a

function of the band bending at the left and right sides of each grain. For the kth (1< k< N ) grain with length Ygk (L = Ygl +
+ YgN ),

ID Z kTp n r ) (
I q Cf { kT(V f r 1 q r 2
D 2q ofE3 of " sfk (3 .3kT)sfk



1(I 2 2 r /2, Q r ),r 3/2 1 ) 3/2]
k) -7 TT - f (Tfk3/ - (fk)J.3




+ sfk
Cof s



where ung is the electron mobility in the intragrain channel. The
combination of (3.5), (3.7), and (3.13) gives ID as a function of the voltage drop V Vr V 1 (the variation in V) along the channel in the
gk k k
kth grain. Since V1 V .r + V _ for 2 1 k Ng, and V = 0 and
k k-i gh(j-1) fo9 g n V1 0an
r . VD, we have related ID to Vgk for all the Ng grains. Vg
The final relationship needed to define ID(VD,VGf) is

(Ng9-I) N
D j=1 gbj k=l gk (3.14)













3.2.2 Numerical Solution

The current-voltage characteristic is evaluated numerically by

solving simultaneously the nonlinear system of equations described- by (2.3) and (3.1) - (3.14), for all j and k. Instead of solving directly

this nonlinear system of equations, we obtain the solutions by first assigning values for ID and VGf, and then calculating the corresponding value of VD. The advantage of this method is that we avoid the typical convergence problems of the iterative methods [BU81] for. solving nonlinear system of equations because we only solve many nonlinear independent equations with one variable.

To illustrate the - predictions of our model, we apply it to a typical (but thick) SOI MOSFET for which N = 1016 cm"3, C - 5.8 x
ACof - .
10-8 F/cm2 (the gate oxide thickness is 600A), Z = L 40um, and ung 700 cm2/V-sec. To emphasize the most likely case (in beamr.ecrystallized SOI VLSI), we let Ng = 2 (one grain boundary). We plot in Fig. 3.2, for NST = 1012 cm-2, ET = Ei (traps at midgap), and Ygl = Yg2 = L/2 (grain boundary at middle of channel), the calculated IF}(Vj) characteristics for several values of (VGf - VTf); the threshold voltage VTf is the value of VGf yielded by (3.5) and (3.7) when Tsf(V = 0) is Sff
twice the Fermi potential of the silicon film body. We note that VFR does not need to be specified because it is related to VTf through (3.5) and (3.7) evaluated at y=O. For comparison we also plot (dashed curves) corresponding characteristics for Ng = I (no grain boundary). The grain

boundary reduces I; as in the linear region (see Chapter Two), its effect is most significant at low VGf. In the saturation region,







60










25
N=2 L VGf--VTf 1.5 V
y91 = y92=
NST 1012 C-2


20- Z=L=40 i.m













10
1.0 V





///'/.75 V




.5 V

00 .5 1.0 1.5

VD (V)
Fig. 3.2 Calculated current-voltage characteristics (solid curves) for
typical large-grain polysilicon SOT MOSFET with one grain
boundary at middle of channel. Without the grain boundary,
the dashed curves derive.













ID(sat) can be substantially limited, although VD(sat) is virtually unaffected since V(y=L) always equals the drain voltage.

The grain-boundary effect is strongly dependent on NST. To

illustrate this dependence, we plot in Fig. 3.3 the square-root of ID(sat) versus (VGf - VTf) for NST ranging from 0 (no grain boundary) to 2 x 1012 cm-2. As NST increases, the grain-boundary potential barrier increases, and hence a larger part of VD(sat) must be dropped across the boundary to enable ID(sat) to flow through it. For NST high, ID(sat) is reduced considerably even for VGf high.

Because the grain-boundary potential barrier increases as the adjacent intragrain inversion level decreases, the effect of the grain boundary will, for VD > 0, be stronger if the boundary is closer to the drain. To emphasize this important position dependence, we show in Fig. 3.4 how the calculated ID(sat)(VGf) characteristic is altered as

the grain boundary, with NST = 1.2 x 1012 cm2, is shifted toward the drain. Since Qn 0 near the saturated drain, a grain boundary there is influential regardless of how high VGf is. A grain boundary near the source however is significant only for VGf low. We also see in Fig. 3.4 that the position of the grain boundary is irrelevant for (VGf - VTf) < .6 V because the inversion level remains nearly constant along the channel for this low VGf.

The grain-boundary effect illustrated in Figs. 3.2 - 3.4 is enhanced as the channel length is shortened. This enhancement is

demonstrated in Fig. 3.5 where we plot the calculated IF(sat)(VGf) characteristic for different L with Z/L = 1 and Yg2 = L/4. The






62









6
6Ng= 2


Y91 = Y92=4 Z=L=40 im

4



7
1.2x 1012 cr02. 2- 1012 crii2
8x 1611 ClT 2,



/2 x1O12 cm-2


0 .5 1.0 15

VGf, VTf (V)






Fig. 3.3 Calculated dependence of drain saturation current, versus gate voltage, on grain-boundary (at middle of channel) trap
density.







63







6

N9=2
NST=1.2 x 1012 cm2 "/ /


Z=L= 40 iJ.m //
//
/ /
4 /



S/ /\//-/
no grain / 20 1i m
0--Q boundary /
- 2 1OJm

7 g2= 1.m
7
7
7
0I
0 .5 1.0 1.5

VGfVTf (V)







Fig. 3.4 Calculated dependence of drain saturation current, versus gate voltage, on grain-boundary position along channel.






64








6
/
Ng=2
Yg2 � / /
NST=I.2 x 10 cm/
, 4 z . ////




n grain --///rn


2- boundary/. // _Om
/ / 10 ir






00 .5 1.0 1.5
VG-VTf (V)





Fi g. 3.5 Calculated dependence of drain saturation current, versus
gate voltage, on channel length with grain boundary L/4 from
d rai n.













reduction in current with decreasing channel length results because the constraint on ID defined by (3.11) and (3.12) is independent of L, and hence Vgb must increase to support higher current densities in the channel.

To further stress the significance of grain boundaries in largegrain polysilicon SOl MOSFETs, we plot in Fig. 3.6 the calculated transconductance in the saturation region, gm(sat) a ID(sat)/aVGf, for one grain boundary in the middle of the channel having different values of NST. Depending on VGf, gm(sat) can be lower or higher than that for the grain-boundary-free (NsT : 0) counterpart. At low VGf, below the "mobility threshold" (V{) the grain boundary virtually inhibits current; thus gm(sat) - 0. As VGf increases, the grain-boundary effect is diminished as the intragrain channel conductance is enhanced, thereby producing unusually high transconductance (like in the linear region analysis of Chapter Two). At high VGf, the grain-boundary effect tends to subside, and gm(sat) approaches that corresponding to NST = 0.


3.3 Experimental Support and Discussion

To provide experimental support for the analysis, we measured current-voltage characteristics of large-grain polysilicon SOl MOSFETs described in Section 2.5.

We find that the measured ID(sat) is smaller than that of the theoretical calculations of the corresponding single-crystal counterpart (NG :1) , and that this relative difference increases as VGf

decreases. This result implies qualitative support for our analysis.






























E

20- 1.2x102 cm 2
1012 -2c
_8 x 1 11 c m 2 1 .5 X l 12 c m -:




0 .5 1.0 1.5
VGf-VTf (V)







Fig. 3.6 Calculated saturation-region transconductance versus gate voltage and grain-boundary (at middle of channel) trap
density.













Unfortunately, quantitative support is not obtained because Ng is not known exactly.

Additional support for our analyses has been presented by Colinge et al. [C083], who developed a technique to control the location of the grain boundaries in SOI MOSFETs. They fabricated two transistors with the same geometry, one beside the other, one of them with a perpendicular grain boundary at the middle of the channel, and the other without grain boundary. They found that ID(sat) for the transistor with a grain boundary is smaller than that of the transistor without a grain boundary.

We conclude this section by stressing three significant'conclusions drawn from this analysis. First, because the ID(VD) characteristics of SOI MOSFETs resemble that of the single crystal counterpart, the device parameters can be easily misinterpreted by using direct MOSFETs theory. Such misinterpretations, which evidently have been made in some previous work, can lead to misconceptions regarding SOl and can impede the development of optimal SOT devices and integrated circuits. Second,

because of the variation in the degree of inversion along the channel produced by VD, a grain boundary close to drain affects IDsat even at high VGf. Third, because part of VD(sat) is dropped across the grain boundaries, ID(sat) is reduced.



3.4 Summary

Using simplifying, but physically reasonable assumptions, we have modeled the effects of grain boundaries on the steady-state current-













voltage characteristics of large-grain polysilicon SOl MOSFETs. We have assumed that the predominant transport mechanism is thermionic emission

over the potential barrier,and we have avoided the use of previous generally invalid assumptions [MIJ61; BA78a]. The complexity of the model is commensurate with the uncertain and variable nature of the grain boundaries, but its predictions are in general accord with

experimental results. Basically the model shows that grain boundaries tend to reduce the MOSFET conductance (ID), but can increase or decrease

the transconductance. Although the grain-boundary effects are most apparent at low gate voltages, they can be quite significant at higher gate voltages ;when the drain voltage-is high, e.g., in the saturation region. Grain boundaries close to the drain are most effective. The effects are enhanced as the channel length is shortened.

We have measured current-voltage characteristics of both [LA831 laser- (Ng >> 1) and graphite-strip-heater- (Ng 2) recrystallized SOl MOSFETs, and have found general agreement with the model predictions. Because M g is not known exactly, it is difficult to make more quantitative comparisons.

A main conclusion of our work is that a single grain boundary in the channel can significantly affect the electrical properties of an SII MOSFET. Thus although the grain size of beam-recrystallized SOl is large, the grain boundaries, with randomly varying properties, can pose problems regarding yield, reproducibility, and reliability of SOl VLSI that cannot be ignored.



















CHAPTER FOUR
ANOMALOUS LEAKAGE CURRENT OF SMALL-GRAIN POLYSILICON MOSFETs



4.1 Introduction
Recent laboratory achievements [MA84; MA85] imply that the first commercial adaptation of three-dimensional integration may be stacked CMOS VLSI memory chips in which one of the complementary transistors (usually p-channel) is fabricated in a- layer of LPCVD polysilicon on silicon dioxide. Grain-boundary passivation (e.g., via hydrogenation FSH841) is required to render the polysilicon MOSFET performance acceptable for the circuit application, although single-crystal silicon device characteristics are not needed. The polysilicon transistor is inferior to the single-crystal counterpart, especially because of anomalous high leakage current and exceptionally high gate-voltage swing [0N82; SH84].

In this chapter we model the OFF-state leakage current of the small-grain polysilicon SOl MOSFET, which we theorize is controlled by grain-boundary traps. By qualitative deduction, we identify a plausible physical mechanism underlying the leakage current, and then show that it is consistent with the anomalously strong dependences on the gate and drain voltages that have been observed [0N82; SH84; MA85]. Such

physical insight can aid the design of polysilicon MOSFETs to control and minimize the leakage.













A typical set of measured current-voltage characteristics of an unpassivated LPCVD polysilicon MOSFET is shown in Fig. 4.1. The

particular device is p-channel and operates in the accumulation mode. The back gate and the source are grounded. In the OFF state (front-gate

voltage VGf> 0), the film body (grains) is completely depleted of free carriers, facilitated by grain-boundary trapping of holes. The front surface is inverted for VGf sufficiently high (> -0), facilitated by positive charge at the interface. The leakage current (IL = ID in the OFF region) increases exponentially with VGf and as a power (> 1) of the drain voltage VD. The device characterized in Fig. 4.1 is long-channel (32 1m), which means- that the anomalous IL(VIf,VD) is not a' shortchannel effect [AK82]. Other measurements [MA85] reveal that IL is virtually independent of the (long) channel length, and that the same anomalies obtain for other polysilicon MOSFET structures, e.g., the n-channel inversion-mode device. Passivation of the grain boundaries in

hydrogen plasma [SH84] reduces IL by two or three orders of magnitude, but does not remove the strong dependences on VGf and VD.

To physically model IL, we first deduce the most plausible mechanism producing the leakage by qualitatively eliminating the possibilities of other significant mechanisms. Although this deduction is not rigorous, we support the model by demonstrating correlation between its IL(VGf,VD) predictions and measured data. A rigorous

corroboration, which would require comprehensive analyses of all the possible mechanisms and extensive measurements of special test structures, is not feasible.












10701 1 1 1 1 1 1 1 1 1


10


0


10-


-0.05 V 12 - - '


-5.0


5.0


VGf (V)

Fig. 4.1 Measured current-voltage characteristics of an unpassivated
LPCVD polysilicon MOSFET (p-channel, accumulfpion-m5ode; Z = 128 pro, L = 32 pin, t = 500 A, NA = 10� cim- ). The
polysilicon film is O.1% pm-thick and was deposited via LPCVD
on a 0.5 pm-thick layer of silicon-dioxide. The back gate
and the source are grounded.


10-













Possibly significant leakage mechanisms in the polysilicon MOSFET

are: (a) space-charge-limited flow [R173; SC82] of holes from source to drain through the (depleted) film body; (b) thermal emission of carriers

[SZ811, via grain-boundary traps, in the depletion region near the drain; (c) field-enhanced (Poole-Frenkel [GR82]) thermal emission in the

drain depletion region; (d) impact ionization (avalanching) [DU78] in the drain depletion region; (e) band-band field emission (tunneling) [R173] in the drain depletion region; and (f) field emission via grainboundary traps [GR84], or possibly metal precipitates [LEF82], in the drain depletion region. The measured independence of IL on (long) channel length [MA85] rules out space-charge-limit-ed flow.- The strong observed dependences of IL on VGf and VD imply that thermal-emission current, which depends only weakly on VD, is not significant. The observed saturation of IL with increasing VGf in Fig. 4.1 is inconsistent with predominant Poole-Frenkel emission or avalanching.

Furthermore the electric field in the drain depletion region, for the values of VGf and VD used in the measurements (Fig. 4.1), is not high enough to produce significant avalanching or band-band tunneling. We are thus left with field emission through grain-boundary traps, or metal precipitates, as the most plausible mechanism underlying the observed IL(VGf,VD). The strong dependence on VGf further implies that the predominant field emission occurs near the front surface, in fact

between the p+ drain and the n inversion layer where the electric field is highest. If the hack surface is inverted, significant field emission can occur there also.













Our analysis of the field emission emphasizes grain-boundary traps, not metal precipitates, for two main reasons. First, neutron activation analyses [SH85] of the LPCVD polysilicon reveal concentrations (< 1013 cm-3) of metallic impurities comparable to those in bulk silicon and much lower than the grain-boundary trap density. Second, the grain boundaries getter metallic impurities, which tends to prevent the formation of metal precipitates.

In the next section, we develop an analytic model for the trapassisted field-emission current in the LPCVD polysilicon MOSFET. To

support the model, we compare its predictions of IL(VGf,VD) with measured data !from p-channel accumulation-mode! and n-channel inversionmode devices. Good correlation is shown, and field emission at the back surface is suggested as the mechanism underlying the minimization of the leakage current at relatively low values of VGf like that illustrated in Fig. 4.1. Insight regarding the physics underlying the anomalously strong IL(VGf,VD) dependences is readily provided by the model, and implies design criteria to control IL in polysilicon MOSFETs.



4.2 Leakage Current Model

To develop a physical model for the leakage current in the LPCVD polysilicon MOSFET, we consider the p-channel accumulation-mode device, the basic structure of which is illustrated in Fig. 1.2. The leakage current in other polysilicon devices, e.g., the inversion-mode MOSFET

[0N82], can be described basically by the same model as we discuss

later. The accumulation-node device is of interest because it can be













designed to have reasonably low threshold voltages [SH84; MA85]. Such design depends on the complete depletion of the small (- 1O00A) grains in the body via carrier trapping at localized grain-boundary states [BA78a; SH84]. The OFF state of the device then obtains in the absence of an accumulation layer under the gate; the surface is either depleted or inverted. Our model is based on the latter, more prevalent surface condition, and hence describes the anomalous strong dependences of the leakage current on the gate and drain voltages [0N82; SH84].

As discussed in Section 4.1, the leakage current is assumed to originate via field emission through grain-boundary traps (bound states)

at the drain junction. .Because of the complete depletion of the body, this emission occurs predominantly at the surface under the gate in the

depletion region between the p+ drain and n inversion layer. This

conclusion is consistent with the observed strong dependence of the leakage current on the gate voltage. Although band-band tunneling in

this surface region would occur only at very high electric fields [R173], substantial field emission can occur at low fields because of the high density of grain boundary traps in the LPCVD polysilicon. To

enable an analytic description of this emission, we assume that the traps are monoenergetic (at ET in the energy gap) and uniformly distributed in space FKA72; DE80; DE84] (with trap density NT = 2NsT/dG where NST is the grain-boundary areal trap density and dG is the average

columnar grain size).
The critical region of the device described above is illustrated in Fig. 4.2. It is the depletion region near the surface between the p+







75









Polyslllcon Gate





n InvearsI on
Layer
y



a- :ae. arm-,
Depletion P+
Region. Drain

















Fig. 4.2 Critical depletion region between the drain and the inversion
layer with important electric field components in (4.11)(4.13) indicated.













drain and the n inversion layer. Because of the lateral diffusion of the drain under the gate, the inversion extends into the drain region with complicated geometry. Thus the effective cross-sectional area of

the n-p+ junction is difficult to define. The electric field in this region, which governs the field emission, is two-dimensional

[FR69; TE84] (for wide channels) depending on both the gate and drain voltages, VGf and VD. Following a previous analysis EFR69] of the bulk MOSFET in the saturation region, we will treat this complex twodimensional problem empirically, which enables us to model the field emission processes as occurring predominantly parallel to the surface (in the y-direction). This simplification is commensurate with device ambiguities, yet yields a model that is consistent with experimental results and hence is insightful.

The energy-band diagram in the'region, including the grain-boundary trap level, is sketched (versus y) in Fig. 4.3. Maintaining the degree

of complexity implied above, we assume that the electric field in the y-direction, Fy = (dEi/dy)/q, is constant in the depletion (barrier) region, and that the electrons (or holes) tunnel through the barrier via

the traps at constant energy [GA70; R0771.

The leakage current derives then from the combined net field emission of holes, ITV, from the traps to the valence band in the drain region, and of electrons, ITC, from the traps to the conduction band in the inversion region. For traps within an incremental width (dy) of the depletion region (see Fig. 4.3) [GA70; R077; GR84],





















Electron Energy


y


ECp


ET EVp EFp


V ,, I "
i I
y(Ecn) Y(Evp)






Fig. 4.3 Electron energy-band diagram along the surface between the
(n) inversion layer and the (p+) drain.














dITV q(l - fT)NTZXedy (4.1)
TV T TV


and

qf TNT ZXe dY
d(-ITc) TTC (4.2)
TC


the rates of the respective inverse processes are negligibly small for the nonequilibrium conditions of interest (e.g., IVD1 >> kT/q). In

(4.1) and (4.2), Z is the channel width of the MOSFET, xe is an

effective depth of the junction region (see Fig. .4.2), fT is the electron occupancy factor of the traps, and TTV and TTC are the time constants for hole and electron tunneling respectively, which depend on Fy and ET as we discuss later.
In the steady state, the number of trapped electrons is constant, and hence in the absence of significant thermal emission, dITV =

d(-ITc). Equating (4.1) and (4.2) then, we have



f T TC (4.3)
T TTC +TTV


The incremetal field-emission current is given by the combination of (4.1) or (4.2) with (4.3). The total (leakage) current is then

expressed by integrating the result over that portion of the depletion region across which valence band-trap-conduction band carrier

transitions at constant energy are possible (see Fig. 4.3):















Y(Evp) _ dy (4.4)
L ZXeNT y(E TC+ TV


Since we assume that Fy is constant in the depletion region, F D E Vp E ECn
Fy qy(Evp) - Y(Ecn)] (4.5)



where D is the potential barrier height and. W is the width. The

tunneling time constants are thus independent of y also, and (4.4) can be written as


1 ) V N 1 (4.6)
IL ZXNT(T + T TV F(
TC TV y

Because the leakage current is low, little voltage is dropped across the inversion layer; VD is dropped across the drain depletion region as indicated in Fig. 4.3:



EFp - EFn qIVr! 1 (4.7)



For JVDI greater than a few tenths of a volt then, we note that the quasi-Fermi level separation in (4.7) equals approximately (Evp - ECOn) in (4.6). Thus


I-- qZx) � (4 .8)
L TC + TTV y













The time constants TTC and TTV reflect the probability per unit time that a trapped carrier will tunnel through a triangular barrier, defined by ET as shown in Fig. 4.3, to its respective band. Based on the WK8 approximation rR077; SZ81; GR84], 4(2mp)1/2(F - EV3/2
T TV T OVexp[ 3qhFy T (4.9)





and

4(2mnI/2(E C- ET)3/2
T TC T OCexp[ 3qhFy T (4.10)



where mp and mn are the appropriate [LU72; GR841 effective masses for the tunneling holes and electrons (mp - mn = 0.2 m0 [GR84] where m0 is the free electron mass), and where Tov. and TOC are effective carrier transit times in the valence and conduction bands, which we assume to be constants [LU721. For a parabolic barrier [R077; SZ81], the numerical constant in the exponential argument is different (lower). The effect of the barrier shape on IL can thus be studied by varying the effective masses in (4.9) and (4.10), which in fact cannot be unequivocally

defined [LU72; GR84].

We stress that the field-emission current IL in (4.8) is predominant because of the high density NT of traps that increase

substantially the tunneling probability, conveyed by (4.9) and (4.10), over that for hand-band tunneling [SZ81]. To complete the model for IL













defined by (4.8)-(4.10), we must describe Fy in terms of VGf and VD. As discussed with reference to Fig. 4.2, the electric field in the depletion region at the surface, and indeed the two-dimensional region itself are virtually impossible to describe analytically. However an

empirical description, commensurate with our one-dimensional fieldemission model, can be given based on a previous analysis [FR69] of the bulk MOSFET in the saturation region.

With reference to Fig. 4.2 three "components" of Fy can be

identified [FR69]:


Fy"=F+F2+F3 . (4.1)



In the empirical representation (4.11), F, is the electric field that exists in the absence of the gate; i.e., F1 is due to the depletion charge in the reverse-biased drain junction. The presence of the gate produces fringing electric fields F2 and F3: F2 is due to the gate-drain potential drop and F3 is due to the potential difference between- the drain end of the inversion layer and the gate. Following [FR69], which has been supported experimentally. [BR811, we assume that F2 and F3 are proportional to the respective normal electric fields at the surface (see Fig. 4.2):


F2 = aFD (4.12)
2 S













F3 13 F (4.13)



whereas and a are constant "field-fringing factors".

At the p+ drain side of the depletion region, the surface potential is nearly zero, and


D) C of + f
F -4V - -V -p
S VGf D -PMS +C (4.14)
s of


where Cof is the .(front) gate oxide capacitance, Off is the fixed charge
+
density at the (front) Si-SiO2 interface, and P is the gate-p+

silicon work function difference. For an n+ polysilicon 'gate,
+
P -E g/q where Eg is the silicon energy gap. At the inversion-layer side of the depletion region,



F Cof - + off E-q) (4.15)
S j-s (VGf cfMS o f -q


since the potential drop between the end of the (strong) inversion layer and the source region (VS = 0) is about Eg/q.

Using the one-dimensional analysis of the reverse-biased p-n

junction [SZ81], we express



F1 : D ]1/2 (4.16)
s


as an average value of the y-dependent electric field in the depletion region between the p+ drain and the n inversion layer. In (4.16), n is defined by (2.3) and (2.21),















Cof
f (VGf " VTf (4.17)
qxi (eff)



where Xi(eff) is the inversion layer thickness (- 100 A) defined in Section 2.2.1 and VTf is the strong-inversion threshold voltage of the MOS structure, the characterization of which depends not only on the

structural properties but also on the polysilicon film properties, e.g., NST, ET, and dG [KA72J. The potential barrier height D (see Fig. 4.3) is defined by VD and the surface potential in the inversion layer. For strong inversion,


E
SD g + IVDI � (4.18)



The combination of (4.8)-(4.18) gives an analytic description of IL

and its dependences on VGf and VD for the p-channel accumulation-mode polysilicon MOSFET. The control of IL by the grain boundaries is

conveyed by NT (= 2NsT/dG) and ET (relative to the band edges) in the i +
model. The parameters Cof, VTf, MS' Qff' and xi(eff) are defined hy the MOSFET structure, or can be estimated. The field-fringing factors a and 0 , and xe must be estimated or evaluated through comparisons of model predictions and measured data; they control the relative significance of VGf and VD in determining IL. The transit times tOV and TOC associated with the field emission are in effect normalization

factors for the tunneling time constants; they have been characterized from first principles [LU721, although not accurately. The model













therefore actually predicts the normalized IL(VGf,VD) dependences; absolute measured values however could be matched by assigning proper

values to-r0V and-TOC.

The model does indeed predict the general IL(VGf,VD) dependences exemplified in Fig. 4.1. To demonstrate this correlation and to

indicate the physical insight afforded, we plot in Fig. 4.4 the

calculated leakage current versus VGf and VD for a device similar to the one measured. Quantitative comparisons of the theoretical and

experimental characteristics should not be made because actual values of many of the model parameters are unknown. In the calculations, we used

Z = 128 um (L is irrelevant) and Cof = 6.9 x 10-8 F/cm2 (= �of/tof with tox = 500 A) corresponding to the device measured. We chose xe = 500 A, greater than xi(eff) but less than the extent of the lateral drain diffusion, and a = 0.2 and 8 = 0.6, crude values based on the bulk MOSFET model [FR69]. We let TrOV = TOC-- To : 10-12 sec, a crude estimate derived experimentally [GR84], and NT : 2 x 1017 cm-3, which

corresponds to NST : 1012 cm"2 and dG = 1000 A. We put ET at midgap. We characterized VTf = VTO - Qff/Cof with Qff/q 1012 cm2 and VTO
i i
V, which yield VTf -2 V. [We stress that VTf is the strong-inversion threshold voltage, in contrast to the turn-ON threshold voltage (for strong accumulation), which is about -4 V as indicated in Fig. 4.1.]

From (4.6) we note that IL is directly proportional to the factor ZxeNT/tO, and hence changes in these parameters simply alter the

magnitude of IL and not shape of the semi-logarithmic IL(VGf,VD) characteristics in Fig. 4.4. Additional calculations show also that the




























101u






--I

10-14 1



10 8 6 4 2 0
VGt (V)













Fig. 4.4 Calculated leakage current versus (front) gate and drain voltages for a p-channel accumulation-mode LPCVD polysilicon
MOSFET.













shape of IL(VGf) is not strongly dependent on a and a. Variations in the oxide capacitance Cof, however, produce significant changes in IL(VGf), primarily because of its influence on F1 described by (4.16)
i
and (4.17). Similar changes are produced by variations in VTf, or VTO as shown by the calculations plotted in Fig. 4.5. The leakage is most sensitive to VGf just above threshold for strong inversion; well above

threshold (high VGf), Fy in (4.11) is high and the tunneling time constants TTV and TTC in (4.9) and (4.10) tend toward minimum values

(TO), thereby causing IL to approach a value independent of VGf.

The calculated dependence of IL on the trap level ET is illustrated

in Fig. 4.6. As can be inferred from (4.9) and (4.10), traps near midgap are most effective in the field-emission processes; shallow traps do not facilitate carrier tunneling to the opposite band. We note that ET could possibly be inferred from measurements of the slope of the IL(VGf) characteristic.

Although the model predictions can he brought into close agreement with the measured leakage current by altering parameter values, the benefit of doing so is questionable because of the uncertainty in the actual physical structure and parameters of the device. For example, variations in the shape of the potential barrier in the drain depletion region, and/or in the effective masses in (4.9) and (4.10) can result in considerable changes in the predicted IL(VGf,VD) characteristics. Such changes are illustrated in Fig. 4.7 where we plot the calculated IL(VGf,VD) with mp = mn varying from 0.1 mo to 0.5 Mo. We note
however from the calculations plotted in Figs. 4.4-4.7 that the measured
















I "


,-14


1U
10


0


VG f (V)


Fig. 4.5 Calculated variation of IL(VGf) for different (stronginversion) threshold voltages V1f = VTO- Off/Cof (with
Off/Cof = 2.3 V).


10 6


- . VTO=-3V


I I I . .


I0"10


0






88












10-F6 - (Ec-ET) E9 E/2








VD=-5v

10 10 8 6 4 2 0

VGf (V)












Fig. 4.6 Calculated dependence of IL(VGf) on the grain-boundary trap
energy level ET.





































1


VGf (V)


Fig. 4.7 Calculated dependence of
effective masses mp = mn-


IL(VGf) on tunneling carrier


1076 10710


-J













IL(VGf,VD) characteristics in Fig. 4.1 could be simulated well by the model with physically reasonable parameter values.

The plots in Figs. 4.4-4.7, as well as the data in Fig. 4.1 which indeed reflect the general IL(VGfVD) dependences seen in a variety of LPCVD polysilicon MOSFETs, show that IL varies predominantly exponentially with VGf (> VTf) for a given value of VD. This dependence results from the exponential dependence of TTV and TTC on Fy expressed in (4.9) and (4.10). The dependence. of IL on VD is also strong, as emphasized by the calculations of Fig. 4.4 replotted in Fig. 4.8. For a given value of VGf (> VT), IL varies as IVDIm where m - 1-10. This

dependence follows from (4.8) and the implicit dependences on VD of Fy and T TC and TTV. Note that m decreases with increasing VGf and jVf)j.

The predicted m vs. VGf variation can be seen in the measured data in Fig. 4.1, although the m vs. IVDI variation cannot. This discrepancy appears to be due to (trap-assisted) avalanching in the drain depletion region that causes the measured leakage current to increase abruptly as IVDI approaches -10 V. We note further that the measured m (1-5) for all the devices is lower than that calculated, which could indicate that the effective masses in (4.9) and (4.10) are lower than 0.2 m0 as we assumed, or that the potential barrier is more parabolic than linear.

Additional calculations reveal that the effective masses must be reduced by about an order of magnitude to bring m down to the measured value. Then to retain theoretical-experimental agreement for the absolute value

of IL, the effective carrier transit times in (4.9) and (4.10) must be reduced by three to four orders of magnitude. Higher values of a and lower values of a also weaken the dependence of IL on VI).




























10-11






1013
-VD (V)














Fig. 4.8 Calculated I (VGf,Vn) characteristics
dependence on rain voltage V.


emphasizing


-J


10
















the













Additional support for the field-emission model for IL is obtained from consideration of the influence of the back-gate bias Vrb. This

influence is related to the minimization of the leakage current at low VGf depicted in Fig. 4.1. As VGf is reduced to switch the device from OFF to ON (accumulation), the measured leakage current reaches a minimum value, whereas the calculated current continues to be reduced monotonically. This simply indicates that the field emission in our model is insignificant at this point, and the actual minimum leakage

current is produced by another mechanism, possibly field emission *via grain-boundary traps near the back surface where positive interfacial charge could indeed cause inversion with the back gate grounded

(VGb : 0). The minimum measured currents in Fig. 4.1 show a strong dependence on VD like our model predicts, and hence we surmise that they result from field emission near the hack surface. We note further that.

the value of VGf at which the minimum IL obtains decreases as VD

increases. This implies that the dependence on VD of the field-emission

current at the back surface is weaker than that of the front-surface current, which, based on our model, is a result of the thicker back-gate (underlying) oxide.

Measured ID(VGf,VGb) characteristics for a hydrogenated n-channel inversion-mode LPCVD thin-film polysilicon MOSFET, with VD 5V, are

plotted in Fig. 4.9. For VGf << 0 (OFF region), ID (= L) is

independent of VGb and increases exponentially with IVGfI in accordance with our model. For low VGf (near the minimum 10), with VCb < 0 which implies that the back surface is accumulated, 10 increases with IVGbI




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xml record header identifier oai:www.uflib.ufl.edu.ufdc:UF0008243800001datestamp 2009-02-09setSpec [UFDC_OAI_SET]metadata oai_dc:dc xmlns:oai_dc http:www.openarchives.orgOAI2.0oai_dc xmlns:dc http:purl.orgdcelements1.1 xmlns:xsi http:www.w3.org2001XMLSchema-instance xsi:schemaLocation http:www.openarchives.orgOAI2.0oai_dc.xsd dc:title Effects of grain boundaries in polysilicon-on-insulator (SOI) MOSFETSdc:creator Ortiz-Conde, Adelmodc:publisher Adelmo Ortiz-Condedc:date 1985dc:type Bookdc:identifier http://www.uflib.ufl.edu/ufdc/?b=UF00082438&v=0000114706270 (oclc)000876113 (alephbibnum)dc:source University of Floridadc:language English