Citation
Modeling small-geometry silicon-on-insulator transistors for device and circuit computer-aided design

Material Information

Title:
Modeling small-geometry silicon-on-insulator transistors for device and circuit computer-aided design
Creator:
Veeraraghavan, Surya, 1962- ( Dissertant )
Fossum, Jerry G. ( Thesis advisor )
Place of Publication:
Gainesville, Fla.
Publisher:
University of Florida
Publication Date:
Copyright Date:
1988
Language:
English
Physical Description:
vi, 172 leaves : ill. ; 28 cm.

Subjects

Subjects / Keywords:
Activating transcription factors ( jstor )
Drains ( jstor )
Electric current ( jstor )
Electric fields ( jstor )
Electric potential ( jstor )
Electrons ( jstor )
Modeling ( jstor )
Narrative devices ( jstor )
Parametric models ( jstor )
Simulations ( jstor )
Metal oxide semiconductor field-effect transistors ( lcsh )
Thin film devices ( lcsh )
Transistor circuits -- Data processing ( lcsh )
City of Gainesville ( local )
Genre:
bibliography ( marcgt )
theses ( marcgt )
non-fiction ( marcgt )

Notes

Abstract:
This dissertation concerns the physical charge-based modeling of small-geometry silicon-on-insulator (SOI) MOSFETs for large-signal transient circuit simulation. A new model for the thin-film SOI MOSFET (the basic device in a technology with the potential for becoming the mainstream for submicron integrated circuits) that accounts for the predominant thin-film and short-channel effects has been developed. The thin-film effects include the coupling between the front and back gates of the MOSFET, and associated floating body effects. The short channel effects, which are physcially linked to the thin-film effects, include threshold-voltage reduction by charge sharing, drain-induced conductivity enhancement, field-dependent mobility and velocity saturation, channel-length modulation, and generation by impact ionization. From the basic physical model, quasi-static charge expressions are calculated for each of the five terminals of the MOSFET. The new five-terminal charge-based model is then implemented in the circuit simulation program SPICE2. A systematic measurement-based parameter-extraction algorithm is defined. The model parameters extracted using this technique, which involves minimal optimization, are shown to be physically meaningful. A preliminary demonstration of the model's predictive capability is done for a contemporary SOI MOSFET technology. through measurements and from the theoretical predictions of the model, short-channel effects in SOI MOSFETs are shown to be unique because of dependences on film thickness and body and substrate (back-gate) biases. The potential advantages of scaling the film thickness with the channel length are demonstrated, and device design criteria are discussed. A new short-channel effect, which we term "back-surface charge modulation," is also presented, and is shown to be predictable from the basic model analysis.
Thesis:
Thesis (Ph. D.)--University of Florida, 1988.
Bibliography:
Includes bibliographical references.
General Note:
Typescript.
General Note:
Vita.
Statement of Responsibility:
by Surya Veeraraghavan.

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University of Florida
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University of Florida
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Copyright Surya Veeraraghavan. Permission granted to the University of Florida to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Resource Identifier:
024554800 ( ALEPH )
19956067 ( OCLC )
AFL2515 ( NOTIS )

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Full Text












MODELING SMALL-GEOMETRY SILICON-ON-INSULATOR TRANSISTORS
FOR DEVICE AND CIRCUIT COMPUTER-AIDED DESIGN










By


SURYA VEERARAGHAVAN


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF DOCTOR OF PHILOSOPHY


UNIVERSITY OF FLORIDA 1988




V OF F LIBRARIES

..












ACKNOWLEDGEMENTS

I wish to express a very deep sense of gratitude to my advisor, Professor Jerry Fossum, who has been a constant source of support, guidance, and friendship throughout the time that I have known him. I would also like to thank the other members of my committee, Professors Lindholm, Burk, Eisenstadt, and Holloway, for their interest in this research and patience in reading through the manuscript.

I am grateful to Harris Semiconductor, Texas Instruments, the Semiconductor Research Corporation, and the Naval Research Laboratory for the financial and technical support that made this work possible, and to the Hewlett-Packard Corporation for its generous donation of the TECAP software package. In particular, I wish to acknowledge Mr. Dan FitzPatrick for rewriting the SPICE2 code to implement the SOI model, and Drs. Wade Krull, Rich Cherne, Ravi Sundaresan, and JeanPierre Colinge for providing test devices.

These acknowledgements would be incomplete without a mention of at least some of the many people I count as both colleagues and friends. In particular, I would like to mention Drs. Robert McDonald, Adelmo Ortiz, and Shuy-Young Yung, and Messrs. Hang-geun Jeong and Myung-suk Jo for countless hours of stimulating discussions.

Finally, I wish to express my gratitude to my soccer team, Entropy, my very good friends Ajit Lalwani and Marcos Rubinstein, and last but far from the least, Anne Hynek and my sisters and parents, whose love and encouragement have sustained me through the years.

ii

..








TABLE OF CONTENTS


ACKNOWLEDGEMENTS.i

ABSTRACT.

CHAPTERS

1 INTRODUCTION. 1

2 PHYSICAL SHORT-CHANNEL MODEL. 8

2.1 Introduction. 8 2.2 Physical Model. 8 2.2.1 Charge Sharing. 9 2.2.2 Drain-Induced Conductivity Enhancement. 13 2.2.3 Carrier Velocity-Field Model. 17 2.3 Triode Region. 20 2.4 Saturation Region. 21 2.4.1 Saturated Drain Current. 21 2.4.2 Channel-Length Modulation. 23 2.4.3 Impact-Ionization Current. 25 2.5 Charge-Based Model. 27 2.5.1 Triode and Saturation Regions. 27 2.5.2 Cutoff Region'. 31
2.6 SPICE2 Implementation.
2.7 Summary. 42

3 MODEL VERIFICATION AND APPLICATIONS TO DEVICE DESIGN .43

3.1 Introduction. 43 3.2 Threshold-Voltage Reduction. 44 3.3 Drain-Induced Conductivity Enhancement (DICE). 50 3.4 Velocity Saturation and Channel-Length Modulation .53 3.5 Hot-Carrier Effects. 60 3.6 Subthreshold Slope. 60 3.7 Back-Surface Charge Modulation. 64 3.8 Summary/Conclusions. 69

4 MODEL CHARACTERIZATION. 71

4.1 Introduction .71 4.2 Model Selection Criteria. 72 4.3 Parameter Extraction. 79 4.3.1 Threshold Voltage Measurements. 82 4.3.2 Linear-Region Conductance Measurements. 86 4.3.3 Determination of Empirical Charge-Sharing Parameters .94 4.3.4 Body-Current Measurements. 96 4.4 Discussion. 102

..







5 MODEL EXTENSIONS.


5.1 Introduction. 5.2 TFA-TFD Model Unification (TFAD) 5.2.1 Physical Model. 5.2.2 Steady-State Currents 5.2.3 Charge Calculations. 5.3 Bulk and TFA-TFAD-TFD Model Unification 5.4 Subthreshold Conduction Model 5.5 Nonuniform Film Doping 5.6 Surface-State Density. 5.7 Bias-Dependent Parasitic Resistances 5.7.1 Parasitic Drain and Source Resistances 5.7.2 Parasitic Body Resistance 5.8 Summary.


7 SUMMARY AND CONCLUSIONS WITH RECOMMENDATIONS. APPENDICES

A USER-DEFINED CONTROLLED SOURCE (UDCS) IMPLEMENTATION B PISCES STUDY OF CHARGE SHARING. C ALGORITHM FOR CALCULATING THRESHOLD VOLTAGE. D CALCULATION OF CHARGES. REFERENCES. BIOGRAPHICAL SKETCH.


112 114 "17
120 123 125 127 132 133 133 135 136

137


153 161

164 166 172


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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

MODELING SMALL-GEOMETRY SILICON-ON-INSULATOR TRANSISTORS
FOR DEVICE AND CIRCUIT COMPUTER-AIDED DESIGN By

SURYA VEERARAGHAVAN

December 1988


Chairman: Dr. J.G. Fossum
Major Department: Electrical Engineering

This dissertation concerns the physical charge-based modeling of small-geometry silicon-on-insulator (SO1) MOSFETs for large-signal transient circuit simulation. A new model for the thin-film SOI MOSFET (the basic device in a technology with the potential for becoming the mainstream for submicron integrated circuits) that accounts for the predominant thin-film and short-channel effects has been developed. The thin-film effects include the coupling between the front and back gates of the MOSFET, and associated floating-body effects. The shortchannel effects, which are physically linked to the thin-film effects, include threshold-voltage reduction by charge sharing, drain-induced conductivity enhancement, field-dependent mobility and velocity saturation, channel-length modulation, and generation by impact ionization. From the basic physical model, quasi-static charge expressions are calculated for each of the five terminals of the

..







MOSFET. The new five-terminal charge-based model is then implemented in the circuit simulation program SPICE2.

A systematic measurement -based parameter -extraction algorithm is defined. The model parameters extracted using this technique, which involves minimal optimization, are shown to be physically meaningful. A preliminary demonstration of the model's predictive capability is done for a contemporary SOI MOSFET technology.

Through measurements and from the theoretical predictions of the model, short-channel effects in SOT MOSFETs are shown to be unique because of dependences on film thickness and body and substrate (backgate) biases. The potential advantages of scaling the film thickness with the channel length are demonstrated, and device design criteria are discussed. A new short-channel effect, which we term "back-surface

charge modulation," is also presented, and is shown to be predictable from the basic model analysis.

..













CHAPTER 1
INTRODUCTION


Thin-film silicon-on-insulator (SOl) technology is becoming increasingly important and viable for very-large-scale-integrated (VLSI) circuits [La87]. MOSFETs fabricated in these films (see Fig. 1.1) are well isolated from each other by the buried oxide layer (made, for example, by oxygen implantation), thus completely eliminating the problem of latch-up which exists in bulk technologies. The presence of an insulating layer with lower permittivity than silicon enables a lowering of the parasitic capacitance to the substrate. The reduced volume occupied by each device also implies increased radiation hardness. In addition, the structure of the device seems to indicate a greater ability to scale the thin-film MOSFET than the bulk MOSFET [Sa80, Th86], and holds out the possibility of three-dimensional integration [Ak86].

While much effort has gone into technology and process development [Ie86, Ie87], not as much work has been done on modeling the

electrical characteristics of thin films. Measurements and numerical simulations of SO1 MOSFETs have shown two major influences on the current-voltage characteristics which are not accounted for in models for bulk MOSFETs (without an underlying oxide). The first of these is the effect of the back-gate (substrate) bias VGbS in determining the conduction of the inversion region at the interface between the front

..























Silicon Film


.S .


Fig. 1.1 Cross-sectional view of a generic n-channel SOI MOSFET
showing the five terminals: the front gate (Gf), the back
gate (Gb), the source (S), the drain (D), and the body (B).

..







3

gate oxide and the silicon film (heretofore referred to as the "front surface") [Li84b, Li84a, Co84]. For example, in n-channel MOSFETs, the application of a large negative bias, VGbS, on the back gate creates an accumulation layer at the interface between the buried oxide layer and the silicon film (heretofore referred to as the "back surface"), thus pinning the potential at that interface to the body voltage, VBS. This causes the threshold voltage VTf to vary linearly with VBS, in contrast to the nonlinear dependence in bulk MOSFETs [Sz8l]. However, for more positive VGbS, the back surface is depleted, and the threshold voltage becomes independent of VBS, but starts to depend linearly on VGbS. Another interesting fact brought out by the measurements and twodimensional simulations is the effect of leaving the film body floating: in the saturation region, holes (in the n-channel device) generated by impact ionization in the drain region [Ti75, E175, Ea78] are injected into the floating body, causing a build-up of the potential of the accumulation region at the back interface, if it exists. This causes an enhancement in the conduction of the MOSFET, and shows up as a "kink" in the ID(VD) characteristics of the device. A similar phenomenon is seen when the MOSFET is turned on rapidly [Ea78, Li84c]: here, the rapidly expanding depletion layer in the silicon film forces holes to build up the body potential. In bulk CMOS circuits, this phenomenon is usually insignificant because the body voltage is kept fixed at the source voltage by an external contact between the body and source terminals, and because the current due to the generated holes is many orders of magnitude less than the channel current. However, in SO1 transistors with floating bodies (and even in

..







4

bulk CMOS devices with floating wells), it becomes essential to properly model the effects of carriers generated by impact ionization.

Various authors [Sa80, Ka85, Ar86, Th86] have presented twodimensional numerical solutions of the semiconductor equations (i.e., Poisson's equation, the electron and hole continuity equations, and the energy balance equations) for the potential T, and the electron and hole concentrations n and p, in SO1 MOSFETs. Though this approach provides insights into the important physical mechanisms involved in the device operation, at present, it has limited use as a method to study the performance of SO1 MOSFETs in large circuits.

Another approach [Li84b, Li84a, 0o84] has been to invoke the gradual-channel approximation, coupled with simple physical models for carrier transport, to get analytic solutions for the terminal currentvoltage characteristics. These models account for the coupling of the front and back gates, and are a good basis for new model development. In Appendix A it is shown that with simple extensions they can be used to simulate, with the circuit simulator SPICE2 [Na75], the floatingbody effects described above. However these models do not incorporate the effects of both small lateral dimensions (i.e. channel length and width) and a thin, possibly floating, film that causes coupling between the front and back gates of the device, and so they are not

comprehensive enough to be used in the detailed design of VLSI devices and circuits.

This dissertation, then, is concerned with the development and implementation of physically representative charge-based models for the small-geometry enhancement-mode MOSFET fabricated in thin SO1 films, as

..






5

well as the development of automated parameter-extraction techniques for the model. This work will facilitate both the design of VLSI SO1 circuits using available devices, as well as an understanding of the electrical behavior of the MOSFET and of ways to improve its performance by innovative device designs. The main contributions made in the work are as follows:

(1) development of a physically representative charge-based model for

the small-geometry SO1 MOSFET;

(2) implementation of the developed model in the source code of the

circuit simulator SPICE2;

(3) demonstration of the unique scaling effects of SO1 MOSFETs, and

use of the model to define device design criteria;

(4) definition of an algorithm to extract model parameters using TECAP

[He85].

In Chapter 2 a novel physical model for the (five-terminal) enhancement-mode SO1 MOSFET is presented. This model accounts for some of the obvious differences (between bulk and SO1 MOSFETs) noted above and in Appendix A, namely the floating body and coupling between the gates, as well as the short-channel effects that have been modeled in bulk MOSFETs [Sh85, Sz8l]: the effect of the drain bias on channel conductivity, field-dependent carrier mobility and velocity saturation, channel-length modulation, and impact ionization. The physical model is used to define a large-signal charge-based model for the SO1 MOSFET, which is then written directly into the source code of the circuit simulator SPICE2 [Fi88].

..







6

In Chapter 3 short-channel effects in thin-film SOI MOSFETs are examined, experimentally and theoretically, by means of the model developed in Chapter 2, and are shown to be unique because of dependences on film thickness and body and back-gate (substrate) biases. The various predictions of the model, in particular the effects of thinning the film, are shown to be consistent with measurements; and

the potential advantages of scaling the thickness of the film as well as the lengths and widths of the transistors are demonstrated. The dependences on film thickness and bias, which enable control of the short-channel effects, are used to define design trade-offs.

Furthermore, a short-channel effect exclusive to SOI MOSFETs, "backsurface charge modulation," is reported and its relevance to device simulation is discussed.

Chapter 4 describes the practical use of the model developed in Chapter 2. Criteria for selecting the appropriate model are defined, and then an algorithm (using TECAP [He85]) to automatically extract the physical parameters needed for device simulation is described. Because of the physical nature of the model, the parameter extraction involves minimal optimization and gives physically meaningful values. The extraction scheme is applied to a contemporary S01 technology to verify

the model and to demonstrate its potential for both device and circuit design.

In Chapter 5, the limitations of the model, which include the neglect of surface states, non-uniform film doping, etc., are

discussed. It is shown that, given the model framework developed above, it is indeed possible to account for these effects in a

..







7

consistent manner. In the absence of unequivocal experimental data on these process-dependent parameters, the completion of such models have not been extensively pursued. The preliminary work done, however, opens

up the possibility of doing simple predictive modeling of device, and in fact, circuit performance, when the technology becomes more stable.

In Chapter 6 the main accomplishments of this dissertation are summarized and suggestions of areas for future work are made.

In Appendix A, a simple yet general technique using "user-defined controlled sources" [Ha841 to incorporate arbitrary charge-based models

in the popular circuit simulator SPICE2 is described. This technique is developed primarily as a tool to aid in the development of the charge-based model. It is useful for checking new transient models in an actual circuit environment, without investing excessive amounts of time in implementation, prior to actually writing the models into the source code of SPIGE2. To demonstrate the utility of the technique, various SOI test circuits are simulated, showing the effects of a floating thin film on circuit performance.

In Appendix B, the two-dimensional numerical simulator PISCES-IIB [Pi84] is used to study the charge-sharing effect that defines the threshold voltage. The model in Chapter 2 for threshold-voltage reduction in short-channel devices is based on this study.

Appendix C describes the algorithm used to determine the threshold

voltage for all bias conditions, which is a basis for the parameter extraction described in Chapter 4.

Appendix D details some of the algebraic manipulations used in the development of the quasi-static charge-based model.

..














CHAPTER 2
PHYSICAL SHORT-CHANNEL MODEL


2.1 Introduction

In this chapter a comprehensive, physically representative chargebased large-signal model for the small-geometry enhancement-mode MOSFET fabricated in thin S01 films is presented. The model is a major revision of the strong- inversion model [Li85] used in Appendix A, and includes the predominant short-channel effects. These effects, which are unique in the thin-film SOI MOSFET, include threshold-voltage reduction due to charge sharing, channel- conductivity enhancement due to a drain bias, field-dependent carrier velocity including velocity saturation, channel-length modulation, and generation current due to impact ionization.

Section 2.2 details the new physical model, designed so that each major short-channel effect is analyzed explicitly. This enables a clearer understanding of the underlying physics and also allows for model improvements where necessary. In Sections 2.3, 2.4, and 2.5, the characterization of the drain current and quasi-static terminal charges (based on the model in Section 2.2) is completed.



2.2 Physical Model

In contrast to conventional modeling [Sz81] of short-channel effects (in bulk devices), in which long-channel current-voltage

..







9

characteristics are modified by introducing a drain-bias-dependent threshold voltage, a more physical approach is taken. Based on

simplifying assumptions that preserve the physical essence, twodimensional characterizations of important mechanisms in the thin-film SO1 MOSFET structure are derived directly. Subsequent integration of the defined channel charge from source to drain yields a representative description of the short-channel effects on both the current-voltage and stored charge-voltage characteristics. The model in this section is presented for the n-channel enhancement-mode device; the corresponding model for the p-channel MOSFET, which differs only in the algebraic signs of some of the parameters, can be similarly derived.



2.2.1 Charge Sharing

The (front-channel) threshold voltage VTf, defined for low drainsource voltage VDS, is reduced in short-channel MOSFETs because some of the depletion charge under the gate is shared by the source and drain [Ak82, Vi85]. In the SOl device, this sharing is influenced by the coupling between the front and back gates.

For VDS 0, the solution of the two-dimensional Poisson equation, which defines the charge sharing and hence VTf, is symmetric as indicated in Fig. 2.1. In strong inversion, the thin film is assumed to be completely depleted, except for sheets of surface charge, QcfO and QcbO, at the front and back surfaces respectively. (The subscripts f and b refer to the front and back surfaces, and the subscript 0 refers to the solution for VDS = 0.) The potential of the front surface Tsf0 is approximately constant between the source and drain and is given by

..










VGf S
T


I T


front oxide I I I


depleted / n+ film /
0 /
Q\/

d buried
oxide



VGbS


Fig. 2.1 A simple charge-sharing model for the thin-film SOI MOSFET
showing the completely depleted film (doping density NA) and the portions 1, 2, and 3, "controlled" by the gates, source
and drain respectively.


m
B


m
m

..






11

TI = 2gB. (eB is the Fermi potential of the neutral film, to which all potentials are referenced.) At the back interface, the potential varies from the junction built-in potential (Vbi) in the source and drain contact regions a surface potential- sb0 midway between the source

and drain.

The depletion charge may be regionally divided into three portions as shown in Fig. 2.1, associated with the gates, source, and drain. The portion 1, which is controlled by the front and back gates, is defined approximately by a trapezoid, and hence the effective depletion charge per unit area controlled by the gates is


Qb(eff) = -qNAtb(l-d/L) A Qb(l-d/L) (2.1)

where tb is the thickness of the silicon film and L is the channel length of the MOSFET. The one-dimensional Poisson's equation is then solved as in [Li84b], but with the doping density NA replaced by a "smeared-out," constant NA(eff) = NA(l d/L). This gives

[ f Cb Cb b(eff)

Q -C V -V (1+---)T + -- b + (2.2a)
cf0 of GfS VFB s(l+ )f0 + sb0 (2.2a)
Cof 2C
of of of

and

[V b Cb Cb Qb(eff)

Qcb Cob V (1 b ---) + b- f + (2.2b)
cb0 ob GbS FB C sb0 o sf0
ob ob 2Cob


where Cb A Es/tb, Cof = cox/tof and Cob = cox/tob are the front and back (buried) oxide capacitances per unit area, and VFB and VFB are the front- and back-gate flatband voltages. (The quantities tof and tob are the thicknesses of the front and back oxides.) Equations (2.2a) and

..







12

(2.2b) are equivalent to (1) and (2) of [Li85], with Qb replaced by

Qb(eff)*

To characterize VTf, the distance d in (2.1) must be analytically approximated. This is done by following [Fr69] to account for the twodimensional electric field near the back surface in portions 2 and 3. The effective lateral component of the electric field, Eb(eff), at the back interface is approximated as

E fE fE + fE
b(eff) 0 E1 af 2 + fE3

f0[qNA (Vbi- I sb0) / 2es 1/2 + (2.3)

e V Vb T V -V +Vb
ox GbS FB sb0 + ox bi GbS FB
f -+ f
ato E t
s tob s ob


where the first term is due to the depletion charge and the second and third terms are the fringing fields from portion 1 and the source to the back gate. In (2.3), f0, fa, and fp are empirical factors between 0 and 1, and can be estimated by curve-fitting measured VTf data (see Chapter 4 for details on parameter extraction, and Appendix B, where it is demonstrated, through PISCES simulations, that this model is indeed physically meaningful). Now

d = (Vbi 'sb0)/Eb(eff) (2.4)

When the back gate is biased to accumulate the back surface, Qcb0 > 0 and Tsb0 VBS, the body-source voltage. Then, in strong inversion, with -sf0 T I, (2.1) through (2.4) yield


Qcf0 Cof (VGfS VTf) (2.5)

f
where VTf ( VFB + (1+Cb/Cof)TI (Cb/Cof)VBS Qb(eff)/2Cof) depends

..







13

on L as well as VBS and VGbS. The back-surface accumulation charge QcbO is also simultaneously defined by (2.1) through (2.4).

When VGbS is set to deplete the back surface, QcbO = 0, and TsbO > VBS is unknown. In this case, (2.1) through (2.4) give a quartic equation which must be solved to determine "sbO, which, when inserted into (2.2a), defines QcfO and VTf. In the model, TsbO is determined by the following simple iterative scheme: (i) assuming no charge sharing, calculate TsbO from (2.2b); (ii) use that value successively in (2.3), (2.4), and (2.1) to determine Qb(eff); (iii) use (2.2b) to determine a modified value for TsbO Steps (ii) and (iii) are repeated until the solution converges, which in fact occurs in only a few iterations.

Note that distinct models have been defined for the two different charge conditions at the back surface. In devices with very short channels it is possible, for a given VGbS, that the charge condition will depend on L. That is, the charge sharing tends to deplete the back surface as L is decreased. This unique short-channel effect, which is discussed through measurements in Chapter 3, can be modeled within the above framework by defining the transition point between the two distinct models, where TsbO VBS and QcbO = 0 simultaneously. The details are in Appendix C.



2.2.2 Drain-Induced Conductivity Enhancement

When a drain voltage is applied to a short-channel MOSFET, the channel current IDS cannot be adequately characterized by the gradualchannel approximation [Sz8l]. In this case, VDS modulates the channel charge indirectly through the two-dimensional Poisson equation in the

..






14

film as well as directly through the induced gradient in sf along the channel. This drain-induced conductivity enhancement (DICE) in strong inversion (which is analogous to drain-induced barrier lowering in weak inversion [Sz8l, Tr79]) is accounted for by modeling the VDS-induced change, AQcf, in the channel charge.

On application of VDS > 0 the potentials T(x,y) in the film and Tsf(y) and Tsb(y) are modified, as are Qcf(y) and Qcb(y), from their values at VDS = 0 by the amounts AT(x,y), Asf(y), A'sb(Y), AQcf(y), and AQcb(y) (see Fig. 2.2). Since the depletion charge density in the thin film cannot change (the film is completely depleted for VDS = 0), Laplace's equation describes the incremental potential:


82 2
a 2(A'F) a2 (ATI)
+ =0 (2.6)
8x 8y2

The boundary conditions for (2.6) are AQ(x,0) = 0, A(x,L) = VDS, AT(O,y) = Aisf(y), and Ag(tb,Y) = Asb(y). In addition, the incremental boundary charges AQcf(y) and AQcb(y) are related to the incremental transverse electric fields (AEx 6 -8(AW)/8x) at the respective surfaces by Gauss's law.

To obtain a closed-form solution for (2.6), it is assumed that the two partial derivatives are not strongly coupled. Extrapolation from the long-channel case for which each term is zero (i.e., gradual channel) gives

a2(AT)/ax2 _-a2(A)/ay2 = (2.7)


where n is a constant that must approach zero as L increases. The L dependence of n is inferred by integrating (2.7) from y = 0 to y = L:

..










_IT


-V0 bi


VGf S f 0cf
sf0 fi0


flln depleted

V2 a qN^ )
0 Go


o0 VbI


sbO cbo


IiS
V
GbS


A/*t( y AQ v 0 Y ) T( VDS


IT


- A.-


S II


no charge


A*/ -0


V2(Z, ) 0


&*y DS


A*sb(y AQob( Y


I


Fig. 2.2 Illustration of the method of solution for the twodimensional Poisson equation in the SOI MOSFET. The superposition of the solution for the VDS 0 boundary-value problem (top) and the incremental solution for the VDS > 0 problem (bottom) gives the total solution for the general
case of arbitrary applied biases.


W

..









S- (2/L2) [VDS + AE y(0)L] = (2/L2)VDS (2.8)

since the incremental longitudinal field AEy (0) at the source is typically much less than the average field VDS/L.

Equation (2.7) is integrated once with respect to x to determine a relationship between the incremental transverse fields AEsf(y) and AEsb(y) at the front (x = 0) and back (x = tb) surfaces of the

silicon film, and then a second time to get a relationship between the incremental surface potentials Asf(y) and Asb(Y):

AEsb(y) = AEsf(y) + ntb (2.9)

and

A~sb(Y) Asf(Y) AEsf(y)tb ntb2/2 (2.10)

In order to relate the fields and potentials derived above to the incremental surface charges AQcf(y) and AQcb(y) the field in the oxide is assumed to be approximately vertical. This is typically true for modern transistors with thin gate oxides [Vi85]. Gauss's law applied to the front and back interfaces, with (2.9) and (2.10), then yields

AQcf(y) = (Cof+Cb)A sf(y) CbAsb(Y) stbn/2 (2.11)

and

AQcb(y) = -CbAsf(y) + (Cob+Cb)A sb(Y) stbn/2 (2.12)

These equations are seen to be the incremental counterparts of Eqs. (1) and (2) in [Li85], with the additional accounting for the twodimensionality in short-channel devices. By inserting the conditions that Asb = 0 when the back surface is accumulated and AQcb 0 when the back surface is depleted, a general expression for AQcf(y) as a function of Asf(y) is derived:

AQcf(y) = Cof(l+a)A9sf(y) 6Cbtbq/2 (2.13)

..






17

where a = Cb/Cof and 1 = 1 for accumulation at the back surface, and a

- CbCob/(Cb+Cob)Cof and 8 = 1 + Cb/(Cb+Cob) for depletion at the back surface.

The expressions for the incremental surface potentials and charges are now added to the solutions for VDS = 0 to give the general expressions for VDS > 0. Thus Wsf(Y) = Tsf0 + Asf(y), Qcf(Y) = Qcf0 + AQcf(y), etc.



2.2.3 Carrier Velocity-Field Model

Due to the possible high transverse electric field in the thin SOI film, as well as the high longitudinal electric field in the short channel, there can be considerable nonlinearity in the carrier velocity-field characteristic. For increasing longitudinal field 1EY= drsf/dy in the channel, the velocity tends to saturate (at vsat = 107 cm/s in bulk silicon). In this work, the following piecewise-continuous model (So84, Ga87] for the carrier velocity in the channel is used:


v(y) for v(y) 5 v
1 + U effE y/2v sat'
eff y sat
vsat otherwise. (2.14)


In (2.14), Aeff is the low-(longitudinal-)field mobility, which is affected by the transverse electric field Ex in the channel as

illustrated in Fig. 2.3. This dependence, along the channel, is modeled [Wh80, Su80, Ga87] in terms of the average Ex(y) in the channel:

no
neff o (2.15)
I + 0 E (Y)

..












carr i er

velocity







"sat




increasing transverse field Ex


longitudinal field lEyl







Fig. 2.3 Sketch of the steady-state carrier velocity as a function of
applied electric field IEyI along the length of the channel, for different applied vertical electric fields Ex. The slope of each curve near the origin gives the value of Peff in
(2.14).

..







19

where 0 is an empirical constant. From the quasi-l-dimensional solution to Poisson's equation at VDS = 0 (with NA(eff) as in Section 2.2.1), the maximum transverse electric field obtained at the front surface of the fully-depleted silicon film can be expressed as


Ex (max)


QcfO

s


sf0- i sb0O
+
tb


Qb(eff)
2 e
s


(2.16)


The average field in the inversion layer at VDS = 0 is then written as follows:


Qcf0
E = E +
xO xO(max) + 2 e
s
G (V V ) 'I 9
of (VGfs VTf) sf0 sb0
= +
2 s tb


Similarly, from the DICE analysis (S

incremental transverse field at any positi

expressed as


Cof Asf(y)
+


AE (y)
x


Qb(eff)

2 e
s


(2.17)


ection 2.2.2) the average on y along the channel can be


AQcf (y)
2cf 2 6


Cof S(a-1) Al sf(y)
2 e
s


(2.18)


a and 6 were defined earlier in the discussion of (2.13). (2.17) and (2.18) are then added to yield the following expression for the average transverse field in the channel for an arbitrary bias:


---

..









Cof [b(eff) Cb Cb tb
Ex(y) V GfS V + 2 (C ) + P VDS
x f fI sb0 + DS
2e sC of C ofC 0 L
2s Gof of of L



(1 a) ATsf(y) (2.19)



With (2.19), (2.15) is rewritten as


pef = (2.20)
eff 1 B Aisf(y) (2.20)


where the newly defined parameters p and B are bias-dependent but spatially constant.



2.3 Triode Region

The steady-state channel current is


IDS = W Qcf(Y) v(y) (2.21)

Using the models in Section 2.2 for v[Tsf(y), d'sf/dy] in (2.21) yields


IDS dsf dsf
-IDS(1-B ATsf) + W Qcf (2.22)
2vsat dy dy


The voltage dependence of IDS is now derived by integrating (2.22) from the source (y = 0) to the drain (y L). To enable this integration, it is noted from (2.13) that d(Qcf) d(AQcf) = Cof(1+a)d(Asf)

Cof(l+a)d(sf), and so the second term on the right-hand side of (2.22) can be rewritten as [W/Cof(1+a)].d[Qcf2/2]/dy. Further, since Asf varies from 0 to VDS from the source to the drain with an

..






21

approximately parabolic dependence on y, it is reasonable to define fAsfdy = fBVDSL, where fB is an empirical parameter of value between

0 and 0.5. The integration yields


2 2
IDS = eff cf cf (2.23)
2 Cof (e+) L ( I + (meff/2VsatL) VDS) with Peff defined as


eff &(2.24)
1 fB B VDS



Interestingly, the direct use of the spatially independent mobility model (2.24) in the integration for IDS results in the same final expression (2.23) as derived more rigorously above. Therefore the simpler expression (2.24) for the effective mobility in (2.14) will be used in the subsequent analyses.



2.4 Saturation Region

In the saturation region of operation of the MOSFET, a high longitudinal electric field occurs near the drain, causing the carrier velocity in that region to saturate at vsat. The channel current in the saturated-velocity portion (see Fig. 2.4) can be expressed as

IDS(sat) W Qcf(Le) vsat (2.25)

where Le : L due to channel length modulation. For long-channel devices, (2.25) implies Qcf(L) = 0, which is the basis for the pinchoff model for the saturation characteristics [Sz8l]. Generally, (2.25) must be used explicitly to model these characteristics, accounting for

..









Gaussian surface


Y y= Le

eI D

I I


L. I
< X >
f eld-dependent setureted
velocity velocity






Fig. 2.4 Schematic cross-section along the length of the channel when
the SOI MOSFET is in saturation, showing the field-dependentand saturated-velocity portions.


Sourc


rain

..







23

channel-length modulation and impact ionization, both of which are closely linked to the velocity saturation.



2.4.1 Saturated Drain Current

In the saturation region, the channel may be divided into a portion (adjacent to the source), in which the carrier velocity is field-dependent, and another (near the drain) in which the velocity is saturated (see Fig. 2.4). At the boundary between the two portions, y = Le, and we define VDS(eff) A A'sf(Le) (5 VDS). Note then that at the onset of operation in the saturation region, Le = L and VDS(eff) VDS(sat), where VDS(sat) is the actual drain saturation voltage.

In the region 0 s y & Le, (2.23) with L and VDS replaced by Le and VDS(eff), expresses IDS(sat). This expression equated to (2.25) gives VDS(eff) as a function of Le:


~V DS~e)- Qcf(0)/Cof(l+a) (2.26)
1DS(eff) (Qcf(0)/Cof(1+a))(fBB +,p/2vsatLe) cf of Bsat e

1

1 + + fB B Qcf(0)/Cof(1+a) 1/2
2 + L- + [- B cf o]
2 4 [1 (Qcf(0)/Cof(l+a))(fBB + p/2vsatLe)]


Then IDS(sat) is fully characterized by (2.23) or (2.25), except for the description of Le, which is derived in the next subsection.



2.4.2 Channel-Length Modulation

Channel-length modulation, which is reflected by finite output conductance in the saturation region, is quantitatively defined by Ld A

..







24

L Le, the length of the portion of the channel in which the carrier velocity is saturated. Following the analysis (for the bulk MOSFET) of [E177a], we describe Ld by determining A'sf(y) and using the boundary conditions at y = Le and y = L.

Since the carrier velocity in the high-field drain region is saturated, the continuity of current in the steady state implies that Qcf(y) is spatially constant in the region. To derive a differential equation in Asf(y), Gauss's law is applied to a narrow strip in the region as shown (Fig. 2.4):


ds 22 [bAs dx CofAsf +CobAsb -AQcf cbAQ (2.27)
dy 0

Following the quasi-two-dimensional DICE analysis in Section 2.2, we approximate the left-hand-side of (2.27) as



s d2 [ s dx d2 [ Asf + sb ] (2.28)
dy 0 2 dy

Using (2.28) in (2.27), and the conditions that AQcb = 0 when the back is depleted or Asb = 0 when the back is accumulated, we obtain the following second-order differential equation in Asf(y):


d2 2 Cof (1 + a) (AT sf- V DS(eff)) 2
2 (sf) Cb2 + (2.29)
dy C b tb

where we have used AIsf(Le) = VDS(eff); a, 6, and j were defined previously. The boundary conditions for (2.29) are A'sf(L) = VDS and d(Asf)/dy = 2vsat/eff at y = Le. The general solution of (2.29), valid for Le y 5 L, is

..










A Devsat c sinh e s y-L 1 (2.30)
sf DS(eff) s [ 1 + 1
2v 1y-L 2 [cshE(2.30)
eff 1 1
where


1 tbb 1 /2 (2.31)
c t 2 Cof (1+a) ( I
of

For typical thin-film SOI MOSFETs, tb < L and the last term of (2.30) can be neglected. Then, using A1sf(L) = VDS in (2.30), we get



-1 Aeff (VDS DS(eff)
L L e L = 1 sinh DS(eff) (2.32)
sat c


The combination of (2.32) and the expression (2.26) for VDS(eff) gives a transcendental equation for Le which can be solved numerically in a few iterations.



2.4.3 Impact-Ionization Current

The flow of electrons through the high-field region near the drain causes impact ionization, which generates holes that flow into the MOSFET body and electrons that flow out the drain. To determine this generation current, for weak impact ionization, we first express the longitudinal electric field, E y -d(A~sf)/dy, using the analysis of

the previous subsection:



e 2 sf DS(eff))2
y E cosh E + 12 (2.33)
c 1 1
c -c

..






26

where E0O A -2Vsat/Peff. Since E0 is relatively small in the high-field region, (2.33) can be used to make the approximation that dEy/dsf

-1/1c.

The generation current IGi due to impact ionization is now defined in terms of an ionization integral in the drain region [E175, E177b]. Let M be defined as the multiplication factor of electron current (in an n-channel device) due to impact ionization and IDS be the channel current. Then

IGi (M-1) IDS (2.34)


It is noted that the bipolar current gain associated with the impact ionization [E177b], which is typically quite small, has been neglected in (2.34). The quantity (M-1) is approximated by the ionization integral as follows (a0 and P0 are assumed to be constant, and ED is the lateral field at the drain, defined by (2.33)):


(M-1) ED a0 e dy = D 0 e (dy/dTsf)(dW'sf/dE)dE
E 0/E 0

0 6 0E ef O E 60/
ED e E CED E eO/
0 c e dE 0 c E E 0
0 0

a0 l -0/ED
0 ED e (2.35)



The last two steps need some justification. The former is seen to be true, by expansion of the total differential, since 60 is typically much larger than E; the latter is true if E0 is small compared to ED. With the further assumption that ED (VDS-VDS(eff))/lc, the following expression for (M-1) is obtained:

..










I a0 "P01 c /(VDs- V DS(eff))
(M-1) (Vs- VDS(eff)) e (2.36)


The impact-ionization current (2.34), when incorporated in the model, accounts for the floating-body effects, e.g., the kink effect [E177b].



2.5 Charge-Based Model

In order to create a large-signal transient circuit model, the charge dynamics as well as the steady-state currents in the device must be described. To do this physically, the spatial dependences of the charges within the MOSFET are integrated out, and then the quasi-static approximation is used to express the charging current at each terminal as the time derivative of a charge associated with that terminal [Ar77, Wa78, Ya83]. For the SO1 MOSFET model, the voltage dependences of the integrated charges associated with the five terminals, QGf, QGb, QS, QD, and QB are derived below, based on the analyses in the preceding sections (with (2.24) for Peff in (2.14)). (See Appendix D for some of the mathematical manipulations used in deriving the following charge expressions.)



2.5.1 Triode and Saturation Regions

In the triode region, Gauss's law implies for the front-gate charge


L f
QGf W Cofr fO (V Gfs -: MS T sf) dy

..










V V2 (1 + s) (1 + a)
WLC V -- + 1 (2.37)
of IGf S M S "I +11 2 12 [-Qcf(0)/Cof] [1 u 2~ cf of 2

f
where 4MS is the front-gate work-function difference, and we define s SPeffVDS/2VsatL and uA -Qcf(0)/Cof(l+a)VDs; Qcf(0) = Qcf0 + AQcf(0) given in Section 2.2.

The source and drain charges comprise, in part, partitioned portions of the total channel charge QCH, which can be expressed as


L
QCH =W Qcf(y) dy
0

2 z (z-l)3
WLCof(1+a)VDS + (u-z) (2.38)
3 (2z-l)


where z A u (IDS/2vsatW)/Cof(l+a)VDS. Since the channel charge is distributed, the drain and source portions, QD(CH) and QS(CH), cannot be unambiguously defined. For the case of constant channel mobility, a partition of QCH that, to first order, accounts for the finite carrier transit time in the channel has been defined [Wa78, Li85, Fo86]. For the general case however, in which the mobility is spatially dependent (e.g., due to velocity saturation), Sevat [Se87] has proposed a

solution to the quasi-static charge-partitioning problem by assuming that the MOSFET is analogous to a ladder network. At any point y along the channel, he defines


aid 8I
gD A and gs A s
a(ATsf) a(ATsf)

..






29

which represent the differential conductances towards the drain and source. Then, the drain and source partitions can be defined as gD/(gD+gS) and gs/(gD+gS). In our case, the continuity equation can be integrated from y = 0 to arbitrary y to give


s eff s
Y + 2v Asf J0 effW Qcfd(Asf) (2.39)
s 2v0
sat

(2.39) is differentiated with respect to Asf and the quasi-static approximation is applied to Is (i.e. Is = IDS) to yield


= effW Qcf + Peff IDS/2Vsat (2.40)
gs (2.40)
y + effAsf/2vsat


Similar manipulation yields


D effW Qcf + Ueff IDS/2vsat (2.41)
gD (2.41)
L y + eff(VDs- AT sf)/2vsat eff DS sf sat

Then, the source and drain partitioning ratios are


gs L y + eff (VDS- A sf)/2vsat (2.42)
= (2.42)
gD + gs L + peffVDS/2Vsat
and

gD Y + eff(VDS- Asf)/2vsat (2.43)
~(2.43) gD + gs L + Meff DS/2vsat

These ratios are identical to those derived in a different manner by [Ya87]. However, for short-channel MOSFETs the specific partition assumed is not critical [Ya87], and for long-channel MOSFETs the ratios defined above become the same as those defined in [Wa78]. In the

..






30

absence of a compelling reason to use the more complicated formulation above, the simpler partition scheme [Wa78] is used in this work. Then, in the triode region,



QD(CH) = 0 L eQf(Y)dy


2 (z-l)3 4 [z 5- (z-l)5] (u-z)
= WLC(1+a)VDs + + -- (2.44)
3 (2z-l) 15 (2z-l) 2


and

QS(CH) = QCH QD(CH) (2.45)

To ensure charge neutrality, the body depletion charge shared by the source and drain (see Section 2.2.1), WL(Qb-Qb(eff))/2, must be accounted for in QS and QD. Also, the excess charge in the drain WLestby associated with DICE (refer to (2.11) and (2.12)) must be included in QD*

For the case of back-surface accumulation, Gauss's law implies for the back-gate charge



Gb = W Cob 0 (VGbS MS sb) dy
b
= WLCb (VGbS S- VBS) (2.46)

b
where MS is the back-gate work-function difference. The neutrality condition,


QGf + QGb + QS + QD + QB + Qff + Qfb -= 0 (2.47)


where Qff and Qfb are the fixed charges at the front and back interfaces, now defines QB*

..







31

For the case of back-surface depletion


QB WLQb ; (2.48)


then the neutrality condition (2.47) defines QGbIn the saturation region, the above charge expressions are used with L and VDS replaced by Le and VDS(eff) respectively, and are supplemented with additional components corresponding to the high-field region near the drain (Le 5 y 5 L). The previous analysis is used to derive these supplementary components: Qs 'D 12f [T [V L'c sat cosh e (.9
QGf= WCof [L-Le][VGfS- SI IVDS(eff) v- 1(249)
"eff Ic


QCH = W [L-L] Qcf (Le) (2.50)



Q(CH) = W Qcf(Le) [L2- L2/2L (2.51)

Qs =Qs -Qs (.2

QS(CH) = QCH QD(CH) (2.52)




2.5.2 Cutoff Region

In this subsection, a model for the cutoff region is derived, in a manner consistent with the strong-inversion model presented above. (As VGfS is made increasingly negative there is a possibility of incomplete depletion of the film, or even accumulation at the front surface. The analysis for these conditions follows bulk MOSFET theory [Sz8l] and is not included here.) This is done to ensure that there are no convergence problems during transient circuit simulation due to dis-

..







32

continuities in the charge expressions at the (model) boundaries between cutoff and strong inversion.

From the strong-inversion analysis above, the cutoff region is defined by the conditions IDS = 0 and Tsf0 < TI, i.e.,


VGfS & VTf P(Cb /Cof )(tb/L)2VDS (2.53)


In this region, with the film completely depleted,



sf sf + AI f(ff) [VGfS- VTf ]+ (Cb/Cof)(t/L)2VDS (54)
sf sf0 +Asf(off) [ Ijlj, .
1+ a 1 + a


where the terms due to the zero-VDS solution and the DICE solution have been separated. The last term on the right-hand side of (2.54) can be interpreted as a drain-induced barrier lowering [Tr79] in weak inversion, and complements the conductivity enhancement (DICE) in strong inversion.

When the back surface is accumulated, Wsb0 = VBS (as before). When there is depletion at the back surface, the following expression for Tsb in terms of Tsb0 and A'sb(off) can be derived:


Sb + Ai- V FB + (Qbeff/2Cob) + (Cb/Cob)9sfO
sb sb0 sb(off)1
1 + C b/Cob
Ab ob
+ Asf(off) + (tb/L)2VDS (2.55)
+ (2.55)
1 + Cb/Cob


Following [Ta78, Fig.8], it is assumed that (2.54) and (2.55) are valid from the source (y = 0) to the effective end of the channel (y = Le). To determine the channel-length modulation the (strong-inversion) analysis of the high-field drain region is extended to the cutoff case.

..






33

This extension can be justified by arguing that even for weak inversion carriers must flow by drift at the saturated velocity near the drain. The following expression for Aeff is used to get an expression for Le that is consistent with (2.32), which was derived for the strong inversion case:


=eff (2.56)
eff 1 + (BCof/2s) (2Cb(sfo Tsb0)/Cof Qbeff)




The effective channel length Le is then given by (2.32) with Peff in (2.56) and VDS(eff) 0.

Finally, following the analysis of Sec. 2.5.1, QGf is expressed as

1 2 2vsaL L-L

WLCo 4GfS M- sf 2- _a [cosh e -I (2.57)
oeff c


In the cutoff region, QCH M 0, and so are QD(CH) and QS(CH)- For the case of back-surface accumulation, QGb is given by (2.46) and then QB can be determined by the neutrality condition (2.47). For the case of back-surface depletion, QB and QGb are defined by (2.48) and (2.47) respectively.



2.6 SPICE2 Implementation

The complete network representation of the charge-based model (neglecting parasitic capacitances) is shown in Fig. 2.5. The model is quasi-static; the charging currents dQ/dt, as well as IDS and IGi are defined by the steady-state analysis. The diodes IR and IGt simulate, respectively, recombination associated with the source-body junction

..








Gf


4


IDS
E 0

dQs/dt
C)


Ig


dQG/dt




sG

dQDfdt

lot


RD
'VV-. D


--VV--* B

0
d~rbfdt


Gb


Fig. 2.5 Network representation of the quasi-static large-signal
transient model for the SOI MOSFET.


RS
So--v

..







35

(for VBS > 0) and thermal generation associated with the drain-body junction (for VBD < 0).

The model was implemented in SPICE2, initially via user-defined controlled sources (see Appendix A), and then by direct modification of the source code [Fi88]. The new SPICE2 model allows a maximum of five external terminals: if only four nodes are specified in the input deck, the body terminal is automatically assumed to be floating. For convenience, three separate models have been defined to account for SO1 devices fabricated on films of all thicknesses: the first two are the thin-film models described above with the back surface accumulated (TFA) and the back surface depleted (TFD), and the third is a semi-bulk

(SB) model derived by adding the back-oxide capacitance WLCob to the bulk-MOSFET model BSIM [Sh85]. It is noted that in the TFD model, VB, which is determined by Kirchoff's current law, is extrinsic in the sense that it does not affect IDS or the charges. The parameters for the model are listed in Table 2.1. In our implementation, we have neglected the bipolar current gain associated with the impact ionization because it is typically quite small. Within the model subroutine, numerical differentiation has been used to calculate the transconductance and transcapacitance matrices needed in the NewtonRaphson iterative solution. The lack of analytic derivatives does not seem to cause any significant degradation in convergence. At this (preliminary) stage of the modeling, the advantages of such a numerical approach seem to outweigh the disadvantages: it is very simple to make an addition to the model without having to worry about time-consuming re-calculation of the 24 independent derivatives.

..









TABLE 2.1

SPICE2 SOI MOSFET MODEL PARAMETERS

Name Description Units Default

Intrinsic

VFBF Front-gate flatband voltage V calc.
VFBB Back-gate flatband voltage V calc.
TOXF Front gate-oxide thickness cm 500e-8
TOXB Back gate-oxide thickness cm 0.5e-4
WKF Front-gate work function difference V calc.
WKB Back-gate work function difference V calc.
NQFF Fixed charge, front gate-oxide 1/cm2 0.0
NQFB Fixed charge, back gate-oxide 1/cm2 0.0

NSUB Substrate background doping density 1/cm3 l.Oe-14
NGATE Polysilicon-gate doping density 1/cm3 l.Oe19
TPG Type of gate material 1.0
+1) opposite to body
-1) same as body
0) aluminum
TPS Type of substrate 1.0
+1) opposite to body
-1) same as body

NBODY Film (body) doping density 1/cm3 calc.
PHIB Twice Fermi potential of body V calc.
TB Film (body) thickness cm 0.1e-4

UO Zero-field mobility cm2/Vs 550
THETA Mobility degradation coefficient cm/V l.Oe-6
BFACT VDS-averaging factor for p-degradation 0.0
VSAT Saturated carrier velocity cm/s 1.0e7

QSMO Charge-sharing parameter f0 0.7
QSMA Charge-sharing parameter fa 0.0
QSMB Charge-sharing parameter f 0.3

ALPHA Impact-ionization parameter 00 1/cm 1.6e6
BETA Impact-ionization parameter P0 V/cm 2.6e6

ETA On/off multiplier for DICE model 1.0 (ON)
LMOD On/off multiplier for channel-length
modulation model 1.0 (ON)


(contd.)

..









TABLE 2.1 -- continued


Name Description Units Default

Extrinsic

CGFDO Gate-drain overlap capacitance F/cm 0.0
CGFSO Gate-source overlap capacitance F/cm 0.0
CGFBO Gate-body overlap capacitance F/cm 0.0

RHOSD Source and drain sheet resistivity 0/square 0.0
RHOB Body sheet resistivity 0/square 0.0
RD Drain parasitic resistance 0 0.0
RS Source parasitic resistance 0 0.0
RB Body parasitic resistance 0 0.0

IRO Parasitic diode current coefficient A/cm 1.0e-10
N Parasitic diode emission coefficient 2.0

DL Channel-length reduction cm 0.0
DW Channel-width reduction cm 0.0

CIITOL Avalanche current tolerance A 1.0e-12


Note: The DC/transient/AC characteristics of the model are defined by
TOXF, TOXB, TB, VFBF, VFBB, NBODY, and UO. If these values are not specified, they are defaulted and/or computed (referred to in the table as "calc.") by SPICE from the given values. If the kink effect is negligible, consider making ALPHA and BETA zero to
improve execution time.

..









Transcapacitances

The charge dynamics are implicit in the model, and may be observed in simulations of the various transcapacitive coefficients (Cil A aQi/avl where i,l = Gf, D, B, Gb, or S). It is stressed that these transcapacitances are not to be viewed as conventional capacitors (and in fact cannot be properly represented by equivalent capacitors), but are nonreciprocal coefficients that mathematically describe the charge dynamics. To exemplify the physical nature of the model, simulations of the gate transcapacitances CGfS, CGfD, CGfGf, and CGfB (neglecting parasitic capacitances like overlap capacitances) for a short-channel device are plotted in Fig. 2.6. These transcapacitances predominantly control the charging of the front gate when the MOSFET is used as the driving stage of a CMOS inverter. In contrast to long-channel devices, where CGfGf in the saturation region does not depend on VGfS, for the short-channel device velocity saturation and the concomitant Qcf(Le) < 0 cause CGfGf to increase with VGfS [Iw87]. Similarly, CGfD, which is negligible for a long-channel device in saturation, is substantive in the short-channel device. These results correspond to biases on the back-gate that cause accumulation at the back surface and VBS 0, and are, in fact, strongly influenced by those biases. Simulation Example

To verify the implementation, various test circuits including CMOS inverters, sense amplifiers, static memory cells, and ring oscillators were simulated using the SPICE2 model. Fig. 2.7 shows a sample simulation deck and output voltages of a five-stage CMOS ring oscillator. For this simulation, all the body terminals of the MOSFETs

..









1.2
LL

-j

C 0.8L 2V 3V

f 0.6-
0 VDS = 0 V
-U 0.4- v--L 0.2- 2V s
C, I ,
U~3 V

01 2 3 4 5
VGFS (V)


1.2 A I
IL
a
h VDS = OV
.J. 1

L 0.8- 3V

0.6O 0 C-)
-J 0.4
IL
0 0. 20 OV 3V
U 0 itzmau t* ==awn:
0 1 2 3 4 5
VGFS CV)




Fig. 2.6 Simulated gate transcapacitances for an L = 2.0 pm SOI MOSFET
with the back surface accumulated (CGfGb = 0) showing the effects of velocity saturation. The solid lines correspond to the normalized CGfS and CGfGf, and the dashed lines
correspond to the normalized CGfD and CGfB.

..









*SVRON.C: UF/IEC/SVR 04/88
* FOR USE WITH VGB << 0 : NMOS IS TFA FLOATING, PMOS IS TFD
*VOLTAGE SOURCE USED TO TURN ON OSCILLATOR:
VON 1 0 PULSE 0.0 5.0 0 5N 5N 1 2
*POWER SUPPLY FOR ALL STAGES: VCC 5 0 5.0
VGB1 6 0 -10.0
*INPUT NAND GATE (FIRST STAGE):


ZNO 2 1 0 ZPO 4 1 5 ZN1 4 3 2 ZP1 4 3 5
*SECOND STAGE:
ZN2 7 4 0 ZP2 7 4 5
*THIRD STAGE:
ZN3 8 7 0 ZP3 8 7 5
*FOURTH STAGE:
ZN4 9 8 0 ZP4 9 8 5
*FIFTH (FINAL)
ZN3 3 9 0 ZP3 3 9 5
*DUMMY CURRENT


6 10
6
6 11
6


TFA TFD TFA TFD


ZNTFA ZPTFD
ZNTFA ZPTFD


L=2E-4 L=2E-4 L-2E-4 L=2E-4


W-10E-4 W=5E-4
W=10E-4 W=5E-4


6 12 TFA ZNTFA L=2E-4 W=5E-4 6 TFD ZPTFD L=2E-4 W-5E-4


6 13
6


TFA ZNTFA L=2E-4 W=5E-4 TFD ZPTFD L-2E-4 W-5E-4


6 14 TFA 6 TFD
STAGE:
6 15 TFA 6 TFD
SOURCES TO


ZNTFA L-2E-4 W=5E-4 ZPTFD L=-2E-4 W=5E-4


ZNTFA
ZPTFD MONITOR


L=2E-4 L=2E-4 VBODY:


W-5E-4 W=5E-4


AD=-1U
AD=lU AD=1U
AD=1U


AS=1U AS=lU AS=lU AS-lU


AD-lU AS=lU AD=-1U AS=lU

AD-lU AS-lU AD-lU AS-lU

AD=lU AS-lU
AD=1U AS-lU

AD=lU AS=lU AD=-lU AS=lU


IB0 10 0 0.0 IB1 11 0 0.0 IB2 12 0 0.0 IB3 13 0 0.0 IB4 14 0 0.0 IB5 15 0 0.0
*N-CHANNEL TFA MODEL: .MODEL ZNTFA NMOSOI NGATE=5E18 NSUB=1E13 NBODY=1E16 NQFF-O NQFB=O & TPS=1 TPG-1 TOXF-2.5E-6 TOXB-4.5E-5 TB-0.25E-4 RD-10 RS-5 RB=5
CGFDO-lP CGFSO-1P CGFBO-0.5P IRO-5N N=-1.8 QSMA-0.2 QSMB=0.6 ETA-1
DL=0 DW=0 UO=500 LMOD-1 ALPHA-1E6 BETA-2.6E6 WKF=0 WKB-0 THETA-3E-6 VSAT=-1E7 BFACT=0.4 CIITOL-IP
*P-CHANNEL TFD MODEL: .MODEL ZPTFD PMOSOI NGATE-5E18 NSUB=1E13 NBODY=1E16 NQFF=0 NQFB=0 & TPS--1 TPG=-1 TOXF=2.5E-6 TOXB=4.5E-5 TB-0.25E-4 RD=10 RS=10 RB=0 CGFDO-1P CGFSO-=P CGFBO=0 IRO=5N N-1.8 QSMA=0.2 QSMB-0.6 ETA=I DL=0 DW-0 UO=300 LMOD=1 WKF=0 WKB-0 THETA=3E-6 VSAT-1E7 BFACT-0.4


Fig. 2.7 (a) Input deck for SOI CMOS ring-oscillator simulator. Note
that we use VGbS = -10 V for the simulation, implying that the n-channel MOSFETs are TFA devices whereas the p-channel
MOSFETs are TFD devices.

..

































10 15 20
Time (s)


25 x 10-"


Fig. 2.7--continued (b) SPICE2-simulated output voltage V9 (solid
line) of the 7-stage SOI CMOS ring-oscillator circuit. Shown also is the body voltage V14 (dotted line) for the n-channel
MOSFET ZN4.


us-.
0
3


.3


I


-2
O

..






42

were left floating; the back-gate bias (VGbS = -10 V) was set to accumulate the n-channel MOSFETs and deplete the p-channel MOSFETs. Note that constant current sources of 0 A have been connected to the body nodes of the n-channel MOSFETs to be able to monitor the body voltages. As shown by the dotted lines in the simulation output (Fig. 2.7), the model predicts the correct transient VB(t) for the body terminal of one of the n-channel MOSFETs in the circuit.



2.6 Summary

A comprehensive charge-based large-signal transient model for the short-channel thin-film SO1 MOSFET in strong inversion has been presented. Although the model has been designed for use in circuit simulators like SPICE2, it preserves a substantial amount of the underlying device physics, and hence avoids large amounts of curvefitting, and can be used for predictive computer-aided device and circuit design. Furthermore, the fact that each dominant effect has been modeled separately enhances an understanding of the effects, and makes it relatively easy to incorporate extensions as necessary, without loss of self-consistency.

..














CHAPTER 3
MODEL VERIFICATION AND APPLICATIONS TO DEVICE DESIGN


3.1 Introduction

In Chapter 2, a physical model for the short-channel SOI MOSFET was derived. In this chapter it is verified, through measurements and simulations, that the model indeed predicts in detail the unique shortchannel effects in thin-film s il icon- on- insulator MOSFETs. In Sections 3.2-3.6 it is shown how these effects can be controlled by appropriate

biasing of the back-gate (i.e., the underlying substrate) and/or the film body, or by changing the film thickness. In general, this study reveals that the thre sho ld -voltage reduction by charge sharing [Ak82], drain-induced (channel) charge enhancement (drain-induced barrier

lowering [Tr79] in weak inversion), and channel-length modulation (and consequently, the saturated drain conductance) are best controlled by scaling the film thickness with the channel length and by biasing the back gate (substrate) to accumulate the back surface. However, it is shown that these improvements due to back-surface accumulation must be

traded-off for reduced saturated drain current, an increased inverse subthreshold slope and possibly increased hot-electron degradation problems. Finally, in Section 3.7, evidence is presented for a shortchannel effect unique to SOI MOSFETs whereby the back-surface charge condition (i.e., accumulation or depletion) depends on the device length as well as the applied drain bias.

..







44

3.2 Threshold-Voltage Reduction

In thin-film SO1 MOSFETs, the back gate participates in the depletion charge sharing [Ak82] with the front gate, source, and drain, and thereby influences the threshold-voltage reduction. In this section, previous studies [Se84, Co87b] of this effect are extended by characterizing its voltage dependences.

Consider a p-channel MOSFET of channel length L and uniform body doping ND fabricated on a thin SO1 film of thickness tb (Fig. 3.1). As long as TsbO stays constant as L is reduced, the reduction in threshold voltage AVTf due to charge sharing can be written as

A Lt V Q V d qN~t(

AVTfb(L,t IVTf(Qb) VTf(Qb(eff))' L (3.)



In Chapter 2, the distance d was related to the bias by defining it in terms of an effective electric field Eb(eff) (see Fig. 3.1):

sb Vb
d s i (3.2)
Eb(eff)


Eb(eff) comprises fringing fields from the back gate oxide, controlled by the back-gate bias VGbS, as well as the component from the junction depletion region. Note from (3.2) that for fixed Tsb0, an increase in Eb(eff) by any means will reduce d and hence the charge-sharing. For example, this may be done by increasing the film doping [De74].

When the back surface is accumulated by a large positive VGbS, qrsb0 is pinned at the body voltage VBS. In this case, AVTf is proportional to tb/L as in (3.1). Then, if the film is made thinner as its lateral dimensions are scaled, VTf will not decrease as much as if

..










I I


VGfS

I
I front oxide I


depleted /
S+ film / p
Sb( tb0bO


d


burIed oxide


I
VGbS


Fig. 3.1 P-channel SOI MOSFET showing the effective lateral field
Eb(eff) and distance d at the back surface that are used to
define the charge sharing.


T I


k1


m

..







46

tb were kept constant. This effect is demonstrated in Fig. 3.2 where measured AVTf versus L and VGbS are plotted for two sets of SO1 MOSFETs fabricated identically on SOT films of different tb.

In addition to the dependence on thickness, the measured AVTf plotted in Fig. 3.2 shows a dependence on VGbS. When VGbS is decreased to deplete the back surface, AVTf is increased. Based on the preceding discussion, this dependence is explained by noting that the fringing fields in Eb(eff) decrease and hence d in (3.2) and the depletion charge shared by the source and drain increases.

This effect of reducing the fringing fields on Eb(eff) is further clarified by a PISCES [Pi84) simulation of an L 1.0 pm SO1 MOSFET in strong inversion. The equipotential contours plotted in Fig. 3.3 for the cases of back-surface accumulation (VGbS 10 V) and back-surface depletion (VGbS 0 V) show that indeed as VGbS decreases, Eb(eff) decreases, causing d and AVTf to increase as mentioned above. (This trend is also discussed in more detail in Appendix B.)

Note in Fig. 3.3 that as VGbS is decreased and the back surface is depleted, Tsbo decreases, and ultimately would approach Vbi as the back surface is inverted. Thus, it is noted from (3.2) that the AVTf(VGbS) trend discussed above is reversed as (4sbO Vbi) approaches zero. This reversal is illustrated in Fig. 3.4, where measured AVTf versus VGbS are plotted for a MOSFET with a mask L = 1.0 pm, showing a maximum in AVTf, for fixed VBS, as the back surface is swept from accumulation (VGbS 20 V) to inversion (VGbS -5 V). (The dependence of AVTf on VBS follows the trend in bulk MOSFETs: as the reverse bias on the

drain-body or source-body junction is increased, AVTf increases due to

..














0.20


0.16



~ 0.12










0.00
0 2 4 6 8 10

L (pm)









Fig. 3.2 Threshold-voltage reduction AVTf(L) for two sets of SO1 pchannel MOSFET's of film thicknesses tb 0.8 ym (solid lines) and 1.3 pm (dotted lines) with identical processing schedules, at two different back-gate (substrate) biases, VGbS 20 V (0) and -5 V (A), corresponding to back-surface accumulation and depletion respectively; VBS 2 V in all
cases.

..























































Fig. 3.3 PISCES-simulated equipotential (T) contours in increments of
0.1 V for a tb 0.27 pm p-channel SOI MOSFET with (a) the back surface accumulated (VGbS 10 V) and (b) the back surface depleted (VGbS 0 V). Only the contours for Vbi < < Vbi+l are shown. In both cases, VDS 0 V (linear region), VGfS -2.5 V (strong inversion), and the (minority-)
electron quasi-Fermi level is set at 0 V.

..












Measured
4W.8 I I i 1
m


3W.8 VD 3 V




IM.8




I *. .
S S I
VS 8 V
a a a Ia a a a, I a
-5.8 9 5.8 19.9 15.8 28.8

VGbS (V)








Fig. 3.4 Measured threshold-voltage reduction AVTf(VBS, VGbS) for an L
1.0 pm p-channel MOSFET fabricated on an SOI film with tb
0.27 pm.

..






50

increased charge-sharing.) Other measurements reveal that the backgate bias at which the maximum in AVTf occurs depends on L.

With regard to scaled device design for minimum AVTf, it is noted that MOSFET operation with the back surface close to inversion is normally undesirable due to problems with leakage. Thus the only viable design options for SO1 MOSFETs are to scale tb with L, setting V~bS to accumulate the back surface, and/or to thin the back gate oxide, all of which tend to increase Eb(eff) and reduce the charge sharing. Of course, other design considerations, some of which are discussed herein, could imply necessary trade-offs as the device is scaled.



3.3 Drain-Induced Conductivity Enhancement (DICE)

When a large (negative) drain voltage VDS is applied to a short pchannel MOSFET, the channel charge is modulated indirectly through the two-dimensional Poisson equation in the film as well as directly through the induced gradient in i sf along the channel (the gradualchannel approximation [Sz8l] accounts for the latter effect). In this section it is shown how the former modulation, i.e. DICE, is affected by the back-surface charge condition in the thin-film SOI MOSFET.

From the DICE analysis of the previous chapter, the charge at the source end of the channel can be expressed as


Q (O)= C(Vfs Vf+ 6 s t(
cf fGfS Tf Cof L 2 VDS) (3.3)

=.Cof(VGfS- VTf(eff))


where 1 or 1 + Cb/(Cb+Cob) depending on whether the back surface is accumulated or depleted and VTf(eff) is defined, mathematically, as an

..







51

"effective" threshold voltage. For a given device and drain bias, the difference between VTf and VTf(eff) is a measure of the modulation of channel charge at the source due to the two-dimensional electric field in the film, i.e., due to DICE. Therefore, (3.3) implies that the the channel charge and hence the device conductance increasingly deviate from the values predicted by the gradual-channel approximation as P increases, or as the back surface goes from accumulation to depletion. Also, (3.3) implies that the two-dimensional DICE effect is enhanced as tb increases.

This control of the two-dimensionality of the potential distribution in the film is demonstrated by a PISCES [Pi84] simulation of the device in Fig. 3.3 with VDS -2.0 V. The equipotential contours plotted in Fig. 3.5 clearly indicate that the distribution is more twodimensional when the back-surface is depleted (VGbS = 0 V) than when it is accumulated (VGbS 10 V). This dependence on the back-surface charge condition is explained qualitatively by noting that the VDSinduced displacement in the depleted film (with fixed charge) must terminate on excess surface charge. Thus the presence of an accumulation layer at the back surface tends to limit the modulation of the (front-) channel charge.

In the saturation region of operation for VGfS VTf(eff) the pchannel current can be written approximately as


2 eff of2(34
IDS(sat) W Le (l+C) VGfS- VTf(eff) (3.4)



where a = Cb/Cof or CbCob/(Cb+Cob)Cof depending on whether the back

..






















































Fig. 3.5 PISCES-simulated equipotential contours in increments of 0.2
V for the SOI MOSFET of Fig. 3.3 with (a) the back surface accumulated (VGbS 10 V) and (b) the back surface depleted (VGbS 0 V). Only the contours for Vbi-2 V < T < Vbi+l V are shown. In both cases, VDS -2 V, VGfS -2.5 V, and the
(minority-) electron quasi-Fermi level is set at 0 V.

..







53

surface is accumulated or depleted. For VGfS VTf(eff), the effective mobility Aeff is virtually independent of VGfS, and the channel-length modulation that determines the effective channel length Le is controlled primarily by VDS. Thus, it is possible to estimate VTf(eff) from a plot of JIDS versus VGfS in the saturation region near threshold.

Measured VTf(eff)(L) characteristics of the tb = 0.8 pm p-channel device in Fig. 3.2, for different VGbS and VDS, are plotted in Fig. 3.6. These data confirm the conclusion derived above that the DICE effect is minimized when the back surface is accumulated. The effect of varying tb is shown by the data plotted in Fig. 3.7. Consistent with (3.3), these data reveal that the DICE effect is increased as tb increases.

With regard to scaled device design for minimizing the DICE then, the same criteria mentioned for minimizing AVTf apply. In this case, thinning the back gate oxide is effective in limiting the DICE effect because it enables the back gate (substrate) to accommodate some of the VDS-induced displacement.



3.4 Velocity Saturation and Channel-Length Modulation

In the saturation region of operation of a MOSFET, the drain current IDS(sat) and the incremental drain conductance gDS(sat) depend on the manner in which the carrier velocity in the channel saturates. This velocity saturation and the channel-length modulation it produces are important in short-channel devices because the channel charge that remains near the drain in the saturation region is proportional to the

..






54



-0.4



>
VGB = -3 V
-0.6









VGB = 3 V

-1.0 '
0 2 4 6 8 10

L (Rm)









Fig. 3.6 Effective threshold voltage VTf(eff)(L) for the tb 0.8 pm
MOSFET of Fig. 3.2, measured at VDS -2 V (+) and -5 V (x) for VGbS ranging from 3 V (back-surface accumulation) to -3 V (back-surface depletion); VBS 2 V for all the
measurements.

..











-0.6


,1


-0.7



-0.8



-0.9



-1.0


-1.1


2 4


Fig. 3.7 Effective threshold voltage
devices of Fig. 3.2, measured for tb 0.8 pm (solid lines)
VGbS 20 V and VBS 2 V.


6 8 10
L (pm)










VTf(eff)(L) for the p-channel at VDS -2 V (+) and -5 V (x) and 1.3 pm (dotted lines) with

..







56

current IDS(sat), which varies inversely with L. For SOl MOSFETs, there are additional dependences on the back-surface charge condition and on tb. In this section, it is shown that accumulating the back surface and/or thinning the film result in a reduction of IDS(sat), which is usually undesirable, as well as in a decrease of gDS(sat), which is usually desirable. Thus, in conjunction with the previous discussions, design trade-offs are implied.

For a long-channel thin-film SOI MOSFET, IDS(sat) l I/(l+a) [Li84b] as indicated in (3.4), and is accordingly decreased as the back surface charge condition is changed from depletion to accumulation. This decrease in IDS(sat) occurs because the transverse field in the film increases and, via Gauss's Law, causes a decrease in the channel charge for fixed (VGfs VTf), resulting in premature velocity saturation. As discussed above, this effect is exacerbated as the channel length is decreased. This is clearly seen in Fig. 3.8, where the normalized quantity IDS(sat)L, derived from measurements on a tb = 0.8 pm device with (VGfs VTf) and VDS fixed, is plotted versus L. The cases of back-surface accumulation (VGbS 20 V) and depletion (VGbS = 0 V) are shown in the figure. Additional measurements show the increase in IDS(sat) with increasing tb.

In addition to the variation of IDS(sat) with L, the drain

conductance gDS(sat) associated with the channel-length modulation is of interest. In Fig. 3.9, the measured normalized conductance gDS(sat)L is plotted versus L for the SOI MOSFET of Fig. 3.8. The plot shows that back-surface depletion results in an increase in gDS(sat) due to an

..












8000





7000





S6000




5000 I '
0 5 10 15 20 25

L (pm)







Fig. 3.8 Measured drain saturation current IDS(sat)(L), normalized by
l/L, for a tb 0.8 pm p-channel SOI MOSFET with (VGfS VTf) -4 V and VDS = -5 V for back-surface accumulation with VGbS = 20 V (0) and back-surface depletion with VGbS = 0 V (A);
VBS 2 V.

..













300


C4 IM


200 100


L (gn)


Fig. 3.9 Incremental conductance gDS(sat)(L),
derived from IDS(sa measurements for Fig. 3.8 (VGbS -201 (0) and 0 V (A))
lines) and 1.3 pm (dotted lines).


normalized by 1/L, the bias conditions of for tb 0.8 pm (solid

..







59

increase in channel-length modulation. This result is explained qualitatively below based on the model developed in Chapter 2.

In Section 2.4.2, Gauss's law was applied to the (thin) high-field region near the drain (where the carrier velocity is saturated) to determine a solution for the potential in that region. This solution was used to express the channel-length modulation Ld in terms of the terminal voltages, including VGbS:



L L-L e 1 sinh l Aeff1VDs_ VDS(eff) 1 (3.5)
de c 2 v 1
sat c


where 1c c (tb)1/2 was a characteristic length which depended on the film thickness as well as the charge condition of the back surface (via fl, which we introduced previously). This dependence reflects the twodimensional effect of the back-surface accumulation layer in limiting the potential variation in the film, and in confining all variations in potential to a region very close to the front surface of the MOSFET. A decrease in 1c has been related to an increase in the maximum longitudinal electric field in the drain region (Em (VDsVDS(eff))/lc), and a simultaneous reduction in the channel-length modulation [E177b, Hu85a]. Thus, back-surface accumulation (which

reduces P) and/or reduction in tb must result in reduced channel-length modulation, consistent with the measurements presented above.

To further clarify these effects on gDS(sat), PISCES-simulated IDS(VDS) for the L = 1.0 pm device of Figs. 3.3 and 3.5 (tb = 0.27 pm) at VGbS 0 V and VGbS = 10 V are compared with simulations of a similar device with tb = 0.135 pm (Fig. 3.10). In order to cancel out

..







60

the effect of variable VTf, all the simulations were done with (VGfSVTf) constant. From the plots it is evident that reduction in tb as well as back-surface accumulation tend to reduce the channel-length modulation as well as IDS(sat).



3.5 Hot-Carrier Effects

The above discussion is now related to previous studies on hotcarrier generation in SOI MOSFETs. Through accelerated stress tests, Colinge [Co87a] has shown that the lifetime of the MOSFET can be improved by depleting the back surface or by allowing the body to float with the back surface in accumulation. For a given VGfS, both these conditions result in a lowered VTf, and hence increased VDS(sat), and therefore a lowered electric field in the drain region. From the discussion in the previous paragraphs, the reason for increased

channel-length modulation in thicker films or when the back is depleted is similar: a decrease in the longitudinal electric field at the drain, which we have modeled in terms of 1c, Thus, a large lc correlates with reduced hot-carrier generation. It therefore appears that the use of ultra-thin SOI films and back-surface accumulation to improve shortchannel behavior would also result in increased device degradation problems. However, further experimental studies are necessary to

conclusively prove this deduction.



3,6 Subthreshold Slope

In the subthreshold region of operation, the inverse slope S dVGfS/d(ln(IDS)) is a useful indicator of the switching speed of the

..









0 x 10"


-10


-0












lines) p-channel MOSFET of Figs. 3.3 and 3.5 at VbS 0
1 -40 .****** .**.








5 V (back-surface accumulation) and VbS 0 V (back-surface
-5 -4 -3 -2 0
DRAIN VOLTAGE (V)









Fig. 3.10 PISCES-simulated IDS(VDS) curves for the tb 0.27 pm (solid
lines) p-channel SOI MOSFET of Figs. 3.3 and 3.5 at VGbS 10
V (back-surface accumulation) and VGbS 0 V (back-surface depletion) compared with simulations of a similar MOSFET with tb 0.135 pm (dotted lines) at the same bias conditions. All simulations were done with (VGfS VTf) = -5 V and the
electron (minority) quasi-Fermi level set to 0 V.

..






62

MOSFET. Most previous studies of the subthreshold behavior of thin-film SO1 MOSFETs [Ha85, Co87b, Yo87] have concentrated on the improvement (i.e. reduction) in S gained by thinning the film while simultaneously depleting the back surface. However, since this work indicates that back-surface accumulation while thinning the film may be a desirable design option for reducing short-channel effects, it is important to investigate this option in the subthreshold region. From the model given in Chapter 2 for the surface potential in the subthreshold region, simple predictions can be made about the dependence of subthreshold characteristics on the film thickness and back-gate bias. From (2.54) one can write dsf/dVGfS = I/(l+a). Since the subthreshold (diffusion) current is proportional to the inversion charge density at the source end of the channel which varies exponentially with Tsf, S is proportional to (1+a). Therefore, since a is larger for accumulation than for depletion and increases as tb is reduced, for thin films S is expected to be larger when the back surface is accumulated than when it is depleted. This prediction is confirmed in the PISCES simulations shown in Fig. 3.11, where the inversion charge density Qcf0/q (for VDS

0) is plotted against VGfS in the subthreshold region at different back-gate biases for the tb 0.135 pm MOSFET of Fig. 3.10. In fact, as the film is thinned further, our theory predicts that in the accumulation case a steadily increases towards infinity (implying that the device can never be turned on), whereas in the depletion case a approaches unity. This large bias-dependent variability in subthreshold slope is unique to thin-film SO1 MOSFETs, and can be considered a disadvantage of back-surface accumulation in a thin film.

..









10a2




1/
1

cm 107












-- 10a -V
N W.4 %A




VGB =1104V
z W






lo
0














-2_ .- 5 -2 -1. 5 -1 -0. 5 0
W









VGBS VGFS V












Fig. 3.11 PISCES-simulated inversion-charge density in the subthreshold
sI




102



101
-2.5 -2 -1.5 -1 -0.5 0
VGFS CV)




Fig. 3.11 PISCES-simulated inversion-charge density in the subthreshold
region of a tb 0.135 am p-channel SOI MOSFET showing the increase of the inverse subthreshold slope as the backsurface charge condition is changed from depletion (VGbS 0
V) to accumulation (VGbS 10 V).

..







64

3.7 Back Surface Charge Modulation

In the previous discussion, it has been implicitly assumed that the back-surface charge condition depends only on the applied biases VBS and VGbS. However, in this section it is shown that in general the back-surface charge condition is also dependent on L.

It is possible, with fixed VBS and VGbS, for a back-surface accumulation layer present in a long-channel SO1 MOSFET to be partially or completely depleted away by a sufficient reduction in L. This unique depletion charge-sharing effect in SO1 MOSFETs is reflected by comparisons in Fig. 3.12 of the linear-region IDs(VGfs;VBs) characteristics for a long and short device with VGbS fixed to accumulate the back-surface of the long-L device. For the long-channel device, the characteristics are seen to show a strong dependence on VBS and, correspondingly, a weak dependence on VGbS (not shown), as

expected for back-surface accumulation. These dependences are reversed for the short-channel device, as expected for back-surface depletion.

Similarly, any accumulation layer present at the back surface, for a given device, can be partially or completely depleted away by a nonzero VDS. This effect has been recognized previously even for long MOSFETs [Li84a], but in fact is exacerbated as L is reduced due to the two-dimensional potential distribution. The overall effect on the drain current can be quite dramatic, as is evident from a comparison of Figs. 3.13a and 3.13b, where we plot measured IDS(VDS, VBS) characteristics for a long (L 5 pm) and a short (L = 0.8 pm) SO1 MOSFET for fixed VGfS and VGbS. In the long device, the presence of an accumulation layer at the back surface allows the applied VBS to

..































Measured linear-region IDS(VGfS, VBS) characteristics of (a) a long (L 5 pm) and (b) a short (L = 0.8 pm) p-channel SOI MOSFET with tb = 0.27 pm and VGbS = 10 V set to accumulate the back-surface of the long-channel device.


Fig. 3.12

..






























-3.0


VGf E Volts 3


0 -2.8
VGf E Volts 3


-3.0

..
































Measured IDS(VDS, VBS) characteristics of (a) the long and
(b) the short SOI MOSFETs of Fig. 3.11, with VGbS = 10 V set to accumulate the back-surface of the long-channel device. In
(b) note the disappearance of the effect of VBS as either VBS or VDS is increased.


Fig. 3.13

..







-88.8

-68.8


S-48.8



-69.9



-2
-29.9


-1.9 -2.8 -3.0 -4.0 -5.9
VID I Volts 3


-2.8 -3.0
VD r Volts I


-5.8

..






69

modulate VTf, and therefore IDS- In the short-channel device, the backsurface accumulation layer is modulated away at large VBS and/or large VDS, and so IDS is much less dependent on VBS.

These back-surface charge modulations in short-channel SO1 MOSFETs can further cause a device designed (for long L) to operate as a semibulk MOSFET to behave as a thin-film device when L is scaled down sufficiently. With regard to SO1 circuit simulation, it is noted that most compact device models assume that the MOSFET operates with a spatially-uniform back-surface charge condition. Thus the length dependence of the back-surface charge condition must be incorporated into any model selection or parameter extraction algorithm.



3.8 Summary/Conclusions

It has been shown that the presence of the additional (back-)gate in SO1 MOSFETs can significantly affect their short-channel behavior. Through measurements and simulations, is has been shown that shortchannel effects like threshold-voltage reduction, drain-induced conductivity enhancement, and channel-length modulation can be controlled by thinning the SO1 film and/or by accumulating the back surface by an applied back-gate bias. However, these advantages of such controls must be weighed against a reduced drive current, an increase in the inverse subthreshold slope, and a possible increase in hotcarrier degradation. A unique short-channel effect in SO1 MOSFETs whereby a reduction in the channel length can deplete away the whole film, negating the control of device properties by the (film) body voltage, has been reported. In essence, then, the short-channel model

..







70

developed in Chapter 2 has been shown to be a useful intuitive guide in device design.

..
















CHAPTER 4
MODEL CHARACTERIZATION


4.1 Introduction

This chapter addresses the practical use of the S01 MOSFET model for simulation and design. As described in Chapter 2, the circuitsimulation model for the thin-film MOSFET has been separated into two models, one applicable when the back surface is depleted, and the other applicable when the back surface is accumulated. This separation, which

was done to avoid undue model complexity, results in rather unique characterization problems when applied to real devices. Since the specialized models are not valid in all regions of operation, a systematic measurement -based technique is required to evaluate the physical parameters needed for device simulation. Such a technique is presented below. First, in Section 4.2, the general applicability of the model to 501 films of all thicknesses is discussed, and criteria for model selection (i.e. the thin-film model versus an appropriately modified bulk NOSFET model) are presented. Then, in Section 4.3, an algorithm for extracting the parameters of the thin-film SOI model developed in Chapter 2 is presented and is applied to a contemporary 501 technology. The method described in Section 4.3 is to define measurements that isolate groups of parameters and then use simplifications of the model equations corresponding to those

measurements to evaluate the parameters individually. This enables the 71

..







72

examination of the inter -dependencies among the parameters, and the identification of reasonable simplifications of the model. In general,

the extraction scheme uses local optimization rather than a global optimization, and the parameters retain their physical values.



4.2 Model Selection Criteria

In the past years, the manufacturing trend for SOI MOSFETs has been generally aimed towards the use of thin films. The scaling and other advantages of such a trend have already been discussed in some detail by many authors and in Chapter 3. Unfortunately, present-day SOI

technologies produce device structures that make it difficult to ascertain in advance whether the S01 film is completely depleted or not

at a given bias condition. Depending on the film thickness, doping density, and channel length, an SOI MOSFET can behave as a thin-film transistor with a back gate that can influence the front-channel conductivity, or as an effective bulk transistor with a neutral, commonly floating body. For devices fabricated on a relatively thick film it may, in some cases, be more appropriate to use a bulk MOSFET model instead of the thin-film model derived in this work. Even for a thin-film device one must be able to distinguish between the two major modes of operation, namely, those with the back surface accumulated and depleted, if one wishes to extract physically meaningful parameters and' simulate the transistor well. In this section, a preliminary method for experimentally selecting S01 MOSFET models for circuit simulation through measurements of threshold voltage is presented. The selection

..







73

criteria are based on the thin-film SO1 MOSFET model, and on comparisons between it and the bulk MOSFET model.

Three compact MOSFET models are defined for each device type, one of which must be chosen as most representative. The three compact models are (1) the thin-film accumulated (TFA) model, which assumes back-surface accumulation, (2) the thin-film depleted (TFD) model, which assumes back-surface depletion, and (3) the semi-bulk (SB)

model, which is simply a bulk-device model [Sh85], to which (floating-) body effects (biasing) and an underlying body-back gate (substrate) capacitance are added. It is of course possible that the actual charge condition at the back surface may vary from accumulation to depletion (inversion is generally avoided) between the source and drain. It is shown in Chapter 5 that it is possible to model this condition, but the resulting model is complex, and a strategic selection of the TFA or TFD model would probably be sufficient in most cases. It must be noted here that this approach of defining simplified models is strictly valid only for SO1 MOSFETs used more or less conventionally, where the body and/or the back-gate biases are fixed. It will not in general apply to new applications of SO1 MOSFETs, for example in three-dimensional circuits, where novel circuit configurations involving large variations in VGbS may be used.

The threshold voltage VTf depends in general on both VBS and VGbS. For the case of back-surface accumulation in a long-channel MOSFET

[Li84a],


VTf Vf + (I+b)2-- VBs (4.1)
SFB B 2Cof

..







74

with a = Cb/Cof, and for back-surface depletion in a long-channel MOSFET,


f Qb b b
VTf VFB + 2B --- a V V 2B + ---] (4.2)
VTf = FB +2B Gb FB2Cof 2Cob


with a = CobCb/(Cob+Cb)Cof. It may be noted that for the accumulation case, VTf of the thin-film MOSFET is linearly dependent on VBS, whereas for the depletion case, VTf is not dependent on VBS. In contrast, VTf of the semi-bulk MOSFET has a nonlinear dependence on VBS:

f 1i/

VTf VFB + 2B + [2sqNA(2B- VBS)/2 (4.3)
Cof


which is applicable for VBS < 2DB, as are (4.1) and (4.2). With the above insight regarding the VBS-dependence, the model selection

criteria can be defined in terms of the measured VTf(eff) (see Section 3.3) in the saturation region. This definition is done in the saturation region, rather than the linear region, because the draininduced depletion under the gate tends to activate front gate-back gate charge coupling. For digital CMOS circuits, in which the transistors operate predominantly in the saturation region, this coupling is significant even though the devices may behave as semi-bulk MOSFETs for low VDS. Note that VBS will also influence the mode of operation since it affects the depletion of the body.

The methodology for SOI1 MOSFET model selection for devices with long L is detailed as follows. With VGbS biased for normal operation and the drain set at the supply voltage (VDD) for the circuit, IDS(sat) versus VGfS is measured for different values of VBS in the vicinity of

..






75

the normal operating body bias. (If the body is to float, then VBS 0 can be taken as the normal bias.) VTf(eff)(VBS, VGbS) is derived from the measurement as described in Section 4.3, and this dependence implies the proper model:

(a) if the dependence is negligibly weak [jdVTf(eff)/dVBSI << a in

(4.1)], then the TFD model is appropriate;

(b) if the dependence is linear [IdVTf(eff)/dVBSI a in (4.1)], then

the TFA model is appropriate;

(c) if the dependence is nonlinear and strong [IdVTf(eff)/dVBSI > a in

(4.1)], then the SB model is appropriate.

To demonstrate the above methodology, it is applied to p-channel SOI1 MOSFETs fabricated at Harris Semiconductor. The measured currentvoltage characteristics plotted in Fig. 4.1 were taken from an

enhancement-mode p-channel device fabricated in a 0.8-pm-thick arsenicdoped SIMOX film with a boron threshold-adjust implant that yields a net doping density of 2-3 x 1015 cm-3. The front-gate oxide thickness is 325 A, and that of the back gate is approximately 3700 A. The (long) channel length is 7.5 pm. The characteristics reflect, through the VGbS-dependence, the front gate-back gate coupling. Note that when VGbS is sufficiently positive, which implies accumulation at the back surface, the VGbS dependence disappears, reflecting either TFA or SB MOSFET behavior.

The proper selection is exemplified nicely by the measured VTf(eff) plotted versus VBS for different values of VGbS in Fig. 4.2. For the relatively thick SOI1 MOSFET the charge-coupling is controlled by VBS. For VBS relatively small, the device is adequately represented

..


















P 2.000/Cliv/VGBS -5V


U) 5V





.0000
.0000 -3.000
VGFS (V)








Fig. 4.1 Measured (saturation-region) current-voltage characteristics
of a p-channel SIMOX/SOI MOSFET with W/L 50 ym/7.5 pm. The square root of IDS(sat) is plotted against VGfS for VGbS ranging from -5 V (depletion at back) to +5 V (accumulation
at back) in 2 V steps; VBS 2 V and VDS = -5 V.

..











-.5


VGBS = -2.5V



OV


-1.0



I-I






-1.5 ,
0.0 1.0 2.0 3.0 4.0 5.0
VBS (V)









Fig. 4.2 Measured threshold voltage versus VBS for different values of
VGbS. The slope (a) of the VTf(VBS) characteristic in the TFA
region is indicated.

..







78

by an SB model (criterion (c) applies), but for larger VBS, the device is indeed a thin-film transistor. In this case, for VGbS :5 0 the TFD model (criterion (a)) is appropriate, but for VGbS > 0 the TFA model (criterion (b)) is the proper one.

In general, more emphasis should be placed on the linearity condition (4.1) in the model selection than on the actual value of a. One reason is that the model assumes a negligible interfacial region between the buried oxide and the silicon film, an assumption that becomes worse as tb is reduced, and so there can be a fair amount of error in calculating a from the process data. Besides, film thicknesses for most processes are specified based on data gathered before

transistors are actually fabricated on the wafer. Thus, typically, the effective film thicknesses are expected to be somewhat smaller than those specified. Also, the device processing, which in some cases involves a deep implant into the body to reduce leakage, can

effectively limit the maximum depletion layer thickness in the film, and thus the effective tb. In such a case, where the bulk MOSFET model is clearly inappropriate, the measured a can be used to define an effective film thickness for use in the model.

For MOSFETs with shorter channel lengths, the back-surface charge modulation effect discussed in the previous chapter can cause a device designed (for long L) to operate with a neutral/accumulation layer near

the back surface to actually behave as a thin-film back-surfacedepleted device when L is scaled down sufficiently. This implies that the length- dependence of the back-surface charge condition must, in general, be incorporated into the model selection defined above. For a

..







79

well-scaled technology, this should not be a problem except for very short devices. In this preliminary stage of the technology, however, it

is important to be constantly aware of this possibility, especially while extracting parameters as described below. In fact, other

subjective criteria can also be used, e.g., in n-channel MOSFETs the presence of a "kink" in the IDS(VDS) characteristics rules out the possibility of operation in the TFD mode.



4.3 Parameter Extraction

In Chapter 2, the general short-channel model for the thin-film SOI MOSFET was derived, with the physical and empirical parameters listed in Table 2.1. In this section we present and demonstrate the use

of an algorithm to extract the parameters required to simulate device characteristics. The general philosophy is to experimentally isolate as

many parameters as possible, thereby enabling their direct extraction from the measurements. The advantages of such a scheme over a global optimization method are, firstly, that it retains the physical meaning

of the parameters and hence the model, secondly, it enables one to examine the inter-relations among the extracted parameters, and lastly, that it is less time-consuming.

In principle, to characterize all the model parameters, only three test devices are required: one with a large L and W, one with a short L and long W, and one with a long W and short L. However, it is prudent

to use as many test devices as available to minimize errors in the measurement and extraction process. Since narrow-width effects are highly technology- dependent, it seems premature to quantify them; the

..






80

focus here is exclusively on the short-channel effects instead of a more general treatment.

N-channel MOSFETs fabricated at Harris Semiconductor with nominal SO1 film thickness 0.25 pm, channel doping density approximately 1017 cm-3, and a nominal buried-oxide thickness of 0.45 pm are used as test vehicles. The mask lengths of the test transistors are 25 pm, 5 pm, 2.5 pm, 1.7 pm, 1.3 pm, and 1 pm, with effective channel lengths down to approximately 0.6 pm; the (wide) channel widths are all 50 pm. The drain and source regions adjacent to the channel are lightly doped using oxide-spacer (LDD) technology to reduce the maximum lateral electric field.

The measurements and much of the subsequent data analysis are done with the TECAP characterization system [He85] run from an HP-217 desktop computer. The TECAP system allows the user to make measurements remotely using any instrument connected to an IEEE-488 standard interface, store the measured data, and then compare and fit the measurements to a user-specified model. The steady-state portion of the short-channel model detailed in Chapter 2 is implemented as a Pascal procedure in TECAP. The model contains 8 nodes (which can collapse to as few as 5 nodes if the parasitic resistances are neglected) and has the same topology as the SPICE2 model previously described. This allows the user to check that the extracted parameters adequately simulate the measured current-voltage characteristics. In addition, various user-defined commands were added to enable the automated extraction of quantities like threshold voltage and conductance.

..







81

The general extraction procedure comprises the following steps. (Lm and Wm are used to denote the mask-lengths and widths, and L and W to denote the corresponding electrically effective quantities, i.e., the values used in the model. Similarly, voltage differences, e.g. VGfS, VDS, etc. are used to denote the biases applied to the intrinsic device; for the terminal voltages, VGf, VD, etc., which are referenced to Vs,are used.)

(a) VTf is measured in the linear-region as a function of VGb and VB.

The measured VTf for the MOSFET with the longest Lm (where,

presumably, there are no short-channel effects) is used to

f b
determine values for the parameters tb, tob, VFB, VFB, and possibly NA. The VTf measurement is also used in the model selection and the determination of channel-length reduction and parasitic

resistances.

(b) The incremental channel resistance at VD = 0 V is measured as a

function of VGf and Lm (and Wm), and used to extract values for channel-length reduction AL (and channel-width reduction AW) due to processing, parasitic resistances RS and RD, mobility po, and

mobility degradation factor 9.

(c) The electrical channel lengths (and widths) extracted in (b) are

used with the short-channel VTf model to find the empirical charge-sharing parameters that fit the short-channel VTf values

measured in (a).

(d) The body current IB and drain current ID are measured as a

function of VD and VGf in the saturation region with the body reverse-biased. This information is used to extract the

..







82

coefficients a0 and P0 for the generation current due to impact ionization, as well as to estimate the recombination current Iro

and body resistance RB.

In the following sub-sections, each of the above steps is described in more detail, with discussions of the possible sources of measurement error and how they can be avoided. The final extracted parameters are listed in Table 4.1 at the end of the chapter.



4.3.1 Threshold-Voltage Measurements

The threshold voltage VTf in the linear region is controlled by tof, tb, tob, VfB, VFB, NA, and the empirical charge-sharing

parameters. Usually, tof can be determined independently (from C-V measurements), or can be assumed to be given by the process data (in our case 25 nm). To determine the rest of the parameters, their relative importances in the various possible operating ranges must first be considered. For long-channel devices, the model for the TFA

f b
case depends on tb, VFB, and NA, and does not depend on tob and VFB. The TFD model, however, is affected by all the parameters listed above. For shorter channel lengths, the characterization of the charge-sharing model in either the TFA or the TFD case depends on parameters common to both models. There are the additional possibilities noted previously that the SB model may be appropriate in certain bias ranges and that the back-surface charge modulation (Chapter 3) is important in shortchannel devices at certain bias conditions, but not at others. In summary, it is very difficult to completely decouple the parameter extraction of the TFA and TFD (and SB) models while continuing to

..







83

retain an acceptable level of confidence in the physical nature of the extracted parameters. Therefore the algorithm for the calculation of VTf is extended to simultaneously account for the TFA, TFD, and SB regions of operation so that VTf can be calculated as a continuous function of both VBS and VGbS. The details are in Appendix C.

VTf is experimentally determined from the linear-region ID(VGf) characteristic measured at a small value of VD (usually around 50 mV). A common technique for extracting VTf is to find the tangent to the ID(VGf) curve at the point of inflexion, and then subtract VD/2 from the x-intercept of the tangent. This gives a value of VTf relatively independent of the actual (small) value of VD used in the extraction. It has been noted that the presence of a parasitic series resistance (e.g., due to the LDD structure) comparable in magnitude to the channel resistance in the linear region can cause an underestimate of VTf [Hu87a]. With this potential problem, then, the measured VTf can be in error by as much as 25 mV, a factor which is relatively unimportant in the determination of the charge-sharing parameters, but can cause errors in the determination of channel-length reduction. (If the

differences in measured VTf over a range of channel lengths were less than 25 mV, it is probably good enough to assume that there are no short-channel effects in that range!)

In Fig. 4.3 the measured VTf are plotted against VGb for different reverse biases VB for the Lm = 25 pm test device. From the plot, and from other measurements similar to the ones in Fig. 4.2, it is deduced that the MOSFET operates in the SB mode for VB 0 V. For the larger values of VB shown, the thin-film models are applicable, with the

..






84








2.5


VB -2 V

2.9-Ve -2 v> 1. 5-
YB-I
>. 1.9- --a



8.5
m

g I 1 I| .i
S-5.9 -10.8 -15.0 -28.8
VGb )









Fig. 4.3 Measured VTf for a long (L 25 pm) n-channel SOI MOSFET
(solid lines connecting the '+' symbols) plotted against VGb for VB ranging from 0 V (semi-bulk) to -2 V (thin-film). The dashed lines are simulations using the parameters in Table
4.1 and the general VTf model in Appendix C.

..







85

distinction between the TFD (VGb = 0 V) and TFA (VGb = -20 V) modes of operation becoming obvious for the VB -2 V curve. More detailed measurements of VTf(VB) at VGb = -20 V (which are not shown here) indicate that the MOSFET is strictly an SB device at VB = 0 V in the linear region, but is for all practical purposes a TFA device at small body reverse biases (VB < -0.5 V), and should be modeled as a TFA device for those biases.

The extraction procedure begins then with the measurements on the Lm = 25 pm device at VGb -20 V. The slope of the VTf(VB) curve at VB = 0 V (SB) correlates well with the doping density of 1017 cm"3 given from the process data, and hence it is reasonable to fix NA at that value. For more negative VB, the VTf(VB)-data is linear (TFA), and is fitted to the model equation (4.1) to yield an approximate value for tb and VFBf. Then, fitting the measured VTf-data at VB = -2 V and VGb near
b
0 V (TFD) to (4.2) yields an approximate value for tob and VFB. With these initial estimates then, the Levenberg-Marquardt nonlinear leastsquares-fitting algorithm in TECAP [Wa82, He85] is used to optimize
f ,b -2 mMSE
tb, VFB, tob, and VFB to fit the measured VTf for the Lm 25 pm MOSFET over the wider range of VB and VGb values for which measurements are done. Fig. 4.3 also shows the simulated VTf using parameters optimized after six iterations of the extraction algorithm. It may be noted that the parameter values obtained (see Table 4.1) are physically reasonable: the extracted tb was 0.18 pm, which is comparable to the
f
process specification of 0.25 pm; VFB correlates well with the workfunction difference due to an n+-polysilicon gate; the difference between the extracted tob 0.39 pm and the process-specified 0.45 pm

..






86

can be explained by the fact that the capacitance due to surface-states at the back interface (which has not been explicitly modeled here) adds

to Cob causing a reduction in the extracted tob. Due to the uncertain nature of the interfaces between the buried oxide and the film and substrate regions, no comments can be made regarding the physical

b
nature of the extracted VFB, except that it enables a good f it to the measured data.



4.3.2 Linear-Region Conductance Measurements

The accuracy of the physical model is greatly dependent on the accuracy of the channel length used in simulations. Usually, L and W are less than the mask length and width Lm and Wm due to lateral diffusion during the processing of the MOSFET. It can be usually assumed that the reductions AL (-. Lm L) and AW (- Wm W) are constant for devices of all lateral dimensions on the same die. Since the channel current in the linear region for a given gate bias is, to first order, proportional to Wui0/L, measurements of the incremental channel resistance in that region for various gate drives can be used to extract AL, AW, and p0o. However, any measurement of the channel resistance will necessarily include the parasitic RS and RD. If it is assumed that for a given device width, RS and RD are constant for devices of all channel lengths, AL, RS, and RD can be determined for a given W as follows.

At VDS 0 V, (2.23) implies

..








dIDS 1 1
[ DS ]i ON
dVDsI (V DS- 0) ON gDS

0 L L [1 + 0[2Cb( I- sb0)-Qb(eff)]/2Es]
RS+ RD+ + (4.4)
S2csWo o W Cof [VGfS- VTf]



Laux [La84] has shown that for LDD MOSFETs where the parasitic resistances can be a function of the gate voltage, the assumption of constant resistances is accurate enough for extraction of AL. In this work, a slight modification of his method has been used. (Equation (4.4) can also serve as a basis for extracting AW by exploitation of the W-dependent terms in it.)

Equation (4.4) indicates that for constant (VGfS VTf), RON is proportional to L, and therefore plots of RON versus the channel mask length for various (VGfS VTf) define straight lines that intersect at (AL, RS + RD). In practice, due to the variation of VTf with L, it is inconvenient to measure resistance with fixed (VGfS VTf), so RON is measured as a function of VGf instead, and the (VGfS VTf)-1

relationship in (4.4) is used to determine (intermediate) values for a fixed set of (VGfS VTf) values by interpolation. (Note the implicit assumption that VGfS VGf.) Figure 4.4 shows a typical set of measured RON data plotted versus (VGfS VTf)-1 for four channel lengths and with VGb -20 V and VB -1 V (TFA). For a fixed set of values of (VGfS VTf), which will not in general correspond to measured values, the values of RON are found by interpolating the data of Fig. 4.4. It must be noted that the choice of (VGfS VTf)1 is critical to the final parameters extracted. For VGfS values near VTf, errors in the

..







2500


2000 -


1500


z
0
C

1000 U)
w
2,


r


500-


0.5 1
1/(VGFS VTF)


1.5


(1/V)


Fig. 4.4 Measured incremental resistance RON at VD 0 V plotted
against 1/(VGfS VTf) for SOI MOSFET's of four different channel lengths. In all cases, VGb -20 V and VB -1 V,
making the thin-film model applicable.


5 um











2.5 um 1.7 umrn 1.3 um

..







89

measurement of VTf (as discussed in the previous subsection) can cause large errors in the interpolated resistances. Furthermore (4.4),

which is based on the strong inversion model of Chapter 2, is itself invalid for values of VGfS close to VTf. Based on this insight, then, further extraction is limited to measurements made for the largest values of VGfS. In the particular example chosen, (VGfS VTf) varies from 2.0 V to 3.5 V. Plotting these (derived) resistances then versus channel mask length (Fig. 4.5) for the various (VGfS VTf) defines a family of straight lines which in principle should have a well-defined intersection point (AL, (RS + RD)). In practice, due to measurement errors, there is no well-defined intersection point, and another linear regression is needed to determine the desired parameters [La84]. From (4.4), it may be noted that the slopes A and y-intercepts B of the fitted lines in Fig. 4.5 are linearly dependent as follows:


B (-AL)A + (RS + R D) (4.5)


Thus a plot of B versus A (Fig. 4.6) defines a straight line, with the slope equal to -AL and the y-intercept equal to (RS + RD). Since the processing of the drain and source regions are identical, it can further be assumed that RS = RD, resulting in an extracted value of approximately 23 0 for these devices. This value can be compared to the resistance of the LDD region which is expected to be the dominant factor in RD. With an approximate LDD length of 0.2 pm, doping density of 1018 cm-3 (implying PLDD = 250 cm2/V-s [Sz8l]), and a conducting area of 0.1 pm x 50 pm, a value of 10 0 is obtained, which is quite close given the approximations made in the estimation. It must also be

..







5000


4500 4000 3500 3000 2500


2000 1500 1000 500


0


Fig. 4.5 Interpolated values of RON for three values of i/(VGfS VTf)
plotted against mask length.


5 10 15 20
MASK LENGTH (MICRONS)

..







10



0



-10


-40



-50


-60



-70
100


150 200


250


A (OHMS/MICRON)





Fig. 4.6 Y-intercepts (B) of the linear fits to the data in Fig. 4.5
plotted against the corresponding slopes (A) for (VGfS VTf)
ranging from 1.5 V to 3 V in equidistant steps.

..






92

noted that the value AL extracted is not necessarily exact, and could be in error for any given device by as much as the error in Lm [Sc87], which can be 0.03 pm or so depending on the technology used.

Additional information can be extracted from the slopes of the fitted straight lines in Fig. 4.5 [Mo82]. From (4.4), the slope A can be expressed as:

[1 + 0[2Cb(FI- TsbO)-Qb(eff)]/2Es] +
A = + (4.6)
Ao W Cof (VGfS- V Tf) 2esWA



Thus, a plot of A versus (VGfS VTf)"I (e.g., Fig. 4.7) is a straight line, and its slope and y-intercept can, in principle, be used to estimate both yo and 0 simultaneously from (4.6). We extracted Po = 537 cm2/Vsec, which was found to be adequate for simulating the I-V characteristics. However, the intercept of the fitted straight line was much smaller in magnitude than the values of A used in the fitting, causing the extracted 0 to be very sensitive to the specific range of VGf values used in the extraction. This sensitivity can be attributed to the fact that at low VGf, mobility degradation is too insignificant to be detected by RON measurements, and at high VGf, there can be confusion in distinguishing between the effects of mobility degradation and the parasitic resistances. In general, a statistical correlation between the extracted values of (RS + RD) and 0 is expected. However, the error in the extracted (RS + RD) is expected to be small, mainly due to the fact that more devices with short L (where the voltage drop in the series resistance was significant) were included in the

parameter extraction than devices with long L (where mobility

..







240 220 200


180 160


140 120100 /
0.3


0.4 0.5 0. 6


1/(VGFS VTF)


0. 7


(1/V)


Fig. 4.7 Slopes (A) of the linear fits to the data in Fig. 4.5 plotted
against l/(VGfS VTf) for (VGfS VTf) ranging from 1.5 V to
3 V in equidistant steps.

..






94

degradation is more important). In summary, it was found that the value extracted for 0, 0.3 cm/MV, was an under-estimate, and had to be adjusted to 0.5 cm/MV so that the TECAP model simulations fitted the measured linear region ID(VGf) curves for the Lm = 25 pm MOSFET. This value compares favorably with the value 0.7 cm/MV that can be derived from the mobility model presented in [Ga87] (which differs only

formally from our model in Chapter 2). In retrospect, it appears that instead of extracting 0 from conductance measurements, it is better to estimate it as some representative value, e.g. 1 cm/MV, and then adjust it to fit the measured ID(VGf) curves for the longest device as indicated above.



4.3.3 Determination of Empirical Charge-Sharing Parameters

With the values of the effective channel length established for each device by the procedure in Section 4.3.2, and the values for tb,
f b
VFB, tob, and VFB determined from the VTf-measurements on the Lm 25 pm MOSFET, the charge-sharing parameters f0, fc, and fp are optimized as before (with the VTf(VBS, VGbS, L) model in Appendix C) to fit the measured VTf-data for the rest of the MOSFETs. All the VTf-data measured (ile., from devices of all channel-lengths) were used to reduce any possible errors in the parameters due to an error in determination of L. However, it turned out that the parameters extracted were fairly insensitive to such considerations. Fig. 4.8 shows the good fits obtained for the Lm 1.0 pm and Lm = 1.3 pm devices. Similar or better fits were obtained for all the other devices as well, with an overall maximum error of 5 percent, and a mean-square

..


Full Text
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