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Schottky clamped MOS transistors for wireless CMOS radio frequency switch applications

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Schottky clamped MOS transistors for wireless CMOS radio frequency switch applications
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Huang, Feng-Jung, 1970-
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ix, 158 leaves : ill. ; 29 cm.

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Bipolar transistors ( jstor )
Circuit switching ( jstor )
Drains ( jstor )
Electric potential ( jstor )
Insertion loss ( jstor )
Inverters ( jstor )
Oxides ( jstor )
Signals ( jstor )
Transistor circuits ( jstor )
Transistors ( jstor )
Dissertations, Academic -- Electrical and Computer Engineering -- UF ( lcsh )
Electrical and Computer Engineering thesis, Ph.D ( lcsh )
Metal oxide semiconductors, Complementary ( lcsh )
Radio frequency ( lcsh )
Semiconductor switches -- Design and construction ( lcsh )
Switching circuits -- Design and construction ( lcsh )
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bibliography ( marcgt )
theses ( marcgt )
non-fiction ( marcgt )

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Thesis:
Thesis (Ph.D.)--University of Florida, 2001.
Bibliography:
Includes bibliographical references (leaves 153-157).
General Note:
Printout.
General Note:
Vita.
Statement of Responsibility:
by Feng-Jung Huang.

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SCHOTTKY CLAMPED MOS TRANSISTORS FOR WIRELESS CMOS RADIO FREQUENCY SWITCH APPLICATIONS













BY
FENG-JUNG HUANG









A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY



UNIVERSITY OF FLORIDA


2001













ACKNOWLEDGMENTS


I wish to express my deepest gratitude to my advisor and supervisory committee chair, Dr. Kenneth K. 0, whose constant support and patient guidance provided a clear path for my research. Through my time on this research I have learned a tremendous amount and am grateful for his encouragement and advice. I would also like to thank Dr. Sheng S. Li, Dr. Mark E. Law, and Dr. Randy Y. Chow for helpful discussions and suggestions.

I have been quite fortunate to have worked with my colleagues: ChihMing Hung, Yochuol Ho at Texas Instrument, Brian A. Floyd, Namkyu Park and Meng-Hsueh Chiang at the University of Florida; Kihong Kim, Jesal Mehta and Carlos Gamero at RF Micro Devices, Hyun Yoon at Motorola, Saket Bhatia at Valence Semiconductor, and all the members of SiMICS (Silicon Microwave Integrated Circuits and Systems) research group, especially Seong-Mo Yim, Dung-Jun Yang and Tod Dickson. I thank all of them for encouragements and being good friends.

My special thanks go to Courtney Hazelton at Texas Instrument for bonding the 0.5-pm switches, and Al Ogden and Steve Schein for the equipment support and instruction on packaging. I highly appreciate the support from National Science Foundation and a Texas Instrument graduate fellowship.













I am most pleased to acknowledge the support, encouragement and helpful discussions on statistical matters regarding measurements from Dr. Chen-Pin Wang at the University of South Florida. Without her, this research work would not have been possible.

I would also like to thank my friends, my parents and my family, especially my father, sisters, Melody and Vivian, Melody's husband, Scott, and my nephews, Sean and Dean, for the support and joy they brought me throughout my graduate study at the University of Florida.













TABLE OF CONTENTS



ACKNOWLEDGMENTS .................................................................................... ii

A B STR A C T ....................................................................................................... vii

CHAPTERS

1 INTRODUCTION .................................................................................. 1
1.1 Transceiver: An Overview .............................................................. 3
1.1.1 Receiver .................................................................................. 3
1.1.2 Transm itter ............................................................................ 5
1.2 Figures of Merit of RF Switches ..................................................... 5
1.3 Concerns for CMOS RF Switches ................................................... 7
1.4 Sum m ary ......................................................................................... 11


2 SCHOTTKY BARRIER DRAIN MOS TRANSISTORS ....................... 14

2.1 Introduction .................................................................................... 14
2.2 SBDR MOS Transistors ................................................................ 15
2.2.1 SBDR MOS Device Structure ............................................ 16
2.2.2 SBDR MOS Device Characteristics .................................... 17
2.2.3 Parasitic Bipolar Actions .................................................. 20
2.3 Sum m ary ....................................................................................... 21


3 SCHOTTKY CLAMPED DRAIN MOS TRANSISTORS .................... 23

3.1 Introduction .................................................................................. 23
3.2 SCDR NMOS and PMOS Transistors .......................................... 24
3.2.1 SCDR MOS Device Structure ............................................ 24
3.2.2 SCDR MOS Device Characteristics .................................... 27
3.2.3 SCDR Junction Characteristics .......................................... 31
3.2.4 Determination of Barrier Height ........................................ 36
3.2.5 Conclusion ............................................................................ 39
3.3 SCDR CMOS Structure with Reduced Layout Area ................... 40
3.3.1 SCDR CMOS Structure ...................................................... 40
3.3.2 Parasitic Bipolar Actions ................................................... 42














3.3.3 SCDR CMOS Inverters with Reduced Layout Area ....... 45
3.4 Sum m ary ....................................................................................... 48


4 CMOS RADIO FREQUENCY SWITCHES ........................................ 50

4.1 Introduction .................................................................................. 50
4.2 Schottky Clamped MOS Transistors ............................................. 51
4.2.1 RF Characteristics .............................................................. 51
4.3 Design and Optimization of RF Switches ................................... 55
4.3.1 Insertion Loss and Conductive Substrate .......................... 56
4.3.2 MOSFET-based RF Switch Design .................................... 63
4.3.3 DC Bias Condition of SPST RF Switches ........................... 67
4.3.4 Experimental Results of 900 MHz SPST Switches ............. 69
4.4 Sum m ary ....................................................................................... 70


5 SCHOTTKY DIODE CLAMPED MERGED DRAIN CMOS STRUCTURE
.................................................................................................................... 72

5.1 Introduction .................................................................................. 72
5.2 SCMD CMOS Transistors ............................................................ 73
5.2.1 SCMD CMOS Device Structure .......................................... 73
5.2.2 Parasitic Bipolar Actions ................................................... 76
5.2.3 Schottky Clamp Length ..................................................... 78
5.3 SCMD CMOS Inverters ................................................................ 85
5.3.1 SCMD CMOS Inverter Characteristics .............................. 85
5.3.2 SCMD CMOS Inverter Chains .......................................... 88
5.4 Sum m ary ....................................................................................... 91


6 SINGLE-POLE DOUBLE-THROW CMOS RF SWITCHES ................. 93
6.1 Introduction .................................................................................. 93
6.2 900-MHz 0.5-jm SPDT Switches ...................................................... 94
6.2.1 Design of 0.5-jim SPDT RF Switches ................................. 94
6.2.2 DC Bias for RF Switches ....................................................... 100
6.2.3 Measured Results of Conventional MOSFET Switches ...... 101 6.2.4 Measured Results of SC MOSFET Switches ........................ 105
6.2.5 Reliability Issues of 0.5-gm MOSFET Switches ......... 106
6.2.6 C onclusion .............................................................................. 112
6.3 900-MHz and 2.4-GHz 0.35-gm SPDT Switches ............. 113













6.3.1 Design of 0.35-gm SPDT RF Switches ................ 114
6.3.2 Measured Results of 900-MHz Switches .............................. 118
6.3.3 Measured Results of 2.4-GHz Switches ................................ 121
6.3.4 Reliability Issues of 0.35-pn MOSFET Switches ................ 123
6.4 Impedance Transformation for High Power RF Switches ............. 125
6.4.1 Design of Impedance Transformation Networks ................. 125
6.4.2 Experimental Results and Discussion .................................. 131
6.5 Sum m ary .......................................................................................... 142


7 SUMMARY AND FUTURE WORK ...................................................... 144
7.1 Sum m ary .......................................................................................... 144
7.2 Future W ork .................................................................................... 146

APPENDIX S21 OF A SHUNT Y-SERIES Z NETWORK ........................... 149

RE FER EN CE S ............................................................................................... 153

BIOGRAPHICAL SKETCH ........................................................................... 158













Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

SCHOTTKY CLAMPED MOS TRANSISTORS FOR WIRELESS
CMOS RADIO FREQUENCY SWITCH APPLICATIONS By

Feng-Jung Huang

May 2001

Chairman: Kenneth K. 0
Major Department: Electrical and Computer Engineering


The feasibility of implementing integrated radio-frequency (RF) complementary metal-oxide-semiconductor (CMOS) switches is demonstrated. The most challenging part of developing CMOS RF switches is the impact of the semiconductive nature of silicon substrates. This degrades insertion loss, limits the power handling capability of switches and may also trigger latchup in CMOS circuits due to a forward biased junction in an integrated switch when the output is mismatched.

Schottky clamped metal-oxide-semiconductor (MOS) transistors for high power RF circuit applications have been implemented in foundry CMOS processes with no process modifications. The use of Schottky clamped MOS transistors in RF switches reduces the minority carrier injection into the body













of the transistors when the source/drain-to-body junctions are forward biased, and this reduces susceptibility to latchup for the surrounding CMOS circuits.

To achieve insertion loss of less than 1 dB in CMOS switches, substrate resistances associated with the transistors are minimized and junction capacitances of the transistors are reduced in order to decrease signal coupling to the substrate and thus reduce substrate loss. Through layout optimization, substrate resistances of less than 20 Q in a 0.5-jm CMOS process using p+ substrates, and substrate resistances of less than 10 Q in a 0.18-jm CMOS process using p- substrates have been achieved. These substrate resistances are low enough to make the substrate effect on insertion loss small. In addition, bias voltages have been optimized to ensure that the transistors operate within a safe voltage region while the voltage swing required to turn on source/drain-to-body junctions is increased, and thus the power handling capability of the switch is maximized.

CMOS RF switches are demonstrated in 0.5-jM and 0.18-pm CMOS processes using 3.3-V MOS transistors. At 900 MHz, the measured insertion loss is as low as 0.5 dB which is competitive to commercially available GaAs switches. At 2.4 GHz, insertion loss is 0.8 dB which is also comparable to that of GaAs switches. The power handling capability of CMOS RF switches has been increased to 24 dBm by using impedance transformation networks.













These are the first CMOS switches to have sufficient performance for ISM band applications near 900 and 2400 MHz. This dissertation work has demonstrated that it is feasible to use bulk silicon CMOS technologies to implement RF switches, which will reduce the cost of RF switches and thus reduce the cost of radios.













CHAPTrER 1
INTRODUCTION


The rapidly increasing demand for digital cellular phones, digital cordless phones and wireless local area network (WLAN) applications have bloomed the market for radio-frequency integrated circuits (RFIC's) [1]. These circuits need to be low cost, to have low operating voltage and low power consumption, and to be small in size with increased functionality. Several semiconductor technologies, gallium arsenide (GaAs), silicon germanium (SiGe), silicon bipolar and silicon complementary metal-oxide-semiconductor (CMOS), are being used to implement radio-frequency (RF) circuits. The GaAs technology has been one of the major technologies for RF applications, especially for high power components such as power amplifiers (PA) and transmit/ receive (TR) switches, due to a higher breakdown voltage, higher electron mobility, and the advantages associated with the semi-insulating nature of GaAs substrates [1-21.

The recent speed improvement of digital CMOS transistors has made it feasible to implement wireless radio-frequency transceivers and their subcomponents in silicon CMOS technologies [3-51. As the feature size of CMOS technologies is scaled down to the deep sub-micrometer regime, the frequency at which CMOS transistors can operate while delivering acceptable performance








should increase. This has increased the possibilities for CMOS RF circuits meeting the stringent requirements of communication systems. A higher level of integration can be achieved with CMOS technologies compared to GaAs technologies. These, along with the potential for lower cost, have made RF CMOS technologies and circuits topics for intense research.

The goals of this dissertation work are to study the feasibility of implementing a critical circuit block used in the RF transceiver front end called the radio-frequency transmit/receive switch, and to study the limitations on the performance of RF switches imposed by the CMOS technology. A high quality microwave switch is a key building block of the RF front end for time-division duplexing (TDD) systems. In recent years, GaAs field-effect-transistor (FET)based switches have been the dominant technology for the RF T/R switch due to their low direct current (DC) power consumption compared to traditional microwave p-i-n diode switches. For RF TJR switch applications, switches built in semiconductor integrated circuit (IC) technologies with insulating substrates (such as GaAs and CMOS/silicon-on-sapphire (SOS)) have significant advantages compared to those fabricated in a bulk CMOS technology [1]. A typical GaAs FET-based switch achieves a 25-dBm P1dB with 0.8 dB insertion loss and 24 dB isolation at 2.4 GHz [6]. A CMOS/SOS switch demonstrates an input-referred third-order intercept point of 18 dBm, with a 1.7-dB insertion loss and greater than 30-dB isolation at 2.4 GHz [7]. Another CMOS/SOS switch with a 1.0-dB insertion loss and 29-dB isolation at 2.0 GHz [8] has been demonstrated. The power handling capability is not reported. Insertion loss








and power handling capability of these CMOS/SOS switches are not very good. More importantly, the cost for CMOS/SOS integrated circuits is considerably higher than that of bulk CMOS integrated circuits.

Despite the fact that a MOS transistor is a natural switch, no MOSFET single-pole double-throw (SPDT) T/R switches suitable for wireless applications at 900 MHz and higher have been reported prior to this dissertation work [9-10]. In this dissertation, RF switches built in bulk CMOS technologies intended for operation in the L band near 1 to 2.6 GHz are developed. Unlike the other previously reported high power GaAs T/R switches [2], [61, the RF switches are implemented in low cost digital CMOS processes and do not require any process modifications and negative control voltages [6].


1.1 Transceiver: An Overview

In this section, operation of the building blocks of an RF front end, which includes a receiver, a transmitter, a frequency synthesizer, a power amplifier and a T/R switch, is discussed. A simplified block diagram of a cellular radio is shown in Figure 1-1 [111. This radio includes RF front end, intermediate-frequency (IF) modulation/demodulation and baseband signal processing circuits.


1.1.1 Receiver

In the receive mode, the T/R switch connects the antenna to the receive path. The RF signal is received by the antenna and passed through the T/R








switch. The T/R switch should have low insertion loss to reduce its impact on noise performance of the receiver. Also, the T/R switch should have good isolation to block the transmit band signal from being fed into the input of the receiver. The received signal is amplified by a low noise amplifier (LNA) followed by an image rejection filter. To avoid overloading the LNA by out of band signals appearing at its input, a bandpass filter (BPF) precedes the LNA. This filter can also be used to reject images. The image rejection is needed to keep the unwanted frequency components from being fed into the input of the RF mixer in order to reduce the unwanted signal at the mixer output. The RF mixer down converts RF signal to intermediate frequency (IF) using the frequency synthesizer output. IF signal is then demodulated by the I/Q demodulator. The output signal of the ADC is used by a digital signal processor to reconstruct the message.

The requirement of a global system for mobile (GSM) receiver is that a 102 dBm signal at the input of the receiver must be detected with a bit error


Figure 1-1 Simplified block diagram of a cellular radio.








probability (BER) of less than 10-4. The system must also be able to reject a 0dBm out-of-band single-tone blocking signal, a -23-dBm in-band single-tone blocking signal and a -43-dBm in-band two-tone blocking signal.



1.1.2 Transmitter

In the transmit mode, the input message is first processed by the digital signal processor to generate in-phase and quadrature-phase data streams. The data streams are then modulated with IF LOs followed by an IF filter. The IF signal is mixed using an RF LO. Finally, the RF signal is filtered and amplified by a power amplifier, and is fed to the antenna through the T/R switch. The T/R switch should provide a low loss path for the transmit signal to the antenna and should also provide a high power handling capability. The peak transmit power requirement of a T/R switch is 30 dBm for GSM, 20 dBm for CT3, 10 dBm for CT2 [12] and between 10 to 30 dBm for north American industrial, scientific, and medical (ISM) band applications [13].


1.2 Figures of Merit of RF Switches

Key figures of merit of an RF switch are insertion loss (IL), isolation and power handling capability. The insertion loss measures the power loss through the RF switch when the switch is turned on. The power loss ratio, PLR, is [14]


PLR = Power Available from Source PAVS 1 Power Delivered to Load PLoad 1 - I lL2









This quantity can be shown to be the reciprocal of I S21 12 if both load and source are matched to the characteristic impedance. The insertion loss in dB is


IL = 10 logPLR (1.2)


The insertion loss of an RF switch is particularly important for the transmitter, because it determines how much of the power delivered by the PA is lost before it reaches the antenna. The insertion loss also can have a profound effect on the receiver. The insertion loss of a switch is the noise figure of the switch. The insertion loss of the RF switch if poor can limit the noise figure of the entire receiver. Thus, it should be sufficiently low, typically less than

1 dB.

The off-state of an RF switch is characterized by its isolation. The definition of isolation is the same as insertion loss. However, isolation measures the power leakage through the RF switch when the switch is turned off. Isolation of an RF switch should be as high as possible to isolate the transmitter and receiver.

The power handling capability of an RF switch is characterized by its power 1-dB compression point (PldB). This parameter is determined by the non-linearities of a switch. Another parameter characterizing the non-linearity of a switch is the third-order intercept point (IP3). The PjdB of a switch is defined as the output power level at which the operating power gain (Gp) of the switch deviates from the small signal power gain by 1 dB. High PldB of a








switch denotes a high power handling capability of the switch. IP3 of a switch is defined as the point where the extrapolated output power curve of the desired signal and power curve of a third order intermodulation component intersect [15]. The input referred IP3 of the device is denoted as the IIP3. In general, the output of an RF switch, when the non-linearity effects are included, has a voltage transfer function that can be written as a Taylor series:

Vout a0 + alvin + a2vin + a3vin +... (1.3)


where vin and vout denote input and output voltage of the switch, respectively and ao, a,, a2, ... are constants. If the input to the system consists of two relatively closely spaced tones at co, and o)2, the vin3 term will generate the thirdorder products at (2co1-o)2) and (2o02-01) which cannot be filtered, even in a narrow-band system [14]. High IP3 means the amplitudes of these third order products are low.


1.3 Concerns for CMOS RF Switches

The power handling capability is a crucial parameter of CMOS RF switches. It is extremely difficult to transmit power in excess of 30 dBm through a switch operating from a low voltage supply (3 V or less). The two problems are maintaining linearity in the on-state and maintaining isolation in the off-state. Junction isolated silicon technologies in particular have great








difficulty in meeting these performance requirements due to the possibility of forward biasing the source/drain-to-body junction diodes during large power excursions at the input and output of the switch [1]. The 30-dBm corresponds to a - 20-V peak-to-peak voltage swing at the output of an RF switch with a 50- load. In CMOS RF switch applications, this 20-V peak-to-peak voltage could easily forward bias the source/drain-to-body junctions of MOS transistors. Simulations for a MOSFET switch with a 50- load in Figure 1-2 illustrate this problem. The available power from the source is 10 dBm in the simulation. The NMOS source/drain-to-body junctions are forward biased when the signal appeared at source and drain swings below the voltage at body (VB) of the MOS transistor. These forward biased junctions not only limit the power handling capability of the switch but also may inject minority carriers into the body of nearby transistors and trigger latchup. This problem can be alleviated by applying DC bias to increase the reverse bias of the source/ drain-to-body junctions. This increases the RF voltage amplitude required to forward bias the junction and thus improving the power handling capability [16]. However, even after applying the DC bias, the maximum RF voltage amplitude still can be limited by the requirement of reverse source/drain-tobody junction bias. Especially, the large RF signal in combination with the output mismatch can still forward bias the junction and trigger latchup as shown in Figure 1-3.

Normally, a transmit/receive (T/R) switch is connected to an antenna, which has a nominal input impedance of 50 U However, this impedance














Input Voltage, VIN
0-0 Drain Voltage, VD
H-u Source Voltage, Vs
- 0Body Voltage, VB

2.01 71N


12.0


11.0
Time (ns)


Figure 1-2 Simulations for a MOSFET switch with in a 50- system.


changes with surrounding structures. Because of this, the switch is required to withstand the voltage or survive the stress even when the output load is mismatched (< 10:1 voltage standing-wave ratio (VSWR)). For instance, when the output load is 500 1% VSWR is 10:1. Figure 1-3 shows the output voltage waveform when the loading condition is 50 and/or 500 Q with 3.0-V reverse










� � 6V
10kOW. = Bias T


.. .. ^ .. - - B, . . . . . . .:
,,,.V1N=3+6sin(2nft) .RB-30QL
_ =GHjz " RL=50Q
T "=" Ior 5000 ~~W/L---612/0.5 (P~m/IW)


10.0 , ,

8.0

S6.0
0
-i 4.0 CF

a)2.0
0) CO 0
> 0.0

-2.0


0.0 10.5 11.0 11.5 12.0
Time (ns)


Figure 1-3 Simplified circuit schematic of an NMOS switch with 500- load
and simulated waveforms at corresponding nodes for the circuit.




biased source/drain-to-body junctions. The available power from the source (PAvs) is about 20 dBm. Under the 50 il load condition, source/drain-to-body junctions are never forward biased. However, for the same input voltage, when the load is 500 4 the NMOS source/drain-to-body junctions are forward


Input Voltage, VIN O--- Drain Voltage, VD 0 Body Voltage, VB
RL=500
*---*Drain Voltage, VD +-*Body Voltage, VB
RL=500C








biased (when the source and drain voltage swings below the voltage at body

(VB) of the MOS transistor). Incidentally, a similar situation exists for RF power amplifiers.

These are serious issues for integrating CMOS RF switches with other circuits. This latchup issue caused by integrated RF switches built in bulk CMOS technologies must be solved before the switch can be integrated with the rest of the transceiver circuits.


1.4 Summary

MOS transistors using Schottky barrier contacts as drains have been developed to reduce the parasitic bipolar actions and the susceptibility to latchup in CMOS technologies. The proceeding chapters will describe the development of MOS transistors using Schottky barrier contacts to reduce latchup susceptibilities for CMOS RF switch applications, and also design and operation of RF switches and their components.

Chapter 2 describes an initial design of integrated Schottky barrier drain MOS transistors with radically reduced susceptibility to latchup and the concerns for the structure. Chapter 3 presents an improved structure, a Schottky clamped drain MOS transistor which exhibits identical output I-V and turn-on characteristics to those of a conventional MOS transistor, while exhibiting radically reduced parasitic bipolar effects. Design for Schottky clamped drain CMOS structures for CMOS RF switch applications is also discussed.








Chapter 4 describes the frequency response of Schottky clamped MOS transistors compared to conventional MOS transistors and design of CMOS RF switches. The effects of substrate resistances and source/drain-to-body capacitances associated with MOS transistors on insertion loss of RF switches have been analyzed showing that substrate resistances and source/drain-tobody capacitances need to be reduced to decrease insertion loss. Single-pole single-throw RF switches were implemented in a 0.5-jim CMOS process. Measurements have been done to understand the feasibility of using conventional CMOS processes to implement single-pole double-throw CMOS RF switches.

Chapter 5 describes a brand new device concept, Schottky diode clamped merged drain MOS transistors for digital CMOS circuit applications. Using Schottky diode clamped merged drain transistors, a 100-stage inverter chain has been implemented. The inverter chain exhibits similar performance to those of conventional CMOS inverter chains while layout area is - 22% smaller. This reduced area should decrease the cost of CMOS integrated circuits.

Chapter 6 presents design, implementation and demonstration of 900MHz and 2.4-GHz single-pole double-throw RF switches, and discusses the reliability issues of RF switches. The 900-MHz switches were implemented in a 0.5-gm CMOS process and also using 0.35-gm 3.3-V MOS transistors in a 0.18-jm CMOS process. The 2.4-GHz switch was implemented using 0.35-jm 3.3-V MOS transistors in the 0.18-jm CMOS process. Impedance transformation networks are used to reduce the RF voltage amplitude at the input and





13

output of RF switches to increase the power handling capability of CMOS RF switches. The use of impedance transformation has increased the power 1-dB compression point from 17 dBm to 24 dBm. Lastly, chapter 7 summarizes this dissertation work and suggests possible future research work.













CHAPTER 2
SCHOTTKY BARRIER DRAIN MOS TRANSISTORS


2.1 Introduction


In bulk CMOS integrated circuit applications, especially for high power applications such as RF T/R switches, it is sometimes unavoidable to have a large voltage signal swing below ground or above supply voltage in some portions of a cycle and thus forward biasing the source/drain to body junctions of MOSFET's as discussed in the previous chapter. This forward biased junction not only limits the power handling capability of the switch but also may trigger latchup. This latchup issue needs to be solved before the switch can be integrated with the rest of the CMOS transceiver circuits. A MOS transistor using Schottky barrier contacts as source and drain reduces the susceptibility to latchup in CMOS [17-181. In this work, the feasibility of integrating Schottky barrier contacts in a foundry 0.8-pm CMOS process without making any process modifications is investigated.

An insulated-gate field-effect transistor (IGFET) using Schottky barrier contacts for source and drain was first proposed in 1968 [19]. The device characteristics are comparable to those of conventional IGFET's at room temperature. The forward and reverse characteristics of silicon Schottky barrier diodes have also been studied extensively [20-24]. Silicon Schottky barrier








diodes with near ideal I-V characteristics can be obtained by using a diffused guard ring [20], a double diffused guard ring [211, and moat-etched techniques [22]. Schottky barrier diodes have also been widely used for microwave networks because of their excellent high frequency behavior [251. Due to the fact that the minority carrier injection from metal-semiconductor contacts of Schottky barrier diodes is negligible in most cases [261, Schottky barrier diodes have been used as source and drain for MOS transistors to reduce the latchup susceptibility associated with CMOS technologies [17-181. Unfortunately, the works reported by Swirhun et al. [17] and Sugino et al. [181 required modifications of the process or suffered from device characteristic degradations which truly limit their applicability.

In this chapter, an experimental MOS transistor, the Schottky barrier drain (SBDR) MOS transistor [27], which radically reduces latchup susceptibility is presented. The structure is implemented in a foundry 0.8-pm Salicide CMOS process. Implementation of the devices does not require any process modifications. The foundry Salicide CMOS process used is similar to those in Peng et al. [281 and Chapman et al. [291. Measured transistor characteristics and current gains of parasitic bipolar transistors of a 1.2-jm SBDR PMOS transistor are discussed.


2.2 SBDR MOS Transistors

In this section, a Schottky barrier drain (SBDR) p-channel MOSFET fabricated in a conventional 0.8-gm foundry CMOS process without making








any process modifications is described. A potentially useful feature of such a device is that the parasitic p+-drain/n-well/p-substrate bipolar transistor actions of CMOS technologies are not present since Schottky barriers do not inject minority carriers. Due to the fact that there is no minority carrier (hole) injection from the Schottky-barrier-drain-to-n-well, current gains of the parasitic drain/n-well/p-substrate transistor structure are negligible. This type of structure could be useful for reducing the latchup susceptibility in integrated RF switch applications where source/drain-to-body junctions could be forward biased due to the high input RF power level.



2.2.1 SBDR MOS Device Structure

A cross section of the SBDR PMOS device structure is shown in Figure 2-1. The gate length and channel width are 1.2 jm and 12.0 pum, respectively.



SBDR Gate Source Body


Figure 2-1 Cross-section of an SBDR PMOS transistor.








A major difference between the SBDR and conventional transistors is that the SBDR device is asymmetric. On the drain side, the lightly doped drain (LDD) and source/drain implantations were masked to form a TiSi2-Si Schottky barrier contact. The Schottky barrier contact replaced the p+-to-n-well junction. At the source side, a conventional source structure was utilized to maintain the turn-on characteristics of the MOS transistor.


2.2.2 SBDR MOS Device Characteristics

Figure 2-2 shows the output I-V characteristics of 1.2-un SBDR and conventional PMOS transistors. The threshold voltage of the device in the reverse mode of operation (using the Schottky barrier contact for source instead of drain) is very high because the LDD region is not present on the drain side. In the forward operation (using SBDR), this absence of the LDD region also prevents current conduction until VDS is lowered below -0.3 V, or VDS is decreased sufficiently for the depletion layer associated with the Schottky-barrier-drain to merge with that of the MOS structure which allows draining of holes from the channel. This phenomenon obviously is not observed in the conventional MOSFET device. The SBDR structure has a higher drain to source saturation voltage (I VDSSAT I )_ At VGS= -2 V, the conventional device will saturate when VDS reaches -0.8 V. However, the SBDR transistor will not saturate until VDS= -2 V at VGS= -2 V. In addition, the source current at VDS = VGS= -5 V is 1.3 mA which is 300 juA lower than that of the conventional












-1.5
VGS= -5V



E -1.0
CO
_ ~~_ .. o...............



//// ..,::.2:ii............ ....=-...
-0.5 P .....


oo. ...... ...ii iiii';i ii~lii il

0.0 -1.0 -2.0 -3.0 -4.0 -5.0
VDS (Volt)


Figure 2-2 Measured IDS-VDS characteristics for conventional and SBDR
PMOS transistors.


device. This is due to a higher series resistance in the SBDR transistor than in the conventional MOSFET. This is a concern for RF power MOS applications, and needs further improvements. Another concern is the reverse leakage current of the SBDR junction. The leakage current was about 13 pA at a 5-V reverse bias and the junction breakdown voltage was about 6 V, and once again, further improvements are needed. Despite these, the overall characteristics of the SBDR-MOS transistors are promising.

Figure 2-3 shows the drain current dependence on VGS of 1.2-pjm conventional and SBDR MOS transistors. When VDS= -0.1 V, the SBDR MOS









-0.25
conventional 1.2-jim PMOS transistor ..-.-.-1.2-gm SBDR-MOS transistor




E


\fDS=-1V



.-" ,VDS=.0.lV


0.0 A
-0.5 -1.0 -1.5 -2.0
VGS (Volt)


Figure 2-3 Measured IDS-VGS characteristics for conventional and SBDR
PMOS transistors.


transistors will not turn on because the absence of the LDD region on the drain side prevents current conduction. When VDS= -1 V, turn-on characteristics of the conventional and SBDR MOS transistors start to look similar and when VDS= -5 V, turn-on characteristics of the conventional and SBDR MOS transistors are very similar. Once again, when VDS is decreased sufficiently for the depletion layer associated with the SBDR to come in good contact with that of the MOS structure, turn-on characteristics of the conventional and SBDR MOS transistors become similar.








2.2.3 Parasitic Bipolar Actions


Figure 2-4 shows Gummel plots of drain/n-well/p'-source parasitic structures for the conventional and SBDR MOS transistors. The drains serve as the emitters of the bipolar transistors. As expected, the collector current associated with the minority carrier injection is very small for the SBDR MOS transistor. Only a small amount of collector-base (p+-source-to-n-well) junction reverse leakage current was present. This in turn should eliminate the parasitic drain/n-well/p-substrate bipolar action.


_10-2 I-


E _106
I3
d


_1 0-8


_10-1o


-0.2


-0.4 -0.6


-0.8


-1.0


VBE (Volt)

Figure 2-4 Gummel plots of drain/n-well/p+-source parasitic pnp bipolar
transistors for conventional and SBDR PMOS transistors.


m Ic of conventional PMOS
-0- IB of conventional PMOS . -. Ic of SBDR PMOS
* - IB of SBDR PMOS


A .0 r * . -0 " - "


m- A' Mm


VCB=OV








2.3 Summary

A p-channel MOSFET using a Schottky barrier contact for the drain has been demonstrated using a 0.8-gm foundry CMOS process. Fabrication of the structure requires no additional mask or process step in the Salicide CMOS process. Measurements showed that SBDR MOS transistors suffer from high drain to substrate leakage current and low breakdown voltages [30] as well as reduced drain currents. The reverse junction leakage current of SBDR junctions was about 13 gA at a 5-V reverse bias and the SBDR junction breakdown voltage was about 6 V. Using this structure, it is possible to eliminate the parasitic bipolar effect due to the p+-drain/n-well/p-substrate structure. This should allow unintentional forward biasing of the drain-to-n-well junction in power RF applications with significantly reduced latchup susceptibility.

Despite the fact that the Schottky barrier drain was separated from the channel by a spacer oxide region, p-channel Schottky barrier drain MOS transistor characteristics were surprisingly good. However, n-channel Schottky barrier drain MOS transistors failed due to the absence of the LDD region. Lastly, the "soft" reverse characteristics of SBDR junctions need improvements.

The work reported by Li et al. [31] has shown that the effective barrier height of Ti-silicon Schottky barrier diode can be increased to as high as 0.96 eV by using low energy ion implantations. The enhancement of effective





22

barrier heights of Schottky barrier diodes should reduce the reverse leakage current of SBDR junctions and increase the junction breakdown voltage.













CHAPTER 3
SCHOTTKY CLAMPED DRAIN MOS TRANSISTORS


3.1 Introduction


MOS transistors using a Schottky barrier contact as a drain have been demonstrated by implementing the transistor in a conventional Salicide CMOS process. The SBDR structure has shown the feasibility of implementing MOS transistors using a Schottky barrier contact as a drain to reduce the latchup susceptibility. However, the high junction leakage current, low breakdown voltage and reduced drain current of SBDR MOS transistors are serious problems.

In this chapter, a transistor structure called Schottky clamped drain (SCDR) MOS transistors [32] is presented. This structure radically reduces the latchup susceptibility while achieving the same drive current as conventional MOS transistors. Implementation of SCDR MOS transistors is similar to SBDR MOS transistors, and requires only simple layout changes but does not require any process modifications. The structure is demonstrated in a 0.8gm foundry Salicide CMOS process.

The parasitic NMOS-drain/p-substrate/n-well (DPN) and PMOS-drainl n-well/p-substrate (DNP) bipolar transistor actions of CMOS technologies are greatly reduced by using the SCDR structure since Schottky barrier diodes








which do not inject minority carriers clamp the drain-to-body junctions [32]. Current gains of the parasitic DPN or DNP bipolar transistors, in turn, are significantly less than those of conventional MOS transistors. As a matter of fact, products of the current gains of the parasitic DPN and DNP bipolar transistors are less than 1 and it should be possible to use this type of structures to eliminate the latchup in CMOS technologies.

The SCDR transistors also suffer significantly less from the high drain to substrate leakage currents and low breakdown voltages of SBDR MOS transistors. Effects of guard band structures on the high drain to substrate leakage currents and low breakdown voltages typically associated with Schottky barrier diodes of the SCDR structure are also studied. Furthermore, the minimum n+-drain-to-p+-drain spacing can be reduced from the minimum allowed by the process since the maximum current gain product of the SCDR CMOS structure with minimum n+-to-p+ spacing allowed by the process is less than the unity. This reduced n+-to-p+ spacing also reduces layout area and increases the packing density of SCDR CMOS circuits.


3.2 SCDR NMOS and PMOS Transistors

3.2.1 SCDR MOS Device Structure


A cross section of the SCDR NMOS device structure is shown in Figure 3-1. The gate length and channel width are 0.8-pgm and 12-Wm, respectively. As stated earlier, implementation of the devices requires simple layout changes









SCDR Gate Source Body



Interlevel Dielectri
Field O------d-e n +n+ eld Ox-i _ . + Field Oxide .841 .2j Gate Oxide
3.29m Spacer xide Region
Schottky Barrier Contact
p-substrate


Figure 3-1 Cross-section of an SCDR NMOS transistor. and does not require any process modifications. A major difference between SCDR and SBDR MOS transistors is that on the drain side, the source/drain implantation was partially masked to form a TiSi2-Si Schottky barrier contact and an n-type guard ring. The SCDR width is 12-jm and the length is 3.2-gm (see Figure 3-1) with a 1.2-pm wide n' guard band along the polysilicon gate and 0.8-jm wide n' guard bands along the other three edges of the Schottky clamping diode. The n' guard band along the polysilicon gate acts as a conventional drain. Along with this, utilizing a conventional source structure preserves the normal turn-on characteristics of MOS transistors as discussed in the context of the SBDR MOS transistor. In addition, the n+ guard band/ring at edges of the Schottky clamp reduces electric fields at corners which in turn reduces the reverse leakage current and raises the breakdown voltage while retaining normal Schottky barrier diode characteristics [20].









SCDR Gate Source Body



Interlevel Dielectri
Field Oxide +lC' p" + Gate Oxid n+ F iel Oxide


4Bl .2 Gate Oxide
3.21-m Spacer xide Region
Schottky B rer Contact
n-well


Figure 3-2 Cross-section of an SCDR PMOS transistor.


A cross section of an SCDR PMOS transistor is shown in Figure 3-2. The basic structure of an SCDR PMOS and NMOS transistors are the same. The channel length and width are 0.8-gm and 12-jm, respectively. Like the SCDR NMOS transistors, on the drain side, the source/drain implantation was partially masked to form a TiSi2-Si Schottky barrier contact and a p-type guard ring for SCDR PMOS transistors. The SCDR width is 12-gm and the length is 3.2-pm (see Figure 3-2) with a 1.2-gm wide p+ guard band along the polysilicon gate and 0.8-jm wide guard bands along the other three edges of the Schottky clamping diode. Once again, the guard band along the polysilicon gate acts as a conventional drain. Along with this, utilizing a conventional source structure preserves the normal turn-on characteristics of MOS transistors as mentioned earlier.








3.2.2 SCDR MOS Device Characteristics

Figure 3-3 (a) shows output I-V characteristics of 0.8-pm SCDR and conventional NMOS devices. Figure 3-3 (b) shows IDS vs. VGS curves of the same transistors. The output and turn-on characteristics of the SCDR NMOS transistors are identical to those of conventional MOS transistors. The subthreshold slope is about 100 mV/decade for both devices. Figures 3-4 (a) and (b) show output I-V and turn-on characteristics of 0.8-jm SCDR and conventional PMOS devices. Like SCDR NMOS transistors, the output and turn-on characteristics of SCDR PMOS transistors are identical to those of conventional PMOS transistors. The subthreshold slope is also about 100 mV/decade for both PMOS transistors. Figure 3-5 (a) shows current gain (0) versus I VBE I curves of NMOS-drain/p-substraten-well (DPN) and PMOS-drain/n-well/p-substrate (DNP) parasitic bipolar transistors for the SCDR and conventional CMOS structures. The drains serve as the emitters of the bipolar transistors. The bipolar structures were constructed using the minimum n+-to-n-well and p+to-p-substrate spacings allowed by the process. As expected, for I VBE I's ranging from 0 V to 1.2 V, current gains of the SCDR structure are significantly less than those of the conventional transistors. For I VBE I's ranging from 0 V to 2.0 V, PDPN and PDNP for the SCDR structure are substantially less than the unity. For VBE's of 0.4 V and 1.0 V, P3DpNS for the SCDR structure are


















0 vGS=3.ov (a)


2.0


1.0


003
1.O .0 2.0 - - 3.0 - 4.0 5.0
VDS (V)


conventional 0.8-pm NMOS transistors
* 0.8-pgm SCDR NMOS transistors

1.0


VDS--4.OV
E (b)


0.5 VDS=I .OV




oo - - - '1 V

0.01
0.010 15 2.0 VGS (Volt)

Figure 3-3 Measured (a) IDS-VDS, and (b) IDS-VGS characteristics for n-channel conventional and SCDR MOS transistors

















(a)
I,
C/)
-1.0 = -3.0V


-0.5 - VG= -2.0V

V= -1.0OV
-0.5,

-1.0 -2.0 -3.0 -4.0 -5.0
VDS (Volt)


-0.4 1 1
conventional 0.8-jim PMOS transistors
0.8-1im SCDR PMOS transistors


E VDS= -4.OV
CO
(b)
-0.2



VDS= -1 .OV VDs= -0.1V



.0 -0.5 -1.0 -1.5 -2.0
VGS (Volt)

Figure 3-4 Measured (a) IDS-VDS, and (b) IDS-VGS characteristics for p-channel conventional and SCDR MOS transistors.








102


100


10-2 10-4 10-6 10-8 10-3


1





""10-6 10-9


2


1.2
IVBEI (Volt)


0.8 1.2 1.6
IVBEI (Volt)


--PDPN of a conventional 0.8-jim NMOS
--9- PDNP of a conventional 0.8-jim PMOS
-m DPN of a 0.8-gm SCDR-NMOS
--e- PDNP of a 0.8-gim SCDR-PMOS


Figure 3-5


(a) Current gain (0) vs. I VBE I plots of drain/p-substrate/n-well (pDPN) and drain/n-well/p-substrate (IDNp) parasitic bipolar transistors for the SCDR and conventional CMOS structures; (b) Current gain product (PDPN x ODNP) vs. I VBE I plots for the SCDR and conventional CMOS structures.


(a) .0









(b)


4


0.8


-E


--.- P products of the SCDR
CMOS structure
-P-- f3 products of the P-SCDR x
conventional NMOS structure
J products of N-SCDR x
conventional PMOS structure P- products of the conventional
CMOS structure


1021 o.








2.4 x 10-6 and 1.6 x 10-2, respectively and for VBE'S of -0.4 V and -1.0 V, PDNp's for the SCDR structure are 5.9 x 10-7 and 1.1 x 10-3, respectively. Figure 3-5

(b) shows products of the current gains of the DPN and DNP parasitic bipolar transistors of the SCDR and conventional CMOS structures. For I VBE I'S ranging from 0 V to 2.0 V, unlike the conventional CMOS structure, the PDPN x PDNP products for the SCDR structure are less than 1. The I3DPN(SCDR) X IPDNP(CONV) and PDPN(CONV) x PDNP(SCDR) products are also less than the unity. The product of maximum current gains (max(OjDpN) x max(OjDgp)) for the SCDR CMOS structure is also less than 1 and a further discussion can be found in the next section. The n+-to-p+ diffusion spacing was 4.8-n which is the minimum n+-to-p+ spacing allowed by the process. These in turn should radically reduce the latchup susceptibility and should allow the spacing between n+-to-p+ diffusion to be further reduced without compromising the latchup susceptibility.


3.2.3 SCDR Junction Characteristics

The transistor characteristics of SCDR transistors are identical to those of conventional MOS transistors. However, SCDR junctions exhibit higher reverse leakage currents than conventional n+-p and p+-n drain junctions due to the edge effect and finite barrier height of the TiSi2-Si Schottky barrier contacts [201, [33-341. SCDR MOS transistors with varying guard band structures have been fabricated to examine the impact of guard bands on reverse leakage










Gate Heavily Doped Drain

SCD SCL 4Field Oxide 12 im
LDD i .
og .4 P.4 . Diffusion
GPL SCL IGOL Im l n e-O
Implant GOL


Figure 3-6 Cross section and layout of a Schottky clamped drain junction
structure with guard bands.


currents of Schottky barrier junctions. The measurement was done at room temperature.

Figure 3-6 shows a cross section and layout of a Schottky clamped drain junction with a guard band structure. The guard band length along the polysilicon edge (GPL), the Schottky clamp length (SCL) and the guard band length along the field oxide edge (GOL) are varied. The remaining two edges of the SCDR utilized the same length as GOL and the drawn width of the SCDR junction was kept at 12.0 m. Figures 3-7 and 3-8 show the measured typical data of reverse leakage currents for both drain-to-p-substrate (NMOS) and drain-to-n-well (PMOS) junctions with varying SCDR structures versus reverse junction bias voltage. At a 5-V reverse bias, the reverse leakage of a Schottky barrier drain (SBDR)-to-body junction (the structure without a guard ring) is about 4x106 - 8x106 times higher than that of conventional p-n junctions. Lengths of these junctions are at the minimum for implementing









_10-6 10-6





-10-9 10-9 < z
z

-10-12 1012




_10 5 , - _ 0 15
-5.0-4.0 -3.0-2.0-1.0 0.0 1.0 2.0 3.0 4.0 5.0
VPN (V) [PMOS] VNP (V) [NMOS]

-- Reverse Current for conventional n+/p+-drain-to-body junctions
-*- Reverse Current for Schottky barrier drain-to-body junctions
(GPL=GOL=O, SCL=2.0-jim)
Reverse current for Schottky clamped drain-to-body junctions
-A- GPL=1.2 RIm, SCL=1.6 lim, GOL=0.8 lim --GPL=1.2 gim, SCL=1.2 gim, GOL=0.8 gim 4- GPL=1.2 lim, SCL=0o.8 gim, GOL=0.8 pim

Figure 3-7 Reverse characteristics of drain-to-body, Schottky drain-to-body,
and Schottky clamped drain-to-body junctions with varying
Schottky clamp widths for NMOS and PMOS transistors.


respective MOSFET structures which are 2.0 gm for both the SBDR and conventional junctions.

Figure 3-7 shows that when the SCL is changed from 1.6 gm to 1.2 gm (with GPL= 1.2 pm and GOL= 0.8 gm), the reverse leakage current is reduced. When SCL is further reduced to 0.8 gm, the leakage current characteristics become the same as those of conventional p-n junctions. This is due to the









10-8







10-9








10-10 10-8 < 1 -9 Ir







10-10


Figure 3-8


Reverse characteristics of Schottky clamped drain-to-body junctions with varying Schottky clamp and guard band lengths at reverse bias of 5 V for (a) NMOS, and (b) PMOS transistors.


--- SCL= 1.2 p.m, GOL= 0.8 gim
--- SCL= 1.6 tm, GOL= 0.8 gm V V SCL= 1.2 gm, GOL= 0
* SCL= 1.6 gm, GOL= 0 VR= 5 V V









N MOS-drain/p-substrate


0.8 1.2 1.6 2.0 Length of Guard Band along Polysilicon-Gate (GPL) (lim)


- SCL= 1.2 im, GOL= 0.8 gm V
-- SCL= 1.6 Rim, GOL= 0.8 pgm V SCL= 1.2 gm, GOL=0 V SCL= 1.6 lim, GOL= 0 VR= 5V








PMOS-drain/n-well



0.8 1.2 1.6 2.0
Length of Guard Band along Poly-Gate (GPL) (im)








lateral diffusion of the guard band during a subsequent thermal step and the misalignment between the LDD and heavy source/drain implant patterns, which can shrink the gap between the guard bands, GPL and GOL, and consequently greatly reduce the Schottky barrier effects. These observations suggest that the Schottky barrier contact still dominates the leakage characteristics.

Measurement results in Figures 3-8 (a) and (b) show that reducing the guard band length along the polysilicon edge (GPL) from 2.0-jim to 0.8-jRm does not notably increase the leakage currents for both n-channel and p-channel MOS transistors. This suggests that it may be possible to reduce the designed 1.2-pjm GPL of the SCDR MOS transistor to 0.8-jm without increasing the leakage current of the SCDR junction. On the other hand, when the guard band length along the field oxide edge (GOL) is changed from 0.8 to 0gm, the leakage current is increased by about three times at a 5-V reverse bias, which implies that the guard bands on all edges of the SCDR's are necessary for improving the reverse characteristics. The minimum length of SCL to maintain low parasitic bipolar current gains is 1.2 Pm.

The reverse junction breakdown voltage of the SCDR-to-p-substrate junctions is about 13 V which is much higher than the 6-V reverse breakdown voltage of a Schottky barrier drain without the guard ring and is the same as the reverse breakdown voltage of conventional n+-drain-to-p-substrate junctions. For SCDR-to-n-well junctions, the reverse junction breakdown voltage is about 18 V, which is the same as that of conventional p+-drain-to-n-well








junctions, again, and is slightly higher than the 16-V reverse breakdown voltage of Schottky barrier drain-to-n-well junctions. The 16-V junction breakdown voltage for the 0.8-pum SBDR-to-n-well junction is much higher than the 6-V junction breakdown voltage for the 1.2-im SBDR-to-n-well junction presented in the previous chapter. Due to the larger junction layout area of the SCDR junctions than conventional drain junctions, the junction capacitances of the SCDR with GPL= 0.8 im, SCL= 1.2 gim, and GOL= 0.8 Im are approximately 10% higher than that of a conventional junction for SCDR-NMOS transistors and 27% higher for SCDR-PMOS transistors.


3.2.4 Determination of Barrier Height

The barrier heights of SCDR diodes were extracted by measuring Schottky barrier contact forward current-voltage characteristics. The principle underlying current transport in Schottky barrier contact is closely analogous to the thermionic emission-diffusion theory of carriers into vacuum [34]. The expression of the current-voltage relationship based on thermionic emission is


J = A**T2 exp(- )[exp( qV - 1] (3.1)



where A** is effective Richardson constant for metal-semiconductor interface (Acm-2K'2), T is temperature in Kelvin, k is Boltzmann constant, OI is the barrier height, n is the ideality factor and V is the bias voltage. For








moderately doped semiconductors, the forward bias current density with V> 3kT/q is
_**m2 (BY( qV(
J = -,-T expt, texp J(3.2)
f11xPkT A nkT)



The extrapolated value of current density at zero voltage is the saturation current, Js, and the barrier height can be obtained from the equation kTln(A**T2 33
(DB = t, (3.3)
q ( is)


Figures 3-9 (a) and (b) show the measured forward current and extrapolated value of Jsn for n-SCDR-to-p-substrate Schottky barrier contacts and Jsp for p-SCDR-to-n-well Schottky barrier contacts. To determine the barrier height, the effective Richardson constants, A**, used in (3.3) are 112 A/cm2K2 for electrons and 32 A/cm2K2 for holes in silicon [35]. The extracted JSn is 1.8 mA/cm2 and Jsp is 3.3 mA/cm2 as shown in Figures 3-9 (a) and (b). At room temperature, 298 K, the barrier heights determined by (3.3) are 0.58 eV for nSCDR-to-p-substrate Schottky barrier contacts and 0.53 eV for p-SCDR-to-nwell Schottky barrier contacts and the ideality factor is 1.05 for both type of Schottky barrier contacts. One thing need to be pointed out is that the value of barrier heights is not very sensitive to the choice of A**, a 100% increase in A** for electrons will cause an increase of only 0.0178 eV in barrier height at room temperature and similarly for holes. The barrier heights for TiSi2-to-p-Si








102

101

1

E 10-1



10-3



1o-4 10-5
0

102

101

1

N
E 10-1

LL
10-2


10-3

10-4 10-5
0

Figure 3-9


(a)






o Measured JF
- Calculated JF from (3.1)


0.05 0.10 0.15 0.20 0.25 VF (Volt)









(b)
Sp o




o Measured JF
- Calculated JF from (3.1)


0.05 0.10 0.15 0.20 0.25 VF (Volt)
Forward characteristics of Schottky clamped drain-to-body junctions diodes for the extrapolation of zero voltage saturation current, Js, to determine the barrier heights for (a) n-channel, and
(b) p-channel SCDR MOS transistors.








is 0.58 eV and for TiSi2-to-n-Si is 0.53 eV from (3.3). These results agree well with the reported data in Sze [34] and show that TiSi2 is a suitable material for both n-channel and p-channel SCDR-MOS transistors because the barrier heights are similar for both electrons and holes. Furthermore, because of this, both n-channel or p-channel SCDR MOS transistors can be formed without making any process modifications.


3.2.5 Conclusion

Both n-channel and p-channel Schottky clamped drain MOS transistors with the identical I-V characteristics to those of conventional MOS transistors have been demonstrated exhibiting greatly reducing parasitic bipolar effects and latchup susceptibilities in CMOS technologies. Using SCDR MOS transistors should allow forward-biasing of drain-to-body junctions in integrated RF switch applications with greatly reduced susceptibility to latchup of CMOS circuits integrated with the switch. Fabrication of the structures requires no additional masks or modifications of the Salicide CMOS process utilized for this work. The reverse leakage currents of the Schottky barrier drain can be greatly reduced by using guard bands.

The dimensions of GPL, SCL and GOL for SCDR's presented in this work are 1.2 pm, 1.2 pm, and 0.8 gm. It may be possible to decrease GPL to 0.8-gm to reduce the increase of the junction capacitance without increasing the leakage current of the SCDR junction.








3.3 SCDR CMOS Structure with Reduced Layout Area


Output I-V characteristics of SCDR NMOS and PMOS transistors are identical to those of conventional MOS transistors, while the current gains of parasitic n+-drain/p-substrate/n-well and p+-drain/n-well/p-substrate bipolar transistors involved in latchup are significantly reduced. This enables a reduction of minimum n+-to-p+ spacing of SCDR CMOS structures. This reduced n+-to-p+ spacing results in a layout area reduction thus increasing the packing density of SCDR CMOS circuits.


3.3.1 SCDR CMOS Structure

Figures 3-10 (a) and (b) show a cross section of an SCDR and a conventional CMOS structure, respectively. The spacings between n+-drain-to-n-well (A, see Figure 3-10 (a)) and p+-drain-to-p-substrate (B, see Figure 3-10 (a)) are primarily set by latchup susceptibility and could be reduced without compromising the latchup susceptibility by using the SCDR structure. SCDR CMOS structures with varying A and B lengths have been fabricated in the 0.8-pm CMOS process to investigate the characteristics of CMOS structures with a reduced n+-to-p+ diffusion spacing. The drain lengths, C and D, are 2.4 gm (GPL= 0.8 gm, SCL= 1.2 gm and GOL= 0.4 Am) and 2.0 gm for SCDR and conventional MOS transistors, respectively.

The output and turn-on characteristics of the SCDR NMOS and PMOS transistors with a 2.4-jim A and B are identical to those of conventional MOS








transistors as shown in section 3.2. The measurement results also show that the output and turn-on characteristics of SCDR NMOS and PMOS transistors with reduced n+-to-p+ spacings (A= B= 1.6 gm and A= B= 0.8 gim) are also almost the same as those of conventional MOS transistors.

The threshold voltage (VTH) of SCDR PMOS transistors with a reduced n+-to-p+ spacing is one of the transistors parameters which deviates from conventional and SCDR MOS transistors with a 4.8-pm n+-to-p+ spacing. NMOS VTH is about 0.70 V all the way down to A of 0.8 pm, while PMOS I VTH I


p-substrate


Figure 3-10 (a) Cross section of an SCDR CMOS structure; (b) Cross section of
a conventional CMOS structure.








decreases to -0.81 V from 0.84 V when B is decreased to 0.8 jIm. The threshold voltage shift is caused by a decrease of the drawn PMOS channel to n-well edge spacing from 4.4 pm of the conventional structure to 3.2 pm. A further discussion of this threshold voltage shift can be found in the proceeding chapters.

The BVCEO's of the parasitic DPN and DNP bipolar transistors of the SCDR structure with A= B= 0.8 jim are 32.4 V and 14.5 V, respectively. These are sufficiently high to provide good transistor isolation between n+-drain-ton-well and p+-drain-to-p-substrate even though the field oxide length is reduced.


3.3.2 Parasitic Bipolar Actions

The parasitic bipolar current gains associated with a CMOS structure increase with a reduced spacing between n+-drain-to-n-well and p+-drain-to-psubstrate. Using SCDR MOS transistors, the current gain can be maintained below those of conventional CMOS structures even though the n+-drain-to-nwell and p+-drain-to-p-substrate spacing are reduced. Figures 3-11 (a) and (b) show current gains (J) versus I VBE I curves of parasitic DPN and DNP bipolar structures for SCDR transistors with a varying n+-to-p+ spacing. The drains serve as the emitters of the bipolar transistors. Current gains of SCDR CMOS structures with a 1.6-jm n+-to-p+ spacing are higher than those of









102


1 0� (a)


10.2 [PDPN of a conventional NMOS with Co. a 4.8-jim n+-to-p+ spacing

10-4 ~ DPN of an SCDR NMOS with
a 4.8-jim n+-to-p+ spacing (A=B=2.4 gm)
** PDPN of an SCDR NMOS with 10-6 a 3.2-gm n+-to-p+ spacing (A=B=1.6 im) H- PDPN of an SCDR NMOS with VCB= 5.0V a 1.6-1im n+-to-p+ spacing (A=B=0.8 jim)
10-81
0.4 0.8 1.2 1.6 2.0 IVBEI (Volt)




100 (b)
102_



10-2 PDNpof a conventional PMOS with
C. ,a 4.8-jim n+-to-p+ spacing

10-4 - IDNp of an SCDR PMOS with
a 4.8-jim n+-to-p+ spacing (A=B=2.4jim) G- PDNP of an SCDR PMOS with 10-6 a 3.2-jim n+-to-p+ spacing (A=B=1.6jim) A--A DNP of an SCDR PMOS with a 1.6-jim n+-to-p+ spacing (A=B-0.8gim) 10-8,,,,,,,,
0.4 0.8 1.2 1.6 2.0 IVBEI (Volt)

Figure 3-11 P} versus I VBEI curves of(a) DPN, and (b) DNP parasitic bipolar
transistors for the SCDR structure with varying n+-to-p+ spacings.









DNPD of conventional CIMOST
1 DNPD of SCDR CMOST 0- DNPS of SCDR CMOST
-*SNPD of SCDR CMOST 103 SPNS of SCDR CMOST
CO 2= E
.E 102
X

0
o
(J) 101


100


10.1 0.8 1.6 2.4
Spacing between n+-to-n-well and p+-to-p-substrate (A and B) (jim)

Figure 3-12 Products of maximum current gains (max(3DpN) x max(3DNp)) for
conventional and SCDR CMOS structures versus spacing
between n+-to-n-well and p+-to-p-substrate (A and B). (D: drain,
S: source, N: n-well, P: p-substrate)



SCDR CMOS structures with a 4.8-jim n+-to-p+ spacing but they are still

lower than those of conventional CMOS structures even when the n+-drain-ton-well and p'-drain-to-p-substrate spacings are both reduced to 0.8-jm.

Figure 3-12 shows the products of maximum current gains (max(pNpN)

x max(PpNp)) against n+-drain-to-n-well and p+-drain-to-p-substrate spacings

(A and B) of the SCDR structure for all the possible PNPN thyristor combinations which could trigger latchup. With a 1.6-gm n+-to-p+ spacing








(A= B= 0.8 pm), the maximum p'-drain/n-wellp-substrate/n'-drain (DNPD) current gain product for SCDR CMOS transistors is still lower than the unity. The product of the p'-source/n-well/p-substrate/n+-source (SNPS) thyristor is higher than 1 but is still much lower than the maximum DNPD product of the conventional CMOS structure. The SNPS is structurally the same as the conventional CMOS parasitic PNPN thyristor. If necessary, the SPNS product can be reduced to lower than 1 by Schottky clamping the NMOS and PMOS sources. Schottky clamped source/drain NMOS and PMOS transistors have also been characterized to exhibit identical output I-V and turn-on characteristics to those of SCDR NMOS and PMOS transistors, respectively. Even with the 1.6-gm n+-to-p+ spacing, the ultra low current gain products for the SCDR CMOS structure should be able to greatly reduce the susceptibility to latchup.


3.3.3 SCDR CMOS Inverters with Reduced Layout Area

CMOS inverters using SCDR NMOS and PMOS transistors with varying n+-drain-to-n-well and p+-drain-to-p-substrate spacings have been implemented with PMOS and NMOS channel widths of 12-gm. Figure 3-13 shows the inverter transfer characteristics of SCDR CMOS inverters with 4.8 gn, 3.2 gm and 1.6 gim n+-to-p+ spacings. The dimensions of the SCDR junctions for the inverters are GPL= 0.8 gm, SCL= 1.2 gim and GOL= 0.4 gm. For SCDR CMOS inverters, the transfer characteristics are almost identical for all the investigated n+-to-p+ spacings. The slightly shift of the inverter switching









5.0
H-SCDR A=B=2.4 ,um SCDR A=B=1.6 gim 4-- SCDR A=B=0.8 Aim
4.0


_ 3. 0
0
I
>:2.0



1.0


00.0 1.0
1.0 3.0
2.0 3. 4.0 5.0 VIN (Volt)


Figure 3-13 Voltage transfer curves of SCDR CMOS inverters for varying n+to-n-well and p+-to-p-substrate spacings (A and B).


point for the structure withA= B= 0.8 gm is due to the slight PMOS VTH shift. Figure 3-14 compares the transfer characteristics and supply currents for both conventional and SCDR CMOS inverters. The n+-to-p+ spacing is 1.6 jim (A= B= 0.8 jm) for the SCDR inverter. The voltage transfer characteristics are almost identical. The off currents of the SCDR inverter are higher than those of the conventional CMOS inverter due to the higher junction leakage currents of SCDR junctions. The ratio of on- and off-current is about 106 for the SCDR CMOS inverter.









5.0 " M M I - Conventional CMOS Inverters 100


4.0 10-3


3.0 10-6
0
o -'
>

02.0' 1o1.0 10-12


0.010
0.0 1.0 2.0 3.0 4.0.0
VIN (Volt)


Figure 3-14 Voltage transfer curves and supply currents for SCDR and conventional CMOS inverters. (WpMos=WNMoS=12 gm)


SCDR CMOS inverters with a reduced n+-to-p+ spacing which exhibit almost the same voltage transfer characteristics to those of conventional CMOS inverters have been implemented. The layout area of the SCDR CMOS inverter with a 1.6-jm n+-to-p+ spacing has a - 17% reduction compared to the conventional CMOS inverter.

The parasitic n+-drain/p-substrate/n-well and p+-drain/n-well/p-substrate bipolar transistor actions of CMOS technologies are also radically reduced even though the spacing between n+-to-p+ is reduced to 1.6-jm from








4.8-pm. The SCDR CMOS structures with a reduced n+-to-p+ spacing also exhibit good transistor isolation.



3.4 Summary

N-channel and p-channel Schottky clamped drain MOSFET's with improved I-V characteristics from those of SBDR MOS transistors have been demonstrated while greatly reducing the parasitic bipolar effects and latchup susceptibility in CMOS structures. Fabrication of the structures requires no additional mask or modifications of the Salicide CMOS process utilized for this work.

Unlike SBDR transistors, SCDR transistors exhibit identical output and turn-on characteristics to those of conventional MOS transistors. In addition, the SCDR junction exhibits a lower leakage current and a higher breakdown voltage than the SBDR junction due to a guard band structure along the edges of the SCDR junction. The guard band structure reduces the electric fields at corners and also preserves the electrical characteristics of a normal MOS transistor. In SCDR MOS transistors, the parasitic n+-drain/p-substrate/ n-well as well as p+-drain/n-well/p-substrate bipolar transistor actions of CMOS technologies are radically reduced since Schottky barrier diodes which do not inject minority carriers clamp the n+-drain-to-p-substrate and p+-drainto-n-well junctions. Like the SBDR structure, these, in turn, reduce current gains of the parasitic bipolar transistors, and lead to significantly reduced latchup susceptibility.





49

The low current gain of SCDR CMOS structures enables a reduction of the minimum n+-to-p+ spacing of SCDR circuits. SCDR CMOS inverters with a reduced n+-to-p+ spacing exhibit almost the same voltage transfer characteristics to those of conventional CMOS inverters, while the layout area is about 17% less than the conventional CMOS inverter. These should enable area reduction of digital and analog circuits using SCDR MOS transistors.













CHAPTER 4
CMOS RADIO FREQUENCY SWITCHES


4.1 Introduction


A high quality transmit/receive switch is a key building block of the RF front end of most time-division duplexing (TDD) communication systems. In this chapter, an RF switch fabricated in a 0.5-jm CMOS process is presented. The effects of substrate resistances and source/drain-to-body capacitances associated with MOS transistors on insertion loss of RF switches have been analyzed. The substrate resistance and source/drain-to-body capacitance must be lowered to decrease insertion loss. A low insertion loss CMOS RF switch can be achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by DC biasing the source/drain nodes of the transistors which decreases the capacitances while increasing the power 1-dB compression point. A single-pole single-throw RF switch was developed. The switch exhibits 0.8 dB insertion loss, and 40 dB isolation for operating frequencies up to 1 GHz. The use of Schottky clamped MOS transistors for the RF switch can greatly reduce the susceptibility to latchup triggered by the forward biasing of the source/drain-to-body junction diodes during large voltage excursions at the input of the switch [1].








4.2 Schottky Clamped MOS Transistors

The transistor characteristics of SCDR, and Schottky clamped source and drain MOS transistors are almost the same as those of conventional MOS transistors. However, the junction capacitances of Schottky clamped junctions are higher than those of conventional source/drain-to-body junctions due to a larger layout area. The increased junction capacitance may reduce the impedance from source/drain to the substrate which in turn increases the RF signal coupling to the substrate and increase the insertion loss of RF switches.

Schottky clamped MOS transistors for RF switch applications have been implemented in a foundry 0.5-Mn CMOS process. Figure 4-1 shows a layout of the Schottky clamped MOS transistor. The transistor width is 612 Pm. The test transistor utilizes a multiple gate finger structure. The width of each gate finger is 9 gm. Both the source and drain of the transistor are Schottky clamped, which can greatly reduce the parasitic bipolar action associated with the parasitic p+-source/drain-to-n-well-to-p-substrate-n+-source/drain (PNPN) thyristor structure which can trigger latchup. The guard band lengths along the polysilicon gates of the Schottky clamped junction are 0.6 gm, and the guard band lengths are 0.3 pm on the other two edges, and the SCL is 0.9 gm for the Schottky clamped MOS transistor.


4.2.1 RF Characteristics

Figure 4-2 shows the measured insertion loss and isolation of conventional and Schottky clamped NMOS transistors. The structure was measured






















Diffusion


_.- Implant Schottky Clamp


Figure 4-1 A layout of the Schottky clamped test transistor.


on-chip using RF probes. Insertion loss was measured when the gate voltage was 5 V to turn on the transistor and source/drain voltages of the transistor were zero volt. Insertion losses of both conventional and Schottky clamped NMOS transistors are similar for frequencies up to 4 GHz. Insertion loss is about 1 dB at 1 GHz. The increased junction capacitance of the Schottky clamped junctions has almost no impact on the insertion loss of the NMOS transistor at on-state at the frequencies of interest between 1 and 2.4 GHz. Isolation was measured when the transistor was turned off (VGs= VGD = 0 V). Isolation characteristics of Schottky clamped MOS transistors are slightly
















CO,00 00
.0



4.0 Conventional NMVOST 4.
0Schottky clamped NMVOST 4.


5.0 F.
0.0 1.0 2.0 3.0.
Frequency (GHz)

Figure 4-2 Measured insertion loss and isolation for conventional and Schottky clamped NMOS transistors as switches. (W/L... 612v/.5Lm,
VE= 5.0 V, VCjjL= 0.0 V)


poorer than that of the conventional NMOS transistor for frequencies up to 4 GHz. At 1 GHz, isolation of the Schottky clamped NMOS transistor is about 1.7 dB lower than the 18.5-dB isolation of the conventional NMOS transistor. The lower isolation of Schottky clamped NMOS transistors is attributed to the increased source/drain-to-body capacitance which increased the signal coupling from input (drain node of the transistor) to output (source node of the transistor) through the substrate of the transistor.

Figure 4-3 shows the measured insertion loss and isolation of conventional and Schottky clamped PMOS transistors. The test structure was









0.0 0.0


1.0 10.0


S2.0200U 20
0
0
0
3.0 ~30.0 c
o




4.0 Conventional PMOST 4.
4 Schottky clamped PMOST 40.0 5.0 , 500
0.0 1.0 2.0 3.0 4.0 Frequency (GHz)


Figure 4-3 Measured insertion loss and isolation for conventional and Schottky clamped PMOS transistors as switches. (W/L= 6121m/0 .5gm,
VCTRL= -5.0 V, VUT 00 V)


similar to the NMOS transistor. Insertion loss was measured when the gate voltage was applied by a -5 V to turn on the transistor and source/drain voltages were 0 V. Insertion losses of both conventional and Schottky clamped PMOS transistors are similar for frequencies up to 4 GHz. Insertion loss is about 1.4 dB at the frequency of 1 GHz. Again, the increased junction capacitance of the Schottky clamped junction has almost no impact on the performance of the PMOS transistor at on-state. Isolation was measured when the transistor was turned off (VGs= VGD = 0 V). Isolation of the Schottky clamped PMOS transistor is slightly poorer than that of the conventional PMOS








transistor. At 1 GHz, isolation of the Schottky clamped PMOS transistor is about 1.3 dB lower than the 14.3-dB isolation of the conventional PMOS transistor.

Schottky clamped NMOS and PMOS transistors have been characterized. The insertion loss and isolation of Schottky clamped MOS transistors are similar to those using conventional MOS transistors especially at the frequencies of interest between 1 and 2.4 GHz. RF switches using Schottky clamped MOS transistors should have similar RF performance as those using conventional MOS transistors while having greatly reduced susceptibility to latchup than conventional MOS transistors. At 1 GHz, NMOS transistors exhibit lower insertions loss and higher isolation than those of PMOS transistors. For 900-MHz switch applications, NMOS transistors should provide a lower insertion loss per unit device area than PMOS transistors.


4.3 Design and Optimization of RF Switches

The ultimate goal of this work is implementing RF switches for L band near 1 to 2.6 GHz applications using both conventional and Schottky clamped MOS transistors. The use of Schottky clamped MOS transistors should reduce the latchup susceptibility in integrated circuits with RF switches. The design of RF switches using Schottky clamped MOS transistors is similar to those using conventional MOS transistors due to the fact that both Schottky clamped and conventional MOS transistors exhibit similar RF characteristics as described in the previous section. Key figures of merit for RF switches are








insertion loss, isolation and power handling capability. For switches implemented in bulk CMOS process, due to the conductive nature of silicon substrates, substrate losses play an important role in determining insertion loss in addition to the channel resistance of the transistor. The impact of substrate loss on insertion loss of switches will be analyzed. In addition, since no bulk CMOS single-pole double-throw (SPDT) T/R switches suitable for 900 MHz wireless applications have been reported [9-10] prior to this work, as a first step, a simple single-pole single-throw (SPST) RF switch for 900 MHz applications will be developed to understand the feasibility of using bulk CMOS technologies for RF switches.


4.3.1 Insertion Loss and Conductive Substrate

In order to quantitatively understand the impact of substrate resistances, capacitances, and on-resistances, insertion loss has been analyzed. To simplify, instead of analyzing a complete switch, the circuit containing a single MOS transistor in Figure 4-4 (a) has been analyzed. For this analysis, the transistor is assumed to be biased in linear region.

Insertion loss (IL) measures the small signal power loss through an RF switch when the switch is turned on. The expressions for insertion loss are given in (1.1) and (1.2). This quantity can be shown to be the reciprocal of the magnitude square of forward transmission coefficient (I S21 12) if both load and source impedance are matched to the characteristic impedance (Zo).









SVGS, VGD >VT


VRF


VRF


Rs RON


VRF


I
I CDB CSBCGD. CG

-- -- - -,


I
sl


'-CT
-I


CDB + SB + (CGD + CGS)CGB
CGD + CGS + CGB


Figure 4-4 (a) A MOS transistor switch in a 5042 system; (b) An equivalent
circuit diagram of the circuit shown in (a) for small signal analyses; (c) An approximate equivalent of the circuit shown in (b).








Figure 4-4 (b) shows the equivalent circuit of the MOSFET switch shown in Figure 4-4 (a) [36]. At low frequencies, on resistance of the transistor determines insertion loss. As the operating frequency is increased, due to an increase of capacitive coupling, the power loss in substrate resistances associated with the transistors is increased. The circuit in Figure 4-4 (b), though relatively simple, unfortunately cannot be easily analyzed to provide meaningful insights. Because of the fact that the impedance of the on-resistance of the transistor is usually small compared to the impedance of the parasitic capacitances of the transistor at 1 GHz, the circuit shown in Figure 4-4 (b) can be approximated as the circuit shown in Figure 4-4 (c). The plots in Figure 4-5 show simulated insertion loss of the circuits in Figures 4-4 (b) and (c) for the typical ranges of values for the on-resistance and source/drain-to-body capacitances of MOS transistors utilized in the RF switches. Both figures show no difference between the curves for the two circuits indicating that the circuit in Figure 4-4 (c) is a good approximation of the circuit in Figure 4-4 (b). For this simplified circuit, insertion loss (IL) is (see Appendix) IL= 1 _ (RoN + 2Zo)2 + 02 CT 2[(RON + 2ZO)RB + (RON + Z0)Z0]2 (4.1)
IS2112 (2Z0) 2(1 + c2CT 2RB2)


where o is the radian frequency, Z0 is the characteristic impedance, RON is the transistor on-resistance, RB is the substrate resistance associated with the transistor and CT = CDB + CSB + (CGDis the equivalent capaciCGD + CGS + CGB

tance shown in Figure 4-4 (c). For 0.5-pn transistors biased in linear region,

















Siulain of tecrutsoniniue44()







0Simulations of the circuit shown in Figure 4-4 (c).


* Simulations of the circuit shown in Figure 4-4 (b) e Simulations of the circuit shown in Figure 4-4 (c)


20.0


1.0
CDB, CSB (pF)


Figure 4-5 (a) Simulated insertion loss versus RON for the circuits shown in
Figures 4-4 (b) and (c) at 1 GHz; (b) Simulated insertion loss versus CDB and CSB for the circuits shown in Figures 4-4 (b) and (c)
at 1 GHz.


10.0
RON (P)


15.0


I I I


0.01
0.

4.0



3.0


2.0


1.0


u.o
0.0


0








CGB is negligible which yields CT = CDB + CSB. IL can also be expressed in terms of the transistor width (W).
RON 2 2 02['-RONO ]
I Rw + 2Zo) + (0 CT [(- w + 2Zo)RBo + (RONO + ZoW)Zo (41
2 2L 2= (4.2) (2Z0)2(1 + o02CTo2 RBo2)

where RBO= RBW, CTO= C09W, and RONO= RONW. For a given technology and layout type, RBO, CTO, and RONO can be assumed to be fixed. In actuality, RB does not scale linearly with the width and this will introduce some errors. It is straightforward to see that when W is large, the numerator of (4.2) becomes large and insertion loss becomes large. When W becomes small, the numerator of (4.2) also becomes large and insertion loss becomes large. This indicates that there is an optimum width for which insertion loss is minimized. For CTO= 1.4 fF/tm, RONO= 3.0 K-gm, and RBO= 8.7 K-pmn of the 0.5-jim CMOS process, insertion loss is near the minimum for widths between -0.6 to

0.9 mm. If CT is zero, IL becomes

IL = ON+ 2Z 2 when CT = 0(4.3)



which is the insertion loss at low frequencies. Comparing (4.1) and (4.3), it is easy to see the detrimental impact of CT which couples signals to the substrate.








It is also easy to show that according to (4.1), there is a value of RB for which insertion loss is the maximum. When RB is infinite, IL becomes the low frequency insertion loss given in (4.3). When RB= 0, IL is IL = (RON + 2Z0)2 + [W�CTZO(RON + z0)]2 when RB = 0 (4.4) (2Z0)2

Figure 4-6 shows IL versus RB plots for the circuits in Figures 4-4 (a) and (c). The plot for the circuit in Figure 4-4 (a) is obtained using Hspice while that for the circuit in Figure 4-4 (c) has been computed using (4.1). Once again, the


1.40 1.20


1.00 0.80


0.60 I-


0.40'


100.0


200.0


300.0


400.0


500.0


RB ()
Figure 4-6 A simulated insertion loss versus RB plot for the circuits shown in
Figure 4-4 (a), and an insertion loss computed with (4.1) versus
RB plot for the circuit shown in Figure 4-4 (c) at 1 GHz. The bias
condition was VGB= 6.0 V and VDB= VSB= 3.0 V.


I I * I
Simulations of the circuit shown in Figure 4-4 (a)
* Numerical evaluation of equation (4.1)
for the circuit shown in Figure 4-4 (c)


I I I


0L








plots are very close. As discussed, there is a maximum point. By maximizing (4.1), it can be shown that the maximum insertion loss occurs at RB(MAX) =

2 2 2 144 2 2 2 2 2
-02 CT . (RONZO + Z02) + .IC4CT4- (RONZO + Z0 ) + 40) CT2. (RON + 2Z0)
2 2
20) CT2. (RON + 2Zo)

(4.5)


To achieve low insertion loss in RF switches fabricated with CMOS technologies, special attention must be paid to avoid transistor substrate resistances near RB(MAX). For typical CMOS RF switches operating at 1 GHz, CT is on the order of a couple pico-Farad and RON is on the order of a few Ohms. Under these conditions, (4.5) can be simplified to RB(MAX) - 1/o(C In hind sight, this is an obvious result. The power loss associated with the RB-CT series network is maximized when RB= 1/o)Cp When this occurs, insertion loss is maximized. For the 0.5-jm transistors utilized in 1-GHz RF switches, as mentioned, CT is generally - 0.8 to 2.0 pF and the corresponding RB(MAX) is - 80 to 200 il Unfortunately, this is in the typical range of RB's for transistors in RF switches if nothing has been done to control the substrate resistance.

These results have shown that insertion loss can be reduced by increasing RB to a very large value or by decreasing RB to near zero. Insertion loss for the case when RB= 0 is larger than the case for infinite RB because of the coCTZO(RON+ZO) term in the numerator of (4.1). Once again, CT must be reduced in order to decrease insertion loss. As discussed earlier, if CT= 0,








insertion loss will become the low frequency loss in (4.3). In terms of the underlying physical mechanism, when RB becomes large, signals cannot couple to RB and the power consumption associated with RB is small. This is the advantage of using semi-insulating substrates over conductive substrates to implement RF switches. When RB is zero, there is no loss associated with RB, and the power loss is once again reduced.



4.3.2 MOSFET-based RF Switch Design

Figure 4-7 is a schematic of an SPST NMOS RF switch. Transistors Ms performs the main switching function, while the shunt transistor Mp is used


I VCTRL

R G


RFIN
and Drain DC Bias


RFOUT
and Source DC Bias


Input Source DC Bias


RGP UR


CB


RGs=RGp=l Ok


Figure 4-7 Circuit schematic of an SPST RF switch.








to improve the isolation of the switch by grounding the RF signal when the switch is off. Static power consumption of the switch can be kept near zero by applying the same DC voltage on the top plate of the bypass capacitor CB as the DC voltage for RF1N node. On-resistance of MS is one of the dominant factors determining the insertion loss. Because of this, only n-channel MOSFET's are used in the design due to the fact that n-channel MOSFET's provide lower insertion loss per unit device area than p-channel MOSFET's at 900 MHz. The drain-to-body and source-to-body junction capacitances of Ms, the drain-tobody junction capacitance of MB and associated parasitic resistances due to the conductive nature of silicon substrates are also critical factors determining the insertion loss.

The gate bias resistances, RGS and RGI are implemented using poly resistors. A typical value for the gate bias resistance is about 10 k. The purpose of RGs and RGp is to improve DC bias isolation [21, [61, [37]. If the gate bias resistance is missing, the VGD and VGS of the transistor can fluctuate due to the high voltage swing at drain and source of the transistor. For MOS RF switches, these fluctuating voltages across the gate dielectric not only affect the MOSFET channel resistance but also may result in excessive voltage drop across the gate dielectric and cause dielectric breakdown.

Figure 4-8 shows the simulation results of insertion loss versus the width of Ms in the SPST switch. For the given bias condition, VGB= 6.0 V, VDB, SB= 3.0 V of MS, as the transistor width is increased, on-resistance decreases and insertion loss decreases. However, if the transistor width is









0.0



0.4 High RON Loss Through
Capacitive Coupling

~0
-j 0.8
0
._E
0

1.2
Frequency=960 MHz



.2 0.4 0.6 0.8 1.0 Width of Transistor Ms (mm)

Figure 4-8 The effects of the transistor width on insertion loss of an SPST
switch. WMS= 2 x Wmp. Bias Condition: VGB= 6.0 V, VDBSB= 3.0 V. increased excessively, the signal loss through capacitive coupling to the substrate becomes significant and insertion loss increases with the increasing width. According to the simulation, for the chosen bias conditions, MS should be 600-jim wide to minimize insertion loss.

Substrate resistance is another critical factor determining insertion loss. Figure 4-9 (a) is a schematic of the SPST switch including important substrate resistances. Figure 4-9 (b) shows the simulated insertion loss of the switch versus parasitic substrate resistances associated with the drain-tobody and source-to-body junction capacitances of MS and Mp at 960 MHz. As shown in the analysis, the simulation also suggests two approaches to











RFIN
and Drain DC Bias


cH


-7-


RB,MS


Input Source DC Bias .%


100.0 200.0 300.0
Substrate Resistance of Ms (S


RFOUT and Source DC Bias





(a)

















(b)










400.0 500.0


Figure 4-9


(a) Circuit schematic of an SPST RF switch including key substrate resistances; (b) The effects of the transistor substrate resistances (resistances from S/D to ground) on insertion loss of an SPST RF switch at 960 MHz. (RB,MP= 2 x RB,MS, RB: substrate resistance).


1.40.
0.0








improve insertion loss. One is to increase the substrate resistances by a large amount to lower the signal coupling into the substrate. However, the practicality of this approach is limited in bulk CMOS integrated circuits on conductive substrates. Another is to radically reduce the substrate resistances to make the substrate almost loss-less. This is more practical in bulk CMOS technologies.


4.3.3 DC Bias Condition of SPST RF Switches

Bias condition is also crucial for RF switches. Insertion loss and the PldB can be largely improved by applying an appropriate DC bias. RFIN node and the sources of Ms and Mp are DC biased to 3 V instead of 0 V. This voltage reverse biases the source/drain-to-body junctions, which decreases the capacitance and RF signal coupled to the substrate and thus insertion loss is improved.

Another purpose of the 3-V DC bias for RFIN and RFouT nodes is to improve the power handling capability measured by PldB. If the DC voltage for RFIN, RFouT and Vc--L is zero, then an RF input voltage with an amplitude of - 0.5 V forward biases the sourcedrain-to-body junctions in some portion of a cycle. This clips the RF signal and causes the output power to compress. When MS is on, with the 3-V DC bias, PldB is limited by unintentional turning on of MI This is because of the RF signal coupling due to the voltage divider form by gate-to-drain, gate-to-source and gate-to-body








capacitances of MP (CGD,MB CGS,MP and CGB,MP). Assuming the total drain voltage of Mp is Vd = VD + vD where VD is the DC drain voltage of Mp and vD is the RF voltage at the drain node of MB the voltage appeared at the gate node of transistor MB Vg, is

V GV'CGD, MP (4.6) Vg = VG + VD� CGD, MP + CGS, MP + CGB, MP



The DC gate voltage for MS is set to 6 V, and that for Mp is set to 2 V to turn on the switch. For the 0.5-jim NMOS transistor under this bias condition, the ratio of CGD, MP is about one-third. If an RF voltage
(CGD, MP + CGS, MP + CGB, MP)

with an amplitude of around 2.7 V is applied, then the minimum voltage at the drain node of MS will be Vd,min= 3.0 - 2.7= 0.3 V, and the source/drain-tobody junctions are reverse biased. The minimum gate voltage of Mp from (4.6) is Vgmin= 2.0 - 2.7 x 1/3 = 1.1 V which is -0.9 V lower than the DC bias voltage due to the RF voltage capacitively fed forward from RFIN [2]. The maximum gate-to-drain voltage (Vgd) of Mp is Vg - Vd= 1.1 V - 0.3 V= 0.8 V, which is higher than the threshold voltage (VTH) of the 0.5-11m transistor, and the transistor, Mm starts to turn on. This unintentionally turned-on transistor clips the output waveform and once again makes the output power of the switch to compress. However, the RF power level before the clipping occurred for the 3V source/drain-to-body bias case is significantly higher than that for the 0-V DC bias case.








4.3.4 Experimental Results of 900 MHz SPST Switches

An SPST RF switch has been implemented in a 0.5-jim CMOS process. The width of Ms and Mp are 612 gm and 306 gm, respectively, to minimize the insertion loss. The substrate resistance of Ms is about 14 Q and the substrate resistance is about 20 Q for MI They are sufficiently low to significantly reduce the substrate losses. The low substrate resistances are achieved by fully surrounding the transistors with large area p+ substrate contacts and filling in any open spaces with substrate contacts.

Figure 4-10 shows the measured and simulated insertion loss and isolation for the SPST RF switch. Measured insertion loss is 0.8 dB, and isolation is 40 dB for operating frequencies up to 1 GHz at a VCTRL or a VGB of 6.0 V, and a drain/source-to-body reverse bias (VDB and VSB) of 3.0 V. The measured insertion loss agrees well with the simulation, while the measured isolation is a few dB lower than that of simulation. Over 40-dB isolation of the switch for frequencies up to 1 GHz is excellent.

The insertion loss of the SPST switch is about 0.2 dB lower than that of the single NMOS switch described in the previous section and isolation is greatly improved by about 22 dB. The lower insertion loss is achieved by optimizing the transistor widths and bias, and by minimizing the substrate resistances, while the higher isolation is achieved by grounding the RF signal through Mp when the switch is off. Lastly, The 6.0-V VCTRL can be obtained by using a voltage doubler.









0.0 1 1 10.0
* Measurement
Simulation
1.0 10.0

S2.0 20.00
0
~2.0
0
3.0 30.0 0 U) O
C

4.0 40.0
0 Q

5.0 150.0
0.0 0.4 0.8 1.2 1.6 2.0 2.40.0 Frequency (GHz)


Figure 4-10 Measured and simulated insertion loss and isolation for the SPST
switch. (VCTRL= 6.0 V, VDB,SB= 3.0 V)




4.4 Summary


Schottky clamped (SC) MOS transistors for RF switch applications have been implemented in a foundry 0.5-jm CMOS process. The transistor width is 612 pm. Both source and drain of the transistor are Schottky clamped. The measured insertion loss and isolation of the structure using a Schottky clamped MOS transistor are similar to those using a conventional MOS transistor especially at the frequencies of interest between 1 and 2.4 GHz. RF switches using Schottky clamped MOS transistors should have








similar performance to those using conventional MOS transistors, while having greatly reduced susceptibility to latchup.

The impact of conductive silicon substrate on insertion loss has been analyzed. The analysis showed that substrate resistances and junction capacitances associated with transistors need to be reduced to improve insertion loss. A single-pole single-throw (SPST) RF switch has also been presented. The switch was fabricated in a foundry 0.5-jm CMOS process. It exhibits a 0.8-dB insertion loss and a 40-dB isolation. The switch has adequate insertion loss and isolation for a number of 900-MHz applications. This work suggests that a single-pole double-throw (SPDT) RF T/R switch could be implemented in bulk CMOS technologies and also be integrated with the other CMOS transceiver circuits.













CHAPTER 5
SCHOTTKY DIODE CLAMPED MERGED DRAIN CMOS STRUCTURE


5.1 Introduction

During this work on developing approaches to reduce latchup susceptibility using Schottky clamped MOS transistors, a TiSi2-Si Schottky diode clamped merged drain (SCMD) CMOS concept has been discovered. In this chapter, this new CMOS structure is demonstrated by fabricating it in a foundry 0.8-prm Salicide CMOS process. Output I-V characteristics of SCMD MOS transistors are almost identical to those of conventional MOS transistors and isolation of the transistors are preserved, while the current gains of parasitic n+-drain/p-substraten-well and p+-drain/n-wellp-substrate bipolar transistors involved in latchup are significantly reduced. This enables a reduction of the n+-to-p+ spacing. This reduction in combination with the decreased drain lengths of transistors in the SCMD CMOS structure results in a - 30% area reduction for an inverter.








5.2 SCMD CMOS Transistors


5.2.1 SCMD CMOS Device Structure


Figures 5-1 (a) and (b) show a cross section of an SCMD and a conventional CMOS structures. Similar to SCDR CMOS transistors, implementation of the SCMD CMOS structure requires simple layout changes and does not require any process modifications. Layouts of SCMD and conventional CMOS


Gate Source n


SCMD Gate
n Source


p-substrate


Figure 5-1 (a) Cross section of an SCMD CMOS structure; (b) Cross section
of a conventional CMOS structure.








structures are shown in Figures 5-2 (a) and (b), respectively. The gate length and channel width are 0.8-jm and 12-jim, respectively. A major difference between SCMD and SCDR MOS transistors is that on the drain side, the field oxide region between n' and p+ drains is removed. The source/drain implantation was partially masked to form a TiSi2-Si Schottky barrier contact, and an n-type and a p-type guard band along the ploysilicon gates. The n' and p+ guard bands along the polysilicon gates act as conventional drains for n-channel and p-channel devices, respectively. In the 0.8-jim CMOS process, the SCMD structure has a smaller drain length of 0.8 jm versus 2.0 Pin, and has an n+-to-p+-drain spacing of 3.2 pim versus 4.8 jm of the conventional CMOS structure. These result in a - 30% area reduction for a CMOS inverter.

The area reduction of an SCMD CMOS structure is accomplished by exploiting the following: (1) TiSi2 forms Schottky barrier junctions to both moderately doped n and p-type silicon regions (doping concentration less than

- 5x1018 cm"3) [341 and TiSi2 forms good ohmic contacts to n+ and p+ regions;

(2) current gains of NMOS-drain/p-substrate/n-well (DPN) and PMOS-drain/ n-well/p-substrate (DNP) parasitic bipolar transistors for Schottky clamped NMOS and PMOS [17] transistors are radically reduced, which allows the spacing between n' and p+ drains to be reduced to 3.2 from 4.8 Pm without compromising the latchup immunity; (3) the lengths of n' and p+ drains can be reduced to 0.8 from 2.0 jim, since using a TiSi2 layer to connect the n' and
















Diffusion


Schottky Diode Clamped Merged Drain (SCMD) n-well


Diffus


p+ Implant K+ Implant


(a)


Diffusion p4 Implant -, n+ Implat


-4en Implant


Figure 5-2 (a) Layout of an SCMD CMOS structure; (b) Layout of a conventional CMOS structure.


Ion


p+ Implant


n-well Diffusion


twn Implant p+ Implant


I








p+ drains eliminates the need for one of the two drain contacts in Figure 5-1

(b) and the remaining contact can be placed anywhere on the TiSi2 layer; (4) because the TiSi2 layer connecting the n' and p+ drains forms reverse biased Schottky barrier junctions to both n-well and p-substrate, the TiSi2 layer is electrically isolated from n-well and p-substrate, and this enables the removal of the field oxide region between the n' and p+ drains in the conventional CMOS structure; (5) the BVCEO's of DPN and DNP bipolar transistors are 19.3 and 13.5 V, respectively and these are sufficiently high to provide good isolation between n+-drain and n-well, and between p+-drain and p-substrate even though the field oxide and field implanted regions are removed; and (5) the on-characteristics of the PMOS in SCMD CMOS structures are only slightly altered. Lastly, the silicide does not have to be TiSi2. Other silicides such as CoSi2 which form Schottky barrier junctions to n- and p-type silicon with comparable barrier heights as TiSi2 [34] should also be applicable.



5.2.2 Parasitic Bipolar Actions

Figure 5-3 shows current gain products for DPN and DNP parasitic bipolar structures of the SCMD and conventional CMOS transistors. The drains serve as the emitters of the bipolar transistors. Current gains of the bipolar structures in the SCMD CMOS structure are significantly reduced. As a matter of fact, for I VBE I's between 0 and 2.0 V, products of the current gains for the SCMD inverter are less than the unity. The parasitic DPN and DNP










1O2

1 DPNX PJDNP 1


10-2



0
.910.4--o PDPN x PDNP of conventional CMOS
transistors with a 4.8-gm n+-to-p+ spacing 10-6 IDPN XJ DNP Of SCMD CMOS transistors with a 3.2-gm n+-to-p+ spacing 10"9 1
0.4 0.8 1.2 1.6 2.0 IVBEI (Volt)


Figure 5-3 Current gain products (PDPN x PDNP) vs. I VBE I plots for NMOSdrain/p-substrate/n-well (DPN) and PMOS-drain/n-well/p-substrate (DNP) parasitic bipolar transistors in SCMD and conventional CMOS transistors.

bipolar actions in the CMOS structure are greatly reduced since Schottky barrier junctions, which do not inject minority carriers, clamp the n+-drain-to-psubstrate and p+-drain-to-n-well junctions [32]. These, in turn, reduce current gains of the parasitic DPN and DNP transistors, and lead to significantly


reduced latchup susceptibility.








5.2.3 Schottky Clamp Length

SCMD CMOS transistors have comparable I-V characteristics to those of conventional MOS transistors. In order to maximize area reduction while maintaining low parasitic bipolar current gains and good transistor isolation, the length of Schottky clamps (SCL, see Figure 5-4) should be optimized. The Schottky clamp length (SCL) should be as short as possible to achieve the maximum area reduction. However, it can not be too short. If the SCL is too short, the Schottky clamping effects may be lost and the isolation between p+drain-to-p-substrate and/or n+-drain-to-n-well may be degraded below the acceptable limit.

As mentioned, the minimum SCL is primarily set by two factors, the transistor isolation and the parasitic bipolar current gain. The minimum acceptable SCL is determined experimentally. The shortest SCL in the experiment is 0.8 jim which is limited by the lateral diffusion of n-well and drain


TiSi2viN
GND VIN VOUT I


VDD


NMO� Drain PMOS Drain

Figure 5-4 Cross section of an SCMD CMOS inverter with the definition of
Schottky clamp length (SCL).








implants. The the longest SCL is 2.4 jlm which corresponds to the drain-to-nwell spacing for the conventional CMOS structure.

Figure 5-5 shows the products of maximum current gains (max(p3NpN) x max(PpNp)) versus SCL of SCMD for all the possible PNPN thyristor combinations which could trigger latchup. As SCL decreases, the products of maximum P's increase. However, they are still much lower than those of the conventional CMOS structure except for the product of the p+-source/n-well/psubstrate/n+-source (SNPS) thyristor. The SNPS is structurally the same as



- DNPD of conventional OMOST 104 ' e DNPD of SCMD CMOST u-u SNPD of SCMD CMOST 1-3 DNPS of SCMD CMOST 1 SNPS of SCMD MOST Y,
E
= 102



0
o101

2
a- 100


10-1
0.8 1.2 1.6 2.0 2.4 Schottky Clamp Length of SCMD (tRm)


Figure 5-5 Products of maximum current gains (max(pNpN) x max(PpNp)) for
conventional and SCMD CMOS structures versus Schottky clamp
length (SCL). (D: drain, S: source, N. n-well, P: p-substrate)








the conventional CMOS parasitic PNPN thyristor. To ensure that this product is less than those of the conventional CMOS structure, SCL must be at least 1.6 pm compared to 2.4 pm in the conventional CMOS structure. This restriction, however, can be easily lifted by Schottky clamping the NMOS and PMOS sources. As mentioned in the previous chapters, MOS transistors use a Schottky clamped source exhibit identical output I-V and turn-on characteristics as those of SCDR MOS transistors.

In Figure 5-6, BVcEo's of the parasitic DNP bipolar transistors of the SCMD inverter remain constant for SCL's ranging between 0.8 and 2.4 m.


0.01, I 1
0.8 1.2 1.6 2.0
Schottky Clamp Length of SCMD (jim)


Figure 5-6 BVCEO of parasitic DPN (n+-drain/p-substrate/n-well) and DNP
(p+-drain/n-wellp-substrate) bipolar transistors of SCMD CMOS
transistors.








For the DPN transistors, BVCEO decreases sharply when SCL is reduced below 1.2 gm. These BVCEO characteristics set the minimum SCL between n' and n-well to 1.2 jim and that between p+ and p-substrate to 0.8 jim.

Figures 5-7 (a) and (b) show IDS-VDS characteristics of SCMD (SCL= 1.6 gm) and conventional NMOS and PMOS transistors. Output characteristics of conventional and SCMD NMOS transistors are identical. Compare to the conventional PMOS transistor, the SCMD PMOS transistor has slightly higher drain current than that for the conventional PMOS due to a 0.1-V increase of the threshold voltage caused by a decrease of the drawn PMOS channel to n-well edge spacing from 4.4 gm of the conventional structure to

2.4 pm.

The threshold voltage of SCMD MOS transistors is one of the transistors parameters which deviate from those of conventional MOS transistors. Figure 5-8 shows plots of I VTH I versus SCL for the NMOS and PMOS transistors. NMOS I VTHI is almost constant all the way down to SCL of 0.8 jm, while PMOS I VTH I decreases to - 0.66 V from 0.84 V when SCL is decreased to 0.8 jm. The higher threshold voltage of SCMD PMOS transistors could be an advantage for some applications where higher drive currrent is desired.

Figure 5-9 shows the SCMD PMOS transistor off-state source current. The off-current increases when SCL is reduced below 1.6 jm. Although - 3 PA/ . at an SCL of 0.8-jm is acceptable, for the off-state current to be independent of SCL, SCL should be greater than or equal to 1.6 jm. The off-state


















E 3.0- VGS=3.OV (a


2.0


1.0- VGs=I"0V


0.0
0.0 1.0 2.0 3.0 4.0 5.0 VDS (Volt)


I- Conventional 0.8-1im PMOS Transistors -25 SCMD PMOS Transistors (SCL=1.6jim)



-2.0 VGS='5"0V


E -1.5 (b)





-0.5
0-.01/ ._i




0.0 -1.0 -2.0 -3.0 -4.0 -5.0
VDS (Volt)

Figure 5-7 (a) Measured IDS-VDS characteristics for SCMD and conventional
NMOS transistors; (b) Measured IDS-VDS characteristics for
SCMD and conventional PMOS transistors.









0.90' _ ' ' 0 HHp-channel SCMD Transistors 0.85 n-channel SCMD Transistors
0.85
Conventional PMOS IVTHI=0.84V
0.80

0
>0.75I
0.70

0.5 Conventional NMOS VTH=0.68V

0.60


0.8 1.2 1.6 2.0 2.4 Schottky Clamp Length of SCMD (im) Figure 5-8 Threshold voltage versus Schottky clamp length of SCMD NMOS
and PMOS transistors.


source current of PMOS transistors is - 0.1 PA/at VDS= -5 V when SCL is greater than or equal to 1.6 pm.

Figure 5-10 shows the leakage currents of junctions in SCMD and conventional CMOS transistors. The leakage currents at room temperature for junctions in SCMD transistors are - 1 nA/Km at a 5 volt reverse bias. This - 1 nA/,m leakage currrent of the SCMD junction is about 10 times higher than that of the SCDR junction. Note that the guard band structure on the field oxide edges is not utilized in the SCMD structure as shown in Figure 5-2 and this may result in a higher leakage current of the SCMD junction. For












-Mean
* Maximum
* Minimum
VDS= -5.0 V VGS= 0.0 V


E 4
C


0
4
0



0
0
(/L
0D



0D O, 0L


I I


1.2 1.6 2.0 Schottky Clamp Length of SCMD (gim)


2.4


Figure 5-9 Off-state source current versus Schottky clamp length for SCMD
PMOS transistors.


temperatures above 300 �K, the leakage current of the Schottky clamped junctions doubles approximately every 10 OK increase in temperature [23], [38-39]. Though the off-current of SCMD inverters is higher, the room temperature leakage is almost low enough to satisfy the off-state leakage current specification of CMOS technologies.

The junction capacitance including the Schottky, p+-n and n+-p junctions of the SCMD structure should be - 10% higher than the conventional junctions. This corresponds to a - 3% increase in the load capacitance for each


-- - - - -----


10-1


1O-2L
0.8


1004



























Conventional
DIP


Conventional
DIN


Figure 5-10 Leakage currents of junctions in SCMD (SCL= 2.0 gim) and conventional CMOS transistors. (D: drain, N: n-well, P: p-substrate) stage in an inverter chain with a fan-out of one. This should have only a small impact on the speed performance.


5.3 SCMD CMOS Inverters


5.3.1 SCMD CMOS Inverter Characteristics


To demonstrate the applicability of the SCMD CMOS structures, SCMD CMOS inverters and a 100-stage inverter chain have been implemented. A cross section of an SCMD CMOS inverter was shown in Figure 5-4.


Mean
-__- * Maximum � Minimum VReverse= 5.0 V


10-3 10-6


SCMD
DIP


SCMD
DIN


I I


I I








Figure 5-11 shows the voltage transfer characteristics (VTC) and supply currents of conventional and SCMD CMOS (SCL= 1.6 Wim) inverters with PMOS Width= NMOS Width= 12 pim. The VTC curves are almost identical. The slight shift is due to the difference in the PMOS threshold voltage. However, the supply currents of the SCMD inverter at output voltages of 0 and 5 V are higher than those of conventional CMOS inverters. The higher supply currents of the SCMD inverter at output voltages of 0 and 5 V are mainly due to the junction leakage current of the Schottky clamped junctions as shown in Figure 5-10.



Conventional CMOS Inverter
5.0 H SCMD CMOS Inverter 10� (SCL= 1.60m)
4.0- 103


>v6 " 3.0 - . _106 o. .



0 2.0i .10"9


0.0 1.0 2.0 3.0 4.0 5.0 VIN (Volt)

Figure 5-11 Voltage transfer curves and supply currents for SCMD and conventional CMOS inverters. (WpMos=WNMoS=12 gm)

















0

02.0



1.0


0.0
0.0 1.0 2.0 3.0 4.0 5.0 VIN (Volt)


Figure 5-12 Voltage transfer curves of SCMD inverters for varying Schottky
clamp lengths.



Figure 5-12 shows VTC curves for varying SCL. Due to the PMOS VTH shift, when SCL is decreased to 1.2 gtm, the inverter switching point is increased by - 80 mV. Based on these discussions and those from the previous section, SCL between the n' and n-well and that between the p+ and p-substrate can be reduced to 1.6 im without affecting the circuit and latchup characteristics and also transistor isolations.








5.3.2 SCMD CMOS Inverter Chains


100-stage SCMD (SCL= 2.0 gm) and conventional CMOS inverter chains with NMOS Width= 1.6 gm and PMOS Width= 3.2 gm have been implemented. The n-channel transistor width of the inverters is the minimum allowed by the process. The guard band lengths along the polysilicon gate (GPL) are 1.2 pum for the SCMD NMOS transistor and 0.8 pm for the SCMD PMOS transistor. Figure 5-13 (a) shows the schematic and a micro-photograph of the inverter chain and delay extraction circuit. The chain for the SCMD and conventional CMOS inverters are enlarged and shown in Figure 5-13 (b) for a clear area comparison. By utilizing the SCMD structure, the inverter chain area (SCL= 2.0 Pim or n'-drain-to-p+-drain spacing of 4.0 gm) has been reduced by - 22%. Figure 5-14 (a) shows output waveforms of the inverter chains. Figure 5-14 (b) shows plots of the inverter propagation delay (ID) versus supply voltage. The plots for both types of inverters are almost identical. As discussed, the junction capacitance including the Schottky, p+-n and n+-p junctions of the SCMD structure should be - 10% higher than those for the conventional junctions. This corresponds to a - 3% increase in the load capacitance for each stage in an inverter chain with a fan-out of one. As seen in Figure 5-14 (a), this has only small impact on the speed performance.

100-stage SCMD and conventional CMOS inverter chains have been implemented. By utilizing the SCMD structure, the inverter chain area






























O- 100-Stage Inverter Chain


<-4.
22% Area Reduction -


SCMD Inverter Chain Conventional Inverter Chain

(b)

Figure 5-13 (a) Circuit schematic and die photo for the SCMD CMOS inverter
chain and propagation delay extraction circuit; (b) Enlarged photos of the SCMD and conventional CMOS inverter chains for clear
area comparison.

















0
o2 I




0.(


-2.



400.


350.0 300.0 250.0


200.0 150.0


...T 100 rD
LI


] D = Propagation Delay





-80.0 -40.0 0.0 40.0 80.0 Time (ns)


- Conventional CMOS Inverter Chain
--- -o SCMD CMOS Inverter Chain


100.01 1 , I I


2.0


3.0


4.0
VDD (Volt)


Figure 5-14 (a) Measured output waveforms of the SCMD and conventional
CMOS circuits shown in Figure 5-13; (b) Inverter delays versus
supply voltage for SCMD and conventional CMOS inverters.


0








(SCL= 2.0 jm or n+-drain-to-p+-drain spacing of 4.0 jm) has been reduced by

- 22% without any process modifications. The 2.0-jim SCL, 1.2-gm NMOS GPL and 0.8-gm PMOS GPL are a conservative design for SCMD CMOS inverters. Based on the study of SCL, SCL between the n' and n-well and that between the p+ and p-substrate can be reduced to 1.6 gm without affecting the circuit and latchup characteristics and also transistor isolations. And based on the study of GPL in chapter 3, NMOS GPL can be reduced to 0.8 jm without affecting the transistor and latchup characteristics, and also junction leakage currents. Layout area of the SCMD inverter chain can be further reduced by using the 1.6-jim SCL, 0.8-jm NMOS GPL and 0.8-jm PMOS GPL instead of the 2.0-jm SCL, 1.2-jim NMOS GPL and 0.8-jim PMOS GPL.



5.4 Summary

A Schottky diode clamped merged drain (SCMD) CMOS structure and a 100-stage SCMD CMOS inverter chain have been implemented in a foundry 0.8-jm Salicide CMOS process. Output I-V characteristics of SCMD NMOS and PMOS transistors are almost identical to those of conventional MOS transistors and transistor isolation characteristics are preserved. The current gains of parasitic n+-drain/p-substrate/n-well and p+-drain/n-well/p-substrate bipolar transistors of the CMOS structure involved in latchup are significantly reduced. The reduced current gains enable a reduction of the n+-drainto-p+-drain spacing which reduces the area of the SCMD CMOS structure.




Full Text

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SCHOTTKY CLAMPED MOS TRANSISTORS FOR WIRELESS CMOS RADIO FREQUENCY SWITCH APPLICATIONS BY FENGJUNG HUANG A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA

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ACKNOWLEDGMENTS I wish to express my deepest gratitude to my advisor and supervisory committee chair, Dr. Kenneth K. O, whose constant support and patient guidance provided a clear path for my research. Through my time on this research I have learned a tremendous amount and am grateful for his encouragement and advice. I would also like to thank Dr. Sheng S. Li, Dr. Mark E. Law, and Dr. Randy Y. Chow for helpful discussions and suggestions. I have been quite fortunate to have worked with my colleagues: ChihMing Hung, Yochuol Ho at Texas Instrument, Brian A. Floyd, Namk}^! Park and Meng-Hsueh Chiang at the University of Florida; Kihong Kim, Jesal Mehta and Carlos Gamero at RF Micro Devices, Hyun Yoon at Motorola, Saket Bhatia at Valence Semiconductor, and all the members of SiMICS (Silicon Microwave Integrated Circuits and Systems) research group, especially Seong-Mo Yim, Dung-Jun Yang and Tod Dickson. I thank all of them for encouragements and being good friends. My special thanks go to Courtney Hazelton at Texas Instrument for bonding the 0.5-|iim switches, and A1 Ogden and Steve Schein for the equipment support and instruction on packaging. I highly appreciate the support from National Science Foundation and a Texas Instrument graduate fellowship. 11

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I am most pleased to acknowledge the support, encouragement and helpful discussions on statistical matters regarding measurements from Dr. Chen-Pin Wang at the University of South Florida. Without her, this research work would not have been possible. I would also like to thank my fnends, my parents and my family, especially my father, sisters. Melody and Vivian, MelodyÂ’s husband, Scott, and my nephews, Sean and Dean, for the support and joy they brought me throughout my graduate study at the University of Florida.

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TABLE OF CONTENTS page ACKNOWLEDGMENTS ABSTRACT CHAPTERS 1 INTRODUCTION 1.1 Transceiver: An Overview 1.1.1 Receiver 3 1.1.2 Transmitter 1.2 Figures of Merit of RF Switches 5 1.3 Concerns for CMOS RF Switches 7 1.4 Summary 2 SCHOTTKY BARRIER DRAIN MOS TRANSISTORS 14 2.1 Introduction 2.2 SBDR MOS Transistors 15 2.2.1 SBDR MOS Device Structure 16 2.2.2 SBDR MOS Device Characteristics 17 2.2.3 Parasitic Bipolar Actions 20 2.3 Summary 21 3 SCHOTTKY CLAMPED DRAIN MOS TRANSISTORS 23 3.1 Introduction 23 3.2 SCDR NMOS and PMOS Transistors 24 3.2.1 SCDR MOS Device Structure 24 3.2.2 SCDR MOS Device Characteristics 27 3.2.3 SCDR Junction Characteristics 31 3.2.4 Determination of Barrier Height 36 3.2.5 Conclusion 39 3.3 SCDR CMOS Structure with Reduced Layout Area 40 3.3.1 SCDR CMOS Structure 40 3.3.2 Parasitic Bipolar Actions 42 IV

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3.3.3 SCDR CMOS Inverters with Reduced Layout Area 45 3.4 Summary 48 4 CMOS RADIO FREQUENCY SWITCHES 50 4.1 Introduction 50 4.2 Schottky Clamped MOS Transistors 51 4.2.1 RF Characteristics 51 4.3 Design and Optimization of RF Switches 55 4.3.1 Insertion Loss and Conductive Substrate 56 4.3.2 MOSFET-based RF Switch Design 63 4.3.3 DC Bias Condition of SPST RF Switches 67 4.3.4 Experimental Results of 900 MHz SPST Switches 69 4.4 Summary 70 5 SCHOTTKY DIODE CLAMPED MERGED DRAIN CMOS STRUCTURE 72 5.1 Introduction 72 5.2 SCMD CMOS Transistors 73 5.2.1 SCMD CMOS Device Structure 73 5.2.2 Parasitic Bipolar Actions 76 5.2.3 Schottky Clamp Length 78 5.3 SCMD CMOS Inverters 85 5.3.1 SCMD CMOS Inverter Characteristics 85 5.3.2 SCMD CMOS Inverter Chains 88 5.4 Summary 91 6 SINGLE-POLE DOUBLE-THROW CMOS RF SWITCHES 93 6.1 Introduction 93 6.2 900-MHz 0.5-|xm SPDT Switches 94 6.2.1 Design of 0.5-pm SPDT RF Switches 94 6.2.2 DC Bias for RF Switches 100 6.2.3 Measured Results of Conventional MOSFET Switches 101 6.2.4 Measured Results of SC MOSFET Switches 105 6.2.5 Reliability Issues of 0.5-|xm MOSFET Switches 106 6.2.6 Conclusion 112 6.3 900-MHz and 2.4-GHz 0.35-pm SPDT Switches 113

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6.3.1 Design of 0.35-|im SPDTRF Switches 6.3.2 Measured Results of 900-MHz Switches 6.3.3 Measured Results of 2.4-GHz Switches 6.3.4 Reliability Issues of0.35-^miMOSFET Switches .. 6.4 Impedance Transformation for High Power RF Switches 6.4.1 Design of Impedance Transformation Networks ... 6.4.2 Experimental Results and Discussion 6.5 Summary 114 118 121 123 125 125 131 142 7 SUMMARY AND FUTURE WORK 7.1 Summary 7.2 Future Work APPENDIX S 21 OF A SHUNT Y-SERIES Z NETWORK REFERENCES BIOGRAPHICAL SKETCH 144 144 146 149 153 158 VI

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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy SCHOTTKY CLAMPED MOS TRANSISTORS FOR WIRELESS CMOS RADIO FREQUENCY SWITCH APPLICATIONS By FengJung Huang May 2001 Chairman: Kenneth K. O Major Department: Electrical and Computer Engineering The feasibility of implementing integrated radio-frequency (RF) complementary metal-oxide-semiconductor (CMOS) switches is demonstrated. The most challenging part of developing CMOS RF switches is the impact of the semiconductive nature of silicon substrates. This degrades insertion loss, limits the power handling capability of switches and may also trigger latchup in CMOS circuits due to a forward biased junction in an integrated switch when the output is mismatched. Schottky clamped metal-oxide-semiconductor (MOS) transistors for high power RF circuit applications have been implemented in foundry CMOS processes with no process modifications. The use of Schottky clamped MOS transistors in RF switches reduces the minority carrier injection into the body vii

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of the transistors when the source/drain-to-body junctions are forward biased, and this reduces susceptibility to latchup for the surrounding CMOS circuits. To achieve insertion loss of less than 1 dB in CMOS switches, substrate resistances associated with the transistors are minimized and junction capacitances of the transistors are reduced in order to decrease signal coupling to the substrate and thus reduce substrate loss. Through layout optimization, substrate resistances of less than 20 Q in a 0.5-pm CMOS process using p substrates, and substrate resistances of less than 10 Q in a 0.18-pm CMOS process using p' substrates have been achieved. These substrate resistances are low enough to make the substrate effect on insertion loss small. In addition, bias voltages have been optimized to ensure that the transistors operate within a safe voltage region while the voltage swing required to turn on source/drain-to-body junctions is increased, and thus the power handling capability of the switch is maximized. CMOS RF switches are demonstrated in 0.5-|im and 0.18-pm CMOS processes using 3.3-V MOS transistors. At 900 MHz, the measured insertion loss is as low as 0.5 dB which is competitive to commercially available GaAs switches. At 2.4 GHz, insertion loss is 0.8 dB which is also comparable to that of GaAs switches. The power handling capability of CMOS RF switches has been increased to 24 dBm by using impedance transformation networks. viii

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These are the first CMOS switches to have sufficient performance for ISM band applications near 900 and 2400 MHz. This dissertation work has demonstrated that it is feasible to use bulk silicon CMOS technologies to implement RF switches, which will reduce the cost of RF switches and thus reduce the cost of radios.

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CHAPTER 1 INTRODUCTION The rapidly increasing demand for digital cellular phones, digital cordless phones and wireless local area network (WLAN) applications have bloomed the market for radio-frequency integrated circuits (RFICÂ’s) [1]. These circuits need to be low cost, to have low operating voltage and low power consumption, and to be small in size with increased functionality. Several semiconductor technologies, gallium arsenide (GaAs), silicon germanium (SiGe), silicon bipolar and silicon complementary metal-oxide-semiconductor (CMOS), are being used to implement radio-frequency (RF) circuits. The GaAs technology has been one of the major technologies for RF applications, especially for high power components such as power amplifiers (PA) and transmit/ receive (T/R) switches, due to a higher breakdown voltage, higher electron mobility, and the advantages associated with the semi-insulating nature of GaAs substrates [1-2]. The recent speed improvement of digital CMOS transistors has made it feasible to implement wireless radio-frequency transceivers and their subcomponents in silicon CMOS technologies [3-5]. As the feature size of CMOS technologies is scaled down to the deep sub-micrometer regime, the frequency at which CMOS transistors can operate while delivering acceptable performance 1

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2 should increase. This has increased the possibilities for CMOS RF circuits meeting the stringent requirements of communication systems. A higher level of integration can be achieved with CMOS technologies compared to GaAs technologies. These, along with the potential for lower cost, have made RF CMOS technologies and circuits topics for intense research. The goals of this dissertation work are to study the feasibility of implementing a critical circuit block used in the RF transceiver front end called the radio-frequency transmit/receive switch, and to study the limitations on the performance of RF switches imposed by the CMOS technology. A high quality microwave switch is a key building block of the RF front end for time-division duplexing (TDD) systems. In recent years, GaAs field-effect-transistor (FET)based switches have been the dominant technology for the RF T/R switch due to their low direct current (DC) power consumption compared to traditional microwave p-i-n diode switches. For RF T/R switch applications, switches built in semiconductor integrated circuit (IC) technologies with insulating substrates (such as GaAs and CMOS/silicon-on-sapphire (SOS)) have significant advantages compared to those fabricated in a bulk CMOS technology [1]. A typical GaAs FET-based switch achieves a 25-dBm PidB with 0.8 dB insertion loss and 24 dB isolation at 2.4 GHz [6]. A CMOS/SOS switch demonstrates an input-referred third-order intercept point of 18 dBm, with a 1.7-dB insertion loss and greater than 30-dB isolation at 2.4 GHz [7]. Another CMOS/SOS switch with a 1.0-dB insertion loss and 29-dB isolation at 2.0 GHz [8] has been demonstrated. The power handling capability is not reported. Insertion loss

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3 and power handling capability of these CMOS/SOS switches are not very good. More importantly, the cost for CMOS/SOS integrated circuits is considerably higher than that of bulk CMOS integrated circuits. Despite the fact that a MOS transistor is a natural switch, no MOSFET single-pole double-throw (SPDT) T/R switches suitable for wireless applications at 900 MHz and higher have been reported prior to this dissertation work [9-10]. In this dissertation, RF switches built in bulk CMOS technologies intended for operation in the L band near 1 to 2.6 GHz are developed. Unlike the other previously reported high power GaAs T/R switches [2], [6], the RF switches are implemented in low cost digital CMOS processes and do not require any process modifications and negative control voltages [6] . 1.1 Transceiver: An Overview In this section, operation of the building blocks of an RF front end, which includes a receiver, a transmitter, a frequency synthesizer, a power amplifier and a T/R switch, is discussed. A simplified block diagram of a cellular radio is shown in Figure 1-1 [11]. This radio includes RF front end, intermediate-frequency (IF) modulation/demodulation and baseband signal processing circuits. 1.1.1 Receiver In the receive mode, the T/R switch connects the antenna to the receive path. The RF signal is received by the antenna and passed through the T/R

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4 switch. The T/R switch should have low insertion loss to reduce its impact on noise performance of the receiver. Also, the T/R switch should have good isolation to block the transmit band signal from being fed into the input of the receiver. The received signal is amplified by a low noise amplifier (LNA) followed by an image rejection filter. To avoid overloading the LNA by out of band signals appearing at its input, a bandpass filter (BPF) precedes the LNA. This filter can also be used to reject images. The image rejection is needed to keep the unwanted frequency components from being fed into the input of the RF mixer in order to reduce the unwanted signal at the mixer output. The RF mixer down converts RF signal to intermediate frequency (IF) using the frequency synthesizer output. IF signal is then demodulated by the I/Q demodulator. The output signal of the ADC is used by a digital signal processor to reconstruct the message. The requirement of a global system for mobile (GSM) receiver is that a 102 dBm signal at the input of the receiver must be detected with a bit error Figure 1-1 Simplified block diagram of a cellular radio.

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5 probability (BER) of less than 10'^. The system must also be able to reject a 0dBm out-of-band single-tone blocking signal, a -23-dBm in-band single-tone blocking signal and a -43-dBm in-band two-tone blocking signal. 1.1.2 Transmitter In the transmit mode, the input message is first processed by the digital signal processor to generate in-phase and quadrature-phase data streams. The data streams are then modulated with IF LOs followed by an IF filter. The IF signal is mixed using an RF LO. Finally, the RF signal is filtered and amplified by a power amplifier, and is fed to the antenna through the T/R switch. The T/R switch should provide a low loss path for the transmit signal to the antenna and should also provide a high power handling capability. The peak transmit power requirement of a T/R switch is 30 dBm for GSM, 20 dBm for CT3, 10 dBm for CT2 [12] and between 10 to 30 dBm for north American industrial, scientific, and medical (ISM) band applications [13]. 1.2 Figures of Merit of RF Switches Key figures of merit of an RF switch are insertion loss (IL), isolation and power handling capability. The insertion loss measures the power loss through the RF switch when the switch is turned on. The power loss ratio, Plr, is [14] _ Power Available from Source _ ^AVS _ 1 (1.1) ~ Power Delivered to Load ^Load I-IFlI^

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6 This quantity can be shown to be the reciprocal of | S 21 1 ^ if both load and source are matched to the characteristic impedance. The insertion loss in dB is IL = 10 . logPLR The insertion loss of an RF switch is particularly important for the transmitter, because it determines how much of the power delivered by the PA is lost before it reaches the antenna. The insertion loss also can have a profound effect on the receiver. The insertion loss of a switch is the noise figure of the switch. The insertion loss of the RF switch if poor can limit the noise figure of the entire receiver. Thus, it should be sufficiently low, typically less than IdB. The off-state of an RF switch is characterized by its isolation. The definition of isolation is the same as insertion loss. However, isolation measures the power leakage through the RF switch when the switch is turned off. Isolation of an RF switch should be as high as possible to isolate the transmitter and receiver. The power handling capability of an RF switch is characterized by its power 1-dB compression point (PidB^This parameter is determined by the non-linearities of a switch. Another parameter characterizing the non-linearity of a switch is the third-order intercept point (IP 3 ). The PidB ^ switch is defined as the output power level at which the operating power gain (Gp) of the switch deviates from the small signal power gain by 1 dB. High PidB of a

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7 switch denotes a high power handling capability of the switch. IP 3 of a switch is defined as the point where the extrapolated output power curve of the desired signal and power curve of a third order intermodulation component intersect [15]. The input referred IP 3 of the device is denoted as the IIP3. In general, the output of an RF switch, when the non-linearity effects are included, has a voltage transfer function that can be written as a Taylor series: Vout = ao + ajvjn + a2Vi^^ + agVj^^ + . . . where Vj^ and Vgut denote input and output voltage of the switch, respectively and ag, aj, a 2 , ... are constants. If the input to the system consists of two relatively closely spaced tones at coj and CD 2 , the Vj^^ term will generate the thirdorder products at ( 2 coi-a) 2 ) and ( 2 c 02 -C 0 i) which cannot be filtered, even in a narrow-band system [14]. High IP 3 means the amplitudes of these third order products are low. 1.3 Concerns for CMOS RF Switches The power handling capability is a crucial parameter of CMOS RF switches. It is extremely difficult to transmit power in excess of 30 dBm through a switch operating from a low voltage supply (3 V or less). The two problems are maintaining linearity in the on-state and maintaining isolation in the off-state. Junction isolated silicon technologies in particular have great

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8 difficulty in meeting these performance requirements due to the possibility of forward biasing the source/drain-to-body junction diodes during large power excursions at the input and output of the switch [1] . The 30-dBm corresponds to a ~ 20-V peak-to-peak voltage swing at the output of an RF switch with a 50-Q load. In CMOS RF switch applications, this 20-V peak-to-peak voltage could easily forward bias the source/drain-to-body junctions of MOS transistors. Simulations for a MOSFET switch with a 50-Q load in Figure 1-2 illustrate this problem. The available power from the source is 10 dBm in the simulation. The NMOS source/drain-to-body junctions are forward biased when the signal appeared at source and drain swings below the voltage at body (Vg) of the MOS transistor. These forward biased junctions not only limit the power handling capability of the switch but also may inject minority carriers into the body of nearby transistors and trigger latchup. This problem can be alleviated by applying DC bias to increase the reverse bias of the source/ drain-to-body junctions. This increases the RF voltage amplitude required to forward bias the junction and thus improving the power handling capability [16]. However, even after applying the DC bias, the maximum RF voltage amplitude still can be limited by the requirement of reverse som*ce/drain-tobody junction bias. Especially, the large RF signal in combination with the output mismatch can still forward bias the junction and trigger latchup as shown in Figure 1-3. Normally, a transmit/receive (T/R) switch is connected to an antenna, which has a nominal input impedance of 50 Q However, this impedance

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9 Figure 1-2 Simulations for a MOSFET switch with in a 50-Q system. changes with surrounding structures. Because of this, the switch is required to withstand the voltage or survive the stress even when the output load is mismatched (< 10:1 voltage standing-wave ratio (VSWR)). For instance, when the output load is 500 Q, VSWR is 10:1. Figure 1-3 shows the output voltage waveform when the loading condition is 50 and/or 500 with 3.0-V reverse

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10 Figure 1-3 Simplified circuit schematic of an NMOS switch with 500-Q load and simulated waveforms at corresponding nodes for the circuit. biased source/drain-to-body junctions. The available power from the source (Pays) about 20 dBm. Under the 50 Q load condition, source/drain-to-body junctions are never forward biased. However, for the same input voltage, when the load is 500 Q, the NMOS source/drain-to-body junctions are forward

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11 biased (when the source and drain voltage swings below the voltage at body (Vb) of the MOS transistor). Incidentally, a similar situation exists for RF power amplifiers. These are serious issues for integrating CMOS RF switches with other circuits. This latchup issue caused by integrated RF switches built in bulk CMOS technologies must be solved before the switch can be integrated with the rest of the transceiver circuits. 1 .4 Summary MOS transistors using Schottky barrier contacts as drains have been developed to reduce the parasitic bipolar actions and the susceptibility to latchup in CMOS technologies. The proceeding chapters will describe the development of MOS transistors using Schottky barrier contacts to reduce latchup susceptibilities for CMOS RF switch applications, and also design and operation of RF switches and their components. Chapter 2 describes an initial design of integrated Schottky barrier drain MOS transistors with radically reduced susceptibility to latchup and the concerns for the structure. Chapter 3 presents an improved structure, a Schottky clamped drain MOS transistor which exhibits identical output I-V and turn-on characteristics to those of a conventional MOS transistor, while exhibiting radically reduced parasitic bipolar effects. Design for Schottky clamped drain CMOS structures for CMOS RF switch applications is also discussed.

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12 Chapter 4 describes the frequency response of Schottky clamped MOS transistors compared to conventional MOS transistors and design of CMOS RF switches. The effects of substrate resistances and source/drain-to-body capacitances associated with MOS transistors on insertion loss of RF switches have been analyzed showing that substrate resistances and source/drain-tobody capacitances need to be reduced to decrease insertion loss. Single-pole single-throw RF switches were implemented in a 0.5-|im CMOS process. Measurements have been done to understand the feasibility of using conventional CMOS processes to implement single-pole double-throw CMOS RF switches. Chapter 5 describes a brand new device concept, Schottky diode clamped merged drain MOS transistors for digital CMOS circuit applications. Using Schottky diode clamped merged drain transistors, a 100-stage inverter chain has been implemented. The inverter chain exhibits similar performance to those of conventional CMOS inverter chains while layout area is ~ 22% smaller. This reduced area should decrease the cost of CMOS integrated circuits. Chapter 6 presents design, implementation and demonstration of 900MHz and 2.4-GHz single-pole double-throw RF switches, and discusses the reliability issues of RF switches. The 900-MHz switches were implemented in a 0.5-pm CMOS process and also using 0.35-pm 3.3-V MOS transistors in a 0.18-pm CMOS process. The 2.4-GHz switch was implemented using 0.35-pm 3.3-V MOS transistors in the 0.18-pm CMOS process. Impedance transformation networks are used to reduce the RF voltage amplitude at the input and

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13 output of RF switches to increase the power handling capability of CMOS RF switches. The use of impedance transformation has increased the power 1-dB compression point from 17 dBm to 24 dBm. Lastly, chapter 7 summarizes this dissertation work and suggests possible future research work.

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CHAPTER 2 SCHOTTKY BARRIER DRAIN MOS TRANSISTORS 2.1 Introduction In bulk CMOS integrated circuit applications, especially for high power applications such as RF T/R switches, it is sometimes unavoidable to have a large voltage signal swing below ground or above supply voltage in some portions of a cycle and thus forward biasing the source/drain to body junctions of MOSFETÂ’s as discussed in the previous chapter. This forward biased junction not only limits the power handling capability of the switch but also may trigger latchup. This latchup issue needs to be solved before the switch can be integrated with the rest of the CMOS transceiver circuits. A MOS transistor using Schottky barrier contacts as source and drain reduces the susceptibility to latchup in CMOS [17-18]. In this work, the feasibility of integrating Schottky barrier contacts in a foundry 0.8-|im CMOS process without making any process modifications is investigated. An insulated-gate field-effect transistor (IGFET) using Schottky barrier contacts for source and drain was first proposed in 1968 [19]. The device characteristics are comparable to those of conventional IGFETÂ’s at room temperature. The forward and reverse characteristics of silicon Schottky barrier diodes have also been studied extensively [20-24]. Silicon Schottky barrier 14

PAGE 24

15 diodes with near ideal I-V characteristics can be obtained by using a diffused guard ring [20], a double diffused guard ring [21], and moat-etched techniques [22]. Schottky barrier diodes have also been widely used for microwave networks because of their excellent high frequency behavior [25] . Due to the fact that the minority carrier injection from metal-semiconductor contacts of Schottky barrier diodes is negligible in most cases [26], Schottky barrier diodes have been used as source and drain for MOS transistors to reduce the latchup susceptibility associated with CMOS technologies [17-18]. Unfortunately, the works reported by Swirhun et al. [17] and Sugino et al. [18] required modifications of the process or suffered from device characteristic degradations which truly limit their applicability. In this chapter, an experimental MOS transistor, the Schottky barrier drain (SBDR) MOS transistor [27], which radically reduces latchup susceptibility is presented. The structure is implemented in a foundry 0.8-fxm Salicide CMOS process. Implementation of the devices does not require any process modifications. The foundry Salicide CMOS process used is similar to those in Peng et al. [28] and Chapman et al. [29]. Measured transistor characteristics and current gains of parasitic bipolar transistors of a 1.2-|xm SBDR PMOS transistor are discussed. 2.2 SBDR MOS Transistors In this section, a Schottky barrier drain (SBDR) p-channel MOSFET fabricated in a conventional 0.8-|im foundry CMOS process without making

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16 any process modifications is described. A potentially useful feature of such a device is that the parasitic p'‘‘-drain/n-well/p-substrate bipolar transistor actions of CMOS technologies are not present since Schottky barriers do not inject minority carriers. Due to the fact that there is no minority carrier (hole) injection from the Schottky-barrier-drain-to-n-well, current gains of the parasitic drain/n-well/p-substrate transistor structure are negligible. This t}^e of structure could be useful for reducing the latchup susceptibility in integrated RF switch applications where source/drain-to-body junctions could be forward biased due to the high input RF power level. 2.2.1 SBDR MOS Device Structure A cross section of the SBDR PMOS device structure is shown in Figure 2-1. The gate length and channel width are 1.2 |xm and 12.0 |im, respectively. SBDR Gate Source Body Figure 2-1 Cross-section of an SBDR PMOS transistor.

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17 A major difference between the SBDR and conventional transistors is that the SBDR device is as 5 nnmetric. On the drain side, the lightly doped drain (LDD) and source/drain implantations were masked to form a TiSi 2 -Si Schottky barrier contact. The Schottky barrier contact replaced the p‘‘’-to-/i-well junction. At the source side, a conventional source structure was utilized to maintain the turn-on characteristics of the MOS transistor. 2.2.2 SBDR MOS Device Characteristics Figure 2-2 shows the output I-V characteristics of 1.2-|im SBDR and conventional PMOS transistors. The threshold voltage of the device in the reverse mode of operation (using the Schottky barrier contact for source instead of drain) is very high because the LDD region is not present on the drain side. In the forward operation (using SBDR), this absence of the LDD region also prevents current conduction until Vj^s is lowered below -0.3 V, or Vds is decreased sufficiently for the depletion layer associated with the Schottky-barrier-drain to merge with that of the MOS structure which allows draining of holes from the channel. This phenomenon obviously is not observed in the conventional MOSFET device. The SBDR structure has a higher drain to source saturation voltage ( | V^s.SAT I )• At Vqs= -2 V, the conventional device will saturate when Vj)s reaches -0.8 V. However, the SBDR transistor will not saturate until Vj)s= -2 V at Vq.s= -2 V. In addition, the source current at Vjjs = Vgs= -5 V is 1.3 mA which is 300 |iA lower than that of the conventional

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18 Figure 2-2 Measured IdS'^DS characteristics for conventional and SBDR PMOS transistors. device. This is due to a higher series resistance in the SBDR transistor than in the conventional MOSFET. This is a concern for RF power MOS applications, and needs further improvements. Another concern is the reverse leakage current of the SBDR junction. The leakage cmrent was about 13 pA at a 5-V reverse bias and the junction breakdown voltage was about 6 V, and once again, further improvements are needed. Despite these, the overall characteristics of the SBDR-MOS transistors are promising. Figure 2-3 shows the drain current dependence on Vqs of 1.2-pm conventional and SBDR MOS transistors. When Vds= -0-1 V, the SBDR MOS

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19 -0.5 -1.0 -1.5 -2.0 Vqs (Volt) Figure 2-3 Measured IdsÂ’Vqs characteristics for conventional and SBDR PMOS transistors. transistors will not turn on because the absence of the LDD region on the drain side prevents current conduction. When Vds= -IV, tum-on characteristics of the conventional and SBDR MOS transistors start to look similar and when Vds= -5 V, tum-on characteristics of the conventional and SBDR MOS transistors are very similar. Once again, when V^s is decreased sufficiently for the depletion layer associated with the SBDR to come in good contact with that of the MOS structure, turn-on characteristics of the conventional and SBDR MOS transistors become similar.

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20 2.2.3 Parasitic Bipolar Actions Figure 2-4 shows Gummel plots of drain/n-well/p‘‘'-source parasitic structures for the conventional and SBDR MOS transistors. The drains serve as the emitters of the bipolar transistors. As expected, the collector current associated with the minority carrier injection is very small for the SBDR MOS transistor. Only a small amount of collector-base (p'*'-source-to-n-well) junction reverse leakage current was present. This in turn should eliminate the parasitic drain/n-well/p-substrate bipolar action. Figure 2-4 Gummel plots of drain/n-well/p "'-source parasitic pnp bipolar transistors for conventional and SBDR PMOS transistors.

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21 2.3 Summary A p-channel MOSFET using a Schottky barrier contact for the drain has been demonstrated using a 0.8-)im foundry CMOS process. Fabrication of the structure requires no additional mask or process step in the Salicide CMOS process. Measurements showed that SBDR MOS transistors suffer from high drain to substrate leakage current and low breakdown voltages [30] as well as reduced drain currents. The reverse junction leakage current of SBDR junctions was about 13 pA at a 5-V reverse bias and the SBDR junction breakdown voltage was about 6 V. Using this structure, it is possible to eliminate the parasitic bipolar effect due to the p'^-drain/w-well/p-substrate structure. This should allow unintentional forward biasing of the drain-to-n-well junction in power RF applications with significantly reduced latchup susceptibility. Despite the fact that the Schottky barrier drain was separated from the channel by a spacer oxide region, p-channel Schottky barrier drain MOS transistor characteristics were surprisingly good. However, /i-channel Schottky barrier drain MOS transistors failed due to the absence of the LDD region. Lastly, the "soft" reverse characteristics of SBDR junctions need improvements. The work reported by Li et al. [31] has shown that the effective barrier height of Ti-silicon Schottky barrier diode can be increased to as high as 0.96 eV by using low energy ion implantations. The enhancement of effective

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22 barrier heights of Schottky barrier diodes should reduce the reverse leakage current of SBDR junctions and increase the junction breakdown voltage.

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CHAPTERS SCHOTTKY CLAMPED DRAIN MOS TRANSISTORS 3.1 Introduction MOS transistors using a Schottky barrier contact as a drain have been demonstrated by implementing the transistor in a conventional Salicide CMOS process. The SBDR structure has shown the feasibility of implementing MOS transistors using a Schottky barrier contact as a drain to reduce the latchup susceptibility. However, the high junction leakage current, low breakdown voltage and reduced drain current of SBDR MOS transistors are serious problems. In this chapter, a transistor structure called Schottky clamped drain (SCDR) MOS transistors [32] is presented. This structure radically reduces the latchup susceptibility while achieving the same drive current as conventional MOS transistors. Implementation of SCDR MOS transistors is similar to SBDR MOS transistors, and requires only simple layout changes but does not require any process modifications. The structure is demonstrated in a 0.8|im foundry Salicide CMOS process. The parasitic NMOS-drain/p-substrate/n-well (DPN) and PMOS-drain/ n-well/p-substrate (DNP) bipolar transistor actions of CMOS technologies are greatly reduced by using the SCDR structure since Schottky barrier diodes 23

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24 which do not inject minority carriers clamp the drain-to-body junctions [32]. Current gains of the parasitic DPN or DNP bipolar transistors, in turn, are significantly less than those of conventional MOS transistors. As a matter of fact, products of the current gains of the parasitic DPN and DNP bipolar transistors are less than 1 and it should be possible to use this type of structures to eliminate the latchup in CMOS technologies. The SCDR transistors also suffer significantly less from the high drain to substrate leakage currents and low breakdown voltages of SBDR MOS transistors. Effects of guard band structures on the high drain to substrate leakage currents and low breakdown voltages typically associated with Schottky barrier diodes of the SCDR structure are also studied. Furthermore, the minimum n^-drain-to-p^-drain spacing can be reduced from the minimum allowed by the process since the maximum current gain product of the SCDR CMOS structure with minimum n'^-to-p'*' spacing allowed by the process is less than the unity. This reduced n'*'-to-p''Â’ spacing also reduces layout area and increases the packing density of SCDR CMOS circuits. 3.2 SCDR NMOS and PMOS Transistors 3.2.1 SCDR MOS Device Structure A cross section of the SCDR NMOS device structure is shown in Figure 3-1. The gate length and channel width are 0.8-pm and 12-|im, respectively. As stated earlier, implementation of the devices requires simple layout changes

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25 SCDR Gate Source Body p-substrate Figure 3-1 Cross-section of an SCDR NMOS transistor. and does not require any process modifications. A major difference between SCDR and SBDR MOS transistors is that on the drain side, the source/drain implantation was partially masked to form a TiSi 2 -Si Schottky barrier contact and an n-type guard ring. The SCDR width is 12-pm and the length is 3.2-pm (see Figure 3-1) with a 1.2-pm wide n"*" guard band along the polysilicon gate and 0.8-pm wide n* guard bands along the other three edges of the Schottky clamping diode. The n'*' guard band along the polysilicon gate acts as a conventional drain. Along with this, utilizing a conventional source structure preserves the normal turn-on characteristics of MOS transistors as discussed in the context of the SBDR MOS transistor. In addition, the guard band/ring at edges of the Schottky clamp reduces electric fields at corners which in turn reduces the reverse leakage current and raises the breakdown voltage while retaining normal Schottky barrier diode characteristics [20].

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26 SCDR Gate Source Body Figure 3-2 Cross-section of an SCDR PMOS transistor. A cross section of an SCDR PMOS transistor is shown in Figure 3-2. The basic structure of an SCDR PMOS and NMOS transistors are the same. The channel length and width are 0.8-}xm and 12-|xm, respectively. Like the SCDR NMOS transistors, on the drain side, the source/drain implantation was partially masked to form a TiSi 2 -Si Schottky barrier contact and a p-type guard ring for SCDR PMOS transistors. The SCDR width is 12-pm and the length is 3.2-)im (see Figure 3-2) with a 1.2-|im wide guard band along the polysilicon gate and 0.8-|im wide guard bands along the other three edges of the Schottky clamping diode. Once again, the guard band along the polysilicon gate acts as a conventional drain. Along with this, utilizing a conventional source structure preserves the normal turn-on characteristics of MOS transistors as mentioned earlier.

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27 3.2.2 SCDR MOS Device Characteristics Figure 3-3 (a) shows output I-V characteristics of 0.8-|xm SCDR and conventional NMOS devices. Figure 3-3 (b) shows vs. Vqs curves of the same transistors. The output and tum-on characteristics of the SCDR NMOS transistors are identical to those of conventional MOS transistors. The subthreshold slope is about 100 “'^/decade both devices. Figures 3-4 (a) and (b) show output I-V and tum-on characteristics of 0.8-pm SCDR and conventional PMOS devices. Like SCDR NMOS transistors, the output and turn-on characteristics of SCDR PMOS transistors are identical to those of conventional PMOS transistors. The subthreshold slope is also about 100 “^/decade both PMOS transistors. Figure 3-5 (a) shows cmrent gain (P) versus | Vbe | curves of NMOS-drain/p-substrate/n-well (DPN) and PMOS-drain/n-well/p-substrate (DNP) parasitic bipolar transistors for the SCDR and conventional CMOS structures. The drains serve as the emitters of the bipolar transistors. The bipolar structures were constructed using the minimum n'*'-to-n-well and p'*'to-p-substrate spacings allowed by the process. As expected, for | VgE I ’s ranging from 0 V to 1.2 V, current gains of the SCDR structure are significantly less than those of the conventional transistors. For | V^e | ’s ranging from 0 V to 2.0 V, and PpivP the SCDR structure are substantially less than the unity. For Vg^’s of 0.4 V and 1.0 V, Pppjv’s for the SCDR structure are

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(VLu) sa, (Vi^) 28 Vgs (Volt) Figure 3-3 Measured (a) Ids*V^DS> (b) Ids'V^GS characteristics for 7i-channel conventional and SCDR MOS transistors

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iDs(mA) 29 Vgs (Volt) Figure 3-4 Measured (a) Ids'V^DS? (^) ^DSÂ’^GS characteristics for p-channel conventional and SCDR MOS transistors.

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pnpojd 30 IVbeI (Volt) Figure 3-5 (a) Current gain (P) vs. | I plots of drain/p-substrate//z-well (Pz>P!At) drain/n-well/p-substrate (Ppjvp) parasitic bipolar transistors for the SCDR and conventional CMOS structures; (b) Current gain product (pppjv x Ppivp) vs. | Vgg | plots for the SCDR and conventional CMOS structures.

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31 2.4 X 10'® and 1.6 x 10"^, respectively and for Vbe’s of -0.4 V and -1.0 V, ^dnp^ for the SCDR structure are 5.9 x lO'"^ and 1.1 x lO'^, respectively. Figure 3-5 (b) shows products of the current gains of the DPN and DNP parasitic bipolar transistors of the SCDR and conventional CMOS structures. For | Vbe I ’s ranging from 0 V to 2.0 V, unlike the conventional CMOS structure, the ^dpn X products for the SCDR structure are less than 1. The PdpmscdR) ^ pDiyP(CONV) and ^DPNiCONV) ^ ^DNPiSCDR) products are also less than the unity. The product of maximum current gains (max(P 2 >piy) x maxi^D^p)) for the SCDR CMOS structure is also less than 1 and a further discussion can be found in the next section. The n'^-to-p'^ diffusion spacing was 4.8-pm which is the minimum rP-to-p^ spacing allowed by the process. These in turn should radically reduce the latchup susceptibility and should allow the spacing between n'^-to-p'^ diffusion to be further reduced without compromising the latchup susceptibility. 3.2.3 SCDR Junction Characteristics The transistor characteristics of SCDR transistors are identical to those of conventional MOS transistors. However, SCDR junctions exhibit higher reverse leakage currents than conventional ri^-p and p^-n drain junctions due to the edge effect and finite barrier height of the TiSi 2 -Si Schottky barrier contacts [20], [33-34]. SCDR MOS transistors with varying guard band structures have been fabricated to examine the impact of guard bands on reverse leakage

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32 Figure 3-6 Cross section and layout of a Schottky clamped drain junction structure with guard bands. currents of Schottky barrier junctions. The measurement was done at room temperature. Figure 3-6 shows a cross section and layout of a Schottky clamped drain junction with a guard band structure. The guard band length along the polysilicon edge (GPL), the Schottky clamp length (SCL) and the guard band length along the field oxide edge (GOL) are varied. The remaining two edges of the SCDR utilized the same length as (X)L and the drawn width of the SCDR junction was kept at 12.0 pm. Figures 3-7 and 3-8 show the measured typical data of reverse leakage currents for both drain-to-p-substrate (NMOS) and drain-to-n-well (PMOS) junctions with varying SCDR structures versus reverse junction bias voltage. At a 5-V reverse bias, the reverse leakage of a Schottky barrier drain (SBDR)-to-body junction (the structure without a guard ring) is about 4x10® ~ 8x10® times higher than that of conventional p-n junctions. Lengths of these junctions are at the minimum for implementing

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33 -•-Reverse Current for conventional rrVp^-drain-to-body junctions -Reverse Current for Schottky barrier drain-to-body junctions (GPL=GOL=0, SCL=2.0-pm) Reverse current for Schottky clamped drain-to-body junctions -AGPL=1 .2 |im, SCL=1 .6 pm, GOL=0.8 pm --GPL=1.2 pm, SCL=1.2 pm, GOL=0.8 pm -+GPL=1 .2 pm, SCL=0.8 pm, GOL=0.8 pm Figure 3-7 Reverse characteristics of drain-to-body, Schottky drain-to-body, and Schottky clamped drain-to-body junctions with varying Schottky clamp widths for NMOS and PMOS transistors. respective MOSFET structures which are 2.0 pm for both the SBDR and conventional junctions. Figure 3-7 shows that when the SCL is changed from 1.6 pm to 1.2 pm (with GPL= 1.2 pm and GOL= 0.8 pm), the reverse leakage current is reduced. When SCL is further reduced to 0.8 pm, the leakage current characteristics become the same as those of conventional p-n junctions. This is due to the

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Ir (A) Ir (A) 34 Length of Guard Band along Polysilicon-Gate (GPL) {\im) 10 '® SCL= 1.2 pm, GOL= 0.8 pm SCL= 1.6 pm, GOL= 0.8 pm V SCL= 1.2 pm. GOL= 0 SCL= 1.6 pm. GOL= 0 Vr=5 V PMOS-drain/n-well 10 10 0.8 1.2 1.6 2.0 Length of Guard Band along Poly-Gate (GPL) (|xm) Figure 3-8 Reverse characteristics of Schottky clamped drain-to-body junctions with varying Schottky clamp and guard band lengths at reverse bias of 5 V for (a) NMOS, and (b) PMOS transistors.

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35 lateral diffusion of the guard band during a subsequent thermal step and the misalignment between the LDD and heavy source/drain implant patterns, which can shrink the gap between the guard bands, GPL and GOL, and consequently greatly reduce the Schottky barrier effects. These observations suggest that the Schottky barrier contact still dominates the leakage characteristics. Measurement results in Figures 3-8 (a) and (b) show that reducing the guard band length along the polysilicon edge (GPL) from 2.0-pm to O.S-pm does not notably increase the leakage currents for both n-channel and p-channel MOS transistors. This suggests that it may be possible to reduce the designed 1.2-|xm GPL of the SCDR MOS transistor to 0.8-|im without increasing the leakage current of the SCDR junction. On the other hand, when the guard band length along the field oxide edge (GOL) is changed from 0.8 to 0pm, the leakage current is increased by about three times at a 5-V reverse bias, which implies that the guard bands on all edges of the SCDR’s are necessary for improving the reverse characteristics. The minimum length of SCL to maintain low parasitic bipolar current gains is 1.2 pm. The reverse junction breakdown voltage of the SCDR-to-p-substrate junctions is about 13 V which is much higher than the 6-V reverse breakdown voltage of a Schottky barrier drain without the guard ring and is the same as the reverse breakdown voltage of conventional n‘'’-drain-to-p-substrate junctions. For SCDR-to-n -well junctions, the reverse junction breakdown voltage is about 18 V, which is the same as that of conventional p'^’-drain-to-n-well

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36 junctions, again, and is slightly higher than the 16-V reverse breakdown voltage of Schottky barrier drain-to-n-well junctions. The 16-V junction breakdown voltage for the 0.8-|im SBDR-to-n-well junction is much higher than the 6-V junction breakdown voltage for the 1.2-|im SBDR-to-n-well junction presented in the previous chapter. Due to the larger junction layout area of the SCDR junctions than conventional drain junctions, the junction capacitances of the SCDR with GPL= 0.8 |im, SCL= 1.2 pm, and GOL= 0.8 pm are approximately 10% higher than that of a conventional junction for SCDR-NMOS transistors and 27% higher for SCDR-PMOS transistors. 3.2.4 Determination of Barrier Height The barrier heights of SCDR diodes were extracted by measuring Schottky barrier contact forward current-voltage characteristics. The principle underl 3 dng current transport in Schottky barrier contact is closely analogous to the thermionic emission-diffusion theory of carriers into vacuum [34] . The expression of the current-voltage relationship based on thermionic emission is J = A*.T^xp(:g2|exp(^)-l] (3.1) where A** is effective Richardson constant for metal-semiconductor interface (Acm-2K-2), T is temperature in Kelvin, k is Boltzmann constant, Og is the barrier height, n is the ideality factor and V is the bias voltage. For

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37 moderately doped semiconductors, the forward bias current density with V> 3kT/q is J = A**T^exp(:g®)(exp^) (3.2) The extrapolated value of current density at zero voltage is the saturation current, Js, and the barrier height can be obtained from the equation ^ kT, Or = — In B q V (3.3) Figures 3-9 (a) and (b) show the measured forward current and extrapolated value of Jsn for n-SCDR-to-p-substrate Schottky barrier contacts and Jsp for p-SCDR-to-n-well Schottky barrier contacts. To determine the barrier height, the effective Richardson constants. A**, used in (3.3) are 112 A/cm^K^ for electrons and 32 A/cm^K^ for holes in silicon [35]. The extracted Jsn is 1.8 mA/cm^ and Jsp is 3.3 mA/cm^ as shown in Figures 3-9 (a) and (b). At room temperature, 298 K, the barrier heights determined by (3.3) are 0.58 eV for nSCDR-to-p-substrate Schottky barrier contacts and 0.53 eV for p-SCDR-to-nwell Schottky barrier contacts and the ideality factor is 1.05 for both type of Schottky barrier contacts. One thing need to be pointed out is that the value of barrier heights is not very sensitive to the choice of A**, a 100% increase in A** for electrons will cause an increase of only 0.0178 eV in barrier height at room temperature and similarly for holes. The barrier heights for TiSi 2 -to-p-Si

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38 Figure 3-9 Forward characteristics of Schottky clamped drain-to-body junctions diodes for the extrapolation of zero voltage saturation current, Jg, to determine the barrier heights for (a) n-channel, and (b) p-channel SCDR MOS transistors.

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39 is 0.58 eV and for TiSi 2 -to-n-Si is 0.53 eV from (3.3). These results agree well with the reported data in Sze [34] and show that TiSi 2 is a suitable material for both n-channel and p-channel SCDR-MOS transistors because the barrier heights are similar for both electrons and holes. Furthermore, because of this, both n-channel or p-channel SCDR MOS transistors can be formed without making any process modifications. 3.2.5 Conclusion Both n-channel and p-channel Schottky clamped drain MOS transistors with the identical I-V characteristics to those of conventional MOS transistors have been demonstrated exhibiting greatly reducing parasitic bipolar effects and latchup susceptibilities in CMOS technologies. Using SCDR MOS transistors should allow forward-biasing of drain-to-body junctions in integrated RF switch applications with greatly reduced susceptibility to latchup of CMOS circvuts integrated with the switch. Fabrication of the structures requires no additional masks or modifications of the Salicide CMOS process utilized for this work. The reverse leakage currents of the Schottky barrier drain can be greatly reduced by using guard bands. The dimensions of GPL, SCL and GOL for SCDR s presented in this work are 1.2 |im, 1.2 pm, and 0.8 pm. It may be possible to decrease GPL to 0.8-pm to reduce the increase of the junction capacitance without increasing the leakage current of the SCDR junction.

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40 3.3 SCDR CMOS Structure with Reduced Layout Area Output I-V characteristics of SCDR NMOS and PMOS transistors are identical to those of conventional MOS transistors, while the current gains of parasitic n'^-drain/p-substrate/Tz-well and p‘‘’-drain/7i-well/p-substrate bipolar transistors involved in latchup are significantly reduced. This enables a reduction of minimum n^-to-p* spacing of SCDR CMOS structures. This reduced n*-to-p^ spacing results in a layout area reduction thus increasing the packing density of SCDR CMOS circuits. 3.3.1 SCDR CMOS Structure Figures 3-10 (a) and (b) show a cross section of an SCDR and a conventional CMOS structure, respectively. The spacings between n'‘‘-drain-to-n-well (A, see Figure 3-10 (a)) and p‘''-drain-to-p-substrate {B, see Figure 3-10 (a)) are primarily set by latchup susceptibility and could be reduced without compromising the latchup susceptibility by using the SCDR structure. SCDR CMOS structures with varying A and B lengths have been fabricated in the O.S-pm CMOS process to investigate the characteristics of CMOS structures with a reduced n’^-to-p'*' diffusion spacing. The drain lengths, C and D, are 2.4 pm (GPL= 0.8 pm, SCL= 1.2 pm and GOL= 0.4 pm) and 2.0 pm for SCDR and conventional MOS transistors, respectively. The output and tum-on characteristics of the SCDR NMOS and PMOS transistors with a 2.4-pm A and B are identical to those of conventional MOS

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41 transistors as shown in section 3.2. The measurement results also show that the output and turn-on characteristics of SCDR NMOS and PMOS transistors with reduced 7i'*'-to-p‘'' spacings (A= B= 1.6 pm and A= B= 0.8 pm) are also almost the same as those of conventional MOS transistors. The threshold voltage (V^h) of SCDR PMOS transistors with a reduced ri^-to-p^ spacing is one of the transistors parameters which deviates from conventional and SCDR MOS transistors with a 4.8-pm spacing. NMOS V-pH is about 0.70 V all the way down to A of 0.8 pm, while PMOS IV-jhI p-Body Source /r-SCDR Q Gate Sate Oxide Spacer Ox'ide Region p-substrate Schottky Junction (Clamp) (a) Gate + _ . Source p n+-Drain o Y 0 p"*^-Drain Source xate Oxide Spacer Oxide Region p-substrate \ P r * D * % 00 * D * Gate Oxide n-well (b) Figure 3-10 (a) Cross section of an SCDR CMOS structure; (b) Cross section of a conventional CMOS structure.

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42 decreases to -0.81 V from 0.84 V when B is decreased to 0.8 |im. The threshold voltage shift is caused by a decrease of the drawn PMOS channel to n-well edge spacing from 4.4 pm of the conventional structure to 3.2 pm. A further discussion of this threshold voltage shift can be found in the proceeding chapters. The BVceo ® of parasitic DPN and DNP bipolar transistors of the SCDR structure with A= 0.8 pm are 32.4 V and 14.5 V, respectively. These are sufficiently high to provide good transistor isolation between /z'''-drain-ton-well and p‘''-drain-to-p-substrate even though the field oxide length is reduced. 3.3.2 Parasitic Bipolar Actions The parasitic bipolar current gains associated with a CMOS structure increase with a reduced spacing between n.'^-drain-to-n-well and p'^'-drain-to-psubstrate. Using SCDR MOS transistors, the current gain can be maintained below those of conventional CMOS structures even though the n'*'-drain-to-nwell and p''’-drain-to-p-substrate spacing are reduced. Figures 3-11 (a) and (b) show current gains (P) versus | Vbe I curves of parasitic DPN and DNP bipolar structures for SCDR transistors with a varying rP'-to-p^ spacing. The drains serve as the emitters of the bipolar transistors. Current gains of SCDR CMOS structures with a 1.6-pm n'^-to-p'^ spacing are higher than those of

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43 10 " CO. VcB= 5.0V 10 -8 0.4 0.8 10 " CO. VcB= -5.0V 10 -8 (a) Pdpa/ of o conventional NMOS with a 4.8-|im rf-Xo-p^ spacing Pdpa/ of SCDR NMOS with a 4.8-)im rf-Xo-p^ spacing {A=B=2A pm) Pdp/v of an SCDR NMOS with a 3.2-pm rf-Xo-p'^ spacing (>4=S=1 .6 pm) Pdpa/ of an SCDR NMOS with a 1 .6-pm n^-Xo-p^ spacing {A=B=0.8 pm) 1.2 IVbeI (Volt) 1.6 2.0 (b) Pda/p of a conventional PMOS with a 4.8-pm rf-Xo-p'^ spacing Poyvpof an SCDR PMOS with a 4.8-pm n^-to-p"^ spacing (>4=S=2.4pm) -O Pda/p of an SCDR PMOS with a 3.2-pm rf-Xo-p'*' spacing {A=B=‘\ .6pm) -A PoA/P of an SCDR PMOS with a 1 .6-pm rf-Xo-p'^ spacing (/4=S=0.8pm) 0.4 0.8 1.2 IVbeI (Volt) 1.6 2.0 Figure 3-11 p versus | V^e | curves of (a) DPN, and (b) DNP parasitic bipolar transistors for the SCDR structure with varying n'^-to-/?'*’ spacings.

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44 Spacing between nMo-n-well and p'^-to-p-substrate {A and S) (|im) Figure 3-12 Products of maximum current gains (max(p£)p^) x maxCP/j^p)) for conventional and SCDR CMOS structures versus spacing between n‘'’-to-n-well and p‘''-to-p-substrate (A and B). (D: drain, S: source, N: n-well, P: p-substrate) SCDR CMOS structures with a 4.8-)im n‘''-to-p''' spacing but they are still lower than those of conventional CMOS structures even when the n‘'’-drain-tora-well and p'^-drain-to-p-substrate spacings are both reduced to 0.8-pm. Figure 3-12 shows the products of maximum current gains (max(Pjyp^) X max(ppjyp)) against n'*'-drain-to-n-well and p'''-drain-to-p-substrate spacings (A and B) of the SCDR structure for all the possible PNPN th 5 n*istor combinations which could trigger latchup. With a l.S-pm n^-to-p'*' spacing

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45 (A= B= 0.8 fim), the maximum p'*'-drain/n-well/p-substrate//i'''-(irain (DNPD) current gain product for SCDR CMOS transistors is still lower than the unity. The product of the p'^-source/n-well/p-substrate/n'^-source (SNPS) th3aistor is higher than 1 but is still much lower than the maximum DNPD product of the conventional CMOS structure. The SNPS is structurally the same as the conventional CMOS parasitic PNPN thyristor. If necessary, the SPNS product can be reduced to lower than 1 by Schottky clamping the NMOS and PMOS sources. Schottky clamped source/drain NMOS and PMOS transistors have also been characterized to exhibit identical output I-V and turn-on characteristics to those of SCDR NMOS and PMOS transistors, respectively. Even with the 1.6-pm n^-to-p^ spacing, the ultra low current gain products for the SCDR CMOS structure should be able to greatly reduce the susceptibility to latchup. 3.3.3 SCDR CMOS Inverters with Reduced Layout Area CMOS inverters using SCDR NMOS and PMOS transistors with varying n'^-drain-to-n-well and p'^-drain-to-p-substrate spacings have been implemented with PMOS and NMOS channel widths of 12-|im. Figure 3-13 shows the inverter transfer characteristics of SCDR CMOS inverters with 4.8 |xm, 3.2 pm and 1.6 pm spacings. The dimensions of the SCDR junctions for the inverters are GPL= 0.8 pm, SCL= 1.2 pm and GOL= 0.4 pm. For SCDR CMOS inverters, the transfer characteristics are almost identical for all the investigated n'^-to-p'^ spacings. The slightly shift of the inverter switching

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46 Figure 3-13 Voltage transfer curves of SCDR CMOS inverters for varying n*to-n-well and />‘‘‘-to-p-substrate spacings (A and B). point for the structure with A= B= 0.8 pm is due to the slight PMOS V^h shift. Figure 3-14 compares the transfer characteristics and supply currents for both conventional and SCDR CMOS inverters. The ri^-to-p'^ spacing is 1.6 pm (A= B= 0.8 pm) for the SCDR inverter. The voltage transfer characteristics are almost identical. The off currents of the SCDR inverter are higher than those of the conventional CMOS inverter due to the higher junction leakage currents of SCDR junctions. The ratio of onand off-current is about 10® for the SCDR CMOS inverter.

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47 Figure 3-14 Voltage transfer curves and supply currents for SCDR and conventional CMOS inverters. |im) SCDR CMOS inverters with a reduced n'''-to-p''' spacing which exhibit almost the same voltage transfer characteristics to those of conventional CMOS inverters have been implemented. The layout area of the SCDR CMOS inverter with a 1.6-|o.m n^-io-p^ spacing has a ~ 17% reduction compared to the conventional CMOS inverter. The parasitic n'^-drain/p-substrate/n-well and p'*'-drain/n-well/p-substrate bipolar transistor actions of CMOS technologies are also radically reduced even though the spacing between ri^-to-p* is reduced to 1.6-pm from

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48 4.8-|im. The SCDR CMOS structures with a reduced ri^-to-p^ spacing also exhibit good transistor isolation. 3.4 Summary iV-channel and p-channel Schottky clamped drain MOSFET’s with improved I-V characteristics from those of SBDR MOS transistors have been demonstrated while greatly reducing the parasitic bipolar effects and latchup susceptibility in CMOS structures. Fabrication of the structures requires no additional mask or modifications of the Salicide CMOS process utilized for this work. Unlike SBDR transistors, SCDR transistors exhibit identical output and turn-on characteristics to those of conventional MOS transistors. In addition, the SCDR junction exhibits a lower leakage current and a higher breakdown voltage than the SBDR junction due to a guard band structure along the edges of the SCDR junction. The guard band structure reduces the electric fields at corners and also preserves the electrical characteristics of a normal MOS transistor. In SCDR MOS transistors, the parasitic /i''’-drain/p-substrate/ n-well as well as /)‘'’-drain//i-well/p-substrate bipolar transistor actions of CMOS technologies are radically reduced since Schottky barrier diodes which do not inject minority carriers clamp the n'*'-drain-to-p-substrate and p'^-drainto-n-well junctions. Like the SBDR structure, these, in turn, reduce current gains of the parasitic bipolar transistors, and lead to significantly reduced latchup susceptibility.

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49 The low current gain of SCDR CMOS structures enables a reduction of the minimum n^-to-p-^ spacing of SCDR circuits. SCDR CMOS inverters with a reduced n^-to-p^ spacing exhibit almost the same voltage transfer characteristics to those of conventional CMOS inverters, while the layout area is about 17% less than the conventional CMOS inverter. These should enable area reduction of digital and analog circuits using SCDR MOS transistors.

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CHAPTER 4 CMOS RADIO FREQUENCY SWITCHES 4.1 Introduction A high quality transmit/receive switch is a key building block of the RF front end of most time-division duplexing (TDD) communication systems. In this chapter, an RF switch fabricated in a 0.5-pm CMOS process is presented. The effects of substrate resistances and source/drain-to-body capacitances associated with MOS transistors on insertion loss of RF switches have been analyzed. The substrate resistance and source/drain-to-body capacitance must be lowered to decrease insertion loss. A low insertion loss CMOS RF switch can be achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by DC biasing the source/drain nodes of the transistors which decreases the capacitances while increasing the power 1-dB compression point. A single-pole single-throw RF switch was developed. The switch exhibits 0.8 dB insertion loss, and 40 dB isolation for operating frequencies up to 1 GHz. The use of Schottky clamped MOS transistors for the RF switch can greatly reduce the susceptibility to latchup triggered by the forward biasing of the source/drain-to-body junction diodes during large voltage excursions at the input of the switch [1]. 50

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51 4.2 Schottkv Clamped MOS Transistors The transistor characteristics of SCDR, and Schottky clamped source and drain MOS transistors are almost the same as those of conventional MOS transistors. However, the junction capacitances of Schottky clamped junctions are higher than those of conventional source/drain-to-body junctions due to a larger layout area. The increased junction capacitance may reduce the impedance from source/drain to the substrate which in turn increases the RF signal coupling to the substrate and increase the insertion loss of RF switches. Schottky clamped MOS transistors for RF switch applications have been implemented in a foundry 0.5-pm CMOS process. Figure 4-1 shows a layout of the Schottky clamped MOS transistor. The transistor width is 612 pm. The test transistor utilizes a multiple gate finger structure. The width of each gate finger is 9 pm. Both the source and drain of the transistor are Schottky clamped, which can greatly reduce the parasitic bipolar action associated with the parasitic p'''-source/drain-to-n-well-to-/?-substrate-n'Â’Â’-source/drain (PNPN) th3uistor structure which can trigger latchup. The guard band lengths along the polysilicon gates of the Schottky clamped junction are 0.6 pm, and the guard band lengths are 0.3 pm on the other two edges, and the SCL is 0.9 pm for the Schottky clamped MOS transistor. 4.2.1 RF Characteristics Figure 4-2 shows the measured insertion loss and isolation of conventional and Schottky clamped NMOS transistors. The structure was measured

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52 Figure 4-1 A layout of the Schottky clamped test transistor. on-chip using RF probes. Insertion loss was measured when the gate voltage was 5 V to turn on the transistor and source/drain voltages of the transistor were zero volt. Insertion losses of both conventional and Schottky clamped NMOS transistors are similar for frequencies up to 4 GHz. Insertion loss is about 1 dB at 1 GHz. The increased junction capacitance of the Schottky clamped junctions has almost no impact on the insertion loss of the NMOS transistor at on-state at the frequencies of interest between 1 and 2.4 GHz. Isolation was measured when the transistor was turned off (Vqs= Vqd = 0 V). Isolation characteristics of Schottky clamped MOS transistors are slightly

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53 Figure 4-2 Measured insertion loss and isolation for conventional and Schottky clamped NMOS transistors as switches. (^/l= VcTRL= 5.0 V, VcTRL= 0.0 V) poorer than that of the conventional NMOS transistor for frequencies up to 4 GHz. At 1 GHz, isolation of the Schottky clamped NMOS transistor is about 1.7 dB lower than the 18.5-dB isolation of the conventional NMOS transistor. The lower isolation of Schottky clamped NMOS transistors is attributed to the increased source/drain-to-body capacitance which increased the signal coupling from input (drain node of the transistor) to output (source node of the transistor) through the substrate of the transistor. Figure 4-3 shows the measured insertion loss and isolation of conventional and Schottky clamped PMOS transistors. The test structure was

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54 Figure 4-3 Measured insertion loss and isolation for conventional and Schottky clamped PMOS transistors as switches. (^/l= VcTRL= '5-0 V, VcTRL= 0.0 V) similar to the NMOS transistor. Insertion loss was measured when the gate voltage was applied by a -5 V to turn on the transistor and source/drain voltages were 0 V. Insertion losses of both conventional and Schottky clamped PMOS transistors are similar for frequencies up to 4 GHz. Insertion loss is about 1.4 dB at the frequency of 1 GHz. Again, the increased junction capacitance of the Schottky clamped junction has almost no impact on the performance of the PMOS transistor at on-state. Isolation was measured when the transistor was turned off (Vgs= V(jd = 0 V). Isolation of the Schottky clamped PMOS transistor is slightly poorer than that of the conventional PMOS

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55 transistor. At 1 GHz, isolation of the Schottky clamped PMOS transistor is about 1.3 dB lower than the 14.3-dB isolation of the conventional PMOS transistor. Schottky clamped NMOS and PMOS transistors have been characterized. The insertion loss and isolation of Schottky clamped MOS transistors are similar to those using conventional MOS transistors especially at the frequencies of interest between 1 and 2.4 GHz. RF switches using Schottky clamped MOS transistors should have similar RF performance as those using conventional MOS transistors while having greatly reduced susceptibility to latchup than conventional MOS transistors. At 1 GHz, NMOS transistors exhibit lower insertions loss and higher isolation than those of PMOS transistors. For 900-MHz switch applications, NMOS transistors should provide a lower insertion loss per unit device area than PMOS transistors. 4.3 Design and Optimization of RF Switches The ultimate goal of this work is implementing RF switches for L band near 1 to 2.6 GHz applications using both conventional and Schottky clamped MOS transistors. The use of Schottky clamped MOS transistors should reduce the latchup susceptibility in integrated circuits with RF switches. The design of RF switches using Schottky clamped MOS transistors is similar to those using conventional MOS transistors due to the fact that both Schottky clamped and conventional MOS transistors exhibit similar RF characteristics as described in the previous section. Key figures of merit for RF switches are

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56 insertion loss, isolation and power handling capability. For switches implemented in bulk CMOS process, due to the conductive nature of silicon substrates, substrate losses play an important role in determining insertion loss in addition to the channel resistance of the transistor. The impact of substrate loss on insertion loss of switches will be analyzed. In addition, since no bulk CMOS single-pole double-throw (SPDT) T/R switches suitable for 900 MHz wireless applications have been reported [9-10] prior to this work, as a first step, a simple single-pole single-throw (SPST) RF switch for 900 MHz applications will be developed to understand the feasibility of using bulk CMOS technologies for RF switches. 4.3.1 Insertion Loss and Conductive Substrate In order to quantitatively understand the impact of substrate resistances, capacitances, and on-resistances, insertion loss has been analyzed. To simplify, instead of analyzing a complete switch, the circuit containing a single MOS transistor in Figure 4-4 (a) has been analyzed. For this analysis, the transistor is assumed to be biased in linear region. Insertion loss (IL) measures the small signal power loss through an RF switch when the switch is turned on. The expressions for insertion loss are given in (1.1) and (1.2). This quantity can be shown to be the reciprocal of the magnitude square of forward transmission coefficient ( | S 21 1 ^) if both load and source impedance are matched to the characteristic impedance (Zq).

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57 (a) 1 Rr * VqsVqd V RF (b) (c) Figure 4-4 (a) A MOS transistor switch in a 50-Q system; (b) An equivalent circuit diagram of the circuit shown in (a) for small signal analyses; (c) An approximate equivalent of the circuit shown in (b). ilMW

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58 Figure 4-4 (b) shows the equivalent circuit of the MOSFET switch shown in Figure 4-4 (a) [36] . At low frequencies, on resistance of the transistor determines insertion loss. As the operating frequency is increased, due to an increase of capacitive coupling, the power loss in substrate resistances associated with the transistors is increased. The circuit in Figure 4-4 (b), though relatively simple, unfortunately cannot be easily analyzed to provide meaningful insights. Because of the fact that the impedance of the on-resistance of the transistor is usually small compared to the impedance of the parasitic capacitances of the transistor at 1 GHz, the circuit shown in Figure 4-4 (b) can be approximated as the circuit shown in Figure 4-4 (c). The plots in Figure 4-5 show simulated insertion loss of the circuits in Figures 4-4 (b) and (c) for the typical ranges of values for the on-resistance and source/drain-to-body capacitances of MOS transistors utilized in the RF switches. Both figures show no difference between the curves for the two circuits indicating that the circuit in Figure 4-4 (c) is a good approximation of the circuit in Figure 4-4 (b). For this simplified circuit, insertion loss (IL) is (see Appendix) TT _ 1 _ (^^on + ^Zq) +C0 [(Rqj^ -I2Zo)Rg + (Rqn + Zo)Zq] ilj _ _ IS 21 I (2Zo)"(1-hco"Ct"Rb ) where co is the radian frequency, Zq is the characteristic impedance, Rqn transistor on-resistance, Rg is the substrate resistance associated with the transistor and C-p ^DB + ^SB + (CpD + Cqs)Cqb ^GD + ^GS + ^GB is the equivalent capacitance shown in Figure 4-4 (c). For 0.5-pm transistors biased in linear region.

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Insertion Loss (dB) Insertion Loss (dB) 59 Figure 4-5 (a) Simulated insertion loss versus Rqn the circuits shown in Figures 4-4 (b) and (c) at 1 GHz; (b) Simulated insertion loss versus Cdb and CgB for the circuits shown in Figures 4-4 (b) and (c) at 1 GHz.

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60 Cqb is negligible which yields C-p = Cp)B + Csg. IL can also be expressed in terms of the transistor width (W). IL = R ONO w + 2Z„]" + 0)"Cto'[(%2 + 2Z„]Rbo + (Rono + ZoW)Zo]' (2Z„)^1 + 0)^Cto^Rbo^) (4.2) where Rbo= Cto= C^/W, and Rqno= I^ON^. For a given technology and layout type, Rbo> ^T0> ^ONO be assumed to be fixed. In actuality, Rb does not scale linearly with the width and this will introduce some errors. It is straightforward to see that when W is large, the numerator of (4.2) becomes large and insertion loss becomes large. When W becomes small, the numerator of (4.2) also becomes large and insertion loss becomes large. This indicates that there is an optimum width for which insertion loss is minimized. For Cto= 1-4 fF/pm, Rono= KQ-pm, and Rbo= Kf2-pm of the 0.5-pm CMOS process, insertion loss is near the minimum for widths between -0.6 to 0.9 mm. If C-p is zero, IL becomes IL I 2Zo J when Crp = 0 (4.3) which is the insertion loss at low frequencies. Comparing (4.1) and (4.3), it is easy to see the detrimental impact of C-p which couples signals to the substrate.

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61 It is also easy to show that according to (4.1), there is a value of Rg for which insertion loss is the maximum. When Rg is infinite, IL becomes the low frequency insertion loss given in (4.3). When Rg= 0, IL is TT _ (^on + 2Zq) + [coC-rZQ(RoN + Zq)] whpn = n (4.4) lJ-< — T B (2Zo)^ Figure 4-6 shows IL versus Rg plots for the circuits in Figures 4-4 (a) and (c). The plot for the circuit in Figure 4-4 (a) is obtained using Hspice while that for the circuit in Figure 4-4 (c) has been computed using (4.1). Once again, the Figure 4-6 A simulated insertion loss versus Rg plot for the circuits shown in Figure 4-4 (a), and an insertion loss computed with (4.1) versus Rg plot for the circuit shown in Figure 4-4 (c) at 1 GHz. The bias condition was VQg= 6.0 V and Vgg= Vgg= 3.0 V.

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62 plots are very close. As discussed, there is a maximum point. By maximizing (4.1), it can be shown that the maximum insertion loss occurs at ^B(MAX) = -CO C-p • (Rqj^Zq + Zq ) + J(£> Crp • (Rqj^Zq + Zq ) + 4co C-j(I^ON 2co Crp • (Rqn ^^ 0 ^ (4.5) To achieve low insertion loss in RF switches fabricated with CMOS technologies, special attention must be paid to avoid transistor substrate resistances near Rb(MAX)typical CMOS RF switches operating at 1 GHz, C-p is on the order of a couple pico-Farad and Rqn is on the order of a few Ohms. Under these conditions, (4.5) can be simplified to Rb(maX) ~ l/wC-p In hind sight, this is an obvious result. The power loss associated with the Rg-Crp series network is maximized when Rg= l/coC-p. When this occurs, insertion loss is maximized. For the 0.5-pm transistors utilized in 1-GHz RF switches, as mentioned, C-p is generally ~ 0.8 to 2.0 pF and the corresponding Rb(MAX) ~ 200 Q. Unfortunately, this is in the typical range of Rg’s for transistors in RF switches if nothing has been done to control the substrate resistance. These results have shown that insertion loss can be reduced by increasing Rg to a very large value or by decreasing Rg to near zero. Insertion loss for the case when Rg= 0 is larger than the case for infinite Rg because of the coC-pZo(RoN+Zo) term in the numerator of (4.1). Once again, C-p must be reduced in order to decrease insertion loss. As discussed earlier, if C-p= 0,

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63 insertion loss will become the low frequency loss in (4.3). In terms of the underlying physical mechanism, when Rg becomes large, signals cannot couple to Rb and the power consumption associated with Rg is small. This is the advantage of using semi-insulating substrates over conductive substrates to implement RF switches. When Rg is zero, there is no loss associated with Rg, and the power loss is once again reduced. 4.3.2 MOSFET-based RF Switch Design Figure 4-7 is a schematic of an SPST NMOS RF switch. Transistors Ms performs the main switching function, while the shunt transistor Mp is used RFin and Drain DC Bias o RFquT and Source DC Bias Me Mp Input Source DC Bias Cb Figure 4-7 Circuit schematic of an SPST RF switch.

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64 to improve the isolation of the switch by grounding the RF signal when the switch is off. Static power consumption of the switch can be kept near zero by appl 5 dng the same DC voltage on the top plate of the bypass capacitor Cg as the DC voltage for RFjn node. On-resistance of Ms is one of the dominant factors determining the insertion loss. Because of this, only n-channel MOSFETÂ’s are used in the design due to the fact that n-channel MOSFETÂ’s provide lower insertion loss per unit device area than p-channel MOSFETÂ’s at 900 MHz. The drain-to-body and source-to-body junction capacitances of Ms, the drain-tobody junction capacitance of Mg and associated parasitic resistances due to the conductive nature of silicon substrates are also critical factors determining the insertion loss. The gate bias resistances, R(js ^GP> implemented using poly resistors. A typical value for the gate bias resistance is about 10 kO. The purpose of Rqs and Rgp is to improve DC bias isolation [2], [6], [37]. If the gate bias resistance is missing, the Vfjg and Vq 3 of the transistor can fluctuate due to the high voltage swing at drain and source of the transistor. For MOS RF switches, these fluctuating voltages across the gate dielectric not only affect the MOSFET channel resistance but also may result in excessive voltage drop across the gate dielectric and cause dielectric breakdown. Figure 4-8 shows the simulation results of insertion loss versus the width of Ms in the SPST switch. For the given bias condition, Vgb= 6.0 V, Vdb sb= ^ transistor width is increased, on-resistance decreases and insertion loss decreases. However, if the transistor width is

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65 Figure 4-8 The effects of the transistor width on insertion loss of an SPST switch. Wms= 2 X W]v[p Bias Condition: V(jb= 6.0 V, SB= ^.0 V. increased excessively, the signal loss through capacitive coupling to the substrate becomes significant and insertion loss increases with the increasing width. According to the simulation, for the chosen bias conditions. Mg should be 600-|im wide to minimize insertion loss. Substrate resistance is another critical factor determining insertion loss. Figure 4-9 (a) is a schematic of the SPST switch including important substrate resistances. Figure 4-9 (b) shows the simulated insertion loss of the switch versus parasitic substrate resistances associated with the drain-tobody and source-to-body junction capacitances of Mg and Mp at 960 MHz. As shown in the analysis, the simulation also suggests two approaches to

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Insertion Loss (dB) 66 RF i IN RF, OUT (a) Figure 4-9 (a) Circuit schematic of an SPST RF switch including key substrate resistances; (b) The effects of the transistor substrate resistances (resistances from S/D to ground) on insertion loss of an SPST RF switch at 960 MHz. (Rb,mp= ^ x Rb,ms» ^Bsubstrate resistance).

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67 improve insertion loss. One is to increase the substrate resistances by a large amount to lower the signal coupling into the substrate. However, the practicality of this approach is limited in bulk CMOS integrated circuits on conductive substrates. Another is to radically reduce the substrate resistances to make the substrate almost loss-less. This is more practical in bulk CMOS technologies. 4.3.3 DC Bias Condition of SPST RF Switches Bias condition is also crucial for RF switches. Insertion loss and the PldB can be largely improved by applying an appropriate DC bias. RFjn node and the sources of Mg and Mp are DC biased to 3 V instead of 0 V. This voltage reverse biases the source/drain-to-body junctions, which decreases the capacitance and RF signal coupled to the substrate and thus insertion loss is improved. Another purpose of the 3-V DC bias for RFjn and RFqut nodes is to improve the power handling capability measured by PidBIf th® DC voltage for RFjn, RFout and Vctrl i® zero, then an RF input voltage with an amplitude of 0.5 V forward biases the source/drain-to-body junctions in some portion of a cycle. This clips the RF signal and causes the output power to compress. When Mg is on, with the 3-V DC bias, PidB I® limited by unintentional turning on of Mp This is because of the RF signal coupling due to the voltage divider form by gate-to-drain, gate-to-source and gate-to-body

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68 capacitances of Mp (Cqp> ^p^ Cqs,mp ^GB.Mp)Assuming the total drain voltage of Mp is = Vj) + vj) where Vj) is the DC drain voltage of Mp and vj) is the RF voltage at the drain node of Mp the voltage appeared at the gate node of transistor Mp Vg, is Vg Vq + Up • ^ 'GD.MP GD, MP + ^GS, MP + ^GB, MP (4.6) The DC gate voltage for Ms is set to 6 V, and that for Mp is set to 2 V to turn on the switch. For the 0.5-pm NMOS transistor under this bias condition, the ratio of 'GD, MP (^GD, MP + ^GS, MP + ^GB, Mp) is about one-third. If an RF voltage with an amplitude of around 2.7 V is applied, then the minimum voltage at the drain node of Ms will be Vj jnin= 3.0 2.7= 0.3 V, and the source/drain-tobody junctions are reverse biased. The minimum gate voltage of Mp from (4.6) is Vg jnin= 2.0 2.7 X V3 = 1.1 V which is -0.9 V lower than the DC bias voltage due to the RF voltage capacitively fed forward from RFjn [2]. The maximum gate-to-drain voltage (Vgj) of Mp is Vg Vd= 1.1 V 0.3 V= 0.8 V, which is higher than the threshold voltage (V-pn) of the 0.5 -pm transistor, and the transistor, Mp starts to turn on. This unintentionally turned-on transistor clips the output waveform and once again makes the output power of the switch to compress. However, the RF power level before the clipping occurred for the 3V source/drain-to-body bias case is significantly higher than that for the 0-V DC bias case.

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69 4.3.4 Experimental Results of 900 MHz SPST Switches An SPST RF switch has been implemented in a 0.5-|im CMOS process. The width of Ms and Mp are 612 |im and 306 pm, respectively, to minimize the insertion loss. The substrate resistance of Ms is about 14 Q and the substrate resistance is about 20 Q for Mp They are sufficiently low to significantly reduce the substrate losses. The low substrate resistances are achieved by fully surrounding the transistors with large area p"*" substrate contacts and filling in any open spaces with substrate contacts. Figure 4-10 shows the measured and simulated insertion loss and isolation for the SPST RF switch. Measured insertion loss is 0.8 dB, and isolation is 40 dB for operating frequencies up to 1 GHz at a Vctrl ^ ^GB ® 0 and a drain/source-to-body reverse bias (Ypp and Vsp) of 3.0 V. The measured insertion loss agrees well with the simulation, while the measured isolation is a few dB lower than that of simulation. Over 40-dB isolation of the switch for frequencies up to 1 GHz is excellent. The insertion loss of the SPST switch is about 0.2 dB lower than that of the single NMOS switch described in the previous section and isolation is greatly improved by about 22 dB. The lower insertion loss is achieved by optimizing the transistor widths and bias, and by minimizing the substrate resistances, while the higher isolation is achieved by grounding the RF signal through Mp when the switch is off. Lastly, The 6.0-V Vqtpl obtained by using a voltage doubler.

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70 Figure 4-10 Measured and simulated insertion loss and isolation for the SPST switch. (VcTRL= V, Vdb SB= 3.0 V) 4.4 Summary Schottky clamped (SC) MOS transistors for RF switch applications have been implemented in a foundry 0.5-pm CMOS process. The transistor width is 612 p.m. Both source and drain of the transistor are Schottky clamped. The measured insertion loss and isolation of the structure using a Schottky clamped MOS transistor are similar to those using a conventional MOS transistor especially at the frequencies of interest between 1 and 2.4 GHz. RF switches using Schottky clamped MOS transistors should have

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71 similar performance to those using conventional MOS transistors, while having greatly reduced susceptibility to latchup. The impact of conductive silicon substrate on insertion loss has been analyzed. The analysis showed that substrate resistances and junction capacitances associated with transistors need to be reduced to improve insertion loss. A single-pole single-throw (SPST) RF switch has also been presented. The switch was fabricated in a foundry 0.5-)im CMOS process. It exhibits a 0.8-dB insertion loss and a 40-dB isolation. The switch has adequate insertion loss and isolation for a number of 900-MHz applications. This work suggests that a single-pole double-throw (SPDT) RF T/R switch could be implemented in bulk CMOS technologies and also be integrated with the other CMOS transceiver circuits.

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CHAPTERS SCHOTTKY DIODE CLAMPED MERGED DRAIN CMOS STRUCTURE 5.1 Introduction During this work on developing approaches to reduce latchup susceptibility using Schottky clamped MOS transistors, a TiSi 2 -Si Schottky diode clamped merged drain (SCMD) CMOS concept has been discovered. In this chapter, this new CMOS structure is demonstrated by fabricating it in a foundry 0.8-|xm Salicide CMOS process. Output I-V characteristics of SCMD MOS transistors are almost identical to those of conventional MOS transistors and isolation of the transistors are preserved, while the current gains of parasitic n‘'’-drain/p-substrate/n-well and p'''-drain/n-well/p-substrate bipolar transistors involved in latchup are significantly reduced. This enables a reduction of the n‘''-to-p''’ spacing. This reduction in combination with the decreased drain lengths of transistors in the SCMD CMOS structure results in a ~ 30% area reduction for an inverter. 72

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73 5.2 SCMD CMOS Transistors 5.2.1 SCMD CMOS Device Structure Figures 5-1 (a) and (b) show a cross section of an SCMD and a conventional CMOS structures. Similar to SCDR CMOS transistors, implementation of the SCMD CMOS structure requires simple layout changes and does not require any process modifications. Layouts of SCMD and conventional CMOS Source SCMD Source n-Body 0 T TiCi. Hate Oxi Spacer Oxide Region p-substrate / 0.8|xm NMOS Drain PMOS Drain (a) p-Body Gate + . Source a -Drain Gate Hate Oxide Spacer Ox'ide Region 2.0 p,m p-substrate (b) Figure 5-1 (a) Cross section of an SCMD CMOS structure; (b) Cross section of a conventional CMOS structure.

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74 structures are shown in Figures 5-2 (a) and (b), respectively. The gate length and channel width are 0.8-pm and 12-|ini, respectively. A major difference between SCMD and SCDR MOS transistors is that on the drain side, the field oxide region between ri^ and drains is removed. The source/drain implantation was partially masked to form a TiSi 2 -Si Schottky barrier contact, and an n-type and a p-type guard band along the ploysilicon gates. The and guard bands along the polysilicon gates act as conventional drains for n-channel and p-channel devices, respectively. In the 0.8-pm CMOS process, the SCMD structure has a smaller drain length of 0.8 pm versus 2.0 pm, and has an M'^-to-p'^-drain spacing of 3.2 pm versus 4.8 pm of the conventional CMOS structure. These result in a ~ 30% area reduction for a CMOS inverter. The area reduction of an SCMD CMOS structure is accomplished by exploiting the following: (1) TiSi 2 forms Schottky barrier junctions to both moderately doped n and p-type silicon regions (doping concentration less than ~ 5x10^® cm'^) [34] and TiSi 2 forms good ohmic contacts to and p^ regions; (2) current gains of NMOS-drain/p-substrate/n-well (DPN) and PMOS-drain/ n-well/p-substrate (DNP) parasitic bipolar transistors for Schottky clamped NMOS and PMOS [17] transistors are radically reduced, which allows the spacing between n"*" and p'*’ drains to be reduced to 3.2 from 4.8 pm without compromising the latchup immunity; (3) the lengths of n'*’ and p~^ drains can be reduced to 0.8 from 2.0 pm, since using a TiSi 2 layer to connect the and

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75 Diffusion p* Implant rf*' Implant Schottky Diode Clamped Merged Drain (SCMD) n-well Diffusion n* Implant p* Implant (a) Diffusion p* Implant n* Implant n-well Diffusion n* Implant p^ Implant (b) Figure 5-2 (a) Layout of an SCMD CMOS structure; (b) Layout of a conventional CMOS structure.

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76 drains eliminates the need for one of the two drain contacts in Figure 5-1 (b) and the remaining contact can be placed an 3 rwhere on the TiSi 2 layer; (4) because the TiSi 2 layer connecting the and p'*’ drains forms reverse biased Schottky barrier junctions to both n-well and p-substrate, the TiSi 2 layer is electrically isolated from n-well and p-substrate, and this enables the removal of the field oxide region between the ri^ and drains in the conventional CMOS structure; (5) the BVceq ® DPN and DNP bipolar transistors are 19.3 and 13.5 V, respectively and these are sufficiently high to provide good isolation between n"'’-drain and n-well, and between p'*'-drain and p-substrate even though the field oxide and field implanted regions are removed; and (5) the on-characteristics of the PMOS in SCMD CMOS structures are only slightly altered. Lastly, the silicide does not have to be TiSi 2 . Other silicides such as CoSi 2 which form Schottky barrier junctions to nand p-type silicon with comparable barrier heights as TiSi 2 [34] should also be applicable. 5.2.2 Parasitic Bipolar Actions Figure 5-3 shows current gain products for DPN and DNP parasitic bipolar structures of the SCMD and conventional CMOS transistors. The drains serve as the emitters of the bipolar transistors. Current gains of the bipolar structures in the SCMD CMOS structure are significantly reduced. As a matter of fact, for | | ’s between 0 and 2.0 V, products of the current gains for the SCMD inverter are less than the unity. The parasitic DPN and DNP

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77 w o 3 T3 O GL s c <0 O C 0) k. 3 o , I , I . 1 1 0.4 0.8 1.2 1.6 2.0 IVbeI (Volt) Figure 5-3 Current gain products {^dpn x PoiVp) I Vbe I plots for NMOSdrain/p-substrate/n-well (DPN) and PMOS-drain/n-well/p-substrate (DNP) parasitic bipolar transistors in SCMD and conventional CMOS transistors. bipolar actions in the CMOS structure are greatly reduced since Schottky barrier junctions, which do not inject minority carriers, clamp the n'^-drain-to-psubstrate and p'^-drain-to-n -well junctions [32]. These, in turn, reduce current gains of the parasitic DPN and DNP transistors, and lead to significantly reduced latchup susceptibility.

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78 5.2.3 Schottkv Clamp Lengfth SCMD CMOS transistors have comparable I-V characteristics to those of conventional MOS transistors. In order to maximize area reduction while maintaining low parasitic bipolar current gains and good transistor isolation, the length of Schottky clamps (SCL, see Figure 5-4) should be optimized. The Schottky clamp length (SCL) should be as short as possible to achieve the maximum area reduction. However, it can not be too short. If the SCL is too short, the Schottky clamping effects may be lost and the isolation between p^drain-to-p-substrate and/or n‘‘’-drain-to-n-well may be degraded below the acceptable limit. As mentioned, the minimum SCL is primarily set by two factors, the transistor isolation and the parasitic bipolar current gain. The minimum acceptable SCL is determined experimentally. The shortest SCL in the experiment is 0.8 pm which is limited by the lateral diffusion of n-well and drain xate Oxi Spacer Oxide Region p-substrate / O.Sum NMOS Drain PMOS Drain Figure 5-4 Cross section of an SCMD CMOS inverter with the definition of Schottky clamp length (SCL).

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79 implants. The the longest SCL is 2.4 pm which corresponds to the drain-to-nwell spacing for the conventional CMOS structure. Figure 5-5 shows the products of maximum current gains (max(p^p^) x max(Pp^p)) versus SCL of SCMD for all the possible PNPN thyristor combinations which could trigger latchup. As SCL decreases, the products of maximum P's increase. However, they are still much lower than those of the conventional CMOS structure except for the product of the p'^’-source/n-well/psubstrate/n‘''-sovu-ce (SNPS) thyristor. The SNPS is structurally the same as Figure 5-5 Products of maximum current gains (max(P^p 2 y) x max(pp^p)) for conventional and SCMD CMOS structures versus Schottky clamp length (SCL). (D: drain, S: source, N: n-well, P: p-substrate)

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80 the conventional CMOS parasitic PNPN thyristor. To ensure that this product is less than those of the conventional CMOS structure, SCL must be at least 1.6 |im compared to 2.4 }im in the conventional CMOS structure. This restriction, however, can be easily lifted by Schottky clamping the NMOS and PMOS sources. As mentioned in the previous chapters, MOS transistors use a Schottky clamped source exhibit identical output I-V and tum-on characteristics as those of SCDR MOS transistors. In Figure 5-6, BVceo ® parasitic DNP bipolar transistors of the SCMD inverter remain constant for SCL’s ranging between 0.8 and 2.4 pm. Figure 5-6 BVceo parasitic DPN (n‘*'-drain/p-substrate/n-well) and DNP (p '-drain/71 -well/p-substrate) bipolar transistors of SCMD CMOS transistors.

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81 For the DPN transistors, BVqeo decreases sharply when SCL is reduced below 1.2 |im. These BVceo characteristics set the minimum SCL between n'^ and n-well to 1.2 |im and that between p'*' and p-substrate to 0.8 |im. Figures 5-7 (a) and (b) show Ids'^DS characteristics of SCMD (SCL= 1.6 |im) and conventional NMOS and PMOS transistors. Output characteristics of conventional and SCMD NMOS transistors are identical. Compare to the conventional PMOS transistor, the SCMD PMOS transistor has slightly higher drain current than that for the conventional PMOS due to a 0.1-V increase of the threshold voltage caused by a decrease of the drawn PMOS channel to n-well edge spacing from 4.4 pm of the conventional structure to 2.4 pm. The threshold voltage of SCMD MOS transistors is one of the transistors parameters which deviate from those of conventional MOS transistors. Figure 5-8 shows plots of | V^jj | versus SCL for the NMOS and PMOS transistors. NMOS I Vth I is almost constant all the way down to SCL of 0.8 pm, while PMOS | | decreases to ~ 0.66 V from 0.84 V when SCL is decreased to 0.8 pm. The higher threshold voltage of SCMD PMOS transistors could be an advantage for some applications where higher drive currrent is desired. Figure 5-9 shows the SCMD PMOS transistor off-state source current. The off-current increases when SCL is reduced below 1.6 pm. Although ~ 3 l,Tn at an SCL of 0.8-pm is acceptable, for the off-state current to be independent of SCL, SCL should be greater than or equal to 1.6 pm. The off-state

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Ids (mA) 82 Figure 5-7 (a) Measured Ids'^ds characteristics for SCMD and conventional NMOS transistors; (b) Measured Ids'^DS characteristics for SCMD and conventional PMOS transistors.

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83 Figure 5-8 Threshold voltage versus Schottky clamp length of SCMD NMOS and PMOS transistors. source current of PMOS transistors is ~ 0.1 at Vds= -5 V when SCL is greater than or equal to 1.6 |im. Figure 5-10 shows the leakage currents of junctions in SCMD and conventional CMOS transistors. The leakage currents at room temperature for junctions in SCMD transistors are ~ 1 at a 5 volt reverse bias. This ~ 1 leakage currrent of the SCMD junction is about 10 times higher than that of the SCDR junction. Note that the guard band structure on the field oxide edges is not utilized in the SCMD structure as shown in Figure 5-2 and this may result in a higher leakage current of the SCMD junction. For

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84 Figure 5-9 Off-state source current versus Schottky clamp length for SCMD PMOS transistors. temperatures above 300 °K, the leakage current of the Schottky clamped junctions doubles approximately every 10 °K increase in temperature [23], [38-39]. Though the off-current of SCMD inverters is higher, the room temperature leakage is almost low enough to satisfy the off-state leakage current specification of CMOS technologies. The junction capacitance including the Schottky, p^-n and ri^-p junctions of the SCMD structure should be ~ 10% higher than the conventional junctions. This corresponds to a 3% increase in the load capacitance for each

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85 10 ^E 3 < C c cc 03 0 _l c _o o c 3 10‘ 10' Mean Maximum • Minimum ^Reverse" ^ SCMD D/P SCMD D/N Conventional D/P Conventional D/N Figure 5-10 Leakage currents of junctions in SCMD (SCL= 2.0 |im) and conventional CMOS transistors. (D: drain, N: n-well, P: p-substrate) stage in an inverter chain with a fan-out of one. This should have only a small impact on the speed performance. 5.3 SCMD CMOS Inverters 5.3.1 SCMD CMOS Inverter Characteristics To demonstrate the applicability of the SCMD CMOS structures, SCMD CMOS inverters and a 100-stage inverter chain have been implemented. A cross section of an SCMD CMOS inverter was shown in Figure 5-4.

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86 Figure 5-11 shows the voltage transfer characteristics (VTC) and supply currents of conventional and SCMD CMOS (SCL= 1.6 pm) inverters with PMOS Width= NMOS Width= 12 pm. The VTC curves are almost identical. The slight shift is due to the difference in the PMOS threshold voltage. However, the supply currents of the SCMD inverter at output voltages of 0 and 5 V are higher than those of conventional CMOS inverters. The higher supply currents of the SCMD inverter at output voltages of 0 and 5 V are mainly due to the junction leakage current of the Schottky clamped junctions as shown in Figure 5-10. Figure 5-11 Voltage transfer curves and supply currents for SCMD and conventional CMOS inverters. (Wpjy[os=WN]viOS=12 pm)

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87 Figure 5-12 Voltage transfer curves of SCMD inverters for varying Schottky . clamp lengths. Figure 5-12 shows VTC curves for varying SCL. Due to the PMOS V-pH shift, when SCL is decreased to 1.2 pm, the inverter switching point is increased by ~ 80 mV. Based on these discussions and those from the previous section, SCL between the ii^ and n-well and that between the and p-substrate can be reduced to 1.6 pm without affecting the circuit and latchup characteristics and also transistor isolations.

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88 5.3.2 SCMD CMOS Inverter Chains 100-stage SCMD (SCL= 2.0 |im) and conventional CMOS inverter chains with NMOS Width= 1.6 |im and PMOS Width= 3.2 |iim have been implemented. The n-channel transistor width of the inverters is the mi ni m um allowed by the process. The guard band lengths along the polysilicon gate (GPL) are 1.2 |im for the SCMD NMOS transistor and 0.8 pm for the SCMD PMOS transistor. Figure 5-13 (a) shows the schematic and a micro-photograph of the inverter chain and delay extraction circuit. The chain for the SCMD and conventional CMOS inverters are enlarged and shown in Figure 5-13 (b) for a clear area comparison. By utilizing the SCMD structure, the inverter chain area (SCL= 2.0 pm or n‘*’-drain-to-p ‘'-drain spacing of 4.0 pm) has been reduced by ~ 22%. Figure 5-14 (a) shows output waveforms of the inverter chains. Figure 5-14 (b) shows plots of the inverter propagation delay (tj)) versus supply voltage. The plots for both types of inverters are almost identical. As discussed, the junction capacitance including the Schottky, p^-n and ri^-p junctions of the SCMD structure should be ~ 10% higher than those for the conventional junctions. This corresponds to a ~ 3% increase in the load capacitance for each stage in an inverter chain with a fan-out of one. As seen in Figure 5-14 (a), this has only small impact on the speed performance. 100-stage SCMD and conventional CMOS inverter chains have been implemented. By utilizing the SCMD structure, the inverter chain area

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89 IN • • • 100-Stage Inverter Chain 100-Stage Inverter Chain (a) OUT put Buffer Figure 5-13 (a) Circuit schematic and die photo for the SCMD CMOS inverter chain and propagation delay extraction circuit; (b) Enlarged photos of the SCMD and conventional CMOS inverter chains for clear area comparison.

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Propagation Delay, xq (ps) 90 (a) 2.0 3.0 4.0 5.0 6.0 Vdd (Volt) Figure 5-14 (a) Measured output waveforms of the SCMD and conventional CMOS circuits shown in Figure 5-13; (b) Inverter delays versus supply voltage for SCMD and conventional CMOS inverters.

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91 (SCL= 2.0 |xm or n‘‘'-drain-to-p "'-drain spacing of 4.0 pm) has been reduced by ~ 22% without any process modifications. The 2.0-pm SCL, 1.2-pm NMOS GPL and 0.8-pm PMOS GPL are a conservative design for SCMD CMOS inverters. Based on the study of SCL, SCL between the n"*" and n-well and that between the p"*" and p-substrate can be reduced to 1.6 pm without affecting the circuit and latchup characteristics and also transistor isolations. And based on the study of GPL in chapter 3, NMOS GPL can be reduced to 0.8 pm without affecting the transistor and latchup characteristics, and also junction leakage currents. Layout area of the SCMD inverter chain can be further reduced by using the 1.6-pm SCL, 0.8-pm NMOS GPL and 0.8-pm PMOS GPL instead of the 2.0-pm SCL, 1.2-pm NMOS GPL and 0.8-pm PMOS GPL. 5.4 Summary A Schottky diode clamped merged drain (SCMD) CMOS structure and a 100-stage SCMD CMOS inverter chain have been implemented in a foundry 0.8-pm Salicide CMOS process. Output I-V characteristics of SCMD NMOS and PMOS transistors are almost identical to those of conventional MOS transistors and transistor isolation characteristics are preserved. The current gains of parasitic n"''-drain/p-substrate/n-well and p"'"-drain/n-well/p-substrate bipolar transistors of the CMOS structure involved in latchup are significantly reduced. The reduced current gains enable a reduction of the n"'"-drainto-p '-drain spacing which reduces the area of the SCMD CMOS structure.

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92 An SCMD CMOS inverter (SCL= 1.6 |im) has a ~ 30% smaller footprint than a conventional CMOS inverter. This reduction should remain the same as the technology is scaled. Voltage transfer characteristics and propagation delays of SCMD CMOS inverters are almost identical to those of conventional CMOS inverters. A major concern for SCMD CMOS circuits is the junction leakage current, which increases the static power consumption. As transistors are scaled, because of the projected increases in drain-to-source and gate leakage currents [40-42], the Schottky barrier junction leakage may become a smaller portion of the overall leakage. However, with the transistor scaling, the channel doping will also increase, which will increase the Schottky barrier diode leakage current. More work is needed to examine these leakage issues and the applicability of the concept to deep sub-micrometer CMOS processes. For circuits dominated by dynamic power consumption, SCMD CMOS structures can be used in present technologies to reduce the area. By using Schottky clamped sources and by re-tuning the PMOS for a smaller SCL, it should be possible to further reduce the ;i‘''-to-p''’ spacing for an even greater area reduction.

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CHAPTER 6 SINGLE-POLE DOUBLE-THROW CMOS RF SWITCHES 6.1 Introduction Schottky clamped (SC) MOS transistors for RF switch applications have been demonstrated. The switch exhibits comparable RF characteristics to those of conventional NMOS switches. A single-pole single-throw (SPST) RF switch has also been implemented in a 0.5-(im CMOS process. It exhibits less than 0.8-dB insertion loss and more than 40-dB isolation for frequencies up to 1 GHz. These suggest that single-pole double-throw (SPDT) switches could be implemented in bulk CMOS technologies and also be integrated with other CMOS transceiver circuits using either Schottky clamped or conventional MOS transistors. In addition, single-pole double-throw (SPDT) CMOS RF switches fabricated using 0.35-|im CMOS transistors in a 0.18-|im CMOS process for 900MHz and 2.4-GHz wireless applications are presented. The switches exhibit usable insertion loss, isolation and power handling capability for a number of TDD wireless applications. The limitations and reliability issues associated with the switches implemented in bulk CMOS processes are also studied. The feasibility of using impedance transformation networks to reduce RF voltage swings at the input and output of RF switches and thus to increase the power 93

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94 handling capability is also examined. The measured output power 1-dB compression point was increased by 7 dB with less than 0.5 dB increase in insertion loss by using 30-Q impedance transformation networks. This demonstrates that it is feasible to use impedance transformation to increase the power handling capability of CMOS RF switches. 6.2 900-MHz 0.5-|im SPDT Switches Single-pole double-throw switches for 900-MHz wireless application were implemented in a 0.5-|im substrate (with an epitaxial layer) CMOS process using both conventional and Schottky clamped (SC) MOS transistors. The switches exhibit less than 0.8 dB insertion loss, over 40 dB isolation, and 17 dBm PidB at 928 MHz. These are the first CMOS switches to have usable insertion loss, isolation and Pi^b ^ number of 900-MHz wireless applications [16]. In addition, power handling capability of the switches has been carefully examined, and the results indicate that the switch can withstand the voltages corresponding to 20-dBm available power from the source (Pavs) ^ VSWR of 10:1 at the output. 6.2.1 Design of 0.5-pm SPDT RF Switches Figure 6-1 is a schematic of an SPDT NMOS RF T/R switch. This schematic is similar to the SPST RF switch presented in chapter 4. Transistors M^ and M 2 perform the main switching function, while the shunt transistors M 3

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95 ANT Figure 6-1 Circuit schematic of an SPDT RF switch. and M 4 are used to improve the isolation of the switch by grounding RF signals on the side which is turned off. This switch also contains bypass capacitors, Cgi and Cb 2 , which allow DC biasing of the TX and RX nodes of the switch. By applying the same DC voltage on the top plates of the b 5 T)ass capacitors, Cg^ and Cg 2 , as the DC voltage for TX and RX nodes, DC power consumption is made negligible. The gate bias resistances, Rgi> ^G 3 Rg 4 , are implemented using poly resistors. The value for the gate bias resistances is about 10 kH The purpose of the gate bias resistances is to improve DC bias isolation. If the gate bias resistors are not present, the fluctuations of Vgd and Vgs of the transistors due to the RF voltage swing at drain and source nodes of the transistors will be higher. These fluctuations not only

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96 affect the MOSFET channel resistance but also may result in excessive voltage drop across the gate dielectric and cause dielectric breakdown. Key figures of merit of a T/R switch are insertion loss and power handling capability measured by power 1-dB compression point (PidB)On-resistance of the transistor is one of the dominant factors determining insertion loss. Because of this, only n-channel MOSFETÂ’s are used in the design. The drain-to-body and source-to-body junction capacitances (Cdb and Csb) of and M 2 , and CbbÂ’s of M 3 and M 4 , and their associated parasitic resistances due to the conductive nature of silicon substrates are also critical factors determining insertion loss. Figure 6-2 shows the simulated insertion loss as a function of the width of Ml (Wjyii) in the SPDT switch. For a given bias condition, as the transistor width is increased, on-resistance decreases and insertion loss decreases. However, if the transistor width is increased excessively, as discussed earlier, the signal loss through capacitive coupling to the substrate becomes significant and insertion loss increases with the increasing width. For the bias conditions used to generate Figure 6-2, Mj should be ~ 0.6 to 0.8 mm wide to minimize insertion loss. This agrees well with the optimal width range estimated by equation (4.2) for a transistor. The width of shunt transistors M 3 and M 4 (W]y [3 and Wm 4 ) are chosen to be a half of W^j. According to simulations, the chosen Wm 3 and Wm 4 can improve the isolation of the switch by more than 10 dB with negligible impact on insertion loss.

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97 Figure 6-2 Effects of the transistor width on insertion loss of an SPDT RF switch. W]VQ= W]vi2= 2 X Wm 3 = 2 x Wjy [4 and ffequency= 928 MHz. Figure 6-3 is a schematic of the SPDT switch including important substrate resistances. Figure 6-4 shows the simulated insertion loss of the switch versus parasitic substrate resistances associated with the drain-to-body and source-to-body junction capacitances of Mj and M 2 at 928 MHz. As seen with a transistor by itself, there is a maximum insertion loss point at Rb(max) (4.5)). When Rg is very large or very close to zero, insertion loss is reduced. From the implementation point of view, as reported in the context of a bipolar LNA [43] , it is not easy to get large RgÂ’s in bulk silicon integrated circuits and also this depends on surrounding circuits and their substrate contacts.

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Insertion Loss (dB) 98 ANT Figure 6-3 Circuit schematic of an SPDT T/R switch including key substrate resistances (Rg). Figure 6-4 The effects of the transistor substrate resistances (resistances from S/D to ground) on insertion loss of an SPDT T/R switch at 928 MHz. Rb,M 3= 2 x Rb,mi= 2 x Rb,M2

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99 Because of this, lowering the resistance is the preferred approach. In addition, reducing the substrate resistance also improves the latchup immunity. Figure 6-3 also includes a list of the measured values of the key substrate resistances (Rbmi> ^B,M4)These resistances were measimed using a test switch implemented using the same technique reported in Colvin et al. [43]. The substrate resistances of 14.2 (Rb,M1= ^B,M2) 20.6 ^ (^B,M3= Rb,M 4) sufficiently low to significantly reduce the substrate losses. The low substrate resistances are achieved by fully surrounding the transistors with large area substrate contacts and filling in any open spaces with substrate contacts. Figure 6-5 is a micro-photograph of the SPDT switch, which integrates the transistors, resistors and capacitors. The total Figure 6-5 Micro-photograph of the 0.5-pm 900-MHz SPDT NMOS RF switch.

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100 chip area is 560 pm x 560 pm. The capacitors are implemented using an inexpensive polysilicon-to-n-well capacitor structure [44]. The substrate contacts occupy approximately 36% of the chip area which is about 0.1 mm^. 6.2.2 DC Bias for RF Switches TX and RX nodes, or the drain nodes of Mj and M 2 , are DC biased to 3 V. This reverse biases the source/drain-to-body junctions which reduces the junction capacitances and RF signal coupled to the substrate and thus decreases insertion loss. As discussed in section 4.3.3, the 3-V DC bias for TX and RX nodes also improves the power handling capability measured by PidBThe DC gate voltages for Mj and M 4 are set to 6 V, and those for M 2 and M 3 are set to 2 V to set the switch in the transmit mode. From (4.6), the maximum gate-to-drain voltage (Vg^) of M 3 is Vg Vd= 1.1 V 0.3 V = 0.8 V which is higher than the threshold voltage (V^h) of the 0.5-pm transistor, and the transistor, M 3 , starts to turn on. This unintentionally tumed-on transistor clips the output waveform and makes the output power of the switch to compress. However, as discussed and will be shown by measurements, the RF power handling capability for the 3-V source/drain DC bias case is significantly higher than that for the 0-V DC bias case.

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101 6.2.3 Measured Results of Conventional MOSFET Switches Figure 6-6 shows the measured insertion^ loss versus drain/source-tobody bias (V^b, Vsb) of when the gate control voltage (V^trl) i® 3.3 V. The measurements were made in an SOIC-like test package with an exposed paddle. The exposed paddle was directly soldered to board ground. The on-chip ground is connected to board ground using five down bonds to reduce the inductance. When the gate-to-drain/source voltages (Vqb and Vqs) of Mj are 3.3 V, on-resistance is the lowest. However, insertion loss is not the minimum because the drain-to-body and source-to-body capacitances (Cj)b Figure 6-6 Measured insertion loss vs. drain/source-to-body bias (Vqb> when VctbrIs 3.3 V and Vqtrl i® ^

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102 at their maximum. This results in lower impedances to the substrate and higher losses in the substrate. Raising Vdb and VgB levels increases the reverse bias of the junctions, which decreases the capacitances. Despite the accompanying decrease in V(jg and increase of the on-resistance, this capacitance reduction lowers insertion loss. If Vdb and VgB are further increased, eventually the decrease of Vqs results in a sharp increase of insertion loss. These measurements indicate that at 1.0 ~ 1.2 V Vdb and VgB, insertion loss IS mimmized for the 3.3-V VctrlAs discussed, applying positive Vdb and VgB also increases Pi^bFigure 6-7 shows the measured insertion loss and isolation of switches using conventional MOS transistors. Insertion loss is less than 0.8 dB, and isolation IS more than 40 dB for operating frequencies up to 1 GHz at Vctrl or Vgb of 6.0 V, Vctrl of 2 V, and drain/source-to-body reverse bias (Vdb and VgB) of 3.0 V. The insertion loss and isolation at Vctrl= 3.3 V and Vdb= VgB= 1.2 V are ~ 0.2 dB higher and 2 dB lower than those at Vctrl= 6 0 V and ^DBVgB3.0 V, respectively. The 6.0-V Vctrl oan be attained by using a voltage doubler from a circuit operating at 3 V. Figure 6-8 shows the power measurement results of the switch in both onand off-states at 928 MHz. Table 6-1 summarizes the switch performance. When VcTRL= 6.0 V, Vctrl = 2.0 V and the switch is on, is 17.2 dBm. This corresponds to an TX and ANT voltage amplitudes of 2.8 and 2.3 V with a 50-G output load. As discussed earlier, the compression is caused by turning

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103 Frequency (MHz) w o su o' 3 s DO Figure 6-7 Measured insertion loss and isolation for the 0.5-|im SPDT RF switch. M 3 on by the applied RF input voltage. Output third order intercept point (IP 3 ) was measured using a two-tone test. The frequencies of the two-tones (fj and f 2 ) are 928 MHz and 927 MHz, and the third order harmonics are measured at 2 fj-f 2 and 2 f 2 -f^ which are 929 MHz and 926 MHz, respectively. Because the mechanisms responsible for IP 3 and Pijb ^^"6 different, this also makes the difference between PidB IP 3 to be around 20 dB instead of the theoretical ~ 10 dB difference [15]. Measured IP 3 is 38.2 dBm which is excellent. The higher power handling capability of the 6.0-V Vctrl case compared to the 3.3-V Vctrl f^ct that it takes a larger input swing to

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104 Figure 6-8 The output 1-dB compression point measurement for both onand off-states, and IP 3 measurement for on-state at 928 MHz when VcTRL” V CTRL“ ^ and Vj)g= Vgg= 3.0 V for switches using conventional MOS transistors. Table 6-1 Summary the 0.5-pm SPDT T/R Switch at 928 MHz Bias Conditions VcTRL= 6-0 V VcTRL= 2.0 V Vdb»Vsb=2.0 V VcTRL= 3.3 V VcTRL= 0-0 V Vdb,Vsb=1.2V Insertion Loss 0.73 dB 0.97 dB Isolation 41.8 dB 40.1 dB PidB (ON) 17.2 dBm 11.5 dBm IPidB (OFF) 17.1 dBm 13.9 dBm IP 3 38.2 dBm 33.3 dBm

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105 forward bias the source/drsdn-to-body junctions and to turn on M 3 . During this set of measurements, a maximum RF input voltage amplitude of 4.2 V or a peak voltage of 7.2 V has been applied without damaging the switch. fi. 2.4 Measured Results of SC MOSFET Switches Figure 6-9 shows the measured insertion loss and isolation of switches using Schottky clamped (SC) MOS transistors. The measurements were also made in an SOIC-like test package with an exposed paddle. Insertion loss is less than 0.8 dB, and isolation is more than 40 dB for operating frequencies up 46.0 44.0 42.0 40.0 5 T o w 38.0 o 36.0 B 34.0 32.0 30.0 800.0 840.0 880.0 920.0 960.0 1000.0 Frequency (MHz) Figure 6-9 Measured insertion loss and isolation for SPDT switches using 0.5-|im SC-MOS transistors.

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106 to 928 MHz at a Vctrl or a Vqb of 6.0 V, and a drain/source-to-body reverse bias (Vdb and Vs^) of 3.0 V. Figure 6-10 shows the power measurement results of the switch in both onand off-states at 928 MHz. Table 6-2 summarizes the switch performance and compares the performance to that of the SPOT switch using conventional MOS transistors. The insertion loss of switches using SC-MOS transistors is about 0.1 dB higher than that of switches using conventional transistors. This is mainly attributed to the slightly increased layout area of SC junctions. Isolation of both switches is similar. When Vctrl^ ^ ^CTRL “ ^.0 V and the switch is on, PidB is 18.2 dBm. This corresponds to an TX and ANT voltage amplitudes of 3.2 and 2.6 V with a 50-Q output load. The compression is, once again, mainly caused by the applied RF input voltage turning on M3. In addition. Verm] of 2.0 V is chosen to reduce the maximum voltage across the gate oxide layer of transistors M2 and M3 when Mj and M4 are turned on. The measured IP3 is 37.2 dBm which is similar to the SPDT RF switch using conventional MOS transistors. These demonstrate that switches using SC-MOS transistors exhibit similar RF characteristics to those of switches using conventional MOS transistors. fi.2.5 Reliability Issues of 0.5-um MOSFET Switches The reliability of switches using MOS transistors is crucial. One of the concerns is the minority carrier injection due to the unwanted forward biased

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107 Figure 6-10 The output IdB compression point measurement for both on and off states, and IP 3 measurement for on state when Vctrl= Vctrl= 2.0 V and Vdb= Vsb= 3.0 V at 928 MHz for 0.5-pm switches using SC-MOS transistors. Table 6-2 O.S-pm SPDT RF Switch Characteristics Comparison at 928 MHz Conventional RF Switch SC-MOS RF Switch Insertion Loss 0.7 dB 0.8 dB Isolation 41.3dB 40.6 dB PidB (ON) 17.2 dBm 18.2 dBm IP 3 38.2 dBm 37.2 dBm

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108 junctions mainly caused by output mismatches. Figure 6-11 shows the Gummel plot of lateral n'^-drain/p-substrate/n'^-source parasitic bipolar transistors (TX node/substrate/ANT node) for SPOT RF switches using both conventional and SC-MOS transistors. The ANT node serves as the collector for bipolar transistors. At 0.97-V Vbe, the collector current for the switch using conventional transistors is ~ 90 mA while it is only 1.4 mA for the switch using SCMOS transistors. More electrons or minority carriers have been injected into the substrate in the switch using conventional transistors and these injected minority carriers can increase the susceptibility to latchup for nearby CMOS Figure 6-11 Gummel plots of n’^-drain(TX)/p-substrate/n‘^-source(ANT) parasitic npn bipolar transistors for 0.5-|im switches using both conventional and SC-NMOS transistors.

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109 circuits. As discussed, the use of SC MOS transistors to implement SPDT RF switches has almost negligible effect on the RF performance compared to those of SPDT switches using conventional MOS transistors, while latchup susceptibility of CMOS circuits integrated with the RF switches can be radically reduced. This suggests that it is feasible to use SC MOS transistors to fabricate RF switches in bulk CMOS technologies to decrease the susceptibility to latchup for CMOS circuits. Another reliability issue is the DC voltage across the gate oxide. The 6_0-V DC gate voltage is acceptable in the 3.3-V 0.5-|xm CMOS process because when the transistors are on, the DC voltage across the gate oxide is 3.0 V due to the 3.0-V Vsb and Vdb. and the formation of an inversion layer in the channel region. When the transistors are off (Vgd= Vgs= ^ = 2.0 V), the maximum DC voltage across the gate oxide is 2.0 V. Because of these, the DC voltage across the gate oxide does not exceed 3.0 V. Another reliability issue for an RF T/R switch is the RF input voltage in combination with the output mismatch. The output node of an RF T/R switch is connected to an antenna, and the impedance looking into the antenna varies depending on structures near the antenna. The worst case mismatch occurs, though infrequent, when the load is an open, which results in total reflection of the input RF signal. In this case, if the impedance of the input source is 50 ^ the RF output voltage will be the maximum, and ~ 2X the voltage of that when the load is 50 For applications with the maximum transmit power of 10 dBm, the output voltage amplitude with a 50-Q load is 1 V.

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110 Thus, the maximum RF voltage amplitude at the output will be 2 V (peak voltage of 5 V) when the output load is an open, and the switch will operate in the safe voltage range. Simulations have been used to estimate the maximum power handling capability of the switch assuming that the maximum allowable voltage across the 9.5-nm gate oxide of the 0.5-|im transistor limited by the reliability requirement is about 4.0 V. The 4.0-V limit is more conservative than that suggested by Hu [45]. On top of this, the stress is AC rather than DC, which makes the 4.0-V limit even more conservative. Figure 6-12 shows simulated Vgd of Ml and Vdg of M2 and M3 when Mi is turned on, and M2 and M3 are turned off. The terminals shown in Figure 6-12 are chosen because they are exposed to the largest voltage drops. The available input power is 16.7 dBm (e.g. output power is 15.6 dBm= 16.7 dBm IL power compression with a 50Q. load) and the output load is an open. The corresponding peak voltage at TX is 7.35 V. Because significant part of the RF voltage between the source/drain of Ml to ground is dropped across Rgi, the maximum Vgd of Mi is about 3.2 V, which should not stress the gate oxide. In addition, the 2.0-V Vctrl sets the maximum Vqg of M2 and M3 to ~ 4.0 V which should be acceptable from the reliability point of view. The 2.0-V Vq^hl keeps the transistors within the safe voltage range for the 3.3-V CMOS process at the input power of 16.7 dBm even when the output load is an open. The 2.0-V Vctrl degrades PidB only by 1 dB in comparison with 0-V Vctrl case. The 1-dB PidB degradation is due to the RF signal loss through

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Ill Figure 6-12 Simulated voltages across the gate oxide layer of Mj, M 2 and M 3 , and Vjjs of M 2 and M 3 when the switch is on and the output load is an open. The available input power is 16.7 dBm, and the maximum voltage across the gate oxide is 4.0 V. M 3 which is turned on instead of PidB being limited by the forward biasing of the source/drainto-body junction diodes. Figure 6-12 also shows the drain-tosource voltages for transistors M 2 and M 3 . The maximum Vos is about 5.0 V which is significantly lower than the 10-V transistor breakdown voltage (BVdss)This should not pose a reliability problem since M 2 and M 3 are turned off during the high Vps portion of a cycle. This switch has been designed to operate within the safe voltage range at the input power of 16.7 dBm with an open output load, Vctrl= b.O V, and

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112 VgxRL= 2.0 V. However, the switches have also been characterized when the available output power (Pavs) much higher than 16.7 dBm. The switch maintained the same insertion loss and isolation at a 10-dBm output power after a 26.5-dBm Pays stress for one minute. At the output Pays of 27.5 dBm, the gate oxide of transistors M 2 and M 3 were ruptured. When the output load is open, this switch should be able to handle Pays of 20 dBm without rupturing the gate oxide layer. These suggest that the switch can be operated all the way up to the PidB point without being limited by a reliability problem. 6.2.6 Conclusion Single-pole double-throw transmit/receive switches using both conventional and Schottky clamped MOS transistors have been presented. The switches were fabricated in a foundry 0.5-)im CMOS process. They exhibit a 0.8-dB insertion loss, a 40-dB isolation, and a 17-dBm PidB ot 928 MHz. The insertion loss of the 0.5-|im switches is comparable to several transmit/receive switches implemented in GaAs technologies for 900-MHz applications while the isolation of this switch is about 15 dB better than those of GaAs switches. The PidB of this switch is about 15 dB lower than that of GaAs switches [2], [ 6 ] , [46] . The effects of substrate resistances and source/drain-to-body capacitances associated with MOS transistors on insertion loss of RF switches have been shown by simulations, analyses and measurements. The substrate resistance and source/drain-to-body capacitance must be lowered to decrease

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113 insertion loss. The low insertion loss of the CMOS transmit/receive switch is achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by DC biasing the TX and RX nodes which decreased the capacitance while increasing the power 1-dB compression point. The switch has adequate insertion loss, isolation, Pi^b and IP 3 for a number of 900-MHz ISM band applications requiring moderate maximum transmit power. The switch should be able to handle 17 dBm output power with a sufficient reliability margin even with the output open. Using Schottky clamped NMOS transistors reduce the minority carrier injection from the switch, and when the switch is integrated with other CMOS circuits, susceptibility to latchup for the CMOS circuits should be reduced. Because the switch is implemented in a foundry CMOS process, this work suggests that a T/R switch could be integrated with other transceiver circuits. 6.3 900-MHz and 2.4-GHz 0.35-|iim SPDT Switches It has been shown that it is feasible to implement RF transmit/receive switches operating at 900 MHz in 0.5-pm CMOS technologies using p"*" substrates. It has also been shown that RF components and circuits implemented on p' substrates exhibit better characteristics than those on p'*' substrates [47] . However, using a p‘ substrate may increase insertion loss of integrated RF switches due to increased substrate resistances. To study the impact of p' substrate on insertion loss as well as the feasibility of CMOS T/R switches for

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114 operating frequencies higher than 900 MHz, SPDT RF switches were fabricated using 3.3-V, 0.35-|ini MOS transistors in a foundry 0.18-)im CMOS process utilizing p' substrates. Using 0.35-|a.m transistors in the 0.18-|xm CMOS process reduces the source/drain-to-body capacitances because of the more aggressive design rules compared to the conventional 0.35-pm CMOS process, which in turn decreases insertion loss. Substrate contacts have been carefully laid out to ensiu*e the impact of p' substrates on insertion loss is reduced. Through these, a 900-MHz switch with an insertion loss of 0.5 dB and isolation of 39 dB at 928 MHz and another switch with a 0.8-dB insertion loss and 24-dB isolation at 2.4 GHz have been demonstrated. Owing to the lower onresistances and substrate resistances, the insertion loss for 0.35-|im 900-MHz switches is much lower than that of the 0.5-|im SPDT RF switch and the maximum operating frequency has been increased to 2.5 GHz. These switches also exhibit a 17-dBm PidB6.3.1 Design of 0.35-|xm SPDT RF Switches Figure 6-13 is a schematic of an SPDT RF T/R switch. This schematic is similar to the switch implemented in a 0.5-|im CMOS process [16]. The DC bias of TX and RX nodes (see Figure 6-13) has been set to 3.0 V, and Vctrl and Vctrl ^ 2.0 V to perform the switching function. The width of transistors Mj and M 2 is a crucial factor determining insertion loss as discussed in the previous section. Under a given bias condition, as the transistor

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115 Rq1 ^G2 gB,Mi= gB,M2= |-0 § for 900-MHz switch "B,M3"B,M4gB,Mi= gB,M2 for 2.4-GHz switch "B,M3"B,M4Figure 6-13 Circuit schematic of an SPDT T/R switch including key substrate resistances. (Rg: substrate resistance) width is increased, on-resistance decreases and insertion loss decreases. However, if the transistor width is increased excessively, the signal loss through capacitive coupling to the substrate becomes significant and insertion loss increases with the increasing width [16], [48]. This is especially important for high frequency applications. Simulations have been used to estimate the optimal width of Ml and M 2 for low insertion loss. The minimum insertion loss at 900 MHz and 2.4 GHz is achieved when the width of Mi is about 660-pm and 300-pm, respectively.

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116 Figure 6-13 also includes critical substrate resistances [36]. As mentioned earlier, substrate resistances were minimized. To accomplish this, the transistors are laid out using multiple-fingered structures and also the transistors are broken into multiple groups. Each group of the transistor is fully surrounded by large area substrate contacts to minimize the series resistance thus maximizing the quality factor of Cdb and CsbIn addition, any open spaces are filled with substrate contacts. This is expected to be especially important for NMOS transistors fabricated on p' substrates since the low resistance shunting path through the p* substrate is not available. Figure 613 also includes a list of measiired values of the key substrate resistances. The measured substrate resistances of 5.0 Q for Rb,mi= I^BM2 nnd 8.5 Q for I^B,M3= I^B,M4 lor the 900-MHz switch and the measured substrate resistances of 8.2 Q for Rb,mi= I^B,M2 nnd 20.0 H for Rb,M3= I^B,M4 Io^ 2.4-GHz switch are sufficiently low to make the substrate loss small. The resistances are measured using a test circuit identical to the switch except that the source/drainto-body junctions are replaced with p^ substrate contacts. Figures 6-14 (a) and (b) are micro-photographs of the 0.35-|j,m 900-MHz and 2.4-GHz SPDT switches, respectively, which integrate the transistors, resistors and capacitors. The capacitors are implemented using an inexpensive polysilicon-to-n-well 3.3-V MOS capacitor structure [44]. The purpose of capacitors Cbi and Cb 2 is, once again, to enable DC biasing of the source/drain nodes of the transistors which reverse biases the source/drain-to-body

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117 Figure 6-14 (a) Micro-photograph of the 0.35-}iin 900-MHz SPDT switch; (b) Micro-photograph of the 0.35-|im 2.4-GHz SPDT switch.

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118 junctions of M2, M3 and M4. This decreases the capacitances and RF signal coupled to the substrate, and thus reduces insertion loss. The DC bias for TX and RX nodes also improves PjdB because it increases the required voltage swing to forward bias the source/drain-to-body junctions of the transistors than the 0-V DC bias case. The gate bias resistors, Rqi, Rg 2> ^G4> implemented using poly resistors. The value for the gate bias resistance is ~ 10 kfl The chip area is 531 x 531 pm^. The substrate contacts occupy approximately 63% and 65% of the chip area for the 900-MHz and 2.4-GHz switches, respectively. 6.3.2 Measured Results of 900-MHz Switches Figure 6-15 shows the measured insertion loss and isolation of the 900MHz switch. The measurements were made in an SOIC-like test package with an exposed paddle. Insertion loss is about 0.5 dB, and isolation is more than 39 dB for operating frequencies up to 1 GHz at Vctrl ^GB= drain/source-to-body reverse bias (Vj^g and V3 b)= 3.0 V. Figure 6-16 shows the power measurement results of the switch at 928 MHz. Table 6-3 summarizes the switch performance at 928 MHz and compares the performance to that of a 0.5-pm SPDT switch under the same bias condition. Both switches exhibit similar characteristics except that the insertion loss of the 0.35-pm switch is reduced. The 0.5-dB insertion loss is competitive to that of a number of GaAs switches at 900-MHz [6], [46]. The reduction on insertion loss is attributed to

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119 QQ m (/> c o r 0 ) (A C Frequency (MHz) Figure 6-15 Measured insertion loss and isolation of the 900-MHz SPDT T/R switch. the lower on-resistances and substrate resistances than those of the 0.5-|ini switch. When V^trl^ ^ and Vctrl= 2.0 V, TX and ANT nodes are connected. PidB is 17.7 dBm, which is similar for both the 0.35-|im and 0.5-|j.m switches. The 3-V DC bias for TX and RX nodes also improves Pi^b by around 8.5 dB because it increases the required voltage swing to forward bias the source/drain-to-body junctions of the transistors than the 0-V TX and RX DC bias case. IP 3 was measured using a two-tone test. The measured IP 3 is 40.1 dBm. The mechanisms determining IP 3 and Pi^b different. IP 3 is measured at low input power levels and is determined by the non-linearity of the

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120 Figure 6-16 The output 1-dB compression point measurement and IP 3 measurement when VcTRL= 6-0 V, Vctrl= 2.0 V and Vdb= Vsg= 3.0 V at 928 MHz. Table 6-3 0.35-pm and 0.5-pm 900-MHz SPDT Switch Characteristics Comparison at 928 MHz A 0.35-pm SPDT Switch A 0.5-|xm SPDT Switch Insertion Loss 0.5 dB 0.7 dB Isolation 39.5 dB 41.3 dB PidB 17.7 dBm 17.2 dBm IP 3 40.1 dBm 38.2 dBm

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121 reverse biased source/drain-to-body junctions, while PidB measured at high input power levels and is determined by the turning on of the shunt transistor (M 3 ). Because of this, the difference between PidB IP 3 is ~ 20 dB instead of the theoretical ~10 dB difference [15]. 6.3.3 Measured Results of 2.4-GHz Switches Figure 6-17 shows the measured insertion loss and isolation of the 2.4GHz switch. The measurements were also made in an SOIC-like test package with an exposed paddle. Insertion loss is about 0.8 dB, and isolation is more Figure 6-17 Measured insertion loss and isolation of the 2.4-GHz SPDT T/R switch.

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122 than 24 dB for operating frequencies up to 2.4 GHz at Vctrl= X and Vjjg and Vs 3 = 3.0 V. Figure 6-18 shows the power measurement results of the switch in on-states at 2.4 GHz. Table 6-4 summarizes the switch performance at 0.9, 1.8 and 2.4 GHz. The switch exhibits 0.8 dB insertion loss for Figure 6-18 The output 1-dB compression point measurement and IP 3 measurement for the 0.35-pm 2.4-GHz switch when Vqtrl= VcTRL~ ^ and Vj)g= V 3 g= 3.0 V at 2.4 GHz. Table 6-4 Summary of 2.4-GHz SPDT Switch Frequency 900 MHz 1.8 GHz 2.4 GHz Insertion Loss 0.7 dB 0.7 dB 0.8 dB Isolation 34.0 dB 27.4 dB 24.4 dB

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123 frequencies up to 2.5 GHz. The insertion loss is comparable to those of the NMOS SPDT T/R switch [16] and a number of GaAs SPDT T/R switches [2], [ 6 ], [46] at their respective operating frequencies. This is the first SPDT silicon MOSFET switch to have usable insertion loss for applications from DC up to 2.5 GHz. When the switch is set to the transmit mode (Vctrl= ^ VcTRL = 2.0 V), PldB is 17.4 dBm. The compression is, once again, caused by the applied RF input voltage turning on M 3 . Vctrl 2.0 V was chosen to reduce the maximum voltage across the gate oxide layer of transistors M 2 and M 3 when Ml and M 4 are turned on. IP 3 was measured using a two-tone test. The frequencies of the twotones (fi and f 2 ) are 2400 MHz and 2399 MHz, and the third order harmonics are measured at 2 fi-f 2 and 2 f 2 -fi which are 2401 MHz and 2398 MHz, respectively. The measured IP 3 is 31.3 dBm. The difference between PidB IP 3 is around 15 dB. 6.3.4 Reliability Issues of 0.35-fxm MOSFET Switches Similar to the 0.5-|im switches, the 6.0-V DC gate voltage is acceptable for the 3.3-V 0.35-|im MOS transistors because when the transistors are on, the DC voltage across the gate oxide is 3.0 V due to the 3.0-V Vsb and V^b, and the formation of an inversion layer in the channel region. When the transistors are off (Vqd= Vqs= -1.0 V and Vqb = 2.0 V), the maximum DC voltage across the gate oxide is 2.0 V. Because of these, the DC voltage across the gate

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124 oxide does not exceed 3.0 V. However, the more significant reliability issue is still the large RF input voltage in combination with output mismatches. The worst case mismatch, though infrequent, occurs when the load is an open, which results in total reflection of the input RF signal and makes the output RF voltage 2X the voltage when the output load is 50 D. At the maximum transmit power of 17.4 dBm for the 2.4-GHz switch, the peak voltage seen by the switch is 2.9 V with a 50-Q output load. Thus, when the output load is changed to an open, the maximum RF voltage amplitude seen by the switch will be ~ 5.8 V. Because the RF voltage is divided by Cq£>, Cqs and Cqb of the transistors, the maximum voltage across the gate oxide is ~ 4.8 V. This voltage should be sufficiently low to prevent the catastrophic failure of the switch due to the breakdown of the 7-nm gate oxide layer. As a matter of fact, when the switches are stressed with a 20-dBm Pays with the output open for one minute, no degradation of the switch characteristics has been observed. In addition, the switches have been stressed at a 26-dBm Pays with a 50-Q output load for one hour. Once again, the switches maintained the same insertion loss and isolation after the stress. These suggest that the switch can be operated all the way up to Pi^b point without being limited by a reliability problem. Lastly, the switch has adequate insertion loss, isolation, Pi^b ond IP 3 for a number of applications up to 2.5 GHz.

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125 6.4 Impedance Transformation for High Power RF Switches 6.4.1 Design of Impedance Transformation Networks The requirement for power handling capability of a T/R switch is 30 dBm for GSM, 20 dBm for CT3 and 10 dBm for CT2 [12]. There also exists numerous 900 MHz ISM band applications where 10 dBm is sufficient. The output power 1-dB compression point for the switches presented in the previous sections is about 17 dBm which is suitable for a number of 900-MHz ISM band applications. However, the PidB is lower than the 20-dBm requirement for CT3 applications. In order to deliver 20 dBm of sinusoidal power to a 50-£l antenna, the peak-to-peak voltage swing at the antenna must be about 6.3 V. This voltage swing is higher that the voltage swing at PidB point of the CMOS SPDT switches. A way to solve this problem is inserting an impedance transformation network between the antenna and switch to transform the 50-Q impedance of the antenna to approximately — rseen by the T/R (6.3/(2X)) switch so that a voltage amplitude of X at the switch delivers 20 dBm of power to the antenna, where X is the maximum voltage amplitude that could be tolerated by the T/R switch without signal distortion. As discussed, for the current design, the signal distortion is limited by unintentionally turning on a shunt transistor, M 3 . As described in section 6.2.2 and estimated by (4.6), the shunt transistor M 3 will start to turn on at an RF input voltage amplitude of 2.7 V under

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126 the given bias condition of SPDT switches presented in this chapter. This unintentionally turned-on transistor clips the output waveform and makes the output power of the switch to compress. In order to deliver 20 dBm of output power without signal distortions, a 2.5-V amplitude of RF voltage is used to determine the transformed source and load impedances seen by the transistors in the switch. For the desired 2.5-V RF voltage amplitude at the output of the switch, the load impedance seen by the transistor needs to be reduced to about 30 Q and this can be done by using a shunt C-series L network or a shunt L-series C network as shown in Figure 6-19. The shunt C-series L network is the preferred approach due to the fact that bond wire and package lead inductances are present in a packaged switch and they can be used as part of the impedance network. In addition, no DC block capacitors are required in the shunt C-series L network as opposed to the shunt L-series C network for DC biasing the switch. In order to transform the 50-Q source and load impedances down to 30 Q by using the shunt C-series L network, the capacitive susceptance component and the inductive reactance component are 0.8 and 0.5, respectively (see Figure 6-19). At 900 MHz, they correspond to 2.8 pF of capacitance and 4.4 nH of inductance. The use of impedance transformation networks increases the insertion loss of the switch due to the extra series resistances of the capacitors and inductors used in the network, and due to the reduced source/load impedances seen by the switch. Thus, high quality factor (Q) inductors and capacitors are needed for the network to minimize the extra insertion loss introduced by the

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127 Figure 6-19 The ZY smith chart and the possible 30-Q impedance transformation networks for switches.

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128 impedance transformation network. Due to the fact that integrated inductors have low Q at 1 GHz [49-50], discrete off-chip inductors, and bond wire and package lead inductances are more suitable for the impedance transformation network. Since discrete off-chip inductors are needed, the capacitor in the impedance transformation network will also need to be a discrete off-chip component. Reducing the soiu*ce/load impedances can reduce the voltage amplitude seen by the transistors in the switch. However, if the source/load impedance is excessively transformed to a low value which is comparable to the on-resistance of the transistors, insertion loss can be greatly increased. For example. the S 21 for a simple resistive network can be shown as 2 Rq + R where Rq is the source/load impedance and R is the resistance of the network (see Appendix). If R= 5 a and Rq= 50 Q, IL is 0.4 dB and the difference between the Pavs and Pl is only 0.4 dB. However, if Rq is transformed to 5 Q to increase the power handling capability of a switch, insertion loss will become 3.5 dB. This means to achieve the same output power, the input RF voltage amplitude must be increased. This increased input RF voltage amplitude can turn on the shunt transistor, M 3 , at a lower output power level than the case when the source/load impedances are moderately transformed. More importantly, the input RF voltage is proportional to ^ . This ratio increases to when Aix(\ “I" IV Rq= R from ~ V 2 when Rq» R. The relation between the transformed source/

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129 Figure 6-20 Two-port network of a series resistance, R. load impedances and the power handling capability of the switch can be analyzed by using the simplified two port network shown in Figure 6-20. For switches with source/load impedance transformation networks, the voltage amplitude at node D (see Figure 6-20) is targeted at X to avoid signal distortions, which is about 2.5 V for the current design of the switch. For the two port network shown in Figure 6-20, the power delivered to the load (Pl) is 2R 0 (6.1) and insertion loss in dB can be obtained from 1/ 1 S 21 1 ^(see Appendix) IL = 20 X log 2Rq + R 2R. (6.2) and power available from the source (Pays) shown as AYS 8Rr 2Rq + R Rq + R xZ = IN 1-|S 11 (6.3)

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130 Pin = 2.(Ro^R) = 2R^ (see Appendix). Pavs> insertion loss are plotted in Figure 6-21 against the transformed source/load impedances (Rq)R of 5 Q is used to generate this plot. As shown in Figure 6-21, when Rq decreases, Pl increases and insertion loss also increases. However, if Rq is transformed to be greater than R (5 in this case), Pl decreases even though Pavs increased. This is due to the sharp increase of insertion loss and thus degrading the power handling capability of the network. In this analysis, the 22.0-dBm maximum Pl can be achieve when Figure 6-21 Pavs> insertion loss versus the transformed source/load impedances (Rq) for the two port network shown in Figure 6-20 with a 5-Q R.

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131 Rq= R= 5 a (IL= 3.5 dB) with a Pays of 25.5 dBm. However, the 3.5 dB insertion loss is too high to be useful and the power handling capability of the network is degraded. Simulations and measurements of SPDT RF switches have also been done to illustrate these and will be presented in the proceeding section. 6.4.2 Experimental Results and Discussion Figure 6-22 shows the block diagram of the 0.35-pm 900-MHz RF switch including impedance transformation networks in a 50-Q system. The switch is represented as a two port network. Rs and Rl are 50-Q source and load impedances and Zs and Zl are the transformed source and load impedances seen by the switch. LgÂ’s and CpÂ’s are discrete off-chip components in this Input Impedance Transformation Network Output Impedance Transformation Network Rl Rg=RL=50Q and Zs=Zi_ Figure 6-22 Block diagram of an RF switch with impedance transformation networks.

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132 configuration. For simplicity, the bond wire and package lead inductances which are about 2.0 to 2.5 nH are included as part of LsÂ’s. As mentioned, in order to transform the 50-Q Rg and Rl to 30-Q Zg and Zl at 900 MHz, the required Cp is 2.8 pF and Lg is 4.4 nH as shown in Figure 6-19. However, due to the availability of discrete off-chip capacitors, 2.7 pF capacitors are used for Cp instead of 2.8 pF. This introduces slight mis-tuning of Zg and Zl. In addition, the parasitic inductance and capacitance of the SMA connectors used in the switch circuit board to connect RF cables need to be taken into account as part of the impedance transformation network. However, for RF switch applications with integrated impedance transformation networks, SMA connectors are not required and the extra parasitics components introduced by SMA connectors can be ignored. An SMA connector can be modeled with a series inductor and a shunt capacitor as shown in Figure 6-23. The parasitic series inductance and shunt capacitance of SMA connectors are extracted by measurements at 900 MHz. The series inductance (Lg|^) is about 2.2 to 3.2 nH and the shunt capacitance (Csma) is about 0.8 to 1.2 pF. The 1-nH variation of LgMA is mainly attributed to the length difference of the center conductor in the SMA connector used in the measurement. In order to reduce the impact of Lgj^, the center conductor of SMA connectors used for the RF switch boards in the measurement has been cut to the shortest possible length to reduce the inductance.

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133 Lsma= 2.2 nH CsMA= 1 -0 PF Ls= 5.3 nH Cp= 2.8 pF Figure 6-23 The ZY smith chart and the impedance transformation network targeting 30-Q Zs and Zl for RF switches including the parasitics associated with the SMA connectors.

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134 In order to obtained Zs and Zl of 30 Q including the parasitics of SMA connectors, a 5.3-nH Ls and a 2.8-pF Cp is needed as shown in Figure 6-23. A 3.3-nH off-chip inductor (Lsq) in series with the bond wire and package lead inductances and a 2.7-pF off-chip capacitor (Cp) is used for actual implementation. The choice of Lgo is about 0.4 nH higher than the value needed to transform the Zg and Zl to 30 Q. One of the reasons for this is due to the availability of off-chip discrete inductors and another reason for the extra 0.4-nH Lgo is to compensate the effect of the ~ 0.7-pF shunt CopÂ’s of and M 3 at the input and the shunt CggÂ’s of and M 2 at the output of the 0.35-p.m RF switch. Figure 6-24 shows the measured insertion loss and isolation for the 0.35-pm RF switch with 30 Q impedance transformation networks. In this switch, the DC bias condition is the same as the RF switches presented previously in this chapter. The measured insertion loss is less than 1 dB and isolation is more than 35 dB for frequencies between 860 MHz and 1 GHz. At 928 MHz, the measured insertion loss is 0.97 dB and isolation is 35.4 dB. Figure 6 25 shows the power measurement of the same switch. When Vctrl= V and Vctrl = 2.0 V, TX and ANT nodes are connected. PidB is 24.3 dBm and IP i^b ( input referred Pi^b) is 26.3 dBm, which is much higher than both the 0.35pm and 0.5-pm switches without impedance transformation networks. IP 3 was measured using a two-tone test. The measured IP 3 is 37.7 dBm and IIP 3 (input referred IP 3 ) is 38.7 dBm. The use of impedance transformation

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135 Figure 6-24 Measured insertion loss and isolation for the 0.35-|ini RF switch with 30-Q Zs and Zl impedance transformation networks. networks has greatly increased the Pijb point from 17.7 dBm to 24.3 dBm for the 900-MHz, 0.35-|im switch with less than 0.5 dB increase on insertion loss. This shows that it is feasible to use impedance transformation to reduce the RF voltage amplitude seen by the transistors and thus increasing the power handling capability of RF switches up to 24.3 dBm while maintaining a less than 1-dB insertion loss. Another impedance transformation network has been designed to transform Zg and Zl to about 5 Q A 2.8-nH Lg and a 10.3-pF Cp are needed as shown in Figure 6-26, which requires a 0.5to 0.8-nH off-chip inductor (Lgo)

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136 Figure 6-25 The output IdB compression point measurement and IP 3 measurement when Vctrl= Vctrl= ^.0 V and Vdb= Vsb= 3.0 V at 928 MHz of the 0.35-pm RF switch with 30-i2 Zs and Zl impedance transformation networks. in series with the bond wire and package lead inductances. The required Lsq is lower than the lowest available off-chip discrete inductors. Because of this, the external inductor was omitted. The actual Ls is about 2.0 to 2.5 nH and Cp is 9.1 pF. The choice of Ls is about 0.3 to 0.8 nH lower than the value needed to transform the Zs and Zl to 5 Q. Simulations show that the impact of the absence of Lso is negligible. Of course, another reason for not using Lso is that a fewer off chip components are preferred. The 9.1-pF Cp is used instead

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137 Cp= 10.3 pF Figure 6-26 The ZY smith chart and the impedance transformation network targeting 5-Q. Zs and Zl for RF switches including the parasitics associated with the SMA connectors.

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138 of the 10.3-pF Cp in order to compensate for mismatches due to the reduction in Lg. Figure 6-27 shows the measured insertion loss and isolation for the 0.35-|im RF switch with 5-Q impedance transformation networks. In this switch, the DC bias condition is the same as the RF switches presented previously in this chapter. At 900 MHz, the measured insertion loss is about 4.7 dB and isolation is 44.3 dB. Due to the fact that Zg and Zl are comparable to the on-resistance of in the switch, as expected, the measured insertion loss is high. Figm*e 6-28 shows the power measurement of the same switch. Pi^b is Frequency (MHz) Figure 6-27 Measured insertion loss and isolation for the 0.35-)im RF switch with 5-Q Zg and Zl impedance transformation networks.

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139 Figure 6-28 The output IdB compression point measurement and IP 3 measurement when VcTRL= ^.0 V and Vj)b= Vsg= 3.0 V at 928 MHz of the 0.35-pm RF switch with 5-Q Zs and Zl impedance transformation networks. 24.0 dBm and IPidB i® 29.5 dBm which corresponds to a Pavs ^0.4 dBm due to the input mismatch which results in high | | of 0.428. IP 3 was measured using a two-tone test. The measured IP 3 is 33.9 dBm and IIP 3 is 38.4 dBm. The use of 5-Q impedance transformation networks has increased the IPidB point to 29.5 dBm. However, due to the increased insertion loss, the output PldB of this switch is similar to the PidB switch using 30-Q impedance transformation networks.

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140 Simulations have been done to examine the relationship of transformed Zg and Zl with insertion loss and PidB of a switch. Figure 6-29 shows the simulation and measured results of insertion loss and PidB versus the transformed Zg and Zl of the 900-MHz 0.35-|xm switch including off-chip impedance transformation networks, bond wire and package parasitics, and connector parasitics. As shown in the simulation, for the 900-MHz 0.35-pm switch, the Zg and Zl should be higher than 30 Q to maintain a less than 1-dB insertion loss and the maximum PidB than 1-dB insertion loss requirement is about 23.5 dBm from simulation and the measured PidB is Zs. Zl (Q) Figure 6-29 Simulations and measured results of insertion loss and PidB versus the transformed Zg and Zl of the 900-MHz 0.35-|j,m switch. Measured data is represented by symbols.

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141 about 23.5 to 24.3 dBm, which agrees well with simulations. When the source/ load impedance is further decreased, the IL increases and PidB ^Iso increase. If the source/load impedance is excessively increased, the sharp increase of insertion loss degrades the PidBaddition, due to the fact that the lower Zs and Zl which are comparable to the on-resistance of the transistor Mj, increases the RF voltage amplitude appeared at the drain nodes of transistors Ml and M3, the input power required to turn on transistor M3 is reduced. This in combination with the increase of insertion loss results in a decreased PidB when Zs and Zl are lower than 10 Q. The highest PidB of 26.6 dBm can be obtained for the 900-MHz 0.35-pm switch when Zs and Zl are about 10 Q However, the 2.6 dB insertion loss is too high to be useful. A possible way to achieve higher PidB with less than 1 dB insertion loss is to re-design the width of the series transistor. Mi (see Figure 6-13). If the on-resistance of transistor Mi in combination with all the parasitic series resistances can be reduced to 0.5 Q and the increased source/drain-to-body junction capacitances due to the increased transistor width are properly compensated by the impedance transformation networks, a Pl of 30 dBm and an insertion loss of 1 dB can be achieved by transforming the Rs and Rl to 2 Q as estimated by (6.1) and (6.2).

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142 6.5 Summary In this chapter, NMOS single-pole double-throw (SPDT) switches for 900-MHz and 2.4-GHz wireless applications have been presented. The switches exhibits usable insertion loss, isolation and power handling capabilities for a number of TDD wireless applications. The limitations and reliability issues associated with the switches have also been examined. Single-pole double-throw switches for 900-MHz wireless application were first implemented in a O.S-pm substrate (with an epitaxial layer) CMOS process using both conventional and Schottky clamped (SC) MOS transistors. The switches exhibit less than 0.8 dB insertion loss, over 40 dB isolation, and 17 dBm PidB 928 MHz. These are the first CMOS switches to have usable insertion loss, isolation and PidB ^ number of 900-MHz wireless applications. In addition, the power handling capability of the switches has been carefully examined, and the results indicate that the switch can withstand the voltages corresponding to 20-dBm available power from the source (Pays) ^ VSWR of 10:1 at the output. In order to understand the impact of p' substrate on insertion loss as well as the feasibility of using CMOS T/R switches for applications with operating frequencies higher than 900 MHz, SPDT RF switches were fabricated using 3.3-V, 0.35-|xm MOS transistors in a foundry 0.18-|im CMOS process. Substrate contacts have been carefully laid out to reduce the impact of p' substrates on insertion loss. The 0.35-|im switches achieve an insertion loss of

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143 0.5-dB and isolation of 39-dB at 928 MHz and a 0.8-dB insertion loss and 24dB isolation at 2.4 GHz. Owing to the lower on-resistances and junction capacitances, the insertion loss for 0.35-pm, 900-MHz switches is much lower than that of the 0.5-|im SPDT RF switches, and the maximum operating frequencies have been increased to 2.5 GHz. These switches also exhibit a 17-dBm PldBImpedance transformation networks have been designed to transform the source and load impedances seen by the switch to a lower value and thus increasing the power handling capability of the switch. A 0.35-pm RF switch with 30 Q impedance transformation networks exhibits a 0.97-dB insertion loss and 24.3-dBm PjdBThis shows that it is feasible to use impedance transformation to reduce the RF voltage amplitude seen by the switch transistors and thus increasing the power handling capability of RF switches for applications requiring a 20-dBm output power while maintaining an insertion loss of less than 1 dB.

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CHAPTER? SUMMARY AND FUTURE WORK 7.1 Summary Schottky clamped MOS transistors for RF switch applications have been demonstrated with identical output and turn-on I-V characteristics to those of conventional MOS transistors, while the parasitic bipolar effects and latchup susceptibility in CMOS structures are greatly reduced. Fabrication of the structures requires no additional mask or modifications of the Salicide CMOS process utilized for this work. The reduced current gain of Schottky clamped CMOS structures enables a reduction of the minimum n^-to-p'^ spacing of CMOS circuits. Schottky clamped CMOS inverters with a reduced ri^drain-to-p '-drain spacing exhibit almost the same voltage transfer characteristics to those of conventional CMOS inverters, while the layout area is about 17% less than a conventional CMOS inverter. These should enable area reduction of digital and analog circuits using Schottky clamped MOS transistors. A Schottky diode clamped merged drain (SCMD) CMOS structure and a 100-stage SCMD CMOS inverter chain have been demonstrated showing that an SCMD CMOS inverter (SCL= 1.6 |im) has a ~ 30% smaller footprint than a conventional CMOS inverter. This area reduction should remain the same as the technology is scaled. The voltage transfer characteristics and the 144

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145 propagation delay of SCMD CMOS inverters are almost identical to those of conventional CMOS inverters. Single-pole double-throw RF transmit/receive switches have been presented using both conventional and Schottky clamped MOS transistors. The switches were fabricated in a foundry 0.5-|xm CMOS process. They exhibit a 0.8-dB insertion loss, a 40-dB isolation, and a 17-dBm PidB MHz. These are the first CMOS switches to have sufficient performance for ISM band applications near 900 MHz. The effects of substrate resistances and source/drain-to-body capacitances associated with MOS transistors on insertion loss of RF switches have been analyzed. The substrate resistance and source/drain-to-body capacitance must be lowered to decrease insertion loss. A low insertion loss CMOS RF switch can be achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by DC biasing the TX and RX nodes which decreases the capacitance, while increasing the power 1-dB compression point. Using Schottky clamped MOS transistors reduce the minority carrier injection from the switch, and when the switch is integrated with other CMOS circuits, susceptibility to latchup for the CMOS circuits should be reduced. Because the switch is implemented in a foundry CMOS process, this dissertation work shows that a T/R switch could be integrated with the other CMOS circuits. The impact of p' substrate on insertion loss as well as the feasibility of using CMOS RF T/R switches for applications with operating frequencies

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146 higher than 900 MHz have also been examined by fabricating SPDT RF switches using 3.3-V, 0.35-|im MOS transistors in a foundry 0.18-|im CMOS process utilizing p' substrates. Substrate contacts have been carefully laid out to reduce the impact of p' substrates on insertion loss. A 900-MHz switch achieves an insertion loss of 0.5 dB and isolation of 39 dB at 928 MHz, while a 2.4-GHz switch achieves a 0.8-dB insertion loss and 24-dB isolation at 2.4 GHz. The 0.5-dB insertion loss of the 900-MHz switch is competitive to that of a number of GaAs switches at 900 MHz [6], [46] and the 2.4-GHz switch is the first bulk CMOS switch to have adequate performance for 2.4-GHz ISM band applications. The source and load impedances seen by the switch have been transformed to a lower value to increase the power handling capability of the switch. A 0.35-pm RF switch with 30-Q impedance transformation networks exhibit a 0.97-dB insertion loss and 24.3-dBm Pi^b point. This shows that it is feasible to use impedance transformation to reduce the RF voltage amplitude seen by the switch transistors and thus increasing the power handling capability of RF switches for applications requiring 20 dBm output power while maintaining insertion loss of less than 1 dB. 7.2 Future Work Efforts on CMOS RF front end have shown promising results for applications at 900 MHz and higher. The focus of the proposed future work should be to design and demonstrate a 2.4-GHz low insertion loss and high power

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147 CMOS RF T/R switch using both conventional and Schottky clamped MOS transistors for 2.4-GHz wireless local area network (WLAN) applications. The 2.4-GHz SPDT switch with impedance transformation networks is expected to exhibit similar performance to those of 900-MHz SPDT switches. That is, insertion loss is expected to be lower than 1 dB and isolation is expected to be more than 20 dB at a PidB of higher than 20 dBm. For 30-dBm applications, in order to deliver 30 dBm of sinusoidal power to a 50-Q antenna, the peak-topeak voltage swing at the antenna must be ~ 20 V. For a 0.35-|0.m MOS transistor, the maximum supply voltage is about 3.3 V. The 20-V voltage swing is impractical for CMOS integrated circuits. The impedance transformation network between the antenna and the switch needs to transform the 50-Q impedance of the antenna to approximately 2 Q. seen by the switch. To achieve reasonable insertion loss, the on-resistance of the switch transistors needs to be much lower than the 2-Q source/load impedance, so that a peak-to-peak voltage swing of about 5 V at the output of a switch delivers 30 dBm of power to the antenna. The use of impedance transformation networks will increase the insertion loss of the switch due to extra series resistances and a reduced ratio between the source/load impedance and the switch resistance. As mentioned in section 6.4.2, the on-resistance of transistors in series with any parasitic series resistances need to be as low as 0.5 Q in order to achieve a Pl of 30 dBm with a less than 1 dB insertion loss. Thus, really high quality factor (Q) inductors and capacitors are needed for the network to reduce the increase of

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148 insertion loss. Discrete off-chip inductors are more suitable for the 2.4-GHz impedance transformation network due to the fact that integrated inductors do not have high Q at 2.4 GHz [49-50]. Through these, the implementation of high power handling capability CMOS RF switches for WLAN applications should be integrated.

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APPENDIX S 21 OF A SHUNT Y-SERIES Z NETWORK In order to quantitatively understand the impact of substrate resistances, capacitances, and on-resistances, insertion loss has been analyzed in chapter 4. To simplify, instead of analyzing a complete switch, the circuit containing a single MOS transistor in Figure 4-4(a) has been analyzed using a circuit model in Figure 4-4(c), where IS21I of the circuit is (4.1). In this appendix, (4.1) will be derived. It has been shown that the scattering (S) parameters of a series impedance, Z, in a network with source and load impedances of Zq as shown in Figure A-1 (a) is [15] Z Z + 2Zq _ 2Zq 21 “ Z + 2Zq (A.1) and from S 3 mimetry, we observe that 822 = and Sj^ 2 = ^ 21 Similarly, the S parameters of a shunt admittance, Y, in a network with source and load impedances of Zq as shown in Figure A-1 (b) is -ZnY S = "0 2 + ZqY ^21 2 + ZnY (A.2) 149

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150 Figure A-1 (a) Two-port network of a series impedance, Z; (b) Two-port network of a shunt admittance, Y. For a circuit shown in Figure A-2 including a series impedance, Z, and a shunt admittance, Y, the S 21 is S21 = 2V2 Y-i— = — 2 Zq Zq + Z Zq + z Y-i+Zq (A.3) Zq + Z Figure A-2 Two-port network of a series impedance, Z, and a shunt admittance, Y

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151 and can be simplified to be ^21 ^^0 2Zn + Z + (ZZq + Zq ) • Y (A.4) For the circuit show in Figure 4-4 (c), Y jCOCrp 1 + jcoCrpRg and Z= RonThus by plugging Z and Y into (A.4) S (2Zo + Ron) + (^on^o + 2q^)(i + j-coCtRe) 2Zo(l + jcoCrpRg) (2Zq 4Ron) *" *" ^on)^b (^on^o )) By taking the reciprocal of | S 21 1 it can be shown that 1 _ (^ON ^^ 0 ) ® [(^ON (^ON ^ 0 )^ 0 ) IS2/ ' (2Zof(l + (o"CTX") where co is the radian frequency, Zq is the characteristic impedance, Rqn is the transistor on-resistance, Rg is the substrate resistance associated with the transistor and C-p ^DB + ^SB + (^GD ^ ^Gs)^GB ^GD + ^GS + ^GB is the equivalent capacitance shown in Figure 4-4 (c). By maximizing the numerator of (4.1) with respect to Rg, it can be shown that the maximum value of occurs at Rg of

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152 I^B{MAX) —CO Crp • (Rqj^Zq + Zq ) + J(£) Crp ^(Rqj^^q + Zq) + 4C0 C-p 2(0 Crp • (RqN 2 ^ 0 ) (^ON 2Zq) 2 (4.5) For typical CMOS RF switches operating at 1 GHz, Ct is on the order of a couple pico-Farad and Rqn is on the order of a few ohms which is much smaller than Zq. Thus, (4.5) can be approximated as R Vc-r^ • Zq + 4coC-r, ; 2p 2 „2 CO ZtQ 16 + 1 B(MAX) ^ 2^ 2 4c0 Crji (A.6) And under these conditions, the first term inside the square root of the numerator is much smaller than 1 and can be ignored. Also, the first term in the numerator is much smaller than the second term in the numerator of (A.6), and thus (A.6) can be simplified to Rb(max) ~ l/oiC-jv

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BIOGRAPHICAL SKETCH Feng-Jung Huang was born in Taipei, Taiwan in 1970. He received the B.S. degree in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 1993, and the M.S. degree from the University of Florida, Gainesville, in 1998. He is currently a Ph.D. degree candidate at the University of Florida, Gainesville. From 1995 to 1996, he worked as a research assistant developing intelligent power integrated circuits for a university and industry cooperated research project at National Tsing Hua University, Hsinchu, Taiwan. Since 1997, he has been with the Silicon Microwave Integrated Circuits and System Research Group (SiMICS), Department of Electrical and Computer Engineering, University of Florida, Gainesville. His research was supported by an NSF research grant, and he has received a TI fellowship in 1999. His current research is focused on developing devices and circuit blocks to implement RF analog and digital systems using silicon IC technologies. 158

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I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Associate Professor of Electrical and Computer Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Professor of Electrical and Computer Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Professor of Electrical and Computer Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. r Rat [dyY. ChiaWO Professor of Computer and Information Science and Engineering

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This dissertation was submitted to the Graduate Faculty of the College of Engineering and to the Graduate School and was accepted as partial fulfillment of the requirements for the degree of Doctor of Philosophy. May 2001 Winfred M. Phillips Dean, Graduate School