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The application of photoconductive switches in AC circuit protection

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Title:
The application of photoconductive switches in AC circuit protection
Creator:
Triaros, Christos P., 1961-
Publication Date:
Language:
English
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xii, 114 leaves : ill. ; 28 cm.

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Subjects / Keywords:
Charge carriers ( jstor )
Electric current ( jstor )
Electric potential ( jstor )
Electric substations ( jstor )
Electrons ( jstor )
Heat sinks ( jstor )
Modeling ( jstor )
Narrative devices ( jstor )
Simulations ( jstor )
Subroutines ( jstor )
Dissertations, Academic -- Electrical Engineering -- UF
Electric power systems -- Protection ( lcsh )
Electrical Engineering thesis Ph. D
Optoelectronic devices ( lcsh )
Semiconductor switches ( lcsh )
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bibliography ( marcgt )
non-fiction ( marcgt )

Notes

Thesis:
Thesis (Ph. D.)--University of Florida, 1991.
Bibliography:
Includes bibliographical references (leaves 111-113).
General Note:
Typescript.
General Note:
Vita.
Statement of Responsibility:
by Christos P. Triaros.

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THE APPLICATION OF PHOTOCONDUCTIVE SWITCHES
IN AC CIRCUIT PROTECTION













By

CHRISTOS P. TRIAROS


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA


1991


























Copyright 1991 by

Christos P. Triaros


























To My Father














ACKNOWLEDGMENTS


I would like to thank my family for their support and encouragement during this work. I am very grateful to my advisor, Dr. Dennis P. Carroll, for his guidance and support in completing this work. I extend a special thanks to Dr. F. Lindholm and Dr. A. Neugroschel for helpful discussions. I also thank Dr. G. Bosman, Dr. A. Domijan, and Dr. A. Varma for serving on my supervisory committee.

I would also like to acknowledge the support of the Electric Power Research Institute (EPRI), the Florida High Technology and Industry Council (FHTIC), and the National Science Foundation (NSF).














TABLE OF CONTENTS



ACKNOWLEDGMENTS .................................. iv

LIST OF SYMBOLS .................................... vii

ABSTRACT ......................................... xii

CHAPTERS

1 INTRODUCTION .................................. 1

1.1 Background .................................... 1
1.2 Objective ............................ ......... 2

2 MODELING OF THE PCE ............................. 5

2.1 Device Physics .................................. 5
2.2 Electrical M odels ................................ 20
2.3 Optical M odels ................................. 29
2.4 Thermal Models ................................ 31

3 POWER SYSTEM SIMULATION STUDIES ................... 37

3.1 System Modeling ................................ 37
3.2 Power System Simulator ........................... 41
3.3 Designs and Results .............................. 44
3.4 Comparison of the PCE with GTO Thyristors................ 65

4 FABRICATION AND TESTING ......................... 67

4.1 Fabrication Process .............................. 67
4.2 Device Testing ................................. 70

5 CONCLUSIONS AND FUTURE RESEARCH .................. 78








APPENDIX .......................................... 80

REFERENCES ....................................... 111

BIOGRAPHICAL SKETCH ............................... 114














LIST OF SYMBOLS



Ap,,e PCE area for current conduction Asink Heat sink area for thermal conduction CAu Empirical constant used to calculate the Auger recombination lifetime Ce Empirical constant used to calculate the PCE saturation current Ctpce Thermal capacitance of PCE Ctsink Thermal capacitance of heat sink c Speed of light (2.998x108 m/sec) CpCe Specific heat of PCE material Cp sink Specific heat of heat sink material Dn Electron diffusion coefficient Dp Hole diffusion coefficient dunit Depth of one PCE unit E Electric field (also symbol for energy) Eg Energy bandgap Eg(0) Energy bandgap at 0 K Emax Maximum hold-off voltage per unit length f Frequency of source voltage g Free carrier generation rate h Planck's constant (6.63x10-34 J-sec) hb Percentage of bulk optical power that is converted to heat









hc Convection coefficient hj Percentage of junction optical power that is converted to heat Ibr Breaker current Ipce PCE current Ioffpoe PCE current under dark conditions isatpce PCE on-state saturation current Jn Electron current density Jp Hole current density k Boltzmann's constant (1.38x1O-23 J/K) kr, Thermal conductivity of PCE material ksink Thermal conductivity of heat sink material La Ambipolar diffusion length Lpce Electrical length of PCE ls System inductance Link Length of heat sink m n Electron density of states effective mass m p Hole density of states effective mass N-A Ionized acceptor concentration N+D Ionized donor concentration Na Acceptor concentration Nc Effective density of states in the conduction band Nref Empirical constant used in electron mobility calculations Nunits Number of units constituting one PCE N, Effective density of states in the valence band n Free electron concentration









ni Intrinsic carder concentration no Equilibrium electron concentration nT Electron concentration on trap level Pgen Heat generated in PCE pb opt Bulk optical power PJopt Junction optical power Pref Empirical constant used in hole mobility calculations P Free hole concentration Po Equilibrium hole concentration q Electronic charge (1.6x10-19 C) Rioad Load resistance Rn Electron recombination rate Rp Hole recombination rate Rpce PCE resistance ROff pee PCE resistance under dark conditions Ronpc" PCE resistance under illuminated conditions Rs System resistance Rtcnv Thermal resistance between heat sink and cooling liquid RtPe" Thermal resistance of PCE Rtsink Thermal resistance of heat sink Rtest Test resistor for experiment current measurements Tamb Ambient temperature Tpce PCE temperature Tnaxpce Worst case temperature rise in PCE Tsirk Heat sink temperature









t Time

tf Time at which a fault occurs Vi Electrostatic potential Vn Electron quasi-Fermi potential VP Hole quasi-Fermi potential Vpce Voltage across PCE VOffpce Voltage across PCE under dark conditions Vsatpce Minimum on-state voltage required across PCE to induce current saturation Vs Instantaneous value of source voltage Vsrms RMS value of source voltage Vth Thermal voltage w Width of one PCE unit AIsatp. Increase in PCE saturation current due to junction optical light An Excess optically generated electron (hole) carrier concentration a Empirical constant used in energy bandgap calculations 13 Empirical constant used in energy bandgap calculations

-y Empirical constant used in electron mobility calculations

6 Empirical constant used in hole mobility calculations bn Excess electron (hole) carrier concentration during transient conditions ES Permittivity 77 Quantum efficiency A Wavelength of optical source /in Electron mobility /nmax Maximum electron mobility liPmax Maximum hole mobility









P nmdn Minimum electron mobility P Pmin Minimum hole mobility LPp Hole mobility Ppee Density of PCE material Psink Density of heat sink material or Total electron and hole conductivity r- Carrier recombination lifetime TAu Auger recombination lifetime TSRH Shockley-Read-Hall recombination lifetime

0 Incident amount of photons per unit time














Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

THE APPLICATION OF PHOTOCONDUCTIVE SWITCHES IN AC CIRCUIT PROTECTION

by

CHRISTOS P. TRIAROS

May 1991

Chairman: Dr. Dennis P. Carroll
Major Department: Electrical Engineering

This study investigates the feasibility of the PCE (photoconductive circuit element) for protective switching applications in AC (alternating current) power transmission and distribution circuits. Designs using both the all-solid-state and hybrid arrangements illustrate several potential advantages over conventional protective devices, which include increased speed of operation, improved precision in interruption point, more compact designs, and greater overall reliability. Electrical, optical, and thermal models are developed for the PCE and are incorporated into a power system simulator which evaluates PCE performance during steady-state and transient operation. Simulation results at the substation, residential, and transmission levels demonstrate the feasibility of the PCE as an interruptor, especially at the higher substation and transmission levels. In addition to theoretical designs and simulations, low power prototype PCE-based breakers are fabricated and tested for proof of concept. Experimental tests exhibit the capability of the PCE to hold off large voltages, and interrupt large currents with precision and at high speeds. Furthermore, experimental results, as well as results from the numerical simulator PC-1D, are used to validate device models and confirm theoretical design results.














CHAPTER 1
INTRODUCTION


The photoconductive switch, often referred to as a photoconductive circuit element or PCE [1], may have great potential for power system applications. This study investigates the feasibility of photoconductive switches in AC circuit protection. Electrical, optical, and thermal models are developed for the PCE and are used in power system simulation studies in order to design and test PCE-based breakers. This work includes designs of all-solid-state as well as hybrid PCE-based breakers at the substation, residential, and transmission levels. It appears from these designs that the PCE may indeed have a future in circuit protection, especially at the higher system levels. Fabrication and testing of low power prototype PCE-based breakers is also part of this study. Experimental results validate theoretical expectations regarding the operation of the PCE.


1.1 Background


A large class of switching applications in the electric utility industry involves the use of mechanical switches to interrupt or limit currents in power circuits [2]. There are numerous types of breakers for both AC and DC (direct current) circuits. These breakers vary in size, principle of operation, interrupting capacity, voltage rating, etc. However, they all have several undesirable properties in common. They all are relatively slow; they are unpredictable as to precisely when they will open or close; and their interrupting capacity is limited by complex arc phenomena. The PCE appears to be an attractive






2
alternative or supplement to mechanical switchgear that could eliminate or minimize these undesirable features.

The PCE consists basically of semi-insulating semiconductor material, which can be made highly conductive through applying laser or other optical excitation that contains photon energy exceeding the semiconductor energy gap. The PCE can be turned on and off very rapidly [3], will conduct large currents, and will hold off very high voltages, yet can be made relatively compact. It is also a bilateral device, which is an advantage over other semiconductor switches for AC applications, and the voltage and current rating of a single unit can be easily scaled to meet the application. In principle, it is possible in a single device to switch high voltages (up to megavolts at 100 kV per cm length) and high currents (up to megamperes at 20 kA per cm width) with more precision and higher efficiency than with any other technology [4]. This switch can be designed to close faster, with less inductance, and less relative jitter than is possible with other technologies. Thus components of circuit interruptors can be made simpler, more efficient, and more compact. The large specific heat and the excellent thermal conductivity of photoconductive materials make the technology applicable to many highpower applications. Furthermore, operation of PCE switches at cryogenic temperatures can improve the optical absorption depth, carrier mobility, and mechanical properties of the device material [5]. In spite of its apparent advantages as a power switch, the PCE as yet is relatively unexplored for power system applications.


1.2 Objective


The principal objective of this study is to investigate the feasibility of the PCE for protective switching applications in AC power transmission and distribution circuits. To achieve this goal, it is planned to develop electrical, thermal, and optical models that






3
accurately describe the behavior of the PCE under both steady-state dark and illuminated conditions, as well as during transient operation. These PCE models will aid in the design of PCE-based breakers. The performance of these designs will be evaluated with the help of equivalent circuit calculations and by the use of digital computer simulations. Performance parameters will include: circuit interruption time, blocking voltages, interruption capacity, device losses, light source requirements, heat dissipation, and cooling methods. Furthermore, low power prototype PCE-based breakers will be fabricated and tested for proof of concept.

Chapter 2 describes the modeling of the PCE. The first section of this chapter presents the semiconductor equations that govern the physical behavior of the PCE. These equations are incorporated into the one-dimensional device simulator PC-1D [6], which is used to numerically model the current versus voltage characteristic of the PCE. The second section gives a description of the electrical models which predict the current versus voltage characteristic of the PCE during both steady-state and transient operation. The third section presents the optical models which are used to calculate the optical power required by the PCE in order to conduct the desired steady-state load current. The last section of Chapter 2 describes the thermal models which predict the temperature of the PCE during both steady-state and transient operation.

Chapter 3 evaluates the performance of PCE-based breakers during both steadystate and transient operation. The PCE is evaluated in both the all-solid-state approach and the hybrid approach. The first section of this chapter describes the power system models being utilized to test the PCE. The second section describes the power system simulator which incorporates the system and device models to numerically evaluate PCE performance. The third section presents breaker designs and simulation results for various applications. These applications include breakers operating at the substation






4

level, the residential level, and the transmission level. The last section of Chapter 3 compares the PCE to various GTO (Gate-Turn-Off) thyristors.

Chapter 4 describes the fabrication process and testing of low power prototype PCE-based breakers. The first section of this chapter presents a qualitative description of the fabrication process which was performed by Leslie Roberts [7] at the University of Florida's Micro Electronics Laboratories. The second section presents experimental test results for the PCE-based laboratory breakers. These results show PCE performance during both steady-state and transient operation.














CHAPTER 2
MODELING OF THE PCE


This chapter describes the modeling of the photoconductive circuit element. The first section presents the semiconductor equations that govern the physical behavior of the PCE. These equations are incorporated into the one-dimensional device simulator PC-1D [6], which is used to numerically model the current versus voltage characteristic of the PCE. The second section gives a description of the electrical models which predict the current versus voltage characteristic of the PCE during both steady-state and transient operation. The third section presents the optical models which are used to calculate the optical power required by the PCE in order to conduct the desired steady-state load current. The last section of this chapter describes the thermal models which predict the temperature of the PCE during both steady-state and transient operation.


2.1 Device Physics


Figure 2.1 shows a typical PCE which consists of an intrinsic photoconductive material, and metal/heavily doped regions which aid in obtaining ohmic contacts to the switch. An optical source is used to increase the conductivity of the PCE by generating electron-hole pairs in the bulk of the material. This section ascertains how the metal/heavily doped regions (contacts) influence the carrier profiles, the electric field profile, and the current versus voltage characteristic.









Light Source

metallic metallic
contact contact




Intrinsic Semiconductor



x-direction z
Figure 2.1. A typical photoconductive circuit element consisting of an intrinsic photoconductive material and metal/heavily doped regions.


2.1.1 The Governing Semiconductor Equations


Photogeneration, recombination, trapping, drift, and diffusion [8] are the main physical processes governing electrons and holes in a photoconductor. The system of governing equations for these processes consists of the electron and hole transport equations, the electron and hole continuity equations, Poisson's equation, and the kinetic rate equation. The one-dimensional time-dependent form of these equations is presented here.

The electron and hole transport equations are written as

J.(x,t) = qpn(x, t)n(x,t)E(x,t) + qDn(x, t)f-X (2.1-1) Ox

and

JP(x't) = qspp(xt)(xt)E(xt) - qDp(xt)O9(x)t) (2.1-2) a9x
These equations define the electron and hole current densities in terms of a drift component and a diffusion component. The drift component, which arises from carriers moving under the influence of an electric field, is proportional to the mobility, carrier






7
concentration, and electric field. The diffusion component, which arises from carriers moving due to a carrier gradient, is proportional to the diffusivity, and the positional rate of change of carrier concentration. The carrier concentrations may further be related to the quasi-Fermi and electrostatic potentials by the following expressions: n(x,t) = niexp (- (Xt) vn(Xt) (2.1-3) Vth (21)

and

P(Xt) = niexp (V (x't) (X't) (2.1-4)



The electron and hole continuity equations are written as

an(x, t) 1 aJ (, t) + g(x,t) - Rn(x,t) (2.1-5) Ot q Ox

and
At q ax + g(x,t) - Rp(x,t) (2.1-6) &o q Ox

These differential equations describe the time dependent rate of change of electron and hole concentrations per unit volume. This temporal rate of change of carrier concentration is given in terms of the divergence of the current density, the per unit volume generation rate, and the per unit volume recombination rate. The first term accounts for all carriers entering and leaving the volume through drift and diffusion, the second term accounts for all carriers being generated in the volume by optical and thermal excitation, and the last term accounts for all carriers recombining in the volume by various recombination processes including Shockley-Read-Hall recombination, Auger recombination, and surface recombination.

Poisson's equation is written as

a2V(x,t) OE(x,t)
-s ax2 =8 6 ax -q[p(x,t)-n(x,t)+N+(x,t)-NA(x,t)] (2.1-7)






8
This equation relates the electric field to the charge density. The charge density is given in terms of mobile carriers and localized (immobile) charge. The mobile carriers are electrons in the conduction band and holes in the valence band. The localized charge is introduced by impurities which emit and/or capture electrons. The term on the left of the first equality is introduced to indicate that the electric field is the negative gradient of the electrostatic potential.

The kinetic rate equation for a single trap level is written as

aT -- Rn(x,t)- Rp(x,t) (2.1-8) This equation gives the temporal rate of change of the electron concentration on the trap, which is equal to the difference in the recombination rates of electrons and holes.

The six coupled differential equations just described are very complicated to use in the power system simulation studies. Therefore, a device simulator, which solves these equations, needs to be used to numerically model the PCE. From these numerical models simple analytical models may be derived for use in the power system simulation studies. Various device simulators [6] have been developed to numerically solve these equations. PC-lD is one such device simulator. The following part of this section presents the results from this device simulator which aided in developing several of the analytical models described in this chapter.


2.1.2 Numerical Simulations Using PC-1D


This part of the section numerically models the electrical and optical behavior of the PCE during its steady-state operation. Figure 2.2 shows the PCE, in its illuminated state with an applied voltage, as used by PC-lD for the numerical simulations being presented. The PCE consists of high resistivity bulk material to which ohmic contacts are formed. An ohmic contact may be formed by depositing metal on implanted or






9
diffused heavily doped regions [9]. In principle, an ohmic contact should have negligible resistance relative to the bulk resistance of the device [10]. In this section it is shown that this is not always the case.

Light Source
metallic Ac
contct--0




- ce

Ipce \metallic
] contact

Figure 2.2. The PCE, in its illuminated state with an applied voltage, as
used by PC-ID for the numerical simulations presented in this section.

High resistivity p-type semiconductors are used as bulk material for the PCEs under study. The principal reason of p-type over n-type bulk material comes from the fact that the value of hole mobility is lower than the value of electron mobility for the semiconductors under study. Therefore, other things being equal the dark resistance for the p-type material will be larger than the dark resistance of the n-type material. Two semiconductor materials are being investigated in this work, primarily Si (silicon), and in a secondary way GaAs (gallium arsenide).

The heavily doped regions which aid in obtaining ohmic contacts to the PCE also form junctions in the device. Since the PCE will be used in an AC environment there are, in principle, only two ways of forming contacts which would affect differently the operation of the device. One way is to make both heavily doped regions of the same type, that is, either p-type or n-type. This configuration always has one of the two junctions forward biased and the other reverse biased, independent of voltage polarity. The other way is to make one heavily doped region p-type and the other heavily doped






10

region n-type. This configuration always has both junctions either forward biased or reverse biased depending on the voltage polarity. The former of the two ways was investigated and following is a discussion on the effects of the reverse biased junction.

A Si-p'p-p+ structure was used to numerically model the effects of the reverse biased junction on the current versus voltage characteristic, the carrier profiles, and the electric field profile. For the sign convention shown in Figure 2.2 the p+/p- junction is reverse biased whereas the p-/p+ junction is forward biased. Figure 2.3 shows a plot of current versus voltage for this device from numerical simulations using PC-1D. The current does not indefinitely increase linearly with increases in voltage, as might be expected for an ideal photoconductor, but instead saturates when the applied voltage reaches some value that depletes the reverse biased junction of carriers. Figure 2.5 shows the carrier concentration being depleted in the vicinity of the reverse biased junction for a voltage bias of 0.8 volts. The corresponding high electric field related to this depleted region is shown in Figure 2.7. This saturation effect, which limits the current carrying capabilities of the PCE, may be alleviated by generating more carriers at the reverse biased junction. One way of achieving this is to apply a second light source that would only generate carriers at the junction. Figure 2.4 shows the result of adding a second light source to the simulated case shown in Figure 2.3. The current saturation level increases from approximately 200 amps to approximately 900 amps at the expense of only 900 watts of optical power. This is due to the increase in generated carriers at the reverse biased junction, which require a higher applied voltage to deplete. Figure 2.6 shows the carrier concentration not being depleted at the reverse biased junction for the same voltage bias as in Figure 2.5. The corresponding low electric field for this case is shown in Figure 2.8.
























0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vpce (volts)

Figure 2.3. Plot of Ipc versus Vpce for a Si-p p-p+ structure with Lpce=l
mm and Apce-4.5 cm2. Other parameters include pbopt=1.8 kW @ 1.06 im,
a=10 cm-1, An=1.37xlO17 cm-3, Tpce=300 K, Yn=592 cm2/(V.s), /p=207
cm2/(V.s), and 7-SRH=5 pssec. The plot is from numerical simulations using PC-1D.


0 0.2 0.4 0.6 0.8 1 Vpce (volts)


1.2 1.4 1.6 1.8


Figure 2.4. Plot of Ip,, versus Vpee for same device structure and parameters as in Figure 2.3 with the addition of PJopt=900 W @ 800 nm. The plot is from numerical simulations using PC-1D.





























1015

1014

-0.2 0 0.2 0.4 0.6 0.8 1 1.2 Position (mm)

Figure 2.5. Plot of hole concentration versus position for a voltage
bias of 0.8 volts. Same device structure and parameters as in Figure 2.3. The plot is from numerical simulations using PC-1D.


-0.2 0 0.2 0.4 0.6 0.8 1 1.2 Position (mm)

Figure 2.6. Plot of hole concentration versus position for a voltage
bias of 0.8 volts. Same device structure and parameters as in Figure 2.4. The plot is from numerical simulations using PC-1D.


1w ,


I1 -t"~




















-1000


-1500


-2000


-2500


-300
-0.2


0 0.2 0.4 0.6 0.8 1 1.2


Position (mm)

Figure 2.7. Plot of electric field versus position for a voltage bias of 0.8 volts. Same device structure and parameters as in Figure 2.3. The plot is from numerical simulations using PC-1D.



I-xt


-0.2 0 02 0.4 0.6 0.8 1 1.2 Position (mm)

Figure 2.8. Plot of electric field versus position for a voltage bias of 0.8 volts. Same device structure and parameters as in Figure 2.4. The plot is from numerical simulations using PC-1D.


gs






14
Simplified models that can predict the observed current saturation phenomenon have been developed for use in the power system simulation studies. Several simulation experiments using PC-1D have been analyzed in order to develop these simplified analog models. The results from these models are in good agreement with the device simulation results if the length of the device is several times larger than the ambipolar diffusion length. As a rule of thumb a factor of ten should be adequate. Figures 2.9, 2.11, 2.13, 2.15, and 2.17 include some of the current versus voltage plots from various simulation experiments. Figures 2.10, 2.12, 2.14, 2.16, and 2.18 show the respective saturation current versus junction light relationships. Results for Si-based devices, as well as GaAs-based devices are shown in these figures. It should be noted that because of device symmetry the current voltage relationships shown in these figures remain unchanged for negative applied voltages.

Simulation experiments using PC-1D indicate that the saturation voltage, which is defined as the applied voltage at which the current saturates, depends on several device parameters. Such parameters include device length, recombination lifetime, and optical power to the reverse biased junction. The saturation voltage changes proportionally with respect to device length and junction optical power and is inversely proportional with respect to recombination lifetime. The expression for calculating the saturation voltage is given in section 2.2.

Furthermore, these numerical experiments show that changes in the applied junction light give linear changes in the current saturation level. These experiments also suggest that this linear relationship is independent of any of the device's bulk parameters. This constant linear relationship may be observed in the slope of the saturation current versus junction light plots, which is approximately the same for the various plots of each semiconductor material.





















500- Popt = 450 W @ 8Oam

~400

300 Popt=225W@ 80urn

200

100 Popt 0W@ 800mn

0,
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vpce (volts)

Figure 2.9. Plots of I,, versus Vp., for a Si-p'p-p+ structure with L =l mm and Apc�=4.5 cm2. Other parameters include pbopt=l.8 kW @ 1.06 pm, a=10 cm-1, An=l.36x1017 cm-3, Tp.=300 K, un=592 cm2/(V.s), pp=207 cm2/(V.s),
and rSRH=5 Msec. The plots are from numerical simulations using PC-ID.




900 800


" 700


S6000.500i





300


200
0 100 200 300 400 500 600 700 800 900 Popt (watts) - junction light Figure 2.10. Plot of ISatpce versus Popt for same device structure and parameters
as in Figure 2.9. The plots are from numerical simulations using PC-lD.


































0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vpce (vols) Figure 2.11. Plots of Ipc versus Vpce for a Si-p+p-p+ structure with Lp=2 mm and APe=4.5 cm2. Other parameters include pbopt=l.8 kW @ 1.06 ym, a=5 cm-1, An=3.8x1017 cm-3, Tp=300 K, Pn=876 cm2/(V.s), pp=313 cm2/(V.s), and 7SRI-=2 psec. The plots are from numerical simulations using PC-1D.




190

180 170

S160

150

140 130

120 110 100 90
0 20 40 60 80 100 120 140 Popt (watts) - junction light Figure 2.12. Plot of IIp versus PJpt for same device structure and parameters
as in Figure 2.11. The plots are from numerical simulations using PC-1D.
























0.8 1 Vpce (volts)


Figure 2.13. Plots of Ipce versus Vpce for a Si-p'p-p structure with Lp-=4 mm
and Apce=9 cm2. Other parameters include pbopt=1.8 kW @ 1.06 am, a=2 cm-', An=2.36x1016 cm-3, Tpce=300 K, tzn=971 cm2/(V.s), jp=350 cm2/(V.s), and TSRH=5 psec. The plots are from numerical simulations using PC-1D.


Popt (watts) - junction light


Figure 2.14. Plot of Isatvee versus Popt for same device structure and parameters
as in Figure 2.13. The plots are from numerical simulations using PC-1D.





















-200

0.
150 Popt=250W@ 827nm"


100


50
Popt =Ow@ 827 nm

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vpce (vols)


Figure 2.15. Plots of Ipe versus Vpm for a GaAs-p'p-p+ structure with Lpm=0.5 mm and Apc=25 cm2. Other parameters include pbopt=500 W @ 830 rm, c=10 cm-1, An=3.3xl014 cm-3 T =300 K, Pn=8353 cm2/(V.s), p=386 cm2/(V.s), and 7SRH=100 nsec. The plots are from numerical simulations using PC-ID.


300250 200 150


100, 50


0 50


100 150 200 250 300 350 400


Popt (watts) - junction light


Figure 2.16. Plot of ISatpce versus PJpt for same device structure and parameters
as in Figure 2.15. The plots are from numerical simulations using PC-ID.























!300


200


100

Popt = OW @ 827 87in

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vpce (volts) Figure 2.17. Plots of Ip versus Vpce for a GaAs-p'p-p structure with Lw=2 mm and Ap,=4 cm2. Other parameters include pbopt=3.2 kW @ 830 imn, a=5 cm-1, An-1.8xl016 cm-3, Tp=300 K, Yn-=6588 cm2/(V.s), p=320 cm2/(V.s),
and rSRH=-1 psec. The plots are from numerical simulations using PC-ID.




550

5W00 450


8
"= 350

~300.250

g200

150 100 50
0 100 200 300 400 500 600 700 800 Popt (watts) - junction light Figure 2.18. Plot of Ilapce versus PJopt for same device structure and parameters
as in Figure 2.17. The plots are from numerical simulations using PC-iD.






20

2.2 Electrical Models


This section presents the electrical modeling of the PCE for steady-state as well as transient operation. The device geometry for these models is shown in Figure 2.19. The PCE consists of several units put in parallel. This is done because of limitations in the penetration depth of light which limits one of the dimensions of the device, dunit, to this penetration depth. For example, the best effective penetration depth that can be achieved in silicon at room temperature is approximately one millimeter [10] when using a Neodymium-Yag laser which has a wavelength of 1.06 micrometers.

Junction Light Source
metallic




p p





t~l Lgh St'cc du'nit


Figure 2.19. Conceptual geometry of the PCE. The direction of the bulk light is chosen to be transverse to the direction of current. Therefore, the electrical length, Lp,, of the device is independent of the light penetration depth and is primarily determined by the required hold-off (blocking) voltage of the switch. The applied static electric field is limited, in principle, by the breakdown voltage of the bulk semiconductor, which for silicon is approximately [10]


E,c= ( <3(10)'5 V/cm (2.2-1)






21

Other mechanisms, such as surface flashover, may reduce Emax below the value indicated in (2.2-1). Careful engineering design, however, can alleviate the influence of such mechanisms [11].

The width, w, of each unit which depends on the total cross sectional area, Ap, and the number of units, Nnu, being used may be expressed as follows: w = (2.2-2) Nunitsdunit

The total cross sectional area depends on the imposed requirements for leakage current. The number of units is chosen so as to give a compact design.


2.2.1 Steady-State-Off Model


Under dark conditions the bulk material dominates the operation of the PCE. The applied voltage is distributed uniformly across the PCE, and under the assumption of Lpe>>La there is no carrier gradient in the bulk of the device. Therefore, the electron and hole transport equations may easily be rewritten to give the following equation which treats the PCE as a resistor which behaves according to Ohm's law.


Rpe LPCe (2.2-3) Apceo

The combined electron and hole conductivity is given by the following expression: o = q(iPnno + IpPo) (2.2-4) This nonilluminated conductivity depends strongly on temperature because of the law of mass action, port = n?, in which ni depends on temperature [2]. This temperature dependence for p-type material is given by the following expressions [12]: N+� 2 + 4ni

Po = 2 (2.2-5)










no = S. (2.2-6) Po

where,

ni(Tpee) = VN-Nexp ( 2 E) (2.2-7) and,
1,27rm* kr Pce 1.
N, = 2 mnk ) (2.2-8)



2rm*kTp 1.5
N, = 2 r-kPc) (2.2-9) The energy bandgap shown in equation 2.2-7 is also temperature dependent. Thurmond [13] expressed this temperature dependence by the following equation: aT2e (2.2-10) Eg(Tpce) = Eg(O) - (Te + 2)


Furthermore, the electron and hole mobilities depend on the carrier densities. The following equations which were empirically derived by Caughey and Thomas [14] should be adequate for this work.
n n
1max - tmin +,n (2.2-11) P'tn 1 + (N/Nref)^' 7 mn



Pa P
PP = maz - - min + PPmin (2.2-12)
1 +(P/Prj)8 n

The parameters Ilnmax, Inmin, Nref, 7, UtPmax, IPmin, Pref, and b, are empirical constants dependent on the type of carrier and semiconductor material. Variables N and P take on the value of electron and hole carrier densities, respectively.























Figure 2.20. PCE current-voltage relationship under steady-state illumination.


2.2.2 Steady-State-On Model


Figure 2.20 shows the current versus voltage characteristic of the PCE for the steady-state illuminated condition. The PCE is treated as a resistor which behaves according to the following equations:


- Lpce for - Vsat

Rpce for Ve > (2.2-14)
__ vsat -4 Rpce Ts:a1PCe r P Pe(.



VPCR for V6 < -V'" (2.2-15)

- -pet pcee Equation 2.2-13 describes the linear region of the current-voltage relationship. In this region the bulk material dominates the operation of the PCE. The applied voltage is distributed uniformly across the PCE, and under the assumption of L >>La there is no carrier gradient in the bulk of the device. Therefore, the electron and hole transport






24
equations may easily be rewritten to give equation 2.2-13, where the combined electron and hole conductivity is given by the following expression: a = q[(/sn + pp)An + Pnno + sppo] (2.2-16) This illuminated conductivity is dominated by the photogenerated excess carrier concentration. The temperature dependent electron and hole equilibrium carrier densities and the carrier density dependent electron and hole mobilities are given by equations

2.2-5 through 2.2-12.

Equations 2.2-14 and 2.2-15 describe the saturation regions of the current-voltage relationship. In this regions the reverse biased junctions dominate the operation of the PCE. The expressions for the saturation voltage and saturation current, which were empirically derived from the numerical simulations of the previous section, are given below:
LpceLa LPCe
V~e - - opt (2.2-17) Inr CeApceTr


vat
r - [LPce/(Aeu)] (2.2-18) The first term on the right of the equality of equation 2.2-17 determines the saturation voltage without an applied junction light. The second term determines the increase in saturation voltage when junction light is applied. Equation 2.2-18 determines the maximum current carrying capability of the PCE which is simply the saturation voltage divided by the PCE resistance in the linear region. The constant C gives the amount of junction light required to increase the saturation current by one ampere and is determined from the device simulation studies. The ambipolar diffusion length may be expressed in terms of carrier mobilities and recombination lifetime as follows [9]: La= rnpVth (2.2-19) L = tn + jtp






25
The recombination lifetime which includes both the Shockley-Read-Hall and Auger recombination processes is given by equations 2.2-22 and 2.2-23.

Figures 2.21-2.26 show several plots of current versus voltage for various device parameters. These figures show that the results from the models given in this section are in good agreement with the results from the numerical simulations using PC-1D.


2.2.3 Turn-Off Model

The turn-off model describes the transition from the on-state conductivity to the off-state conductivity. This transition occurs when the light source is interrupted, resulting in the decay of the excess carrier concentration from its initial steady-state value to zero. The expression for this transient may be derived from the continuity equations. Under the assumption of a long device, Lpce>>La, which results in constant current densities in the bulk of the device, the solution to the continuity equations is given by the following expression:

bn = Anexp (-l) (2.2-20) The combined electron and hole conductivity may thus be written as o = q[(p, + pp)bn + Pnno + lpPol (2.2-21) The recombination lifetime which accounts for both the Shockley-Read-Hall and Auger recombination processes is given by the following equation:

7 = (rH + -1 (2.2-22) Shockley-Read-Hall recombination is usually dominant. This process involves transitions between the conduction and valence bands and deep level traps. At higher electron and hole concentrations, the impact-Auger process starts to compete for dominance with the Shockley-Read-Hall mechanism. Auger recombination utilizes a third mobile particle,























0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vpcc (volts)
Figure 2.21. Comparison of Ipce versus Vpce from analytical models (PSS-PCE) and numerical simulations (PC-ID) for a Si-p+p-p+ structure with Lpce=l mm and Ape=4.5 cm2. Other parameters include Pbopt=1.8 kW @ 1.06 tm, a=10 cm-1, An=l.36x1017
cm-3, Tpc,=300 K, pn=592 cm2/(V.s), yp=207 cm2/(V.s), and rsRH=5 /sec.


Vpce (volts)


Figure 2.22. Comparison of Ip,, versus Vpe from analytical models
(PSS-PCE) and numerical simulations (PC-1D) for same device structure and parameters as in Figure 2.21 with the addition of PJopt=900 W @ 800 nm.












Using PSS-PCE





40

20


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vpce (volts)

Figure 2.23. Comparison of Ipce versus Vpce from analytical models (PSS-PCE) and numerical simulations (PC-ID) for a Si-p'p-p+ structure with Lp,,=2 mm and Apce=4.5 cm2. Other parameters include pb t1.8 kW @ 1.06/zm, a=5 cm, An=3.8x cmn-3, TP=300 K,/Zn=876 cm /(V.s), p=313 cm2/(V.s), and rSRH=2 tisec.


vpce (volts)


Figure 2.24. Comparison of Ipc versus Vpe from analytical models
(PSS-PCE) and numerical simulations (PC-1D) for same device structure and parameters as in Figure 2.23 with the addition of P3opt=135 W @ 800 nm.


Al1


















~40

30 20 10

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vpc (volts)

Figure 2.25. Comparison of Ip,, versus Vpce from analytical models (PSS-PCE) and numerical simulations (PC-1D) for a Si-p+p-p+ structure with Lp -=4 mm and Ap,--9 cm2. Other parameters include Pbopt=l.8 kW @ 1.06 ym, a=2 cm-', An=2.36x1016
cm-3, Tpce=300 K, n---971 cm2/(V.s), /p=350 cm2/(V.s), and rSRH=5 psec.


0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8


Vpce (volts)

Figure 2.26. Comparison of Ipce versus Vpe from analytical models
(PSS-PCE) and numerical simulations (PC-lD) for same device structure and parameters as in Figure 2.25 with the addition of Popt=90 W @ 800 run.






29

rather than phonons, to conserve energy. Thus the Auger recombination lifetime may be expressed as [15]
1
Tau = CAUAn2 (2.2-23)



2.2.4 Turn-On Model

The turn-on model describes the transition from the off-state conductivity to the on-state conductivity. This transition occurs when light is shined on the device resulting in the increase of the excess carrier concentration from its initial zero value to its final steady-state value. This transient may be expressed by the following equation: bn = An[1 - exp ( )](2.2-24) The derivation of this equation follows similar arguments to the derivation of the turn-off model. Furthermore, the total conductivity and the recombination lifetime are expressed by equations 2.2-21 and 2.2-22, respectively.


2.3 Optical Models


This section describes the optical models which are used to calculate the optical power required by the PCE in order to conduct the desired steady-state load current. Two models are required for this purpose, a bulk optical model which controls the PCE's illuminated conductivity, and a junction optical model which controls the PCE's maximum current-carrying capability.


2.3.1 Bulk Optical Model


The bulk optical model is used to calculate the optical power necessary to uniformly generate, in the bulk of the material, a desired amount of excess carrier concen-






30
tration. The expression for this model can be derived as follows. Each photon which penetrates the surface has an energy E = hc J/photon (2.3-1)


The number of photons per second is related to the bulk optical power by the relation pb
= opt photons/s (2.3-2)
E

The generation rate of electron-hole pairs, given some quantum efficiency, is given by

- 770 EHP/ cm 3.s (2.3-3) g=LpceApce

From the continuity equations the steady-state generation rate may also be expressed as An
g = (2.3-4)
T

By combining equations 2.3-1 through 2.3-4, the bulk optical power is given by the relation

Pb= hcLpceApceAn
optz7A (2.3-5)


2.3.2 Junction Optical Model


The junction optical model is used to calculate the optical power necessary, in the vicinity of the reverse biased junction, to increase the current saturation level by some desired amount. The expression for this model, which is derived empirically from the numerical simulations of section 2.1, is given by the relation pop - C A sat
op- e APee (2.3-6) The empirical constant C, which is independent of any of the device's bulk parameters, gives the amount of junction light required to increase the saturation current by one ampere. For silicon Ce=1.25 W/A, and for gallium arsenide Ce=1.45 W/A.






31

2.4 Thermal Models

This section presents the methodology and thermal models for cooling the PCE. Two cooling methods are described in this section - cooling by heat sinking and cooling by direct immersion. The thermal models are used in the power system simulation studies to predict the temperature of the PCE during both steady-state and transient operation. Temperature is an important parameter in the operation of the PCE especially during the turn-off period. During turn-off inadequate cooling will induce a thermal runaway in the PCE which will have the effect of an unsuccessful interruption.


2.4.1 Cooling By Heat Sinking


This cooling method involves the PCE being deposited on a heat sink and the heat sink being surrounded by a cooling liquid or gas. Figure 2.27 shows the relationship between device geometry and temperature. Heat that is generated in the device due to resistive power dissipation and/or optical power dissipation is either stored in the device or conducted out of the device and into the heat sink. In turn heat conducted into the heat sink is either stored in the heat sink or conducted toward the heat sink surfaces where it is removed by convection.

Asink

L~eApce .1,1. sn I-ink




HetSikTamb T3


Tamb

Figure 2.27. Relationship between device geometry and
temperature for thermal model using cooling by heat sinking.






32
Under the assumptions that the top surface of the device is thermally insulated, that heat is conducted from the top surface of the device toward the bottom surface of the heat sink (x-direction), that heat is removed only at the bottom surface of the heat sink, and that a linear temperature gradient exists in the device, a one-dimensional thermal model is adequate to predict the temperature of the PCE. The differential equations describing this simplified thermal model are given below [16,17]:

Pgen k (9Tce p9ceTP (2.4-1)


-ksink AsinkOTik - hcAsink(T.I - Tamb) + PsinkLsinkAsinkc sinkffink (2.4-2)
-5kA~kOx &~~~98~

Equation 2.4-1 equates the heat generated in the PCE to the sum of heat conducted out of the PCE and into the heat sink and heat stored in the PCE. Equation 2.4-2 equates the heat conducted into the heat sink to the sum of heat convected out of the heat sink and heat stored in the heat sink.

For computer simulation purposes equations 2.4-1 and 2.4-2 are discretized in the x-direction. For simplicity only three nodes are used. Figure 2.27 shows these nodes as being related to the geometries of the device and heat sink. Node 1 is taken to be the top surface of the PCE, node 2 is taken to be the interface between the PCE and the heat sink, and node 3 is taken to be the bottom of the heat sink. The discretized versions of equations 2.4-1 and 2.4-2 are given by the following expressions: Pgej T1 - T2 dTpe (24-3) ?Pce dt


- - Tmb + Cedde (2.4-3)
-h , dt
where,


Pgen =IJ2 Rpc= + hbPpt + hPP(


(2.4-5)










C = pC e Lpce ApceC Ce (2.4-6)


link = T i _sink (2.4-7) t sink-sinkt


L pc~pe (2.4-8)




n Lsink (2.4-9) ksinkAsink

1 nv = (hcAsink)-1 (2.4-10)




Tpce 1 + T2 (2.4-11)
2


Tsink - (2.4-12)
2

Using the relationships of equations 2.4-11 and 2.4-12 and the assumption that the heat conducted out of the PCE is equal to the heat conducted into the heat sink, equations

2.4-3 and 2.4-4 may be rewritten in terms of only Tp.e and Tsnk as follows:


Pgen Tpce - Tink + CI)ce dTpce (2.4-13) Rt +C dt


Tpce - Tsink Tsink - Tamb Tsjnk - Tpce + Cink dTsink (2.4-14)
Rtl Rt2 Rt3 dt

where,
RtPce R ink
Rtl 2 t (2.4-15)










(2.4-16)


R13~n =Rv(Rre i ~nk)
t +Rs
Rt3 --ml ink


(2.4-17)


Figure 2.28 shows the equivalent circuit model of equations 2.4-13 and 2.4-14. Note that heat is equivalent to current in an electrical circuit, temperature is equivalent to voltage in an electrical circuit, and thermal resistances and capacitances are equivalent to resistors and capacitors in an electrical circuit, respectively.


Figure 2.28. Equivalent circuit for thermal model using cooling by heat sinking.


2.4.2 Cooling By Direct Immersion


This cooling method involves the PCE being directly immersed into a cooling fluid. This technique eliminates the thermal resistance involved in heat sinking a device, and thus more heat may be extracted from the PCE. Work done by Iversen (Coriolis Corporation) and Whitaker (University of California) [18] shows a process using such a technique which results in very low junction to fluid thermal resistances and very high heat flux dissipation capabilities.


Rt2 =- p~nv






35
Figure 2.29 illustrates the relationship between device geometry and temperature, for one of the units of the PCE, for this cooling method. Heat that is generated in the volume of each unit is removed by forced convection at the two surfaces associated with the width and length of each unit. Assuming uniform heat generation in the volume of each unit, equal heat removal rates at the two surfaces associated with the width and length of each unit, and no heat removal at the remaining surfaces, then a one-dimensional thermal model is adequate to predict the temperature of the PCE. Furthermore, under these assumptions heat is conducted toward the heat removal surfaces via a temperature gradient within the unit. Therefore, the hottest plane related to the width and length of each unit is midpoint of the depth. The temperature at this plane is taken to be the PCE temperature.

tTamb










dunit


Figure 2.29. Relationship between device geometry and
temperature for thermal model using cooling by direct immersion.

The differential equation describing this thermal model is given below [16,17]:


Pge, - e dTpce Tce - Tamb
=ge UI -t + RPCe (2.4-18) dt .C

where,
Pa 'I2CRPce + hbPIpt + hjP't
Pgen 2N,,it. OP (2.4-19)










_ V~ ppceCppewdunsiLpce
e = 2 (2.4-20)


2ktce w Lit (2.4-21) 2klceWLpce
Equation 2.4-18 equates the heat generated in half the volume of each unit to the sum of heat stored in half the volume of each unit and heat conducted out of half the volume of each unit. Figure 2.30 shows the equivalent circuit for this thermal model.


Tpce A A A


Tmb


Figure 2.30. Equivalent circuit for thermal model using cooling by direct immersion.














CHAPTER 3
POWER SYSTEM SIMULATION STUDIES


This chapter evaluates the performance of PCE-based breakers during both steadystate and transient operation. The PCE is evaluated in both the all-solid-state approach and the hybrid approach. In the all-solid-state approach the breaker is composed primarily of the PCE which is used to carry the load current at all times as well as interrupt the load or fault current when required. In the hybrid approach the breaker is composed of a PCE in parallel with a mechanical switch. The mechanical switch is used to carry the load current, whereas the PCE is used to interrupt the load or fault current. The first section of this chapter describes the power system models being utilized to test the PCE. The second section describes the power system simulator which incorporates the system and device models to numerically evaluate PCE performance. The third section presents breaker designs and simulation results for various applications. These applications include breakers operating at the substation level, the residential level, and the transmission level. The last section compares the PCE to various existing GTO thyristors.


3.1 System Modeling

This section describes the power system models being utilized to test the PCE. Two types of models are being presented, the all-solid-state model and the hybrid model. Figure 3.1 shows the circuit representation of the all-solid-state model. The system is defined by a single phase source, and its relating series resistance and inductance,






38
connected to a purely resistive load. The breaker, which is composed of a PCE in parallel with a surge arrester, is connected between the source and the load. Furthermore, a fault switch is connected in parallel to the resistive load. Figure 3.2 shows the circuit representation of the hybrid model. The main difference between this model and the all-solid-state model is the addition of the mechanical switch in parallel to the PCE.

Rs L p
T'e




V -- --2'f Sf/

Surge
Arrester




Figure 3.1. A simplified power system model for the all-solid-state approach.








Sbrurg
S Sf Road



Arrester



Figure 3.2. A simplified power system model for the hybrid approach.

In both these models the resistive load controls the load current. Given the system voltage the load resistance is chosen so as to give the desired load current. The fault switch is used to simulate a ground fault. When this switch closes it shorts out the






39
resistive load and thus generates a fault condition. The system inductance controls the amount of fault current in the system. Assuming that the inductive reactance is much larger than the combined system and breaker resistance, the fault current is equal to the system voltage divided by the inductive reactance. The system resistance is included to account for the system resistive losses.

In the all-solid-state model the breaker is defined by a PCE and a surge arrester in parallel to the PCE. In this case the PCE is required to handle the full load current as well as interrupt the flow of current when necessary. The surge arrester is included to limit the transient recovery voltage across the PCE. During an interruption the PCE experiences a high voltage buildup due to its high interrupting speed. The surge arrester helps alleviate this voltage buildup by allowing the excess current flow through it when the PCE voltage reaches the surge arrester hold-off voltage. In the simulations of this work the surge arrester hold-off voltage is chosen to be one and a half times the system voltage.

In the hybrid model the breaker is defined by a mechanical switch in parallel to a PCE and a surge arrester. In this case the load current is carried by the mechanical switch whereas the PCE is only required to handle all the necessary interruptions. In order for the PCE to interrupt, the system current has to first be commutated from the mechanical switch to the PCE. This is done by opening the mechanical switch and turning on the PCE. If commutation is successful the PCE is then turned off to complete the interruption.

The steady-state-on instantaneous breaker current may be expressed in closed form by the relation

1br(t) = I,, sin (27rft - 0,n) (3.1-1)


where In and O, are given by






40

n = / ( + Ron (3.1-2) /(Rjo~a + Rs + Ron)p + (27rfL,)


eon =tan- 2,rfL (3.1-3) =Rload + Rs + Rpc e
for the all-solid-state model and by Ion = vV"s (3.1-4) V/(Road + R3)2 + (27rfL,)2


Oon = tan-1 ( 2rfL ) (3.1-5) Rload + Rs
for the hybrid model. It should be noted that the PCE current is equal to the breaker current in the all-solid-state model, whereas, it is equal to zero in the hybrid model.

The steady-state-off instantaneous breaker current may also be expressed in closed form and is given by the relation Ibr(t) = Ioff sin (2rft - 0of) (3.1-6) where Ioj and 0off are given by 101 = V arms 2 (3.1-7) /(Rload + Rs + Rce) + (2rfL,)2


Ooff = tan- ( 2rfLs (3.1-8) Road + Rs + Rpofe 3.-8 for both the all-solid-state and the hybrid models. In contrast to the steady-state-on model the PCE current is equal to the breaker current in both the all-solid-state and hybrid models.

During a fault condition in the all-solid-state model the PCE resistance changes with respect to time and thus the breaker current may not be expressed in closed form. Therefore, the describing system differential equation given by

dIbr(t) _ Road + Rs + Rp,(t) Ibr(t) + -V(t) (3.1-9) dt LL






41
is numerically solved using Runge-Kutta to determine the breaker current. On the other hand during a fault condition in the hybrid model none of the system elements is time dependent enabling a closed form solution given by the relation

Ibr(t) =I sin (2rft - Of

- [If sin (2rftf -Of) - I. sin (27rftf -0.)] exp ( rv- t) (3.1-10) In the above equation If, Of, and rf are given by


if v2 (3.1-11) /R, + (2irfL.)2



Of tan-1 (2rfL) (3.1-12)



Tf = La (3.1-13)


Furthermore, Ion and 9on are given by equations 3.1-4 and 3.1-5, respectively.

The turn-off and turn-on processes involve transients in the PCE resistance that bar a closed form solution to the system differential equation given by 3.1-9. Therefore, during either of these processes the breaker current is calculated by numerically solving equation 3.1-9.


3.2 Power System Simulator


The system models described in the previous section are combined with the device models of Chapter 2 to develop a system simulator which tests the PCE during steadystate and transient operation. Figure 3.3 shows a block diagram illustrating the main parts of the program. The source code of the program, written in Fortran, is given in the Appendix.









Read Input File


Figure 3.3. Block diagram of power system simulator.

The program first reads the input file which allows the user to specify the system level by setting the source voltage, the system resistance and inductance, and the load current. The user also specifies the type of breaker to be simulated, all-solid-state or hybrid. The user may also choose the PCE semiconductor material by assigning the material physical parameters which are required to calculate the energy bandgap, the intrinsic carrier concentration, the electron and hole mobilities, the thermal resistance, and the thermal capacitance. Furthermore, the user specifies the electrical length of the PCE, the desired leakage current, the junction optical power, as well as the temperature of the cooling environment (ambient temperature). Finally, the user selects the type of interruption to be simulated, fault interruption or load interruption.






43
The next step of the program is to calculate the PCE dimensions, and the steadystate electrical, optical, and thermal parameters. Using the steady-state electrical models the program calculates the device conduction area, the dark and illuminated PCE resistance, and the resistive losses under illuminated and dark conditions. Furthermore, using the optical models the program calculates the required bulk optical power to achieve the illuminated resistance, as well as the PCE saturation current. Finally, using the thermal model the program calculates the PCE temperature during both the illuminated and dark state.

Following the time independent calculations the program proceeds with the time dependent simulation. After it decides the type of breaker, all-solid-state or hybrid, to be tested it proceeds to simulate the steady-state-on condition using the system and device models for this state. These calculations continue until a fault or load interruption has to be initiated. The time for inducing a fault or a load interruption is controlled by the user. For the all-solid-state breaker a load interruption is simulated by simply turning-off the light source. The system and device turn-off models are being utilized for the simulated interruption. For the hybrid breaker an interruption is simulated by first commutating the current from the mechanical switch to the PCE, by opening the mechanical switch and turning on the PCE, and then turning off the light source. If a fault interruption is being simulated the program initiates a fault condition by closing the fault switch which eliminates the load. The program uses the system and device models for these calculations. For the hybrid breaker the fault current is allowed to build up and after several cycles an interruption is initiated near a current zero. On the other hand for the all-solid-state breaker an interruption follows the fault condition as soon as the fault is detected. The interruption process following a fault is simulated the same way a load interruption is simulated. During these time dependent calculations the program






44
calculates and outputs for each time step, the time, the source voltage, the breaker current, and the PCE current, voltage, resistance, power dissipation, and temperature.

Finally, the program outputs information relating to the design and experiment. This data includes, device dimensions, device dark and illuminated resistance, device dark and illuminated power dissipation, device optical requirements, and device temperature during steady-state-on and steady-state-off operation. Furthermore, information relating to the experiment includes the PCE instantaneous current when the interruption is initiated and the time interval for a successful interruption.


3.3 Designs and Results


This section presents breaker designs and simulation results for PCE-based allsolid-state and hybrid AC breakers operating at the substation level, the residential level, and the transmission level. Two semiconductor materials are used for these PCE-based breaker designs, primarily Si, and in a secondary way GaAs. Table 3.1 shows several empirical and physical parameters for Si and GaAs which are used by the power system simulator to evaluate the energy bandgap, the intrinsic carrier concentration, the electron and hole mobilities, the Auger recombination lifetime, the thermal resistance, and the thermal capacitance. These parameters were obtained from various sources which are also given in Table 3.1.

Designing the optimum PCE-based breaker for a specified application is not a trivial task. Improving one design parameter may weaken some other design parameter. Therefore, careful engineering design is required to obtain an optimum balance among the parameters of interest which include the hold-off voltage, the leakage current, the onstate maximum current, the on-state resistive losses, the on-state optical requirements, the turn-off time, and the device temperature during both steady-state and transient operation.






45
Table 3.1. Si and GaAs empirical and physical parameters which
are used in the power system simulation studies of this work.


Empirical and Physical Parameters


Silicon Gallium Arsenide Parameters
Value Ref. # Value Ref. # m*n (kg) 9.67x1031 [191 7.74x10-31 [20] m*p (kg) 5.38x10-31 [19] 1.00x10-30 [21] Eg(O) (eV) 1.17 [13] 1.519 [13] a (eV/K) 4.73x10-4 [13] 5.405x10-4 [13]
# (K) 636 [13] 204 [13]
/Inmax (cm2/V.s) 1330 [14] 8569 [6] Ynmin (cm2/V.s) 65 [14] 961 [6]
Nref (cm-3) 8.5x1016 [14] 9.646x1016 [6]
7 0.72 [14] 0.622 [6]
Pmax (cm2/V.s) 495 [14] 408 [6] YPmin (cm2/V.s) 47.7 [14] 7.5 [6]

Pref (cm-3) 6.3x1016 [14] 4.46x1017 [6]
b 0.76 [14] 0.397 [6]
kpee (W/m.K) 150 [10] 46 [10] ppc (kg/m3) 2328 [10] 5320 [10] cpPc (J/kg.K) 700 [10] 350 [10] CAu (cm6/s) 1.66x10-30 [22] 4.72x10-30 [23]

Furthermore, understanding how the user controlled parameters affect the calculated parameters is important since the designs are obtained on a trial and error basis using PSSPCE. The user controlled parameters include the electrical length, the leakage current, the dark resistivity, the generated bulk carrier concentration, the SRH recombination lifetime, the junction optical power, and the ambient temperature. The calculated parameters






46

include the hold-off voltage, the on-state maximum current, the on-state resistive losses, the on-state bulk optical power, the turn-off time, and the device temperature during both steady-state and transient operation. The hold-off voltage is controlled by the electrical length of the device. Increasing the electrical length of the device increases the hold-off voltage. The on-state resistive losses are controlled by the electrical length, the leakage current, the generated bulk carrier concentration, and the SRH recombination lifetime. Increasing the electrical length increases the on-state resistive losses. However, the on-state resistive losses are reduced with any increases in leakage current, generated bulk carrier concentration, or SRH recombination lifetime. The turn-off time is mainly controlled by the SRH recombination lifetime. Decreasing the SRH recombination lifetime reduces the turn-off time.

The on-state maximum current (saturation level) is controlled by the electrical length, the leakage current, the SRH recombination lifetime, the generated bulk carier concentration, and the junction optical power. The bulk optical power is controlled by the electrical length, the leakage current, the SRH recombination lifetime, and the generated bulk carrier concentration. Figure 3.4 shows the effect the electrical length has on the current saturation level as well as on the bulk optical power. Decreasing the length of the device increases the current saturation level and decreases the bulk optical power. Figure 3.5 shows the effect the leakage current has on the current saturation level as well as on the bulk optical power. Increasing the leakage current increases the current saturation level and decreases the bulk optical power. Figure 3.6 shows the effect the SRH recombination lifetime has on the current saturation level as well as on the bulk optical power. Increasing the SRH recombination lifetime increases the current saturation level and decreases the bulk optical power. Furthermore, increasing the generated carrier concentration increases both the current saturation level and the bulk

































0 2 4 6 8


Popt (watts) - bulk light


Figure 3.4. Plots of ISatp versus Phopt for various device lengths. For all three curves I�o p, =5 A and rSRH=5 / sec. For curve (a) L,,,=2 mm and Apce=4.3 cm2, for curve (b) L =5 mm and Apce=10.8 cm2, and for curve (c) Lre=10 mm and Ap,=21.6 cm . The plots are from simulations using PSS-PCE.




1200 1000


.~800~600





0






Popt (watts) - bulk light x104


Figure 3.5. Plots of ISatp versus pbopt for various device off-currents. For all three curves Lpce=5 mm and TSRH=5 /sec. For curve (a) Iffp=10 A and A We=21.6 cm2, for curve (b) Ilfe =5 A and Apre=10.8 cm2, and for curve (c) Iffpce=2 A and Ap,,=4.3 cm2. The plots are from simulations using PSS-PCE.


10 12














800






200

0
0 2 4 6 8 10 12 Popt (watts) - bulk light X104

Figure 3.6. Plots of Satpce versus Pbopt for various SRH recombination lifetimes. For all three curves Lp,=5 mm, A =10.8 cm2 and Ioff c=5
A. For curve (a) rSRH=50 psec, for curve (brSR=5 fisec, and for
curve (c) TSRH=l psec. The plots are from simulations using PSS-PCE.

optical power. In addition, as shown in Chapter 2 the current saturation level increases linearly with increases in junction optical power. Following are some sample designs for both the all-solid-state and hybrid approaches.


3.3.1 All-Solid-State Approach


Table 3.2 shows some sample designs for the PCE-based all-solid-state AC substation breaker. The PCE for this application is designed to hold off the system voltage rated at 15.5 kVrms, carry a continuous load current of 600 Arms, and interrupt a fault current of 12,000 Arms. The semiconductor material used for designs 1-4 is Si, whereas GaAs is used for design 5. Design 1 is designed to have the shortest electrical length that would theoretically hold off the system voltage. This allows for a smaller device which requires less optical power and exhibits lower on-state resistive losses. Thermal






49
Table 3.2. Sample designs for the all-solid-state substation breaker.



All-Solid-State Substation Breaker System Voltage: 15.5 kVrms L-L Continuous Load Current: 600 Arms Fault Current: 12,000 Arms


Design # 1 2 3 4 5

Material Si Si Si Si GaAs

Lpce (mm) 2 5 5 10 5 ArM (cm2) 4.3 10.8 4.3 4.3 4.3

Irffp% (Arms) 5 5 2 1 2.5xlO-4

rSRH (usec) 2 2 4 10 1 pbopt (kW) 1.0 2.5 2.5 3.0 1.5 Piopt (kW) 1.0 1.0 1.0 1.0 1.25 Rnpce (mQ) 9.72 21.2 14.4 22.3 17.3

Isatpee (A) 848 852 862 854 876

dunit (Ptm) 100 500 500 500 1

Tamb (K) 232 232 232 232 232
Tmaxc (K) 331 255 346 354 232


constraints, however, require that the depth of each unit for this design be less than the maximum allowed depth, in order to reduce the thermal resistance. Design 1 exhibits a worst case temperature rise of 99 K. The electrical length is increased in designs 2-4 in order to achieve more practical breakdown voltage to length ratios. An increase in the electrical length requires more bulk optical power and increases the on-state resistive losses. This is shown by design 2. The larger volume of design 2 allows for an increase in the depth of each unit which shows a worst case temperature rise of only






50
23 K. This small amount of temperature rise allows for a decrease in the conduction cross sectional area which reduces the leakage current, as well as an increase in the SRH recombination lifetime which reduces the on-state resistive losses. Design 3 shows these results along with the penalty for these improvements which is an increase of the worst case temperature rise from 23 K to 114 K. Design 4 has the longer and maybe the most practical electrical length for this application. The bulk optical power requirements are kept comparable to designs 2 and 3 by increasing the SRH recombination lifetime. This, however, reduces the speed of the device and also causes a worst case temperature rise of 124 K. Design 4 also exhibits the lowest leakage current among the Si-based designs. Note that the Si designs assume a dark resistivity of 40,000 il-cm at 300 K, a value limited by today's technology. In theory, intrinsic silicon at 300 K has a dark resistivity of about 800,000 Q-cm and thus, with technological improvements, the leakage current could be reduced by about one order of magnitude. Design 5 illustrates some possible advantages in using GaAs-based PCEs. The principal advantage is a reduction in leakage current which is several orders of magnitude less than the Si designs. Another advantage might be a faster switch for comparable device dimensions, optical power requirements, and on-state resistive losses. The GaAs device is a surface device and would require much more space to accommodate as compared with a Si device of the same dimensions. This might be a disadvantage in using GaAs. If, however, compactness is not an issue, having a surface device improves device cooling.

Table 3.3 shows some sample designs for the PCE-based all-solid-state AC residential breaker. The PCE for this application is designed to hold off the system voltage rated at 480 Vrms, carry a continuous load current of 100 Arms, and interrupt a fault current of 10,000 Arms. Similar to the substation designs the semiconductor material used for designs 1-4 is Si, whereas GaAs is used for design 5. Design 1 has the smallest






51
Table 3.3. Sample designs for the all-solid-state residential breaker.


All-Solid-State Residential Breaker System Voltage: 480 Vrms L-L
Continuous Load Current: 100 Arms Fault Current: 10,000 Arms


Design # 1 2 3 4 5

Material Si Si Si Si GaAs

Lee (mm) 0.2 0.5 0.5 0.5 0.5 Apce (cm2) 0.56 1.4 0.69 0.69 0.54
Ioffp (Arms) 0.2 0.2 0.1 0.1 1.0x0-5

TSRH (sec) 2 2 5 10 1
pbopt (W) 35 75 55 40 35 Piopt (W) 160 160 160 160 200
Ronpce (mQ) 3.58 8.02 6.23 5.18 7.84

Isatpee (A) 144 144 143 142 141

dunit (Pm) 200 500 500 500 1

Tamb (K) 273 273 273 273 273
Taxpce (K) 325 282 314 346 273


overall dimensions and thus requires the least amount of optical power and exhibits the least amount of on-state resistive losses. Design 2 shows the effects of increasing the electrical length of design 1. These effects include an increase in optical power requirements and an increase of the on-state resistive losses. Design 3 illustrates the effects of decreasing the conduction cross sectional area and increasing the SRH recombination lifetime of design 2. These effects include a decrease in leakage current, a decrease in optical power requirements, and a decrease of the on-state resistive losses. Design






52

Table 3.4. Sample designs for the all-solid-state transmission breaker.



All-Solid-State Transmission Breaker System Voltage: 230 kVrms L-L
Continuous Load Current: 1000 Arms Fault Current: 20,000 Arms

Design # 1 2 3 4 5

Material Si Si Si Si GaAs

LrM (cm) 2 5 5 10 5 Apm (cm2) 5.8 14.6 7.3 5.8 5.8
IOffp, (Arms) 10 10 5 2 5.0x10-4

TSRH( (sec) 1 1 2 5 1 pbopt (kW) 30 75 70 75 35 Piopt (kW) 1.7 1.7 1.7 1.7 2.0 RnP, (mS2) 66.4 143 97.3 170 77.8

Isatpee (A) 1460 1470 1490 1460 1410

dunit (pm) 100 500 500 500 1

Tmb (K) 232 232 232 232 232
Tmaxpee (K) 347 254 323 357 232


4 shows that the optical power requirements and on-state resistive losses of design 3 can be reduced even more by increasing the SRH recombination lifetime. Design 5 is a GaAs-based switch of comparable dimensions, optical power requirements, and on-state resistive losses as the Si-based devices. Similar to the substation designs the GaAs switch exhibits a reduction in leakage current which is several orders of magnitude less than the Si designs.






53

Table 3.4 shows some sample designs for the PCE-based all-solid-state AC transmission breaker. The PCE for this application is designed to hold off the system voltage rated at 230 kVrms, carry a continuous load current of 1000 Arms, and interrupt a fault current of 20,000 Arms. Again Si is used for designs 1-4, whereas GaAs is used for design 5. Design 1 has the smallest overall dimensions. Design 2 shows the effects of increasing the electrical length of design 1. Design 3 illustrates the effects of decreasing the conduction cross sectional area and increasing the SRH recombination lifetime of design 2. Design 4 exhibits the effects of increasing the electrical length, decreasing the conduction cross sectional area, and increasing the SRH recombination lifetime of design

3. Finally, design 5 shows the effects of designing a PCE using GaAs instead of Si.

Total power losses, including both optical and resistive, given as a percentage of total power being delivered might be one of the criteria utility companies use in deciding for or against PCE-based all-solid-state breakers. For the substation designs the total power losses range from 0.1-0.2 percent of the total per phase power being delivered. The residential designs show total power losses ranging from 0.8-1.1 percent of the total per phase power being delivered. The transmission designs exhibit total power losses ranging from 0.07-0.18 percent of the total per phase power being delivered. It appears that these percentage losses are low enough to allow consideration of the PCE-based all-solid-state breaker. The percentage losses are considerably less for the larger substation and transmission applications, thus favoring PCE-based all-solid-state breakers for applications at the higher system levels. However, this does not exclude applications at the lower system levels since the actual amount of total power losses is very small.

The designs given in Tables 3.2-3.4 were numerically tested during both steadystate and transient operation. All breakers performed successful interruptions under






54
any type of circumstances. Figures 3.7-3.11 show plots of various system and breaker parameters during a fault interruption at the substation level using design 4 of Table 3.2. Figure 3.7 shows a plot of the source voltage during steady-state-on, fault, and interruption. Figure 3.8 shows a plot of the breaker current, which is also the system current, during steady-state-on, fault, and interruption. In this sample case the fault occurs slightly before a current zero and results in a very large rate of change in system current. The current buildup is limited by the saturation value of the PCE which is larger than the rated continuous load current. When the system current reaches this saturation level an interruption is initiated and successfully completed as shown in Figure 3.8. Figure 3.9 shows in more detail the breaker current as well as the PCE current during this interruption. During part of the interruption the PCE current is less than the total breaker current. This is due to the high interrupting speed of the PCE which generates a large voltage buildup across the PCE. When this voltage reaches the breakdown limit of the surge arrester, it is clipped, and the excess breaker current flows through the surge arrester. Figure 3.10 illustrates the voltage buildup across the PCE during this interruption as well as the voltage clipping forced by the surge arrester. Figure 3.11 shows a plot of the PCE temperature during this interruption. The temperature rises very quickly from the on-state value of 232 K to a peak value of 295 K during interruption. The use of the surge arrester significantly aids in keeping the peak value below temperature levels that could induce a thermal runaway. The declining temperature immediately following the interruption signifies the success of the interruption. It should be noted that the waveforms of breaker and system parameters, during steady-state-on and interruption, for any system level using the all-solid-state breaker, are of the form shown in Figures 3.7-3.11.



































Time (msec)


Figure 3.7. Plot of V, during steady-state-on, fault, and interruption, for substation design #4 of Table 3.2. The plot is from numerical simulations using PSS-PCE.




1000 800 600 400 200 ___


Time (msec)


Figure 3.8. Plot of Ibr during steady-state-on, fault, and interruption, for substation design #4 of Table 3.2. The plot is from numerical simulations using PSS-PCE.



















600- Nb

~5w

400

'300

200 100

0
34.2 34.25 34.3 34.35 34.4 34.45 Time (msec) Figure 3.9. Plots of Ib, and Ie during interruption for substation design #4 of Table 3.2. The plots are from numerical simulations using PSS-PCE.


Time (msec)


Figure 3.10. Plot of Vje during interruption for substation design #4 of Table 3.2. The plot is from numerical simulations using PSS-PCE.









IL',


290280 270

~260

250 240

230
34.2 34.25 34.3 34.35 34.4 34.45 Time (msec)

Figure 3.11. Plot of Tpce during interruption for substation design #4 of Table 3.2. The plot is from numerical simulations using PSS-PCE.


3.3.2 Hybrid Approach


Tables 3.5-3.7 show sample designs for PCE-based hybrid breakers operating at the substation, residential, and transmission levels. The PCE is designed to operate under illuminated conditions for 100 microseconds before and after a current zero. Under this constraint the PCE is required to handle an on-state current equivalent to the instantaneous fault current at 100 microseconds after a current zero. Furthermore, since the PCE operates under illuminated conditions for very short periods of time the on-state PCE resistance is allowed to be as large as 500 milliohms, assuming such a large value does not negate current commutation. Allowing a larger on-state PCE resistance reduces the optical power requirements. In addition, the short operating window requires fast PCE switching speeds. A SRH recombination lifetime of one microsecond provides adequate switching speed and, therefore, this value is used in all the designs.






58

Table 3.5. Sample designs for the hybrid substation breaker.



Hybrid Substation Breaker
System Voltage: 15.5 kVrms L-L Continuous Load Current: 600 Arms Fault Current: 12,000 Arms

Design # 1 2 3 4 5

Material Si Si Si Si GaAs

L, (mm) 2 5 5 10 5 Atco (cm2) 0.86 2.2 1.1 2.2 1.7
Ioff p (Arms) 1 1 0.5 0.5 1.0x0-4

TSRH (usec) 1 1 1 1 1
pbpt (W) 90 450 200 800 100 PJopt (W) 800 800 800 800 900 t, (psec) 182 187 187 187 182
Rnpce (me2) 178 219 490 489 237

Isatr (A) 644 647 644 647 622

dunit (pm) 500 500 500 500 1

Tamb (K) 232 232 232 232 232

Tmpaxpce (K) 311 246 263 240 232

Table 3.5 shows sample designs for the PCE-based hybrid AC substation breaker. The PCE for this application is designed to hold off the system voltage rated at 15.5 kVrms and interrupt a fault current of 12,000 Arms. Silicon is used in designs 1-4 and gallium arsenide is used in design 5. Design 1 has the smallest overall dimensions and requires the least amount of optical power. Design 2 has a longer electrical length than design 1 and consequently requires more optical power. The longer length, however,






59
makes design 2 a better candidate for practical applications. Design 3 is an improvement of design 2 in terms of leakage current and optical power requirements. Design 4 shows the effect of increasing the electrical length of design 3 which mainly includes an increase in optical power requirements. Design 5, the GaAs-based PCE, exhibits a reduction in leakage current which is several orders of magnitude less than the Si designs. All designs exhibit low temperature rises mainly because current commutation and interruption occur near a current zero. Furthermore, because of the short conduction time the optical energy required by these designs is very small ranging from 0.178-0.325 joules.

Table 3.6 shows sample designs for the PCE-based hybrid AC residential breaker. The PCE for this application is designed to hold off the system voltage rated at 480 Vrms and interrupt a fault current of 10,000 Arms. The Si device of design 1 has the smallest overall dimensions. Design 2 is designed using a longer electrical length than design 1. Design 3 is an improvement of design 2 in terms of leakage current. Design 4 is designed using the longest electrical length. Design 5 illustrates the effects of using a GaAs-based PCE instead of a Si-based PCE. The bulk optical power in all five designs is significantly lower than the junction optical power and, therefore, increases in bulk optical power requirements due to larger overall device dimensions do not disadvantage the larger designs. Furthermore, decreases in total optical power requirements, which occur when allowing increases to the on-state PCE resistance, are insignificant and, therefore, the on-state PCE resistance in all five designs is allowed to be below 100 milliohms. The corresponding optical energy requirements for each interruption process using these designs is very small ranging from 0.14-0.16 joules. It is also worth noting that the maximum current handling capability of these designs is much larger than the continuous load current because of the large fault current and method of breaker operation.






60

Table 3.6. Sample designs for the hybrid residential breaker.



Hybrid Residential Breaker
System Voltage: 480 Vrms L-L
Continuous Load Current: 100 Arms Fault Current: 10,000 Arms


Design # 1 2 3 4 5

Material Si Si Si Si GaAs

Lp,, (mm) 0.2 0.5 0.5 1.0 0.5 Apee (cm2) 0.56 1.4 0.69 1.4 2.2
IOff (Arms) 0.2 0.2 0.1 0.1 4.0x10rsSRH ,usec) 1 1 1 1 1
pbopt (W) 2 10 10 40 10 PJopt (W) 700 700 700 700 800 tc (psec) 215 215 215 215 195

Ronpce (mQ) 75 93 96 96 24

Isatp. (A) 561 562 562 563 553

dunit (,am) 200 500 500 500 1

Tamb (K) 243 243 243 243 243

Tmaxpce (K) 313 264 286 254 243

Table 3.7 shows sample designs for the PCE-based hybrid AC transmission breaker. The PCE for this application is designed to hold off the system voltage rated at 230 kVrms and interrupt a fault current of 20,000 Arms. Again Si is used in designs 1-4 and GaAs is used in design 5. Design 1 has the smallest overall dimensions and requires the least amount of optical power. Increasing the electrical length of design 1 considerably increases the optical power requirements as shown by design 2. Design 3 improves upon






61

Table 3.7. Sample designs for the hybrid transmission breaker.



Hybrid Transmission Breaker
System Voltage: 230 kVrms L-L Continuous Load Current: 1000 Arms Fault Current: 20,000 Arms


Design # 1 2 3 4 5

Material Si Si Si Si GaAs

Lr, (cm) 2 5 5 10 5 APee (cm2) 1.2 2.9 1.5 2.9 2.3

Ioff (Arms) 2 2 1 1 2.0x104

rSRH ( sec) 1 1 1 1 1 pbopt (kW) 5 75 30 120 15 P0opt (kW) 1.4 1.4 1.4 1.4 1.5 tc (pssec) 173 173 173 173 173

Ronpce (mg) 384 196 461 461 183
Isatp. (A) 1140 1210 1160 1200 1050

dunit (rim) 200 500 500 500 1

Tamb (K) 232 232 232 232 232
Tmax Pce (K) 360 253 274 243 232


design 2 in terms of leakage current and optical power requirements by reducing the conduction cross sectional area and allowing a higher on-state resistance. Design 4 illustrates the effects of doubling the electrical length of design 3 which includes a quadrupling of optical power requirements. Design 5 shows the effects of using GaAs instead of Si to design the PCE-based breaker. The optical energy required per interruption process by these designs ranges from 1.3-24.3 joules.






62

The designs given in Tables 3.5-3.7 were numerically tested during both load and fault interruptions. The PCEs performed successfully for either of these type of interruptions. Figures 3.12-3.15 show plots of various system and breaker parameters during a fault interruption at the substation level using design 4 of Table 3.5. Figure 3.12 shows plots of the source voltage and breaker (system) current during steadystate-on and fault conditions. A line to neutral fault is initiated near a current zero resulting a large system current. The fault current is allowed to exist for several cycles before commencing the interruption process. It is worth noting the large phase shift that takes place between the source voltage and system current a few cycles following the fault occurrence. Figure 3.13 shows plots of breaker and PCE currents during current commutation and interruption. As described earlier and shown here current commutation begins within 100 microseconds prior to a current zero. After the current is transferred from the mechanical switch to the PCE, the PCE carries the fault current for approximately 200 microseconds and then proceeds with the interruption. Figure 3.14 shows a plot of the voltage across the PCE during current commutation and interruption. The voltage builds up across the PCE during the interruption and is clipped when it reaches the surge arrester breakdown voltage. Figure 3.15 shows a plot of the PCE temperature during current commutation and interruption. The temperature rise during this period is only 8 K. The declining temperature immediately following the interruption signifies the success of the interruption. The waveforms of breaker and system parameters, during steady-state-on, fault, current commutation, and interruption, for any system level using the hybrid breaker, are of the form shown in Figures 3.12-3.15.



































Time (msec)


Fipre 3.12. Plots of design #4 of Table 3.5.


Vr and Ibr during steady-state-on and fault for substation The plots are from numerical simulations using PSS-PCE.


-2W0

-40

-600

-800

-1000

-1200


-1400' C
86.65 86.7 86.75 86.8 86.85 869 86.95 87 Time (msec)

Figure 3.13. Plots of Ibr and Ip. during current commutation and interruption for substation design #4 of Table 3.5. The plots are from numerical simulations using PSS-PCE.

































86.65 86.7 86.75 86.8 86.85 86.9 86.95 87 Time (msec)

Figure 3.14. Plot of V.. during current commutation and interruption for substation
design #4 of Table 3.5. The plot is from numerical simulations using PSS-PCE.


zL'.-


239 F


235 -


86.65


86.7 86.75 86.8 86.85 86.9 86.95 87


Time (msec)

Figure 3.15. Plot of Tpm during current commutation and interruption for substation
design #4 of Table 3.5. The plot is from numerical simulations using PSS-PCE.


I . .il 4


Z---


lft et






65

3.4 Comparison of the PCE with GTO Thyristors


This section compares the PCE to conventional GTO thyristors. The PCE is a new type of semiconductor switching device which appears to have potential for power system applications. A large family of GTO thyristors, however, can already be found in use in power system applications. Therefore, a comparison between PCEs and GTO thyristors would be very informative in assessing the future of PCEs in power system applications, especially in the area of circuit protection.

As described earlier the PCE is a bilateral bulk device which can be turned on and off very rapidly, will conduct large currents, and hold off very high voltages. GTO thyristors are one-directional junction devices which can also be turned on and off very rapidly, and will conduct considerable amounts of current, but cannot hold off very large voltages. The PCE seems to have several inherent advantages over GTO thyristors. The PCE is a very simple device and, therefore, requires less fabrication processes and will probably cost less to fabricate than GTO thyristors. The PCE can be scaled to hold off any amount of voltage, whereas, GTO thyristors are limited by junction lengths to what amount of voltage they can hold off. Therefore, for very high voltage applications only one PCE is required to hold off the system voltage, whereas, many GTO thyristors in series are required to hold off the same voltage. Another advantage the PCE has over GTO thyristors is the ability to conduct current in both directions, and thus for bidirectional operation where one PCE can do the job, a combination of antiparallel GTO thyristors is required.

Table 3.8 gives a comparison between PCE-based breakers and GTO thyristorbased breakers at the substation level. Each breaker is required to hold off the system voltage when open, carry the continuous load current when closed, and interrupt a load or fault current when necessary. The table compares resistive and optical power losses






66
Table 3.8. Comparison of the PCE with GTO thyristors at the substation level.



System Voltage: 15.5 kWrms L-L
Continuous Load Current: 600 Arms
Fault Current: 12,000 Arms

Device: Si-PCE GaAs-PCE GTO Thyristors - 12 devices
(Model FG1500AI70 by Powerex)

Pei (kW) 3.5 6.0 14.4 Popt (kW) 2.0 2.75

Ioff (Arms) 5 2.5x10-4 0.150

toff (/zsec) 20 10 15

during on-state operation, leakage currents, and turn-off times. The PCE-based breakers are designs taken from Table 3.2. The Si PCE is design 1 of Table 3.2 and the GaAs PCE is design 5 of Table 3.2. The thyristor-based breaker is designed using 12 GTO thyristors which are currently available on the market. The thyristor-based breaker exhibits much higher resistive losses than both the Si and GaAs PCE-based breakers. However, the thyristor-based breaker displays no optical power losses which are inherent to the PCE-based breakers. Nevertheless, the total power losses exhibited by the PCEbased breakers are still less than the resistive losses displayed by the thyristor-based breaker. The leakage current for the Si PCE is much larger than what is allowed by the thyristors. This can be alleviated by using a GaAs-based PCE as illustrated by the results. The last parameter being compared is turn-off time. As shown by the table comparable turn-off times may be achieved using either PCEs or GTO thyristors.

In conclusion, it is safe to state that bulk photoconductive circuit elements have a promising future in power system applications, especially in the area of circuit protection.













CHAPTER 4
FABRICATION AND TESTING


This chapter describes the fabrication process and testing of low power prototype PCE-based breakers. Section one of this chapter presents a qualitative description of the fabrication process which was performed by Leslie Roberts [7] at the University of Florida's Micro Electronics Laboratories. Section two presents experimental test results for the PCE-based laboratory breakers. These results show PCE performance during both steady-state and transient operation.


4.1 Fabrication Process

This section describes the various processes involved in the fabrication of the low power PCE-based breaker. High resistivity p-type silicon wafers were used for the purposes of this work. The PCE is a bulk device and, therefore, a high resistivity semiconductor material is required in order to achieve large off to on resistance ratios. As discussed in Chapter 2 the choice of p-type material was made primarily because holes are less mobile than electrons.

Figure 4.1 shows a flowchart of the principal processes involved in the fabrication of the PCE-based breaker. The wafer to be processed goes through an initial cleaning in order to remove any surface contamination. Following this cleaning heavily doped p-type regions are formed on both wafer surfaces. These p-type regions are formed using ion implantation techniques. Boron is used for these implantations because of its well documented use. The dopant schedule is chosen to provide at least a 0.5 micron depth



































Bonding of wires

Figure 4.1. Flowchart of the principal processes involved
in the fabrication of the low power PCE-based breaker.

of heavily doped region in order to achieve a low sheet resistance and, therefore, a low contact resistance [7]. Following ion implantation the wafer is cleaned again and put through an annealing process which activates the implanted dopants.

The next step in the fabrication process is to metallize both sides of the wafer. Aluminum is deposited on top of the heavily doped regions using electron beam evaporation techniques. Photolithography is then used for opening the metallization windows and for etching the metallization pattern of the top surface of each device. The final devices have a top surface aluminum coverage of approximately fifteen percent of the total surface area. Following metallization an AR (anti-reflecting) coating is applied to






69
the top surface of the device. This reduces the reflectivity of the top surface which results in decreases of the optical power losses.

At this point in the fabrication process the wafer is diced into individual devices. Each die is then mounted to a standard (gold plate on copper) JEDEC TO-3 header. The header allows attachment of large leads for testing purposes. It also provides a good heat sink to the PCE, and it can be attached itself to an even larger heat sink for better device cooling. The final step in the fabrication process is the bonding of wires from the two terminals of the device to the header posts using one mil diameter gold wires. The end result of this process is a Si-pp-p photoconductive circuit element. Figure 4.2 shows the top view of the fabricated PCE-based breaker. The cross sectional view is shown in Figure 4.3.












Figure 4.2. Top view of fabricated PCE-based breaker.


metallic
contacts
P P..
+i


Figure 4.3. Cross-sectional view of fabricated PCE-based breaker.


Heat Sink metallic contact
Z/






70
The fabrication process just described does not include all the details involved in fabricating the laboratory PCE-based breaker. For a more detailed description as well as quantitative information of this process the reader is referred to Robert's work [7].


4.2 Device Testing


This section presents experimental test results for the PCE-based breakers which were fabricated at the University of Florida's Micro Electronics Laboratories. The PCE is tested under both dark and illuminated conditions as well as during both steadystate and transient operation. These tests have been very helpful in the development of the device models described in Chapter 2. Comparisons between experimental and numerical results validate theoretical expectations.

Figure 4.4 shows a schematic of the circuit being utilized to experimentally test the laboratory PCE-based breakers. The circuit consists of a 60 Hz voltage source in series with a PCE, a test resistor, and a load of light bulbs. Not part of the circuit, but required to illuminate the PCE, a 50 watt continuous wave Neodymium YAG laser is used to provide the optical power. In addition to the testing circuit and optical source several data acquisition equipment are required to record the experiments. For measuring the PCE voltage and current the LeCroy 9400A Digital Sampling Oscilloscope (DSO) is used. This scope provides a 100 megahertz sampling rate of two input channels with a storage capacity of 32,000 8-bit samples per channel. Stored data can be downloaded to a personal computer for easier processing of results. The speed and resolution of this scope is adequate for the experimental tests of this work. Optical power measurements are taken using a 50 watt power probe. Measuring the optical power being dissipated by the PCE is not a trivial task because some light is reflected by the top surface of the PCE. The absorbed optical power is estimated from measurements of the incident and reflected









+Vl~ _v2







VS Light Bulbs
pb
opt
Figure 4.4. Schematic of circuit being utilized to
experimentally test the laboratory PCE-based breaker.

beams. The temperature of the device is measured using a digital thermometer. This thermometer allows only steady-state temperature measurements.

The experimental test results of the laboratory PCE-based breakers are now presented. Several devices were tested during nonilluminated operation. These tests were performed using the circuit of Figure 4.4 with a source voltage of 120 volts RMS. The current versus voltage characteristic of each of the devices tested shows a nearly linear response. Furthermore, the off-state resistance of these PCEs is very close to that predicted by theory. Figure 4.5 shows the experimental nonilluminated current versus voltage characteristic of PCE #22. This plot demonstrates the ability of the PCE to hold off large voltages with small amounts of leakage current. PCE #22 has a vertical geometry similar to that shown in Figures 4.2 and 4.3 with a length of 0.5 mm and a cross-sectional area of 0.36 cm2. The bulk material of this device is composed of p-type silicon having a resistivity of 35,000 Q2-cm. Given these device parameters the theoretical off-state resistance is indeed close to the experimental result. As the voltage increases, however, there is a drop in the off-state resistance due to inadequate device cooling. An attempt to apply larger steady-state voltages induces thermal runaway in the









0.08

0.06

0.04 0.02
0.

-0.02

-0.04

-0.06

-200 -150 -100 -50 0 s0 100 150 200 vpce (volts)
Figure 4.5. Experimental nonilluminated current versus voltage characteristic of PCE #22. Device structure as in Figures 4.2 and 4.3 with Lpce=0.5 mm and Apce=0.36 cm2. device. Thermal runaway occurs when a large power dissipation in the device increases the temperature, which results in larger current. The larger current causes more power dissipation and the cycle continues until overheating results in the destruction of the device. Pulse testing [7], which reduces power dissipation, showed that the PCE was able to withstand in excess of 600 volts.

Several devices were tested during steady-state illuminated operation. The current versus voltage characteristic of each of the devices tested shows the theoretical expected linear and saturation regions. In the linear region the current is proportional to the applied voltage, whereas, in the saturation region the current is constant and independent of the applied voltage. Figure 4.6 shows the experimental illuminated current versus voltage characteristic of PCE #22 for an optical excitation of 11 watts. Figure 4.6 also shows the current versus voltage curve from numerical simulations using PC-1D. In the numerical simulations the same device dimensions as those of PCE #22 are used. Furthermore, the same optical power dissipation is used. Observation of the experimental and numerical














Experimatal


-0.6 -0.4 -0.2 0 0.2 0.4 0.6
Vpce (volts)


Figure 4.6. Comparison of experimental and numerical (Using
PC-ID) illuminated (Pbop=l1 W) current versus voltage characteristic
for PCE #22. In the numerical simulation rSRH=4 sec.


Vpce (volts)


Figure 4.7. Comparison of experimental and numerical (Using
PC-1D) illuminated (pbopt=24 W) current versus voltage characteristic
for PCE #22. In the numerical simulation TSRH=4 /ssec.






74
plots exhibited in Figure 4.6 shows identical saturation levels. This match was obtained when the SRH recombination lifetime in the numerical simulations was set to four microseconds. This result is important in that it provides a method for estimating a device's carrier lifetime.

The on-state resistance, in the linear region of both the experimental and numerical plots shown in Figure 4.6, is in the range of tenths of milliohms. The value of the experimental resistance, however, is larger than the expected numerical value. It appears this discrepancy may have two possible reasons. First, there might exist an undesirable high resistance in the contact regions due to the fabrication process. Experimental tests using some of the initial fabricated devices showed orders of magnitude larger than expected on-state resistances. Better care in fabricating the contact regions reduced drastically the on-state resistance. However, it is possible that some unwanted resistance in the contact regions of our devices still exists. A second reason for the larger experimental on-state resistance might be due to inaccuracies in the experiment itself. It is possible that high frequency noise which is generated by some of the equipment used in the experiments, and is of the order of the low voltages being measured, interferes with the accurate measurement of the device's electrical characteristics. The difference between the experimental and numerical value of the on-state resistance is not large enough to suspect a fundamental error in the analysis of photoconductive circuit elements.

Figure 4.7 shows the experimental and numerical current versus voltage plots for PCE #22 under increased optical excitation. An increase in the absorbed optical power is expected to increase the current carrying capability of the device and also reduce the on-state resistance in the linear region of the current versus voltage characteristic. These outcomes may be observed by comparing the experimental plots shown in Figures 4.6 and 4.7. Again the experimental result very closely matches the numerical result in the saturation region, whereas, some deviation exists in the linear region.






75
A required feature of the PCE-based breaker is the ability to interrupt large amounts of current. Several interruption experiments using the fabricated prototypes revealed very encouraging results. Several amps of current were able to be interrupted at very high speeds. Figure 4.8 shows the PCE current during and prior to a load interruption using PCE #22. As illustrated by this plot the PCE interrupts a load current, which is in excess of three amps RMS, in a matter of microseconds. It should be noted here that the switching time of the optical source is of the order of tenths of nanoseconds and thus does not degrade the measured interruption time. Figure 4.9 shows the corresponding PCE voltage for the load interruption shown in Figure 4.8. The voltage drop across the PCE is negligible prior to interruption, whereas, following the fast interruption there is a voltage build-up across the PCE equivalent to the source voltage as is expected.

Figure 4.10 shows in detail the PCE current during an experimental load interruption using PCE #22. A load interruption from a numerical simulation using PSS-PCE is also exhibited in Figure 4.10. In the numerical simulation the same device dimensions as those of PCE #22 are used. Furthermore, the same optical power dissipation is used. The SRH recombination lifetime is set to four microseconds, a value derived earlier. The testing scheme in the numerical simulation is similar to that used in the experiments. The same source voltage is applied, and the same steady-state load current is allowed to flow. The interruption in the numerical simulation is initiated at a point on the current waveform similar to that of the experimental interruption. Observation of the experimental and numerical plots exhibited in Figure 4.10 shows that the numerical result closely matches the experimental result, especially during the initial phase of the interruption. Since carrier recombination lifetime is the principal parameter affecting the numerical transient response, matching the numerical result to the experimental result via lifetime variations introduces another method for estimating a device's carrier



































-51
0 5 10 15 20 25 30 35 40 45 50 Time (msec)


Figure 4.8. Experimental load interruption using PCE #22. pbopt=24 W prior to interruption. Plot shows PCE current during both steady-state and interruption.




20W 150 100 50


-50
0



-100,


-150


-200
0 5 10 15 20 25 30 35 40 45 50 Time (msec) Figure 4.9. Experimental load interruption using PCE #22.
Plot shows PCE voltage for same interruption as in Figure 4.8.
















~25
2

1.5


015 Using PmS-Pa
0.5 Using PSS-PCE

-20 10 0 10 20 30 40 50 60 Tume (microeconds)

Figure 4.10. Comparison of experimental and numerical (Using PSS-PCE) load interruption using PCE #22. Pbopt=24 W prior
to interruption. In the numerical simulation rSRH=4 Psec.

recombination lifetime. The experimental result shows a larger leakage current at the tail end of the interruption process. This larger than expected leakage current is due to a significant increase in the temperature of the device during on-state operation. Better device cooling can alleviate this problem.

The experimental results described in this section are consistent with the theoretical analysis presented in Chapter 2. The tested devices exemplified the ability to hold off large voltages with low leakage currents, carry significant amount of load current with minimal resistive losses, and accurately interrupt a load current at very high speeds. Furthermore, comparisons between experimental and numerical results validate the device modeling of Chapter 2.














CHAPTER 5
CONCLUSIONS AND FUTURE RESEARCH


This study investigated the feasibility of the PCE for protective switching applications in AC power transmission and distribution circuits. Designs using both the all-solid-state and hybrid arrangements illustrate several potential advantages which include increased speed of operation, improved precision in interruption point, more compact designs, and greater overall reliability. Electrical, optical, and thermal models were developed for the PCE and were incorporated into a power system simulator which evaluates PCE performance during steady-state and transient operation. Simulation results at the substation, residential, and transmission levels show the feasibility of the PCE as an interruptor, especially at the higher substation and transmission levels if one is to consider the electrical losses involved in operating the PCE. In addition to theoretical designs and simulations, low power prototype PCE-based breakers were fabricated and tested for proof of concept. Experimental tests illustrate the ability of the PCE to interrupt significant amounts of current with precision and at high speeds. Furthermore, experimental results as well as results from the numerical simulator PC-1D, validate the device models and confirm theoretical design results.

More work, especially in the area of fabrication and testing, is probably required before the PCE could become an attractive alternative for various switching applications in the power utility industry. Fabrication and testing of devices for use at high current and voltage ratings is one possible area for future research. This task will require careful engineering design in order to achieve a robust device which could handle all






79
the strenuous electrical, optical, and thermal requirements of the PCE. Experimental work using two light sources, one for bulk carrier generation and one for junction carrier generation, is another area for future research. Such testing would illustrate the enormous savings in optical power requirements due to increased carrier generation in the junction areas. Fabrication of GaAs-based PCEs as an alternative to Si-based PCEs is yet another area for future research. As demonstrated by theoretical designs in this study, GaAs devices could reduce leakage currents and increase interruption speeds with comparable on-state electrical and optical losses as those exhibited by the Si devices. More theoretical work could be done in the area of device physics in order to further refine device models. For example, the transient electrical models could be refined to account for the effect of the transit time. Finally, more numerical experiments using more complex power system models could be made in order to test the PCE in a more realistic environment.













APPENDIX
SOURCE CODE FOR PSS-PCE





C
C POWER SYSTEM SIMULATOR C USING C PHOTOCONDUCTIVE CIRCUIT ELEMENTS
C
C (PSS-PCE)
C
C >>> VERSION 8 <<<
C



C
C Brief Description: The power system simulator (PSS) uses PCE C models (electrical, thermal, and optical) C to simulate load and fault interruptions. C The PCE is used in both the all solid C state approach as well as in the hybrid C approach.
C



C
C List of Variables:
C
C A : PCE area for current conduction C alfe : Exponent factor in electron mobility calculations C alfh : Exponent factor in hole mobility calculations C alpha : Constant in units of eV/K used in Eg calculation C beta : Constant in units of K used in Eg calculation








C c : Speed of light C CAu : Constant for calculating the Auger lifetime C Ce : Empirical constant relating Pjopt to Ipcemx C Cflt : Magnitude of current phasor during fault C cntr : Controls number of iterations C Con : Magnitude of current phasor during steady-state-on C convrg : Checks for convergence problems C Cp : Specific heat of semiconductor material C Ctpce : Thermal capacitance of PCE C d : Depth of PCE (same direction as light) C delint : Estimated interruption period (-20 X tau) C dt : Simulation time step (variable) C dtint: Actual interruption period C dunit: Depth of each PCE subunit C Ego: Bandgap at 0 degrees Kelvin C EgT : Bandgap of PCE material C f : Frequency of power source C F1 : Stores results of FUN C F2: Same as F1 C F3 : Same as Fl C F4: Same as Fl C FUN : Calculates system current using Runge-Kutta C FUN1 : Calculates PCE temperature using Runge-Kutta C Gel : Stores results of FUN1 C Ge2: Same as Gel C Ge3 : Same as Gel C Ge4 : Same as Gel C h : Planck's constant C Ibr : Breaker current in amps C icntr: Controls number of iterations C Ipce: PCE current in amps C Ipcemx : PCE saturation current in amps C Ipceof : PCE off-current in Arms C Ipceon: PCE on-current in Arms C Ipcetf: Current through PCE at tf C Ipceti: Current through PCE at ti C Ipceto : Current through PCE at to C k : Boltzmann's constant C kpce : Thermal conductivity of PCE C 1 : Length of PCE C La : Ambipolar diffusion length C lmd : Wavelength of optical source C Ls : System inductance








C Mmne : Minimum electron mobility C Mmnh : Minimum hole mobility C Mmxe : Maximum electron mobility C Mmxh : Maximum hole mobility C Mn : Electron density of states effective mass C Mo : Electronic rest mass C Mp : Hole density of states effective mass C Mun : Mobility of electrons in PCE C Munoff Mobility of electrons during off-state C Munon: Mobility of electrons during on-state C Mup : Mobility of holes in PCE C Mupoff: Mobility of holes during off-state C Mupon: Mobility of holes during on-state C Na: Acceptor doping concentration C Nc: Effective density of states in the conduction band C Ni Intrinsic carrier concentration C Nmax : Generated carrier concentration C No : Hole equilibrium concentration in PCE C Nrfe : Reference concentration for electron mobility calc C Nrfh : Reference concentration for hole mobility calc C Numdev : Number of PCE subunits in parallel (d/dunit) C Nv: Effective density of states in the valence band C one: one = 1.0
C phiflt: Phase of current phasor during fault C phion: Phase of current phasor during steady-state-on C pi : pi = 3.14159265 C Pjopt : Required optical power at the junctions C Po : Electron equilibrium concentration in PCE C Pop: PCE instantaneous optical power C Popt: Required optical power during on-state C Ppce: Instantaneous power dissipation by PCE C Ppceof: Average power dissipation by PCE during off-state C Ppceon: Average power dissipation by PCE during on-state C q : Electronic charge magnitude C qe : Quantum efficiency C Rbr: Total breaker resistance C rho: Density of semiconductor material C Rload: System load resistance C Rloadi: Saves value of Rload C Rm : Mechanical breaker resistance C Rmof: Mechanical breaker resistance during off-state C Rmon: Mechanical breaker resistance during on-state








C Rpce : PCE resistance C Rpceof: PCE resistance during off-state C Rpceon: PCE resistance during on-state C Rs : System resistance C Rtot : PCE bulk resistance + PCE junction resistance C Rtpce : PCE thermal resistance C six : six =6.0
C t : Simulation time C Tamb : Ambient temperature C tau : Recombination lifetime (includes Auger and SRH) C tauAu: Auger recombination lifetime C tauflt: Time constant for dumping after fault occurs C taum: Time constant for Rm on-to-off transition C tauSRH : SRH recombination lifetime C Temp: PCE temperature C tend: Tune when each simulation process is completed C tendi: Time when interruption is completed C testl : Choice of breaker: C testl=l >>> all solid state C testl=2 >>> hybrid C test2: Choice of simulation: C test2=l >>> only steady-state calculations C test2=2 >>> fault simulation C test2=3 >>> interrupt simulation C test2=4 >>> fault followed by interruption C test2=5 >>> Popt versus Ipce calculations C tf : Tune when fault occurs C ti : Time when interruption begins C to : Time when PCE turns on (hybrid breaker) C Toff: PCE temperature during off-state C Ton: PCE temperature during on-state C two: two = 2.0 C V : Volume of PCE C var(i) : Variables used for intermediate calculations C Vpce: PCE voltage in volts C Vpceof: PCE off-voltage in Vrms C Vpceon: PCE on-voltage in Vrms C Vs : Source voltage in volts C Vsat : PCE on-voltage at which Ipce saturates C Vsrms : Source voltage in Vrms C Vstf : Source voltage at tf C Vsti : Source voltage at ti








C Vsto: Source voltage at to C Vth: Thermal voltage C w : Width of PCE
C X : Vector storing t and Ibr C X1 : Vector storing PCE Temp C Y Vector storing intermediate steps of X C Yl Vector storing intermediate steps of X1
C



C
C MAIN PART OF PROGRAM - CONTROL UNIT
C



C
C Define program variables:
C
IMPLICIT DOUBLE PRECISION (A-Z)
INTEGER convrg
COMMON/blk01/Mmxe,Mmne,Nrfe,alfe,Mmxh,Mmnh,Nrfh,alfh COMMON/blkO2/Mun,Mup/blkO3/No,Po/blkO4/Nmax/blkO5/one
COMMON/blkO6/t/blkO7/to/blkO8/tau/blkO9/ti
COMMON/blk1/alpha,beta,Ego/blk 11/Mn,Mp/blkl2/h,k
COMMON/blk13fNa/blkl4/pi/blkl5/Temp/blkl6/two
COMMON/blkl7/Ctpce,Rtpce/blkl 8/Numdev/blkl9/Tamb/blk2O/Pop
COMMON/blk21/Ppce/blk22/dt/blk23/six/blk25/f
COMMON/blk26/Ls/blk27/Rbr/blk28/Rload/blk29/Rs/blk3O/Vsrms
COMMON/blk31/lbr/blk33/Cflt,phiflt,tauflt
COMMON/blk34/Con,phion/blk35/Mo/blk36/Ipceof,Ipceon
COMMON/blk37/Cp,kpce,rho/blk38/d/blk39/dunit/blk4O/
COMMON/blk4 l/Ce/blk42/delint/blk43/lmd/blk44/Pjopt/blk45/qe
COMMON/blk46/Rmof/blk47/Rmon/blk48/taum/blk49/tauSRH
COMMON/blk50/testl/blk5 1/test2/blk52/tf/blk53/Toff
COMMON/blk54/c/blk55/V,w/blk56/A/blk57/tauAu/blk58fTon
COMMON/blk59/Ppceof,Ppceon,Rpceof,Rpceon,Vpceof,Vpceon
COMMON/blk6O/Rloadi/blk61/lpcemx/blk62/Popt/blk63/q
COMMON/blk64/convrg/blk65/Ipce/blk66/Rpce,Vpce,Vs COMMON/blk67/Ipcetf,Vstf/blk68/lpceti,Vsti,tendi,dtint
COMMON/blk69/lpceto,Vsto/blk7O/CAu








C
C Open input and output files:
C
OPEN (UNIT=5,FILE='Pce8.in') OPEN (UNIT=6,FILE='Pcedev') OPEN (UN1T=7,FILE='Poplmx')
OPEN (UNIT=8,FILE='Pceiv') OPEN (UN1T=10,FILE='Time')
C
C Read data from input file:
C
CALL PCEIN
C
C Define various constants:
C
CALL PHYCON
C
C Check whether or not calculations of the PCE maximum C on-current versus optical power are desired:
C
IF (INT(test2).NE.5) GO TO 10
C
C Calculate and output the PCE maximum on-current versus C optical power:
C
CALL IMXPOP
GO TO 100
C
C Calculate the PCE dimensions as well as the PCE steady-state C conditions:
C
10 CALL PCEDIM
C
C Check whether or not simulation is desired:
C
IF (INT(test2).EQ.1) GO TO 100
C
C Calculate and output breaker parameters during system C on-state:
C
IF (INT(testl).EQ.1) THEN
CALL PSON1








ELSE
CALL PSON2
ENDIF
IF (convrg.EQ.1) GO TO 100
C
C Check whether or not fault simulation is desired:
C
IF (INT(test2).NE.2.AND.INT(test2).NE.4) GO TO 20
C
C Calculate and output breaker parameters during system C fault-state:
C
IF (INT(testl).EQ.1) THEN
CALL PSFLT1
ELSE
CALL PSFLT2
ENDIF
IF (convrg.EQ.1) GO TO 100
C
C Check whether or not interrupt simulation is desired:
C
20 IF (INT(test2).NE.3.AND.INT(test2).NE.4) GO TO 100
C
C Calculate and output breaker parameters during system C interruption-state:
C
IF (INT(testl).EQ.1) THEN
CALL PSINT1
ELSE
CALL PSINI2
ENDIF
C
C Output the given and calculated information regarding C the PCE:
C
100 CALL PCEDEV
C
C Stop execution of program:
C
STOP END












C
C Subroutine PCEIN is used to read the input file:
C
SUBROUTINE PCEIN
IMPLICIT DOUBLE PRECISION (A-Z)
COMMON/blkOl/Mmxe,Mmne,Nrfe,alfe,Mmxh,Mmnh,Nrfh,alfh
COMMON/blk04/Nmax/blk06/t/blk07/to/blk09/ti
COMMON/blkl/alpha,beta,Ego/blkl 1/Mn,Mp/blkl 3/Na/blkl9/Tamb
COMMON/blk25/f/blk26/Ls/blk29/Rs/blk30Nsrms
COMMON/blk36/lpceof,Ipceon/blk37/Cp,kpce,rho/blk381d
COMMON/blk39/dunit/blk4O/l/blk41/Ce/blk42/delint/blk43/Ixd
COMMON/blk44/Pjopt/blk45/qe/blk46/Rmof/blk47/Rmon
COMMON/blk48/taum/blk49/tauSRH/blk5O/testl/blk5 l/test2
COMMON/blk52/tf/blk53/Toff/blk7O/CAu
READ (5,10) Vsrms
READ (5,10) f
READ (5,10) Ipceof READ (5,10) Ipceon
READ (5,10) 1 READ (5,10) d
READ (5,10) dunit
READ (5,10) Mn READ (5,10) Mp READ (5,10) Ego
READ (5,10) alpha READ (5,10) beta
READ (5,10) Mmxe READ (5,10) Mmne
READ (5,10) Nrfe READ (5,10) alfe
READ (5,10) Mmxh READ (5,10) Mmnh
READ (5,10) Nrfh READ (5,10) alfh READ (5,10) rho READ (5,10) Cp
READ (5,10) kpce READ (5,10) Tamb READ (5,10) Toff
READ (5,10) Na








READ (5,10) Nmax
READ (5,10) qe
READ (5,10) tauSRH
READ (5,10) CAu READ (5,10) lmd
READ (5,10) Pjopt
READ (5,10) Ce READ (5,10) Ls READ (5,10) Rs
READ (5,10) Rmon READ (5,10) Rmof READ (5,10) taum READ (5,10) testl READ (5,10) test2
READ (5,10) t READ (5,10) tf READ (5,10) to READ (5,10) ti
READ (5,10) delint
10 FORMAT (52X,E13.6)
RETURN
END



C
C Subroutine PHYCON is used to define various constants:
C
SUBROUTINE PHYCON
IMPLICIT DOUBLE PRECISION (A-Z)
COMMON/blkO5/one/blkl2/h,k/blkl4/pi/blkl 6/two/blk23/six
COMMON/blk35/Mo/blk54/c/blk63/q
h = 0.663D-33
c = 0.2998D+09
q = 0.16D-18 k = 0.138D-22
Mo = 0.911D-30 pi = 3.141592654
one = 1.0 two = 2.0 six = 6.0 RETURN
END




Full Text

PAGE 1

THE APPLICATION OF PHOTOCONDUCTIVE SWITCHES IN AC CIRCUIT PROTECTION By CHRISTOS P. TRIAROS A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULnLLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 1991

PAGE 2

Copyright 1991 by Christos P. Triaros

PAGE 3

To My Father

PAGE 4

ACKNOWLEDGMENTS I would like to thank my family for their support and encouragement during this work. I am very grateful to my advisor, Dr. Dennis P. Carroll, for his guidance and support in completing this work. I extend a special thanks to Dr. F. Lindholm and Dr. A. Neugroschel for helpful discussions. I also thank Dr. G. Bosman, Dr. A. Domijan, and Dr. A. Varma for serving on my supervisory committee. I would also like to acknowledge the support of the Electric Power Research Institute (EPRI), the Rorida High Technology and Industry Council (FHTIC), and the National Science Foundation (NSF). IV

PAGE 5

TABLE OF CONTENTS ACKNOWLEDGMENTS iv LIST OF SYMBOLS vu ABSTRACT xii CHAPTERS 1 INTRODUCTION 1 1.1 Background 1 1.2 Objective 2 2 MODELING OF THE PCE 5 2.1 Device Physics 5 2.2 Electrical Models 20 2.3 Optical Models 29 2.4 Thermal Models 31 3 POWER SYSTEM SIMULATION STUDIES 37 3.1 System Modeling 37 3.2 Power System Simulator 41 3.3 Designs and Results 44 3.4 Comparison of the PCE with GTO Thyristors 65 4 FABRICATION AND TESTING 67 4.1 Fabrication Process 67 4.2 Device Testing 70 5 CONCLUSIONS AND FUTURE RESEARCH 78 V

PAGE 6

APPENDIX 80 REFERENCES Ill BIOGRAPHICAL SKETCH 114 VI

PAGE 7

LIST OF SYMBOLS Apce PCE area for current conduction Asink Heat sink area for thermal conduction Cau Empirical constant used to calculate the Auger recombination lifetime Ce Empirical constant used to calculate the PCE saturation current Thermal capacitance of PCE CfSink Thermal capacitance of heat sink c Speed of light (2.998x10* m/sec) CpP** Specific heat of PCE material Op®'** Specific heat of heat sink material D„ Electron diffusion coefficient Dp Hole diffusion coefficient dunit Depth of one PCE unit E Electric field (also symbol for energy) Eg Energy bandgap Eg(0) Energy bandgap at 0 K Emax Maximum hold-off voltage per unit length f Frequency of source voltage g Free carrier generation rate h Planck’s constant (6.63x10'^'* J-sec) hb Percentage of bulk optical power that is converted to heat vu

PAGE 8

he Convection coefficient hj Percentage of junction optical power that is converted to heat Ibr Breaker current ipee PCE current I°%ce PCE current under dark conditions P%ce PCE onstate saturation current Jn Electron current density Jp Hole current density k Boltzmann’s constant (1.38x10'^ J/K) kpce Thermal conductivity of PCE material ksink Thermal conductivity of heat sink material La Ambipolar diffusion length Lpce Electrical length of PCE Ls System inductance Lsink Length of heat sink m*n Electron density of states effective mass m*p Hole density of states effective mass N~a Ionized acceptor concentration N'^d Ionized donor concentration Na Acceptor concentration Nc Effective density of states in the conduction band Nref Empirical constant used in electron mobility calculations Nunits Number of units constituting one PCE Nv Effective density of states in the valence band viii n Free electron concentration

PAGE 9

Intrinsic carrier concentration ^ Equilibrium electron concentration Electron concentration on trap level Pgen Heat generated in PCE P*’opt Bulk optical power P^opt Junction optical power Pref Empirical constant used in hole mobility calculations P Free hole concentration Po Equilibrium hole concentration q Electronic charge (1.6x10'^^ C) Rioad Lx>ad resistance Pn Electron recombination rate Pp Hole recombination rate Ppce PCE resistance P°^pce PCE resistance under dark conditions P°"pce PCE resistance under illuminated conditions Ps System resistance Pt^'^ Thermal resistance between heat sink and cooling liquid Pt^® Thermal resistance of PCE PtSink Thermal resistance of heat sink Ptest Test resistor for experiment current measurements Tamb Ambient temperature Tpce PCE temperature T^“pce Worst case temperature rise in PCE Tsink Heat sink temperature IX

PAGE 10

t Time tf Time at which a fault occurs Vi Electrostatic potential V„ Electron quasi-Fermi potential Vp Hole quasi-Fermi potential Vpce Voltage across PCE V°^pce Voltage across PCE under dark conditions V^^^pce Minimum on-state voltage required across PCE to induce current saturation Vs Instantaneous value of source voltage Vs™® RMS value of source voltage Vth Thermal voltage w Width of one PCE unit AP*^pce Increase in PCE saturation current due to junction optical light An Excess optically generated electron (hole) carrier concentration a Empirical constant used in energy bandgap calculations /? Empirical constant used in energy bandgap calculations 7 Empirical constant used in electron mobility calculations S Empirical constant used in hole mobility calculations Excess electron (hole) carrier concentration during transient conditions Cs Permittivity Quantum efficiency A Wavelength of optical source /^n Electron mobility A^"max Maximum electron mobility A^^max Maximum hole mobility X

PAGE 11

/y" • p mm Minimum electron mobility Minimum hole mobility /Xp Hole mobility Ppce Density of PCE material A^sink Density of heat sink material a Total electron and hole conductivity T Carrier recombination lifetime '^Au Auger recombination lifetime TSRH Shockley-Read-Hall recombination lifetime Incident amount of photons per unit time XI

PAGE 12

Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy THE APPLICATION OF PHOTOCONDUCTIVE SWITCHES IN AC CIRCUIT PROTECTION by CHRISTOS P. TRIAROS May 1991 Chairman: Dr. Dennis P. Carroll Major Department: Electrical Engineering This study investigates the feasibility of the PCE (photoconductive circuit element) for protective switching applications in AC (alternating current) power transmission and distribution circuits. Designs using both the all-solid-state and hybrid arrangements illustrate several potential advantages over conventional protective devices, which include increased speed of operation, improved precision in interruption point, more compact designs, and greater overall reliability. Electrical, optical, and thermal models are developed for the PCE and are incorporated into a power system simulator which evaluates PCE performance during steady-state and transient operation. Simulation results at the substation, residential, and transmission levels demonstrate the feasibility of the PCE as an interruptor, especially at the higher substation and transmission levels. In addition to theoretical designs and simulations, low power prototype PCE-based breakers are fabricated and tested for proof of concept. Experimental tests exhibit the capability of the PCE to hold off large voltages, and interrupt large currents with precision and at high speeds. Furthermore, experimental results, as well as results from the numerical simulator PCID, are used to validate device models and confirm theoretical design results. XU

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CHAPTER 1 INTRODUCTION The photoconductive switch, often referred to as a photoconductive circuit element or PCE [1], may have great potential for power system applications. This study investigates the feasibility of photoconductive switches in AC circuit protection. Electrical, optical, and thermal models are developed for the PCE and are used in power system simulation studies in order to design and test PCE-based breakers. This work includes designs of all-solid-state as well as hybrid PCE-based breakers at the substation, residential, and transmission levels. It appears from these designs that the PCE may indeed have a future in circuit protection, especially at the higher system levels. Fabrication and testing of low power prototype PCE-based breakers is also part of this study. Experimental results validate theoretical expectations regarding the operation of the PCE. 1.1 Background A large class of switching appUcations in the electric utility industry involves the use of mechanical switches to interrupt or limit currents in power circuits [2]. There are numerous types of breakers for both AC and DC (direct current) circuits. These breakers vary in size, principle of operation, interrupting capacity, voltage rating, etc. However, they all have several undesirable properties in common. They all are relatively slow; they are unpredictable as to precisely when they will open or close; and their interrupting capacity is limited by complex arc phenomena. The PCE appears to be an attractive 1

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2 alternative or supplement to mechanical switchgear that could eliminate or minimize these undesirable features. The PCE consists basically of semi-insulating semiconductor material, which can be made highly conductive through applying laser or other optical excitation that contains photon energy exceeding the semiconductor energy gap. The PCE can be tinned on and off very rapidly [3], will conduct large currents, and will hold off very high voltages, yet can be made relatively compact. It is also a bilateral device, which is an advantage over other semiconductor switches for AC applications, and the voltage and current rating of a single unit can be easily scaled to meet the application. In principle, it is possible in a single device to switch high voltages (up to megavolts at 1(X) kV per cm length) and high currents (up to megamperes at 20 kA per cm width) with more precision and higher efficiency than with any other technology [4]. This switch can be designed to close faster, with less inductance, and less relative jitter than is possible with other technologies. Thus components of circuit interruptors can be made simpler, more efficient, and more compact. The large specific heat and the excellent thermal conductivity of photoconductive materials make the technology applicable to many highpower applications. Furthermore, operation of PCE switches at cryogenic temperatures can improve the optical absorption depth, carrier mobility, and mechanical properties of the device material [5]. In spite of its apparent advantages as a power switch, the PCE as yet is relatively unexplored for power system applications. 1.2 Objective The principal objective of this study is to investigate the feasibility of the PCE for protective switching applications in AC power transmission and distribution circuits. To achieve this goal, it is planned to develop electrical, thermal, and optical models that

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3 accurately describe the behavior of the PCE under both steady-state dark and illuminated conditions, as well as during transient operation. These PCE models will aid in the design of PCE-based breakers. The performance of these designs will be evaluated with the help of equivalent circuit calculations and by the use of digital computer simulations. Performance parameters will include: circuit interruption time, blocking voltages, interruption capacity, device losses, light source requirements, heat dissipation, and cooling methods. Furthermore, low power prototype PCE-based breakers wiU be fabricated and tested for proof of concept. Chapter 2 describes the modeling of the PCE. The first section of this chapter presents the semiconductor equations that govern the physical behavior of the PCE. These equations are incorporated into the one-dimensional device simulator PCID [6], which is used to numerically model the current versus voltage characteristic of the PCE. The second section gives a description of the electrical models which predict the current versus voltage characteristic of the PCE during both steady-state and transient operation. The third section presents the optical models which are used to calculate the optical power required by the PCE in order to conduct the desired steadystate load current. The last section of Chapter 2 describes the thermal models which predict the temperature of the PCE during both steady-state and transient operation. Chapter 3 evaluates the performance of PCE-based breakers during both steadystate and transient operation. The PCE is evaluated in both the all-solid-state approach and the hybrid approach. The first section of this chapter describes the power system models being utilized to test the PCE. The second section describes the power system simulator which incorporates the system and device models to numerically evaluate PCE performance. The third section presents breaker designs and simulation results for various applications. These applications include breakers operating at the substation

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4 level, the residential level, and the transmission level. The last section of Chapter 3 compares the PCE to various GTO (Gate-Tum-Off) thyristors. Chapter 4 describes the fabrication process and testing of low power prototype PCE-based breakers. The first section of this chapter presents a qualitative description of the fabrication process which was performed by Leslie Roberts [7] at the University of FloridaÂ’s Micro Electronics Laboratories. The second section presents experimental test results for the PCE-based laboratory breakers. These results show PCE performance during both steady-state and transient operation.

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CHAPTER 2 MODELING OF THE PCE This chapter describes the modeling of the photoconductive circuit element. The first section presents the semiconductor equations that govern the physical behavior of the PCE. These equations are incorporated into the one-dimensional device simulator PCID [6], which is used to numerically model the ciurent versus voltage characteristic of the PCE. The second section gives a description of the electrical models which predict the current versus voltage characteristic of the PCE during both steady-state and transient operation. The third section presents the optical models which are used to calculate the optical power required by the PCE in order to conduct the desired steady-state load current. The last section of this chapter describes the thermal models which predict the temperature of the PCE during both steady-state and transient operation. 2.1 Device Physics Figure 2.1 shows a typical PCE which consists of an intrinsic photoconductive material, and metal/heavily doped regions which aid in obtaining ohmic contacts to the switch. An optical source is used to increase the conductivity of the PCE by generating electron-hole pairs in the bulk of the material. This section ascertains how the metal/heavily doped regions (contacts) influence the carrier profiles, the electric field profile, and the current versus voltage characteristic. 5

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6 Light Source metallic contact .+ x-direction > Figure 2.1. A typical photoconductive circuit element consisting of an intrinsic photoconductive material and metal/heavily doped regions. 2.1.1 The Governing Semiconductor Equations Photogeneration, recombination, trapping, drift, and diffusion [8] are the main physical processes governing electrons and holes in a photoconductor. The system of governing equations for these processes consists of the electron and hole transport equations, the electron and hole continuity equations, PoissonÂ’s equation, and the kinetic rate equation. The one-dimensional time-dependent form of these equations is presented here. The electron and hole transport equations are written as These equations define the electron and hole current densities in terms of a drift com(2.1-1) and (2.1-2) ponent and a diffusion component. The drift component, which arises from carriers moving under the influence of an electric field, is proportional to the mobility, carrier

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7 concentration, and electric field. The diffusion component, which arises from carriers moving due to a carrier gradient, is proportional to the diffusivity, and the positional rate of change of carrier concentration. The carrier concentrations may further be related to the quasi-Fermi and electrostatic potentials by the following expressions: These differential equations describe the time dependent rate of change of electron and hole concentrations per unit volume. This temporal rate of change of carrier concentration is given in terms of the divergence of the current density, the per unit volume generation rate, and the per unit volume recombination rate. The first term accounts for all carriers entering and leaving the volume through drift and diffusion, the second term accounts for all carriers being generated in the volume by optical and thermal excitation, and the last term accounts for all carriers recombining in the volume by various recombination processes including Shockley-Read-Hall recombination. Auger recombination, and surface recombination. PoissonÂ’s equation is written as ( 2 . 1 3 ) and ( 2 . 1 4 ) The electron and hole continuity equations are written as dn(x,t) IdJn(x^t) dt q dx + g{x,t) Rn{x,t) ( 2 . 1 5 ) and ( 2 . 1 6 )

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8 This equation relates the electric field to the charge density. The charge density is given in terms of mobile carriers and localized (immobile) charge. The mobile carriers are electrons in the conduction band and holes in the valence band. The localized charge is introduced by impurities which emit and/or capture electrons. The term on the left of the first equality is introduced to indicate that the electric field is the negative gradient of the electrostatic potential. The kinetic rate equation for a single trap level is written as Rp{x,t) (2.1-8) This equation gives the temporal rate of change of the electron concentration on the trap, which is equal to the difference in the recombination rates of electrons and holes. The six coupled differential equations just described are very complicated to use in the power system simulation studies. Therefore, a device simulator, which solves these equations, needs to be used to numerically model the PCE. From these numerical models simple analytical models may be derived for use in the power system simulation studies. Various device simulators [6] have been developed to numerically solve these equations. PCID is one such device simulator. The following part of this section presents the results from this device simulator which aided in developing several of the analytical models described in this chapter. 2.1.2 Numerical Simulations Using PC-ID This part of the section numerically models the electrical and optical behavior of the PCE during its steady-state operation. Figure 2.2 shows the PCE, in its illuminated state with an applied voltage, as used by PCID for the numerical simulations being presented. The PCE consists of high resistivity bulk material to which ohmic contacts are formed. An ohmic contact may be formed by depositing metal on implanted or

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9 diffused heavily doped regions [9]. In principle, an ohmic contact should have negligible resistance relative to the bulk resistance of the device [10]. In this section it is shown that this is not always the case. Figure 2.2. The PCE, in its illuminated state with an applied voltage, as used by PCID for the numerical simulations presented in this section. High resistivity p-type semiconductors are used as bulk material for the PCEs under study. The principal reason of p-type over n-type bulk material comes from the fact that the value of hole mobility is lower than the value of electron mobility for the semiconductors under study. Therefore, other things being equal the dark resistance for the p-type material will be larger than the dark resistance of the n-type material. Two semiconductor materials are being investigated in this work, primarily Si (silicon), and in a secondary way GaAs (gallium arsenide). The heavily doped regions which aid in obtaining ohmic contacts to the PCE also form junctions in the device. Since the PCE will be used in an AC environment there are, in principle, only two ways of forming contacts which would affect differently the operation of the device. One way is to make both heavily doped regions of the same type, that is, either p-type or n-type. This configuration always has one of the two junctions forward biased and the other reverse biased, independent of voltage polarity. The other way is to make one heavily doped region p-type and the other heavily doped

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10 region n-type. This configuration always has both junctions either forward biased or reverse biased depending on the voltage polarity. The former of the two ways was investigated and following is a discussion on the effects of the reverse biased junction. A Si-p‘‘'p“p'*' structure was used to numerically model the effects of the reverse biased junction on the current versus voltage characteristic, the carrier profiles, and the electric field profile. For the sign convention shown in Figure 2.2 the p^p” junction is reverse biased whereas the p'/p'*’ junction is forward biased. Figure 2.3 shows a plot of current versus voltage for this device from numerical simulations using PCID. The current does not indefinitely increase linearly with increases in voltage, as might be expected for an ideal photoconductor, but instead saturates when the applied voltage reaches some value that depletes the reverse biased junction of carriers. Figure 2.5 shows the carrier concentration being depleted in the vicinity of the reverse biased junction for a voltage bias of 0.8 volts. The corresponding high electric field related to this depleted region is shown in Figure 2.7. This saturation effect, which limits the current carrying capabilities of the PCE, may be alleviated by generating more carriers at the reverse biased junction. One way of achieving this is to apply a second light source that would only generate carriers at the junction. Figure 2.4 shows the result of adding a second light source to the simulated case shown in Figure 2.3. The current saturation level increases from approximately 200 amps to approximately 900 amps at the expense of only 900 watts of optical power. This is due to the increase in generated carriers at the reverse biased junction, which require a higher applied voltage to deplete. Figure 2.6 shows the carrier concentration not being depleted at the reverse biased junction for the same voltage bias as in Figure 2.5. The corresponding low electric field for this case is shown in Figure 2.8.

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11 Figure 2.3. Plot of Ipce versus Vpce for a Si-p'‘'p p"*” structure with Lpce=l mm and Apce=4.5 cm^. Other parameters include P*’opt=1.8 kW @ 1.06 ^m, a=10 cm~\ An=1.37xl0^'^ cm'^ Tpce=300 K, /i„=592 cm2/(V.s), fXp=201 cm^/(V.s), and tsrh= 5 ^sec. The plot is from numerical simulations using PCID. Figure 2.4. Plot of Ipce versus Vpce for same device structure and parameters as in Figure 2.3 with the addition of pjopt=900 W @ 800 nm. The plot is from numerical simulations using PCID.

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12 Position (mm) Figure 2.5. Plot of hole concentration versus position for a voltage bias of 0.8 volts. Same device structure and parameters as in Figure 2.3. The plot is from numerical simulations using PC-ID. > .s 'w' g 1 s o o a: lOM 1019 101 » 1017 ; 10161 — 0.2 0.2 0.4 0.6 Position (mm) 0.8 1.2 Figure 2.6. Plot of hole concentration versus position for a voltage bias of 0.8 volts. Same device structure and parameters as in Figure 2.4. The plot is from numerical simulations using PCID.

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13 500 -500 <»*s I b -1000 3 o £ g -1500 -2000 -2500 -3000' ' ' ' ' ' ' -0.2 0 0.2 0.4 0.6 0.8 1 1.2 Position (mm) Figure 2.7. Plot of electric field versus position for a voltage bias of 0.8 volts. Same device structure and parameters as m Figure 2.3. The plot is from numerical simulations using PCID 0.4 0.6 Position (mm) Figure 2.8. Plot of electric field versus position for a voltage bias of 0.8 volts. Same device structure and parameters as in Figure 2.4. The plot is from numerical simulations using PCID,

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14 Simplified models that can predict the observed current saturation phenomenon have been developed for use in the power system simulation studies. Several simulation experiments using PCID have been analyzed in order to develop these simplified analog models. The results from these models are in good agreement with the device simulation results if the length of the device is several times larger than the ambipolar diffusion length. As a rule of thumb a factor of ten should be adequate. Figures 2.9, 2.11, 2.13, 2.15, and 2.17 include some of the current versus voltage plots from various simulation experiments. Figures 2.10, 2.12, 2.14, 2.16, and 2.18 show the respective saturation current versus junction light relationships. Results for Si-based devices, as well as GaAs-based devices are shown in these figures. It should be noted that because of device symmetry the current voltage relationships shown in these figures remain unchanged for negative applied voltages. Simulation experiments using PC-ID indicate that the saturation voltage, which is defined as the applied voltage at which the current saturates, depends on several device parameters. Such parameters include device length, recombination lifetime, and optical power to the reverse biased junction. The saturation voltage changes proportionally with respect to device length and junction optical power and is inversely proportional with respect to recombination lifetime. The expression for calculating the saturation voltage is given in section 2.2. Furthermore, these numerical experiments show that changes in the applied junction light give linear changes in the current saturation level. These experiments also suggest that this linear relationship is independent of any of the deviceÂ’s bulk parameters. This constant linear relationship may be observed in the slope of the saturation current versus junction light plots, which is approximately the same for the various plots of each semiconductor material.

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15 Figure 2.9. Plots of Ipce versus Vpce for a Si-p'^p'p'^ structure with Lpce=l nun and Apce=4.5 cm^. Other parameters include P‘’opt=l-8 kW @ 1.06 /xm, a=10 cm“^ An=1.36xl0^^ cm~^, Tpce=300 K, /xn=592 cmV(V.s), )Up=207 cm^(V.s), and tsrh=5 /xsec. The plots are from numerical simulations using PCID. Figure 2.10. Plot of P®^pce versus P^opt for same device structure and parameters as in Figure 2.9. The plots are from numerical simulations using PCID.

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16 Figure 2.11. Plots of Ipce versus Vpce for a Si-p‘*'p“p''' structure with Lpce=2 mm and Apce=4.5 cm^. Other parameters include P*’opt=l-8 kW (a) 1.06 //m, o:=5 cm~^, An=3.8xlO^^ cm“^, Tpce=300 K, /Xn=876 cm^/(V.s), /xp=313 cm^/(V.s), and tsrh=2 fj,sec. The plots are from numerical simulations using PCID. Figure 2.12. Plot of P“pce versus P^opt for same device structure and parameters as in Figure 2.11. The plots are from numerical simulations using PC-ID.

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17 Figure 2.13. Plots of Ipce versus Vpce for a Si-p'^p'p'^ structure with Lpce=4 mm and Apce=9 cm^. Other parameters include P*’opt=l-8 kW @ 1.06 //m, o:=2 cm“^ An=2.36xl0^^ cm“^, Tpce=300 K, ^n=971 cmV(V.s), ^p=350 cm^/(V.s), and rsRH=5 //sec. The plots are from numerical simulations using PCID. Figure 2.14. Plot of P^pce versus P^opt for same device structure and parameters as in Figure 2.13. The plots are from numerical simulations using PCID.

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18 Figure 2.15. Plots of Ipce versus Vpce for a GaAs-p‘''p“p‘'’ structure with Lpce=0.5 mm and Apce=25 cm^. Other parameters include P'’opt=500 W @ 830 nm, a=10 cm"\ An=3.3xl0^'* cm“^, Tpce=300 K, /in=8353 cm^/(V.s), ^p=386 cm^/(V.s), and rsRH=100 nsec. The plots are from numerical simulations using PCID. Figure 2.16. Plot of P^pce versus P^opt for same device structure and parameters as in Figure 2.15. The plots are from numerical simulations using PCID.

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19 Figure 2.17. Plots of Ipce versus Vpce for a GaAs-p'^p"p'*' structure with Lpce=2 mm and Apce=4 cm^. Other parameters include P*’opt=3.2 kW @ 830 nm, a=5 cm“^ An=1.8xl0^^ cm“^, Tpce=300 K, //n=6588 cm^/(V.s), //p=320 cm^/(V.s), and rsRH=l fJ-scc. The plots are from numerical simulations using PCID. Figure 2.18. Plot of P^pce versus P^opt for same device structine and parameters as in Figure 2.17. The plots are from numerical simulations using PCID.

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20 2.2 Electrical Models This section presents the electrical modeling of the PCE for steady-state as well as transient operation. The device geometry for these models is shown in Figure 2.19. The PCE consists of several units put in parallel. This is done because of limitations to this penetration depth. For example, the best effective penetration depth that can be achieved in silicon at room temperature is approximately one millimeter [10] when using a NeodymiumYag laser which has a wavelength of 1.06 micrometers. The direction of the bulk light is chosen to be transverse to the direction of current. Therefore, the electrical length, Lpce, of the device is independent of the light penetration depth and is primarily determined by the required hold-off (blocking) voltage of the switch. The applied static electric field is limited, in principle, by the breakdown voltage of the bulk semiconductor, which for silicon is approximately [10] in the penetration depth of light which limits one of the dimensions of the device, dunit. 'pee Figure 2.19. Conceptual geometry of the PCE. y/cm ( 2 . 2 1 )

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21 Other mechanisms, such as surface flashover, may reduce Emax below the value indicated in (2.2-1). Careful engineering design, however, can alleviate the influence of such mechanisms [11]. The width, w, of each unit which depends on the total cross sectional area, Apce, and the number of units, Nunits. being used may be expressed as follows: w = ipce Nunitsdunit (2.2-2) The total cross sectional area depends on the imposed requirements for leakage current. The number of units is chosen so as to give a compact design. 2.2.1 Steady-State-Off Model Under dark conditions the bulk material dominates the operation of the PCE. The applied voltage is distributed uniformly across the PCE, and under the assumption of Lpce»La there is no carrier gradient in the bulk of the device. Therefore, the electron and hole transport equations may easily be rewritten to give the following equation which treats the PCE as a resistor which behaves according to Ohm’s law. Rpce = ^pce^ The combined electron and hole conductivity is given by the following expression: cr = q{fXnrio + UpPo) (2.2-4) This nonilluminated conductivity depends strongly on temperature because of the law of mass action, pgUo = n?, in which nj depends on temperature [2]. This temperature dependence for p-type material is given by the following expressions [12]: Na + y/N[+^ Po = 2 (2.2-5)

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22 where, and, Po \/ NcNv exp iV, =< ^‘KTYlj^hTpc^ 1.5 ( 2 . 2 6 ) (2.2-7) (2.2-8) 1.5 ’I (2.2-9) The energy bandgap shown in equation 2.2-7 is also temperature dependent. Thurmond [13] expressed this temperature dependence by the following equation: cx.T^ Eg(Tpce) = Eg(0) ( 2 . 2 10 ) Furthermore, the electron and hole mobilities depend on the carrier densities. The following equations which were empirically derived by Caughey and Thomas [14] should be adequate for this work. Pn — Pmax Pmin 1 + {N/N^^fY + pI (2.2-11) Pp = P P l^max 1^ mtn I P ' r^m (2.2-12) 1 + (P!Pr,ff The parameters /z"max. p^ min, Nref, 7 , p^^msa., P^min, Pref. and S, are empirical constants dependent on the type of carrier and semiconductor material. Variables N and P take on the value of electron and hole carrier densities, respectively.

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23 Figure 2.20. PCE current-voltage relationship under steady-state illumination. 2.2.2 Steady-State-On Model Figure 2.20 shows the current versus voltage characteristic of the PCE for the steady-state illuminated condition. The PCE is treated as a resistor which behaves according to the following equations: Rpce = . for •'pee — ''pee — Vpce (2.2-13) for Vpce > VpfJ (2.2-14) for Vpce< -V/ce' (2.2-15) Equation 2.2-13 describes the linear region of the currentvoltage relationship. In this region the bulk material dominates the operation of the PCE. The applied voltage is distributed uniformly across the PCE, and under the assumption of Lpce»La there is no earner gradient in the bulk of the device. Therefore, the electron and hole transport p _ Vpce ^r>ce '^pce D _ Vpce ^pce ^pce

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24 equations may easily be rewritten to give equation 2.2-13, where the combined electron and hole conductivity is given by the following expression: = ^[(/^n + Mp)An + + tipPo] (2.2-16) This illuminated conductivity is dominated by the photogenerated excess carrier concentration. The temperature dependent electron and hole equilibrium carrier densities and the carrier density dependent electron and hole mobilities are given by equations 2.2-5 through 2.2-12. Equations 2.2-14 and 2.2-15 describe the saturation regions of the current-voltage relationship. In this regions the reverse biased junctions dominate the operation of the PCE. The expressions for the saturation voltage and saturation current, which were empirically derived from the numerical simulations of the previous section, are given below: Lpce La PnT + p 3 T Ce-^pce^ (2.2-17) TTSat rsat _ *pce (2.2-18) The first term on the right of the equality of equation 2.2-17 determines the saturation voltage without an applied junction light. The second term determines the increase in saturation voltage when junction light is applied. Equation 2.2-18 determines the maximum current carrying capability of the PCE which is simply the saturation voltage divided by the PCE resistance in the linear region. The constant Ce gives the amount of junction light required to increase the saturation current by one ampere and is determined from the device simulation studies. The ambipolar diffusion length may be expressed in terms of carrier mobihties and recombination lifetime as follows [9]: l ^'^PnPpyth Y Pn + Pp (2.2-19)

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25 The recombination lifetime which includes both the Shockley-Read-Hall and Auger recombination processes is given by equations 2.2-22 and 2.2-23. Figures 2.21-2.26 show several plots of current versus voltage for various device parameters. These figures show that the results from the models given in this section are in good agreement with the results from the numerical simulations using PCID. 2.2.3 Turn-Off Model The turn-off model describes the transition from the on-state conductivity to the off-state conductivity. This transition occurs when the light source is interrupted, resulting in the decay of the excess carrier concentration from its initial steady-state value to zero. The expression for this transient may be derived from the continuity equations. Under the assumption of a long device, Lpce»La, which results in constant current densities in the bulk of the device, the solution to the continuity equations is given by the following expression: ^n = Anexp^— — ^ (2.2-20) The combined electron and hole conductivity may thus be written as <7 -f -|fijiHg -jfJ'pPol (2.2—21) The recombination lifetime which accounts for both the Shockley-Read-Hall and Auger recombination processes is given by the following equation: ’ = + ’!«)' ( 2 2 22 ) Shockley-Read-Hall recombination is usually dominant. This process involves transitions between the conduction and valence bands and deep level traps. At higher electron and hole concentrations, the impact-Auger process starts to compete for dominance with the Shockley-Read-Hall mechanism. Auger recombination utilizes a third mobile particle.

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26 Figure 2.21. Comparison of Ipce versus Vpce from analytical models (PSS-PCE) and numerical simulations (PCID) for a Si-p'^p~p'^ structure with Lpce=l mm and Apce=4.5 cm^. Other parameters include P*’opt=l-8 kW @ 1.06 o;=10 cm~\ An=1.36xl0^'^ cm“^, Tpce=300 K, //„=592 cm^/(V.s), /xp=207 cm^/(V.s), and tsrh=5 /xsec. Figure 2.22. Comparison of Ipce versus Vpce from analytical models (PSS-PCE) and numerical simulations (PC-ID) for same device structure and parameters as in Figure 2.21 with the addition of PJopt=900 W @ 800 nm.

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27 Figure 2.23. Comparison of Ipce versus Vpce from analytical models (PSS-PCE) and numerical simulations (PCID) for a Si-p'^p'p'^ structure with Lpce=2 mm and Apce=4.5 cm^. Other parameters include P‘’opt=l-8 kW @ 1.06 fxm, a=5 cm~^ An=3.8xlO^^ cm“^, Tpce=300 K, /in=876 cm%V.s), //p=313 cm^/(V.s), and tsrh=2 ^sec. Figure 2.24. Comparison of Ipce versus Vpce from analytical models (PSS-PCE) and numerical simulations (PCID) for same device structure and parameters as in Figure 2.23 with the addition of PJ'opt=135 W @ 800 nm.

PAGE 40

28 Figure 2.25. Comparison of Ipce versus Vpce from analytical models (PSS-PCE) and numerical simulations (PCID) for a Si-p‘^p~p'^ structure with Lpce=4 mm and Apce=9 cm^. Other parameters include P*’opt=l-8 kW @ 1.06 //m, a=2 cm"^ An=2.36xl0^^ cm"^, Tpce=300 K, //n=971 cm^/(V.s), ^^=350 cm^/(V.s), and tsrh=5 ^sec. Figure 2.26. Comparison of Ipce versus Vpce from analytical models (PSS-PCE) and numerical simulations (PCID) for same device structure and parameters as in Figure 2.25 with the addition of Pjopt=90 W @ 800 nm.

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29 rather than phonons, to conserve energy. Thus the Auger recombination lifetime may be expressed as [15] 1 " C'^„An2 (2.2-23) 2.2.4 Tum-On Model The tum-on model describes the transition from the off-state conductivity to the on-state conductivity. This transition occurs when light is shined on the device resulting in the increase of the excess carrier concentration from its initial zero value to its final steady-state value. This transient may be expressed by the following equation: 6n = An 1 — exp (2.2-24) The derivation of this equation follows similar arguments to the derivation of the tiun-off model. Furthermore, the total conductivity and the recombination lifetime are expressed by equations 2.2-21 and 2.2-22, respectively. 2.3 Optical Models This section describes the optical models which are used to calculate the optical power required by the PCE in order to conduct the desired steady-state load current. Two models are required for this purpose, a bulk optical model which controls the PCE’s illuminated conductivity, and a junction optical model which controls the PCE’s maximum current-carrying capability. 2.3. 1 Bulk Optical Model The bulk optical model is used to calculate the optical power necessary to uniformly generate, in the bulk of the material, a desired amount of excess carrier concen-

PAGE 42

30 tration. The expression for this model can be derived as follows. Each photon which penetrates the surface has an energy E = he T J/ photon (2.3-1) The number of photons per second is related to the bulk optical power by the relation = — ^ photons /s E (2.3-2) The generation rate of electron-hole pairs, given some quantum efficiency, is given by T](f> Lpce Apee EHP/cm'\s (2.3-3) From the continuity equations the steady-state generation rate may also be expressed as An 9 = (2.3^) By combining equations 2.3-1 through 2.3-4, the bulk optical power is given by the relation pb _ ^opi h cLpce Apee^'f^ rjXT (2.3-5) 2.3.2 Junction Optical Model The junction optical model is used to calculate the optical power necessary, in the vicinity of the reverse biased junction, to increase the current saturation level by some desired amount. The expression for this model, which is derived empirically from the numerical simulations of section 2.1, is given by the relation P4, = C.A/“‘ (2.3-6) The empirical constant Ce, which is independent of any of the device’s bulk parameters, gives the amount of junction light required to increase the saturation current by one ampere. For silicon Ce=1.25 W/A, and for gallium arsenide Ce=1.45 W/A.

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31 2.4 Thermal Models This section presents the methodology and thermal models for cooling the PCE. Two cooling methods are described in this section — cooling by heat sinking and cooling by direct immersion. The thermal models are used in the power system simulation studies to predict the temperature of the PCE during both steady-state and transient operation. Temperature is an important parameter in the operation of the PCE especially during the turn-off period. During turn-off inadequate cooling will induce a thermal runaway in the PCE which will have the effect of an unsuccessful interruption. 2.4.1 Cooling By Heat Sinking This cooling method involves the PCE being deposited on a heat sink and the heat sink being surrounded by a cooling liquid or gas. Figure 2.27 shows the relationship between device geometry and temperature. Heat that is generated in the device due to resistive power dissipation and/or optical power dissipation is either stored in the device or conducted out of the device and into the heat sink. In turn heat conducted into the heat sink is either stored in the heat sink or conducted toward the heat sink surfaces where it is removed by convection. Tamb Figure 2.27. Relationship between device geometry and temperature for thermal model using cooling by heat sinking.

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32 Under the assumptions that the top surface of the device is thermally insulated, that heat is conducted from the top surface of the device toward the bottom surface of the heat sink (x-direction), that heat is removed only at the bottom surface of the heat sink, and that a linear temperature gradient exists in the device, a one-dimensional thermal model is adequate to predict the temperature of the PCE. The differential equations describing this simplified thermal model are given below [16,17]: P gen — dT, , pee j . n pce-^pce I f'pce-^pce-^pce^p ce ^Ppee dt (2.4-1) ^sink-^sink (2.4-2) dx ” -^aTTlO/ l rStriK-^SinK-^ ^StUK'^p Equation 2.4—1 equates the heat generated in the PCE to the sum of heat conducted out of the PCE and into the heat sink and heat stored in the PCE. Equation 2.4—2 equates the heat conducted into the heat sink to the sum of heat convected out of the heat sink and heat stored in the heat sink. For computer simulation purposes equations 2.4-1 and 2.4-2 are discretized in the x-direction. For simplicity only three nodes are used. Figure 2.27 shows these nodes as being related to the geometries of the device and heat sink. Node 1 is taken to be the top surface of the PCE, node 2 is taken to be the interface between the PCE and the heat sink, and node 3 is taken to be the bottom of the heat sink. The discretized versions of equations 2.4—1 and 2.4—2 are given by the following expressions: ^ _ Ti T2 , ^pcedTpce X^npti — I genj^^e dt (2.4-3) where. ^2 7a ^ ^3 Tqmb , Qsink^jin^ j^stnk Jlcnv + t Pgen = I^ePpce + -f hjP^p^ (2.4-4) ( 2 . 4 5 )

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33 _ T A ^pce — Hpce -^ pce -^ pce^p (2.4-^) C/'"*' = PsinkLaink^sinkCp sink (2.4-7) Rr = ^pce ^ h A ^pce^pce (2.4-8) j^ink ^sink ^sink-^sink (2.4-9) = ( hcAs ^ nk ) -1 (2.4-10) Tpce = TI + T2 (2.4-11) Tsink = T2 + T3 (2.4-12) Using the relationships of equations 2.4-11 and 2.4-12 and the assumption that the heat conducted out of the PCE is equal to the heat conducted into the heat sink, equations 2.4—3 and 2.4—4 may be rewritten in terms of only Tpce and Tsink as follows: Tpce Tg{jii~ >dTn o -^pce •‘•sink ^ ^pce'^-'-pce 4 gen — n > Rti dt (2.4-13) Tpce — Tsink Tsink Tamb , Tgink ~ T, Rn Rt2 + Rt:^ pee ^ ^sink dTsijih dt where, Rt\ = R^e ^ J^sink (2.4-14) 2 (2.4-15)

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34 Rt2 = nr (2.4-16) -R<3 = Jisink (2.4-17) Figure 2.28 shows the equivalent circuit model of equations 2.4-13 and 2.4-14. Note that heat is equivalent to current in an electrical circuit, temperature is equivalent to voltage in an electrical circuit, and thermal resistances and capacitances are equivalent to resistors and capacitors in an electrical circuit, respectively. Figure 2.28. Equivalent circuit for thermal model using cooling by heat sinking. 2.4.2 Cooling By Direct Immersion This cooling method involves the PCE being directly immersed into a cooling fluid. This technique eliminates the thermal resistance involved in heat sinking a device, and thus more heat may be extracted from the PCE. Work done by Iversen (Coriolis Corporation) and Whitaker (University of California) [18] shows a process using such a technique which results in very low junction to fluid thermal resistances and very high heat flux dissipation capabilities.

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35 Figure 2.29 illustrates the relationship between device geometry and temperature, for one of the units of the PCE, for this cooling method. Heat that is generated in the volume of each unit is removed by forced convection at the two siufaces associated with the width and length of each unit. Assuming uniform heat generation in the volume of each unit, equal heat removal rates at the two surfaces associated with the width and length of each unit, and no heat removal at the remaining surfaces, then a one-dimensional thermal model is adequate to predict the temperature of the PCE. Furthermore, under these assumptions heat is conducted toward the heat removal surfaces via a temperature gradient within the unit. Therefore, the hottest plane related to the width and length of each unit is midpoint of the depth. The temperature at this plane is taken to be the PCE temperature. Figure 2.29. Relationship between device geometiy and temperature for thermal model using cooling by direct immersion. The differential equation describing this thermal model is given below [16,17]: (2.4-18) where. p — gen — ^pce ^pce + ^bPppt ~h ^jPppt (2.4-19)

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36 ^pce Ppce(^ ‘^dunitLpce * ~ 2 (2.4-20) j^pce _ dunit 2 kpce W Lpce (2.4-21) Equation 2.4-18 equates the heat generated in half the volume of each unit to the sum of heat stored in half the volume of each unit and heat conducted out of half the volume of each unit. Figure 2.30 shows the equivalent circuit for this thermal model. Figure 2.30. Equivalent circuit for thermal model using cooling by direct immersion.

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CHAPTER 3 POWER SYSTEM SIMULATION STUDIES This chapter evaluates the performance of PCE-based breakers during both steadystate and transient operation. The PCE is evaluated in both the allsolid-state approach and the hybrid approach. In the all-solid-state approach the breaker is composed primarily of the PCE which is used to carry the load current at all times as well as interrupt the load or fault current when required. In the hybrid approach the breaker is composed of a PCE in parallel with a mechanical switch. The mechanical switch is used to carry the load current, whereas the PCE is used to interrupt the load or fault current. The first section of this chapter describes the power system models being utilized to test the PCE. The second section describes the power system simulator which incorporates the system and device models to numerically evaluate PCE performance. The third section presents breaker designs and simulation results for various applications. These applications include breakers operating at the substation level, the residential level, and the transmission level. The last section compares the PCE to various existing GTO thyristors. 3.1 System Modeling This section describes the power system models being utilized to test the PCE. Two types of models are being presented, the all-solid-state model and the hybrid model. Figure 3.1 shows the circuit representation of the all-solid-state model. The system is defined by a single phase source, and its relating series resistance and inductance. 37

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38 connected to a purely resistive load. The breaker, which is composed of a PCE in parallel with a surge arrester, is connected between the source and the load. Furthermore, a fault switch is connected in parallel to the resistive load. Figure 3.2 shows the circuit representation of the hybrid model. The main difference between this model and the all-solid-state model is the addition of the mechanical switch in parallel to the PCE. In both these models the resistive load controls the load current. Given the system voltage the load resistance is chosen so as to give the desired load current. The fault switch is used to simulate a ground fault. When this switch closes it shorts out the

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39 resistive load and thus generates a fault condition. The system inductance controls the amount of fault current in the system. Assuming that the inductive reactance is much larger than the combined system and breaker resistance, the fault current is equal to the system voltage divided by the inductive reactance. The system resistance is included to account for the system resistive losses. In the all-solid-state model the breaker is defined by a PCE and a surge arrester in parallel to the PCE. In this case the PCE is required to handle the full load current as well as interrupt the flow of current when necessary. The surge arrester is included to limit the transient recovery voltage across the PCE. During an interruption the PCE experiences a high voltage buildup due to its high interrupting speed. The surge arrester helps alleviate this voltage buildup by allowing the excess current flow through it when the PCE voltage reaches the surge arrester hold-off voltage. In the simulations of this work the surge arrester hold-off voltage is chosen to be one and a half times the system voltage. In the hybrid model the breaker is defined by a mechanical switch in parallel to a PCE and a surge arrester. In this case the load current is carried by the mechanical switch whereas the PCE is only required to handle all the necessary interruptions. In order for the PCE to interrupt, the system current has to first be commutated from the mechanical switch to the PCE. This is done by opening the mechanical switch and turning on the PCE. If commutation is successful the PCE is then turned off to complete the interruption. The steady-state-on instantaneous breaker current may be expressed in closed form by the relation hr(t) = Ion sin {2tt ft Oon) ( 3 . 1 1 ) where Ion and ^on are given by

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40 Ion — V2V/ yj {Rload + -Rs + -Rpce) + {^'^fl'sf 0f)n — ij3«IX for the all-solidstate model and by Ion — -1 2TTfLs Rload + -Rs -IRpce . ^v: Oqyi — i)3>rx -1 { \ (3.1-2) (3.1-3) (3.1^) (3.1-5) ^R-load ”1” Rg for the hybrid model. It should be noted that the PCE current is equal to the breaker current in the all-solid-state model, whereas, it is equal to zero in the hybrid model. The steady-state-off instantaneous breaker current may also be expressed in closed form and is given by the relation hr{t) = /o//sin 9off) where loff and ^off are given by hu = V2K rma )J (^Rload + R5 + Rpci^ + (2-KfLgy 9 f f — tan -1 27T/L, (3.1-6) (3.1-7) (3.1-8) ^ Rload + Rs + RpU ^ for both the all-solid-state and the hybrid models. In contrast to the steadystate-on model the PCE current is equal to the breaker current in both the all-solid-state and hybrid models. During a fault condition in the all-solid-state model the PCE resistance changes with respect to time and thus the breaker current may not be expressed in closed form. Therefore, the describing system differential equation given by dlhr{t) __ Rload Rg "f" Rpctif) j, 1 yr / ~nr r. (3.1-9)

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41 is numerically solved using Runge-Kutta to determine the breaker current. On the other hand during a fault condition in the hybrid model none of the system elements is time dependent enabling a closed form solution given by the relation Ibr(t) =If sin {27 t ft 9 f)[if sin {2-Kftf Of) Ion sin (2nftf 6 on)] exp In the above equation If, 0f, and rf are given by tf-t \ (3.1-10) / If = V2v;^^ yjR-i + (3.1-11) Of = tan ^ (3.1-12) (3.1-13) Furthermore, Ion and ^on are given by equations 3.1-4 and 3.1-5, respectively. The turn-off and tum-on processes involve transients in the PCE resistance that bar a closed form solution to the system differential equation given by 3.1-9. Therefore, during either of these processes the breaker current is calculated by numerically solving equation 3.1-9. 3.2 Power System Simulator The system models described in the previous section are combined with the device models of Chapter 2 to develop a system simulator which tests the PCE during steadystate and transient operation. Figure 3.3 shows a block diagram illustrating the m ain parts of the program. The source code of the program, written in Fortran, is given in the Appendix.

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42 Figure 3.3. Block diagram of power system simulator. The program first reads the input file which allows the user to specify the system level by setting the source voltage, the system resistance and inductance, and the load current. The user also specifies the type of breaker to be simulated, all-solid-state or hybrid. The user may also choose the PCE semiconductor material by assigning the material physical parameters which are required to calculate the energy bandgap, the intrinsic carrier concentration, the electron and hole mobilities, the thermal resistance, and the thermal capacitance. Furthermore, the user specifies the electrical length of the PCE, the desired leakage current, the junction optical power, as well as the temperature of the cooling environment (ambient temperature). Finally, the user selects the type of interruption to be simulated, fault interruption or load interruption.

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43 The next step of the program is to calculate the PCE dimensions, and the steadystate electrical, optical, and thermal parameters. Using the steady-state electrical models the program calculates the device conduction area, the dark and illuminated PCE resistance, and the resistive losses under illuminated and dark conditions. Furthermore, using the optical models the program calculates the required bulk optical power to achieve the illuminated resistance, as well as the PCE saturation current. Finally, using the thermal model the program calculates the PCE temperature during both the illuminated and dark state. Following the time independent calculations the program proceeds with the time dependent simulation. After it decides the type of breaker, all-solid-state or hybrid, to be tested it proceeds to simulate the steady-state-on condition using the system and device models for this state. These calculations continue until a fault or load interruption has to be initiated. The time for inducing a fault or a load interruption is controlled by the user. For the all-solid-state breaker a load interruption is simulated by simply tuming-off the light source. The system and device turn-off models are being utilized for the simulated interruption. For the hybrid breaker an interruption is simulated by first commutating the current from the mechanical switch to the PCE, by opening the mechanical switch and turning on the PCE, and then turning off the light source. If a fault interruption is being simulated the program initiates a fault condition by closing the fault switch which eliminates the load. The program uses the system and device models for these calculations. For the hybrid breaker the fault current is allowed to build up and after several cycles an interruption is initiated near a current zero. On the other hand for the all-solidstate breaker an interruption follows the fault condition as soon as the fault is detected. The interruption process following a fault is simulated the same way a load interruption is simulated. During these time dependent calculations the program

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44 calculates and outputs for each time step, the time, the source voltage, the breaker current, and the PCE current, voltage, resistance, power dissipation, and temperature. Finally, the program outputs information relating to the design and experiment. This data includes, device dimensions, device dark and illuminated resistance, device dark and illuminated power dissipation, device optical requirements, and device temperature during steady-state-on and steadystate-off operation. Furthermore, information relating to the experiment includes the PCE instantaneous current when the interruption is initiated and the time interval for a successful interruption. 3.3 Designs and Results This section presents breaker designs and simulation results for PCE-based allsolid-state and hybrid AC breakers operating at the substation level, the residential level, and the transmission level. Two semiconductor materials are used for these PCE-based breaker designs, primarily Si, and in a secondary way GaAs. Table 3.1 shows several empirical and physical parameters for Si and GaAs which are used by the power system simulator to evaluate the energy bandgap, the intrinsic carrier concentration, the electron and hole mobilities, the Auger recombination lifetime, the thermal resistance, and the thermal capacitance. These parameters were obtained from various sources which are also given in Table 3.1. Designing the optimum PCE-based breaker for a specified application is not a trivial task. Improving one design parameter may weaken some other design parameter. Therefore, careful engineering design is required to obtain an optimum balance among the parameters of interest which include the hold-off voltage, the leakage current, the onstate maximum current, the on-state resistive losses, the on-state optical requirements, the turn-off time, and the device temperature during both steady-state and transient operation.

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45 Table 3.1. Si and GaAs empirical and physical parameters which are used in the power system simulation studies of this work. Empirical and Physical Parameters Parameters Silicon Gallium Arsenide Value Ref. # Value Ref. # m*n (kg) 9.67x10-31 [19] 7.74x10-31 [20] (kg) 5.38x10-31 [19] l.OOxlO-30 [21] Eg(0) (eV) 1.17 [13] 1.519 [13] a (eV/K) 4.73x10^ [13] 5.405x10-^ [13] ^(K) 636 [13] 204 [13] (cm^A^.s) 1330 [14] 8569 [6] (cm^A^.s) 65 [14] 961 [6] Nref (Cm'^) 8.5x101^ [14] 9.646x101^ [6] 7 0.72 [14] 0.622 [6] M^max (cm^A^.s) 495 [14] 408 [6] (cm^A^.s) 47.7 [14] 7.5 [6] Pref (Cm-^) 6.3x101^ [14] 4.46x1011 [6] 8 0.76 [14] 0.397 [6] kpce (W/m.K) 150 [10] 46 [10] Ppce (kg/m^) 2328 [10] 5320 [10] CpP"« (J/kg.K) 700 [10] 350 [10] Cau (cm^/s) 1.66x10-30 [22] 4.72x10-30 [23] Furthermore, understanding how the user controlled parameters affect the calculated parameters is important since the designs are obtained on a trial and error basis using PSSPCE. The user controlled parameters include the electrical length, the leakage current, the dark resistivity, the generated bulk carrier concentration, the SRH recombination lifetime, the junction optical power, and the ambient temperature. The calculated parameters

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46 include the hold-off voltage, the on-state maximum current, the on-state resistive losses, the on-state bulk optical power, the turn-off time, and the device temperature during both steady-state and transient operation. The hold-off voltage is controlled by the electrical length of the device. Increasing the electrical length of the device increases the hold-off voltage. The on-state resistive losses are controlled by the electrical length, the leakage current, the generated bulk carrier concentration, and the SRH recombination lifetime. Increasing the electrical length increases the on-state resistive losses. However, the on-state resistive losses are reduced with any increases in leakage current, generated bulk carrier concentration, or SRH recombination lifetime. The turn-off time is mainly controlled by the SRH recombination lifetime. Decreasing the SRH recombination lifetime reduces the turn-off time. The on-state maximum current (saturation level) is controlled by the electrical length, the leakage current, the SRH recombination lifetime, the generated bulk carrier concentration, and the junction optical power. The bulk optical power is controlled by the electrical length, the leakage current, the SRH recombination lifetime, and the generated bulk carrier concentration. Figure 3.4 shows the effect the electrical length has on the current saturation level as well as on the bulk optical power. Decreasing the length of the device increases the current saturation level and decreases the bulk optical power. Figure 3.5 shows the effect the leakage current has on the current saturation level as well as on the bulk optical power. Increasing the leakage current increases the current saturation level and decreases the bulk optical power. Figure 3.6 shows the effect the SRH recombination lifetime has on the current saturation level as well as on the bulk optical power. Increasing the SRH recombination lifetime increases the current saturation level and decreases the bulk optical power. Furthermore, increasing the generated carrier concentration increases both the current saturation level and the bulk

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47 Figure 3.4. Plots of P® pee versus P^’opt for various device lengths. For all three curves I°®pce=5 A and tsrh=5 /xsec. For curve (a) Lpce=2 mm and Apce=4.3 cm^, for curve (b) Lpce=5 mm and Apce=10.8 cm^, and for curve (c) Lpce=10 mm and Apce=21.6 cm^. The plots are from simulations using PSS-PCE. Figure 3.5. Plots of P%ce versus P^’opt for various device off-currents. For all three curves Lpce=5 mm and tsrh=5 ^sec. For curve (a) I°^pce=10 A and Apce=21.6 cm^, for curve (b) I°®pce=5 A and Apce=10.8 cm^, and for curve (c) P pce=2 A and Apce=4.3 cm^. The plots are from simulations using PSS-PCE.

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48 Figure 3.6. Plots of P“‘pce versus P^’opt for various SRH recombination lifetimes. For all three curves Lpce=5 mm, Apce=10.8 cm^ and I°®pce=5 A. For curve (a) tsrh=50 /usee, for curve (d) tsrh=5 /xsec, and for curve (c) tsrh=1 //sec. The plots are from simulations using PSS-PCE. optical power. In addition, as shown in Chapter 2 the current saturation level increases linearly with increases in junction optical power. Following are some sample designs for both the all-solid-state and hybrid approaches. 3.3.1 All-Solid-State Approach Table 3.2 shows some sample designs for the PCE-based all-solid-state AC substation breaker. The PCE for this application is designed to hold off the system voltage rated at 15.5 kVrms, carry a continuous load current of 600 Arms, and interrupt a fault current of 12,000 Arms. The semiconductor material used for designs 1-4 is Si, whereas GaAs is used for design 5. Design 1 is designed to have the shortest electrical length that would theoretically hold off the system voltage. This allows for a smaller device which requires less optical power and exhibits lower on-state resistive losses. Thermal

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49 Table 3.2. Sample designs for the all-solid-state substation breaker. All-Solid-State Substation Breaker System Voltage: 15.5 kVrms L-L Continuous Lx>ad Current: 600 Arms Fault Current: 12,000 Arms Design # 1 2 3 4 5 Material Si Si Si Si GaAs Lpce (mm) 2 5 5 10 5 Apce (cm^) 4.3 10.8 4.3 4.3 4.3 r^pce (Arms) 5 5 2 1 2.5x10^ T'SRH (/^sec) 2 2 4 10 1 P^pt (kW) 1.0 2.5 2.5 3.0 1.5 Popt (kW) 1.0 1.0 1.0 1.0 1.25 R°"pce (mfi) 9.72 21.2 14.4 22.3 17.3 P V (A) 848 852 862 854 876 dunit (A*m) 100 500 500 500 1 Tamb (K) 232 232 232 232 232 T^^pce (K) 331 255 346 354 232 constraints, however, require that the depth of each unit for this design be less than the maximum allowed depth, in order to reduce the thermal resistance. Design 1 exhibits a worst case temperature rise of 99 K. The electrical length is increased in designs 2-4 in order to achieve more practical breakdown voltage to length ratios. An increase in the electrical length requires more bulk optical power and increases the on-state resistive losses. This is shown by design 2. The larger volume of design 2 allows for an increase in the depth of each unit which shows a worst case temperature rise of only

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50 23 K. This small amount of temperature rise allows for a decrease in the conduction cross sectional area which reduces the leakage current, as well as an increase in the SRH recombination lifetime which reduces the on-state resistive losses. Design 3 shows these results along with the penalty for these improvements which is an increase of the worst case temperature rise from 23 K to 114 K. Design 4 has the longer and maybe the most practical electrical length for this application. The bulk optical power requirements are kept comparable to designs 2 and 3 by increasing the SRH recombination lifetime. This, however, reduces the speed of the device and also causes a worst case temperature rise of 124 K. Design 4 also exhibits the lowest leakage current among the Si-based designs. Note that the Si designs assume a dark resistivity of 40,000 fi-cm at 300 K, a value limited by todayÂ’s technology. In theory, intrinsic silicon at 300 K has a dark resistivity of about 800,000 fi-cm and thus, with technological improvements, the leakage current could be reduced by about one order of magnitude. Design 5 illustrates some possible advantages in using GaAs-based PCEs. The principal advantage is a reduction in leakage current which is several orders of magnitude less than the Si designs. Another advantage might be a faster switch for comparable device dimensions, optical power requirements, and on-state resistive losses. The GaAs device is a surface device and would require much more space to accommodate as compared with a Si device of the same dimensions. This might be a disadvantage in using GaAs. If, however, compactness is not an issue, having a surface device improves device cooling. Table 3.3 shows some sample designs for the PCE-based all-solid-state AC residential breaker. The PCE for this application is designed to hold off the system voltage rated at 480 Vrms, carry a continuous load current of 100 Arms, and interrupt a fault current of 10,000 Arms. Similar to the substation designs the semiconductor material used for designs 1^ is Si, whereas GaAs is used for design 5. Design 1 has the smallest

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51 Table 3.3. Sample designs for the all-solid-state residential breaker. All-Solid-State Residential Breaker System Voltage: 480 Vrms L-L Continuous Load Current: 100 Arms Fault Current: 10,000 Arms Design # 1 2 3 4 5 Material Si Si Si Si GaAs Lpce (mm) 0.2 0.5 0.5 0.5 0.5 Apce (cm^) 0.56 1.4 0.69 0.69 0.54 I%ce (Arms) 0.2 0.2 0.1 0.1 1.0x10-^ 7-sRH (//sec) 2 2 5 10 1 P^pt (W) 35 75 55 40 35 Popt (W) 160 160 160 160 200 R°Ve (mfi) 3.58 8.02 6.23 5.18 7.84 P%ce (A) 144 144 143 142 141 dunit (/^m) 200 500 500 500 1 Tamb (K) 273 273 273 273 273 r"“pce (K) 325 282 314 346 273 overall dimensions and thus requires the least amount of optical power and exhibits the least amount of on-state resistive losses. Design 2 shows the effects of increasing the electrical length of design 1. These effects include an increase in optical power requirements and an increase of the on-state resistive losses. Design 3 illustrates the effects of decreasing the conduction cross sectional area and increasing the SRH recombination lifetime of design 2. These effects include a decrease in leakage current, a decrease in optical power requirements, and a decrease of the on-state resistive losses. Design

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52 Table 3.4. Sample designs for the all-solid-state transmission breaker. All-Solid-State Transmission Breaker System Voltage: 230 kVrms L-L Continuous Lx)ad Current: 1000 Arms Fault Current: 20,000 Arms Design # 1 2 3 4 5 Material Si Si Si Si GaAs Lpce (cm) 2 5 5 10 5 Apce (cm^) 5.8 14.6 7.3 5.8 5.8 I°^pce (Arms) 10 10 5 2 5.0x10-^ 'TSRH (//sec) 1 1 2 5 1 P^pt (kW) 30 75 70 75 35 Popt (kW) 1.7 1.7 1.7 1.7 2.0 R°"pce (m^^) 66.4 143 97.3 170 77.8 I%ce (A) 1460 1470 1490 1460 1410 dunit (//nt) 100 500 500 500 1 Tamb (K) 232 232 232 232 232 T^^^pce (K) 347 254 323 357 232 4 shows that the optical power requirements and on-state resistive losses of design 3 can be reduced even more by increasing the SRH recombination lifetime. Design 5 is a GaAs-based switch of comparable dimensions, optical power requirements, and on-state resistive losses as the Si-based devices. Similar to the substation designs the GaAs switch exhibits a reduction in leakage current which is several orders of magnitude less than the Si designs.

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53 Table 3.4 shows some sample designs for the PCE-based allsolid-state AC transmission breaker. The PCE for this application is designed to hold off the system voltage rated at 230 kVrms, carry a continuous load current of 1000 Arms, and interrupt a fault current of 20,000 Arms. Again Si is used for designs 1^, whereas GaAs is used for design 5. Design 1 has the smallest overall dimensions. Design 2 shows the effects of increasing the electrical length of design 1. Design 3 illustrates the effects of decreasing the conduction cross sectional area and increasing the SRH recombination lifetime of design 2. Design 4 exhibits the effects of increasing the electrical length, decreasing the conduction cross sectional area, and increasing the SRH recombination lifetime of design 3. Finally, design 5 shows the effects of designing a PCE using GaAs instead of Si. Total power losses, including both optical and resistive, given as a percentage of total power being delivered might be one of the criteria utility companies use in deciding for or against PCE-based all-solid-state breakers. For the substation designs the total power losses range from 0. 1-0.2 percent of the total per phase power being delivered. The residential designs show total power losses ranging from 0.8-1. 1 percent of the total per phase power being delivered. The transmission designs exhibit total power losses ranging from 0.07-0.18 percent of the total per phase power being delivered. It appears that these percentage losses are low enough to allow consideration of the PCE-based all-solid-state breaker. The percentage losses are considerably less for the larger substation and transmission applications, thus favoring PCE-based all-solid-state breakers for applications at the higher system levels. However, this does not exclude applications at the lower system levels since the actual amount of total power losses is very small. The designs given in Tables 3.2-3.4 were numerically tested during both steadystate and transient operation. All breakers performed successful interruptions under

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54 any type of circumstances. Figures 3.7-3. 1 1 show plots of various system and breaker parameters during a fault interruption at the substation level using design 4 of Table 3.2. Figure 3.7 shows a plot of the source voltage during steady-state-on, fault, and interruption. Figure 3.8 shows a plot of the breaker current, which is also the system current, during steady-state-on, fault, and interruption. In this sample case the fault occurs slightly before a current zero and results in a very large rate of change in system current. The current buildup is limited by the saturation value of the PCE which is larger than the rated continuous load current. When the system current reaches this saturation level an interruption is initiated and successfully completed as shown in Figure 3.8. Figure 3.9 shows in more detail the breaker current as well as the PCE current during this interruption. During part of the interruption the PCE current is less than the total breaker current. This is due to the high interrupting speed of the PCE which generates a large voltage buildup across the PCE. When this voltage reaches the breakdown limit of the surge arrester, it is clipped, and the excess breaker current flows through the surge arrester. Figure 3.10 illustrates the voltage buildup across the PCE during this interruption as well as the voltage clipping forced by the surge arrester. Figure 3.11 shows a plot of the PCE temperature during this interruption. The temperature rises very quickly from the on-state value of 232 K to a peak value of 295 K during interruption. The use of the surge arrester significantly aids in keeping the peak value below temperature levels that could induce a thermal runaway. The declining temperature immediately following the interruption signifies the success of the interruption. It should be noted that the waveforms of breaker and system parameters, during steadystate-on and interruption, for any system level using the allsolidstate breaker, are of the form shown in Figures 3.7-3.11.

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55 xl(H Figure 3.7. Plot of Vs during steady-state-on, fault, and interruption, for substation design #4 of Table 3.2. The plot is from numerical simulations using PSS-PCE. Figure 3.8. Plot of Ibr during steady-state-on, fault, and interruption, for substation design #4 of Table 3.2. The plot is from numerical simulations using PSS-PCE.

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56 Figure 3.9. Plots of Ibr and Ipce during interruption for substation design #4 of Table 3.2. The plots are from numerical simulations using PSS-PCE. xlO< Figure 3.10. Plot of during interruption for substation design #4 of Table 3.2. The plot is from numerical simulations using PSS-PCE.

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57 Figure 3.11. Plot of T^ce during interruption for substation design #4 of Table 3.2. The plot is from numerical simulations using PSS-PCE. 3.3.2 Hybrid Approach Tables 3.5-3.7 show sample designs for PCE-based hybrid breakers operating at the substation, residential, and transmission levels. The PCE is designed to operate under illuminated conditions for 100 microseconds before and after a current zero. Under this constraint the PCE is required to handle an on-state current equivalent to the instantaneous fault current at 100 microseconds after a current zero. Furthermore, since the PCE operates under illuminated conditions for very short periods of time the on-state PCE resistance is allowed to be as large as 500 milliohms, assuming such a large value does not negate current commutation. Allowing a larger on-state PCE resistance reduces the optical power requirements. In addition, the short operating window requires fast PCE switching speeds. A SRH recombination lifetime of one microsecond provides adequate switching speed and, therefore, this value is used in all the designs.

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58 Table 3.5. Sample designs for the hybrid substation breaker. Hybrid Substation Breaker System Voltage: 15.5 kVrms L-L Continuous Load Current: 600 Arms Fault Current: 12,000 Arms Design # 1 2 3 4 5 Material Si Si Si Si GaAs Lpce (mm) 2 5 5 10 5 Apce (cm^) 0.86 2.2 1.1 2.2 1.7 r^pce (Arms) 1 1 0.5 0.5 1.0x10-^ rsRH (/xsec) 1 1 1 1 1 P^pt (W) 90 450 200 800 100 Popt (W) 800 800 800 800 900 tc (/xsec) 182 187 187 187 182 R°"pce (mfi) 178 219 490 489 237 P"‘pce (A) 644 647 644 647 622 dunit (/^*Tl) 500 500 500 500 1 Tamb (K) 232 232 232 232 232 T^^pce (K) 311 246 263 240 232 Table 3.5 shows sample designs for the PCE-based hybrid AC substation breaker. The PCE for this application is designed to hold off the system voltage rated at 15.5 kVrms and interrupt a fault current of 12,000 Arms. Silicon is used in designs 1—4 and gallium arsenide is used in design 5. Design 1 has the smallest overall dimensions and requires the least amount of optical power. Design 2 has a longer electrical length than design 1 and consequently requires more optical power. The longer length, however.

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59 makes design 2 a better candidate for practical applications. Design 3 is an improvement of design 2 in terms of leakage current and optical power requirements. Design 4 shows the effect of increasing the electrical length of design 3 which mainly includes an increase in optical power requirements. Design 5, the GaAs-based PCE, exhibits a reduction in leakage current which is several orders of magnitude less than the Si designs. All designs exhibit low temperature rises mainly because current commutation and interruption occur near a current zero. Furthermore, because of the short conduction time the optical energy required by these designs is very small ranging from 0.178-0.325 joules. Table 3.6 shows sample designs for the PCE-based hybrid AC residential breaker. The PCE for this application is designed to hold off the system voltage rated at 480 Vrms and interrupt a fault current of 10,000 Arms. The Si device of design 1 has the smallest overall dimensions. Design 2 is designed using a longer electrical length than design 1. Design 3 is an improvement of design 2 in terms of leakage current. Design 4 is designed using the longest electrical length. Design 5 illustrates the effects of using a GaAs-based PCE instead of a Si-based PCE. The bulk optical power in all five designs is significantly lower than the junction optical power and, therefore, increases in bulk optical power requirements due to larger overall device dimensions do not disadvantage the larger designs. Furthermore, decreases in total optical power requirements, which occur when allowing increases to the onstate PCE resistance, are insignificant and, therefore, the on-state PCE resistance in all five designs is allowed to be below 100 milliohms. The corresponding optical energy requirements for each interruption process using these designs is very small ranging from 0.14-0.16 joules. It is also worth noting that the maximum current handling capability of these designs is much larger than the continuous load current because of the large fault current and method of breaker operation.

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60 Table 3.6. Sample designs for the hybrid residential breaker. Hybrid Residential Breaker System Voltage: 480 Vrms L-L Continuous Load Current: 100 Arms Fault Current: 10,000 Arms Design # 1 2 3 4 5 Material Si Si Si Si GaAs Lpce (mm) 0.2 0.5 0.5 1.0 0.5 Apce (cm^) 0.56 1.4 0.69 1.4 2.2 P^pce (Arms) 0.2 0.2 0.1 0.1 4.0x10-5 'TsRH (/isec) 1 1 1 1 1 P^pt (W) 2 10 10 40 10 Pjopt (W) 700 700 700 700 800 tc (/xsec) 215 215 215 215 195 R°"pce (mJ^) 75 93 96 96 24 (A) 561 562 562 563 553 dunit (/^m) 200 500 500 500 1 Tamb (K) 243 243 243 243 243 T^^pce (K) 313 264 286 254 243 Table 3.7 shows sample designs for the PCE-based hybrid AC transmission breaker. The PCE for this application is designed to hold off the system voltage rated at 230 kVrms and interrupt a fault current of 20,000 Arms. Again Si is used in designs 1—4 and GaAs is used in design 5. Design 1 has the smallest overall dimensions and requires the least amount of optical power. Increasing the electrical length of design 1 considerably increases the optical power requirements as shown by design 2. Design 3 improves upon

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61 Table 3.7. Sample designs for the hybrid transmission breaker. Hybrid Transmission Breaker System Voltage: 230 kVrms L-L Continuous Lx)ad Current: 1000 Arms Fault Current: 20,000 Arms Design # 1 2 3 4 5 Material Si Si Si Si GaAs Lpce 2 5 5 10 5 Apce (cm^) 1.2 2.9 1.5 2.9 2.3 r^pce (Arms) 2 2 1 1 2.0x10-^ TSRH (/isec) 1 1 1 1 1 P^pt (kW) 5 75 30 120 15 Popt (kW) 1.4 1.4 1.4 1.4 1.5 tc (/isec) 173 173 173 173 173 R°Ve 384 196 461 461 183 P V (A) 1140 1210 1160 1200 1050 dunit 200 500 500 500 1 Tamb (R) 232 232 232 232 232 T^**pce (K) 360 253 274 243 232 design 2 in terms of leakage current and optical power requirements by reducing the conduction cross sectional area and allowing a higher on-state resistance. Design 4 illustrates the effects of doubling the electrical length of design 3 which includes a quadrupling of optical power requirements. Design 5 shows the effects of using GaAs instead of Si to design the PCE-based breaker. The optical energy required per interruption process by these designs ranges from 1.3-24.3 joules.

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62 The designs given in Tables 3.S-3.7 were numerically tested during both load and fault interruptions. The PCEs performed successfully for either of these type of interruptions. Figures 3.12-3.15 show plots of various system and breaker parameters during a fault interruption at the substation level using design 4 of Table 3.5. Figure 3.12 shows plots of the source voltage and breaker (system) current during steadystate-on and fault conditions. A line to neutral fault is initiated near a current zero resulting a large system current The fault current is allowed to exist for several cycles before commencing the interruption process. It is worth noting the large phase shift that takes place between the source voltage and system current a few cycles following the fault occurrence. Figure 3.13 shows plots of breaker and PCE currents during current commutation and interruption. As described earlier and shown here current commutation begins within 100 microseconds prior to a current zero. After the current is transferred from the mechanical switch to the PCE, the PCE carries the fault current for approximately 200 microseconds and then proceeds with the interruption. Figure 3.14 shows a plot of the voltage across the PCE during current commutation and interruption. The voltage builds up across the PCE during the interruption and is clipped when it reaches the surge arrester breakdown voltage. Figure 3.15 shows a plot of the PCE temperature during current commutation and interruption. The temperature rise during this period is only 8 K. The declining temperature immediately following the interruption signifies the success of the interruption. The waveforms of breaker and system parameters, during steady-state-on, fault, current commutation, and interruption, for any system level using the hybrid breaker, are of the form shown in Figures 3.12-3.15.

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63 1 10 -' Fijgure 3.12. Plots of V* and Ibr during steadystate-on and fault for substation design #4 of Table 3.5. The plots are from numerical simulations using PSS-PCE. Figure 3.13. Plots of Ibr and Ipce during current commutation and interruption for substation design #4 of Table 3.5. The plots are from numerical simulations using PSS-PCE.

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64 86.65 86.7 86.75 86.8 86.85 86.9 86.95 87 Time (msec) Figure 3.14. Plot of Vpce during current commutation and interruption for substation design #4 of Table 3.5. The plot is from numerical simulations using PSS-PCE. Figure 3.15. Plot of Tpce during current commutation and interruption for substation design #4 of Table 3.5. The plot is from numerical simulations using PSS-PCE.

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65 3.4 Comparison of the PCE with GTO Thyristors This section compares the PCE to conventional GTO thyristors. The PCE is a new type of semiconductor switching device which appears to have potential for power system applications. A large family of GTO thyristors, however, can already be found in use in power system applications. Therefore, a comparison between PCEs and GTO thyristors would be very informative in assessing the future of PCEs in power system applications, especially in the area of circuit protection. As described earlier the PCE is a bilateral bulk device which can be turned on and off very rapidly, will conduct large currents, and hold off very high voltages. GTO thyristors are one-directional junction devices which can also be turned on and off very rapidly, and will conduct considerable amounts of current, but cannot hold off very large voltages. The PCE seems to have several inherent advantages over GTO thyristors. The PCE is a very simple device and, therefore, requires less fabrication processes and will probably cost less to fabricate than GTO thyristors. The PCE can be scaled to hold off any amount of voltage, whereas, GTO thyristors are limited by junction lengths to what amount of voltage they can hold off. Therefore, for very high voltage applications only one PCE is required to hold off the system voltage, whereas, many GTO thyristors in series are required to hold off the same voltage. Another advantage the PCE has over GTO thyristors is the ability to conduct current in both directions, and thus for bidirectional operation where one PCE can do the job, a combination of antiparallel GTO thyristors is required. Table 3.8 gives a comparison between PCE-based breakers and GTO thyristorbased breakers at the substation level. Each breaker is required to hold off the system voltage when open, carry the continuous load current when closed, and interrupt a load or fault current when necessary. The table compares resistive and optical power losses

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66 Table 3.8. Comparison of the PCE with GTO thyristors at the substation level. System Voltage: 15.5 kVrms L-L Continuous Load Ciurent: 600 Arms Fault Current: 12,000 Arms Device: Si-PCE GaAs-PCE GTO Thyristors 12 devices (Model FG1500A/70 by Powerex) Pei(kW) 3.5 6.0 14.4 Popt (kW) 2.0 2.75 — loff (Arms) 5 2.5x10-^ 0.150 toff (//sec) 20 10 15 during on-state operation, leakage currents, and tum-off times. The PCE-based breakers are designs taken from Table 3.2. The Si PCE is design 1 of Table 3.2 and the GaAs PCE is design 5 of Table 3.2. The thyristor-based breaker is designed using 12 GTO thyristors which are currently available on the market. The thyristor-based breaker exhibits much higher resistive losses than both the Si and GaAs PCE-based breakers. However, the thyristor-based breaker displays no optical power losses which are inherent to the PCE-based breakers. Nevertheless, the total power losses exhibited by the PCEbased breakers are still less than the resistive losses displayed by the thyristor-based breaker. The leakage current for the Si PCE is much larger than what is allowed by the thyristors. This can be alleviated by using a GaAs-based PCE as illustrated by the results. The last parameter being compared is tum-off time. As shown by the table comparable tum-off times may be achieved using either PCEs or GTO thyristors. In conclusion, it is safe to state that bulk photoconductive circuit elements have a promising future in power system applications, especially in the area of circuit protection.

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CHAPTER 4 FABRICATION AND TESTING This chapter describes the fabrication process and testing of low power prototype PCE-based breakers. Section one of this chapter presents a qualitative description of the fabrication process which was performed by Leslie Roberts [7] at the University of RoridaÂ’s Micro Electronics Laboratories. Section two presents experimental test results for the PCE-based laboratory breakers. These results show PCE performance during both steady-state and transient operation. 4.1 Fabrication Process This section describes the various processes involved in the fabrication of the low power PCE-based breaker. High resistivity p-type silicon wafers were used for the purposes of this work. The PCE is a bulk device and, therefore, a high resistivity semiconductor material is required in order to achieve large off to on resistance ratios. As discussed in Chapter 2 the choice of p-type material was made primarily because holes are less mobile than electrons. Figure 4.1 shows a flowchart of the principal processes involved in the fabrication of the PCE-based breaker. The wafer to be processed goes through an initial cleaning in order to remove any surface contamination. Following this cleaning heavily doped p-type regions are formed on both wafer smfaces. These p-type regions are formed using ion implantation techniques. Boron is used for these implantations because of its well documented use. The dopant schedule is chosen to provide at least a 0.5 micron depth 67

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68 Figure 4.1. Flowchart of the principal processes involved in the fabrication of the low power PCE-based breaker. of heavily doped region in order to achieve a low sheet resistance and, therefore, a low contact resistance [7]. Following ion implantation the wafer is cleaned again and put through an annealing process which activates the implanted dopants. The next step in the fabrication process is to metallize both sides of the wafer. Aluminum is deposited on top of the heavily doped regions using electron beam evaporation techniques. Photolithography is then used for opening the metallization windows and for etching the metallization pattern of the top surface of each device. The final devices have a top surface aluminum coverage of approximately fifteen percent of the total surface area. Following metallization an AR (anti-reflecting) coating is applied to

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69 the top surface of the device. This reduces the reflectivity of the top surface which results in decreases of the optical power losses. At this point in the fabrication process the wafer is diced into individual devices. Each die is then mounted to a standard (gold plate on copper) JEDEC TO-3 header. The header allows attachment of large leads for testing purposes. It also provides a good heat sink to the PCE, and it can be attached itself to an even larger heat sink for better device cooling. The final step in the fabrication process is the bonding of wires from the two terminals of the device to the header posts using one mil diameter gold wires. The end result of this process is a Si-p'*'p“p‘^ photoconductive circuit element. Figure 4.2 shows the top view of the fabricated PCE-based breaker. The cross sectional view is shown in Figure 4.3. Figure 4.2. Top view of fabricated PCE-based breaker. Figure 4.3. Cross-sectional view of fabricated PCE-based breaker.

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70 The fabrication process just described does not include all the details involved in fabricating the laboratory PCE-based breaker. For a more detailed description as well as quantitative information of this process the reader is referred to RobertÂ’s work [7]. 4.2 Device Testing This section presents experimental test results for the PCE-based breakers which were fabricated at the University of FloridaÂ’s Micro Electronics Laboratories. The PCE is tested under both dark and illuminated conditions as well as during both steadystate and transient operation. These tests have been very helpful in the development of the device models described in Chapter 2. Comparisons between experimental and numerical results validate theoretical expectations. Figure 4.4 shows a schematic of the circuit being utilized to experimentally test the laboratory PCE-based breakers. The circuit consists of a 60 Hz voltage source in series with a PCE, a test resistor, and a load of light bulbs. Not part of the circuit, but required to illuminate the PCE, a 50 watt continuous wave Neodymium YAG laser is used to provide the optical power. In addition to the testing circuit and optical source several data acquisition equipment are required to record the experiments. For measuring the PCE voltage and current the LeCroy 9400A Digital Sampling Oscilloscope (DSO) is used. This scope provides a 100 megahertz sampling rate of two input channels with a storage capacity of 32,000 8-bit samples per channel. Stored data can be downloaded to a personal computer for easier processing of results. The speed and resolution of this scope is adequate for the experimental tests of this work. Optical power measurements are taken using a 50 watt power probe. Measuring the optical power being dissipated by the PCE is not a trivial task because some light is reflected by the top surface of the PCE. The absorbed optical power is estimated from measurements of the incident and reflected

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71 beams. The temperature of the device is measured using a digital thermometer. This thermometer allows only steady-state temperature measurements. The experimental test results of the laboratory PCE-based breakers are now presented. Several devices were tested during nonilluminated operation. These tests were performed using the circuit of Figure 4.4 with a source voltage of 120 volts RMS. The current versus voltage characteristic of each of the devices tested shows a nearly linear response. Furthermore, the off-state resistance of these PCEs is very close to that predicted by theory. Figure 4.5 shows the experimental nonilluminated current versus voltage characteristic of PCE #22. This plot demonstrates the ability of the PCE to hold off large voltages with small amounts of leakage current. PCE #22 has a vertical geometry similar to that shown in Figures 4.2 and 4.3 with a length of 0.5 mm and a cross-sectional area of 0.36 cm^. The bulk material of this device is composed of p-type silicon having a resistivity of 35,000 fi-cm. Given these device parameters the theoretical off-state resistance is indeed close to the experimental result As the voltage increases, however, there is a drop in the off-state resistance due to inadequate device cooling. An attempt to apply larger steady-state voltages induces thermal runaway in the

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72 Figure 4.5. Experimental nonilluminated current versus voltage characteristic of PCE #22. Device structure as in Figures 4.2 and 4.3 with Lpce=0.5 mm and Apce=0.36 cm^. device. Thermal runaway occurs when a large power dissipation in the device increases the temperature, which results in larger current. The larger current causes more power dissipation and the cycle continues until overheating results in the destruction of the device. Pulse testing [7], which reduces power dissipation, showed that the PCE was able to withstand in excess of 600 volts. Several devices were tested during steady-state illuminated operation. The current versus voltage characteristic of each of the devices tested shows the theoretical expected linear and saturation regions. In the linear region the current is proportional to the applied voltage, whereas, in the saturation region the current is constant and independent of the applied voltage. Figure 4.6 shows the experimental illuminated current versus voltage characteristic of PCE #22 for an optical excitation of 1 1 watts. Figure 4.6 also shows the current versus voltage curve from numerical simulations using PCID. In the numerical simulations the same device dimensions as those of PCE #22 are used. Furthermore, the same optical power dissipation is used. Observation of the experimental and numerical

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73 Figure 4.6. Comparison of experimental and numerical (Using PCID) illuminated (P*Â’opt=H W) current versus voltage characteristic for PCE #22. In the numerical simulation tsrh= 4 //sec. Figure 4.7. Comparison of experimental and numerical (Using PCID) illuminated (P^Â’opt =24 W) current versus voltage characteristic for PCE #22. In the numerical simulation tsrh= 4 /isec.

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lA plots exhibited in Figure 4.6 shows identical saturation levels. This match was obtained when the SRH recombination lifetime in the numerical simulations was set to four microseconds. This result is important in that it provides a method for estimating a deviceÂ’s carrier lifetime. The on-state resistance, in the linear region of both the experimental and numerical plots shown in Figure 4.6, is in the range of tenths of milliohms. The value of the experimental resistance, however, is larger than the expected numerical value. It appears this discrepancy may have two possible reasons. First, there might exist an undesirable high resistance in the contact regions due to the fabrication process. Exp>erimental tests using some of the initial fabricated devices showed orders of magnitude larger than expected on-state resistances. Better care in fabricating the contact regions reduced drastically the on-state resistance. However, it is possible that some unwanted resistance in the contact regions of our devices still exists. A second reason for the larger experimental on-state resistance might be due to inaccuracies in the experiment itself. It is possible that high frequency noise which is generated by some of the equipment used in the experiments, and is of the order of the low voltages being measured, interferes with the accurate measurement of the deviceÂ’s electrical characteristics. The difference between the experimental and numerical value of the on-state resistance is not large enough to suspect a fundamental error in the analysis of photoconductive circuit elements. Figure 4.7 shows the experimental and numerical current versus voltage plots for PCE #22 under increased optical excitation. An increase in the absorbed optical power is expected to increase the current carrying capability of the device and also reduce the on-state resistance in the linear region of the current versus voltage characteristic. These outcomes may be observed by comparing the experimental plots shown in Figures 4.6 and 4.7. Again the experimental result very closely matches the numerical result in the saturation region, whereas, some deviation exists in the linear region.

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75 A required feature of the PCE-based breaker is the ability to interrupt large amounts of current. Several interruption experiments using the fabricated prototypes revealed very encouraging results. Several amps of current were able to be interrupted at very high speeds. Figure 4.8 shows the PCE current during and prior to a load interruption using PCE #22. As illustrated by this plot the PCE interrupts a load current, which is in excess of three amps RMS, in a matter of microseconds. It should be noted here that the switching time of the optical source is of the order of tenths of nanoseconds and thus does not degrade the measured interruption time. Figure 4.9 shows the corresponding PCE voltage for the load interruption shown in Figure 4.8. The voltage drop across the PCE is negligible prior to interruption, whereas, following the fast interruption there is a voltage build-up across the PCE equivalent to the source voltage as is expected. Figure 4.10 shows in detail the PCE current during an experimental load interruption using PCE #22. A load interruption from a numerical simulation using PSS-PCE is also exhibited in Figure 4.10. In the numerical simulation the same device dimensions as those of PCE #22 are used. Furthermore, the same optical power dissipation is used. The SRH recombination lifetime is set to four microseconds, a value derived earlier. The testing scheme in the numerical simulation is similar to that used in the experiments. The same source voltage is applied, and the same steady-state load current is allowed to flow. The interruption in the numerical simulation is initiated at a point on the current waveform similar to that of the experimental interruption. Observation of the experimental and numerical plots exhibited in Figure 4.10 shows that the numerical result closely matches the experimental result, especially during the initial phase of the interruption. Since carrier recombination lifetime is the principal parameter affecting the numerical transient response, matching the numerical result to the experimental result via lifetime variations introduces another method for estimating a deviceÂ’s carrier

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76 Figure 4.8. Experimental load interruption using PCE #22. P*Â’opt=24 W prior to interruption. Plot shows PCE current during both steady-state and interruption. Figure 4.9. Experimental load interruption using PCE #22. Plot shows PCE voltage for same interruption as in Figure 4.8.

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77 Figure 4.10. Comparison of experimental and numerical (Using PSS-PCE) load interruption using PCE #22. P*Â’opt=24 W prior to interruption. In the numerical simulation tsrh= 4 /xsec. recombination lifetime. The experimental result shows a larger leakage current at the tail end of the interruption process. This larger than expected leakage current is due to a significant increase in the temperature of the device during on-state operation. Better device cooling can alleviate this problem. The experimental results described in this section are consistent with the theoretical analysis presented in Chapter 2. The tested devices exemplified the ability to hold off large voltages with low leakage currents, carry significant amount of load current with minimal resistive losses, and accurately interrupt a load current at very high speeds. Furthermore, comparisons between experimental and numerical results validate the device modeling of Chapter 2.

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CHAPTER 5 CONCLUSIONS AND FUTURE RESEARCH This study investigated the feasibility of the PCE for protective switching applications in AC power transmission and distribution circuits. Designs using both the all-solid-state and hybrid arrangements illustrate several potential advantages which include increased speed of operation, improved precision in interruption point, more compact designs, and greater overall reliability. Electrical, optical, and thermal models were developed for the PCE and were incorporated into a power system simulator which evaluates PCE performance during steady-state and transient operation. Simulation results at the substation, residential, and transmission levels show the feasibility of the PCE as an interruptor, especially at the higher substation and transmission levels if one is to consider the electrical losses involved in operating the PCE. In addition to theoretical designs and simulations, low power prototype PCE-based breakers were fabricated and tested for proof of concept. Experimental tests illustrate the ability of the PCE to interrupt significant amounts of current with precision and at high speeds. Furthermore, experimental results as well as results from the numerical simulator PCID, validate the device models and confirm theoretical design results. More work, especially in the area of fabrication and testing, is probably required before the PCE could become an attractive alternative for various switching applications in the power utility industry. Fabrication and testing of devices for use at high current and voltage ratings is one possible area for future research. This task will require careful engineering design in order to achieve a robust device which could handle all 78

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79 the strenuous electrical, optical, and thermal requirements of the PCE. Experimental work using two light sources, one for bulk carrier generation and one for junction carrier generation, is another area for future research. Such testing would illustrate the enormous savings in optical power requirements due to increased carrier generation in the junction areas. Fabrication of GaAs-based PCEs as an alternative to Si-based PCEs is yet another area for future research. As demonstrated by theoretical designs in this study, GaAs devices could reduce leakage currents and increase interruption speeds with comparable on-state electrical and optical losses as those exhibited by the Si devices. More theoretical work could be done in the area of device physics in order to further refine device models. For example, the transient electrical models could be refined to account for the effect of the transit time. Finally, more numerical experiments using more complex power system models could be made in order to test the PCE in a more realistic environment.

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APPENDIX SOURCE CODE FOR PSS-PCE ^ 3fc 9|e 9{e 9|(:fe :fc ^ ^ ^ ^ % 9fe :|c 4e :|e 9|c)|c % :|c :)e >|e :|c % :)e :i|c :)e :)( )|c )|o|c a|c 9)c{(:|o)c :fc ;fe % :|e % :|e :|e :)( :|c9|e ^ }fe s|( :1c ^ a|e 9|c :1c ^ % :4c % :|e :|e :1c :1c :1c :|e :1c ;!( :|e :1c :1c 4t :1c :1c )|e :|e :1c :1c :1c 4t 4c 4c 4c :1c :|e :|c :1c :1c ;lc 4c :le 4e 4e :fc :fc :1c :|c :|c % :|c 4c * 4c 4e )|c 4e % 4c }|e 3|e 4e 3|c 3|c % % 3fc * 3fc ifc sfc C C POWER SYSTEM SIMULATOR C USING C PHOTOCONDUCTIVE CIRCUIT ELEMENTS C C (PSS-PCE) C C »> VERSION 8 «< C ^ 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c ^ 4( 4e 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c ^ 4e 4e 4e 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4e 4c 4e 4e 4e 4c 4e 4e 4c 4e 4e 4e 4e 4e 4e 4e 4e 4c 4e 4e 4c 4c 4c 4c 4c 4e 4c 4c 4c 4c 4e 4c 4c 4c 4c 4c 4c C c c c c c c c Brief Description: The power system simulator (PSS) uses PCE models (electrical, thermal, and optical) to simulate load and fault interruptions. The PCE is used in both the all solid state approach as well as in the hybrid approach. Q* % :|c 3): * 4c * * % :|c * 9ic9|: * 9k >|c * * * ik * ^ 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4: 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4< 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c ^ 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4< 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c c C List of Variables: C C A : PCE area for current conduction C alfe : Exponent factor in electron mobility calculations C alfh : Exponent factor in hole mobility calculations C alpha : Constant in units of eV/K used in Eg calculation C beta : Constant in units of K used in Eg calculation 80

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81 C c : Speed of light C CAu : Constant for calculating the Auger lifetime C Ce : Empirical constant relating Pjopt to Ipcemx C Cfit : Magnitude of current phasor during fault C cntr : Controls number of iterations C Con : Magnitude of current phasor during steady-state-on C convrg : Checks for convergence problems C Cp : Specific heat of semiconductor material C Ctpce : Thermal capacitance of PCE C d : Depth of PCE (same direction as light) C delint : Estimated interruption period (~20 X tau) C dt : Simulation time step (variable) C dtint : Actual interruption period C dunit : Depth of each PCE subunit C Ego : Bandgap at 0 degrees Kelvin C EgT : Bandgap of PCE material C f : Frequency of power source C FI : Stores results of FUN C F2 : Same as FI C F3 : Same as FI C F4 : Same as FI C FUN : Calculates system current using Runge-Kutta C FUN 1 : Calculates PCE temperature using Runge-Kutta C Gel : Stores results of FUN 1 C Ge2 : Same as Gel C Ge3 : Same as Gel C Ge4 : Same as Gel C h : PlanckÂ’s constant C Ibr : Breaker current in amps C icntr : Controls number of iterations C Ipce : PCE current in amps C Ipcemx : PCE saturation current in amps C Ipceof : PCE off-current in Arms C Ipceon : PCE on-current in Arms C Ipcetf : Current through PCE at tf C Ipceti : Current through PCE at ti C Ipceto : Current through PCE at to C k : BoltzmannÂ’s constant C kpce : Thermal conductivity of PCE C 1 : Length of PCE C La : Ambipolar diffusion length C Imd : Wavelength of optical source C Ls : System inductance

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82 C Mmne : Minimum electron mobility C Mmnh : Minimum hole mobility C Mmxe : Maximum electron mobility C Mmxh ; Maximum hole mobility C Mn : Electron density of states effective mass C Mo : Electronic rest mass C Mp : Hole density of states effective mass C Mun ; Mobility of electrons in PCE C Munoff : Mobility of electrons during offstate C Munon : Mobility of electrons during on-state C Mup : Mobility of holes in PCE C Mupoff : Mobility of holes during off-state C Mupon : Mobility of holes during on-state C Na : Acceptor doping concentration C Nc : Effective density of states in the conduction band C Ni : Intrinsic carrier concentration C Nmax : Generated carrier concentration C No : Hole equilibrium concentration in PCE C Nrfe : Reference concentration for electron mobility calc C Nrfh : Reference concentration for hole mobility calc C Numdev : Number of PCE subunits in parallel (d/dunit) C Nv : Effective density of states in the valence band C one : one = 1.0 C phiflt : Phase of current phasor during fault C phion : Phase of current phasor during steady-state-on C pi : pi = 3.14159265 C Pjopt : Required optical power at the junctions C Po : Electron equilibrium concentration in PCE C Pop : PCE instantaneous optical power C Popt ; Required optical power during on-state C Ppce : Instantaneous power dissipation by PCE C Ppceof : Average power dissipation by PCE during off-state C Ppceon : Average power dissipation by PCE during on-state C q : Electronic charge magnitude C qe : Quantum efficiency C Rbr ; Total breaker resistance C rho : Density of semiconductor material C Rload : System load resistance C Rloadi : Saves value of Rload C Rm : Mechanical breaker resistance C Rmof : Mechanical breaker resistance during off-state C Rmon : Mechanical breaker resistance during on-state

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83 C C c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c Rpce : PCE resistance Rpceof : PCE resistance during off-state Rpceon : PCE resistance during on-state Rs : System resistance Rtot : PCE bulk resistance + PCE junction resistance Rtpce : PCE thermal resistance six : six = 6.0 t : Simulation time Tamb : Ambient temperature tau : Recombination lifetime (includes Auger and SRH) tauAu : Auger recombination lifetime tauflt : Time constant for dumping after fault occurs taum : Time constant for Rm on-to-off transition tauSRH : SRH recombination lifetime Temp : PCE temperature tend : Time when each simulation process is completed tendi : Time when interruption is completed testl : Choice of breaker: test 1=1 »> all solid state test 1=2 »> hybrid testl : Choice of simulation: test2=l »> only steady-state calculations test2=2 »> fault simulation test2=3 »> interrupt simulation test2=4 »> fault followed by interruption test2=5 »> Popt versus Ipce calculations tf : Time when fault occurs ti : Time when interruption begins to : Time when PCE turns on (hybrid breaker) Toff : PCE temperature during off-state Ton : PCE temperature during on-state two : two = 2.0 V : Volume of PCE var(i) : Variables used for intermediate calculations Vpce : PCE voltage in volts Vpceof : PCE off-voltage in Vrms Vpceon : PCE on-voltage in Vrms Vs : Source voltage in volts Vsat : PCE on-voltage at which Ipce saturates Vsrms : Source voltage in Vrms Vstf : Source voltage at tf Vsti : Source voltage at ti

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84 Vsto : Source voltage at to Vth : Thermal voltage w : Width of PCE Vector storing t and Ibr : Vector storing PCE Temp Vector storing intermediate steps of X : Vector storing intermediate steps of XI X : XI Y : Y1 C C c c c c c c ^ 4c }|c 3k 4: >l< * 4: Ik % 4c * 4c 4c * 4c i|t III * * * 4: 4: Ik * 4c III lie 4c 4c iic * >i< 3i< * Â’ll >|t 4c sic * * 4: :<< ^ 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4< 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c ^ 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4: 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c c C MAIN PART OF PROGRAM CONTROL UNIT C ^ :4c :fc % He :|c :4c 9fe >(c :fc :iie :)c :fe 9|c :|e :4c :|e :fc :iK s|c afe % % % 4c 4c :fc :fe Jic 3|c 4e :fc ^ 4c % 3(t s|e :fe sfc ^ 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4e 4c 4c 4c 4c 4c 4c 4c 4< 4c 4c 4c 4c 4c 4c 4< 4c 4c 4c 4c 4c 4c 4c % ^ ^ ^ Â’Ic 4c 4c 4c % 4c 4c 4c %%%% 3|c 4e 4c 4c 4c 4c 4c 4c C C Define program variables: C IMPLICIT DOUBLE PRECISION (A-Z) INTEGER convrg COMMON/blk01/Mmxe,Mmne,Nrfe,alfe,Mmxh,Mmnh,Nrfh,aIfh COMMON/blk02/Mun,Mup/blk03/No,Po/blk04/Nmax/blk05/one COMMON/blk06/t/blk07/to/blk08/tau/blk09/ti COMMON/blk 10/alpha, beta, Ego/blk 1 l/Mn,Mp/blkl 2/hJc COMMON/blkl3/Na/blkl4/pi/blkl5/Temp/blkl6/two COMMON/blk 1 7/Ctpce,Rtpce/blk 1 8/Numde v/blk 1 9/Tamb/blk20/Pop COMMON/blk21/Ppce/blk22/dt/blk23/six/blk25/f COMMON/blk26/Ls/blk27/Rbr/blk28/Rload/blk29/Rs/blk30/Vsrms COMMON/blk31/Ibr/blk33/Cflt,phiflt,tauflt COMMON/blk34/Con,phion/blk35/Mo/blk36/Ipceof,Ipceon COMMON/blk37/Cp3cpce,rho/blk38/d/blk39/dunit/blk40/l COMMON/blk41/Ce/blk42/delint/blk43Amd/blk44/Pjopt/blk45/qe COMMON/blk46/Rmof/blk47/Rmon/blk48/taum/blk49/tauSRH COMMON/blk50/testl/blk51/test2/blk52/tf/blk53/Toff COMMON/blk54/c/blk55/V,w/blk56/A/blk57/tauAu/blk58/Ton COMMON/blk59/Ppceof,Ppceon,Rpceof,Rpceon,Vpceof,Vpceon COMMON/blk60/Rloadi/blk61/Ipcemx/blk62/Popt/blk63/q COMMON/blk64/convrg/blk65/Ipce/blk66/Rpce,Vpce,Vs COMMON/blk67/Ipcetf,Vstf/blk68/Ipceti,Vsti,tendi,dtint COMMON/blk69/Ipceto,Vsto/blk70/CAu

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uuu uuu uuu uuuu uuuu uuuu uuu 85 Open input and output files: OPEN (UNIT=5,FILE=Â’Pce8.inÂ’) OPEN (UNIT=6,FILE=Â’PcedevÂ’) OPEN (UNIT=7,FILE=Â’PopImxÂ’) OPEN (UNIT=8,FILE=Â’PceivÂ’) OPEN (UNIT=10,FILE=Â’TimeÂ’) Read data from input file: CALL PCEIN Define various constants: CALL PHYCON Check whether or not calculations of the PCE maximum on-current versus optical power are desired: IF (ESfT(test2).NE.5) GO TO 10 Calculate and output the PCE maximum on-current versus optical power: CALL IMXPOP GOTO 100 Calculate the PCE dimensions as well as the PCE steady-state conditions: 10 CALL PCEDIM Check whether or not simulation is desired: IF (INT(test2).EQ.l) GO TO 100 C C Calculate and output breaker parameters during system C on-state: C IF (INT(testl).EQ.l) THEN CALL PSONl

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uuo uuuu uuu uuuu uuuu uuu 86 ELSE CALL PS0N2 ENDIF IF (convrg.EQ.l) GO TO 100 Check whether or not fault simulation is desired: IF (INT(test2).NE.2.AND.INT(test2).NE.4) GO TO 20 Calculate and output breaker parameters during system fault-state: IF (INT(testl).EQ.l) THEN CALL PSFLTl ELSE CALL PSFLT2 ENDIF IF (convrg.EQ.l) GO TO 100 Check whether or not interrupt simulation is desired: 20 IF (INT(test2).NE.3.AND.INT(test2).NE.4) GO TO 100 Calculate and output breaker parameters during system interruption-state: IF (INT(testl).EQ.l) THEN CALL PSINTl ELSE CALL PSINT2 ENDIF Output the given and calculated information regarding the PCE: 100 CALL PCEDEV Stop execution of program: STOP END

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non 87 Q;jc**H‘*3|c*********>|i*4:************4c4:*4:************s|c*!|‘:|c3|:************* Q:|ciic*:|c4c9|c4:*4c***4:************ii<************************************** Q^i;ic:(c*Hcilc*4c***llc**************************************************** Subroutine PCEIN is used to read the input file: SUBROUTINE PCEIN IMPLICIT DOUBLE PRECISION (A-Z) COMMON/blkOI/Mmxe,Mmne,Nrfe,alfe,Mmxh,Mmnh,Nrfh,alfh COMMON/blk04/Nmax/blk06/t/blk07/to/blk09/ti COMMON/blklO/alpha,beta,Ego/blklI/Mn,Mp/blkI3/Na/blkl9/Tamb COMMON/blk25/f/blk26/Ls/blk29/Rs/blk30A^srms COMMON/blk36/Ipceof,Ipceon/blk37/Cp,kpce^ho/blk38/d COMMON/blk39/dunit/blk40/l/blk41/Ce/blk42/delint/blk43/lmd COMMON/blk44/Pjopt/blk45/qe/blk46/Rmof/blk47/Rmon COMMON/blk48/taum/blk49/tauSRH/blk50/testl/blk51/test2 COMMON/blk52/tf/blk53/Toff/blk70/CAu READ (5,10) Vsrms READ (5,10) f READ (5,10) Ipceof READ (5,10) Ipceon READ (5,10) 1 READ (5,10) d READ (5,10) dunit READ (5,10) Mn READ (5,10) Mp READ (5,10) Ego READ (5,10) alpha READ (5,10) beta READ (5,10) Mmxe READ (5,10) Mmne READ (5,10) Nrfe READ (5,10) alfe READ (5,10) Mmxh READ (5,10) Mmnh READ (5,10) Nrfh READ (5,10) alfh READ (5,10) rho READ (5,10) Cp READ (5,10) kpce READ (5,10) Tamb READ (5,10) Toff READ (5,10) Na

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o n n 88 READ (5,10) Nmax READ (5,10) qe READ (5,10) tauSRH READ (5,10) CAu READ (5,10) Imd READ (5,10) Pjopt READ (5,10) Ce READ (5,10) Ls READ (5,10) Rs READ (5,10) Rmon READ (5,10) Rmof READ (5,10) taum READ (5,10) testl READ (5,10) test2 READ (5,10) t READ (5,10) tf READ (5,10) to READ (5,10) ti READ (5,10) delint 10 FORMAT (52X,E13.6) RETURN END ^ ;|c 3|c ^ :|c % % % ;|c ;|c !|C ;)c :(c ^ ;|c % % % :|c >|c 4c * 4c >1: >11 * ik lit * * 4: !|c 3k * ^ 4c :|c :|c !|c 4c ill He % !|< * :k Q4c 4c 4c 4c 4c 4c 4: 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c Subroutine PHYCON is used to define various constants: SUBROUTINE PHYCON IMPLICIT DOUBLE PRECISION (A-Z) COMMON/blk05/one/blkl2/hJc/blkI4/pi/blkl6/two/blk23/six COMMON/blk35/Mo/blk54/c/blk63/q h = 0.663D-33 c = 0.2998D+09 q = 0.16D-18 k = 0.138D-22 Mo = 0.911D-30 pi = 3.141592654 one = 1.0 two = 2.0 six = 6.0 RETURN END

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89 (^************J|c******>|c******************************************** ^**************************************************************** (>************************************************************* c C Subroutine IMXPOP calculates and outputs the PCE maximum C on-current versus optical power: C SUBROUTINE IMXPOP IMPLICIT DOUBLE PRECISION (A-Z) INTEGER I COMMON/blk04/Nmax/blk 1 8/Numdev/blk20/Pop COMMON/blk36/Ipceof,Ipceon/blk38/d/blk44/Pjopt/blk58/Ton COMMON/blk6 l/Ipcemx/blk62/Popt Nmaxx = 5.0D+21 Nmax = Nmaxx varl = 0.5 var2 = 350.0 var3 = 1000.0 DO 20 1=3, 300 CALL PCEDIM d = d*Numdev Ipceof = Ipceof*Numdev Ipceon = Ipceon*Numdev Popt = Popt*Numdev Pjopt = Pjopt*Numdev Pop = Popt+Pjopt Ipcemx = Ipcemx*Numdev Nmax = varl*DBLE(FLOAT(I))*Nmaxx WRITE (7,10) Ipcemx, Pop, Ton 10 FORMAT (1X,3(E14.7,1X)) IF (Ton.GT.var2) GO TO 30 IF (Ipcemx.GT.var3) GO TO 30 20 CONTINUE 30 d = d/Numdev Ipceof = Ipceof/Numdev Ipceon = Ipceon/Numdev Popt = Popt/Numdev Pjopt = Pjopt/Numdev Ipcemx = Ipcemx/Numdev RETURN END

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90 ^ J||^ ^ ^ «||^ 4^ «|^ c C Subroutine PCEDIM is used to calculate the PCE dimensions C as well as the steady-state conditions: C SUBROUTINE PCEDIM IMPLICIT DOUBLE PRECISION (A-Z) COMMON/blk01/Mmxe,Mmne,Nrfe,alfe,Mmxh,Mmnh,Nrfh,alfh COMMON/blk04/Nmax/blk05/one/bIk08/tau/blkl0/alpha, beta, Ego COMMON/blkll/Mn,Mp/blkl2/hJc/blkl3/Na/blkl4/pi/blkl5/Temp COMMON/blk 1 6/two/blk 1 7/Ctpce,Rtpce/blk 1 8/N umdev/blk 1 9/Tamb COMMON/blk20/Pop/blk28/RIoad/blk29/Rs/blk30A^srms/blk35/Mo COMMON/blk36/Ipceof,Ipceon/blk37/Cp,kpce,rho/blk38/d COMMON/blk39/dunit/blk40/l/blk41/Ce/blk43/lmd/bIk44/Pjopt COMMON/blk45/qe/blk49/tauSRH/blk50/testl/blk53/Toff COMMON/blk54/c/blk55A^,w/blk56/A/blk57/tauAu/blk58/Ton COMMON/blk59/Ppceof,Ppceon,Rpceof,Rpceon,Vpceof,Vpceon COMMON/blk60/Rloadi/blk6I/Ipcemx/bIk62/Popt/blk63/q COMMON/blk70/CAu IF (d.GT.dunit) THEN Numdev = d/dunit ELSE Numdev = one ENDIF Rpceof = Vsrms/Ipceof Ppceof = Vsrms*Ipceof varl = 1.5 Nc = two*(((Mn*Mo/h)*(two*pi*k*Toff/h))**varI) Nv = two*(((Mp*Mo/h)*(two*pi*k*Toff/h))**varI) EgT = Ego-alpha*Toff*Toff/(Toff+beta) Ni = DSQRT(Nc*Nv)*DEXP(-EgT*q/(two*k*Toff)) Po = (Na+DSQRT(Na*Na+two*two*Ni*Ni))/two No = Ni*Ni/Po Munoff = Mmne+(Mmxe-Mmne)/(one+(No/Nrfe)**aIfe) Munon = Mmne+(Mmxe-Mmne)/(one+(Nmax/Nrfe)**alfe) Mupoff = Mmnh+(Mmxh-Mmnh)/(one+(Po/Nrfh)**alfh) Mupon = Mmnh+(Mmxh-Mmnh)/(one+(Nmax/Nrfh)**aIfh) A = l/(Rpceof*q*(Munoff*No+Mupoff*Po)) Rpceon = l/(q*A*(Munon+Mupon)*Nmax) RIoad = Vsrms/Ipceon-Rs

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91 Rloadi = Rload Vpceon = Ipceon*Rpceon Ppceon = Vpceon*Ipceon tauAu = one/(CAu*Nmax*Nmax) tau = one/(one/tauSRH+one/tauAu) Popt = A*l*h*c*Nmax/(tau*lmd*qe) w = A/d V = A*1 d = d/Numdev A = A/Numdev V = V/Numdev Rpceon = Rpceon*Numdev Ipceon = Ipceon/Numdev Ppceon = Ppceon/Numdev Popt = Popt/Numdev Pjopt = Pjopt/Numdev Pop = 0.0 IF (ENT(testl).EQ.l) Pop=Popt+Pjopt Rpceof = Rpceof*Numdev Ipceof = Ipceof/Numdev Vpceof = Vsrms Ppceof = Ppceof/Numdev Rtpce = d/(kpce*l*w*two) Ctpce = rho*V*Cp/two Ton = Tamb+(Popt+Ppceon)*Rtpce/two Toff = Tamb+Ppceof*Rtpce/two Temp = Tamb IF (INT(testl).EQ.l) Temp=Ton Vth = k*Ton/q La = DSQRT(two*Vth*Munon*Mupon*tau/(Munon+Mupon)) Vsat = l*La/(Munon*tau) Ipcemx = Vsat/Rpceon Ipcemx = Ipcemx+Pjopt/Ce Vsat = Rpceon *Ipcemx WRITE (8,10) 0.0, 0.0 WRITE (8,10) Vsat,Ipcemx*Numdev WRITE (8,10) 1.3*Vsat,Ipcemx*Numdev 10 FORMAT (1X,2(E14.7,1X)) RETURN END

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92 Q***3|c:|c4:**9|c****>ic*************!ic*!i<****i|c*************!icii<***********4c*>ic Qi|c**********!|c**:jc:icHc********>ic**********3|<*********%***************** c C Subroutine PSONl calculates and outputs breaker parameters C during system on-state for the allsolid-state breaker: C SUBROUTINE PSONl IMPLICIT DOUBLE PRECISION (A-Z) INTEGER convrg COMMON/blk02/Mun,Mup/blk03/No,Po/blk04/Nmax/blk05/one COMMON/blk06/t/blk09/ti/blkl4/pi/blkl5/Temp/blkl6/two COMMON/blk 17/Ctpce,Rtpce/blk 1 8/Numdev/blk2 l/Ppce/blk22/dt COMMON/blk25/f/blk27/Rbr/blk30A^srms/blk3 1/Ibr COMMON/blk34/Con,phion/blk40/l/blk51/test2/blk52/tf/blk56/A COMMON/blk63/q/blk64/convrg/blk65Apce/blk66/Rpce,Vpce,Vs convrg = 0 varl = 150.0 dt = (one/f)/varl var2 = Rtpce*Ctpce IF (var2.LT.dt) dt=var2 IF (INT(test2).EQ.2.0R.INT(test2).EQ.4) THEN tend = tf ELSE tend = ti ENDIF GO TO 30 10 WRITE (10,20) t, Vs, Ibr, Ipce, Vpce, Temp 20 FORMAT (1X,E14.7,5(1X,E12.5)) t = t+dt CALL PCETEM 30 CALL EQCONC CALL MOBON Rpce = l/(q*((Mun+Mup)*Nmax+Mup*Po+Mun*No)*A*Numdev) Rbr = Rpce CALL SSON Vs = DSQRT(two)*Vsrms*DSIN(two*pi*f*t) Ibr = Con*DSIN(two*pi*f*t-phion) Ipce = Ibr Vpce = Ipce*Rpce Ppce = Vpce*Ipce IF (DABS(Ipce).GT.1.0D+10) GO TO 40 IF (Temp.GT.lOOO) GO TO 40

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93 IF (t.LT.tend) GO TO 10 GO TO 50 40 convrg = 1 50 RETURN END ^ >|t % % % 4: 4c 4c iic 3|c sk 31: Â’ll i|c * 4c 31: 3): >1: * 4c 3|c :|c :|c :{c 3|c :|c :|c 4c :|c :|ci|c 9|c 9|c 4c Ik iN ^ Â’ll 4c >1^ !|E !
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94 Ibr = Con*DSIN(two*pi*f*t-phion) Ipce = Ibr*Rmon/(Rmon+Rpce) Vpce = Ipce*Rpce Ppce = Vpce*Ipce IF (DABS(Ipce).GT.1.0D+10) GO TO 40 IF (Temp.GT.lOOO) GO TO 40 IF (t.LT.tend) GO TO 10 GO TO 50 40 convrg = 1 50 RETURN END Q************)(c!|c***s|c******)|c***!|c**)|c**j|cj|ts|c:|c****s|c***jjc*********:)c******* c C Subroutine PSFLTl calculates and outputs breaker parameters C during system fault-state for the all-solidstate breaker: C SUBROUTINE PSFLTl IMPLICIT DOUBLE PRECISION (A-Z) INTEGER cntr,convrg,icntr COMMON/blk02/Mun,Mup/blk03/No,Po/blk04/Nmax/blk05/one COMMON/blk06/t/blkl4/pi/blkl5/Temp/blkl6/two COMMON/blkl7/Ctpce,Rtpce/blkl8/Numdev/blk21/Ppce/blk22/dt COMMON/blk25/f/blk27/Rbr/blk28/Rload/blk29/Rs/blk30A^srms COMMON/blk3 l/Ibr/blk40/l/blk52/tf/blk56/A/blk6 1/Ipcemx COMMONA)lk63/q/blk64/convrg/blk65/Ipce/blk66/Rpce,Vpce,Vs COMMON/blk67Apcetf, Vstf convrg = 0 Vstf = Vs Ipcetf = Ipce tf = t Rload = 0.0 var2 = 2.5 varl = DSQRT(two)*Vsrms/var2 IF (Vs.LT.varl) THEN varl = 4000.0 ELSE varl = 20000.0 ENDIF dt = (one/f)/varl var3 = Rtpce*Ctpce IF (var3.LT.dt) dt=var3

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95 cntr = 0 icntr = 0 GO TO 20 10 icntr = icntr+1 IF (icntr.GT.cntr) icntr=0 IF (icntr.NE.O) GO TO 40 20 WRITE (10,30) t. Vs, Ibr, Ipce, Vpce, Temp 30 FORMAT (1X,E14.7,5(1X,E12.5)) 40 CALL PCETEM CALL EQCONC CALL MOBON Rpce = l/(q*((Mun+Mup)*Nmax+Mup*Po+Mun*No)*A*Numdev) Rbr = Rpce CALL SYSTMl Vs = DSQRT(two)*Vsrms*DSIN(two*pi*f*t) Ipce = Ibr IF (DABS(Ipce).GT.Ipcemx*Numdev) THEN Ipce = (DABS(Ipce)/Ipce)*Ipcemx*Numdev Ibr = Ipce Rtot = DABS(Vs)/DABS(Ibr) Rpce = Rtot-Rs-Rload Rbr = Rpce Vpce = Ipce*Rpce Ppce = Vpce*Ipce GO TO 60 ENDIF Vpce = Ipce*Rpce Ppce = Vpce*Ipce IF (DABS(Ipce).GT.1.0D+10) GO TO 50 IF (Temp.GT.lOOO) GO TO 50 GO TO 10 50 convrg = 1 60 RETURN END Qs|es|c******,|c,(c***;|c*%*!(c**:|c:jc*%%:(c*%%%*:je%**,(c:)c%***,|t****%:)e***%,|e*,|t*******;)e:je c**************************************************************** c C Subroutine PSFLT2 calculates and outputs breaker parameters C during system fault-state for the hybrid breaker: C SUBROUTINE PSFLT2 IMPLICIT DOUBLE PRECISION (A-Z)

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96 INTEGER cntr,convrg,icntr COMMON/blk02/Mun,Mup/blk03/No,Po/blk05/one/blk06/t COMMON/blk07/to/blk 1 4/pi/blkl 5/Temp/blkl 6/two COMMON/blkl7/Ctpce,Rtpce/blkl8/Numdev/blk21/Ppce/blk22/dt COMMON/blk25/f/blk27/Rbr/blk28/Rload/blk30/Vsrms/blk31/Ibr COMMON/blk33/Cflt,phiflt,tauflt/blk34/Con,phion/blk40/l COMMON/blk47/Rmon/blk52/t^lk56/A/blk63/q/blk64/convrg COMMON/blk65/Ipce/blk66/Rpce,Vpce,Vs/blk67/Ipcetf,Vstf convrg = 0 Vstf = Vs Ipcetf = Ipce tf = t tend = to Rload = 0.0 varl = 150.0 dt = (one/f)/varl var2 = Rtpce*Ctpce IF (var2.LT.dt) dt=var2 cntr = 3 icntr = 0 GO TO 20 10 icntr = icntr+1 IF (icntr.GT.cntr) icntr=0 IF (icntr.NE.0) GO TO 40 20 WRITE (10,30) t, Vs, Ibr, Ipce, Vpce, Temp 30 FORMAT (1X,E14.7,5(1X,E12.5)) 40 t = t+dt CALL PCETEM CALL EQCONC CALL MOBOFF Rpce = l/(q*(Mup*Po+Mun*No)*A*Numdev) Rbr = one/(one/Rmon+one/Rpce) CALL SSFLT Vs = DSQRT(two)*Vsrms*DSIN(two*pi*f*t) Ibr = Cflt*DSIN(two*pi*f*t-phiflt)$Cflt*DSIN(two*pi*f*tf-phiflt)*DEXP((tf-t)/tauflt)+ $Con*DSIN(two*pi*f*tf-phion)*DEXP((tf-t)/tauflt) Ipce = Ibr*Rmon/(Rmon+Rpce) Vpce = Ipce*Rpce Ppce = Vpce*Ipce IF (DABS(Ipce).GT.1.0D+10) GO TO 50 IF (Temp.GT.lOOO) GO TO 50 IF (t.LT.tend) GO TO 10

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97 GO TO 60 50 convrg = 1 60 RETURN END ^ * % * % 3k * * :jc % % :|c 3|C 3|c sic :|c :|c :|c :i< ik 4c :)< 3|: ik % ^ iic * 3i< !
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98 20 WRITE (10,30) t, Vs, Ibr, Ipce, Vpce, Temp 30 FORMAT (1X,E14.7,5(1X,E12.5)) 40 CALL PCETEM CALL EQCONC CALL SYSTMl CALL MOBINT varl = l/(q*((Mun+Mup)*Nmax*DEXP((ti-t)/tau)+Mup*Po+ $Mun*No)*A*Numdev) IF (varl.GE.Rpce) Rpce=varl Rbr = Rpce Vs = DSQRT(two)*Vsrms*DSIN(two*pi*f*t) Ipce = Ibr Vpce = Ipce*Rpce var2 =1.5 var3 = var2*DSQRT(two)*Vsrms IF (DABS(Vpce).GT.var3) THEN Vpce = var3*(Vpce/DABS(Vpce)) Ipce = Vpce/Rpce ENDIF IF (Rpce.GT.varl) THEN Ipce = (DABS(Ipce)/Ipce)*Ipcemx*Numdev Ibr = Ipce Rtot = DABS(Vs)/DABS(Ibr) Rpce = Rtot-Rs-Rload Rbr = Rpce Vpce = Ipce*Rpce ENDIF Ppce = Vpce*Ipce dt = two*Ls/(Rbr+Rload+Rs) IF (var5.LT.dt) THEN dt = var5 cntr = 0 ELSE var6 = ((tend-ti)/dt)/var4 cntr = INT(var6) ENDIF IF (DABS(Ipce).GT.1.0D+10) GO TO 50 IF (Temp.GT.lOOO) GO TO 50 IF (t.LT.tend) GO TO 10 GO TO 60 50 convrg = 1 60 tend! = t dtint = tendi-ti

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99 RETURN END (^ ***************************!),** J(t * J|C ^ * jjC ^ 5jC jjj ^ ^ j,; j|; ;J5 j|( j); 5,; jj, ^ 5,; (^***********************S|CJ|<*************************************** Q**************************************************************** c C Subroutine PSINT2 calculates and outputs breaker parameters C diuing system interruptstate for the hybrid breaker: C SUBROUTINE PSINT2 IMPLICIT DOUBLE PRECISION (A-Z) INTEGER cntr,convrg,icntr COMMON/blk02/Mun,Mup/blk03/No,Po/blk04/Nmax/blk05/one COMMON/blk06/t/blk07/to/blk08/tau/blk09/ti/blkl4/pi COMMON/blk 1 5/Temp/blk 1 6/two/blk 1 8/Numdev/blk20/Pop COMMON/blk2 l/Ppce/blk22/dt/blk25/fd)lk26/Ls/blk27/Rbr COMMON/blk28/Rload/blk29/Rs/blk30A^srms/blk31/Ibr/blk40/l COMMON/blk42/delint/blk44/Pjopt/blk46/Rmof/blk47/Rmon COMMON/blk48/taum/blk56/A/blk61/Ipcemx/blk62/Popl/blk63/q COMMON/blk64/convrg/blk65/Ipce/blk66/Rpce,Vpce,Vs COMMON/blk68/Ipceti, Vsti,tendi,dtint/blk69/Ipceto, Vsto convrg = 0 undrfl = 200.0 Vsto = Vs Ipceto = Ipce to = t Pop = Popt+Pjopt tend = ti var4 = 150.0 var5 = (tend-to)/var4 dt = two*Ls/(Rbr+Rload-i-Rs) IF (var5.LT.dt) THEN dt = var5 cntr = 0 ELSE var6 = ((tend-to)/dt)/var4 cntr = INT(var6) ENDIF icntr = 0 GO TO 20 10 icntr = icntr+1 IF (icntr.GT.cntr) icntr=0 IF (icntr.NE.O) GO TO 40

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100 20 WRITE (10,30) t, Vs, Ibr, Ipce, Vpce, Temp 30 FORMAT (1X,E14.7,5(1X,E12.5)) 40 CALL PCETEM CALL EQCONC CALL SYSTMl IF ((t-to)/tau.GT.undrfl) GO TO 50 CALL MOBTON Rpce = l/(q*((Mun+Mup)*Nmax*(one-DEXP((to-t)/tau))+Mup*Po+ $Mun*No)*A*Numdev) GO TO 60 50 CALL MOBON Rpce = l/(q*((Mun+Mup)*Nmax+Mup*Po+Mun*No)*A*Numdev) 60 Rm = Rmon+Rmof*(one-DEXP((to-t)/taum)) Rbr = one/(one/Rm+one/Rpce) Vs = DSQRT(two)*Vsrms*DSIN(two*pi*f*t) Ipce = Ibr*Rm/(Rm+Rpce) Vpce = Ipce*Rpce Ppce = Vpce*Ipce dt = two*Ls/(Rbr+Rload+Rs) IF (var5.LT.dt) THEN dt = var5 cntr = 0 ELSE var6 = ((tend-to)/dt)/var4 cntr = INT(var6) ENDIF IF (DABS(Ipce).GT.I.0D+10) GO TO 150 IF (Temp.GT.IOOO) GO TO 150 IF (t.LT.tend) GO TO 10 Vsti = Vs Ipceti = Ipce ti = t Pop = 0.0 tend = ti+delint var4 = 200.0 var5 = (tend-ti)/var4 dt = two*Ls/(Rbr+Rload+Rs) IF (var5.LT.dt) THEN dt = var5 cntr = 0 ELSE var6 = ((tend-ti)/dt)/var4 cntr = INT(var6)

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101 ENDIF icntr = 0 GO TO 120 110 icntr = icntr+1 IF (icntr.GT.cntr) icntr=0 IF (icntr.NE.O) GO TO 140 120 WRITE (10,130) t. Vs, Ibr, Ipce, Vpce, Temp 130 FORMAT (1X,E14.7,5(1X,E12.5)) 140 CALL PCETEM CALL EQCONC CALL SYSTMl CALL MOBINT Rpce = l/(q*((Mun+Mup)*Nmax*DEXP((ti-t)/tau)+Mup*Po+ $Mun*No)*A*Numdev) Rbr = one/(one/Rmof+one/Rpce) Vs = DSQRT(two)*Vsrms*DSIN(two*pi*f*t) Ipce = Ibr*Rmof/(Rmof+Rpce) Vpce = Ipce*Rpce var2 =1.5 var3 = var2*DSQRT(two)*Vsrms IF (DABS(Vpce).GT.var3) THEN Vpce = var3*(Vpce/DABS(Vpce)) Ipce = Vpce/Rpce ENDIF Ppce = Vpce*Ipce dt = two*Ls/(Rbr+Rload+Rs) IF (var5.LT.dt) THEN dt = var5 cntr = 0 ELSE var6 = ((tend-ti)/dt)/var4 cntr = INT(var6) ENDIF IF (DABS(Ipce).GT.1.0D+10) GO TO 150 IF (Temp.GT.lOOO) GO TO 150 IF (tLT.tend) GO TO 110 GO TO 160 150 convrg = 1 160 tendi = t dtint = tendi-ti RETURN END

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102 ^***:|c:|c;ic***!ic*4:*****4c;|c4;:jc:«c*3|c**4;:)c**:ic*****;|c:jc9|c*:|c3ic***4‘************!ic3|c**:ic* ^:|c*4c:fc*:jc:ic;ic*:|c4c;|c;ic:ic:jc**9|i%3|c*4;4c4:%%H(**>|E******9ic*********!ic********4c3|c4c****** c C Subroutine SSON calculates various system on-constants: C SUBROUTINE SSON IMPLICIT DOUBLE PRECISION (A-Z) COMMON/blkl4/pi/blkl6/two/blk25/m)lk26/Ls/blk27/Rbr COMMON/blk28/Rload/blk29/Rs/blk30A^srms/blk34/Con,phion varl = Rs+Rbr+Rload var2 = two*pi*f*Ls var3 = var2/varl phion = DATAN(var3) varl = varl*varl var2 = var2*var2 var3 = varl+var2 var3 = DSQRT(var3) Con = DSQRT(two)*Vsrms/var3 RETURN END (^*********************j|c*********j|c***s(t******j|,****:(c***5|j*:jt5,C5^jjjj,j;jt^j(.j);jj.^ (^****!(C****************5|t*******:)C****;jj;^j^5^*^;),;,5j,j^*^^5,j^j^jJ.^^^^^^^^^^^j^j^ Q*********)|<*****S|C**********)|<************************************* c C Subroutine SSFLT calculates various system fault-constants: C SUBROUTINE SSFLT IMPLICIT DOUBLE PRECISION (A-Z) COMMON/blkl4/pi/blkl6/two/blk25/f/blk26/Ls/blk27/Rbr COMMON/blk28/Rload/blk29/Rs/blk30A^srms COMMON/blk33/Cflt,phiflt,tauflt varl = Rs+Rbr+Rload var2 = two*pi*f*Ls var3 = var2/varl phiflt = DATAN(var3) varl = varl*varl var2 = var2*var2 var3 = varl+var2 var3 = DSQRT(var3) Cflt = DSQRT(two)*Vsrms/var3 tauflt = Ls/(Rs+Rbr+Rload) RETURN END

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103 ^***************)|C*******************J|C****SiC******!iC**************** Q lie * 3|c :{c :|c lie :jc 9|( % 4c :|c 4c :|c 4c :jc 3|c 4c 4; 4c « ;|c :|c :|c :|c * 4; 4c 4c * * * !|c * * * * lie * * * * >it * !|c :|c :|c :Jc 4c lie 4c * 4c * !)t 4c * :|c 4c :|c 4c :jc :(c 3k * c C Subroutine SYSTMl calculates the system current during a C transient: C SUBROUTINE SYSTMl IMPLICIT DOUBLE PRECISION (A-Z) INTEGER I DIMENSION F1(3),F2(3),F3(3),F4(3)^(3),Y(3) COMMON/blk06/t/blk 1 6/two/blk22/dt/blk23/six/blk3 1/Ibr X(l) = t X(2) = Ibr CALL FXl (Fl^) DO 10 1=1, 2 10 Y(I) = X(I)+dt*Fl(I)/two CALL FXl (F2,Y) DO 20 1=1, 2 20 Y(I) = X(I)+dt*F2(I)/two CALL FXl (F3,Y) DO 30 1=1, 2 30 Y(I) = X(I)+dt*F3(I) CALL FXl (F4,Y) DO 40 1=1, 2 40 X(I) = X(I)+dt*(Fl(I)+two*(F2(I)+F3(I))+F4(I))/six t = X(l) Ibr = X(2) RETURN END ^ 4c 4c 4: 4c 4= i)< 4e 4c 4= * 4c 4< * 4c 4= 4c 4c 4c 4c 4c 4c 4c 4c 4e 4e 4c 4c 4c 4c 4c * 4= * 4c 4c 4c 4< * 4c 4c 4c 4c lie 4c 4c 4c ik 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c Q4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 3k 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4c 4: 4c 4c 4c 4c c C Subroutine FXl defines the system differential equations: C SUBROUTINE FXl (FUN,X) IMPLICIT DOUBLE PRECISION (A-Z) DIMENSION FUN(3),X(3) COMMON/bIk05/one/blkl4/pi/blkl6/two/blk25/^lk26/Ls COMMON/blk27/Rbr/blk28/Rload/blk29/Rs/blk30A^srms FUN(l) = one FUN(2) = -(Rbr+Rs+Rload)*X(2)/Ls+DSQRT(two)*Vsrms*

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non 104 $DSIN(two*pi*f *X( 1 ))/Ls RETURN END ^ 4c ************ sk ***** !ici|c 3|C 3|C 4c * lie 4CI|< >|< * ;|c * :|c :1c * s(c 3|ciic **** I|CI(C * ifciic 4C1|C !|C ;|c 4c s|c * 4c *** 9|c Q************************************:|c******************:)::^4c****** ^*********************************************:|c****************** c C Subroutine PCETEM calculates the temperature of the PCE C during its operation: C SUBROUTINE PCETEM IMPLICIT DOUBLE PRECISION (A-Z) INTEGER I DIMENSION Gel(2),Ge2(2),Ge3(2),Ge4(2),Xl(2),Yl(2) COMMON/blkl5/Temp/blkl6/two/blk22/dt/blk23/six Xl(l) = Temp CALL FX2 (Gel,Xl) DO 10 1=1, 1 10 Y1(I) = Xl(I)+dt*Gel(I)/two CALL FX2 (Ge2,Yl) DO 20 1=1, 1 20 Y1(I) = Xl(I)+dt*Ge2(I)/two CALL FX2 (Ge3,Yl) DO 30 1=1, 1 30 Y1(I) = Xl(I)+dt*Ge3(I) CALL FX2 (Ge4,Yl) DO 40 1=1, 1 40 X1(I) = Xl(I)+dt*(Geia)+two*(Ge2a)+Ge3(I))+Ge4a))/six Temp = Xl(l) RETURN END Q***************************j(c****J^****:^*:j.;^*:^,,,5^j^*,,,;^„,j^^^^,,,^jJj,^^j^^^^^ (^*******************j^********,^,^,|,**^^^,^,,,^^^,^,^,^^^,^^^^^^^^^^^^^^jj^^^^ Subroutine FX2 defines the thermal differential equations: SUBROUTINE FX2 (FUN 1, XI) IMPLICIT DOUBLE PRECISION (A-Z) DIMENSION FUN1(2),X1(2) COMMON/blk 1 6/two/blk 1 7/Ctpce,Rtpce/blk 1 8/Numdev/blk 1 9/Tamb COMMON/blk20/Pop/blk2 1/Ppce FUNI(I) = ((Tamb-Xl(l))/Rtpce+Ppce/(two*Numdev)+Pop/two)/

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105 $Ctpce RETURN END (^****!(c***!|C*******!|e***!|t*********j|t*********>|C!|£********************** (^**************************;)c*****s|c****j(;*:),***5|j:)t*^*S^:^*;(t5,t^^j,,j,j^^^^^^ Q**************************************************************** c C Subroutine EQCONC calculates the equilibrium concentration C of No and Po: C SUBROUTINE EQCONC IMPLICIT DOUBLE PRECISION (A-Z) COMMON/blk03/No,Po/blklO/alpha,beta,Ego/blkll/Mn,Mp COMMON/blkl2/hj£/blkl3/Na/blkl4/pi/blkl5/Temp/blkI6/two COMMON/blk35/Mo/blk63/q varl = 1.5 Nc = two*(((Mn*Mo/h)*(two*pi*k*Temp/h))**varl) Nv = two*(((Mp*Mo/h)*(two*pi*k*Temp/h))**varl) EgT = Ego-alpha*Temp*Temp/(Temp+beta) Ni = DSQRT(Nc*Nv)*DEXP(-EgT*q/(two*k*Temp)) Po = (Na+DSQRT(Na*Na+two*two*Ni*Ni))/two No = Ni*Ni/Po RETURN END C**************************************************************** ^ ************************ :)C ** J(t * )|C * :((* 5|t ;jt ;|C 5|t J(5 Jj( ;)5 J|5 ^ j|5 ;(5 5|5 ^ ^ J(. Jj; ^ Jj, jjj Jj, ^ ^ jjj jjj J(J Jjj ^* *************************************************** c C Subroutine MOBON calculates the electron and hole mobilities C during the PCE on-state: C SUBROUTINE MOBON IMPLICIT DOUBLE PRECISION (A-Z) COMMON/blk01/Mmxe,Mmne,Nrfe,alfe,Mmxh,Mmnh,Nrfh,alfh COMMON/blk02/Mun,Mup/blk03/No,Po/blk04/Nmax/blk05/one Mun = Mmne+(Mmxe-Mmne)/(one+((No-i-Nmax)/Nrfe)**alfe) Mup = Mmnh+(Mmxh-Mmnh)/(one+((Po+Nmax)/Nrfh)**alfh) RETURN END C*************************il‘*********>li**>li*******************>t:**ilt:lc*

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106 C C Subroutine MOBTON calculates the electron and hole mobilities C during the PCE tum-on-state; C SUBROUTINE MOBTON IMPLICIT DOUBLE PRECISION (A-Z) COMMON/blk01/Mmxe,Mmne,Nrfe,alfe,Mmxh,Mmnh,Nrfh,alfh COMMON/blk02/Mun,Mup/blk03/No,Po/blk04/Nmax/blk05/one COMMON/blk06/t/blk07/to/blk08/tau Mun = Mmne+(Mmxe-Mmne)/(one+((Nmax*(one-DEXP((to-t)/tau)) $+No)/Nrfe)**alfe) Mup = Mmnh+(Mmxh-Mmnh)/(one+((Nmax*(one-DEXP((to-t)/tau)) $+Po)/Nrfh)**alfh) RETURN END c C Subroutine MOBINT calculates the electron and hole mobilities C during the PCE interruption-state: C SUBROUTINE MOBINT IMPLICIT DOUBLE PRECISION (A-Z) COMMON/blkOI/Mmxe,Mmne,Nrfe,alfe,Mmxh,Mmnh,Nrfh,alfh COMMON/blk02/Mun,Mup/blk03/No,Po/blk04/Nmax/blk05/one COMMON/blk06/t/blk08/tau/blk09/ti Mun = Mmne+(Mmxe-Mmne)/(one+((Nmax*DEXP((ti-t)/tau)+No) $/Nrfe)**alfe) Mup = Mmnh+(Mmxh-Mmnh)/(one+((Nmax*DEXP((ti-t)/tau)+Po) $/Nrfh)**alfh) RETURN END ^*****j|c*****:t!****!|c******!(t******!|c!(c**!|t*)|e****j|t**:)c**!(c**:)c!(£4::jc;(c:(.*:j;:)t;j;*j(jjjtj|; (2**********!|!*******************j|c***!(c*****5|cj(c*:)c:),:)cs|c*:)(j|t**:(,:(t;)cj)(*jjtj|;j(5j|5^jj;jjj C****************il!ilc******:lc*:i::l:**********:lt:ltilc*!lc********************* c C Subroutine MOB OFF calculates the electron and hole mobilities C during the PCE off-state: C SUBROUTINE MOBOFF

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non n n n 107 IMPLICIT DOUBLE PRECISION (A-Z) COMMON/blk01/Mmxe,Mmne,Nrfe,alfe,Mmxh,Mmnh,Nrfh,alfh COMMON/blk02/Mun,Mup/blk03/No,Po/blk05/one Mun = Mmne+(Mmxe-Mmne)/(one+(No/Nrfe)**alfe) Mup = Mmnh+(Mmxh-Mmnh)/(one+(Po/Nrfh)**alfh) RETURN END Q * :|c 4: * :|ciic 4c *4; :)c ** 4; ** :1c i|c 4c 4c 4c ** :|c % :|c * He ********** ii< * 4: ************ 4c !|c :|c :)c :jc :|c ^****************************3|C*************)JC********************* Q******************************:|c********************************* c C Subroutine PCEDEV is used to output given and calculated C information regarding the PCE: C SUBROUTINE PCEDEV IMPLICIT DOUBLE PRECISION (A-Z) COMMON/blk04/Nmax/blk07/to/blk08/tau/blk09/ti/blkl3/Na COMMON/blk 1 5/Temp/blk 17/Ctpce,Rtpce/blk 1 8/N umdev/blk 1 9/Tamb COMMON/blk26/Ls/blk29/Rs/blk36/Ipceof,Ipceon/blk38/d COMMON/blk40/l/blk44/Pjopt/blk49/tauSRH/blk50/testl COMMON/blk51/test2/blk52/tf/blk53/Toff/blk55A^,w/blk56/A COMMON/blk57/tauAu/blk58/Ton COMMON/blk59/Ppceof,Ppceon,Rpceof,Rpceon,Vpceof,Vpceon COMMON/blk60/Rloadi/bIk61/Ipcemx/blk62/Popt/blk65/Ipce COMMON/blk67/Ipcetf, Vstf/blk68/Ipceti, Vsti,tendi,dtint COMMON/blk69/Ipceto, Vsto Output the number of parallel devices to be used: WRITE (6,10) INT(Numdev) 10 FORMAT (IX, Â’NUMBER OF PCE DEVICES IN PARALLEL: Â’,1X,I4) Output the given device parameters: WRITE (6,20) 20 FORMAT (/1X,Â’GIVEN DEVICE PARAMETERS:Â’) WRITE (6,21) Na 21 FORMAT (15X,Â’Na :Â’,lX,E10.3,lX,Â’m-cu inv.Â’) WRITE (6,22) Nmax 22 FORMAT (15X,Â’Nmax :Â’,lX,E10.3,lX,Â’m-cu inv.Â’) WRITE (6,23) tauAu 23 FORMAT (15X,Â’tauAu :Â’,lX,E10.3,lX,Â’secÂ’) WRITE (6,24) tauSRH

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108 24 FORMAT (15X,Â’tauSRH:MX,E10.3,lX,Â’secÂ’) WRITE (6,25) tau 25 FORMAT (15X,Â’tau :MX,E10.3,lX,Â’secÂ’) C C Output the calculated device dimensions: C WRITE (6,30) 30 FORMAT (/1X,Â’DEVICE DIMENSIONS;Â’,28X, TOTALÂ’) WRITE (6,31) 1,1 31 FORMAT (15X,Â’l :Â’,lX,E10.3,lX,Â’mÂ’,9X,E10.3) WRITE (6,32) d,d*Numdev 32 FORMAT (15X,Â’d :Â’,lX,E10.3,lX,Â’mÂ’,9X,E10.3) WRITE (6,33) w,w 33 FORMAT (15X,Â’w :Â’,lX,E10.3,lX,Â’mÂ’,9X,E10.3) WRITE (6,34) A,A*Numdev 34 FORMAT (15X,Â’A :Â’,lX,E10.3,lX,Â’m-sqÂ’,6X,E10.3) WRITE (6,35) V,V*Numdev 35 FORMAT (15X,Â’V :Â’,lX,E10.3,lX,Â’m-cuÂ’,6X,E10.3) C C Output the calculated steadystate-on conditions: C WRITE (6,40) 40 FORMAT (/1X,Â’DEVICE ON-CONDITIONS:Â’) WRITE (6,41) Rpceon,Rpceon/Numdev 41 FORMAT (15X,Â’Rpceon:Â’,lX,E10.3,lX,Â’ohmsÂ’,6X,E10.3) WRITE (6,42) Vpceon,Vpceon 42 FORMAT (15X,Â’Vpceon:Â’,lX,E10.3,lX,Â’VrmsÂ’,6X,E10.3) WRITE (6,43) Ipceon,Ipceon*Numdev 43 FORMAT (15X,Â’Ipceon:Â’,lX,E10.3,lX,Â’ArmsÂ’,6X,E10.3) WRITE (6,44) Ipcemx,Ipcemx*Numdev 44 FORMAT (15X,Â’Ipcemx:Â’,lX,E10.3,lX,Â’AmpsÂ’,6X,E10.3) WRITE (6,45) Ppceon,Ppceon*Numdev 45 FORMAT (15X,Â’Ppceon:Â’,lX,E10.3,lX,Â’wattsÂ’,5X,E10.3) WRITE (6,46) Popt,Popt*Numdev 46 FORMAT (15X,Â’Popt :Â’,lX,E10.3,lX,Â’wattsÂ’,5X,E10.3) WRITE (6,47) Pjopt,Pjopt*Numdev 47 FORMAT (15X,Â’Pjopt :Â’,lX,E10.3,lX,Â’wattsÂ’,5X,E10.3) C C Output the calculated steadystate-off conditions: C WRITE (6,50) 50 FORMAT (/1X,Â’DEVICE OFF-CONDITIONS:Â’) WRITE (6,51) Rpceof,Rpceof/Numdev

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uuu uuu ouu 109 51 FORMAT (15X,Â’Rpceof:MX,E10.3,lX, Â’ohmsÂ’, 6X.E10.3) WRITE (6,52) Vpceof,Vpceof 52 FORMAT (15X,Â’Vpceof:Â’,lX,E10.3,lX,Â’VrmsÂ’,6X,E10.3) WRITE (6,53) Ipceof,Ipceof*Numdev 53 FORMAT (15X,Â’Ipceof:Â’,lX,E10.3,lX,Â’ArmsÂ’,6X,E10.3) WRITE (6,54) Ppceof,Ppceof*Numdev 54 FORMAT (15X,Â’Ppceof:Â’,lX,E10.3,lX,Â’wattsÂ’,5X,E10.3) Output the thermal parameters: WRITE (6,60) 60 FORMAT (/1X,Â’THERMAL PARAMETERS:Â’) WRITE (6,61) Rtpce 61 FORMAT (15X,Â’Rtpce :Â’,1X,E10.3,1X,Â’K/WÂ’) WRITE (6,62) Ctpce 62 FORMAT (15X,Â’Ctpce :Â’,lX,E10.3,lX,Â’W.sec/KÂ’) WRITE (6,63) Tamb 63 FORMAT (15X,Â’Tamb :Â’,1X,E10.3,1X,Â’KÂ’) WRITE (6,64) Ton 64 FORMAT (15X,Â’Ton :Â’,1X,E10.3,1X,Â’KÂ’) WRITE (6,65) Toff 65 FORMAT (15X,Â’Toff :Â’,1X,E10.3,1X,Â’KÂ’) Output the system parameters: WRITE (6,70) 70 FORMAT (/1X,Â’SYSTEM PARAMETERS:Â’) WRITE (6,71) Ls 71 FORMAT (15X,Â’Ls :Â’,1X,E10.3,1X,Â’HÂ’) WRITE (6,72) Rs 72 FORMAT (15X,Â’Rs :Â’,lX,E10.3,lX,Â’ohmsÂ’) WRITE (6,73) Rloadi 73 FORMAT (15X,Â’Rload :Â’,lX,E10.3,lX,Â’ohmsÂ’) Output the operating conditions: 100 IF (INT(test2).NE.2.AND.INT(test2).NE.3.AND. $INT(test2).NE.4) GO TO 400 WRITE (6,80) 80 FORMAT (/1X,Â’0PERATING CONDITIONS:Â’) IF (INT(test2).NE.2.AND.INT(test2).NE.4) GO TO 200 WRITE (6,81) Vstf 81 FORMAT (15X,Â’Vstf :Â’,1X,E13.6,1X,Â’VÂ’)

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no WRITE (6,82) Ipcetf 82 FORMAT (15X,Tpcetf:’,lX,E13.6,lX,’A’) WRITE (6,83) tf 83 FORMAT (15X,’tf :’,lX,EI3.6,lX,’sec’) 200 IF (INT(test2).NE.3.AND.INT(test2).NE.4) GO TO 400 IF (INT(testl).EQ.l) GO TO 300 WRITE (6,84) Vsto 84 FORMAT (15X,’Vsto :’,1X,E13.6,1X,’V’) WRITE (6,85) Ipceto 85 FORMAT (15X,Tpceto:’,lX,EI3.6,lX,’A’) WRITE (6,86) to 86 FORMAT (15X,’to :MX,E13.6,lX,’sec’) 300 WRITE (6,88) Vsti 88 FORMAT (15X,’Vsti :’,1X,E13.6,1X,’V’) WRITE (6,89) Ipceti 89 FORMAT (15X,Tpceti:’,IX,E13.6,IX,’A’) WRITE (6,90) ti 90 FORMAT (15X,’ti :MX,E13.6,lX,’sec’) WRITE (6,91) tendi 91 FORMAT (15X,’tendi :’,lX,E13.6,lX,’sec’) WRITE (6,92) dtint 92 FORMAT (15X,’dtint :’,lX,E13.6,lX,’sec’) 400 IF (INT(test2).EQ.l) GO TO 500 IF (ABS(Ipce).GT.1.0D+10) GO TO 600 500 IF (Temp.LE.1000) GO TO 900 600 DO 700 1=1, 3 700 WRITE (6,800) 800 FORMAT (//lX,’Sorry !!! PCE blown-up !!!’) 900 RETURN END (^******************j(,****:)c**j(,*****:)c**********j),*,)c**,|;*,(c*,),*;)c:(t,|t,),****,(5,(c (^***j|c*****j|c*s|c**j|e**********J|c*J|t*J|<*****s|(*!|t************************** J|C ************************* :)„|t ** J), ,|t ,(5 ,(5 ,|j ,(5 ,1; Jj;

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REFERENCES [1] B. Y. Hwang, F. A. Lindholm, and R. B. Hammond, “Methodology for Calculating Turn-Off Transients of Photoconductive Circuit Elements in Picosecond Optoelectronics,” IEEE Journal of Quantum Electronics , Vol. QE-19, No. 4, April 1983, pp. 648-657. [2] C. P. Triaros, D. P. Carroll, and F. A. Lindholm, “Photoconductive Switches for AC Circuit Protection,” IEEE Transactions on Electron Devices , Vol. 37, No. 12, Dec. 1990, pp. 2526-2531. [3] D. H. Auston, “Picosecond Optoelectronic Switching and Gating in Silicon,” Applied Physics Letters , Vol. 26, No. 3, Feb. 1975, pp. 101-103. [4] W. C. Nunnally and R. B. Hammond, “80-MW Photoconductor Power Switch,” Applied Physics Letters . Vol. 44, Feb. 1984, pp. 980-982. [5] R. A. Petr, W. C. Nunnally, and C. V. Smith, “Cryogenic Silicon Photoconductive Switches for High Power Lasers,” SPIE Proceedings . Vol. 871, Jan. 1988, pp. 297-306. [6] P. A. Basore, D. T. Rover, and A.W. Smith, “PCID Version 2: Enhanced Numerical Solar Cell Modeling,” 20th IEEE Photovoltaic Specialists Conf. , Las Vegas, Sept. 1988. [7] L. C. Roberts, “The Fabrication and Testing of Silicon Photoconductive Circuit Elements for Power System Applications,” Thesis, University of Florida, 1990. [8] A. E. Iverson, “The Mathematical Modeling of Photoconductive Power Switches,” Transactions of the Society for Computer Simulation . Vol. 5, No. 3, July 1988, pp. 175-191. [9] S. E. Thompson and F. A. Lindholm, “Influence of Heavily Doped Contacts on Photoconductive Switch Properties,” IEEE Transactions on Electron Devices, Vol. 37, No. 12, Dec. 1990, pp. 2542-2553. Ill

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112 [10] S. M. Sze, Physics of Semiconductor Devices , Second ed., Wiley-Interscience, New York, 1981. [11] F. J. Zutavem, G. M. Loubriel, M. W. O’Malley, L. P. Shanwald, W. D. Helgerson, D. L. McLaughlin, and B. B. McKenzie, “Photoconductive Semiconductor Switch Experiments for Pulsed Power Applications,” IEEE Transactions on Electron Devices , Vol. 37, No. 12, Dec. 1990, pp. 2472-2477. [12] B. G. Streetman, Solid State Electronic Devices , Second ed., Prentice Hall, Englewood Cliffs, New Jersey, 1980. [13] C. D. Thurmond, “The Standard Thermodynamic Functions for the Formation of Electrons and Holes in Ge, Si, GaAs, and GaP,” Journal of Electrochemical Society , Vol. 122, No. 8, Aug. 1975, pp. 1133-1141. [14] D. M. Caughey and R. E. Thomas, “Carrier Mobilities in Silicon Empirically Related to Doping and Field,” Proceedings of the IEEE , Dec. 1967, pp. 2192-2193. [15] K. Misiakos, Ju-Sung Park, and A. Neugroschel, “Carrier Lifetimes in Highly Injected Silicon,” Journal of Applied Physics , Vol. 67, No. 5, March 1990, pp. 2576-2582. [16] J. H. Seely and R. C. Chu, Heat Transfer in Microelectronic Equipment , M. Dekker, New York, 1972. [17] F. Kreith and W. Black, Basic Heat Transfer , Harper & Row, New York, 1980. [18] A. H. Iversen and S. Whitaker, “A Uniform Temperature, Ultra High Heat Flux Liquid Cooled, Power Semi-Conductor Package,” lAS-IEEE Annual Meeting, San Diego, Oct. 1989. [19] H. D. Barber, “Effective Mass and Intrinsic Concentration in Silicon,” Solid State Electronics , Vol. 10, No. 11, Nov. 1967, pp. 1039-1051. [20] G. D. Pitt and J. Lees, “The Xic Conduction Band Minimum in High Purity Epitaxial n-Type Gallium Arsenide,” Solid State Communications , Vol. 8, No. 7, April 1970, pp. 419-495.

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113 [21] O. V. Emelyanenko, “Dependence of the Thermal EMF on the Hole Generation in Gallium Arsenide Crystals, Phys. Status Solidi , Vol. 8, No. 3, March 1965, pp. K155-K158. [22] R. A. Sinton and R. M. Swanson, “Recombination in Highly Injected Silicon,” IEEE Transactions on Electron Devices , Vol. ED-34, No. 6, June 1987, pp. 1380-1389. [23] P. T. Lands berg, “The Band-Band Auger Effect in Semiconductors,” Solid State Electronics , Vol. 30, No. 11, Nov. 1987, pp. 1107-1115.

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BIOGRAPHICAL SKETCH Christos P. Triaros was bom in Famagusta, Cyprus, on December 25, 1961. He received the B.S.E.E. and M.E. in electrical engineering degrees from the University of Florida, Gainesville, in 1986 and 1988, respectively. He is currently working toward the Ph.D. degree in electrical engineering at the University of Florida, which he expects to receive in May of 1991. His research involves a study to investigate the feasibility of photoconductive switches for protective switching applications in AC power transmission and distribution circuits. 114

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I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Dennis P. Carroll, Chairman Professor of Electrical Engineering I certify that I have read this smdy and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Gys Bosman Professor of Electrical Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Assistant Professor of Electrical Engineering I certify that 1 have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Fred A. Lindholm Professor of Electrical Engineering

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I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. 'I / Amost Neugroschel Professor of Electrical Engineering 1 certify that I have read this smdy and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Arun K. Varma Professor of Mathematics This dissenation was submitted to the Graduate Faculty of the College of Engineering and to the Graduate School and was accepted as partial fulfillment of the requirements for the degree of Doctor of Philosophy. May 1991 Dean, College of Engineering Madelyn M. Lockhart Dean, Graduate School