
Citation 
 Permanent Link:
 http://ufdc.ufl.edu/AA00037501/00001
Material Information
 Title:
 Physical modeling of MOScontrolled highvoltage devices for integrated circuit computeraided design
 Creator:
 Kim, YeongSeuk, 1957
 Publication Date:
 1990
 Language:
 English
 Physical Description:
 vi, 163 leaves : ill. ; 29 cm.
Subjects
 Subjects / Keywords:
 Electric current ( jstor )
Electric potential ( jstor ) Electrons ( jstor ) Latch up ( jstor ) Modeling ( jstor ) Narrative devices ( jstor ) Simulations ( jstor ) Spices ( jstor ) Subroutines ( jstor ) Transistors ( jstor ) Computeraided design ( lcsh ) Dissertations, Academic  Electrical Engineering  UF Electrical Engineering thesis Ph. D Integrated circuits  Design and construction ( lcsh ) Metal oxide semiconductors ( lcsh ) Transistors ( lcsh )
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 bibliography ( marcgt )
nonfiction ( marcgt )
Notes
 Thesis:
 Thesis (Ph. D.)University of Florida, 1990.
 Bibliography:
 Includes bibliographical references (leaves 159162).
 General Note:
 Typescript.
 General Note:
 Vita.
 Statement of Responsibility:
 by YeongSeuk Kim.
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 University of Florida
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 University of Florida
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 The University of Florida George A. Smathers Libraries respect the intellectual property rights of others and do not claim any copyright interest in this item. This item may be protected by copyright but is made available here under a claim of fair use (17 U.S.C. Â§107) for nonprofit research and educational purposes. Users of this work have responsibility for determining copyright status prior to reusing, publishing or reproducing this item for purposes other than what is allowed by fair use or other copyright exemptions. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder. The Smathers Libraries would like to learn more about this item and invite individuals or organizations to contact the RDS coordinator (ufdissertations@uflib.ufl.edu) with any additional information they can provide.
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PHYSICAL MODELING OF MOSCONTROLLED HIGHVOLTAGE
DEVICES FOR INTEGRATED CIRCUIT COMPUTERAIDED DESIGN
By
.XEONGSEUK KIM
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
1990
UNIVRITY CF I A LIBRARIES
ACKNOWLEDGEMENTS
I wish to express my sincere appreciation to my advisor, Professor Jerry G. Fossum, for his support and guidance throughout the course of this work. I also would like to thank Professors Dorothea E. Burk, Sheng S. Li, Khai D.T. Ngo, and Kevin S. Jones for their participation on my supervisory committee.
I am grateful to Dr. M. Ayman Shibib of AT&T Bell Laboratories and Mr. Richard K. Williams of Siliconix Inc. for providing the test devices and helpful discussions. Thanks are also extended to many of my friends, JinYoung Choi, Joohyun Jin, SangGug Lee, Edward Solley, HaeSeok Cho, Dongwook Suh, Keith Green, Ghyboong Hong, DeokSu Jeon, and HanJin Cho, for helpful discussions and encouragement. Last I am deeply indebted to my parents, parentsinlaw, my brother and sisters, and my wife for their love and support.
TABLE OF CONTENTS
ACKNOWLEDGEMENTS ......... .................... ii
ABSTRACT .................................... v
CHAPTERS
1 INTRODUCTION ...................................... 1
2 EFFECTS OF THE BUFFER LAYER ON VIGBT PERFORMANCE ... 7 2.1 Introduction ........................... 7
2.2 VIGBT Model ................................... 10
2.2.1 SteadyOnState ..................... 10
2.2.2 Transient TurnOff ..... ................... ..16
2.3 TheoreticalExperimental Interpretations ........ 18 2.4 Summary ........ .............................. .28
3 STATIC AND DYNAMIC LATCHUP IN THE LIGBT ........ 30 3.1 Introduction ......... .................. 30
3.2 Numerical Simulations ................... 32
3.2.1 Static LatchUp ...... ..................... .34
3.2.2 Dynamic LatchUp ....... ..................... 40
3.3 SPICE Model ........ ........................... ..47
3.4 Model Verification ...... ...................... ..53
3.5 Summary ........... .............................. 57
4 PHYSICAL VDMOST MODELING FOR HIGHVOLTAGE IC CAD . . 62 4.1 Introduction ........ .......................... ..62
4.2 Model ........... ............................... 64
4.2.1 Channel Region ........ ...................... 64
4.2.2 Drift Region ....... ........................ ..69
4.2.3 Parasitic BJT ...... ....................... ..74
4.3 SPICE Model ........ ........................... ..78
4.4 Model Verification ...... ...................... ..83
4.5 Summary .......... .............................. 90
iii
5 NEW PHYSICAL INSIGHTS AND MODELS FOR LDMOST IC CAD. 91 5.1 Introduction .......................... 91
5.2 New Insights By Numerical Simulations ........... 94
5.2.1 LDD LDMOST ......... ......................... 94
5.2.2 RESURF LDMOST ...... ...................... .101
5.3 LDMOST Model ......... ......................... 104
5.3.1 LDMOST Channel ...... ..................... ..105
5.3.2 LDD Region ......... ........................ 107
5.3.3 npn BJT ....... .......................... ...111
5.4 SPICE Simulations And Discussion ............ ...116
5.5 Summary ........ ............................. ..126
6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK ........... 128
APPENDICES
A BASE CHARGE PARTITIONING IN WIDEBASE BJT'S ..... ....131
B MODEL IMPLEMENTATION IN SPICE VIA UDCS'S ........ ...136
REFERENCES ............ ................................ 159
BIOGRAPHICAL SKETCH ....... .......................... .163
Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
PHYSICAL MODELING OF MOSCONTROLLED HIGHVOLTAGE
DEVICES FOR INTEGRATED CIRCUIT COMPUTERAIDED DESIGN By
YEONGSEUK KIM
August 1990
Chairman: Dr. J. G. Fossum
Major Department: Electrical Engineering
This dissertation presents methodology for physical chargebased modeling of MOScontrolled highvoltage (HV) devices for integrated circuit (HVIC) computeraided design (CAD). New models for two different MOScontrolled HV devices, the insulatedgatebipolar transistor (IGBT) and the doublediffused MOS transistor (DMOST), are developed. The effects of the buffer layer and static/dynamic latchup in the IGBT are characterized, and quasisaturation, spacechargelimited current flow, and effects of the inherent BJT in both vertical and lateral DMOSTs are modeled. These effects, which are not properly represented in conventional equivalent(sub)circuit models, are physically and sometimes seminumerically accounted for in our models. Twodimensional
numerical device simulations were used extensively to study the effects and to aid the model development.
The developed models are implemented in the circuit simulator SPICE via FORTRAN subroutines (UDCSs). With only known structural (device) parameters and crudely extracted model parameters, device/circuit simulations favorably predicted measured characteristics of test devices. The models in SPICE provide a capability of mixedmode device/circuit simulation, which is not afforded by other equivalent(sub)circuit models, and hence can facilitate computeraided optimal device/circuit design of HVICs.
CHAPTER 1
INTRODUCTION
Recent advances in highvoltage (HV) device technology have enabled the integration of HV devices with lowvoltage control circuitry on the same chip. Such highvoltage integrated circuits (HVICs) now commonly use MOScontrolled HV devices, exploiting the high input impedance of the MOS gate relative to that of power bipolarjunction transistors (BJTs). The MOS channel is usually formed by a doublediffusion process; sequential diffusion of p and ntype impurities in the epi (or substrate) region yields the MOS channel as shown in Fig. 1.1. The doublediffusion process is widely used for HV devices because of easier process steps to achieve short channels while realizing high breakdown voltages. MOScontrolled HV devices built with the doublediffusion process include vertical and lateral insulatedgatebipolar transistors (IGBTs) and doublediffused MOS transistors (DMOSTs). The difference between these two structures is due to the anode (drain) design; the IGBT is a modification of the DMOST structure made by forming a pn junction at the drain contact as shown in Fig. 1.1 (for nchannel devices).
Cathode
Gate
Sn+poly
Drain/
Anode
n
or p+
ndrift region
Fig. 1.1 Crosssectional view of the IGBT (p+diffusion in
the anode) and the DMOST (n+diffusion in the drain). Typical gate oxide thickness and channel
length are 0.1 jim and 2 /im, respectively.
3
Along with the matured process technology of HV devices and integrated circuits, CAD simulation tools should be developed to support optimal device and circuit design. The equivalent(sub)circuit SPICE models for HV devices that are used today are too empirical and do not properly account for the unique behavior of the HV devices, such as latchup in the IGBT and quasisaturation and spacechargelimited current flow in the DMOST. Therefore the development of physically based models for MOScontrolled HV devices, and implementation into the simulation tool, e.g., SPICE, are needed.
The purpose of this dissertation is to develop and implement physical models of MOScontrolled HV devices, i.e., IGBTs and DMOSTs, for HVIC CAD. The effects of the buffer layer and static/dynamic latchup in the IGBT are characterized, and quasisaturation, spacechargelimited current flow, and effects of the inherent BJT in both vertical and lateral DMOSTs are modeled. The developed models are implemented in the circuit simulator SPICE via FORTRAN subroutines (UDCSs). The major contributions made in this dissertation are
(1) the formulation and solution of the steadystate
and transient carrier transport problems in the IGBT
including a buffer layer;
(2) the study of static and dynamic latchup in the IGBT
based on twodimensional numerical device simulations and the development of models for circuit simulation;
4
(3) the development and experimental verification of
physical chargebased models for both vertical and
lateral DMOSTs;
(4) the implementation of the IGBT and DMOST models into
SPICE using userdefined controlled sources (UDCSs).
In Chapter 2, a theoreticalexperimental study of the effects of the buffer layer on steadystate and transient vertical IGBT (VIGBT) performance is presented. Results indicate that previous studies are incomplete and hence misleading, and that in fact optimal design criteria for the buffer layer must be defined based on more comprehensive analyses. The study gives physical insight, needed in such definition, and describes proper model parameterextraction techniques not previously considered.
In Chapter 3, an insightful study of static and dynamic latchup in the lateral IGBT (LIGBT), based on extensive twodimensional numerical device simulations, is described. The insight is then used as a basis for developing a physical SPICE LIGBT model, which is useful for device simulation and design (e.g., for latchup immunity) as well as for HVIC simulation. The basic mechanisms underlying latchup in the LIGBT are identified for various excitations. The significance of the effective pin diode that materializes via the conductivity modulation in the regenerative process is stressed in the simulations, as is the importance of nonquasistatic bipolar
5
transistor behavior, heretofore unrecognized. The SPICE model is supported by measurements of test devices and by the numerical device simulations.
In Chapter 4, a physical, seminumerical chargebased model for vertical DMOSTs (VDMOSTs) is developed and implemented in SPICE. The model is derived from regional quasistatic analyses of carrier transport which implicitly characterize the device currents and charges and which require numerical solution. NewtonRaphson iterative device solutions are derived within the circuit nodal analysis framework of SPICE. PISCES simulations and measurements of test devices support the model, which is demonstrated in dc and transient SPICE simulations of VDMOSTs and HVICs.
In Chapter 5, two different structures of the lateral DMOST (LDMOST), i.e., the LDD and RESURF LDMOSTs, are studied extensively using the twodimensional device simulator PISCES. The PISCES simulations provide new physical insights on the normal and reversemode operations of the LDMOSTs, which are used for developing the composite LDD LDMOST model. In the modeling methodology, the LDD LDMOST is regionally partitioned into three main components (the channel, the drift region, and the npn BJT), and carriertransport problems in each region are solved. The composite model is implemented in SPICE for HVIC CAD and is supported by measurements. The modeling methodology is also applicable to the RESURF LDMOST.
6
In Chapter 6, the main accomplishments of this dissertation are summarized, and suggestions for further research are discussed.
Appendix A, related to Chapter 3, describes the algebraic manipulations of a base charge partitioning to represent nonquasistatic behavior in the bipolar transistor of the IGBT.
Appendix B lists the UDCS source code of the LDMOST SPICE model developed in Chapter 5.
CHAPTER 2
EFFECTS OF THE BUFFER LAYER ON VIGBT PERFORMANCE
2.1 Introduction
This chapter presents a bufferlayer model for the vertical IGBT (VIGBT) [Bali84]. The model, based on the onedimensional representation of the device, accounts for bufferlayer effects on both steadystate and transient characteristics of the VIGBT. The carriertransport (continuity/ambipolar) equations in the quasineutral regions of the device are solved to yield the dc currentvoltage dependence I1(1'1) and the turnoff transient characteristics 14(t) of the VIGBT. Some of the modeling is applicable as well to the lateral IGBT with a buffer layer, which is discussed in the next chapter.
The VIGBT, also called the COMFET [Rus83], has recently emerged as a useful highvoltage power switch. It is a merged MOS/bipolar structure that exploits the advantages of MOS and bipolar devices to yield low forward (ON) voltage drop, fast switching time, and high input impedance.
The basic structure of the vertical nchannel IGBT, shown in Fig. 2.1, has a DMOST merged with a widebase pnp BJT. The n+buffer layer [Goo83] between the nbase and the p+emitter is commonly included to prevent punchthrough in the forwardblocking mode and indeed to enhance the device performance
Fig. 2.1 Unitcell structure of vertical nchannel IGBT with
n+buffer layer. The external circuitry and gate bias indicated correspond to a transient turnoff
from the steadyONstate.
9
[Goo83, Nak85]. Such enhancement has been experimentally demonstrated as an increase in the (static) current required to latch the pnpn structure [Goo83] and as an improvement in the tradeoff between the steadyONstate voltage drop and the turnoff time [Nak85]. A recent theoretical study [Kuo86] implied design criteria for the epitaxial (n and n+) layers of the device to effect this tradeoff. The study was not sufficiently rigorous however to guarantee optimal designs, as demonstrated in this chapter.
A comprehensive theoretical study [Hef86] of bufferlayer effects on VIGBT performance, predicting that the buffer layer decreases the switching energy loss, was recently presented. This study involved much mathematical detail but little experimental support, and hence its results cannot be put into proper perspective because the relative significance of various physical mechanisms cannot be ascertained. In this chapter we use a similar, but simpler and more insightful model to fully explain performance data, including new experimental results given herein that seem to contradict [Nak85, Kuo86] and that suggest optimal design criteria for the buffer layer. The simple analytic model accounts for bufferlayer effects on both steadystate and transient characteristics of the VIGBT. We support the model expermentally, introducing useful parameterextraction techniques, and we discuss its utility alluded to above, explaining the seemingly contradictory data.
10
2.2 VIGBT Model
Our study of the buffer layer is done effectively using a simple model to describe both steadystate and transient characteristics of the VIGBT. The model is based on a regional analysis [Hef86, McD85, Fos86] of the onedimensional representation of the vertical p+n+np BJT in the VIGBT illustrated in Fig. 2.2.
2.2.1 SteadyONState
In the steadyONstate, a voltage 1) is applied as shown between the emitter (anode) and collector (cathode) terminals, and the base is driven by the DMOST, the gate of which is biased above the threshold voltage to enable ONstate conduction. Consistent with typical operation, we assume highlevel injection (p  n) in the quasineutral nbase region, and lowlevel injection in the n+buffer and p+emitter regions. We further neglect recombination in the relatively narrow buffer layer, an assumption which we have found to be reasonable for typical devices. We stress that the primary effect of the buffer layer on the device performance is manifested through the carrier transport across the layer, irrespective of any recombination in the layer. Additional simplification of the steadystate analysis is effected by noting that the BJT is constrained to operate in (near) the forwardactive mode, with negligible basewidth modulation, since the voltage drop across the DMOST is small [Fos86J.
VAO?
IA
X=O Wjf WiIII'i
ili II
n+ n p
(Emitter) (Buffer) (Base) (Collector)
lil I 
4wt.
Fig. 2.2 Onedimensional representation of vertical p+n+np
BJT in the VIGBT. The junction spacecharge regions
are indicated by the dashed lines.
4 WB 
__01
12
Using a regional modeling approach (region boundaries are defined in Fig. 2.2), we first solve the steadystate ambipolar transport equation in the quasineutral nregion, obtaining [Fos88]
inii +
p(,) p fI ) 711
where LA is the ambipolar diffusion length and lV=B',t is the quasineutral base width. Note in (2.1) that the carrier density drops to zero at the edge of the basecollector depletion region (:r T)+ï¿½TV). The analogous solution in the quasineutral n+buffer layer, for a uniform doping density and negligible recombination, is P(Tf+)  p(O)
1(x) = f. +p(O) (2.2)
In (2.2) we have used the fact that the width of the
n+n spacecharge region is much narrower than the bufferlayer width 117, but have properly accounted the significant difference between p(1f1) and p(TV). In fact, for quasiequilibrium in the spacecharge region, IT (ip)A)f = fI' (v)12 (2.3) where NDf is the bufferlayer doping density.
To derive the dc currentvoltage dependence 1II(I1) of the VIGBT and relate it to the bufferlayer properties, we must connect the boundary hole densities, p(O), p(117), p(IT f) in
13
(2.1) and (2.2), to the terminal conditions. To make this connection, we first express the hole current density in the buffer layer as
1p (0 < .z < IT+)  (T) f (2.4)
where D,f is the bufferlayer hole diffusivity. The electron
current density at X = 0 is, for negligible recombination in the p+n+ spacecharge region, defined by the recombination in the quasineutral p+emitter [McD85]:
.]NO
JN (0) (No P0) (2.5)
where JVo is the electron saturation current density for the
p+emitter. Combining (2.4) and (2.5) then yields the total device current density in terms of p(O) and p(IT+):
( ï¿½ ~~ ~ f,,()
,+= +)(0)  qDej) V+) (2.6)
A second expression for .JA in terms of the boundary hole densities is derived as follows. Applying 3A Jp + JN, with
) f: ii, at the edge (;r = T7) of the quasineutral base, and noting that JV (v)  JV (0), we obtain [McD85] , (0) z  IT ) (2.7) J+ I0) _  + qDA T f
where b is the electronhole mobility ratio and DA is the ambipolar diffusivity in the base region. Now (2.1), (2.5), and (2.7) give
1 + , .14\, 1 + 1, (_ h t11./L ) (2.8)
JA = l ,(0) +4 11()1F) (2.8)
The three equations (2.3), (2.6), and (2.8) define the boundary hole densities in terms of JA but also involve
TV, another unknown variable. To define I(1',) then, two additional expressions relating V4 to the unknown variable must be derived. Referring to Fig. 2.1, we write I', as the sum of the internal voltage drops:
1= + Y+n + 1''+' ï¿½ l;,, + IARs + IJIR.Io.,, (2.9) where 1A =AJ4, IB =AJB, and A is the device area. In (2.9), 1 = I  (0 "O)7ND (2.10)
is the drop across the emitterbuffer junction,
,V',,L (; (2.11)
is the drop across the bufferbase junction, .ND, is the epi doping density, and
tIrm
I q(1 + b)pb, p(x} 1 [(vis the drop across the (conductivitymodulated) nepi region, which is approximated as the integral of the electric field [McD85] from 11 f to 1,,, the point at which p(.) in (2. 1) equals N0D. The last two terms in (2.9) are ohmic drops across the
15
extrinsic series resistance RS and across the DMOST through which the BJT base current, I, flows in the steady state. Note that the DMOST drop equals (for normal operation below latchup) the reverse bias on the basecollector junction, which we have assumed is small. The final relation needed
to characterize IA(1'I) is
JI q h.()dX + JN(O) (2.13)
which equates the base current to the integrated recombination in the quasineutral base and emitter regions. In (2.13), rH is the highinjection carrier lifetime in the base.
The resulting system of equations underlying (2.9) can be solved numerically to give 14(1'4), and incidently the BJT current gain, 3 = (,1 1y)/IB, which indicates (for the onedimensional structure) how the VIGBT (BJT emitter) current is divided between the DMOST and the BJT collector. The results depend on the structural device parameters and doping densities, including the bufferlayer width 11f and (uniform) doping density NDf, as well as ry, the highinjection carrier lifetime in the nbase region, and JVo, the electron saturation current density in the p+emitter region. To make the onedimensional analysis representative of actual VIGBTs, we use a semiempirical constant A. (<1) that accounts for multidimensional carrier flow. Crudely K4 is the ratio of the collector and emitter areas (Fig. 2.1), and therefore
16
IK4/[ I(1 +(1  KA). We stress that models based strictly on onedimensional analyses [Nak85, Kuo86, Hef86] can be quite misleading.
2.2.2 Transient TurnOff
The unique transient turnoff characteristic of the VIGBT, comprising an initial rapid drop in forward current followed by a slower decay, was previously modeled [Fos86] without accounting for the buffer layer. An extended version of this model, derived straightforwardly following Fossum and McDonald [Fos86], is used here to account for the bufferlayer effects. The initial rapid drop, I, is modeled as in Fossum and McDonald [Fos86], but is based on the steadystate characterization including the buffer layer described above. The slower transient, TIf(t), is modeled as Q,,(t)/t,, [Fos86], where 1,, is the (average) base transit time, but now the hole charge in the quasineutral base, Q,,, is governed by a modified [Hef86] differential equation (in time t) which accounts for the buffer layer in the relation between Q, and Q,, the minority electron charge in the quasineutral emitter:
IB = QM+ + f+ 0 (2.14)
where r,, is the effective recombination time for the electrons in the emitter and dQ,/dt is negligibly small. Using the steadystate analysis in the previous subsection, in
17
particular (2.3), (2.6), and (2.8), and assuming quasistatic conditions for the transient, we can show that Qn =CQ + C2Qp (2.15) where C, and C, are constants given by C1  4q2 ( 4r.,,, )ir 1  II7.Jvij1f/bqD,ff7, (2.16)
Aq B (T IVn )21X~~qD,
and
C= 411fr"..x.f 1 (2.17)
q(T!1B  XIm) III 1  11.f Jx1AvDJbqD,,j,(
In (2.16) and (2.17), 1'd,, is the width (.,, in Fig. 2.1) of the basecollector junction depletion region corresponding to IA  I! [Fos86].
The differential equation, which is quasistatic, is nonlinear, but can be solved analytically to give 1' ( tï¿½ l t ! H( f. 1 8 )
1I4q , ,,1  trH(,ff)]
where I1 = 11,AW is the current at the beginning of the slower transient phase of the turnoff [Io is characterized by the steadyONstate analysis underlying (2.9) ], and rll(ff) is an effective carrier lifetime which differs from rH because of the presence of the buffer layer:
1 1 4.JV1 Np
 + A 1 f ) (2.19) rI(cff) 111 q ( IT i'/ l .r,h. ,,, ,
The remaining terminology in (2.18) and (2.19) is defined in Fossum and McDonald [Fos86]. We note that if 1V./ approaches
zero (viz., no buffer layer), TJl((ff) approaches TI!, and (2.18) simplifies to the result derived in Fossum and McDonald [Fos86]. Physically, the second term on the right side of (2.19) represents the effect of recombination in the p+emitter on 14(t), influenced by the buffer layer through which the recombining electrons must flow. Hence even with a buffer layer in place, if JNI) becomes negligibly small, then also TrH(,ff) 2 Tl1 and 11(t) 1 lp . p(f/rH).
2.3 TheoreticalExperimental Interpretations
VIGBTs fabricated at RCA/DSRC were measured. Typical 14(V1) data taken from an nchannel device (with the gate biased at 10 V, about 8 V above the threshold voltage) are plotted in Fig. 2.3. The simulated characteristic, also shown, was derived from the model outlined in Section 2.2, using known structural device parameters and doping densities. The key model parameters, i.e., rJ. J.\'. RJ, and R.110, , were extracted from additional steadystate and transient measurements as follows.
The transient turnoff characteristic, modeled by (2.18), was measured for an ONstate current 4, low enough to ensure that I.A(t) is exponential as described by the numerator of (2.18). This measurement gives 7rI(,ff) directly, subject of course to the validity of the model assumptions. (We have found that if the OFFstate voltage is high enough (> 200 V) to cause a significant transient variation of the quasineutral
80 F
VG 10V
60
C4J
E
40 Measured
4 2 Calculated
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VA (V)
Fig. 2.3 Measured and calculated steadyONstate current
(density)voltage characteristics for nchannel
VIGBT (T = 250 C). Model parameter values used are rf = 12 lis, Jv(, 1.1 x 1013 A/cm2, I?; = 0.08 11, and R10o,; = 0.04 Q; also, ')f = 5 x 1016 cm3, I1 = 10 /,m,  = 1 x 1014 cm3, TlV/ = 45 /,m,
and K. = 0.5.
base width (11r,j), then rH(,ff) can be overestimated.) Using (2.19) then, TH and If were evaluated by fitting the model prediction for the turnoff time T, and its dependence on 10. T, is the time required for 14(t) to drop to 0.l1 f; it was measured by pulsing the gate ON (10 V) and OFF (0 V), while the anode was biased through a resistive load. The modelpredicted T, vs. 11 was derived by first modeling the steady state, and using the results to characterize the transient turnoff as described in Section 2.2.
Plotted in Fig. 2.4 are the measured T, vs. 1t data along with the model characteristic (which corresponds to rH  12 Its and JA( 2 1.1 X 1013 A/cm2 at T = 25ï¿½C). The theoreticalexperimental fits illustrated in Figs. 2.3 and 2.4 also involve iterative evaluation of R., (cz 0.08 Q) and R110, (f 0.04 Q), the dependence of which on gate voltage enables separation from the series resistance. Since the T,(4)) characteristic is not strongly dependent on the small resistances R , and R.1, their extraction is made mainly from the I(IV,) characteristic. In all cases the model predictions matched the measurements well, without much empiricism involved. The theoreticalexperimental agreement gives credence to our model and demonstrates the utility of the parameterextraction techniques.
We now show how the model can be used to give physical insight and thereby aid the optimal design of the buffer
15 , e 13
13/Measured
Calculated
119
7 VG 10V
5
0 1 2 3 4 5 10 (A)
Fig. 2.4 Measured and calculated turnoff time vs. ONstate
current (T = 250 C) . The model parameter values
used are the same as those given in Fig. 2.3.
05  ,N Af = 1.9 X 1011 cm3 41
3
To (gs)
4 5 6 7 8910
Fig. 2.5 Measured forwardvoltage drop vs. turnoff time
taken from pchannel VIGBTs having different carrier lifetimes in the epi base region. The ONstate current was held constant as indicated for a pellet area of 120 x 120 mil2; the OFFstate voltage V3 = 400 V. The data points are connected by straight lines to emphasize the parametric
dependences.
>3
2 1
i I = I
I= 10A
9x 1017cm" 3 71
4xI017 cm'3'"Z.
I I 1 I I i i
layer. Plotted in Fig. 2.5 are additional data taken from pchannel VIGBTs fabricated at RCA/DSRC. The measured ONstate voltage, V,., versus T, for three bufferlayer doping densities, A1, was obtained from devices in which the carrier lifetime was varied by heavymetal diffusion. The ONstate current 10 was held constant. The data show that predominantly for a given T. V, increases as AN1f is increased, thus suggesting that Nf be low for optimal design. This suggestion is contrary to that emanating from corresponding (nchannel VIGBT) data (Nak85], which show that for a given T,. '1 decreases as NDf is increased, and from theoretical predictions [Kuo86]. This apparent contradiction can be explained with reference to our analysis. We note that for a given TH, an increase in Nf will tend to decrease the carrier injection level in the nbase region, which concomitantly tends to decrease T,, but to increase VA because of the higher 1I, in (2.9). If the decreasedT, tendency is predominant, and the increase in VI is less significant because, for example, 1Ii is negligibly small, then the implication regarding optimal N'Df [Nak85, Kuo86] is obtained. Otherwise, the opposite implication in Fig. 2.5 is obtained. Based on our studies, we deduce that this opposite effect is evident only when the injection level in the nbase region is predominantly low, thus yielding a very high I" I,, as in the ordinary power MOSFET. In fact the VIGBT with a very high NDf (and/or wide IT) behaves as a power MOSFET with
24
no benefit from conductivity modulation. Thus optimizing the bufferlayer design is more involved than previously stated [Nak85, Kuo86, Hef86] and must involve a more comprehensive study of the effects of all regions of the VIGBT.
Such a (theoretical) study is illustrated in Figs. 2.6, 2.7, and 2.8 where we plot calculated VA T, curves for different values of key device parameters, NDf, lTV, and *JNO. The curves were derived by varying rH between 0.1 and 100 lis while holding 10 and VB constant. Note in each figure that points corresponding to a specific 7H define a locus on the V1T, coordinate system having a negative slope; viz., shortening T0 via the parametric changes indicated necessarily increases I. In Fig. 2.6, the insight discussed above regarding the influence of NDf is illustrated. The convergence of the differentNDf curves varies as the key device parameters, especially JAo, are varied. Additional calculations show that increasing JVo moves the point of convergence to the left, thereby enhancing the tendency shown in Nakagawa and Ohashi [Nak85] and predicted in Kuo and Hu [Kuo86]. Decreasing
*Ivo moves the point to the right, enhancing the tendency reflected in Fig. 2.5. The convergence of the curves in Fig. 2.6, although predicted by our analysis based on highlevel injection in the nbase region, nevertheless implies the onset of low injection which, as mentioned above, intensifies the opposite V T, vs. VDf tendency shown in Fig. 2.5.
ï¿½ 100 A/cm2
VB =100 V
: 2ND =2 x1017 cm3
1 x 10118 c m 3
6 X 1017cm3
1 I I t ii II]i I I 111111 t
0.1 1.0 10 To (gs)
Fig. 2.6 Simulated forwardvoltage drop vs. turnoff time
for two values of N/)f, with 11f = 10 /,Im, J v = 1
x 1013 A/cm2, and ITVB = 45 /,m.
L= 100 A/CM2
A
VB 100V
O=2 Ix1013 A/cm2
5 x 1013A/cm2
1 1 1 1 1 ii I It l! I ! ! II11
0.1 1.0 10
To (As)
Fig. 2.7 Simulated forwardvoltage drop vs. turnoff time
for two values of .Jvn, with XDf = 2 x 10 7 cm3,
117 = 10 pm, and T11 = 45 pm.
10gm 10 =100 A/cm2 VB 100 V
:
Wf = 15gm BUFFER LAYER)
1 1 I I lI I I I I I I I I I I
0.1 1.0 10 To(p'S)
Fig. 2.8 Simulated forwardvoltage drop vs. turnoff time
for two values of TJf, with rDJ = 2 x 1017 cm3, and for no buffer layer, all with .'Vo = 5 X 1013
A/cm2, and IVB = 45 /,m.
28
The significance of JN0 is further emphasized in Fig. 2.7. For a specified buffer layer, the calculated data plotted show that increasing JN1 decreases T but also increases I', for the same 4). This is similar to the effect of the buffer layer: the BJT 3 is lowered, thereby reducing the quasiFermi level separation (forward bias) at the emitterbase junction and the injection level in the nbase region.
Finally in Fig. 2.8, calculated dependences on 117 are shown. Increasing T1, analogous to increasing J.\, decreases T, but increases V,. For comparison, the case 117 = 0 (no buffer layer) is also shown, indicating that adding the buffer produces the same tendencies as increasing JA.. However, as can be inferred from our discussion, the effects of the buffer layer on the VIGBT performance cannot be ascertained without considering the significance of all key device parameters. We note for example that the benefit of the buffer layer is enhanced by a reduction of 11B because 1, in (2.9) tends to become less significant, and hence the T 14 tradeoff discussed is less critical.
2.4 Summary
A simplified physical model for the VIGBT has been used to interpret both steadyONstate and transient turnoff measurements reflecting significant effects of the buffer layer. The theoreticalexperimental study has (i) provided good physical insight, (ii) implied optimal bufferlayer
29
design criteria, (iii) described model parameterextraction techniques, and (iv) indicated shortcomings in corresponding results of previous work due to a lack of comprehensiveness in the analyses.
CHAPTER 3
STATIC AND DYNAMIC LATCHUP IN THE LIGBT
3.1 Introduction
This chapter presents static and dynamic latchup models for the lateral IGBT (LIGBT) [Darw84, Pat86]. In Chapter 2, an analytic bufferlayer model for the VIGBT, which is similar in structure to the LIGBT except the anode layout, was developed and experimentally verified. The physical insight gained from the modeling of the VIGBT, and from PISCES simulations discussed here is used to develop the latchup models for the LIGBT.
The LIGBT is a highvoltage powerswitching device that can be used in highvoltage integrated circuits (HVICs). However the LIGBT, and VIGBT as well can be latched into an undesirable state in which gate control is lost. This state, which can be triggered either statically (by sufficiently high quasistatic current) or dynamically (by sufficiently high displacement, or transient charging current), results from the latchup [Rob86] of the parasitic pnpn structure in the LIGBT. The LIGBT must therefore be designed to avoid latchup in the operation of the HVIC. Computeraided design that includes latchup modeling for both device and circuit simulation is required.
Very little previous work on the simulation of latchup (especially dynamic latchup, which is the predominant problem in HVICs) in LIGBTs has been done [Pat86, Darw87, Chow87]. In this chapter, we describe an insightful study of the static and dynamic latchup phenomena in the LIGBT, which culminates in the development of a physical model for SPICE simulation of HVICs. The study is based on extensive simulations of latchup in the LIGBT using the twodimensional device simulator PISCES [Pin84]. The simulations reveal the internal mechanisms underlying static and dynamic latchup for a variety of excitations, and they show that the lateral pnpn structure becomes an effective pin diode after latchup because of the excessive conductivity modulation near the surface. In fact, the conductivity modulation is observed to be the governing mechanism in the latching and in the latched state (in accord with analyses of latchup in CMOS ICs [Sei87, Cou88]), and hence must be properly accounted for in the simulations. Also noteworthy is the discovered significance of nonquasistatic bipolar behavior (Foss86] in the dynamic latchup, as well as the possibility of different controlling charging currents, depending on the transient terminal conditions. Dynamic latchup can occur for very fast gatevoltage switching and/or for very high blocking voltages.
The SPICE model for the LIGBT, including latchup, is developed by extending the chargebased VIGBT model in Chapter
2, which comprises onedimensional physical representations of the ambipolar carrier transport in different regions of the device. The model is implemented in SPICE via userdefined controlled sources (FORTRAN subroutines) and is verified by measurements of test devices fabricated at AT&T Bell Laboratories, as well as by the PISCES simulations.
3.2 Numerical Simulations
To gain the physical insight needed to develop the latchup model, PISCES [Pin84] was used to study both static and dynamic latchup in the representative LIGBT structure shown in Fig. 3.1. PISCES is a twodimensional device simulator, for dc or transient terminal conditions, that utilizes finiteelement approximations and a Gummel/Newton numerical method to solve the discretized semiconductor equations defining the carrier transport (Cou88], including contemporary models for the semiconductor parameters. Dopingdensity profiles and structural dimensions corresponding to our test devices from AT&T Bell Laboratories (see Section 3.3) were assumed. Although these LIGBTs are dielectrically isolated [Luc88], the insight afforded by the simulations and modeling we describe is helpful in analyzing the junctionisolated resurf device structure, which includes an additional vertical constituent bipolar transistor and which could include a shorted anode [Darw87, Chow87, Fos88]. As indicated in Fig. 3.1, in the steady onstate, the constituent DMOST gate is biased
V,> VT
\_0
Fig. 3.1 LIGBT test structure with external circuitry and
gate drive for a turnoff transient.
34
above the threshold voltage and the anode is biased above the source/cathode (ground) through a load resistor. In the transient turnoff, the gate voltage drops, in a finite fall time, to zero.
3.2.1 Static LatchUp
The static latchup is demonstrated in Fig. 3.2 where a PISCESsimulated dc currentvoltage characteristic of the LIGBT is shown. To enable simulations of the entire (multivalued current) characteristic, in reasonable computation time [Cou88], the applied anode voltage was increased incrementally to derive the sublatch current, but after latchup (onset at point where (1/d = 0), the anode was driven with an increasing current and the voltage was derived from the simulation. Above the onset of static latchup, a negativeresistance region reflects the regenerative latching mechanism involving the lateral pnp transistor (the anode is the emitter) and the parasitic npn transistor at the cathode (the DMOST source is the emitter); see Fig. 3.1.
The regeneration occurs because holes injected from the forwardbiased anode are collected and flow laterally though the npn base pinch resistor R,1B, producing a forward bias (predominantly under the DMOST gate) on the npn emitterbase junction. Electrons thereby injected (predominantly laterally) from the source drive the npn base harder, producing additional forward bias on the anode junction and
50 x 106
40
N 20
10 I
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VA [V] IA VA (PISCES) Fig. 3.2 PISCESsimulated LIGBT currentvoltage characteristic showing static latchup. The gate bias is
10 V.
36
additional hole injection. The process thus enhances the conductivity modulation of the pnp base region, including the adjacent spacecharge region at the npn basecollector junction. This junction is ultimately neutralized as TA increases by the holeelectron plasma, and the steady latched state is characterized by the effective pin diode that materializes [Sei87, Cou88].
For a point in Fig. 3.2 below latchup, Fig. 3.3 shows the simulated current flowlines within the device. Normal LIGBT operation is evident; the channel current of the DMOST supplies electrons to the base of the lateral pnp transistor which support, through recombination, the hole transport current. The LIGBT (anode) current equals the channel current plus the pnp collector current. Note that most of the hole current flows laterally through R11 in the npn base region, but the induced ohmic drop is not sufficient to significantly forwardbias the source junction; the electron current is confined predominantly to the DMOST channel.
The simulated current flowlines in Fig. 3.4 reflect operation above the onset of latchup in Fig. 3.2. In contrast to the condition pictured in Fig. 3.3, we see in Fig. 3.4 significant injection of electrons from the n+source (emitter) into the npn base and collector (pnp base). The hole current flowing through RpB produces a voltage drop which in this case is high enough to activate the npn transistor,
Fig. 3.3
... .............. ... it ................ ... ........a
IN,
PISCESsimulated current flowlines in the LIGBT in Fig. 3.1 biased below latchup. The anode current is 1.9 x 105 A//im and the gate voltage is 10 V. The flowlines are plotted such that equal currents
(Al) flow between any two adjacent flowlines. For the whole device (a), Al = 0.2 x 109 A/pm; In the vicinity of the DMOST (b), _I = 0.1 x 105 A/pm.
\ \'"~< _____ 77 /(a)
___ _/ _
p Bodyn1s./. (b )
Fig. 3.4 PISCESsimulated current flowlines in the LIGBT in
Fig. 3.1 biased above latchup. The anode current is 3.4 x 105 A/tm and the gate voltage is 10 V. For the whole device (a), \I = 0.2 x 105 A/,im; In the vicinity of the DMOST (b), I = 0.1 x 105 A/lm.
39
and initiate the regenerative process in the pnpn structure. The predominant electron injection occurs laterally from the source under the DMOST gate where the forward bias is highest. For sufficiently high current, the basecollector junction of the npn and pnp transistors is highly conductivitymodulated (as in a quasisaturated transistor [Sze8l]) by holes and electrons just below the surface, and an effective pin diode exists between the anode and the cathode/source of the LIGBT. The currentvoltage characteristic of this pin diode defines the negative resistance in Fig. 3.2, as well as the conductance of the latched device [Sei87, Cou88]. In this condition, removal of the gate voltage does not necessarily result in the turnoff of the LIGBT.
As a leadin to the next subsection on dynamic latchup, we note here that the simulated steadystate 14(V1) characteristic in Fig. 3.2 is not the characteristic which would be observed in common currentvoltage measurements. In a curvetracer measurement, the voltage is swept up and down, and hence a multivalued current characteristic like that in Fig. 3.2 would show an apparent hysteresis. This hysteresis could be eliminated by sweeping the current instead of the voltage, but the dynamic nature of these measurements also can cause a hysteresis. In fact, the hysteresis observed in curvetracer measurements of latchup can be attributed, in part, to the dynamic nature of the current. PISCES and SPICE (using the LIGBT model presented in Section 3.3) simulations of a
40
sweepingcurrent measurement show the hysteresis, with the latchup occurring at a higher current when 1.4 is increasing with time than when it is decreasing with time. The actual steadystate characteristic lies within the hysteresis loop. These results are consistent with HP4145 currentdriven measurements we have made and can be understood based on the insight gained in the next subsection. Another reason for the discrepancy between a (twodimensionally) simulated steadystate latching characteristic and a measurement is the (threedimensional) inhomogeneities in the actual device that can cause nonuniform latching and hence also a hysteresis.
3.2.2 Dynamic LatchUp
With regard to actual HVIC operation, dynamic latchup of the LIGBT is the real problem. When the gate voltage is dropped to turn off the LIGBT from an unlatched onstate, the device can latchup and continue to conduct. There are two distinct conditions which induce dynamic latchup. One is when the gate voltage drops very fast and induces excessive displacement current through the gate oxide that drives pj. The other one is when the (offstate) blocking voltage is quite high and induces excessive charging currents within the LIGBT during the switching transient that drive J?,,B. Of course the probability of dynamic latchup increases as
41
the steady onstate condition approaches the static latchup onset (depicted in Fig. 3.2).
For a resistive load as shown in Fig. 3.1, Fig. 3.5 shows PISCESsimulated transient turnoff characteristics, I(t), for a short gatevoltage fall time (tf = 0.5 ns) and for two different initial steady onstate currents (b/IL = 0.25, 0.86, where I, is the static latchup onset current). The offstate voltage used is low (' = 10 V). For the lower initial current I(, the turnoff is normal, but for the higher If, a delay is seen Fig. 3.5. The device current flowlines for the latter case at three different times, shown in Fig. 3.6, reveal the nature of the transient delay. The induced gateoxide displacement current (predominantly electrons flowing off the gatedrain overlap capacitance into the pnp base) tends to drive the regenerative process in the pnpn structure. Although initially (t = 0.44 ns) the gate depletion (dis)charging current diverts holes away from R,, later (t = 2.55 ns), long after the gate voltage has been removed, the transient voltage drop across RpB is sufficient to activate the npn transistor, and significant conductivity modulation prevails in the device. The reason for this delayed activation is that the discharging of the depletion capacitance occurs relatively fast, and precedes a transient (electron current) drive on the pnp base from the discharging overlap capacitance, which increases the hole current through
1.1
1.0 0.9
0.8 10  0.881L
0.7
S0.6 o.25IL
0.5
0.4 0.3
0.2 0.1
0 .0 "' I t ..
0 5 10 15 20 25 30 35 40 45 50 x 109 t [sec]
IA/I0  t (PISCES)
Fig. 3.5
PISCESsimulated transient turnoff characteristics for a short gatevoltage fall time of 0.5 ns and for two different initial onstate currents, '0/IL where IL = 2.2 x 105 A/im is the static latchup onset current.
Fig. 3.6
Current flowlines (Al = 0.1 x 105 A/lm) in the vicinity of the DMOST at three different times in the transient turnoff simulation in Fig. 3.5 for II = 0.86.
. . a. . . f. . . . I . . . . . ,I , , , , ,1 1 , \ . , ,\ , :
44
R,1. However, in this simulation, this transient (quasidynamic) latchup is not sustained because of the low VB and the simple circuit configuration which are insufficient to force a steady latched condition. The LIGBT ultimately turns off after the delay caused by temporary activation of the effective pin diode. In real HVICs, this quasidynamic latchup can be converted to an actual dynamic latchup by stray capacitance and/or inductance and by higher 1.
PISCESsimulated transient turnoff characteristics for higher ly (50 V, 400 V) and longer tj (50 ns) are shown in Fig. 3.7. In the case of the higher VB, dynamic latchup is evident, even though the gate displacement current is insignificant. As indicated by the current flowlines in Fig. 3.8, the latchup in this case results because of substantial charging currents induced in the LIGBT which flow through R,,11. Note in Fig. 3.8 that the lateral current flowing through RI increases with time. This is explained as follows. During the first phase of the turnoff transient, 14(t) drops rapidly due to the removal of the DMOST channel current (Fos86]. Then, in the resistiveload circuit, the anode voltage 1'1 increases accordingly, which causes three distinct internal charging currents to flow, all of which are manifested by holes flowing through R1,B which tend to induce the latchup. One is the displacement current that charges the basecollector junction as its reverse bias increases. This current is defined by the transient depletion capacitance of the junction [Fos86I.
1.1
1.0
0.9 VB 400 V
0.8 0.7
S0.6
0.5
0.4 0.3
0.2 V
VB =50 V
0.1 ....................... .................
0 .0 . I I f I I
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 x 106
t [sec] IA/I0  t (PISCES) Fig. 3.7 PISCESsimulated transient turnoff characteristics for a relatively long gatevoltage fall time of 50 ns and for two different blocking voltages
I'B.
t=o [I
A 1
Fig. 3.8 Current flowlines (LI = 0.1 x 10 5 A/,m) in the
vicinity of the DMOST at two different times in the transient turnoff simulation in Fig. 3.7 for
I = 400 V.
47
Another current is the transient base transport (collector) current of the pnp transistor, which increases because of the shrinking quasineutral base width [Fos86]. The third current, which has previously not been recognized as being significant, is the component of the quasineutral base discharging current that flows out the collector. Conventional quasistatic transistor models [Sze8l] do not account for this charge partitioning (Foss86], which actually reflects a nonquasistatic behavior, and simply associate all the base charging current with the emitter. For fast transients, like latchup in the LIGBT, the base charge partitioning must be used to account for transient charge redistribution [Foss86]. Our SPICE simulations (discussed in the next section) reveal that the nonquasistatic collector component of the base discharging current is critical in simulating dynamic latchup in the LIGBT. In fact, this component is typically (for our devices) the largest discharging current flowing during the turnoff transient; it controls the dynamic latchup.
3.3 SPICE Model
Using the physical insight gained from the PISCES simulations described in Section 3.2, we extend the physical SPICE model for the LIGBT [Fos88] to properly account for latchup. The network representation of the new SPICE model is shown in Fig. 3.9, superimposed on the LIGBT structure. All the elements in the model, the underlying physics of which is
Ve > VT
\0
Fig. 3.9 Network representation of the SPICE LIGBT model
superimposed on the device structure.
49
described below or in Fossum et al. [Fos88], are implemented in SPICE via userdefined controlled sources (UDCSs) [Vee86], which are FORTRAN subroutines in SLICE [Har84], an enhanced version of SPICE2. The new model in SPICE provides a mixedmode device/circuit simulation capability, which in fact is essential for realistic simulations of latchup in HVICs and which is prohibitive in PISCES because of limitations on the allowed terminal drive conditions and because of the prodigious computation times required for the device simulation. (Computation times are compared in Section 3.4.)
The new model in Fig. 3.9 includes basic LIGBT elements defined in Fossum et al. [Fos88]. They were derived by regionally partitioning the LIGBT into onedimensional widebase bipolar transistors coupled to the DMOST. The ambipolar transport problem for high injection in the transistor was solved analytically, but not in closed form, to define a chargebased module. The system of module equations is solved by the circuit simulator during the nodal analysis to characterize all elemental currents, including the charging currents (IQ/It, based on the quasistatic approximation. The model extension presented here includes (a) a module for the parasitic npn transistor, including the emitter as well as the base resistances, (b) nonquasistatic charge partitioning in one pnp transistor module (the second pnp module [Fos88] is not crucial here), and (c) representation of the effective
50
pin diode that forms during latchup. These extensions, needed for the proper simulation of latchup, are now described.
The current sources 4',, and IB, model the parasitic npn transistor at the cathode which, in latchup, is activated by the voltage drop across the base pinch resistor RIB. Following conventional bipolar modeling [Sze8l], we describe, to first order, the collector current as ,= I [ /(3.1) and the base current as
18n = I IC,/ ,, (3.2) where I, (which is proportional to RpB) and ;1,, are constants. In (3.1), the baseemitter voltage VBE, is given by the drop across RpB minus the lateral voltage drop across R,,E in the emitter (n+source), caused by the emitter current (I,, plus IB,) plus the DMOST channel current (see Fig. 3.9). Note that increasing RE, which could be done by lengthening the source and/or by lowering the doping density, tends to improve latching immunity but also results in higher onresistance for the LIGBT (see Section 3.5).
As indicated in Fig. 3.9, the hole charge stored in the quasineutral base of the pnp transistor is partitioned into two components, QBE and QBC, associated with the emitter and collector. The partitioning, which is physically representative of bipolar transistors (Foss86], is defined by integrating the carrier continuity equations in the base (see
51
the Appendix A) to give the best approximation for the nonquasistatic behavior associated with the distributed charge
dynamics. As described in the Appendix A for high injection and significant base recombination, QBE (2/3) Qu (3.3)
and
QBC (1/3)Qu (3.4) where QB is the total quasistatic hole charge stored in the quasineutral base region [Fos88]. Interestingly the charge partitioning in (3.3) and (3.4) is approximately the same as that derived for the case of low injection in a uniformly doped base with negligible recombination [Foss86J. We stress that the conventional quasistatic model [Sze8l], in which QBE = QB and QB( = 0, will give significantly erroneous simulations of latchup in the LIGBT.
In general (see the Appendix A and Fossum et al. [Fos88]), QBE and QBC depend on both the emitterbase and basecollector junction voltages. This means, for example in the predominant forwardactive mode of the pnp transistor, that the charging current dQBC/dt cannot be represented by a simple capacitor [Fos88]; in fact, the component (OQB./O7.j),V..B1/df reflects a transcapacitance, and the network in Fig. 3.9 inherently accounts, to first order, for any nonreciprocity and nonquasistatic behavior in the device.
52
In a transient turnoff simulation of the LIGBT, dQBc/dis important because it reflects the finite carrier transit time in the quasineutral base [Foss86]. Thus, as we will illustrate in Section 3.4, it tends to reduce the fast initial drop in LIGBT current by the removal of the DMOST channel, and it places an additional transient drive on RBg which renders the LIGBT more vulnerable to dynamic latchup.
When the LIGBT latches, the effective pin diode between the anode and the cathode materializes because of the conductivity modulation of the basecollector junction of the pnp and npn transistors. This pin diode, which actually defines the latching characteristics [Sei87], is simulated in our model by a semiempirical nonlinear resistor ?,)i,, as indicated in Fig. 3.9. The resistor, which effectively shunts the basecollector junction when the npn current is sufficiently high, is characterized in accord with quasisaturation modeling of the npn transistor [Sze8l]. If we assume that the electrons drift through the junction spacecharge region with saturated drift velocity i, then the electron (and hole) density in the region is approximately I,,/qA,'s where A represents an area of the junction (predominantly under the DMOST gate) that is modulated. Consequently we assume that the modulated region is a shunting resistance (for hole flow) given by
R,,, lI ,./fp,(,, (3.5)
53
where Ilqrr represents the width of the highfield spacecharge region, which is assumed to be a constant extrapolated crudely from the equilibrium depletionregion width. The important dependence in (3.5) is that on I.,. Below latchup, the npn transistor is not activated significantly, and the low I(,, defines a large R,,i, that is inconsequential in the model network. As IC,, increases, R,,,, decreases, simulating the effective removal of the junction potential barrier by the holeelectron plasma. This semiempirical model for the effective pin diode is simple, but as we show in the next section it portrays LIGBT latchup adequately.
3.4 Model Verification
LIGBT test structures with two different pnp base widths (111 = 78 /,m, 128 itm) were fabricated using the dielectricisolation bipolarCMOSDMOS (BCDMOS) technology [Luc88] at AT&T Bell Laboratories. Each device is contained in a separate silicon tub dielectrically isolated from the substrate as well as other components, and all terminals are accessible from the top surface.
Measured and SPICEsimulated (quasi) static latchup currentvoltage characteristics are shown in Fig. 3.10. The measured data in Fig. 3.10(a), taken with an HP4145 parameter analyzer using a currentsource driver, show an abrupt transition from normal LIGBT operation to the latched pindiode mode, in which the gate control is lost (the
.4000/div
0.030
0.024
:E0.018
0.012 0.008 0.000
0.0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.8 4.0
VA [V]
Fig. 3.10 LIGBT currentvoltage characteristics, showing
static latchup, for two different lateral base
widths TTjj. (a) Measured; (b) SPICEsimulated.
(mA)
Acia.
3.000Z
/div
rz r2f 2M
.0000
WB 78 UM 128 UM
( V)
4. 000
310.
55
device cannot be turned off by removing the gate voltage). The simulation results in Fig. 3.10(b) show the latchup, not so abruptly but representatively. No rigorous model parameter extraction was done; representative values [Fos88] were assumed. Note that the latchup onset current decreases with decreasing IVY, in both Figs. 3.10(a) and 3.10(b), and that the latchedmode conductance is higher for the narrower ITB. These results are due to the dependence of the pnp current gain 3,, on T113, which is implicitly modeled by the system of pnp module equations [Fos88J underlying ., (,, and 1,i in Fig. 3.9. Decreasing TVB increases .,, (from about 0.6 to 1.0 in this case), which means, for a specific anode current IA, a larger fraction of it flows through R,,1B, thereby promoting the latchup at lower IA. The good correlation between the measurements and simulations in Fig. 3.10 provides sufficient support to conclude that the SPICE model, with the semiempirical Rl,,,, in (3.5), does indeed give reasonable simulations of static latchup.
A dynamic latchup simulation, for the case of very high blocking voltage (Vy = 400 V) as discussed in Section 3.2, is shown in Fig. 3.11. For contrast, the simulation of the turnoff transient of the same device but with a lower VB (= 50 V) is also shown; this turnoff does not result in latching. In the case of the higher VB, the LIGBT latches because of higher charging currents flowing through R,B.
1.1
1.0
0.9 "".. VB 400 V
0.8
0.7 0.4
S0.5
0.4 ""
0.3 "...... v  o v
0.2 "
0.1 .
0.0 ,,,,
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 x 106
t [sec] IA/I0  t (SLICE) Fig. 3.11 SPICEsimulated transient turnoff characteristics for a gatevoltage fall time of 50 ns and
for two different blocking voltages 1l3.
The significance of the base charge partitioning (nonquasistatic discharging) in the pnp transistor is demonstrated in Fig. 3.12 where we plot the excess (above the steady onstate bias) transient baseemitter voltage of the npn transistor taken from the SPICE simulation of the 1 = 400 V turnoff. For comparison, the component of this excess voltage due to the current ulQB,/,dI flowing through 11?,B is also plotted in the figure. This component in fact exceeds transient voltages due to the other two discharging currents. Other simulations reveal that the maximum controllable (onstate) current for the LIGBT is overestimated when QB3( is neglected as in conventional quasistatic transistor models. Comparison of the transient simulations in Fig. 3.11 with the corresponding PISCES simulations in Fig. 3.7, which show qualitative agreement, gives support for the SPICE model in dynamic latchup simulation. (No attempt was made to tune the SPICE model parameters based on the PISCES simulations.) We note further that the SPICE simulations required only about 1/600 of the computation time of the PISCES simulations.
3.5 Summary
An insightful study of static and dynamic latchup in the LIGBT, based on extensive PISCES simulations, has revealed the important underlying physical mechanisms and has facilitated the development of a physical SPICE LIGBT model for HVIC simulation. The SPICE model was supported by measurements
0.20 0.18 0.16
0.14
,0.12 40.10
0.08
0.06
0.04 0.02
0.00 ......
0 10 20 30 40 50 60 70 80 90 100 X 10t [sec] A VBEN  t (SLICE) Fig. 3.12 The excess transient baseemitter voltage (solid
curve) of the npn transistor in the V13 = 400 V SPICE simulation in Fig. 3.11, and the component of this excess voltage (dotted curve) due to the
partitioned discharging current (QBCo/,t.
59
of test devices as well as by the PISCES simulations. The study showed that the latchup is controlled by an effective pin diode that materializes between the anode and the cathode/source due to excessive conductivity modulation by the holeelectron plasma near the surface of the device. In the dynamic case, the regenerative process in the lateral pnpn structure can be triggered by either displacement current in the DMOST gatedrain overlap capacitance (for very fast gatevoltage switching) and/or by internal charging currents in the constituent pnp bipolar transistor (for very high blocking voltages). Both PISCES and SPICE simulations of dynamic latchup in the LIGBT demonstrated, for the first time, the significance of nonquasistatic bipolar behavior (pnp base charge partitioning) in defining the maximum controllable onstate current.
The chargebased SPICE model is useful in LIGBT as well as in HVIC design. Since the model parameters are predominantly physical, structural designs to maximize latchup immunity can be derived and checked. The mechanisms by which a fast falling gate voltage and/or a high blocking voltage result in dynamic latching, subject to the proximity to static latchup in the steady onstate, can be simulated in such designs. Indeed dynamic latching under all possible circuit transients can be simulated representatively and with computational efficiency. Such simulations can lead to optimal designs, for a given technology, which could involve control of not only R,,B, which
60
previous studies [Rob86] emphasize, but also of R,,E. I, ,. II'>, and even the DMOST properties [Cho88]. For example, we have done simulations, exemplified in Fig. 3.13, which show that latchup can be avoided for normal operating conditions by increasing the DMOST source resistance R,,E to values which, albeit increase the onstate resistance of the LIGBT, are not infeasible. In such a design, the voltage drop across R,,E is exploited to counteract that across J?,qB, and thereby reduce the bias on the parasitic npn transistor (see Fig. 3.9).
0.030
0.024
.Z ".0 0 1 8
RnE 0.2 OHM 10 OHMS
0.012 0.006 0.000
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.8 4.0
VA [VI IA  VA (SLICE) Fig. 3.13 SPICEsimulated LIGBT currentvoltage characteristics showing the effect of varying the DMOST
source resistance R,,E.
CHAPTER 4
PHYSICAL VDMOST MODELING FOR HIGHVOLTAGE IC CAD
4.1 Introduction
This chapter presents a chargebased model for the vertical DMOST (VDMOST) [Huc84]. As in Chapter 3, the twodimensional device simulator PISCES is used to gain the physical insight of the device operation and to aid the model development. The device is regionally partitioned into several onedimensional components and the carriertransport equations are solved in each region. The model is implemented in SPICE using FORTRAN subroutines.
DMOSTs can now be merged with lowpower control circuitry to produce highvoltage integrated circuits (HVICs) Effective CAD of such HVICs, and of those containing IGBTs described in Chapters 2 and 3, requires a physical DMOST model implemented in a circuit simulator such as SPICE. However the equivalentcircuit MOST models in SPICE today are too empirical and do not properly account for important unique features of the highvoltage DMOST such as quasisaturation, spacechargelimited (SCL) current, channel dopingdensity gradient, and local heating. In this chapter, we present a physical modeling methodology for DMOSTs intended for HVIC CAD. A seminumerical model, implemented in SPICE, is developed for vertical DMOSTs.
63
Some of the modeling is applicable as well to lateral DMOSTs (LDMOSTs), which are discussed in the next chapter.
In the methodology, the DMOST is regionally partitioned into two main components: the doublediffused MOS transistor (viz., the channel) and the lightly doped drain (drift region). The constituent components are represented by chargebased models in which the current and charges are implicitly related to internal node voltages. The characteristics of the composite DMOST model are derived seminumerically within the nodal analysis framework of SPICE. The model is supported by twodimensional numerical simulations done with PISCES and by measurements of test VDMOSTs. The PISCES simulations also aid the model development by giving physical insight regarding the unique field distribution in the channel, the excess carrier distribution in the drift region, and depletionregion modulation due to free carriers.
The composite chargebased VDMOST model is not a simple equivalent circuit, but is a physical, seminumerical representation (in SPICE) of the underlying carriertransport equations. The critical elements are defined by an implicit set of nonlinear equations that require numerical solution, which is done using a NewtonRaphson iterative method within the model routine. In addition to the constituent channel and driftregion models, the (nchannel) VDMOST model accounts for the parasitic npn BJT, which is especially important
with regard to the transient charge dynamics of the VDMOST. Further, localheating effects are included in the electron mobility model, which enables simulation of the negative resistance in the DMOST saturationregion characteristics. The intrinsic charge dynamics are accounted for directly via total time derivatives of stored charges, which are characterized seminumerically by the regional analyses. SPICE simulations of VDMOSTs and HVICs are presented to demonstrate the model.
4.2 Model
The VDMOST (shown in Fig. 4.1) model is derived from regional analyses of carrier transport in the channel and drift regions. The parasitic BJT is accounted for in the composite model by physically based current elements, which can be activated by the lateral voltage drop across the pbody resistance.
4.2.1 Channel Region
The doublediffused nMOS transistor has a nonuniformly doped [NA(r)] channel region defined by the compensation between the pbody and nsource lateral diffusions. N1(.r) has a maximum (Nw) near the source and decreases sharply toward the drain. Consequently, as quantified by PISCES simulations for TD, > 0, the inversion charge is minimum at the source, and hence the longitudinal electric field is maximum there (1h N EQ,,). Fig. 4.2 shows PISCESsimulated equipotential
65
s G ï¿½P f L i
Di C
Fig. 4.1 VDMOST structure. The partitioning of the drift
region is shown and geometrical parameters are defined. The common deep p+body region, which does not influence our regional analyses, is not
shown.
Channel
x=L Drift region
Fig. 4.2 PISCESsimulated equipotential contours (Al' = 0.1
V) in the vicinity of the VDMOST (Luc88] channel (11) = 50 V, 1I;s = 10 V) . On the . and yaxes,
1 division = 0.1 pim.
Source
x=O
67
contours in the channel of a typical DMOST [Luc88]. The high density of lines near the source indicates the high electric field there. Our channel model is representative of these properties, and involves an appropriate gradualchannel approximation that yields the channel currentvoltage characteristic, with the threshold voltage defined by N, and the saturation controlled by driftvelocity saturation at the source (rather than at the drain as in the conventional MOST).
We approximate the nonuniform doping density along the channel as an exponential function [N=(r) and we use a piecewisecontinuous electron velocity model [Sod84]:
t m f f E r o i ' i al
1 + (II s .m,,,)f~/1~~ ft
1 i'.,t othirwi. (4.1) In (4.1) E., 114/d.r is the longitudinal electric field (magnitude), , (c 10' cn/.) is the saturated drift velocity, and /ilff = ji,,./[1+ï¿½9(1(;s1T)j where p,,o is the lowfield mobility, 0 is the fitting parameter which defines the transversefield dependence, and V1r= 'Bz + 2 toB1 + "4eVjj o j' (4.2)
is the threshold voltage. For strong inversion and negligible shortchannel effects, the quasistatic channel current is described by solving for E, in ,h =TT'Q,, (TT: is the device
width and Q,, is the channel charge density) and integrating it from source (,=0) to drain (r=L): lr,,,ss Q*,(L)  Q2, (0)] (4.3)
.,, = 2L [I + (.,,,fsst21,,,,jL) V h] (',,i + C,) i(
where 1,h is the channel voltage drop. The body depletion capacitance,
C1   [qfN 1 21 1,;,)kBI) (4.4) (11'  14k1(7B c
is assumed to be invariant along the channel to obtain a firstorder characterization of the depletion charge Q(, in terms of the voltage I(_ Ich./L) along the channel. In (4.3),
Q,, (L) = Cor [V s;  i  l{.# (1 + C'tlC',,.i) (4.5) and
Q,, (0) = C), (1;s,  VT) (4.6) Combining (4.3)(4.6), we get the channel currentvoltage characteristic in the triode region of operation:
Ic#,= TV1 f I:/,nIf f .
2L [1 + (i,,,ff/2,,,,L) 1,h]
12Co, ( .  l ) (C'o, + C',,1) r'h + 2qC'<,,, I, lt] (4.7) where C,, = vSVqKo40/4toj. The effect of the channel dopingdensity gradient is reflected in (4.7) by q. When q = 0, (4.7) simplifies to the conventional MOST expression. Note in (4.5) that Cd is typically negative, and much larger in magnitude than C'o.r. This unusual "depletion capacitance",
69
with il > 0, simulates the added channel conductance due to the smaller depletion charge away from the source.
As V'D," increases, .,, increases, and ultimately the electron velocity saturates near the source (at .'=O) as characterized
by (4.1). Then the saturation current is expressed as
'rbfs,,f) = tq',,,( ),, (ar = O)
= Tll'q ,,jC',, (V'..s.  1,r) .(4.8)
Unlike in the conventional MOST, the saturation current in (4.8) is independent of Cd, and cannot be modeled by a channel pinchoff approximation. Combining (4.8) with (4.7) yields
for a given I;s., above which .h =
4.2.2 Drift Region
Depending on the VDMOST structure, the (quasi) saturation characteristics can be controlled by the drift region instead
of the channel [Dar86] . Whereas the channel model is applicable to both vertical and lateral DMOSTs, as well as to the IGBT, different driftregion models are needed for the VDMOST and the LDMOST.
For the VDMOST in the normal mode, the PISCES simulations (Fig. 4.3) reveal that the drift region can be partitioned into three sections as shown in Figs 4.1 and 4.3 to simplify the analysis. The voltage drops in the sections, which are characterized seminumerically based on reasonable approximations for the carrier transport, are added to define
70
n+
pBody A
P . .
....
nDrift Region
B
000,
C
Fig. 4.3 PISCES simulated current flowlines (AI = 9.7x106
A/,'m) in the VDMOST [Luc88] (1)s = 50 V, I~s= 10 V), including the deep p+body region. The implied
driftregion partitioning is indicated. On the.r
and uraxes, 1 division = 1. 0 /im.
71
the composite quasitwodimensional model. In section A, excess electrons supplied through the channel (for IC% > V.) accumulate to support the negative gradient of the vertical electric field for VDS > 0 [Dar86]. These excess electrons, which accumulate even before the drift velocity saturates, produce SCL current. The underlying Poisson equation is complex, but can be solved analytically to give an implicit characterization of the voltage drop across the region. In section B, the electron current spreads laterally with an angle n ( 450) which can be assumed, in accord with the PISCES simulations, to be independent of the bias condition and the structural geometry [Huc84]. The boundary locations are defined by the depletion region of the pbody junction, which varies with the voltage drop across section A. The region is assumed to be quasineutral (11 ND). Section C is also neutral but has a constant crosssection. The (moving) boundary between sections B and C is also controlled by the depletionregion width of the pbody junction. Conventional MOST models, which do not account for SCL current, underestimate the drain current. Our simulations show that this underestimation can be quite significant at high ID,In each section, the drain current is generally expressed using a continuous version of (4.1) II ,,,.L1,
ID = 1 ï¿½ Eq/E( for E. > 0 (4.9)
72
where E(, = 'qi/,,d and /1,4 is the lowfield electron mobility. Combining (4.9) with Poisson's equation in one (vertical) dimension yields
d _' 1) I) N o (4.10)
In (4.9) and (4.10), A, is the crosssectional area at depth y and E,, = d1/y is the magnitude of the (vertical) electric field.
In section A, A,(= ITVL') is assumed to be constant. This assumption is based on the PISCES simulations, which reveal
a slight JFET effect in section A at low 17js but show it compensated at higher IDS due to predominant excess electrons [Dar86]. Equation (4.10) is solved analytically by extending the analysis in [Lam70] (which does not account for velocity saturation) to yield expressions for the position y and the voltage V at y in terms of E.,. The nonlinear !I(E.) and V(E.) expressions then implicitly give the section voltage drop,
(4.11)
which requires numerical solution; Ili is defined in Fig. 4.1 and 11Vi is the depletion region width of the bodydrift
junction. Note that the depletionregion width I;i depends on (1'ï¿½l h), the effective reverse bias on the pbody junction. EY is everywhere increasing with yi, so the velocity of the electrons increases along the vertical direction from the surface. However the excess electron density decreases with
increasing y because the gradient of E, becomes smaller. In our analysis, we neglected the diffusion component of current, which is confirmed to be negligible by both PISCES simulations and analytic solutions.
In sections B and C, n L Np). (The error resulting from the quasineutrality assumption is insignificant; results of accurate analytic solutions show little difference with those obtained using the approximation.) With Ay = TL'fLd+ï¿½yW,!T,)cotn] in section B and constant in section C, (4.9) is solved for E,, and the result is integrated over the thicknesses of sections B and C to obtain
I B + I 1 1 [TP: N D/in ,I (L, ï¿½ L,)  IflE c 1
+ 1 qjND11,,,cot, I #I#qNDpi,,jL,I  Ij/E ] + ~ ~ ~ (~ I _,  ' mi 4.2
+ I'(L,j + Lt,) qND11,,d  IDtE(, ) I  itLt,, ).( 12
The geometric parameters in (4.12) are defined in Fig. 4.1. Note that current continuity is effected in section B by the electron velocity decreasing with increasing crosssectional area. This occurs within the realm of the quasineutrality condition.
Now the total driftregion voltage drop of the VDMOST is I'd,.if, = VI + I _ + IC (4.13) For a given current Ip, which equals Lh from the channelregion analysis, (4.13) must be solved numerically because of the implicit nature of I1(fD) in (4.9)(4.11). The NewtonRaphson iterative method is used (in the model routine) to
solve these equations. Note that the voltage drop in the accumulation layer under the extended gate, which varies inversely with , has been neglected in (4.13).
4.2.3 Parasitic BJT
The parasitic npn BJT in the nchannel VDMOST, (upmode) activated in the PISCES simulations of Fig. 4.4, plays an important role in both normal and reversemode operations. In the normal mode, where a positive voltage is applied to the drain, the npn BJT near the channel (downmode: see Fig. 4.4) can be activated either statically (by impactionization current) or dynamically (by displacement or charging current) due to the pbody voltage drop. (In typical devices, this voltage drop is minimized by using a deep p+body diffusion to reduce the body resistance R1,B.) In the reverse mode, where a negative voltage is applied to the drain (which could happen during transient switching of the VDMOST in an HVIC), the BJT near the body contact (upmode: see Fig. 4.4) becomes an essential part of the VDMOST operation.The reverse recovery is very slow due to large stored charge in the drift region (where high injection prevails), and can sometimes drive the BJT to saturation, which would lengthen the recovery and could possibly lead to destructive breakdown [Bal87].
The npn BJT is modeled following conventional bipolar transistor analysis for the normal mode, and accounting for highlevel injection in the drift region for the reverse
Upmode BJT Downmode BJT
+ +
1 1 in4 1 1 1 T1 oF
I~f19. .., J.
I I I
Fig. 4.4 PISCESsimulated current flowlines (Al = 2.4x103
A/tm) in the reversemode operation of the VDMOST (Luc88], which show the activation of the upmode BJT (ID.5 = 2.0 V, ITh, = 0 V). The regions functioning as the emitter and collector of both the upmode and downmode BJTs are indicated. On
the . and yaxes, 1 division = 1.0 /,m.
76
mode. The base transport current is characterized in terms of the internal junction voltages:
'CT = C'(i1'P(VIBE,/I'T)  ~o'v2unIj)(4.14) where two different saturation currents are used because the BJT action takes place at different locations depending on the mode of operation. In the reverse mode of the VDMOST, the bodydrift region junction is forwardbiased ( > 0) predominantly near the body contact; and 'Ix'ii in (4.14) is relevant. In the normal mode, the sourcebody junction can be forwardbiased (If,, > 0), predominantly near the channel, due to the lateral voltage drop across the body resistance; and I(,(,o in (4.14) is relevant. We neglect the BJT base current for the latter case. For the reverse mode, it is defined predominantly by the hole transport in the drift region.
The transport mechanism in the drift region, where highlevel injection occurs in the reverse mode, is characterized by the ambipolar transport equation. For J) ?1, the solution [Fos88] is
p(Y)= ) (11,  !I)/L.1] + 1) Inh (Y  IUJA (4.15)
where LA .4r1 is the ambipolar diffusion length, D, is the ambipolar diffusivity, and 7H is the highinjection carrier lifetime. The boundary carrier densities are )(IT,) = (,?2/VD) rpI(,,/) and p1(TT)= )D(.r'p(IJ,,,+/II) where V1,.+ is the voltage drop across the lowhigh junction at the
I
77
drain, which is solved from the following boundary conditions. The hole and electron current expressions are combined to give two boundary conditions, neglecting recombination in the pbody and n+drain regions: I, (Y = lTJ ) 2 ICT and I, (! = IT 1) _ 0 [McD85]. For given V1BEn and lB, these boundary conditions are solved to give p(IV,) and p(IT) in (4.15). Then, the reversemode base current is IR = Qp/Tr[ (4.16) where Qp is the hole charge stored in the drift region: Qp =qll(i P L f 1) !1 (4.17)
The voltage drop across the drift region in the reverse mode can be obtained by integrating the electric field, using
p(!I) in (4.15), and by adding 1',,+:
I *',
I'drift = E, () di + I',,,+ (4.18) where E(y) is related to p(y) through a combination of the hole and electron current expressions [Fos88]. The integration in (4.18), done analytically, yields lIrift as a function of p V,(! ) and J)(TT,).
The VDMOST charge dynamics are defined predominantly by Qp in (4.17) in the reverse mode. In the normal mode, the bodydrift region junction depletion charge,
(4.19)
Qj 2 q1V:LJ?, DI1;d
78
is significant, as well as charge associated with the gate discussed in the next section.
4.3 SPICE Model
Based on the analysis of the VDMOST in Section 4.2, we propose a physical seminumerical SPICE model, the basis of which is
S= ~h + 1,ft (4.20) where Ijft is given either by (4.13) or (4.18) depending on the mode of operation. The complete network representation of the new SPICE model is shown in Fig. 4.5. The model is not a simple equivalent circuit. The elements shown represent physical components of current and voltage in the VDMOST, described implicitly by the analysis, which requires numerical solution. Note in Fig. 4.5 that 1lE,, (the voltage drop across the pbody resistance J,,R) and V1BO,,(= rh), which control 'CT and BR, are defined in accordance with the analysis of the parasitic BJT.
The transient behavior of the device is simulated using both the quasistatic currents/voltages and charging currents dQ/dt. The charges within the device are expressed in terms of node voltages as described in Section 4.2, and the transient charging currents are represented by the timederivative of the charges, using the quasistatic approximation:
 6 6 dA (4.21)
I. 4dQGD
Body/Soure CGS Lh dt
VB+Oh+
+ : R PBCT
VBCn ;I IBR dQp/dt dQj/dt
+
Fig. 4.5 Network representation of the chargebased VDMOST
model.
80
where i = P, J, and GD and . = GS, c,, BE,,. Included in (4.21) is the DMOST gatedrain charging current dQ(;D/dt. This current arises from the charge near the surface of the drift region under the gate electrode and is important in the switching performance of the VDMOST. The associated gate charge QGD is characterized by basic MOS theory for two different modes of operation. Whenl(;Sch, pFB > 0, the surface
is accumulated with electrons, and Q(;I)  LIT1:C,,r (;  h 1FB) with the approximation that the surface potential ..  0. When (; ;  i, VFB < 0, only depletion charge can exist under the gate electrode due to the usual highfrequency operation of
the device. In this case, I ;'  I",.h  =FB ='is + Q(D)/Co'r and QGD = Lr1IU V2qEN(7, ) define the charge.
The effective gatedrain capacitance associated with
dQ(D/l)t is amplified by the Miller effect into an equivalent input gate capacitance, thus slowing down the gatecontrolled
switching. Furthermore, dQGD/dt, with gatecircuit resistance can cause dl/dtinduced turnon [Bal87]. When I D.. is abruptly increased while 1';, < IT, the charging current through the gate resistance can increase the gate potential above I T, thus turning on the VDMOST. Also included in the model is C(,;,, the gatesource capacitance, the most significant component of which is that due to gate electrode overlapping the n+source.
All of the elements in the model are implemented in SPICE2 via userdefined controlled sources (UDCSs), which are
81
FORTRAN subroutines in SLICE [Har84], an enhanced version of SPICE2. Each UDCS accesses the VDMOST model routine, which is flowcharted in Fig. 4.6. The model routine numerically solves, using the NewtonRaphson iteration method, the implicit system of quasistatic equations developed in Section 4.2. The UDCSs, for a given NewtonRaphson iterate on 1g. lA, and 'BE, in the SPICE2 nodal analysis, provide the element currents, or voltage for IdrIfI, and the needed partial derivatives with respect to the node voltages. The derivatives are calculated via difference equations, based on multiple calls of the model routine. In the chargingcurrent UDCSs, backward Euler method for numerical integration is used to get best numerical stability. The seminumerical VDMOST model, implemented in SPICE, provides then a twolevel Newton method for device/circuit simulation. Note that the model, once finalized, can be written directly into the SPICE2 source code by modifying the algorithm in Fig. 4.6 to accept the device terminal voltages as input from the circuit nodal analysis.
The negative resistance often observed in lJ)s  V,)S measurements of the VDMOST is mainly due to the local heating of the device. When  is increased for a given l g in the saturation region, the local power dissipation elevates the device temperature, and concomitantly reduces the carrier mobility as well as the saturation velocity; hence IDS decreases. If the duty cycle for the pulsedmode
y
Normal Mode Calculate I oh
Fig. 4.6 Seminumerical VDMOST modelroutine flowchart. Both
normal and reversemode paths are shown within the
outer iteration loop for local heating.
83
measurements is reduced, less heating occurs and consequently the negative slope in the IsIDs characteristics tends to be eliminated. To account for this effect for general DMOST/HVIC simulation, we implement the concept of thermal resistance in the SPICE model. The device junction temperature (1') is different from the ambient temperature (7T,) as follows:
T = To + RthI IDS (4.22) where Rth is the thermal resistance of the device. Empirical relationships between mobility and saturation velocity and temperature [Mu177] are used to implement (4.22) in parameters ifl,.1,d, and i,. This implementation (which does not include the BJT temperature dependence) requires another iterative solution around the basis model routine as shown in Fig. 4.6. It can be superseded if local heating is negligible.
4.4 Model Verification
Test VDMOSTs are fabricated at AT&T Bell Laboratories using the dielectric isolation (DI) BCDMOS technology [Luc88]. Our initial measurements were done using a very low duty cycle
(1%) to avoid the negativeresistance effect in the II)s Vl) characteristics. The duty cycle is a critical parameter in the measurements as we note below in the discussion of localheating simulations.
In Fig. 4.7, measured dc Ii(;. ; ) data for two VDMOSTs having driftregion widths L,1 are compared and
0. 8 W 
12V
0ï¿½ 0V
0 2
1
Ld4um
0.0 00 BV
0.2
VGS6V
O0 1 __ ..... . 1..
0 20 40 60 80 100 VDS [V]
Fig. 4.7 Simulated (curves) and measured (points) VDMOST
currentvoltage characteristics for two different
driftregion widths L,I.
85
show good agreement with modelsimulated currentvoltage characteristics. The simulated characteristics were derived from SPICE with our new DMOST model, using known structural device parameters and crudely extracted model parameters that fit the measured data. The channel length L is 2 /,m. The device width TV. was taken as the sum of subcell widths and thus effectively accounts for the device layout. The key model parameters which determine the (channel) saturation characteristics are 1,,. N11, and , in the channel region. Parameters N,,). N1), and , in the drift region are the key parameters for the quasisaturation characteristics. Quasisaturation, reflected by no dependence of the drain current on the gate bias and by high output conductance without the current saturation, is predominant for the L,1 = 4 /im device.
In Fig. 4.8 we show SPICEsimulated transient characteristics of the VDMOST with an inductive load. As the gate voltage is dropped to turn off the device, the drain voltage ( I ,) is abruptly increased above the offstate blocking voltage due to the negative voltage drop across the inductor
(LL). Due to this quick increase of V the charging current of the depletion region of the bodydrift region junction (dQ./dt) flowing through 17,,B produces a voltage drop jE,,, which can turn on the downmode npn BJT. In addition to Lf, the load resistance RL also affects the turnoff time. As RL increases, (QJ/dt slows down due to small drain current; thus the turnoff time is increased.
60
5040"
20 10.
0
time Ceac]
Fig. 4.8
Simulated inductive turnoff transients for the LI= 10 ;,m VDMOST. The inductor (LL = 5 /,H) in series with RL (= 250 Q) is connected to the drain from the blocking voltage source (l'q = 20 V), and 1(;,; is pulsed as indicated. The simulated 17)s(f) and IBE.(t), the voltage drop across the pbody resistance, are shown.
2 4 8
1
8
x107
87
Simulated reverserecovery characteristics of the VDMOST is shown in Fig. 4.9. Initially the device is in the reverse mode, in which the upmode BJT is activated and a high concentration of carriers (holes and electrons) is stored in the drift region. Therefore the reverse recovery is slow, controlled by the carrier lifetime (nil = 0.2 i,;) in the drift region. The device is then switched from the reverse mode to the normal blocking mode. For R,,B = 0, the simulation shows about a 0.1 ,ts delay. But for R,,13 = 2.5 ohm, the downmode BJT is turned on by the voltage drop across RlB (IdQ,/dtIR,,H>0.7'); the delay is longer (0.2 lS). For larger RIB = 10 ohm, the BJT becomes heavily saturated, and the VDMOST does not turnoff for times up to 1 lis. It will eventually turn off unless destructive breakdown occurs.
Figure 4.10 shows Ij, DS, characteristics of the VDMOST measured with a higher duty cycle (3%), which show localheating effects. The simulated characteristics, also shown in the figure, were fitted to the measurements by varying the parameter Rth in (4.22). As l;S and I increase, the local heating becomes more severe and the negative resistance becomes more predominant as indicated by the measurements and predicted by the simulations. Note that Rft tends to be higher for DI devices than for junctionisolated devices.
0.4 RPmlOohm
0. 0. 25o
0.4
0.8 I __ I I
0 0.2 0.4 0.6 0.8 1
t Ime Ceao)3 x10Fig. 4.9 Simulated reverserecovery current transients for
the L4i = 10 /im VDMOST with different pbody resistances. The drainsource voltage, applied through a 10Q series resistor, changes from 5 V
to +4 V with a 0.1ps rise time starting at 0.1 js.
0. 8 L..LJJUa r V f
!~ 0.0
(OV
S0.4
BV
0.2
VGSOV
0 20 40 60 80 100 VDS CV3
Fig. 4.10 Simulated (curves) and measured (points) VDMOST
currentvoltage characteristics which show localheating effects. The duty cycle used in the measurements is 3% and the extracted thermal
resistance Rth is 0.5.
90
4.5 Summary
The VDMOST model developed herein is useful for HVIC CAD, which requires reliable physical device/circuit simulation. Some of the modeling is applicable to LDMOSTs as well. The chargebased models are quasistatic; nonquasistatic (NQS) effects, which can be significant in HVICs, could be accounted for via physicsbased extensions [Fos88]. Comprehensive transientmodel verification based on device/circuit measurements would be required to ascertain the significance of NOS behavior. The models are seminumerical, an unavoidable trait of good physical models, but are implemented in SPICE. The UDCS implementation described is CPUintensive and is intended only for preliminary SPICE model verification. Indeed once the models are finalized, they can be written directly into SPICE source code, creating a seminumerical device/circuit simulator for MOS HVICs.
CHAPTER 5
NEW PHYSICAL INSIGHTS AND MODELS FOR LDMOST IC CAD
5.1 Introduction
This chapter presents a physical composite model for lateral DMOSTs (LDMOSTs) [Cla86]. The modeling methodology developed in previous chapters culminates in this chapter: the physical insights gained from PISCES simulations are used as a basis for developing the composite LDMOST model, in which the device is regionally partitioned into several onedimensional components, and carriertransport equations in each region are solved. The model is implemented in SPICE using FORTRAN subroutines and is supported by measurements. Device and circuit simulations show the superiority of the model over equivalentcircuit models.
Highvoltage integrated circuits (HVICs) including LDMOSTs are now viable alternatives to hybrid circuits comprising discrete highvoltage devices. Optimal design of these HVICs requires physical LDMOST models implemented in a circuit simulator like SPICE. Equivalent(sub)circuit SPICE models for the highvoltage LDMOST [Wil87] have some utility, but are fundamentally deficient; they cannot simulate unique power device characteristics such as quasisaturation and reverserecovery transients.
92
Several physical investigations of the onresistance of LDMOSTs (Col81, Men86, Poc76] have been done, but a complete physical model has not been reported. LDMOSTs in HVICs are subjected to unusual operating conditions, and hence robust models are needed. For example, an inductive load in power circuits will force the LDMOST into high current/voltage regimes where reverse current flow through the device may occur. Claessen and van der Zee [Cla86] presented a model for the LDMOST covering the high current/voltage region. But their model is limited to dc conditions, and it does not account for quasisaturation nor the inherent BJT, which is commonly activated in HVICs.
In this chapter we develop a new physical chargebased LDMOST model which accounts for the BJT. We study both the lightly dopeddrain (LDD) and the reducedsurfacefield (RESURF) nchannel LDMOST structures, using the twodimensional device simulator PISCES [Pin84] for guidance. The PISCES simulations provide new insights on normaland reversemode dc operation of the LDMOSTs and on the significance of the inherent npn BJT in transient reverserecovery characteristics. We emphasize the LDD LDMOST structure (see Fig. 5.1(a)), which we regionally partition into three components: the channel, the drift region, and the npn BJT. The composite model is implemented in SPICE for HVIC CAD. The modeling methodology is also applicable to the RESURF LDMOST structure (see Fig. 5.1(b)), and with our
G
(a) p
G
P (b)
n
p
Fig. 5.1 Unitcell structure of (a) the LDD and (b) the
RESURF LDMOST.
94
physical VDMOST modeling in Chapter 4 defines LDMOST models for either technology.
5.2 New Insights By Numerical Simulations
PISCES [Pin84] simulations have been done to gain physical insight regarding both the LDD and the RESURF LDMOST structures. This new insight facilitates the device modeling for circuit simulation described in the next section. PISCES is a twodimensional numerical semiconductor device simulator, for either dc steadystate or transient bias conditions. It solves the basic semiconductor device transport equations, using plausible physical models. For the LDD LDMOST, we used dopingdensity profiles and structural dimensions obtained from Siliconix, Inc. [Wil87]. The LDMOSTs were biased into both normal mode (VDS > 0) and reverse mode (IDs < 0) in the dc simulations; the LDMOSTs were switched from the reverse mode into the normal mode in the transient reverserecovery simulation.
5.2.1 LDD LDMOST
The selfisolated LDD LDMOST is shown in Fig. 5.1(a). The channel region, which functions as a fast switch for the electron current flow, consists of two different regions: the doublediffused channel and the substrate channel. The doublediffused channel is nonuniformly doped by the difference of lateral diffusions between the pbody and the n+source. The

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PHYSICAL MODELING OF MO S CONTROLLED HIGHVOLTAGE DEVICES FOR INTEGRATED CIRCUIT COMPUTERAIDED DESIGN By JEONGSEUK KIM A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 1990 UK1VZR2I7Y CF FLORIDA LIBRARIES
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ACKNOWLEDGEMENTS I wish to express my sincere appreciation to my advisor, Professor Jerry G. Fossum, for his support and guidance throughout the course of this work. I also would like to thank Professors Dorothea E. Burk, Sheng S. Li, Khai D.T. Ngo, and Kevin S. Jones for their participation on my supervisory committee . I am grateful to Dr. M. Ayman Shibib of AT&T Bell Laboratories and Mr. Richard K. Williams of Siliconix Inc. for providing the test devices and helpful discussions. Thanks are also extended to many of my friends, JinYoung Choi, Joohyun Jin, SangGug Lee, Edward Solley, HaeSeok Cho, Dongwook Suh, Keith Green, Ghyboong Hong, DeokSu Jeon, and HanJin Cho, for helpful discussions and encouragement. Last I am deeply indebted to my parents, parentsinlaw, my brother and sisters, and my wife for their love and support.
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TABLE OF CONTENTS ACKNOWLEDGEMENTS ii ABSTRACT v CHAPTERS 1 INTRODUCTION 1 2 EFFECTS OF THE BUFFER LAYER ON VIGBT PERFORMANCE ... 7 2.1 Introduction 7 2.2 VIGBT Model 10 2.2.1 SteadyOnState 10 2.2.2 Transient TurnOff 16 2.3 TheoreticalExperimental Interpretations 18 2 . 4 Summary 28 3 STATIC AND DYNAMIC LATCHUP IN THE LIGBT 30 3.1 Introduction 30 3.2 Numerical Simulations 32 3.2.1 Static LatchUp 34 3.2.2 Dynamic LatchUp 40 3.3 SPICE Model 47 3.4 Model Verification 53 3.5 Summary 57 4 PHYSICAL VDMOST MODELING FOR HIGHVOLTAGE IC CAD . . 62 4 . 1 Introduction 4.2 Model 4.2.1 Channel Region 64 4.2.2 Drift Region 69 4.2.3 Parasitic BJT 74 4.3 SPICE Model 4 . 4 Model Verification 33 4.5 Summary
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5 NEW PHYSICAL INSIGHTS AND MODELS FOR LDMOST IC CAD . 91 5.1 Introduction 91 5.2 New Insights By Numerical Simulations 94 5.2.1 LDD LDMOST 94 5.2.2 RESURF LDMOST 101 5.3 LDMOST Model 104 5.3.1 LDMOST Channel 105 5.3.2 LDD Region 107 5.3.3 npn BJT HI 5.4 SPICE Simulations And Discussion 116 5.5 Summary 126 6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK 128 APPENDICES A BASE CHARGE PARTITIONING IN WIDEBASE BJT' S 131 B MODEL IMPLEMENTATION IN SPICE VIA UDCS'S 136 REFERENCES 159 BIOGRAPHICAL SKETCH 163 iv
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy PHYSICAL MODELING OF MO SCONTROLLED HIGHVOLTAGE DEVICES FOR INTEGRATED CIRCUIT COMPUTERAIDED DESIGN By YEONGSEUK KIM August 1990 Chairman: Dr. J. G. Fossum Major Department: Electrical Engineering This dissertation presents methodology for physical chargebased modeling of MOScontrolled highvoltage (HV) devices for integrated circuit (HVIC) computeraided design (CAD) . New models for two different MOScontrolled HV devices, the insulatedgatebipolar transistor ( IGBT) and the doublediffused MOS transistor (DMOST) , are developed. The effects of the buffer layer and static/dynamic latchup in the IGBT are characterized, and quasisaturation, spacechargelimited current flow, and effects of the inherent BJT in both vertical and lateral DMOSTs are modeled. These effects, which are not properly represented in conventional equivalent(sub) circuit models, are physically and sometimes semi numerically accounted for in our models. Twodimensional v
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numerical device simulations were used extensively to study the effects and to aid the model development. The developed models are implemented in the circuit simulator SPICE via FORTRAN subroutines (UDCSs) . With only known structural (device) parameters and crudely extracted model parameters, device/circuit simulations favorably predicted measured characteristics of test devices . The models in SPICE provide a capability of mixedmode device/circuit simulation, which is not afforded by other equivalent(sub) circuit models, and hence can facilitate computeraided optimal device/circuit design of HVICs . vi
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CHAPTER 1 INTRODUCTION Recent advances in highvoltage (HV) device technology have enabled the integration of HV devices with lowvoltage control circuitry on the same chip. Such highvoltage integrated circuits (HVICs) now commonly use MOScontrolled HV devices, exploiting the high input impedance of the MOS gate relative to that of power bipolarjunction transistors (BJTs) . The MOS channel is usually formed by a doublediffusion process; sequential diffusion of pand ntype impurities in the epi (or substrate) region yields the MOS channel as shown in Fig. 1.1. The doublediffusion process is widely used for HV devices because of easier process steps to achieve short channels while realizing high breakdown voltages. MOScontrolled HV devices built with the doublediffusion process include vertical and lateral insulatedgatebipolar transistors (IGBTs) and doublediffused MOS transistors (DMOSTs) . The difference between these two structures is due to the anode (drain) design; the IGBT is a modification of the DMO ST structure made by forming a pn junction at the drain contact as shown in Fig. 1.1 (for nchannel devices) . 1
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2 Gate Drain/ Fig. 1.1 Crosssectional view of the IGBT (p + Â— diffusion in the anode) and the DMOST (n + Â— diffusion in the drain) . Typical gate oxide thickness and channel length are 0.1 //m and 2 //m, respectively.
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3 Along with the matured process technology of HV devices and integrated circuits, CAD simulation tools should be developed to support optimal device and circuit design. The equivalent (sub) circuit SPICE models for HV devices that are used today are too empirical and do not properly account for the unique behavior of the HV devices, such as latchup in the IGBT and quasisaturation and spacechargelimited current flow in the DMOST . Therefore the development of physically based models for MOScontrolled HV devices, and implementation into the simulation tool, e.g., SPICE, are needed. The purpose of this dissertation is to develop and implement physical models of MOScontrolled HV devices, i.e., IGBTs and DMOSTs, for HVIC CAD. The effects of the buffer layer and static/dynamic latchup in the IGBT are characterized, and quasisaturation, spacechargelimited current flow, and effects of the inherent BJT in both vertical and lateral DMOSTs are modeled. The developed models are implemented in the circuit simulator SPICE via FORTRAN subroutines (UDCSs) . The major contributions made in this dissertation are (1) the formulation and solution of the steadyÂ— state and transient carrier transport problems in the IGBT including a buffer layer; (2) the study of static and dynamic latchup in the IGBT based on twodimensional numerical device simulations and the development of models for circuit simulation;
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4 (3) the development and experimental verification of physical chargebased models for both vertical and lateral DMOSTs; (4) the implementation of the IGBT and DMO ST models into SPICE using userdefined controlled sources (UDCSs) . In Chapter 2, a theoreticalexperimental study of the effects of the buffer layer on steadystate and transient vertical IGBT (VIGBT) performance is presented. Results indicate that previous studies are incomplete and hence misleading, and that in fact optimal design criteria for the buffer layer must be defined based on more comprehensive analyses. The study gives physical insight, needed in such definition, and describes proper model parameterextraction techniques not previously considered. In Chapter 3, an insightful study of static and dynamic latchup in the lateral IGBT (LIGBT) , based on extensive twodimensional numerical device simulations, is described. The insight is then used as a basis for developing a physical SPICE LIGBT model, which is useful for device simulation and design (e.g., for latchup immunity) as well as for HVIC simulation. The basic mechanisms underlying latchup in the LIGBT are identified for various excitations. The significance of the effective pin diode that materializes via the conductivity modulation in the regenerative process is stressed in the simulations, as is the importance of nonquasistatic bipolar
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5 transistor behavior, heretofore unrecognized. The SPICE model is supported by measurements of test devices and by the numerical device simulations. In Chapter 4, a physical, seminumerical chargebased model for vertical DMOSTs (VDMOSTs) is developed and implemented in SPICE. The model is derived from regional quasistatic analyses of carrier transport which implicitly characterize the device currents and charges and which require numerical solution. NewtonRaphson iterative device solutions are derived within the circuit nodal analysis framework of SPICE. PISCES simulations and measurements of test devices support the model, which is demonstrated in dc and transient SPICE simulations of VDMOSTs and HVICs . In Chapter 5, two different structures of the lateral DMO ST (LDMOST) , i.e., the LDD and RESURF LDMOSTs , are studied extensively using the twodimensional device simulator PISCES. The PISCES simulations provide new physical insights on the normaland reversemode operations of the LDMOSTs, which are used for developing the composite LDD LDMOST model. In the modeling methodology, the LDD LDMOST is regionally partitioned into three main components (the channel, the drift region, and the npn BJT) , and carriertransport problems in each region are solved. The composite model is implemented in SPICE for HVIC CAD and is supported by measurements. The modeling methodology is also applicable to the RESURF LDMOST.
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6 In Chapter 6, the main accomplishments of this dissertation are summarized, and suggestions for further research are discussed. Appendix A, related to Chapter 3, describes the algebraic manipulations of a base charge partitioning to represent nonquasistatic behavior in the bipolar transistor of the IGBT . Appendix B lists the UDCS source code of the LDMOST SPICE model developed in Chapter 5 .
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CHAPTER 2 EFFECTS OF THE BUFFER LAYER ON VIGBT PERFORMANCE 2 . 1 Introduction This chapter presents a bufferlayer model for the vertical IGBT (VIGBT) [Bali84] . The model, based on the onedimensional representation of the device, accounts for bufferlayer effects on both steadystate and transient characteristics of the VIGBT. The carriertransport (continuity/ambipolar) equations in the quasineutral regions of the device are solved to yield the dc currentvoltage dependence I.\(V\) and the turnoff transient characteristics I\(t) of the VIGBT. Some of the modeling is applicable as well to the lateral IGBT with a buffer layer, which is discussed in the next chapter. The VIGBT, also called the COMFET [Rus83], has recently emerged as a useful highvoltage power switch. It is a merged MOS/bipolar structure that exploits the advantages of MOS and bipolar devices to yield low forward (ON) voltage drop, fast switching time, and high input impedance. The basic structure of the vertical nchannel IGBT, shown in Fig. 2.1, has a DMO ST merged with a widebase pnp B JT . The n + Â— buffer layer [Goo83] between the n~Â— base and the p + emitter is commonly included to prevent punchthrough in the forwardblocking mode and indeed to enhance the device performance 7
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8 Fig. 2.1 Unitcell structure of vertical nchannel IGBT with n + Â— buffer layer. The external circuitry and gate bias indicated correspond to a transient turnoff from the steadyONstate .
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9 [Goo83, Nak85] . Such enhancement has been experimentally demonstrated as an increase in the (static) current required to latch the pnpn structure [Goo83] and as an improvement in the tradeoff between the steadyONstate voltage drop and the turnoff time [Nak85] . A recent theoretical study [Kuo86] implied design criteria for the epitaxial (n and n + ) layers of the device to effect this tradeoff. The study was not sufficiently rigorous however to guarantee optimal designs, as demonstrated in this chapter. A comprehensive theoretical study [Hef86] of bufferlayer effects on VIGBT performance, predicting that the buffer layer decreases the switching energy loss, was recently presented. This study involved much mathematical detail but little experimental support, and hence its results cannot be put into proper perspective because the relative significance of various physical mechanisms cannot be ascertained. In this chapter we use a similar, but simpler and more insightful model to fully explain performance data, including new experimental results given herein that seem to contradict [Nak85, Kuo86] and that suggest optimal design criteria for the buffer layer. The simple analytic model accounts for bufferlayer effects on both steadystate and transient characteristics of the VIGBT. We support the model expermentally , introducing useful parameterextraction techniques, and we discuss its utility alluded to above, explaining the seemingly contradictory data.
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10 2.2 VIGBT Model Our study of the buffer layer is done effectively using a simple model to describe both steadystate and transient characteristics of the VIGBT. The model is based on a regional analysis [Hef86, McD85, Fos86] of the onedimensional representation of the vertical p + n + nÂ“p BJT in the VIGBT illustrated in Fig. 2.2. 2.2.1 SteadyONState In the steadyONstate, a voltage is applied as shown between the emitter (anode) and collector (cathode) terminals, and the base is driven by the DMOST, the gate of which is biased above the threshold voltage to enable ONstate conduction. Consistent with typical operation, we assume highlevel injection (p ~ n) in the quasineutral n~Â— base region, and lowlevel injection in the n + buffer and p + emitter regions. We further neglect recombination in the relatively narrow buffer layer, an assumption which we have found to be reasonable for typical devices. We stress that the primary effect of the buffer layer on the device performance is manifested through the carrier transport across the layer, irrespective of any recombination in the layer. Additional simplification of the steadystate analysis is effected by noting that the BJT is constrained to operate in (near) the forwardactive mode, with negligible basewidth modulation, since the voltage drop across the DMOST is small [Fos86] .
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11 x=o w f + w f pri n i i i i i i n + j i i i i i i i i n T 1 1 1 P ( 'A (Emitter)  i i i j ! (Butter)  i i i i i i i i (Base) i i i i i i i i [(Collector) i i i J U Â— w tÂ— ! W B 2.2 Onedimensional representation of vertical p + n + n~p BJT in the VIGBT. The junction spacecharge regions are indicated by the dashed lines . Fig.
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12 Using a regional modeling approach (region boundaries are defined in Fig. 2.2), we first solve the steadystate ambipolar transport equation in the quasineutral nÂ“region, obtaining [Fos88 ] p(.r) ; / Wf +H'Â”Â— * smn I Â— L j[ sinl Â‘ (rr) ( 2 . 1 ) where L \ is the ambipolar diffusion length and TF = TT'/j is the quasineutral base width. Note in (2.1) that the carrier density drops to zero at the edge of the basecollector depletion region (x = W~ + IT") . The analogous solution in the quasineutral n + buffer layer, for a uniform doping density and negligible recombination, is p(Â»?) p(Â«) i,x = ifc *+PÂ«>) Â• (2.2) In (2.2) we have used the fact that the width of the n*n spacecharge region is much narrower than the bufferlayer width ir ,, but have properly accounted the significant difference between p (ir+) and p(\Vj). In fact, for quasiequilibrium in the spacecharge region, p{ W f) N Df= [P(W F )Y ( 2 . 3 ) where N Df is the bufferlayer doping density. To derive the dc current voltage dependence I A (V A ) of the VIGBT and relate it to the bufferlayer properties, we must connect the boundary hole densities, p( 0), p (V+) , p (uj) in
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13 (2.1) and (2.2), to the terminal conditions. To make this connection, we first express the hole current density in the buffer layer as Jp (o < .r < ir+ ) ~
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14 J A = l + b J X0 b "i/Nof p( 0) + 1 + b coth ( W/ L A ) qD A (Â”Â’/) Â• ( 2 . 8 ) The three equations (2.3), (2.6), and (2.8) define the boundary hole densities in terms of J A but also involve TT', another unknown variable. To define I,\(V A ) then, two additional expressions relating V A to the unknown variable must be derived. Referring to Fig. 2.1, we write V\ as the sum of the internal voltage drops : ^A = y'j Â” + I . " " + V f Â„, + I a Hs + IbRmos (2.9) where I A = AJ Al Iq Â— AJb, and A is the device area. In (2.9), + ..+ v; " = V T ln P( 0)N Df ( 2 . 10 ) is the drop across the emitterbuffer junction, (">') = V T lv A Ue ( 2 . 11 ) is the drop across the bufferbase junction, X De is the epi doping density, and J A f1r + b)n v p{x) It 7 Â— In 6 + 1 p(Tr w ) ( 2 . 12 ) is the drop across the (conductivitymodulated) n _ epi region, which is approximated as the integral of the electric field [McD85 ] from IT ^ to IT the point at which />(;Â»Â•) in (2.1) equals Dr Â• The last two terms in (2.9) are ohmic drops across the
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15 extrinsic series resistance /?
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16 /* A. 4 /J/[l + (1 AVj)/J]. we stress that models based strictly on onedimensional analyses [Nak85, Kuo86, Hef86] can be quite misleading. 2.2.2 Transient TurnOff The unique transient turnoff characteristic of the VIGBT, comprising an initial rapid drop in forward current followed by a slower decay, was previously modeled [Fos86] without accounting for the buffer layer. An extended version of this model, derived straightforwardly following Fossum and McDonald [Fos86], is used here to account for the bufferlayer effects. The initial rapid drop, A/, is modeled as in Fossum and McDonald [Fos86], but is based on the steadystate characterization including the buffer layer described above. The slower transient, /,(,), is modeled as Q p (t) /r, p [Fos86] , where r lp is the (average) base transit time, but now the hole charge in the quasineutral base, Q pr is governed by a modified [Hef86] differential equation (in time t) which accounts for the buffer layer in the relation between Q p and Q nt the minority electron charge in the quasineutral emitter : Ir Qp(*) , T ll 'IQp ( * ) , Qn(t) approaches
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18 zero (viz., no buffer layer), T If(eff) approaches r n , and (2.18) simplifies to the result derived in Fossum and McDonald [Fos86] . Physically, the second term on the right side of (2.19) represents the effect of recombination in the p Â—emitter on I A (f) r influenced by the buffer layer through which the recombining electrons must flow. Hence even with a buffer layer in place, if ./ Vo becomes negligibly small, then aiso T I1{(ff) ~ t, { and I t (/) ~ I\txp{ t/r H ) . 2 Â• 3 TheoreticalExperimental Interpretations VIGBTs fabricated at RCA/DSRC were measured. Typical I A (V\) data taken from an nchannel device (with the gate biased at 10 V, about 8 V above the threshold voltage) are plotted in Fig. 2.3. The simulated characteristic, also shown, was derived from the model outlined in Section 2.2, using known structural device parameters and doping densities. The key model parameters, i.e., r H . J v Â„, /?. v , and B ]IOSr were extracted from additional steadystate and transient measurements as follows . The transient turnoff characteristic, modeled by (2.18), was measured for an ONstate current /Â„ low enough to ensure that I A (f) is exponential as described by the numerator of (2.18). This measurement gives r //(f//) directly, subject of course to the validity of the model assumptions. (We have found that if the OFFstate voltage is high enough (> 200 V) to cause a significant transient variation of the quasineutral
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19 Fig. 2.3 Measured and calculated steadyONstate current V^GB? 1 '
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20 base width (IT nr,i), then r H{t ff) can be overestimated.) Using (2.19) then, t h and J N() were evaluated by fitting the model prediction for the turnoff time T 0 and its dependence on /Â„. T 0 is the time required for I A (t) to drop to 0.1/Â„; it was measured by pulsing the gate ON (10 V) and OFF (0 V), while the anode was biased through a resistive load. The modelpredicted T 0 vs. was derived by first modeling the steady state, and using the results to characterize the transient turnoff as described in Section 2.2. Plotted in Fig. 2.4 are the measured T 0 vs. data along with the model characteristic (which corresponds to t h ~ 12 [is and ./ jVo ~ 1.1 x 10 13 A/ cm 2 at T = 25Â°C) . The theoreticalexperimental fits illustrated in Figs. 2.3 and 2.4 also involve iterative evaluation of R s (~ o.08 ft) and R uos (~ 0.04 ft) , the dependence of which on gate voltage enables separation from the series resistance. Since the T 0 (l o) characteristic is not strongly dependent on the small resistances R s and R MOSr their extraction is made mainly from the I A (V A ) characteristic. in all cases the model predictions matched the measurements well, without much empiricism involved. The theoretical experimental agreement gives credence to our model and demonstrates the utility of the parameterextraction techniques. We now show how the model can be used to give physical insight and thereby aid the optimal design of the buffer
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21 2.4 Measured and calculated turnoff time vs. ONstate ~ 25 Â° C) Â’ ThS model Parameter values used are the same as those given in Fig. 2.3 Fig.
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22 Fig. 2.5 Measured forwardvoltage drop vs. turnoff time taken from pchannel VIGBTs having different llfetimes in the epi base region. The ONstate current was held constant as indicated Â°f. a pe }. le ^ araa of 120 X 120 mil 2 ; the OFFstate oltage ] B 400 V. The data points are connected dependences*! t0 em P hasi ^ th * Parametric
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23 layer. Plotted in Fig. 2.5 are additional data taken from pchannel VIGBTs fabricated at RCA/DSRC. The measured 0Nstate voltage, V Ar versus T 0 for three bufferlayer doping densities, j\ Af , was obtained from devices in which the carrier lifetime was varied by heavymetal diffusion. The ONstate current I 0 was held constant. The data show that predominantly for a given T a , ] A increases as N Af is increased, thus suggesting that N Af be low for optimal design. This suggestion is contrary to that emanating from corresponding (nchannel VIGBT) data [Nak85], which show that for a given T Â°' } [ decrease s as X Df is increased, and from theoretical predictions [Kuo86] . This apparent contradiction can be explained with reference to our analysis. We note that for a given t h , an increase in N Uf will tend to decrease the carrier injection level in the n'base region, which concomitantly tends to decrease T 0 , but to increase V A because of the higher V fpi in (2.9). if the decreased^ tendency is predominant, and the increase in V A Â± 8 less significant because, for example, V ept is negligibly small, then the implication regarding optimal X Df [Nak85, Kuo86] is obtained. Otherwise, the opposite implication in Fig. 2.5 is obtained. Based on our studies, we deduce that this opposite effect is evident only when the injection level in the n~base region is predominantly low, thus yielding a very high i;,,, as in the ordinary power MOSFET. In fact the VIGBT with a very high N Df (and/or wide TT'y) behaves as a power MOSFET with
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24 no benefit from conductivity modulation. Thus optimizing the bufferlayer design is more involved than previously stated [Nak85, Kuo86, Hef86] and must involve a more comprehensive study of the effects of all regions of the VIGBT . Such a (theoretical) study is illustrated in Figs. 2.6, 2.7, and 2 . 8 where we plot calculated V A T n curves for different values of key device parameters, Nu f . Wj, and ./ jVo . The curves were derived by varying r H between 0.1 and 100 /is while holding J 0 and Vb constant. Note in each figure that points corresponding to a specific t h define a locus on the V A T 0 coordinate system having a negative slope; viz., shortening T 0 via the parametric changes indicated necessarily increases 1 4 . In Fig. 2.6, the insight discussed above regarding the influence of Nof is illustrated. The convergence of the dif f erent Â— curves varies as the key device parameters, especially J NOf are varied. Additional calculations show that increasing J ^ 0 moves the point of convergence to the left, thereby enhancing the tendency shown in Nakagawa and Ohashi [Nak85] and predicted in Kuo and Hu [Kuo86] . Decreasing Â•7 ; vo moves the point to the right, enhancing the tendency reflected in Fig. 2.5. The convergence of the curves in Fig. 2.6, although predicted by our analysis based on highlevel injection in the n Â—base region, nevertheless implies the onset of low injection which, as mentioned above, intensifies the opposite \ A Â— T 0 vs. Nd/ tendency shown in Fig. 2.5.
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25 Fig. 2.6 Simulated forwardvoltage drop vs. turnoffor two values of N nfr with ? Vf m Â°* X 10 A/cm Â» an Â°i U' B = 45 //m. time = 1
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26 Fxg. 2.7 Simulated forwardvoltage drop vs for two values of J Xo , with X Df U f ~ 10 /'"W and W B = 45 /,m. turnoff time 2 x 10 17 cm 3 ,
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27 Fig. 2.8 Simulated forwardvoltage drop vs. for two values of \Y f , with X Df = and for no buffer layer, all with A/cm , and II q = 45 /im . turnoff time 2 x 10 17 cmÂ’ 3 , /.Vo = 5 x 10 13
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28 The significance of J ^ u is further emphasized in Fig. 2.7. For a specified buffer layer, the calculated data plotted show that increasing ./, Vn decreases TÂ„ but also increases V'i, for the same / () . This is similar to the effect of the buffer layer: the BJT f3 is lowered, thereby reducing the quasiFermi level separation (forward bias) at the emitterbase junction and the injection level in the nÂ“Â— base region. Finally in Fig. 2.8, calculated dependences on W f are shown. Increasing IT/, analogous to increasing ./ v Â„, decreases T 0 but increases V A . For comparison, the case \V f = 0 (no buffer layer) is also shown, indicating that adding the buffer produces the same tendencies as increasing ./ iVo . However, as can be inferred from our discussion, the effects of the buffer layer on the VIGBT performance cannot be ascertained without considering the significance of all key device parameters . We note for example that the benefit of the buffer layer is enhanced by a reduction of TT'# because V, p , in (2.9) tends to become less significant, and hence the TÂ„ V A tradeoff discussed is less critical. 2 . 4 Summary A simplified physical model for the VIGBT has been used to interpret both steadyONstate and transient turnoff measurements reflecting significant effects of the buffer layer. The theoreticalexperimental study has (i) provided good physical insight, (ii) implied optimal bufferlayer
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29 design criteria, (iii) described model parameterextraction techniques, and (iv) indicated shortcomings in corresponding results of previous work due to a lack of comprehensiveness in the analyses .
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CHAPTER 3 STATIC AND DYNAMIC LATCHUP IN THE LIGBT 3 . 1 Introduction This chapter presents static and dynamic latchup models for the lateral IGBT (LIGBT) [Darw84, Pat86] . in Chapter 2 , an analytic bufferlayer model for the VIGBT, which is similar in structure to the LIGBT except the anode layout, was developed and experimentally verified. The physical insight gained from the modeling of the VIGBT, and from PISCES simulations discussed here is used to develop the latchup models for the LIGBT. The LIGBT is a highvoltage powerswitching device that can be used in highvoltage integrated circuits (HVICs) . However the LIGBT, and VIGBT as well can be latched into an undesirable state in which gate control is lost. This state, which can be triggered either statically (by sufficiently high quasistatic current) or dynamically (by sufficiently high displacement, or transient charging current), results from the latchup [Rob86] of the parasitic pnpn structure in the LIGBT. The LIGBT must therefore be designed to avoid latchup in the operation of the HVIC. Computeraided design that includes latchup modeling for both device and circuit simulation is required. 30
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31 Very little previous work on the simulation of latchup (especially dynamic latchup, which is the predominant problem in HVICs) in LIGBTs has been done [Pat86, Darw87, Chow87] . In this chapter, we describe an insightful study of the static and dynamic latchup phenomena in the LIGBT, which culminates in the development of a physical model for SPICE simulation of HVICs. The study is based on extensive simulations of latchup in the LIGBT using the twodimensional device simulator PISCES [Pin84] . The simulations reveal the internal mechanisms underlying static and dynamic latchÂ— up Â£ot a variety of excitations, and they show that the lateral pnpn structure becomes an effective pin diode after latchup because of the excessive conductivity modulation near the surface. In fact, the conductivity modulation is observed to be the governing mechanism in the latching and in the latched state (in accord with analyses of latchup in CMOS ICs [Sei87, Cou88]), and hence must be properly accounted for in the simulations. Also noteworthy is the discovered significance of nonquasistatic bipolar behavior [Foss86] in the dynamic latchup, as well as the possibility of different controlling charging currents, depending on the transient terminal conditions . Dynamic latchup can occur for very fast gatevoltage switching and/or for very high blocking voltages. The SPICE model for the LIGBT, including latchup, is developed by extending the chargebased VIGBT model in Chapter
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32 2, which comprises onedimensional physical representations of the ambipolar carrier transport in different regions of the device. The model is implemented in SPICE via userdefined controlled sources (FORTRAN subroutines) and is verified by measurements of test devices fabricated at AT&T Bell Laboratories , as well as by the PISCES simulations. 3.2 Numerical Simulations To gain the physical insight needed to develop the latchup model, PISCES [Pin84] was used to study both static and dynamic latchup in the representative LIGBT structure shown in Fig. 3.1. PISCES is a twodimensional device simulator, for dc or transient terminal conditions, that utilizes finiteelement approximations and a Gummel/Newton numerical method to solve the discretized semiconductor equations defining the carrier transport [Cou88], including contemporary models for the semiconductor parameters. Dopingdensity profiles and structural dimensions corresponding to our test devices from AT&T Bell Laboratories (see Section 3.3) were assumed. Although these LIGBTs are dielectrically isolated [Luc88], the insight afforded by the simulations and modeling we describe is helpful in analyzing the junctionisolated resurf device structure, which includes an additional vertical constituent bipolar transistor and which could include a shorted anode [Darw87, Chow87, Fos88] . As indicated in Fig. 3.1, in the steady onstate, the constituent DMO ST gate is biased
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33 V 8 >V t Fig . 3.1 LIGBT test structure with external circuitry and gate drive for a turnoff transient.
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34 above the threshold voltage and the anode is biased above the source/cathode (ground) through a load resistor. In the transient turnoff, the gate voltage drops, in a finite fall time, to zero. 3.2.1 Static LatchUp The static latchup is demonstrated in Fig. 3.2 where a PISCESsimulated dc currentvoltage characteristic of the LIGBT is shown. To enable simulations of the entire (multivalued current) characteristic, in reasonable computation time [Cou88] , the applied anode voltage was increased incrementally to derive the sublatch current, but after latchup (onset at point where dV A /dI A = 0) , the anode was driven with an increasing current and the voltage was derived from the simulation. Above the onset of static latchup, a negativeresistance region reflects the regenerative latching mechanism involving the lateral pnp transistor (the anode is the emitter) and the parasitic npn transistor at the cathode (the DMO ST source is the emitter); see Fig. 3.1. The regeneration occurs because holes injected from the forwardbiased anode are collected and flow laterally though the npn base pinch resistor R pBr producing a forward bias (predominantly under the DMO ST gate) on the npn emitterbase junction. Electrons thereby injected (predominantly laterally) from the source drive the npn base harder, producing additional forward bias on the anode junction and
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35 LA. Â— VA (PISCES) Fig. 3.2 PISCESsimulated LIGBT current voltage characteristic showing static latchup. The gate bias is
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36 additional hole injection. The process thus enhances the conductivity modulation of the pnp base region, including the adjacent spacecharge region at the npn basecollector junction. This junction is ultimately neutralized as I\ increases by the holeelectron plasma, and the steady latched state is characterized by the effective pin diode that materializes [Sei87, Cou88] . For a point in Fig. 3.2 below latchup, Fig. 3.3 shows the simulated current flowlines within the device. Normal LIGBT operation is evident; the channel current of the DMO ST supplies electrons to the base of the lateral pnp transistor which support, through recombination, the hole transport current. The LIGBT (anode) current equals the channel current plus the pnp collector current . Note that most of the hole current flows laterally through R pH in the npn base region, but the induced ohmic drop is not sufficient to significantly forwardbias the source junction; the electron current is confined predominantly to the DMO ST channel . The simulated current flowlines in Fig. 3.4 reflect operation above the onset of latchup in Fig. 3.2. In contrast to the condition pictured in Fig. 3.3, we see in Fig. 3.4 significant injection of electrons from the n + source (emitter) into the npn base and collector (pnp base) . The hole current flowing through R r n produces a voltage drop which in this case is high enough to activate the npn transistor.
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37 Fig. 3.3 PISCES simulated current flowlines in the LIGBT in . * 9 1 q * 1 ^ased below latchup. The anode current mu X , . 10 A // ,m and the gate voltage is 10 V. arS plotted such th at equal currents , r between an y two adjacent flowlines. For the whole device (a), A/ = 0.2 x 10~ 5 A//,m; in the vicinity of the DMO ST (b) , A/ = 0.1 x 10" 5 A//,m
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38 Fig. 3.4 PISCES simulated current flowlines in the LIGBT in Fig. 3.1 biased above latchup. The anode current is 3.4 x 10 A///m and the gate voltage is 10 V. For the whole device (a). A/ = 0.2 x 10Â“ 5 A//,m; In the vicinity of the DMO ST (b) , A/ = 0 . 1 x 10~ 5 A//,m.
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39 and initiate the regenerative process in the pnpn structure. The predominant electron injection occurs laterally from the source under the DMOST gate where the forward bias is highest. For sufficiently high current, the basecollector junction of the npn and pnp transistors is highly conductivitymodulated (as in a quasisaturated transistor [Sze81]) by holes and electrons just below the surface, and an effective pin diode exists between the anode and the cathode/source of the LIGBT . The currentvoltage characteristic of this pin diode defines the negative resistance in Fig. 3.2, as well as the conductance of the latched device [Sei87, Cou88] . In this condition, removal of the gate voltage does not necessarily result in the turnoff of the LIGBT. As a leadin to the next subsection on dynamic latchup, we note here that the simulated steadystate Ii{V.\) characteristic in Fig. 3.2 is not the characteristic which would be observed in common current voltage measurements. In a curvetracer measurement, the voltage is swept up and down, and hence a multivalued current characteristic like that in Fig. 3.2 would show an apparent hysteresis. This hysteresis could be eliminated by sweeping the current instead of the voltage, but the dynamic nature of these measurements also can cause a hysteresis. In fact, the hysteresis observed in curvetracer measurements of latchup can be attributed, in part, to the dynamic nature of the current. PISCES and SPICE (using the LIGBT model presented in Section 3.3) simulations of a
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40 sweepingcurrent measurement show the hysteresis, with the latchup occurring at a higher current when I\ is increasing with time than when it is decreasing with time. The actual steadystate characteristic lies within the hysteresis loop. These results are consistent with HP4145 current driven measurements we have made and can be understood based on the insight gained in the next subsection. Another reason for the discrepancy between a (twodimensionally) simulated steadystate latching characteristic and a measurement is the (threedimensional) inhomogeneities in the actual device that can cause nonunif orm latching and hence also a hysteresis . 3.2.2 Dynamic LatchUp With regard to actual HVIC operation, dynamic latchup of the LIGBT is the real problem. When the gate voltage is dropped to turn off the LIGBT from an unlatched onstate, the device can latchup and continue to conduct. There are two distinct conditions which induce dynamic latchup. One is when the gate voltage drops very fast and induces excessive displacement current through the gate oxide that drives 7?,,^. The other one is when the (offstate) blocking voltage is quite high and induces excessive charging currents within the LIGBT during the switching transient that drive /?,,#. Of course the probability of dynamic latchup increases as
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41 the steady onstate condition approaches the static latchup onset (depicted in Fig. 3.2). For a resistive load as shown in Fig. 3.1, Fig. 3.5 shows PISCESsimulated transient turnoff characteristics, I.\(t), for a short gatevoltage fall time (t f = 0.5 ns) and for two different initial steady onstate currents (Iu/Il = 0.25, 0.86, where Ii is the static latchup onset current). The off state voltage used is low (Vjj = 10 V) . For the lower initial current I t) , the turnoff is normal, but for the higher J 0 , a delay is seen Fig. 3.5. The device current flowlines for the latter case at three different times, shown in Fig. 3.6, reveal the nature of the transient delay. The induced gateoxide displacement current (predominantly electrons flowing off the gatedrain overlap capacitance into the pnp base) tends to drive the regenerative process in the pnpn structure. Although initially {t = 0.44 ns) the gate depletion (dis) charging current diverts holes away from /? /)0 , later (/ = 2.55 ns), long after the gate voltage has been removed, the transient voltage drop across R l>n is sufficient to activate the npn transistor, and significant conductivity modulation prevails in the device. The reason for this delayed activation is that the discharging of the depletion capacitance occurs relatively fast, and precedes a transient (electron current) drive on the pnp base from the discharging overlap capacitance, which increases the hole current through
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42 IA/IO t (PISCES) Fig. 3.5 PISCES simulated transient turnoff characteristics for a short gatevoltage fall time of 0.5 ns and for two different initial onstate currents, h/I r where //. = 2.2 x 10~ 5 A//,m is the static latchup onset current .
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43 Fig. 3.6 Current flowlines (A/ = 0.1 x 10 5 A///m) in the vicinity of the DMO ST at three different times in the transient turnoff simulation in Fig. 3.5 for /it///, = 0.86.
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44 RpB Â• However, in this simulation, this transient (quasidynamic) latchup is not sustained because of the low V B and the simple circuit configuration which are insufficient to force a steady latched condition. The LIGBT ultimately turns off after the delay caused by temporary activation of the effective pin diode. In real HVICs, this quasidynamic latchup can be converted to an actual dynamic latchup by stray capacitance and/or inductance and by higher V B . PISCESsimulated transient turnoff characteristics for higher (50 V, 400 V) and longer /y (50 ns) are shown in Fig. 3.7. In the case of the higher V B , dynamic latchup is evident, even though the gate displacement current is insignificant. As indicated by the current flowlines in Fig. 3.8, the latchup in this case results because of substantial charging currents induced in the LIGBT which flow through R pB . Note in Fig. 3.8 that the lateral current flowing through R j)B increases with time. This is explained as follows. During the first phase of the turnoff transient, I A (t) drops rapidly due to the removal of the DMO ST channel current [Fos86] . Then, in the resistiveload circuit, the anode voltage V A increases accordingly, which causes three distinct internal charging currents to flow, all of which are manifested by holes flowing through R pB which tend to induce the latchup. One is the displacement current that charges the basecollector junction as its reverse bias increases. This current is defined by the transient depletion capacitance of the junction [Fos86] .
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45 1.1 1.0 0.9 0.8 0.7 g Â°6 23 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 x 10Â“ a t [sec] IA/IO t (PISCES) Fig. 3.7 PISCESsimulated transient turnoff characterist i C tn f Â° r a relativel Y long gatevoltage fall time of 50 ns and for two different blocking voltages ' B Â• VB = 400 V VB = 50 V
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46 Current flowlines (AI = 0.1 x 10~ 5 A/,/m) in vicinity of the DMO ST at two different times the transient turnoff simulation in Ficr 3 7 V B = 400 V. the in for Fig. 3.8
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47 Another current is the transient base transport (collector) current of the pnp transistor, which increases because of the shrinking quasineutral base width [Fos86] . The third current, which has previously not been recognized as being significant, is the component of the quasi neutral base discharging current that flows out the collector. Conventional quasistatic transistor models [Sze81] do not account for this charge partitioning [Foss86] , which actually reflects a nonquasistatic behavior, and simply associate all the base charging current with the emitter. For fast transients, like latchup in the LIGBT, the base charge partitioning must be used to account for transient charge redistribution [Foss86] . Our SPICE simulations (discussed in the next section) reveal that the nonquasistatic collector component of the base discharging current is critical in simulating dynamic latchup in the LIGBT. In fact, this component is typically (for our devices) the largest discharging current flowing during the turnoff transient; it controls the dynamic latchup. 3.3 SPICE Model Using the physical insight gained from the PISCES simulations described in Section 3.2, we extend the physical SPICE model for the LIGBT [Fos88] to properly account for latchup. The network representation of the new SPICE model is shown in Fig. 3.9, superimposed on the LIGBT structure. All the elements in the model, the underlying physics of which is
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48 V 0 >V T Fig. 3.9 Network representation of the SPICE LIGBT model superimposed on the device structure .
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49 described below or in Fossum et al . [Fos88] , are implemented in SPICE via userdefined controlled sources (UDCSs) [Vee86] , which are FORTRAN subroutines in SLICE [Har84], an enhanced version of SPICE2. The new model in SPICE provides a mixedmode device/circuit simulation capability, which in fact is essential for realistic simulations of latchup in HVICs and which is prohibitive in PISCES because of limitations on the allowed terminal drive conditions and because of the prodigious computation times required for the device simulation. (Computation times are compared in Section 3.4.) The new model in Fig. 3.9 includes basic LIGBT elements defined in Fossum et al . [Fos88] . They were derived by regionally partitioning the LIGBT into onedimensional widebase bipolar transistors coupled to the DMOST . The ambipolar transport problem for high injection in the transistor was solved analytically, but not in closed form, to define a charge based module. The system of module equations is solved by the circuit simulator during the nodal analysis to characterize all elemental currents, including the charging currents dQ/dt, based on the quasistatic approximation. The model extension presented here includes (a) a module for the parasitic npn transistor, including the emitter as well as the base resistances, (b) nonquasistatic charge partitioning in one pnp transistor module (the second pnp module [Fos88] is not crucial here) , and (c) representation of the effective
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50 pin diode that forms during latchup. These extensions, needed for the proper simulation of latchup, are now described. The current sources IcÂ„. and IgÂ„ model the parasitic npn transistor at the cathode which, in latchup, is activated by the voltage drop across the base pinch resistor R v g. Following conventional bipolar modeling [Sze81], we describe, to first order, the collector current as Icn = IsCXp[
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51 the Appendix A) to give the best approximation for the nonquasistatic behavior associated with the distributed charge dynamics. As described in the Appendix A for high injection and significant base recombination, Qbe Â— (2/3 )Qb (3.3) and Qbc (l/3)Qfl (3.4) where Qb is the total quasistatic hole charge stored in the quasineutral base region [Fos88] . Interestingly the charge partitioning in (3.3) and (3.4) is approximately the same as that derived for the case of low injection in a uniformly doped base with negligible recombination [Foss86] . We stress that the conventional quasistatic model [Sze81] , in which Qbe = Qb an <* Qbc ~ 0, will give significantly erroneous simulations of latchup in the LIGBT. In general (see the Appendix A and Fossum et al . [Fos88]), Qbe and Qbc depend on both the emitterbase and basecollector junction voltages. This means, for example in the predominant forwardactive mode of the pnp transistor, that the charging current dQ bc l dt cannot be represented by a simple capacitor [Fos88]; in fact, the component (dQ Bc / OVeb) dV EB l dt reflects a transcapacitance, and the network in Fig. 3.9 inherently accounts, to first order, for any nonreciprocity and nonquasistatic behavior in the device.
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52 In a transient turnoff simulation of the LIGBT, dQgc/dt is important because it reflects the finite carrier transit time in the quasineutral base [Foss8 6] . Thus, as we will illustrate in Section 3.4, it tends to reduce the fast initial drop in LIGBT current by the removal of the DMO ST channel, and it places an additional transient drive on which renders the LIGBT more vulnerable to dynamic latchup. When the LIGBT latches, the effective pin diode between the anode and the cathode materializes because of the conductivity modulation of the basecollector junction of the pnp and npn transistors. This pin diode, which actually defines the latching characteristics [Sei87], is simulated in our model by a semiempirical nonlinear resistor R pin as indicated in Fig. 3.9. The resistor, which effectively shunts the basecollector junction when the npn current is sufficiently high, is characterized in accord with quasisaturation modeling of the npn transistor [Sze81] . if we assume that the electrons drift through the junction spacecharge region with saturated drift velocity v a , then the electron (and hole) density in the region is approximately I Cn /qAv s where A represents an area of the junction (predominantly under the DMO ST gate) that is modulated. Consequently we assume that the modulated region is a shunting resistance (for hole flow) given by Rpin Â— scrV 9 / flplcn (3.5)
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53 where ir, rr represents the width of the highfield spacecharge region, which is assumed to be a constant extrapolated crudely from the equilibrium depletionregion width. The important dependence in (3.5) is that on I c Â„ . Below latchup, the npn transistor is not activated significantly, and the low I Cll defines a large R v , n that is inconsequential in the model network. As If,, increases, decreases, simulating the effective removal of the junction potential barrier by the holeelectron plasma. This semiempirical model for the effective pin diode is simple, but as we show in the next section it portrays LIGBT latchup adequately. 3 . 4 Model Verification LIGBT test structures with two different pnp base widths (N B = 7 8 /'m, 128 //m) were fabricated using the dielectricisolation bipolar CMOS DMOS (BCDMOS) technology [Luc88] at AT&T Bell Laboratories. Each device is contained in a separate silicon tub dielectrically isolated from the substrate as well as other components, and all terminals are accessible from the top surface. Measured and SPICEsimulated (quasi) static latchup current voltage characteristics are shown in Fig. 3.10 The measured data in Fig. 3.10(a), taken with an HP4145 parameter analyzer using a currentsource driver, show an abrupt transition from normal LIGBT operation to the latched pindiode mode, in which the gate control is lost (the
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54 IA CmA) Fig. 3.10 LIGBT static widths i U ^ r t nt ~ VOltage characteristics, showing latchup, for two different lateral base (a) Measured; (b) SPICEsimulated.
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55 device cannot be turned off by removing the gate voltage) . The simulation results in Fig. 3.10(b) show the latchup, not so abruptly but representatively. No rigorous model parameter extraction was done; representative values [Fos88] were assumed. Note that the latchup onset current decreases with decreasing TT'y, in both Figs. 3.10(a) and 3.10(b), and that the latchedmode conductance is higher for the narrower ir fl . These results are due to the dependence of the pnp current gain /3 p on TT Br which is implicitly modeled by the system of pnp module equations [Fos88] underlying I E , I Cr and ] fpi in Fig. 3.9. Decreasing 1V B increases l r (from about 0.6 to 1.0 in this case), which means, for a specific anode current I Ar a larger fraction of it flows through R v Bt thereby promoting the latchup at lower I A . The good correlation between the measurements and simulations in Fig. 3.10 provides sufficient support to conclude that the SPICE model, with the semi empirical in (3.5), does indeed give reasonable simulations of static latchup. A dynamic latchup simulation, for the case of very high blocking voltage (\ B = 400 V) as discussed in Section 3.2, is shown in Fig. 3.11. For contrast, the simulation of the turnoff transient of the same device but with a lower V B (= 50 V) is also shown; this turnoff does not result in latching. In the case of the higher V Br the LIGBT latches because of higher charging currents flowing through R pB .
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56 IA/IO Â— t (SLICE) Fig. 3.11 SPICE simulated transient turnoff characteristics for a gatevoltage fall time of 50 ns and for two different blocking voltages ]' B .
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57 The significance of the base charge partitioning (nonquasistatic discharging) in the pnp transistor is demonstrated in Fig. 3.12 where we plot the excess (above the steady onstate bias) transient baseemitter voltage of the npn transistor taken from the SPICE simulation of the ]' B = 400 V turnoff. For comparison, the component of this excess voltage due to the current < IQ DC M flowing through n,, B is also plotted in the figure. This component in fact exceeds transient voltages due to the other two discharging currents . Other simulations reveal that the maximum controllable (onstate) current for the LIGBT is overestimated when Q B c is neglected as in conventional quasistatic transistor models. Comparison of the transient simulations in Fig. 3.11 with the corresponding PISCES simulations in Fig. 3.7, which show qualitative agreement, gives support for the SPICE model in dynamic latchup simulation. (No attempt was made to tune the SPICE model parameters based on the PISCES simulations.) We note further that the SPICE simulations required only about 1/600 of the computation time of the PISCES simulations. 3 . 5 Summary An insightful study of static and dynamic latchup in the LIGBT, based on extensive PISCES simulations, has revealed the important underlying physical mechanisms and has facilitated the development of a physical SPICE LIGBT model for HVIC simulation. The SPICE model was supported by measurements
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58 AVBEN Â— t (SLICE) Fig. 3.12 The excess transient baseemitter voltage (solid pb Â° f the npn transistor in the V B = 400 V ^Â“ Ulati Â°" in Fi9 ' 3 11 ' Â“d the "component Of this excess voltage (dotted curve) due to the partitioned discharging current
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59 of test devices as well as by the PISCES simulations. The study showed that the latchup is controlled by an effective pin diode that materializes between the anode and the cathode/source due to excessive conductivity modulation by the holeelectron plasma near the surface of the device. In the dynamic case, the regenerative process in the lateral pnpn structure can be triggered by either displacement current in the DMO ST gatedrain overlap capacitance (for very fast gatevoltage switching) and/or by internal charging currents in the constituent pnp bipolar transistor (for very high blocking voltages). Both PISCES and SPICE simulations of dynamic latchup in the LIGBT demonstrated, for the first time, the significance of nonquasistatic bipolar behavior (pnp base charge partitioning) in defining the maximum controllable onstate current. The chargebased SPICE model is useful in LIGBT as well as in HVIC design, since the model parameters are predominantly physical, structural designs to maximize latchup immunity can be derived and checked. The mechanisms by which a fast falling gate voltage and/or a high blocking voltage result in dynamic latching, subject to the proximity to static latchup in the steady onstate, can be simulated in such designs. Indeed dynamic latching under all possible circuit transients can be simulated representatively and with computational efficiency. Such simulations can lead to optimal designs, for a given technology, which could involve control of not only which
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60 previous studies [Rob86] emphasize, but also of RÂ„ F . y ;) . jÂ„. and even the DM0 ST properties [Cho88] . For example, we have done simulations, exemplified in Fig. 3.13, which show that latchup can be avoided for normal operating conditions by increasing the DMO ST source resistance R, lF to values which, albeit increase the onstate resistance of the LIGBT, are not infeasible. In such a design, the voltage drop across R llF is exploited to counteract that across R l>Dr and thereby reduce the bias on the parasitic npn transistor (see Fig. 3.9).
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IA[A] 61 Fig. IA VA (SLICE) 3 ' 13 sp ICE simulated LIGBT current voltage chÂ»rÂ»rtÂ„ rstrcs showing the effect of varying the DMOsi source resistance RÂ„ E . y g tne DM0ST
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CHAPTER 4 PHYSICAL VDMOST MODELING FOR HIGHVOLTAGE IC CAD 4 . 1 Introduction This chapter presents a chargebased model for the vertical DMO ST (VDMOST) [Huc84] . As in Chapter 3, the twodimensional device simulator PISCES is used to gain the physical insight the device operation and to aid the model development . The device is regionally partitioned into several onedimensional components and the carriertransport equations are solved in each region. The model is implemented in SPICE using FORTRAN subroutines . DMOSTs can now be merged with lowpower control circuitry to produce highvoltage integrated circuits (HVICs) . Effective CAD of such HVICs, and of those containing IGBTs described in Chapters 2 and 3, requires a physical DMO ST model implemented in a circuit simulator such as SPICE. However the equivalentcircuit MOST models in SPICE today are too empirical and do not properly account for important unique features of the highvoltage DMO ST such as quasisaturation, spacechargelimited (SCL) current, channel dopingdensity gradient, and local heating. In this chapter, we present a physical modeling methodology for DMOSTs intended for HVIC CAD. A seminumerical model, implemented in SPICE, is developed for vertical DMOSTs. 62
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63 Some of the modeling is applicable as well to lateral DMOSTs (LDMOSTs) , which are discussed in the next chapter. In the methodology, the DMO ST is regionally partitioned into two main components: the doublediffused MOS transistor (viz., the channel) and the lightly doped drain (drift region) . The constituent components are represented by chargebased models in which the current and charges are implicitly related to internal node voltages . The characteristics of the composite DMO ST model are derived seminumerically within the nodal analysis framework of SPICE. The model is supported by twodimensional numerical simulations done with PISCES and by measurements of test VDMOSTs. The PISCES simulations also aid the model development by giving physical insight regarding the unique field distribution in the channel, the excess carrier distribution in the drift region, and depletionregion modulation due to free carriers . The composite chargebased VDMOST model is not a simple equivalent circuit, but is a physical, semi numerical representation (in SPICE) of the underlying carriertransport equations. The critical elements are defined by an implicit set of nonlinear equations that require numerical solution, which is done using a NewtonRaphson iterative method within the model routine. In addition to the constituent channel and driftregion models, the (nchannel) VDMOST model accounts for the parasitic npn BJT, which is especially important
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64 with regard to the transient charge dynamics of the VDMOST. Further, localheating effects are included in the electron mobility model, which enables simulation of the negative resistance in the DMOST saturationregion characteristics . The intrinsic charge dynamics are accounted for directly via total time derivatives of stored charges, which are characterized semi numerically by the regional analyses. SPICE simulations of VDMOSTs and HVICs are presented to demonstrate the model. 4.2 Model The VDMOST (shown in Fig. 4.1) model is derived from regional analyses of carrier transport in the channel and regions. The parasitic BJT is accounted for in the composite model by physically based current elements, which can be activated by the lateral voltage drop across the pÂ— body resistance. 4.2.1 Channel Region The doublediffused nMOS transistor has a nonuniformly doped [Vi (.r)] channel region defined by the compensation between the pbody and nsource lateral diffusions. Y,(.,) has a maximum (iV 4 Â„) near the source and decreases sharply toward the dram. Consequently, as quantified by PISCES simulations for Vqs > 0, the inversion charge is minimum at the source, and hence the longitudinal electric field is maximum there (I r h oc E x Q n ) . Fig. 4.2 shows PISCESsimulated equipotential
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65 Fig. 4.1 VDMOST structure. The partitioning of the drift region is shown and geometrical parameters are defined. The common deep p + Â— body region, which does not influence our regional analyses, is not shown .
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66 PISCESsimulated equipotential contours (AT = 0 1 (V in _ t co 7 r lcd i nity of the ^OST [LUC88] channel O/rs; 50 V, ] r;s = 10 V) . On the and ,/axes 1 division = 0.1 ,, m . Â’ es ' Fig. 4.2
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67 contours in the channel of a typical DMO ST [Luc88] . The high density of lines near the source indicates the high electric field there. Our channel model is representative of these properties, and involves an appropriate gradualchannel approximation that yields the channel currentvoltage characteristic, with the threshold voltage defined by iV \o and the saturation controlled by driftvelocity saturation at the source (rather than at the drain as in the conventional MOST) We approximate the nonuniform doping density along the channel as an exponential function [X A (.v ) = i].r/L )] , and we use a piecewisecontinuous electron velocity model [Sod84] : ntf f 1 + ( Une f fE r / 2 V 9a i ) = v.wi otherwise . for v < v $al (4.1) In (4.1) E r Â— (J\ /dx is the longitudinal electric field (magnitude), (~ 10' cm/s) is the saturated drift velocity, and I'veff = /<Â»n/[l + 0Oc;5 VV )J where is the lowfield mobility, h is the fitting parameter which defines the transverseÂ— field dependence, and 1 T = Vfb + 2 \&b \ + IobII 172 or (4.2) is the threshold voltage. For strong inversion and negligible shortchannel effects, the quasistatic channel current is described by solving for E, in I ch = W xV QÂ„ (TH is the device
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68 width and QÂ„ is the channel charge density) and integrating it from source (.r = 0) to drain (r = Z): l rh ^ :l l n< f f V idneff/t'satL) I r ft] ( C or where 1 r /, is the channel voltage capacitance, [Ql\L)Qj;(0)] (4.3) < ^ ro P Â• The body depletion C d i\?b\ \ a Wd\\ V Vch ) (4.4) is assumed to be invariant along the channel to obtain a firstorder characterization of the depletion charge Q d in terms of the voltage ( (~ Y r , t .v/L) along the channel. In (4.3), Q n (L) = C' ox [I as Â— VtV ch ( 1 + C\i/ C or )] (4.5) and Qn (0) = Â— CÂ‘ or (I GS Â— I'r) Â• (4 6) Combining (4.3) (4. 6), we get the channel currentvoltage characteristic in the triode region of operation: I rh W:l'vrff 2L l 1 + {t'n f ff/2r, (ll L) r f/l J (h [2CÂ„ r ( \ GS Vt)(C 0T + 0 /( , ) 1 + 2/, 0,(1 \o B \\ where 0/o = \/^X. W?R Â• The effect of the channel dopingdensity gradient is reflected in (4.7) by when /, = 0, (4.7) simplifies to the conventional MOST expression. Note in (4.5) that 0/ is typically negative, and much larger in magnitude than CÂ„, . This unusual "depletion capacitance"
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69 ?/ > 0, simulates the added channel conductance due to the smaller depletion charge away from the source. As V DS increases, ]' rh increases, and ultimately the electron velocity saturates near the source (at c=0) as characterized by (4.1) . Then the saturation current is expressed as Ich{.iu1) ^ r I'sat^Ju (Â•*Â’ Â— 0) = N s l 'sa I C ox ( I as Vt) . (4.8) Unlike in the conventional MOST, the saturation current in (4.8) is independent of C\i and cannot be modeled by a channel pinchoff approximation. Combining (4.8) with (4.7) yields ^ rh{.mi) for a given V GS , above which I,. h = I c , . 4.2.2 Drift Region Depending on the VDMOST structure, the (quasi) saturation characteristics can be controlled by the drift region instead of the channel [Dar86] . Whereas the channel model is applicable to both vertical and lateral DMOSTs, as well as to the IGBT, different driftregion models are needed for the VDMOST and the LDMOST . For the VDMOST in the normal mode, the PISCES simulations (Fig. 4.3) reveal that the drift region can be partitioned into three sections as shown in Figs 4.1 and 4.3 to simplify the analysis. The voltage drops in the sections, which are characterized semi numerically based on reasonable approximations for the carrier transport, are added to define
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70 n + Fig. 4.3 ^ SC ? S 7 simulated cu rrent flowlines (AI = 9 7xl0Â“ 6 A//,m) xn the VDMOST [Luc88] (Fnc = 50 V 1',. . in dkft n ?ea?on 9 ^ pM>U Sigio^ Tilled ZFrZS? rssxrs i s 0 indicated on tL // m.
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71 the composite quasitwodimensional model. In section A, excess electrons supplied through the channel (for V GS > \j) accumulate to support the negative gradient of the vertical electric field for ] ns > 0 [Dar86] . These excess electrons, which accumulate even before the drift velocity saturates, produce SCL current. The underlying Poisson equation is complex, but can be solved analytically to give an implicit characterization of the voltage drop across the region. In section B, the electron current spreads laterally with an angle n (~ 45Â°) which can be assumed, in accord with the PISCES simulations, to be independent of the bias condition and the structural geometry [Huc84]. The boundary locations are defined by the depletion region of the pbody junction, which varies with the voltage drop across section A. The region is assumed to be quasineutral (// ~ N D ) . Section C is also neutral but has a constant crosssection. The (moving) boundary between sections B and C is also controlled by the depletionregion width of the pbody junction. Conventional MOST models, which do not account for SCL current, underestimate the drain current. Our simulations show that this underestimation can be quite significant at high Y J)S . In each section, the drain current is generally expressed using a continuous version of (4.1) : n ii it 1 + EJE C In = A y qn for Ey > 0 (4.9)
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72 where Ec = r aai /n nd and //,Â„< is the lowfield electron mobility. Combining (4.9) with Poisson's equation in one (vertical) dimension yields In (4.9) and (4.10), A v is the crosssectional area at depth U and E,, = dV/dy is the magnitude of the (vertical) electric field. In section A, Ay(=W z L,i) is assumed to be constant. This assumption is based on the PISCES simulations, which reveal a slight JFET effect in section A at low V us but show it compensated at higher ] due to predominant excess electrons [Dar86] . Equation (4.10) is solved analytically by extending the analysis in [Lam70] (which does not account for velocity saturation) to yield expressions for the position y and the voltage 1 at y in terms of E u . The nonlinear y(E v ) and V(EÂ„) expressions then implicitly give the section voltage drop. which requires numerical solution; U' 7 is defined in Fig. 4.1 and TT (/ is the depletion region width of the bodydrift junction. Note that the depletionregion width depends on E u is everywhere increasing with .?/, so the velocity of the electrons increases along the vertical direction from the surface. However the excess electron density decreases with (4.10) I (y Â— IT j + IT ,( ) = . (4.11) 0Â’i + l>*), the effective reverse bias on the pbody junction.
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73 increasing y because the gradient of Â£Â„ becomes smaller. In our analysis, we neglected the diffusion component of current, which is confirmed to be negligible by both PISCES simulations and analytic solutions. In sections B and C, n ~ i\ d . (The error resulting from the quasineutrality assumption is insignificant; results of accurate analytic solutions show little difference with those obtained using the approximation.) With A Â„ = TT[L,i + (y \Yj ]V,i)rota] in section B and constant in section C, (4.9) is solved for E v , and the result is integrated over the thicknesses of sections B and C to obtain Vb + Vc [d l J ( 1 N Dl'nd cot O + Ip M ( Ld + L p )qNi)liÂ„,i (L,i + L t , ) Â— Ip/Er W.qNDfivdLdI d/E c Ip/Er _ Lptano). (4.12) The geometric parameters in (4.12) are defined in Fig. 4.1. Note that current continuity is effected in section B by the electron velocity decreasing with increasing crosssectional area. This occurs within the realm of the quasineutrality condition . Now the total driftregion voltage drop of the VDMOST is ^ drift Â— l .1 + 1 B + Ec (4.13) For a given current I u , which equals /,,, from the channelregion analysis, (4.13) must be solved numerically because of the implicit nature of in (4 . 9) (4 . 11) . The NewtonRaphson iterative method is used (in the model routine) to
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74 solve these equations. Note that the voltage drop in the accumulation layer under the extended gate, which varies inversely with \\;s, has been neglected in (4.13). 4.2.3 Parasitic BJT The parasitic npn BJT in the nchannel VDMOST, (upmode) activated in the PISCES simulations of Fig. 4.4, plays an important role in both normaland reversemode operations. In the normal mode, where a positive voltage is applied to the drain, the npn BJT near the channel (downmode: see Fig. 4.4) can be activated either statically (by impactionization current) or dynamically (by displacement or charging current) due to the pbody voltage drop. (in typical devices, this voltage drop is minimized by using a deep p + body diffusion to reduce the body resistance R p0 .) m the reverse mode, where a negative voltage is applied to the drain (which could happen during transient switching of the VDMOST in an HVIC) , the BJT near the body contact (upmode: see Fig. 4.4) becomes an essential part of the VDMOST operation . The reverse recovery is very slow due to large stored charge in the drift region (where high injection prevails) , and can sometimes drive the BJT to saturation, which would lengthen the recovery and could possibly lead to destructive breakdown [Bal87] . The npn BJT is modeled following conventional bipolar transistor analysis for the normal mode, and accounting for highlevel injection in the drift region for the reverse
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75 Upmode BJT Downmode BJT Fig. 4.4 PISCES simulated current flowlines (A/ = 2.4xl0 3 th u3 f eve f se mod e operation of the VDMOST [Luc 8 8 ] , which show the activation of the upmode BJT { \ DS = 2.0 V, V as = 0 V). The regions functioning as the emitter and collector of^oth the upmode and downmode BJTs are indicated. On the .iÂ— and //Â—axes, 1 division = 1.0 //m.
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76 mode. The base transport current is characterized in terms of the internal junction voltages : Ict IcCi)C*'P ( 1 BEn/] T ) Â— lEC'0?rp(2VBCn/VT) (4.14) where two different saturation currents are used because the BJT action takes place at different locations depending on the mode of operation. In the reverse mode of the VDMOST, the bodydrift region junction is forwardbiased (Vue, > 0) predominantly near the body contact; and I ecu in (4.14) is relevant. In the normal mode, the sourcebody junction can be forwardbiased {V Bt:n > 0), predominantly near the channel, due to the lateral voltage drop across the body resistance; and /cco in (4.14) is relevant. We neglect the BJT base current for the latter case. For the reverse mode, it is defined predominantly by the hole transport in the drift region. The transport mechanism in the drift region, where highlevel injection occurs in the reverse mode, is characterized by the ambipolar transport equation. For p ~ Â„, the solution [Fos88] is P(y) = [or, !I)/La\ + p(W,)*h,h \(y W,)/L ,1 (4.15) sink [(IF, T Vj)/L A ] where L A = ^D a tÂ„ is the ambipolar diffusion length, D A is the ambipolar diffuaivity, and rÂ„ is the highinjection carrier lifetime. The boundary carrier densities are ;><"Â•,)= (nl/ND)c.r P iV ttÂ€n /V T) an d p(ir,) = X D(r ,,(V Jn .Â„ t /V r ) where iS the volta ge drop across the lowhigh junction at the
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77 drain, which is solved from the following boundary conditions. The hole and electron current expressions are combined to give two boundary conditions, neglecting recombination in the pbody and n + drain regions: /Â„({/ = TT>) ~ I CT and I p (y = TT',) ~ 0 [McD85] . For given \ BEn and I oCnr these boundary conditions are solved to give p(Wj) and ;>(!!',) in (4.15). Then, the reversemode base current is where Q P is the hole charge stored in the drift region: u , Qp = (Tr,). The VDMOST charge dynamics are defined predominantly by Qp in (4.17) in the reverse mode. In the normal mode, the bodydrift region junction depletion charge. Ibr = Qp/ry (4.16) (4.18) Q.J qW z L v X D \Y d . (4.19)
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78 is significant, as well as charge associated with the gate discussed in the next section. 4.3 SPICE Model Based on the analysis of the VDMOST in Section 4.2, we propose a physical semi numerical SPICE model, the basis of which is ^ DS ^ ch ^ drift Â• (4.20) where V is given either by (4.13) or (4.18) depending on the mode of operation. The complete network representation of the new SPICE model is shown in Fig. 4.5. The model is not a simple equivalent circuit. The elements shown represent physical components of current and voltage in the VDMOST, described implicitly by the analysis, which requires numerical solution. Note in Fig. 4.5 that V BEn (the voltage drop across the pbody resistance R, )R ) and V BCn (= Y ch ), which control I CT and I BB , are defined in accordance with the analysis of the parasitic BJT . The transient behavior of the device is simulated using both the quasistatic currents/voltages and charging currents (IQ /dt. The charges within the device are expressed in terms of node voltages as described in Section 4.2, and the transient charging currents are represented by the timederivative of the charges, using the quasistatic approximation: <]Qi_ v ' bVj (It (It (4.21)
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79 Gate Body/Source Cfls T oh (P Â© VBEn + Â— vw^PB v BCnÂ©I B R Â©dQp/dt Â©dQj/dt dQoD dt Â“V oh + Olci 0 + v drift Drain 1 Fig. 4.5 Network representation of the chargebased VDMOST model .
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80 where i = P, ./, and GD and j = GS, rh , BEn. Included in (4.21) is the DMOST gatedrain charging current dQ^o/dt. This current arises from the charge near the surface of the drift region under the gate electrode and is important in the switching performance of the VDMOST . The associated gate charge Qgq is characterized by basic MOS theory for two different modes of operation. Whenlcslrfc Â— VfB > 0/ the surface is accumulated with electrons, and Q cw ~ L ( ,W z C'ox ( Vas ~ Kh ~ V FW ) with the approximation that the surface potential i.'s ~ 0. When t as ~ ^ ch ~ ^FB < 0, only depletion charge can exist under the gate electrode due to the usual highfrequency operation of the device. In this case, \qs Â— ^ ch ~ ^ FD Â— 'i'S + Qcw/C'or and Qg'D = ~ L,/]] s yj2(ieNj) ( Â—u's) define the charge. The effective gatedrain capacitance associated with Â•IQcn/M is amplified by the Miller effect into an equivalent input gate capacitance, thus slowing down the gatecontrolled switching. Furthermore, (IQgd/^G with gatecircuit resistance can cause dV/dtinduced turnon [Bal87] . When V DS is abruptly increased while 1 as < 1 Tr the charging current through the gate resistance can increase the gate potential above V T , thus turning on the VDMOST. Also included in the model is Ca s' , the gatesource capacitance, the most significant component of which is that due to gate electrode overlapping the n + Â— source. All of the elements in the model are implemented in SPICE2 via userdefined controlled sources (UDCSs) , which are
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81 FORTRAN subroutines in SLICE [Har84] , an enhanced version of SPICE2. Each UDCS accesses the VDMOST model routine, which is flowcharted in Fig. 4.6. The model routine numerically solves, usincf the Newt on Â— Raphson iteration method, the implicit system of quasistatic equations developed in Section 4.2. The UDCSs, for a given NewtonRaphson iterate on V GS . V ch , and V BE Â„ in the SPICE2 nodal analysis, provide the element currents, or voltage for and the needed partial derivatives with respect to the node voltages . The derivatives are calculated via difference equations, based on multiple calls of the model routine. In the chargingcurrent UDCSs, backward Euler method for numerical integration is used to get best numerical stability. The seminumerical VDMOST model, implemented in SPICE, provides then a twolevel Newton method for device/circuit simulation. Note that the model, once finalized, can be written directly into the SPICE2 source code by modifying the algorithm in Fig. 4.6 to accept the device terminal voltages as input from the circuit nodal analysis . The negative resistance often observed in I, )S V ns measurements of the VDMOST is mainly due to the local heating of the device. When } ' Ds is increased for a given \ GS in the saturation region, the local power dissipation elevates the device temperature, and concomitantly reduces the carrier mobility as well as the saturation velocity; hence I DS decreases. If the duty cycle for the pulsedmode
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82 Given V GS ,V ch ,and V BEn T a =^=300Â° Y Normal Mode Calcula ' e * ch Calculate I qp N Reverse Mode Assume \?=\ Calculate (^partitioning) X Solve for using NewtonÂ— Raphson bs1 ch^ 1 CT _I BR ^DS~^ch~V drift T j =T a +R th v DS I DS STOP Semi numerical VDMOST modelroutine flowchart. Both norma 1 and reversemode paths are shown within the outer iteration loop for local heating Fig. 4.6
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83 measurements is reduced, less heating occurs and consequently the negative slope in the I D $ Â— ]' DS characteristics tends to be eliminated. To account for this effect for general DMOST/HVIC simulation, we implement the concept of thermal resistance in the SPICE model. The device junction temperature (T ; ) is different from the ambient temperature ( T a ) as follows: Tj = T a + n, I, \ dsIds ( 4 . 22 ) where R lh is the thermal resistance of the device. Empirical relationships between mobility and saturation velocity and temperature [Mul77] are used to implement ( 4 . 22 ) in parameters I 1 ""' l 1 Â”*' and v Â™t Â• Thi s implementation (which does not include the BJT temperature dependence) requires another iterative solution around the basis model routine as shown in Fig. 4 . 6 . It can be superseded if local heating is negligible. 4 Â• 4 Model Verification Test VDMOSTs are fabricated at AT&T Bell Laboratories using the dielectric isolation (DI) BCDMOS technology [Luc88] . Our initial measurements were done using a very low duty cycle (1%) to avoid the negativeresistance effect in the I us y l)s characteristics. The duty cycle is a critical parameter in the measurements as we note below in the discussion of localheating simulations . in Fig. 4 . 7 , measured dc I DS (V os . r cs ) data for two VDMOSTs having driftregion widths L,, are compared and
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IDS ca:i ids ca: 84 Fig. 4 .7 Simulated (curves) and measured (points) VDMOST currentvoitage characteristics for two different driftregion widths L,i .
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85 show good agreement with modelsimulated currentvoltage characteristics . The simulated characteristics were derived from SPICE with our new DMO ST model, using known structural device parameters and crudely extracted model parameters that fit the measured data. The channel length L is 2 /im. The device width TJ\ was taken as the sum of subcell widths and thus effectively accounts for the device layout. The key model parameters which determine the (channel) saturation characteristics are jV.iÂ„, and v snt in the channel region. Parameters A and rÂ„ (7 in the drift region are the key parameters for the quasisaturation characteristics. Quasisaturation, reflected by no dependence of the drain current on the gate bias and by high output conductance without the current saturation, is predominant for the L d = 4 /in device. In Fig. 4.8 we show SPICEsimulated transient characteristics of the VDMOST with an inductive load. As the gate voltage is dropped to turn off the device, the drain voltage Od.v) is abruptly increased above the offstate blocking voltage due to the negative voltage drop across the inductor (Li) ' Due to this ^ ick Crease of V DS , the charging current of the depletion region of the bodydrift region junction (dQ. l /(It) flowing through R llB produces a voltage drop V Bh Â„, which can turn on the downmode npn BJT. In addition to Lf , the load resistance R L also affects the turnoff time. As U L increases, dQj/df slows down due to small drain current; thus the turnoff time is increased.
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CAD G)A 86 time CqqcD xlO Â” 7 Simulated inductive turnoff transients for the L,i 10 /i m VDMOST . The inductor (Li = 5 //H) in series with R L _ (= 250 12) is connected to the drain from the blocking voltage source {Y^ = 20 V), and \c;s is pulsed as indicated. The simulated 1 ' Ds ( / ) and _ \nEn(t), the voltage drop across the pbodv resistance, are shown. J Fig. 4.8
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87 Simulated reverserecovery characteristics of the VDMOST is shown in Fig. 4.9. Initially the device is in the reverse mode, in which the upmode BJT is activated and a high concentration of carriers (holes and electrons) is stored in the drift region. Therefore the reverse recovery is slow, controlled by the carrier lifetime ( 77 / = 0.2 //.s) in the drift region. The device is then switched from the reverse mode to the normal blocking mode. For R pB = 0, the simulation shows about a 0.1 B s delay. But for R )tB = 2.5 ohm, the downmode BJT is turned on by the voltage drop across R j)B {\/dt\n pH > 0.7V) 1 the delay is longer ( 0.2 /is). For larger n v n = 10 ohm, the BJT becomes heavily saturated, and the VDMOST does not turnoff for times up to 1 /is. It will eventually turn off unless destructive breakdown occurs. Figure 4.10 shows Ids Â— Vds characteristics of the VDMOST measured with a higher duty cycle ( 3 %) , which show localheating effects. The simulated characteristics, also shown ^n the figure, were fitted to the measurements by varying the parameter R lh in (4.22). As V GS and I DS increase, the local heating becomes more severe and the negative resistance becomes more predominant as indicated by the measurements and predicted by the simulations. Note that R, h tends to be higher for DI devices than for junctionisolated devices.
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IDS Ct) CA] 88 time Cocao!) xlOÂ“Â° Fig. 4.9 Simulated reverserecovery current transients for the L,i = 10 / im VDMOST with different pbody resistances. The drainsource voltage, applied through a 10ft series resistor, changes from Â—5 V to +4 V with a 0 . l/,s rise time starting at 0.1 // s.
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cvn sai 89 vds cv: Fig. 4.10 Simulated (curves) and measured (points) VDMOST currentvoltage characteristics which show localheating effects. The duty cycle used in the measurements is 3% and the extracted thermal resistance /?,/, is 0.5.
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90 4 . 5 Summary The VDMOST model developed herein is useful for HVIC CAD, which requires reliable physical device/circuit simulation. Some of the modeling is applicable to LDMOSTs as well. The chargebased models are quasistatic; nonquasistatic (NQS) effects, which can be significant in HVICs, could be accounted for via physicsbased extensions [Fos88] . Comprehensive transientmodel verification based on device/circuit measurements would be required to ascertain the significance of NQS behavior. The models are seminumerical, an unavoidable trait of good physical models, but are implemented in SPICE. The UDCS implementation described is CPUintensive and is intended only for preliminary SPICE model verification. Indeed once the models are finalized, they can be written directly into SPICE source code, creating a seminumerical device/circuit simulator for MOS HVICs.
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CHAPTER 5 NEW PHYSICAL INSIGHTS AND MODELS FOR LDMOST IC CAD 5 . 1 Introduction This chapter presents a physical composite model for lateral DMOSTs (LDMOSTs) [Cla86] . The modeling methodology developed in previous chapters culminates in this chapter: the physical insights gained from PISCES simulations are used as a basis for developing the composite LDMOST model, in which the device is regionally partitioned into several onedimensional components, and carriertransport equations in each region are solved. The model is implemented in SPICE using FORTRAN subroutines and is supported by measurements. Device and circuit simulations show the superiority of the model over equivalentcircuit models. Highvoltage integrated circuits (HVICs) including LDMOSTs are now viable alternatives to hybrid circuits comprising discrete highvoltage devices. Optimal design of these HVICs requires physical LDMOST models implemented in a circuit simulator like SPICE. Equivalent(sub) circuit SPICE models for the highvoltage LDMOST [Wil87] have some utility, but are fundamentally deficient; they cannot simulate unique power device characteristics such as quasisaturation and reverserecovery transients. 91
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92 Several physical investigations of the onresistance of LDMOSTs [C 0 I 8 I, Men 86 , Poc76] have been done, but a complete physical model has not been reported. LDMOSTs in HVICs are subjected to unusual operating conditions, and hence robust models are needed. For example, an inductive load in power circuits will force the LDMOST into high current /voltage regimes where reverse current flow through the device may occur. Claessen and van der Zee [Cla 8 6 ] presented a model for the LDMOST covering the high current /voltage region. But their model is limited to dc conditions, and it does not account for quasisaturation nor the inherent BJT, which is commonly activated in HVICs. In this chapter we develop a new physical chargebased LDMOST model which accounts for the BJT. We study both the lightly dopeddrain (LDD) and the reducedsurfacefield (RESURF) nchannel LDMOST structures, using the twodimensional device simulator PISCES [Pin84] for guidance. The PISCES simulations provide new insights on normaland reversemode dc operation of the LDMOSTs and on the significance of the inherent npn BJT in transient reverserecovery characteristics. We emphasize the LDD LDMOST structure (see Fig. 5.1(a)), which we regionally partition into three components: the channel, the drift region, and the npn BJT. The composite model is implemented in SPICE for HVIC CAD. The modeling methodology is also applicable to the RESURF LDMOST structure (see Fig. 5.1(b)), and with our
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93 Fig. 5.1 Unitcell structure of (a) the RESURF LDMOST . LDD and (b) the
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94 physical VDMOST modeling in Chapter 4 defines LDMOST models for either technology. 5 . 2 New Insights By Numerical Simulations PISCES [Pin84 ] simulations have been done to gain physical insight regarding both the LDD and the RESURF LDMOST structures. This new insight facilitates the device modeling for circuit simulation described in the next section. PISCES is a twodimensional numerical semiconductor device simulator, for either dc steadystate or transient bias conditions. It solves the basic semiconductor device transport equations, using plausible physical models. For the LDD LDMOST, we used dopingdensity profiles and structural dimensions obtained from Siliconix, Inc. [Wil87] . The LDMOSTs were biased into both normal mode 0 DS ^ 0) and reverse mode 07xs < 0) in the dc simulations; the LDMOSTs were switched from the reverse mode into the normal mode in the transient reverserecovery simulation. 5.2.1 LDD LDMOST The self isolated LDD LDMOST is shown in Fig. 5.1(a). The channel region, which functions as a fast switch for the electron current flow, consists of two different regions: the doublediffused channel and the substrate channel. The doublediffused channel is nonuniformly doped by the difference of lateral diffusions between the pbody and the n + source. The
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95 substrate channel has constant doping density, defined by the substrate doping. PISCES simulations show that the electron velocity saturates near the source in the doublediffused channel, not near the drain as in conventional MOSFETs . We discussed this unusual behavior in Chapter 4 . The LDD (n _ Â— drift) region is used to block high voltages in the OFFstate without breaking down, but it also affects the currentvoltage characteristics in the ONstate. The simulated ONstate {\cs >^Tr ^ DS > 0) current flowlines shown in Fig. 5.2 indicate that the current is confined near the surface of the LDD region due to the LDD Â— substrate junction electric field. As 1 ps is increased, the junction depletion region widens, and hence reduces the effective crosssection of current flow ( JFET action) . At a critical V DSf for a specific V G s, the carriers (electrons) attain their maximum (saturated) drift velocity near the drain, and begin to accumulate to support incremental current . This electron accumulation counteracts the JFET action near the drain. The npn BJT inherent in the LDD LDMOST (see Fig. 5.1(a)) is activated when a (transient) reverse current flows through the LDMOST, as is forced by some powerswitching circuits, e.g., switching power supplies [Bal87] . The BJT causes a reverserecovery delay and a troublesome abrupt current change, which we discuss later. There are two different modes of operation of the BJT, depending on the bias conditions as discussed
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96 Fig. 5.2 PISCES simulated current flowlines (Al=4 OxlO' 6 A//,m) in the vicinity of the drift region of the LDD LDMOST (I'ps 16 V, 1 D , = 20 V, . The "unction depletion region is indicated by the dashed curves .
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97 in Chapter 4. To study the two modes, we have done PISCES simulations of the reverserecovery characteristics. For the transient simulations, ]'d S increases from Â— 5V to 5V through a load resistor in a finite rise time, with T > /s = OV (< } j ) . PISCES simulated reverserecovery characteristics is shown in Fig. 5.3. To indicate the activation of the two BJT modes, we have separated out three current components: Is(t), and I B (t) are the currents flowing into the n + drain, the n + Â— source, and the pbody, respectively. For 0 < / < 45 ns, Is(t) > 0, implying inversemode operation with the drainsubstrate junction forwardbiased. For 45 ns < / < 05 ns, Is(t) < 0, implying forwardmode operation with the sourcebody junction forwardbiased (near the channel) . with a negative voltage applied to the drain (source and body contacts are tied to ground) at / = 0 sec, all the junction (P _ P ' P n , and n~n + ) potential barriers are lowered such that conductivity modulation (highinjection) is prevalent in the p Â—substrate and n _ drift regions. A BJT action, with zero collectorbase voltage, supports the current: ~ Us + Id) = Â—{fll + 1 )IbFigure 5.4(a) shows PISCESsimulated current flowlines at t = 0 sec . It reveals the inversemode BJT action. About 75% of the total current (I n ) is collector current (I s ) , electrons flowing in the n + source. The rest of the total current is base current (I B ) , holes flowing in from the body contact to support the highinjection recombination in the substrate/drift region. High gain ( j,) of
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I(t) [A///m] 98 Fig. 5.3 PISCES simulated reverserecovery current tran^n? tS HÂ°^ the LDM0ST ^e drainsource voltage, ? L M v Â°^ 9 ^ <= 54 KS7Â— //m) , changes from 5 r arp , W h lth a 0 1 /'Â« rise t^e. I D (t), 7 S (/), and .J 1 f e the curr ents flowing into the n + drain, the n source, the pbody, respectively.
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99 Fig. 5 . 4 PISCESsimulated current flowlines (a) at / = 0 s in the reverserecovery transients in Fia 5 3 of the inversemode Bji (Al7.4xl0 A///m) and (b) at /= 50 ns, showino A/^mt CtlVati Â° n Â° f thS forwardmode BJT (Al=8.1xl0~^
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100 this inversemode transistor decreases the reverserecovery delay because there is less charge stored corresponding to a specific reverse current. Optimal design of the device would hence require a high gain for the inversemode BJT, but a low gain for, or suppression of the forwardmode BJT (using the deep p + body diffusion), which we now discuss. The direction of /y(/) changes during the reverse recovery (at t ~ 7 ns in Fig. 5.3) due to the increased current (
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101 Since HVICs require high voltage/current operation of the LDMOST, impact ionization in the LDD region can be important. We briefly discuss this phenomenon. When the LDMOST operates at high drain bias, carriers (electrons) moving through the highfield LDD region acquire high enough kinetic energy to generate electronhole pairs via impact ionization. The generated electrons add to the drain current and generated holes are swept into the pbody region, increasing the body potential and thus activating the forwardmode npn B JT . Our PISCES simulations reveal that the impact ionization occurs in the LDD region, and not in the channel region. The impact ionization occurs first near the drain where the electric field is highest and spreads toward the channel as Vds is increase d. Then both the LDD and substrate regions are conductivitymodulated with electronhole plasma, which results in lower voltage drop across the device. This is the so called "latchback" effect [Huc82] . 5.2.2 RESURF LDMOST The RESURF LDMOST, shown in Fig. 5.1(b), is similar in structure to that of the LDD LDMOST with the exception of the driftregion design. The whole n'epi layer functions as a drift region, and its thickness and doping density are controlled to produce low surface electric field to provide high breakdown voltage [App79] . We discuss the n'drift region in the normal mode of operation and the npn B JT in the reverse
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102 mode of operation. The doublediffused channel is as same as that of the LDD LDMOST . Under normal operation, the reversebiased episubstrate junction has a depletion region which effectively reduces the crosssectional area of electron current flow, as in the JFET. At high currents, excess electrons accumulate in the drift region due to driftvelocity saturation (which was ignored [Cla86]>. The excess electrons produce spacechargelimited (SCL) current flow and modulate the episubstrate junction barrier, thus compensating for the widening of the depletion region. This quasisaturation is similar to that in the LDD LDMOST, but a main difference between the two versions of the LDMOST is the magnitude of onresistance; the RESURF LDMOST shows smaller onresistance due to the thicker drift region. Figure 5.5(a) shows PISCESsimulated current flowlines in the RESURF device for normal ONstate operation. The gate voltage is biased very high to avoid channelcurrent saturation. The current flow in the drift region near the channel is controlled by the reversebiased episubstrate junction (JFET action) . Near the n*^irain, the crosssectional area of electron current is smaller due to larger reverse bias across the episubstrate junction, and " >' V Â° dUe t0 the ^riftvelocity saturation. This conductivity modulation compensates the JFET action. The inherent npn BJT in the RESURF LDMOST is slightly different from that in the LDD LDMOST (see Fig. 5.1). when
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103 Fig. 5 IT (a) (b) PISCES simulated current flowlines (a) in the normalmode operation of the RESURF LDMOST 6 ' ],)S=40Vf and ^I=7.8xl06 A/,,m) and (b) nT7 re y erse " mod e operation of the RESURF LDMOST (Ic.Â’SOV, \ ds=~ 0.8V, and Al=1.8xlQ6 A//>m) .
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104 a negative voltage is applied to the drain (source, body, and substrate contacts are shorted to ground) , inverseand forwardmode BJT action can be triggered, as in the LDD LDMOST. But the RESURF LDMOST has a vertical pin diode, which is like an extrinsic base. Furthermore, highinjection occurs in the p~Â— substrate where significant recombination occurs. Figure 5.5(b) shows PISCESsimulated current flowlines in the reversemode operation (V GS = 0 V, V DS = 0.8 V). There are three important current components in this mode: 1) the collector current flowing in the n + Â— source (/ s ~ 0.40 Id); 2) the recombination current flowing in the pbody (If), ~ 0.15 Ip) / 3) the recombination current flowing in the p~Â— substrate {I lie Â— 0.45 Id) Â• The ratio of two base recombination currents (Ilii/Ilie) varies depending on the device structure. For example, a thick substrate reduces /g f . The reverserecovery characteristic of the RESURF LDMOST is similar to that of the LDD LDMOST, but it exhibits a longer delay for the same carrier lifetime. This is due to the additional charge stored in the vertical pin diode, i.e., in both the epi and substrate regions . 5 . 3 LDMOST Model Based on physical insights gained from the simulations discussed in Section 5.2, we model the LDMOST regionally partitioning it into three main components: the channel, the drift region, and the inherent BJT. We describe a physical
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105 composite model for the LDD nchannel LDMOST, which is implemented in SPICE and hence has utility for HVIC CAD. The modeling methodology is also applicable to the RESURF LDMOST . 5.3.1 LDMOST Channel The LDD LDMOST channel is modeled based on the VDMOST channel model in Chapter 4 , but expanded to account for the extended channel over the substrate as illustrated in Fig. 5.1(a). We thus approximate the channel doping density as i\ A % N Ai) exp( ifx/Li ) 0 < r < L x = Nas Li < r < L\ + L> ( 5 . 1 ) where L\ and Z 2 are the doublediffused and substrate channel lengths. We use a piecewisecontinuous electron velocity model : PneffEr 1 + [PneffE r /2v s Â„i) ~ l' sat for v < othtnvisf (5.2) where E x c/T /dx\ is the longitudinal electric field, (as lO'cm/s) is the saturation velocity, /i nrff = Pao/[l + 0(VasV T )] where is the lowfield mobility, and 0 is the fitting parameter which defines the transversefield dependence .
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106 Following the methodology used in Chapter 4, we describe the stronginversion channel current by integrating I rh = N'VÂ’Qn from r = 0 to Ij + L>: ^ zUntf f 2(1] +L 2 ) [1 + (untff/ 2r sa( (Li + L,)) T' r/ ,] Qt(L\) Â— Qj ( 0 ) ( Qi[L { +L,)Qi(Lx) Cox 4* Crfi C or "I C/,i where V ck is the total channel voltage drop, and (5.3) r (,c ^ 1 1 m <d l = Â— jjy(;r = 0 ) Â« . i ^Â« 1/2 1 3'/ o/j r, and r t1Qd t t 'IfX.AS 4 \ D \ 1/2 (5.4) (5.5) are the body depletion "capacitances" for the doubledif fused and substrate channels, respectively. In (5.4), Tj is the doublediffused channel voltage drop, which is defined by equating the following two equations for channel current obtained from integrations along the respective channels: W zlhie f f /fit Â— Ch = Qi(Li)QUO) L\ [l +  ) ( j] 2 ( C or + C ) Qj(L i +Â£ > )Q;,(L\ Li [l 4(//Â„ f / / /2v s ,uL >) 0 ch Â— (  )] 2 (C' 0 . F + C ',/2 In this formalism, (5.6) (5.7) Qn ( 0 ) Â— ~C 0 r ( 1 QS Â— 1 7 Qn ( /1 ) Â— Â—Cor 1 f/s 1 r 1 1 ( 1 477 C C or (5.8) (5.9) Qn (Â£1 4L >) = Â—C 0 r GS r r r,(i + Â£ kL)_ ( ,4 r ,/i + ^ ^ o.r Co, (5.10)
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107 and the threshold voltage V T is defined by the doping density at the source as in Chapter 4 : \/46)>
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108 P Fig. 5 .6 Magnified view of the LDD region showing the Gaussian volume (thick solid lines) .
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109 I LDD < lu)P(Mt) In this case, E r is not high to cause velocity saturation. Hence the carrier density does not exceed the doping density Nfj, and the LDD region (only section A exists) is described by conventional JFET theory [Sze81] . The drain current is expressed, using a continuous electron velocityfield function, as 1 1 ,DD = 11 % [llj yd ( Â•<Â’ )] qXo I 1 ml 'E r 1 + Er/E r (5.13) where yj is the metallurgical LDD junction depth, y,i(.r) is the extent of the junction depletion region into the LDD at .Â»Â•, /'Â»(/ is the lowfield electron mobility, and E r = r.Â„, ////Â„, / . Integrating (5.13), we get the relationship between the drain current and the LDD region voltage drop Vldd : I LDD = (i + fe) 2e jS AS <1^ u ( Nas + , 1 LDD + 1 bi ) ,/2 1 Â’b/' (5.14) which, for a given IujDr is solved analytically for Yldd Note from (5.13) that hDD(sai) = IV, [f)j !J,I (L,i)]qX D c s , lt (5.15) where )/,/(Â£,/) is given by the depletion approximation and ^ LDU{$at)r which follows from equating (5.15) to (5.14).
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110 I LDP > hpp( sal) In this current range, the LDD region is subdivided into two sections, A and B, since the electron velocity saturates near the drain. In section A, electrons move by the fielddependent velocity, but in section B by the saturation velocity. At the boundary r = L.\ between these two sections, the drain current is, from (5.13), I LDD = ITÂ’, [yj yj (L . 4 )] qN/jr,,,, where ij,i(L a ) depends on the voltage V A at v = L \ through the depletion approximation. This current expression yields h.pp V ( 1^p ( Has + ftp ) 'a = [yjr. bt (5.16) H pl'sat ) 2ei\ where i3 the sxabstrate doping density used in ( 5 . 1 ). With (5.16), the JFET theory applied to section A defines the section A length, L A . In section B, we apply Gauss's theorem to a volume enclosed by planes of unit width (see thick solid lines of Fig. 5.6) : fh Hj r !lj 6 I EjdV + f I ( Â—Ea )
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Ill position y. All of these assumptions concerning the electric field are consistent with PISCES simulations. Differentiating both sides of (5.17) with respect to x gives TÂ” f Ej njj = ( i lX uyj + Qn = <1 X 'DIJ) hup H : I'.itit (5.18) This equation is integrated twice to give the section B voltage drop ' 7j = ( L,i L \ )~ '2eyj]V z r slll (Ildd IT f Â«yi\ pijjVsai + f E j 1 1 ) f ( L,i Â— ) E, . (5.19) Now the complete LDDregion voltage drop is X LDD = X A + X B < (5.20) where, for a given IldDi 1 .1 and 1# are characterized by (5.16) and (5.19). The equations constitute the LDDregion model. Because Ej in (5.19) depends on YldDi equations require iterative numerical solution, which is done within the model routine implemented in SPICE (see Section 5.4). 5.3.3 npn BJT The inherent npn BJT of the LDD LDMOST is modeled based on physical insights from Section 5.2 and on our VDMOST BJT model in Chapter 4 . Because most of the BJT current flows through the p Â—substrate as shown in Fig. 5.4(a), the onedimensional
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112 n + Â— pp~Â— n + structure, shown in Fig. 5.7, is representative of the basic device operation. As discussed in Section 5.2, the BJT can possibly operate in the forward mode, where the sourcebody (n + Â— p) junction is forwardbiased, or in the inverse mode, where the drainsubstrate (n + Â— p~) junction is forwardbiased. In the latter case, carriers (electrons) are hardly injected through the LDDsubstrate (n~Â— p _ ) junction due to the voltage drop (debiasing) across the LDD region. The integral chargecontrol relation (ICCR) is applied only to the pbody base region to obtain the base transport current. Actually there is a composite base region for the npn BJT, comprising the pbody base and the p Â— substrate base. But we focus on the pbody base where J p ~ 0; the predominant hole current flows vertically through the bodysubstrate junction under the body contact, removed from the intrinsic pbody base, as shown in Fig. 5.4(a). The ICCR in the quasineutral pbody base region, for low injection, gives gD" [Â» (r Fp ) p (r Ep ) n ()Â•/?,,) p (.vr,,)] t b>. f N a ( .r ) )/> (Â•'Â•Â£>) = "hrp(VuEn/V T ) (5.22) and n (*B P )p (* b p ) p 1 ( n I,,) Â— ^ as (X P (2Vj pp /V t ) (5.23)
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113 Fig. 5.7 The onedimensional n + ppn + transistor of the LDD LDMOST.
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114 The junction voltages and boundaries in (5 . 21) (5 . 23) are defined in Fig. 5.7. High injection was assumed in the p~Â— substrate (p~n>N AS ) to derive (5.23). Combining these equations yields the net pbase transport current, r A'~) = ("i/x \s) f.rp(V Jp n + /Y r ) . (5.27)
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115 The boundary current conditions are h UÂ‘Bi>~) Â— ~h'T (5.28) and I P (scp) 0 (5.29) where we assume negligible recombination in the n + Â— drain region. Equations (5 . 26) (5 . 29) define n (. v Bp ~) and Â» (.r C/ ,) for given \ bEh and Yj pp [McD85] . Now the recombination current for inversemode operation is given by where 77 / is the (highinjection) carrier lifetime in the p~Â— substrate . The substrateregion voltage drop is significant for inversemode BJT operation. It is characterized by integrating the electric field in the substrate, derived from the ambipolartransport analysis [McD85] , and by adding r, + ; Note here that the two bases (body and substrate) are linked by (5.24) and (5.28); I cr is controlled by Yj pp and Ibi is a function of I CT . Thus for specified junction voltages (5.30) (5.31) ^BEh and Y Jpp r the above formalism analytically describes the pertinent BJT characteristics, i.e., I CT , I B j f and Y, lth .
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116 5 . 4 SPICE Simulations And Discussion The physical, seminumerical composite model for the LDD LDMOST described in Section 5.3 is implemented in SPICE. Figure 5.8 shows the network representation of the model, based on integration of the regional analysis with I,h = Ildi )Â• This is not a simple equivalentcircuit, but represents the physical chargebased model. All the elements in Fig. 5.8 are implemented in SPICE via userdefined controlled sources (UDCSs) which access the model routine that numerically solves the implicit system of equations developed in Section 5.3. UDCSs are FORTRAN subroutines in SLICE [Har84], an enhanced version of SPICE2 . The sources in the model network in Fig. 5.8 are voltagecontrolled current/voltage sources defined in terms of node voltagedifferences 1 qs > ^ r h > an d 1 z?irÂ» Â• The voltage source Y,i n fi represents ] ldd in normalmode operation of the LDMOST and Yaub in reversemode operation. The transient characteristics of the device are simulated by the chargingÂ— current UDCSs, ']Qi = v 0Q,'lYj ( It DYj (It (5.32) where i Â— P, ./, and j Â— GS, eh, DEn. This charge dynamics is based on the quasistatic approximation with the charges derived from the analysis in Section 5.3: Q, w n ( .r )
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117 Gate Fig. 5.8 Network representation of the LDD LDMOST model.
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118 with n (~ p) given by (5.25), is the hole charge stored in the p~Â— substrate for inversemode operation of the inherent BJT; with \ t qs = \\h + 1 LDDr is the LDDsubstrate junction depletion charge for normalmode operation of the LDMOST . (The excess electron charge in the LDD due to velocity saturation is negligible as discussed in Chapter 4 . ) Also included in the model is C'qsi the gatesource capacitance, the most significant component of which is that due to the gate electrode overlapping the n + Â— source. The charging currents are calculated numerically using finitedifference approximations for the voltagederivatives . These approximations are also used for the transcapacitances and transconductances needed for circuit nodal analysis. In the nodal analysis, SPICE calls the UDCSs iteratively, which in turn access the LDMOST model routine flowcharted (relative to Ildd\*<,i)) paths exist, both yielding the LDMOST solution with Vds = V c h + ^ LDD Â• In the reverse mode (T'y, < ()) , the BJT analysis is activated with 1 = Â— T *./, , yielding the BJT solution with V DS = Y Jpp . + V 9Kb . Test structures of LDD LDMOST s were fabricated using lateralchargecontrol technology at Siliconix, Inc. [Wil87] . (5.34) in Fig. 5.9. The model routine, given V (;Sf V ch , and Y IJEnl first determines the mode of operation by checking the sign of \ 0) , lowand highcurrent
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119 Fig. 5.9 The LDD LDMOST model flowchart .
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120 Figure 5.10 shows measured and simulated I ns ]' l)s characteristics for the LDD LDMOST . For the simulations, model parameters were crudely extracted to fit measured data without any optimization. Other parameters like geometry and doping density are given technologically. Quasisaturation, in which I DS is independent of V GS and the output conductance is high, is predicted in simulations for l'c;s = 8, 10, 12 V, m agreement with the measurements. The abrupt current transition from the triode region to the saturation region for the lowerVos simulations is due to the piecewisecontinuous electron velocity model in (5.2) In Fig. 5.11, we show measured and modelsimulated reverserecovery characteristics of the LDD LDMOST. When t < 100 us, the device, in reversemode operation (V DS < () V) where the inversemode BJT is activated, stores a high concentration of holes and electrons in the psubstrate and n'drift regions . At t = 100 ns, a voltage pulse (5 V to +4 V with 100ns rise time) is applied to the drainsource terminals through a resistor (152 ft) to switch the device from the reverseONstate to the normalOFFstate . Then the stored holes and electrons in the substrate/drift regions begin to diminish predominantly by chargingcurrent JQJJt, and by recombination current I Bl . The time delay from initiation of switching until the device recovers to a specified OFFstate is defined the "reverserecovery time". The reverserecovery time controlled by a) the rise time of the switching pulse; as is b)
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IDS [A] 121 IDSVDS VDS [V] 120.0 Fig. 5.10 Measured (small rectangles) and SPICEsimulated (curves) currentvoltage characteristics of the LDD LDMOST {L d = 42 //m) .
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IDS [mA] 122 Fig. time [sec] 5.11 Reverserecovery characteristics for the LDD LDMOST (L,i = 42 //m) : (a) measured (1 division on the xaxis = 100 ns and 1 division on the yaxis = 13.2 mA) ; (b) SPICEsimulated . The drainsource voltage, applied through Rj (= 152 Q) changes from 5 V to +4 V with a 100ns rise timi starting at t = 100 ns.
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123 T H ' and c ) RpBFast switching risetime, short 77 /, and small R pB reduce the reverserecovery time. In Fig. 5.11 the forwardmode BJT is not triggered because the induced ohmic voltage drop across R pB is not sufficient to forwardbias the sourcebody junction. Note that the measurement shows a long recovery tail due to stray capacitances on the probe station. However the storagetime simulation corresponds well with the measurement. Figure 5.12 shows our test circuit for transient simulations. This circuit, which is a basic building block for a variety of DMO ST applications, e.g., two quadrant chopper circuit, tests both normalÂ— and reversemode operations, including transient reverse recovery. Figure 5.13 shows results of transient simulations. Initially (t = 0 ) , V Ct S >V T ; so LDMOST1 is OFF and LDMOST2 is ON. As V GS goes to zero ( t = 0.15 /is) r LDMOST2 is turned off and I DSI decreases. Consequently, the current through L l , I Lr decreases and induces a voltage drop across L l . Then the voltage at node P, Y P , is greater than the supply voltage V Br and this voltage difference turns on the npn BJT (so called the integral diode) of LDM0ST1. when V GS increases again ( / = 0.25 //s) , the npn BJT of LDMOST1 should be turned off, but undergoes the reverse recovery, in a mean time LDMOST2 is turned on, but Iosi = lDSi(ON)+It{R\, where I RRx i s the reverserecovery current of LDMOST 1 , because I L ( = I 0 S 2 ~ I D s\ ) changes very little due to L l . This peak current occurs at an instant when V DS2 i s
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124 Fig. 5.12 Test circuit for the LDD LDMOST transients. R a 50 il, L l = 5 mH, R l = 250 12 , and V D = 20 V. '
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125 time [sec] Fig. 5.13 SPICE simulation results for the circuit in Fig. w Â• JL Z Â• i(0 [ mA l
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126 also high. This results in high power consumption which can induce second breakdown by the impactionization discussed in Section 5.3. //?/?] is higher when the turnon time of \r;s is shorter. In this case the second breakdown is more probable. The simulations shown in Figs. 5.11(b) and 5.13, which reveal effects of the inherent BJT in LDMOST circuits, demonstrate a capability of mixedmode device/circuit simulation. This feature of our physical model, which is not afforded by other equivalent(sub) circuit models, can be quite useful in computeraided optimal device/circuit design of HVICs . 5 . 5 Summary New physical insights with regard to two structures of LDMOSTs (LDD and RESURF LDMOSTs) have been obtained by using the twodimensional device simulator PISCES. These insights were used to develop a physical, semi numerical composite model for the LDD LDMOST. The modeling methodology is also applicable to the RESURF LDMOST. The chargebased model is implemented in SPICE via UDCSs and supported by measurements of test devices. Transient simulations for both normaland reversemode operations were demonstrated to show the superiority of our physical model over empirical equivalent(sub) circuit models for HVIC CAD. The developed physical SPICE model is useful for computeraided optimal design of LDMOSTs as well as of HVICs. Device and structural model parameters, e.g., t h , B,, Br and L, lf are
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127 adjusted to derive optimal device/circuit performance. For example, to satisfy the specified reverserecovery time, deep p +_ diffusion into the pbody is employed to reduce R v h, or the electron irradiation [Bal87] can be used to reduce 77 / . Then subsequent device/circuit simulations can be done directly to predict effects of the adjustments on performance.
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CHAPTER 6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK In this dissertation, new models for MOScontrolled HV devices (IGBTs and DMOSTs) have been developed and shown to be useful for optimal device/circuit CAD of HVICs . The unique features of HV devices such as latchup in the IGBT and quasisaturation in the DMOST were studied extensively using the twodimensional numerical device simulator PISCES. The physical insights gained from the numerical simulations and experimental measurements of test devices were used to develop our chargebased HV^levice models. The models were implemented in SPICE2 via FORTRAN subroutines (UDCSs) , by which the model equations are solved seminumerically within the nodal analysis framework of SPICE. Our new models were verified by measurements of specially designed test devices, using simulations with model parameters evaluated from device structural information and/or crudely extracted without any optimization to fit the measured data. Furthermore circuit simulations of HVICs were done to demonstrate the superiority of our model over equivalentcircuit models with regard to technology CAD . Based on the research discussed herein, we suggest the following topics for future research consideration. 128
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129 First, we recommend a study of optimum cell design of HV devices based on our modeling methodology. The HVdevice characteristics, e.g., ONresistance of the DMOST and latchup of the IGBT, are strongly dependent on the (threedimensional) cell design: triangular, square, rectangular, hexagonal, circular, or parallelline structures. Threedimensional device simulations may be required to study the cell design. Our models effectively account for the device layout of HV devices; the device width is taken as the sum of subcell widths. Second, we recommend PISCES modifications to account for general terminal boundary conditions needed in HVdevice simulations. The HV devices with circuit or stray inductances loading the terminals cannot be simulated by PISCES. Third, we recommend the extension of our DMOS channel model for all regions of operation including the reverse channeldrive mode. During the transients of HVIC simulations, DMOSTs can operate in this reverse mode . Fourth, we recommend the development of a latchback model for the DMOSTs. As the DMOSTs in HVICs are subjected to unusual high current /voltage operating regimes due to inductive loads, latchback can be an important phenomenon. Fifth, we recommend the implementation of our models directly into SPICE source code. The UDCS implementation which we have used is CPUintensive and is intended for
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130 preliminary SPICE model verification and not for practical CAD application of the models. The direct SPICE implementation requires the model routine to evaluate all the element values from the device terminal voltages, instead of the internal nodevoltage differences used in the UDCS implementation. The required modification in the modelroutine formalism however is straightforward. Sixth, we recommend overall model refinements, for example to account for parasitic effects in actual multicell devices and HVICs . In particular the gatedrain charging current .$Â•Â— ' dependence than that described by our Q (; D ( ( ' Ds ) .
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APPENDIX A BASE CHARGE PARTITIONING IN WIDEBASE BJT' S In this appendix we describe the base charge partitioning of the widebase p + Â— n~p BJT structure in the IGBTs discussed nonquasistatic behavior in bipolar transistors was defined [Foss86] for the simple case of low injection in a uniformly doped quasineutral base region with negligible recombination. These conditions imply no electric field and hence no drift current. For the charge partitioning in the IGBT, we must account for high injection, which implies an electric field and a drift component of current, and for recombination in the wide base of the constituent lateral pnp transistor. Following the derivation [Foss86] but accounting for these IGBT properties, we integrate the onedimensional hole continuity equation over the quasineutral base width TT to in Chapter 3 . A base charge partitioning to best represent derive II (A.l) o 131
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132 where rp is the highinjection carrier lifetime and Que is a part of the stored hole charge defined as H' Qbe = J <1^ (l jyr) p(x.t)dx ; (A. 2) o A is the device area. With regard to errors introduced by the quasistatic approximation, the most critical term in (A.l) is the transportcurrent integral which can convey significant nonquasistatic behavior. Thus the idea [Foss86] was to reorganize the continuity equation to make the transportcurrent term quasistatic, thereby minimizing the error introduced when the entire equation is characterized by the quasistatic approximation. For the highinjection case here, combining the hole and electron current expressions, with p ~ n, yields If(t) 1+6 qAD dp ' dr (A. 3) where h is the electronhole mobility ratio, D i is the ambipolar diffusivity, and I E represents at any point the sum of the hole and electron currents. If the effective base contact for this onedimensional transistor is assumed to be located near the basecollector junction, as is the case for the constituent pnp in the IGBT structure (see Fig. 3.1), then If: is spatially constant, as indicated in (A. 3), and it is in fact the emitter current of the transistor. Consequently, the transport current integral in (A.l), with (A. 3), is
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133 quasistatic; i.e., it is independent of the transient hole distribution in the quasineutral base and depends only on the boundary hole densities which are virtually quasistatic. Since the nonquasistatic nature of the recombination term, Qbe/th, in (A.l) is of lesser significance, we can assume that (A.l) can be well approximated as being quasistatic. A similar, but reverse double integration of the hole continuity equation yields \v Â— Yp Ip (.v. f) dx + o Qbc TH + ''Qbc dt (A. 4) Qbc = j qA (^jpix.t)dir (A. 5) o is the other part of the stored hole charge. Note that Qbe + Qbc = Q B Â• By the same argument given above, (A. 4) can be assumed, to first order, to be quasistatic. Hence, (A.l) and (A. 4) , which characterize the hole transport in the quasineutral base region, define a partitioning of the total base charge Q H between the emitter and collector of the transistor. This partition, which defines how the emitter and collector share in the discharging of the base, gives a firstorder accounting for nonquasistatic behavior due to the finite carrier transit time in the base [Foss86] .
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134 To incorporate the charge partitioning into the transient network model for the transistor and the IGBT, we recognize that the steadystate component of base current, Ib Qbe Qbc T H T H + In e (A. 6) where I\p is the back injection of electrons into the emitter, must flow between the emitter and base terminals. Thus (A.l) and (A. 4) imply that 11 Ic = [ Ip ( x. i ) dr Â— (A. . 7 ) ' ' ./ TH I) = If Ib and that the partitioned chargebased model for the pnp transistor should be represented in the IGBT model as shown in Fig. 3.9, where Ip and I c are defined [Fos88] via the quasistatic approximation and the ambipolar transport analysis. This analysis [Fos88], which gives p(.v.t) = p((),t) silih [(TT .r)/L,\Y sivh ( \V/L i ) (A. 8) where La is the ambipolar diffusion length, also defines the c I uas i~static partitioned charges Qyp and Q hc . Inserting (A. 8) into (A. 2) and (A. 5), with some mathematical manipulation, yields Qbe(^) = qAp(OJ) I i ^ (2/3 )Q g (A. 9)
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135 and Q BC (t) = qAp(0.t)L A 'La , /irv 1 'sch ( Â— ) tr U,t/J Â— ( 1 / 3 ) Qu . (A. 10) The time dependences of and Qbc are defined by the time dependences of the emitterbase and basecollector voltages which control />(()./) and II' [Fos88]. The numerical approximations in (A. 9) and (A. 10) follow from the corresponding expression for Q B and the fact that typically L \ is greater than IT'/ 4 in IGBTs .
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APPENDIX B MODEL IMPLEMENTATION IN SPICE VIA UDCS'S In this appendix we overview the SPICE implementation of the composite LDMOST model developed in Chapter 5. All of the elements in the network representation of the LDMOST model shown in Fig. 5.8 are implemented in SPICE via userdefined controlled sources (UDCSs) , which are FORTRAN subroutines in SLICE [Har84], an enhanced version of SPICE2. UDCSs (UUID, UUVEP, UUIBR, UUICT, UUQP, UUQJC in the following sourcecode listing) access the differentiation routine DEFF to calculate the element values, transconductances, and transcapacitances needed for circuit nodal analysis. The subroutine DEFF calculates the derivatives via difference equations based on multiple calls of the model routine DMT (flowcharted in Fig. 5.9). Finally, the subroutine DMT numerically solves the implicit system of equations in the model using a straight iteration method. The general theory behind the implementation of UDCS network models in SLICE is discussed in the SLICE Manual Rev. 4.08 [Har84] and Veeraraghavan et al . [Vee86] . The FORTRAN source code, which details each UDCS and model routine for the LDD LDMOST model shown in Fig. 5.8, is listed on the following pages. 136
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137 c ************************************************************ c* SPICE2 Userdefined controlledsource subroutine for the * c* channel current in the LDD LDMOST by Y.S. Kim 3/1/90. * 0************************************************************ c* * c* Return 'y' as value of source if 'iflag'=0, or as value * c* of 'iflag'th component of gradient of source if * c* 'iflag'>0. * c* * c* Perform onetime initialization of error checking if * c* 'iflag'=l. * c* * c* Optionally return 'j error ' as integer in the range * Â» c* 1..9999 to cause SPICE2 to print an error message * c* containing the value of 'jerror', or in the range (1).. * c* (9999) to cause SPICE2 to print an error message and * c* halt execution, the values outside these ranges are * c* reserved for use by SPICE2 . * c* * c* No other argument or variables should be changed, except * c* variables added by the user. * c* * c* Description of input arguments: * c* * c* LP pointer to settable parameters * c* NP number of settable parameters (use is optional) * c* The settable parameters (if any, i. e. if np>0) are * c* referenced as x(lp+l) , x(lp+2) , ..., x(lp+np) . * c * * c* LC pointer to controlling arguments (voltages or * c* currents) * c* NC number of controlling arguments (use is optional) * c* The controlling arguments are referenced as * c* x ( lc+1 ) , x ( lc+2 ) , ..., x(lc+nc). * c* * c* The elements of both of the above lists must be in one* c* toone correspondence with the values specified on every * c* SPICE2 element card referencing this subroutine. * c* * c* The manual has errors: 'special common blank' line must * c* be deleted; 'implicit double precision' must be added; * c**************** *********************** ****** *************** subroutine UUID (y , if lag , lp , np ,1c, nc , j error) implicit double precision (ah,oz) common /blank/ x(64) common /parm/ z,xll,xl2,unch,xna,xnae,vsatch,und,xnd, &xld , vsatd , gqs , ta , xiccO , xiecO , rth , h , dum c ************************************************************ c *****lp= 7 s , np=18 , lc=96 , nc=3 z= x(lp+l) xll= x ( lp+2 ) xl2= x ( lp+3 ) unch= x ( lp+4 ) xna= x ( lp+5) xnae= x(lp+6) vsatch= x ( lp+7 ) und= x ( lp+8 )
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138 xnd= x ( lp+9 ) xld= x ( lp+10) vsatd= x ( lp+11 ) gqs= x ( lp+12 ) ta= x ( lp+13 ) xicc0= x ( lp+14 ) xiec0= x(lp+15) rth= x ( lp+16 ) h= x ( lp+17 ) dum= x ( lp+18 ) vg= x ( lc+1) vch= x(lc+2) vben= x(lc+3) c* *********************************************************** c*****if lag=l : error checking. c*****iflag= 0: evaluate y= (value of source). c*****iflag= 1: evaluate y=d(value of source) /dx (lc+1) . c*****ifiag= 2: evaluate y=d (value of source) /dx (lc+2 ) . c*****iflag= 3: evaluate y=d(value of source) /dx (lc+3 ) . goto (25,50,100,200,300) ,iflag +2 c* *********************************************************** c* perform onetime initialization or error checking * c* *********************************************************** 25 continue if (nc .ne. 3) jerror = 99010 goto 99901 c* *********************************************************** c* y=ID (channel current) * c* *********************************************************** 50 continue call DEFF (1, 0,y,vg, vch,vben) goto 99901 c* *********************************************************** c* y=dID/dVG * c* *********************************************************** 100 continue call DEFF (1,1, y , vg, vch, vben) goto 99901 c* *********************************************************** c* y=dID/dVch * c* *********************************************************** 200 continue call DEFF ( 1 , 2 , y , vg , vch, vben) goto 99901 C* *************************************************** * * + c* y=dID/dVBEn * c* *********************************************************** 300 continue y=0 goto 99901 c 99901 continue c return end
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139 c* ********************************************************** * c* SPICE2 Userdefined controlledsource subroutine for the * c* drift region voltage drop in the LDD LDMOST . * c* * c* Refer to the comment in UUID.f. * c************************************************************ subroutine UUVEP(y , if lag, lp, np, lc, nc, j error) implicit double precision (ah,oz) common /blank/ x(64) common /parm/ z,xll,xl2,unch,xna,xnae,vsatch,und,xnd, &xld , vsatd , gqs , ta , xiccO , xiecO , rth , h , dum c ************************************************************ c *****lp=78, np=18 , lc=96 , nc=3 z= x(lp+l) xll= x ( lp+2 ) xl2= x ( lp+3 ) unch= x ( lp+4 ) xna= x(lp+5) xnae= x(lp+6) vsatch= X ( lp+7 ) und= X ( lp+8 ) xnd= X ( lp+9 ) xld= X(lp+10) vsatd= x ( lp+ 11 ) gqs= x ( lp+12 ) ta= x ( lp+13 ) xicc0= x ( lp+14 ) xiec0= x ( 1 p+ 1 5 ) rth= x ( lp+16 ) h= x ( lp+17 ) dum= x ( lp+18 ) vg= x ( lc+1 ) vch= x(lc+2) vben= x ( lc+3 ) c***** ****** ******************* ****************************** c*****iflag=l : error checking. c*****if iag= 0: evaluate y= (value of source) . c*****ifiag= l: evaluate y=d(value of source)/dx(lc+l) . c*****ifiag= 2: evaluate y=d(value of source) /dx (lc+2 ) . c*****ifiag= 3: evaluate y=d(value of source) /dx ( lc+3 ) . goto (25,50,100,200,300) , if lag +2 c* *********************************************************** c* perform onetime initialization or error checking * c************************************************************ 25 continue if (nc .ne. 3) jerror = 99010 goto 99901 c************************************************************ c* y=Vepi (drift region voltage drop) * C****************************************** ************* ****)' 50 continue call DEFF (2,0 , y , vg, vch, vben) goto 99901 C* ************************************** * k * + * * * * * Â£Â£*Â£***Â£*** * c* y=dVepi/dVG * c ************************************************************
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140 100 continue call DEFF(2 , l,y,vg, vch, vben) goto 99901 C* ********* k *************** k * * It ****** k ************ k ******** k * c* y=dVepi/dVch * c ** ************************************* * ****** * * * * * * * * * * * * * * 200 continue call DEFF(2,2,y,vg,vch,vben) goto 99901 c************************************************************ c* y=dVepi/dVBEn * 0*********************************** ***************** ******** 300 continue call DEFF (2 , 3 ,y, vg, vch, vben) goto 99901 c 99901 continue c return end 0* *********************************************************** c* SPICE2 Userdefined controlledsource subroutine for the * c* reverse base current in the npn BJT of the LDD LDMOST. * c* * c* Refer to the comment in UUID.f. * 0* *********************************************************** subroutine UUIBR (y , if lag, lp , np , lc, nc , j error) implicit double precision (ah,oz) common /blank/ x(64) common /parm/ z,xll,xl2,unch,xna,xnae,vsatch,und,xnd, &xld , vsatd , gqs , ta , xiccO , xiecO , rth , h , dum c *************************************************** ******* ** C *****lp=78 , z= xll= xl2 = unch= xna= xnae= vsatch= und= xnd= xld= vsatd= gqs= ta= xicc0= xiec0= rth= np=18, lc=96 , x(lp+l) X ( lp+2 ) X ( lp+3 ) X ( lp+4 ) X ( lp+5 ) X ( lp+6 ) X ( lp+7 ) x ( lp+8 ) X ( lp+9 ) x(lp+10) x(lp+ll) x ( lp+12 ) x ( lp+13 ) x ( lp+14 ) x ( lp+15 ) x(lp+16) nc=3
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141 h= dum= vg= vch= vben= c************* c*****iflag=l c*****iflag= 0 c*****iflag= 1 c*****ifiag= 2 c*****iflag= 3 goto (25 c* *********** * c* perform one q* *********** * x ( lp+17 ) x ( lp+18 ) x ( lc+1) x(lc+2) x(lc+3) *********************************************** : error checking. : evaluate y= (value of source) . : evaluate y=d(value of source) /dx ( lc+1) . : evaluate y=d(value of source) /dx ( lc+2 ) . : evaluate y=d (value of source) /dx (lc+3 ) . ,50,100,200,300) ,iflag +2 *********************************************** time initialization or error checking * *********************************************** 25 continue if (nc .ne. 3) jerror = 99010 goto 99901 c * *********************************************************** c* y=lBR (reverse base current of npn TR) * c* *********************************************************** 50 continue call DEFF (3 , 0 , y , vg, vch, vben) goto 99901 c************************************************************ c* y=dIBR/dVG * c************************************************************ 100 continue call DEFF(3 , l,y,vg, vch, vben) goto 99901 c* *********************************************************** c* y=dIBR/dVch * c* *********************************************************** 200 continue call DEFF (3, 2, y,vg, vch, vben) goto 99901 C* ********************************************************** * c* y=dIBR/dVBEn * c* ********************************************************** * 300 continue call DEFF (3,3 ,y,vg, vch, vben) goto 99901 c 99901 continue c return end
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142 C* * * ic * * k * * * * * * * * * * * * * * * * * c* SPICE2 Userdefined controlledsource subroutine for the * c* collector current in the npn BJT of the LDD LDMOST. * c* * c* Refer to the comment in UUID.f. * C* * * * * * * * * * * * * k * * * * * * * * Â•* subroutine UUICT(y, iflag, lp,np, lc,nc, jerror) implicit double precision (ah,oz) common /blank/ x(64) common /parm/ z,xll,xl2,unch,xna,xnae,vsatch,und,xnd, &xld , vsatd , gqs , ta , xiccO , xiecO , rth , h , dum c* *********************************************************** c *****lp=7 8 , np=18 , lc=96, nc=3 z= x(lp+l) xll= x(lp+2) xl2= X ( lp+3 ) unch= x ( lp+4 ) xna= x(lp+5) xnae= x ( lp+6) vsatch= x ( lp+7 ) und= x ( lp+8 ) xnd= x ( lp+9) xld= x (lp+10) vsatd= x(lp+ll) gqs= x ( lp+12 ) ta= x ( lp+13 ) xicc0= x ( lp+14 ) xiec0= x ( lp+15) rth= x ( lp+16 ) h= x ( lp+17 ) dum= x ( lp+18 ) vg= x(lc+l) vch= x(lc+2) vben= x(lc+3) c* *********************************************************** c*****ifiag=l: error checking. c*****ifiag= 0: evaluate y= (value of source) . c*****ifiag= 1: evaluate y=d(value of source) /dx (lc+1) . c*****ifiag= 2: evaluate y=d (value of source) /dx (lc+2 ) . c*****ifiag= 3: evaluate y=d (value of source) /dx ( lc+3 ) . goto (25,50,100,200,300) , iflag +2 c* *********************************************************** c* perform onetime initialization or error checking * c ************************************************************ 25 continue if (nc .ne. 3) jerror = 99010 goto 99901 c ************************************************************ c* y=ICT (collector transport current of npn TR) * c* ********************************************************** * 50 continue call DEFF(4,0,y,vg,vch,vben) goto 99901 c ************************************************************ c* y=dICT/dVG * C***************************************^),^^*********** *****/( 100 continue
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143 call DEFF(4, l,y,vg,vch,vben) goto 99901 C* ********************************************************** * c* y=dICT/dVch * c************************************************************ 200 continue call DEFF(4,2,y,vg,vch,vben) goto 99901 c* *********************************************************** c* y=dICT/dVBEn * c* ********************************************************** * 300 continue call DEFF(4,3,y,vg,vch,vben) goto 99901 c 99901 continue c return end c* *********************************************************** c* SPICE2 Userdefined controlledsource subroutine for the c* drift region charging current in reverse mode of the c* LDD LDMOST. c* c* Refer to the comment in UUID.f. c* *********************************************************** subroutine UUQP (y , iflag, lp, np, lc, nc, j error) implicit double precision (ah,oz) common /blank/ x(64) common /parm/ z,xll,xl2,unch,xna,xnae,vsatch,und,xnd, &xld , vsatd , gqs , ta , xiccO , xiecO , rth , h , dum common /status/ omega, time, delta, delold(7) ,ag(7) ,vt, &xni , egfet , mode , modedc , icalc , init f , method , iord , maxord , Snoncon , iterno , itemno , nosolv common /knstnt/ twopi , xlog2 , xloglO , root2 , rad, boltz , &charge , ctok , gmin , reltol , abstol , vntol , trtol , chgtol , epso , Sepssil , epsox c*****lp=262, np=241, lc=286, nc=3 if (time. eq. 0. ) then z= x(lp+l) xll= x ( lp+2 ) Xl2= X ( lp+3 ) unch= x ( lp+4 ) xna= x ( lp+5 ) xnae= x(lp+6) vsatch= x ( lp+7 ) und= x(lp+8) xnd= x ( lp+9) xld= x(lp+l0) vsatd= x ( lp+ll ) gqs= x ( lp+12 ) ta= x ( lp+13 )
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144 xiccO= x ( lp+14 ) xiecO= x ( lp+15 ) rth= x ( lp+16 ) h= x ( lp+17 ) dum= x(lp+18) ynoer= x(lp+24) end if c* *********************************************************** c*****ifiag=l: error checking. c*****ifiag= 0: evaluate y= (value of source). c*****ifiag= 1: evaluate y=d(value of source) /dx ( lc+1) . c*****iflag= 2: evaluate y=d(value of source) /dx( lc+2 ) . c*****ifiag= 3: evaluate y=d(value of source) /dx ( lc+3 ) . goto (25,50,100,200,300) , iflag +2 25 continue return c************************************************************ c* Initialize the voltages and make current =0.0 in DC case * c* *********************************************************** 50 continue vg= x(lc+l) vch= x ( lc+2 ) vben= x(lc+3) if (time. eq. 0 . ) then call DEFF (6, 0,yy, vg, vch, vben) qp=yy x(lp+19)=qp y=o. x ( lp+20) =y x(lp+21)=delta x ( lp+22 ) =qp x ( lp+23 ) =y return else c***** ******************************************************* c* Update old charge and current, iteration at a new time c* point if local truncation error criteria are met c* ***************** ****************************************** if ( (initf.eq.6) .and. (delta. ge.x(lp+21) ) ) then x(lp+19) =x( lp+22) x ( lp+20) =x ( lp+23 ) end if call DEFF(6, 0,yy,vg, vch, vben) qp=yy x ( lp+22 ) =qp x ( lp+21) =delta if (delta. eq. 0. ) then y=0. else c *********Use Backward Euler approximation for numerical c********* integration c* ******* *x( lp+19) =x ( tn) ,x (lp+22 )=x(tn+l) c********* x (lp+20) =y(tn) ,x (lp+23 )=y(tn+l) c*********x (lp+ 21 ) =delta (tn) , delta=delta (tn+ 1 ) c********* y (tn+1) =[x (tn+1) x(tn) ]/delta y=(qpx( lp+19) ) /delta c*********use Trapezodial approximation for numerical
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145 c* ******** integration c*********y(tn+l)=2*[x(tn+l) x(tn) ]/deltay (tn) c y=(qpx(lp+19) ) *2 . 0/del tax ( lp+20) end if x ( lp+23 ) =y end if c****************************************************** ****** c* IF ynoer=0 then no errorchecking. c* Error checking is done presuming that SLICE/SPICE2 does c* check for current convergence. If the current converges c* and not the charge, then this program increments the c* parameter noncon. c********************************************* ****** ********* if (ynoer.ne. 0 . ) then toli=reltol*dmaxl (dabs (y) , dabs (x (lp+20) ) ) +abstol if ( (dabs (yx(lp+20) ) ) . It . toli) then tol=reltol*dmaxl (dabs (qp) ,dabs (x(lp+19) ) ) +chgtol if ( (dabs (qpx (lp+19) ) ) .ge. tol) noncon=noncon+l end if end if c no error checking c ynoer=0 return c* *********************************************************** c* Derivative w.r.t. VG. y=dQP/dVG c* *********************************************************** 100 continue if (delta. eq. 0. ) then y=0. else call DEFF (6,1, yy , vg , vch , vben ) y=2 . *yy/delta end if return c* *********************************************************** c* Derivative w.r.t. VCH. y=dQP/dVCH c* *********************************************************** 200 continue if (delta. eq.0. ) then y=0. else call DEFF (6, 2 ,yy, vg, vch, vben) y=2 . *yy/delta end if return c ************************************************************ c* Derivative w.r.t. VBEn . y=dQP/dVBEn c***************************************************** ******* 300 continue if (delta. eq. 0. ) then y=0. else call DEFF (6, 3 ,yy, vg, vch, vben) y=2 . *yy/delta end if return end
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146 Q"k "k ic ic ie ie "k ic ic ie ic ie ie k ie ie ie ic k k ic ic ic ic ic ic ic k ic ie "k ic ic ic ie "k ic ic k ie ic k ic k ic ic ic ic k ic k "k k k k ic k ic k c* SPICE2 Userdefined controlledsource subroutine for the * c* LDDdrift spacecharge region displacement current of the* C* LDD LDMOST . * c* * c* Refer to the comment in UUID.f. * c***************************************************** ******* subroutine UUQJC (y , iflag, lp, np, lc, nc, j error) implicit double precision (ah,oz) common /blank/ x(64) common /parm/ z,xll,xl2,unch,xna,xnae,vsatch,und,xnd, &xld , vsatd , ggs , ta , xiccO , xiecO , rth , h , dum common /status/ omega , time , delta , delold ( 7 ) , ag ( 7 ) , vt , &xni , egf et , mode , modedc , icalc , init f , method , iord , maxord , Snoncon , iterno , itemno , nosolv common /knstnt/ twopi , xlog2 , xloglO , root2 , rad, bolt z , Scharge, ctok,gmin, reltol , abstol , vntol , trtol , chgtol , epso, Sepssil , epsox c *****lp=2 62 , np=241 , lc=286, nc=3 if (time. eg. 0. ) then z= x(lp+l) xl 1= x ( lp+2 ) Xl2= x ( lp+3 ) unch= x ( lp+4 ) xna= x(lp+5) xnae= x ( lp+6) vsatch= X ( lp+7 ) und= X ( lp+8 ) xnd= X ( lp+9 ) xld= X(lp+10) vsatd= x(lp+ll) ggs= x ( lp+12 ) ta= x ( lp+13 ) xicc0= x ( lp+14 ) xiec0= x(lp+15) rth= x (lp+16) h= x ( lp+17 ) dum= x ( lp+18 ) ynoer= x ( lp+24 ) end if c*********** ************************* **************i,^.) e .) C .f (it ^^ i(it c*****ifiag=l: error checking. c*****ifiag= 0: evaluate y= (value of source) . c*****ifiag= l: evaluate y=d(value of source) /dx (lc+1) . c*****ifiag= 2: evaluate y=d(value of source)/dx(lc+2) . c*****ifiag= 3: evaluate y=d(value of source)/dx(lc+3 . goto (25,50,100,200,300) , iflag +2 25 continue return c* *********************************************************** c* Initialize the voltages and make current =0.0 in DC case * c ************************************************************ 50 continue vg= x ( lc+1 ) vch= x ( lc+2 ) vben= x ( lc+3 ) if (time. eg. 0 . ) then
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147 call DEFF (5 , 0 , yy , vg, vch, vben) q j c=yy x( lp+19 )=qjc y=0. x(lp+20)=y x(lp+21) =delta x ( lp+22 ) =qj c x ( lp+23 ) =y return else C* **************** k ***************************************** * c* Update old charge and current, iteration at a new time c* point if local truncation error criteria are met. c* ********************************************************** * if ( ( initf . eq. 6) . and. (delta . ge . x (lp+21) ) ) then x ( lp+19 ) =x ( lp+22 ) x(lp+20) =x( lp+23) end if call DEFF(5, 0,yy,vg, vch, vben) q j c=yy x( lp+22 )=qjc x (lp+21) =delta if (delta. eq. 0. ) then y=0. else c*********use Backward Euler approximation for numerical c********* integration c*********x( lp+19) =x(tn) ,x (lp+22 )=x(tn+l) c*********x(lp+20)=y (tn) , x ( lp+23 ) =y (tn+1) c********+x( lp+21) =delta (tn) , delta=delta (tn+1) c*********y (tn+1) =[x( tn+1) x (tn) ]/delta y=(qjcx( lp+19) ) /delta c*********use Trapezodial approximation for numerical c*********integration c********* y (tn+1) =2* [x (tn+1) x (tn) ]/deltay (tn) c y= ( (qj cx ( lp+19 ) ) * 2 . 0/delta) x ( lp +2 0 ) end if x (lp+23 )=y end if C* ************** k ******************************************* * c* IF ynoer=0 then no errorchecking. c* Error checking is done presuming that SLICE/SPICE2 does c* check for current convergence. If the current converges c* and not the charge, then this program increments the c* parameter noncon. C* ****** k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k if (ynoer.ne. 0. ) then toli=reltol*dmaxl (dabs (y) ,dabs (x(lp+20) ) ) +abstol if ( (dabs (yx ( lp+20) ) ) . It. toli) then tol=reltol*dmaxl(dabs(qjc) , dabs (x ( lp+19 ) ) ) +chgtol if ( (dabs (qj cx (lp+19) ) ) .ge.tol) noncon=noncon+l end if end if no error checking ynoer=0 return c c
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148 c* ********************************************************** * c* Derivative w.r.t. VG. y=dQJC/dVG q* ********************************************************** * 100 continue if (delta. eq. 0. ) then y=o. else call DEFF (5,1, yy , vg , vch , vben ) y=2 . *yy/delta end if return d************************************************************ c* Derivative w.r.t. VCH. y=dQJC/dVCH c* ********************************************************** * 200 continue if (delta. eq. 0 . ) then y=0. else call DEFF(5,2,yy,vg,vch,vben) y=2 . *yy/delta end if return c * *********************************************************** c* Derivative w.r.t. VBEn . y=dQJC/dVBEn c ************************************************************ 300 continue if (delta. eq.O. ) then y=0. else call DEFF (5, 3 ,yy, vg, vch, vben) y=2 . *yy/delta end if return end c ************************************************************ c* SPICE2 UserÂ— defined controlledÂ— source subroutine * c* for differentiating the source. * c* * c* Format to call this subroutine in UU%% file: * c* 1) to calculate %%; call DEFF(#, 0,y,vg, vch, vben) * c * 2) to calculate d%%/dvg; call DEFF (#, l,y,vg, vch, vben) * c* 3) to calculate d%%/dvch; call DEFF(# , 2 ,y, vg, vch, vben) * c* 4) to calculate d%%/dvben; call DEFF ( # , 3 , y , vg, vch, vben) * c* where #=1 for %%=ID, #=2 for %%=VEP, #=3 for %%=IBR, * c* #=4 for %%=ICT , #=5 for %%=dQJC/dt #=6 for %%=dQP/dt. * c ************************************************************ subroutine DEFF (mf lgl , mf lg2 , y , vg, vch , vben) implicit double precision (ah,oz) common /parm/ z,xll,xl2,unch,xna,xnae,vsatch,und,xnd, &xld , vsatd , gqs , ta , xiccO , xiecO , rth , h , dum common /status/ omega, time, delta, delold(7) ,ag(7) ,vt, &xni , egfet , mode , modedc , icalc , init f , method , iord , maxord ,
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149 Snoncon , iterno , itemno , nosolv common /poggy/ vicon(lO) , itprev, viconl (10) ,vicon2 (10) , &vicon3 (10) ,vicon4 (10) c* *********************************************************** c h=ld3 vbcn=vch c* *********************************************************** c* This part speeds up the program. c* ' iterno' is the iteration number in the SPICE. c* 'itprev' is the previous iteration number. c* c* At any iteration number (iterno>itprev) , once one of the c* UDCSs calls DEFF which in turn calls DMTs , then it sets c* itprev=iterno. c* c* When other UDCSs in the same iteration number call DEFF c* (iterno=itprev) , it skips calling of DMTs. c* c* In case of more than one devices, which has several c* different sets of controlling voltages, UDCSs with c* different controlling voltages need calling of DMTs even c* though iterno=itprev. For this case we need to compare c* controlling voltages. c************************************************************ if ( iterno . eg . 0 ) then if (mflg2 .eg. 0) then call DMT ( xid , vep , xibr , xict , g j c , qp , qgd , xi i , vg , vch , vben ) vicon(l) =xid vicon(2) =vep vicon(3)=xibr vicon(4)=xict vicon (5) =qjc vicon (6) =qp vicon(7)=qgd vicon (8) =xii end if if (mflg2 .eq. 1) then vg=vg+0 . 01+h call DMT (xid , vep , xibr , xict , qj c , qp , qgd , xii , vg , vch , vben ) viconl (1) =xid viconl (2 )=vep viconl (3) =xibr viconl (4) =xict viconl (5) =qjc viconl (6) =qp viconl (7) =qgd viconl (8) =xii vg=vg0 . 01h end if if (mf lg2 . eq. 2 ) then vch=vch+h call DMT (xid, vep, xibr , xict , qjc, qp , qgd, xii , vg, vch , vben) vicon2 (1) =xid vicon2 (2) =vep vicon2 (3)=xibr vicon2 (4) =xict
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150 vicon2 (5) =qjc vicon2 (6) =qp vicon2 (7) =qgd vicon2 (8) =xii vch=vchh end if if (mf lg2 . eq. 3 ) then vben=vben+h call DMT ( xid , vep , xibr , xict , q j c , qp , qgd , xi i , vg , vch , vben ) vicon3 (1) =xid vicon3 (2) =vep vicon3 (3)=xibr vicon3 (4)=xict vicon3 (5) =qjc vicon3 (6) =qp vicon3 (7) =qgd vicon3 (8) =xii vben=vbenh end if c itprev=iterno c end if c if (iterno.gt. itprev) then del=ld6 else if ( (dabs (vgvgp) .gt.del) .or. (dabs (vchvchp) .gt.del) .or. (dabs (vbenvbenp) [. gt.del) ) then call DMT ( xid , vep , xibr , xict , q j c , qp , qgd , xi i , vg , vch , vben ) vicon (l)=xid vicon(2) =vep vicon(3)=xibr vicon(4)=xict vicon (5) =qjc vicon(6)=qp vicon (7) =qgd vicon (8) =xii vg=vg+0 . 01+h call DMT ( xid , vep , xibr , xict , qj c , qp , qgd , xi i , vg , vch , vben ) viconl (1) =xid viconl (2) =vep viconl (3 )=xibr viconl ( 4 ) =xict viconl (5) =qjc viconl (6) =qp viconl (7) =qgd viconl (8) =xii vg=vg0. 01h vch=vch+h call DMT ( xid , vep , xibr , xict , q j c , qp , qgd , xi i , vg , vch , vben ) vicon2 (1) =xid vicon2 (2) =vep vicon2 ( 3 ) =xibr vicon2 (4) =xict vicon2 (5) =qjc vicon2 (6) =qp vicon2 (7) =qgd vicon2 (8) =xii vch=vchh
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151 vben=vben+h call DMT ( xid , vep , xibr , xict , q j c , qp , qgd , xi i , vg , vch , vben ) vicon3 (1) =xid vicon3 (2) =vep vicon3 (3)=xibr vicon3 (4)=xict vicon3 (5) =qjc vicon3 (6) =qp vicon3 (7) =qgd vicon3 (8) =xii vben=vbenh c itprev=iterno end if c*****end of speeding block********************************** c 50 continue c************************************************************ c* Source value; y=ID, VEP, IBR, ICT, QJC, QP, QGD, II * c* *********************************************************** if (mflg2 . eq. 0) then goto (110, 120, 130, 140, 150, 160, 170, 180 ) ,mflgl 110 y=vicon(l) goto 400 120 y=vicon(2) goto 400 130 y=vicon(3) goto 400 140 y=vicon(4) goto 400 150 y=vicon(5) goto 400 160 y=vicon(6) goto 400 170 y=vicon(7) goto 400 180 y=vicon(8) goto 400 400 continue goto 9999 end if c :************************************************************ c* Gradient of source ; c* y=d ( ID , VEP , IBR , ICT , QJC , QP , QGD , II ) /d ( VG , Vch , VBEn , VBCn , ) c ************************************************************ if (mf lg2 . ne . 0) then xidl= vicon(l) vepl= vicon(2) xibrl=vicon(3) xictl=vicon ( 4 ) qjcl= vicon(5) qpl= vicon(6) qgdl= vicon(7) xiil= vicon(8) goto (510, 520, 530, 540, 550, 560, 570, 580) ,mflgl if (mf lg2 . eq. 1) then y=(viconl (1) xidl) / (0 . 01+h) else if (mflg2.eq.2) then y=(vicon2 (1) xidl)/h 510
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520 530 540 550 560 570 580 152 else if (mflg2 . eq. 3 ) then y=(vicon3 (1) xidl)/h end if goto 800 if (mflg2 . eq. 1) then y=(viconl (2) vepl) / (0. 01+h) else if (mflg2 . eq. 2) then y=(vicon2 (2) vepl)/h else if (mf lg2 . eq. 3 ) then y= ( vicon3 ( 2 ) vepl ) /h end if goto 800 if (mflg2 .eq. 1) then y=(viconl (3) xibrl) / (0 . 01+h) else if (mflg2 . eq. 2 ) then y= (vicon2 ( 3 ) xibrl) /h else if (mf lg2 . eq. 3 ) then y=(vicon3 (3) xibrl) /h end if goto 800 if (mf lg2 . eq. 1) then y= (viconl ( 4 ) xictl) / ( 0 . 01+h) else if (mflg2 . eq. 2) then y=(vicon2 (4) xictl) /h else if (mflg2 .eq. 3) then y=(vicon3 (4) xictl)/h end if goto 800 if (mflg2 .eq. 1) then y= (viconl (5) qj cl) / ( 0 . 01+h) else if (mflg2 . eq. 2) then y=(vicon2 (5) qjcl) /h else if (mflg2.eq.3)then y=(vicon3 (5) qjcl) /h end if goto 800 if (mf lg2 . eq. 1) then y= (viconl (6) qpl)/ (0. 01+h) else if (mflg2 . eq. 2 ) then y=(vicon2 (6) qpl)/h else if (mflg2.eq.3) then y=(vicon3 (6) qpl)/h end if goto 800 if (mf lg2 . eq. 1) then y= (viconl (7 )qgdl)/( 0 . 01 +h) else if (mflg2.eq.2)then y=(vicon2 (7) qgdl)/h else if (mflg2 .eq. 3) then y= (vicon3 (7) qgdl)/h end if goto 800 if (mf lg2 . eq. 1) then y= (viconl (8) xiil) / ( o . 01+h) else if (mflg2 . eq. 2) then y=(vicon2 (8) xiil)/h else if (mflg2 . eq. 3) then
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153 y= (vicon3 ( 8 ) xiil) /h end if end if c 800 continue c 9999 continue v gp=vg vchp=vch vbenp=vben return end c************************************************************ c* This program is the LDD LDMOST model subroutine which is * c* accessed by the LDD LDMOST SPICE model UDCSs * c***************************** ********************* ********** c* The format to call this subroutine; * c* call DMT(xid,vdr,xibr,xict,qj , qp, qgd, vg, vch, vben) . * C* ************************************************** ie ******* * subroutine DMT ( xid , vdr , xibr , xict , qj , qp , qgd , xii , vg , vch , &vben) implicit double precision (ah,oz) common /parm/ w,xll,xl2,unch,xna,xnas,vsatch,und,xnd, &xld , vsatd , dvt , ta , xiccO , xiecO , rth , h , dum c* ********************************************************** * c* Device parameters with physical constants. * c* ********************************************************** * esi= q= vt0= xni= maxitl= 1.0d12 1 . 6d19 0.0259 1 . 45dl0 50 c * * * * *channel ***************** vfb= 0.92 pb= 0.39 cox= dum c cox= 3 . 452d8 theta= 2 . 83d2 eta= 9 . 0 c*****depletion MOST********** pba= 0.23 vfba= 0.76 c*****drift region************ bu= 2 . 9 yj= 2 . ld4 pbd= 0.29 vfbd= 0.26 xlo= 2 . Od4 c* *********************************************************** c* Account for temperature dependence of vsat and u. c* Muller & Kamins p37: vl>vsat, vl/Ec>u.
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154 c************************************************************ tam=300 tj=300 do 1000 k=l,maxitl tu=l . 01d6*dexp (2 . 42*dlog (tj ) ) tv=143.*dexp(0.87*dlog(tj) ) vtt=vtO*t j/tam uncht=unch*tu undt=und*tu vsatcht=vsatch*tv vsatdt=vsatd*tv da=2 . *vtt*undt/ (bu+1 . ) xla=dsqrt (da*ta) c* *********************************************************** c* Channel current for given VG and Vch c* vch is the total voltage drop across the whole channel, c* vl is the voltage drop across the doubledf fused channel, c* *********************************************************** qdlO=dsqrt ( 4 . *q*xna*esi*pb) qd20=dsqrt (4 . *q*xnas*esi*pba) vt=vfb+2 . *pbqdlO/cox+dvt c*****when vgcvt id=vdr=small_value (subthreshold) if(vg.le.vt) then xid=0 . goto 50 end if cdlO=q*xna*esi/qdlO cd2=q*xnas*esi/qd20 xk=cox* (vgvt) +2 . *eta*cdlO*pb unef f=uncht/ ( 1 . +theta* (vgvt) ) ec=2 . *vsatcht/unef f qn0=cox* (vgvt) c*****calculation of VI, sat xidsat=w*vsatcht*qnO a= (cox+cdlO) b=xk+qn0+xidsat*2 ./w/unef f/ec c=xidsat*2 . *xll/w/unef f bbac=b*b4 . *a*c if (bbac. It. 0) then print *, 'During cal. of vl,sat, D<0' print No posssible solution for vl,sat' print *, ' Try different vsat(ch)' stop end if vlsat=(bdsqrt (bbac) )/2./a c*****calculation of Vch, sat a=(cox+cd2) b=2 Â• *xk+2 . * (cdl0cd2) *vlsat+xidsat*2 ./w/uneff/ec c=2 . *xk*vlsat+ (cox2 . *cdl0+cd2 ) *vlsat*vlsat & +xidsat*2 . * (xl2vlsat/ec) /w/unef f bbac=b*b4 . *a*c if (bbac. It . 0) then print *, 'During cal. of Vch, sat, D<0' stop end if vchsat=(bdsqrt (bbac) )/ 2 ./a
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155 c *****when vch<0, NEED to DEVELOP a MODEL**** if(vch.lt.O) vch=vch if (vch. lt.vchsat) then bO=l ./ec* (cdl0+cd2 ) bl=xll* (cox2 . *cdl0+cd2) xl2* (cox+cdlO) & +l./ec* ( (cdlO2 . *cd2cox) *vch+xk+qnO) b2=xll* (2 . * (cdl0cd2) *vch+2 . *xk) +xl2* (xkqnO) & +vch/ec* ( xkqnO+ ( cox+cd2 ) *vch) b3=xll* (2 . *xk*vch+ (cox+cd2 ) *vch*vch) al=bl/bO a2=b2/b0 a3=b3/b0 vl=cubic (al , a2 , a3 ) xid0=w*uneff/2 ./xll/ (l.+vl/ec/xll) xid=xidO*vl* (2 . *qn0+2 . *eta*pb*cdlO(cox+cdlO) *vl) else xid=xidsat end if if (vch. It. 0) then xid=xid vch=vch end if c*****end of calculation of channel curent. 50 continue c* *********************************************************** c* NORMAL MODE * c* Calculation of LDDregion voltage drop * c ************************************************************ if(vch.ge.O) then if (dabs(xid) .le.l.d9) then vdr=0 goto 300 end if ecd=2 . *vsatdt/undt vbi=vtt*dlog(xnd*xnas/xni/xni) xne=xnd* (xnd+xnas) /xnas de=l./yj*dsqrt(2 . *esi/q/xne) c*****determining vdl,xidl c*****Above xidl, LDD region is divided into two sections, c*****a and B. C *****carriers in section A has fielddependent velocity. C *****carriers in section B has saturated velocity. al=3./de a2=3 . * (xld*ecdvbi) a3=4 . *vbi*dsqrt (vbi) +3 ./de*vbi+3 ./de*xld*ecd x=cubic(al,a2,a3) vdl=x*xvbi if (vdl.le.O) then print *,'vdl<0 in cal. of idl' stop end if xidl=w*yj * ( 1 . de*dsqrt (vdl+vbi) ) *xnd*q*vsatdt c*****determining xid2 c*****Above xid2 , LDD region has only section B. xk2=0 . 5 al=3 . /de
PAGE 162
156 a2=3 . * (xk2*yj*ecdvbi) a3=4 . *vbi*dsqrt (vbi) +3 ./de*vbi+3 ./ de * xk 2*yj *ecd x=cubic (al , a2 , a3 ) vc2=x*xvbi if (vc2 . le. 0) then print *,'vc2<0 in cal. of id2' stop end if xid2=w*yj * ( 1 . de*dsqrt (vc2+vbi) ) *xnd*q*vsatdt c*****iv for region I if (xid. le. xidl) then al= (xid/2 ./w/yj/xnd/q/vsatdt1 . ) *3./2./de a3= (xid*xld/w/yj/q/undt/xnd* ( 1 . vbi/xld/ecd) & 2 ,/3 . *de*vbi*dsqrt (vbi) +vbi) *1 . 5/de x=cubic(al, 0,a3) vdr=x*xvbi c*****iv for region II and III c*****vel is the voltage at the boundary bet. of section c*****a and B. c*****xlel is the length of section A. c*****yel is the depth of section B. c*****el is the electric field at the boundary, else if (xid. Ie.xid2) then vel= (yj xid/w/q/xnd/vsatdt) * (yj xid/w/q/xnd/vsatdt ) * & q*xne/2 ./esivbi if (vel.lt.O) vel=0 xlel=w*yj *q*undt*xnd/xid* ( vel2 . /3 . *de* ( & (vel+vbi) *dsqrt (vel+vbi) vbi*dsqrt (vbi) ) ) vel/ecd else vel=vc2 xlel=xk2*yj end if c yel=l. 0* (yjdsqrt (2 . 0*esi/q/xne* (vdl+vbi) ) ) el=ecd eyl=dsqrt (2 . 0*q/esi*vel/ ( 1 . 0/xnd+l . 0/xnas) ) vdr=2 . 0*vel do 200 i=l,50 eyd=dsqrt ( 2 . 0*q/esi*vdr/ ( 1 . 0/xnd+l . 0/xnas ) ) ej=(eyl+eyd)/2 . 0 ve2=(xldxlel) * (xldxlel)/2 . O/esi/yj/w/vsatdt* & (xidw*q*xnd*yj *vsatdt+esi*ej *w*vsatdt ) + & (xldxlel) *el vdr=vel+ve2 if (i Â• eq. 50) print *,'NO CONV. in Vep' if (dabs (vdrvdro) .It. 0.1) goto 210 vdro=vdr 200 continue 210 continue end if c*****end of calcualtion of V(drift reqion) 300 continue qj=q*w* (xld+yj ) *xnas*dsqrt (dabs ( & _q Â’ 0*esi*xnd/q/xnas/ (xnas+xnd) * (vch+vdr+2 . *pbd) )) xibr=0 c*****end of normal mode end if
PAGE 163
157 c************************************************************ c* REVERSE MODE c* IBR( reverse base current) is predominantly the c* recombination current in the substrate base region. c* c* ICT is the base transport current, c* c* QP(drift charge) is given by integrating n(x) over the c* substrate base region, c* c* Vdr (drift region voltage drop) is given by integrating c* E(x) (from Jn and Jp) over the substrate base region, c* c* Width of the substrate base is xb=xl2+xld. c* Area of the substrate base is sb=w*yj . c* *********************************************************** xr=0 . 2 vj pp=xr*vch xict=xiccO*dexp (vben/vtt ) xiecO*dexp (2 . 0*vjpp/vtt) if(vch.lt.O) then xb=xl2+xld sb=w*yj wx=xb/xla gj=0 xnO=xnas*dexp (vjpp/vtt) xnwl=xla*dsinh(wx) * (xict) /q/sb/da/ & (bu*dcosh(wx) +1. ) xnw2= (bu+dcosh (wx) )/(bu*dcosh(wx)+l. ) *xnO xnw=xnwl+xnw2 qp=q*sb*xla/dsinh (wx) * (dcosh (wx) 1 . ) * (xnO+xnw) xibr=qp/ta c*******calculating Vepi if (xnO . It . xnas) xnO=xnas if (xnw. It . xnas) xnw=xnas x i = (l* + bu) *q*sb*da/xla/dsinh(wx) * (xnw*dcosh (wx) xnO) pp=(xnwxnO*dexp(wx) )/2 ./dsinh(wx) qq= (xnO*dexp (wx) xnw) /2 . /dsinh (wx) if (pp*qq. eq. 0) print *, 'warning! ! ! pp*qq=o in DMT . f ' qqpp=qq/pp if (qqpp.lt.O) then dqp=dsqrt ( qq/pp ) xp=xla/2./dsqrt(pp*qq) *( & dlog (dabs ( (dexp (wx) dqp) / (dexp (wx) +dqp) ) ) & dlog (dabs ( (1. dqp)/ (l.+dqp) ) ) ) else dpq=dsqrt(pp/qq) xp=xla/ dsqrt (pp*qq) * ( datan (dpq*dexp (wx) ) & datan (dpq) ) end if vdrO=xi/q/sb/ ( 1 . +1 ./bu) /undt*xp
PAGE 164
158 vdrl=vtt* (bu1. ) / (bu+1 . ) *dlog (dabs (xnO/xnw) ) vdr2=vtt*dlog(dabs (xnw*xnas/xni/xni) ) vdr= ( 1xr) /xr*vjppvdr0vdrlvdr2 end if c*****end of reverse mode qgd=0 xii=0 if (k. eq.maxitl) print *,'No Temp, convergence' tjp=tj vd=vch+vdr xit=xidxibr tj=dabs (tam+rth*vd*xit) if (dabs (tjtjp) .It. 1.0) goto 1100 1000 continue 1100 continue return end c*****function to solve for cubic eq. function cubic (al , a2 , a3 ) implicit double precision (ah,oz) qq= (3.*a2al*al)/9. rr= (9 . *al*a227 . *a32 . *al*al*al) /54 . if ( (qq*qq*qq+rr*rr) .gt. 0) then print *, 'During function call "cubic", D>0' stop end if if (qq.gt.0) then print *, 'During function call "cubic", qq>0' stop end if cth=rr/dsqrt ( ~qq*qq*qq) th=dacos (cth) cubic=2 . *dsqrt (qq) *dcos (th/3 .+4 ./3 . *3 . 14159) al/3 . return end
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REFERENCES [App79] Appels, J. A. and Vaes, H. M. J., "High voltage thin layer devices (RESURF devices)," in IEDM Tech. Dig. , pp. 238241, 1979. [Bal87] Baliga, B. J., Modern Power Devices. New York: Wiley, 1987. [Bali84 ] Baliga, B. J., Adler, M. S., Love, R. P., Gray, P. V. , and Zommer, N. D., "The insulated gate transistor: A new threeterminal MOScontrolled bipolar power device," IEEE Trans. Electron Devices, vol . ED31, pp. 821828, June t wr. [Cho88] Chow, T. P., Baliga, B. J., and Pattanayak, D. N., "Counterdoping of MOS channel (CDC) A new technique of improving suppression of latching in insulated gate bipolar transistors," IEEE Electron Device Lett . , vol. 9, pp. 2931, Jan. 1988. [Chow87] Chow, T. P., Pattanayak, D. N., Baliga, B. J., and Adler, M. S., "Latching in lateral insulated gate bipolar transistors," in IEDM Tech. Dig., pp. 774777, 1987. [Cla86] Claessen, H. R. and Van Der Zee, P., "An accurate DC model for highvoltage lateral DMOS transistors suited for CAD," IEEE Trans. Electron Devices, vol. ED33, pp. 1964T970, Dec. [Col81 ] Colak, S., "Effects of drift region parameters on the static properties of power LDMOST, " IEEE Trans. Electron Devices , vol. ED28, pp. 14551466, Dec. [Cou88 ] Coughran, W. M. , Jr., Pinto, M. R. , and Smith, R. K., "Computation of steadystate CMOS latchup characteristics," IEEE Trans. ComputerAided Design , vol. 7, pp . 307323, Feb. 1988. [Dar86] Darwish, M. N., "Study of the quasisaturation effect in VDMOS transistors," IEEE Trans. Electron Devices , vol. ED33, pp. 17101716, Nov. 1986. 159
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160 [Darw84] [Darw87] [Fos86] [Fos88 ] [Foss86] [Goo83] [Har84 ] [Hef 86] [Huc82 ] [Huc84 ] [Kuo86] [ Lam7 0 ] Darwish, M. N. and Board, K., "Lateral resurfed COMFET," Electron. Lett. , vol . 20, pp. 519520, June 1984. Darwish, M. N. and Shibib, M. A., "DC and transient analysis of lateral insulated gate conductivity modulated transistors," in Proc. ECS Symp. on High Voltage and Smart Power Devices , pp. 295309, 1987. Fossum, J. G. and McDonald, R. J., "Chargecontrol analysis of the COMFET turnoff transient," IEEE Trans. Electron Devices , vol. ED33, pp . 13771382 , Sept . 1986 . Fossum, J. G., McDonald, R. J., and Shibib, M. A., "Network representations of LIGBT structures for CAD of power integrated circuits," IEEE Trans. Electron Devices , vol. 35, pp. 507515, Apr. 1988. Fossum, J. G. and Veeraraghavan, S., "Partitionedchargebased modeling of bipolar transistors for nonquasistatic simulation , " IEEE Electron Device Lett . , vol. EDL7 , pp. 652654"; DecT 1986 . Goodman, A. M. , Russell, J. P., Goodman, L. A., Nuese, C. J., and Neilson, J. M., "Improved COMFETs with fast switching speed and highcurrent capability," I EDM Tech. Dig. , pp . 7982, 1983. Harris Semiconductor Corp., SLICE Manual Rev. 4.08, Melbourne, FL, Jan. 1984. Hefner, A. R., Jr. and Blackburn, D. L., "Performance tradeoff for the insulated gate bipolar transistor: buffer layer versus base lifetime reduction," presented at IEEE Power Electronics Specialists Conference , 1986. Hu, C. and Chi, M.H., "Second breakdown of vertical power MOSFET's," IEEE Trans. Electron Devices, vol ED29, pp. 12871293, Aug. TWT. Hu, C ., Chi, M.H., and Patel, V. M., "Optimal design of power MOSFET's," IEEE Trans. Electron Devices, vol. ED31, pp. 16931700, Dec. mi; Kuo, D.S. and Hu, C., "Optimization of epitaxial layers for power bipolarMOS transistor, " IEEE Electron Device Lett . , vol. EDL7, pp. 5105T27 Lampert, M. A. and Mark, P., Current Infection in Solids , New York: Academic Press"; 1970 .
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161 [Luc88 ] Lu, C.Y., Tsai, N.S., Dunn, C. N., Riffe, P. C., Shibib, M. A., Furnanage, R. A., and Goodwin, C. A., "An analog/digital BCDMOS technology with dielectric isolationdevices and processes," IEEE Trans. Electron Devices , vol . 35, pp . 230239, Feb. 1988 . Â“ [McD85] McDonald, R. J., Fossum, J. G., and Shibib, M. A., "A physical model for the conductance of gated pin switches," IEEE Trans. Electron Devices, vol. ED32, pp. 13141320, July 1985. [Men86] Mena, J. G. and Salama, C. A. T., "Highvoltage multipleresistivity driftregion LDMOS , " SolidSt Electron. , vol. 29, pp. 647656, 1986. [Mul77 ] Muller, R. S. and Kamins, T. I., Device Electronics for Integrated Circuits . New York: Wiley, 1977 . [Nak85] Nakagawa, A. and Ohashi, H., "600and 1200V bipolarmode MOSFET' s with highcurrent capability, " IEEE Electron Device Lett . , vol. EDL6, pp . 378380, July 1985. [Pat86 ] Pattanayak, D. N., Robinson, A. L., Chow, T. P., Adler, M. S., Baliga, B. J., and Wildi, E. J., "nchannel lateral insulated gate transistors: Part ISteadystate characteristics," IEEE Trans. Electron Devices , vol. ED33, pp . 19561963, Dec. 1986. [Pin84] Pinto, M. R., Rafferty, C. S., and Dutton, R. W., "PISCESII user's manual," Stanford Electronics Labs., Stanford University, Stanford, CA, 1984. [Poc76 ] Pocha, M. D. and Dutton, R. w., "A computeraided design model for highvoltage double diffused MOS (DMOS ) transistors," IEEE J. SolidState Circuits, vol. SC11, pp. 718726, Oct. V5TZ~. [Rob86] Robinson, A. L., Pattanayak, D. N. , Adler, M. S., Baliga, B. J., and Wildi, E. J. , "Lateral insulated gate transistors with improved latching characteristics, " IEEE Electro n Device Lett. , vol EDL7, pp . 6163, Feb. 1986 . Â— [Rus83 ] Russell, J. P., Goodman, A. M., Goodman, L. A., and Neilson, J. M., "The COMFETA new high conductance MOSgated device," IEEE Electron Device Lett., vol. EDL4 , pp. 6365, Mar . 1983. Â‘ Seitchik, J. A., Chatter jee, A., and Yang, P., An analytic model of holding voltage for latchup _ in epitaxial CMOS," IEEE Electron Device T.Atlvol. EDL8, pp. 157159, Apr. 1^87. ~ [Sei87]
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[Sod84 ] [Sze81] [Vee86 ] [W1187] 162 Sodini, C. G., Ko, P., and Moll, J. L., "The effect of high fields on MOS device and circuit performance," IEEE Trans. Electron Devices. vol.ED31, PP . 1386T393, Oct. IJWT. Sze, S. M., Physics of Semiconductor Device s, 2nd ed. New York! Wiley, 1961 . Veeraraghavan, S., Fossum, J. G., and Eisenstadt, W. R., "SPICE simulation of SOI MOSFET integrated circuits," IEEE Trans. ComputerAided Desian. vol cad5, pp. " 65 3 638 , oct 1986 . 3 ~ Williams, R. K., Timmes, F. X., Busse, R. W., and Siu, I. K., "Twodimensional device simulation of highvoltage lateral DMOST's," in Proc. ECS 318 P 327 n H 1987 V Â° ltaqe and Smart Power Devices , pp.
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BIOGRAPHICAL SKETCH YeongSeuk Kim was born in Kyungnam, Korea, on July 3, 1957. He received the B.S. and M.S. degrees in electronics from Seoul National University, Korea, in 1980 and 1982, respectively. Since October 1985, he has been working toward the Ph.D. degree in electrical engineering at the University of Florida, Gainesville. His doctoral research involves modeling of semiconductor power devices. From 1982 to 1985, he was with the Central Research Laboratories of Gold Star, Seoul, Korea, where he designed integrated circuits for consumer electronics . 163
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I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the a degree of Dpctor of Philosophy. Jtfrry C/. Fossum, Chairman rofessor of Electrical Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as degree of Doctor of Philosophy. a dissertation for the 7L Sheng S . Li'" Professor of Electrical Engineering I certify that I have read this study and that in my opinion it confopns to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. IzL. Dorothea E . Burk Professor of Electrical Engineering 1 certify that I have read this study and that in ay opinion it confopns to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Li/luv^ Khai D . T . Ngo ^ Assistant Professor of Electrical Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Do^r of Philosophy. 5 Kevin S . Jones Assistant PptJfessor of Materials Science and Engineering
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This dissertation was submitted to the Graduate Faculty of the College of Engineering and to the Graduate School and was accepted as partial fulfillment of the requirements for the degree of Doctor of Philosophy. August 1990 Winfred M. Phillips Dean, College of Engineering Madelyn M. Lockhart Dean, Graduate School

