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## Material Information- Title:
- Design and analysis of double-gate CMOS for low-voltage integrated circuit applications, including physical modeling of silicon-on-insulator MOSFETS
- Creator:
- Kim, Keunwoo, 1968-
- Publication Date:
- 2001
- Language:
- English
- Physical Description:
- vii, 190 leaves : ill. ; 29 cm.
## Subjects- Subjects / Keywords:
- Capacitance ( jstor )
Doping ( jstor ) Electric current ( jstor ) Electric fields ( jstor ) Electrons ( jstor ) Ions ( jstor ) Modeling ( jstor ) Narrative devices ( jstor ) Oxides ( jstor ) Simulations ( jstor ) - Genre:
- bibliography ( marcgt )
theses ( marcgt ) non-fiction ( marcgt )
## Notes- Thesis:
- Thesis (Ph. D.)--University of Florida, 2001.
- Bibliography:
- Includes bibliographical references (leaves 183-189).
- General Note:
- Printout.
- General Note:
- Vita.
- Statement of Responsibility:
- by Keunwoo Kim.
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DESIGN AND ANALYSIS OF DOUBLE-GATE CMOS FOR LOW-VOLTAGE INTEGRATED CIRCUITAPPLICATIONS, INCLUDING PHYSICAL MODELING OF SILICON-ON-INSULATOR MOSFETS By KEUNWOO KIM A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2001 ACKNOWLEDGMENTS I would like to express my sincere appreciation to the chairman of my supervisory committee, Professor Jerry G. Fossum, for his guidance and support throughout my work. Without his invaluable guidance and encouragement, this work could not have come to fruition. I also would like to thank Professors Tim Anderson, Gijs Bosman, and Sheng Li for their willing service and guidance on my committee. I thank Mary Fossum and Erlinda Lane for all of their help arranging travel plans for numerous reviews and conferences, and Linda Kahila and Greta Sbrocco for administrative guidance. I thank the Semiconductor Research Corporation and the University of Florida for financial support. I would like to thank MengHsueh Chiang, who helped me in many ways with profound technical discussions, and I also thank fellow students Duckhyun Chang, Yan Chong, Brian Floyd, Lixin Ge, Hyun-jong Ko, Sangchoon Kim, Sungphil Kim, Bin Liu, Namkyu Park, Mario Pelella, Dongwook Suh, Inchang Seo, Glenn O. Workman, Kehuey Wu, Dung-jun Yang, Ji-woon Yang, Seong-mo Yim, and Wenyi Zhou for their daily companionship. Also, I thank all of the friends who made my years at the University of Florida such an enjoyable chapter of my life. ii Finally, I must acknowledge the support I received from all of my extended family members; aunts, uncles, nieces, and nephews. I am deeply thankful to my immediate family, all of whom stressed the importance of education to me. In particular, I am grateful to my parents, Unyong Kim and Duran Youn, for their unceasing support and my parents in law for their emotional support. Finally, I thank my lovely wife, Hyeyun Jang, whose endless love and encouragement were most valuable to me. iii TABLE OF CONTENTS page ACKNOWLEDGMENTS ..................................... ........................ ii ABSTRACT ....................................................... ........... ..............vi CHAPTERS 1 INTRODUCTION ................................................................ 1 2 ACHIEVING THE BALLISTIC-LIMIT CURRENT IN SI MOSFETS ..6 2.1 Introduction ............................................................. 6 2.2 Ballistic-Limit Current ........................................ ............ 2.2.1 Theory ..................................... .......................7 2.2.2 Analysis ......................................... ............... 10 2.3 Double-Gate MOSFET ....................................... ......... 20 2.4 Conclusions ..................................................... .........22 3 MODELING AND INCORPORATION OF TUNNELING CURRENTS IN UFSOI MOSFET MODELS ...... ..................... .. 23 3.1 Introduction ..................................... ....................... 23 3.2 M odel Developments ......................................... .......... 24 3.2.1 Gate-Induced Drain Leakage Current ....................... 24 3.2.2 Reverse-Bias Junction Tunneling Current ..........36 3.3 Model Implementation/Verification ..................................... 44 3.4 BJT Amplification by Tunneling Currents .........................49 3.5 Model Application to CMOS Circuit .................................... 53 3.6 Conclusions ..................................... ................. 55 4 DOUBLE-GATE CMOS .......................................... .............. 60 4.1 Introduction ...................................... ...................... 60 4.2 Scalability of Fully Depleted SOI MOSFETs .......................61 4.3 General Comparison of Symmetrical and Asymmetrical Double-Gate Devices ............................................................ 66 4.3.1 MEDICI Simulation Results ..................................... 67 4.3.2 Analytical Insights ...........................................77 4.3.3 Asymmetrical DG CMOS ........................................... 85 iv 4.4 Extremely Scaled Double-Gate CMOS Performance Projections Including GIDL-Controlled Off-State Current ...89 4.4.1 50 nm Asymmetrical DG CMOS ................... 90 4.4.2 GIDL Effects for 50 nm Asymmetrical DG CMOS .......95 4.5 Conclusions ........................................ 101 5 25 NM DOUBLE-GATE CMOS DESIGN ........................................ 104 5.1 Introduction ........................................ 104 5.2 Preliminary Classical MEDICI-Based Design ...................... 106 5.2.1 Device Characteristics ...................................... 106 5.2.2 Short-Channel Effects ...................................... 118 5.3 Schr6dinger-Poisson Solver (SCHRED)-Based Analysis ...... 131 5.3.1 Threshold Shift ...................................... 131 5.3.2 Capacitance Degradation ...................................... 134 5.4 25 nm DG Device Design with Quantum-Mechanical Effects 138 5.4.1 Device Characteristics ...................................... 138 5.4.2 Short-Channel Effects for Newly Designed Devices .. 150 5.4.3 Sensitivity Study ...................................... 155 5.4.4 Bottom-Gate Underlap ...................................... 167 5.4.5 CMOS-Inverter Speed Estimation ........................... 170 5.5 UFDG-Aided Design ...................................... 172 5.6 Conclusions ........................................ 177 6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK ............. 179 6.1 Summary ........................................ 179 6.2 Suggestions for Future Work ...................................... 181 REFERENCES ........................................ 183 BIOGRAPHICAL SKETCH .................................................................. 190 v Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy DESIGN AND ANALYSIS OF DOUBLE-GATE CMOS FOR LOW-VOLTAGE INTEGRATED CIRCUIT APPLICATIONS,INCLUDING PHYSICAL MODELING OF SILICON-ON-INSULATOR MOSFETS By Keunwoo Kim August 2001 Chairman: Jerry G. Fossum Major Department: Electrical and Computer Engineering This dissertation mainly focuses on analysis and design of scaled double-gate (DG) silicon-on-insulator (SOI) complementary metal-oxidesemiconductor (CMOS) field-effect transistors (FETs) for low-voltage integrated circuit (IC) applications; related physical modeling of fully depleted (FD) and partially depleted (or non-fully depleted, NFD) SOI MOSFETs is presented as well. Achieving the ballistic-limit current in Si MOSFETs is discussed based on a theoretical analysis of the fundamental limit current. The study considers measured data of extremely scaled bulk-Si and SOI CMOS devices, and Monte Carlo-simulated data of 25 nm bulk-Si and DG CMOS devices, and concludes that, for controlled off-state current, only an optimally designed DG structure could yield a ballisticlimit on-state current. Because off-state current in SOI MOSFETs is one vi of the major issues for contemporary low-voltage/low-power IC applications, gate-induced drain leakage (GIDL) and reverse-bias junction tunneling currents, which can significantly govern off-state current, are physically analyzed and incorporated in the University of Florida SOI (UFSOI) MOSFET models. The viability of FD/SOI CMOS is examined for deep-submicron (< 0.1 gm) channel lengths, suggesting that the DG MOSFET is the structure needed for scaling the FD/SOI technology. The DG MOSFETs, with either symmetrical or asymmetrical gates, are strong candidates for future CMOS IC applications due to the charge coupling of the two gates via the thin, fully depleted silicon film body. Comparison of asymmetrical and symmetrical DG devices is comprehensively done for the first time. Numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical DG CMOS, using n+ and p+ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons. The GIDL effects, which tend to be more severe in the asymmetrical DG device, are analyzed and shown to be controlled via optimal design. Simulation-based design and analysis of 25 nm DG CMOS are presented, showing feasibility of extremely scaled DG MOSFETs, even when imperfectly fabricated. Quantum-mechanical issues and quasi-ballistic transport are considered in the simulation-based design of 25 nm DG CMOS; circuit performance projections suggest that optimal DG CMOS is far superior to the bulk-Si counterpart technology. vii CHAPTER 1 INTRODUCTION Continuous CMOS scaling has been a main factor of silicon technology advancement, including the improvements of the MOSFET performance. However, the continued scaling process beyond 0.1 gm channel lengths will have to cope with unknown lithographic capabilities. Furthermore, the improved performance gain through such miniaturized channel lengths is unclear due to severe short-channel effects [Vee89], [Gha00] and fundamental limits of silicon material characteristics [Lun97], that will prevail near the end of SIA roadmap [Sem99]. To face these problems, new device structures for next-generation technology have been proposed such as metal-gate fully-depleted (FD) SOI MOSFET [Cha98], double-gate (DG) MOSFET [Fra92], SiGe MOSFET [Ism95], lowtemperature CMOS [Tau97], and even quantum dot device [Wel97]. Among them, DG CMOS is a very promising candidate with its superior performance implied by excellent control of short-channel effects (SCEs), steep subthreshold slope, and high drive current and transconductance [Fos98b], [Fra92]. With the immunity of SCEs, less severe scaling rules and channel-doping designs are possible for DG MOSFETs. A traditional approach for alleviating SCEs in conventional CMOS technologies is to increase the channel-doping density and to 1 2 decrease the gate oxide thickness. Such high doping density and thin oxide can limit device/circuit performance due to decreased carrier mobility, increased junction capacitance, and increased junction tunneling leakage current. However, DG MOSFETs can be designed with low-doped channel and relatively thicker oxide, which yield higher mobility, thereby enhancing the drive current to more than double that of bulk-Si or SOI MOSFETs. This work is mainly focused on viable DG CMOS design for circuit applications and its physical analysis, and includes upgrades and improvements of the UFSOI models [Fos98a] for contemporary SOI as well as DG CMOS technologies. In Chapter 2, achieving the ballistic-limit current in Si MOSFETs is discussed. For the ultimately scaled silicon-based devices, questions about fundamental performance limits arise [Lun97]. Comprehensive analysis regarding the fundamental current limit for particular CMOS applications is needed to identify the performance limit of conventional MOSFETs and to predict the viability of future DG devices. Theoretical analysis of these limits, with comparisons to currents that have actually been achieved in recent CMOS technologies and that have been predicted by Monte Carlo simulations, gives insight about why the limits have not been reached and how they might be reached. The study considers SOI as well as bulk-Si devices, and suggests that, for controlled off-state current, only an optimally designed DG structure could yield a ballistic-limit on-state current. 3 In Chapter 3, quantum-mechanical tunneling currents are modeled. The scaling of contemporary deep-submicron SOI MOSFETs demands a reduction of oxide thickness and an increase in channel doping density to control SCEs. However, thin gate oxide raises the vertical electric field in gate-to-drain overlap of SOI MOSFETs, and high channel doping density increases the lateral electric field in body-to-drain junction of SOI MOSFETs. Due to such high fields, previously ignored quantummechanical tunneling currents, gate-induced drain leakage (GIDL) current [Che87] and reverse-bias junction tunneling current [Fos85], become significant. Both the tunneling currents can be important components of off-state current and should be minimized for low voltage/ low power integrated circuit applications [Fos98c]. The GIDL current and reverse-bias junction tunneling current are incorporated in UFSOI models [Fos98a] to assure the validity for scaled device simulations and to enhance the predictive capability. More detailed analysis for GIDL current, including its drain-body bias dependence, is given as well. In Chapter 4, DG MOSFETs, including conventional FD/SOI MOSFETs, are analyzed. FD/SOI MOSFETs offer several potential advantages including enhanced current, ideal subthreshold slope, and reduced short-channel effects over bulk-silicon or partially-depleted (PD) SOI counterparts for VLSI CMOS applications [Yeh95]. However, these advantages tend to fade as the channel length is shrunk to 0.1 gm, due to unacceptably low threshold voltage and poor subthreshold characteristics 4 [Yeh96]. The scalability of FD/SOI CMOS is examined to indicate a need of significant technology innovation for viable FD/SOI CMOS in the future. With the advantages of FD/SOI transistors, DG MOSFETs have their own benefits, with the possibility of scaling to extremely short channel lengths below 0.1 gtm due to the electrical coupling of two gates. Two kinds of DG CMOS technologies are suggested: symmetrical DG devices, which can have n+ polysilicon front and back gates for the nMOSFET (and p+ polysilicon for the pMOSFET), and asymmetrical DG devices, which can have n+ and p+ polysilicon gates for front and back gates for both nMOS and pMOS devices. Much of this interest stems from the two-channel property of the symmetrical-gate DG device and the implied higher current drive. However, performance of the asymmetrical DG device, with only one channel, is less understood. Comprehensive performance analysis for asymmetrical and symmetrical DG devices is comparatively discussed for the first time. GIDL effects for DG MOSFETs, which tend to be worse in the asymmetrical device, are analyzed and shown to be controllable via optimal design. In Chapter 5, simulation-based 25 nm DG CMOS design is presented. The design of feasible DG devices with Leff = 25 nm gives good insight and guidelines for future revolutionary DG CMOS technology. Due to the extremely short channel, the carrier transport behavior will be quasi-ballistic with the influence of velocity overshoot [Fra92], and due to 5 the required extremely scaled Si film and oxide thickness for such a scaled channel length device, the carrier behavior within the film is expected to be largely quantum mechanical [Gam98], [Maj98]. Based on the insights from the results of a one dimensional (1-D) self-consistent SchrodingerPoisson tool (SCHRED-2) [VasOO], quasi-ballistic carrier transport and quantum-mechanical effects are included in design and analysis of 25 nm DG MOSFETs, done via a two-dimensional (2-D) device simulator (MEDICI) [Ava99]. Then, projection of 25 nm DG CMOS circuit performance is presented via a compact UFDG [Chi01] model in SPICE3. In Chapter 6, this dissertation is concluded with summaries of the primary contributions and suggestions for future upgrades of the UFSOI and UFDG models to effectively aid the development of SOI and DG CMOS technologies. CHAPTER 2 ACHIEVING THE BALLISTIC-LIMIT CURRENT IN SI MOSFETS 2.1 Introduction The motivation for the aggressive scaling of CMOS technologies has been increased integrated-circuit functionality per cost, which has been tantamount to improved performance, or higher currents in smaller devices. A prevalent thought has been that the on-state channel current (Ion) could be continuously increased by scaling (effective) channel length (Leff), with carrier velocity overshoot obviating the limit implied by velocity saturation [Pin93], until Ion ultimately reaches the fundamental, or ballistic-limit current, defined by an average thermal injection velocity (vT) of near-equilibrium carriers in the source [Lun97]. However, as Leff has been decreased, 2D short-channel effects (SCEs) have become harder to control, necessitating higher channel-doping density and thinner gate oxides. These modifications of the device structure have resulted in higher transverse electric field in the channel, and hence more degradation of onstate carrier mobility via increased surface scattering [Tau98a]. The lower mobility tends to inhibit velocity overshoot [Pin93] and to prevent Ion from approaching the ballistic limit. Actual (bulk-Si and SOI) devices scaled to Leff 50 nm reflect this tendency, as do Monte Carlo simulations of devices with Leff as short as 25 nm. In this chapter, we discuss the 6 7 injection velocity and the ballistic-limit current, comparing the latter to currents that have actually been achieved in recent CMOS technologies and that have been predicted by Monte Carlo simulations. Insight gained from this analysis clarifies why the ballistic limit is not being reached, and it suggests how, via optimally designed double-gate MOSFETs, it could be. 2.2 Ballistic-Limit Current 2.2.1 Theory Lundstrom [Lun97] recently presented a scattering theory which suggests that the kinetics of thermal carriers in the source defines the fundamental upper limit of saturated, or on-state channel current (Ion) in extremely scaled silicon MOSFETs. As illustrated in Figure 2.1 for short L, the lateral electric field (-dys/dy) shows a large gradient along the channel for high VDS, but is zero at the virtual source. Hence carriers there, which have diffused from the source, are virtually in thermal equilibrium. In the ballistic limit of negligible backscattering of carriers from the channel to the source, the ultimate current limit is thus implied directly by the kinetic-limit, or unidirectional average velocity (vKL) [Gha68] of the carriers at the virtual source. The actual injection velocity of carriers entering the channel is vT = 2vKL [Ber74], the average velocity of all the carriers (n+) having (positive) components of velocity toward the channel. In thermal equilibrium, n+ = n- = n/2, and hence n+vT = nvKL, in accord with the classical definition and derivation of vKL (= [kBT/2nm*] 1/2 for nondegenerate carriers) [Gha68]. 8 Vs Drain VDS Virtual Source Source 0 0+ Leff Y Figure 2.1 Electric potential variation across the channel of an extremely scaled silicon nMOSFET. The virtual channel where the longitudinal electric field is zero, defined by the application of VDS = VDD, is indicated. 9 Ignoring series resistance for the time being, we can express the on-state current of a typical (single-gate) nMOSFET as Ion = -WQi(0+)v(0+) = WCG(on)(VDD VT(on))V(0+) (2.1) where CG(on) (< Cox = sox/tox due to finite inversion-layer capacitance, or thickness [Tau98a], [Vas97]) is the total gate capacitance, VT(on) is the VDD-defined saturation-region threshold voltage, including SCEs, and v(0+) is the average carrier (diffusion) velocity at the virtual source (y = 0+ in the channel as shown in Figure 2.1). For the ballistic limit, v(O+) = vT, LIM and Ion = Ion We stress that VT(on) in Equation (2.1) must implicitly account for polysilicon-gate depletion [Tau98a] and carrier-energy quantization [Tau98a], which tend to increase it, as well as source/drain charge-sharing and DIBL [Tau98a], which tend to decrease it. Further, a more representative expression for vT in scaled devices must account for carrier-energy quantization (2D conduction subbands), carrier degeneracy (Fermi-Dirac statistics), and differences between the density-of-states effective mass (mDj*) and the conductivity effective mass (mcj*) for each subband (j) [AssOO]: 1 2kBTmcj* F1/2[(EF Ej)/kBT] n j=L[i (mDj) 2 In[1 + exp((EF- Ej)/kBT) (2.2) where Ej is the subband energy, nj is the electron density in subband j, and N N is the number of occupied subbands; n = Z nj. Note that the Fermij= 1 10 Dirac correction factor in Equation (2.2) is greater than unity. We used SCHRED-2 [Vas00], a 1D self-consistent Schridinger-Poisson solver, to check typical values of injection velocities for electrons and holes. For an MOS structure with Nchannel = 1018 cm-3 and tox = 2 nm, Figure 2.2 shows predicted vT versus the gate voltage overdrive, (VG VT), for inversion electrons and holes. For normal VG, both vT(n) and vT(p) exceed 107 cm/s, and they increase significantly with VG due to the carrier degeneracy. For our initial analysis, which is not intended to be exact, we will assume, based on Figure 2.2 for representative I VG VT I = 1.0 V, that VT(n) 1.5x107 cm/s and VT(p) = 1.2x107 cm/s. Note that these injection velocities differ by -25%, and hence so do the ballistic-limit currents defined by Equation (2.1) and its counterpart for a pMOSFET. We further assume in Equation (2.1) that CG(on)/Cox = 0.9 is representative of the inversion layer-capacitance effect [Tau98a], [Vas97] in scaled MOSFETs. 2.2.2 Analysis Measured characteristics recently reported in [Yan98], [Rod98], [Har98], [Leo98] reflect the performances of contemporary advanced CMOS technologies, including SOI [Leo98] as well as bulk-Si [Yan98], [Rod98], [Har98] devices. These technologies are yielding devices having Leff = 55-110 nm with (actual) gate oxide thicknesses (tox) of 2-2.5 nm. Measured on-state currents (at VDS = VGS = VDD = 1.0-1.5 V) in nMOS and pMOS devices from these technologies are tabulated in Table 2.1, which 1.6x107 1.4x107 nMOS 1.2x107 1.0x107 pMOS 0.8x107 0.0 0.2 0.4 0.6 0.8 1.0 IVG- VTI (V) Figure 2.2 SCHRED-2 [VasOO]-predicted electron and hole injection velocities versus gate voltage overdrive in bulk-Si MOSFETs with tox = 2 nm and Nchannel = 1018 cm-3. 12 Table 2.1 Measured On-State Currents in Recently Reported Scaled CMOS Technologies Versus Fundamental Ballistic-Limit Currents Derived from Equation (2.1) LIM Device Leff tox VG-VT(on) on Ion (nm) (nm) (V) (mA/gm) (mA/gm) nMOS -90 2.0 1.20 0.94 2.84 [Yan98] pMOS -110 2.0 1.26 0.42 1.98 [Yan98] nMOS <90 2.5 1.05 0.58 1.99 [Rod98] pMOS <90 2.5 0.95 0.24 1.19 [Rod98] nMOS -60 2.0 1.35 0.82 3.17 [Har98] pMOS -80 2.0 1.30 0.42 2.04 [Har98] nMOS -55 2.0 0.75 0.40 1.77 [Leo98] pMOS -80 2.0 0.65 0.12 1.02 [Leo98] 13 also includes corresponding ballistic-limit currents predicted by Equation (2.1) with the assumptions noted in Sec. II; VT(on) (defined as VGS for IDS/ (W/Leff) 10-7 A) and tox were taken from the cited papers. Note that for all the technologies the measured currents are substantively less than the corresponding limit currents. The measured ratio of the nMOS/pMOS currents is -2 or larger in all the technologies, and thus the pMOS currents are much more below the limits than the nMOS currents. Although the SOI (partially depleted) nMOS device [Leo98] has the LIM shortest L, its Ion is farthest (23%) from its Ion This discrepancy could be due, in part, to high source series resistance, or to VT(on) uncertainty due to the floating-body effect [Fos98c] and/or the pulse (transient)measurement reliability [Jen95]; or to our use of vT evaluated (from Figure 2.2) at relatively high gate voltage overdrive. In Equation (2.1) and in Table 2.1, we have ignored the effect of LIM finite source series (specific) resistance (Rs), which reduces Ion by lowering VGS = VDD in Equation (2.1) by the associated ohmic drop LIM (RsIon /W). This reduction is significant for representative Rs (100-500 LIM Q-gm) as illustrated by the Ion vs. RS plot in Figure 2.3. We can infer from Equation (2.1) that unless Rs << 1/(CoxvT) the reduction will be important. For 2 nm oxides as in Figure 2.3, we need RS << -400 Q-gm, which is approachable but not strictly achievable. For Rs = 100 -gm, LIM Ion is reduced by 19% from the ideal value. Note, however, that for all the technologies in Table 2.1, the measured currents are still significantly 14 2.5 2.0 6 1.5 1.0 0.5 to = 2 nm VGS VT(on) = 1.0 V 0 .0 . ' 1 101 102 103 104 Rs (Q-gm) Figure 2.3 Ballistic-limit current versus source (specific) series resistance implied by Equation (2.1) for an nMOSFET with the ohmic drop accounted for. 15 less than the corresponding limit currents even when reasonable Rs is accounted for. Next, consider the Monte Carlo-predicted currents for projected Leff = 25 nm nMOS and pMOS bulk-Si MOSFETs [Tau98b], contrasted in Table 2.2 with the corresponding ballistic-limit currents defined by Equation (2.1); Rs is not modeled here, and hence the comparisons are more insightful. Note that even in these devices, scaled to near the end of the 1999 SIA roadmap [Sem99], the limit currents exceed the predictions significantly. Finally, consider the Monte Carlo-predicted currents for Leff = 30 nm (symmetrical) double-gate (DG) MOSFETs [Tau97], contrasted in Table 2.3 with the corresponding ballistic-limit currents. Because the differences are smaller than in Tables 2.1 and 2.2, we have calculated LIM more exact values of Ion here. We used SCHRED-2 [VasOO] to predict the electron and hole injection velocities in the DG device structures, and used different values depending on the gate voltage overdrive as shown in Figure 2.4. Note that the low-VG vT's for the DG devices are comparable with those for the bulk-Si devices in Figure 2.2, but the carrier-degeneracy effect for increasing VG is less pronounced since the DG oxides are thicker (tox = 3 nm) and hence the inversion-carrier densities (per channel) are lower. We also accounted for Rs, assumed in [Tau97] to be 50 Q-gm. Finally, we multiplied the current derived from Equation (2.1), expanded to account for RS, by 2 to account for both channels. 16 Table 2.2 Extremely scaled (Leff = 25 nm, tox = 1.5 nm) bulk-Si MOSFET currents predicted by Monte Carlo simulations [Tau98b] versus fundamental ballistic-limit currents derived from Equation (2.1) VG-VT MC LIM Device Gs-T(on) Ion on (V) (mA/pm) (mA/4m) nMOS -0.7 0.65 2.20 nMOS -0.9 1.05 2.84 pMOS -0.7 0.35 1.46 pMOS -0.9 0.63 1.88 Table 2.3 Extremely scaled (Leff = 30 nm, tox = 3.0 nm, tsi = 5 nm) doublegate MOSFET currents predicted by Monte Carlo simulations [Tau97] versus fundamental ballistic-limit currents derived from Equation (2.1), extended for finite Rs (= 50 G-gm) V V MC LIM Device VGS-VT(on) VT IoMIon (V) (cm/s) (mA/gm) (mA/jtm) nMOS 0.43 1.24x107 0.93 0.97 nMOS 0.63 1.27x107 1.41 1.46 pMOS 0.33 0.82x107 0.36 0.52 pMOS 0.53 0.83x107 0.62 0.84 17 1.4x107 1.3x107 nMOS 1.2x107 1.1x107 1.0x107 0.9x107 pMOS 0.8x107 0.0 0.2 0.4 0.6 0.8 1.0 I VG- VTI (V) Figure 2.4 SCHRED-2 [Vas00]-predicted electron and hole injection velocities versus gate voltage overdrive in symmetrical DG MOSFETs with tox = 3 nm, Nchannel = 1015 cm-3, and Si-film thickness tsi = 5 nm. 18 The results in Table 2.3 show that the predicted DG nMOSFET current is virtually at the ballistic limit! It is still a factor of -2 higher than the DG pMOSFET current, which is below its limit, but much closer to it than that of the bulk-Si device in Table 2.2. Further, comparison of the Monte Carlo simulation results in Tables 2.2 and 2.3 reveals that even though the DG devices have thicker tox = 3 nm (which means that CG(on) in Equation (2.1) is approximately 50% lower than that for the bulk-Si devices with tox =1.5 nm), their on-state currents per channel are higher. These results, in our interpretation, reflect a significance of electron velocity overshoot in the DG MOSFETs, which tends to reduce the backscattering coefficient [Lun97] at the virtual source. In a quasiballistic-transport theory (i.e., one population of carriers flows ballistically while another is scattered), higher average velocity near the drain results in lower Ey there, and hence, for a specific VDS, higher Ey and higher velocity (i.e., less backscattering) just beyond the virtual source (at y = 0"++) [Ge01]. Indeed, the predicted channel transport of carriers in both DG devices is, as reflected by the carrier energies along LIM the channels, seemingly ballistic [Tau97]; but Ion < Ion in the pMOSFET means that the hole transport is only quasi-ballistic. The mentioned velocity overshoot is physically linked to high carrier mobility [Pin93], [GeOl], and the lower hole mobility is thus restricting the quasi-ballistic current in the pMOSFET. Interestingly, based on the results of Tables 2.2 and 3, we can infer that Ion of the DG nMOSFET would be a factor of -5 19 higher than that of the bulk-Si nMOSFET with the same tox (= 3 nm) and gate voltage overdrive. To better understand the results in Tables 2.1, 2.2, and 2.3, consider how Ion can be increased in a scaled device. Since tox scaling is limited due to gate tunneling [Tau98a] and VT(on) cannot be reduced due to Ioff considerations [Tau98a], Ion in Equation (2.1) cannot be increased via higher inversion-charge density (Qi); it can be increased only by increasing v(0+), which tends to be less than vT mainly because of surface scattering, reflected by the transverse field (Ex)-defined degradation of carrier mobility (g). For a bulk-Si MOSFET, Ex(O) (Ex at the surface) is expressed via Gauss's law as Qi Qd Ex(0) i (2.3) Es Es where Qd is the depletion charge density. For strong inversion, Qi in Equation (2.3) tends to predominate, but Qd can be significant in extremely scaled devices because the channel doping density is high (> 1018 cm-3) for SCE control. Thus, higher Ex(O) implies lower m, which limits v(O0+) directly, and further inhibits significant velocity overshoot (quasi-ballistic transport) near the drain [Tau97], which tends to increase the longitudinal field (Ey(O ) = v(O )/gt) near the virtual source. Thus, to get v(0+) near vT, Qd as well as Qi must be reduced, but lower Qi would seem to decrease Ion in Equation (2.1). 20 2.3 Double-Gate MOSFET This apparent dilemma in scaled MOSFET design seems to be avoided in DG MOSFETs fabricated in very thin Si films. Applying Gauss's law over half of the Si film of a symmetrical DG device, we get Ex(0) = (Qi(tot)+ Qd) Q( (2.4) 2F-S 8E where Qi(tot) = 2Qi is the total inversion-charge density; Qd in Equation (2.4) can be negligible if the Si-film body is lightly doped (-1015 cm-3), which is the case for the DG devices in Table 2.3. Predictions of Ex(0) vs. -Qi/q (per channel) for symmetrical DG and bulk-Si nMOSFETs, derived from SCHRED-2 [VasOO] simulations, are shown in Figure 2.5. Note that Ex(0) of the DG device is much lower than that of the bulk-Si counterpart. Furthermore, DG MOSFETs with ultra-thin Si bodies effectively suppress SCEs, and hence acceptable Ioff can be achieved with thicker tox. This implies even lower Ex(0) via lower Qi in Equation (2.4), but the two (electrically coupled) channels actually give higher Qi(tot). Hence, Ex can be quite low, rendering high mobility (subject to quantum-mechanical confinement effects in the thin Si film [Gdm98]) and yielding (in DG nMOSFETs) significant velocity overshoot with v(O0) vT (subject to Rs limitations) and high, near-ballistic Ion. The DG pMOSFET would need thicker tox because of the lower hole mobility. Note that scaling tox in the DG device would enhance Qi but lower mobility, thereby suppressing the overshoot effect; Io. would still be 21 2.0x106 1.5x106 1.0x106 Bulk-Si MOSFET 0.5x106 DG MOSFET 0 I I*I I I I I I I 1011 1012 1013 -Qi/q (cm-2) Figure 2.5 SCHRED-2 [Vas00]-predicted transverse surface electric field versus inversion-charge density (per channel) for bulkSi (Nchannel = 1018 cm-3) and symmetrical DG (Nchannel = 1015 cm-3, tsi = 5 nm) nMOSFETs. 22 high, but vT would not be reached. Often, the optimal design should exploit overshoot, thereby yielding ballistic-limit Ion with acceptable Ioff. Such design would directly enhance intrinsic CMOS speed governed by the delay (t 1/v(0+)) of unloaded inverters. For loaded circuits, thinner tox for DG CMOS can improve the speed performance (t CloadVDD/Ion) even if Ion does not reach the ballistic-limit current. 2.4 Conclusions To achieve the ultimate ballistic-limit current, velocity overshoot near the drain must be exploited by reducing the transverse field-induced degradation of mobility and increasing the longitudinal electric field near the source. Optimally designed DG MOSFETs with controlled Ioff can potentially yield the ultimate ballistic-limit current, but this is not the case for extremely scaled bulk-Si or (partially depleted) SOI MOSFETs due to the high transverse field caused by high gate-induced surface charge density. CHAPTER 3 MODELING AND INCORPORATION OF TUNNELING CURRENTS IN UFSOI MOSFET MODELS 3.1 Introduction Off-state current (Ioff) in SOI MOSFETs is one of the major issues for contemporary low-voltage/low-power VLSI circuit applications [Fos98c]. Since gate-induced drain leakage (GIDL) and reverse-bias junction tunneling currents can significantly govern Ioff, it is important to understand the physics of the tunneling currents and to be able to predict their severity. The modeling studies of GIDL current [Che87], [Ned91], [Wan95] and reverse-bias junction tunneling current [Sto83] that have been done previously are either empirical or too complicated to be used for engineering design. Reliable compact, but physical models for the currents in SOI MOSFETs are thus needed for IC design. In this chapter, we give an in-depth discussion about these issues in three parts. The first part of this chapter focuses upon physical modeling of GIDL current and reverse-bias junction tunneling current, based on quantum-mechanical tunneling theory [Kan61]. Then, model verification is discussed based on data from SOI device measurements. Finally, circuit applications with upgraded UFSOI models in SOISPICE [Fos98a] are exemplified by simulations of an SOI CMOS ring oscillator, 23 24 the results of which give physical insight into SOI CMOS performance projection regarding speed and power as influenced by the tunneling currents. 3.2 Model Developments 3.2.1 Gate-Induced Drain Leakage Current With Figure 3.1, GIDL current in scaled SOI nMOS devices is explained as follows. Valence band electrons of the p-type body, for VBD < 0, can tunnel directly into the conduction band of the drain under the condition of inversion somewhere in the gate-to-drain overlap region (W(DL)/2), as illustrated in Figure 3.2. For VBD 2 0 in Figure 3.1, the tunneling can not occur because the valence band can not reach above the conduction band in the neutral region, Ec(-); Ev(O) is pinned at EFp(O) < Ec(o), and there is no band-band overlap for tunneling. But for VBD < 0, the hole quasi-Fermi level could be higher than Ec, for which the valence band can reach above Ec(o); hence the tunneling can occur. In order to model the tunneling current, we first need to define the tunneling probability, which we can do by assuming one-dimensional band-to-band tunneling with Wentzel-Kramers-Brillouin (WKB) approximation [Sze81] through a parabolic potential barrier: p exp( 2J2 m* 3/2 P = exp( 12nEg /2qhEx) [Kan61] where Eg is the bandgap of the semiconductor, mn is the effective mass for tunneling electrons, and Ex (< 0 as indicated in Figure 3.1) is the electric field across the tunneling 25 bre - - - - - - Oxide E, 40 0 x Figure 3.1 Energy band diagram for tunneling process of GIDL current. Electrons (point) in the valance band tunnel across the forbidden tunneling barrier into the conduction band. 26 DL/2 VG < OV (DL)eff/2 inversion region electron B tunneling process -- VD > OV *--------* 5 D' D p-body n+-drain BOX Figure 3.2 GIDL mechanism shown in an SOI nMOS device. An inversion is formed among the gate-to-drain overlap region as VGD decrease, and then tunneling process continues with electrons supported from the body. Therefore, electrons (points) flow via B, B', D', and D in the figure. 27 barrier. Then, the tunneling current density is derived from the theory of field-enhanced tunneling [Kur89], [Sze81] by accounting for occupied initial states in the valance band, which are above Ec(o), and empty final states in the conduction band [Wan89]: r2 -* 3/2 JqmnEg(-qVBD) -Ex (2 2m J 3/2 exp n g (3.1) h3 2 E3/2 2qhEx 2qh where JT is zero at VBD = 0 as implied in Figure 3.1. Since Equation (3.1) is not applicable when VBD is positive, we use a smoothing function [McA91] for VBD to turn off the tunneling current for VBD > 0: In(1 + exp(-BVBD)) (3.2) VBD = VBDO- B (3.2) where VBDO = ln(2)/B, which forces VBD to zero for VBD = 0; B (= 50) is a constant. In fact, the GIDL tunneling process, as illustrated in Figure 3.2, must be detail-balanced by its inverse process in thermal equilibrium (VBD = 0). As shown in Figure 3.3, the smoothing function in Equation (3.2) approaches VBDO (= 13.9 mV) for VBD > 0, which makes JT in Equation (3.1), with VBD replaced by VBD, negligible. For VBD < 0, VBD approaches VBD, and thus enables JT. In order to model the GIDL current, we must know the crosssection area for the tunneling current. As depicted in Figure 3.4, the net doping density varies from zero at the body-drain metallurgical junction 28 VBDO 0.0 ------ -- -- --- -0.2 -0.4 -0.6 -0.8 1 .0 .. . . -1.0 -0.5 0.0 0.5 VBD (V) Figure 3.3 Smoothed VBD used to give a general characterization of GIDL current for all values of VBD. Note that VBD = 0 at VBD = 0. 29 I I (DL)Le/f2 highly doped drain actual GIDL region: y = Lmet 0 y DL/2 Figure 3.4 The variation of the net doping density (Nnet) in gate/drain overlap region. The value of Nnet approaches to zero at the metallurgical junction (y = Lmet) and the value of Nnet, to that of the drain doping density (NDs) at y = Lmet + DL/2. 30 (y = Lmet) to a very high level (NDs) inside the drain region. Consequently, the onset of GIDL current occurs in some region (W(DL)efV2) between the metallurgical junction (y = Lmet) and y = (Lmet + DL)/2, as shown in Figure 3.2, when the band banding (> Eg) and a relatively small voltage difference between gate and drain can cause inversion. Therefore, with Equation (3.1), the GIDL current equation is formulated as (DL)eff7qmnEg(-qVBD) -EsD ( 2mnE 3/2 IGIDL 2 h3 2 3/2e 2qhEsD 2qh where W(DL)efV2 is the effective area over which GIDL current occurs, and Ex = EsD is assumed to be the vertical electric field at the silicon surface. Indeed, the maximum band-to-band tunneling current occurs in the high-field region which is located at the surface [Che87]. As shown in Figure 3.5, the voltage relation for the SOI MOSFET D D applies to the gate-to-drain overlap region: VGD-VFB = sD -Qi/Coxf D where Qsi = -ESiEsD by Gauss's law. Then, we derive the electric field EsD with the assumption that the surface potential 1VsD (< 0) is pinned near the (-Eg/q + VBD) when GIDL current occurs: D E VGD- VFB + VBD EsD 3toxfq (3.4) so 3t v, 31 -qVoxf Ec EFG- E, -qVGD -qVsD e Ec EFn (= EFP) Ev Figure 3.5 The energy band diagram between gate and drain for tunneling process of GIDL current (from B' to D' in the Figure 3.2. 32 where esi/ox_= 3 has been used. In the UFSOI models, the flatband D voltage VFB in Equation (3.4) is modeled as D D Qff 1-TPG Qff VFB MS C o (Eg/q) (3.5) where Qff is the fixed charge density at front Si-SiO2 interface and TPG is a UFSOI model parameter designating the gate material: TPG = 1 for opposite types of doping in gate and body and TPG = -1 for the same type of doping in gate and body. Equation (3.5) applies to nMOS devices; for pMOS devices, the sign of the first term on the right-hand side is negative. Since Equation (3.4) can only be applied when EsD is negative (i.e., toward the surface), we re-characterize the electric field at the surface, using another smoothing function [McA91] for VGD to keep the effective EsD negative and to force IGIDL to zero as VGD increases: VGD VFB + -g VBD EsD t, (3.6) 3toxf with In(1 + exp [-C(VGD VGDO) ) VGD = VGDO C (3.7) where VGDO is the value of VGD which forces EsD in Equation (3.6) to zero: D E9 VGDO VFB + VBD ; (3.8) q 33 C (= 5) is a constant. Small value for C is used to get a smooth variation of EsD near VGDO, as illustrated in Figure 3.6. The smoothing function in Equation (3.7) approaches VGDO for increasing VGD, which means EsD and IGIDL go to zero; and it approaches VGD for decreasing VGD, which makes EsD < 0 and enables IGIDL. The smoothed electric field in Equation (3.6), which renders a general characterization of IGIDL in Equation (3.3) for all VGD, is illustrated in Figure 3.6. Therefore, we model the GIDL current as GDLiqmnEg(-qVBD) -EsD ex fBGIDL) (39) IGIDL-- 2 3 BIexp (3.9) h GIDL EsD where VBD and EsD are smoothed as defined by Equations (3.2) and (3.6), respectively. The uncertainty of the effective DL/2 ((DL)efj2) in Equation (3.3), which depends on the drain-extension doping profile, is absorbed by a model parameter BGIDL: 2 E- 3/2 B =g (3.10) BGIDL 2qh (3.10) thus DL/2 is used directly in Equation (3.9). We incorporate the GIDL current in the UFSOI models [Fos98a], and further apply it to a 0.35 gm NFD/SOI nMOSFET for demonstration. Model-predicted IGIDL, reflecting VGD and VBD dependences, is shown in Figure 3.7. IGIDL is a strong function of VGD and VBD due to the exponential dependence of the field. IGIDL increases for decreasing VGD 34 EsD D EsD (actual) VFB / VGDO / VGD Figure 3.6 Smoothed surface electric field used to give a general characterization of GIDL current for all values of VGD. The actual field (dashed curve) is zero at VFB, whereas the smoothed field goes to zero as VGD increases and VGD in Equation (3.7) approaches VGDO. 35 10-13 VDS = 1.8 V ICH (channel current) IGIDL 10-15 -1.0 -0.5 0.0 VGfS (V) (a) 10-14 VGfD = -1.5 V I S10-15 GIDL IGt (thermal generation current) 10-16 -1.0 -0.5 0.0 VBD (V) (b) Figure 3.7 Model-predicted (a) IDS-VGfS and (b) IBD-VBD characteristics of a 0.35 gm NFD/SOI nMOSFET; oxide thickness (toxf) = 5.6 gm and BGIDL = 3.3x109 V/cm. The characteristics reflect the bias dependence of IGIDL where it is predominant. 36 due to higher (negative) field from Equation (3.6). However, IGIDL decreases for decreasing VBD, which yields more band-band overlap for tunneling as illustrated in Figure 3.1 but lower (negative) field from Equation (3.6). Note that the low current for very negative VBD in Figure 3.7(b), which is nearly constant, is predominantly thermal generation current in the UFSOI models. The GIDL current can be combined with impact-ionization current in the UFSOI models [Fos98a] because both of the currents are related to drain. For the double-gate devices [Fos98b], [Fra92], additional GIDL current for the back surface, modeled analogously, is summed with Equation (3.9) in the UFDG model [Chi01]. In Chapter 4, more discussion about GIDL current in DG devices is given. 3.2.2 Reverse-Bias Junction Tunneling Current Experimental data of highly doped SOI MOSFETs show high leakage current beyond thermal generation current and GIDL current. When the body doping density exceeds -1018 cm-3, the possibility of reverse-bias junction tunneling current should be considered [Sto83]. In SOI devices, the predominant reverse-bias junction tunneling current occurs by trap-assisted mechanism [Fos85], since many traps are created near the back-gate oxide by the processing of SOI devices [Fos85]. As shown in Figure 3.8, for the drain junction, we assume that there is no thermal emission during the trap-assisted tunneling mechanism, which yields in the steady state [Fos85] 37 p-type body n+-type drain Et EF EFp E p j(Eg + qVDB) (Et Ev) qVDB (Ec Et) O.. . EFn Ecn dIv; -Et d(-ITC) Evn E, WD y(E)vp y(Ecn) Emax ------------------------------------Figure 3.8 Energy-band diagram and lateral electric field near neutral body-to-drain junction. 38 qWtefNTady dITV d(-ITc) qW N dy (3.11) tTV + tTC where ITV and ITC are the field-emission currents of holes from the traps to the valence band in the body and electrons from the traps to the conduction band in the drain; NTR is a trap density, and 'TV and TTC are the time constants for electron and hole tunneling. Wteff in Equation (3.11) is the effective tunneling cross-section area. Figure 3.9 shows the assumed structures in the UFSOI NFD model formalism. The area of the reverse-bias junction tunneling current can be assumed as the neutral body-to-drain junction area (W(tf- tb)) for retrograded doping profiles and the halo-doped body-to-drain junction area (Wthalo) for halo structures [Fos98a]. Since the tunneling process, which is described minutely in Figure 3.8, is predominantly through the depletion region (y(Evp) y < y(E,,)), the tunneling current can be expressed as T(REV) d qWteN dy (3.12) y(Ev) dIv WteffNTRy(E,) TTV + TTC where the tunneling time constants are derived from Wentzel-KramersBrillouin (WKB) approximation, assuming a triangular potential barrier [Gro84]: 8 2 (Et-E)3/2 (3.13) TTV TOVexp (3qhEy (3.13) 39 Gf S D NBL tb NDS NDS (a) Gb Gf IsID NLDD NLDD tf NDS NDS thalo (b) Gb Figure 3.9 UFSOI NFD device structures: (a) without halo-doped body and (b) with halo-doped body. 40 and "TC toc exp(_ 3qhE ; (3.14) TOV and Toc are the values of the effective carrier transit times in the valance and conduction band (yov = oc 10-12 s) [Gro84], mp and mn are the effective masses for the tunneling holes and electrons (m = mn = 0.2mo [Gro84] where mo is the free electron mass), and Ey (< 0 as indicated in Figure 3.8) is the electric field across the tunneling barrier. By assuming that traps are located at a mid-gap, and the values of the tunneling effective masses for electrons and holes are the same [Gro84], we can expect that the time constants for electrons and holes in Equations (3.13) and (3.14) are the same: Teff =ovexp BE V) = TTV = tTC (3.15) In Equation (3.15), BTREV is a probability coefficient defined as S8 2mp(Eg/2)3/2 BTREV 3qh (3.16) By combining Equations (3.12) and (3.15), we get IT(REV) qWteffNTR(E) dy (3.17) y(Evp) 2teff 41 Since reff depends exponentially upon Ey, the value of reff changes rapidly in the depletion region (y-direction), as shown in Figure 3.10. The meanvalue theorem for definite integrals is applied in order to make a closedform solution for the tunneling equation: y(Ec,) dy Ayeff (3.18) Jy(Ep) 2reff min eff in where Ayeff is defined as the region in which teff < 10emff In Equation (3.18), rinf is estimated when Ey has the maximum value (Emax): n (BTREV\ efn t- ovexp E ) (3.19) eff Emax To make an analytic expression for Equation (3.18), we first differentiate Equation (3.15) with respect to Ey: TeffBTREV Aeff = 2 A~E (3.20) and then apply Poisson's equation: qNBHEFF AE = NBHEFFAy (3.21) ESi By combining Equations (3.20) and (3.21) with the mean-value theorem as min min indicated in Figure 3.10 (Areff 10teff which is applied near ueff where Ey approaches Emax), we get 42 teff A Yeff Areff -10mmin lfteff mmn eff --- ---------------- y y(Ep) y(Ecn) (a) (Teff)-1 A Yeff my y(Evp) y(Ecn) (b) Figure 3.10 The variation of effective time constant (seff) along the region where the hole tunneling process occurs: (a) 'eff versus y and (b) (eff)-1 versus y. 43 Ae22 2 Ayeff SEi AeffE Y Si 10Emax (3.22) Yeff = qNBHEFFBTREV Teff min qNBHEFF BTREV Teff = eff, Ey = Emax where, in the UFSOI/NFD model [Fos98a], [Wor99], NBHEFF is NBH for non-halo structure and NHALO for halo structure, as shown in Figure 3.9. Now, the reverse-bias junction tunneling current is modeled analytically from Equations (3.15), (3.16), (3.17), (3.18), and (3.22): max BTREV IT(REV) = effr T exp E (3.23) ITREV) = WtefNBHEFFTOVB TREV max The maximum electric field across the tunnel barrier occurs close to the body-to-drain metallurgical junction, as shown in Figure 3.8, and is modeled as 2( + VDB Emax WD (3.24) where WD in Equation (3.24) is estimated by the depletion approximation: 2eSiND + NBHEFF E 2Si + VDB WD = + VDB (3.25) q NDNBHEFF Kq q q NBHEFF The tunneling process is detail-balanced by its inverse process in thermal equilibrium (VDB = 0) [Sze81l]. Therefore, the tunneling current in Equation (3.23) is modified to force it to zero at VDB = 0: 44 5N, ESiEmax BTREV IT(REV)2 Wety T" maexp REV O (3.26) BHEFFOVB TREV max where 10 IT(REV) = WteN B exp iBv, teff5N TR sE0 BTREV T(REV) VDB = 0V eNBHEFFCOVBTREVexp( Eo and Eo _-2(E IT(REV) in Equation (3.26) is combined with generation/ recombination currents in UFSOI models because both of the currents are derived from junction regions, of both the source and drain sides. One tuning parameter (NTR) is used for the IT(REV) model. Actually, we do not know how many traps there are, where traps are located, nor the exact value of the tunneling effective mass. These uncertainties for the actual device structure turn out one parameter (NTR), an "effective" trap density, since we assume that traps are located at mid-gap and the value of effective tunneling mass is 0.2mo when we estimate BTREV in Equation (3.16). 3.3 Model Implementation/Verification The models for GIDL current and reverse-bias junction tunneling current were implemented in the UFSOI models in SOISPICE and 45 SPICE3 [Fos98a]. The network representation of the UFSOI FD and NFD models is shown in Figure 3.11. The GIDL current is combined with the impact-ionization current, and the reverse-bias junction tunneling current (in the NFD model only) is combined with recombination/ generation currents from both the source and drain junctions. One parameter for each tunneling current, BGIDL and NTR, respectively, is good for device designers to tune to their technologies. By the symmetrical nature of MOSFETs, gate-induced source leakage (GISL) current can occur, which could be important for some applications such as pass transistor; GISL is a subject of future work (suggested in Chapter 6). In order to verify the model of GIDL current, the actual calibration to a real SOI technology is demonstrated. A 0.14 gm NFD/SOI technology with very scaled gate oxide (tox = 2.5 nm) is used for the study of GIDL current. As shown in Figure 3.12, the GIDL current in UFSOI models is quite consistent with measurement data. We have found that the tuned value of BGIDL does not vary much, always being close to the theoretical prediction. Typically, BGIDL 3-6x107 V/cm. The model is now applied to a NFD/SOI technology to verify the validity and efficiency of the model of the reverse-bias junction tunneling current with measurement data. Adequate value of parameter NTR is 1014 cm-3 for a 0.15 gm NFD/SOI MOSFET, as shown in Figure 3.13. Based on parameter evaluation of the 0.15 gm NFD nMOS SOI technology, the reverse-bias junction tunneling current in UFSOI models for a 1 um NFD 46 ICH IBJT I4 Gf dQGf dQS dt dQD VLDD Rs + RLDS D" RD+ RLDD S S d D D dQB dQGb dt dt Gb IGi + IGIDL B9 IRGtS IT(REV)S IRGtD + IT(REV)D RB B Figure 3.11 Network representation for new UFSOI FD and NFD models [Suh95b], [Wor991. Note that IT(REV) is only in NFD model. 47 10-2 L/W = 0.14 gm/10 gm 10-4 VDS = 1.8 V 10-6 10-8 / 0*, 10-10 , w/ GIDL 10-12 -- - - w/o GIDL 10-14 -1.0 -0.5 0.0 0.5 1.0 VGfS (V) Figure 3.12 Measured (points) and UFSOI-predicted current-voltage characteristics of a 0.14 gm NFD/SOI nMOSFET showing the GIDL-current calibration. Note that for decreasing VGfS, the data appear to be approaching the predicted GIDL-controlled current. 48 10-2 10-4 10-6 SNTR 10-8 10-10 L/W = 0.15 pm/10 pm VDS = 1.5 V 10 -12 , , -0.5 0.0 0.5 1.0 VGfS (V) Figure 3.13 Measured (points) and UFSOI-predicted current-voltage characteristics of a 0.15 gm NFD/SOI nMOSFET for increasing a parameter NTR (= 0, 1013, 1014, 1015 cm-3) systematically. Evaluated value of NTR is 1014 cm-3 in this device. 49 nMOS SOI MOSFET, from the same technology as the 0.15 gm device, shows good agreement with measured data as shown in Figure 3.14. Reverse-bias junction tunneling current increases Ioff, and drive current via a floating-body effect. Note that the high tunneling current would overwhelm kink effect, as indicated in Figure 3.14(b). GIDL current goes up rapidly as front-gate bias (VGfS) decreases, but the reverse-bias junction tunneling current is independent of VGfS. In other words, the vertical electric field is dominant mechanism for GIDL current and the lateral electric field mainly defines the reverse-bias junction tunneling current. Figure 3.15 illustrates IBS-VGfS characteristics in a 0.21 jm body-tied source NFD/SOI device, which clarifies that UFSOI MOSFET models with GIDL current and reverse-bias junction tunneling current enhance the predictive capability. Figure 3.16 shows IDS-VGfS characteristics for NFD/SOI pMOSFETs with floating body and body-tied source; UFSOI models are in good agreement with measured data showing significant GIDL and reverse-bias junction tunneling currents. 3.4 BJT Amplification by Tunneling Currents In floating-body SOI MOSFETs, the GIDL current and reversebias junction tunneling currents are amplified by the parasitic BJT [Che92]. If IGIDL represents the actual GIDL current resulting from carrier tunneling in the drain junction under the gate overlap, as modeled in Section 3.2.1, then the component of drain current driven by GIDL is 50 10-3 10-6 10-9 10-12 * L/W = 1 gm/lO gm 10-15 -0.5 0.0 0.5 1.0 1.5 VGfS (V) (a) 1.2 0.9 0.6 ,. ---------- . * 0.3 * 0.0 0.0 0.5 1.0 1.5 VDS (V) (b) Figure 3.14 Measured (points) and UFSOI-predicted current-voltage characteristics of a 1gm NFD/SOI nMOSFET with IT(REV) (solid curve) and without IT(REV) (dashed curve): (a) IDS-VGfS at VDS = 0.05, 1.5 V, (b) IDs-VDs at VGfS = 0.5, 0.75, 1.0, 1.25, 1.5 V. 51 10-9 L/W = 0.21 gm/10 gm 10-10 10-11 I I 10-12 i Measured data W IGIDL + IT(REV) - w/ IGIDL, W/O IT(REV) - W/O IGIDL & IT(REV) 10-13 -1.0 -0.5 0.0 0.5 1.0 1.5 -VGfS (V) Figure 3.15 Measured (points) and UFSOI-predicted IBS (body-to-source current) versus VGfS for a 0.21 gm body-tied source NFD/SOI pMOSFET at VDS = -1.5 V. Evaluated value of NTR is 6.0x1014 cm-3 in this device. 52 L/W = 0.14 gm/10 gm 10-5 S10-9 / *Measured data w IGIDL + IT(REV) 10-11 w/ IGIDL, W/O IT(REV) - W/O IGIDL & IT(REV) 10-13. ----------1.0 -0.5 0.0 0.5 1.0 1.5 -VGfS (V) (a) 10-3 L/W = 0.21 gm/10 pm 10-5 10-7 10-9 / *Measured data S-- w IGIDL + IT(REV) 10-11 - W/IGIDL, W/O IT(REV) .- W/O IGIDL & IT(REV) 10-13 I I -1.0 -0.5 0.0 0.5 1.0 1.5 -VGfs (V) (b) Figure 3.16 Measured (points) and UFSOI-predicted current-voltage characteristics of NFD/SOI pMOSFETs at VDS = 1.5 V for (a) floating-body device and (b) body-tied source device. 53 IDS(GI GIDL + IGIDL (3.27) DS(GIDL) 1_ ) GIDL where P in the BJT current gain and M is the multiplication factor for impact ionization caused by the BJT current flowing through the highfield drain region [Kri96]. At the off-state condition, M is typically near unity, but (M-1) > 0 depending on VDS. Hence, if impact ionization is ignored, interpretation of measured off-state current due to GIDL can give erroneously high values of P as in [Che92]. Nonetheless, IGIDL is amplified as defined by Equation (3.27), and it must be considered in the design of extremely short (or narrow-base) MOSFETs including SOI devices. In the same way, we can write for reverse-bias junction tunneling current I IT(REV) + (3.28) IDS(T(REV)) = 1- B(M- 1) IT(REV) Figure 3.17 shows UFSOI-predicted current-voltage characteristics when the parasitic BJT is turned off and on. Indeed, the BJT, via Equations (3.27) and (3.28), is significant in defining IGIDL- and IT(REV)-controlled components of drain current in SOI devices. 3.5 Model Application to CMOS Circuit It is worthwhile to investigate the effects of the new models on circuit performance. We simulate an unloaded 9-stage CMOS inverter ring oscillator based on the calibrated model cards for 0.14 pm NFD SOI technologies, which are represented in Figures 3.12 and 3.16(a). As 54 10-6 10-7 L/W = 0.15 gm/10 Lm VDS = 1.5 V 10-8 10-9 w/ BJT 10-10 10-11 w/o BJT 10-12 .. . -1.0 -0.5 0.0 VGfS (V) Figure 3.17 UFSOI-predicted current-voltage characteristics with and without the parasitic BJT amplification for a 0.15 gim NFD/ SOI nMOSFET, as shown in Figure 3.13. IGIDL and IT(REV) induce a huge BJT current. 55 illustrated in Figure 3.18, simulated results for the circuit with both GIDL and reverse-bias junction tunneling currents tend to speed up the circuit, via the floating-body effect, by less than 5% for all the supply voltages, and the circuit consumes only 5% more dynamic power. However, for the NFD/ SOI technology as shown in Figure 3.13, reverse-bias tunneling current can significantly effect on circuit performance for high NTR as depicted in Figure 3.19. GIDL and reverse-bias junction tunneling currents cause more static power consumption due to increased Ioff. Figure 3.20 shows static power consumption versus VDD for the CMOS inverters. The static power is increased significantly, and hence the tunneling currents must be effectively controlled, especially for memory applications such as DRAM. Possible solution for suppressing the GIDL current would be the use of graded gate-oxide devices [Ko84] to reduce the electric field in Equation (3.6). Control of the reverse-bias junction tunneling current is still an issue for VLSI device scaling [GhaOO]. 3.6 Conclusions New physical models for GIDL and reverse-bias junction tunneling currents have been presented and implemented in the UFSOI MOSFET models. The device uncertainties for tunneling effective mass and contact area of the current turn out one parameter (BGIDL) for the GIDL current model, and the uncertainties for tunneling effective mass, 56 240 200 w/ IGIDL & IT(REV) - w/o IGIDL & IT(REV) 160 120 so g 80 400 0 0.50 0.75 1.00 1.25 1.50 VDD (V) (a) 6.0 w/ IGIDL & IT(REV) 5.0 - w/o IGIDL & IT(REV) 4.0 3.0 2.0 1.0 S0.0 0.50 0.75 1.00 1.25 1.50 VDD (V) (b) Figure 3.18 UFSOI-predicted (a) average propagation delay versus VDD and (b) average dynamic power consumption versus VDD of an unloaded 9-stage CMOS inverter ring oscillator with and without IGIDL and IT(REV). 57 33 I I I I I I 1.6 1.5 31 1.4 29 1.3 o 27 1.1 25 1.0 100 102 104 106 108 1010 1012 1014 1016 NTR (cm-3) Figure 3.19 UFSOI-predicted average propagation delay and dynamic power consumption versus NTR of an unloaded 9-stage CMOS inverter ring oscillator at VDD = 1.0 V. 58 10-7 w IGIDL + IT(REV) S- w/ IGIDL, W/O IT(REV) S---- w/o IGIDL & IT(REV) 10-8 U/ 10-9 0.25 0.50 0.75 1.00 1.25 1.50 1.75 VDD (V) Figure 3.20 UFSOI-predicted average static power consumption versus VDD for CMOS inverter. Both IGIDL and IT(REV) increase static power due to increased Ioff. 59 trap density, and trap location yield one parameter (NTR) for the reversebias junction tunneling current. The models are verified with experimental data from scaled SOI MOSFETs by using physically reasonable values for the parameters. For CMOS inverter circuits, propagation delay and dynamic power are not changed too much by GIDL and reverse-bias junction tunneling currents. However, both currents in SOI MOSFETs increase Ioff and hence static power consumption. They must be controlled by optimal device design. CHAPTER 4 DOUBLE-GATE CMOS 4.1 Introduction It is well known that the double-gate (DG) fully-depleted (FD) SOI MOSFET can extend the scaling limitation of FD/SOI technology beyond the 0.1 gm regime because of superior short channel-effect immunity [Fra92], [Fos98b]. In the first part of this chapter, we will examine the scalability of FD/SOI CMOS to indicate a need of significant technology innovation, i.e, DG devices, for viable FD/SOI CMOS in the future. In the second part of this chapter, a general comprehensive comparison between asymmetrical and symmetrical DG devices will be done. Numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical double-gate (DG) CMOS, utilizing n+ and p+ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons, only one of which is its previously noted threshold-voltage control. The most noteworthy result is that asymmetrical DG MOSFETs, optimally designed with only one predominant channel, yield comparable, and even higher drive currents at low supply voltages. The simulations further give good physical insight 60 61 pertaining to the design of DG devices with channel lengths of 50 nm and less. Finally, GIDL current in DG devices will be studied. A simulation-based analysis of extremely scaled DG CMOS, emphasizing the effects of GIDL, is described. Device and ring-oscillator simulations project an enormous performance potential for DG/CMOS, but also show how and why GIDL can be much more detrimental to off-state current in asymmetrical (n' and p+ polysilicon gates) DG devices than in the singlegate counterparts. However, the analysis further shows that the GIDL effect can be controlled by tailoring the back (p+-gate) oxide thickness, which implies design optimization regarding speed as well as static power in DG/CMOS circuits. 4.2 Scalability of Fully Depleted SOI MOSFETs For low-voltage/low-power integrated digital circuit applications, FD/SOI MOSFETs are potentially superior to partially depleted (PD) SOI counterparts due to their ideal subthreshold slope, high drive current and transconductance, and much reduced floating-body effects, but the advantages rapidly disappear as the channel length is shrunk to O.1gm, due to two-dimensional field fringing in the silicon film and back-gate oxide [Yeh95]. Such an effect causes threshold voltage (VT) falloff and increases off-state current (Ioff) significantly. In order to improve short-channel effects (SCEs), halo-doped structures have been suggested for bulk-Si and PD/SOI MOSFETs 62 [Chr85], but it is still unknown that halo doping is also beneficial for FD/ SOI MOSFETs. The MEDICI [Ava99] two-dimensional device simulator is used to investigate whether the conventional FD/SOI device can be applicable down to 0.1 m CMOS technologies with halo doping. Figure 4.1 illustrates 0.1 gm FD/SOI device structures: uniform doped FD/SOI and halo-doped FD/SOI nMOSFET, which are used in simulations. The two devices have the same front-gate oxide thickness (toxf = 3 nm), back-gate oxide thickness (toxb = 40 nm), and Si-film thickness (tsi = 40 nm). As shown by the simulation results in Figure 4.2, the increase of halo doping density significantly reduces Ioff by improving subthreshold slope and DIBL effect. But, the halo-doped FD/SOI MOSFET has floatingbody effects as shown in Figure 4.3. This means that halo-doped FD/SOI MOSFET has a quasi-neutral region similar to retrograded PD/SOI MOSFET. To maintain the FD condition, tsi must be decreased. Such scaling for halo-doped structure becomes prohibitive. Furthermore, in order to suppress Ioff to a reasonable value (< 10 nA/gm) for FD/SOI CMOS circuit application, the halo doping density needs to be higher than -3x1018 cm-3, as shown in Figure 4.2. However, such a high halo doping density causes significant degradation of the drive current (IDS), as indicated in Figure 4.3, due to the increased VT and the increased (body) depletion capacitance in SOI MOSFETs [Suh95]. Hence, the conventional FD/SOI MOSFET will not be useful with halo doping. Indeed, as suggested in [Yeh95], the FD/SOI CMOS technology appears to be unscalable. 63 S Gf D n++ P n++ --L- Gb (a) S Gf D n++ P [n Gb (b) Figure 4.1 Simulated 0.1 gm FD/SOI nMOSFET structures for (a) uniform doped FD/SOI MOSFET, (b) halo-doped FD/SOI MOSFET. 64 10-2 10"3 VDS = 1 V- 10-4 10-5 10-6 10-7 ...... w/o halo 10-8 10-9 NHALO = lx1018, 2x1018, 3x1018 cm3 10-10 -0.5 0 0.5 1.0 1.5 VGfS (V) Figure 4.2 MEDICI-predicted IDS-VGfS characteristics for 0.1 gm FD/ SOI nMOSFETs with varying halo doping density (Nhalo). 65 0.25 VGFS = 0.3 V 0.20 0.20 - - w/o halo 0.15- NHALO = 1x1018 cm3 P 0.10 2x1018 cm0.05 3x1018 cm-3 0 0.5 1.0 1.5 2.0 VDS (V) Figure 4.3 MEDICI-predicted IDS-VDS characteristics for 0.1 m FD/ SOI nMOSFETs with varying halo doping density (Nhalo). 66 4.3 General Comparison of Symmetrical and Asymmetrical Double-Gate Devices In contrast to conventional FD/SOI devices, as well as PD/SOI and bulk-Si devices, DG MOSFETs, having very thin Si-film bodies, will, because of their near-ideal intrinsic features, quite possibly constitute the CMOS technology of the future as the lateral scaling limit (Lmet 10 nm) is approached [Fra92]. In addition to the inherent suppression of shortchannel effects (SCEs) and naturally steep subthreshold slope, DG MOSFETs offer high drive current (Ion) and transconductance, generally attributed to the two-channel property of the symmetrical DG device [Won98]. More important, we believe, is the electrical coupling of the two gate structures through the charged Si film. This charge coupling underlies the noted features of the device, which translate to high Ion/Ioff ratios when the threshold voltage is properly controlled. Such control has been shown to be easily effected via asymmetrical gates of n+ and p+ polysilicon [Tan94], [Fos98b], which, however, would seem to undermine the current drive because the resulting device has only one predominant channel. Contrarily, we show in this chapter that the gate-gate coupling in the asymmetrical DG MOSFET is more beneficial than in the symmetrical counterpart, resulting in superiority of the former device for more reasons than just the threshold-voltage control. We rely on 2D numerical device simulations using MEDICI and its hydrodynamictransport option [Ava99], supplemented by a Schrodinger-Poisson solver (SCHRED-2 [Vas971, [VasOO0) and analytical characterization, to convey 67 insight regarding performance and design and to reveal the inherent superiority of asymmetrical DG CMOS. Predicted current-voltage characteristics of Lmet = 50 nm DG nMOSFETs are presented in Section 4.3.1, revealing comparable Ion in asymmetrical- and symmetrical-gate devices designed for equal Ioff at low supply voltages (VDD). Explanation of this surprising result is given in Section 4.3.2 using analytical characterizations of the basic DG MOSFET physics, which lead to simplified expressions for subthreshold slope and inversion charge integrated over the thin Si film. Additional potential advantages of asymmetrical DG CMOS are discussed in Section 4.3.3, giving good insight for optimal device design at 50 nm and below. 4.3.1 MEDICI Simulation Results We used MEDICI to simulate 50 nm DG nMOSFETs having abrupt source/drain junctions (i.e., Leff = Lmet = 50 nm [Tau98a]); the device structure is illustrated in Figure 4.4. The Si-film bodies are lightly doped (NA = 1015 cm-3) and quite thin (tsi = 10 nm), and the gate oxides are relatively thick (tox = toxf = toxb = 3 nm) for Ioff control. (Note that the SCE suppression inherent in DG MOSFETs [Won98] allows for thicker oxides than that needed for single-gate MOSFETs.) Predicted IDS-VGS characteristics of symmetrical (n+ polysilicon gates) and asymmetrical (n' and p+ polysilicon gates) DG devices, contrasted to those of the single-gate (SG: back gate grounded) counterparts, are shown in Figure 4.5. (The MEDICI-predicted currents for strong inversion are too high because the 68 x Gf Gb Figure 4.4 The (asymmetrical) double-gate MOSFET structure. For the asymmetrical device, the front and back gates are n and p polysilicon, respectively. For the symmetrical device, the gates can be n' polysilicon, but should have near-mid-gap work functions for off-state current control. 69 10-2 VDS = 1.0 V 10-3 10-4 10-8 S 10-7 Asymmetrical DG *--Symmetrical DG S--- Asymmetrical SG -s 0 Symmetrical SG 10-9 . . -0.5 0.0 0.5 1.0 1.5 VGS (V) Figure 4.5 MEDICI-predicted current-voltage characteristics of 50 nm asymmetrical (n+ and p+ polysilicon gates) and symmetrical (n+ polysilicon gates) DG nMOSFETs, contrasted to the characteristics of the single-gate (SG: back gate grounded) counterparts. (The strong-inversion currents are overpredicted, as discussed in the text of this chapter, but the relative values, and the subthreshold currents, are meaningful.) 70 carrier velocity overshoot, or energy-relaxation time, was simply defaulted and not calibrated. However, the relative values for the symmetrical- and asymmetrical-gate devices, and the subthreshold currents, which are not significantly affected by the overshoot, are meaningful.) Note the inherent SCE superiority (implied by the subthreshold slope) of the DG devices relative to their SG counterparts. The symmetrical DG nMOSFET, however, has an unacceptable (negative) threshold voltage. Pertinent comparison of Ion for the two DG device structures must be done for equal Ioff, for which the symmetrical MOSFET will need gate material with tailored work function (eM) and/or very high body doping density (-1019 cm-3) [Won98]. Such high doping density necessitates extremely thin tsi (< 5 nm) to ensure effective gate-gate coupling (or "full depletion" [Lim83]), and hence implies lower carrier mobility due to structural quantummechanical (QM) confinement [Gdm98] as well as impurity scattering. Furthermore, the energy-quantization effects due to the confinement become severe [Maj98]. Theoretically, a "near-mid-gap" gate material with fM = X(si) + 0.375Eg(si) will reduce loff to the noted equality as shown in Figure 4.6, where the predicted IDs-VGS characteristic of the so modified symmetrical-gate MOSFET at VDS = 1.0 V is compared with that of the asymmetrical-gate device. Interestingly, when the off-state currents are made equal, the on-state currents for both devices are comparable, even though the asymmetrical device has only one predominant channel (for 71 10-2 , Asymmetrical 10-3 Symmetrical VDS = 1.0 V 10-4 1.2 10-5 . 10-6 1 1.0 10-7 0 S0.9 10-8 0.5 1.0 1.5 VDD (V) 10-9 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VGS (V) Figure 4.6 MEDICI-predicted current-voltage characteristics of the modified symmetrical DG MOSFET, contrasted to that of the asymmetrical device of Figure 4.5; both devices have equal Ioff. The predicted VDD dependence of the asymmetrical/ symmetrical I,,on ratio for the DG nMOSFETs is shown in the inset. 72 low and moderate VGS) as revealed by the plots of its current components in Figure 4.7. The corresponding Ion(asym/Ion(sym) ratio, plotted versus VDD in the inset of Figure 4.6, is actually greater than unity for lower VDD. We attribute this VDD dependence to better suppression of DIBL [Tau98] in this asymmetrical device. Simulations of longer Lmet = 0.5 gm devices yield Ion(asym/Ion(sym) = 1, independent of VDD. For the longer devices, the predicted IDs-VGS characteristics are plotted on a linear scale in Figure 4.8 for low and high values of VDS. The near-equality of the currents in both devices is clearly evident. The MEDICI simulations are based on semi-classical physics with analytical accounting for quantization effects [Ava99]. To ascertain that the predicted symmetrical-versus-asymmetrical DG benchmarking results are not precluded by the effects of QM confinement of electrons in the thin Si film, we used SCHRED-2 [Vas97], [Vas00], a 1D (in x) selfconsistent solver of the Poisson and Schridinger equations, to check them. SCHRED-predicted areal electron charge density (Qc, which correlates with the channel current) versus VGS in both devices is plotted for VDS = 0 in Figure 4.9. Although the QM electron distributions across the Si film (with n(x) forced to zero at the two Si-SiO2 boundaries by the wavefunction conditions), shown in Figure 4.10 differ noticeably from the classical results, Qc is nearly the same in both devices, implying nearly equal currents as predicted by MEDICI. We hence are confident that the QM effects will not alter the main conclusions of our DG device benchmarking, which we now explain analytically. 73 10-2 10-3 VDS = 1.0 V 00000000 0 10-5 oo 0 0 o o 10-7 10-8 Total channel current 0 Front-channel current 10-9 o o Back-channel current 0 10-10 11 11 11 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VGS (V) Figure 4.7 MEDICI-predicted channel-current components (integrated over the front and back halves of the Si film) for the 50 nm asymmetrical DG nMOSFET. The back-channel current (with p+ gate) is not significant, but the front-channel current is enhanced by the gate-gate charge coupling and beneficial inversion-layer capacitance. 74 1.6 I *.I 1.4 Asymmetrical DG Symmetrical DG 1.2 VDS = 0.05 V, 1.0 V 1.0 0.8 0.6 0.4 0.2 0 0.0 0.5 1.0 1.5 VGS (V) Figure 4.8 MEDICI-predicted current-voltage characteristics of longerchannel (Lmet = 0.5 pm) asymmetrical and symmetrical DG nMOSFETs with the same structure as the devices in Figure 4.6. The currents are approximately equal for low and moderate VGS; for VGS > 1 V, the back-channel current in the asymmetrical device becomes significant, especially at high VDS (due to back-surface DIBL). 75 8x1012 - 2.0x10-6 Asymmetrical DG 0 a * Symmetrical DG . " 6x1O12 1.5x10-6 4x1012 1.0x10-6 2x1012 5.0x10-5 0I I 0.0 0.0 0.2 0.4 0.6 0.8 1.0 VGS (V) Figure 4.9 SCHRED-predicted integrated electron charge density in the asymmetrical and symmetrical DG nMOSFETs; VDS = 0. Also shown are the corresponding predicted VGs-derivatives of the charge densities. 76 2.5x1019 Asymmetrical DG -- Symmetrical DG 2.0x1019 VGS = 0.5 V, 1.0 V 1.5x1019 o 1.0x1019 0.5x10l9 0.0 0.0 2.0 4.0 6.0 8.0 10.0 x (nm) Figure 4.10 SCHRED-predicted electron charge density (-Qc(x)/q) across the Si film of the asymmetrical and symmetrical DG nMOSFETs; VDS = 0. 77 4.3.2 Analytical Insights To gain physical insight and explain the surprising benchmark results presented in Sec. II, we begin with a first-order analytical solution of Poisson's equation (ID in x) applied to the thin Si-film body. For a general two-gate nMOSFET with long Lmet at low VDS, assuming inversion-charge sheets (ti = 0) at the front and back surfaces of the fully depleted Si film, we have [Lim83] VGf = VFBf + + Cb Qf (41) CBf of/s of Cof 2Cof (4.1) and Cb + Cb s Qcb Qb (4.2) ob obl'sb (4.2) VGbS = VFBb obsf +1 + Cob 2Cob where VGfs and VGbS are the front and back gate-to-source voltages, VFBf and VFBb are the front- and back-gate flatband voltages, Wsf and NVsb are the front and back surface potentials, Qcf and Qcb are the front- and backsurface inversion charge densities, Qb = -qNAtsi is the depletion charge density, Cof = Eox/toxf and Cob = Eox/toxb are the front- and back-gate oxide capacitances, and Cb = Esi/tsi is the depletion capacitance. By setting VGS = VGfS = VGbS (implying no gate-gate resistance [Fos98b]) and eliminating the Isb terms from Equations (4.1) and (4.2), we derive the following expression for the DG structure: 78 1 +__ Qb 1 (4.3) VGS = Wsf + +(VFBf + rVFBb) +f r_ (Qb+ r2ob (4.3) where r is a gate-gate coupling factor expressed as CbCob 3toxf Cof(Cb + Cob) 3toxb + tSi (4.4) the approximation in Equation (4.4) follows from SSi/Sox = 3. Note that r decreases with increasing tsi. 4.3.2.1 Subthreshold Slope Since Equation (4.3) applies to a general DG device structure, it implies that both the asymmetrical- and symmetrical-gate devices should have near-ideal subthreshold slope, or gate swing: S = n(10) GS- 60mV (4.5) q dWsf because, with Qcf and Qcb negligible for weak inversion, dVGs/dxVsf = 1. The Lmet = 0.5 pm simulation results in Figure 4.8 are in accord with this result. The 50 nm devices in Figure 4.6 show S = 65 mV for both devices, greater than 60 mV (at T = 300 K) due to mild SCEs (which subside for thinner tsi). The gate-gate coupling, implicit in Equation (4.3), underlies the near-ideal S in the DG MOSFET. So, as is evident in Figure 4.6, the asymmetrical DG MOSFET current tracks that of the symmetrical counterpart as VGS is increased 79 from the off-state condition where the currents are equal, in accord with Equations (4.3)-(4.5). We now have to explain why this tracking continues, in essence, into the strong-inversion region as illustrated in Figure 4.8, and as implied by the electron charge densities Qc(VGs) in Figure 4.9. 4.3.2.2 Strong-Inversion Charge Effects of finite inversion-layer thickness (ti) [Tau98a] on Qc(VGs) in DG devices are quite important. For the symmetrical DG (nchannel) device, the effective ti(sym) (for the front and back channels) is defined by integrating the electron density over half of the Si film [L6p00]: tsi/2xn(x)dx t() 2q tsi/2 xn(x)dx ; (4.6) ti(sym)- ts/2 n(x)dx Qc(sym) d Jo and the total Qc(sym) is analytically expressed by combining Poisson's equation and Gauss's law [L6p00]: Qc(sym) = -2CGf(sym)(VGs VTf(sym)) (4.7) where CGf(sym) = Cof Cof (4.8) 1 + of 1+ li(sym) Ci(sym) 3 toxf is the total front-gate (or back-gate) capacitance, and 80 VT(sym) = v ofGfS- 1+ Cf (4.9) 2) 2CGf 4- F tsi is a nearly constant threshold voltage for strong-inversion conditions [L6p00]. In Equation (4.8), Ci(sym) = Ei/ti(sym) represents the (front or back) inversion-layer capacitance, -(dQc(sym)/df)/2 [Tau98]. The factor of 2 in Equation (4.7) reflects two identical channels and gates. Relative to the single-gate device, for which CGf could differ from CGf(sym) slightly, we thus infer an approximate doubling of the drive current, but exotic gate material is needed as noted in Sec. 4.3.1. For the asymmetrical DG (n-channel) device, we define the effective ti(asym) (for the predominant front channel) by integrating the electron density over the entire Si film: ti(asym) Sxq ixn(x)dx (4.10) ti(asym) n(x)dx Qc(asym)J To derive the counterpart to Equation (4.7), we first write the 1D Poisson equation as d xd q x(n(x) + NA)+ d+ (4.11) dx dx esi dx Integrating Equation (4.10) across the entire Si film yields 81 Qc(asym) Qb (4.12) i(asym) b where Esb I is the electric field at the back surface. x = tsi The gate-voltage (Faraday) relations for the DG MOSFET structure are VGfS = sf + Vof (GfS (4.13) and VGbS = sb + Vob+ (GbS (4.14) where Vof and Vob are the potential drops across the front and back oxides, and (PGfS and (GbS are the front and back gate-body work-function differences. Applying Gauss's law across the entire Si film of the asymmetrical device, we get (for no interfacial charge) Vof = Cof (iEsb Qc(asym) Qb) ; (4.15) oof and applying Gauss's law to the back-surface, we get ESiEsb sVobb (4.16) Cob Now, by setting VGS = VGfS = VGbS in Equations (4.13) and (4.14) and eliminating Ysb and Eshb from Equations (4.12), (4.14), (4.15), and (4.16), we finally derive the integrated electron charge expression: 82 Qc(asym) -CGf(asym)(1 + r)(VGs VTf(asym)) (4.17) where Co C CG ) of of (4.18) Gf(asym) C 1 rti(asym) Ci(asym) 3 toxf partly defines the total front-gate capacitance, and 1 Qb Qb VT(asym) = Vsft1 + 1 [ GfS + rGbS) ( of (4.19) is a nearly constant threshold voltage for strong-inversion conditions. In Equations (4.17)-(4.19), r > 0, defined in Equation (4.4) by a charge-sheet analysis, reflects the benefit of the "dynamic threshold voltage" [Lim83] of the asymmetrical DG MOSFET due to the gate-gate charge coupling. This effect is preempted in the symmetrical DG device because of the (backchannel) inversion charge, which shields the electric-field penetration in the Si film and pins Ysb. For the particular asymmetrical device simulated, r = 0.47. We note further in Equations (4.17) and (4.18) the dependence of Qc(asym) on ti(asym), different from the ti(sym) dependence in Equations (4.7) and (4.8), which reflects an additional benefit due to the n(x) distribution in the Si-film channel. By comparing Equation (4.18) with Equation (4.8), which are illustrated by the SCHRED-predicted -dQc/dVGS plots included in Figure 4.10, we see that for finite ti(asym) and ti(sym), which are 83 comparable (classically as well as quantum mechanically), CGf(asym) > Cof whereas CGf(sym) < Cof. The latter inequality for the symmetrical device is the well known effect of finite inversion-layer capacitance [Tau98], as characterized in Equation (4.8): An incremental increase in VGS must support an incremental increase in the potential drop across the inversion layer, at the expense of the increase in -Qc(sym). (Note that the inversionlayer potential drop is zero when ti = 0 and Qc is a charge sheet.) The former inequality for the asymmetrical device, however, is unusual. It can be explained by referring to the predicted transverse electric-field variations (Ex(x)) across the Si film (channel) shown in Figure 4.11 for the asymmetrical and symmetrical devices. The fact that Ex(x=tsi/2) = 0 always in the symmetrical device underlies the noted, detrimental (regarding current and transconductance) inversion-layer capacitance effect. However, in the asymmetrical device, typically Ex(x) > 0 everywhere, but an incremental increase in VGS will, while increasing Ex(x=O), decrease Ex(x=tsi) (-Esb in Equation (4.12)), ultimately forcing Esb < 0 as in Figure 4.11 where VGS = 1.0 V. This field perturbation results in an incremental decrease in the potential drop across the Si film (inversion layer), and hence more increase in -Qc(asym) as reflected by Equation (4.18). For the particular DG devices simulated, CGf(asym/ CGf(sym) = 1.21 at VGS = 1.0 V, and this ratio is even larger for lower VGSQuantitatively, the two noted benefits to Qc(asym) yield Qc(asym)/ Qc(sym) = 0.88 at VGS = 1.0 V, which is consistent with Figures 4.9 and 84 6x105 4x105 2x105 Asymmetrical DG 0 -2x105 Symmetrical DG -4x105 VDS = 0 V VGS = 1.0 V -6x105 , , , , 0 2 4 6 8 10 x (nm) Figure 4.11 MEDICI-predicted transverse electric-field variations across the Si film (tsi = 10 nm) of the asymmetrical and symmetrical DG nMOSFETs. Note that the field in the symmetrical device is always zero at the center of the film (x = tsi/2). 85 4.11, and with Figure 4.8 when small differences in average (MEDICImodeled, based on n(x) and Ex(x) as shown in Figure 4.11) electron mobility in the two devices are accounted for. We conclude then that the near-equality of the currents in the asymmetrical and symmetrical DG devices is due to the extended gate-gate charge coupling, characterized by r, which underlies near-ideal subthreshold slope in Equation (4.6) and the (1 + r) enhancement of Qc(asym) in Equation (4.17), and to the reverse inversion-layer capacitance effect on CGf(asym) in Equation (4.18) in contrast to the (common) detrimental one on CGf(sym) in Equation (4.8). We thus infer for the asymmetrical DG MOSFET a near-doubling of the drive current, and conventional polysilicon gates are adequate. Note further in Equations (4.17)-(4.19) the possibility for structural design optimization of the asymmetrical device, which is not possible for the symmetrical device as evident in Equations (4.7) and (4.8). 4.3.3 Asymmetrical DG CMOS For the low supply voltages anticipated for highly scaled DG CMOS, the high current drive which, based on the analysis herein, can be anticipated for asymmetrical DG MOSFETs, and their inherent design flexibility for controlling parasitics such as gate-overlap capacitance, gate "underlap" [Won94], gate-gate resistance [Fos98b], and GIDL (which could be a show-stopper for symmetrical devices with near-mid-gap gates), indeed seem to make the asymmetrical devices superior to the symmetrical-gate counterparts, which will be discussed in this chapter. 86 Further, the latter devices seem to show worse SCEs (e.g., DIBL) as implied by the inset of Figure 4.6, commensurate with lower transverse electric field. In fact, both DG MOSFETs operate at lower transverse fields (see Figure 4.11) relative to the bulk-Si counterpart (because of negligible depletion charge), which means higher carrier mobilities, less polysilicongate depletion, and ameliorated energy quantization (unless tSi is ultrathin (< ~5 nm) [Maj98]). For CMOS, the asymmetrical DG pMOSFET can be designed quite similarly to the nMOSFET as indicated in Figure 4.12; the p+ gate is now the active one. However, the symmetrical pMOS device introduces more problems. For example, if the same "0.375Eg(si)" gates are used, the pMOSFET threshold voltage is too high as evident in Figure 4.12. This portends the need to use two different, "exotic" gate materials for the symmetrical nMOS and pMOS devices. The asymmetrical DG CMOS speed, governed by high Ion (and low intrinsic gate capacitance at low VGS [Fos98b]) is projected to be extremely fast (-5 ps unloaded ring-oscillator delays at VDD < 1 V), even with moderate gate overlaps [Fos98b]. Gate "underlap" [Won94] is an issue because of the anticipated difficulty in two-gate self-alignment. MEDICI simulations of DG MOSFETs for which the back gate does not cover the entire channel region (due to misalignment), suggest that the asymmetrical device can be more forgiving in this regard. The results plotted in Figure 4.13, for an assumed 40% back-gate underlap, reveal that the reduction in Ion is substantially 87 10-2 Asymmetrical DG 10-3 Symmetrical DG 10-4 VDS = 1.0 V 10-5 10-6 10-7 pMOS nMOS 10-8 10-9 10-10 -1.0 -0.5 0.0 0.5 1.0 VGS (V) Figure 4.12 MEDICI-predicted current-voltage characteristics of 50 nm asymmetrical (curve) and symmetrical (points) DG CMOS devices. The symmetrical devices have the same "exotic" gates (with OM = X(si) + 0.375Eg(si))- 88 1.3 ', I ' 1.2 1.1 Asymmetrical Ay iao 1.0 0.9 0.8 0.7 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VDD (V) Figure 4.13 MEDICI-predicted VDD dependence of the relative (to Ion(ideal), the current for no underlap) variation of Ion for an assumed 40% back-gate underlap at the source side of the asymmetrical and symmetrical DG nMOSFETs. 89 larger in the symmetrical device. This seems intuitively obvious, but note that the symmetrical-device current is not simply reduced by a factor of 2. In fact, the back-gate underlap creates a two-dimensional perturbation of the electrostatic potential in the Si film, like an SCE, which affects the current in the front channel as well as the back channel. This effect similarly increases Ion of the asymmetrical device, especially for low VDD, as shown in Figure 4.13. However, it also increases Ioff (xl0 for VDD = 1.0 V, versus x3 for the symmetrical device). 4.4 Extremely Scaled Double-Gate CMOS Performance Projections Including GIDL-Controlled Off-State Current Double-gate (DG) fully depleted MOSFETs have been promoted as potential candidates for mainstream CMOS devices in the future when the lateral scaling limit of -30 nm for channel length is approached [Fra92]. Such promotion is based on the near-ideal performance potential of scaled DG devices [Fra92] and circuits [Fos98b], implied by the intrinsic coupling of the two gates, which underlies excellent control of shortchannel effects (SCEs), steep subthreshold slope, high drive current and transconductance, and low subthreshold intrinsic capacitance. Gate propagation delays near 5 ps with VDD < 1 V seem possible in extremely scaled DG/CMOS circuits [Fos98b]. Off-state current (Ioff) of DG MOSFETs is an issue, however, that has not been addressed. It has been argued that asymmetrical n+ and p+ polysilicon gates will be needed to achieve acceptable threshold voltages 90 [Suz95], [Yeh96], with the implicit assumption that Ioff will be weakinversion channel current. With such asymmetry, with extremely thin gate oxides, and with the gate-drain overlap that must be anticipated in real DG/CMOS technologies [Won97], gate-induced drain leakage (GIDL) current [Che87], amplified by the parasitic BJT in the floating-body device [Che92], [Fos98c] must be carefully considered and acknowledged in design. In this chapter we present a simulation-based analysis of extremely scaled DG/CMOS, projecting enormous performance potential but emphasizing the effects of GIDL. With regard to the latter, device and ring-oscillator simulations reveal an optimal device design approach for Ioff control, which involves speed as well. 4.4.1 50 nm Asymmetrical DG CMOS A 50 nm (Leff) asymmetrical (n' and p+ polysilicon gates) DG/ CMOS technology was defined based on device and circuit simulations using the process-based UFSOI fully depleted (FD) SOI MOSFET model in SOISPICE [Cho98]. The UFSOI/FD model has been shown to be useful for asymmetrical DG devices which have only one predominant conducting channel [Cho98], [Fos98b], and its process basis enables good estimation of model parameters solely from device structure and physics [Chi98]. Predicted nMOS and pMOS IDs-VGS characteristics are shown in Figure 4.14. The gate oxides are 2.5 nm thick, and the FD/SOI film is 17 nm thick and lightly doped (1015 cm-3). The nMOS and pMOS threshold voltages are 0.23 V and -0.25 V, respectively, and both devices show a near-ideal 65 mV 91 10-1 W/L = 10 pm/50 nm 10-2 VDS I = 50 mV, 1.0 V 10-3 10-4 p10-5 pMOS nMOS 10-6 10-7 10-8 10-9 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 VGS (V) Figure 4.14 Predicted current-voltage characteristics of 50 nm asymmetrical (n+/p+) DG/CMOS devices. The dashed curves are single-gate (SG: back gate grounded) characteristics at VDS = +1.0 V. For both nMOS and pMOS devices, S = 65 mV for DG whereas S = 90 mV for SG. 92 subthreshold gate swing (S). The latter characteristic reflects a dynamic threshold voltage due to the gate charge coupling [Yeh96], and minimal SCEs. The on-state currents (Ion) are very good: 0.8 mA/p.m for nMOS and 0.6 mA/pm for pMOS at VDD = 1.0 V. These currents are comparable, as are the predicted transconductances (1.0 mS/ptm and 0.85 mS/jm), because they are limited in the model by carrier velocity saturation; vsat (7-8x106 cm/s) for holes and electrons is nearly the same. (Velocity overshoot, or quasi-ballistic transport, which tends to extend this limit, especially for electrons [Fra92], is not accounted for here. Carrier energy quantization [Jal97], which tends to offset the benefit due to overshoot, is neglected as well.) The near-ideal S underlies enhanced Ion relative to the singlegate (SG: back gate grounded) counterpart, even for the asymmetrical DG design, as indicated in Figure 4.14. The predicted current enhancement versus VDD is illustrated in Figure 4.15 for the nMOS device. For low VDD, Ion is more than double that of the SG device, even though the DG MOSFET has only a single predominant channel. The superiority of the DG device is further illustrated in Figure 4.16 [Cho98] [Fos98b], which shows the predicted intrinsic gate capacitance-voltage characteristic contrasted to that of the SG device. The DG capacitance is nearly zero in the subthreshold region because of device neutrality, i.e., dQGf =_ -dQGb [Cho98]. Of course, in the suprathreshold region the DG capacitance is higher because of the two gates, but not double that of the SG device because there is only one strongly inverted channel (for low enough VGS). 93 2.8 2.6 nMOS 2.4 2.2 r 2.0 1.8 1.6 1.4 * 0.5 0.6 0.7 0.8 0.9 1.0 VDD (V) Figure 4.15 Predicted VDD dependence of the DG/SG Ion ratio for 50 nm asymmetrical nMOSFETs. Note that the off-state (VGS = 0) current in the DG and SG devices is the same. |

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DESIGN AND ANALYSIS OF DOUBLE-GATE CMOS FOR
LOW-VOLTAGE INTEGRATED CIRCUITAPPLICATIONS, INCLUDING PHYSICAL MODELING OF SILICON-ON-INSULATOR MOSFETS By KEUNWOO KIM A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2001 ACKNOWLEDGMENTS I would like to express my sincere appreciation to the chairman of my supervisory committee, Professor Jerry G. Fossum, for his guidance and support throughout my work. Without his invaluable guidance and encouragement, this work could not have come to fruition. I also would like to thank Professors Tim Anderson, Gijs Bosman, and Sheng Li for their willing service and guidance on my committee. I thank Mary Fossum and Erlinda Lane for all of their help arranging travel plans for numerous reviews and conferences, and Linda Kahila and Greta Sbrocco for administrative guidance. I thank the Semiconductor Research Corporation and the University of Florida for financial support. I would like to thank Meng- Hsueh Chiang, who helped me in many ways with profound technical discussions, and I also thank fellow students Duckhyun Chang, Yan Chong, Brian Floyd, Lixin Ge, Hyun-jong Ko, Sangchoon Kim, Sungphil Kim, Bin Liu, Namkyu Park, Mario Pelella, Dongwook Suh, Inchang Seo, Glenn O. Workman, Kehuey Wu, Dung-jun Yang, Ji-woon Yang, Seong-mo Yim, and Wenyi Zhou for their daily companionship. Also, I thank all of the friends who made my years at the University of Florida such an enjoyable chapter of my life. 11 Finally, I must acknowledge the support I received from all of my extended family members; aunts, uncles, nieces, and nephews. I am deeply thankful to my immediate family, all of whom stressed the importance of education to me. In particular, I am grateful to my parents, Unyong Kim and Duran Youn, for their unceasing support and my parents in law for their emotional support. Finally, I thank my lovely wife, Hyeyun Jang, whose endless love and encouragement were most valuable to me. in TABLE OF CONTENTS page ACKNOWLEDGMENTS ii ABSTRACT vi CHAPTERS 1 INTRODUCTION 1 2 ACHIEVING THE BALLISTIC-LIMIT CURRENT IN SI MOSFETS ..6 2.1 Introduction 6 2.2 Ballistic-Limit Current 7 2.2.1 Theory 7 2.2.2 Analysis 10 2.3 Double-Gate MOSFET 20 2.4 Conclusions 22 3 MODELING AND INCORPORATION OF TUNNELING CURRENTS IN UFSOI MOSFET MODELS 23 3.1 Introduction 23 3.2 Model Developments 24 3.2.1 Gate-Induced Drain Leakage Current 24 3.2.2 Reverse-Bias Junction Tunneling Current 36 3.3 Model Implementation/Verification 44 3.4 BJT Amplification by Tunneling Currents 49 3.5 Model Application to CMOS Circuit 53 3.6 Conclusions 55 4 DOUBLE-GATE CMOS 60 4.1 Introduction 60 4.2 Scalability of Fully Depleted SOI MOSFETs 61 4.3 General Comparison of Symmetrical and Asymmetrical Double-Gate Devices 66 4.3.1 MEDICI Simulation Results 67 4.3.2 Analytical Insights 77 4.3.3 Asymmetrical DG CMOS 85 IV 4.4 Extremely Scaled Double-Gate CMOS Performance Projections Including GIDL-Controlled Off-State Current ...89 4.4.1 50 nm Asymmetrical DG CMOS 90 4.4.2 GIDL Effects for 50 nm Asymmetrical DG CMOS 95 4.5 Conclusions 101 5 25 NM DOUBLE-GATE CMOS DESIGN 104 5.1 Introduction 104 5.2 Preliminary Classical MEDICI-Based Design 106 5.2.1 Device Characteristics 106 5.2.2 Short-Channel Effects 118 5.3 Schrodinger-Poisson Solver (SCHRED)-Based Analysis 131 5.3.1 Threshold Shift 131 5.3.2 Capacitance Degradation 134 5.4 25 nm DG Device Design with Quantum-Mechanical Effects 138 5.4.1 Device Characteristics 138 5.4.2 Short-Channel Effects for Newly Designed Devices .. 150 5.4.3 Sensitivity Study 155 5.4.4 Bottom-Gate Underlap 167 5.4.5 CMOS-Inverter Speed Estimation 170 5.5 UFDG-Aided Design 172 5.6 Conclusions 177 6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK 179 6.1 Summary 179 6.2 Suggestions for Future Work 181 REFERENCES 183 BIOGRAPHICAL SKETCH 190 v Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy DESIGN AND ANALYSIS OF DOUBLE-GATE CMOS FOR LOW-VOLTAGE INTEGRATED CIRCUIT APPLICATIONS,INCLUDING PHYSICAL MODELING OF SILICON-ON-INSULATOR MOSFETS By Keunwoo Kim August 2001 Chairman: Jerry G. Fossum Major Department: Electrical and Computer Engineering This dissertation mainly focuses on analysis and design of scaled double-gate (DG) silicon-on-insulator (SOI) complementary metal-oxide- semiconductor (CMOS) field-effect transistors (FETs) for low-voltage integrated circuit (IC) applications; related physical modeling of fully depleted (FD) and partially depleted (or non-fully depleted, NFD) SOI MOSFETs is presented as well. Achieving the ballistic-limit current in Si MOSFETs is discussed based on a theoretical analysis of the fundamental limit current. The study considers measured data of extremely scaled bulk-Si and SOI CMOS devices, and Monte Carlo-simulated data of 25 nm bulk-Si and DG CMOS devices, and concludes that, for controlled off-state current, only an optimally designed DG structure could yield a ballistic- limit on-state current. Because off-state current in SOI MOSFETs is one vi of the major issues for contemporary low-voltage/low-power IC applications, gate-induced drain leakage (GIDL) and reverse-bias junction tunneling currents, which can significantly govern off-state current, are physically analyzed and incorporated in the University of Florida SOI (UFSOI) MOSFET models. The viability of FD/SOI CMOS is examined for deep-submicron (< 0.1 pm) channel lengths, suggesting that the DG MOSFET is the structure needed for scaling the FD/SOI technology. The DG MOSFETs, with either symmetrical or asymmetrical gates, are strong candidates for future CMOS IC applications due to the charge coupling of the two gates via the thin, fully depleted silicon film body. Comparison of asymmetrical and symmetrical DG devices is comprehensively done for the first time. Numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical DG CMOS, using n+ and p+ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons. The GIDL effects, which tend to be more severe in the asymmetrical DG device, are analyzed and shown to be controlled via optimal design. Simulation-based design and analysis of 25 nm DG CMOS are presented, showing feasibility of extremely scaled DG MOSFETs, even when imperfectly fabricated. Quantum-mechanical issues and quasi-ballistic transport are considered in the simulation-based design of 25 nm DG CMOS; circuit performance projections suggest that optimal DG CMOS is far superior to the bulk-Si counterpart technology. Vll CHAPTER 1 INTRODUCTION Continuous CMOS scaling has been a main factor of silicon technology advancement, including the improvements of the MOSFET performance. However, the continued scaling process beyond 0.1 pm channel lengths will have to cope with unknown lithographic capabilities. Furthermore, the improved performance gain through such miniaturized channel lengths is unclear due to severe short-channel effects [Vee89], [GhaOO] and fundamental limits of silicon material characteristics [Lun97], that will prevail near the end of SIA roadmap [Sem99], To face these problems, new device structures for next-generation technology have been proposed such as metal-gate fully-depleted (FD) SOI MOSFET [Cha98], double-gate (DG) MOSFET [Fra92], SiGe MOSFET [Ism95], low- temperature CMOS [Tau97], and even quantum dot device [Wel97]. Among them, DG CMOS is a very promising candidate with its superior performance implied by excellent control of short-channel effects (SCEs), steep subthreshold slope, and high drive current and transconductance [Fos98b], [Fra92]. With the immunity of SCEs, less severe scaling rules and channel-doping designs are possible for DG MOSFETs. A traditional approach for alleviating SCEs in conventional CMOS technologies is to increase the channel-doping density and to 1 2 decrease the gate oxide thickness. Such high doping density and thin oxide can limit device/circuit performance due to decreased carrier mobility, increased junction capacitance, and increased junction tunneling leakage current. However, DG MOSFETs can be designed with low-doped channel and relatively thicker oxide, which yield higher mobility, thereby enhancing the drive current to more than double that of bulk-Si or SOI MOSFETs. This work is mainly focused on viable DG CMOS design for circuit applications and its physical analysis, and includes upgrades and improvements of the UFSOI models [Fos98a] for contemporary SOI as well as DG CMOS technologies. In Chapter 2, achieving the ballistic-limit current in Si MOSFETs is discussed. For the ultimately scaled silicon-based devices, questions about fundamental performance limits arise [Lun97]. Comprehensive analysis regarding the fundamental current limit for particular CMOS applications is needed to identify the performance limit of conventional MOSFETs and to predict the viability of future DG devices. Theoretical analysis of these limits, with comparisons to currents that have actually been achieved in recent CMOS technologies and that have been predicted by Monte Carlo simulations, gives insight about why the limits have not been reached and how they might be reached. The study considers SOI as well as bulk-Si devices, and suggests that, for controlled off-state current, only an optimally designed DG structure could yield a ballistic-limit on-state current. 3 In Chapter 3, quantum-mechanical tunneling currents are modeled. The scaling of contemporary deep-submicron SOI MOSFETs demands a reduction of oxide thickness and an increase in channel doping density to control SCEs. However, thin gate oxide raises the vertical electric field in gate-to-drain overlap of SOI MOSFETs, and high channel doping density increases the lateral electric field in body-to-drain junction of SOI MOSFETs. Due to such high fields, previously ignored quantum- mechanical tunneling currents, gate-induced drain leakage (GIDL) current [Che87] and reverse-bias junction tunneling current [Fos85], become significant. Both the tunneling currents can be important components of off-state current and should be minimized for low voltage/ low power integrated circuit applications [Fos98c]. The GIDL current and reverse-bias junction tunneling current are incorporated in UFSOI models [Fos98a] to assure the validity for scaled device simulations and to enhance the predictive capability. More detailed analysis for GIDL current, including its drain-body bias dependence, is given as well. In Chapter 4, DG MOSFETs, including conventional FD/SOI MOSFETs, are analyzed. FD/SOI MOSFETs offer several potential advantages including enhanced current, ideal subthreshold slope, and reduced short-channel effects over bulk-silicon or partially-depleted (PD) SOI counterparts for VLSI CMOS applications [Yeh95]. However, these advantages tend to fade as the channel length is shrunk to 0.1 pm, due to unacceptably low threshold voltage and poor subthreshold characteristics 4 [Yeh96]. The scalability of FD/SOI CMOS is examined to indicate a need of significant technology innovation for viable FD/SOI CMOS in the future. With the advantages of FD/SOI transistors, DG MOSFETs have their own benefits, with the possibility of scaling to extremely short channel lengths below 0.1 Â¡im due to the electrical coupling of two gates. Two kinds of DG CMOS technologies are suggested: symmetrical DG devices, which can have n+ polysilicon front and back gates for the nMOSFET (and p+ polysilicon for the pMOSFET), and asymmetrical DG devices, which can have n+ and p+ polysilicon gates for front and back gates for both nMOS and pMOS devices. Much of this interest stems from the two-channel property of the symmetrical-gate DG device and the implied higher current drive. However, performance of the asymmetrical DG device, with only one channel, is less understood. Comprehensive performance analysis for asymmetrical and symmetrical DG devices is comparatively discussed for the first time. GIDL effects for DG MOSFETs, which tend to be worse in the asymmetrical device, are analyzed and shown to be controllable via optimal design. In Chapter 5, simulation-based 25 nm DG CMOS design is presented. The design of feasible DG devices with Leff = 25 nm gives good insight and guidelines for future revolutionary DG CMOS technology. Due to the extremely short channel, the carrier transport behavior will be quasi-ballistic with the influence of velocity overshoot [Fra92], and due to 5 the required extremely scaled Si film and oxide thickness for such a scaled channel length device, the carrier behavior within the film is expected to be largely quantum mechanical [Gam98], [Maj98]. Based on the insights from the results of a one dimensional (1-D) self-consistent Schrodinger- Poisson tool (SCHRED-2) [VasOO], quasi-ballistic carrier transport and quantum-mechanical effects are included in design and analysis of 25 nm DG MOSFETs, done via a two-dimensional (2-D) device simulator (MEDICI) [Ava99]. Then, projection of 25 nm DG CMOS circuit performance is presented via a compact UFDG [ChiOl] model in SPICE3. In Chapter 6, this dissertation is concluded with summaries of the primary contributions and suggestions for future upgrades of the UFSOI and UFDG models to effectively aid the development of SOI and DG CMOS technologies. CHAPTER 2 ACHIEVING THE BALLISTIC-LIMIT CURRENT IN SI MOSFETS 2.1 Introduction The motivation for the aggressive scaling of CMOS technologies has been increased integrated-circuit functionality per cost, which has been tantamount to improved performance, or higher currents in smaller devices. A prevalent thought has been that the on-state channel current (Ion) could be continuously increased by scaling (effective) channel length (Leff), with carrier velocity overshoot obviating the limit implied by velocity saturation [Pin93], until Ion ultimately reaches the fundamental, or ballistic-limit current, defined by an average thermal injection velocity (v-p) of near-equilibrium carriers in the source [Lun97]. However, as Leff has been decreased, 2D short-channel effects (SCEs) have become harder to control, necessitating higher channel-doping density and thinner gate oxides. These modifications of the device structure have resulted in higher transverse electric field in the channel, and hence more degradation of on- state carrier mobility via increased surface scattering [Tau98a]. The lower mobility tends to inhibit velocity overshoot [Pin93] and to prevent Ion from approaching the ballistic limit. Actual (bulk-Si and SOI) devices scaled to Leff ~ 50 nm reflect this tendency, as do Monte Carlo simulations of devices with Leff as short as 25 nm. In this chapter, we discuss the 6 7 injection velocity and the ballistic-limit current, comparing the latter to currents that have actually been achieved in recent CMOS technologies and that have been predicted by Monte Carlo simulations. Insight gained from this analysis clarifies why the ballistic limit is not being reached, and it suggests how, via optimally designed double-gate MOSFETs, it could be. 2.2 Ballistic-Limit Current 2.2.1 Theory Lundstrom [Lun97] recently presented a scattering theory which suggests that the kinetics of thermal carriers in the source defines the fundamental upper limit of saturated, or on-state channel current (Ion) in extremely scaled silicon MOSFETs. As illustrated in Figure 2.1 for short L, the lateral electric field (-d\|/s/dy) shows a large gradient along the channel for high Vgg, but is zero at the virtual source. Hence carriers there, which have diffused from the source, are virtually in thermal equilibrium. In the ballistic limit of negligible backscattering of carriers from the channel to the source, the ultimate current limit is thus implied directly by the kinetic-limit, or unidirectional average velocity (v^l) [Gha68] of the carriers at the virtual source. The actual injection velocity of carriers entering the channel is v-p = 2vrl [Ber74], the average velocity of all the carriers (n+) having (positive) components of velocity toward the channel. In thermal equilibrium, n+ = n' = n/2, and hence n+v-p = nv^L, in accord with the classical definition and derivation of v^l (= [kgT/2ran*]1/2 for nondegenerate carriers) [Gha68]. 8 Figure 2.1 Electric potential variation across the channel of an extremely scaled silicon nMOSFET. The virtual channel where the longitudinal electric field is zero, defined by the application of is indicated. 9 Ignoring series resistance for the time being, we can express the on-state current of a typical (single-gate) nMOSFET as Ion = -WQi(0+)v(0+) = WCG(on)(VDD-VT(on))v(0+) (2.1) where CG(on) (< Cox = eox/tox due to finite inversion-layer capacitance, or thickness [Tau98a], [Vas97]) is the total gate capacitance, Vp(on) is the Vj)j3-defined saturation-region threshold voltage, including SCEs, and v(0+) is the average carrier (diffusion) velocity at the virtual source (y = 0+ in the channel as shown in Figure 2.1). For the ballistic limit, v(0+) = vp, and Ion = IgnM- We stress that Vp(on) in Equation (2.1) must implicitly account for polysilicon-gate depletion [Tau98a] and carrier-energy quantization [Tau98a], which tend to increase it, as well as source/drain charge-sharing and DIBL [Tau98a], which tend to decrease it. Further, a more representative expression for v-p in scaled devices must account for carrier-energy quantization (2D conduction subbands), carrier degeneracy (Fermi-Dirac statistics), and differences between the density-of-states effective mass (mp)j*) and the conductivity effective mass (mGj*) for each subband (j) [AssOO]: 1 N = -y n j = 1L /2 k BTmcj* Fl/2Ã(^F ~ ^j)/IcBrI'] I o L /J 7u(mDj*) ^ln[l + exp((EF-8j)/kBT)] (2.2) where Â£j is the subband energy, nj is the electron density in subband j, and N N is the number of occupied subbands; n = ^ nj. Note that the Fermi- j = i 10 Dirac correction factor in Equation (2.2) is greater than unity. We used SCHRED-2 [VasOO], a ID self-consistent SchrÃ³dinger-Poisson solver, to check typical values of injection velocities for electrons and holes. For an MOS structure with Nchannei = 1018 cm'3 and tox = 2 nm, Figure 2.2 shows predicted v-p versus the gate voltage overdrive, (Vq - Vp), for inversion electrons and holes. For normal Vq, both v-p(n) and v-p(p) exceed 107 cm/s, and they increase significantly with Vq due to the carrier degeneracy. For our initial analysis, which is not intended to be exact, we will assume, based on Figure 2.2 for representative |Vq - Vp | = 1.0 V, that v-p(n) = 1.5xl07 cm/s and v-p(p) = 1.2xl07 cm/s. Note that these injection velocities differ by -25%, and hence so do the ballistic-limit currents defined by Equation (2.1) and its counterpart for a pMOSFET. We further assume in Equation (2.1) that Cq(oi1)/Cox = 0.9 is representative of the inversion layer-capacitance effect [Tau98a], [Vas97] in scaled MOSFETs. 2.2.2 Analysis Measured characteristics recently reported in [Yan98], [Rod98], [Har98], [Leo98] reflect the performances of contemporary advanced CMOS technologies, including SOI [Leo98] as well as bulk-Si [Yan98], [Rod98], [Har98] devices. These technologies are yielding devices having Leff = 55-110 nm with (actual) gate oxide thicknesses (tox) of 2-2.5 nm. Measured on-state currents (at V^g = Vqs = Vqp) = 1.0-1.5 V) in nMOS and pMOS devices from these technologies are tabulated in Table 2.1, which v-r (cm/s) 11 |VG- VT| (V) Figure 2.2 SCHRED-2 [VasOO]-predicted electron and hole injection velocities versus gate voltage overdrive in bulk-Si MOSFETs with tox = 2 nm and Nchannei = 1018 cm'3. 12 Table 2.1 Measured On-State Currents in Recently Reported Scaled CMOS Technologies Versus Fundamental Ballistic-Limit Currents Derived from Equation (2.1) Device Leff (nm) tox (nm) VGSâ€™VT(on) (V) Ion (mA/pm) tLIM -^on (mA/pm) nMOS [Yan98] ~90 2.0 1.20 0.94 2.84 pMOS [Yan98] -110 2.0 1.26 0.42 1.98 nMOS [Rod98] <90 2.5 1.05 0.58 1.99 pMOS [Rod98] <90 2.5 0.95 0.24 1.19 nMOS [Har98] -60 2.0 1.35 0.82 3.17 pMOS [Har98] -80 2.0 1.30 0.42 2.04 nMOS [Leo98] -55 2.0 0.75 0.40 1.77 pMOS [Leo98] -80 2.0 0.65 0.12 1.02 13 also includes corresponding ballistic-limit currents predicted by Equation (2.1) with the assumptions noted in Sec. II; Vt(0I1) (defined as Vqs for I^g/ (W/Leff) ~ 10'7 A) and tox were taken from the cited papers. Note that for all the technologies the measured currents are substantively less than the corresponding limit currents. The measured ratio of the nMOS/pMOS currents is ~2 or larger in all the technologies, and thus the pMOS currents are much more below the limits than the nMOS currents. Although the SOI (partially depleted) nMOS device [Leo98] has the shortest L, its Ion is farthest (23%) from its 1Â° â„¢. This discrepancy could be due, in part, to high source series resistance, or to Vt(oi1) uncertainty due to the floating-body effect [Fos98c] and/or the pulse (transient)- measurement reliability [Jen95]; or to our use of v-p evaluated (from Figure 2.2) at relatively high gate voltage overdrive. In Equation (2.1) and in Table 2.1, we have ignored the effect of finite source series (specific) resistance (Rg), which reduces 1^â„¢ by lowering VQg = Vdd in Equation (2.1) by the associated ohmic drop (RgIpâ„¢/W). This reduction is significant for representative Rg (100-500 il-pm) as illustrated by the Ipâ„¢ vs. Rg plot in Figure 2.3. We can infer from Equation (2.1) that unless Rg Â« l/(C0Xvrr) the reduction will be important. For 2 nm oxides as in Figure 2.3, we need Rg << -400 il-pm, which is approachable but not strictly achievable. For Rg = 100 il-pm, Ipâ„¢ is reduced by 19% from the ideal value. Note, however, that for all the technologies in Table 2.1, the measured currents are still significantly LIM 14 RÂ§ (Q-pm) Figure 2.3 Ballistic-limit current versus source (specific) series resistance implied by Equation (2.1) for an nMOSFET with the ohmic drop accounted for. 15 less than the corresponding limit currents even when reasonable Rg is accounted for. Next, consider the Monte Carlo-predicted currents for projected Leff = 25 nm nMOS and pMOS bulk-Si MOSFETs [Tau98b], contrasted in Table 2.2 with the corresponding ballistic-limit currents defined by Equation (2.1); Rg is not modeled here, and hence the comparisons are more insightful. Note that even in these devices, scaled to near the end of the 1999 SIA roadmap [Sem99], the limit currents exceed the predictions significantly. Finally, consider the Monte Carlo-predicted currents for Leff = 30 nm (symmetrical) double-gate (DG) MOSFETs [Tau97], contrasted in Table 2.3 with the corresponding ballistic-limit currents. Because the differences are smaller than in Tables 2.1 and 2.2, we have calculated more exact values of Iâ€ž *M here. We used SCHRED-2 [VasOO] to predict the electron and hole injection velocities in the DG device structures, and used different values depending on the gate voltage overdrive as shown in Figure 2.4. Note that the Iow-Vq v^â€™s for the DG devices are comparable with those for the bulk-Si devices in Figure 2.2, but the carrier-degeneracy effect for increasing Vq is less pronounced since the DG oxides are thicker (tox = 3 nm) and hence the inversion-carrier densities (per channel) are lower. We also accounted for Rg, assumed in [Tau97] to be 50 Q-pm. Finally, we multiplied the current derived from Equation (2.1), expanded to account for Rg, by 2 to account for both channels. 16 Table 2.2 Extremely scaled (Leg- = 25 nm, tox = 1.5 run) bulk-Si MOSFET currents predicted by Monte Carlo simulations [Tau98b] versus fundamental ballistic-limit currents derived from Equation (2.1) Device VGS-VT(on) (V) tmc â– ^on (mA/pm) tLIM â– ^on (mA/pm) nMOS ~0.7 0.65 2.20 nMOS -0.9 1.05 2.84 pMOS t> o i 0.35 1.46 pMOS -0.9 0.63 1.88 Table 2.3 Extremely scaled (Leg- = 30 nm, tox = 3.0 nm, tgj = 5 nm) doubleÂ¬ gate MOSFET currents predicted by Monte Carlo simulations [Tau97] versus fundamental ballistic-limit currents derived from Equation (2.1), extended for finite Rg (= 50 Q-pm) Device VGS"VT(on) (V) vt (cm/s) tmc â€¢^on (mA/pm) tlim â– ^on (mA/pm) nMOS 0.43 1.24xl07 0.93 0.97 nMOS 0.63 1.27xl07 1.41 1.46 pMOS 0.33 0.82xl07 0.36 0.52 pMOS 0.53 0.83xl07 0.62 0.84 (cm/s) 17 |VG-VT| (V) Figure 2.4 SCHRED-2 [VasOO]-predicted electron and hole injection velocities versus gate voltage overdrive in symmetrical DG MOSFETs with tox = 3 nm, Nchannei = 1015 cm'3, and Si-film thickness tgÂ¿ = 5 nm. 18 The results in Table 2.3 show that the predicted DG nMOSFET current is virtually at the ballistic limit! It is still a factor of ~2 higher than the DG pMOSFET current, which is below its limit, but much closer to it than that of the bulk-Si device in Table 2.2. Further, comparison of the Monte Carlo simulation results in Tables 2.2 and 2.3 reveals that even though the DG devices have thicker tox = 3 nm (which means that CQ(on) in Equation (2.1) is approximately 50% lower than that for the bulk-Si devices with tox =1.5 nm), their on-state currents per channel are higher. These results, in our interpretation, reflect a significance of electron velocity overshoot in the DG MOSFETs, which tends to reduce the backscattering coefficient [Lun97] at the virtual source. In a quasi- ballistic-transport theory (i.e., one population of carriers flows ballistically while another is scattered), higher average velocity near the drain results in lower Ey there, and hence, for a specific V^g, higher Ey and higher velocity (i.e., less backscattering) just beyond the virtual source (at y = 0++) [GeOl]. Indeed, the predicted channel transport of carriers in both DG devices is, as reflected by the carrier energies along the channels, seemingly ballistic [Tau97]; but Ion < I^M in the pMOSFET means that the hole transport is only quasi-ballistic. The mentioned velocity overshoot is physically linked to high carrier mobility [Pin93], [GeOl], and the lower hole mobility is thus restricting the quasi-ballistic current in the pMOSFET. Interestingly, based on the results of Tables 2.2 and 3, we can infer that Ion of the DG nMOSFET would be a factor of -5 19 higher than that of the bulk-Si nMOSFET with the same tox (= 3 nm) and gate voltage overdrive. To better understand the results in Tables 2.1, 2.2, and 2.3, consider how Ion can be increased in a scaled device. Since tox scaling is limited due to gate tunneling [Tau98a] and Vr(on) cannot be reduced due to I0ff considerations [Tau98a], Ion in Equation (2.1) cannot be increased via higher inversion-charge density (Qj); it can be increased only by increasing v(0+), which tends to be less than v^ mainly because of surface scattering, reflected by the transverse field (Ex)-defined degradation of carrier mobility (p). For a bulk-Si MOSFET, Ex(0) (Ex at the surface) is expressed via Gaussâ€™s law as E (0) = - â€” - â€” (2.3) where is the depletion charge density. For strong inversion, QÂ¡ in Equation (2.3) tends to predominate, but can be significant in extremely scaled devices because the channel doping density is high (> 1018 cm'3) for SCE control. Thus, higher Ex(0) implies lower m, which limits v(0++) directly, and further inhibits significant velocity overshoot (quasi-ballistic transport) near the drain [Tau97], which tends to increase the longitudinal field (Ey(0++) = v(0++)/|i) near the virtual source. Thus, to get v(0+) near v-p, QÂ¿ as well as Qj must be reduced, but lower would seem to decrease Ion in Equation (2.1). 20 2.3 Double-Gate MOSFET This apparent dilemma in scaled MOSFET design seems to be avoided in DG MOSFETs fabricated in very thin Si films. Applying Gaussâ€™s law over half of the Si film of a symmetrical DG device, we get E*(0)=-Â¿;(Qâ€˜ where Qi(tot) = 2Qj is the total inversion-charge density; in Equation (2.4) can be negligible if the Si-film body is lightly doped (~1015 cm'3), which is the case for the DG devices in Table 2.3. Predictions of Ex(0) vs. -Q/q (per channel) for symmetrical DG and bulk-Si nMOSFETs, derived from SCHRED-2 [VasOO] simulations, are shown in Figure 2.5. Note that Ex(0) of the DG device is much lower than that of the bulk-Si counterpart. Furthermore, DG MOSFETs with ultra-thin Si bodies effectively suppress SCEs, and hence acceptable I0ff can be achieved with thicker tox. This implies even lower Ex(0) via lower QÂ¡ in Equation (2.4), but the two (electrically coupled) channels actually give higher Qj(tot). Hence, Ex can be quite low, rendering high mobility (subject to quantum-mechanical confinement effects in the thin Si film [GÃ¡m98]) and yielding (in DG nMOSFETs) significant velocity overshoot with v(0+) ~ v-p (subject to Rg limitations) and high, near-ballistic Ion. The DG pMOSFET would need thicker tox because of the lower hole mobility. Note that scaling tox in the DG device would enhance but lower mobility, thereby suppressing the overshoot effect; Ion would still be Ex(0) (V/cm) 21 -Qi/q (cm'2) Figure 2.5 SCHRED-2 [VasOOJ-predicted transverse surface electric field versus inversion-charge density (per channel) for bulk- Si (N^annei = 1018 cm'3) and symmetrical DG (Nchannei = 1015 cm'3, tgj = 5 nm) nMOSFETs. 22 high, but v-p would not be reached. Often, the optimal design should exploit overshoot, thereby yielding ballistic-limit Ion with acceptable I0ff. Such design would directly enhance intrinsic CMOS speed governed by the delay (t <*= l/v(0+)) of unloaded inverters. For loaded circuits, thinner tox for DG CMOS can improve the speed performance (t Â°c C]oaÂ¿Vp)D/Ion) even if Ion does not reach the ballistic-limit current. 2.4 Conclusions To achieve the ultimate ballistic-limit current, velocity overshoot near the drain must be exploited by reducing the transverse field-induced degradation of mobility and increasing the longitudinal electric field near the source. Optimally designed DG MOSFETs with controlled I0ff can potentially yield the ultimate ballistic-limit current, but this is not the case for extremely scaled bulk-Si or (partially depleted) SOI MOSFETs due to the high transverse field caused by high gate-induced surface charge density. CHAPTER 3 MODELING AND INCORPORATION OF TUNNELING CURRENTS IN UFSOI MOSFET MODELS 3.1 Introduction Off-state current (I0ff) in SOI MOSFETs is one of the major issues for contemporary low-voltage/low-power VLSI circuit applications [Fos98c]. Since gate-induced drain leakage (GIDL) and reverse-bias junction tunneling currents can significantly govern I0ff, it is important to understand the physics of the tunneling currents and to be able to predict their severity. The modeling studies of GIDL current [Che87], [Ned91], [Wan95] and reverse-bias junction tunneling current [Sto83] that have been done previously are either empirical or too complicated to be used for engineering design. Reliable compact, but physical models for the currents in SOI MOSFETs are thus needed for IC design. In this chapter, we give an in-depth discussion about these issues in three parts. The first part of this chapter focuses upon physical modeling of GIDL current and reverse-bias junction tunneling current, based on quantum-mechanical tunneling theory [Kan61]. Then, model verification is discussed based on data from SOI device measurements. Finally, circuit applications with upgraded UFSOI models in SOISPICE [Fos98a] are exemplified by simulations of an SOI CMOS ring oscillator, 23 24 the results of which give physical insight into SOI CMOS performance projection regarding speed and power as influenced by the tunneling currents. 3.2 Model Developments 3.2.1 Gate-Induced Drain Leakage Current With Figure 3.1, GIDL current in scaled SOI nMOS devices is explained as follows. Valence band electrons of the p-type body, for VBp) < 0, can tunnel directly into the conduction band of the drain under the condition of inversion somewhere in the gate-to-drain overlap region (W(DL)/2), as illustrated in Figure 3.2. For VBd > 0 in Figure 3.1, the tunneling can not occur because the valence band can not reach above the conduction band in the neutral region, Ec(Â°Â°); Ev(0) is pinned at Epp(Â°Â°) < Ec(Â°Â°), and there is no band-band overlap for tunneling. But for VBD < 0, the hole quasi-Fermi level could be higher than Ec, for which the valence band can reach above Ec(Â°Â°); hence the tunneling can occur. In order to model the tunneling current, we first need to define the tunneling probability, which we can do by assuming one-dimensional band-to-band tunneling with Wentzel-Kramers-Brillouin (WKB) approximation [Sze81] through a parabolic potential barrier: P = exp (ft2 ^m* Eg/2/2qhEx) [Kan61] where Eg is the bandgap of the semiconductor, m^ is the effective mass for tunneling electrons, and Ex (< 0 as indicated in Figure 3.1) is the electric field across the tunneling Electron Energy (eV) 25 Figure 3.1 Energy band diagram for tunneling process of GIDL current. Electrons (point) in the valance band tunnel across the forbidden tunneling barrier into the conduction band. 26 Figure 3.2 GIDL mechanism shown in an SOI nMOS device. An inversion is formed among the gate-to-drain overlap region as Vqd decrease, and then tunneling process continues with electrons supported from the body. Therefore, electrons (points) flow via B, Bâ€™, Dâ€™, and D in the figure. 27 barrier. Then, the tunneling current density is derived from the theory of field-enhanced tunneling [Kur89], [Sze81] by accounting for occupied initial states in the valance band, which are above Ec(Â°Â°), and empty final states in the conduction band [Wan89]: 7cqm*Eg(-qvBD) -Ex h3 1 CXP 2m*â€žEÂ®/2 l 2qhEx j 2qh (3.1) where J-p is zero at Vbd = 0 as implied in Figure 3.1. Since Equation (3.1) is not applicable when Vbd is positive, we use a smoothing function [McA91] for Vgj) to turn off the tunneling current for Vbd > 0: w ln(l + exp(-BVBD)) VBD - vBDO Ãœ (3.2) where Vbdo = ln(2)/B, which forces Vbd to zero for Vbd = 0; B (= 50) is a constant. In fact, the GIDL tunneling process, as illustrated in Figure 3.2, must be detail-balanced by its inverse process in thermal equilibrium (Vbd = 0)- As shown in Figure 3.3, the smoothing function in Equation (3.2) approaches Vbdo (= 13.9 mV) for Vbd > 0Â» which makes Â«Fp in Equation (3.1), with Vbd replaced by VbdÂ» negligible. For Vbd < 0Â» Vbd approaches VBdÂ» and thus enables J-p. In order to model the GIDL current, we must know the cross- section area for the tunneling current. As depicted in Figure 3.4, the net doping density varies from zero at the body-drain metallurgical junction 28 Vbd (V) Figure 3.3 Smoothed Vbd used to give a general characterization of GIDL current for all values of Vbd- Note that Vbd = 0 at Vbd = 0. 29 Figure 3.4 The variation of the net doping density (Nnet) in gate/drain overlap region. The value of Nnet approaches to zero at the metallurgical junction (y = Lmet) and the value of Nnet, to that of the drain doping density (N^g) at y - Lmet + DL/2. 30 (y = Lmet) to a very high level (N^g) inside the drain region. Consequently, the onset of GIDL current occurs in some region (W(DL)eff/2) between the metallurgical junction (y = Lmet) and y = (Lmet + DL)/2, as shown in Figure 3.2, when the band banding (> Eg) and a relatively small voltage difference between gate and drain can cause inversion. Therefore, with Equation (3.1), the GIDL current equation is formulated as Wsw (DL)eff7rqm^Es(-qVBD) -EsD 3/2 g it2j2 nj2mâ€™.E3'^ n g 2qhEsD (3.3) 2qh where W(DL)eff/2 is the effective area over which GIDL current occurs, and Ex = EsD is assumed to be the vertical electric field at the silicon surface. Indeed, the maximum band-to-band tunneling current occurs in the high-field region which is located at the surface [Che87]. As shown in Figure 3.5, the voltage relation for the SOI MOSFET applies to the gate-to-drain overlap region: VGD - VFB â€œ VsD â€œ Qsi/Coxf where QgÂ¿ = -eSiEsD by Gaussâ€™s law. Then, we derive the electric field Esj) with the assumption that the surface potential \j/sÂ£) (< 0) is pinned near the (-Eg/q + VBd) when GIDL current occurs: EsD = Vgd-V?b + ^-Vbd 3t oxf (3.4) 31 Ec EFn Ev (= EFp) Figure 3.5 The energy band diagram between gate and drain for tunneling process of GIDL current (from Bâ€™ to Dâ€™ in the Figure 3.2. 32 where eSi/eox = 3 has been used. In the UFSOI models, the flatband voltage VpB in Equation (3.4) is modeled as ttD _ - D VFB = ^MS_q Qff _ 1-TPG,^ , N Qff = 9 (E /q)-- oxf Â¿ ^oxf (3.5) where Qff is the fixed charge density at front Si-Si02 interface and TPG is a UFSOI model parameter designating the gate material: TPG = 1 for opposite types of doping in gate and body and TPG = -1 for the same type of doping in gate and body. Equation (3.5) applies to nMOS devices; for pMOS devices, the sign of the first term on the right-hand side is negative. Since Equation (3.4) can only be applied when Esp) is negative (i.e., toward the surface), we re-characterize the electric field at the surface, using another smoothing function [McA91] for Vqj) to keep the effective Esd negative and to force Iqidl to zero as Vqd increases: EsD = Vgd-V^ + ^-Vbd 3t oxf (3.6) with VGd = V, ln(l + exp[-C(VGD-VGD0)]) GDO (3.7) where Vqdo is the value of which forces Esq in Equation (3.6) to zero: D Eâ€ž â€” VGDO-VpB--g + VBi> ; (3.8) 33 C (= 5) is a constant. Small value for C is used to get a smooth variation of Esq near Vqdo, as illustrated in Figure 3.6. The smoothing function in Equation (3.7) approaches Vqdo for increasing Vqd, which means Esp and Iqidl SÂ° zero; and it approaches Vqd for decreasing Vqd, which makes EsD < 0 and enables Igidl- The smoothed electric field in Equation (3.6), which renders a general characterization of Iqidl in Equation (3.3) for all Vqd, is illustrated in Figure 3.6. Therefore, we model the GIDL current as W^w 2 DLrcqmnE (-qVBD) -EsD B GIDL â– exp BGIDL^| EsD ' (3.9) where VBD and Esd are smoothed as defined by Equations (3.2) and (3.6), respectively. The uncertainty of the effective DL/2 ((DL)eff/2) in Equation (3.3), which depends on the drain-extension doping profile, is absorbed by a model parameter BqIDL: bgidl â€œ (3.10) thus DL/2 is used directly in Equation (3.9). We incorporate the GIDL current in the UFSOI models [Fos98a], and further apply it to a 0.35 |im NFD/SOI nMOSFET for demonstration. Model-predicted IqidlÂ» reflecting Vqd and VBq dependences, is shown in Figure 3.7. Iqidl is a strong function of Vqd and VBd due to the exponential dependence of the field. Iqidl increases for decreasing Vqd 34 Figure 3.6 Smoothed surface electric field used to give a general characterization of GIDL current for all values of Vqd- The actual field (dashed curve) is zero at VpB, whereas the smoothed field goes to zero as increases and Vqd in Equation (3.7) approaches Vq^q- 35 (a) VBD (V) (b) Figure 3.7 Model-predicted (a) IdS'^GÃS and (b) IbD'^BD characteristics of a 0.35 pm NFD/SOI nMOSFET; oxide thickness (toxf) = 5.6 pm and Bqjdl = 3.3xl09 V/cm. The characteristics reflect the bias dependence of Igidl where it is predominant. 36 due to higher (negative) field from Equation (3.6). However, Igidl decreases for decreasing Vgj), which yields more band-band overlap for tunneling as illustrated in Figure 3.1 but lower (negative) field from Equation (3.6). Note that the low current for very negative in Figure 3.7(b), which is nearly constant, is predominantly thermal generation current in the UFSOI models. The GIDL current can be combined with impact-ionization current in the UFSOI models [Fos98a] because both of the currents are related to drain. For the double-gate devices [Fos98b], [Fra92], additional GIDL current for the back surface, modeled analogously, is summed with Equation (3.9) in the UFDG model [ChiO 1]. In Chapter 4, more discussion about GIDL current in DG devices is given. 3.2.2 Reverse-Bias Junction Tunneling Current Experimental data of highly doped SOI MOSFETs show high leakage current beyond thermal generation current and GIDL current. When the body doping density exceeds ~1018 cm'3, the possibility of reverse-bias junction tunneling current should be considered [Sto83]. In SOI devices, the predominant reverse-bias junction tunneling current occurs by trap-assisted mechanism [Fos85], since many traps are created near the back-gate oxide by the processing of SOI devices [Fos85]. As shown in Figure 3.8, for the drain junction, we assume that there is no thermal emission during the trap-assisted tunneling mechanism, which yields in the steady state [Fos85] 37 p-type body n+-type drain Figure 3.8 Energy-band diagram and lateral electric field near neutral body-to-drain junction. 38 d^TV = d(-lTc) qWteffNTRdy TrpV ^TC (3.11) where I-py and I-pc are the field-emission currents of holes from the traps to the valence band in the body and electrons from the traps to the conduction band in the drain; N^r is a trap density, and and ^TC are the time constants for electron and hole tunneling. Wteff in Equation (3.11) is the effective tunneling cross-section area. Figure 3.9 shows the assumed structures in the UFSOI NFD model formalism. The area of the reverse-bias junction tunneling current can be assumed as the neutral body-to-drain junction area (W(tf-1^)) for retrograded doping profiles and the halo-doped body-to-drain junction area (Wthaj0) for halo structures [Fos98a]. Since the tunneling process, which is described minutely in Figure 3.8, is predominantly through the depletion region (y(Evp) < y < y(Ecn)), the tunneling current can be expressed as ry(-^cn) ,T ry(^vn) dv / IT(REV,sJy(E[)dITV sqWt.ffNraJy(iwâ€”â€” (3.12) where the tunneling time constants are derived from Wentzel-Kramers- Brillouin (WKB) approximation, assuming a triangular potential barrier [Gro84]: f Ttv â€”^ovexP ' V 8nj2m;(Et-Ey)3/2' 3qhEy (3.13) 39 Figure 3.9 UFSOI NFD device structures: (a) without halo-doped body and (b) with halo-doped body. 40 and f TTCSTOCexP V 8nj2^n(Ec-Etf/2^ 3qhEy (3.14) Xqv and Xqc are the values of the effective carrier transit times in the valance and conduction band (tqv = xOC = 10~12 s) [Gro84], m"p and mn are the effective masses for the tunneling holes and electrons (mp = m^ = 0.2m0 [Gro84] where m0 is the free electron mass), and Ey (< 0 as indicated in Figure 3.8) is the electric field across the tunneling barrier. By assuming that traps are located at a mid-gap, and the values of the tunneling effective masses for electrons and holes are the same [Gro84], we can expect that the time constants for electrons and holes in Equations (3.13) and (3.14) are the same: Xeff = XOVexP h Btrev^ Ey J - xTV - ttc (3.15) In Equation (3.15), B^rey is a probability coefficient defined as B TREY I * 3/2 8jtA/2mp(Eg/2) 3qh (3.16) By combining Equations (3.12) and (3.15), we get IT(REV) = qWteffNTRjy(Evp)2^; * (3'17) 41 Since Teff depends exponentially upon Ey, the value of xeff changes rapidly in the depletion region (y-direction), as shown in Figure 3.10. The mean- value theorem for definite integrals is applied in order to make a closed- form solution for the tunneling equation: j-y(Ecn) dy __ Ayeff â€¢â€™y(Evp)2xeff 2x^n (3.18) where Ayeff is defined as the region in which xeff < 10xeff . In Equation (3.18), xâ„¢n is estimated when Ey has the maximum value (Emax): min I Â®TREVA Xeff =T0Vexp - E max (3.19) To make an analytic expression for Equation (3.18), we first differentiate Equation (3.15) with respect to Ey: Ateff â€œ Teff^TREV E? AE, and then apply Poissonâ€™s equation: (3.20) AE, 9nbheff Ay -Si (3.21) By combining Equations (3.20) and (3.21) with the mean-value theorem as indicated in Figure 3.10 (Axeff = 10x^n which is applied near x^n where Ey approaches Emax), we get 42 ('teff)'1 (b) Figure 3.10 The variation of effective time constant (xeff) along the region where the hole tunneling process occurs: (a) xeff versus y and (b) (Teff)'1 versus y. 43 Ayeff = -Si AxeffEy (1NBHEFFBTREV Xeff -Si 10E max ^eff = C, Ey=En 9NBHEFF etrev (3.22) where, in the UFSOI/NFD model [Fos98a], [Wor99], NBfjEFF is -^BH fÂ°r non-halo structure and Njjalo fÂ°r halo structure, as shown in Figure 3.9. Now, the reverse-bias junction tunneling current is modeled analytically from Equations (3.15), (3.16), (3.17), (3.18), and (3.22): = Wt 5N TR eSiEmax T(REV) vvueff-vr T u BHEFF^OV^TREV exp btrev') E max )â– (3.23) The maximum electric field across the tunnel barrier occurs close to the body-to-drain metallurgical junction, as shown in Figure 3.8, and is modeled as E max â€” 2M + V DB w D (3.24) where Wp in Equation (3.24) is estimated by the depletion approximation: WD = 2eSiND + NBHEFF/Eg ^ ^ I 9 NDNBHEFF v q DB = 2e Si q + V DB y 9 nbheff (3.25) The tunneling process is detail-balanced by its inverse process in thermal equilibrium (Vj)B = 0) [Sze81]. Therefore, the tunneling current in Equation (3.23) is modified to force it to zero at Vj)B = 0; 44 (3.26) where *0-I-t(REV)L I V i DB and It(rev) in Equation (3.26) is combined with generation/ recombination currents in UFSOI models because both of the currents are derived from junction regions, of both the source and drain sides. One tuning parameter (N^r) is used for the It(reV) model. Actually, we do not know how many traps there are, where traps are located, nor the exact value of the tunneling effective mass. These uncertainties for the actual device structure turn out one parameter (N^r), an â€œeffectiveâ€ trap density, since we assume that traps are located at mid-gap and the value of effective tunneling mass is 0.2m0 when we estimate B-trev in Equation (3.16). 3.3 Model Implementation/Verification The models for GIDL current and reverse-bias junction tunneling current were implemented in the UFSOI models in SOISPICE and 45 SPICE3 [Fos98a]. The network representation of the UFSOI FD and NFD models is shown in Figure 3.11. The GIDL current is combined with the impact-ionization current, and the reverse-bias junction tunneling current (in the NFD model only) is combined with recombination/ generation currents from both the source and drain junctions. One parameter for each tunneling current, Bqjdl and N-jr, respectively, is good for device designers to tune to their technologies. By the symmetrical nature of MOSFETs, gate-induced source leakage (GISL) current can occur, which could be important for some applications such as pass transistor; GISL is a subject of future work (suggested in Chapter 6). In order to verify the model of GIDL current, the actual calibration to a real SOI technology is demonstrated. A 0.14 pm NFD/SOI technology with very scaled gate oxide (tox = 2.5 nm) is used for the study of GIDL current. As shown in Figure 3.12, the GIDL current in UFSOI models is quite consistent with measurement data. We have found that the tuned value of Bqjj^l does not vary much, always being close to the theoretical prediction. Typically, Bqjql ~ 3-6xl07 V/cm. The model is now applied to a NFD/SOI technology to verify the validity and efficiency of the model of the reverse-bias junction tunneling current with measurement data. Adequate value of parameter NpR is 1014 cm'3 for a 0.15 pm NFD/SOI MOSFET, as shown in Figure 3.13. Based on parameter evaluation of the 0.15 pm NFD nMOS SOI technology, the reverse-bias junction tunneling current in UFSOI models for a 1 pm NFD 46 ÃCH Figure 3.11 Network representation for new UFSOI FD and NFD models [Suh95b], [Wor99], Note that It(rev) is only in NFD model. 47 VGfS (V) Figure 3.12 Measured (points) and UFSOI-predicted current-voltage characteristics of a 0.14 pm NFD/SOI nMOSFET showing the GIDL-current calibration. Note that for decreasing Vq^, the data appear to be approaching the predicted GIDL-controlled current. 48 VGfS (V) Figure 3.13 Measured (points) and UFSOI-predicted current-voltage characteristics of a 0.15 pm NFD/SOI nMOSFET for increasing a parameter N^r (= 0, 1013, 1014, 1015 cm'3) systematically. Evaluated value of NTr is 1014 cm'3 in this device. 49 nMOS SOI MOSFET, from the same technology as the 0.15 pm device, shows good agreement with measured data as shown in Figure 3.14. Reverse-bias junction tunneling current increases I0ff, and drive current via a floating-body effect. Note that the high tunneling current would overwhelm kink effect, as indicated in Figure 3.14(b). GIDL current goes up rapidly as front-gate bias (Vq^) decreases, but the reverse-bias junction tunneling current is independent of VgÃs- In other words, the vertical electric field is dominant mechanism for GIDL current and the lateral electric field mainly defines the reverse-bias junction tunneling current. Figure 3.15 illustrates IbS'^GÃS characteristics in a 0.21 pm body-tied source NFD/SOI device, which clarifies that UFSOI MOSFET models with GIDL current and reverse-bias junction tunneling current enhance the predictive capability. Figure 3.16 shows IdS'VgÃS characteristics for NFD/SOI pMOSFETs with floating body and body-tied source; UFSOI models are in good agreement with measured data showing significant GIDL and reverse-bias junction tunneling currents. 3.4 BJT Amplification by Tunneling Currents In floating-body SOI MOSFETs, the GIDL current and reverse- bias junction tunneling currents are amplified by the parasitic BJT [Che92]. If Iqidl represents the actual GIDL current resulting from carrier tunneling in the drain junction under the gate overlap, as modeled in Section 3.2.1, then the component of drain current driven by GIDL is 50 0.0 0.5 1.0 1.5 VDS (V) (b) Figure 3.14 Measured (points) and UFSOI-predicted current-voltage characteristics of a l|im NFD/SOI nMOSFET with It(rev) (solid curve) and without It(Rev) (dashed curve): (a) Ids'^GAS at VDS = 0.05, 1.5 V, (b) IDS-VDS at VGfB = 0.5, 0.75, 1.0, 1.25, 1.5 V. 51 -VGfS (V) Figure 3.15 Measured (points) and UFSOI-predicted Igg (body-to-source current) versus VGfg for a 0.21 pm body-tied source NFD/SOI pMOSFET at V^g = -1.5 V. Evaluated value of N^r is 6.0xl014 cm'3 in this device. 52 (a) (b) Figure 3.16 Measured (points) and UFSOI-predicted current-voltage characteristics of NFD/SOI pMOSFETs at V^g = 1.5 V for (a) floating-body device and (b) body-tied source device. 53 IDS(GIDL) - i_(3(M>^1) + Igidl (3.27) where P in the BJT current gain and M is the multiplication factor for impact ionization caused by the BJT current flowing through the high- field drain region [Kri96]. At the off-state condition, M is typically near unity, but (M-l) > 0 depending on V^g. Hence, if impact ionization is ignored, interpretation of measured off-state current due to GIDL can give erroneously high values of P as in [Che92]. Nonetheless, Iqidl is amplified as defined by Equation (3.27), and it must be considered in the design of extremely short (or narrow-base) MOSFETs including SOI devices. In the same way, we can write for reverse-bias junction tunneling current T _ P^T(REV) , T Â¡ q C}Q\ ^SmREV)) - l_p(M-l) T(REV) ' Figure 3.17 shows UFSOI-predicted current-voltage characteristics when the parasitic BJT is turned off and on. Indeed, the BJT, via Equations (3.27) and (3.28), is significant in defining IgidL" and lT(REV)â€˜con^roHe^ components of drain current in SOI devices. 3.5 Model Application to CMOS Circuit It is worthwhile to investigate the effects of the new models on circuit performance. We simulate an unloaded 9-stage CMOS inverter ring oscillator based on the calibrated model cards for 0.14 pm NFD SOI technologies, which are represented in Figures 3.12 and 3.16(a). As 54 VGfS (V) Figure 3.17 UFSOI-predicted current-voltage characteristics with and without the parasitic BJT amplification for a 0.15 pm NFD/ SOI nMOSFET, as shown in Figure 3.13. Iqidl and It(REV) induce a huge BJT current. 55 illustrated in Figure 3.18, simulated results for the circuit with both GIDL and reverse-bias junction tunneling currents tend to speed up the circuit, via the floating-body effect, by less than 5% for all the supply voltages, and the circuit consumes only 5% more dynamic power. However, for the NFD/ SOI technology as shown in Figure 3.13, reverse-bias tunneling current can significantly effect on circuit performance for high N^r as depicted in Figure 3.19. GIDL and reverse-bias junction tunneling currents cause more static power consumption due to increased I0ff. Figure 3.20 shows static power consumption versus Vqd for the CMOS inverters. The static power is increased significantly, and hence the tunneling currents must be effectively controlled, especially for memory applications such as DRAM. Possible solution for suppressing the GIDL current would be the use of graded gate-oxide devices [Ko84] to reduce the electric field in Equation (3.6). Control of the reverse-bias junction tunneling current is still an issue for VLSI device scaling [GhaOO]. 3.6 Conclusions New physical models for GIDL and reverse-bias junction tunneling currents have been presented and implemented in the UFSOI MOSFET models. The device uncertainties for tunneling effective mass and contact area of the current turn out one parameter (Bqjql) for the GIDL current model, and the uncertainties for tunneling effective mass, 56 Figure 3.18 UFSOI-predicted (a) average propagation delay versus and (b) average dynamic power consumption versus of an unloaded 9-stage CMOS inverter ring oscillator with and without Igidl and It(REV)- 57 1.6 1.5 1.4 1.3 1.2 1.1 1.0 Figure 3.19 UFSOI-predicted average propagation delay and dynamic power consumption versus N^r of an unloaded 9-stage CMOS inverter ring oscillator at = 1.0 V. RO Dynamic Power (mW/stage) CMOS Inverter Static Power (W/stage) 58 VDD (V) Figure 3.20 UFSOI-predicted average static power consumption versus VDd for CMOS inverter. Both Iqidl anc* It(REV) increase static power due to increased I0ff. 59 trap density, and trap location yield one parameter (N^r) for the reverse- bias junction tunneling current. The models are verified with experimental data from scaled SOI MOSFETs by using physically reasonable values for the parameters. For CMOS inverter circuits, propagation delay and dynamic power are not changed too much by GIDL and reverse-bias junction tunneling currents. However, both currents in SOI MOSFETs increase I0ff and hence static power consumption. They must be controlled by optimal device design. CHAPTER 4 DOUBLE-GATE CMOS 4.1 Introduction It is well known that the double-gate (DG) fully-depleted (FD) SOI MOSFET can extend the scaling limitation of FD/SOI technology beyond the 0.1 pm regime because of superior short channel-effect immunity [Fra92], [Fos98b]. In the first part of this chapter, we will examine the scalability of FD/SOI CMOS to indicate a need of significant technology innovation, i.e, DG devices, for viable FD/SOI CMOS in the future. In the second part of this chapter, a general comprehensive comparison between asymmetrical and symmetrical DG devices will be done. Numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical double-gate (DG) CMOS, utilizing n+ and p+ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons, only one of which is its previously noted threshold-voltage control. The most noteworthy result is that asymmetrical DG MOSFETs, optimally designed with only one predominant channel, yield comparable, and even higher drive currents at low supply voltages. The simulations further give good physical insight 60 61 pertaining to the design of DG devices with channel lengths of 50 nm and less. Finally, GIDL current in DG devices will be studied. A simulation-based analysis of extremely scaled DG CMOS, emphasizing the effects of GIDL, is described. Device and ring-oscillator simulations project an enormous performance potential for DG/CMOS, but also show how and why GIDL can be much more detrimental to off-state current in asymmetrical (n+ and p+ polysilicon gates) DG devices than in the singleÂ¬ gate counterparts. However, the analysis further shows that the GIDL effect can be controlled by tailoring the back (p+-gate) oxide thickness, which implies design optimization regarding speed as well as static power in DG/CMOS circuits. 4.2 Scalability of Fully Depleted SOI MOSFETs For low-voltage/low-power integrated digital circuit applications, FD/SOI MOSFETs are potentially superior to partially depleted (PD) SOI counterparts due to their ideal subthreshold slope, high drive current and transconductance, and much reduced floating-body effects, but the advantages rapidly disappear as the channel length is shrunk to 0.1pm, due to two-dimensional field fringing in the silicon film and back-gate oxide [Yeh95]. Such an effect causes threshold voltage (V-jO falloff and increases off-state current (I0ff) significantly. In order to improve short-channel effects (SCEs), halo-doped structures have been suggested for bulk-Si and PD/SOI MOSFETs 62 [Chr85], but it is still unknown that halo doping is also beneficial for FD/ SOI MOSFETs. The MEDICI [Ava99] two-dimensional device simulator is used to investigate whether the conventional FD/SOI device can be applicable down to 0.1 pm CMOS technologies with halo doping. Figure 4.1 illustrates 0.1 pm FD/SOI device structures: uniform doped FD/SOI and halo-doped FD/SOI nMOSFET, which are used in simulations. The two devices have the same front-gate oxide thickness (toxf = 3 nm), back-gate oxide thickness (toxb = 40 nm), and Si-film thickness (tgi = 40 nm). As shown by the simulation results in Figure 4.2, the increase of halo doping density significantly reduces I0ff by improving subthreshold slope and DIBL effect. But, the halo-doped FD/SOI MOSFET has floating- body effects as shown in Figure 4.3. This means that halo-doped FD/SOI MOSFET has a quasi-neutral region similar to retrograded PD/SOI MOSFET. To maintain the FD condition, tgi must be decreased. Such scaling for halo-doped structure becomes prohibitive. Furthermore, in order to suppress I0ff to a reasonable value (< 10 nA/pm) for FD/SOI CMOS circuit application, the halo doping density needs to be higher than ~3xl018 cm'3, as shown in Figure 4.2. However, such a high halo doping density causes significant degradation of the drive current dog), as indicated in Figure 4.3, due to the increased Vt and the increased (body) depletion capacitance in SOI MOSFETs [Suh95]. Hence, the conventional FD/SOI MOSFET will not be useful with halo doping. Indeed, as suggested in [Yeh95], the FD/SOI CMOS technology appears to be unscalable. 63 Gf D (a) Gf D i Eiz ++ P n++ n P+ P+ Si02 1 P' < Gb (b) Figure 4.1 Simulated 0.1 pm FD/SOI nMOSFET structures for (a) uniform doped FD/SOI MOSFET, (b) halo-doped FD/SOI MOSFET. (uirf/v) sal 64 vGfS (V) Figure 4.2 MEDICI-predicted Ios'^GfB characteristics for 0.1 pm FD/ SOI nMOSFETs with varying halo doping density (N^aio)- (uirl/ym) SQj 65 Figure 4.3 MEDICI-predicted Ids'^DS characteristics for 0.1 pm FD/ SOI nMOSFETs with varying halo doping density (Nhai0)- 66 4.3 General Comparison of Symmetrical and Asymmetrical Double-Gate Devices In contrast to conventional FD/SOI devices, as well as PD/SOI and bulk-Si devices, DG MOSFETs, having very thin Si-film bodies, will, because of their near-ideal intrinsic features, quite possibly constitute the CMOS technology of the future as the lateral scaling limit (Lmet ~ 10 nm) is approached [Fra92]. In addition to the inherent suppression of short- channel effects (SCEs) and naturally steep subthreshold slope, DG MOSFETs offer high drive current (Ion) and transconductance, generally attributed to the two-channel property of the symmetrical DG device [Won98]. More important, we believe, is the electrical coupling of the two gate structures through the charged Si film. This charge coupling underlies the noted features of the device, which translate to high Ior/Ioff ratios when the threshold voltage is properly controlled. Such control has been shown to be easily effected via asymmetrical gates of n+ and p+ polysilicon [Tan94], [Fos98b], which, however, would seem to undermine the current drive because the resulting device has only one predominant channel. Contrarily, we show in this chapter that the gate-gate coupling in the asymmetrical DG MOSFET is more beneficial than in the symmetrical counterpart, resulting in superiority of the former device for more reasons than just the threshold-voltage control. We rely on 2D numerical device simulations using MEDICI and its hydrodynamic- transport option [Ava99], supplemented by a Schrodinger-Poisson solver (SCHRED-2 [Vas97], [VasOO]) and analytical characterization, to convey 67 insight regarding performance and design and to reveal the inherent superiority of asymmetrical DG CMOS. Predicted current-voltage characteristics of Lmet = 50 nm DG nMOSFETs are presented in Section 4.3.1, revealing comparable Ion in asymmetrical- and symmetrical-gate devices designed for equal I0ff at low supply voltages (Vdjj). Explanation of this surprising result is given in Section 4.3.2 using analytical characterizations of the basic DG MOSFET physics, which lead to simplified expressions for subthreshold slope and inversion charge integrated over the thin Si film. Additional potential advantages of asymmetrical DG CMOS are discussed in Section 4.3.3, giving good insight for optimal device design at 50 nm and below. 4.3.1 MEDICI Simulation Results We used MEDICI to simulate 50 nm DG nMOSFETs having abrupt source/drain junctions (i.e., Leff = Lmet = 50 nm [Tau98a]); the device structure is illustrated in Figure 4.4. The Si-film bodies are lightly doped (N^ = 1015 cm'3) and quite thin (tgj = 10 nm), and the gate oxides are relatively thick (tox = toxf = toxb = 3 nm) for I0ff control. (Note that the SCE suppression inherent in DG MOSFETs [Won98] allows for thicker oxides than that needed for single-gate MOSFETs.) Predicted IdS'^gs characteristics of symmetrical (n+ polysilicon gates) and asymmetrical (n+ and p+ polysilicon gates) DG devices, contrasted to those of the single-gate (SG: back gate grounded) counterparts, are shown in Figure 4.5. (The MEDICI-predicted currents for strong inversion are too high because the 68 Figure 4.4 The (asymmetrical) double-gate MOSFET structure. For the asymmetrical device, the front and back gates are n+ and p+ polysilicon, respectively. For the symmetrical device, the gates can be n+ polysilicon, but should have near-mid-gap work functions for off-state current control. (uirf/v) Sdj 69 Figure 4.5 MEDICI-predicted current-voltage characteristics of 50 nm asymmetrical (n+ and p+ polysilicon gates) and symmetrical (n+ polysilicon gates) DG nMOSFETs, contrasted to the characteristics of the single-gate (SG: back gate grounded) counterparts. (The strong-inversion currents are overÂ¬ predicted, as discussed in the text of this chapter, but the relative values, and the subthreshold currents, are meaningful.) 70 carrier velocity overshoot, or energy-relaxation time, was simply defaulted and not calibrated. However, the relative values for the symmetrical- and asymmetrical-gate devices, and the subthreshold currents, which are not significantly affected by the overshoot, are meaningful.) Note the inherent SCE superiority (implied by the subthreshold slope) of the DG devices relative to their SG counterparts. The symmetrical DG nMOSFET, however, has an unacceptable (negative) threshold voltage. Pertinent comparison of Ion for the two DG device structures must be done for equal I0ff, for which the symmetrical MOSFET will need gate material with tailored work function (O^) and/or very high body doping density (~1019 cm'3) [Won98]. Such high doping density necessitates extremely thin tgÂ¡ (< 5 nm) to ensure effective gate-gate coupling (or â€œfull depletionâ€ [Lim83]), and hence implies lower carrier mobility due to structural quantum- mechanical (QM) confinement [GÃ¡m98] as well as impurity scattering. Furthermore, the energy-quantization effects due to the confinement become severe [Maj98]. Theoretically, a â€œnear-mid-gapâ€ gate material with = X(gÂ¡) + 0.375Eg(gi) will reduce I0ff to the noted equality as shown in Figure 4.6, where the predicted IdS'^GS characteristic of the so modified symmetrical-gate MOSFET at Vjjg = 1.0 V is compared with that of the asymmetrical-gate device. Interestingly, when the off-state currents are made equal, the on-state currents for both devices are comparable, even though the asymmetrical device has only one predominant channel (for (rari/v) SQj 71 VGs (V) Figure 4.6 MEDICI-predicted current-voltage characteristics of the modified symmetrical DG MOSFET, contrasted to that of the asymmetrical device of Figure 4.5; both devices have equal I0ff. The predicted Vpj) dependence of the asymmetrical/ symmetrical Ion ratio for the DG nMOSFETs is shown in the inset. 72 low and moderate Vgg) as revealed by the plots of its current components in Figure 4.7. The corresponding I0n(asym/Ion(sym) ratio, plotted versus Vdd in the inset of Figure 4.6, is actually greater than unity for lower Vdd- We attribute this Vdd dependence to better suppression of DIBL [Tau98] in this asymmetrical device. Simulations of longer Lmet = 0.5 pm devices yield I0n(asym/Ion(sym) = 1> independent of Vdd- For the longer devices, the predicted Ids'^GS characteristics are plotted on a linear scale in Figure 4.8 for low and high values of Vds- The near-equality of the currents in both devices is clearly evident. The MEDICI simulations are based on semi-classical physics with analytical accounting for quantization effects [Ava99]. To ascertain that the predicted symmetrical-versus-asymmetrical DG benchmarking results are not precluded by the effects of QM confinement of electrons in the thin Si film, we used SCHRED-2 [Vas97], [VasOO], a ID (in x) self- consistent solver of the Poisson and Schrodinger equations, to check them. SCHRED-predicted areal electron charge density (Qc, which correlates with the channel current) versus Vgg in both devices is plotted for VDs = 0 in Figure 4.9. Although the QM electron distributions across the Si film (with n(x) forced to zero at the two Si-Si02 boundaries by the wavefunction conditions), shown in Figure 4.10 differ noticeably from the classical results, Qc is nearly the same in both devices, implying nearly equal currents as predicted by MEDICI. We hence are confident that the QM effects will not alter the main conclusions of our DG device benchmarking, which we now explain analytically. (uirl/y) SQj 73 VGS (V) Figure 4.7 MEDICI-predicted channel-current components (integrated over the front and back halves of the Si film) for the 50 nm asymmetrical DG nMOSFET. The back-channel current (with p+ gate) is not significant, but the front-channel current is enhanced by the gate-gate charge coupling and beneficial inversion-layer capacitance. (mri/yui) SQj 74 VGS (V) Figure 4.8 MEDICI-predicted current-voltage characteristics of longer- channel (Lmet = 0.5 |xm) asymmetrical and symmetrical DG nMOSFETs with the same structure as the devices in Figure 4.6. The currents are approximately equal for low and moderate Vgg; for Vqs > 1 V, the back-channel current in the asymmetrical device becomes significant, especially at high Vj)S (due to back-surface DIBL). -Qc/q (cm 75 I ft* Â«0 o ft* C GG VGS (V) Figure 4.9 SCHRED-predicted integrated electron charge density in the asymmetrical and symmetrical DG nMOSFETs; Vug = 0- Also shown are the corresponding predicted VQg-derivatives of the charge densities. Electron Density (cm 76 x (nm) Figure 4.10 SCHRED-predicted electron charge density (-Qc(x)/q) across the Si film of the asymmetrical and symmetrical DG nMOSFETs; Vpg = 0. 77 4.3.2 Analytical Insights To gain physical insight and explain the surprising benchmark results presented in Sec. II, we begin with a first-order analytical solution of Poissonâ€™s equation (ID in x) applied to the thin Si-film body. For a general two-gate nMOSFET with long Lmet at low Vgg, assuming inversion-charge sheets (tÂ¡ = 0) at the front and back surfaces of the fully depleted Si film, we have [Lim83] (4.1) and (4.2) where V^fg and VobS are the front and back gate-to-source voltages, V^gf and VpBb are the front- and back-gate flatband voltages, \j/sf and \|/sb are the front and back surface potentials, Qcf and Qct, are the front- and back- surface inversion charge densities, = -qN^tgi is the depletion charge density, C0f = Â£ox/toxf and C0b = Eox^oxb ara the front- and back-gate oxide capacitances, and = Â£si/tsi is the depletion capacitance. By setting Vq.s = ^GfS = ^GbS (implying no gate-gate resistance [Fos98b]) and eliminating the \j/sb terms from Equations (4.1) and (4.2), we derive the following expression for the DG structure: 78 VGS ~ Vsf + 1 + r (VFBf + r^FBb) " I qâ€” + rQ fQcf Qcb^ f Qb Qb x'-'of VJob^' 'Â¿Jv^ob>'J 2C , + r2a (4.3) where r is a gate-gate coupling factor expressed as CbCQb = 3toxf . (4 4) ~ Cof(Cb + Cob)"3toxb + tSi â€™ the approximation in Equation (4.4) follows from Â£si/e0x = 3. Note that r decreases with increasing tgj. 4.3.2.1 Subthreshold Slope Since Equation (4.3) applies to a general DG device structure, it implies that both the asymmetrical- and symmetrical-gate devices should have near-ideal subthreshold slope, or gate swing: S = Ã â€” In (10 )1^â€”^-S = 60 mV (4.5) V q JdMf sf because, with Qcf and Qcb negligible for weak inversion, dVQg/d\|/sf = 1. The Lmet = 6-6 pm simulation results in Figure 4.8 are in accord with this result. The 50 nm devices in Figure 4.6 show S = 65 mV for both devices, greater than 60 mV (at T = 300 K) due to mild SCEs (which subside for thinner tgj). The gate-gate coupling, implicit in Equation (4.3), underlies the near-ideal S in the DG MOSFET. So, as is evident in Figure 4.6, the asymmetrical DG MOSFET current tracks that of the symmetrical counterpart as Vgg is increased 79 from the off-state condition where the currents are equal, in accord with Equations (4.3)-(4.5). We now have to explain why this tracking continues, in essence, into the strong-inversion region as illustrated in Figure 4.8, and as implied by the electron charge densities Qc(Vqs) in Figure 4.9. 4.3.2.2 Strong-Inversion Charge Effects of finite inversion-layer thickness (tÂ¡) [Tau98a] on Qc(Vgs) in DG devices are quite important. For the symmetrical DG (n- channel) device, the effective tÂ¡(sym) (for the front and back channels) is defined by integrating the electron density over half of the Si film [LÃ³pOO]: f Jo (4.6) and the total Qc(sym) is analytically expressed by combining Poissonâ€™s equation and Gaussâ€™s law [LÃ³pOO]: ^c(sym) ^^Gf(sym)(^GS ^Tf(sym)) (4.7) where ^Gf(sym) (4.8) is the total front-gate (or back-gate) capacitance, and 80 (4.9) is a nearly constant threshold voltage for strong-inversion conditions [LÃ³pOO]. In Equation (4.8), Cj(sym) = Â£si/ti(sym) represents the (front or back) inversion-layer capacitance, -(dQc(sym)/dv|/sf)/2 [Tau98]. The factor of 2 in Equation (4.7) reflects two identical channels and gates. Relative to the single-gate device, for which Cgf could differ from CGf(sym) slightly, we thus infer an approximate doubling of the drive current, but exotic gate material is needed as noted in Sec. 4.3.1. For the asymmetrical DG (n-channel) device, we define the effective ti(asym) (for the predominant front channel) by integrating the electron density over the entire Si film: (4.10) To derive the counterpart to Equation (4.7), we first write the ID Poisson equation as (4.11) Integrating Equation (4.10) across the entire Si film yields 81 Vsf = Vsb- Qc(asym) Ã± i(asym) Qb 2CÂ¡ + tSiEsb (4.12) is the electric field at the back surface. x = tsi The gate-voltage (Faraday) relations for the DG MOSFET structure are where E sb dvj/ "dx VGfS â€œ Vsf + Vof + ^GfS (4.13) and VGbS â€œ Vsb + Vob + ^GbS Â» (4.14) where vj/0f and iy0b are the potential drops across the front and back oxides, and 0GfB and are the front and back gate-body work-function differences. Applying Gaussâ€™s law across the entire Si film of the asymmetrical device, we get (for no interfacial charge) Vof = oâ€œ^(eSiEsb-Qc(asym)~Qb) 5 (4.15) and applying Gaussâ€™s law to the back-surface, we get Vob = - eSiEsb Cob (4.16) Now, by setting Vqq = Vq^ = Vq^s in Equations (4.13) and (4.14) and eliminating ysb and Esb from Equations (4.12), (4.14), (4.15), and (4.16), we finally derive the integrated electron charge expression: 82 where Qc(asym) â€” ^-'Gf(asym)( ^ r)(^GS ^Tf(asym)) (4.17) 'of 'of 'Gf(asym) 1 - r 'of C, _ r^j(asym) (4.18) i(asym) 3 t oxf partly defines the total front-gate capacitance, and VTf(asym) ~ Vsf + 1 1 + r (^GfS + r^Gbs) ~ (4.19) is a nearly constant threshold voltage for strong-inversion conditions. In Equations (4.17)-(4.19), r > 0, defined in Equation (4.4) by a charge-sheet analysis, reflects the benefit of the â€œdynamic threshold voltageâ€ [Lim83] of the asymmetrical DG MOSFET due to the gate-gate charge coupling. This effect is preempted in the symmetrical DG device because of the (back- channel) inversion charge, which shields the electric-field penetration in the Si film and pins y^. For the particular asymmetrical device simulated, r = 0.47. We note further in Equations (4.17) and (4.18) the dependence of Qc(asym) on ^i(asym)> different from the ti(sym) dependence in Equations (4.7) and (4.8), which reflects an additional benefit due to the n(x) distribution in the Si-film channel. By comparing Equation (4.18) with Equation (4.8), which are illustrated by the SCHRED-predicted -dQc/dVQg plots included in Figure 4.10, we see that for finite ti(asym) and t}(sym), which are 83 comparable (classically as well as quantum mechanically), CGf(asym) > C0f whereas CGf(sym) < C0f. The latter inequality for the symmetrical device is the well known effect of finite inversion-layer capacitance [Tau98], as characterized in Equation (4.8): An incremental increase in VGg must support an incremental increase in the potential drop across the inversion layer, at the expense of the increase in -Qc(sym). (Note that the inversion- layer potential drop is zero when tj = 0 and Qc is a charge sheet.) The former inequality for the asymmetrical device, however, is unusual. It can be explained by referring to the predicted transverse electric-field variations (Ex(x)) across the Si film (channel) shown in Figure 4.11 for the asymmetrical and symmetrical devices. The fact that Ex(x=tgÂ¿/2) = 0 always in the symmetrical device underlies the noted, detrimental (regarding current and transconductance) inversion-layer capacitance effect. However, in the asymmetrical device, typically Ex(x) > 0 everywhere, but an incremental increase in Vqs will, while increasing Ex(x=0), decrease Ex(x=tgÂ¿) ( = Esk in Equation (4.12)), ultimately forcing Esb < 0 as in Figure 4.11 where VGg = 1.0 V. This field perturbation results in an incremental decrease in the potential drop across the Si film (inversion layer), and hence more increase in -Qc(asym) as reflected by Equation (4.18). For the particular DG devices simulated, CQf(asym)/ CGf(Sym) = 1-21 at VGg = 1.0 V, and this ratio is even larger for lower VGg. Quantitatively, the two noted benefits to Qc(asym) yield Qc(asym)/ Qc(sym) = 0-88 at VGS = 1.0 V, which is consistent with Figures 4.9 and (V/cm) 84 x (nm) Figure 4.11 MEDICI-predicted transverse electric-field variations across the Si film (tgj = 10 nm) of the asymmetrical and symmetrical DG nMOSFETs. Note that the field in the symmetrical device is always zero at the center of the film (x = tgÂ¿/2). 85 4.11, and with Figure 4.8 when small differences in average (MEDICI- modeled, based on n(x) and Ex(x) as shown in Figure 4.11) electron mobility in the two devices are accounted for. We conclude then that the near-equality of the currents in the asymmetrical and symmetrical DG devices is due to the extended gate-gate charge coupling, characterized by r, which underlies near-ideal subthreshold slope in Equation (4.6) and the (1 + r) enhancement of Qc(asym) in Equation (4.17), and to the reverse inversion-layer capacitance effect on CQf(asym) in Equation (4.18) in contrast to the (common) detrimental one on CGf(sym) in Equation (4.8). We thus infer for the asymmetrical DG MOSFET a near-doubling of the drive current, and conventional polysilicon gates are adequate. Note further in Equations (4.17)-(4.19) the possibility for structural design optimization of the asymmetrical device, which is not possible for the symmetrical device as evident in Equations (4.7) and (4.8). 4.3.3 Asymmetrical DG CMOS For the low supply voltages anticipated for highly scaled DG CMOS, the high current drive which, based on the analysis herein, can be anticipated for asymmetrical DG MOSFETs, and their inherent design flexibility for controlling parasitics such as gate-overlap capacitance, gate â€œunderlapâ€ [Won94], gate-gate resistance [Fos98b], and GIDL (which could be a show-stopper for symmetrical devices with near-mid-gap gates), indeed seem to make the asymmetrical devices superior to the symmetrical-gate counterparts, which will be discussed in this chapter. 86 Further, the latter devices seem to show worse SCEs (e.g., DIBL) as implied by the inset of Figure 4.6, commensurate with lower transverse electric field. In fact, both DG MOSFETs operate at lower transverse fields (see Figure 4.11) relative to the bulk-Si counterpart (because of negligible depletion charge), which means higher carrier mobilities, less polysilicon- gate depletion, and ameliorated energy quantization (unless tgÂ¡ is ultra- thin (< ~5 nm) [Maj98]). For CMOS, the asymmetrical DG pMOSFET can be designed quite similarly to the nMOSFET as indicated in Figure 4.12; the p+ gate is now the active one. However, the symmetrical pMOS device introduces more problems. For example, if the same â€œ0.375Eg(gÂ¿)â€ gates are used, the pMOSFET threshold voltage is too high as evident in Figure 4.12. This portends the need to use two different, â€œexoticâ€ gate materials for the symmetrical nMOS and pMOS devices. The asymmetrical DG CMOS speed, governed by high Ion (and low intrinsic gate capacitance at low VQg [Fos98b]) is projected to be extremely fast (~5 ps unloaded ring-oscillator delays at V^d < 1 V), even with moderate gate overlaps [Fos98b]. Gate â€œunderlapâ€ [Won94] is an issue because of the anticipated difficulty in two-gate self-alignment. MEDICI simulations of DG MOSFETs for which the back gate does not cover the entire channel region (due to misalignment), suggest that the asymmetrical device can be more forgiving in this regard. The results plotted in Figure 4.13, for an assumed 40% back-gate underlap, reveal that the reduction in Ion is substantially (uirl/v) SQj 87 VGS (V) Figure 4.12 MEDICI-predicted current-voltage characteristics of 50 nm asymmetrical (curve) and symmetrical (points) DG CMOS devices. The symmetrical devices have the same â€œexoticâ€ gates (with on/Aon(ideal) 88 VDD (V) Figure 4.13 MEDICI-predicted dependence of the relative (to I0n(ideal)> the current for no underlap) variation of Ion for an assumed 40% back-gate underlap at the source side of the asymmetrical and symmetrical DG nMOSFETs. 89 larger in the symmetrical device. This seems intuitively obvious, but note that the symmetrical-device current is not simply reduced by a factor of 2. In fact, the back-gate underlap creates a two-dimensional perturbation of the electrostatic potential in the Si film, like an SCE, which affects the current in the front channel as well as the back channel. This effect similarly increases Ion of the asymmetrical device, especially for low Vj)j), as shown in Figure 4.13. However, it also increases I0ff (xlO for Vdd = 1.0 V, versus x3 for the symmetrical device). 4.4 Extremely Scaled Double-Gate CMOS Performance Projections Including GIDL-Controlled Off-State Current Double-gate (DG) fully depleted MOSFETs have been promoted as potential candidates for mainstream CMOS devices in the future when the lateral scaling limit of -30 nm for channel length is approached [Fra92]. Such promotion is based on the near-ideal performance potential of scaled DG devices [Fra92] and circuits [Fos98b], implied by the intrinsic coupling of the two gates, which underlies excellent control of short- channel effects (SCEs), steep subthreshold slope, high drive current and transconductance, and low subthreshold intrinsic capacitance. Gate propagation delays near 5 ps with Vdd < 1 V seem possible in extremely scaled DG/CMOS circuits [Fos98b]. Off-state current (I0ff) of DG MOSFETs is an issue, however, that has not been addressed. It has been argued that asymmetrical n+ and p+ polysilicon gates will be needed to achieve acceptable threshold voltages 90 [Suz95], [Yeh96], with the implicit assumption that I0ff will be weak- inversion channel current. With such asymmetry, with extremely thin gate oxides, and with the gate-drain overlap that must be anticipated in real DG/CMOS technologies [Won97], gate-induced drain leakage (GIDL) current [Che87], amplified by the parasitic BJT in the floating-body device [Che92], [Fos98c] must be carefully considered and acknowledged in design. In this chapter we present a simulation-based analysis of extremely scaled DG/CMOS, projecting enormous performance potential but emphasizing the effects of GIDL. With regard to the latter, device and ring-oscillator simulations reveal an optimal device design approach for I0ff control, which involves speed as well. 4.4,1 50 nm Asymmetrical DG CMOS A 50 nm (Leff) asymmetrical (n+ and p+ polysilicon gates) DG/ CMOS technology was defined based on device and circuit simulations using the process-based UFSOI fully depleted (FD) SOI MOSFET model in SOISPICE [Cho98]. The UFSOI/FD model has been shown to be useful for asymmetrical DG devices which have only one predominant conducting channel [Cho98], [Fos98b], and its process basis enables good estimation of model parameters solely from device structure and physics [Chi98]. Predicted nMOS and pMOS Ids'^GS characteristics are shown in Figure 4.14. The gate oxides are 2.5 nm thick, and the FD/SOI film is 17 nm thick and lightly doped (1015 cm'3). The nMOS and pMOS threshold voltages are 0.23 V and -0.25 V, respectively, and both devices show a near-ideal 65 mV 91 Figure 4.14 Predicted current-voltage characteristics of 50 nm asymmetrical (n+/p+) DG/CMOS devices. The dashed curves are single-gate (SG: back gate grounded) characteristics at Vds = Â±1.0 V. For both nMOS and pMOS devices, S = 65 mV for DG whereas S = 90 mV for SG. 92 subthreshold gate swing (S). The latter characteristic reflects a dynamic threshold voltage due to the gate charge coupling [Yeh96], and minimal SCEs. The on-state currents (Ion) are very good: 0.8 mA/fim for nMOS and 0.6 mA/(im for pMOS at = 1.0 V. These currents are comparable, as are the predicted transconductances (1.0 mS/pm and 0.85 mS/gm), because they are limited in the model by carrier velocity saturation; vsat (7-8x10 cm/s) for holes and electrons is nearly the same. (Velocity overshoot, or quasi-ballistic transport, which tends to extend this limit, especially for electrons [Fra92], is not accounted for here. Carrier energy quantization [Jal97], which tends to offset the benefit due to overshoot, is neglected as well.) The near-ideal S underlies enhanced Ion relative to the singleÂ¬ gate (SG: back gate grounded) counterpart, even for the asymmetrical DG design, as indicated in Figure 4.14. The predicted current enhancement versus Vjjd is illustrated in Figure 4.15 for the nMOS device. For low V^d, Ion is more than double that of the SG device, even though the DG MOSFET has only a single predominant channel. The superiority of the DG device is further illustrated in Figure 4.16 [Cho98] [Fos98b], which shows the predicted intrinsic gate capacitance-voltage characteristic contrasted to that of the SG device. The DG capacitance is nearly zero in the subthreshold region because of device neutrality, i.e., dQ(jf = -dQQ^ [Cho98]. Of course, in the suprathreshold region the DG capacitance is higher because of the two gates, but not double that of the SG device because there is only one strongly inverted channel (for low enough Vqs)- 93 VDD (V) Figure 4.15 Predicted V^d dependence of the DG/SG Ion ratio for 50 nm asymmetrical nMOSFETs. Note that the off-state (Vqs = 0) current in the DG and SG devices is the same. cGG m 94 VGS (V) Figure 4.16 Predicted intrinsic gate capacitance for 50 nm asymmetrical DG and SG nMOSFETs (W x L = 10 pm x 50 nm; V^g = 50 mV). Note that the DG on-state capacitance will be twice that of the SG device only for higher Vgg at which the back channel is strongly inverted. 95 4.4.2 GIDL Effects for 50 nm Asymmetrical DG CMOS The predicted Ids'^GS characteristics shown in Figure 4.14 do not include GIDL. Accounting for GIDL in DG/SOI MOSFETs has been implemented in the UFSOI/FD model. It includes GIDL components originating in both the front and back gate-overlap regions: ^GIDL ~ ^GIDL(f) + ^GIDL(b) (4.20) where I GIDL(f/b) _ ^7DL(f/b)n(lmnEg(~qVBD)â€” EsD(f/b)^ f BGIDL ^ B GIDL E (4.21) sD(f/b) as developed in Chapter 3. Here, IgidL(9 and ^GIDLCb) are GIDL currents in front and back gate-overlap regions derived, and _ VGD-VFB(f/b) + â€”^-VBD EsD(f/b) = ^ 2 â€¢ (4.22) ,-5^ox(f/b) As shown in Equation (4.21) and discussed in Chapter 3, GIDL current is exponentially dependent on the electric field (Eg^f/b)). For asymmetrical (n+ and p+) gates, the flatband voltage in Equation (4.22), VFB^ = ^MScf) - Qff/Cox(f/b), will differ from that for the back gate by about the bandgap (Eg/q = 1.12 V at 300 K, less bandgap narrowing defined by heavy doping) as defined by the work-function differences. Hence, because of the exponential dependence on EsG(f/b), defined by Equation (4.22), the GIDL 96 current at one surface will be much larger than that at the other, meaning that the DG Iqidl in Equation (4.20) will tend to be much greater than that for a typical single-gate MOSFET. For example, for an asymmetrical DG nMOSFET having an n+ front gate and a p+ back gate, Igidlcw Â» â– ^GIDL(f)- With the GIDL effects now included, the IdS'^GS characteristic shown in Figure 4.17 is predicted for the asymmetrical DG nMOS device of Figure 4.14 at Vqs = 1-0 V. We assumed DL(f/t>) = 20 nm in both front and back gate, but the predominant structural dependence of Igidl is defined by the noted exp(BGiDL/EsD(f/b)) term in Equation (4.21). (We assumed a typical value for Bgidl = 5.8xl07 V/cm; we note that variations in Bqjdl could alter our results, but the general insight they afford is not equivocal.) This strong dependence on EsQ(f/b), which results in huge GIDL current due to the back (p+) gate (where ^MScb) ~ E(j/q) and hence high off- state current, is made evident in Figure 4.17 by including the predicted characteristic of the SG counterpart, for which I0ff is unaffected by GIDL. We also include in Figure 4.17 the asymmetrical device characteristic predicted when the parasitic BJT is turned off in the UFSOI model. Indeed, the BJT, via Equation (3.29), is quite significant in defining the GIDL-controlled component of drain current in this device. The excessive GIDL-induced drain current (Igidl = ^GIDL(b)) in the asymmetrical DG device tends to undermine I0ff, and must somehow be controlled. Changing the back p+ gate to n+, i.e., going to a symmetrical- 97 VGS (V) Figure 4.17 Predicted current-voltage characteristics of the 50 nm asymmetrical DG nMOSFET of Figure 4.14 (W = 10 pm) including GIDL current, with and without the parasitic BJT amplification. The predicted characteristic of the SG counterpart (slightly different from that in Figure 4.14 due to minor UFSOI code revisions) makes the huge amplified GIDL current at the back (p+) gate of the asymmetrical DG device evident. 98 gate design, would suppress the excessive GIDL current, but, as noted previously, would give unacceptable (negative) threshold voltage. Use of different gate material does not seem to be a viable option; e.g., mid-gap gates yield threshold voltages that are too high for ~ 1 V or less [Yeh96]. Reducing (3 in Equation (3.29) is not feasible for extremely short L, and, as implied previously, reducing DL in Equation (4.21) is not effective. Insight from Equations (4.21) and (4.22), applied to the back surface and the p+ back gate, suggests that increasing the back-gate thickness (toxj,) will substantively decrease iGlDL(b) v^a a reduction in EsD(b). The predicted subthreshold characteristics for the asymmetrical DG nMOSFET with increasing toxk shown in Figure 4.18 confirm this suggestion. Moderate increases in toxt> reduce Igidl and loff dramatically; but increasing it too much tends to deteriorate the subthreshold channel- current characteristic because of excessive SCEs involving source/drain field fringing in the back oxide [Yeh96]. As indicated by the I0ffvs. toxb plot in Figure 4.19, there seems to be an optimal thickness for off-state current control: ~3 nm in this case. Interestingly, as indicated by the Ion vs. toxb plot also included in Figure 4.19, such optimization can also yield higher drive current than that of the device with toxb = toxf = 2.5 nm in Figure 4.14. Increasing toxb, while suppressing lGiDL(b)> reduces the threshold voltage via the noted SCEs; design optimization based on tailoring toxb to effect a good I0ff versus speed trade-off is implied. The predicted ring- 99 VGS (V) Figure 4.18 Predicted current-voltage characteristics of the 50 nm DG nMOSFET of Fig. 1 (W = 10 |im, toxb = toxf = 2.5 nm) with increasing values of back-oxide thickness. Ioff (|iA) 100 toxb (nm) Figure 4.19 Predicted off- and on-state currents of the 50 nm DG nMOSFET of Figure 4.14 (W = 10 |im) versus back-oxide thickness. (mA) 101 oscillator delays plotted in Figure 4.20 for different toxb suggest that while controlling I0ff and static power, the asymmetrical DG/CMOS speed, affected by the back-gate capacitance as well as Ion, can be enhanced, especially at low V^r). With such design optimization, very low-voltage DG/CMOS is clearly projected to be far superior to the bulk-Si counterpart when the lateral scaling limit is approached. 4.5 Conclusions The insights gained from simulation results of 0.1 pm FD/SOI MOSFETs predict that an FD/SOI technology using complex doping variation such as halo-doped structure will not be so promising for future FD/SOI CMOS applications; the highly doped halo structure induces floating-body effects similar to PD/SOI CMOS. This study for FD/SOI MOSFETs strongly suggests that FD/SOI CMOS needs a significant technology innovation for viable FD/SOI CMOS in the future; DG CMOS seems to be that innovation. Based on numerical device simulations, we conclude that scaled asymmetrical DG MOSFETs, with n+ and p+ polysilicon gates, yield the same or higher current drive at low than the symmetrical DG counterparts. Further, they are easier to fabricate, give more design flexibility, are more forgiving regarding gate underlap, and could be more amenable to Lmet < 50 nm CMOS applications because of better SCE control. In addition to threshold control, the key feature underlying the 102 t0xb (nm) Figure 4.20 Predicted gate propagation delay versus back-oxide thickness (for pMOS as well nMOS devices) and supply voltage by UFSOI/SOISPICE simulations of an unloaded 9- stage CMOS-inverter ring oscillator comprising 50 nm asymmetrical DG devices. 103 asymmetrical-gate CMOS superiority is the extended gate-gate charge coupling (â€œdynamic threshold voltageâ€) and the reverse inversion-layer capacitance effect, which enable low I0ff and extraordinarily high Ion. The charge coupling is preempted in the symmetrical DG MOSFET by the two- channel inversion charge which pins the surface potentials. A simulation-based analysis of extremely scaled DG/CMOS, using the process-based UFSOI/FD model in SOISPICE, has been described. Device and ring-oscillator simulations projected enormous performance potential for DG/CMOS at very low voltages, even with asymmetrical gates needed for proper threshold voltage. For Leff = 50 nm, delays less than 5 ps for = 1.0 V and less than 10 ps for = 0.5 V were predicted. The effect of GIDL on off-state current, which can be severe in asymmetrical (n+ and p+ polysilicon gates) devices, was emphasized. Simulations of the nMOS device showed, however, that the GIDL effect and I0ff can be controlled by tailoring the back (p+-gate) oxide thickness, and such tailoring further gives some flexibility in the required threshold voltage. The simulation results thus give good insight regarding possible design optimization for speed as well as static power in DG/CMOS circuits. CHAPTER 5 25 NM DOUBLE-GATE CMOS DESIGN 5.1 Introduction As the end of SIA roadmap is approached, oxide thickness and power supply voltage for bulk-Si and SOI MOSFETs should be continuously scaled down to control short-channel effects (SCEs) [Sem99]. However, oxide tunneling [Lo97] and non-scaling of threshold voltage (V-jO [Iwa99] are fundamental issues. A possible device design for 25 nm bulk- Si CMOS was shown using two-dimensional nonuniform (super-halo) doping profiles [Tau98b]; however the bulk-Si device, designed with such a complex super-halo structure, still shows significant SCEs, including drain-induced barrier lowering (DIBL) [Tau98a]. Double-gate (DG) MOSFETs can potentially overcome this hurdle for SCEs because of the electrical coupling of the two gates. Furthermore, the DG MOSFET has better performance potential due to its inherent higher mobility [Ern99] and less field-induced carrier energy quantization [Jal97]. Two types of DG CMOS can be designed for future 25 nm CMOS technology: symmetrical DG [Fra92] and asymmetrical DG CMOS [Fos98b]. From the insights drawn from Chapter 4 and from previous analyses of 50 nm DG CMOS via MEDICI [Ava99] and UFSOI/FD in SOISPICE [Fos98a], [Yeh96], optimal design and more comprehensive 104 105 analysis of 25 nm asymmetrical DG CMOS, with comparison to bulk-Si CMOS and symmetrical DG CMOS, are presented. Quantum mechanical issues [Ern99], [GÃ¡m98], [Jal97], [Maj98] and non-ideal effects including gate overlap and gate underlap [Won94j are discussed and considered in the design and analysis of the devices [Cho98], [Fos99]. MEDICI, SCHRED-2 [VasOO], and UFDG in SPICE3 [ChiOl] are used for design and analysis of 25 nm asymmetrical DG CMOS. Use of the classical physics- based two-dimensional (2-D) numerical simulator (MEDICI) for designing such extremely scaled DG devices does not account for quantum- mechanical effects, but mainly gives insights regarding SCEs. This chapter is organized as follows. In Section 5.2, preliminary 25 nm DG device design including analysis of SCEs based on MEDICI simulations is presented. In Section 5.3, analysis of quantum-mechanical confinement, which severely occurs in the 25 nm devices due to high transverse field and thin film, is analyzed using the one-dimensional (1- D) self-consistent Shrodinger-Poisson solver SCHRED-2 [VasOO]. Then, in Section 5.4, the 25 nm DG devices are re-designed via MEDICI by considering quantum-mechanical corrections. The study of SCEs and device sensitivity regarding channel doping, front- and back-gate oxide thicknesses, Si-film thickness, bottom-gate underlap, all with regard to CMOS speed estimation for newly designed DG devices, are included as well. Finally, UFDG [Chi01]-aided 25 nm DG CMOS circuit performance projection is presented in Section 5.5. 106 5.2 Preliminary Classical MEDICI-Based Design 5.2.1 Device Characteristics We first simulated a 30 nm symmetrical DG nMOSFET [Fra92] having abrupt source/drain junction (i.e., Leff = Lmet = 30 nm [Tau98a]), using the 2-D numerical device simulator (MEDICI) [Ava99] with its hydrodynamic (HD)-transport option, considering velocity overshoot effects [Pin93]. The device structure is designed according to [Fra92], with lightly doped (N^ = 1015 cm'3) and thin (tgi = 5 nm) Si-film, and relatively thick (tox = toxf = toxb = 3 nm) gate oxides. The gate material, or work function, is arbitrary here; we used a â€œmid-gapâ€ gate material = XgÂ¡ + 0.5Eg(gj)). To account for ballistic transport [Fra92] in the 30 nm DG device with the HD model in MEDICI simulation, we estimate the energy relaxation time (xn = xp = 0.56 ps) from the experimental values of energy relaxation length ()iw(n) = ^w(p) = 65 nm) [Slo91] and saturation velocity (vsat(n) = vsat(p) = 7xl06 cm/s) [Tau93]. Figure 5.1 shows MEDICI- simulated current-voltage characteristics for the 30 nm symmetrical DG nMOSFET, with comparison to Monte-Carlo predicted results [Fra92]. As discussed in Chapter 2, the 30 nm DG nMOSFET current reaches the limit current, which is well calibrated with the HD model as shown in Figure 5.1. This implies the electron velocity near the source in MEDICI simulation is close to the thermal-limit velocity (v-jO [Lun97]. A 25 nm asymmetrical DG nMOSFET is simulated with the same HD models extracted for 30 nm symmetrical DG nMOSFET. The assumed (uirl/yiu) Sdj 107 VDS (V) Figure 5.1 MEDICI-predicted current-voltage characteristics for the 30 nm symmetrical DG nMOSFET with tgi = 5 nm, = 1015 cm"3, and tox = toxf = toxb = 3 nm, contrasted to Monte Carlo simulated results. V-p is determined by a criterion of Vqs for a IDS/(W/Leff) ~ 10"7 A [Fra92], 108 source-to-drain profile (in y) is shown in Figure 5.2 which defines that the metallurgical channel length (Lmet) is 18 nm, but the effective channel length (Leff) is 25 nm [Tau98a]. The Si-film body is lightly doped (N^ody = 1015 cm'3) and quite thin (tgÂ¡ = 5 nm ~ Leff/4 [Tau98a]) to control SCEs, and the gate oxide is scaled down to the thickness limitation implied by gate tunneling current (tox = toxf = toxb = 1.5 nm) [Lo97] to achieve higher current drive and better short-channel controllability. The gates are n+ and p+ polysilicon. As depicted in Figure 5.3, the asymmetrical DG nMOSFET shows excellent performance; a near-ideal subthreshold gate swing (S = 65 mV), immunity to SCEs including much suppressed DIBL (DIBL = 34 mV at Vds = 1-0 V), high drive current (Ion = 2.55 mA/pm at Vj)D = 1-0 V), and high maximum transconductance (gm(max) = 4.12 mS/pm at Vpg = 1-0 V). We estimate the electron velocity near the source in the asymmetrical DG device by v(0+) = Ij)g/(WQj(0+)) from Equation (2.1) in Chapter 2, and compare it to the thermal-limit velocity (vpO obtained from SCHRED simulation of the same device structure. The evaluated v(0+) approaches to within 86% of the corresponding vp- = 1.4xl07 cm/s; therefore MEDICI- simulated currents are close to the ballistic limit. The predicted currents in this asymmetrical device reach a bit lower than the limit due to lower carrier mobility (or more surface scattering) for the thinner oxide. Note that v-p is higher for the thinner oxide due to more carrier degeneracy [AssOO]. 109 tÃ o tÃ u -m tÃ Â© O tÃ o O Ã¼jd tÃ â€¢fH & O Q Figure 5.2 MEDICI-predicted source-to-drain doping profile for the asymmetrical DG nMOSFET: Leff = 25 nm and Lmet = 18 nm. 110 Vgs (V) (a) VDS (V) (b) Figure 5.3 MEDICI-predicted current-voltage characteristics for the 25 nm asymmetrical DG nMOSFET: (a) Ids'^GS ^DS = 0-05, 1.0 V and (b) IdSâ€œ^DS Vqq = 0-4, 0.6, 0.8, 1.0 V. Ill In order to compare the device performance of asymmetrical DG, symmetrical DG, and bulk-Si nMOSFETs for equal I0ff, a symmetrical DG device is used with â€œnear-mid-gapâ€ gate material = XgÂ¿ + 0.394Eg(gj)), and a bulk-Si MOSFET is designed with super-steep retrograded (SSR) doping profile to control SCEs as shown in Figure 5.4. Figure 5.5 shows MEDICI-predicted Ids'^gs characteristics of the three devices designed to have equal I0ff for Vj^g = 1.0 V. Figure 5.6 depicts MEDICI-predicted Ion ratios for the three devices. Both asymmetrical and symmetrical DG nMOSFETs show comparable device performance regarding S, DIBL, Ion, and gm(max), as presented for 50 nm DG devices in Chapter 4, but have much better performance than the bulk-Si counterpart. For the bulk-Si nMOSFET, S = 89 mV, DIBL = 104 mV at VDS = 1.0 V, and Ion = 0.93 mA/ pm and gm(max) = 1.88 mS/pm at Vpg = 1.0 V. As shown in Figure 5.5, the Ion(asym/Ion(sym) ratio versus VÂ¡)d is nearly unity due to comparable DIBL (-34 mV for the asymmetrical device and ~35 mV for the symmetrical device at V^g = 1.0 V). However, Ionâ€™s for the DG devices are more than twice that of Ion(bulk)> even for high Vp^ (> 1 V), due to lower V-j and velocity overshoot in DG devices [Fra92]. For decreasing V^d, the Ion ratio significantly increases because S of the DG devices is much lower than that of the bulk-Si device. Note that the MEDICI-predicted currents for strong inversion are much below the fundamental current limits in the bulk-Si device, but close to that in the two DG devices, which is consistent with the conclusion of Chapter 2. Concentration (cm 112 x (nm) Figure 5.4 MEDICI-predicted substrate doping profile for the bulk-Si nMOSFET. Note this device is designed with Leff = 25 nm and Lmet = 18 nm. (uirl/v) sal 113 VGS (V) Figure 5.5 MEDICI-predicted current-voltage characteristics for the 25 nm asymmetrical DG, symmetrical DG, and bulk-Si nMOSFETs, which have equal I0ff for V^g = 1.0 V. ratio 114 VDD (V) Figure 5.6 MEDICI-predicted Vqj) dependence of asymmetrical /bulk-Si Ion and asymmetrical/symmetrical Ion at Leff = 25nm and tox = 1.5nm. 115 For low Vqs = 0.05 V in Figure 5.5, the effective electron mobility (|in(eff)) [Tau98a] in the simulated symmetrical DG device is -600 cm2/V-s at VGS = 0 V, which is consistent with Monte Carlo simulated results [GÃ¡m97]. For the asymmetrical one, fAn(eff) is ~350 cm2/V-s, which is lower than that of the symmetrical counterpart because of higher transverse field in the asymmetrical device. In the expression of the on-state current of an nMOSFET, Ion = -WQc(0++)v(0++) (5.1) where Qc(0++) and v(0++) are the channel-charge density and carrier velocity just beyond the virtual source (at y = 0++), both Qc(0++) and Ion must be comparable for the asymmetrical and symmetrical DG devices, since the two devices have comparable current as well as charge (see Chapter 4). Therefore, v(0++) must be nearly equal for the two DG devices. v(0++) in Equation (5.1) can be expressed as v(0++) = pn(eff)Ey(0++) (5.2) where Ey(0++), the longitudinal electric field at the y = 0++, is higher for higher drain-saturation voltage VGg(sat): Ey(0++) Â°c VGg(sat)/Le with Le < Leff due to channel-length modulation [Vee89]. The asymmetrical device has lower JJ-n(eff) due to higher transverse field (pin(ef0 oc Ex"1) [Tau98a]. However, the higher front-channel charge density in asymmetrical DG device, Qcf(asym) = 2Qcf(sym), yields a higher VDS(sat) [Tau98a], which 116 implies Ey(0++) is higher in the asymmetrical device. This higher Ey(0++) in the asymmetrical device tends to counteract the mobility-degradation effect and gives near-equal v(0++) with the symmetrical counterpart. Hence the asymmetrical DG device can have near-equal current with the symmetrical device even at the ballistic limit [AssOO]. Figure 5.7 shows off-state current (I0ff) versus on-state current don) with varying oxide thickness (tox = toxf = toxb) for symmetrical DG, asymmetrical DG, and bulk-Si nMOSFETs. Note that three devices have equal I0ff for tox = 1.5 nm and Vpjg = 1 V. For the bulk-Si MOSFET, I0ff is increased with decreasing tox due, in part, to the decreased V-p and to the increased gate capacitance. For very highly doped channel (> 1018 cm'3), the Qd/Cox term in the V-p formalism [Tau98a] becomes significant, thereby decreasing V-p with decreasing tox. For the symmetrical DG device, I0ff decreases as tox decreases due to the suppressed SCEs, or improved subthreshold slope. For the asymmetrical DG device, I0ff is reduced with decreasing tox down to 1.5 nm due mainly to the suppressed SCEs, but for further scaling of tox below 1.5 nm, I0ff increases due to the decreased V-p and the increased gate capacitance. This asymmetrical device can be optimally designed around tox = 1.5 nm, due to less sensitive I off (or V-p) for the variation of tox. As shown in Equation (4.19) of the previous chapter, V-p in the asymmetrical DG device is a function of the gate-gate coupling factor r, which can be expressed as r = (1 + tgi/St^)'1 for toxf = toxio = tox; r can be a significant factor for tgi/3tox > 1, or for tox < (uirl/v) JJÂ°i 117 Ion (mA/|im) Figure 5.7 MEDICI-predicted I0ff versus Ion characteristics with varying tox (= 1.0, 1.5, 2.0, 2.5, 3.0 nm) at Vj)j) = 1.0 V for the 25 nm asymmetrical DG, symmetrical DG, and bulk-Si nMOSFETs, which have equal I0ff for tox = 1.5 nm. 118 1.67 nm for tgÂ¡ = 5 nm. However, this analysis may not be applicable for tsi Â» Leff/4 due to the increased SCEs. 5.2.2 Short-Channel Effects In several respects, DG MOSFETs have much less severe SCEs [Vee89] than conventional bulk-Si MOSFETs. In DG devices, the electric field generated by the drain is better screened from the source end of the channel, due to the two-gate control. Low body doping in DG devices yields negligible depletion charge shared by the gates. However, SCEs in DG MOSFETs could arise by perturbation of lateral potential profile, which yields DIBL and slight degradation of subthreshold slope. As depicted in Figure 5.8, the asymmetrical and symmetrical DG devices show comparable SCEs, but they are dramatically suppressed relative to those of the bulk-Si counterpart. 5.2.2.1 Drain-Induced Barrier Lowering To model DIBL, we must solve the two-dimensional Laplaceâ€™s equation for the V^g-induced incremental change of the potential in the depleted body region [Vee89]: ~s 2 2 â€”tA\|/ + â€”â€”= 0 . (5.3) dx dy To obtain a closed-form solution for Equation (5.3), we approximate it as Ioff (A/|im) 119 Leff (nm) Figure 5.8 MEDICI-predicted I0ff versus Leff characteristics at V^s = 1.0 V for the 25 nm asymmetrical DG, symmetrical DG, and bulk-Si nMOSFETs, which have equal I0ff for Leff = 25 nm. 120 â€”-Ay = = -r| (5.4) dx2 dy2 where r\ = (2/Leff2)Vj)s if the incremental longitudinal field AEy(0) at the source is much less than the average field Vj)g/Leff [Vee89]. For very high VDS, Equation (5.4) is not valid since the two partial derivatives are strongly coupled; and for very low V^g, rj can not be assumed to be equal to (2/Leff2)Vj)s since AEy(0) becomes significant. By integrating Equation (5.4) once with respect to x, we get the relationship between the incremental front- and back-surface transverse fields, and by integrating it twice, we determine the relationship between the incremental front- and back-surface potentials: AEsb(y) = AEsf(y) + r|tSi (5.5) and Aysb(y) = Aysf(y) - AEsf(y)tSi - 2 (5.6) Applying Gaussâ€™s law to the front and back surfaces, we get AQcf - Â£SiAEsf - CofAyof - Â£SiAEsf + CofAysf (5.7) and AQcb â€œ _eSiAEsb â€œ CobAVob ~ _Â£SiAEsb + ^obAVsb Â» (5.8) where AQcf and AQcb are an incremental increase of front- and back- surface inversion-charge densities, i. e., sheets in this chapter. From the combinations of Equations (5.5)-(5.8),we get AQcf - (Cof + Cb)A\|isf(y) - CbA\|/sb(y) - Ssitsih 2 (5.9) and AQcb - -CbA\|/sf(y) â€œ ^ob + ^b^Vsbty) â– (5.10) For bulk-Si MOSFETs, we can assume A\|/sb = 0 since the body is neutral, and tgj in Equations (5.5), (5.6), (5.9), and (5.10) must be changed to depletion-region width tÂ¿. With negligible incremental charge AQcf = 0 in weak inversion, the DIBL effect for bulk-Si MOSFETs can hence be represented as . bulk Aysf = ESitdh ^dW^DS 2^ox(1 + a) Lgff(l + a) (5.11) where a = C(j/Cox = 3tox/tÂ¿; the approximations follow from Â£gi/eox = 3. From MOSFET theory [Tau98a], tÂ¿ in Equation (5.11) can be written as t, |4eSikTln(NA/ni) (5.12) 122 For the asymmetrical DG MOSFET, we can assume AQcb = 0 since there is only one predominant channel, and from Equations (5.SIÂ¬ CS.10), the DIBL effect is characterized as AÂ¥safsym esi1^ 2Cof 3tSitoxfVDS Jeff (5.13) For the symmetrical DG MOSFET, the transverse electric field in is always zero at the center of the film (x = tgÂ¿/2). Hence, we integrate Equation (5.4) in x through half of the Si film, which, because AEX = 0 at x = tgj/2 due to the symmetry, yields AEsf(y) = - Ttg_i 2 From Equations (5.7) and (5.14), we get (5.14) AQcf - - eSitSirl 2 + CofAVsf (5.15) With negligible incremental charge AQcf = 0 in weak inversion, the DIBL effect for symmetrical DG MOSFET can be represented as A vT eSitSiTl 2Cof 3tSitoxfVDS 9 9 Leff (5.16) which is same expression as that derived for asymmetrical DG device in Equation (5.13). 123 From the relation between A\|/Sf and AVqs> the DIBL-induced threshold shift can be analyzed as AVt dV, GS = AVpq = , GS dVsf AVsf > (5.17) where dVGg/d\|/sf = 1 for DG MOSFETs and dVQg/dv(/sf = 1 + a for the bulk- Si MOSFET [Vee89]. Figure 5.9 shows MEDICI-predicted AVp between Yds = 0-05 V and 1 V versus Leff, compared with the model predictions based on Equations (5.11), (5.13), (5.16), and (5.17). The models are quite consistent with MEDICI simulation results for the bulk-Si and DG MOSFETs. Note that DIBL is comparable in the DG devices, but is dramatically reduced relatively to that in the bulk-Si device. 5.2.2.2 Subthreshold Slope DG MOSFETs, because of their excellent immunity of SCEs, are expected to have ideal 60 mV subthreshold slope or gate swing (S). Since DIBL causes a parallel shift of the IdS'Ygs curve, the S is independent of Vp)S if other SCEs such as fringing field [Yeh96] and punchthrough [Tau98a] are not significant. Figure 5.10 depicts longitudinal electric potential variations for a long- and an extremely short- channel nMOSFET, which are consistent with MEDICI prediction. In Figure 5.10, the potential for VDg = 0 is written as v|/(x,y) = y^x) + Ay2(x,y) where ^(x) is a one-dimensional (1-D) potential and Ai|/2(x,y) is an incremental potential induced by two-dimensional (2-D) SCEs. For extremely scaled 124 Leff (nm) Figure 5.9 MEDICI-predicted AVqs between Vj)g = 0.05 V and 1.0 V versus Leff characteristics for the bulk-Si, asymmetrical DG, and symmetrical DG nMOSFETs, which have equal I0ff for Leff = 25 nm. 125 Figure 5.10 Longitudinal electric potential variations of a long- and an extremely short-channel nMOSFETs for Vpg = 0; \y(x,y) = \|/j(x) + Av|/2(x,y) where \|/j(x) is a 1-D potential and A\|/2(x,y) is an 2-D incremental potential, and V^j is a built-in potential of source-body junction. As Leff increases, A\|/2(x,y) = 0 occurs for more y values. As Vqs increases, A\y2(x,y) decreases. 126 Leff, A\y2(x,y) is zero only near y = Leff/2 as shown in Figure 5.10. Note that this situation occurs even for well-designed devices with Leff < 25 nm, based on MEDICI-simulated results, and it can be called source/drain junction-induced barrier lowering (SIBL). The region where A\|/2(x,y) is not zero, induces less vertical contollability or more 2-D SCEs, which yield lower d\|/sf/dVQg; hence S could be higher than 60 mV, even for DG devices. As Vqs is increased, Av|/2(x,y) is reduced as indicated in Figure 5.10; hence two gates in DG devices enable better control of SCEs. For Vqs = 0, we apply Poissonâ€™s equation for \|/(x,y), which yields Laplaceâ€™s equation for A\|/2(x,y) since the depletion charge density is not changed by Ai|/2(x,y): â€”pA\|/2 +â€”s-A\|/2 = 0 . (5.18) dx2 dy2 To obtain the closed-form solution for Equation (5.18), we approximate it as 2 2 -^2 A y2 = 2A^2 = â€œho (5-19) dx dy where r|0 is an empirical parameter that must approach zero as Leff increases; it can be characterized by integrating Equation (5.19) from y = 0 to y = yc (critical length), which is defined at AEy(yc) << AEy(0) as indicated in Figure 5.11: 127 Figure 5.11 Longitudinal electric field variation for V^g = 0; the critical length yc is defined at Ey(yc) = Ey(0)/10, and % = Ey(0)/yc decreases as VQg increases. 128 TIO = AEy(0) - AEy(yc) ~ Ey(0) yc " yc (5.20) where the incremental longitudinal field AEy(0) at the source, which is equal to Ey(0) and which is ignored in the DIBL analysis, must be considered for VDg = 0. Note in Equation (5.20) that r|0 decreases as VGg increases. The incremental surface potential A\|/sÂ£> for V^g = 0 can be derived from the same analysis with DIBL. For both asymmetrical and symmetrical DG devices, Av|/Sf2 can be expressed, similar to Equations (5.13) and (5.16), and it is characterized from Equation (5.20): A dg _ esitsi^lo AVsf2 â€œ 2C of 3tSitoxfEy(Â°) 2yc (5.21) where Â£gÂ¡/eox = 3. The subthreshold gate swing (S) can be expressed as kT â€” ln(10) a _ _2 dVsf 60mV 60mV dV -(Â¥sfi + Av|/sf2) GS dV( S(Av|/Â°f2) GS 1 + 5V, GS (5.22) where d\|/sf;i/dVGg = 1 as shown in Equation (4.5) of Chapter 4 and 8(A\|/sf2)/8VGS can be estimated from MEDICI simulations based on Equation (5.21); it could be different for asymmetrical and symmetrical DG devices because their vertical structure-induced lateral potential profiles are different, which causes different SIBL (or A\j/Sf). From the insights of Equations (5.21) and (5.22), DG devices need to be designed 129 with sufficiently thin gate oxides and Si-film in order to achieve low S for short Leff. Note that 5(A\j/sf2)/5VGS has a negative value, since A\j/sf2 is decreased by decreasing T|0 as VGg increases, and 8(A\i/sf2)/5VGS has a smaller negative value as Leff increases, since Ey(0) is less reduced by increasing VGg due to less change of SCEs for variation of VGg. For bulk-Si devices, Av|/Sjf2 can be derived from the same analysis with DIBL, similar to Equation (5.11), and it is characterized from Equation (5.20): . bulk _ EsiVlo _ 3tdtoxfEy(Â°) Â¥sf2 2C0X(1 + a) 2(1 + a)y (5.23) and, since dVgfq/dVQg = l/(l+a) [Vee89], S is characterized as S = (1 + (mV). (5.24) 5(AÂ¿u2lk) svGS Figure 5.12 depicts MEDICI-predicted S versus Leff at V^g = 0.05 V, compared with model predictions where the models are based on Equations (5.22) and (5.24). The models are in good agreement with MEDICI simulation results; we have demonstrated S > 60 mV for DG devices due to SIBL. Note that S is nearly the same for Vpg = 0.05 V and 1 V. S of the asymmetrical DG device is a bit lower than that of the symmetrical counterpart due to higher transverse electric field in the asymmetrical DG device, which causes less SIBL with higher dv|rsf/dVGg. 130 Leff (nm) Figure 5.12 MEDICI-predicted subthreshold swing (S) versus Leff characteristics at V^g = 0.05 V for the bulk-Si, asymmetrical DG, and symmetrical DG nMOSFETs, which have equal I0ff for Leff = 25 nm. Solid curves are based on Equations (5.22) for DG devices and Equation (5.24) for bulk-Si device; 8(A\|/sf2)/5VGS is estimated from MEDICI simulations. 131 5.3 SchrÃ³dinger-Poisson Solver (SCHRED)-Based Analysis 5.3.1 Threshold Shift Quantum-mechanical (QM) effects must be considered in highly scaled MOSFETs, by which the threshold voltage (Vp) is significantly increased due mainly to the high transverse electric field at the silicon surface; AVp Â°c (Esf)2/3 for Esf > 105 V/cm [Jan98], [Tau98a]. We use the one-dimensional self-consistent Schrodinger-Poisson solver SCHRED [VasOO] to gain insight on the QM effects in DG MOSFETs. Figure 5.13 shows predicted integrated electron density versus Vqs in the preliminary designed asymmetrical and symmetrical DG devices; QM results are contrasted to classical ones derived solely from Poissonâ€™s equation. Note how the QM effects increase Vp of the asymmetrical DG nMOSFET by 100 mV and V-p of the symmetrical one by 35 mV. Higher transverse electric field in the asymmetrical device causes more V-p shift [Jan98], [Tau98a]. Below the threshold voltage, the parallel shifts in the Qc-Vqs characteristics are still exhibited, as depicted in Figure 5.14. For the asymmetrical DG device, the transverse electric field is still high enough for QM effects (> 105 V/cm) [Tau98a] in the subthreshold region due to high back-surface electric field, even though the inversion-charge density (Qc) is negligible in the subthreshold region. By Gaussâ€™s law, we write Qc + Esb = Esb - eSi CobVob Â£Si (5.25) -Qc/q (cm 132 Figure 5.13 SCHRED-predicted electron density versus V^g for the asymmetrical and symmetrical DG nMOSFETs with quantum-mechanical (QM) and classical (CL) options; tox = toxf = toxk =1.5 nm, tgj = 5 nm, and =1015 cm'3. Note that the DG devices have equal charge density for V^g = 0 with QM option. UIO) Vfo- 133 Figure 5.14 SCHRED-predicted electron density versus Vqs by log scale for the asymmetrical and symmetrical DG nMOSFETs with quantum-mechanical (QM) and classical (CL) options. 134 where \|/0b = VQbS ' ^GbS ' Vsb- Note Esf = 6xl05 V/cm for the asymmetrical DG device, with toxb = 1.5 nm, at VQg = 0 from Equation (5.25). For the symmetrical DG device, Esf is negligibly small, but the effective Si-film thickness per channel is half of the actual tgÂ¡. Hence, structural quantum confinement [GÃ¡m98] in symmetrical DG device is dominant, and underlies the parallel shift in the Qc-Vqs curve seen in Figure 5.13. For the bulk-Si nMOSFET design in Figure 5.4, the higher transverse electric field at the surface (~2Esf(asym)) due to the significant depletion charge causes more significant quantum-mechanical confinement effects than those in the DG devices. As shown in Figure 5.15, Vp is increased by 180 mV due to QM effects. In order to control V-p in the bulk-Si device, the channel-doping density must be decreased, which would yield more SCEs. 5.3.2 Capacitance Degradation Another important QM effect in MOSFETs is degradation of gate capacitance due mainly to increased inversion-layer thickness (tÂ¿), or lower inversion-layer capacitance (CÂ¿ = egj/tj) by more pronounced carrier distribution [Tau98a], [Vas97]. Figure 5.16 shows SCHRED-predicted electron-density ratios with classical and quantum-mechanical options versus gate voltage overdrive (Vqs ' V-p) for the asymmetrical DG, symmetrical DG, and bulk-Si nMOSFETs. In the QM option of SCHRED simulations of Figure 5.16, the electron density (or gate capacitance) is degraded by -10% for the bulk-Si device, and by more than 10% for the -Qc/q (cm 135 Vqs (V) Figure 5.15 SCHRED-predicted electron density versus Vqs for the bulk- Si nMOSFETs with quantum-mechanical (QM) and classical (CL) options; tox = 1.5 nm and = 5xl018 cm'3. Qc(QM)/Qc(CL) 136 VGs -Vt (V) Figure 5.16 SCHRED-predicted electron density ratios between quantum-mechanical (QM) and classical (CL) options versus gate voltage overdrive (V^g - V-p) for the asymmetrical DG, symmetrical DG, and bulk-Si nMOSFETs. 137 symmetrical DG device, but only by less than 1% for the asymmetrical DG device. The front-gate capacitance is defined as [Tau98a] n _ d(-Qcf) d(-Qcf) dysf 5(-Qcf) dysb (z nc\ Gf = dVGS = 3v|/sf 8Vgs 9v|/sb 3VGS ' The inversion-charge density, or CGf is degraded by lower 3 (-Qcf)/3 \|/sf due to QM effects, since more pronounced QM electron distribution induces more incremental increase of \j/sf for the incremental Qcf. Note that 9v|/sf/ aVGS could be a bit higher by QM effects due to less distributed electrons near the surface, which yields more variation of \|/sf for VGg. Note also that 3 (-Qcf)/3 x|/sb = 0 in the symmetrical DG and bulk-Si devices, but 9(-Qcf)/ 9\|/sb > 0 and 9v|/sb/8VGg > 0 in the asymmetrical DG device due to the extended gate-gate coupling. For the asymmetrical DG device, QM effects decrease the first term in Equation (5.26), but increase the second term because more QM electron density near the back surface induces less variation of \|fs^ for VGg, which yield slightly lower d^sb^^GS hut higher d (-Qcf)/9 Vsb5 hence less degradation of gate capacitance occurs in the asymmetrical DG device. This also implies that in the asymmetrical DG device is less decreased by QM effects than that in the symmetrical DG or bulk-Si counterpart, since CÂ¡ can be defined as d(-Qcf) _ d(-Qcf) + d(-Qcf)c)\|/sb dVsf ~ d\|/sf + 3\j/sb axj/sf â€™ (5.27) 138 the second term is zero in the symmetrical DG and bulk-Si devices, but it is higher by QM effects in the asymmetrical DG device, as discussed above. 5.4 25 nm DG Device Design with Quantum-Mechanical Effects 5.4.1 Device Characteristics Preliminary DG devices were designed based on classical physics in Section 5.2. In this section, the asymmetrical DG device is re-designed with consideration of QM effects, by which device characteristics would be significantly changed. Device parameters such as front- and back-gate oxide thickness and film thickness must be re-considered for optimal design. It is shown herein how we can design DG devices using classical simulator but accounting for QM effects. Then optimal design points are suggested. SCEs for the newly designed DG devices are examined based on previous analysis, and sensitivity of the DG devices to variations of device parameters is studied. Back-gate underlap [Won94] and speed estimation for DG devices are discussed as well. 5.4.1.1 Re-Design for Controlled Off-State Current While keeping off-state current acceptable for VLSI circuit applications according to the SIA roadmap [Sem99], an optimally designed 25 nm asymmetrical DG device is presented. From the Vp formalism given in Chapter 4 (Equation (4.19)), Vp is a function of the gate-gate coupling factor (r = 3toxf/(3toxb + tgj)). Figure 5.17(a) shows MEDICI-predicted current-voltage characteristics with varying Si film thickness. Vp is 139 i 3 Vgs (V) (a) fi =1 03 Q VGS (V) (b) Figure 5.17 MEDICI-predicted current-voltage characteristics for the 25 nm asymmetrical DG nMOSFET at V^g = 1.0 V; = 1015 cm'3: (a) fixed tox = toxf =toxk = 1.5 nm, varied tgj = 5, 6, 7, 9, 10 nm, (b) fixed tgj = 9 nm, varied tox = toxf = toxb = 1, 1.5 nm. 140 decreased for thicker tgÂ¡, because r is decreased. Since is increased by 100 mV due to the QM effect, as shown in Figure 5.13, the optimal tgÂ¡ is 9 nm for controlled I0ff (~ 10-7 A/(im) [GhaOO], [Sem99], Now, for fixed tgÂ¡ = 9 nm, we reduce front- and back-gate oxide thickness down to 1 nm, the ultimate limit, using nitrided-Si02 gates [GhaOO], for controlling the gate tunneling current [Tau98a] and gaining higher current drive. Figure 5.17(b) shows MEDICI-predicted current-voltage characteristics with varying oxide thickness for tgi = 9 nm. From Figure 5.17, optimal 25 nm asymmetrical DG nMOSFET can be, as shown in Table 5.1, designed with tgj = 9 nm, tox = toxf = toxb = 1 nm, and lightly-doped body (N^ = 1015cm'3), which makes highest Ion and controlled I0ff. Note that MEDICI-predicted currents for strong inversion, as shown in Figure 5.17, are close (-87%) to the corresponding ballistic-limit currents. 5.4.1.2 Device Characteristics for Newly Designed DG Devices Figure 5.18 shows MEDICI-predicted current-voltage characteristics for the newly designed optimal asymmetrical DG nMOSFET, with n+ and p+ polysilicon gates, contrasted to the symmetrical device. Note that the symmetrical DG nMOSFET is designed for equal I0ff by using exotic gate material with = X(gÂ¡) + 0.28Eg(gj). The corresponding I0n(asym/Ion(syin) ratiÂ° is plotted versus in the inset of Figure 5.18. Ioniasym/^nisym) is lower for higher VDD up to 1.1 V due to better suppression of DIBL [Tau98a] in this asymmetrical device; 141 Table 5.1 Preliminary and newly designed asymmetrical DG nMOSFETs Device parameter Preliminary Newly Leff (nm) 25 25 Lmet (nm) 18 18 tâ€žxf (nm) 1.5 1.0 toxb (nm) 1.5 1.0 tSi (nm) 5 9 ^body (cm ) 1015 1015 Nds (cm'3) 1020 h-1 o to o however, I0n(asym/Ion(sym) increases for Vj)D > 1.1 V since the back surface in the asymmetrical device becomes strongly inverted. For DG CMOS devices, the asymmetrical DG pMOSFET is designed quite similarly to the nMOSFET as indicated in Figure 5.19; the p+ gate is now the active one. If the same â€œ0.28Eg(gj)â€ gates are used for the symmetrical DG nMOS and pMOS devices, the pMOSFET threshold voltage is much higher as evident in Figure 5.19. In order to obtain I0ff to that of the asymmetrical DG pMOSFET (in which the threshold could be reasonable for CMOS application), an additional, different â€œexoticâ€ gate material in the symmetrical pMOSFET, with = X(gi) + 0.704Eg(gj), must be used, as depicted in Figure 5.19. The Ion(asym/Ion(sym) (uirl/v) SQj 142 VGS (V) Figure 5.18 MEDICI-predicted current-voltage characteristics of the asymmetrical and symmetrical DG nMOSFETs; both devices have equal I0ff for V^g = 1.0 V. The predicted dependence of the asymmetrical/symmetrical Ion ratio for the DG nMOSFETs is shown in the inset. (uirf/v) sal 143 Figure 5.19 MEDICI-predicted current-voltage characteristics of the asymmetrical and symmetrical DG pMOSFETs; tgÂ¡ = 9 nm, tox = W = W =1 nm> and nA = 1q15 cm'3- 144 characteristic of the DG pMOSFETs is quite similar to that of the DG nMOSFETs. 5.4.1.3 Quantum-Mechanical Effects Quantum-mechanical effects are examined for the newly designed asymmetrical DG device, as well as the symmetrical DG device, with comparison to the previous, classically designed DG devices. Figure 5.20 shows SCHRED [VasOO]-predicted electron density versus VQg with classical and quantum-mechanical options for classically (tgÂ¡ = 5 nm, tox = toxf = t^b = 1.5 nm) and newly designed (tgj = 9 nm, tox = toxf = toxb = 1 nm) asymmetrical DG nMOS devices. As shown in Figure 5.20, QM effects equally increase Vp for both asymmetrical DG devices by -100 mV. This is because the transverse electric fields at the surface (Esf) are quite equal in the two asymmetrical devices. The newly designed device has thicker film which tends to decrease Esf, but thinner oxide thickness which tends to increase Esf. More discussion regarding this will be presented in the section 5.4.3. However, the newly designed symmetrical device has less Vp shift (-15 mV) by QM effect, which is predominantly structural confinement and which is not so severe in the thicker Si film, as depicted in Figure 5.21. Newly designed DG devices have larger inversion-layer thickness (tj) due to thicker film [GÃ¡mOO]. More degradation of gate capacitance occurs in the newly designed devices by QM effect, as shown in Figure 5.22; -5% decrease for the asymmetrical device and -20% UID) b/Â°fr- 145 Figure 5.20 SCHRED-predicted electron density versus Vqq for the asymmetrical DG nMOSFETs with quantum-mechanical (QM) and classical (CL) options. rao) b/Â°{)- 146 Figure 5.21 SCHRED-predicted electron density versus Vqs for the symmetrical DG nMOSFETs with quantum-mechanical (QM) and classical (CL) options. Qc(QM)/Qc(CL) 147 VGS -Vt (V) Figure 5.22 SCHRED-predicted electron density ratios between quantum-mechanical (QM) and classical (CL) options versus gate voltage overdrive (Vgs " Vt) for the newly designed asymmetrical and symmetrical DG nMOSFETs, contrasted to the classically designed ones 148 decrease for the symmetrical device result from the QM effect. However, thicker film (tgÂ¿ > 6 nm) for DG devices has many important advantages. Less Coulomb scattering occurs due to thicker tÂ¿ for thicker tgi, which enhances mobility [Bal87], [GÃ¡mOl]. Thicker tgj decreases phonon scattering [GÃ¡m98] as well as self-heating and parasitic series resistance [LÃ³pOO]. 5.4.1.4 Performance Comparison with Quantum-Mechanical Effects DG devices have been designed with consideration of QM effects, which tend to increase the threshold voltage (Vp) and decrease the gate capacitance. The actual threshold voltage (V-p) is written as VT(actual) = VT(CL) + AVT(QM) (5.28) where Vp(CL) is the threshold voltage by classical (CL) analysis and AVt(qm) is the difference of V-p between CL and QM results. Figure 5.23 shows MEDICI-predicted current-voltage characteristics for the newly designed asymmetrical nMOSFET at low Vp>g (= 0.05 V). VT(qd can be estimated by linear extrapolation at the maximum value of transconductance, gm = dIp>g/dVQg. The extracted Vt(cl) in the asymmetrical device is 0.13 V, and AVp is obtained as 0.1 V by QM simulation result as shown in Figure 5.20. Hence, VT(actuap is inferred as 0.23 V at low Vp)g. For high Vp)g, Victual) is decreased by DIBL effect, and in the newly designed 25 nm asymmetrical DG nMOSFET is estimated as 0.18 V at Vpg = 1 V; i. e., the Ids'^GS curve is (rigidly) shifted by 50 mV (uiri/gui) 149 a a Gfi Figure 5.23 MEDICI-predicted I^g and transconductance (gm) versus Vqs characteristics of the asymmetrical DG nMOSFET at Yds = 0.05 V; VT(CL) is estimated by linear extrapolation at the maximum value of gm. 150 for Vj)g = 1 V. By the same methodology, Victual) in the newly designed symmetrical DG device is calculated as 0.165 V at V^g = 0.05 V and 0.111 V at Vj)g = 1.0 V; these values are lower than those of the asymmetrical device due to the lower AVt(qm) in the symmetrical device. As shown in Figure 5.18, Ion of the classically designed symmetrical DG nMOSFET is higher than that of the asymmetrical counterpart at VDD = 1 V; Ioniasym/Wsym) = Â°-86- However, the Ionâ€™s are comparable for QM designs due to more degradation of gate capacitance in the symmetrical device; I0n(asym/Ion(sym) = 1-02. Table 5.2 describes the projection of asymmetrical DG device with considering QM effects. The asymmetrical DG nMOSFET has much higher Ion (~x4.3) at Vod = 1 V than 25 nm bulk-Si nMOSFET designed with tox = 1.5 nm [Tau98b], Note that I0n(asym)Hon(bulk) Â» 2 results from thinner oxide (1.0 nm versus 1.5 nm), lower threshold voltage (0.18 V versus 0.25 V), and being closer to ballistic limit in DG devices as discussed in Chapter 2. The DG devices have less DIBL (~50 mV), superior to that of the published bulk-Si nMOSFET (~70 mV). 5.4.2 Short-Channel Effects for Newly Designed Devices The newly designed DG devices are far superior to the published bulk-Si device in controlling SCEs [Tau98b]. For 20% decrease of Leff from Leff = 25 nm, I0ff of the DG nMOSFET is -8 times higher as shown in Figure 5.24, but I0ff of the bulk-Si device is -25 times higher [Tau98b]. Note that I0ff is varied by Leff a bit more in the symmetrical device in 151 Table 5.2 Projection of newly designed asymmetrical DG nMOSFET Ion at Vdd = 1 V 3.6 mA/pm I0ff at VDS =1 V 5.5xl08 A/pm gm(max) at VDS = 1 V 5.5 mS/pm Vp at Vpjg = 1 V 0.18 V DIBL at VDS = 1 V 50 mV S 70 mV Figure 5.24. This result is opposite for the previous design as depicted in Figure 5.8. As film thickness is thicker, SCEs are more prevalent in the symmetrical DG device due to lower transverse electric field in the thicker film. Figure 5.25 shows MEDICI-predicted AVp (or DIBL) versus Leff for the DG devices. The previously discussed DIBL models are in a good agreement with the simulated results. It is interesting that the asymmetrical DG device exhibits less DIBL. Figure 5.26 shows MEDICI- predicted subthreshold gate swing (S) versus Leff for the DG devices. S of the asymmetrical device is lower than that of the symmetrical counterpart. The previously discussed subthreshold slope models are consistent with the simulated results. The asymmetrical DG device has higher transverse electric field, which yields more gate (1-D) control (or (uirl/v) &Â°i 152 Figure 5.24 MEDICI-predicted I0ff versus Leff characteristics at V^g = 1.0 V for the asymmetrical and symmetrical DG nMOSFETs, which have equal I0ff for Leff = 25 nm. 153 Leff (nm) Figure 5.25 MEDICI-predicted AV^g between Vpg = 0.05 V and 1.0 V versus Leff characteristics for the asymmetrical and symmetrical DG nMOSFETs, which have equal I0ff for Leff = 25 nm. 154 Figure 5.26 MEDICI-predicted subthreshold swing (S) versus Leff characteristics at Vj)s = 0.05 V for the asymmetrical and symmetrical DG nMOSFETs, which have equal I0ff for Leff = 25 nm. Solid and dashed curves are based on Equation (5.22); DG 5(A\|/sf2)/8VGS is estimated from MEDICI simulations. 155 higher d\j/sf/dVQg), thereby turning out less DIBL and lower S from Equations (5.17) and (5.22). 5.4.3 Sensitivity Study Device characteristics are changed by structural variations, mainly because threshold voltage is changed. In Chapter 4, the derived analytic expression for threshold voltage in DG nMOSFETs, Equation (4.19), is a function of the front-surface potential (\j/sf), which can be expressed from classical theory as [Tau98a] (5.29) where n(0) is the electron density at the surface, nÂ¡ is the intrinsic carrier density, and <|)p = (kT/q)ln(N^/nj) is the film-body Fermi potential in p-type Si film; <|)p is also defined as (j)F = | EÂ¡(Â°o) - Ep |/(kT) [Tau98a] where EÂ¡(Â°Â°) is the intrinsic Fermi energy at a hypothetical neutral film-body (x = Â°Â°) [Lim83] and EF is the Fermi energy. For non-degenerated electron density [Tau98a], (5.30) where Nc (= 3.2xl019 cm'3 at T = 300 K [Tau98a]) is the effective density of states in the conduction band and Ec(0) is the conduction-band energy at the surface. By combination of Equation (5.29) and (5.30), we write 156 EÂ¡(Â°o) -Ec(0) q (5.31) Since n(0) in scaled DG devices is higher than Nc for VQg > Vp, Ec(0) is virtually pinned at Ep; Ec(0) - Ep = 0, where |EÂ¡(Â°Â°) - Ec(0)|/(kT) = (|)p. Therefore, Equation (5.31) can be written as (5.32) since (kT/q)ln(Nc/ni) = Eg/2q. With Equations (5.32), (4.19) now gives a well defined threshold voltage. Note that for highly degenerated electron density (n(0) > 1020 cm"3), \|/sf could be a bit higher than that in Equation (5.32)from Fermi-Dirac statistics [Sze81]; it can be expressed as v)/sf = Eg/2q + <|>p + nkT where n > 4. 5.4.3.1 Channel Doping Because of the lightly-doped and thin Si film in DG devices, depletion charge is negligible, which makes device characteristics totally insensitive to doping variations until the doping density becomes very high (~1019 cm"3). For the analytic expression of threshold voltage for asymmetrical (n+/p+-polysilicon gates) DG devices in Equation (4.19), the front and back gate-body work-function differences are written as OQfg = -Eg/2q - <))p and = Eg/2q - <])p [Tau98a]. Using Equation (5.32) for \]/sf in Equation (4.19) thus yields 157 V, Tf(asym) Es + 2q 1 + r s + r^W^-r ^of ÃÃ-- â– - , A 2q 2q) Qb 2CV (5.33) For negligible Qb in lightly doped thin-film DG devices, V-pf^gyjn) is independent of N^. As channel-doping density is increased, (j)p is increased, but it does not effect Vrf(asym) nor inversion-charge density (Qc) because the value of + rO(jbs)Al+r) in Equation (4.19) is decreased by the same amount as the increase of <|)p. Further, changing channel doping type in the Si film of DG nMOSFETs does not effect on DG device characteristics. For n-type channel in the nMOSFET, we can write \j/sf = Eg/2q - (J)p, d>GfS = -Eg/2q + ln(ND/nj); hence VTf(asym) is exactly same as Equation (5.33). 5.4.3.2 Oxide Thickness However, oxide thickness in DG devices is a very important device parameter in determining I0n/I0ff and controlling SCEs. Figure 5.27 depicts the threshold voltage of asymmetrical DG device, as characterized in Equation (4.19) or Equation (5.33); it is a strong function of the gate- gate coupling factor (r = 3toxf/(3toxb + tgi)). Note VTf(asym) = 0.225 V at tgi = 9 nm and tox = toxf = toxb = 1 nm in Figure 5.27, which is consistent with the SCHRED result from the classical (CL) option shown in Figure 5.20. Figure 5.28 depicts front-gate oxide capacitance versus oxide thickness in the asymmetrical DG device, (l+r)C0X in Equation (4.17). Note that total gate capacitance (CG) would be higher than (l+r)C0X due to reverse Tf(asym) 158 Figure 5.27 The threshold voltage V^f in the asymmetrical DG nMOSFET versus oxide thickness. V-pf increases as r increases. (l+r)Coxf (F/cm2) 159 Oxide Thickness (nm) Figure 5.28 The gate capacitance in the asymmetrical DG nMOSFET versus oxide thickness without considering the inversion- layer capacitance Cj. 160 inversion-layer capacitance effect as discussed in Chapter 4. However, the characteristics of Cq. versus V^g has quite similar tendency as Figure 5.28. From Figures 5.27 and 5.28, we can predict characteristics of Ion (or gate capacitance) and I0ff (or V-jO for variation of oxide thickness in asymmetrical DG devices, if SCEs are not severe. As tox = toxf = toxt> or toxf decreases, Vt decreases by decreasing r. However, as toxb decreases, Vp increases by increasing r. Gate capacitance is increased by decreasing tox = toxf = toxk or toxf due to more induced charge for thinner oxide, as shown in Figure 5.27. For decreasing toxb, the front-surface charge is increased by increasing r, which increases gate capacitance as shown in Figure 5.28. Hence, higher r, which implies more coupling, tends to increase Vt and gate capacitance. Physically, coupling increases the back-surface potential \j/sb faster than the front-surface potential \|/sf for increasing V(jg due to positive flatband voltage for the back gate; v[/s^ increases even when \|/sf is nearly pinned due to extended gate-gate charge coupling, as discussed in Chapter 4. This yields lower front-surface electric field (Esf) for given VQg since Esf ~ (\|/sf - Vsb^Siâ€™ which translates to higher Vt- MEDICI-predicted I0ff versus Ion with varying front- and back- gate oxide thickness tox = toxf = toxb, and S versus tox = toxf = toxb for the newly designed DG nMOSFETs are shown in Figure 5.29. The DG devices have equal I0ff for tox = toxf = toxb = 1 nm. For the symmetrical DG device, I0ff decreases as tox decreases due to the suppressed SCEs, or improved 161 (b) Figure 5.29 MEDICI-predicted (a) I0ff versus Ion characteristics with varying tox =toxf = toxb (= 0.5, 1.0, 1.5 nm) at Vde> = 1-0 V, and (b) S versus tox at V^g = 1.0 V for the newly designed asymmetrical and symmetrical DG nMOSFETs. 162 subthreshold slope. As shown in Figure 5.29, S of the symmetrical device is more sensitive to variation of tox than that of the asymmetrical counterpart, which implies more severe SCEs occur in the symmetrical device for thicker tox. For the asymmetrical DG device, I0ff is a bit reduced with decreasing tox down to 1.0 nm due mainly to the suppressed SCEs, but I0ff increases for tox < 1.0 nm due mainly to the increased gate capacitance, as depicted in Figures 5.28. Around a certain value of tox, I0ff(aSym) would be inferred, from the insight of Figure 5.29, to be less sensitive to tox variation than that of the symmetrical counterpart. Ion(sym) and Ion(asym) increase for decreasing tox due to the increased gate capacitance. MEDICI-predicted I0ff versus Ion with varying toxf or toxb, and S versus toxf or toxb for the newly designed DG nMOSFETs are shown in Figure 5.30 and Figure 5.31, respectively. I0ff(Sym) decreases as toxf or toxb decreases due to less SCEs (or lower S) for thinner toxf or toxb. However, I0ff(asym) increases for decreasing toxf under fixed toxb, due partly to the decreased V-p since r is most sensitive to variation of toxf, and due partly to the increased gate capacitance for thinner toxf. As depicted in Figure 5.31, S for the asymmetrical device is lower for thinner toxf. Ion(sym) and lon(asym) increase for decreasing toxf due to the increased gate capacitance. For decreasing toxb under fixed toxf, I0ff(asym) decreases since more gate-gate coupling occurs, reflected by increasing r, which increases V-p, as shown in Figure 5.27, and decreases SCEs with the improved S, as (uirl/v) wÂ°i 163 Ion (mA/|_im) Figure 5.30 MEDICI-predicted I0ff versus Ion characteristics with varying toxf or toxt, (= 0.5, 1.0, 1.5 nm) at Vj)p = 1.0 V for the newly designed asymmetrical and symmetrical DG nMOSFETs. 164 Oxide thickness (nm) Figure 5.31 MEDICI-predicted S versus toxf or toxb at Vdd = 1.0 V for the newly designed asymmetrical and symmetrical DG nMOSFETs. 165 shown in Figure 5.31. Note that r in this asymmetrical device is less changed for Atoxb than Atoxf; r = 3toxf/(3Atoxb + tSi) = 3toxf/tSi for Atoxb Â« tgi (= 9 nm). Note also in Figure 5.31 that S for the asymmetrical DG device is less sensitive to Atoxb than Atoxf, which implies that SCEs are less changed for Atoxb. Ion(asym) is nearly constant for variation of toxb. As toxb is decreased, V-p is increased and SCEs are reduced, which would induce lower I0n(asym)> but gate capacitance is increased, as shown in Figure 5.28, and back channel current is increased, which would induce higher Ion(aSym)- These effects tend to counteract each other, yielding nearÂ¬ constant Ion(asym) regarding Atoxb. 5.4.3.3 Film Thickness The dependence of V-p upon film thickness is a bit more significant in the asymmetrical DG device because V-p is a function of the coupling factor r. MEDICI-predicted I0ff versus Ion with varying tgÂ¡, and S versus tgj for the newly designed DG nMOSFETs are shown in Figure 5.32. As tgj decreases, I0ff(Sym) and I0ff(asym) decrease due to the suppressed SCEs, which also tend to decrease Ion for both devices. I0ff(asym) decreases more than I0ff(Sym) ^ue to the increased V-p by the increased gate-gate coupling (or r) in the asymmetrical DG device. Physically, for the thinner tgÂ¿ in the asymmetrical DG device, more coupling from the back gate induces higher V-p. However, this coupling is limited in the symmetrical DG device when strong-inversion charges at both front and back surfaces 166 (b) Figure 5.32 MEDICI-predicted (a) I0ff versus Ion characteristics with varying tgj (= 8, 9, 10 nm) for = 1 V, and (b) S versus tox at Vj3g = 1.0 V for the newly designed asymmetrical and symmetrical DG nMOSFETs; toxf = toxk = 1 nm. 167 pin the surface potentials; hence Vp is not significantly changed by variation of tgj. 5.4.4 Bottom-Gate Underlap Fabrication of DG devices, scaled down to 25 nm with ideal self- aligned structure, is difficult [Won94]. Back-gate â€œunderlapâ€, yielded by the anticipated difficulty in two-gate self-alignment, was presented at the 50 nm regime in Chapter 4. Figure 5.33 shows MEDICI-predicted Ion and I0ff versus gate underlap ratio LunÂ¿eriap/Leff at Vp>p) = 1.0 V for the DG nMOSFETs. Ion(asym) is nearly constant regarding gate underlap, which is quite similar to Ion(asym) characteristics for tox^ variation as shown in Figure 5.30. As Luncjeriap is increased, less coupling would induce less charge in the front surface, like increase of toxb, thereby lowering Ion(asym)> but the decreased Vp and the increased SCEs would induce higher I0n(asym)> like increase of toxb; hence Ion(asym) Is nÂ°t severely degraded by gate underlap. However, Ion(sym) Is reduced substantially because one channel at the back surface is degraded due to the back-gate underlap. I0ff(sym) does not significantly change, but I0ff(asym) Is increased more for increasing Lun(jerjap due mainly to the decreased Vp for less than 30% of underlap. For the further gate underlap, SCEs occur significantly because back gate does not fully contribute to gate-gate coupling. Figure 5.34 shows MEDICI-predicted S and DIBL versus gate underlap for the DG nMOSFETs. In Figure 5.34, S sharply increases above 30% gate underlap, which increases I0ff(asym) significantly (x7.5 for 168 (b) Figure 5.33 MEDICI-predicted Ion and I0ff versus an assumed back-gate underlap at the source side of the asymmetrical and symmetrical DG nMOSFETs. 169 (a) (b) Figure 5.34 MEDICI-predicted (a) S and (b) DIBL versus an assumed back-gate underlap at the source side of the asymmetrical and symmetrical DG nMOSFETs. 170 40% gate underlap versus x2.8 for the symmetrical device). This I0ff(asym) variation is still acceptable. Note that I0ff(asym) is increased by x8.0 for 20% reduction of Leff, which is ~x3 lower than that for the published 25 nm bulk-Si counterpart [Tau98b] as shown in Figure 5.24. Interestingly, this asymmetrical device has better immunity of DIBL for gate underlap as indicated in Figure 5.34 due to less SCEs (or lower S). The potential barrier at the surface below the uncovered gate is reduced by gate underlap due to less gate control, which induces more DIBL in the symmetrical DG device relative to the asymmetrical device where the back-surface charge is negligible. From the insights of Figures 5.33 and 5.34, gate underlap in 25 nm asymmetrical DG devices would not seriously undermine the technology for VLSI CMOS circuit applications. However, gate underlap would severely degrade the performance of 25 nm symmetrical counterpart due to reduced Ion from Figure 5.33(a). 5.4.5 CMOS-Inverter Speed Estimation Based on the MEDICI-predicted Ionâ€™s, the speed of the DG CMOS inverter for loaded circuits can be estimated by the CV/I metric. For the controlled I0ff (< 100 nA/pm) [GhaOO] and oxide limitation (> 1.0 nm) [GhaOO] due to gate tunneling current, Ion would be the highest at toxf = toxb = 1-0 nm for both DG devices; hence CMOS inverter speed of both DG devices would be fastest at toxf = toxb =1.0 nm for loaded circuits (xioad = ^load^DD^on)- By considering QM effects, Ion for the DG devices is nearly equal, so that Tjoaci would be comparable. However, the loaded DG CMOS 171 circuit could be more than 2 times faster than the bulk-Si counterpart, due to their higher Ion; Ion(DG) > 2Ion(bulk) at equal I0ff as indicated in Figure 5.6. For unloaded circuits, intrinsic CMOS speed (xunioa(j l/v(0+)) for both DG devices would be comparable as well because v(0+) for the DG devices is not significantly different. However, the bulk-Si CMOS device has lower v(0+) due to the lower mobility caused by higher depletion charge and lower Ey(0++). Can the 25 nm asymmetrical DG CMOS be better optimized than the symmetrical counterpart? If the GIDL current [Che87] in the back surface is controlled, the asymmetrical DG device might achieve a bit higher Ion by further reduction of the back-gate oxide toxb down below 1 nm; toxb of the asymmetrical device can be scaled down more than toxf since the electric field of the back-gate oxide (Eoxb) is lower than that of the front-gate oxide (Eoxf) due to the p+ back gate, which yields less gate tunneling current from the back gate under equal oxide thickness (toxf = toxb). From the gate-voltage relations of the DG MOSFET structure shown in Equations (4.13) and (4.14), Eoxf and Eoxb can be written as Eoxf = (VGg - Ysf" Â®GfsVW and Eoxb = -(VGS -Vsb - ^GbsVtoxb- For the limitation of toxf = 1 nm [GhaOO], toxb can be limited by VGS - Vsb ~ ^GbS < VGS ~ Vsf ~ ^GfS toxb lnm (5.34) 172 By assuming \j/sf = (Eg/2q + ())jr)/2 (weak inversion) and vj/st> = 0 (accumulation) for V^g = 0 V, we can evaluate the lower limit of toxb as 0.64 nm based on Equation (5.34). As toxt, decreases, Vp increases as shown Figure 5.27, but Vp can be controlled by increasing tgj. Figure 5.35 shows MEDICI-predicted current-voltage characteristics for the newly designed (toxf = toxb = 1 nm and tgj = 9 nm) and re-optimized (toxf = 1 nm, toxb = 0.64 nm and tgj = 0.95 nm) asymmetrical nMOSFETs. The two asymmetrical devices have equal I0ff for Vp)g = 1 V. The corresponding Ion(re-opt/Ion ratio, plotted versus Vppj in the inset of Figure 5.35, is nearly unity. The I0n(re-opt/Ion ratio increases for higher Vpjp), because the back-surface current for the re-optimized DG device is higher for higher Vdd due to thinner toxb. Ion(asym) is improved only by 2% at = 1 V; hence the asymmetrical DG CMOS could not be much better than the symmetrical counterpart even if GIDL current is suppressed for such a reduced toxb. 5.5 UFDG-Aided Design In this section we study the device and circuit performance using a process-based circuit simulator, UFDG in SPICE3 [ChiOl] [Fos98a]. Performance assessment of the 25 nm asymmetrical DG devices, defined by MEDICI [Ava99] and SCHRED [VasOO], is projected via the classical version of the UFDG model [ChiOl], Although the UFSOI/FD SOI MOSFET model [Fos98a], [Yeh96] has some utility for asymmetrical DG (uiri/v) SQj 173 Vqs (V) Figure 5.35 MEDICI-predicted current-voltage characteristics for the newly designed (toxf = toxb = 1 nm and tgÂ¡ = 9 nm) and reÂ¬ optimized (toxf = 1 nm, toxb = 0.64 nm and tgi = 0.95 nm) asymmetrical nMOSFETs; both devices have equal I0ff for Vds = 10 V. The predicted Vdd dependence of the reÂ¬ optimized/newly designed Ion(asyin) ratio for the DG nMOSFETs is shown in the inset. 174 devices which have only one predominant channel [Cho98], the UFDG model is much more useful because it accounts for strong-inversion charge distribution throughout the Si film [ChiOl], and it is generic, being applicable to symmetrical as well as asymmetrical DG MOSFETs. Note that the charge distribution near the back surface in the asymmetrical device can be significant even for low gate bias; in Figure 4.7, the back- channel current contributes ~5% of the total-channel current at Vqs = 1 V. UFDG-predicted current-voltage characteristics for the 25 nm asymmetrical DG CMOS devices are shown in Figure 5.36. Device structures are the newly designed DG MOSFETs as indicated in Table 5.1; the front- and back-gate oxides are ultimately scaled to 1 nm based on limitation of gate tunneling leakage [GhaOO], and the Si film is lightly doped (1015 cm'3) and quite thin (tgi = 9 nm). The UFDG process-based parameters are well evaluated from the device structures and underlying physics. As shown in Figure 5.36, the UFDG predictions are consistent with MEDICI results; the nMOS and pMOS threshold voltages are 0.15 V and -0.17 V, and subthreshold swings are 70 mV due to minor SCEs. Note that actual threshold voltages should be increased by 0.1 V due to QM effects. To assess circuit performance, we used UFDG to simulate an unloaded nine-stage asymmetrical DG CMOS inverter ring-oscillator, checking speed. Figure 5.37 shows UFDG-predicted propagation delay per stage versus supply voltage. We assumed moderate front- and back-gate (uitÃ/y) SQj 175 VGS (V) Figure 5.36 UFDG-predicted (curve) current-voltage characteristics of 25 nm asymmetrical DG CMOS devices at |Vpsl = 0.05, 1 V, with MEDICI results (points). Delay (ps/stage) 176 Vdd (V) Figure 5.37 UFDG-predicted propagation gate delay versus supply voltage for an unloaded nine-stage 25 nm asymmetrical DG CMOS inverter ring oscillator, with comparison to bulk-Si and PD/SOI CMOS ones. Note that the DG results would actually correspond to somewhat lower (-(V^d - 0.1 V)) due to the QM effect unaccounted for in the UFDG simulations. 177 overlap capacitance. For 40% gate overlap, the estimated delay time is 2.9 ps at Vpo = 0.9 V in Figure 5.37, which is representative of Vdd = 1 V operating when the QM-induced V-p shifts shown in Figure 5.20 are accounted for. The delay time is about 1.7 times faster than that of the 25 nm bulk-Si counterpart [Tau98b], and much faster than 100 nm bulk-Si or SOI CMOS [MisOO]. This faster intrinsic circuit speed for DG CMOS results from lower threshold voltage enabled by lower S, near-zero gate capacitance in the subthreshold region due to device neutrality as shown in Figure 4.16, and higher p and higher Ey(0++) (or Vp>s(Sat))Â» which make Ion(DG) closer to the ballistic limit as discussed in Chapter 2. Asymmetrical DG CMOS, with design optimization as presented here, is clearly projected to have enormous performance potential even for very low voltages. Note that the UFDG-predicted results for 25 nm symmetrical DG CMOS are -15% faster than for the asymmetrical counterpart due to higher Ion; but the actual performance would be comparable if QM effects are considered, due to more degradation of gate capacitance in the symmetrical device (20% versus 5% in the asymmetrical device as shown in Figure 5.22). 5.6 Conclusions 25 nm asymmetrical DG CMOS design was presented with quantum-mechanical analysis. The simulation-based optimal device design in ultimately scaled DG CMOS technology gives a guideline for 178 future revolutionary DG technologies. It was shown that optimal 25 nm asymmetrical DG CMOS is far superior to the bulk-Si (or SOI) counterpart technology, and has comparable performance to the symmetrical DG CMOS counterpart. However, the asymmetrical design appears to be the better DG choice. Gate underlap does not degrade the performance of 25 nm asymmetrical DG device. Therefore, non-self-aligned bottom gate seems viable for asymmetrical DG CMOS circuit, but self-aligned structure must be required for symmetrical DG CMOS counterpart. CHAPTER 6 SUMMARY AND SUGGESTIONS FOR FUTURE WORK 6.1 Summary In this dissertation, design and analysis of DG CMOS for low- voltage integrated circuit applications were presented, and physical modeling of SOI MOSFETs was discussed. The major contributions for the research are summarized as follows. In Chapter 2, fundamental current limits for silicon-based CMOS devices were theoretically discussed. Reported currents obtained in advanced CMOS technologies and Monte Carlo-predicted currents of extremely scaled DG devices were analyzed, and DG CMOS was suggested as a strong candidate for a future CMOS technologies, since it can approach the ballistic-limit current due to relatively low transverse electric field, which will not be the case in the extremely scaled bulk- silicon or SOI devices. In Chapter 3, new modeling regarding gate-induced drain leakage (GIDL) current and reverse-bias trap-assisted junction tunneling current were physically analyzed and implemented in UFSOI models. The model predictions were consistent with experimental data. Effects on devices and circuits were shown mainly to increase off-state leakage current (I0ff) and static power consumption. In Chapter 4, insights gained from simulation results of 0.1 pm FD/SOI MOSFETs suggested that the conventional FD/SOI technology, using complex doping variation such as halo doping, will not be so 179 180 promising for future FD/SOI CMOS applications. Comprehensive analysis of asymmetrical and symmetrical DG MOSFETs was comparatively analyzed. It was suggested that scaled (Leff = 50 nm) asymmetrical DG CMOS with n+ and p+ polysilicon gates, which is easier to fabricate, is more viable to CMOS application, is more forgiving regarding gate underlap, has less severe SCEs, gives more design flexibility, and yields the same or better performance (Ion and gm). A 1-D self-consistent Schrodinger-Poisson solver (SCHRED-2) solidified our theory and results. Although the effect of GIDL on off-state current (I0ff) in asymmetrical DG devices is significant, simulations of the nMOS device showed, however, that the GIDL effect and I0ff can be controlled by tailoring the back (p+- gate) oxide thickness, and such tailoring further gives some flexibility in the required threshold voltage. The simulation results thus give good insight regarding possible design optimization for speed as well as static power in DG CMOS circuits. In Chapter 5, analysis of 25 nm asymmetrical and symmetrical DG MOSFET was presented. Quantum-mechanical issues including carrier confinement, and non-ideal effects including gate overlap and underlap were discussed and applied to design and analysis of the devices. Quasi-ballistic transport (or velocity overshoot) was considered as well. SCHRED-predicted results give quantum-mechanical insight of DG CMOS device, which was applied to design and analysis of 25 nm DG CMOS. Performance assessment of the 25 nm asymmetrical DG devices, 181 based on insights from theoretical analysis and MEDICI- and SCHRED- simulated results, was projected via the UFDG model to have excellent performance potential even for very low-voltage applications. 6.2 Suggestions for Future Work The following research tasks are suggested as future work regarding scaled SOI and DG devices. (1) For negative Vqq, a tunneling current could occur in gate-to-source overlap region, as GIDL current occurs in the gate-to-drain overlap region for negative Vqj). This current, which can be called gate-induced source leakage (GISL) current, could be important for some applications such as pass transistor. Modeling and analysis of GISL current are suggested. (2) Additional tunneling currents, such as forward-bias junction tunneling current and source-to-body direct tunneling current are recommended for study. For scaled SOI nMOSFETs with highly doped-channel, forward- bias junction tunneling current can flow from body to source like recombination current; it could reduce the parasitic bipolar current since VBS decreases when the forward-bias tunneling current turns on. For ultimately scaled (Leff ~ 10 nm) devices, source-to-body direct tunneling current will occur and increase off-state current significantly. (3) Mobility degradation by phonon and Coulomb scatterings in ultra-thin Si films should be addressed. In designing ultimately scaled (Leff < 10 nm) DG devices, the Si-film thickness must be extremely reduced (tgj ~ Leff/3) 182 to control SCEs. For such an extremely thin film (< 5 nm), carrier mobility can be significantly degraded by enhanced phonon and Coulomb scatterings, the latter being due to trapped charge in surface states. (4) More DG CMOS applications are recommended. Based on the methodology provided in Chapter 5, performance of DG circuit can be projected with accounting for QM-induced V-j shift and gate-capacitance degradation. However, QM effects on mobility were not included, but could be important, especially for ultra-thin Si films. In addition, physical modeling of subthreshold slope will be needed for better understanding of performance projection. REFERENCES [AssOO] [Ava99] [Bal87] [Ber74] [Cha98] [Che87] [Che92] [ChiOl] [Cho98] F. Assad, Z. Ren, D. Vasileska, S. Datta, and M. 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Dig., pp. 197-200, Dec. 1998. [Yeh95] P. C. Yeh and J. G. Fossum, â€œPhysical subthreshold MOSFET modeling applied to viable design of deep-submicron fully depleted SOI low-voltage CMOS technology,â€ IEEE Trans. Electron Devices, vol. 42, pp. 1605-1613, Sep. 1995. [Yeh96] P. C. Yeh, â€œModeling and design of deep-submicron fully depleted silicon-on-insulator complementary metal-oxide- semiconductor for low-voltage integrated circuit applications,â€ Ph.D Dissertation, University of Florida, 1996. BIOGRAPHICAL SKETCH Keunwoo Kim was born in Taegu, Korea, in 1968. He received a B.S. degree in physics from Sung-Kyun-Kwan University, Seoul, Korea, in 1993, and an M.S. degree in electrical and computer engineering from the University of Florida, Gainesville, in 1998. He is currently pursuing a Ph.D. degree as a graduate research assistant at the University of Florida. His research interests involve device design and modeling of CMOS technology including digital and analog circuit design. He is particularly interested in double-gate fully depleted SOI MOSFETs and their low-voltage CMOS circuit applications. Upon graduation he will join IBM Thomas. J. Watson research center in Yorktown Heights, New York, as a research staff member working on double-gate SOI devices and circuits. 190 I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Jerry G. Fossum, Chairman Professor of Electrical and Computer Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Gijs Bosman Professor of Electrical and Computer Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Sheng S. Li Professor of Electrical and Computer Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Timothy J. Anderson Professor of Chemical Engineering This dissertation was submitted to the Graduate Faculty of the College of Engineering and to the Graduate School and was accepted as partial fulfillment of the requirements for the degree of Doctor of Philosophy. August 2001 Pramod P. Khargonekar Dean, College of Engineering Winfred M. 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