PROCESSBASED COMPACT MODELING AND ANALYSIS OF SILICONONINSULATOR CMOS DEVICES AND CIRCUITS,
INCLUDING DOUBLEGATE MOSFETS
By
MENGHSUEH CHIANG
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA 2001
ACKNOWLEDGMENTS
I extend my sincere appreciation to the chairman of my supervisory committee, Professor Jerry G. Fossum, for his guidance and support throughout the course of this work. His great knowledge in semiconductor physics motivated my devotion to the field of semiconductor devices. He was a role model for me, put things in proper perspective, and contributed to my positive attitude. I would also like to thank the members of my supervisor committee (Professors Gijs Bosman, Sheng S. Li, Kenneth K. O, and Timothy J. Anderson) for their guidance and interest in this work. I appreciate Mary Fossum, Courtney Feagle, and Erlinda Lane for all of their help preparing trips for numerous research reviews and conferences.
I am grateful to the Semiconductor Research Corporation, and the University of Florida for their financial support. I thank Advanced Micro Devices, Texas Instruments, Purdue University, and MIT for providing much of the data and information in this work. I also thank Avant!, Silvaco, and Cadence for providing software support.
I would also like to thank fellow students Srinath Krishnan, Jonathan Brodsky, Doug Weiser, Duckhyun Chang, Chip Workman, Keunwoo Kim, Yan Chong, Wenyi Zhou, Mario Pelella, Lixin Ge, Bin Liu, Kehuey Wu, Susan Earles and Brian Floyd for their insightful and technical discussions and friendships.
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111
I am fortunate to have my wife, ChiaHui Lin, my son, Tony Chiang, and my daughter, Shannon Chiang, here with me through the long years of graduate study. Finally, I express heartfelt thanks to my father, LungChuan Chiang; and my mother, MinTze Lu, for their endless love and support in many ways through the years.
TABLE OF CONTENTS
p~ge
ACKNOWLEDGMENTS ................................................ii
KEY TO ABBREVIATIONS............................................. vi
ABSTRA CT ...... ....................................................vii
CHAPTERS
1 INTRODUCTION ................................................... 1
2 MODELING POLYSILICON DEPLETION AND ENERGY QUANTIZATION... 7
2.1 Introduction..... ..............................................7
2.2 PolysiliconGate Depletion.......................................8
2.2.1 Model Formalism........................................ 9
2.2.2 Model Implementation and Discussion ...................... 20
2.3 EnergyQuantization Effect .....................................21
2.3.1 M odel Development....................................26
2.3.2 Discussion .... .......................................32
2.4 Verification and Circuit Performance..............................35
2.5 Conclusion ..................................................38
3 UFSOI MODEL PARAMETER EVALUATION: PROCESSBASED
CALIBRATION METHODOLOGY....................................40
3.1 Introduction..... .............................................40
3.2 Parameter Evaluation for NFD/SOI MOSFETs ....................... 41
3.2.1 Preliminary Model Card ................................44
3.2.2 LongL Calibration ....................................46
3.2.3 ShortL Calibration ....................................59
3.2.4 Verification (SelfHeating) ..............................66
3.3 Parameter Evaluation for FD/SOI MOSFETs ........................ 70
3.3.1 Preliminary M odel Card .................................78
3.3.2 LongL Calibration ....................................80
3.3.3 ShortL Calibration ....................................85
3.3.4 Verification .... ......................................89
3.4 Sum m ary....................................................94
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4 DESIGN ISSUES AND INSIGHTS FOR LOWVOLTAGE HIGHDENSITY
SOI DRAM .................................................... 98
4.1 Introduction.................................................. 98
4.2 Dynamic Data Retention ........................................ 99
4.3 Sense Amplifier Operation..................................... 108
4.3.1 Overview of the Sense Amplifier ......................... 109
4.3.2 Dynamic Instabilities..................................112
4.3.3 Designs to Avoid Instabilities...........................116
4.4 Conclusion .................................................123
5 COMPACT DOUBLEGATE MOSFET MODEL ......................... 125
5.1 Introduction.................................................125
5.2 UFDG Development..........................................126
5.2.1 Regional M odeling....................................126
5.2.2 WeakInversion Formalism.............................130
5.2.3 StrongInversion Formalism ............................. 133
5.2.4 ModerateInversion Formalism ........................... 165
5.3 Model Demonstration and Verification ............................ 165
5.3.1 M odel Calibration ....................................166
5.3.2 Model Corroboration..................................173
5.3.3 Device/Circuit Application .............................. 176
5.4 Conclusion .................................................181
6 SUMMARY AND RECOMMENDATIONS FOR FUTURE WORK .......... 184
6.1 Sum m ary................................................... 184
6.2 Recommendations for Future Work..............................187
APPENDICES
A MODELING AND IMPLEMENTATION OF THE CONTINUOUS DRAIN
SATURATION VOLTAGE IN UFSOI MODELS ........................189
B ASSESSMENT OF NOVEL BODYTIEDTOBODY SOI CMOS ........... 196
C ANALYTICAL DERIVATIVES FOR UFSOI SPEEDUP .................. 203
REFERENCES.......................................................207
BIOGRAPHICAL SKETCH ............................................215
v
KEY TO ABBREVIATIONS BTB bodytiedtobody BTS bodytiedtosource CMOS complementary metaloxidesemiconductor DG doublegate DIBL draininduced barrier lowering DICE draininduced current enhancement FB floating body FD fully depleted GIDL gateinduced drain leakage IC integrated circuit LDD/S lightlydoped drain/source MOSFET metaloxidesemiconductor fieldeffect transistor NFD nonfully depleted (partially depleted) SOI silicononinsulator UFDG University of Florida doublegate (model) UFSOI University of Florida silicononinsulator (models)
vi
Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
PROCESSBASED COMPACT MODELING AND ANALYSIS OF SILICONONINSULATOR CMOS DEVICES AND CIRCUITS,
INCLUDING DOUBLEGATE MOSFETS By
MengHsueh Chiang
August 2001
Chairman: Jerry G. Fossum
Major Department: Electrical and Computer Engineering
The main topic of this dissertation is processbased modeling of scaled silicononinsulator (SOI) complementary metaloxidesemiconductor (CMOS) fieldeffect transistors (FETs), including doublegate (DG) MOSFETs. The University of Florida SOI (UFSOI) fully depleted (FD) and partially depleted (or nonfully depleted, NFD) SOI MOSFET compact models are refined and upgraded in order to apply them in simulations of scaled SOI CMOS devices and circuits. For DG MOSFETs, the first version of the University of Florida DG (UFDG) compact model is developed.
As CMOS technologies are being scaled down to deep submicron dimensions, more and more previously unimportant physical phenomena in the shrinking MOSFETs are becoming significant. Polysilicongate depletion and carrierenergy quantization, both of which reduce the drive current and the effective
vii
gate capacitance, are now important, and hence they are incorporated in the UFSOI models to assure accuracy of scaled device and circuit simulations. The UFSOI models are processbased, and hence their calibration must be done properly to ensure their reliability. To obtain a set of unequivocal model parameters, reflecting the process information and underlying physics of SOI MOSFETs, a processbased modelcalibration methodology, which is simple and systematic, is developed and demonstrated for both FD and NFD devices.
We further apply UFSOI to gain insight into the behavior of SOI MOSFETs in integrated circuits via the physical nature of the model. A physicsbased study of floatingbody (FB) effects on the operation of SOI DRAM is done. Design insight regarding dynamic retention time and sensing is provided. However, due to the historydependent FB effects in SOI CMOS circuits, comprehensive and intensive simulations are usually necessary. Hence, approximate analytical derivatives, needed for the NewtonRaphsonbased nodal analysis in circuit simulation, are incorporated in UFSOI in order to reduce the run time for simulationbased study of the hysteresis.
Although SOI CMOS performance is superior to that of the bulksilicon counterpart, its scalability is no better. A revolutionary approach to continuously exploit advantages of SOI without the worrisome FB effects is aimed at technologies like extremely scaled DG CMOS, which is evolved from FD/SOI. To extend the capability of UFSOI/FD for general DG application, a new processbased UFDG model is developed. The UFDG model is generic, enabling the evaluation of different DG structures and technologies at the circuit level. The model is demonstrated in comparisons of symmetrical and asymmetricalgate DG MOSFETs involving device and circuit simulations.
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CHAPTER 1
INTRODUCTION
Silicononinsulator (SOI) complementary metaloxidesemiconductor (CMOS) has become a promising candidate for future mainstream CMOS technologies with its superior attributes such as lower parasitic junction capacitance, immunity to soft error, reduced cross talk and bipolar latchup in circuits, and simplified processing. Two major types of SOI devices, nonfully depleted (NFD), or partially depleted (PD), and fully depleted (FD) SOI MOS fieldeffect transistors (FETs), both showing the inherent SOI superiority over the bulksilicon MOSFETs, are addressed. However, the NFD SOI MOSFET has its unique floatingbody (FB) effects, which makes the reuse of design rules from bulksilicon circuits suboptimal. Further, the FD SOI MOSFET has difficulty in threshold control due to the twodimensional field effects in the silicon film and buried oxide, and to threshold sensitivity to film thickness. To exploit the idea of FD SOI with the expectation of nearideal subthreshold slope and high current drivability, and to scale CMOS to the end of the SIA roadmap [Sem99], the doublegate (DG) MOSFET is of interest in spite of the challenging fabrication issues. All of the issues mentioned above must be examined carefully, and the complicated underlying device physics must be taken into account in reliable device and circuit design. Hence, compact, yet physical models are needed for exploring the possible problems and predicting the potential performance of SOI CMOS integrated circuits.
1
2
This work focuses on upgrades and enhancements of processbased UFSOI models [Suh95a], [Yeh95], [Kri96a], [Cha97], [Wor98], [Fos98b], with a systematic methodology for modelparameter evaluation and applications to optimal SOI CMOS design. Further, it includes the development of a processbased DG MOSFET compact model (UFDG). The models have been implemented in a TypeI interface (API) that can be glued to Spice3e2, as used in this work, or to any circuit simulator.
In contemporary CMOS technologies, the device structures have been scaled down to deep submicron dimensions for highspeed and lowpower applications. As MOSFETs continue to shrink, more and more previously insignificant physical device phenomena become important. Compact device models, which involve many assumptions, must be updated frequently to physically account for such evolution of the relevant device physics. Polysilicongate depletion and carrierenergy quantization, both of which reduce the drive current and effective gate capacitance due to high transverse electric field, are incorporated in UFSOI models, as described in Chapter 2, to ensure accuracy of scaled device and circuit simulations. We physically account for their effects, particular for SOI MOSFETs, on surface potential (threshold voltage), and thus the current (conductance) and charge density (capacitance) are implicitly updated via the physical nature of the models. Our simulation results show that the circuit performance is degraded due to these two effects. In addition to the model upgrades for polysilicongate depletion and carrierenergy quantization, several revisions and refinements of the UFSOI models are incorporated as well. An important refinement that ensures a smooth transition from
3
the linear to the saturation regions of MOSFET operation is developed in Appendix A.
The UFSOI FD and NFD compact MOSFET models are physical and processbased, meaning that their key parameters relate directly to device structure and underlying physics of SOI MOSFETs. The parameter evaluation thus can be and should be done based on knowledge of the SOI technology. Chapter 3 introduces a processbased calibration methodology for UFSOI model parameter evaluation. The methodology, which is simple and systematic, is developed to include some tuning of particular parameters based on only a few electrical measurements of devices having more than one channel length and width in specific bias regions. The methodology can be defined with good physical insight to be reliable and much simpler than conventional parameter extraction, or optimization via leastsquares fits to measured data. In fact, such a processbased methodology seems essential for reliable SOI model calibration because of complications due to device selfheating and dynamic FB effects [Jen96].
We further apply UFSOI to gain insight into the behavior of SOI CMOS circuits via the predictive capability of the physical model. Chapter 4 describes a physicsbased study of floatingbody effects on the operation of SOI DRAM. The SOI has been of interest for highdensity memories operating at low voltage [Yam95] because of its immunity to latchup, low susceptibility to soft errors, suppressed (normal) body effect, and small parasitic (source/drain) capacitance. A physicsbased study of floatingbody effects on the operation of SOI DRAM is done. The study, which is based on device and circuit simulations using the physical UFSOI/NFD model
4
calibrated to an actual PD SOI DRAM technology, addresses the performance of the peripheral circuitry, e.g., the sense amplifier, as well as the dynamic retention of the data storage cell. Design insight for lowvoltage highdensity SOI DRAM is attained. Doable cell design is shown to yield dynamic retention time long enough for gigabit memories, and crude bodysource ties for nMOS, with pMOS bodies floating, are shown to effectively suppress instabilities in the sense amplifier. Therefore, alternative bodytied structures will be applicable to this solution. Besides the body ties suggested in this work, a novel bodytiedtobody (BTB) SOI CMOS inverter configuration is suggested in Appendix B. This new approach is shown to suppress the historydependent FB effects (hysteresis) of SOI CMOS circuits without sacrificing the performance of SOI. However, due to the hysteresis, comprehensive and intensive simulations are usually necessary, and hence the simulation time could be considerable. To reduce the run time for simulationbased studies of the hysteresis, analytical derivatives needed for the NewtonRaphsonbased nodal analysis in circuit simulation are incorporated in UFSOI, as described in Appendix C.
Although SOI CMOS performance is superior to that of the bulksilicon counterpart, it does not provide better device scalability as MOSFETs continue to shrink. A revolutionary approach to continuously exploit the advantages of SOI and to achieve higher performance for sub0.1 gm design without the worrisome FB effects is aimed at technologies like extremely scaled DG CMOS [Fra92] evolved from FD/SOI. In order to extend the capability of UFSOI/FD for general DG application, a new processbased compact model for DG MOSFETs having only physical and structural parameters is developed and is presented in Chapter 5.
5
Because the UFSOI/FD model does not account for the backchannel current in strong inversion, the use of the model for DG is limited; therefore, the model can only apply to a small range of operation for asymmetrical DG (e.g., with n+/p+ polysilicon gates) MOSFETs where the back channel does not reach the condition of strong inversion. However, (near) symmetrical DG (e.g., n+ polysilicon gates for nMOSFETs) MOSFETs need an extended model which accounts for two coupled stronginversion channels. Hence, we develop a generic compact model for the DG MOSFET, beginning with the processbased UFSOI/FD model and extending it to account for stronginversion charge distribution throughout the thin Si film. The generic nature of UFDG enables the assessment and comparison of different DG structures for technology development. More importantly, the compact model is essential for predicting the potential performance of DG CMOS circuits, accounting for parasitics. The utility of UFDG is demonstrated in comparisons of both symmetrical and asymmetrical DG MOSFETs involving device and circuit simulations.
Appendix A addresses the modeling and implementation of a continuous drain saturation voltage (VDS(eff)) in UFSOI models, in conjunction with the model upgrades described in Chapter 2. Due to the piecewiselinear velocity model, a discontinuity in the output conductance previously existed at the boundary of saturation and triode regions. Using the continuous VDS(eff) model, with a refined channellength modulation model, we obtain a unified expression for the channel current and a smooth transition from the linear to the saturation regions of MOSFET operation.
6
Appendix B assesses the performance of a new BTB SOI CMOS inverter configuration. The bodytied NFD SOI MOSFET is a common solution for ameliorating the FB effects, as discussed previously. However, the efficacy and optimization of real (with finite resistance) body ties are crucial. In this appendix, we first discuss the characteristics of a bodytied structure, based on measured and simulated data. Then, the novel BTB SOI CMOS, which can suppress the hysteresis of FB SOI CMOS circuits while retaining the speed performance for low supply voltage, as implied by preliminary simulations, is proposed and explained.
Appendix C presents an efficient speedup scheme applied to the UFSOI NFD model. Due to the historydependent FB effects of SOI CMOS circuits, as revealed in Chapter 4, comprehensive and intensive simulations are usually necessary. However, the inefficient difference approximations, that require four extra calls of the model routine for each call by the NewtonRaphsonbased nodal analysis, were previously used in the model. In order to reduce run time, approximate analytical derivatives, which do not require any extra call of the model routine, are incorporated, and their benefit is noted.
CHAPTER 2
MODELING POLYSILICON DEPLETION AND ENERGY QUANTIZATION
2.1 Introduction
The UFSOI FD [Yeh95] and NFD [Suh95a] MOSFET models are physical and processbased, enabling the prediction of the potential performance of SOI CMOS circuits. However, as MOSFETs continue to shrink, more and more previously ignored physical phenomena become significant, and hence the original models become inadequate for simulation of extremely scaled SOI MOSFETs. Frequent model revisions and upgrades accounting for the new fundamental and technological issues are essential for an effective compact model. This chapter presents the main upgrades of the UFSOI models done in this research.
Polysilicongate depletion and carrierenergy quantization, both due to high transverse electric field in scaled MOSFEETs, are incorporated in the UFSOI models as upgrades in order to assure reliable simulation of advanced SOI CMOS devices and circuits. Although these effects are also common for conventional bulkSi MOSFETs, the physical modeling of them is somewhat different for SOI MOSFETs due to charge coupling and floatingbody effects. For each phenomenon, the new modeling is presented, and impacts on circuit performance are revealed via simulations. In addition to these model upgrades, a refinement that ensures a smooth transition from the linear to the saturation region of MOSFET operation is developed
7
8
in Appendix A. Indeed, the physical nature of the UFSOI models facilitates these upgrades.
2.2 PolysiliconGate Depletion
Current n /p+ dualgate CMOS technology limits the electrically active doping concentration in implanted polysilicon to 5x1019 cm3 [Sch93]. The implant and annealing condition for the polysilicon must be carefully selected to avoid impurity penetration through the gate oxide, while controlling the depth and the lateral diffusion of source/drain junctions [Rio94]. As a result, a depletion layer can exist near the polysilicon/oxide interface, and a significant potential drop can be developed across this depletion region depending on gate biases; this is referred to as the polydepletion effect. Though we can use an electrical oxide thickness to empirically emulate polydepletion effects, it might lose accuracy while the device is further scaled, and further the transient effect of gatedepletion capacitance is ignored in this empiricism. We hence need to account for polysilicon depletion with a physicsbased model.
Some studies presented analytical models [Rio94], [Aro95], [Che95] and characterization [Ric96] of polysilicon depletion for bulk MOSFETs, but they are not fully adequate for SOI MOSFETs. Here, we present new modeling for FD and NFD SOI MOSFETs, and implement this modeling in UFSOI models. We also investigate and discuss the effects of IV and CV degradation due to polydepletion, and its translations to circuit performance. In addition, optimal design criteria for devices as well as circuits are suggested from the simulation results and discussions.
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2.2.1 Model Formalism
The UFSOI models are extended with polydepletion modeling, which is implemented in strong inversion only, since the polydepletion effect is less significant in weak inversion. The reason can be understood from the weakinversion electricfield distribution in Fig. 2.1. The frontgate depletion potential (Ngf) is much smaller than the frontgate surface potential (Vsf) since Np (gate doping) >> NB (channel doping). However, the gatedepletion model is used to evaluate the current and charge solution at the stronginversion boundary, which then influences the moderateinversion solution. The polydepletion modeling still maintains the continuities of charges and currents. Here we discuss the model formalism based on an nchannel device, for both NFD and FD models as implied in [Vee88a]. gf and Channel Charge When VDS = 0
We modify the physical relationship among the frontgate bias, VGfS, the front surface potential, NVsf, the voltage drop across frontgate oxide, Nof, and the workfunction difference, D fms, [Lim83] to account for polysilicon depletion:
VGfS = isf + gf + of+ Dfms, (2.1) which leads to [Vee88a]
f ( Cb Cb Qb(eff)/2 +Qc
VGfS = VfFB + Ngf + 1 + C f sf  C sb  f(2.2) of) of of
where VFB is the frontgate flatband voltage, Cb = s/tb, Cof = Eox/tof, Qb(eff) is the effective body depletion charge, Qcf is the frontgate channel charge, and Vsb is
10
P 0 Ex S
I
VI/gf Wsf Figure 2.1 Schematic of electricfiled distribution in weak inversion.
Electricfiled distribution across (n+) polysilicon (P), oxide (0), and (p) silicon
(S) in an nMOSFET biased in weak inversion.
11
the backgate surface potential; eox and Fs are the dielectric constants of oxide and silicon, respectively, tof is the front oxide thickness, and tb is the lowdoped film thickness for NFD SOI or film thickness for FD SOI. Similarly, for the back gate [Lim83], [Vee88a]:
VGbS = Wsb + ob + Dbms (2.3)
and
b b Cb Qb(eff)/2 + Qcb VGbS = V FB  obsf + 1+ C sb  ob(2.4) Cob ob ob
where VbFB is the backgate flatband voltage, Cob = ox/tob, and Qcb is the backgate channel charge; tob is the back oxide thickness. The backgate (substrate) depletion potential is not accounted for since the back oxide is very thick, and the field is low compared with that at the front gate. Note that Vsf used here for the derivation of gate depletion has been updated for carrierenergy confinement, as described later in Section 2.3.
Now, consider the frontgate depletion. Using the depletion approximation for the polysilicon gate yields
qNpxdp = qNp 2 1/2 (2.5)
where xdp is the depletion width. Applying Gauss's law to the front polysiliconoxide interface with (2.1), we get
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1/2 f Qdgf = [2EsqNpwgf]1/2 = EoEof = Cof(VGfS  _VsfVgf ims) . (2.6) Thus gf can be solved analytically as
1 2 f
= 12 (qNps + C2of(VGfS  ms
11'gf 2 0 +C(VGfS  (I) flS  Vsf
Cof
2 f2
(qNpEs(qNpEs + 2Cof(VGfS ms  sf))) (2.7)
AQcf(y) and AQcb(y) When VDS > 0
Now, to account for the perturbation due to VDS > 0, we need to evaluate Qcf + AQcf, Qcb + AQcb, sf + AYsf' sb + ANsb, and qgf + ANgf with AVsf(0) = 0 and AxVsf(L) = VDS. When VDS > 0 in strong inversion, the channel charge change due to drain bias, AQcf, is not included in gradualchannel approximation (GCA), so we follow the DICE analysis [Vee88a], and obtain AEsb(y)= AEsf(y)  tb1, (2.8) and
2
tb(
A'Vsb(Y) = Asf(y) AEsf(y)tb 2 (2.9)
where r1  (2/L2)VDs. Also, (2.1) gives ANsf(y) + ANgf(y) + AVof(y) = 0. (2.10) Applying Gauss's law to the front interface, with (2.8), (2.9) and (2.10), then yields
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AQcf(y) =  CofAVof(y) + EsAEsf(y)
Estbll
= CofAgf(Y) + (Cof + Cb)Asf(Y)  CbAWsb(y) 2 . (2.11)
Although, no backgate (substrate) depletion is accounted for, we also calculate AQcb to give another relation between ANsf and ANsb, which will be used later. Similarly, applying Gauss's law to the back gate, with (2.8), (2.9), and AJsb(y) + Avob(y) = 0 derived from (2.3), yields
EstbT
AQcb(y) = (Cob + Cb)ANfsb(y)  CbAXVsf(y) 2 b (2.12)
2
geff and Ex(y)
In order to check the polydepletion effect on carrier mobility, we apply the polydepletion modeling to the derivation of the low longitudinalfield mobility, geff, which is dependent of the transverse field in the channel. The insightful analysis suggests that the polydepletion effect is negligible and the previous model is still maintained. We demonstrate as follows based on the UFSOI/NFD model,. for which Wsb = VBS (given condition); such a derivation is applicable to the UFSOI/FD model as well.
The field dependence of mobility is modeled [Whi80], [Sun80], [Gar87] by the average of the transverse field as
geff= 1 no (2.13)
1 + OEx(Y)
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where 0 is a mobility degradation factor, and Ex(y) = Exo + AEx(y). Exo is defined at VDS = 0 as [Vee88b]:
 Isf  VBS Qcf Qb(eff) (2.14) EX tb 2s 2s s
where iVsf is pinned at ~20f in strong inversion; and AEx(y) is calculated as CofAVsf(y) AQcf(y)
AEx(y) =  + 2f (2.15) Es 2es
Substituting (2.11) into (2.15), we rewrite AEx(y) as Cb  of Cof tbO AEx(y) = 2 AVsf(Y) + 2 Agf(y)  4. (2.16)
S S
By rearranging (2.13) with (2.14) and (2.16), we can express teff as =no/(1+0 Vsf  VB Qcf Qb(eff) Reff = En/(1 + ( tb 2es 2 s Cb 2 oS Us
+ Cb CoAVsf(y) + Co Agf(y)  t) (2.17) + 2s 2~A~fs y 4 Now, to see the Agf(y) dependence of mobility and also compare it to AVsf(y), we may check the derivative of Aygf(y) with respect to AVsf(y) via (2.7) as Axygf(y) k (2.18) Agsff(y) VGfS = constant
where
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1
k = 1 + (2.19) 2Cof f I + p(VGfS Vsf(0 fms) qNpezS
Then we rewrite geff as ( OCof2Cb Qcf Qb(eff) geff = 2 s C o f V B s)  C C
Cb Cof tbsIo
+ Cof AWsf(y) + kAVsf(y)  2Cof. (2.20)
For conventional SOI CMOS operation in strong inversion, k is only about 0.1 from the estimation of (2.19), which is negligible compared to the coefficient of AVsf(y). Therefore we can ignore the effect of polysilicon depletion on mobility degradation and express geff as [Suh95b]
eff = (2.21) eff 1B(A~sf)
where
4 = Eno (2.22) OCof 2Cb o Qcf Qb(eff) tbsl (2.22)
1 + (sf  Vsb>
2Es .Cof Cof Cof 2Cof
and
B= ~nkOC~fp. (1 Cb)~'
B= Cb (2.23)
2 8 J1,, a Cof)
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Channel Current
For channel current calculation, we need to relate the channel charge, AQcf, to ANsf directly, and hence we can enable the channel charge integration from source to drain to define Ich [Vee88b]. The NFD and FD models are discussed individually with the same methodology as follows.
First, for the NFD SOI model, Nsb = VBS { f(y)}; hence from (2.11)
d(AQcf) = Cofd(AWgf) + (Cof + Cb)d(AxVsf) (2.24) without dAVsb. To obtain a direct connection between dAQcf and dANsf from (2.24), we can relate dAxfgf to dAWsf from (2.6). However, no closedform solution can be found from this nonlinear differential equation. We thus simply use a representative ygf evaluated at the source for the charge derivative, and then a linear equation from (2.6) can be attained:
CofdAVsf + CofdAlgf  CdgfdAxgf (2.25) where Cdgf is computed and approximated as
1 1
Cdf d(AQgf) EsqNp 2 EsqNp2 (2.26)
dgf d(Agf) 2(ygf + AqIgf) 2 gf)
Substituting dAgf from (2.25) into (2.24) yields an expression for the channel charge, dQcf, in terms of the modulated surface potential dNsf, as
dQcf = d(AQcf) = Cof(1 + a')d(AsJf) = Cof(1 + (x')dWsf (2.27)
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where x'  c  1/(1 + ug), X Cb/Cof, and ag Cdgf/Cof.
Next, for the FD SOI model, from (2.12) with AQcb=0, we get the relation between AWsf(y) and AVsb(y), which in (2.11) gives
AQcf(y) = CofAgf(y) + Cof( 1 + a)AXVsf  PCbt211/2 (2.28)
where (x = CbCob/((Cb + Cob)Cof) and 0 = 1 + Cb/(Cb + Cob), which are slightly different when accounting for surface states, as included in UFSOI [Yeh96]. Again, substituting dAxgf from (2.25) into (2.28), we can write
dQcf = Cof(1 + a')dWsf (2.29) where '= a  1/(1 + ag) with ag Cdgf/Cof , which is same as (2.27) but with different cx.
Following the same analysis in [Vee88b] with (2.27) and (2.29) for FD and NFD MOSFETs, respectively, we modify the channel current as
2 2
W.eff(Qcf(0)  Qcf(Le))
Ich = (2.30) 2CofLe(1 + a') 1 + VDSX
where Le and VDSX are effective (smoothed) channel length and VDS, respectively, in strong inversion (see Appendix A), and Reff = 9/(1 fBBVDSX) with constant fB. In addition, VDSX is also a function of a' since we calculate VDS(eff) from (2.30) implicitly in saturation region. Note that the only difference in (2.30) compared with the previous model without polysilicon depletion is a', which reflects a simple yet physical upgrade.
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ChannelLength Modulation
We apply Gauss's law for the VDsinduced incremental field and charge in a subregion of length dy to obtain a differential equation for AVsf(y) [Suh95b]:
AQcf(y)dy = esAEx(tb, y)dy  oxAEox(y)dy + esdy AEydx. (2.31)
Substituting (2.8), (2.11) with y = Le, and oxAEox = EoxAWsf/tox = Cof(AVsf + Agf) into (2.31) and solving for Le, we get (Reff(VDs  VDS(eff))
Le L  lc asinh .s (2.32) e 2Vsatlc
where lc =Estb/(2Cof(1 + a)), which is the same form as the old model but with different VDS(eff). Note that Le is now smoothed, and VDS(eff) is replaced with VDSX (in Appendix A).
Charge Modeling
First, we modify the charge formalism of the NFD model [Cha97] to account for polysilicon depletion:
21
in f VDSX VDSX(l+s)( l+ a')
QGfs = W(L  AL)Cof VGfS gf ms Vsfs 12 Q (0) (2.33)
 1
Cof u u)
2
sat IWALC f 2 cosh AL 1)], (2.34) QGfS = WALCof (VGfS  Vgf  Ims  NfsfS  VDSX) 2 c shL 1 (2.34) I geff (, 1c
19
lin sat (2.35)
QGfS GfS Gfs+ QGfS(2.35) lin 2z  (Z  1)3 )
Qch = W(L  AL)Cof(1 + a')VDsx 2 z + (u  z) , (2.36)
QSatch = WALQ(L AL), (2.37)
lin sat
Qh= ch c+ Qch , (2.38)
Qlin Iv [2(z 1) 4 z (z 1)5 + (u_z) (2.39) D = WLCof(1 + a')VDSX 3 2z  1 15 (2z  1)239) (2z  1)2 ]
sat = W2ALJAQ(Le), (2.40)
lin sat
QD QD Q D (2.41) and
Qs = Qch QD (2.42) Tlin sat
where Q Gfs is the gate charge component between y = 0 to y = LAL, QGfS is the gate charge component in the saturation region from y = LAL to y = L, AL is the modulated channel length in strong inversion [Suh95b], s = 4effVDs/2VsatL, z = u  (IDsW/2Vsat)Cof(1 + a')VDS, and u = Qcf(0)/(Cof(1 + (x')VDS).
The charge formalism for the FD model [Cha97] can be updated accordingly.
20
Boundary of Strong Inversion (VTs)
Since we do not have an explicit relation between Wgf and the lower limit of stronginversion, VsfS [Tsi82], the modified VTS accounting for polysilicon depletion could be approximated by one iteration. To start the calculation, we first define an ideal VTS ( f(VGfs)) with the original Vsfs; then we solve for ygf from (2.7) with values of VGfs and Vsf replaced by VTS and VsfS, respectively. The second iteration of VTS is done by adding this y/gf to VTS. However, the iterative solution may be inefficient. Polysilicon depletion is typically more important in the stronginversion region due to high surface field, but it could be still negligible around the lower limit of strong inversion. In addition, the simulations suggest that the IV and CV characteristics with the new VTS do not show any significant differences from those with the original VTS; VTS changes by 5%, resulting in 1% change in IDS when VGfS = VTS, and no change in IDS in deep strong inversion. Therefore, the original VTS definition without iteration is still applicable.
To ensure the continuity between moderate and stronginversion, the solutions of the model calculated at VTS for spline interpolation have to be updated with our analysis for polysilicon depletion as well, though we know the depletion effect could be still small around VTS.
2.2.2 Model Implementation and Discussion
This physical model has been implemented in UFSOI [Fos98b] without any additional parameter since NGATE ( Np) is already a parameter. All the model upgrades, including current and charge models, are done in strong inversion and at the upper limit of moderate inversion, since the polysilicondepletion effect is
21
negligible in weak inversion. The polysilicon depletion exhibits its importance when the oxide thickness is scaled due to higher field and limited polysilicon doping (5x1019) [Sch93]. Therefore, the key parameters affecting polysilicon depletion are NGATE and TOXF ( tof); the information about gate doping and oxide thickness is important for parameter evaluation.
As shown in Fig. 2.2, we apply the model upgrade to an NFD/SOI technology with W/L = 20 im/0.35 gm, tof = 7 nm, and assumed Np = lx1019 cm3, and then compare the new solution with previous simulations without the polysilicondepletion model. Though this technology has been calibrated to SOISPICE/ver 4.4 [Fos97a] without the model upgrade, we use the same model card to verify and check its effects. As shown in Fig. 2.2, we see the DC current and gate capacitance degradations, respectively, which can be varied by different gate dopings as well.
With this model implemented in UFSOI, we can simulate the physical polysilicondepletion effect without having to estimate the electrical oxide thickness, which has been usually done. In contrast to polysilicon depletion, the polysilicon gate may be accumulated instead, if the type of front gate is the same as body (TPG = 1). As a result, the frontgate potential drop (gf) is pinned at ~ OV for accumulation, and the polysilicondepletion model is ignored automatically by forcing gf = 0 and a = a.
2.3 EnergyQuantization Effect
Another important physical mechanism in highly scaled devices is carrierenergy quantization in the inversion layer. The quantummechanical (QM) effect is
22
10.0 * I I
w/XlVgf VGfs= 3 V 8.0 W/O gf
6.0 VGfs 2 V
2.0
10 W/fs 1gV 0.0 I I , I
0.0 1.0 2.0 3.0
VDS (V)
30 I ' I s i I ' VDS = 0.1 V,
o20
L.
10  ' w/ Vgf
wo___W/o gf
0 .0 . I . I . 1 . 1
2.0 1.0 0.0 1.0 2.0 3.0 VGfS (V)
Figure 2.2 Simulated device characteristics of an NFD/SOI nMOSFET.
(a) IDS VGfS characteristics, (b) CGf VGfS characteristics.
23
mainly due to the high electric field at the Si/SiO2 interface, which results from highly doped channel and extremely thin gate oxide (tof). In the very high transversefield channel region (inversion layer), the continuum energy band analysis for free electrons (or holes) becomes invalid, since the electrons are confined to a potential well and the motion of electrons perpendicular to the interface is quantized. Then the 3D electrons can be treated as a 2D gas system along the channel region. As a result, the classically defined energy level, EC or Ev for free electrons or holes, will not agree with the lowest split energy subband from the quantum nature of the 2D electron gas. In such case, the quantization effect associated with the confinement of the minority carriers in the inversion layer can be treated as effective bandgap widening [Dor94] semiclassically. Furthermore, the distribution of mobile carriers from the solution of density of states is altered, i.e., the peak density is not right on the surface, and it is lower than that of the classical solution.
The effect should be treated with quantum mechanics for rigorous analyses. As the bandgap is virtually expanded, the intrinsic carrier density (ni) tends to decrease at the same temperature, and hence the threshold voltage increases. Again, this is mainly because the lowest quantized subband energy is higher/lower than EC/ Ev, and the total density of states in a quantized (2D) system is less than that in a classical (3D) one.
Many QM models like selfconsistent simulation [Ohk90], firstprinciple full band formalism [Jal97], simpler 3subband model [Har98a], and effective bandgap widening for electrons [Dor94] (revisited for holes [Har97]) have been published and developed in conventional numerical device simulators. However, for compact
24
device modeling, solving the Schr6dinger wave function is not preferable, since the efficiency is one of the most important concerns for circuit simulators. We hence utilize the physical model presented by van Dort, et al. [Dor94] as our main reference; this model was intended for numerical device simulators, but the physical nature of UFSOI enables its use here as well. In van Dort's model, the QM effect is done by introducing an induced bandgap widening, as discussed earlier, and the corresponding ni is recalculated. Based on this same approach, UFSOI model formalisms are modified where ni is involved.
In UFSOI models, we define three regions, strong, moderate, and weak inversion, with two boundaries, VTS (between strong and moderate inversion) and VTW (between moderate and weak inversion), according to the criteria of [Tsi82]. The moderateinversion regime is defined by cubicspline interpolation between the two boundaries. While accounting for the QM effect for circuit simulation, the classical MOSFET models, assuming that surface potential is pinned in strong inversion, become inaccurate and must be upgraded. Therefore, the surface potential involving ni to define VTS must be changed, and then other associated models are implicitly upgraded as well. Since the impact of quantization effects can be important somewhat even near the threshold voltage [Har98a], to efficiently model the energy quantization without losing its physical and realistic meaning, it is accounted for not only in strong inversion, but also in weak inversion, which then implicitly influences the moderateinversion solution. Thus, the weakinversion channel current
2
predominated by diffusion, which depends on oc ni , must be updated. However the
25
effect of altered VTW due to energy quantization is weak based on simulations, so we only redefine VTS and skip the similar numerical iteration for VTW.
As the QM effect in the accumulation layer is inconsequential for most of typical circuit operations, it can be less important than weak and strong inversions in such region. Besides, the bulk carriers that are not confined in bound states have a significant contribution to the total accumulation charge, i.e., a large portion of the accumulation carriers have to be considered as classical particles [Har98a]. Accurately modeling of the potential well in an accumulation layer thus needs to partition the entire carrier population into the quantum and classical domains according to the total energy of carriers [Shi97]. However, the carrier partitioning involves numerical analyses, and seems impractical for compact model application. While considering the implementation of this effect in a regional compact model, we can ignore or simplify some unnecessary calculations where the quantization effect is not or less significant; this is one of the advantages of regional modeling. Therefore, for UFSOI, the QM effect (involving majority carriers) is ignored in the accumulation region.
We discuss how we incorporate the newly developed QM model in the UFSOI models, and how we derive its formalism for implementation in SOISPICE [Fos98b] (now in a TypeI interface glued to Spice3). We also present AC and DC simulations accounting for QM effects to check validity of the model, including DC IDSVGfS and IDSVDS as well as frontgate quasistatic CV simulations. Finally, the simulations of a 9stage CMOS inverter ring oscillator show the QM effects on circuit performance, and check the capability of model prediction comprehensively.
26
2.3.1 Model Development
This quantization model is implemented in both FD and NFD models; the original models related to this topic should be revisited and upgraded. First, we begin the model development with the discussion of van Dort's model [Dor94], where the QM effect is modeled by calculating the effective intrinsic carrier density (niQM) corresponding to the bandgap widening:
13n ( Es 23
AEg = Q ' E , xfo) (eV); (2.43)
niQM = ni exp AE (2.44)
1 1 2kBgT)
where AEg represents an effective bandgap widening, 3 (= 4.1 x 108 eV cm) is a constant determined by fitting measured threshold voltage shifts at high doping levels [Dor92], Exfo (V/cm) is the vertical surface electric field, and QM ( QM) is a new model parameter which can be set up as a flag (0 = OFF) or can be tuned to give a better fitting for different technologies. The main reason to add this new parameter is because that, for rigorous modeling, we need to accurately consider the variation of Esf(x) and ni(x) at each point inside the inversion layer, which is impractical for this model implementation. Though 13 was originally determined for electrons, i.e., for nMOS [Dor92], other published data show that it is very close to the extracted value for holes obtained by fitting the modelpredicted results to experimental and to selfconsistently simulated data as well [Har97], [Jal96]. Thus a unified model can be applied to both p and ntype MOSFETs. We demonstrate how
27
we incorporate this model formalism into NFD and FD models individually as follows.
NFD Model Formalism
Consider first the stronginversion model. The QM upgrade is developed for the NFD model by redefining niQM from (2.44) and EgQM (=Egonv+ AEg) from (2.43). Further, the previously defined boundary at the upper limit of moderate inversion (VTs), with the corresponding surface potential (VsfS), must be upgraded accordingly. However, the convergence and nonlinearity issues might be brought out in circuit simulation due to the newly defined biasdependent boundaries, which should be treated carefully when implementing this model. (We will discuss the details in the final part of this model formalism.)
In the NFD model, the stronginversion boundary was defined as [Suh95a]
VTS = VTSO + AVTS (2.45) where VTSO is evaluated at VDS = 0, and AVTs is introduced by a 2D draininduced effect (DICE). To calculate VTSO, we should know the surface potential, Vsfs, which is solved iteratively, subject to the criterion defined in [Tsi82]:
2 2 2qniQM V Exfo = Ex(2F) + sNBLexpV , (2.46) f[10NBLExfo
Vss = Vln EO 2 (Cof + Cb) (2.47) qnm2 b
28
where NBL is the channel doping, 24F = VTln(NBL/nQM), and Cb Es/tb; VT = kaT/q is the thermal voltage. (The factor 10 in (2.47) has been modified to 6 to make the transconductance smoother in moderate inversion in UFSOI/Ver. 4.41 due to spline interpolation.) Note that the new njQM in (2.46) and (2.47) is a function of gate bias, and must be updated accordingly through iteration, which we will discuss later. Equation (2.46) was derived from the integration of Poisson's equation,
2 B niQM2NL 'Vj(s
d 2 sfqN + exp , (2.48) dx2 [ BL (!IT
over the predominant inversion layer, with niQM assumed to be independent of x.
Now, to properly incorporate nijQM into this YsfS evaluation, we first need to obtain niQM by solving (2.43) and (2.44) with given Exfo defined as
f
Eox(VGfs  V FBVsfS) (2.49)
Exfo= Es tof (2.49)
Note that the frontgate depletion potential (xygf) is ignored in (2.49) because it is relatively smaller than Vsfs, and also Wgf is calculated after VsfS is defined in the model routine. In order to obtain Vsfs, a few iterations (usually about 5) are required through (2.43), (2.44), (2.46), (2.47), and (2.49), and then VTS can be defined with the final solution of VsfS [Suh95a]. However, as indicated in (2.49), such VTS can vary with gate bias, i.e., VTS increases as VGfS increases, and it is not stable and adequate. Therefore, we need a true and VGfSindependent VTS as a fixed boundary to ensure the continuity over moderate and stronginversion regions.
29
The actual VTS (=f(VTs)) must be defined first before we can determine the region of MOSFET operation, and this boundary can only solved via iteration. For the first iteration, VGfs and xVsfs in (2.49) are replaced with initial guesses for VTS and Vsfs, respectively. Then, a new Vsfs is obtained by solving (2.43), (2.44), (2.46), (2.47), and (2.49), and hence a new VTS can be defined based on VsfS. Finally, the VGFSindependent VTS is found with four iterations. (The fixed number of iteration can also help reduce numerical noise.) The same approach is done for the FD model.
For strong inversion (VGfs > VTS), VsfS must be updated via same iteration based on a given VGfS for (2.49). (Again, the number of iteration is fixed at four.) Therefore, Vsfs(VGfs), which accounts for the QM effect in the entire stronginversion region, results in the corrections of current and charge solutions implicitly and automatically. No any other additional calculations or empirical fitting is necessary, which reflects one of the main advantages of a physical model over an empirical one.
Regarding weak inversion, since the effect of altered VTW due to energy quantization is weak based on our simulations (i.e., VTw(VGfs) is approximately the original VTW), we ignore the similar numerical iteration for VTW to preserve the previous model without losing the efficiency of simulation. Though the quantummechanical model is ignored for VTW calculation, the weakinversion diffusion2
dominant current (oc ni ) still needs to be updated in order to predict a more accurate subthreshold slope based on the consistent strong and weakinversion models. However, no complicate iteration, as shown previously for strong inversion, is needed; we simply calculate niQM from (2.43), (2.44), and (2.49) with an analytical
30
Vsf [Suh95a]. Substituting niQM into ni of the weakinversion model [Suh95a] yields a new solution for channel current. The simulation time is not lengthened as the weakinversion current is calculated analytically without iteration.
For VTW < VGfS < VTS, the solutions at the boundaries are also updated according to weak or stronginversion modeling, and hence the moderateinversion solutions are implicitly influenced via spline interpolation.
FD Model Formalism
To account for the QM effect in the FD model, we again apply the aforementioned theory for the NFD model in a similar manner; (2.43) and (2.44) are still the main bases here. The regional modeling approach involving two boundaries is adopted as well.
As demonstrated for the NFD model, the basic derivation can be similarly applied to the FD model [Yeh95] with the same criterion for defining the stronginversion boundary [Tsi82]:
2 2qNAVt[sf exp(sf2B (2.50) xfo = Es LVT + exp V (2.50)
t20VT(1 + a.)Cof)
Wss = 2B + 2VTln T + a)C (2.51) rQr
with
B = VTln A (2.52)
31
and
2 QM2
d 2Vst q ni Q2 Vst
7x12sf sNA + NA exp(VT)]
2 NlA N
dx2 sL A Vj
qNA1 + Ysf  24B,
 1I + exp Vsf B (2.53)
where (2.50), (2.51), and (2.53) are equivalent to (2.46), (2.47), and (2.48), Qr = 2qsEV, a = CbrbCob/(rfCof(Cb + rbCob)) with rf = 1 + qNsf/Cof and rb = 1 + qNsb/Cob, Nsf and Nsb are the front and backgate surfacestate densities, and NA is the film doping density. Again, we apply Gauss's law in one dimension to express the frontsurface transverse field including surfacestate density as
EXfO C s(1 + qNsf/Cof)  (VGfS  VFBf) (2.54)
Exfo =of
Es
Then ~VsfS can be found by solving (2.43), (2.44), (2.50), (2.51), and (2.54) iteratively. However, as discussed earlier, Vsfs(VGfs) gives an unstable VTS. Instead, we define a true and VGfSindependent VTS (=f(VTs)) with the same approach for the NFD model. The regional upgrades incorporated in the NFD model are applied here as well.
For strong inversion (VGfs > VTS), VsfS is solved iteratively with a given VGfs in (2.54). After VsfS is obtained, the current and charge solutions are automatically updated. For weak inversion, the current is assumed to be predominantly diffusion and calculated through charge integration. Note that this model has been recently upgraded to avoid the discontinuity due to the determination
32
of a minimum potential between front and back gates [Cho98]. The weakinversion
2
current of this model is proportional to ni and can be updated analogously as our previous derivation for the NFD model. Based on the upgrades for weak and strong inversions, the moderateinversion solutions are implicitly influenced via spline interpolation.
With these upgrades accounting for the quantization effect in NFD and FD models, the corrected charge and current solutions can be explicitly shown from device and circuit simulations. In addition, other device characteristics related to VsfS are also modified implicitly such as BJT current [Kri96a], effective gate capacitance, and mobility degradation [Vee88a].
Charge Modeling
While we simply use the updated 'VsfS(VGfS) to account for the QM effect in charge modeling without any extra upgrade, the displacement of inversion charge distribution, i.e., centroid, is not included explicitly due to the fundamental model assumption of charge sheet. However, van Dort's model [Dor94] used here has implicitly accounted for the increase of the average distance to the interface compared to the classical solution. Therefore, we are still able to effectively model the integrated charge density based on Gauss's law, which validates the calculations for capacitances as well.
2.3.2 Discussion
Since we only use the representative surface field without integrating the whole inversion layer due to the fundamental model assumption, the QM effect on
33
the characteristics of SOI MOSFETs could have been overestimated. Therefore the calibration of the QM upgrade is important. Furthermore, it should be calibrated consistently to the numerical device simulation as well as experimental data to assure reliable simulation.
The calibration of the parameter QM is based on CV simulations with different channel dopings from 1017 to 1018 cm3 and oxide thickness of 4 and 14nm without polysilicongate depletion (assumed metallike) to estimate the threshold voltage shift (AVT) due to the quantization effect. Also, to ensure no floatingbodyinduced errors during this process, we used an ideal bodytied structure for calibration. Referring to published data [Jal97], QM is optimally evaluated as 0.45 and 0.42 for ntype and ptype channels, respectively, which should be representative for the physical model. We will use both of these reasonable numbers for QM simulations in the following applications.
This model is then applied to a 0.35 .m NFD/SOI technology with tox = 7 nm technology for demonstration, as shown in Fig. 2.3 including both AC and DC simulations. We can clearly see the degradations of current drivability and gate capacitance, and the threshold voltage is raised as well. The QM effects shown here could be more significant as the gate oxide continues to shrink.
The frontgate CV characteristics are essential for verification of QM modeling. Note that the very low capacitance in the accumulation region (shown in both NFD and FD SOI devices) is due to the nature of the floating body in SOI MOSFETs. Physically, the floating body is capacitively coupled to the gate, but the hole charge in the body cannot respond at the high frequency; hence the source/drain
34
100 ,
w/QM. VDS= 2 V w/o QM  105 VDS= 0.1 V
CO
1010 ,
SW/L = 20 pm/0.35 Rm
1015 , 2
1.0 0.0 1.0 2.0 VGfS (V)
(a)
40 , w/QM. w/o QMO 3030
20
VDS= 0.1 V 10 ' '
2.0 1.0 0.0 1.0 2.0 3.0 VGfs (V)
(b)
Figure 2.3 Predicted characteristics of an NFD/SOI nMOSFET.
(a) IDS VGfS characteristics, (b) CGf VGfS characteristics (f = 1 MHz).
35
junction capacitance becomes important in this region. Also, the gate capacitances is lowered in strong inversion where the QM effect is modeled and plays an important role as the gate bias and surface field are increased. This decreased capacitance has been implicitly modeled as
CGf dQGf d[WLCox(VGfS 'ms  sf)]2.55) Gf dVGfs dVGfs
where > 0 with QM; it was 0 with the assumption of a pinned surface
dVGfs
potential. This physical effect consequently implies an equivalent gate oxide (> tof). However, empirically fitting the electrical oxide without accounting for the QM effect in the model has no physical meaning and can lead to erroneous calibration.
Another physical effect on carrier mobility can be predicted by this model as well. In UFSOI models, the fielddependent mobility is modeled as in (2.13). With accounting for the QM effect, the calculated inversionlayer charge density is less than that of the classical model, so the electric field (Ex) decreases and the mobility increases as shown in Fig. 2.4, which agrees with the selfconsistent simulation [Ohk90]. Although the carrier mobility is higher, the channel current does not increase accordingly because of the decreased inversion charge. The QM effects presented here could be more significant as oxide thickness continues to scale.
2.4 Verification and Circuit Performance
In order to verify the models of polysilicon depletion and energy quantization, an actual calibration to a real technology is demonstrated. A 0.14gm NFD/SOI technology with tof = 2.5 nm is used for this purpose. Figure 2.5(a) shows
36
350.0 QM
35,, Classical
E
S300.0  L 0.35 pm
tof = 7 nm
VDS =0.1 V
250.0I I
1.0 1.5 2.0 2.5 3.0 VGfS (V)
Figure 2.4 Predicted inversionlayer electron mobilities versus gate bias.
Mobility comparison of QM and classical models.
37
150.0
120.0 VDS 00 V
V90.0
. 60.0
30.0
0.0 *  Model w/ QM and 'gf .... Model w/o QM and 9Vgf
30.0 Measured data
2.0 1.0 0.0 1.0 2.0 3.0 VGfS (V)
Figure 2.5 CV characteristics of an NFD/SOI nMOSFET (f = 1 MHz).
Floatingbody CGfVGfS characteristics (100 um x 100 um).
38
its AC floatingbody CV calibration and the counterpart of old simulation as well. Significant capacitance degradation is predicted for this scaled technology.
With regard to circuit application, it is worthwhile to investigate the effects predicted by the new models on circuit performance. We simulate an unloaded 9stage CMOS inverter ring oscillator (L = 0.35 gm) with different gate dopings, and repeat the simulation without the QM upgrade for comparison. As shown in Fig. 2.6, QM and polysilicondepletion (lower gate doping) effects tend to slow down the circuit speed, whereas the circuit consumes less power due to degraded drive current predicted by powerdelay product.
2.5 Conclusion
Polysilicongate depletion and carrierenergy quantization were incorporated in the UFSOI models. From the model applications to circuits, we observed that they can be beneficial due to lowered effective gate capacitance, and also can be undesirable due to degraded current drivability. To scale device properly, some related factors like gate oxide thickness, channel doping, as well as applied bias must be considered and investigated in depth based on the limitations due to polysilicon depletion and QM effects. We can further apply the upgraded UFSOI models to gain physical insight into the behavior of scaled SOI MOSFETs in integrated circuits, and to facilitate optimal circuit and device design with better prediction of device characteristics and circuit performance. Additionally, an important model refinement that ensures a smooth transition from the linear to the saturation regions of MOSFET operation was developed (in Appendix A).
39
50.0
w/QM
45.0 w/o QM .1) U,
CO,
o 40.0()
E
> 40.0
35.0 ...
1018 1019 1020 1021 1022 FrontGate Doping (cm"3)
(a)
110.0
w/QM
100.0w/oQM 90.0
.
0
80.0
VDS = 2.5 V
70 .0 . .. ..
1018 1019 1020 1021 1022 FrontGate Doping (cm3)
(b)
Figure 2.6 Predicted circuit performance of NFD SOI CMOS.
UFSOIpredicted (a) delay time and (b) powerdelay product vs. gate doping for
a 9stage CMOS inverter ring oscillator.
CHAPTER 3
UFSOI MODEL PARAMETER EVALUATION: PROCESSBASED CALIBRATION METHODOLOGY
3.1 Introduction
The UFSOI FD [Yeh95] and NFD [Suh95a] MOSFET models are physical and processbased, meaning that their key parameters relate directly to device structure and physics. The parameter evaluation thus can be and should be done based on knowledge of the SOI technology [Kri96a]. A unique processbased calibration methodology, which reliably links the physical models to the measured device characteristics instead of fitting the model simulations to the experimental data, is introduced in this work. The methodology should include some tuning of particular parameters based on electrical measurements of devices having more than one channel length and width in specific bias regions. Also, it can be defined with good physical insight to be reliable and much simpler than conventional parameter extraction, or optimization via leastsquares fits to measured data. In fact, such a processbased methodology, in contrast to optimization of empirical parameters via curve fitting [FunOO], seems essential for reliable SOI model calibration because of complications due to device selfheating and dynamic floatingbody effects [Jen96]. More importantly, the UFSOI models then have some predictive capability.
This chapter extends and refines the parameterevaluation algorithm described in [Kri96a], yielding a straightforward calibration methodology for the
40
41
UFSOI models which requires minimal knowledge of device structure, measured DC currentvoltage characteristics of two floatingbody devices having long and short (target) channel lengths, and a measured gate capacitancevoltage characteristic. The systematic processbased methodology is amenable to implementation in software for automated parameter evaluation. (Its use in UTMOST [Si197] has been effected.) The methodology is demonstrated here via application to an AMD 0.35tm NFD/SOI CMOS technology and to an MIT Lincoln Lab 0.25gm FD/SOI CMOS technology. The demonstration are based on UFSOI/Ver. 4.5 [Fos98b], but the defined methodology is easily extended to later UFSOI revisions.
3.2 Parameter Evaluation for NFD/SOI MOSFETs
Unlike bulkSi MOSFET models, SOI device models must be properly calibrated to account for both DC and dynamic floatingbody effects. The chargebased UFSOI NFD model formalism is BiMOS [Kri96a], accounting for parasitic bipolar features, intrinsically coupled to the MOS analysis, which underlie these effects. The processbased nature of the model enables a quick preliminary parameter estimation based on device structure and physics, which facilitates the subsequent systematic and efficient tuning of a few key parameters via specific device measurements. The Ver. 4.5 model parameters, along with their descriptions and typical values for current stateoftheart NFD/SOI technologies, are listed in Table
3.1 [Fos98b].
42
Table 3.1 UFSOI4.5 NFD MOSFET Model Parameters
Name Description Units Default Typical Values NQFF Front oxide fixed charge cm2 0.0 _1010 (normalized)
NQFB Back oxide fixed charge cm2 0.0 ~1011 (normalized)
NQFSW Effective sidewall fixed charge cm2 0.0 _+1012
(0 for no narrowwidth effect)
TOXF Frontgate oxide thickness m 10.x109 (38)x109 TOXB Backgate oxide thickness m 500.x109 (80400)x109 NSUB Substrate doping density cm3 1.0x1015 10151017 NGATE Polygate doping density cm3 0.0 10191020
(0 for no polygate depletion)
NBL Low body doping density cm3 5.0x1016 10171018 NBH High body doping density cm3 5.0x1017 1x1018 NDS Source/drain doping density cm3 5.0x1019 1019_102O TF Silicon (SOI) film thickness m 200.x109 (100200)x109
TB Effective (depleted) film thickness m 100.x109 (2550)x109
QM Energy Quantization Parameter 0.0 00.5
(0 for no quantization)
THALO Halo thickness (0 for no halo) m 0.0 (50100)x109 NHALO Halo doping density cm3 0.0 1x1018 LRSCE Characteristic length for reverse m 0.0 0.1x106
shortchannel effect (0 for no RSCE)
UO Lowfield mobility cm2*Vl*s1 700 (n) 200700 (nMOS) 250 (p) 70400 (pMOS)
THETA Mobility degradation coefficient cm*V1 1.0x106 (0.13)x106 VSAT Carrier saturated drift velocity cms1 1.0x 107 (0.51)x107
43
Table 3.1 UFSOI4.5 NFD MOSFET Model Parameters
ALPHA Impactionization coefficient cm1 0.0 2.45x106
(0 for no impact ionization)
BETA Impactionization exponential factor V*cm1 0.0 1.92x106 LLDD LDD region length (0 for no LDD) m 0.0 (0.050.2)x106 NLDS LDD/LDS doping density cm3 5.0x1019 lx1019
(>1x1019: D/S extensions)
BGIDL GIDL exponential factor V*m1 0.0 (48)x109 (0 for no GIDL)
NTR Effective trap density for cm3 0.0 10141015 trapassisted junction tunneling
(0 for no tunneling)
JRO Bodysource/drain junction A*m1 1.0x1010 1011109 recombination current coefficient
M Junction nonideality factor  2.0 12 CGFDO Gatedrain overlap capacitance F*m1 0.0 1x1010 CGFSO Gatesource overlap capacitance F*m1 0.0 1x1010 CGFBO Gatebody overlap capacitance F*m1 0.0 0.0
RD Specific drain parasitic resistance .*m 0.0 (1001000)x106 RS Specific source parasitic resistance .*m 0.0 (1001000)x106 RHOB Body sheet resistance O/sq. 0.0 30x103
DL Channellength reduction m 0.0 (0.050.15)x106 DW Channelwidth reduction m 0.0 (0.10.5)x106 LDIFF Effective diffusion length in m 0.1x106 (0.10.5)x106 source/drain
SEFF Effective recombination velocity in cm*s1 1.0x105 (0.55)x105 source/drain
FNK Flicker noise coefficient F*A 0.0 01025 (0 for no flicker noise)
FNA Flicker noise exponent  1.0 0.52.0
44
Table 3.1 UFSOI4.5 NFD MOSFET Model Parameters Flag Parameters
Name Description Units Default Typical Value BJT Parasitic bipolar flag (0: off; 1: on)  1 1 TPG Type of gate poly (+1: opposite to body;  +1 +1
1: same as body)
TPS Type of substrate (+1: opposite to body;  1 1
1: same as body)
SELFT Selfheating flag  0 0
(0: no self heating; 1: approximate
model; 2: full model)
Optional Parameters
Name Description Units Default Typical Values TAUO Carrier lifetime in lightly doped s Calculated 107_ 105 region
VFBF Frontgate flatband voltage V Calculated 1 (nMOS) +1 (pMOS)
VFBB Backgate flatband voltage V Calculated WKF Frontgate work function difference V Calculated  VFBF WKB Backgate work function difference V Calculated BFACT VDSaveraging factor for mobility  0.3 0.10.5 degradation
FVBJT BJT current directional partitioning  0.0 01
factor (0 for lateral 1D flow)
RHOSD Source/drain sheet resistance f/sq. 0.0 50
3.2.1 Preliminary Model Card
We begin the calibration by defining a preliminary set of model parameters estimated directly from each device structure (TOXF, TOXB, NSUB, NGATE, TPG,
45
TPS, NDS, TF, TB, THALO and NHALO (if applicable), NBL, NBH, LLDD and NLDS (if applicable), CGFDO, CGFSO, CGFBO, RD, RS, RB, RHOB, DL, DW) and the pertinent device physics (UO, THETA, VSAT, ALPHA, BETA, TAUO, JRO, M, LDIFF, SEFF, BGIDL, QM, NTR, LRSCE). This estimation can be done quickly, and our experience has shown that the preliminary model card typically is a good representation of the technology, even when the device structure is not precisely known. For the AMD technology, with dualpolysilicon gates (n+ poly for nMOS and p+ poly for pMOS), the parameters given in Table 3.2 are defined unequivocally for
Table 3.2 Model Parameters Evaluated Directly from Technology Information
Parameter Value
TOXF 7.0 nm
TOXB 0.36 gm
TF 0.12 gm
TPG +1
TPS 1, +1
W (drawn) 20 gm
L (drawn) 1.0 and 0.35 gm
both nMOS and pMOS devices. TOXF is the physical thickness of the gateoxide; polysilicongate depletion and energy quantization are options in UFSOI4.5. If these options are used, then we initially estimate NGATE to be 5.0x1019 and QM to be 0.4, where the latter is based on a general calibration of the UFSOI model to numerically simulated devices with channel doping in the range 1016  1018 cm3 [Jal97]. TOXF should be set to the measured electrical value of the oxide thickness,
46
which is typically 1020% thicker than the physical value, if the polysilicondepletion and energyquantization options are not used.
Several of the parameters listed in Table 3.1 are either unimportant or inapplicable for this technology. For example, NQFF is typically low enough that it is not significant in a scaled technology, and NQFB is generally not critical in NFD devices. NQFSW can be set to 0 generally, unless narrowwidth effects on threshold voltage are important, in which case measured data from a narrowW device is needed for evaluation. We can also assume for the nMOS device that the impactionization parameters, ALPHA and BETA, retain their physical values of 2.45 x 106 and 1.92 x 106, respectively, as confirmed experimentally for electrons [Slo87], [Kri96b]. For the pMOS device, ALPHA and BETA are less important since the impactionization rate for holes is much smaller than that for electrons; they can be adequately estimated in the tuning process as we describe. Thus, there are only 17 key parameters that have to be tuned beyond their initial estimated values: NBL, TF, TB, UO, THETA, VSAT, BGIDL, TAUO, JRO, M, RD, RS, DL, LRSCE, NGATE, QM and NTR. The overlap capacitances, CGFDO and CGFSO, can be estimated by calculation (EoxDL/2TOXF), but should be tuned based on a measured gate CV characteristic because of possible nonlinearities and fringing effects. The parameter tuning is done systematically as detailed in the following sections.
3.2.2 LongL Calibration
First, we calibrate to longL devices to tune TB, NBL, NGATE, QM, NGATE, UO, THETA, JRO, M, and BGIDL. These evaluations are simplified since DL, LRSCE, VSAT, RD and RS are not significant for long L. In addition, self
47
heating is less significant for long L and hence can be easily avoided. Since UFSOI4.5 accounts for carrier thermal generation throughout the channel region, the parameter evaluation for a longL device, for which such generation can be significant, can be done easily and reliably. We choose 1.0 gm devices for the longL calibration.
Stage 1
Evaluated Parameter Measurement Data Device
TB IDS vs. VGfS @ low VDS (100 mV) LongL
With the preliminary model parameter set, we can tune TB for subthreshold slope using the measured IDSVGfs characteristic at low VDS (no kink) as illustrated in Fig. 3.1. The subthreshold slope is given approximately as [Suh95a]
S=60 1 + (3.1) Cox
where Cd = Es/TB is the depletion capacitance and Cox = Eox/TOXF is the gate capacitance. We thereby obtain TB = 58 nm for both nMOS and pMOS, which is consistent with the technology.
Stage 2
Evaluated Parameters Measurement Data Device
NBL (NBH) IDS vs. VGfs @ low VDS (100 mV) LongL
As illustrated in Fig. 3.2, NBL can be tuned to fit the subthreshold current from the IDSVGfS characteristic at low VDS (no kink). The subthreshold current
48
100
VDS= 2 V 105  o VDS = 0.1 V
O
~O
1010  oa ' 0 "
S0 Slope Fit
O
1015
2.0 0.0 2.0 4.0 VGfS (V)
(a)
100
1 0 5V D S =  2 V 
105 / DS 0.1 V
O
O
1010 0 /
0Slope Fit
0
1015
2.0 0.0 2.0 4.0
VGfS (V)
(b)
Figure 3.1 IDS VGfS characteristics of 1.0 gm NFD/SOI devices (Stage 1).
(a) nMOS. (b) pMOS.
49
100
VDS= 2 V 105  VDS = 0.1 V
1010
O
Current Fit
0
Cm 0
1015
2.0 0.0 2.0 4.0 VGfS (V)
(a)
100o
VDS 2 2 105  VD 01 V V S =  2 V VS e  0
1 1010
111 1
Current Fit
00a
1015
2.0 0.0 2.0 4.0
VGfS (V)
(b)
Figure 3.2 IDS VGfS characteristics of 1.0 gm NFD/SOI devices (Stage 2).
(a) nMOS. (b) pMOS.
50
varies inversely with NBL. We obtain NBL = 3.1 x 1017 cm3 for nMOS and 2.5 x 1017 cm3 for pMOS, which are also consistent with the technology. The technology does not have steep retrograded channels; we therefore assume, based on typical channel doping profiles, that NBH is about a factor of two higher than NBL. As we discuss later, the value of NBH can be updated based on the gate CV characteristic. Stage 3 (optional with TOXF set to electrical gateoxide thickness)
Evaluated Parameters Measurement Data Device
QM, NGATE CGfS vs. VGfS @ low VDS (0 V) LongL
(CGFSO, CGFDO) (ShortL MOSC)
Calibration as well as verification via CV characteristics are essential for reliable transient as well as AC simulations. We exemplify the CV calibration here to lay the foundation for tuning the polydepletion and quantization parameters of the UFSOI model, in addition to evaluating the gatesource and gatedrain overlap capacitances, CGFSO and CGFDO (from a shortL gate MOSC).
From the frontgate (source/drain) CV characteristic of the floatingbody device, QM and NGATE can be tuned based on the estimation of capacitance lowering in strong inversion, respectively, as depicted in Fig. 3.3. Physically, both polygate depletion and energy quantization affect current and capacitances predominantly in strong inversion. Energy quantization can be important even near threshold, and hence tends to lower the subthreshold current and increase the threshold voltage. Consequently, the calibration of subthreshold current demonstrated in Stage 2 might need refinement, depending on the significance of the quantization. In this example, the gate CV characteristics are derived from AC
51
5.0 .
4.0 Measurement cSimulation
3.0
2.0
.0I I I
1.04.0 3.0 2.0 1.0 0.0 1.0 2.0 3.0 4.0
VGfS (V)
(a)
5.0
4.0 Measurement cSimulation
3.0
bO 0
U
2.0
1.04.0 3.0 2.0 1.0 0.0 1.0 2.0 3.0 4.0
VGfS (V)
(b)
Figure 3.3 CV characteristics of floatingbody NFD/SOI MOSFETs (Stage 3).
(a) nMOS. (b) pMOS. (L/W = 0.5 p.m/2000 gm, f = 1 MHz, VDS = 0 V)
52
simulations, and the measured data are taken at 1 MHz from floatingbody nMOSFETs and pMOSFETs with VDS = 0. The gate width and length of the devices are 2000 gm and 0.5 im, respectively. Note that the latter is not long, and hence CGFSO and CGFDO can be tuned as well. However, to avoid the effects of overlap capacitances and DL, longL devices are preferable. In this example, NGATE and QM are tuned as 2.0 x 1019 cm3 and 0.45, respectively, for nMOS, and 7.5 x 1019 cm3 and 0.4, respectively, for pMOS. Note that the nMOS characteristic implies a flatband voltage that is slightly different from that of the devices used to calibrate the model.
In addition, other parameters can be either evaluated or verified via the CV characteristic in the accumulation region. As indicated in Fig. 3.3, floatingbody effects are apparent and must be accounted for. The floating body is capacitively coupled to the gate, but the hole charge in the body cannot respond at the high frequency; hence the source/drain junction capacitance becomes important in the accumulation region. Examination of the measured and simulated CV characteristics in different gatebias regions gives good insight on the floatingbody effects and lends support to the UFSOI basic charge/capacitance modeling and calibration. In the accumulation region, the relatively low capacitance, in contrast to that of a tiedbody device, reflects the predominant source and drain junction capacitances, as well as overlap capacitances. In this region then, NBH and TF can be refined, and the overlap capacitances can be tuned. We find that CGFDO and CGFSO are effective values, larger than eoxDL/2TOXF, because of the fringing components not accounted for explicitly in the UFSOI model. NBH and TF influence
53
the low capacitance in the accumulation region, but not as much as CGFDO and CGFSO.
Stage 4
Evaluated Parameters Measurement Data Device JRO, TAUO, M, BGIDL, NTR IDS vs. VGfS @ high VDS (2.0 V) LongL ALPHA, BETA (pMOS)
If GIDL is not prevalent, JRO and M can be evaluated from the draininduced shift in current (without kink) and the slope (with kink), respectively, of the IDSVGfS characteristic at high VDS, as demonstrated in Fig. 3.4. The shift in current is due in part to DIBL, modeled internally, but mainly it is due to the floatingbody effect, i.e., the induced VBS > 0 caused by injection (e.g., generation) of majority carriers into the body. The DC VBS is defined by the balance of the carrier generation from the bodydrain junction and recombination from the bodysource junction as well as the quasineutral source. The recombination current is modeled as [Kri96a]
2
VBS qni (VBTS
IR(VBS) = WJROexp B + WTFN eff)SEFFexp Y) (3.2)
where the first term tends to be predominant in this context. Thus, if the generation current (due to impact ionization here) is characterized well, M and JRO can be evaluated from the highVDS subthreshold IDSVGfS characteristic. However, the generation current can have more than one component, and hence the general evaluation will usually involve other parameters associated with it as well. In fact, GIDL can influence the offstate leakage current near the kink. We hence include
54
100
VDS = 2 V Kink Fit 105 _ VDS='V Current Fit 1010  0
101 I.. 21 4 VGfS (V)
(a)
100
VD = 2V Kink Fit 1ï¿½5 VDS= 0.1V
4,, Current Fit
1010
1 5,0, 2.0 ' 4.
VGfS (V)
(b)
Figure 3.4 IDS VGfs characteristics of 1.0 gm NFD/SOI devices (Stage 4).
(a) nMOS. (b) pMOS.
55
BGIDL evaluation in this stage, knowing that it is independent of L.
For scaled devices, the thermal generation should correlate with the thermal recombination. Hence, the value of TAUO should be loosely correlated with JRO in accord with basic pnjunction recombination/generation properties as follows: qniTFyd
JRO =_ qnTFy (3.3) Tr
and
2TAUO.4)
r g 1 + NBH/No
where Yd, typically 50 nm, is a junction space chargeregion width, and No is 5x1016 cm3. With (3.3) and (3.4), TAUO calculated from the default JRO (1.0x1010 A*m1) is on the order of 1 ts, which is physically consistent with recent technologies. In UFSOI4.5, TAUO is defaulted to 0 and used as a flag for internal calculation of the generation current, based only on JRO as indicated by (3.3) and (3.4). However, for longL devices, the generation current from the channel/body region will require tuning of TAUO, which is done as described herein.
We suggest that BGIDL first be tuned to fit GIDL current of the IDSVGfS characteristic at high VDS and VGfS < 0 (where GIDL is most significant) for nMOS, as demonstrated in Fig. 3.4(a), using an estimated DL from the technology. Then we tune JRO to calibrate the prekink region of the highVDS curve, and tune M to set the kink effect, as well as finetune the prekink region in conjunction with JRO. This calibration is illustrated in Fig. 3.4(a). Once JRO is obtained, TAUO (for the longL
56
device) can be first estimated using (3.3) and (3.4), and then tuned as described in Stage 6. In the VGfS < 0 region of the highVDS IDSVGfS characteristic, we can tune the junctiontunneling parameter, NTR, in conjunction with BGIDL to match the leakage current if it is underpredicted by accounting for the thermal generation. A few iterations on the values of these parameters may be necessary; BGIDL should be iterated too if GIDL seems important near the subthreshold kink. (Because a weighting factor is used in the characterization of the source/drain junction recombination/generation currents to ensure symmetry, varying TAUO can cause a slight variation in the longL model characteristic in the prekink region.)
As was mentioned previously, the impactionization rate for holes is much smaller than that for electrons. Since there is no clear indication of the values of ALPHA and BETA for holes in the literature, they should also be tuned for pMOS, along with JRO, from the kink shown by the data in Fig. 3.4(b). If we increase BETA, the onset voltage of the kink will be pushed out. (ALPHA and BETA can also be checked later to match the kinks of IDS VDS characteristics, as plotted in Fig. 3.6.) We obtain JRO = 1.0 x 1010 A/m, TAUO = 1.0 x 106 s, M = 1.5, BGIDL = 4.5 x 109 V*m1, and NTR = 4.5 x 1014 cm3 for nMOS (with ALPHA and BETA given previously), and JRO = 1.0 x 1010 A/m, TAUO = 1.0 x 106 s, M = 1.5, BGIDL = 4.6 x 109 V*m1, ALPHA = 2.45 x 106 cm1, BETA = 3.0 x 106 V/cm, and NTR = 9.0 x 1014 cm3 for pMOS.
Note in Fig. 3.4 that the longL devices, especially nMOS, show anomalous leakage current at high VDS near VGfS = 0. This current, which in fact varies substantially in different devices from the technology, can influence the drain
57
induced floatingbody effect on offstate current as well as subthreshold kink as indicated in Fig. 3.4(a). Furthermore, it can undermine the accuracy of calibrated parameters. Therefore, BGIDL and NTR for nMOS were evaluated using the shortL device IDSVGfS characteristic, as shown in Fig. 3.7(a). Stage 5
Evaluated Parameters Measurement Data Device
UO, THETA IDS vs. VGfS @ low VDS (100 mV) LongL
From the IDSVGfS characteristic at low VDS, UO and THETA can be tuned directly, as indicated in Fig. 3.5, since RD and RS are not significant here for long L. The low (longitudinal)field mobility is dependent on the transverse field (Ex) in the channel, which is modeled by the average field as UO
geff =' U (3.5) eff 1 + THETAEx(y) (3.5)
In this calibration, some iterations are required, but the optimization is not complex. (An alternative methodology that can be used is based on gmVGfs at low VDS, as shown in Fig. 3.12(a) and Fig. 3.13(a).) The calibration should be precise here, even though the shortL tuning will alter the parameter values somewhat. We obtain UO = 800 cm2/V/s and THETA = 2.3 x 106 cm/V for nMOS, and UO = 250 cm2/V/s and THETA = 1.9 x 106 cm/V for pMOS. Stage 6
Evaluated Parameter Measurement Data Device
TAUO, NTR IDS vs. VDS @ low VGfS (1 V) LongL
58
8.0e03
6.0e03 o
0
VDS = 2 V
4.0e03  Calibrated
2.0e03 VDS= 0.1 V
0.0e+00
2.0 0.0 2.0 4.0 VGfS (V)
(a)
3.0e03 I
VDS= 2 V
2.0e03
Calibrated
1.0e03
VDS =0.1 V
0.Oe+00
2.0 0.0 2.0 4.0
VGfs (V)
(b)
Figure 3.5 IDS VGfS characteristics of 1.0 gm NFD/SOI devices (Stage 5).
(a) nMOS. (b) pMOS.
59
Since TAUO has been initially estimated in Stage 4, we only need to finetune the value to negate possible inaccuracies of approximations, e.g., 'tr = g. The finetuning serves as a verification of the JROdefined TAUO as well.
Large changes in TAUO should not be allowed here; such changes would reflect another current component, e.g., due to junction trapassisted tunneling, which can be used to tune the effective trap density, NTR. Fig. 3.6 shows the refining of TAUO from IDS VDS characteristics at VDS  VDS(sat) (no kink) and low VGfS where IDS(sat) is controlled by pinchoff and where it reflects clearly the threshold lowering due to the thermal generation currentdriven floatingbody effect. If we see the current increasing with VDS in this same region, then we will have to tune NTR. The effects of carrier velocity saturation (VSAT) at higher VGfs, which will be discussed later, should be avoided here. The values of TAUO and NTR evaluated in Stage 4 are still valid here.
3.2.3 ShortL Calibration
The parameter set obtained from the longL device tuning is now used to initiate the tuning from the shortL (target) device. The shortL calibration is similar to that described for long L, but with some additional parameters. In fact, if longL data is not available, the calibration could be done with the shortL data only, albeit with a bit more complexity. Selfheating is usually more prevalent in shortL device data, so it must be cautiously avoided for reliable parameter evaluation. (The UFSOI models do have a selfheating option [Kri96a], [Wor98], which uses two additional parameters (RTH and CTH) that could be tuned. However, a reliable calibration can
60
8.0e03 ,
VGfS= 4 V
6.0e03 _ Calibrated .......... o __ o
6.O03 Calibrated 000000000000000000000
0
4.0e03 
oa VGfS= 23 V
O 000000000 .00000000
2.0e03  . . 0
VGfS= 1 V O.Oe+00 I I
0.0 1.0 2.0 3.0 4.0 VDS (V)
(a)
4.0e03 I I I
3.0e03  )
.0.002.0o 3. 4.. .0
OO
O
O
!. VGfS= 3 V
2.0e03  o00000.0.
VDs (V)
(b)
(a) nMOS. (b) pMOS.
C
fo .. V~fS=2 V
1.0e03  .", 0. ....=. 0000
VGfS = 1 V
0.Oe00 0
0.0 1.0 2.0 3.0 4.0
VDS (V
(b)
Figure 3.6 IDS VDS characteristics of 1.0 gm NFD/SOI devices (Stage 6).
(a) nMOS. (b) pMOS.
61
be done without considering selfheating.) The remaining parameters to be evaluated from the shortL device data are DL, RD, RS, VSAT, and LRSCE. Stage 7
Evaluated Parameters Measurement Data Device
DL, LRSCE IDS vs. VGfs @ low VDS (100 mV) ShortL and high VDS (2.0 V)
If the technology shows significant reverse shortchannel effect (RSCE), then the effective channel doping in the shortL device will be higher than NBL obtained from the longL device, and the general validity of the calibration would be invalidated. Therefore, LRSCE needs to be tuned here to retain the model scalability.
Using the model parameter set we have at this point, we find that the shortL model gives the same subthreshold slope as seen in the lowVDS IDS VGfS data, which implies good TB. Since, we do not see any RSCE in this example, we hence can easily obtain DL by fitting the shortchannel effect (DIBL) from the IDS VGfS characteristics as shown in Fig. 3.7. In other cases, however, the shortL data may show a higher threshold voltage, implying that RSCE must be accounted for. In order to evaluate DL and LRSCE independently, we tune (refine) LRSCE to fit the subthreshold current, which strongly depends upon doping, and we tune (refine) DL to match DIBL from the IDS VGfS characteristics as shown in Fig. 3.7. (Note that when LRSCE > 0, NHALO or NBH can affect the effective channel doping through a physical link modeled in UFSOI4.5.) We obtain DL = 0.07 pm for nMOS and 0.08 pm for pMOS, which are consistent with the technology, and LRSCE = 0.0 pm for both nMOS and pMOS. Once DL is tuned, we may skip further NBL, JRO, M,
62
100
VDS 2 V 105 _DS= 01V
1010
Calibrated
o1015  co
2.0 0.0 2.0 4.0 VGfS (V)
(a)
100
VDS = 2 V 105 VDS=0.1V
1010
Calibrated
1015 I I
2.0 0.0 2.0 4.0
VGfs (V)
(b)
Figure 3.7 IDS VGfs characteristics of 0.35 pm NFD/SOI devices (Stage 7).
(a) nMOS. (b) pMOS.
63
ALPHA, and BETA tuning if no discrepancies are seen in the characteristics; otherwise some finetuning is needed. Stage 8
Evaluated Parameters Measurement Data Device
RD, RS IDS vs. VGfS @ low VDS (100 mV) ShortL
As can be seen in Fig. 3.8. RD and RS are evaluated from the linear region of the IDS VGfS characteristics where the equivalent ON resistance is given approximately by
VDS RS+RD LDL
RON IDS  W WCof(VGfS  VT)eff(UO, THETA) (3.6)
Since RS = RD due to device symmetry and UO and THETA have been tuned previously, this evaluation is straightforward without iteration. (Note: Since RS/RD could have been of some importance in the longL device, UO and THETA can be finetuned here to sustain the agreement with the longL data.) Hence RS/RD is tuned as 400 x 106 Qm for nMOS and 1100 x 106 Km for pMOS. Stage 9
Evaluated Parameter Measurement Data Device
VSAT IDS vs. VDS @ low power region ShortL
Figure 3.9 shows that we can tune VSAT from the IDSVDS characteristic at high VGfS with VDS ~ VDS(sat), where the saturation is governed by velocity
64
1.5e02 , I , 1
1.0e02
VDS = 0.1 V
0.0e+00 <'
2.0 0.0 2.0 4.0
VGfS (V)
(a)
8.0e03 ,
0
6.0e03
00
VDS = 2 Vo
O
' 4.0e03 
 Calibrated (linear)
2.0e03
VDS = 0.1 V O.Oe+0 o
0.0e+00 acc=2.0 0.0 2.0 4.0 VGfS (V)
(b)
Figure 3.8 IDS VGfs characteristics of 0.35 ptm NFD/SOI devices (Stage 8).
(a) nMOS. (b) pMOS.
8.0e03 I
6.0e03
VDS 2 V 0
0
'~4.0e03
Calibrated (linear)
2 . 0 e  0 3 V D
VDS =0O.IV
0.Oe+00 ccoo
2.0 0.0 2.0 4.0
VGfS (V
(b)
Figure 3.8 IDS VGfS characteristics of 0.35 g~m NFD/SOI devices (Stage 8).
(a) nMOS. (b) pMOS.
65
1.5e02 , I VGfS= 4 V
.Higher Power VGfs = 3 V
\ o oo o o ooooo o o o o
1.0e02
5 . e 0 S . \ . .... . . . . .
O.Oe+0 ' i I , 1::]
0.0 1.0 2.0 3.0 4.0
VDS (V)GfS= 2 V
(a)
oo
5.0e03 o..
V =1
rd0.
0.Oe+00
0.0 1.0 2.0 3.0 4.0 VDS (V)
(a)
SHigher Power VGfS = 4 e V
8.0e03 
\ oo ooo
6.0e03  \ oooo VGfS
\ oc o ooooooo O ï¿½
4.0e03  \f 2 ooV
2.0e030.0 1.0 2.0 3.0 4_0
VDS (V)
(b)
Figure 3.9 IDS VDS characteristics of 0.35 gm NFD/SOI devices (Stage 9).
(a) nMOS. (b) pMOS.
66
saturation and not pinchoff of the channel charge (Qc). In this case, the saturation current is expressed as [Suh95a]
ICH(sat)= WVSATQc(L). (3.7) As indicated in the figure, device selfheating can and must be avoided while tuning VSAT. If VGfS is set too high, then the power dissipation will be too high, and the selfheating will distort the data as evident in Fig. 3.9; if VGfs is set too low, then (3.7) will not apply. VSAT is tuned to 0.8 x 107 cm/s for nMOS and 0.9 x 107 cm/s for pMOS.
3.2.4 Verification (SelfHeating)
After the key parameters have been tuned, both short and longL devices should be simulated with the single set of model parameters for verification. Further, the selfheating option [Fos98b] can be turned on for a more comprehensive comparison, after having evaluated the thermalresistance parameter, RTH, via tuning to the shortL device in the highpower regions. In general, if the self heating
(AT) exceeds 20 'C, where [Wor98]
AT = RTH P (3.8) and
P = VDSIDS VD'S'(ICH + IBJT) + (ICH + IBJT) 2(Rs + RD + RLDS + RLDD), (3.9)
then selfheating effects should be taken into account. For this technology, with L = 0.35 jim, RTH is derived from highP data as 4.5 K/W for nMOS and 2.5 K/W for
67
pMOS. With L = 1.0 pm, RTH is derived as 2.2 K/W for nMOS, and ignored for pMOS due to less power consumption. Although the selfheating effects can prevail in the longL device too, they tend to be less significant since RTH varies inversely with device size.
For a more complete calibration, some parameters may be tuned based on additional measured data. For example, following [Kri96a] the bipolarrelated source/drain parameters SEFF and LDIFF can be evaluated from transient IBJT(t) data. If such transient data is not available, SEFF can also be estimated from the kink in the IDSVDS characteristics at lower VGfS where it influences recombination and hence the kink current level. Finally, by matching the breakdown voltage in the IDSVDS characteristics, FVBJT and NBH can be tuned.
The characteristics reflecting the final calibration of the NFD model to the AMD SOI CMOS technology are plotted in Figs. 3.10 and 3.11; the selfheating option was used in the L = 0.35 pm device simulations. Overall the model predictions match the measured data well, except for the anomalous leakage currents at VGfS < 0 in Fig. 3.10(d) which, as mentioned previously, could vary substantially in different devices from the technology. In Fig. 3.10(f), there are discrepancies in the IDSVDS characteristics in and around the kink regions; the data show less abrupt kinks. The anomalous leakage currents mentioned above, which could become predominant in charging the floating body, could also underlie these discrepancies. They might also be due to nearFD conditions induced by the bias. Such conditions are suggested by the loss of the kink with increasing VGfS shown by the characteristics in Fig. 3.10(c) for the shortL device, in which source/drain charge
68
100 10ï¿½
V DS= 2 V V D . VV DS = 2 c
105 MDS=.] V 105
1010  1010
COc CCC
10.15 1015 I"0 D I'COD Oï¿½ 1
2.0 0 2.0 4.0 2.0 0.0 2.0 4.0 (a) IDS VGfS characteristics; L = 0.35 gm (d) IDS  VGfS characteristics; L = 1.0 gm
1.5e2 , 8.0e3 '
6.0e3
1.0e2 0 0O
V~~=V 0 0 VDS= 2 V e3 VDS= 2 V o0o
4.0 0
5.0e3
2.0e3
S VDS = 0.1 V VDS = 0.1 V.
o 40
I 0.0
0.2.0 4.0 2.0 4.0
(b) IDS VGfS characteristics; L = 0.35 gm (d) IDS  VGfS characteristics; L = 1.0 jm
1.5e2 8.0e3
VGfs= 4 V  VGfS = 4 V
00000 00000000000
.......0 . .o 6.0e3 .. .
1.0e2 00. VGfS=3Vf 33V
Soo ooo oooo o 000000000
.0e3 ... 000000
5~~.0e3  a o',oo 2 VGfS= 2 V 2.e3o0
5.0e3  ooooooo..
2.0e3 oo oo o
Vpfs= 1 I oV
0. V0fs= 1 V
08.0 1.0 2.0 3.0 4.0 0. 1.0 2.0 3.0 4.0 (c) IDS VDs characteristics; L = 0.35 gm (f) IDS VDS characteristics; L = 1.0 im
Figure 3.10 Calibrated I(A)  V(V) characteristics of NFD/SOI nMOS devices.
69
100 i , 100 __ '
VDS = 2 V VDS= 2 V
o105  VDS=O.V  105 VDs = 0
1010  1010
1015  0 I , 1015 . , I
2.0 002.0 4.0 2.0 0.0 2.0 4.0 (a) IDS VGfS characteristics; L = 0.35 gm (d) IDS VGfs characteristics; L= 1.0 gm
8.0e3 I , 3.0e3 ,
6.0e3 O
2.0e3
VDS= 2 V VDS= 2 V
4.0e3
1.0e3
2.0e3 
VDs = 0.1 V VDS= 0.1 V 00 00.1
2.0 4.0 2.0 4.0
(b) IDS VGfs characteristics; L = 0.35 gm (e) IDS VGfS characteristics; L = 1.0 jm
1.0e2 , i ' I 4.0e3 I VGfS = 4 V
8.0e3 VGfS= 4 V oooo0o.o 3.0e3 
000o
6.0e3 o VGfS = 3 V  VGfs = 3 V
oo o . 2.0e3 ...o..o.oo ooo o o
4ooV V G fs .=.2 .V
02.0e3e3
4.Oe3 0000 V~f 2 V
o , , c ; o o o o o o 0 1 . e, , , oo o .,
0.e o .O
VGfs= 1 V VGfS= 1 V
000 00 000 000 0000
0..0 1.0 2.0 3.0 4.0 0.0 1.0 2.0 3.0 4.0
(c) IDS VDS characteristics; L = 0.35 Im (f) IDS VDs characteristics; L = 1.0 gm
Figure 3.11 Calibrated I(A)  V(V) characteristics of NFD/SOI nMOS devices.
70
sharing could be supporting full depletion of the body. Figures 3.12 and 3.13 show corresponding simulated and measured conductances; the agreement is very good, although the predicted kinks in gm are too sharp as in Figs. 3.10 and 3.11. The nMOS and pMOS model parameters derived for the target channel length are listed in Table 3.3. Unlisted parameters are either inapplicable or unimportant, and are set with their default values. With the parameters evaluated and tuned as described herein, the UFSOI NFD model should reliably predict not only the DC but also the transient and AC characteristics of devices and circuits from the AMD 0.35pm SOI CMOS technology.
To exemplify the predictive capability of the model with this processbased methodology, we use a 151stage floatingbody NFD/SOI CMOS inverter ring oscillator for verification. The circuit was build on a 0.14 pm NFD/SOI CMOS technology. Following the methodology described in this chapter, the model parameters were systematically evaluated and tuned. Without further parameter evaluation for transient measurement, we can still predict the inverter delay over a wide range of supply voltage, as shown in Fig. 3.14. In contrast, empirical parameter extraction would not be useful for predictive simulation, especially for SOI due to dynamic floatingbody effects.
3.3 Parameter Evaluation for FD/SOI MOSFETs
The UFSOI model parameter evaluation for FD MOSFETs also exploits the processbased nature of the model. The methodology is similar to that described for the UFSOI NFD model. The bipolarrelated and impactionization parameters are
71
4.0e03 ,
3.0e03
VDS = 2 V o
lO
2.0e03
4 1.0e03
VDS = 0.1 V
0.0e+00
1.0e03
2.0 0.0 2.0 4.0 VGfS (V)
(a)
1.5e02 I
1.0e02 0
VGfS = 1, 2, 3, 4 V (bottom to top)
5.0e03
00
0.Oe+00
5.0e03 I I . I .
0.0 1.0 2.0 3.0 4.0 VDS (V)
(b)
Figure 3.12 Calibrated conductances of NFD/SOI nMOS device.
(a) Transconductance; L = 0.35 gm.
(b) Output conductance; L = 0.35 um.
72
3.0e03
2.0e03 VDS = 2 V
1.0e03
SVDS = 0.1V
0.0e+00
1.0e03 I
2.0 0.0 2.0 4.0
VGfs (V)
(a)
8.0e03 I
6.0e03 VGfS = 1, 2, 3, 4 V (bottom to top)
0
O
2 .0 e0 3 o 000
0.0e+00
2.0e03 , I , I , I ,
0.0 1.0 2.0 3.0 4.0
VDS (V)
(b)
Figure 3.13 Calibrated conductances of NFD/SOI pMOS device.
(a) Transconductance; L = 0.35 gm.
(b) Output conductance; L = 0.35 tm.
73
Table 3.3 Evaluated Key Parameters for AMD's 0.35Rjm NFD/SOI CMOS Devices
Parameters nMOS pMOS
TOXF 7.0 nm 7.0 nm TOXB 0.36 lm 0.36 jtm
TB 0.058 gm 0.058 lm TF 0.12 Lm 0.12 jim
NBL 3.1x1017 cm3 2.5x1017 cm3 NBH 5.0x1017 cm3 4.0x1017 cm3 UO 800. cm2/V/s 250. cm2/V/s
THETA 2.3x106 cm/V 1.9x106 cm/V VSAT 0.8x107 cm/s 0.9x107 cm/s
TPG 1 1 TPS 1 1
ALPHA 2.45x106 cm1 2.45x106 cm1 BETA 1.92x106 V/cm 3.0x106 V/cm
RD 400.x106 2m 1100.x106 O2m RS 400.x106 jm 1100.x106 gm
TAUO 1.0x106 s 1.0x107 s
JRO 1.0x1010 A/m 1.0x1010 A/m
M 1.5 1.5
BGIDL 4.5x109 V/m 4.6x109 V/m NTR 4.5x1014 cm3 9.0x1014 cm3
DL 0.07 Lm 0.08 jim
LRSCE 0.0 jim 0.0 jm
SEFF 9.0x105 cm/s 7.0x105 cm/s NGATE 2.0x1019 cm3 7.5x1019 cm3
QM 0.45 0.4
CGFSO 0.245x109 F/m 0.245x109 F/m CGFDO 0.245x109 F/m 0.245x109 F/m
74
50
A Measured Data (FB/SOI) n  UFSOI (after 0.5 gs, steady state)
40
CD, a/)
30
C,)
20 Lgate=O.14 gm
Wn/Wp=2.52 pgm/5.04 gm
10* *
0.8 1.0 1.2 1.4 1.6 1.8 VDD (V)
Figure 3.14 Predicted and measured delay of a NFD/SOI CMOS inverter RO.
The simulation was done without further parameter evaluation for transient
measurement.
75
evaluated identically. Since the FD device is somewhat immune to floatingbody effects, parameters associated with them are less important. However, the FD channelcurrent formalism in weak inversion is more complex, accounting for 2D fringing fields in the buried oxide (BOX) emanating from the source/drain junctions [Yeh95], [Yeh96]; two additional parameters for this effect must be tuned. The Ver. 4.5 model parameters, along with their descriptions and typical values, are listed inTable 3.4 [Fos98b].
Table 3.4 UFSOI4.5 FD MOSFET Model Parameters
Name Description Units Default Typical Values NQFF Front oxide fixed charge (normalized) cm2 0.0 ~ 1010 NQFB Back oxide fixed charge (normalized) cm2 0.0  1011 NQFSW Effective sidewall fixed charge cm2 0.0 +1012 (normalized)
(0 for no narrowwidth effect)
NSF Front surface state density cm2 0.0 _ 1010 NSB Back surface state density cm2 0.0 1011 TOXF Frontgate oxide thickness m 10.x109 (38)x109 TOXB Backgate oxide thickness m 500.x109 (80400)x109 NSUB Substrate doping density cm3 1.0x1015 10151017 NGATE Polygate doping density cm3 0.0 10191020
(0 for no polygate depletion)
NBODY Film (body) doping density cm3 5.0x1016 10171018 NDS Source/drain doping density cm3 5.0x1019 1019_1020 TB Film (body) thickness m 100.x109 (30100)x109
QM Energy Quantization Parameter  0.0 00.5
(0 for no quantization)
76
Table 3.4 UFSOI4.5 FD MOSFET Model Parameters
UO Lowfield mobility cm2*V1*s1 700 (n) 200700 (nMOS) 250 (p) 70400(pMOS)
THETA Mobility degradation coefficient cmV1 1.0x106 (0.13)x106 VSAT Carrier saturated drift velocity cm*s1 1.0x107 (0.51)x107 ALPHA Impactionization coefficient cm1 0.0 2.45x106 BETA Impactionization exponential factor V*cm1 0.0 1.92x106 LLDD LDD region length (0 for no LDD) m 0.0 (0.050.2)x106 NLDS LDD/LDS doping density cm3 5.0x1019 1x1019 (>1x1019: D/S extensions)
GAMMA BOX fringing field weighting factor 0.3 0.31.0 KAPPA BOX fringing field weighting factor  0.5 0.51.0 BGIDL GIDL exponential factor V*m1 0.0 (48)x 109 (0 for no GIDL)
JRO Bodysource/drain junction A*m1 1 .0x1010 1011109
recombination current coefficient
M Junction nonideality factor  2.0 1.02.0 CGFDO Gatedrain overlap capacitance F*m1 0.0 1x1010 CGFSO Gatesource overlap capacitance F*m1 0.0 1x1010 CGFBO Gatebody overlap capacitance F*m1 0.0 0.0
RD Specific drain parasitic resistance .m 0.0 (1001000)x106 RS Specific source parasitic resistance KIm 0.0 (1001000)x106 RHOB Body sheet resistance ,/sq. 0.0 30x103 DL Channellength reduction m 0.0 (0.050.15)x106
DW Channelwidth reduction m 0.0 (0.10.5)x106 LDIFF Effective diffusion length in m 0.1x106 (0.10.5)x106 source/drain
77
Table 3.4 UFSOI4.5 FD MOSFET Model Parameters
SEFF Effective recombination velocity in cm*s1 105 (0.55)x105 source/drain
FNK Flicker noise coefficient F.A 0.0 0_1025 (0 for no flicker noise)
FNA Flicker noise exponent  1.0 0.52 Flag Parameters
Name Description Units Default Typical Value BJT Parasitic bipolar flag (0: off; 1: on)  1 1 TPG Type of gate poly (+1: opposite to body;  +1 +1
1: same as body)
TPS Type of substrate (+1: opposite to body;  1 1
1: same as body)
SELFT Selfheating flag  0 0 (0: no self heating;
1: approximate model; 2: full model)
Optional Model Parameters
Name Description Units Default Typical Values TAUO Carrier lifetime in lightly doped region s Calculated 107_105 VFBF Frontgate flatband voltage V Calculated 1 (nMOS) 1 (pMOS)
VFBB Backgate flatband voltage V Calculated WKF Frontgate work function difference V Calculated  VFBF WKB Backgate work function difference V Calculated BFACT VDSaveraging factor for  0.3 0.10.5
mobility degradation
FVBJT BJT current directional partitioning  0.0 01
factor (0 for lateral 1D flow)
RHOSD Source/drain sheet resistance Q/sq. 0.0 50
78
3.3.1 Preliminary Model Card
We begin the calibration by defining a preliminary model card for each device with the parameters estimated directly from the device structure (TOXF, TOXB, NSUB, NGATE, TPG, TPS, NDS, TB, NBODY, LLDD and NLDS (if applicable), CGFDO, CGFSO, CGFBO, RD, RS, RB, DL, DW) and the pertinent device physics (NSF, NSB, GAMMA, KAPPA, UO, THETA, VSAT, ALPHA, BETA, TAUO, JRO, M, LDIFF, SEFF, BGIDL, QM, LRSCE). To account for the 2D fringing fields in the BOX, GAMMA and KAPPA must be properly evaluated. The initial values for GAMMA and KAPPA, based on TOXB, were extracted from 2D MEDICI simulations [Yeh96]; they are given in Table 3.5. Since the UFSOI model
Table 3.5 BOX FringingField Parameters (Extracted from MEDICI) TOXB (nm) GAMMA KAPPA
<50 1.0 1.0
100 0.7 0.9
200 0.5 0.7
350 0.3 0.5
assumes that the FD device is strongly fully depleted (except in accumulation), the parameters associated with floatingbody effects, such as ALPHA, BETA, TAUO, JRO, M, LDIFF, and SEFF, are less important for most FD/SOI MOSFETs. Nonetheless, the transient bipolar effect in the FD/SOI MOSFET can be important in certain applications, for which the associated parameters must be tuned reliably; these parameters, JRO, M, SEFF, and LDIFF, can be evaluated from transient leakagecurrent measurements [Kri96a]. As for the NFD model, several of the
79
parameters listed in Table 3.4 are either unimportant or inapplicable for this technology. For example, NQFF is typically low enough that it is not significant in a scaled technology, and NQFB is generally not critical relative to the charge defined by NSB. NQFSW can be set to 0 generally, unless narrowwidth effects on threshold voltage are important, in which case measured data from a narrowW device is needed for evaluation. We suggest that the impactionization parameters, ALPHA and BETA, be set to their default (physical) values of 2.45x106 /cm and 1.92x106 V/ cm, respectively, for nMOS [Slo87], [Kri96b], and adequately adjusted for pMOS. Also, SEFF could be tuned roughly to the BJTinduced drainsource breakdown voltage for highvoltage applications.
For the MIT Lincoln Lab technology, with dualpolysilicon gates (n+ poly for nMOS and p+ poly for pMOS), the parameters listed in Table 3.6 are evaluated
Table 3.6 Model Parameters Evaluated Directly from Technology Information Parameter Value
TOXF 8.0 nm
TOXB 185 gm
TB 50 nm
TPG +1
TPS 1, +1
W (drawn) 7 grm
L (drawn) 0.5 and 0.25 gm
directly, for both nMOS and pMOS devices. Now, only 14 key parameters, which are initially estimated as noted, need to be tuned: NSB, NBODY, TB (if necessary), QM,
80
NGATE, UO, THETA, VSAT, GAMMA, KAPPA, BGIDL, RD, RS, and DL. Since the measured data we acquired do not include CV characteristics, we do not tune QM and NGATE for this example. Actually, since the gateoxide thickness of this technology is not very thin, these parameters are not really significant. In other cases, however, if the polysilicon gatedepletion and energyquantization options are needed, we initially estimate NGATE to be 5.0x1019 and QM to be 0.4, where the latter is based on a general calibration of the UFSOI model to numerically simulated devices with channel doping in the range 1016  1018 cm3 [Jal97]. The methodology for tuning NGATE and QM discussed in the NFD calibration is applicable here as well. If the noted options are not used, then TOXF is set to the measured electrical value of the oxide thickness, which is typically 1020% thicker than the physical value. The overlap capacitances, CGFDO and CGFSO, can be calculated
aoxDL
( 2TOXF , which neglects possible fringing) or can be tuned from a measured gate CV characteristic. The other parameters are either unimportant or inapplicable for this technology. The tuning is done systematically as detailed in the following sections.
3.3.2 LongL Calibration
Unlike the parameter evaluation for the NFD model, the FD model parameters can not always be tuned for long and short L sequentially because of the BOX fringingfield effect. If the subthreshold slope (S) increases abnormally as channel length is decreased or VDS is increased, then the fringing fields are probably significant, and GAMMA and KAPPA must be tuned beyond the values in Table 3.5. In spite of this effect however, other parameters such as DL, RD, RS, and VSAT can
81
still be evaluated according to their importance in shortL devices only. In this section, we will focus on the evaluations of NSB, GAMMA, TB, NBODY, UO, and THETA. Due to the limited availability of measured data, we choose the 0.5 p~m device to demonstrate the longL calibration, even though it is not long enough to be absolutely void of shortchannel effects.
Stage 1
Evaluated Parameters Measurement Data Device NSB, GAMMA, TB, IDS vs. VGfs @ low VDS (50 mV) Long  L
NBODY
In weak inversion, the diffusion of carriers throughout the "fully depleted" film body is accounted for in the UFSOI model by integrating the carrier charge across the entire film; "front" and "back" channels are thereby defined, and front and back channellength modulation is accounted for as well [Yeh96]. The increased charge at the back surface will also reduce the frontchannel threshold voltage through the chargecoupling effect [Lim84]. Therefore both front and backgate surface charge can influence the subthreshold characteristic. However, since the frontgate oxide thickness is typically much thinner than backgate oxide thickness, NSF tuning is usually not needed. We first check the subthreshold slope of the IDSVGfS characteristic at low VDS for the longL device to determine the importance of NSB. If S is near ideal (60mV), then NSB must be low, and hence we can skip its evaluation. In this example, S is found to be 64.4 and 64.3 mV for the nMOS and pMOS devices, respectively (>60mV because of the fringing field in the BOX), and so we do not evaluate NSB initially. We next tune TB and NBODY (and perhaps
82
NSB) iteratively to fit the current and slope of the IDsVGfs characteristic at low VDS in weak inversion; GAMMA is initially estimated from Table 3.5. Results are illustrated in Fig. 3.15.
As part of the 2D BOX fringingfield modeling, an effective backgate bias is defined as [Yeh96]
TOXB2
VGbS(eff) VGbS + T 2 (KAPPAVDs + GAMMAEoL) (3.10)
where E0 ( ~P/y 1x = TB y=0 ) represents the source of the fringing field; VGbS(eff) reduces to VGbS for very long L and/or thin TOXB. As evident in (3.10) then, GAMMA and KAPPA can be evaluated with reference to their relative significance for different L's and VDS's; for example, KAPPA is more important for high VDS, which will be discussed later. Since TB not only affects the slope but also affects the current magnitude (i.e., threshold voltage), an iterative yet uncomplicated scheme should be used in this stage. We thereby confirm GAMMA = 0.5 (given previously) and TB = 50 nm (consistent with technology) for both nMOS and pMOS, and we get NBODY = 2.2 x 1017 cm3 and 2.0 x 1017 cm3 for nMOS and pMOS, respectively.
Note in Fig. 3.15(a) the significant discrepancy at high VDS for the nMOS device; a subthreshold kink is exhibited. We infer that it is mainly due to the device becoming NFD (when VBS > 0, which tends to shrink the channel depletion region in a MOSFET). This characteristic stresses the fact that in order to develop a good FD/SOI MOSFET with reliable (and predictable) characteristics without floating
83
100
VDS = 2 V 105 _ 0
0 a VDs = 0.05 V
lOOO
Calibrated 1015 , I ,
1.0 0.0 1.0 2.0 VGfS (V)
(a)
100
VDS= 2 V 105
VDs= 0.05 V
1010
Calibrated
0
1015 L
1.0 0.0 1.0 2.0
VGfS (V)
(b)
Figure 3.15 IDS VGfs characteristics of 0.5 gm FD/SOI devices (Stage 1).
(a) nMOS. (b) pMOS.
84
body effects, the body doping and film thickness must be carefully designed to ensure full depletion of the body over the entire range of anticipated bias.
An additional stage could be inserted here to evaluate BGIDL from the highVDS IDSVGfS subthreshold characteristic included in Fig. 3.15. The evaluation would follow from simply fitting the GIDL current, usually seen for VGfS < 0 for nMOS and VGfS > 0 for pMOS. However, the characteristics we have for the FD/SOI technology do not show much GIDL current, and hence BGIDL is not evaluated. Stage 2 (optional with TOXF set to electrical gateoxide thickness)
Evaluated Parameters Measurement Data Device
QM, NGATE CGfs vs. VGfS @ low VDS (~0 V) LongL
From the frontgate CV characteristic, QM and NGATE can be tuned based on the estimation of capacitance lowering in strong inversion, respectively, as depicted in Fig. 3.3 for the NFD model calibration. Physically both poly depletion and energy quantization have influences on capacitances and currents, especially in the stronginversion regime. Nonetheless energy quantization could be still important around threshold voltage, and hence can lower the subthreshold current and increase the threshold voltage. As a consequence, the calibration of subthreshold current demonstrated in Stage 1 might need refinement. In this example, CV data are not available, and further QM and NGATE are not important. When they are, refer to the more detailed discussion of CV calibration in Stage 3 of the NFD model calibration.
85
Stage 3
Evaluated Parameters Measurement Data Device
UO, THETA IDS vs. VGfS @ low VDS (50 mV) LongL
Similar to Stage 5 of the NFDmodel parameter tuning, UO and THETA can be tuned directly from the IDSVGfS characteristic at low VDS, as indicated in Fig. 3.16. However, this stage should be linked to the RD/RS evaluation in Stage 5, at least in this example, since the 0.5 pm device is not totally immune from RD/RS influence. For a longerL device, e.g., L = 1 pgm, UO and THETA could be tuned independent of RD/RS. In conjunction with Stage 5, we obtain UO = 700 cm2/V/s and THETA = 0.75 x 106 cm/V for nMOS, and UO = 200 cm2/V/s and THETA = 1.6 x 106 cm/V for pMOS.
3.3.3 ShortL Calibration
Now the tuning process continues with the shortL (target) device, beginning with the parameter set obtained from the longL device tuning. In fact, if longL device data are not available, the calibration could be done with only the shortL device data, albeit with a bit more complexity. As noted in the shortL calibration of the NFD model, selfheating is usually more prevalent in shortL device data, and must be carefully avoided to ensure the integrity of the parameter evaluation. (The UFSOI models do have a selfheating option [Fos98b], which uses two additional parameters (RTH and CTH) that could be tuned). The remaining parameters to be evaluated from the shortL device data are DL, KAPPA, RD, RS, and VSAT. We choose the target device with L = 0.25 gm for the shortL calibration.
86
2.5e03
2.0e03
VDS = 2 V o
0
0
1.5e03
00
0
1.0e03 
Calibrated 5.0e04 O.Oe+O0 000000 VDS 0.05 V
1.0 0.0 1.0 2.0 VGfS (V)
(a)
8.0e04
0
6.0e04 VDS = 2 Vo
0
0
4.0e04
Calibrated 2.0e04
VDS = 0.05
0.0e+00
1.0 0.0 1.0 2.0
VGfS (V)
(b)
Figure 3.16 IDS VGfs characteristics of 0.5 im FD/SOI devices (Stage 3).
(a) nMOS. (b) pMOS.
87
Stage 4
Evaluated Parameters Measurement Data Device
DL, KAPPA IDS vs. VGfS @ high (2 V) & low ShortL VDS (50 mV)
The channellength reduction DL can be evaluated (refined) from its influence on the shortchannel effects. For example, in the subthreshold region, the DIBL effect is worsened as DL increases. However, as described in (3.10), KAPPA tends to be predominant for high VDS and short L. So, to account for both the fringingfield and the shortL effects, we tune (refine) DL and KAPPA simultaneously by fitting the current and slope of subthreshold IDsVGfS characteristics at different values of VDS, as illustrated in Fig. 3.17. Unexpectedly, we find that KAPPA for the nMOS device needs to be increased significantly from the value in Table 3.6 to match the abnormally high subthreshold current at high VDS. Although the BOX fieldfringing could be the underlying reason for the high current, this result portends the possibility of punchthrough or, as was evident for the longL device, a draininduced transition to the NFD mode, which would result in a higher S (see (3.1)) as in Fig. 3.17(a). Nonetheless, we obtain DL = 0.06 gm and KAPPA = 1.0 for nMOS, and DL = 0.018 gm and KAPPA = 0.7 (given previously) for pMOS. Stage 5
Evaluated Parameters Measurement Data Device
RD, RS IDS vs. VGfs @ low VDS (50 mV) ShortL
88
100
VDS= 2 V
105  VDS = 0.05 V
1010
Calibrated
O
1015
1.0 0.0 1.0 2.0 VGfS (V)
(a)
100
VDS = 2 V 105
101
Calibrated 1015 II
1.0 0.0 1.0 2.0
VGfS (V)
(b)
Figure 3.17 IDS VGfs characteristics of 0.25 gm FD/SOI devices (Stage 4).
(a) nMOS. (b) pMOS.
89
Figure 3.18 shows that RD and RS can be evaluated from the linear region of the IDS VGfS characteristics. Since RS/RD could have been of some importance in the "longL" device, UO and THETA should be finetuned here to sustain the agreement with the longL data, unless the channel length is so long that RS/RD will not cause any noticeable effect. Assuming RS = RD due to device symmetry, we tune RS/RD to 200 x 106 Qm for nMOS and 900 x 106 gm for pMOS. Stage 6
Evaluated Parameter Measurement Data Device
VSAT IDS vs. VDS @ low power region ShortL
As shown in Fig. 3.19, we tune VSAT from the IDSVDS characteristics at high VGfS with VDS  VDS(sat), where the saturation is governed by velocity saturation and not pinchoff. Note that selfheating can and must be avoided; it is apparent in the nMOS device at higher VDS where the DC power dissipation is larger. We tune VSAT to be 0.65 x 107 cm/s for nMOS and 0.45 x 107 cm/s for pMOS.
3.3.4 Verification
Due to the thinner body of the FD/SOI MOSFET, which implies higher thermal resistance, the selfheating phenomenon, discussed in Section 3.2.4, may be more severe than in the NFD/SOI device. However, the characteristics showing the final calibration of the FD model to the MIT Lincoln Lab CMOS technology, plotted in Figs. 3.20 and 3.21, do not cover very highpower regions; only the measured nMOS characteristics for VDS and VGfS near 2 V reflect any selfheating. The FD model (without selfheating) calibration is very good, except where the nMOS
90
3.5e03
3.0e03 73.e03 VDS = 2 V 2
2.5e03  000
0
0
2.0e03 000
0
0
1.5e03  00
S1eCalibrated o0
1.0e03 
5.0e04  co VDs = 0.05 V
0.0e+00
1.0 0.0 1.0 2.0
VGfS (V)
(a)
1.5e03
0
0
VDS =2 V co
O
1.0e03 c
0
00
rd~ 0
0
5 eCalibrated o
0
0
0
5.0e04 
0 VDS= 0.05 V
0.0e+00
1.0 0.0 1.0 2.0
VGfS (V)
(b)
Figure 3.18 IDS VGfs characteristics of 0.25 gm FD/SOI devices (Stage 5).
(a) nMOS. (b) pMOS.
91
3.5e03 ,
Calibrated VGfS = 2 V
3.0e03 2.5e03  VGfS = 1.6 V
1 .0e03 /ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½
O00000000000
1.0e03
5 .0e04
VGfS = 1.2 V
1.5e03  00oo..c00ooo ooooooooooooooo
1.0e03  o0 VGfS = 0.8 V
5.0e04 00000000000000000000000000 a00000,00
0.0e+00 I
0.0 0.5 1.0 1.5 2.0 VDS (V)
(a)
1.5e03 I
Calibrated VGfS = 2 V
1.0e03 VGfS= 1.6 V14 VGfS = 1.2 V
5.0e04
..0 VGfS = 0.8 V a u VGfS = 0.4 V
0.0e+00
0.0 0.5 1.0 1.5 2.0
VDS (V)
(b)
Figure 3.19 IDS VDS characteristics of 0.25 gm FD/SOI devices (Stage 6).
(a) nMOS. (b) pMOS.
92
100 I 100
VDS = 2 V VDS = V
COO
10 0 0 0 VDS = 0.05 V  1 c VS=00
1010   1010 oo
C
1.0 0.0 1.0 2.0 1.0 0.0 1.0 2.0
(a) IDS VGfS characteristics; L = 0.25 pim (d) IDS  VGfS characteristics; L = 0.5 pm
4.0e03 I 2.5e03 I I
2.0e03
3.0e03
00
C
VDS = 2 V  1.seo03  VDS = 2V
2.0e03
101.0e03
1.0e03
VDS = 0.05 V 5.Oe04  VDS 0.05 V
0
o.08+00 0.0e+00 Loooo
1.0 0.0 1.0 2.0 1.0 0.0 1.0 2.0 (b) IDS VGfs characteristics; L = 0.25 pm (e) IDS VGfS characteristics; L = 0.5 pm
3.5e03 I 2.5e03 I
3.oeo3 VGfS =2 V VGfS = 2 V
.5e03 0oooooooooooooo 2.0e03
2.5e03 1.6 V
2.0e03 1.5e03 VGfS =
000 oooooo000oo00000000000000 VGfS = .20V V
0o0
5.0e044
5.0e04 0000..00000 00 0 0000V00000 00.4 0
..ooooocooooOOï¿½ï¿½ VfS = 0. V ~Su o
r;==,,0 .0. .... ,, 0=0oooooCooooo i n, 0 e Vf = 0.4 o V
0.5+0 0 0.Oe+00
0.00.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0
(c) IDS VDs characteristics; L = 0.25 p.m (f) IDS VDS characteristics; L = 0.5 pm
Figure 3.20 Calibrated I(A)  V(V) characteristics of FD/SOI nMOS devices.

182
VDD (V)
Figure 5.17 Modelpredicted inverter delay versus power supply.
Comparison of performance for asymmetricalgate DG and SG (back gate
grounded) CMOS circuits.
129
V
Q
Gbs = V'fb1 VSf + (1 + ^ Wsb p
'ob v ''ob' "~ob
Qb/2 + Qcb
(5.2)
where \)/sf and i/sb are the front and backsurface potentials, VbFB and VbFB are
flatband voltages, Qcf and Qcb are inversion charges, Qb = qNAtSi, and
Cb = Â£Si/tSi Fr an asymmetrical (generic) DG MOSFET with a usual front
channel at VGfS(= VGbS) = VTS, we can ignore Qcb, and model VTS by combining
(5.1) and (5.2) to get Qcf = Cof(VGfSVTS), with
V
TS
where r =
1 +r
cbcob
1 ,,.f ,b .
(V fb + rV fb) + v/ssf
3t,
of
Cof(Cob + Cb) tSi(eff) + 3tob
4 2 2
\/ssf = VTlog(10 NA/nÂ¡). The surface potential is assumed pinned at \/ssf, which
4
follows from n(0) = 10 NA to ensure the validity of the stronginversion formalism
(i.e., (5.13) for virtually all x), which is described later. In the expression for r,
tsi(eff)< lsi is used t0 account for the finite inversionlayer thickness:
esEsf Qcf
^Si(eff) = hi ~ linv = hi ~ ^0) WherC Esf ( ^ defmed by GauSSS laW 1S als0 a
function of VTS. Therefore, we need one iteration to obtain a sufficiently accurate
VTS; the initial VTS is solved from (5.3) with tSi(eff^ = tSi, and then it is updated
with a more accurate tSi(eff) based on the first solution. For a symmetrical DG, VTS
f Qb
will naturally merge to VTS = V fb + v/ssf , which can also be obtained from
2Cof
rj_+
r ^Qb
(5.3)
lcof
C0J 2
Si02
gate insulator
and
(5.1) and (5.2).
21
negligible in weak inversion. The polysilicon depletion exhibits its importance when
the oxide thickness is scaled due to higher field and limited polysilicon doping
(~5xl019) [Sch93]. Therefore, the key parameters affecting polysilicon depletion are
NGATE and TOXF (s tof); the information about gate doping and oxide thickness is
important for parameter evaluation.
As shown in Fig. 2.2, we apply the model upgrade to an NFD/SOI technology
with W/L = 20 pm/0.35 pm, tof = 7 nm, and assumed NP = lxlO19 cm'3, and then
compare the new solution with previous simulations without the polysilicon
depletion model. Though this technology has been calibrated to SOISPICE/ver 4.4
[Fos97a] without the model upgrade, we use the same model card to verify and check
its effects. As shown in Fig. 2.2, we see the DC current and gate capacitance
degradations, respectively, which can be varied by different gate dopings as well.
With this model implemented in UFSOI, we can simulate the physical
polysilicondepletion effect without having to estimate the electrical oxide thickness,
which has been usually done. In contrast to polysilicon depletion, the polysilicon
gate may be accumulated instead, if the type of front gate is the same as body (TPG
= 1). As a result, the frontgate potential drop (\/gf) is pinned at ~ 0V for
accumulation, and the polysilicondepletion model is ignored automatically by
forcing V/gf = 0 and a = a.
2.3 EnergyQuantization Effect
Another important physical mechanism in highly scaled devices is carrier
energy quantization in the inversion layer. The quantummechanical (QM) effect is
APPENDIX B
ASSESSMENT OF NOVEL BODYTIEDTOBODY SOI CMOS
While SOI is merging to the mainstream of CMOS technologies, problematic
floatingbody (FB) effects can be critical in some applications and also can increase
the complexity of device and circuit design. The bodytied NFD SOI MOSFET
provides a common solution for both DC and transient FB issues such as
subthreshold kink, premature breakdown, transient bipolar leakage [Kri96a], circuit
instability [Suh94b], [Lu97], and hysteresis [Ass96], [Hou98], [Pur98], [Suh94b].
Many schemes of body tie have been proposed over the decade [Hwa91], [Che96],
[Koh97], [Sle97]. In this appendix, a novel bodytiedtobody (BTB) SOI CMOS
inverter configuration is presented. A tie between the body of nMOS and the body of
pMOS is used, which allows the exchange of excessive body charges. With this
structure, the speed advantage of SOI is retained and even improved over FB SOI
circuits at low voltage. The fundamental characteristics of conventional body ties
will first be discussed in this section, and then a preliminary assessment of BTB SOI
CMOS is described.
B.l Body Tie Characterization
Ideally, the body tie can remove all of the possible FB effects. Nonetheless,
a real body tie with its associated parasitics may not work properly during transient
196
CHAPTER 4
DESIGN ISSUES AND INSIGHTS FOR LOWVOLTAGE HIGHDENSITY
SOI DRAM
4.1 Introduction
SOI DRAM, because of its immunity to latchup, low susceptibility to soft
errors, suppressed (normal) body effect, and small parasitic (source/drain)
capacitance, is attracting interest for highdensity memories operating at low voltage
[Yam95]. Indeed, recent demonstrations of highdensity SOI DRAM circuits
[Kim95], [Oas96] portend viable gigabit technologies in SOI, although lowvoltage
floatingbody effects in partially, or nonfully depleted (NFD) SOI MOSFETs imply
possible problems in dynamic data retention [Mor95], [Suh96], [Man96] and in data
sensing [Suh94b] and other peripheral functions [Sum94] of the DRAM circuit. The
data retention can be undermined by transient leakage current in the cell transistor
due to the parasitic BJT and/or thresholdvoltage lowering [Suh96], [Man96], both
of which are driven by dynamic body charging caused by intrinsic capacitive
coupling [Kri96a]. Several device and circuit design schemes to suppress the body
charging have been proposed [Yam95], [Suh96], [Man96], [Tom96], [Ter96]. The
peripheral functions seem to be sensitive to the floating bodycharging effects as
well, and hence most demonstrations of SOI DRAM have resorted to body ties in the
peripheral transistors [Oas96], [Sum94], which necessitate tradeoffs regarding
process overhead and circuit performance. Fully depleted (FD) SOI MOSFETs tend
98
Abstract of Dissertation Presented to the Graduate School of the
University of Florida in Partial Fulfillment of the Requirements
for the Degree of Doctor of Philosophy
PROCESSBASED COMPACT MODELING AND ANALYSIS OF
SILICONONINSULATOR CMOS DEVICES AND CIRCUITS,
INCLUDING DOUBLEGATE MOSFETS
By
MengHsueh Chiang
August 2001
Chairman: Jerry G. Fossum
Major Department: Electrical and Computer Engineering
The main topic of this dissertation is processbased modeling of scaled
silicononinsulator (SOI) complementary metaloxidesemiconductor (CMOS)
fieldeffect transistors (FETs), including doublegate (DG) MOSFETs. The
University of Florida SOI (UFSOI) fully depleted (FD) and partially depleted (or
nonfully depleted, NFD) SOI MOSFET compact models are refined and upgraded
in order to apply them in simulations of scaled SOI CMOS devices and circuits. For
DG MOSFETs, the first version of the University of Florida DG (UFDG) compact
model is developed.
As CMOS technologies are being scaled down to deep submicron
dimensions, more and more previously unimportant physical phenomena in the
shrinking MOSFETs are becoming significant. Polysilicongate depletion and
carrierenergy quantization, both of which reduce the drive current and the effective
Vll
167
Table 5.1 UFDG Model Parameters
VS AT
Carrier saturated drift velocity
ernes'1
l.OxlO7
VO
Velocityovershoot parameter

0.0
ALPHA
Impactionization coefficient
cm"1
0.0
BETA
Impactionization exponential factor
V'cm"1
0.0
BGIDL
GIDL exponential factor
(0 for no GIDL)
V'm"1
0.0
JRO
Bodysource/drain junction
recombination current coefficient
A^m'1
l.OxlO'10
M
Junction nonideality factor

2.0
CGFDO
Front gatedrain overlap capacitance
FmtT1
0.0
CGFSO
Front gatesource overlap capacitance
FmtT1
0.0
CGBDO
Back gatedrain overlap capacitance
Fnn"1
0.0
CGBSO
Back gatesource overlap capacitance
Fnn'1
0.0
RD
Specific drain parasitic resistance
ilm
0.0
RS
Specific source parasitic resistance
Qm
0.0
DL
Channellength reduction
m
0.0
DW
Channelwidth reduction
m
0.0
LDIFF
Effective diffusion length in source/drain
m
O.lxlO"6
SEFF
Effective recombination velocity in source/
drain
ernes'1
105
FNK
Flicker noise coefficient
(0 for no flicker noise)
F.A
0.0
FNA
Flicker noise exponent

1.0
Flag Parameters
Name
Description
Units
Default
BJT
Parasitic bipolar flag (0: off; 1: on)

0
94
devices possibly become NFD as noted previously. Figures 3.22 and 3.23 show
corresponding simulated and measured conductances, with very good agreement as
well. The nMOS and pMOS model parameters derived for the target channel length
are listed in Table 3.7. Unlisted parameters, which are unimportant, are set to their
Table 3.7 Evaluated Parameters for MITs 0.25mm FD/SOI CMOS Devices
Parameters
nMOS
pMOS
TOXF
8.0 nm
8.0 nm
TOXB
0.185 Jim
0.185 Jim
TB
0.05 im
0.05 im
NBODY
2.2xl017 cm'3
2.0xl017 cm'3
UO
700. cm2/V/s
200. cm2/V/s
THETA
0.75x10'6 cm/V
1.6x10'6 cm/V
VS AT
0.65xl07 cm/s
0.45x107 cm/s
KAPPA
1.0
0.7
GAMMA
0.5
0.5
TPG
1
1
TPS
1
1
RD
200.x 10'6 Qm
900.x 1 O'6 Qm
RS
200.x 1O'6 Om
900.x 10"6 am
DL
0.06 im
0.018 Jim
default values.
3.4 Summary
A processbased calibration methodology for UFSOI model parameter
evaluation has been developed. The UFSOI FD and NFD compact MOSFET models
173
evaluated and tuned from the systematic methodology, the UFDG model should
reliably predict the DC, AC, and transient characteristics of devices and circuits from
the calibrated DG CMOS technology.
5.3.2 Model Corroboration
The UFDG model is corroborated by comparisons compared with MEDICI
simulations, done without the QM option. We simulated the asymmetrical (n+ and p+)
and symmetrical DG MOSFETs used for Fig. 5.6, except the two gates of the symmetrical
device are now replaced with near midgap gates to give an equal threshold voltage for the
two devices. (The structure of the devices, as indicated in Fig. 5.1, is designed with tof = tob
= 3 nm, tSi = 10 nm, NA = 1015 cm'3, and L (= Lmet) = 50 nm.) With such redesign of the
symmetrical device, the model and MEDICIpredicted (channel) currentvoltage
characteristics are shown in Fig. 5.12. (Here, the default HD parameters in MEDICI were
used, and the leff parameters in (5.31) were tuned to the MEDICI mobility model.) With
no optimization of the device model parameters, the agreement is excellent for all bias
conditions, except for the discrepancy in the subthreshold slope due to some uncertainty in
weak inversion. Note that the respective Ions in the two devices are nearly equal, even
though the asymmetrical DG device has only one predominant channel. This result is
consistent with the prediction for inversion charge, as discussed previously in Sec. 5.2.3.
Verification via CV characteristics are essential for reliable transient as well
as AC simulations. We apply the UFDG model to the same devices (with
WxL = 10imx50nm) to examine their CV characteristics. Figure 5.13 shows
the simulated (quasistatic) gate CV characteristics of the asymmetrical and
symmetrical DG MOSFETs. In the highbias region, the capacitances of the two
188
(QM) confinement is one of the most urgent issues for highly scaled DG MOSFETs.
To account for QM effects in ultrathin Si films, we need to solve Poisson and
Schrodinger equations selfconsistently and iteratively, for which this classical
version of UFDG will provide the initial bases. The effects of QM confinement on
other device characteristics such as mobility will need to be linked physically.
Since the DG MOSFET is a futuristic device, the measured data during the
model development could be very limited. Some physicsbased model collaboration
with more fundamental device simulators, e.g., MonteCarlo simulation, can be
helpful in minimizing the use of empirical parameters. Therefore, it is of interest to
construct a reliable and systematic methodology to link the compact and numerical
device simulators.
Using UFDG to assess DG CMOS technology has not yet been done
comprehensively. Effects of parasitics, e.g., gategate resistance, overlaps, source/
drain resistance due to the thin Si film, and other parasitics due to the external gate
link, on DG CMOS performance will need to be checked. Also, if the device
characteristics are sensitive to misalignment, which results in nonequal electrical
channel lengths for front and back gates, gradual channel approximation will become
invalid; therefore, some model upgrade will be needed.
Novel device structures including a SiGe channel might help increase the
carrier mobility. For ultrathin Si films, QM confinement can also effect the
mobility. However, the study of carrier mobility in a heterojunction (in vertical or
lateral direction) channel subject to QM confinement has never been done. Such a
structure might be also used to define the threshold voltage via the work function.
Preliminary study can be done based on device simulation.
166
and numerical simulation results will be compared as well. Finally, the model utility
will be demonstrated via some examples of device and circuit simulations with
UFDG/Spice3.
5.3.1 Model Calibration
The UFDG model is processbased, involving only physical and structural
parameters. The parameter evaluation thus can be done systematically, based on
knowledge of the DG technology and underlying physics. Only a few key parameters
need to be tuned via specific device measurements. The UFDG model parameters, as
listed in Table 5.1, are very similar to those of the UFSOI/FD model without fringing
Table 5.1 UFDG Model Parameters
Name
Description
Units
Default
NQFF
Front oxide fixed charge (normalized)
2
cm
0.0
NQFB
Back oxide fixed charge (normalized)
.2
cm z
0.0
NQFSW
Effective Sidewall fixed charge (normalized)
(0 for no narrowwidth effect)
2
cm z
0.0
NSF
Front surface state density
.9
cm
0.0
NSB
Back surface state density
2
cm
0.0
TOXF
Frontgate oxide thickness
m
3.0.xl09
TOXB
Backgate oxide thickness
m
3.0 xlO"9
NBODY
Film (body) doping density
3
cm
l.OxlO15
NDS
Source/drain doping density
3
cm
5.0xl019
TB
Film (body) thickness
m
10.0x1 O'9
UO
Lowfield mobility
cm2\rls'1
700 (n)
250 (p)
THETA
Mobility degradation coefficient
cm*r'
1.0x106
30
\fsf [Suh95a]. Substituting nÂ¡^M into nÂ¡ of the weakinversion model [Suh95a] yields
a new solution for channel current. The simulation time is not lengthened as the
weakinversion current is calculated analytically without iteration.
For VTW < VQfs < VTS, the solutions at the boundaries are also updated
according to weak or stronginversion modeling, and hence the moderateinversion
solutions are implicitly influenced via spline interpolation.
FD Model Formalism
To account for the QM effect in the FD model, we again apply the
aforementioned theory for the NFD model in a similar manner; (2.43) and (2.44) are
still the main bases here. The regional modeling approach involving two boundaries
is adopted as well.
As demonstrated for the NFD model, the basic derivation can be similarly
applied to the FD model [Yeh95] with the same criterion for defining the strong
inversion boundary [Tsi82]:
(2.50)
20Vt(1 +a)Cof
Qr
(2.51)
with
0B VTln
(2.52)
12
1 /2 f
Qdgf = [2Â£sqNp\/gf] = e0Eof = C0f(VGfs\/sfV/gfO ms)
(2.6)
Thus V/gf can be solved analytically as
Vgf =
CofV
qNpÂ£s + Cof(VGfS ms Vsf)
(qNpe,(qNpEs + 2C^,(Vofs 4fms Â¥sf))>
(2.7)
AQcf(y) and AQcb(y) When VDS > 0
Now, to account for the perturbation due to VDS > 0, we need to evaluate
Qcf + AQcf Qcb + AQcb> Vsf + AVsf> Â¥sb + AVsb and Vgf + AÂ¥gf with
A\/sf(0) = 0 and A\/sf(L) = VDS. When VDS > 0 in strong inversion, the channel
charge change due to drain bias, AQcf, is not included in gradualchannel
approximation (GCA), so we follow the DICE analysis [Vee88a], and obtain
AEsb(y)= AEsf(y)tbti, (2.8)
and
AvSb(y) = AvSf(y)AEsf(y)tb2
where r\ = (2/L2)VDS. Also, (2.1) gives
AÂ¥Sf(y) + Avgf(y) + Av0f(y) =
(2.9)
(2.10)
Applying Gausss law to the front interface, with (2.8), (2.9) and (2.10), then yields
87
Stage 4
Evaluated Parameters
Measurement Data
Device
DL, KAPPA
IDS vs. V(3fS @ high (2 V) & low
VDS (50 mV)
ShortL
The channellength reduction DL can be evaluated (refined) from its
influence on the shortchannel effects. For example, in the subthreshold region, the
DIBL effect is worsened as DL increases. However, as described in (3.10), KAPPA
tends to be predominant for high VDS and short L. So, to account for both the
fringingfield and the shortL effects, we tune (refine) DL and KAPPA
simultaneously by fitting the current and slope of subthreshold Ios'^GfS
characteristics at different values of VDS, as illustrated in Fig. 3.17. Unexpectedly,
we find that KAPPA for the nMOS device needs to be increased significantly from
the value in Table 3.6 to match the abnormally high subthreshold current at high VDS.
Although the BOX fieldfringing could be the underlying reason for the high current,
this result portends the possibility of punchthrough or, as was evident for the longL
device, a draininduced transition to the NFD mode, which would result in a higher
S (see (3.1)) as in Fig. 3.17(a). Nonetheless, we obtain DL = 0.06 Jim and KAPPA =
1.0 for nMOS, and DL = 0.018 p,m and KAPPA = 0.7 (given previously) for pMOS.
Stage 5
Evaluated Parameters
Measurement Data
Device
RD, RS
IDS vs. VGfS @ low VDS (50 mV)
ShortL
110
VDD
Figure 4.4 Schematic diagram of DRAM senseamplifier circuit.
The DRAM sense amplifier includes precharge and enable circuitry and shows
two complementary datastorage cells on the bitlines.
J 11 11
8
in Appendix A. Indeed, the physical nature of the UFSOI models facilitates these
upgrades.
2.2 PolysiliconGate Depletion
Current n+/p+ dualgate CMOS technology limits the electrically active
doping concentration in implanted polysilicon to ~5xl019 cm'3 [Sch93], The implant
and annealing condition for the polysilicon must be carefully selected to avoid
impurity penetration through the gate oxide, while controlling the depth and the
lateral diffusion of source/drain junctions [Rio94], As a result, a depletion layer can
exist near the polysilicon/oxide interface, and a significant potential drop can be
developed across this depletion region depending on gate biases; this is referred to
as the polydepletion effect. Though we can use an electrical oxide thickness to
empirically emulate polydepletion effects, it might lose accuracy while the device
is further scaled, and further the transient effect of gatedepletion capacitance is
ignored in this empiricism. We hence need to account for polysilicon depletion with
a physicsbased model.
Some studies presented analytical models [Rio94], [Aro95], [Che95] and
characterization [Ric96] of poly silicon depletion for bulk MOSFETs, but they are not
fully adequate for SOI MOSFETs. Here, we present new modeling for FD and NFD
SOI MOSFETs, and implement this modeling in UFSOI models. We also investigate
and discuss the effects of IY and CV degradation due to polydepletion, and its
translations to circuit performance. In addition, optimal design criteria for devices as
well as circuits are suggested from the simulation results and discussions.
55
BGIDL evaluation in this stage, knowing that it is independent of L.
For scaled devices, the thermal generation should correlate with the thermal
recombination. Hence, the value of TAUO should be loosely correlated with JRO in
accord with basic pnjunction recombination/generation properties as follows:
qnÂ¡TFyd
JRO =
(3.3)
and
2TAUO
1 + NBH/N0
(3.4)
where yd, typically ~50 nm, is a junction space chargeregion width, and N0 is
5xl016 cm'3. With (3.3) and (3.4), TAUO calculated from the default JRO (1.0x10'
10 A^m'1) is on the order of 1 is, which is physically consistent with recent
technologies. In UFSOI4.5, TAUO is defaulted to 0 and used as a flag for internal
calculation of the generation current, based only on JRO as indicated by (3.3) and
(3.4). However, for longL devices, the generation current from the channel/body
region will require tuning of TAUO, which is done as described herein.
We suggest that BGIDL first be tuned to fit GIDL current of the Ios'^GfS
characteristic at high VDS and VGfS < 0 (where GIDL is most significant) for nMOS,
as demonstrated in Fig. 3.4(a), using an estimated DL from the technology. Then we
tune JRO to calibrate the prekink region of the highVDS curve, and tune M to set
the kink effect, as well as finetune the prekink region in conjunction with JRO. This
calibration is illustrated in Fig. 3.4(a). Once JRO is obtained, TAUO (for the longL
101
4.1. The parasitic BJT current Ibjt(^bS^Bd) as we^ as the bipolar components of
terminal charges have been recently upgraded [Kri96a], The NFD MOSFET model
was calibrated to the (nchannel) cell transistor of a contemporary SOI DRAM
technology (see Table 4.1), with channel doping of 6.8x10 cm and oxide
Table 4.1 Characteristics of SOI DRAM MOSFETs
Sense Amplifier
VTN
0.5 V
VTp
0.6 V
wn/ln
5 pm/0.24 pm
Wp/Lp
4 pm/0.24 pm
Storage Cell
vT
1.0 V
W/L
0.2 pm/0.36 pm
thickness of 8 nm, which define the threshold voltage of about 1 V. The gate size is
W/L = 0.2 pm/0.36 pm, with the effective channel length being 0.3 pm. The
calibration resulted in predicted DC device characteristics and transient leakage
current matching measured data [Kri96a].
To put our simulations in perspective, consider the floatingbody effects of
the bitline (source) dropping from Vs = VDD (or from VDD/2) to 0 V as indicated in
Fig. 4.1, with the storage node (drain) at VSN = 1.5 V and the wordline (gate) at 0 V.
If the DC condition has obtained prior to the Vs(t) pulse, then the bodysource
junction bias, VBS, is zero (or, for Vs = VDD/2, slightly positive (~0.1 V) in support
of the junction recombination that balances the generation from the reversebiased
bodydrain junction). Then the drop of Vs(t) induces, due to the gatebodysource
152
bulk Si; the carrier mobility in lowfield region, as shown in Fig. 5.8, can hence be
calibrated to measured data. Also, we can alter 0 to determine the mobility
degradation in the highfield region where the surface scattering is predominant.
Though these parameters are quasiempirical and hence their values will vary for
different devices, their mechanisms are linked to the model with a physical basis. The
results shown in Fig. 5.8 are consistent with published MonteCarlosimulated
results [Gam98] and measured data [MasOl], Note that when quantummechanical
confinement is taken into account, volume inversion in ultrathin DG devices could
result in higher jieff at high Esf [Gam97], [GamOl], Other researchers have provided
different explanations for the mobility decrease with decreasing tsi, e.g., the stress
increase due to lattice defects [Cho95] or the increase in Coulomb scattering rate due
to the interface trap density at the back surface [Tor95]. Nonetheless, these
arguments are supplementary to the universal model presented here since all of
them affect the mobility similarly.
Current
Based on the previously described analysis, we develop here a model for the
channel current in the linear/triode region of operation of the generic DG MOSFET.
For strong inversion, the channel current is dominated by the drift component
classically. The carrier drift velocity in the channel tends to saturate at vsat for a very
high longitudinal field Ey. However, for the scaled DG MOSFET, velocity
overshoot (> vsat) must be accounted for. So, vsat is being augmented for possible
quasiballistic transport; vsat is replaced by vsat(eff)(VGfs, VGbS, VDS), which is
defined (in preprocessing) based on a simplified energy balance equation [GeOl].
153
The velocity overshoot is significant in scaled devices because the gradient of lateral
electric field (Ey) is very high in the channel, and hence the nonstationary carrier
transport can be anticipated as the carrier transit time approaches, or becomes less
than, the energy relaxation time. The vsat(eff) model provides a physical link between
classical driftdiffusion and ballistic transports.
We now express the drift velocity as [Sod84], [Gar87], [Vee88b]:
v(y) =
MeffE>
1 +
M'eff Ey ^^vsat(eff)
for v < v
sat(eff)
(5.32)
Jleff is characterized in (5.31). Since VTS as defined in Sec. 5.2.1 is lower than the true
onset voltage for strong inversion [Tsi82] (which is used in the UFSOI/FD model),
our stronginversion analysis must account for diffusion current as well as drift
current. Therefore, we express the steadystate channel current as
dQc(y)
Ich = WQc(y)v(y) + WD^i (5.33)
kBT
with Dn = ieff ; Qc(y=0) at the source is that characterized in (5.23).
Substituting v(y) of (5.32) into (5.33), with Ey = defined by a representative
potential along the channel, yields
^hdy +
Ic.h.^iLdv)/
0 \r
zvsat(eff)
kRT kRT u.pff
 WQcneffdÂ¥ + WÂ£ne(fdQc + wS^r52
sat(eff)
d\/
: dy
dQc^.
(5.34)
We assume that the variation of \\r along y is independent of x; then
54
(a)
(b)
Figure 3.4 IDS VGfS characteristics of 1.0 im NFD/SOI devices (Stage 4).
(a) nMOS. (b) pMOS.
181
the asymmetrical DG device has nearideal S and almost twice higher Ion than the SG
counterpart as results of the inherent gategate charge coupling. A similar result has
been predicted in Fig. 5.5 for comparison of inversion charge.
Using the same 9stage RO circuit for previous example, we also check the
performance of DG and SG CMOS circuits, as demonstrated in Fig. 5.17. The DG
MOSFET not only has better scalability and higher density, but also has dramatically
superior performance over the SG counterpart due to higher vsat(eff) implied by
higher mobility. For low VDD, the DG circuit performs even much better than the SG
one because the dynamic threshold effect implied by low S gives a higher gate
overdrive (VGS VT). Additionally, in weak inversion, near zero gate capacitance of
the DG device due to charge neutrality is another great advantage over conventional
bulklike CMOS, as noted earlier.
5.4 Conclusion
A preliminary version of processbased compact DG model (UFDG) was
developed, using UFSOI/FD MOSFET model as the initial basis. Charge coupling
and inversion charge distribution were accounted for in the thin Si film via key
approximations. The dependence of carrier mobility on thin Sifilm thickness was
included.
To ensure model reliability for scaled DG MOSFET applications, the
solutions from the classical version of UFDG will be the initial bases for quantum
mechanical (QM) analyses, which solve Poisson and Schrodinger equations self
52
simulations, and the measured data are taken at 1 MHz from floatingbody
nMOSFETs and pMOSFETs with VDS = 0. The gate width and length of the devices
are 2000 im and 0.5 im, respectively. Note that the latter is not long, and hence
CGFSO and CGFDO can be tuned as well. However, to avoid the effects of overlap
capacitances and DL, longL devices are preferable. In this example, NGATE and
QM are tuned as 2.0 x 1019 cm'3 and 0.45, respectively, for nMOS, and 7.5 x 1019
cm'3 and 0.4, respectively, for pMOS. Note that the nMOS characteristic implies a
flatband voltage that is slightly different from that of the devices used to calibrate
the model.
In addition, other parameters can be either evaluated or verified via the CV
characteristic in the accumulation region. As indicated in Fig. 3.3, floatingbody
effects are apparent and must be accounted for. The floating body is capacitively
coupled to the gate, but the hole charge in the body cannot respond at the high
frequency; hence the source/drain junction capacitance becomes important in the
accumulation region. Examination of the measured and simulated CV
characteristics in different gatebias regions gives good insight on the floatingbody
effects and lends support to the UFSOI basic charge/capacitance modeling and
calibration. In the accumulation region, the relatively low capacitance, in contrast to
that of a tiedbody device, reflects the predominant source and drain junction
capacitances, as well as overlap capacitances. In this region then, NBH and TF can
be refined, and the overlap capacitances can be tuned. We find that CGFDO and
CGFSO are effective values, larger than Â£oxDL/2TOXF, because of the fringing
components not accounted for explicitly in the UFSOI model. NBH and TF influence
93
(a) IDS VGfs characteristics; L = 0.25 im (d) IDS VGfS characteristics; L = 0.5 (im
Figure 3.21 Calibrated 1(A) V(V) characteristics of FD/SOI pMOS devices.
76
Table 3.4 UFSOI4.5 FD MOSFET Model Parameters
uo
Lowfield mobility
cm2*V'1s'1
700 (n)
250 (p)
200700 (nMOS)
70400(pMOS)
THETA
Mobility degradation coefficient
crmV"1
1.0x1 O'6
(0.13)xl0'6
VS AT
Carrier saturated drift velocity
cms']
l.OxlO7
(0.5l)xl07
ALPHA
Impactionization coefficient
cm'1
0.0
2.45x106
BETA
Impactionization exponential factor
Vnrni'1
0.0
1.92xl06
LLDD
LDD region length (0 for no LDD)
m
0.0
(0.050.2)xl06
NLDS
LDD/LDS doping density
(>lxl019: D/S extensions)
3
cm
5.0xl019
lxlO19
GAMMA
BOX fringing field weighting factor

0.3
0.31.0
KAPPA
BOX fringing field weighting factor

0.5
0.51.0
BGIDL
GIDL exponential factor
(0 for no GIDL)
Vnn'1
0.0
(48)xl09
JRO
Bodysource/drain junction
recombination current coefficient
Ann'1
l.OxlO'10
q
i
o
i
VO
M
Junction nonideality factor

2.0
1.02.0
CGFDO
Gatedrain overlap capacitance
FmT1
0.0
lxlO'10
CGFSO
Gatesource overlap capacitance
F^m"1
0.0
X
o
1
CGFBO
Gatebody overlap capacitance
Fm'1
0.0
0.0
RD
Specific drain parasitic resistance
ilm
0.0
(IOOIOOO)xIO'6
RS
Specific source parasitic resistance
ilm
0.0
(IOOIOOO)xIO'6
RHOB
Body sheet resistance
Q/sq.
0.0
30x103
DL
Channellength reduction
m
0.0
(0.050.15)xl0'6
DW
Channelwidth reduction
m
0.0
(0.10.5)xl0'6
LDIFF
Effective diffusion length in
source/drain
m
O.lxlO'6
(0.10.5)xl06
This dissertation was submitted to the Graduate Faculty of the College of
Engineering and to the Graduate School and was accepted as partial fulfillment of the
requirements for the degree of Doctor of Philosophy.
August 2001
Pramod P. Khargonekar
Dean, College of Engineering
Winfred M. Phillips
Dean, Graduate School
100
Gf
BL
WL
DD
vs(t)
NFD/nMOS
ySN(t)
= CS
0
Figure 4.1 SOI DRAM pass transistor with the network representation.
SOI DRAM pass transistor circuit with the network representation of the
SOISPICE chargebased (nMOS) model.
178
asymmetrical DG device like an FD SOI MOSFET, for which the high Ioff becomes
an issue. Conversely, the symmetrical DG device has lower Ion for thicker back oxide
because of less backchannel current.
Note that, as shown in Fig. 5.14(b), the nominal Ion of the asymmetrical DG
device is about 10% lower than that of the symmetrical one due to less total charge.
However, Fig. 5.7 shows that the difference in charge is as much as 14% for the two
devices, although we expect to see more mobility degradation due to the higher
surface field and hence less current for the asymmetrical DG device. Because the
predominant channel of the asymmetrical DG device has more charge than any
channel of the symmetrical one, its VDS(sat) controlled by velocity saturation is
higher and hence higher saturation current (Ion) can be obtained in spite of mobility
degradation.
For the same backoxide thickness variation, we further look at its impact on
the inverter delay. An unloaded 9stage CMOSinverter ring oscillator with 20% gate
overlaps on both gates is simulated in order to extract the inverter delay, as shown in
Fig. 5.15. The delay is predominantly governed by Ion, which has similar sensitivity
to tob variation. Also, the nominal inverter delay of the symmetrical DG device is
faster due to its higher Ion. Even though thicker tob seems better for the asymmetrical
DG CMOS circuit in performance, as indicated in Fig. 5.15, the Ioff issue will prevent
the use of thick back oxide. The predictive capability and generic nature of the DG
model is useful for sensitivity study at both the device and circuit levels.
Finally, we apply the UFDG model to the 50 nm asymmetrical DG and SG
(with backgate grounded) MOSFETs for comparison. As can be seen in Fig. 5.16,
109
assessed to determine if body ties are really needed, and if so, how sophisticated they
must be with regard to yielding low enough body resistance. Calibrating the NFD
model and the circuit to the mentioned SOI DRAM technology, we apply SOISPICE
to the DRAM sense amplifier to make this assessment, and to explore other possible
designs for controlling the dynamic floatingbody effects in the peripheral circuits.
4.3.1 Overview of the Sense Amplifier
The schematic of the full CMOS senseamplifier circuit is shown in Fig. 4.4.
The characteristics of the constituent SOI/NFD MOSFETs are listed in Table 4.1.
The sense amplifier is composed of two coupled nMOS/pMOS pairs, Nl/Pl and N2/
P2. The biasing circuit, comprising NO, P0, N3, and P3, is activated by the enable
signal VSE. The pMOS transistors P4, P5, and P6 represent the precharging circuit,
which charges the bitlines, BL and BL, up to VDD/2 (= 0.75 V) when activated by
VpRE. Such precharging is commonly used to improve the speed performance of
sensing, but as implied in Sec. 4.2, it will influence the dynamic floatingbody effects
in the amplifier. Cell pass transistors, e.g., NCI and NC2, are part of the circuit
simulated; the storage capacitors, e.g., CS1 and CS2, have capacitance Cs = 25 fF,
which reflects neargigabit technology. The bitline capacitances, represented by
CBL. are 250 fF, which corresponds roughly to 512 cells, or wordline (WL) rows.
The normal sensing operation of the amplifier is indicated by the sequential
pulses of VPRE, V(WL), and VSE as shown in Fig. 4.5; we assume 10ns precharge
and sense times with Ins rise and fall times. The sense amplifier must respond to the
small differential voltage established across the bitlines by activation of WL1 (while
WL2 remains off),
27
we incorporate this model formalism into NFD and FD models individually as
follows.
NFD Model Formalism
Consider first the stronginversion model. The QM upgrade is developed for
the NFD model by redefining njQM from (2.44) and EgQM (=Egconv+ AEg) from
(2.43). Further, the previously defined boundary at the upper limit of moderate
inversion (VTS), with the corresponding surface potential (irsfS), must be upgraded
accordingly. However, the convergence and nonlinearity issues might be brought out
in circuit simulation due to the newly defined biasdependent boundaries, which
should be treated carefully when implementing this model. (We will discuss the
details in the final part of this model formalism.)
In the NFD model, the stronginversion boundary was defined as [Suh95a]
vTS vTSO + avts
(2.45)
where VTSO is evaluated at VDS = 0, and AVXS is introduced by a 2D draininduced
effect (DICE). To calculate VTS0, we should know the surface potential, \j/sfS, which
is solved iteratively, subject to the criterion defined in [Tsi82]:
(2.46)
(2.47)
37
Figure 2.5 CV characteristics of an NFD/SOI nMOSFET (f = 1 MHz).
Floatingbody CGfVGfS characteristics (100 (im x 100 im).
112
AV = V(BL)V(BL) = ) (42)
For example, when reading a 0 on CS1, AV < 0 must result in N1 and P2 being
turned on, and N2 and PI off, which means V(BL) and V(BL) go to 0 and VDD,
respectively. The bit is thus read, and the referenced cell is simultaneously refreshed.
With regard to possible floating bodyinduced instabilities, N1 and N2, which drive
the proper states of the coupled transistor pairs in response to AV, are the most
crucial devices.
4.3.2 Dynamic Instabilities
The threshold voltages of N1 and N2 with floating bodies are dynamic, or
timedependent and hysteretic [Suh94b]. If, in normal operation of the sense
amplifier, the transistors are in different bias conditions that define different carrier
recombination/generation rates in the bodies for extended periods of time, then
subsequent gate pulses will induce different VBS(t) that will define different dynamic
threshold voltages, VT(t). Because AV in (2) is small, the VT(t)s of N1 and N2 can
be randomly unbalanced enough to cause instability in the sense amplifier. It is
possible that the read/refresh operation described above will not flip the coupled
pairs correctly, yielding an erroneous bit which in turn is written onto the referenced
storage capacitor.
The possible instabilities due to the dynamic floatingbody effects in N1 and
N2 are exemplified as follows. Suppose that the circuit is held for a lengthy time with
V(BL) = 0 and V(BL) = VDD (as in an extended read or write0). This means that
Vds(N2) = VDD and VDS(N1) =0, and hence VBS(N2) > VBS(N1) by about 0.2 V,
123
4.4 Conclusion
A physical, SOISPICE simulationbased study of lowvoltage floatingbody
effects on the operation of NFD/SOI DRAM has been described. With the NFD
MOSFET model in SOISPICE calibrated to an actual SOI DRAM technology, the
longterm dynamic retention of the datastorage cell and the general performance of
the sense amplifier were examined. The dynamic retention for normal accessmode
was found to be defined predominantly by the thermal generation leakage current
and, subject to the carrier lifetime, suitable for gigabit applications. However,
several V(BL) = VDD quiescent periods between datarefresh cycles in the page mode
can lead to shortened retention time; but doable improved device design (with SiGe
source/drain) was shown to be effective in resolving this problem. The simulations
of the sense amplifier predicted instabilities (bit errors) due to thresholdvoltage
imbalances caused by hysteretic dynamic body charging. However, crude nMOS
bodytosource ties, having very high (distributed) resistance, were found, even with
floating pMOS bodies, to be effective in suppressing the instabilities. A process/
circuitbased sensitivity analysis of the critical body resistance needed for the
suppression gave good insight on how dynamic body charging can produce the VT
imbalances and the instabilities, and on how a simple BTSbased design is effective
in suppressing them.
Additionally, a novel bodytiedtobody (BTB) SOI CMOS inverter
configuration, which can effectively suppress the historydependent floatingbody
effects while attaining the beneficial capacitive coupling in floatingbody SOI
MOSFETs was introduced and assessed (in Appendix B). Although the simulation
39
Figure 2.6 Predicted circuit performance of NFD SOI CMOS.
UFSOIpredicted (a) delay time and (b) powerdelay product vs. gate doping for
a 9stage CMOS inverter ring oscillator.
77
Table 3.4 UFSOI4.5 FD MOSFET Model Parameters
SEFF
Effective recombination velocity in
source/drain
cm's'1
105
(0.55)xl05
FNK
Flicker noise coefficient
(0 for no flicker noise)
F.A
0.0
010'25
FNA
Flicker noise exponent

1.0
0.52
Flag Parameters
Name
Description
Units
Default
Typical Value
BJT
Parasitic bipolar flag (0: off; 1: on)

1
1
TPG
Type of gate poly
(+1: opposite to body;
1: same as body)

+1
+1
TPS
Type of substrate
(+1: opposite to body;
1: same as body)

1
1
SELFT
Selfheating flag
(0: no self heating;
1: approximate model; 2: full model)
0
0
Optional Model Parameters
Name
Description
Units
Default
Typical Values
TAUO
Carrier lifetime in lightly doped region
s
Calculated
o
i
l
o
1
U\
VFBF
Frontgate flatband voltage
V
Calculated
1 (nMOS)
1 (pMOS)
VFBB
Backgate flatband voltage
V
Calculated

WKF
Frontgate work function difference
V
Calculated
VFBF
WKB
Backgate work function difference
V
Calculated

BFACT
VDSaveraging factor for
mobility degradation

0.3
0.10.5
FVBJT
BJT current directional partitioning
factor (0 for lateral ID flow)

0.0
01
RHOSD
Source/drain sheet resistance
O/sq.
0.0
50
176
devices are nearly equal to 2C0f since both surfaces of both devices are strongly
inverted. Note, however, the lower CG (< 2Cof) of the asymmetrical DG device in
strong inversion, which can give an advantage in circuit performance. In the weak
inversion region, near zero capacitance is predicted due to charge neutrality, which
is another great advantage of DG MOSFETs. Note that the capacitance in the
accumulation region is very low. The floating body is capacitively coupled to the
gate, but the hole charge in the body cannot respond at the high frequency; hence the
(low) source/drain junction capacitance becomes predominant.
5.3.3 Device/Circuit Application
The main utility of the UFDG model is for circuit application, which will be
demonstrated in this section via a few examples. The generic DG model is useful for
assessment of various device structures at both the device and circuit levels. More
importantly, the model can be applied to gain insight on the effects of device
parasitics (e.g., overlap capacitance) on device and circuit performance.
We first exemplify the model application with modelpredicted Ioff and Ion
versus backoxide thickness variation for the 50 nm asymmetrical and symmetrical
DG MOSFETs previously described. As indicated in Fig. 5.14, very different
sensitivities are predicted for the same backoxide thickness variation. The Ioff of the
asymmetrical DG device increases rapidly as backoxide thickness increases due to
less chargecoupling effect; a lower threshold voltage can be predicted via (5.4) with
smaller Cob (prevalent) and r, as indicated earlier in the section of VTS. In other
words, the threshold voltage of the asymmetrical DG MOSFET has a stronger
dependence on the back oxide thickness. Continuously increasing tob will make the
113
which is the DC value defined by Ir(Vbs) = IGt in N2. But more importantly,
VGfS(N2) =0 and VGfs(Nl) = VDD, which means that the body charges (QB) of N1
and N2 are unbalanced significantly; N1 is on and N2 is off, meaning QB(N2) >
Qb(N1). Note that this nearDC QB imbalance occurs irrespective of the VBS
imbalance. Now when a subsequent sense cycle including precharge occurs as
indicated in Fig. 4.5, the gatebodysource capacitive coupling [Kri96a], influenced
by the QB imbalance, will produce transient VBS(t)s that define unbalanced dynamic
threshold voltages, VT(N2) < VT(N1), and an erroneous bit can possibly be recorded.
In this case, the possible error would result from reading a 0; the lower VT of N2
relative to that of N1 could prevent the proper flipping of the coupled pairs. Note that
reading a 1 would proceed normally however in this case, without the possibility
of error. Obviously an extended period with opposite bitline voltages would result in
a read1 instability though.
The SOISPICE simulation results in Fig. 4.6 illustrate such instabilities in
the sense amplifier and reveal why the noted extended period is the underlying cause.
The simulation was started by using SPICE ICs to set V(BL) to 0 and V(BL) to
VDD, and then, in the transientsimulation mode, letting the circuit stabilize for
several (35) nanoseconds. This startup emulates an extended period between a read
or write0 operation and the precharge prior to a sense operation. Note the initial VBS
imbalance, but note especially how the imbalance worsens when the precharge pulse
starts at t = 35 ns. As all nodes are brought to VDD/2, the strong gatebody capacitive
coupling in N2, due to the high QB, causes VB to follow VGf, and hence VBS(N2)
decreases relatively little as Vs is brought up. Contrarily, the gatebody capacitive
137
(b)
Figure 5.3 MEDICIsimulated electric fields and potentials for DG devices.
(a)electric fields and (b)potentials for asymmetrical and symmetrical devices at
VGfS = VGbS = 05 v with tsi = 10 nm> Na = 1.0x10s /cm3, and t0Xf = t0xb = 3
nm. As can be seen in (a), the asymmetrical device has a predominant front
gate, while the virtually constant E along the Si film indicates a weakly
inverted back channel, and the symmetrical device has two equally inverted
channels with E(tSi) = E(0).
105
Figure 4.3 SOISPICEpredicted decay of VSN(t) for different threshold voltages.
The threshold voltage of NFD/SOI passtransistor is varied by channel doping
density.
KEY TO ABBREVIATIONS
BTB
bodytiedtobody
BTS
bodytiedtosource
CMOS
complementary metaloxidesemiconductor
DG
doublegate
DIBL
draininduced barrier lowering
DICE
draininduced current enhancement
FB
floating body
FD
fully depleted
GIDL
gateinduced drain leakage
IC
integrated circuit
LDD/S
lightlydoped drain/source
MOSFET
metaloxidesemiconductor fieldeffect transistor
NFD
nonfully depleted (partially depleted)
SOI
silicononinsulator
UFDG
University of Florida doublegate (model)
UFSOI
University of Florida silicononinsulator (models)
vi
Ill
1.5 V
OV
VPRE
2.5 Vr
OV
V(WL1)
0 V
V(WL2)
1.5 Vr
ov
V
SE
10 ns
Figure 4.5 Representative pulse sequence for sensing data in DRAM.
PROCESSBASED COMPACT MODELING AND ANALYSIS OF
SILICONONINSULATOR CMOS DEVICES AND CIRCUITS,
INCLUDING DOUBLEGATE MOSFETS
By
MENGHSUEH CHIANG
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2001
148
We start the mobility model development from the classical universal
mobility model. For conventional MOSFETs, the transverse electricfield
dependence of carrier mobility, or surfacescattering rate, is modeled [Sch55],
[Whi80], [Sun80], [Gar87] in terms of an average of the transverse field as
Meff
H0_
1 + 0ExO
(5.25)
where 0 is a mobility degradation factor, Ex0 is defined at the source by the induced
inversion and depletion charge densities, and (i0 is the lowfield mobility in the bulk
silicon, defined by the doping density. However, for the DG MOSFET, the
dependence of carrier mobility on the Si film thickness will be significant and must
be taken into account.
Â¡IÂ¡
Basically, ieff may be related to the conductivity effective mass m and the
relaxation time as
Meff ~
q('c)
m*
where (t) is an average momentumrelaxation time computed by
J = 1 I
<*> *b +
(5.26)
(5.27)
where xb is the momentumrelaxation time in bulk silicon and Ts is defined by surface
scattering. We need to define xb to account for the excess phonon scattering in the
thin Si film as discussed previously. We thus let
42
Table 3.1 UFSOI4.5 NFD MOSFET Model Parameters
Name
Description
Units
Default
Typical Values
NQFF
Front oxide fixed charge
(normalized)
_2
cm
0.0
~1010
NQFB
Back oxide fixed charge
(normalized)
.9
cm
0.0
~10n
NQFSW
Effective sidewall fixed charge
(0 for no narrowwidth effect)
2
cm ^
0.0
~1012
TOXF
Frontgate oxide thickness
m
lO.xlO"9
(38)xl0'9
TOXB
Backgate oxide thickness
m
500.x 10'9
(80400)xl09
NSUB
Substrate doping density
3
cm
l.OxlO15
10151017
NGATE
Polygate doping density
(0 for no polygate depletion)
3
cm
0.0
1019102
NBL
Low body doping density
3
cm
5.0xl016
10171018
NBH
High body doping density
3
cm
5.0xl017
lxio18
NDS
Source/drain doping density
3
cm
5.0xl019
1019102
TF
Silicon (SOI) film thickness
m
200.x 10"9
(100200)xl0'9
TB
Effective (depleted) film thickness
m
100.x 1 O'9
(2550)xl09
QM
Energy Quantization Parameter
(0 for no quantization)

0.0
00.5
THALO
Halo thickness (0 for no halo)
m
0.0
(50100)xl0'9
NHALO
Halo doping density
3
cm
0.0
lxlO18
LRSCE
Characteristic length for reverse
shortchannel effect (0 for no RSCE)
m
0.0
O.lxlO'6
UO
Lowfield mobility
cmW's'1
700 (n)
250 (p)
200700 (nMOS)
70400 (pMOS)
THETA
Mobility degradation coefficient
cm*V1
1.0x10'6
(0.13)xl0"6
VSAT
Carrier saturated drift velocity
crms'1
l.OxlO7
(0.5l)xl07
128
physical regional modeling. The VTW characterization [Yeh95] accounts for the
condition when two channels are in weak inversion, including their chargecoupling
effect; it is applicable to the model for DG MOSFETs, whereas the UFSOI VTS
characterization, based on a single channel, is not. For UFDG, we hence need to
redefine VTS, based on the new stronginversion formalism to be described.
However, since the boundaries are usually not critical, a simpler chargesheet
formalism can be useful for deriving VTS. To have a consistent and more efficient
model, the simplified approach, which is described as follows, is also adopted for
VTW derivation as well.
StrongInversion Threshold
The stronginversion boundary, VTS, needs to be defined based on the
underlying physics, including the charge coupling between the two gates. The
analytical equations to be derived later for stronginversion formalism can be useful
for this definition. However, using the Newton iteration to solve for VTS seems
inefficient and impractical since this boundary will not substantially effect the
solutions. Moreover, its dependence on gate bias can often lead to numerical
instability. So, instead we employ an analytical theory to give a simple yet physical
expression for VTS independent of VGfS and VGbs.
Following [Lim83], assuming inversioncharge sheets for the moment, we
write the following equations:
(5.1)
197
operation, while it seems effective enough in DC. Here the parasitics associated with
the body tie will be characterized based on measured and simulated data.
The characterization technique for body resistance can be done from the
breakdown characteristics [Suh94a] or the transient measurement [Sle98], However, we
provide a simpler methodology based on DC bipolar measurement. The layout of an actual
Hgate NFD pMOSFET used for this study is shown in Fig. B.l. This device has 9.96pm
channel length, 2.5nm gate oxide, 200nm back oxide, and 100nm silicon film, and was
fabricated for 0.21pm target length. A large device (10 pm x 9.96pm) is chosen for this
study to separate out the body resistance from other parasitics associated with the junction
recombination/generation current underneath the Hgate sidejunction (Ws), as indicated
in Fig. B.l.
The test device was measured in a BJT configuration: VGf = 1 V, VD(VC) =
0 V, VB = 0 V, sweep Vs (VE). The measured Gummel plot is shown in Fig. B.2. As
can be seen in this figure, the currents start to degrade in the higherinjection region
where the body resistance becomes predominant as
VBE(eff) = VBE
= vbeIbrb
(6.1)
This characteristic gives the importance of RB, and hence we can further calibrate its
body sheet resistivity, pB. According to the lumpedRB model and the layout in Fig.
B.l, the total RB can be calculated as
(6.2)
208
[Dor92] M. J. van Dort, P. H. Woerlee, A. J. Walker, C. A. H. Juffermans, and H.
Lifka, Influence of High Substrate Doping Levels on the Threshold Voltage
and the Mobility of DeepSubmicrometer MOSFETs, IEEE Trans.
Electron Devices, vol. 39, pp. 932938, April 1992.
[Dor94] M. J. Van Dort, P. H. Woerlee and A. J. Walker, A Simple Model for
Quantization Effects in HeavilyDoped Silicon MOSFETs at Inversion
Conditions, SolidState Electronics, vol. 37, pp. 411414, March 1994.
[Ern99] T. Ernst, D. Munteanu, S. Cristoloveanu, T. Ouisse, N. Hefyene, S.
Horiguchi, Y. Ono, Y. Takahashi, K. Murase, Ultimately Thin SOI
MOSFETs: Special Characteristics and Mechanisms, Proc. IEEE Intemat.
SOI Conf., pp. 9293, October 1999.
[Fos97a] J. G. Fossum, D. Chang, S. Krishnan, D. Suh, G. O. Workman, and P.
C. Yeh., SOISPICE4 IVer. 4.41 Users Guide. University of Florida,
Gainesville, January 1997.
[Fos97b] J. G. Fossum, SOISPICE4 (Ver. 4.41s) Users Guide. University of
Florida, Gainesville, December 1997.
[Fos98a] J. G. Fossum and Y. Chong, Simulationbased assessment of 50nm
doublegate CMOS performance, Proc. IEEE Intemat. SOI Conf., pp.
107108, October 1998.
[Fos98b] J. G. Fossum, SOISPICE4 tVer. 4.5) Users Guide. University of
Florida, Gainesville, Novemberl998.
[Fos99] J. G. Fossum, UFSQI5.0 Users Guide. University of Florida,
Gainesville (http://www.soi.tec.ufl.edu/), December 1999.
[FosOO] J. G. Fossum, Z. Ren, K. Kim, and M. Lundstrom, Extraordinarily
High Drive Currents in Asymmetrical DoubleGate MOSFETs,
Silicon Nano Workshop, pp. 1819, June 2000.
[Fra92] D. J. Frank, S. E. Laux, and M. V. Fischetti, Monte Carlo simulation
of 30 nm dualgate MOSFET: How short can Si go?, Tech. Digest
1992 Intemat. Electron Devices Meeting, pp. 553556, 1992.
[FunOO] S. K. H. Fung, L. Wagner, M. Sherony, N. Zamdmer, J. Sleight, M.
Michel, E. Leobandung, S. H. Lo, T. C. Chen, and F. Assaderaghi, A
PartiallyDepleted SOI Compact Model Formulation and Parameter
Extraction, Symp. VLSI Tech. Dig., pp. 206207, 2000.
[Gam97] F. Gamiz, J. B. Roldan, J. A. LopezVillanueva and J. E. Carceller, Monte
Carlo Simulation of Electron Mobility in Double Gate SOIMOSFETs,
Proc. Eighth Intemat. Symp. on SOI technology and Devices, vol. 9723, pp.
233238, September 1997.
[Gam98] F. Gamiz, J. A. Lopez.Villanueva, J. B. Roldan, J. E. Carceller, and P.
Cartujo, Monte Carlo Simulation of Electron Transport Properties in
Extremely Thin SOI MOSFETs, IEEE Trans. Electron Devices, vol. 45,
pp. 11221126, May 1998.
60
VDS (V)
(b)
Figure 3.6 IDS VDS characteristics of 1.0 im NFD/SOI devices (Stage 6).
(a) nMOS. (b) pMOS.
16
Channel Current
For channel current calculation, we need to relate the channel charge, AQcf,
to A\]/sf directly, and hence we can enable the channel charge integration from source
to drain to define Icb [Vee88b]. The NFD and FD models are discussed individually
with the same methodology as follows.
First, for the NFD SOI model, \/sb = VBS { f(y)}; hence from (2.11)
d(AQcf) = Cofd(AVgf) + (Cof + Cb)d(AÂ¥sf) (2.24)
without dA\/sb. To obtain a direct connection between dAQcf and dA\/sf from (2.24),
we can relate dA\/gf to dAv/sf from (2.6). However, no closedform solution can be
found from this nonlinear differential equation. We thus simply use a representative
\/gf evaluated at the source for the charge derivative, and then a linear equation from
(2.6) can be attained:
C0fdA\/sf + CofdAygf = CdgfdA\/gf
(2.25)
where Cdgf is computed and approximated as
l 1
d(AQgf)
r Â£sqNp i
2 /esqNpA
d(A\/gf)
L2(\/gf + At/gf)J
l 2Â¥gf J
(2.26)
Substituting dAt)/gf from (2.25) into (2.24) yields an expression for the channel
charge, dQcf, in terms of the modulated surface potential d\/sf, as
dQCf = d(AQcf) = Cof(l+a)d(AÂ¥sf) = Cof(l+a')dVsf
(2.27)
139
jg
E*b = E;to[l + exp^JJ, (5.21)
VT
with E+ = being a lower limit for the smoothing functions in (5.20) and (5.21).
hi
Qif and Qib are inversion charge densities associated with the front and back gates,
respectively. In (5.17), E'sb is only important when the back channel is strongly
inverted, and is thus smoothed to zero via (5.19) when Esb becomes positive.
Conversely, E+sb is only significant when Esb is positive, and is thus smoothed to
zero via (5.21) when the back channel is inverted. In other words, either the second
or fourth term on the righthand side of (5.15) will be dominant when the back
channel is strongly or weakly inverted, respectively. The first and third terms are
treated similarly for the front channel. Though a usual front channel is assumed, for
numerical reasons we need to account for the case of negative Esf, as reflected by
(5.15), (5.16), (5.18), and (5.20), to give an equitable treatment for both channels.
Because, for perfectly symmetrical gates, VGbs could be slightly higher than VGfs
during the NewtonRaphson nodal analysis (e.g., in Spice), thereby making the back
channel predominant, this equitable treatment is necessary for numerical stability.
Now, \/sf, \/sb, Esf, and Esb can be derived from (5.11), (5.12), (5.14), and
(5.15) via a NewtonRaphson iteration method that is acceptable for physical,
processbased compact modeling. We can accelerate this calculation by solving for
only two unknowns, \/sf and V(/sb from (5.14) and (5.15) with Esf and Esb replaced via
(5.11) and (5.12), respectively. We hence get from (5.14)
C0f(VGfs V FB Vsf) <'ob(VGbS V FB ~ Vsb)
85
Stage 3
Evaluated Parameters
Measurement Data
Device
UO, THETA
IDS vs. VGfS @ low VDS (50 mV)
LongL
Similar to Stage 5 of the NFDmodel parameter tuning, UO and THETA can
be tuned directly from the Ios^GfS characteristic at low VDS, as indicated in Fig.
3.16. However, this stage should be linked to the RD/RS evaluation in Stage 5, at
least in this example, since the 0.5 lm device is not totally immune from RD/RS
influence. For a longerL device, e.g., L = 1 xm, UO and THETA could be tuned
independent of RD/RS. In conjunction with Stage 5, we obtain UO = 700 cm2/V/s
and THETA = 0.75 x 10'6 cm/V for nMOS, and UO = 200 cm2/V/s and THETA = 1.6
x 10'6 cm/V for pMOS.
3.3.3 ShortL Calibration
Now the tuning process continues with the shortL (target) device, beginning
with the parameter set obtained from the longL device tuning. In fact, if longL
device data are not available, the calibration could be done with only the shortL
device data, albeit with a bit more complexity. As noted in the shortL calibration of
the NFD model, selfheating is usually more prevalent in shortL device data, and
must be carefully avoided to ensure the integrity of the parameter evaluation. (The
UFSOI models do have a selfheating option [Fos98b], which uses two additional
parameters (RTH and CTH) that could be tuned). The remaining parameters to be
evaluated from the shortL device data are DL, KAPPA, RD, RS, and VSAT. We
choose the target device with L = 0.25 (im for the shortL calibration.
69
(a) IDS VGfS characteristics; L = 0.35 (d) IDS VGfS characteristics; L= 1.0 pin
Figure 3.11 Calibrated 1(A) V(V) characteristics of NFD/SOI nMOS devices.
79
parameters listed in Table 3.4 are either unimportant or inapplicable for this
technology. For example, NQFF is typically low enough that it is not significant in
a scaled technology, and NQFB is generally not critical relative to the charge defined
by NSB. NQFSW can be set to 0 generally, unless narrowwidth effects on threshold
voltage are important, in which case measured data from a narrowW device is
needed for evaluation. We suggest that the impactionization parameters, ALPHA
and BETA, be set to their default (physical) values of 2.45xl06 /cm and 1.92xl06 V/
cm, respectively, for nMOS [Slo87], [Kri96b], and adequately adjusted for pMOS.
Also, SEFF could be tuned roughly to the BJTinduced drainsource breakdown
voltage for highvoltage applications.
For the MIT Lincoln Lab technology, with dualpolysilicon gates (n+ poly
for nMOS and p+ poly for pMOS), the parameters listed in Table 3.6 are evaluated
Table 3.6 Model Parameters Evaluated Directly from Technology Information
Parameter
Value
TOXF
8.0 nm
TOXB
185 jim
TB
50 nm
TPG
+1
TPS
L+l
W (drawn)
7 im
L (drawn)
0.5 and 0.25 Jim
directly, for both nMOS and pMOS devices. Now, only 14 key parameters, which are
initially estimated as noted, need to be tuned: NSB, NBODY, TB (if necessary), QM,
& V
193
(a)
(b)
Figure A.2 Modelpredicted VDS(eff) and Le versus VDS.
Simulated (a) VDS(eff) and (b) Le of an NFD/SOI nMOSFET (L = 0.35 im).
126
some utility for asymmetrical DG MOSFETs that have only one predominant strong
inversion channel [Fos98a], However, symmetrical DG MOSFETs, or even near
symmetrical DG devices, require a more comprehensive stronginversion model. We
develop herein a generic compact model for the DG MOSFET (UFDG, the University
of Florida DG model), beginning with the processbased UFSOI/FD model and
extending it to account for stronginversion charge distribution throughout the thin
Si film. We describe the channelcurrent modeling, including scaleddevice effects,
and the associated terminalcharge modeling, as well as verification and application
of UFDG in Spice3 for CMOS design.
5.2 UFDG Development
5.2.1 Regional Modeling
The operation of DG MOSFETs can be physically characterized in weakand
stronginversion regions of operation via analyses that are applicable to compact
modeling. However, moderate inversion is not amenable to such modeling. Based on
the underlying physics in each region, the regional modeling approach can be
considerably simplified with proper assumptions. We use this approach for UFDG
development, as illustrated in Fig. 5.1, with physically defined threshold boundaries
VTW ar)d VTS, which will be described later. The weak and stronginversion
formalisms are defined directly, whereas a spline numerical interpolation is applied
for moderate inversion [Fos99].
Two boundaries, VTW (lower limit of moderate inversion) and VTS (upper
limit of moderate inversion), are defined in the UFSOI/FD model to achieve the
192
Figure A.l Flow chart of VDSX model implementation.
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53
the low capacitance in the accumulation region, but not as much as CGFDO and
CGFSO.
Stage 4
Evaluated Parameters
Measurement Data
Device
JRO, TAUO, M, BGIDL, NTR
ALPHA, BETA (pMOS)
IDs vs ^Gfs high Yds (20 V)
LongL
If GIDL is not prevalent, JRO and M can be evaluated from the draininduced
shift in current (without kink) and the slope (with kink), respectively, of the Ios^GfS
characteristic at high VDS, as demonstrated in Fig. 3.4. The shift in current is due in
part to DIBL, modeled internally, but mainly it is due to the floatingbody effect, i.e.,
the induced VBS > 0 caused by injection (e.g., generation) of majority carriers into
the body. The DC VBS is defined by the balance of the carrier generation from the
bodydrain junction and recombination from the bodysource junction as well as the
quasineutral source. The recombination current is modeled as [Kri96a]
2
IR(VBS, = WJROexp(^) + WTF^SEFFexp^) (3.2)
where the first term tends to be predominant in this context. Thus, if the generation
current (due to impact ionization here) is characterized well, M and JRO can be
evaluated from the highVDS subthreshold Ios'^GtS characteristic. However, the
generation current can have more than one component, and hence the general
evaluation will usually involve other parameters associated with it as well. In fact,
GIDL can influence the offstate leakage current near the kink. We hence include
103
DC value (0.15 V). Consequently, grossly underestimated retention time was
predicted due to the parasitic BJT current [Suh96]. (Such error possibly occurred in
the numerical device simulations of [Man96] as well, which similarly predicted an
abnormally high value of VBS after many bitline pulses.)
However, using insight from the above discussion of the floatingbody
effects, we see that we can emulate the (worstcase) accessmode operation,
irrespective of the actual bitline pulsing, by simply simulating the longtime transient
of the bitline voltage dropping from DC VDD = 1.5 V to 0 V (with fall time of 1 ns)
as indicated in Fig. 4.1; the wordline voltage is fixed at 0V. In this case, the induced
VBS(t) drives a continuous transient (drain) leakage current, discharging Cs, and the
integrated charge removed from Cs over long time will be virtually the same as that
removed for arbitrary bitline pulsing, starting from the DC Vs = VDD condition.
Results of this simulation (at room temperature) are shown in Figs. 4.2 and
4.3. The induced transient leakage current comprises four possible components:
IBJT(t) driven directly by VBS(t), IGH(t) due to the transient reduction in threshold
voltage defined by VBS(t), a displacement current in dQD/dt due to VBD(t), and the
ordinary thermalgeneration leakage current, IGt, from the drain junction. (Note that
GIDL, which typically is significant only when VDS is high and VGfs is negative, is
usually not important in the DRAM cell transistor.) The displacement current is
substantial only during the bitline pulse, and furthermore flows in opposite directions
during successive pulses in normal operation; hence its effect on retention time is
virtually nil. The other three current components derived from the simulation are
plotted in Fig. 4.2 over 10 s, along with VBs(t). The peak BJT current is about 1.5
117
a bandgap reduction of about 100 meV [Yos97] as before, commensurately increased
the appropriate components of source/drainbody recombination current and charge
storage in the NFD model, and repeated the circuit simulation of Fig. 4.6. The
instabilities still occurred; VBS(t) was only slightly decreased, and the N1N2 VT
imbalance prevailed. The lack of benefit afforded by the SiGe source/drain in this
case is understandable. Its effect (=exp(qVBS/kBT)) on recombination and charge
storage is significant only for relatively high VBS (>0.6 V). In the sense amplifier,
VBS(t) is low as evidenced in Fig. 4.6, and is hence governed predominantly by
junction spacechargeregion recombination and (depletion) charge/capacitance,
which are not strongly affected by the SiGe source.
Periodic Precharging
As noted in the previous section, the fatal VT imbalance could be effectively
removed by an abnormally long precharge, but such a precharge is impractical. Its
simulation shows however that the instabilities could be avoided by periodic
precharging, done even without sensing when the amplifier is idle. Our simulations
imply that the minimum frequency of precharge needed is about 104 times per
second. The circuit design to effect such a precharging rate seems problematic
though. Likewise, a synchronous DRAM design, which does not allow extended
periods with unbalanced bitlines, could be a resolution.
Body Ties
As illustrated in Fig. 4.6(a), body ties, at least those yielding negligible body
resistance, eliminate the floatingbody instabilities. However, because of the finite
131
?2 7\2
^\/(x,y)+^\j/(x,y) = ^NA, (5.5)
5x2 3y2 8s
based on the depletion approximation. With boundary conditions properly defined at
the SiSi02 interfaces and metallurgical junctions, an analytical solution of (5.5) can
be obtained by assuming a secondorder polynomial function for the electric
potential \)/(x, y). Also, the shortchannel effects, such as DIBL and Ldependent
subthreshold slope, can be implicitly predicted from the 2D weakinversion analysis,
though they are shown to be less significant in DG MOSFETs [KimOl]. Front and
back surface states, which tend to lower the subthreshold slope, are accounted for in
the weakinversion formalism as well. The complementary quasi2D analysis in the
original model [Yeh95] for the fringing electric field in the underlying back oxide is
now ignored, as the back oxide is highly scaled for the DG MOSFET.
The derived potential is then used to model the subthreshold current, which
is assumed to be predominantly diffusion along a modulated channel length, by
integrating the current density over the entire Si film. The total weakinversion
current Iwk can be expressed as the sum of front and backchannel components
[Yeh95]:
*WK ^WKf^Mnefftf)Qnf) + ^WKb^Mneffib)Qnb)
where Qnf and Qnb are the channel charges, and p.neff(f) and ineff(b) are the electron
mobilities. Recently, some upgrades, which include the removal of a current
discontinuity and the avoidance of a negative mobility in the weakinversion
205
(strong inversion).
(C.4)
^Gfs 2Qch(l + a)CofVDS
For moderate inversion, the spline numerical interpolation, as used for channel
current, is applied to the derivative as well. Next, we approximate the derivatives of
frontgate charge:
(C.5)
(weak inversion),
= CofWL (strong inversion).
^GfS
(C.6)
For moderate inversion, a linear interpolation is used for simplicity. The derivatives
of all other current and charge components are done similarly. Note that the
derivatives must be continuous over all the regions of operation to ensure the model
stability for convergence.
The analytical derivatives were implemented with respect to VGfS, VDS,
VBS, and VGbS. However, this analytical approach is restricted for VBS derivatives
due to FB effects, which tend to worsen the truncation error associated with
inaccurate derivatives and tolerances, especially for longtime hysteresis
simulations. Hence, the VBS derivatives are removed from the model. Note that
future model upgrades will require updated derivatives as well.
C.2 Results
With the analytical derivatives, for each Spice iteration, the model routine is
now only calculated twice for operation point and VBS derivatives. The runtime
PAGE 1
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calibrated to an actual PD SOI DRAM technology, addresses the performance of the
peripheral circuitry, e.g., the sense amplifier, as well as the dynamic retention of the
data storage cell. Design insight for lowvoltage highdensity SOI DRAM is attained.
Doable cell design is shown to yield dynamic retention time long enough for gigabit
memories, and crude bodysource ties for nMOS, with pMOS bodies floating, are
shown to effectively suppress instabilities in the sense amplifier. Therefore,
alternative bodytied structures will be applicable to this solution. Besides the body
ties suggested in this work, a novel bodytiedtobody (BTB) SOI CMOS inverter
configuration is suggested in Appendix B. This new approach is shown to suppress
the historydependent FB effects (hysteresis) of SOI CMOS circuits without
sacrificing the performance of SOI. However, due to the hysteresis, comprehensive
and intensive simulations are usually necessary, and hence the simulation time could
be considerable. To reduce the run time for simulationbased studies of the
hysteresis, analytical derivatives needed for the NewtonRaphsonbased nodal
analysis in circuit simulation are incorporated in UFSOI, as described in Appendix C.
Although SOI CMOS performance is superior to that of the bulksilicon
counterpart, it does not provide better device scalability as MOSFETs continue to
shrink. A revolutionary approach to continuously exploit the advantages of SOI and
to achieve higher performance for sub0.1 Jim design without the worrisome FB
effects is aimed at technologies like extremely scaled DG CMOS [Fra92] evolved
from FD/SOI. In order to extend the capability of UFSOI/FD for general DG
application, a new processbased compact model for DG MOSFETs having only
physical and structural parameters is developed and is presented in Chapter 5.
159
model, is satisfied. We divide the discussion for the modeling methodology into two
parts: triode and saturation regions, even though they will be eventually merged for
a continuous model.
In the triode region, we can calculate QGf as
Qg = wCofJo(vGfs*GfsVsf(y))dy
= WLCof[(VGfs4.GfsV,f(0))i^AVsf(y)dy]. (5.48)
Rearranging (5.36) and neglecting the diffusion current, we obtain
, fwQc(y) i
dy = 4eff {~r~ +
ch ^Vsat(eff)
dÂ¥sf
= i^(<3c()+ AvSf(y)(cor+cob) + 2V";,w)dAv.f <549>
^Vsat(eff)^
W^eff(Qc()Qc(L)) (J.effV DS
Where l* = 21 (C +C vuo (dfferent than with s = 2v i? and
ZL(L'of + 1 + zvsat(eff)L
Qc(0) is given by (5.23). Replacing dy in the integral of (5.48) with (5.49) for
integration with respect to dAv/sf yields
j^Av/Sf(y)dy = l^ +
VDs(Cof + Cob)(l+s)
6[2Qc(0) + (Cof + Cob)VDS]
(5.50)
Substituting (5.50) in (5.48) yields
QGf = WLC
of
VGfS
VDs(C0f + Cob)(l+S)
2 6[2Qc(0) + (Cof + Cob)VDS]
(5.51)
Similarly,
50
vares inversely with NBL. We obtain NBL = 3.1 x 1017 cm'3 for nMOS and 2.5 x
1017 cm'3 for pMOS, which are also consistent with the technology. The technology
does not have steep retrograded channels; we therefore assume, based on typical
channel doping profiles, that NBH is about a factor of two higher than NBL. As we
discuss later, the value of NBH can be updated based on the gate CV characteristic.
Stage 3 (optional with TOXF set to electrical gateoxide thickness)
Evaluated Parameters
Measurement Data
Device
QM, NGATE
(CGFSO, CGFDO)
CGfS vs ^GfS lw ^DS (~0 V)
LongL
(ShortL MOSC)
Calibration as well as verification via CV characteristics are essential for
reliable transient as well as AC simulations. We exemplify the CV calibration here
to lay the foundation for tuning the polydepletion and quantization parameters of the
UFSOI model, in addition to evaluating the gatesource and gatedrain overlap
capacitances, CGFSO and CGFDO (from a shortL gate MOSC).
From the frontgate (source/drain) CV characteristic of the floatingbody
device, QM and NGATE can be tuned based on the estimation of capacitance
lowering in strong inversion, respectively, as depicted in Fig. 3.3. Physically, both
polygate depletion and energy quantization affect current and capacitances
predominantly in strong inversion. Energy quantization can be important even near
threshold, and hence tends to lower the subthreshold current and increase the
threshold voltage. Consequently, the calibration of subthreshold current
demonstrated in Stage 2 might need refinement, depending on the significance of the
quantization. In this example, the gate CV characteristics are derived from AC
163
sat fL y (L2Le2)
Qoth) = wiIiQc(y)dysW^r5Qc(Le)
(5.65)
and
Qsjch) = QSQdiU) (566)
These charges calculated for saturation are still not sufficient to meet the
charge neutrality because some additional drain charge (QsatD(D)) associated with the
quasi2D highfield region is not yet accounted for, as illustrated by the shadowed
region in Fig. 5.10. However, based on our analysis, this portion of QD is negligible.
All of the evaluated charges for saturation are added to their respective
terminals as follows:
Qg = Qf(LeVDS(eff)) + Qf
(5.67)
Qb = QGb(Le VDS(eff)) + Qb >
(5.68)
Q(ch) = Q(ch)(LeVDS(eff)) + QD(ch)
(5.69)
Qs(ch) = Qs(ch)(LeVDS(eff)) + Qs(ch)
(5.70)
Again, as discussed in the previous section for Ich, we smooth VDS
and L to VDS(eff)
and Le, respectively, thus defining a fully continuous charge model.
For the model implementation in UFDG/Spice3, we use the charge neutrality
to define QGb as
162
Qof = WC0/ (V0fsO0fsVsf(y))dy
JLC
= WCof^(L Le)(VGfS 0GfS \j/sf(0) VDS(eff))
"jL (A\/sf(y)VDS(eff))dyJ.
(5.61)
Plugging (5.45) into (5.61) yields
.sat
QGf ~ WCof (L Le)(VGfS d>GfS Â¥sf(0) VDS(eff))
^vsat(eff)^c
Heff
(5.62)
Similarly,
.sat
Qb W('Ob(LLe)(VGbSOGfS\^sb(0) VDS(eff))
,2
^Vsat(eff)^c
Meff
cosh
fLU
V L
 1
(5.63)
Since the carrier velocity is saturated in the highfield region, based on the
current continuity, the charge density will be nearly uniform along y, and we can
obtain a simple integration for channel charge as
Q:ah = wf Qc(y)dy = W(L Le)Qc(Le) (5.64)
JLe
where Qc(Le) = Qc(0) + (Cof + Cob)VDS(eff). Analogous to the partition scheme for
the triode region, as shown in (5.57), we get
CHAPTER 2
MODELING POLYSILICON DEPLETION AND ENERGY QUANTIZATION
2.1 Introduction
The UFSOI FD [Yeh95] and NFD [Suh95a] MOSFET models are physical
and processbased, enabling the prediction of the potential performance of SOI
CMOS circuits. However, as MOSFETs continue to shrink, more and more
previously ignored physical phenomena become significant, and hence the original
models become inadequate for simulation of extremely scaled SOI MOSFETs.
Frequent model revisions and upgrades accounting for the new fundamental and
technological issues are essential for an effective compact model. This chapter
presents the main upgrades of the UFSOI models done in this research.
Polysilicongate depletion and carrierenergy quantization, both due to high
transverse electric field in scaled MOSFEETs, are incorporated in the UFSOI models
as upgrades in order to assure reliable simulation of advanced SOI CMOS devices
and circuits. Although these effects are also common for conventional bulkSi
MOSFETs, the physical modeling of them is somewhat different for SOI MOSFETs
due to charge coupling and floatingbody effects. For each phenomenon, the new
modeling is presented, and impacts on circuit performance are revealed via
simulations. In addition to these model upgrades, a refinement that ensures a smooth
transition from the linear to the saturation region of MOSFET operation is developed
7
115
coupling in N1 is weaker, due to the low QB, and hence VBS(N1) decreases
substantively as Vs is brought up. The subsequent dynamic VBS(N2) > VBS(N1)
imbalance is maintained when the amplifier is enabled at t = 56ns; VDS(N0) drops to
0, thereby increasing both VBS(N2) and VBS(N1) via the gatebodysource capacitive
coupling, and the resulting VBS(t)s define unbalanced VT(t)s. This dynamic
Vt(N2) < Vt(N1) imbalance is large enough to prevent a valid read0 operation, as
can be seen in Fig. 4.6; the coupled pairs in the sense amplifier flip improperly, and
an erroneous 1 is sensed and recorded. The floating bodyinduced instability is
emphasized in Fig. 4.6 by the corresponding errorfree results obtained by simulating
the circuit with all transistor bodies ideally tied, i.e., all nMOS bodies shorted to
ground and all pMOS bodies shorted to VDD.
Subsequent sense operations are included in the simulations of Fig. 4.6. After
a precharge starting at t = 85ns, a read1 from an adjacent cell on the bitline (not
shown in Fig. 4.4) is done successfully; the VT(N2) < VT(N1) imbalance is
inconsequential for this operation. However, later when the read0 is attempted
again, the instability recurs. Indeed the instability will remain until the dynamic QB
imbalance of N1 and N2 is removed by carrier generation in N1 (during precharge
periods), which, if not done intentionally, will take a long time. In fact, a simulation
of the circuit starting with nearDC precharge conditions, and hence nearly equal
Qb(N1) and QB(N2), shows no instabilities.
We have presumed that the fatal hysteretic VT imbalance between N1 and N2
must be initiated by an extended period with unequal VGfs(Nl) and VGfS(N2). A
simulation of such a period, following a read0 from a steadystate precharge
165
Qb (Qf + Qb+ Qs+ Qd + Qff + Qfb+ Qb) (5.7i)
which is consistent with QGb as previously described; (5.71) is used in the model
routine merely for computational efficiency.
5.2.4 ModerateInversion Formalism
The channel current and terminal charges (QGf, Qs> Qd) in the moderate
inversion region are computed by spline numerical interpolations [Cha87], which
link the stronginversion analysis to the refined weakinversion analysis. The current
and charges, and their derivatives which are calculated by difference
approximations, evaluated at VTS and VTW are needed for the splines. For example,
the spline used to define the channel current in moderate inversion is expressed as
ln(Ich) = a0 + al(^GfS ^Tw) + a2(^GfS ~ ^Tw) + a3^GfS ^Tw) (572)
where the a coefficients are defined by (VTS VTW), ln(Ich), and dln(Ich)/dVGfs
evaluated at the boundaries. Though the BSIM3 numerical interpolation is used for
charges in the UFSOI models [Cha97], it is now replaced by the spline interpolation
since the BSIM3 approach tends to fail when VTS and VTW are close to each other,
as in the UFDG model.
5.3 Model Demonstration and Verification
The UFDG model needs to be corroborated and compared with numerically
simulated and measured data to assure its validity. An example of model calibration
using processbased parameter evaluation will be first given. For verification, model
144
(a)
x1013
(b)
Figure 5.6 Model and MEDICIpredicted (normalized) inversion charge.
Simulated inversion charge for symmetrical and asymmetricalgate DG
nMOSFETs at low VDS on (a) log and (b) linear scales.
209
[GamOl]
F. Gamiz, J. B. Roldan, J. A. LopezVillanueva, and P. Cartujo
Cassinello, J. E. Carceller, and P. Cartujo, Monte Carlo simulation of
electron transport in silicononinsulator devices, Proc. Tenth
Internat. Symp. SOI Technology and Devices, March 2001.
[Gar87]
S. L. Garverick and C. G. Sodini, A Simple Model for Scaled MOS
Transistors That Includes FieldDependent Mobility, IEEE J. Solid
State Circuits, vol. 22, p. Ill, February 1987.
[GeOO]
L. Ge and J. G. Fossum, Proc. IEEE Internat. SOI Conf., pp. 114115,
October 2000.
[GeOl]
L. Ge, J. G. Fossum, and B. Liu, Physical compact modeling and
analysis of velocity overshoot in extremely scaled CMOS devices and
circuits, IEEE Trans. Electron Devices, vol. 48, 2001.
[Har97]
S. A. Hareland, S. Jallepalli, G. L. Chindalore, W.K. Shih, A. F. Tasch,
Jr., and C. M. Maziar,, A Simple Model for Quantum Mechanical Effects
in Hole Inversion Layers in Silicon PMOS Devices, IEEE Trans. Electron
Devices, vol. 44, pp. 11721173, July 1997.
[Har98a]
S. A. Hareland, S. Jallepalli, W.K. Shih, H. Wang, G. L. Chindalore, A. F.
Tasch, and C. M. Maziar, A PhysicallyBased Model for Quantization
Effects in Hole Inversion Layers, IEEE Trans. Electron Devices, vol. 45,
pp. 179186, January 1998.
[Har98b]
S. A. Hareland, M. Manassian, W.K. Shih, S. Jallepalli, H. Wang, G.
L. Chindalore, A. F. Tasch, and C. M. Maziar, Computationally
Efficient Models for Quantization Effects in MOS Electron and Hole
Accumulation Layers, IEEE Trans. Electron Devices, vol. 45, pp.
14831493,July 1998
[His91]
D. Hisamoto, T. Kaga, and E. Takeda, Impact of the Vertical SOI
DELTA Structure on Planar Device Technology, IEEE Trans.
Electron Devices, vol. 38, pp. 14191424, June 1991.
[Hou98]
T. Houston and S. Unnikrishnan, A Guide to Simulation of Hysteretic Gate
Delays Based on Physical Understanding, Proc. IEEE Internat. SOI Conf.,
pp. 121122, October 1998.
[Hwa91]
J. M. Hwang, H. Lu, Y. D. Sheu, W. Bailey, P. Mei, and G. Pollack,
Premature Breakdown in NonFully Depleted SOI/MOSFETs with Body
TiedtoSource Structure, Proc. IEEE Internat. SOI Conf, pp. 3435,
October 1991.
[IkeOO]
R. Ikeno, and M. Aoki, An Equivalent ElectricField Approximation for
Formulating Sheet Density of Induced Electrons in a Silicon Layer of
Symmetric and Asymmetric DoubleGate SOI MOSFETs, SolidState
Electronics, vol. 44, pp. 605611, April 2000.
[Jal96]
S. Jallepalli, J. Bude, W.K. Shih, M. R. Pinto, C. M. Maziar, and A. F.
Tasch, Jr., Effect of Quantization on the Electrical Characteristics of Deep
Submicron p and nMOSFETs, Symp. VLSI Tech. Dig., pp. 138139,
1996.
107
regeneration of body charge. Long enough quiescence would result in nearDC body
charge conditions; according to our simulations (with the wordline off), such
conditions obtain via IGt (from the source and drain junctions) after about 50 ms. If
Np is the number of times per second that such quiescence, followed by normal
(arbitrary) bitline pulsing, occurs, then the maximum retention time attainable is
defined by AVSN = 60 mV:
0.5V 8
ret(max) NpAVSN ~ Np
(4.1)
Hence if NP > 1 s'1, a dynamic data retention problem is implied (for the assumed
value of xg). Note that although shorter quiescent times would mean smaller AVSN
and hence higher limits for NP, (4.1) conveys the general problem stemming from
recurring bitline quiescence at VDD, or even VDD/2. To ensure that the problem,
albeit seemingly not common, is avoided, AVSN for arbitrary quiescence should be
minimized, which means VBS(t) should be restricted.
Several device engineering schemes have been suggested to ameliorate
floatingbody effects in SOI MOSFETs. A prevalent one is the SiGesource/drain
technology [Yos97] that is intended to enhance recombination and thereby restrict
Vbs by creating a bodysource heterojunction. According to [Yos97], the bandgap in
the source is reduced by the incorporation of Ge, allowing more hole injection, or
recombination, when VBS > 0. Note that the bandgap reduction will also enhance the
(bipolar) charge storage in the source region, and hence result in added diffusion
capacitance [Kri96a], which will affect the dynamic body charging as well.
202
Table B.l Performance Comparison of BTB and FB SOI CMOS Inverters
VDD (V)
Delay/Stage
(IC)
Delay/Stage
(Steady State)
Hysteresis
Static Power
(DC)
Dynamic
Power
1.2
(Floatingbody)
26.68 ps
24.49 ps
8.22%
0.04 lW
0.65 mW
1.0
(BTB)
w/ Rb=10 mq
27.27* ps
27.37* ps
0.37*%
0.29 (iW
0.45 mW
* Insensitive to RB<10 M2
VBSs to depart from their DC values during the transient switching. It also consumes
less dynamic power due to lower VDD, but consumes higher static power due to
junction leakage current. In addition, the circuit performance is insensitive to RB,
implying the flexible implementation of the body tie.
18
ChannelLength Modulation
We apply Gausss law for the VDSinduced incremental field and charge in a
subregion of length dy to obtain a differential equation for Aysf(y) [Suh95b]:
AQcf(y)dy = Â£sAEx(tb,y)dyeoxAEox(y)dy + Â£sdyr
b^AE dx. (2.31)
Substituting (2.8), (2.11) with y = Le, and Â£0XAE0X = Â£oxA\/sf/tox = Cof(A\/sf + Aygf)
into (2.31) and solving for Le, we get
(2.32)
where lc = Â£stb/(2Cof(l + a)), which is the same form as the old model but with
different VDS(eff). Note that Le is now smoothed, and VDS(eff) is replaced with VDSX
(in Appendix A).
Charge Modeling
First, we modify the charge formalism of the NFD model [Cha97] to account
for polysilicon depletion:
(2.33)
^cosh
) (234)
161
QD(ch) = W0Qc(y)dy
= WL(Cof + Cob)VDS
2(z l)3 4[z5(z l)5] uz
3(2z 1) 15(2z 1)2 2
(5.57)
Qs(ch) Qch ~ Q(ch) (5.58)
We finally define
Qb = WLqNAtSi, (5.59)
which is simply the body depletion charge. However, parasitic effects can add
dynamic components to QB, e.g., that associated with the parasitic BJT [Kri96a], The
bipolar charges (minority carriers) associated with source, drain, and body [Kri96a]
are added, respectively. Also, the fixed charge in the gate oxide, which may be
significant in newly developed DG technology, can affect the threshold voltage and
should not be ignored. Now, all the charges are well defined. Due to the physical
bases of the model, the charge neutrality,
Qf+ Qb + Qs + Qd + Qff+ Qfb + Qb = 0 (5.60)
is satisfied, even though such condition is not utilized to define any charge
component before.
In the saturation region, the charges defined previously will be still valid
with L replaced by Le and VDS replaced VDS(eff), and then they will be augmented
with the charges associated with the highfield region. With Le and VDS(eff) solved
previously for the channel current, we define
149
Tb > Tb =
l+f(tsi)
(5.28)
where f(tsi) gives the dependence on tsi, which will be described as follows.
According to results derived from a selfconsistent Schrodinger and Poisson
tool [Sho99], the EQL is reached via structural confinement for tSi < 5 nm. We
hence define tsi = 5 nm as an upper limit, below which the inverse tsidependence in
(5.24) is absolute. The phonondefined mobility degradation, apparent for low fields
(Ex <105 V/cm), becomes insignificant for tSi >15 nm [Cho95], [Gam98]. So we set
this thickness as a lower limit, above which the mobility is virtually independent of
tsi. To implement these limits, we define f(tsÂ¡) empirically:
f{,sl) = lOlnm) j
rSi
(5.29)
where
W = 10
log^l + exp^B^l Sl
10
log(l + exp(B))
V
(nm)
(5.30)
is a smoothed function of tSi. With the 10 (nm) in (5.30) being the mean between 5nm
and 15nm, and B (=3) chosen to properly control the stiffness of f in (5.29),
tSi' = 10 nm when tSi > 10 nm and tSi' = tSi when tSi < 10 nm. Therefore, for thick
films, Tb' = Tb from (5.28), implying no severe excess phonon scattering; i.e., the
lowfield mobility will be independent of film thickness. For extremely thin films,
however, xb will be determined directly by the film thickness from (5.28), and so will
96
VGfs (V)
(a)
VDS (V)
(b)
Figure 3.23 Calibrated conductances of FD/SOI pMOS device.
(a) Transconductance; L = 0.25 im.
(b) Output conductance; L = 0.25 im.
170
TB and NBODY to fit the current and slope of the Ios'^GfS characteristic at low VDS
without shortchannel effects. Though the (default) gate flatband voltages
(workfunctions) are not modified here, some additional tuning might be needed to
obtain a correct threshold, especially for nonpolysilicon gates. Note that NSF and
NSB should be evaluated if the surface states are prevalent, resulting in a lower
subthreshold slope. We also tune BGIDL (with BJT = 1) to fit GIDL current of the
IosVcfs characteristic at high VDS and VGfs > 0 (where GIDL is most significant
for pMOS), using an estimated DL from the technology. Further, from the strong
inversion region of the Ios'^GfS characteristic at low VDS, UO and THETA can be
tuned directly since RD and RS are not significant here for long L. The evaluated TB,
NBODY, and UO are consistent with the technology.
With the parameter set obtained from the longL device tuning, we continue
to tune DL, RD, RS, VSAT, and VO from the shortL device data. First, the channel
length reduction DL can be evaluated (refined) from its influence on the short
channel effects, e.g., DIBL. Because this shortL device for calibration is not short
enough to exhibit significant shortchannel effects, DL is estimated from the
magnitude of the subthreshold current. The evaluated DL is consistent with that
estimated by shiftandratio method. Next, RD and RS can be evaluated from the
linear region of the IDS VGfs characteristic at low VDS. Finally, we tune VSAT from
the Ids'^ds characteristic at high VGfs with VDS ~ VDS(sat), where the saturation is
governed by velocity saturation and not pinchoff. However, for scaled DG
MOSFETs, the velocity overshoot parameter VO should be tuned instead with a
given physical VSAT. The entire evaluation procedure is straightforward without
Ill
I am fortunate to have my wife, ChiaHui Lin, my son, Tony Chiang, and my
daughter, Shannon Chiang, here with me through the long years of graduate study.
Finally, I express heartfelt thanks to my father, LungChuan Chiang; and my mother,
MinTze Lu, for their endless love and support in many ways through the years.
Vsf. Vsb (V)
141
VGfS=VGbS (V)
Figure 5.4 Modelpredicted DG surface potentials.
The simulated front and backsurface potentials for asymmetric (n+/p+ poly) and
symmetric (n+/n+ poly) DG nMOSFETs with VGfs = VGbS at lw VDS. Note the
predominant front channel for the asymmetric device and the negative threshold
voltage for the symmetric device, which needs midgap gates to obtain a proper
threshold voltage.
14
where 0 is a mobility degradation factor, and Ex(y) = Ex0 + AEx(y). Ex0 is defined at
VDS = 0 as [Vee88b]:
Ex0 
Vsf^BS Qcf Q
b(eff)
2es 2es
(2.14)
where V/sf is pinned at ~2
Ae , cofAVsf(y) AQcf(y)
AEx(y) = T 2e~
(2.15)
Substituting (2.11) into (2.15), we rewrite AEx(y) as
'of*... ,__x tb1!
AEx(y) = Cb2e'AÂ¥sf(y) + 2iV/gf(y) ~ ~T'
(2.16)
By rearranging (2.13) with (2.14) and (2.16), we can express ieff as
M'eff = M'no/
1 + Q^sf ~ VBS Qcf Qb(eff)
v tb
2es 2es
+^rA^+Â§Hf(y)!r))'
(2.17)
Now, to see the A\/gf(y) dependence of mobility and also compare it to
A\/Sf(y), we may check the derivative of Aygf(y) with respect to A\/sf(y) via (2.7) as
= k (2.18)
VGfS = constant
Aygf(y)
AVsf(y)
where
147
Carrier Mobility
Unlike in conventional mobility models, unique physical mechanisms that
influence the fieldeffect mobility (ieff) in the thin Si film of the DG MOSFET must
be taken into account. The dependence of jLLeff on tsÂ¡ can be important for tsi less than
~25 nm [Gam97]. The increase in the phonon scattering rate as a consequence of the
greater confinement of carriers in thinner Si films substantially decreases the
mobility [Pri81], as predicted theoretically [Gam98], [Maj98] and corroborated
experimentally [Cho95], [Ern99].
Acoustic phonon scattering via the deformation potential is usually the most
important scattering mechanism in undoped silicon near room temperature [Li93].
Since DG MOSFETs will typically have lightly doped Sifilm channels, acoustic
phonon scattering can be prevalent. In the extreme quantumconfinement limit
(EQL), electrons predominantly occupy the lowest energy subband [Ste67]. We
assume that such condition is still valid for DG MOSFETs. Accordingly, the
scattering of thermal and even hot electrons is confined within this energy level, and
the deformationpotential scattering rate for acoustic phonons is inversely
proportional to film thickness [Rid82]:
1
x
b
3SkTm
2ll3cLtsi
(5.24)
where xb is the momentumrelaxation time, E is the deformation potential, and cL is the
elastic constant associated with acoustic vibration.
75
evaluated identically. Since the FD device is somewhat immune to floatingbody
effects, parameters associated with them are less important. However, the FD
channelcurrent formalism in weak inversion is more complex, accounting for 2D
fringing fields in the buried oxide (BOX) emanating from the source/drain junctions
[Yeh95], [Yeh96]; two additional parameters for this effect must be tuned. The Ver.
4.5 model parameters, along with their descriptions and typical values, are listed
inTable 3.4 [Fos98b],
Table 3.4 UFSOI4.5 FD MOSFET Model Parameters
Name
Description
Units
Default
Typical Values
NQFF
Front oxide fixed charge (normalized)
2
cm ^
0.0
~ 1010
NQFB
Back oxide fixed charge (normalized)
2
cm ^
0.0
~ 1011
NQFSW
Effective sidewall fixed charge
(normalized)
(0 for no narrowwidth effect)
_2
cm z
0.0
1012
NSF
Front surface state density
cm ^
0.0
~ 1010
NSB
Back surface state density
2
cm
0.0
~ 1011
TOXF
Frontgate oxide thickness
m
lO.xlO"9
(38)xl0"9
TOXB
Backgate oxide thickness
m
500.x 1 O'9
(80400)xl0'9
NSUB
Substrate doping density
3
cm
l.OxlO"15
10151017
NGATE
Polygate doping density
(0 for no polygate depletion)
3
cm
0.0
1019102
NBODY
Film (body) doping density
3
cm
5.0xl016
oo
1
r
O
NDS
Source/drain doping density
3
cm
5.0xl019
io19io20
TB
Film (body) thickness
m
100.x 1 O'9
(30100)xl0'9
QM
Energy Quantization Parameter
(0 for no quantization)

0.0
00.5
92
(b) IDs VGfS characteristics; L = 0.25 Jim (e) IDS VGfS characteristics; L = 0.5 im
2.5e03
0.0e+00,
0.0 0.5 1.0 1.5
(c) IDS VDS characteristics; L = 0.25 (xm
2.0e03 
1.5e03
1.0e03
5.0e04
0.0e+00
2.0 0.0
UTJUoUUOOOOOOOOOl)
GfS=l6V
xxxxxioooooooooooa >
0.5 1.0 1.5 2.0
(f) IDS VDS characteristics; L = 0.5 im
Figure 3.20 Calibrated 1(A) V(V) characteristics of FD/SOI nMOS devices.
211
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Technology and Devices, March 2001.
[Mca91] C. C. McAndrew, B. K. Bhattacharyya, and O. Wing, A singlePiece C 
Continuous MOSFET Model Including Subthreshold Conduction, IEEE
Electron Device Lett., vol. 12, pp.565567, October 1991.
[Med99] MEDICI 4.0: TwoDimensional Device Simulation Program.
Sunnyvale, CA: Avant! Corp. and TMA, Inc., 1999.
[Mor95] F. Morishita, K. Suma, M. Hirose, T. Tsuruda, Y. Yamaguchi, T.
Eimori, T. Oashi, K. Arimoto, Y. Inoue, and T. Nishimura, Leakage
Mechanism due to Floating Body and Countermeasure on Dynamic
Retention Mode of SOIDRAM, Symp. VLSI Tech. Dig., pp. 141142,
Kyoto, Japan, June 1995.
[Oas96] T. Oashi, T. Eimori, F. Morishita, T. Iwamatsu, Y. Yamaguchi, F.
Okuda, K. Shimomura, H. Shimano, N. Sakashita, K. Arimoto, Y.
Inoue, S. Komori, M. Inuishi, T. Nishimura, and H. Miyoshi, 16Mb
DRAM/SOI Technologies for SubIV Operation, IEEE IEDM Tech. Dig.,
pp. 609612, December 1996.
[Ohk90] Y. Ohkura, Quantum Effects in Si nMOS Inversion Layer at High
Substrate Concentration, SolidState Electronics, vol. 33, pp. 1581
1585, December 1990.
[Pri81] P. J. Price, TwoDimensional Electron Transport in Semiconductor
Layers. I: Phonon Scattering, Ann. of Phys, vol. 133, pp. 217239, May
1981.
[Pur98] R. Puri and C. T. Chuang, Histeresis Effect in PassTransistor Based
PartiallyDepleted SOI CMOS Circuits, Proc. IEEE Internat. SOI
Conf, pp. 103104, October 1998.
[Ric96] B. Ricco, R. Versari, and D. Esseni, Characterization of Polysilicon
Gate Depletion in MOS Structure, IEEE Electron Device Lett., vol. 17,
pp. 103105, March 1996.
[Rid82] K. B. Ridley, The ElectronPhonon Interaction in QuasiTwo Dimensional
Semiconductor QuantumWell Structures, J. Phys. C: Solid State Phys.,
vol. 15, pp. 58995917, 1982.
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Figure 5.9 Schematic diagram of a highfield region near the drain.
The carrier velocity in the highfield region is being saturated.
213
[Suh95a]
D. Suh and J. G. Fossum, A Physical ChargeBased Model for Non
Fully Depleted SOI MOSFETs and Its Use in Assessing Floating
Body Effects in SOI CMOS Circuits, IEEE Trans. Electron Devices,
vol. 42, pp. 728737, April 1995.
[Suh95b]
D. Suh, Modeling of NonFully Depleted SilicononInsulator
MOSFETs, and Applications to HighPerformance/Low Power ULSI
Design, Ph.D. Dissertation, University of Florida, Gainesville, 1995.
[Suh96]
D. Suh, J. G. Fossum, and M. M. Pelella, Dynamic Data Retention and
Implied Design Criteria for FloatingBody SOI DRAM, IEEE Electron
Device Lett., vol. 17, pp. 385387, August 1996.
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K. Suma, T. Tsuruda, H. Hidaka, T. Eimori, T. Oashi, Y. Yamaguchi,
T. Iwamatsu, M. Hirose, F. Morishita, K. Arimoto, K. Fujishima, Y.
Inoue, T. Nishimura, and T. Yoshihara, An SOIDRAM with Wide
Operating Voltage Range by CMOS/SIMOX Technology, IEEE J. Solid
State Circuits, vol. 29, pp. 13231329, November 1994.
[Sun80]
S. C. Sun and J. D. Plummer, Electron Mobility in Inversion and
Accumulation Layer on Thermally Oxidized Silicon Surfaces, IEEE
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[Suz95]
K. Suzuki, and T. Sugii, Analytical Models for n+p+ DoubleGate SOI
MOSFETs IEEE Trans. Electron Devices, vol. 42, pp. 19401948,
November 1995.
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K. Tamizawa, Numerical Simulation of Submicron Semiconductor
Devices, Artech House, 1993.
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Y. Taur, An Analytical Solution to a DoubleGate MOSFET with Undoped
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Current in 0.15im SOI DRAM, Proc. IEEE Intemat. SOI Conf., pp. 138
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S. Tomishima, F. Morishita, M. Tsukude, T. Yamagata, and K. Arimoto,
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A. Toriumi, J. Koga, H. Satake and A. Ohata, Performance and
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Y. Tsividis, Moderate Inversion in MOS Devices, SolidState Electronics,
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[Vee88a]
S. Veeraraghavan and J. G. Fossum, A Physical ShortChannel Model for
the ThinFilm SOI MOSFET Applicable to Device and Circuit CAD, IEEE
Trans. Electron Devices, vol. 35, pp. 18661875, November 1988.
145
VTS (=0.35 V) where (5.13) is still reasonable, as predicted in Fig. 5.4 as well. For
low VGS, where volume inversion does not obtain, the model is, not surprisingly,
inaccurate. Most importantly, the simulation results demonstrate the generic nature
of the UFDG model for different device structures. Note that if the threshold voltage of
the symmetricalgate device were increased (e.g., via nearmidgap gates) to equal that of
the asymmetrical device (equal Ioff\s), the respective Qcs in the two devices would be
nearly equal, as shown in Fig. 5.7, even though the later device has only one predominant
channel. Similar results have been predicted by MEDICI [Kim99], and ID Poisson
Schrodinger solver (SCHRED) [FosOO] as well. The reason for comparable currents
can be explained by extended charge coupling due to unequal gate workfunctions and
a reverse inversionlayer capacitance effect [KimOl],
For scaled MOSFET applications, effects of quantummechanical (QM)
confinement in the thin Si film, dependent on tsi as well as E, must be accounted for
in the model. This classical version of UFDG will provide the initial bases for a QM
iteration. A compact PoissonSchrodinger solver [GeOO] will use the potentials and
electric fields from this model as the initial solutions, and then solve for the eigenvalues
(quantized subband energies), eigenfunctions (electron distribution in x), and electric
potential selfconsistently and iteratively. FermiDirac statistics and effects of carrier
degeneracy will be included in the QM model with the 2D density of states of the
confined electrons. Finally, we will have an updated Qc based on the QM solution
via (5.23).
I certify that I have read this study and that in my opinion it conforms to
acceptable standards of scholarly presentation and is fully adequate, in scope and
quality, as a dissertation for the degree of Doctor of Philosophy.
Jerry G. Fossum, Chairman
Professor of Electrical and Computer
Engineering
I certify that I have read this study and that in my opinion it conforms to
acceptable standards of scholarly presentation and is fully adequate, in scope and
quality, as a dissertation for the degree of Doctor of Philosophy.
Gijs Bosman
Professor of Electrical and Computer
Engineering
I certify that I have read this study and that in my opinion it conforms to
acceptable standards of scholarly presentation and is fully adequate, in scope and
quality, as a dissertation for the degree of Doctor of Philosophy.
Sheng S. Li
Professor of Electrical and Computer
Engineering
I certify that I have read this study and that in my opinion it conforms to
acceptable standards of scholarly presentation and is fully adequate, in scope and
quality, as a dissertation for the degree of Doctor of Philosophy.
Kenneth K. O
Associate Professor of Electrical and
Computer Engineering
I certify that I have read this study and that in my opinion it conforms to
acceptable standards of scholarly presentation and is fully adequate, in scope and
quality, as a dissertation for the degree of Doctor of Philosophy.
Timothy J. Anderson
Professor of Chemical Engineering
56
device) can be first estimated using (3.3) and (3.4), and then tuned as described in
Stage 6. In the VGfS < 0 region of the highVDS IS'^GfS characteristic, we can tune
the junctiontunneling parameter, NTR, in conjunction with BGIDL to match the
leakage current if it is underpredicted by accounting for the thermal generation. A
few iterations on the values of these parameters may be necessary; BGIDL should be
iterated too if GIDL seems important near the subthreshold kink. (Because a
weighting factor is used in the characterization of the source/drain junction
recombination/generation currents to ensure symmetry, varying TAUO can cause a
slight variation in the longL model characteristic in the prekink region.)
As was mentioned previously, the impactionization rate for holes is much
smaller than that for electrons. Since there is no clear indication of the values of
ALPHA and BETA for holes in the literature, they should also be tuned for pMOS,
along with JRO, from the kink shown by the data in Fig. 3.4(b). If we increase BETA,
the onset voltage of the kink will be pushed out. (ALPHA and BETA can also be
checked later to match the kinks of IDS VDS characteristics, as plotted in Fig. 3.6.)
We obtain JRO = 1.0 x 1010 A/m, TAUO = 1.0 x 10'6 s, M = 1.5, BGIDL = 4.5 x 109
V'm1, and NTR = 4.5 x 1014 cm3 for nMOS (with ALPHA and BETA given
previously), and JRO = 1.0 x 1010 A/m, TAUO = 1.0 x 106 s, M = 1.5, BGIDL = 4.6
x 109 Vm1, ALPHA = 2.45 x 106 cm1, BETA = 3.0 x 106 V/cm, and NTR = 9.0 x
1014 cm3 for pMOS.
Note in Fig. 3.4 that the longL devices, especially nMOS, show anomalous
leakage current at high VDS near VGfs = 0. This current, which in fact varies
substantially in different devices from the technology, can influence the drain
APPENDIX A
MODELING AND IMPLEMENTATION OF THE CONTINUOUS DRAIN
SATURATION VOLTAGE IN UFSOI MODELS
Because the drain saturation voltage, VDS(eff), in UFSOI models was
inefficiently calculated by iteration, and also VDS(eff) is usually close to VDS(sat)
solved at the onset of saturation, an approximate modeling should be adequate to
replace the iteration. Further, the discontinuity of conductance between saturation
and triode regions due to the piecewiselinear velocity model needed to be fixed. The
implementation of these model upgrades in SOISPICE4.41 [Fos97b] is described in
this appendix.
A.l Removing the Vpstefn Iteration
The iteration for the VDS(eff) calculation in UFSOI models (NFDMOD.f and
SOIMOD.f) can be removed directly. However, the approximation of
VDS(eff) = VDS(sat)) is not very accurate for VDS >VDS(sat), especially for short
channel devices. We hence use one iteration to calculate a more accurate VDS(eff),
and the new model shows a good agreement with Ver. 4.4 [Fos97a] (with numerical
iteration).
In addition, the VDS(eff) modeling associated with channellength
modulation should be unified for the triode and saturation operations. For this
purpose, a smoothing function [Mca91]:
189
BIOGRAPHICAL SKETCH
MengHsueh Chiang was born in Chiayi, Taiwan in 1970. He received a B.S.
degree in electrical engineering from National ChengKung University, Tainan,
Taiwan, R.O.C., in 1992, and the M.S. degree in electrical and computer engineering
from University of Florida, Gainesville, FL, in 1995, where he is currently pursuing
the Ph.D. degree as a graduate research assistant.
During the summer of 1998, he worked as summer intern in charge of device
characterization and optimization for SOI CMOS technology at the Strategic
Technology Group, AMD, Sunnyvale, CA. His interests include the modeling of
semiconductor devices and their applications. He is currently engaged in the
development of physicsbased compact models for SOI and DG MOSFETs.
215
89
Figure 3.18 shows that RD and RS can be evaluated from the linear region of
the IDS VGfS characteristics. Since RS/RD could have been of some importance in
the longL device, UO and THETA should be finetuned here to sustain the
agreement with the longL data, unless the channel length is so long that RS/RD will
not cause any noticeable effect. Assuming RS = RD due to device symmetry, we tune
RS/RD to 200 x 10'6 Qm for nMOS and 900 x 106 Qm for pMOS.
Stage 6
Evaluated Parameter
Measurement Data
Device
VSAT
IDs vs Vds @ low power region
ShortL
As shown in Fig. 3.19, we tune VS AT from the Ids_^DS characteristics at
high VGfs with VDS ~ VDS(sat), where the saturation is governed by velocity
saturation and not pinchoff. Note that selfheating can and must be avoided; it is
apparent in the nMOS device at higher VDS where the DC power dissipation is larger.
We tune VSAT to be 0.65 x 107 cm/s for nMOS and 0.45 x 107 cm/s for pMOS.
3.3.4 Verification
Due to the thinner body of the FD/SOI MOSFET, which implies higher
thermal resistance, the selfheating phenomenon, discussed in Section 3.2.4, may be
more severe than in the NFD/SOI device. However, the characteristics showing the
final calibration of the FD model to the MIT Lincoln Lab CMOS technology, plotted
in Figs. 3.20 and 3.21, do not cover very highpower regions; only the measured
nMOS characteristics for VDS and VGfS near 2 V reflect any selfheating. The FD
model (without selfheating) calibration is very good, except where the nMOS
gate capacitance, are now important, and hence they are incorporated in the UFSOI
models to assure accuracy of scaled device and circuit simulations. The UFSOI
models are processbased, and hence their calibration must be done properly to
ensure their reliability. To obtain a set of unequivocal model parameters, reflecting
the process information and underlying physics of SOI MOSFETs, a processbased
modelcalibration methodology, which is simple and systematic, is developed and
demonstrated for both FD and NFD devices.
We further apply UFSOI to gain insight into the behavior of SOI MOSFETs
in integrated circuits via the physical nature of the model. A physicsbased study of
floatingbody (FB) effects on the operation of SOI DRAM is done. Design insight
regarding dynamic retention time and sensing is provided. However, due to the
historydependent FB effects in SOI CMOS circuits, comprehensive and intensive
simulations are usually necessary. Hence, approximate analytical derivatives, needed
for the NewtonRaphsonbased nodal analysis in circuit simulation, are incorporated
in UFSOI in order to reduce the run time for simulationbased study of the hysteresis.
Although SOI CMOS performance is superior to that of the bulksilicon
counterpart, its scalability is no better. A revolutionary approach to continuously
exploit advantages of SOI without the worrisome FB effects is aimed at technologies
like extremely scaled DG CMOS, which is evolved from FD/SOI. To extend the
capability of UFSOI/FD for general DG application, a new processbased UFDG
model is developed. The UFDG model is generic, enabling the evaluation of different
DG structures and technologies at the circuit level. The model is demonstrated in
comparisons of symmetrical and asymmetricalgate DG MOSFETs involving device
viii
and circuit simulations.
23
mainly due to the high electric field at the Si/Si02 interface, which results from
highly doped channel and extremely thin gate oxide (tof). In the very high transverse
field channel region (inversion layer), the continuum energy band analysis for free
electrons (or holes) becomes invalid, since the electrons are confined to a potential
well and the motion of electrons perpendicular to the interface is quantized. Then the
3D electrons can be treated as a 2D gas system along the channel region. As a
result, the classically defined energy level, Ec or Ev for free electrons or holes, will
not agree with the lowest split energy subband from the quantum nature of the 2D
electron gas. In such case, the quantization effect associated with the confinement of
the minority carriers in the inversion layer can be treated as effective bandgap
widening [Dor94] semiclassically. Furthermore, the distribution of mobile carriers
from the solution of density of states is altered, i.e., the peak density is not right on
the surface, and it is lower than that of the classical solution.
The effect should be treated with quantum mechanics for rigorous analyses.
As the bandgap is virtually expanded, the intrinsic carrier density (nÂ¡) tends to
decrease at the same temperature, and hence the threshold voltage increases. Again,
this is mainly because the lowest quantized subband energy is higher/lower than Ec/
Ev, and the total density of states in a quantized (2D) system is less than that in a
classical (3D) one.
Many QM models like selfconsistent simulation [Ohk90], firstprinciple full
band formalism [Jal97], simpler 3subband model [Har98a], and effective bandgap
widening for electrons [Dor94] (revisited for holes [Har97]) have been published and
developed in conventional numerical device simulators. However, for compact
9
2.2.1 Model Formalism
The UFSOI models are extended with polydepletion modeling, which is
implemented in strong inversion only, since the polydepletion effect is less
significant in weak inversion. The reason can be understood from the weakinversion
electricfield distribution in Fig. 2.1. The frontgate depletion potential (\/gf) is much
smaller than the frontgate surface potential (\/sf) since NP (gate doping) NB
(channel doping). However, the gatedepletion model is used to evaluate the current
and charge solution at the stronginversion boundary, which then influences the
moderateinversion solution. The polydepletion modeling still maintains the
continuities of charges and currents. Here we discuss the model formalism based on
an nchannel device, for both NFD and FD models as implied in [Vee88a].
\jrgf and Channel Charge When VDS = 0
We modify the physical relationship among the frontgate bias, VGfs, the
front surface potential, \j/sf, the voltage drop across frontgate oxide, and the
workfunction difference, Ofms, [Lim83] to account for polysilicon depletion:
VGfS = Vsf + Vgf + Vof + ^ms,
(2.1)
which leads to [Vee88a]
Qb(eff/2 + Qcf
Cof
(2.2)
where VfFB is the frontgate flatband voltage, Cb = Â£s/tb, C0f = Â£ox/tof, Qb(eff)1S
the effective body depletion charge, Qcf is the frontgate channel charge, and \/sb is
114
>
3
pq
>
2.0
1.5
1.0
0.5
0.0
0.5
0 50 100 150 200
Time (ns)
(a)
Figure 4.6 Simulated sequence of SOI/NFD senseamplifier operations in time.
Along period with unbalanced bitlines (e.g., an extended read/write0) is followed
by a read0/readl/read0 sequence. The predicted transient bitline voltages for
floating and ideally tied bodies are shown in (a), which illustrates the prevalent
read0 instability; and the predicted transient bodysource voltages of N1 and N2
for the floatingbody case are shown in (b), which reflects the N1N2 dynamic
thresholdvoltage imbalance that underlies the instability.Representative pulse
sequence for sensing data in DRAM.
51
(a)
(b)
Figure 3.3 CV characteristics of floatingbody NFD/SOI MOSFETs (Stage 3).
(a) nMOS. (b) pMOS. (LAV = 0.5 (im/2000 [im, f = 1 MHz, VDS = 0 V)
3
the linear to the saturation regions of MOSFET operation is developed in
Appendix A.
The UFSOI FD and NFD compact MOSFET models are physical and
processbased, meaning that their key parameters relate directly to device structure
and underlying physics of SOI MOSFETs. The parameter evaluation thus can be and
should be done based on knowledge of the SOI technology. Chapter 3 introduces a
processbased calibration methodology for UFSOI model parameter evaluation. The
methodology, which is simple and systematic, is developed to include some tuning
of particular parameters based on only a few electrical measurements of devices
having more than one channel length and width in specific bias regions. The
methodology can be defined with good physical insight to be reliable and much
simpler than conventional parameter extraction, or optimization via leastsquares fits
to measured data. In fact, such a processbased methodology seems essential for
reliable SOI model calibration because of complications due to device selfheating
and dynamic FB effects [Jen96].
We further apply UFSOI to gain insight into the behavior of SOI CMOS circuits
via the predictive capability of the physical model. Chapter 4 describes a physicsbased
study of floatingbody effects on the operation of SOI DRAM. The SOI has been of
interest for highdensity memories operating at low voltage [Yam95] because of its
immunity to latchup, low susceptibility to soft errors, suppressed (normal) body
effect, and small parasitic (source/drain) capacitance. A physicsbased study of
floatingbody effects on the operation of SOI DRAM is done. The study, which is
based on device and circuit simulations using the physical UFSOI/NFD model
43
Table 3.1 UFSOI4.5 NFD MOSFET Model Parameters
ALPHA
Impactionization coefficient
(0 for no impact ionization)
cm'1
0.0
2.45xl06
BETA
Impactionization exponential factor
V'cm"1
0.0
1.92xl06
LLDD
LDD region length (0 for no LDD)
m
0.0
(0.050.2)xl0"6
NLDS
LDD/LDS doping density
(>lxl019: D/S extensions)
3
cm
5.0xl019
lxlO19
BGIDL
GIDL exponential factor
(0 for no GIDL)
Vto'1
0.0
(48)xl09
NTR
Effective trap density for
trapassisted junction tunneling
(0 for no tunneling)
3
cm
0.0
10141015
JRO
Bodysource/drain junction
recombination current coefficient
Ann'1
l.OxlO"10
10'n10'9
M
Junction nonideality factor

2.0
12
CGFDO
Gatedrain overlap capacitance
FmT1
0.0
o
i
CGFSO
Gatesource overlap capacitance
FmT1
0.0
lxlO"10
CGFBO
Gatebody overlap capacitance
FmT1
0.0
0.0
RD
Specific drain parasitic resistance
flnn
0.0
(IOOIOOO)xIO'6
RS
Specific source parasitic resistance
Â£lm
0.0
(IOOIOOO)xIO'6
RHOB
Body sheet resistance
Q/sq.
0.0
30x103
DL
Channellength reduction
m
0.0
(0.050.15)xl O'6
DW
Channelwidth reduction
m
0.0
(0.10.5)xl06
LDIFF
Effective diffusion length in
source/drain
m
O.lxlO'6
(0.10.5)xl0"6
SEFF
Effective recombination velocity in
source/drain
ernes'1
l.OxlO5
(0.55)xl05
FNK
Flicker noise coefficient
(0 for no flicker noise)
F*A
0.0
010'25
FNA
Flicker noise exponent

1.0
0.52.0
86
(a)
1.0 0.0 1.0 2.0
^GfS 00
(b)
Figure 3.16 IDS VGfS characteristics of 0.5 fim FD/SOI devices (Stage 3).
(a) nMOS. (b) pMOS.
108
We assumed a bandgap reduction of about 100 meV [Yos97],
commensurately increased the appropriate components of source/drainbody
recombination current and charge storage in the NFD model, and repeated the SOI
DRAM cell simulation indicated in Fig. 4.1. The simulation predicts a reduction of
AVSn by a factor of about 35, which translates via (4.1) to a safe maximum value of
NP ~ 40 s'1 for gigabit DRAM. Since at least 50 ms is required to attain the quiescent
state, this value of NP is not possible. Hence the long retention time defined by IGt
as described previously is ensured, even if the actual bandgap reduction is somewhat
less than that assumed.
We stress that (4.1) is based on a worstcase analysis with the wordline
always off. In fact, normal (or optimal [Man96]) pulsing of the wordline tends to
discharge the body and reduce the subsequent VBS(t) and hence AVSN [Suh96].
Furthermore, (1) relates to the page mode [Man96] where the bitline drops abruptly
from (quiescent) VDD to 0 V. For normal accessmode pulsing with precharging,
where it might drop only to VDD/2, or for bitline quiescence at VDD/2, the quick
reductions in VSN that might occur are much smaller than 60 mV.
4.3 Sense Amplifier Operation
The implicit conclusion that body ties are needed in the peripheral circuity
of SOI DRAM seems to be superficially based on observed (DC) floatingbody kink
effects and premature drainsource breakdown due to the parasitic BJT [Sum94],
However, the lowvoltage transient bodycharging effects noted in Sec. 4.2,
especially the dynamic threshold voltage which is hysteretic [Suh94b], need to be
180
Figure 5.16 Modelpredicted currentvoltage characteristics.
Comparison of IDSVGs characteristics for asymmetricalgate DG and SG (back
gate grounded) nMOSFETs. The asymmetrical DG device has nearideal S and
~2x stronginversion current of the SG counterpart.
45
TPS, NDS, TF, TB, THALO and NHALO (if applicable), NBL, NBH, LLDD and
NLDS (if applicable), CGFDO, CGFSO, CGFBO, RD, RS, RB, RHOB, DL, DW)
and the pertinent device physics (UO, THETA, VSAT, ALPHA, BETA, TAUO, JRO,
M, LDIFF, SEFF, BGIDL, QM, NTR, LRSCE). This estimation can be done quickly,
and our experience has shown that the preliminary model card typically is a good
representation of the technology, even when the device structure is not precisely
known. For the AMD technology, with dualpolysilicon gates (n+ poly for nMOS and
p+ poly for pMOS), the parameters given in Table 3.2 are defined unequivocally for
Table 3.2 Model Parameters Evaluated Directly from Technology Information
Parameter
Value
TOXF
7.0 nm
TOXB
0.36 pm
TF
0.12 Jim
TPG
+ 1
TPS
1,+1
W (drawn)
20 pm
L (drawn)
1.0 and 0.35 pm
both nMOS and pMOS devices. TOXF is the physical thickness of the gateoxide;
polysilicongate depletion and energy quantization are options in UFSOI4.5. If
these options are used, then we initially estimate NGATE to be 5.0xl019 and QM to
be 0.4, where the latter is based on a general calibration of the UFSOI model to
numerically simulated devices with channel doping in the range 1016 1018 cm'3
[Jal97]. TOXF should be set to the measured electrical value of the oxide thickness,
185
modeling. Good insights gained from the upgraded models can facilitate optimal
circuit design and device scaling. In addition to the main model upgrades discussed
in this chapter, a continuous VDS(eff) model, as introduced in Appendix A, was
incorporated in UFSOI models. Utilizing this continuous model with a refined
channellength modulation model, an analytical and unified expression for channel
current over triode and saturation regions was obtained.
In Chapter 3, a processbased calibration methodology for UFSOI model
parameter evaluation was developed. The key parameters to be evaluated are directly
related to device structure and physics. Therefore, based on knowledge of the SOI,
the parameter evaluation thus can be simply done without optimization via least
squares fits to measured data, commonly used for conventional parameter extraction.
Moreover, since the parameters are physically linked to their underlying physics,
they are more general and hence can be unambiguously evaluated from minimum
data. The systematic procedures were illustrated with two examples of application to
an NFD/SOI CMOS technology and an FD/SOI CMOS technology.
In Chapter 4, a physical, SOISPICE simulationbased study of lowvoltage
floatingbody effects on the operation of NFD/SOI DRAM was described. Regarding
floatingbody effects, dynamic retention time and sense amplifier operation were
examined comprehensively with an actual SOI DRAM technology calibrated to the
UFSOI/NFD model. The SOI DRAM was concluded viable for gigabit applications
according to the predicted longterm retention time, which is predominantly
controlled by the thermal generation leakage current. However, several V(BL) = VDD
quiescent periods between datarefresh cycles in the page mode can shorten the
65
VDS(V)
(a)
(b)
Figure 3.9 IDSVDS characteristics of 0.35 imNFD/SOI devices (Stage 9).
(a) nMOS. (b) pMOS.
CHAPTER 6
SUMMARY AND RECOMMENDATIONS FOR FUTURE WORK
6.1 Summary
This dissertation presented modeling of scaled SOI MOSFETs, including DG
MOSFETs. The UFSOI NFD and FD models were upgraded and refined, and the first
version of the UFDG model was developed. The physics and processbased models
are essential to gain insight into the circuits of highly scaled CMOS, especially for
NFD/SOI due to floatingbody effects and DG MOSFETs due to the gategate
coupling. More importantly, the device characteristics and circuit performance not
only can be simulated, but also can be predicted by the physical models. The
applications of the modeling were demonstrated with simulationbased device and
circuit studies.
In Chapter 2, a compact yet physical model accounting for polysilicon
depletion and quantummechanical effects was introduced and implemented. These
effects can be beneficial due to lowered effective gate capacitance, and also can be
undesirable due to degraded current drivability. Though the modeling could be
implemented directly based on the underlying physics, SOIspecific body effects and
capacitive coupling should be accounted for as well. The capability of the physics
based upgrades was exemplified with model calibration to some SOI CMOS
technologies. Their consequential impact on circuit performance was further
examined with various dopings and structures via the advantage of processbased
184
116
condition, reveals that the underlying QB imbalance takes at least 0.1ms to obtain.
This time is defined mainly by the carrier recombination rates in N1 and N2, by
which the Qgs diverge from their equal values corresponding to the precharge
condition. The VT imbalance would be ultimately removed by carrier generation
during periodic precharges in normal operation, but over a very long period of time.
The imbalance could be effectively removed by an abnormally long precharge, after
which Vbs(N1) = Vbs(N2) ( =40 mV after 50 ms according to our simulations).
Because of the sizable difference between the pertinent recombination and
generation times, it is conceivable that a fatal imbalance could result even without
the extended period. Simulations show, for example, that a sequence of repeated
read0 operations tends to create the imbalance, but the number (>104) required to
make it important is unrealistic.
As suggested in this work, due to the historydependent floatingbody effects
(or hysteresis), intensive simulations are usually required in order to obtain a reliable
analysis of FB SOI CMOS circuits. As a result, the efficiency of the circuit simulator
becomes an important issue. Therefore, analytical derivatives are implemented for
UFSOI/NFD speedup, as described in Appendix C, with which dramatic
improvement in run time is achieved.
4.3.3 Designs to Avoid Instabilities
Source/Drain Engineering
We first consider the possibility that the SiGesource/drain technology
[Yos97], which we showed in Sec. 4.2 to be effective in improving the dynamic
retention of the DRAM cell, can avoid the senseamplifier instabilities. We assumed
CHAPTER 5
COMPACT DOUBLEGATE MOSFET MODEL
5.1 Introduction
Interest in the doublegate (DG) MOSFET has been growing as the end of the
SIA roadmap [Sem99] is being approached. The inherent gategate charge coupling
via the thin Si film effectively reduces shortchannel effects (SCEs) and yields higher
drive current [Fra92]. The novel DG device retains the advantages of the FD/SOI
MOSFET, and is highly scalable, unlike the FD/SOI device, which is plagued by
underlying BOX fringing fields and associated SCEs [Yeh95],
In order to study and analyze DG CMOS devices and circuits
comprehensively, a generic compact physical model is needed. A few analytical
models for DG MOSFETs have been published [Suz95], [Bac95], [IkeOO], [TauOO]
in the past, but they are either not suitable for general devices with arbitrary gate
structures and/or do not account for stronginversion charge distributed throughout
the thin Si film. Indeed, most of the models we have seen assume symmetrical gates.
In contrast, a truly useful (generic) model should not have this restriction, and should
be processbased [Fos99] with predictive capability.
Two types of DG SOI MOSFETs are contemplated for future CMOS:
symmetricalgate and asymmetricalgate (e.g., n+/p+ polysilicon gates) devices.
Since the UFSOI/FD model [Yeh95], [Fos99] already accounts for weakinversion
backchannel current, with the charge coupling between two gates, the model has
125
160
Qcb = WLC
ob
vGbS
VDs(Cof + Cob)(l+s)
2 6[2Qc(0) + (Cof + Cob)VDS]
(5.52)
Next, we need to evaluate the integrated inversion charge in the channel:
Qch = Wj Qc(y)dy,
(5.53)
which will be the basis for source and drain charges. We can ignore the diffusion
current for now because the inversion charge is negligible when the diffusion current
is predominant. Therefore, we approximate (5.36) as
Wdy ~ W^effr 7p o
L'of + L'ob z
1 dQc Ich^eff
2v
sat(eff)
dV/.
(5.54)
Integrating both sides of (5.54) from 0 to y, we obtain
2 2 Icb Meff
Wy = f r (Qc(> Q,(y>) 2f AV(y>
c, + cob
sat(eff)
(5.55)
where A\/(y) =
Qc(y)Qc(0)
c0f + cob
We can now describe Qc(y) analytically from the
quadratic equation (5.55), and hence (5.53) can be integrated out as
Qch = WL(Cof + C
ob)VDs[u~
z +
2[z3(zl)3r
3(2z 1)
(5.56)
where u =
Qc()
, W + 2Wvsat(eff)Qc(0) a ]
and Z = rTTT ttt A simple
(C0f + Cob)VDS 2Wvsat(eff)(Cof + Cob)VDS
partition scheme [War78], [Vee88b] is used to divide the inversion charge to drain
and source components as follows:
82
NSB) iteratively to fit the current and slope of the Ios'^GfS characteristic at low VDS
in weak inversion; GAMMA is initially estimated from Table 3.5. Results are
illustrated in Fig. 3.15.
As part of the 2D BOX fringingfield modeling, an effective backgate bias
is defined as [Yeh96]
2
TOXR
VGbS(eff)a VGbS + (KAPPAVDS + GAMMAEqL) (3.10)
L
where E0 ( = 3'F/3yx = TB y = Q ) represents the source of the fringing field;
VGbS(eff) reduces to VGbS for very long L and/or thin TOXB. As evident in (3.10)
then, GAMMA and KAPPA can be evaluated with reference to their relative
significance for different Ls and VDSs; for example, KAPPA is more important for
high VDS, which will be discussed later. Since TB not only affects the slope but also
affects the current magnitude (i.e., threshold voltage), an iterative yet uncomplicated
scheme should be used in this stage. We thereby confirm GAMMA = 0.5 (given
previously) and TB = 50 nm (consistent with technology) for both nMOS and pMOS,
and we get NBODY = 2.2 x 1017 cm'3 and 2.0 x 1017 cm'3 for nMOS and pMOS,
respectively.
Note in Fig. 3.15(a) the significant discrepancy at high VDS for the nMOS
device; a subthreshold kink is exhibited. We infer that it is mainly due to the device
becoming NFD (when VBS > 0, which tends to shrink the channel depletion region
in a MOSFET). This characteristic stresses the fact that in order to develop a good
FD/SOI MOSFET with reliable (and predictable) characteristics without floating
90
(a)
1.0 0.0 1.0 2.0
VGfS(V)
(b)
Figure 3.18 IDS VGfS characteristics of 0.25 (im FD/SOI devices (Stage 5).
(a) nMOS. (b) pMOS.
36
Figure 2.4 Predicted inversionlayer electron mobilities versus gate bias.
Mobility comparison of QM and classical models.
64
VGfs(V)
(a)
Figure 3.8 IDS VGfS characteristics of 0.35 (xm NFD/SOI devices (Stage 8).
(a) nMOS. (b) pMOS.
130
WeakInversion Threshold
The weakinversion boundary, VTW, is defined based on a twodimensional
(2D) weakinversion formalism, and is solved iteratively in the UFSOI/FD model.
For UFDG, we employ the analytical theory, as used for VTS, to give a simple yet
physical expression for VTW.
Following the UFSOI/FD model, we define the surface potential for the usual
front channel at this boundary as \/wsf = 2
Fermi potential in the Si film. Then we can obtain the corresponding
VGfs(= VGbS) = VTW directly from (5.1) and (5.2) with Qcf and Qcb ignored for
weak inversion:
(5.4)
which is consistent with VTS.
5.2.2 Weakinversion Formalism
A twodimensional (2D) weakinversion analysis as in the UFSOI/FD model
[Yeh95], which accounts for backchannel current with the charge coupling between
two gates, is applicable to the DG MOSFET. We hence use this model as the initial
basis to evaluate the channel current, which is obtained by integrating the
predominant diffusion current over the entire Si film.
For an nchannel device, the model basically solves Poissons equation
applied to the intrinsic region of Si film,
10
Figure 2.1 Schematic of electricfiled distribution in weak inversion.
Electricfiled distribution across (n+) polysilicon (P), oxide (O), and (p) silicon
(S) in an nMOSFET biased in weak inversion.
210
[Jal97] S. Jallepalli, J. Bude, W.K. Shih, M. R. Pinto, C. M. Maziar, A. F. Tasch,
Electron and Hole Quantization and Their Impact on Deep Submicron
Silicon p and nMOSFET Characteristics, IEEE Trans. Electron Devices,
vol. 44, pp. 297303, February 1997.
[Jen96] K. A. Jenkins, Y. Taur, and J. Y.C. Sun, Single Pulse Output of
Partially Depleted SOI FETs, Proc. IEEEInternat. SOI Conf., pp. 72
73, October 1996.
[Kim95] H.S. Kim, S.B. Lee, D.U. Choi, J.H. Shim, K.H. Lee, K.P. Lee, K.
N. Kim, J.W. Park, A High Performance 16M DRAM on a Thin Film
SOI, Symp. VLSI Tech. Dig., pp. 143144, Kyoto, Japan, June 1995
[Kim99] K. Kim and J. G. Fossum, Optimal doublegate MOSFETs: Symmetrical
or asymmetrical gates? Proc. IEEE Internat. SOI Conf., pp. 9899,
October 1999.
[KimOl] K. Kim and J. G. Fossum, DoubleGate CMOS: Symmetrical Versus
AsymmetricalGate Devices, IEEE Trans. Electron Devices, vol. 48, pp.
294299, February 2001.
[Koh97] Y.H. Koh, J.H. Choi, M.H. Nam, and J.W. Yang, BodyContacted
SOI MOSFET Structure with Fully Bulk CMOS Compatible Layout
and Process, IEEE Electron Device Lett., vol. 18, pp. 102104, March
1997.
[Kri96a] S. Krishnan, Analysis and Modeling of Nonlocal and Dynamic
FloatingBody Effects for Application in Scaled SOI CMOS
Technology, Ph.D. Dissertation, University of Florida, Gainesville,
1996.
[Kri96b] S. Krishnan and J. G. Fossum, Compact NonLocal Modeling of Impact
Ionization in SOI MOSFETs for Optimal CMOS Device/Circuit Design,
SolidState Electronics, vol. 39, pp. 661668, May 1996.
[Li93] S. S. Li, Semiconductor Physical Electronics. New York, Plenum
Press, 1993.
[Lim83] H.K. Lim and J. G. Fossum, Threshold Voltage of ThinFilm Silicon
onInsulator (SOI) MOSFETs, IEEE Trans. Electron Devices, vol.
30, pp. 12441251, October 1983.
[Lim84] H.K. Lim, and J. G. Fossum, CurrentVoltage Characteristics of Thin
Film SOI MOSFETs in Strong Inversion, IEEE Trans. Electron Devices,
vol. 31, pp. 401408, April 1984.
[Lu97] P.F. Lu, C.T. Chuang, J. Ji, L. F. Wagner, C.M. Hsieh, J. B. Kuang,
L. L.C. Hsu, M. M. Pelella, Jr., S.F. S. Chu, and C. J. Anderson,
FloatingBody Effects in Partially Depleted SOI CMOS Circuits,
IEEE J. SolidState Circuits, vol. 8, pp. 12411253, August 1997.
[Lum97] M. Lundstrom, Elementary scattering theory of the Si MOSFET,
IEEE Electron Device Lett., vol. 18, pp. 361363, July 1997.
142
inversion, the coupling is gone and the slope of \/sb decreases. Ultimately, for very
high VGS, both V]/sf and v/sb are pinned, thereby yielding two separated channels
where the transverse field is shielded by the inversion layers.
Although the model is developed for strong inversion, the subthresholdlike
characteristic is predicted, as depicted in Fig. 5.4. The ideal subthreshold slope
reflecting the gategate charge coupling is shown in weak inversion, implied by
(5.11) and (5.12) with small variation in the electric field. Accordingly, the model is
not only valid for strong inversion but also somewhat reasonable for VGS < VTS.
Another important characteristic to be evaluated is the inversion charge
density. Applying Gausss law to front and back interfaces, we can express the
integrated inversion charge density as
Qc = es(Esf Esb)= ~[<'of(VGfs V FB Vsf) + E'ob(VGbS ~ V FB ~ Vsb)] (523)
where (5.11) and (5.12) give the dependences on V/sf and \/sb. Later (5.23) will be applied
to the calculation of channel current. Modelpredicted QC(VGS) (without the noted
quantummechanical perturbations) for asymmetrical DG and SG (back gate
grounded, which reflects the robustness of our compact device model) MOSFETs are
compared in Fig. 5.5. The DG MOSFET shows nearideal subthreshold slope and
higher charge density as results of the inherent gategate charge coupling [KimOl].
To check the validity of this model and associated assumptions for strong
inversion, UFDGpredicted QC(VGS) for symmetrical and asymmetricalgate DG
MOSFETs are compared with MEDICI (classical) simulation results in Fig. 5.6. Good
agreement is evident over a wide range of gate bias for both devices, even for VGS <
31
and
(2.53)
where (2.50), (2.51), and (2.53) are equivalent to (2.46), (2.47), and (2.48),
Qr = V2(1Â£sVT a = Cb^Cob/^fCoftCb + rbCob)) with rf = 1 + qNsf/Cof and
rb = 1 + qNsb/Cob, Nsf and Nsb are the front and backgate surfacestate densities,
and Na is the film doping density. Again, we apply Gausss law in one dimension to
express the frontsurface transverse field including surfacestate density as
Vsfst1 + qNsf/Cof) (VGfS VFBf)
(2.54)
Â£
Then V/sfs can be found by solving (2.43), (2.44), (2.50), (2.51), and (2.54)
iteratively. However, as discussed earlier, t/sfs(VGfS) gives an unstable VTS. Instead,
we define a true and VGfSindependent VTS (=f(VTS)) with the same approach for the
NFD model. The regional upgrades incorporated in the NFD model are applied here
as well.
For strong inversion (VGfS > VTS), \)/sfS is solved iteratively with a given
VGfs in (2.54). After \/sfS is obtained, the current and charge solutions are
automatically updated. For weak inversion, the current is assumed to be
predominantly diffusion and calculated through charge integration. Note that this
model has been recently upgraded to avoid the discontinuity due to the determination
179
Figure 5.15 Modelpredicted inverter delay versus backoxide thickness variation.
Simulated delay (via 9stage RO simulations w/ parasitics) vs. tob for
asymmetrical and symmetrical (with near midgap gates)gate DG nMOSFETs.
6
Appendix B assesses the performance of a new BTB SOI CMOS inverter
configuration. The bodytied NFD SOI MOSFET is a common solution for
ameliorating the FB effects, as discussed previously. However, the efficacy and
optimization of real (with finite resistance) body ties are crucial. In this appendix, we
first discuss the characteristics of a bodytied structure, based on measured and
simulated data. Then, the novel BTB SOI CMOS, which can suppress the hysteresis
of FB SOI CMOS circuits while retaining the speed performance for low supply
voltage, as implied by preliminary simulations, is proposed and explained.
Appendix C presents an efficient speedup scheme applied to the UFSOI
NFD model. Due to the historydependent FB effects of SOI CMOS circuits, as
revealed in Chapter 4, comprehensive and intensive simulations are usually
necessary. However, the inefficient difference approximations, that require four
extra calls of the model routine for each call by the NewtonRaphsonbased nodal
analysis, were previously used in the model. In order to reduce run time, approximate
analytical derivatives, which do not require any extra call of the model routine, are
incorporated, and their benefit is noted.
186
retention time. Improved device design (with SiGe source/drain) was shown to be
effective in resolving this problem. Imbalanced dynamic threshold voltages,
introduced by hysteretic dynamic body charging, can cause dynamic instability of
sense amplifier. Nonetheless, using crude nMOS bodytosource ties while leaving
pMOS bodies floating were shown to be an efficient solution without increasing the
complex of technology. Also, the minimum requirement for a body tie to completely
suppress the instability was assessed via a process/circuitbased sensitivity analysis.
In addition to the bodytied structures mentioned in this chapter, a novel BTB SOI
CMOS inverter configuration, as proposed in Appendix B, is a promising solution as
the beneficial capacitive coupling in floatingbody SOI MOSFETs is still attained.
Also, due to the intensive simulation needed for the analysis of hysteresis, the
considerable run time was reduced by implementing analytical derivatives in UFSOI/
NFD model, as described in Appendix C.
In Chapter 5, a processbased compact model for doublegate (DG)
MOSFETs was presented and developed. This model, having only physical and
processrelated parameters, is generic and is suitable for the evaluation of different
DG structures. Furthermore, the physicsbased nature of the model allows the
upgrades of quantummechanical confinement to be implemented in a simple way.
Using the UFSOI/FD MOSFET model as the initial basis, the gategate charge coupling
and inversion charge distribution throughout the entire Si film were accounted for in the
UFDG model. Due to the extremely thin Si film for DG application, the associated
scattering mechanisms were accounted for in the carrier mobility model. The terminal
charge modeling, using the quasistatic approximation, was implemented as well for a
transient largesignal circuit model. The model was then applied to gain valuable insight
138
f
Jn
Edx = \/sb \/sf = Esftif + Esbtib + E'sftSi + EsbtSi
(5.15)
where
lif =
Q,
if
T.+
Â£sEsf
qn(0) f 2/v ^ rVsf
(qni/NA)expl
(5.16)
tib =
Qi
ib
Â£sEsb
qn(tSi} 2/M (VsbV
(qni /NA)eXP[yJ
(5.17)
exp
F 
csf
Eo ,
1 + exp
EsfE^
v Eo ,
Esf.
(5.18)
Esb =
exp
r
fEsb+E0y
\
c 
\
V
Eo ).
/
1 + exp
f
fEsb + E;
\\
l E0
))
Esb >
(5.19)
2(bR
with Eo = 2( w~
P^bQNa
being an upper limit based on the depletion
dep' 'V s
approximation for the smoothing functions in (5.18) and (5.19); also in (5.15),
Esf = E> 1 + exp
^sf
(5.20)
and
29
The actual VTS (=f(VTS)) must be defined first before we can determine the
region of MOSFET operation, and this boundary can only solved via iteration. For
the first iteration, VGfS and \/sfs in (2.49) are replaced with initial guesses for VTS
and \/Sfs, respectively. Then, a new \/sfs is obtained by solving (2.43), (2.44), (2.46),
(2.47), and (2.49), and hence a new VTS can be defined based on \/sfS. Finally, the
VGFSindependent VTS is found with four iterations. (The fixed number of iteration
can also help reduce numerical noise.) The same approach is done for the FD model.
For strong inversion (VGfS > VTS), \j/sfS must be updated via same iteration
based on a given VGfs for (2.49). (Again, the number of iteration is fixed at four.)
Therefore, t/sfS(VGfS), which accounts for the QM effect in the entire strong
inversion region, results in the corrections of current and charge solutions implicitly
and automatically. No any other additional calculations or empirical fitting is
necessary, which reflects one of the main advantages of a physical model over an
empirical one.
Regarding weak inversion, since the effect of altered VTW due to energy
quantization is weak based on our simulations (i.e., VTW(VGfS) is approximately the
original VTW), we ignore the similar numerical iteration for VTW to preserve the
previous model without losing the efficiency of simulation. Though the quantum
mechanical model is ignored for VTW calculation, the weakinversion diffusion
2
dominant current ( nÂ¡ ) still needs to be updated in order to predict a more accurate
subthreshold slope based on the consistent strong and weakinversion models.
However, no complicate iteration, as shown previously for strong inversion, is
needed; we simply calculate nÂ¡^M from (2.43), (2.44), and (2.49) with an analytical
204
approximated derivatives are useful, e.g., difference approximations for NRbased
nodal analysis in circuit simulations. In our UFSOI models, due to the physicsbased
nature, no direct analytical derivatives are available and extra calls of the model
routine are needed in order to calculate difference approximations. To speed up the
model, we replace the derivatives evaluated from difference approximations with
approximated analytical derivatives. Therefore, the model routine is only calculated
once. Even though, due to the inaccuracy of approximated analytical derivatives, the
number of iteration might be higher than that with difference approximations, the
overall efficiency of the simulation is greatly improved by removing the extra calls
of the model routine for each Spice iteration. Since the simulation for FD SOI CMOS
circuits can be usually done in a straightforward manner without the hysteresis, the
model upgrade is only focused on the UFSOI/NFD model.
In the UFSOI/NFD model, the analytical derivatives are derived and
implemented for ICH, IBJT, IGi, IGIDL, IRGt, IXun, QGf, QGb, Qs, and QD, as indicated
in Fig. 4.1; the analytical derivatives for QB are simply done via charge neutrality:
3Qb 3QÂ¡
avis = f avis
(C.2)
with i = Gf, Gb, S, D, and j = Gf, Gb, D, B. To exemplify the modeling approach, we
first approximate the derivatives of channel current with respect to VGfs:
31
ch
q^h
3VGfskT(l+a)
(weak inversion),
(C.3)
187
to the characteristics of DG MOSFETs via a few examples involving device and circuit
simulations. Without the physical compact model, it is impossible to predict the
performance of DG CMOS circuits reliably and efficiently.
6.2 Recommendations for Future Work
For the NFD SOI MOSFET, a nonfixed depletion region (TB) in the channel
might be needed for the condition of high VBS or nonretrograded doping. More
importantly, in subthreshold region, the TB effect associated with the floating body
can have a significant impact.
BTB SOI CMOS, as proposed in this dissertation, appears to be very
promising, especially for lowvoltage application. The issue for the additional
junction leakage will go away when the supply voltage is near IV or below. More
processbased study regarding the parasitics and technology complexity can be done.
The ballistictransport channel, which is limited to the thermal velocity,
might be eventually reached or approached. A predictive model accounting for this
limit is essential for performance projection. Carrier degeneracy must be included in
the evaluation of thermal velocity as well. This upgrade will be needed for both
UFSOI and UFDG models.
Though the UFDG model is generic, it is not applicable to other alternative
DG structures, e.g, delta structure [His91], gateallaround [Col97], etc. When the
DG device is being developed, all different kinds of structures might need to be
evaluated simultaneously for comparison. Model extension to account for alternative
structures might be a necessary task in the future. Besides, quantummechanical
44
Table 3.1 UFSOI4.5 NFD MOSFET Model Parameters
Flag Parameters
Name
Description
Units
Default
Typical Value
BJT
Parasitic bipolar flag (0: off; 1: on)

1
1
TPG
Type of gate poly
(+1: opposite to body;
1: same as body)

+1
+1
TPS
Type of substrate
(+1: opposite to body;
1: same as body)

1
1
SELFT
Selfheating flag
(0: no self heating; 1: approximate
model; 2: full model)
0
0
Optional Parameters
Name
Description
Units
Default
Typical Values
TAUO
Carrier lifetime in lightly doped
region
s
Calculated
10'7105
VFBF
Frontgate flatband voltage
V
Calculated
1 (nMOS)
+1 (pMOS)
VFBB
Backgate flatband voltage
V
Calculated

WKF
Frontgate work function difference
V
Calculated
VFBF
WKB
Backgate work function difference
V
Calculated

BFACT
VDsaveraging factor for mobility
degradation

0.3
0.10.5
FVBJT
BJT current directional partitioning
factor (0 for lateral ID flow)

0.0
01
RHOSD
Source/drain sheet resistance
Q/sq.
0.0
50
3.2.1 Preliminary Model Card
We begin the calibration by defining a preliminary set of model parameters
estimated directly from each device structure (TOXF, TOXB, NSUB, NGATE, TPG,
122
4.2, which reflect variations in the number of rows in the DRAM array, affect AV in
(4.2), and the prevalent sensitivity predicted (lower RBS(crit) fr higher CBL) is in
accord with this, except for the highCBLcase (500 fF corresponding to 1024 rows).
The results for this case are inconsistent, implying that AV is too small to effectively
drive the amplifier simulation, which is limited by numerical error. Indeed, this
suggests that the actual circuit would not function properly for such a high value of
bitline capacitance. The 10% variations in LN in Table 4.2, which are representative
of the technology, define changes in the effective VT via shortchannel effects in the
device model, but the main effect on RBs(Crit) *s ^ue to the variation in the gate
capacitance. It decreases with decreasing LN, meaning less capacitive coupling
between the body and the gate and hence less dynamic N1N2 VBS(t) imbalance
induced by the fall of the precharge pulse. Thus RBs(Crit) *s higher for shorter LN. The
increase in RBs(Crit) fr increasing T given in Table 4.2 is mainly due to the increasing
recombination rate associated with the bodysource junction, and the concomitant
restrictions of QB and VBS.
In addition to the bodytied solutions aforementioned, we suggest a novel
bodytiedtobody (BTB) SOI CMOS inverter configuration, which can effectively
suppress the historydependent floatingbody effects while attaining the beneficial
capacitive coupling in floatingbody SOI MOSFETs. Based on a preliminary analysis
presented in Appendix B, we believe BTB SOI CMOS could offer significant
benefits in particular applications.
212
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[Ste67]
F. Stern and W. E. Howard, Properties of Semiconductor Surface
Inversion Layers in the Electric Quantum Limit, Physical Review,
vol. 163, pp. 816835, November 1967.
[Suh94a]
D. Suh and J. G. Fossum, The Effect of Body Resistance on the Breakdown
Characteristics of SOI MOSFETs IEEE Trans. Electron Devices, vol. 41,
pp. 10631066, June 1994.
[Suh94b]
D. Suh and J. G. Fossum, Dynamic FloatingBody Instabilities in
Partially Depleted SOI CMOS Circuits, Tech. Digest 1994 Internat.
Electron Devices Meeting, pp. 661664, December 1994.
135
'of
(5.11)
and
(5.12)
f b
V FB = ^GfS Qff/Cof and v FB = ^GbS Qfb/Cob are flatband voltages
referenced to the (hypothetical) neutral body, Qff and are fixed front and back
oxide charge densities, \/of and v/ob are the potential drops across the front and back
gate oxides, and Esf and Esb are the front and backsurface electric fields. (The
surfacestate charge, accounted for explicitly in the weakinversion formalism
[Yeh95], is presumed to be part of Qff and here. Gate depletion, modeled in
Chapter 2, is peculiar to polysilicon gates and is neglected.) Note that \j/sf and \/sb are
also referenced to the mentioned neutral body. Equations (5.9) (5.12) are
fundamental and provide sufficient and necessary information for deriving the
surface potentials, the electric fields, and the carrier densities. However, the system,
involving both differential and integral equations, cannot be solved analytically
without making simplifying approximations.
To get a compact model for strong inversion (n NA), we approximate (5.9)
as
(5.13)
81
still be evaluated according to their importance in shortL devices only. In this
section, we will focus on the evaluations of NSB, GAMMA, TB, NBODY, UO, and
THETA. Due to the limited availability of measured data, we choose the 0.5 pm
device to demonstrate the longL calibration, even though it is not long enough to be
absolutely void of shortchannel effects.
Stage 1
Evaluated Parameters
Measurement Data
Device
NSB, GAMMA, TB,
NBODY
IDS vs. VGfs @ low VDS (50 mV)
Long L
In weak inversion, the diffusion of carriers throughout the fully depleted
film body is accounted for in the UFSOI model by integrating the carrier charge
across the entire film; front and back channels are thereby defined, and front and
back channellength modulation is accounted for as well [Yeh96]. The increased
charge at the back surface will also reduce the frontchannel threshold voltage
through the chargecoupling effect [Lim84], Therefore both front and backgate
surface charge can influence the subthreshold characteristic. However, since the
frontgate oxide thickness is typically much thinner than backgate oxide thickness,
NSF tuning is usually not needed. We first check the subthreshold slope of the IDS
VGfs characteristic at low VDS for the longL device to determine the importance of
NSB. If S is near ideal (~60mV), then NSB must be low, and hence we can skip its
evaluation. In this example, S is found to be 64.4 and 64.3 mV for the nMOS and
pMOS devices, respectively (>60mV because of the fringing field in the BOX), and
so we do not evaluate NSB initially. We next tune TB and NBODY (and perhaps
106
o
iA, and indeed IBjr(t) (exp(qVBS/kBT)) is the predominant component early in
time, but it decreases faster than IGH(t) as VBs(t) decays. In the longtime simulation,
in fact, IGt (ocnj/Tg), for which we assume a (body dopingdependent) thermal
generation lifetime of about Ins, defines the predominant loss of charge and voltage
on Cs as implied in Fig. 4.2; IBJT and ICH ultimately become inconsequential as
VBS(t) approaches the DC value. (Note then the inherent advantage of SOI over bulk
Si DRAM due to its much smaller drain junction area over which IGt is generated.)
The predicted decay of VSN(t) is shown in Fig. 4.3, along with decays
derived from simulations with celltransistor threshold voltages (VT) less than IV
(effected by decreasing the channel doping density in the device model). The
sensitivity to VT is due to the early discharging of Cs by ICH as well as IBJT. For VT
> IV however, ICH is unimportant, and IBJT exclusively causes about a 60 mV early
drop in VSN in about 0.2 is. This quick AVSn is insignificant in this case. As
reflected by Figs. 4.2 and 4.3, IGt (= 1.4 fA) predominantly defines the retention time
(tret for 0.5 V decay), which is about 7 s, subject of course to xg. In this case, the
retention time is directly proportional to xg; thus if xg were 10 ns, then tret would be
about 70 s. Although AVSN would be larger for highertemperature operation (mainly
because IBJT nÂ¡2), these results would seem to suggest then that a threshold voltage
of IV for the cell transistor would render long enough retention time for gigabit SOI
DRAM, as concluded in [Ter96].
However, insight from our analysis suggests that the worst case for dynamic
retention would be a sequence of bitline pulses like that reflected by Figs. 4.2 and
4.3, with the bitline recurrently becoming quiescent at VDD and thereby enabling
201
IN
(b)
Figure B.3 The configuration of BTB SOI CMOS.
(a) BTB SOI CMOS with bodies tied via finite resistance RB and (b) predicted
offstate current: I0ff ~ Ich(vBs) w/VBS defined by RB.
IDS (A) & go (A/V) IDS (A) & go (A/V)
195
(a)
0.0060
0.0040
0.0020
0.000^
(b)
Figure A.3 Modelpredicted IDSVDs characteristics and conductances.
Simulated IDSVDs characteristics of an NFD/SOI nMOSFET (W/L = 10 pm/
0.35 pm) with (a) LMOD = 1 (default) and (b) LMOD = 0 (no channellength
modulation).
99
to ameliorate floatingbody effects, but the FD state is not necessarily maintained for
all bias conditions (such as in pass transistors), and the FD device threshold voltage
is difficult to control [Kri96a].
None of the previous work though has included a comprehensive study of the
floatingbody effects on the operation of SOI DRAM, nor of the design criteria to
control them. In fact there is some controversy about whether the dynamic data
retention is an issue at all ([Ter96] suggests it is not), and it is not clear whether real
body ties (with high resistance due to the thin SOI) provide any significant benefit in
the peripheral circuits. The purpose of this chapter is thus to examine the floating
body effects in SOI DRAM from a physicsbased perspective, and to give
unequivocal insights on design for avoiding them. The study is based on device and
circuit simulations using SOISPICE [Kri96a] and its physical UFSOI/NFD MOSFET
model [Suh95a] calibrated to an actual SOI DRAM technology. The chargebased
model, which accounts for the parasitic BJT coupled to the MOSFET formalism, has
been verified based on applications in several SOI technologies [Kri96a]. We address
two critical lowvoltage highdensity SOI DRAM issues: longterm dynamic
retention of the floatingbody cell; and performance of the sense amplifier, subject
to hysteretic effects implied by floating and even tied bodies.
4.2 Dynamic Data Retention
The SOI DRAM cell depicted in Fig. 4.1, operating at low VDD = 1.5 V with
Cs = 25 fF, is simulated using SOISPICE to assess longterm dynamic data retention.
The network representation for the SOISPICE (nMOS) model is also shown in Fig.
172
x10"4 x10'5
(a) IDS VGfS characteristics; L = 1.2 (im (c) IDs vGfS characteristics; L = 4.2 (im
x10'4
VDS (V)
(b) IDSV DS characteristics; L = 1.2 im
x10"4
VDS (V)
(d) IDS VDS characteristics; L = 4.2 pm
Figure 5.11 Calibrated 1(A) V(V) characteristics of DG pMOS devices.
Same model parameters are used for the two devices. (W = 3 pm)
78
3.3.1 Preliminary Model Card
We begin the calibration by defining a preliminary model card for each
device with the parameters estimated directly from the device structure (TOXF,
TOXB, NSUB, NGATE, TPG, TPS, NDS, TB, NBODY, LLDD and NLDS (if
applicable), CGFDO, CGFSO, CGFBO, RD, RS, RB, DL, DW) and the pertinent
device physics (NSF, NSB, GAMMA, KAPPA, UO, THETA, VSAT, ALPHA,
BETA, TAUO, JRO, M, LDIFF, SEFF, BGIDL, QM, LRSCE). To account for the 2
D fringing fields in the BOX, GAMMA and KAPPA must be properly evaluated. The
initial values for GAMMA and KAPPA, based on TOXB, were extracted from 2D
MEDICI simulations [Yeh96]; they are given in Table 3.5. Since the UFSOI model
Table 3.5 BOX FringingField Parameters (Extracted from MEDICI)
TOXB (nm)
GAMMA
KAPPA
<50
1.0
1.0
100
0.7
0.9
200
0.5
0.7
350
0.3
0.5
assumes that the FD device is strongly fully depleted (except in accumulation), the
parameters associated with floatingbody effects, such as ALPHA, BETA, TAUO,
JRO, M, LDIFF, and SEFF, are less important for most FD/SOI MOSFETs.
Nonetheless, the transient bipolar effect in the FD/SOI MOSFET can be important in
certain applications, for which the associated parameters must be tuned reliably;
these parameters, JRO, M, SEFF, and LDIFF, can be evaluated from transient
leakagecurrent measurements [Kri96a]. As for the NFD model, several of the
13
AQcf(y) = CofAyof(y) + Â£sAEsf(y)
= CofAygf(y) + (Cof + Cb)AVsf(y)CbAVsb(y)^ (2.11)
Although, no backgate (substrate) depletion is accounted for, we also calculate AQcb
to give another relation between A\/sf and A\(/sb, which will be used later. Similarly,
applying Gausss law to the back gate, with (2.8), (2.9), and A\/sb(y) + A\/ob(y) = 0
derived from (2.3), yields
AQcb(y) = (Cob + Cb)AVsb(y)CbAÂ¥Â¡f(y)AA (2.12)
(ieff and Ex(y)
In order to check the polydepletion effect on carrier mobility, we apply the
polydepletion modeling to the derivation of the low longitudinalfield mobility, leff,
which is dependent of the transverse field in the channel. The insightful analysis
suggests that the polydepletion effect is negligible and the previous model is still
maintained. We demonstrate as follows based on the UFSOI/NFD model,, for which
Vsb = VBS (given condition); such a derivation is applicable to the UFSOI/FD model
as well.
The field dependence of mobility is modeled [Whi80], [Sun80], [Gar87] by
the average of the transverse field as
Meff ~
4
no
l+9Ex(y)
(2.13)
41
UFSOI models which requires minimal knowledge of device structure, measured DC
currentvoltage characteristics of two floatingbody devices having long and short
(target) channel lengths, and a measured gate capacitancevoltage characteristic. The
systematic processbased methodology is amenable to implementation in software
for automated parameter evaluation. (Its use in UTMOST [Sil97] has been effected.)
The methodology is demonstrated here via application to an AMD 0.35pm NFD/SOI
CMOS technology and to an MIT Lincoln Lab 0.25pm FD/SOI CMOS technology.
The demonstration are based on UFSOI/Ver. 4.5 [Fos98b], but the defined
methodology is easily extended to later UFSOI revisions.
3.2 Parameter Evaluation for NFD/SOI MOSFETs
Unlike bulkSi MOSFET models, SOI device models must be properly
calibrated to account for both DC and dynamic floatingbody effects. The charge
based UFSOI NFD model formalism is BiMOS [Kri96a], accounting for parasitic
bipolar features, intrinsically coupled to the MOS analysis, which underlie these
effects. The processbased nature of the model enables a quick preliminary parameter
estimation based on device structure and physics, which facilitates the subsequent
systematic and efficient tuning of a few key parameters via specific device
measurements. The Ver. 4.5 model parameters, along with their descriptions and
typical values for current stateoftheart NFD/SOI technologies, are listed in Table
3.1 [Fos98b],
155
In the saturation region of operation of the DG MOSFET, a high longitudinal
electric field is developed near the drain, which will eventually saturate the carrier
velocity at vsat(eff) (presuming the ballistic limit [Lun97] is not reached). However,
in the future, if Ich >WQc(0)vT (or v(0) > vT) where vT is the thermal injection
velocity, the ballistic limit is reached and hence this limit should be accounted for in
the model later. In this region (VDS > Vj}s(sat))>
(5.39)
^ch _WQc(Le)vsat(eff)
where Le is less than L due to channellength modulation, which will be described
later. For VDS > VDS(sat), Le < L and a highfield region ((Le
which the carrier velocity is vsat(eff). For y < Le, the carrier velocity is still given by
(5.32), and the channel current is defined by VDS(eff) < VDS across the modulated
channel. Forcing current continuity at y = Le by equating (5.37), with VDS replaced
by VDS(eff) and L replace by Le, and (5.39) yields
WHerf(Qc()Qc(L,))
(5.40)
 WQc(Le)vsat(eff).
The diffusioncurrent term (second on lefthand side) is negligible for this condition.
Hence (5.40) gives
Meff
vsat(eff)^e
(5.41)
Qc(0)2(Cof + Cob)
^eff
91
vds (y)
(a)
Vds (V)
(b)
Figure 3.19 IDS VDS characteristics of 0.25 im FD/SOI devices (Stage 6).
(a) nMOS. (b) pMOS.
190
F(Vds, VDS(sat)) = 1 
ln(l+eB(1~VDs/VDS(sal>))
ln(l +eB)
(A. 1)
where B is a constant which controls the stiffness of the smoothing function, has been
used in the new modeling. From the smoothing function, we obtain F = VDS/VDs(sat)
when VDS < VDS(sat), and F = 1 when VDS > VDS(sat). To implement this model,
VDs(Sat) is fifSt solved at the onset of saturation including DICE [Vee88a] by solving
Ich =
Wpeff[Qc(0)Qc(L)]
2LCof(l+a)(^l + P^s^t)j
= WvsatQc(L) ,
(A.2)
and then smoothed as
^DSsat(smoothed) ^ ^DS(sat)) ^DS(sat) (A.3)
The smoothed VDS(sat) is also used to estimate channellength modulation [Vee88a]
by solving
Le = Llcsinh
l
Meff
2v j ^DS ^DSsat(smoothed))
sat c
(A.4)
Eat
SLb
where lc = / r Then, a more accurate VDS(effN is solved based on this
Le substituted into (A.2) for one iteration. Once this VDS(eff) is obtained, the
smoothing function is used again for VDS(eff):
VDSX P(VDS VDS(eff)) VDS(eff)
(A.5)
63
ALPHA, and BETA tuning if no discrepancies are seen in the characteristics;
otherwise some finetuning is needed.
Stage 8
Evaluated Parameters
Measurement Data
Device
RD, RS
IDS vs. VGfS @ low VDS (100 mV)
ShortL
As can be seen in Fig. 3.8. RD and RS are evaluated from the linear region
of the IDS VGfs characteristics where the equivalent ON resistance is given
approximately by
R = Vds RS + RD LDL
ON Ids ~ W WCc((Vofs VT)neff(UO, THETA) '
Since RS = RD due to device symmetry and UO and THETA have been tuned
previously, this evaluation is straightforward without iteration. (Note: Since RS/RD
could have been of some importance in the longL device, UO and THETA can be
finetuned here to sustain the agreement with the longL data.) Hence RS/RD is tuned
as 400 x 10'6 Qm for nMOS and 1100 x 10'6 Qm for pMOS.
Stage 9
Evaluated Parameter
Measurement Data
Device
VSAT
IDS vs. VDS @ low power region
ShortL
Figure 3.9 shows that we can tune VSAT from the Ids'^ds characteristic at
high VGfS with VDS ~ VDS(sat), where the saturation is governed by velocity
97
are physical and processbased, meaning that their key parameters relate directly to
device structure and physics. The parameter evaluation thus can be and should be
done based on knowledge of the SOI technology. The methodology can be defined
with good physical insight to be reliable and much simpler than conventional
parameter extraction, or optimization via leastsquares fits to measured data. Two
examples of application to an NFD/SOI CMOS technology and an FD/SOI CMOS
technology were demonstrated.
Ot HOt ire
104
Figure 4.2 Simulated transient leakage currents and VBS(t) in a DRAM cell.
SOISPICEsimulated transient leakage current components and dynamic body
source bias in SOI/NFD DRAM cell over long time.
73
Table 3.3 Evaluated Key Parameters for AMDs 0.35pm NFD/SOI CMOS Devices
Parameters
nMOS
pMOS
TOXF
7.0 nm
7.0 nm
TOXB
0.36 pm
0.36 pm
TB
0.058 pm
0.058 pm
TF
0.12 pm
0.12 pm
NBL
3.1xl017 cm"3
2.5xl017 cm'3
NBH
5.0xl017 cm'3
4.0xl017 cm'3
UO
800. cm2/V/s
250. cm2/V/s
THETA
2.3x1 O'6 cm/V
1.9x1 O'6 cm/V
VS AT
0.8xl07 cm/s
0.9x107 cm/s
TPG
1
1
TPS
1
1
ALPHA
2.45x106 cm'1
2.45x106 cm'1
BETA
1.92xl06 V/cm
3.0xl06 V/cm
RD
400.X10'6 Qm
1100.x 1 O'6 Qm
RS
400.x 10'6 Qm
1100.x 10'6 Qm
TAUO
1.0x1 O'6 s
1.0x10'7 s
JRO
l.OxlO'10 A/m
l.OxlO'10 A/m
M
1.5
1.5
BGIDL
4.5x109 V/m
4.6x109 V/m
NTR
4.5xl014 cm'3
9.0xl014 cm'3
DL
0.07 (im
0.08 pm
LRSCE
0.0 pm
0.0 pm
SERF
9.0x105 cm/s
7.0xl05 cm/s
NGATE
2.0xl019 cm'3
7.5xl019 cm'3
QM
0.45
0.4
CGFSO
0.245x1 O'9 F/m
0.245x1 O'9 F/m
CGFDO
0.245x1 O'9 F/m
0.245x1 O'9 F/m
158
Avsf(y)VDS(e[f) = ^2Â£smh(^5)
I Mb
where lc = Letting y = L in (5.45) yields
VCof + Cob
LL
e
2Vsat(efL)sinh1
Heff
'MeffC^PS ^DS(eff)^
^vsat(eff)^c
(5.45)
(5.46)
Note the reduced channellength modulation in the DG MOSFET, relative to the SG
counterpart, due to smaller lc implied by the (Cof + Cob) term. Analogous to the
saturationregion modeling for the UFSOI models discussed in Appendix A, we
smooth VDS and L in (5.37) to VDS(eff) and Le, respectively, thus defining a fully
continuous model.
Charge Modeling
The voltagedependent charges, QGf, QGb, Qs> Qd> anc* Qb> fr fiye terminals
of the DG MOSFET must be characterized in order to model the charge dynamics for
largesignal transient simulations. The terminal charges are assumed quasistatic,
and are individually integrated based on spatial dependences in the MOSFET which
follow from the analyses in preceding sections. The charging/discharging current at
each terminal is evaluated by the time derivative of the integrated terminal charge as
dQÂ¡ y>Q dVjS
dt YaVjS dt
(5.47)
with i = Gf, Gb, S, D, B, and j = Gf, Gb, D, B. Charge conservation (or charge
neutrality), which is important for the stability and the convergence of a compact
59
Since TAUO has been initially estimated in Stage 4, we only need to fine
tune the value to negate possible inaccuracies of approximations, e.g., Tr = T The
finetuning serves as a verification of the JROdefined TAUO as well.
Large changes in TAUO should not be allowed here; such changes would
reflect another current component, e.g., due to junction trapassisted tunneling,
which can be used to tune the effective trap density, NTR. Fig. 3.6 shows the refining
of TAUO from IDS VDS characteristics at VDS ~ VDS(saG (no kink) and low VGfs
where IDS(sat) is controlled by pinchoff and where it reflects clearly the threshold
lowering due to the thermal generation currentdriven floatingbody effect. If we see
the current increasing with VDS in this same region, then we will have to tune NTR.
The effects of carrier velocity saturation (VSAT) at higher VGfS, which will be
discussed later, should be avoided here. The values of TAUO and NTR evaluated in
Stage 4 are still valid here.
3.2.3 ShortL Calibration
The parameter set obtained from the longL device tuning is now used to
initiate the tuning from the shortL (target) device. The shortL calibration is similar
to that described for long L, but with some additional parameters. In fact, if longL
data is not available, the calibration could be done with the shortL data only, albeit
with a bit more complexity. Selfheating is usually more prevalent in shortL device
data, so it must be cautiously avoided for reliable parameter evaluation. (The UFSOI
models do have a selfheating option [Kri96a], [Wor98], which uses two additional
parameters (RTH and CTH) that could be tuned. However, a reliable calibration can
5
Because the UFSOI/FD model does not account for the backchannel current in
strong inversion, the use of the model for DG is limited; therefore, the model can
only apply to a small range of operation for asymmetrical DG (e.g., with n+/p+
poly silicon gates) MOSFETs where the back channel does not reach the condition of
strong inversion. However, (near) symmetrical DG (e.g., n+ polysilicon gates for
nMOSFETs) MOSFETs need an extended model which accounts for two coupled
stronginversion channels. Hence, we develop a generic compact model for the DG
MOSFET, beginning with the processbased UFSOI/FD model and extending it to
account for stronginversion charge distribution throughout the thin Si film. The
generic nature of UFDG enables the assessment and comparison of different DG
structures for technology development. More importantly, the compact model is
essential for predicting the potential performance of DG CMOS circuits, accounting
for parasitics. The utility of UFDG is demonstrated in comparisons of both
symmetrical and asymmetrical DG MOSFETs involving device and circuit
simulations.
Appendix A addresses the modeling and implementation of a continuous
drain saturation voltage (VDS(eff)) in UFSOI models, in conjunction with the model
upgrades described in Chapter 2. Due to the piecewiselinear velocity model, a
discontinuity in the output conductance previously existed at the boundary of
saturation and triode regions. Using the continuous VDS(eff) model, with a refined
channellength modulation model, we obtain a unified expression for the channel
current and a smooth transition from the linear to the saturation regions of MOSFET
operation.
168
Table 5.1 UFDG Model Parameters
TPGF
Type of frontgate material
(+1: opposite to body;
1: same as body)

+1
TPGB
Type of backgate material
(+1: opposite to body;
1: same as body)

1
SELFT
Selfheating flag (0: no self heating; 1:
approximate model; 2: full model)

0
Optional Model Parameters
Name
Description
Units
Default
TAUO
Carrier lifetime in lightly doped region
s
Calculated
VFBF
Frontgate flatband voltage
V
Calculated
VFBB
Backgate flatband voltage
V
Calculated
WKF
Frontgate work function difference
V
Calculated
WKB
Backgate work function difference
V
Calculated
FVBJT
BJT current directional partitioning factor
(0 for lateral ID flow)

0.0
RHOSD
Source/drain sheet resistance
n/sq
0.0
fieldrelated parameters, GAMMA and KAPPA, and QM. Note that if TPGF and
TPGB are specified (for polysilicon gates), WKF and WKB (or VFBF and VFBB)
will be calculated based on the assumption of Fermi level in the gate pinned at the
majoritycarrier band edge. For nonpolysilicon gates, the values of WKF and WKB
(or VFBF and VFBB) are needed to obtain a correct threshold. The calibration
methodology is demonstrated here via application to a Purdue selfaligned DG
technology.
Following the methodology for UFSOI/FD model, as described in Chapter 3,
we begin the calibration by defining a preliminary set of model parameters estimated
183
consistently and iteratively. The ultimate version of UFDG will be a compact Poisson
Schrodinger solver via iteration.
The UFDG model was verified and calibrated to numerically simulated and
measured IV data. Comprehensive analyses of various device structures can be done
with UFDG/Spice3 DC and transient circuit simulations, accounting for parasitics.
ACKNOWLEDGMENTS
I extend my sincere appreciation to the chairman of my supervisory
committee, Professor Jerry G. Fossum, for his guidance and support throughout the
course of this work. His great knowledge in semiconductor physics motivated my
devotion to the field of semiconductor devices. He was a role model for me, put
things in proper perspective, and contributed to my positive attitude. I would also
like to thank the members of my supervisor committee (Professors Gijs Bosman,
Sheng S. Li, Kenneth K. O, and Timothy J. Anderson) for their guidance and interest
in this work. I appreciate Mary Fossum, Courtney Feagle, and Erlinda Lane for all of
their help preparing trips for numerous research reviews and conferences.
I am grateful to the Semiconductor Research Corporation, and the University
of Florida for their financial support. I thank Advanced Micro Devices, Texas
Instruments, Purdue University, and MIT for providing much of the data and
information in this work. I also thank Avant!, Silvaco, and Cadence for providing
software support.
I would also like to thank fellow students Srinath Krishnan, Jonathan
Brodsky, Doug Weiser, Duckhyun Chang, Chip Workman, Keunwoo Kim, Yan
Chong, Wenyi Zhou, Mario Pelella, Lixin Ge, Bin Liu, Kehuey Wu, Susan Earles and
Brian Floyd for their insightful and technical discussions and friendships.
11
132
formalism, were done in the UFSOI/FD model for DG MOSFET applications
[Cho98]. For UFDG, the effective mobility in (5.6) is further modified as
io
^f,(,/b) = i + f(ts,) + eEsf/b (5'7)
where 0 is a mobility degradation factor, Esf/b is smoothed to zero to avoid the
possibility of negative mobility due to negative Esf/b, and f(tsi) accounts for the film
thickness dependence, which will be discussed later. In addition, the quantum
mechanical model, which defines a higher effective bandgap and thereby reduces the
weakinversion current as described in Chapter 2, is not applicable to ultrathin Si
films, which can yield significant volume inversion [Bal87] and structural
confinement [Maj98]; therefore, it is not included in UFDG. Later, a new quantum
mechanical model [GeOO] will update the weakinversion current by defining a A\/sf
<0 based on a selfconsistent solution of the Poisson and Schrodinger equations.
For terminal charge modeling, analogous to [Yeh95], QGf, QGb, Qs> Qd> and
Qb are individually evaluated. QGf is calculated based on the surface potential from
the 2D weakinversion analysis. The small channel charge for weak inversion is
ignored and so are the intrinsic components of Qs and QD. The body charge QB is
simply defined as the depletion charge in the Si film, WLqNAtSi. Finally, QGb is
directly obtained from charge neutrality: QGb = (QGf + Qs + QD + QB) Fr
accumulation, we simplify the previous model by assuming that the two gates are
decoupled when either surface is accumulated, and hence the onset voltage for
accumulation is defined as VFBf/b + VBS The accumulation charge is imaged on the
gates:
84
body effects, the body doping and film thickness must be carefully designed to
ensure full depletion of the body over the entire range of anticipated bias.
An additional stage could be inserted here to evaluate BGIDL from the high
Vds ^DS'^GfS subthreshold characteristic included in Fig. 3.15. The evaluation
would follow from simply fitting the GIDL current, usually seen for VGfS < 0 for
nMOS and VGfs > 0 for pMOS. However, the characteristics we have for the FD/SOI
technology do not show much GIDL current, and hence BGIDL is not evaluated.
Stage 2 (optional with TOXF set to electrical gateoxide thickness)
Evaluated Parameters
Measurement Data
Device
QM, NGATE
QjfS vs ^GfS lw ^DS (~0 V)
LongL
From the frontgate CV characteristic, QM and NGATE can be tuned based
on the estimation of capacitance lowering in strong inversion, respectively, as
depicted in Fig. 3.3 for the NFD model calibration. Physically both poly depletion
and energy quantization have influences on capacitances and currents, especially in
the stronginversion regime. Nonetheless energy quantization could be still
important around threshold voltage, and hence can lower the subthreshold current
and increase the threshold voltage. As a consequence, the calibration of subthreshold
current demonstrated in Stage 1 might need refinement. In this example, CV data
are not available, and further QM and NGATE are not important. When they are,
refer to the more detailed discussion of CV calibration in Stage 3 of the NFD model
calibration.
102
capacitive coupling [Kri96a], an increased VBS(t), which underlies the transient
leakage current [Suh96]. (If Vs(t) drops from VDD/2, the increase in VBS(t) is
smaller.) While Vs(t) = 0 V, VBS(t) decays as excess carriers in the body recombine.
When Vs(t) is returned high, VBS(t) will not return to its DC value, but will go
negative in support of carrier generation to replenish the body charge lost due to the
recombination. Because the generation rate is extremely slow, a very long time
would be needed to return to the DC condition. For subsequent normal pulsing on the
bitline then, the carrier generation for Vs(t) high is negligible until the carrier
recombination for Vs(t) low reduces VBS(t) to the point where a steady state between
the recombination and the generation obtains. In this state, VBS(t) fluctuates near its
DC value [Ter96]. To induce significant transient leakage current from this point on,
the bitline would have to stay high for a time long enough (~10 ms) for substantial
body charging (carrier generation) to recur.
For normal operation then, without such long quiescent periods with VBS(t)
< 0, the transient leakage current would not seem to be problematic [Ter96]. To
check this, we ran longtime transient simulations emulating the access mode (with
0.75 V precharging), beginning with a write1 (with the wordline boosted to 2.5 V),
which tends to discharge the body [Suh96], and continuing with successive bitline
pulses (1.5 V to 0.75 V to 0 V). Unfortunately, because of the floatingbody charge
dynamics, we found that such longtime circuit simulations led to prohibitive
truncation error in the numerical integration of charging currents. After some time,
each bitlinevoltage transition tended to erroneously charge the body, resulting in
(after ~10 ps) a steadystate peak value of VBS(t) (~0.5 V) that was well above the
TABLE OF CONTENTS
page
ACKNOWLEDGMENTS ii
KEY TO ABBREVIATIONS vi
ABSTRACT vii
CHAPTERS
1 INTRODUCTION 1
2 MODELING POLYSILICON DEPLETION AND ENERGY QUANTIZATION... 7
2.1 Introduction 7
2.2 PolysiliconGate Depletion 8
2.2.1 Model Formalism 9
2.2.2 Model Implementation and Discussion 20
2.3 EnergyQuantization Effect 21
2.3.1 Model Development 26
2.3.2 Discussion 32
2.4 Verification and Circuit Performance 35
2.5 Conclusion 38
3 UFSOI MODEL PARAMETER EVALUATION: PROCESSBASED
CALIBRATION METHODOLOGY 40
3.1 Introduction 40
3.2 Parameter Evaluation for NFD/SOI MOSFETs 41
3.2.1 Preliminary Model Card 44
3.2.2 LongL Calibration 46
3.2.3 ShortL Calibration 59
3.2.4 Verification (SelfHeating) 66
3.3 Parameter Evaluation for FD/SOI MOSFETs 70
3.3.1 Preliminary Model Card 78
3.3.2 LongL Calibration 80
3.3.3 ShortL Calibration 85
3.3.4 Verification 89
3.4 Summary 94
IV
124
based study can provide good physical insights for SOI CMOS circuit design, due to
the hysteresis, comprehensive and intensive simulations are usually necessary. To
reduce the run time, analytical derivatives needed for the NewtonRaphsonbased
nodal analysis in circuit simulation were incorporated in UFSOI (as described in
Appendix C).
175
Vqs (V)
Figure 5.13 Modelpredicted AC CV characteristics.
Comparison of CGVGS characteristics for asymmetrical and symmetrical
(with near midgap gates)gate DG nMOSFETs. (L = 50 nm, tof = tob = 3 nm,
tsi = 10 nm, Na = 1015 cm'3, f = 100 MHz, VDS = 0 V)
35
junction capacitance becomes important in this region. Also, the gate capacitances is
lowered in strong inversion where the QM effect is modeled and plays an important
role as the gate bias and surface field are increased. This decreased capacitance has
been implicitly modeled as
Ccf dy
dQGf d[WLC0X(VGfS
GfS
dV
(2.55)
Gfs
where
dVSf
dV
> 0 with QM; it was 0 with the assumption of a pinned surface
Gfs
potential. This physical effect consequently implies an equivalent gate oxide (> tof).
However, empirically fitting the electrical oxide without accounting for the QM
effect in the model has no physical meaning and can lead to erroneous calibration.
Another physical effect on carrier mobility can be predicted by this model as
well. In UFSOI models, the fielddependent mobility is modeled as in (2.13). With
accounting for the QM effect, the calculated inversionlayer charge density is less
than that of the classical model, so the electric field (Ex) decreases and the mobility
increases as shown in Fig. 2.4, which agrees with the selfconsistent simulation
[Ohk90]. Although the carrier mobility is higher, the channel current does not
increase accordingly because of the decreased inversion charge. The QM effects
presented here could be more significant as oxide thickness continues to scale.
2.4 Verification and Circuit Performance
In order to verify the models of polysilicon depletion and energy
quantization, an actual calibration to a real technology is demonstrated. A 0.14pm
NFD/SOI technology with tof = 2.5 nm is used for this purpose. Figure 2.5(a) shows
47
heating is less significant for long L and hence can be easily avoided. Since UFSOI
4.5 accounts for carrier thermal generation throughout the channel region, the
parameter evaluation for a longL device, for which such generation can be
significant, can be done easily and reliably. We choose 1.0 (im devices for the long
L calibration.
Stage 1
Evaluated Parameter
Measurement Data
Device
TB
IDS vs. VGfS low VDS (100 mV)
LongL
With the preliminary model parameter set, we can tune TB for subthreshold
slope using the measured Ios'^GfS characteristic at low VDS (no kink) as illustrated
in Fig. 3.1. The subthreshold slope is given approximately as [Suh95a]
SÂ£6(l+g) (3.1)
where Cd s es/TB is the depletion capacitance and Cox = eox/TOXF is the gate
capacitance. We thereby obtain TB = 58 nm for both nMOS and pMOS, which is
consistent with the technology.
Stage 2
Evaluated Parameters
Measurement Data
Device
NBL (NBH)
IDS vs. VGfS @ low VDS (100 mV)
LongL
As illustrated in Fig. 3.2, NBL can be tuned to fit the subthreshold current
from the Ios'^GfS characteristic at low VDS (no kink). The subthreshold current
127
Weak inversion Moderate inversion Strong inversion
Figure 5.1 Modeling approach for the UFDG model.
The model mainly focuses on strong inversion with a newly defined boundary,
VTS.
151
Figure 5.8 Modelpredicted carrier mobility (ieff) versus the electric field.
Modelpredicted electron mobility versus transverse electric field in an
asymmetricalgate DG nMOSFET at low VDS for different Sifilm thicknesses.
194
apply the model to an NFD/SOI technology and check the improvements from the
new model. The simulation results are exemplified in Fig. A.3.
66
saturation and not pinchoff of the channel charge (Qc). In this case, the saturation
current is expressed as [Suh95a]
IcH(sat)=WVSATQc(D (37)
As indicated in the figure, device selfheating can and must be avoided while tuning
VSAT. If VGfS is set too high, then the power dissipation will be too high, and the
selfheating will distort the data as evident in Fig. 3.9; if VGfs is set too low, then
(3.7) will not apply. VSAT is tuned to 0.8 x 107 cm/s for nMOS and 0.9 x 107 cm/s
for pMOS.
3.2.4 Verification (SelfHeating)
After the key parameters have been tuned, both short and longL devices
should be simulated with the single set of model parameters for verification. Further,
the selfheating option [Fos98b] can be turned on for a more comprehensive
comparison, after having evaluated the thermalresistance parameter, RTH, via
tuning to the shortL device in the highpower regions. In general, if the self heating
(AT) exceeds ~20 C, where [Wor98]
AT = RTH P (3.8)
and
P = VDSIDS = ^d'S^ch + Ibjt) + (*ch + ^bjt) (^S + + ^LDS + ^LDd) (3.9)
then selfheating effects should be taken into account. For this technology, with L =
0.35 im, RTH is derived from highP data as 4.5 K/W for nMOS and 2.5 K/W for
15
k = 1 +
2C
ll+^(VGfsÂ¥sf4>fms)
qNpes
Then we rewrite jieff as
'of '"of
+ ^r^AVsf(y) + kAÂ¥s[(y) 
''of Z{~c
tbÂ£sTl
of
(2.19)
(2.20)
For conventional SOI CMOS operation in strong inversion, k is only about
0.1 from the estimation of (2.19), which is negligible compared to the coefficient of
A\j/sf(y). Therefore we can ignore the effect of polysilicon depletion on mobility
degradation and express peff as [Suh95b]
^eff 1B(AV(/Sf)
(2.21)
where
V
no
i +
ecnf/2c.
'Off*
2es vcof
(VsfVsb)F^
Qcf Qb(eff) tbesTl
"of
"of
2C
of
(2.22)
and
^ofMYj Cb^
" 2es^noV Cj
(2.23)
191
where VDSX represents the effective VDS(eff) for strong inversion. The same scenario
is applied to moderate inversion to define strong inversion limits as well. The flow
chart of the new methodology is illustrated in Fig. A.l, and VDS(eff), VDSX, and Le
are shown in Fig. A.2.
A.2 Unifying the Current in Triode and Saturation Regions
The discontinuity of output conductance can be removed by joining the
stronginversion current model. It is convenient to use the smoothed VDS and Le
(smoothed implicitly) to modify the general expression for Ich, following [Vee88a]:
Wpeff[Qc(0)Qc(Le)]
(A.6)
The new model is also used to define the solution at the stronginversion boundary
limit, which then influences the moderateinversion solution via spline interpolation.
The newly upgraded model gives a continuous channel current as well as
related charges in strong inversion, which means the flags in the model source code
for saturation and triode regions (i.e., LLIN and LSAT) can be removed. In addition,
a similar smoothing function used for charge modeling [Cha97] has also been
removed, since the smoothed VDS and Le are already solved in the current model.
Note that the statement to ignore impact ionization in the triode region is not used
any longer, and therefore the impactionization current is always calculated over
strong inversion; this is in fact physical, without an abrupt boundary. We finally
154
dQc = dQc dysf t dQc d\/sb dQc  dQc
dV d\/sf dy + d\/sb dy d\/sf + d\/sb '
(5.35)
Using (5.35) to express Qcd\/ = dQ^/l 2^1 in (5.34) and further replacing ^
d\[/
dy
with Vds/L, we obtain
t ^chMeff ,
^hdy + dv
2v
sat(eff)
= Wfl,
1
dQc ,kBT,. ,kBT Meff VDSJ(^
effCof + Cob 2 W q ^effdQc + W q 2v T dQc
(5.36)
sat(eff)
which can be integrated from source to drain to derive the channel current as
id, =
w^ff(Q(()Qc2(i))
2L(Cof + Cob)l+^)
^ zvsat(eff)'
WkRT
+ LX^ff(Qc(L)Qc(0))
(5.37)
Note that the VDSdependence in (5.37), which was introduced by the noted crude
approximation for ^ in (5.34), is only a secondary dependence. In (5.37),
QC(L) = Qc(0) + (Cof + Cob)VDS, (5.38)
which follows from integrating (5.35) combined with (5.23); Qc(0) is given directly
by (5.23).
Note also that the ydependence of ieff is ignored when integrating (5.36) to
derive the channel current; i.e., the variation of Esf (or \j/), used to characterize le^
in (5.31), is excluded in the integration. Instead, we merely define a representative ie^
at the source.
171
iterative optimization. The evaluated model parameters are listed in Table 5.3.
Table 5.3 Evaluated Key Parameters for the Purdue DG Devices
Parameters
pMOS
TOXF
12 nm
TOXB
12 nm
TB
110 nm
NBODY
2xl016 cm"3
UO
230 cm2/V/s
THETA
0.75xl0'6 cm/V
VSAT
0.45x107 cm/s
TPGF
1
TPGB
1
RD
2000.x 1 O'6 Qm
RS
2000.x 106 Qm
BGIDL
3.15xl09 V/m
DL
0.75 (im
BJT
1
Unlisted parameters are either inapplicable or unimportant, and are set with their
default values. Though we demonstrate the methodology with measured data for two
different devices, the calibration, however, could be done with the shortL data only.
The characteristics reflecting the final calibration of the UFDG model to the
Purdue selfaligned DG technology are plotted in Fig. 5.11. Same device parameters
are used for the two devices, though there might be some process variation, as indicated in
the linear region of longL IDS VDS characteristics, in the technology under development.
Overall the model predictions match the measured data well. With the parameters
95
VDS (V)
(b)
Figure 3.22 Calibrated conductances of FD/SOI nMOS device.
(a) Transconductance; L = 0.25 (im.
(b) Output conductance; L = 0.25 (im.
164
Highfield region (2D)
Figure 5.10 The lateral field in the Si film for an nMOSFET beyond saturation.
120
Figure 4.7 Simulation results of the sense amplifier with nMOS BTS structures.
The sense amplifier is with nMOS BTS structures characterized by RB$ = 750
KO/ No instabilities are predicted as evident in (a). For (b), the distributed
nature the BTS resistance was ignored, and RBS was lowered to 275 KQ/D ,
which correlates with 750 KO/ for the distributed resistance.
169
directly from each device structure. The initial parameter set based on the device
structure for Purdues pMOSFET with n+ poly gates is given in Table 5.2. Using the
Table 5.2 Model Parameters Evaluated Directly from Technology Information
Parameter
Value
TOXF
12 nm
TOXB
12 nm
TB
110 nm
TPGF
1
TPGB
1
W (drawn)
3 pm
L (drawn)
1.2 and 4.2 pm
initial parameter set, we start the systematic methodology for the remaining key
parameters, some of which can also be initially estimated, e.g., UO, THETA, VSAT,
RD, and RS. The methodology is similar to that described for the UFSOI/FD model
in Chapter 3.
Two devices with different channel lengths are calibrated sequentially. Due
to the limited availability of measured data, we choose the 4.2 pm device to
demonstrate the longL calibration and the 1.2 pm device to demonstrate the shortL
calibration. Though the devices are not quite scaled, the important charge coupling
of the DG MOSFET can be predicted, and is useful for calibration. First, we calibrate
to the longL device to tune TB, NBODY, BGIDL, UO, and THETA. (VFBF and
VFBB (or WKF and WKB) might be tuned, especially for nonpolysilicon gates.)
With the preliminary model parameter set, we calibrate to longL devices by tuning
32
of a minimum potential between front and back gates [Cho98]. The weakinversion
2
current of this model is proportional to nÂ¡ and can be updated analogously as our
previous derivation for the NFD model. Based on the upgrades for weak and strong
inversions, the moderateinversion solutions are implicitly influenced via spline
interpolation.
With these upgrades accounting for the quantization effect in NFD and FD
models, the corrected charge and current solutions can be explicitly shown from
device and circuit simulations. In addition, other device characteristics related to
vj/sfS are also modified implicitly such as BJT current [Kri96a], effective gate
capacitance, and mobility degradation [Vee88a],
Charge Modeling
While we simply use the updated ttsfs(VGfs) to account for the QM effect in
charge modeling without any extra upgrade, the displacement of inversion charge
distribution, i.e., centroid, is not included explicitly due to the fundamental model
assumption of charge sheet. However, van Dorts model [Dor94] used here has
implicitly accounted for the increase of the average distance to the interface
compared to the classical solution. Therefore, we are still able to effectively model
the integrated charge density based on Gausss law, which validates the calculations
for capacitances as well.
2.3.2 Discussion
Since we only use the representative surface field without integrating the
whole inversion layer due to the fundamental model assumption, the QM effect on
62
3 xAxxxxcco* 1 1 1
2.0 0.0 2.0 4.0
VGfS (V)
(a)
Figure 3.7 IDS VGfs characteristics of 0.35 im NFD/SOI devices (Stage 7).
(a) nMOS. (b) pMOS.
19
r^'n rsat
^GfS ^GfS + VQfS
(2.35)
3 3
W(L AL)Cof( 1 + )VDsxfS:^Z_~1) + I
(2.36)
.sat
Qch = WALQC(LAL),
(2.37)
,.lin .sat
Qch Qch + Qch
(2.38)
WLCof( 1 + (x')VDSX
2(z l)3 4 z5(z l)5 (uz)
3 2z~ 1 15 (2z l)2 2
(2.39)
(2.40)
+ Qd"
(2.41)
and
Qs = QchQD (2.42)
where Qg"s is the gate charge component between y = 0 to y = LAL, Qq{s is the
gate charge component in the saturation region from y = LAL to y = L, AL is the
modulated channel length in strong inversion [Suh95b], s = iIeffVDS/2vsatL,
z = u (IDSW/2vsat)Cof(1 + ot')VDS, and u = Qcf(0)/(Cof(l + a')VDS).
The charge formalism for the FD model [Cha97] can be updated accordingly.
68
Figure 3.10 Calibrated 1(A) V(V) characteristics of NFD/SOI nMOS devices.
140
2qnfvTesf
= ^^lexp
(5.22)
to be solved with (5.15), using a secondorder Jacobian. We note, however, that the
square terms in (5.22) imply the existence of multiple solutions, which could lead to
nonphysical results, e.g., unreasonable or imaginary numbers, and consequentially
cause numerical errors or divergence. The proper selection of initial guesses for the
Newtonbased iteration is crucial and can help resolve this issue. So, the initial guess
for \/sf is set to be slightly higher than the initial \)/sb, in accordance with the
assumption of a usual front channel. Further, because convergence can be slowed
down or the iteration can be stopped when (exp) overflow or underflow occurs due
to the limited capability of computer arithmetic, we need to limit the maximum
iterative excursion (A\rsf and/or A\/sb) and set solution boundaries. To do so, if the
excursion for one iteration exceeds 5VT, it is limited to 2VT. Also, two fixed
22 2 oo 'x
boundaries for \/sf and \/sb, 1 V and VTln(10 NA/nÂ¡) (based on nlimit=10 /cm ),
are defined, between which the exact solutions for surface potentials should be
found. Otherwise, the same 2VT limit is applied if the solutions from an iteration go
beyond the boundaries. Typically, the number of iterations is less than ten in order
to achieve 1 p.V tolerance.
The solutions for \/sf and \j/sb, as exemplified in Fig. 5.4 for symmetrical (n+
polysilicon gates) and asymmetrical (n+p+ poly silicon gates) DG MOSFETs, will be the
main bases for the model, and hence their derivation is one of the major tasks. As can
be seen in the figure, the slopes of vysf and \j/sb for the asymmetricalgate device are
ideal in weak inversion due to strong charge coupling. Once \j/sf is pinned in strong
67
pMOS. With L = 1.0 pm, RTH is derived as 2.2 K/W for nMOS, and ignored for
pMOS due to less power consumption. Although the selfheating effects can prevail
in the longL device too, they tend to be less significant since RTH varies inversely
with device size.
For a more complete calibration, some parameters may be tuned based on
additional measured data. For example, following [Kri96a] the bipolarrelated
source/drain parameters SEFF and LDIFF can be evaluated from transient Ibjt(0
data. If such transient data is not available, SEFF can also be estimated from the kink
in the Ids'^DS characteristics at lower VGfS where it influences recombination and
hence the kink current level. Finally, by matching the breakdown voltage in the IDS
VDS characteristics, FVBJT and NBH can be tuned.
The characteristics reflecting the final calibration of the NFD model to the
AMD SOI CMOS technology are plotted in Figs. 3.10 and 3.11; the selfheating
option was used in the L = 0.35 pm device simulations. Overall the model predictions
match the measured data well, except for the anomalous leakage currents at VGfs <
0 in Fig. 3.10(d) which, as mentioned previously, could vary substantially in
different devices from the technology. In Fig. 3.10(f), there are discrepancies in the
IdsVds characteristics in and around the kink regions; the data show less abrupt
kinks. The anomalous leakage currents mentioned above, which could become
predominant in charging the floating body, could also underlie these discrepancies.
They might also be due to nearFD conditions induced by the bias. Such conditions
are suggested by the loss of the kink with increasing VGfS shown by the
characteristics in Fig. 3.10(c) for the shortL device, in which source/drain charge
83
VGfS (V)
(a)
VGfs(V)
(b)
Figure 3.15 IDS VGfs characteristics of 0.5 im FD/SOI devices (Stage 1).
(a) nMOS. (b) pMOS.
61
be done without considering selfheating.) The remaining parameters to be evaluated
from the shortL device data are DL, RD, RS, VS AT, and LRSCE.
Stage 7
Evaluated Parameters
Measurement Data
Device
DL, LRSCE
IDS vs. VGfs @ low VDS (100 mV)
and high VDS (2.0 V)
ShortL
If the technology shows significant reverse shortchannel effect (RSCE),
then the effective channel doping in the shortL device will be higher than NBL
obtained from the longL device, and the general validity of the calibration would be
invalidated. Therefore, LRSCE needs to be tuned here to retain the model scalability.
Using the model parameter set we have at this point, we find that the short
L model gives the same subthreshold slope as seen in the lowVDS IDS VGfs data,
which implies good TB. Since, we do not see any RSCE in this example, we hence
can easily obtain DL by fitting the shortchannel effect (DIBL) from the IDS VGfS
characteristics as shown in Fig. 3.7. In other cases, however, the shortL data may
show a higher threshold voltage, implying that RSCE must be accounted for. In order
to evaluate DL and LRSCE independently, we tune (refine) LRSCE to fit the
subthreshold current, which strongly depends upon doping, and we tune (refine) DL
to match DIBL from the IDS VGfs characteristics as shown in Fig. 3.7. (Note that
when LRSCE > 0, NHALO or NBH can affect the effective channel doping through
a physical link modeled in UFSOI4.5.) We obtain DL = 0.07 J.m for nMOS and 0.08
p,m for pMOS, which are consistent with the technology, and LRSCE = 0.0 im for
both nMOS and pMOS. Once DL is tuned, we may skip further NBL, JRO, M,
CHAPTER 1
INTRODUCTION
Silicononinsulator (SOI) complementary metaloxidesemiconductor
(CMOS) has become a promising candidate for future mainstream CMOS
technologies with its superior attributes such as lower parasitic junction capacitance,
immunity to soft error, reduced cross talk and bipolar latchup in circuits, and
simplified processing. Two major types of SOI devices, nonfully depleted (NFD),
or partially depleted (PD), and fully depleted (FD) SOI MOS fieldeffect transistors
(FETs), both showing the inherent SOI superiority over the bulksilicon MOSFETs,
are addressed. However, the NFD SOI MOSFET has its unique floatingbody (FB)
effects, which makes the reuse of design rules from bulksilicon circuits suboptimal.
Further, the FD SOI MOSFET has difficulty in threshold control due to the two
dimensional field effects in the silicon film and buried oxide, and to threshold
sensitivity to film thickness. To exploit the idea of FD SOI with the expectation of
nearideal subthreshold slope and high current drivability, and to scale CMOS to the
end of the SIA roadmap [Sem99], the doublegate (DG) MOSFET is of interest in
spite of the challenging fabrication issues. All of the issues mentioned above must be
examined carefully, and the complicated underlying device physics must be taken
into account in reliable device and circuit design. Hence, compact, yet physical
models are needed for exploring the possible problems and predicting the potential
performance of SOI CMOS integrated circuits.
1
11
the backgate surface potential; eox and es are the dielectric constants of oxide and
silicon, respectively, tof is the front oxide thickness, and tb is the lowdoped film
thickness for NFD SOI or film thickness for FD SOI. Similarly, for the back gate
[Lim83], [Vee88a]:
VGbS = Vsb + Vob + bms
(2.3)
and
(2.4)
where VbFB is the backgate flatband voltage, Cob = eox/tob, and Qcb is the back
gate channel charge; tob is the back oxide thickness. The backgate (substrate)
depletion potential is not accounted for since the back oxide is very thick, and the
field is low compared with that at the front gate. Note that ysf used here for the
derivation of gate depletion has been updated for carrierenergy confinement, as
described later in Section 2.3.
Now, consider the frontgate depletion. Using the depletion approximation
for the polysilicon gate yields
qNPxdP = qNp
(2.5)
where xdp is the depletion width. Applying Gausss law to the front polysiliconoxide
interface with (2.1), we get
46
which is typically 1020% thicker than the physical value, if the polysilicon
depletion and energyquantization options are not used.
Several of the parameters listed in Table 3.1 are either unimportant or
inapplicable for this technology. For example, NQFF is typically low enough that it
is not significant in a scaled technology, and NQFB is generally not critical in NFD
devices. NQFSW can be set to 0 generally, unless narrowwidth effects on threshold
voltage are important, in which case measured data from a narrowW device is
needed for evaluation. We can also assume for the nMOS device that the impact
ionization parameters, ALPHA and BETA, retain their physical values of 2.45 x 106
and 1.92 x 106, respectively, as confirmed experimentally for electrons [Slo87],
[Kri96b]. For the pMOS device, ALPHA and BETA are less important since the
impactionization rate for holes is much smaller than that for electrons; they can be
adequately estimated in the tuning process as we describe. Thus, there are only 17
key parameters that have to be tuned beyond their initial estimated values: NBL, TF,
TB, UO, THETA, VSAT, BGIDL, TAUO, JRO, M, RD, RS, DL, LRSCE, NGATE,
QM and NTR. The overlap capacitances, CGFDO and CGFSO, can be estimated by
calculation (Â£oxDL/2TOXF), but should be tuned based on a measured gate CV
characteristic because of possible nonlinearities and fringing effects. The parameter
tuning is done systematically as detailed in the following sections.
3.2.2 LongL Calibration
First, we calibrate to longL devices to tune TB, NBL, NGATE, QM,
NGATE, UO, THETA, JRO, M, and BGIDL. These evaluations are simplified since
DL, LRSCE, VSAT, RD and RS are not significant for long L. In addition, self
2
This work focuses on upgrades and enhancements of processbased UFSOI
models [Suh95a], [Yeh95], [Kri96a], [Cha97], [Wor98], [Fos98b], with a systematic
methodology for modelparameter evaluation and applications to optimal SOI CMOS
design. Further, it includes the development of a processbased DG MOSFET
compact model (UFDG). The models have been implemented in a TypeI interface
(API) that can be glued to Spice3e2, as used in this work, or to any circuit simulator.
In contemporary CMOS technologies, the device structures have been scaled
down to deep submicron dimensions for highspeed and lowpower applications. As
MOSFETs continue to shrink, more and more previously insignificant physical
device phenomena become important. Compact device models, which involve many
assumptions, must be updated frequently to physically account for such evolution of
the relevant device physics. Polysilicongate depletion and carrierenergy
quantization, both of which reduce the drive current and effective gate capacitance
due to high transverse electric field, are incorporated in UFSOI models, as described
in Chapter 2, to ensure accuracy of scaled device and circuit simulations. We
physically account for their effects, particular for SOI MOSFETs, on surface
potential (threshold voltage), and thus the current (conductance) and charge density
(capacitance) are implicitly updated via the physical nature of the models. Our
simulation results show that the circuit performance is degraded due to these two
effects. In addition to the model upgrades for polysilicongate depletion and carrier
energy quantization, several revisions and refinements of the UFSOI models are
incorporated as well. An important refinement that ensures a smooth transition from
17
where a' = al/(l+ag), asCb/Cof, and ag = Cdgf/Cof.
Next, for the FD SOI model, from (2.12) with AQcb=0, we get the relation
between A\/sf(y) and A\)/sb(y), which in (2.11) gives
AQcf(y) = CofAVgf(y) + Cof( 1 + a)Avi/sf 3Cbtbr/2 (2.28)
where a = CbCob/((Cb + Cob)Cof) and (3 = 1 + Cb/(Cb + Cob), which are slightly
different when accounting for surface states, as included in UFSOI [Yeh96]. Again,
substituting dA\j/gf from (2.25) into (2.28), we can write
dQcf = CofO +')dVSf (229)
where a' = a l/( 1 + ag) with agsCdgf/Cof, which is same as (2.27) but with
different a.
Following the same analysis in [Vee88b] with (2.27) and (2.29) for FD and
NFD MOSFETs, respectively, we modify the channel current as
Ich =
wpeff(Qcf(0) Qcf(Le))
2CofLe(l+a')
1 +
^etf y
2v. JL Vdsx
sat e
(2.30)
where Le and VDSX are effective (smoothed) channel length and VDS, respectively,
in strong inversion (see Appendix A), and jleff = l/(l fBBVDSX) with constant
fB. In addition, VDSX is also a function of a since we calculate VDS(eff) from (2.30)
implicitly in saturation region. Note that the only difference in (2.30) compared with
the previous model without polysilicon depletion is a, which reflects a simple yet
physical upgrade.
24
device modeling, solving the Schrodinger wave function is not preferable, since the
efficiency is one of the most important concerns for circuit simulators. We hence
utilize the physical model presented by van Dort, et al. [Dor94] as our main
reference; this model was intended for numerical device simulators, but the physical
nature of UFSOI enables its use here as well. In van Dorts model, the QM effect is
done by introducing an induced bandgap widening, as discussed earlier, and the
corresponding nÂ¡ is recalculated. Based on this same approach, UFSOI model
formalisms are modified where nÂ¡ is involved.
In UFSOI models, we define three regions, strong, moderate, and weak
inversion, with two boundaries, VTS (between strong and moderate inversion) and
VTw (between moderate and weak inversion), according to the criteria of [Tsi82].
The moderateinversion regime is defined by cubicspline interpolation between the
two boundaries. While accounting for the QM effect for circuit simulation, the
classical MOSFET models, assuming that surface potential is pinned in strong
inversion, become inaccurate and must be upgraded. Therefore, the surface potential
involving nÂ¡ to define VTS must be changed, and then other associated models are
implicitly upgraded as well. Since the impact of quantization effects can be important
somewhat even near the threshold voltage [Har98a], to efficiently model the energy
quantization without losing its physical and realistic meaning, it is accounted for not
only in strong inversion, but also in weak inversion, which then implicitly influences
the moderateinversion solution. Thus, the weakinversion channel current
2
predominated by diffusion, which depends on nj must be updated. However the
198
B
I Neck
Parasitics
Figure B. 1 Layout of an Hgate NFD pMOSFET for experiment.
W/L = 10 (im/9.96 (im, Ws = 0.5 im.
48
2.0 0.0 2.0 4.0
^GfS (V)
(a)
2.0 0.0 2.0 4.0
VGfs (V)
(b)
Figure 3.1 IDS VGfS characteristics of 1.0 im NFD/SOI devices (Stage 1).
(a) nMOS. (b) pMOS.
58
(a)
vGfs (V)
(b)
Figure 3.5 IDS VGfS characteristics of 1.0 Jim NFD/SOI devices (Stage 5).
(a) nMOS. (b) pMOS.
177
(b)
Figure 5.14 Modelpredicted device characteristics vs. backoxide thickness variation.
Simulated (a) Ioff vs. tob and (b) Ion vs. tob for asymmetrical and symmetrical
(with near midgap gates)gate DG nMOSFETs. (L = 50nm, tof = 3nm, nominal
tob = 3nm, tsi = lOnm, NA = 1015cm'3, VDD = IV)
80
NGATE, UO, THETA, VSAT, GAMMA, KAPPA, BGIDL, RD, RS, and DL. Since
the measured data we acquired do not include CV characteristics, we do not tune
QM and NGATE for this example. Actually, since the gateoxide thickness of this
technology is not very thin, these parameters are not really significant. In other cases,
however, if the polysilicon gatedepletion and energyquantization options are
needed, we initially estimate NGATE to be 5.0xl0'19 and QM to be 0.4, where the
latter is based on a general calibration of the UFSOI model to numerically simulated
devices with channel doping in the range 1016 1018 cm'3 [Jal97]. The methodology
for tuning NGATE and QM discussed in the NFD calibration is applicable here as
well. If the noted options are not used, then TOXF is set to the measured electrical
value of the oxide thickness, which is typically 1020% thicker than the physical
value. The overlap capacitances, CGFDO and CGFSO, can be calculated
eoxDL
(=  which neglects possible fringing) or can be tuned from a measured gate
2TOXF
CV characteristic. The other parameters are either unimportant or inapplicable for
this technology. The tuning is done systematically as detailed in the following
sections.
3.3.2 LongL Calibration
Unlike the parameter evaluation for the NFD model, the FD model
parameters can not always be tuned for long and short L sequentially because of the
BOX fringingfield effect. If the subthreshold slope (S) increases abnormally as
channel length is decreased or VDS is increased, then the fringing fields are probably
significant, and GAMMA and KAPPA must be tuned beyond the values in Table 3.5.
In spite of this effect however, other parameters such as DL, RD, RS, and VSAT can
150
the mobility. A wide range of film thicknesses and the impact of tsÂ¡ on mobility are
hence empirically, but properly accounted for in the model. Although we do not
introduce any new parameter, the factor 10 in (5.29) and (5.30), defined as a
transition point, could be an optional parameter for different technologies.
Now, following (5.27) with the updated xb' in (5.28), we find a new average
momentumrelaxation time (x). Next, substituting the updated (x) into (5.26), in
conjunction with (5.25), yields
Heff
Ho
l+f(tSi) + 0Esf
(5.31)
where from UFDG Esf is used for simplicity; p,0 = q xb/m and 0 are now model
parameters to be tuned based on measured data, although they are physicsbased and
representative values can be defined, as demonstrated in Chapter 3. In essence, this
mobility model is very similar to the conventional one, but it contains an additional
dependence on Si film thickness. The mobility degradation due to the highfield
effect is still present in the model. For thick tSi, f(tsi) approaches zero, and (5.31) and
(5.25) are equivalent.
A symmetrical DG nMOSFET with various film thicknesses and 3nm gate
oxides is used to examine the capability of the model. As illustrated in Fig. 5.8, the
mobility degradation due to the phonon scattering is greater for thinner films because
more phonons can assist carrier transitions in which the carriers are confined in a
quasi2D system [Gam98], [Pri81], [Tam93]. For high fields, however, the surface
scattering becomes predominant for all tSi. According to (5.31), we can change lG to
control lowfield mobility in thick films, which is governed by scattering rate in the
134
Gb
Figure 5.2 Crosssectional view of a DG nMOSFET.
The structure shows an example of an asymmetricalgate device, which has
different types of gates. The gates can be also identical for a symmetricalgate
device. For the general DG device structure, the gate workfunction (0Gf/b)can be
arbitrary.
APPENDIX C
ANALYTICAL DERIVATIVES FOR UFSOI SPEEDUP
As discussed in Chapter 4, simulationbased studies using physical UFSOI
can give insight for predictive circuit and device design. Due to the history
dependent FB effects of SOI CMOS circuits, comprehensive but intensive
simulations are usually necessary. To develop a compact model for NFD SOI CMOS
circuits, the model efficiency becomes a substantial issue and should be accounted
for. In this work, approximate analytical derivatives are first time shown to be viable
for the physicsbased model having nonclosedformalisms.
In order to reduce run time, approximate analytical derivatives, needed for
NewtonRaphson (NR)based nodal analysis in circuit simulations, are incorporated
in UFSOI, which used difference approximations, e.g.,
Mch
^VGfS
AI
ch
AV
GfS
(C.l)
that require four extra calls of the model routine (with AVGfs, AVDS, AVBS, AVGbS)
for each call by the nodal analysis.
C.l Modeling Approach
For a nonlinear system, derivatives are required for finding the solution via
a NRbased iteration. However, it is not necessary to use exact derivatives;
203
199
VEB (V)
Figure B.2 Gummel plot of an Hgate NFD pMOSFET for experiment.
W/L = 10 pm/9.96 pm, Ws = 0.5 pm.
71
(a)
1.5e02
5.0e03 1 1 1 1 1 1 1
0.0 1.0 2.0 3.0 4.0
VDS (V)
(b)
Figure 3.12 Calibrated conductances of NFD/SOI nMOS device.
(a) Transconductance; L = 0.35 im.
(b) Output conductance; L = 0.35 p.m.
200
where the factor 0.345 follows the distribution factor of transmissionline theory, and
the factor 2.4 accounts for the extra neck resistance indicated in Fig. B.l. We thereby
obtain pB = 2.6 KQ/D, which is close to its theoretical value estimated from doping
and carrier mobility. Based on the understanding of the nonideal body tie with its
parasitics, we should be able to design around it.
B.2 Preliminary BodyTiedtoBody SOI CMOS Simulations
Since the body tie is a common solution to prevent significant dynamic body
charging and hysteresis in NFD SOI CMOS logic circuits, a good bodytied SOI
CMOS circuit design yielding minimal performance loss is of interest. Hence, a new
concept of bodytiedtobody SOI CMOS is proposed here.
The structure of BTB SOI is plotted in Fig. B.3(a); nMOS and pMOS bodies
are tied via finite resistance RB in inverter structure. Additional leakage current via
Rb is also investigated, as shown in Fig. B.3(b). In fact the leakage current through
Rb is negligible, but RBdefined VBSs control the predominant channel leakage
currents. A proper Ioff should be ensured within possible range of RB and VDD.
Basically, low VDD makes this design viable by reducing the pn junction leakage via
Rb, lowering RBdefined VBS, and hence inducing less channel leakage currents.
It is of interest to see the circuit performance with this new structure. We
start with a calibrated 0.14p.m NFD/SOI CMOS inverter ring oscillator with
VDD = 1.2 V. From the preliminary results, as listed in Table B.l, the BTB SOI
circuit shows less hysteresis because the body tie provides the exchange
(recombination) of excess body charges which can cause the transient steadystate
4 DESIGN ISSUES AND INSIGHTS FOR LOWVOLTAGE HIGHDENSITY
SOI DRAM 98
4.1 Introduction 98
4.2 Dynamic Data Retention 99
4.3 Sense Amplifier Operation 108
4.3.1 Overview of the Sense Amplifier 109
4.3.2 Dynamic Instabilities 112
4.3.3 Designs to Avoid Instabilities 116
4.4 Conclusion 123
5 COMPACT DOUBLEGATE MOSFET MODEL 125
5.1 Introduction 125
5.2 UFDG Development 126
5.2.1 Regional Modeling 126
5.2.2 WeakInversion Formalism 130
5.2.3 StrongInversion Formalism 133
5.2.4 ModerateInversion Formalism 165
5.3 Model Demonstration and Verification 165
5.3.1 Model Calibration 166
5.3.2 Model Corroboration 173
5.3.3 Device/Circuit Application 176
5.4 Conclusion 181
6 SUMMARY AND RECOMMENDATIONS FOR FUTURE WORK 184
6.1 Summary 184
6.2 Recommendations for Future Work 187
APPENDICES
A MODELING AND IMPLEMENTATION OF THE CONTINUOUS DRAIN
SATURATION VOLTAGE IN UFSOI MODELS 189
B ASSESSMENT OF NOVEL BODYTIEDTOBODY SOI CMOS 196
C ANALYTICAL DERIVATIVES FOR UFSOI SPEEDUP 203
REFERENCES 207
BIOGRAPHICAL SKETCH 215
v
143
Figure 5.5 Modelpredicted (normalized) inversion charge versus gate bias.
Comparison of inversion charge for asymmetricalgate DG and SG (back gate
grounded) nMOSFETs.
22
VDS (V)
VGfs (V)
Figure 2.2 Simulated device characteristics of an NFD/SOI nMOSFET.
(a) IDS VGfS characteristics, (b) CGfVGfs characteristics.
20
Boundary of Strong Inversion (VTS)
Since we do not have an explicit relation between \j/gf and the lower limit of
stronginversion, \/sfS [Tsi82], the modified VTS accounting for polysilicon
depletion could be approximated by one iteration. To start the calculation, we first
define an ideal VTS f(VGfS)) with the original \j/sfS; then we solve for \j/gf from
(2.7) with values of VGfS and \/sf replaced by VTS and \/sfs, respectively. The second
iteration of VTS is done by adding this V/gf to VTS. However, the iterative solution
may be inefficient. Polysilicon depletion is typically more important in the strong
inversion region due to high surface field, but it could be still negligible around the
lower limit of strong inversion. In addition, the simulations suggest that the IV and
CV characteristics with the new VTS do not show any significant differences from
those with the original VTS; VTS changes by ~5%, resulting in ~1% change in IDS
when VGfS = VTS, and no change in IDS in deep strong inversion. Therefore, the
original VTS definition without iteration is still applicable.
To ensure the continuity between moderate and stronginversion, the
solutions of the model calculated at VTS for spline interpolation have to be updated
with our analysis for polysilicon depletion as well, though we know the depletion
effect could be still small around VTS.
2.2.2 Model Implementation and Discussion
This physical model has been implemented in UFSOI [Fos98b] without any
additional parameter since NGATE ( = NP) is already a parameter. All the model
upgrades, including current and charge models, are done in strong inversion and at
the upper limit of moderate inversion, since the polysilicondepletion effect is
214
[Vee88b]
[War78]
[Whi80]
[Wor98]
[Yam95]
[Yeh95]
[Yeh96]
[Yos97]
S. Veeraraghavan, Modeling SmallGeometry SilicononInsulator
Transistors for Device and Circuit ComputerAided Design, Ph.D.
Dissertation, University of Florida, Gainesville, 1988.
D. E. Ward and R. W. Dutton, A ChargeOriented Model for MOS
Transistor Capacitance, IEEE J. SolidState Circuits, vol. 13, p. 703,
October 1978.
M. H. White, F. Van de Wiele and J.R Lambot, HighAccuracy MOS
Models for ComputerAided Design, IEEE Trans. Electron Devices, vol.
27, pp. 899906, May 1980.
G. O. Workman, J. G. Fossum, S. Krishnan, M. M. Pelella Jr., Physical
Modeling of Temperature Dependences of SOI CMOS Devices and Circuits
Including SelfHeating, IEEE Trans. Electron Devices, vol. 45, pp. 125
133, January 1998.
Y. Yamaguchi and Y. Inoue, SOI DRAM: Its Features and Possibility,
Proc. IEEE Intemat. SOI Conf., pp. 122124, October 1995.
P. C. Yeh and J. G. Fossum, Physical Subthreshold MOSFET Modeling
Applied to Viable Design of DeepSubmicron Fully Depleted SOI Low
Voltage CMOS Technology, IEEE Trans. Electron Devices, vol. 42, pp.
16051613, September 1995.
P. C. Yeh, Modeling and Design of DeepSubmicron Fully Depleted
SilicononInsulator Complementary MetalOxideSemiconductor for
LowVoltage Integrated Circuit Applications, Ph.D. Dissertation,
University of Florida, Gainesville, 1996.
M. Yoshimi, M. Terauchi, A. Nishiyama, O. Arisumi, A. Murakoshi, K.
Matsuzawa, N. Shigyo, S. Takeno, M. Tomita, K. Suzuki, Y. Ushiku,
and H. Tango, Suppression of the FloatingBody Effect in SOI
MOSFETs by the Bandgap Engineering Method Using a Sij.xGex Source
Structure, IEEE Trans. Electron Devices, vol. 44, pp. 423430, March
1997.
26
2.3.1 Model Development
This quantization model is implemented in both FD and NFD models; the
original models related to this topic should be revisited and upgraded. First, we begin
the model development with the discussion of van Dorts model [Dor94], where the
QM effect is modeled by calculating the effective intrinsic carrier density (nÂ¡^M)
corresponding to the bandgap widening:
(2.43)
nÂ¡exp
2kBTj
(2.44)
where AEg represents an effective bandgap widening, (3 (= 4.1 x 10'8 eV cm) is a
constant determined by fitting measured threshold voltage shifts at high doping
levels [Dor92], Exfo (V/cm) is the vertical surface electric field, and QM (= QM) is
a new model parameter which can be set up as a flag (0 = OFF) or can be tuned to
give a better fitting for different technologies. The main reason to add this new
parameter is because that, for rigorous modeling, we need to accurately consider the
variation of Esf(x) and nÂ¡(x) at each point inside the inversion layer, which is
impractical for this model implementation. Though (3 was originally determined for
electrons, i.e., for nMOS [Dor92], other published data show that it is very close to
the extracted value for holes obtained by fitting the modelpredicted results to
experimental and to selfconsistently simulated data as well [Har97], [Jal96]. Thus a
unified model can be applied to both p and ntype MOSFETs. We demonstrate how
121
Since BTS appears to be a pragmatic solution to the instability problem in
the sense amplifier, we used SOISPICE to check sensitivity of its efficacy (in nMOS
only, with pMOS floating) to common process/circuit variations. We show in Table
4.2, for different ambient temperatures, the predicted critical (maximum) value of
Table 4.2 SOISPICEPredicted Sensitivity of Critical BTS Sheet Resistances
SOISPICEPredicted Sensitivity of (WorstCase) Critical
BTS Sheet Resistance Needed for SenseAmplifier Stability
Subject to Common Process/Circuit Variations
CBl (fF)/Rows
Ln (ftm)
Temperature (C)
RBS(crit) /scl)
62.5/128
0.24
25
2750 M
125/256
0.24
25
500 M
250/512
0.24
25
275 K
500/1024
0.24
25

250/512
0.264
25
200 K
250/512
0.216
25
500 K
250/512
0.24
75
600 K
250/512
0.24
125
5 M
BTS sheet resistivity, RBS(crit)> needed to suppress the instabilities, corresponding to
variations in the bitline capacitance (CBL) and in the nMOS channel length (LN). For
this sensitivity analysis, we ignored the distributed nature of the BTS resistance; so
the RBS(crit) values given are, in a sense, worstcase, but the sensitivities implied are
representative. The sensitivities are consistent with the fact that the instabilities that
occur for RBs too high (>RBS(Crit)(W/L)) are due to the dynamically induced N1N2
Vbs and VT imbalances as we previously described. The variations in CBl in Table
136
2
ni / xi/Tx)^
where n = exp is modeled classically and nondegenerately for now;
ma v vT y
VT = kBT/q is the thermal voltage. In writing (5.13), we have assumed a volume
inversion condition [Bal87], which allows carriers to be anywhere in the thin Si film
(and which is consistent with the mentioned quantummechanical analysis). Fermi
Dirac distribution and effects of carrier degeneracy will be discussed later in
conjunction with the quantummechanical iteration and the 2D density of states of
the confined electrons. Multiplying both sides of (5.13) by 2(d\//dx)dx and
integrating from the back surface to the front surface, we obtain
2qnÂ¡ rVsr
Lf
a J\ L
esNAJVsb
exp
2qnfvT/
^rlexp
(5.14)
which provides a useful relationship between electric fields and surface potentials in
an analytical form. However, (5.14) still can not be solved analytically. To simplify
this analysis, we include an approximation for (5.10) as another coupled equation to
be solved.
For a compact model, we need an approximation for the integral in (5.10)
because numerical integration is inefficient and is impractical. We thus assume a
prevalent front channel for this analysis, treating the condition of the back channel
as strong inversion for symmetrical devices or weak inversion for asymmetrical
devices. Furthermore, we note that main components of [S'Edx in (5.10) are defined
Jo
where significant inversion charge exists, as revealed by MEDICI [Med99]
simulations exemplified in Fig. 5.3. Relying on physical insight attained from these
simulations, we approximate the integral of (5.10) as
38
its AC floatingbody CV calibration and the counterpart of old simulation as well.
Significant capacitance degradation is predicted for this scaled technology.
With regard to circuit application, it is worthwhile to investigate the effects
predicted by the new models on circuit performance. We simulate an unloaded 9
stage CMOS inverter ring oscillator (L = 0.35 (im) with different gate dopings, and
repeat the simulation without the QM upgrade for comparison. As shown in Fig. 2.6,
QM and polysilicondepletion (lower gate doping) effects tend to slow down the
circuit speed, whereas the circuit consumes less power due to degraded drive current
predicted by powerdelay product.
2.5 Conclusion
Polysilicongate depletion and carrierenergy quantization were
incorporated in the UFSOI models. From the model applications to circuits, we
observed that they can be beneficial due to lowered effective gate capacitance, and
also can be undesirable due to degraded current drivability. To scale device properly,
some related factors like gate oxide thickness, channel doping, as well as applied bias
must be considered and investigated in depth based on the limitations due to
polysilicon depletion and QM effects. We can further apply the upgraded UFSOI
models to gain physical insight into the behavior of scaled SOI MOSFETs in
integrated circuits, and to facilitate optimal circuit and device design with better
prediction of device characteristics and circuit performance. Additionally, an
important model refinement that ensures a smooth transition from the linear to the
saturation regions of MOSFET operation was developed (in Appendix A).
119
shorted the body terminal of the middle submodel to the source. The results,
exemplified in Fig. 4.7(a) for the same read0/readl/read0 sequence as in Fig. 4.6,
suggest that the instabilities can be avoided even with crude BTS structures; i.e., very
high values of RBS will suffice. For the nominal transistors characterized in Table
4.1, our simulations predict that RBS = 750 KQ/D for nMOS ties is low enough to
suppress the instabilities: contrast Fig. 4.7(a) with Fig. 4.6(a). This sheet resistivity
is more than an orderofmagnitude higher than what can be achieved with relatively
simple BTS structures [Suh94a], and suggests that the simple linkedbody [Che96],
or BC [Koh97] structure is a viable option. Crude body ties are effective in the sense
amplifier because they enable relatively quick body charging when VBS(t) < 0, and
hence prevent the dynamic VBS imbalance that obtains during the precharge period
as we described with reference to Fig. 4.6. Because of the distributed BTS resistance,
VBS varies along the width of the transistor; so we illustrate, in Fig. 4.7(b), the noted
prevention of the imbalance by comparing VBs(t) of N1 and N2 derived from a
simulation in which a lumped BTS resistance (=RBS(W/L)) is assumed. (We note that
ignoring the distributed nature of the BTS resistance in the senseamplifier
simulations implies a smaller critical value of RBS (275 KQ/D), but one that
correlates with the actual value for varying device/circuit conditions.) We stress that
the elimination of the initial nearDC imbalance seen in Fig. 4.7(b), which in fact can
be done with much larger RBS, is not the reason for the suppression of the instability.
Other simulations with RBS > 275 KQ/D predict the instability even though there
is no DC imbalance.
206
benefits for DC and transients simulations are shown in Table C.l with the original
Table C.l UFSOI/NFD Run Time (Normalized)
Simulation
Ver. 4.5
(w/ difference
approximations)
Ver. 4.5F
(w/ analytical
derivatives)
Ver. 5
(w/ analytical
derivatives
except VBS)
DC (IdsVm)
1
0.29
0.52
DC (IDSVGS)
1
0.25
0.51
Transient
(CMOS Inverter)
1
0.33
0.56
upgrade including VBS derivatives for comparison. Note that the Ver. 5 [Fos99] of
UFSOI takes slightly longer time due to other added models. Dramatic speedup is
anticipated (~2x), which would make the processbased UFSOI/NFD model more
generally applicable for circuit design as well as IC TCAD.
74
Figure 3.14 Predicted and measured delay of a NFD/SOI CMOS inverter RO.
The simulation was done without further parameter evaluation for transient
measurement.
49
2.0 0.0 2.0 4.0
VGfS (V)
(a)
2.0 0.0 2.0 4.0
Vofs (V)
(b)
Figure 3.2 IDS VGfS characteristics of 1.0 Jim NFD/SOI devices (Stage 2).
(a) nMOS. (b) pMOS.
72
VDS(V)
(b)
Figure 3.13 Calibrated conductances of NFD/SOI pMOS device.
(a) Transconductance; L = 0.35 (im.
(b) Output conductance; L = 0.35 ^tm.
146
Vqs (V)
Figure 5.7 Predicted inversion charge densities for equal threshold voltages.
Asymmetricaldevice charge, in only one predominant channel, is comparable;
due to extended GfGb charge coupling and the reverse inversionlayer
capacitance effect [KimOl].
28
where NBL is the channel doping, 2
VT = kBT/q is the thermal voltage. (The factor 10 in (2.47) has been modified to 6
to make the transconductance smoother in moderate inversion in UFSOI/Ver. 4.41
due to spline interpolation.) Note that the new nÂ¡^M in (2.46) and (2.47) is a function
of gate bias, and must be updated accordingly through iteration, which we will
discuss later. Equation (2.46) was derived from the integration of Poissons equation,
d Vsf q
dx2 es
+
npM
N
exp
BL
(2.48)
over the predominant inversion layer, with nÂ¡^M assumed to be independent of x.
Now, to properly incorporate nÂ¡^M into this evaluation, we first need to
obtain nÂ¡^M by solving (2.43) and (2.44) with given Exfo defined as
Exfo
eox(^GfS^ FBtl/sfs)
lof
(2.49)
Note that the frontgate depletion potential (\/gf) is ignored in (2.49) because it is
relatively smaller than \]/sfS, and also \/gf is calculated after \j/sfS is defined in the
model routine. In order to obtain l/sfS, a few iterations (usually about 5) are required
through (2.43), (2.44), (2.46), (2.47), and (2.49), and then VTS can be defined with
the final solution of \/sfS [Suh95a], However, as indicated in (2.49), such VTS can
vary with gate bias, i.e., VTS increases as VGfs increases, and it is not stable and
adequate. Therefore, we need a true and VGfSindependent VTS as a fixed boundary
to ensure the continuity over moderate and stronginversion regions.
CHAPTER 3
UFSOI MODEL PARAMETER EVALUATION: PROCESSBASED
CALIBRATION METHODOLOGY
3.1 Introduction
The UFSOI FD [Yeh95] and NFD [Suh95a] MOSFET models are physical
and processbased, meaning that their key parameters relate directly to device
structure and physics. The parameter evaluation thus can be and should be done
based on knowledge of the SOI technology [Kri96a], A unique processbased
calibration methodology, which reliably links the physical models to the measured
device characteristics instead of fitting the model simulations to the experimental
data, is introduced in this work. The methodology should include some tuning of
particular parameters based on electrical measurements of devices having more than
one channel length and width in specific bias regions. Also, it can be defined with
good physical insight to be reliable and much simpler than conventional parameter
extraction, or optimization via leastsquares fits to measured data. In fact, such a
processbased methodology, in contrast to optimization of empirical parameters via
curve fitting [FunOO], seems essential for reliable SOI model calibration because of
complications due to device selfheating and dynamic floatingbody effects [Jen96],
More importantly, the UFSOI models then have some predictive capability.
This chapter extends and refines the parameterevaluation algorithm
described in [Kri96a], yielding a straightforward calibration methodology for the
40
57
induced floatingbody effect on offstate current as well as subthreshold kink as
indicated in Fig. 3.4(a). Furthermore, it can undermine the accuracy of calibrated
parameters. Therefore, BGIDL and NTR for nMOS were evaluated using the short
L device Ios^^GfS characteristic, as shown in Fig. 3.7(a).
Stage 5
Evaluated Parameters
Measurement Data
Device
UO, THETA
Ids VGfÂ¡ @ low Vds (100 mV)
LongL
From the Ios'^GfS characteristic at low VDS, UO and THETA can be tuned
directly, as indicated in Fig. 3.5, since RD and RS are not significant here for long
L. The low (longitudinal)field mobility is dependent on the transverse field (Ex) in
the channel, which is modeled by the average field as
Meff ~
UO
1 + THETAEx(y) '
(3.5)
In this calibration, some iterations are required, but the optimization is not complex.
(An alternative methodology that can be used is based on gmVGfs at low VDS, as
shown in Fig. 3.12(a) and Fig. 3.13(a).) The calibration should be precise here, even
though the shortL tuning will alter the parameter values somewhat. We obtain UO
= 800 cm2/V/s and THETA = 2.3 x 106 cm/V for nMOS, and UO = 250 cm2/V/s and
THETA = 1.9 x 1 O'6 cm/V for pMOS.
Stage 6
Evaluated Parameter
Measurement Data
Device
TAUO, NTR
Ids vs Vds@ Iw VGfs (~1 V)
LongL
70
sharing could be supporting full depletion of the body. Figures 3.12 and 3.13 show
corresponding simulated and measured conductances; the agreement is very good,
although the predicted kinks in gm are too sharp as in Figs. 3.10 and 3.11. The nMOS
and pMOS model parameters derived for the target channel length are listed in Table
3.3. Unlisted parameters are either inapplicable or unimportant, and are set with their
default values. With the parameters evaluated and tuned as described herein, the
UFSOI NFD model should reliably predict not only the DC but also the transient and
AC characteristics of devices and circuits from the AMD 0.35im SOI CMOS
technology.
To exemplify the predictive capability of the model with this processbased
methodology, we use a 151stage floatingbody NFD/SOI CMOS inverter ring
oscillator for verification. The circuit was build on a 0.14 im NFD/SOI CMOS
technology. Following the methodology described in this chapter, the model
parameters were systematically evaluated and tuned. Without further parameter
evaluation for transient measurement, we can still predict the inverter delay over a
wide range of supply voltage, as shown in Fig. 3.14. In contrast, empirical parameter
extraction would not be useful for predictive simulation, especially for SOI due to
dynamic floatingbody effects.
3.3 Parameter Evaluation for FD/SOI MOSFETs
The UFSOI model parameter evaluation for FD MOSFETs also exploits the
processbased nature of the model. The methodology is similar to that described for
the UFSOI NFD model. The bipolarrelated and impactionization parameters are
174
VGS (V)
Figure 5.12 Model and MEDICIpredicted currentvoltage characteristics.
Simulated IDSVGS characteristics for (a) asymmetrical and (b) symmetrical
(with near midgap gates) DG nMOSFETs. (L = 50 nm, tof = tob = 3 nm, tsi =
10 nm, and NA = 10*5 cm'3)
lDS (mA/pm) Ids (mA/pm)
34
(a)
(b)
Figure 2.3 Predicted characteristics of an NFD/SOI nMOSFET.
(a) IDS VGfS characteristics, (b) CGf VGfS characteristics (f = 1 MHz).
133
QaCCGf/b = C0f/bWL(VGf/bSOGf/bSVBS),
(5.8)
which is modeled by assuming that is pinned at 0, and then it is added to QGf
and QGb; the total accumulation charge is subtracted from QB via a smoothing
function [Cha97] to ensure a continuous transition.
5.2.3 StrongInversion Formalism
Basic Charge Coupling
The gategate charge coupling is what makes the DG MOSFET unique and,
intrinsically, nearly ideal [Fos98a], Its accounting in UFDG for stronginversion
conditions is based on the solution of the onedimensional (ID) Poissons equation
(PE). Quantummechanical confinement [Maj98], which perturbs the coupling, will
be added to UFDG as an iterative extension. Shortchannel (2D) effects in DG
MOSFETs are prevalent mainly for weakinversion conditions; only channellength
modulation will be accounted for in strong inversion.
For the general DG device (nMOSFET) structure shown in Fig. 5.2, the ID
PE applied to the Si film between the gates,
(5.9)
could be solved numerically. Such solution would show
(5.10)
where \/sf and \/sb relate to the front and backgate voltages via
156
As can be seen in (5.41), the higher vsat(ef^ resulting from velocity overshoot tends
to give a higher VDS(eff> and hence a higher Ich(sat)> until the ballistic limit [Lun97]
is reached.
In order to characterize the channellength modulation, we employ a quasi
2D analysis in the highfield region near the drain, as indicated in Fig. 5.9, analogous
to the analysis for SOI MOSFETs [Vee88b]. Applying Gausss law to the vertical
strip shown in the figure, we obtain
ftbdAE (y)
 Eox^oxt0 y)dy + W^oxt0 y)dy + My L dx = AQc(y)dy (5.42)
0 dy
where the A terms are VDSinduced changes; (5.42) can be further rearranged as
0 dy
= Cof(AVsf(y) ~ AVsf(Le))dy + Cob(Aysb(y) Aysb(Le))dy. (5.43)
d2 fb A,, u dVA't/sf(y) + AVsb(y)^
d7doAv(y)dx=vl2J
Assuming
dAv/(y) dA\/sf(y) ~ dAysb(y)
and
dy
dy
dy
based on gradualchannel approximation, we
simplify (5.43) to
^AÂ¥sf(y) = (C' + Cb)(AVif(y)AÂ¥ (L )). (5.44)
dy Mb
Solving the differential equation (5.44) with boundary conditions
AVs,(Le) = VDS(eff). AÂ¥sr(L) = VDS, and ^Aysf(Le) = implied by
(5.32), we obtain
25
effect of altered VTW due to energy quantization is weak based on simulations, so we
only redefine VTS and skip the similar numerical iteration for VTW.
As the QM effect in the accumulation layer is inconsequential for most of
typical circuit operations, it can be less important than weak and strong inversions in
such region. Besides, the bulk carriers that are not confined in bound states have a
significant contribution to the total accumulation charge, i.e., a large portion of the
accumulation carriers have to be considered as classical particles [Har98a].
Accurately modeling of the potential well in an accumulation layer thus needs to
partition the entire carrier population into the quantum and classical domains
according to the total energy of carriers [Shi97]. However, the carrier partitioning
involves numerical analyses, and seems impractical for compact model application.
While considering the implementation of this effect in a regional compact model, we
can ignore or simplify some unnecessary calculations where the quantization effect
is not or less significant; this is one of the advantages of regional modeling.
Therefore, for UFSOI, the QM effect (involving majority carriers) is ignored in the
accumulation region.
We discuss how we incorporate the newly developed QM model in the
UFSOI models, and how we derive its formalism for implementation in SOISPICE
[Fos98b] (now in a TypeI interface glued to Spice3). We also present AC and DC
simulations accounting for QM effects to check validity of the model, including DC
IdsVgs and ^DS'^DS as we^ as frontgate quasistatic CV simulations. Finally, the
simulations of a 9stage CMOS inverter ring oscillator show the QM effects on
circuit performance, and check the capability of model prediction comprehensively.
88
VGfS(V)
(a)
VGfs(V)
(b)
Figure 3.17 IDS VGfS characteristics of 0.25 im FD/SOI devices (Stage 4).
(a) nMOS. (b) pMOS.
118
conductance of the thin body region, an inherent nonzero resistance exists in actual
ties. The body resistance is distributed, depending on the tie structure, but its
effective value is proportional to W/L and to the sheet resistivity (RBS) defined by
the SOI film conductivity and thickness [Suh94a], To check the efficacy of real ties,
we did a series of SOISPICE simulations of the sense amplifier, assuming different
values of RBS, and in doing so gained insight about how sophisticated the ties have
to be to suppress dynamic instabilities in the circuit. (We noted that the simulations
with body ties were more numerically intensive. We thus had to tighten the SPICE
tolerance parameters (e.g., ABSTOL=lE18) considerably to ensure accurate
results.)
With reference to the ideally tiedbody simulation of Fig. 4.6, we found that
virtually the same results are obtained when all the pMOS bodies float. We further
found that no instabilities occur when the nMOS bodies are tied (shorted) to the
sources, rather that to ground. These results imply directly substantial simplification
of the technology; only nMOS devices need ties, and the ties can be bodytosource
(BTS) [Suh94a], which can be made intrinsically with significantly less area penalty
than for extrinsic ties.
For this simplified design, we next simulated the amplifier circuit for finite
and varying values of RBS. We initially accounted for the distributed nature of the
BTS resistance in the critical transistors (N1 and N2) by partitioning each device
along the width and representing it by five submodels having common gate, drain,
and source, but with bodies separated by the appropriate components of resistance
defined by RBS and the segment widths (W/5). We assumed a central tie, and hence
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207
33
the characteristics of SOI MOSFETs could have been overestimated. Therefore the
calibration of the QM upgrade is important. Furthermore, it should be calibrated
consistently to the numerical device simulation as well as experimental data to assure
reliable simulation.
The calibration of the parameter QM is based on CV simulations with
different channel dopings from 1017 to 1018 cm'3 and oxide thickness of 4 and 14nm
without polysilicongate depletion (assumed metallike) to estimate the threshold
voltage shift (AVT) due to the quantization effect. Also, to ensure no floatingbody
induced errors during this process, we used an ideal bodytied structure for
calibration. Referring to published data [Jal97], QM is optimally evaluated as 0.45
and 0.42 for ntype and ptype channels, respectively, which should be representative
for the physical model. We will use both of these reasonable numbers for QM
simulations in the following applications.
This model is then applied to a 0.35 im NFD/SOI technology with tox = 7
nm technology for demonstration, as shown in Fig. 2.3 including both AC and DC
simulations. We can clearly see the degradations of current drivability and gate
capacitance, and the threshold voltage is raised as well. The QM effects shown here
could be more significant as the gate oxide continues to shrink.
The frontgate CV characteristics are essential for verification of QM
modeling. Note that the very low capacitance in the accumulation region (shown in
both NFD and FD SOI devices) is due to the nature of the floating body in SOI
MOSFETs. Physically, the floating body is capacitively coupled to the gate, but the
hole charge in the body cannot respond at the high frequency; hence the source/drain
