A Comparative Simulation Study of a Modified Homeplug AV PLC System with Novel Adaptive Bit Loading and LDPC Codes


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A Comparative Simulation Study of a Modified Homeplug AV PLC System with Novel Adaptive Bit Loading and LDPC Codes
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Prasad, Gautham
University of Florida
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Gainesville, Fla.
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Master's ( M.S.)
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University of Florida
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Electrical and Computer Engineering
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homeplug -- ldpc -- qc-ldpc -- turbo
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Electrical and Computer Engineering thesis, M.S.
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Data communication through existing power lines has been the subject of much research over the past decade. Different industry collaborations have tried to develop standards for Power Line Communication (PLC) and the HomePlug AV (HPAV) standard has been the most successful so far. HPAV uses Orthogonal Frequency Division Multiplexing (OFDM) to achieve multicarrier modulation and adaptive bit loading on each of these orthogonal sub carriers. Data rates can be improved by using novel adaptive bit loading strategies to exploit the frequency selective nature of the harsh powerline channel. Various bit loading algorithms are simulated and a new algorithm is proposed to boost the data rates. Analysis and simulation results reveal a 43% improvement in the data rates from 34.44 Mbps to 49.39 Mbps for a real powerline channel with an un-encoded BER of 10^-2. HPAV systems also use turbo codes for Forward Error Correction (FEC) as opposed to Low Density Parity Check Codes (LDPC) because of its high performance at low Signal to Noise Ratios (SNR) which is common in longer powerline runs. The successful implementation of turbo codes in HPAV also resulted in IEEE 1901 standards incorporating turbo codes for FEC. However, turbo codes are licensed and usually require a patent fee to be paid for each turbo code enabled product. The objective of this project is to examine whether the unlicensed LDPC codes could be a viable FEC alternative for HPAV systems. Extensive analysis and simulation results are provided to show that the LDPC codes of block length 32400, improve the Bit Error Rates (BER) by 28% even at a low SNR of 1 dB. However, increase in block length is accompanied by higher memory requirement. A simple implementation of low-memory LDPC codes in the form of Quasi-Cyclic LDPC (QC-LDPC) is also discussed. All simulations are run on 10 different real powerline channels with HPAV specifications.
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by Gautham Prasad.
Thesis (M.S.)--University of Florida, 2014.

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Performance Limits and Analysis of Contention-based IEEE 802.11 MAC Shao-Cheng Wang and Ahmed Helmy Department of Computer and Information Science and Engineering, University of Florida (shaochew, helmy} @ufl.edu AbstractRecent advance in IEEE 802.11 based standard has pushed the wireless bandwidth up to 600Mbps while keeping the same wireless medium access control (MAC) schemes for full backward compatibility. However, it has been shown that the inefficient protocol overhead casts a theoretical throughput upper limit and delay lower limit for the IEEE 802.11 based protocols, even the wireless data rate goes to infinitely high. Such limits are important to understand the bottleneck of the current technology and develop insight for protocol performance improvements. This paper uses a queuing system approach to extend the discussions of IEEE 802.11 protocol throughput and delay limits to the situation that arbitrary non-saturated background traffic is present in the network. We derive analytical models to quantify the performance limits for Distributed Coordination Function (DCF) of legacy 802.11a/b/g and Enhanced Distributed Coordination Access (EDCA) of IEEE 802.11e. We find such limits are functions of the underlying MAC layer backoff parameters and algorithms, and are highly dependent on the load that background traffic injects into the network. Depending on the rate of arrival traffic, the packet delay limit may become unbounded such that no delay sensitive services can be operated under such condition. Moreover, we also discuss the effects of different frame aggregation schemes on the performance limits when data rate is infinite. The developed model and analysis provide a comprehensive understanding of the performance limitations for IEEE 802.11 MAC, and are useful in gauging the expected QoS for the purposes such as admission control. Keywords-IEEE 802.11, MAC, DCF, EDCA, Performance Analysis, Non-saturation, Throughput, Delay. I. INTRODUCTION In recent years, the IEEE 802.11-based [1] wireless local area networks (WLANs), namely IEEE 802.11b [2], 802.1ig [3], and 802.1 la [4], have been increasingly popular in providing low-cost high-bandwidth (up to 54Mbps) wireless connections. With the growing demands of higher bandwidth for applications such as high-definition video streaming, network storage, and online gaming, the industry has been working to seek higher data rate (HDR) extensions [5]-[7] to the family of IEEE 802.11 specifications. Earlier this year, IEEE Working Group meeting approved the first draft of IEEE 802.1 In [8], in which the data rate is expected to be as high as 600Mbps. Moreover, the 802.1 In specification adopts the same medium access control (MAC) schemes to ensure backward compatibility with existing IEEE 802.11 specifications. The industry also seeks advancement in providing better Quality-of-Service (QoS) at the MAC layer. A QoS amendment of IEEE 802.11 MAC, IEEE 802.1le [9], aims to provide service differentiations to different traffic types. In particular, the Enhanced Distributed Channel Access (EDCA) contention-based medium access improves the legacy IEEE 802.11 Distributed Coordination Function (DCF) by providing differentiated medium contention opportunities to high priority traffic. Despite the efforts on advancing data rate and QoS of IEEE 802.11, an analysis of theoretical throughput and delay limit was first discussed in [10] by Xiao and Rosdahl. The paper emphasized on the 802.11 MAC overhead effectiveness and proved the existence of theoretical throughput and delay limits for IEEE 802.11 DCF protocol. The authors concluded that, given that the PHY data rate has advanced to infinitely high and only one station transmits in the ideal channel condition, the minimum time required for completing one packet transmission task is bounded by transmission time of PHY and MAC headers as well as MAC layer backoff waiting time, and consequently bounds the maximum achievable throughput and minimum achievable packet delay. In [11], the authors extended the derivation of packet transmission time to consider collisions and backoff freeze in the case that multiple stations transmit in saturation mode. However, the results in [10] and [11] only represent the throughput and delay limit in aforementioned special cases but are unsuitable to real-world scenarios, which typically consist of multiple wireless stations operating in non-saturation mode. Besides, the delay analysis presented in [11] only considers the "medium access delay" and fails to address the waiting time packets spent when backlogged. On the other hand, as the models used in [10] and [11] are only applicable to legacy IEEE 802.11 DCF, it is also important to expand the explorations of theoretical limits to the QoS enhanced IEEE 802.1 le specification. In particular, it is essential to answer the following questions: will the similar performance boundaries exist in the EDCA MAC protocol? If so, how to quantify such boundaries in different prioritized traffic categories and what are the subsequent impacts in fulfilling the QoS requirements promised by IEEE 802.1 le EDCA? Therefore, this paper aims to provide a comprehensive understanding of the performance limitations on throughput and total system delay of both IEEE 802.11 DCF and EDCA MAC protocols with arbitrary amount of saturated and nonsaturated competing traffic. Such analysis is critical and distinct from other IEEE 802.11 performance modeling paper in the sense that it not only pinpoints the performance bottleneck of state-of-the-art IEEE 802.11 technologies but also develops insight for future protocol performance improvements. The key point of this paper is in proposing a queuing system point of view to directly analyze the access dynamics of 802.11 contention-based MAC. Each wireless station is modeled as a queuing system with the packet 1-4244-0419-3/06/$20.00 IEEE 418


generation process as the 'arrival process' and the variable amount of time a packet spends on MAC layer medium contention as the packet 'service process'. The packet throughput and delay bound is then derived with infinitely high operating data rate. The results are validated through extensive simulations under various network loading and operation conditions. The challenges to such analysis are in modeling the dynamic interactions between the arrival pattern of the considered node and the significantly variable amount of network delay incurred by the backoff, collision, and retransmission procedures under different background traffic load level. Our paper makes the following contributions: We construct a lightweight mathematical model for characterizing the throughput and delay limits and performance of contention-based IEEE 802.11 MAC. The proposed model enables us to systematically explore the effects of backoff settings, arrival processes, competing traffic characteristics, and frame aggregation schemes on theoretical throughput and delay limit of different versions of IEEE 802.11 MAC protocols, including legacy DCF and QoS enhanced EDCA. We discover a performance bottleneck of the 802.11 DCF and EDCA that is not explicitly discussed in a quantifiable manner from previous literature: under the presence of background traffic, there is a turning point that packet delay becomes unboundedly high when packets arrive faster than the packet 'service' rate. The rest of the paper is outlined as follows. Section II provides background information for IEEE802.11 MAC standard. Section III describes the queuing system based mathematical model for packet throughput and delay of IEEE 802.11 MAC. Evaluations and simulation comparisons of the proposed model is presented in Section IV. Section V concludes and provides future work directions. II. BACKGROUND In this section, we briefly review the legacy IEEE 802.11 DCF MAC protocol and the enhanced IEEE 802.1le EDCA. We also describe the differences among 802.1 lb, 802.1 Ig, and 802.1 la. We highlight the different backoff settings, including the special protection feature for 802.1lg devices to interoperate with 802.1 lb devices, which affect the derivation of the proposed model. A. DCF and EDCA of 802.11 Standard The DCF of IEEE 802.11 is a "listen-before-talk" medium access scheme based on the Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) protocol. Before initiating any packet delivery, the station detects the wireless medium to be idle for a minimum duration called DCF Interframe Space (DIFS). The station randomly select the backoff timer interval from [0, CW..in] number of slot-time, where slot-time is a parameter depends on the underlying physical layer (PHY), and then enters the backoff process. During the count-down of backoff timer, if the station senses the medium busy, it stops decrementing the timer and does not reactivate the paused value until the channel is sensed idle again for more than a DIFS. At the timer expiration, the station is free to access the medium for packet transmission. AIFS[j] = AlFSnU] AC CWmin CWmax AIFSn *Slot time+SIFS AC BK 31 1023 7 AC-BE 31 1023 3 AlFS[i] AC_VI 15 31 2 AC_VO 7 15 2 DIFS c ~~Cc DIFSSAIFSS COT I Figure 1. IEEE 802.1le EDCA TABLE I. TIMING PARAMETERS OF 802.1 1A, 802.1 IG, AND 802.1 lB STANDARD SlotTime SIFS DIFS TP Tply cwmin Supported Data Bit Rate (Mbps) 54 802.11la 802.1lg (pure/hybrid) 9gs 9gs/20gs 16gs 16gs/lOus 34gs 34gs/50I s 16gs 16gs/72gs* 4gs 4gsI24gs 15 15 t, 48, 36, 24 54, 48, 36, 24, 18, 12,9,6 18, 12,9,6/11, 5.5, 2, 1 802.lb 20pts lOgs 50pts 72gs* 24gs 31 11,5.5,2, 1 Tp: transmission time of physical preambles TPHY: transmission time of PHY header *short preamble mechanism Upon receiving an acknowledgement frame, the transmission is considered successful; the CW is reset to minimum CWmin and the station stands-by for the next packet arrival. The transmission is considered failed if no acknowledgement is received within a specified timeout; the station repeats the backoff process with CW selection range doubled up to maximum contention window, CWmax. If the transmission has been re-tried for up to RetryLimit times, the packet will be discarded and the CW is reset to CWmin. The EDCF is a variant of DCF and provides prioritized Quality-of-Service (QoS) support among different traffic types. Each QoS-enhanced station (QSTA) maps the packets arriving at MAC layer into four different access categories (ACs) and assigns a set of backoff parameters, namely Arbitration IFS (AIFS), CWmin, and CWmax to each AC. As illustrated in Figure 1, each AC uses its own backoff parameters to contend for the wireless medium by the same backoff rules as legacy DCF stations in the previous paragraph. The AIFS [AC], determined by AIFS [AC] = AIFSn[AC]. slot-time + aSIFSTime, replaces the fixed DIFS in DCF. Shorter AIFS[AC] in higher priority AC provides high priority traffic earlier timing to unfreeze the paused timer after each busy wait period. On the other hand, smaller CW sizes probabilistically provide shorter backoff stages to high priority traffic. More detailed description of DCF and EDCF can be found in [2] and [9] respectively. B. IEEE 802.11b, 802.11g, and 802.11a The IEEE 802.1 lb, 802.1 la, and 802.llg are higher-speed physical layer (PHY) extensions of the IEEE 802.11 standard. They all use the same DCF medium access mechanism 419


described in previous section. Note that, on the other hand, IEEE 802.1le is the MAC QoS enhancement amendment to the IEEE 802.11 standard and can be incorporated with any of the three higher-speed PHY extensions. The detailed operational parameter settings of the three versions of standard are summarized in Table I. Compared to IEEE 802.11b, IEEE 802.11a offers higher data rate, shorter PHY header, MAC slot time, and lower minimum contention window. On the other hand, IEEE 802.1lg operates at the same band as 802.1 lb and supports data rates and PHY/MAC parameters of both 802.11b and 802.11a. When there are no 802.11b stations present in the network, all 802.1lg stations utilize the same PHY/MAC settings specified in 802.11a. In the case when 802.1lg stations co-exist with 802.11b stations in the network, 802.1 1g-capable stations shall switch to longer 20ms slot time in order to be synchronized with the timing of 802.1 lb stations. In addition, whenever 802.1 1g-capable stations use OFDM modulated high rate to transmit DATA and ACK frames, a special protection RTS-CTS or CTS-toself exchange formed in 802.11b decodable control frames must precede the data frame in order to ensure interoperability. As we will show later, these parameters have substantial effects in theoretical protocol performance limits. III. ANALYSIS MODEL In this section, we derive the theoretical throughput and delay limit with non-saturation background traffic for IEEE 802.11 DCF and EDCA contention-based wireless medium access methods. We consider the infrastructure Basic Service Set (BSS) scenario, which consists of multiple wireless nodes and a base station connected with wired networks. Following the "best-case scenario" philosophy in [10] and [11], we make the following assumptions: 1) The wireless channel is ideal without errors. 2) All nodes are within "carrier sensing range" of each other. 3) All nodes use the basic access operation (no RTS/CTS) for shorter transmission cycles. The key idea to our analysis is to model the MAC layer timing dynamics, from packet arriving into the sending station until the packet received by the intended node, as a GIG/1 queuing system. The theoretical throughput and delay limit are thus derived with infinite data rate. We will show that, even with infinitely high data rate, the overhead of background packets causing non-negligible amount of time in the backoff stages is the dominant factor that bounds the MAC layer throughput and delay limit. In the extended version [18], we show that our model can also be applied to quantify the throughput and delay performance in practical scenarios such as finite data rate and non-ideal wireless channel. A. Packet Arrivals Depending on the application layer, the traffic arriving at each wireless station can be characterized with different probabilistic models. In our proposed model, we treat the packet arrivals as the 'general' arrival process of GIG/1 queue. For special case arrival process such as Voice over IP (VoIP) with deterministic arrival rate, it can be treated as D/G/1 queue in our model. B. MAC Layer Service Time The packet service time of the proposed model is defined as CBakoff stage j \MM ..... b-C I< Tb.sy Tb.sy T,., Transmission \ by other nodes Collison with other no Backoff stage j +1 f.Z.g-...Z............. S;, *;<5>Ss ...........I........ Tfail T_ Successful ransmission Of the tagged nodes Figure 2. Packet transmission and collision events during MAC backoff MAC layer service time: the time duration from the instant that a packet becomes the head of the transmission queue and starts MAC layer contention backoff process, to the instant that the packet is successfully received or being dropped because of maximum retry limit has reached. As shown in Figure 2, we model MAC layer service time by analyzing the duration and occurring probability of different events take place at backoff stages. 1) When the backoff timer decrements, either no transmission is sensed in the time slot and Tslot (the length of one time slot) elapses, or the slot is sensed busy with TbUsy taken. Here TbUsy is the average time interval the wireless medium being occupied by background traffic transmissions. We define Pbusy be the probability that, at a given time slot, the backoff timer is frozen due to busy medium in carrier sensing. The occurring probability of idle slot is simply 1Pbusy. 2) When the backoff timer expires (i.e. decrements to zero), the attempt of packet transmission might either fail or succeed. In the failure case, which occurs with probability Pfail, Tfail is taken. Note that, in the case of ideal wireless channel, Pfil equals Pbusy because transmission attempt collides only when the slot is supposed to be busy. 3) In the success case, it takes TSUCC for the packet transmission process and then the packet is considered 'served' and therefore departs the queue. The probability of transmission attempt succeeds is simply 1Pfail. Note that we assume that Pbusy (and Pfail) is constant in steady-state and independent of the backoff stages of the node under consideration (i.e. the tagged node). l As a result, nodes can obtain Pbusy (and Pfail) by monitoring the channel activity and gathering the long-term statistics of the ratio that medium is busy over all time slots [12]. Likewise, Tbusy and Tfail can also be obtained by channel activity monitoring. On the other hand, TbUsy, Tfail, and TSUCC can be formulated by considering the frame exchanges and MAC layer timing parameters involved in a successful or collided transmission cycle. For example, TSUCC can be expressed by the duration of DATA and ACK frame for pure 802.1 1a/b/g traffic, or by the duration of CTS, DATA, and ACK frame when the tagged node operates at hybrid 802.1 Ig environment and has CTS-toself protection turned on. In the case when the attempt of packet transmission fails, considering the ACK timeout effect, Tfail is expressed with the longest data frame involved in the collision. Furthermore, the duration of busy slot, TbUsy, can be expressed either by TSUCC when the busy slot is occupied by successful transmission of the background traffic, or by Tfail when the busy slot is occupied by packet collisions. Interested reader can refer to [18] for detailed discussions regarding the 1 Previous work has shown that this assumption has very meager effects on model accuracy [12]. 420


length of successful or collided slots with parameters from different IEEE 802.11 specifications. Finally, note that, with infinitely high data rate, the time duration to carry the payload of CTS, DATA, and ACK frames become infinitesimal. As a result, depending on the network operates in pure 802.11a/b/g, or in hybrid 802.11b/g environment, TSUCCi Tfail, and TbUsy can be expressed by T pure -T pure -T pure succ fail busy (I a) 2TP + 2TPHY + 28 + SIFS + DIFS TI Ig hybrid-T llghybrid T1 Ig hybrid succ fail busy (lb) =Tl + T4j1l + 2T_ + P2T1 ure +3+2SIFS+DIFS where Tp and TPHY is the preamble and PHY layer overhead. SIFS is the mandatory Short IFS inserted between frames. 6 is the propagation delay. C. Throughput and Delay Model of Legacy DCF To derive the throughput and delay of IEEE 802.11 MAC, we need to construct the detailed service time distribution, which will then be applied to standard queuing theory model. In this subsection, we derive the detailed service time distribution by carefully examining the variable amount of time spent on busy and silent slots and the corresponding occurring probabilities throughout the backoff stages. We first define the occurring probability F,J/-k that, in any single backoff stage j with backoff timer selected from 0 to Wj, there are exactly k busy time slots and (n-k) idle slots is, 1 + Fkw.Puy( -Puy WJ O

an upper bound of the system waiting time, W < A''(1)+B"'(1) (10) 2[A' (1) B' (1)]' And hence the upper bound of total system delay is DelayG/GII < B'(1)+W. (11) D. Throughput and Delay Model of EDCA The QoS-enabled IEEE 802.1 le EDCA mechanism provides prioritized medium access by assigning different AIFS and backoff window parameters (CW..in and CWmax) to different traffic categories. In particular, AIFS provides advanced opportunity to high priority traffic to access the medium by shorten the amount of time a station defers access to the channel following a busy time slot. However, AIFS changes the way we construct the occurring probability of busy and idle slot combinations. Therefore, we need to redefine Equation 2. In order to perform theoretical throughput and delay analysis, we again assume the "best-case scenario". That is, we assume that only the tagged node utilize the short AIFS traffic category, i.e. AC_VO or AC-VI with AIFSn=2, while all other competing traffic utilize the AC-BE traffic category with AIFSn=3. In this way, only the tagged node has higher advanced priority to access the medium and thus is considered as "best-case" scenario. Under this setting, what happens in the last backoff time slot of the tagged node decides two different scenarios. 1) When last backoff slot (cw=l) was an idle slot, the transmission is subject to collision. 2) When last backoff slot was a busy slot, the tagged node un-freezes the backoff timer one time slot before all other traffic. As a result, the backoff timer of tagged node expires before all other traffic un-freeze the timer, and thus the transmission is guaranteed to be successful without collision. Here we first consider the case last backoff slot was an idle slot. We define the occurring probability FCCA n-k that, in any single backoff stage j, there are exactly k busy time slots and (n-k) idle slots is, FCC1 i =1 C n-k-lp 1 n p n-2k-I k,n -k W k busy ( busy) (12) 0 < k < (W1 +1)/2-1, 2k +1 < n < W1. Note that this formulation differs from Equation 2 in the occurring probability of idle slots. The very first time slot and the time slots after busy slot always happen before all other traffic with probability 1. The slots other than these special slots and busy slots in Equation 2 are all classified as idle slot with occurring probability (I-Pbusy). We then consider the case last backoff slot was a busy slot. We define the occurring probability FNCJ -k that, in any single backoff stage j, there are exactly k busy time slots and (n-k) idle slots is, FNC k k =1 WCk-l buy (1 Pbusy ) 1

TABLE II TGN USAGE MODELS IN HIGH PERFORMANCE NETWORKS Offered Number of applications in Application Load Traffic TGn1: TGn-2: TGn-3: (MbPS) Type DIGrrAL DIGITAL PUBLIC HOME OFFICE HOTSPOT VoIP 0.096 UDP 3 30 15 Video Conferencing 0.5 TCP 1 10 0 /Video Phone A/V Streaming 2-4 UDP 1 0 10 STDV 4 UDP 1 1 1 HDTV 19.2-24 UDP 2 0 0 Internet File N/A TCP 1 0 10 Transfer Local File N/A TCP 0 10 2 Transfer Pbusy (with unlimited data rate) 0.159 0.217 0.47 50 E a 40 E > 30 a) 20 Q 10 0 0.2 -8-02.1l1b I sy25us 802.11g,hybrid, iong slot, 2 206us 0.4 0.6 0.8 Busyness ratio 802.1 la/g, short slot, TbI ,=90us 802.11g, pure, long slot, TbI ,=90us 802.1le AC_VO TbI ,=90us 802.1le AC-VI TbI ,=90us Figure 3. Average MAC layer service time of different 802.11 specifications of TbU,S, potentially varies about an order of magnitude for different versions of 802.11 standard, impact on throughput and delay limits of IEEE 802.11 MAC protocols. B. MAC Layer Packet Service Time To study the theoretical packet throughput and delay limit of IEEE 802.11 MAC, we first examine the MAC layer packet service time. Note that, even with infinitely high data rate, this is the minimum required time that the packets need to wait during MAC backoff due to finite protocol overhead of background traffic in busy slots. Figure 3 plots the average MAC layer service time of different versions of 802.11 standard in the presence of nonsaturated background traffic. We can see that packet service time of all 802.11 specifications increases with Pbusy. In a network with business ratio Pbusy as low as 0.5-0.6, the MAC layer packet service time can be in the order of tens of milliseconds. As we will see in later sections, this significant amount of medium access time limits the achievable packet throughput and delay of IEEE 802.11-based protocols. Besides, we can refer the MAC parameters and overhead of different IEEE 802.11 specifications in Table I and see such parameters do affect the packet service time significantly. For example, because the minimum contention window (CW.in) of 802.1 ig is only half of that of 802.1 ib, it takes roughly half of the time for a packet from 802.1lg station to be served, compared to a packet from 802.11b station. Due to shorter TbUsy, packet service time of pure 802.11 a/g network is further decreased, compared to 802.1lg station in hybrid 802.11 b/g networks. Moreover, through the medium access advantage of 802.1le AIFS differentiation, the packet service time in 802.1 le networks reduces by an order of magnitude, compare to legacy 802.11 protocols. On the other hand, by comparing pure 802.1lg in long slot and short slot setting, we find it interesting that shorter slot time does not help in reducing the packet service time too much. It is because shorter slot time only saves the time spent in idle slots by couple of microseconds, which are relatively insignificant compared to the duration of busy slots in hundreds of microseconds. From the observations we made above, we find that, through the progression of recent PHY and MAC amendments on 802.11 standard, the minimum medium access time has been reduced significantly. In the following sections, we will 700 600 ; 500 -, 400 300 aD 200 -D 1 00 MTU=2346 bytes 802 .1e, AC VO 802.1le, AC_VI ... 802.1 1 a/g, short slot 802.1 1 g, long slot + 802.1 lb 0.2 0.4 0.6 0.8 Busyness ratio Figure 4. Theoretical throughput limit of different 802.11 specifications examine such effects on packet throughput and delay. C. Theoretical Throughput Limit In this section, we examine the theoretical maximum throughput of different 802.11 specifications with infinite data rate. From previous section we know that, even with infinitely high data rate, there is a minimum medium access time that the packets need to wait during MAC backoff. As a result, the maximum amount of data delivered in a given period of time is bounded by this minimum medium access time and thus a theoretical throughput limit of 802.11 MAC exits. Figure 4 plots the theoretical throughput limits with arbitrary background traffic at different level of busyness ratio. When there is no background traffic, i.e. Pbu,y =0, our result is consistent with the theoretical throughput limit presented in [10]. As Pbusy increases, we can see the maximum throughput decreases exponentially. In a network with Pbusy about 0.5, the throughput limit has decreased for more than an order of magnitude. Moreover, as the latest IEEE 802.1 In proposal aims to provide 100Mbps effective throughput at the MAC layer, our result indicates that theoretically, even with infinite data rate, such goal can only be achieved at the condition that the busyness ratio of the network is less than 0.3 (or 0.2) with 802.1 le AC_VO (or AC-VI) being employed. Such QoS performance boundary is not identified before. D. Theoretical Delay Limit From the results we present above, the existence of finite 423


MAC service time, in the case of infinitely high data rate, bounds the minimum packet delay that can be achieved by IEEE 802.11-based MAC. Moreover, recall from Section III, depending on the type of packet arrival process, additional backlog waiting time will be added to the total packet delay. In this section, by using the queuing system based MAC layer packet delay model, we present the results of theoretical delay limit of different 802.11 MAC specifications in the presence of arbitrary background traffic. Figure 5 shows the theoretical packet delay limit of different 802.11 specifications with infinite operation data rate. Here we use the deterministic arrival process of a G. 711 VoIP application with lOms inter-arrival time as a case study. We can see the delay limits increase exponentially as Pbusy increases. It is because the MAC layer service time increases as the network get busier, and thus increases the backlog waiting time significantly. An observation that worth special attention in this figure is that there is a point where the packet delay becomes unbounded. Recall from the queuing model in Section III, this is because the fact that whenever the queue service time approaches or even exceeds the packet arrival time (i.e. lOms in this case), the queue becomes unable to handle packets in a timely manner, and eventually packets become indefinitely backlogged. The existence of such turning point demonstrates an important performance limitation of 802.11-based MAC: with the presence of background traffic, the packet delay of 802.11-based MAC can be boundlessly high even with infinite operating data rate. Our model identifies a network condition boundary, such as Pbusy > 0.45 for lOms-frame G. 711 VoIP in 802.11b networks, that any delay-sensitive application may never be able to meet the delay requirement beyond such boundary. Furthermore, from previous section we know the MAC layer service time reduces as the MAC parameters, such as CW.in, protocol overhead, and AIFS, improve from 802.1 lb, to 802.1lg, to 802.1la, and then to 802.1le. Therefore, we see the turning point of boundless delay moves toward higher busyness ratio in the same order. On the other hand, we also explore the effects of arrival process on packet delay limits, particularly for the turning point of boundless packet delay. As the packet delay limit of 802.1 le appears to be finite in all level of busyness ratio in Figure 5, we plot Figure 6 for the packet delay limit of prioritized 802.1 le MAC with decreasing arrival time. We can see a turning point of unbounded delay eventually emerges as the arrival time decreases less than 2.5ms. It is because when arrival time decreases, it poses stricter delay constraints to the queue system, consequently results in packet delay limit curve moving toward less busy environments. Out result indicates the performance bottleneck also exists for the latest QoS-enabled IEEE 802.1 le EDCA. E. Model Validation with TGn Usage Scenarios We further validate the accuracy of our model with ns-2 simulations of non-saturated TGn scenarios listed in Table II. With the traffic characteristics specified in Table II, each TGn scenario corresponds with a particular Pbusy value. We collect simulation results of packet delay for G.711 lOms inter-arrival VoIP traffic and compare to the delay derived from the analytical model under the same Pbusy value. Table III shows a close match between our model and simulations (error < 10%). 150 D/G/1 inter-arrival=lOis + 802.11b E 120 CZ 802.11g (in hybrid o 90 802.11b/g network, long slot) CZ 802.la short slot 060 802.1leAC VO D( 30 0 0 0.2 0.4 0.6 Busyness ratio 0.8 Figure 5. Theoretical delay limit of different 802.1 1 specifications 150 802.11eAC_VI, D/G/1 arrival inter-arival=1.5ms u 120 inter-arrival=2.5ms >1 -o 90 60 C 3 a) > 30 inter-arrival=5ms inter-arrival=lOms 0 0.2 0.4 0.6 Busyness ratio 0.8 Figure 6. Theoretical delay limit of 802.1le AC_VI with different arrival process F. Performance Improvements on Frame Bursting and Block Acknowledgement From the observations we made in previous subsections, we know that the major contributor to the delay in 802.11 based networks is the delay introduced during backoff stages. It is especially inefficient in terms of channel utilization that such backoff medium contention has to be repeated for every arriving packet. On the other hand, the amendments of IEEE 802.11 standard specify two frame aggregation schemes to improve channel utilizations by aggregating multiple transmissions in one medium contention, namely FrameBursting (FB) and Block Acknowledgment (BTA). As Frame-Bursting does not require explicit signaling between the source and receiver nodes, it inserts a burst (say, m number) of DATA frames and corresponding ACK frames back-to-back without initiating another round of random backoff to reduce the overhead. Meanwhile, Block ACK further mitigates the inefficiency of protocol overhead by placing a burst of DATA frames separated by a SIFS period without being acknowledged. At the end of the burst, the sender initiates an explicit Block ACK Request (BAR) to enquire the number of frames successfully received by the receiver. The receiver then responds with a Block ACK (BA) frame. The number of frames in BTA burst (say n) is broadcasted by the access point or pre-negotiated between the sender and the receiver. It is obvious that, with the same number of data frames in a burst (m=n), BTA transmits fewer frames and thus saves more overhead compared to FB. Assuming the considered node always has data packets to 424


COMPARISON OF PACKET DELAY FROM MODEL AND TGn-1 802.11b TGn-2 TGn-3 TGn-1 802.11g TGn-2 TGn-3 802.1le, TGn2I AC VI TGn-2 802.1le TGn-I AC VI TGn32 PBUSy 0.159 0.217 0.47 0.159 0.217 0.47 0.159 0.217 0.47 0.159 0.217 0.47 SIMULATIONS Delay (Model) 2.000ms 3.239ms 0.996ms 1.471ms 15.020ms 0.533ms 0.609ms 0.949ms 0.899ms 1.060ms 1.798ms Delay (Simulation) 1.945ms 3.120ms 656.669ms 0.957ms 1.450ms 13.926ms 0.502ms 0.664ms 0.912ms 0.810ms 1.075ms 1.773ms Error (%) 2.75% 3.67% N/A 3.92% 1.43% 7.28% 5.82% 9.03% 3.90% 9.90% 1.42% 1.39% send, we are able to explore the theoretical throughput of legacy MAC with FB and BTA aggregation schemes by slight modifications in Equation 10 Tput B' T +*LDATA M (14) TuFB B'(1) +(Tp + TpHy + SIFS) *2m'(4 TPUtBTA 8 LDATA *fn B'(1)+(TP +TPHy +SIFS)*(n+2) (15) Figure 7 shows the theoretical throughput of Frame-bursting and Block ACK schemes with different burst sizes in the presences of non-saturated competing traffic. In particular, we can see that, with the same burst size m=n=16, the performance improvements from BTA is greater than that from FB in low busyness environments. The difference in throughput improvements between BTA and FB, however, becomes insignificant as the wireless medium becomes busier. It is because the waiting time in backoff contention becomes the dominant factor that limits the theoretical throughput under such network conditions V. CONCLUSION In this paper, we investigate the theoretical limits of IEEE 802.11 MAC throughput and delay performance in the presence of non-saturated background traffic. A queuing system based analytical model is proposed to evaluate the throughput and delay bounded by PHY and MAC overhead and backoff waiting time even the operating data rate is infinitely high. We present a detailed analysis for theoretical throughput and delay limits in different IEEE 802.11 specifications. We identify a performance bottleneck beyond which the packet delay becomes infinitely high. Such bottleneck exists for all IEEE 802.11 contention-based DCF and EDCA MAC protocol, although the exact turning point depends on the packet arrival pattern in consideration. We also show that such theoretical limits are functions of the MAC layer parameters the nodes operate on and the busyness of the wireless medium caused by competing traffic. We study the effects of factors like backoff contention windows, protocol overhead, system slot time, and interframe space time on throughput and delay limits. One of the key observations is that the advanced medium access opportunity enabled by AIFSn in high priority EDCA voice and video access categories is the primary contributor which 180 160 140 0n 120 100 0a = 80 0v HBTA, n=64 BTA, n =16 ....E. FB, nm 16 FB, m=2 + legacy 802.llg 60 40 20 n ~ U 0 0.2 0.4 0.6 Busyness ratio 0.8 1 Figure 7. Theoretical throughput of Frame-bursting and Block ACK schemes with different burst sizes significantly improves the QoS in terms of maximum achievable throughput and minimum achievable delay. The effects of Frame-bursting and Block ACK frame aggregation schemes on packet performance are also discussed. We plan to extend the analytic model to discuss the packet delay performance of Frame-bursting and Block ACK schemes with arbitrary arrival processes. REFERENCES [1] IEEE Standard for Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Sep. 1999 [2] IEEE Standard for Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher Data Rate Extension in the 2.4 GHz Band (802.1 lb), Sep. 1999. [3] IEEE Standard for Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band (802.1 ig), June. 2003 [4] IEEE Standard for Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 1: high-speed physical layer in the 5 GHz band (802.1 la), Sep. 1999. [5] V.K. Jones, R. DeVegt, and J. Terry, "Interest for HDR extension to 802.1la," IEEE 802.11-02-081rO, Jan. 2002. [6] M. Tzannes, T. Cooklev, and D. Lee, "Extended Data Rate 802.11a," IEEE 802.11-02-232rO, Mar. 2002. [7] S. Hori, Y. Inoue, T. Sakata, and M. Morikura, "System capacity and cell radius comparison with several high data rate WLANs," IEEE 802.11-02-159rl, Mar. 2002. [8] HT MAC Specification, Interoperability MAC Specification vI.24, Enhanced Wireless Consortium publication, Jan. 2006. [9] IEEE Standard for Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 7: Medium Access Control Quality of Service (QoS) Enhancements (802.1 le), Jan. 2005. [10] Y. Xiao and J. Rosdahl, "Throughput and delay limits of IEEE 802.11," IEEE Communications Letters, vol. 6, Aug. 2002, pp. 355 357. [11] Y. Xiao and J. Rosdahl, "Performance analysis and enhancement for the current and future IEEE 802.11 MAC protocols," ACM Mobile Computing and Communications Review, vol. 7, April 2003, pp. 6-19. [12] G. Bianchi and I. Tinnirello, "Kalman Filter Estimation of the Number of Competing Terminals in an IEEE 802.11 network," INFOCOM 2003 [13] H. Bruneel and B. G. Kim, Discrete-time models for communication systems including ATM," Kluwer Academic Publisher, 1993. [14] LD Servi, "D/G/I queue with vacation," Oper. Res. (1986). [15] L. Kleinrock, Queueing Systems, Volume II: Computer Applications, Wiley Interscience, New York, 1976. [16] G. Bianchi, "Performance Analysis of the IEEE 802.11 Distributed Coordination Function", JSAC, March 2000 [17] A. P. Stephens et al., 802.11 TGn Functional Requirements, IEEE 802.11 -03/802r23, May 2004. [18] S. Wang and A. Helmy, "Performance Limits and Analysis of Contention-based IEEE 802.11 MAC", University of Southern California Computer Science Technical Report 06-883. 425 T I 4 4 TABLE III MTU=2346 bytes




2014 Gautham Prasad


To my parents and T he Lord Almighty


4 ACKNOWLEDGMENTS I would like to express deep gratit ude to my advisor, Prof. Haniph Latchman. It is his constant guidance and encouragement that has brought me this far in my research. I am thankful to Dr. Richard Newman and Dr. Janise McNair for accepting to serve as members of my thesis committee. I than k my colleagues at the Laboratory for Information Systems and Telecommunication (LIST) for all the insightful discussions we have had on this wonderful and ever growing field of Power Line Communications (PLC). I am fortunate to have fo und lovely friends at Gainesville who have shared my happiness and sorrows and encouraged me at all times. I owe many thanks to University of Florida Information Technology (UFIT) for providing access to MATLAB I am extremely grateful to my parents for the unconditional lo ve and support they have given me I would not be where I am without their encouragement.


5 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ .. 4 LIST OF TABLES ................................ ................................ ................................ ............ 7 LIST OF FIGURES ................................ ................................ ................................ .......... 8 LIST OF ABBREVIATIONS ................................ ................................ ............................. 9 ABSTRACT ................................ ................................ ................................ ................... 11 CHAPTER 1 INTRODUCTION ................................ ................................ ................................ .... 13 2 LITERATURE REVIEW ................................ ................................ .......................... 18 HomePlug Powerline Alliance and HomePlug Standards ................................ ....... 18 Low De nsity Parity Check Codes ................................ ................................ ............ 19 Encoding ................................ ................................ ................................ .......... 20 Decoding ................................ ................................ ................................ .......... 20 Turbo Codes ................................ ................................ ................................ ........... 22 Encoding ................................ ................................ ................................ .......... 22 Decoding ................................ ................................ ................................ .......... 22 HomePlug System with LDPC Encoding ................................ ................................ 23 3 HOMEPLUG AV SYSTEM MODEL ................................ ................................ ........ 26 Scrambler ................................ ................................ ................................ ............... 28 Turbo Convolutional Encoder ................................ ................................ ................. 29 ROBO Modes ................................ ................................ ................................ ......... 29 Mapping ................................ ................................ ................................ .................. 30 Multicarrier Modulation Using OFDM ................................ ................................ ...... 31 Tone Mask ................................ ................................ ................................ .............. 32 4 MODIFIED ADAPTIVE BIT LOADING ALGORITHM ................................ .............. 33 Review of E xisting Bit Loading Algorithms ................................ .............................. 33 Water Filling Algorithm ................................ ................................ ..................... 34 WLK Algorithm ................................ ................................ ................................ 35 Drawbacks for PLC Implementation ................................ ................................ 36 Modified Adaptive Modulation Algorithm ................................ ................................ 37 Simulation Results and Performance Evalua tion ................................ .................... 37 5 LDPC AND TURBO CODES WITH REAL POWERLINE NOISE ........................... 43


6 LDPC System Implementation ................................ ................................ ................ 43 Turbo Encoding and Decoding ................................ ................................ ............... 43 Performance Evaluation of LDPC and Turbo Codes With Real Powerline Noise ... 44 6 LDPC AND TURBO CODES ON A REAL POWERLINE CHANNEL AND HOMEPLUG AV STANDARDS ................................ ................................ .............. 48 Encoding and Decoding Process for LDPC ................................ ............................ 49 Simulati on Environment and System Implementation ................................ ............. 50 System Parameters Specified by HPAV ................................ ........................... 50 Implementation of Forward Error Correction Codi ng ................................ ........ 52 Digital Modulation ................................ ................................ ............................. 52 Carrier Notching for FCC Compliance ................................ .............................. 53 OFDM ................................ ................................ ................................ ............... 53 Guard Intervals (GI) ................................ ................................ .......................... 53 Signal Power ................................ ................................ ................................ .... 53 Receiver ................................ ................................ ................................ ........... 54 PLC Channel and Noise Effects ................................ ................................ ....... 54 Simulation Results and Performance Evaluation ................................ .................... 58 7 QUASI CYCLIC LOW DENSITY PARITY CHECK CODES (QC LDPC) ............. 61 8 CONCLUSIONS AND FUTURE WORK ................................ ................................ 63 LIST OF REFERENCES ................................ ................................ ............................... 66 BIOGRAPHICAL SKETCH ................................ ................................ ............................ 68


7 LIST OF TABLES Table page 4 1 Data rates for different algorithms an d error rates ................................ .............. 42 6 1 Error rates for different FEC schemes ................................ ................................ 59


8 LIST OF FIGURES Figure page 2 1 Tanner graph for an LDPC code ................................ ................................ ......... 21 3 1 Block diagram of the HPAV PHY Layer ................................ .............................. 28 4 1 Bit loading profile using water filling algorithm ................................ .................... 39 4 2 Bit loading profile using WLK algorithm ................................ .............................. 40 4 3 Bit loading profile using modified WLK algorithm ................................ ................ 41 5 1 Noise samples seen on powerline channels ................................ ....................... 45 5 2 Error rate performance of LDPC and Turbo codes under powerline noise environment ................................ ................................ ................................ ........ 46 6 1 PLC network configuration for channel measurement ................................ ........ 55 6 2 Impulse responses of the PLC channels ................................ ............................ 56 6 3 Frequency responses of the PLC channels ................................ ........................ 57 6 4 Power Spectral Density of the transmitted and the received signal .................... 58 6 5 BER performance of LDPC and Turbo codes on a real powerline channel ........ 59


9 LIST OF ABBREVIATIONS ABL APP ARQ AWGN BEC BER BPSK COMSOC DFT FCC FDM FEC FFT HD PLC HPAV HPGP ICI IDFT IFFT ISI ITU LDPC LU T Adaptive Bit Loading A Posteriori Probability Automatic Repeat Request Additive White Gaussian Noise Backward Error Correction Bit Error Rate Binary Phase Shift Keying Communications Socie ty Discrete Fourier Transform Federal Communications Commission Frequency Division Multiplexing Forward Error Correction Fast Fourier Transform High Definition Power Line Communication HomePlug AV HomePlug Green PHY Inter Carrier Interference Inverse Dis crete Fourier Transform Inverse Fast Fourier Transform Inter Symbol Interference International Telecommunication Union Low Density Parity Check Look Up Table


10 MAC MIMO MPDU NEK OFDM PCCC PLC PSD QAM QC LDPC QPSK SCCC SNR TCC Medium Access Control Multiple Input Multiple Output MAC Protocol Data Unit N etwork Encryption Key Orthogonal Frequency Division Multiplexing Parallel Concatenated Convolutional Codes Powerline Communication Power Spectral Density Quadrature Amplitude Modulation Quasi Cyclic Low Density Parity Check Quadrature Phase Shift Keying Serial Concatenated Con volutional Codes Signal to Noise Ratio Turbo Convolutional Codes


11 Abstract of Thesis Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Master of Science A COM PARATIVE SIMULATION STUDY OF A MODIFIED HOMEPLUG AV PLC SYSTEM WITH NOVEL ADAPTIVE BIT LOADING AND LDPC CODES By Gautham Prasad May 2014 Chair: Haniph A. Latchman Major: Electrical and Computer Engineering Data communication through existing power lines has been the subject of much research over the past decade Different industry collaborations have tried to develop standards for Power Line Communication ( PLC ) and the HomePlug AV (HPAV ) standard has been the most success ful so far. HPAV uses Orthogonal Frequency Division Multiplexing (OFDM) to achieve multicarrier modulation and adaptive bit loading on each of the se orthogonal sub carriers. D ata rates can be improved by using novel adaptive bit loading strategies to exploit the frequency selective nature of the harsh powerline channel. Various bit loading algorithms are simulated and a new algorithm is proposed to boost the data rates. Analysis and simulation results reveal a 43% improvement in the data rates from 34.44 Mbps to 49.39 Mbps for a real power line channel with an un encoded BER of 10 2 HPAV systems also use t urbo codes for Forward Error Correction (FEC) as opposed to Low Density Parity Check Codes (LDPC) because of its high performance at low Signal to Noise Ratios (SNR) which is common in lo ng er powerline runs The successful implementation of t urbo codes in HPAV also resulted in IEE E 1901 standards incorporating t urbo codes for FEC. However, t urbo codes are licensed and


12 usually require a patent fee to be paid for each turbo code enabled prod uct. The objective of this project is to examine whether the unlicensed LDPC codes could be a viable FEC alternative for HPAV systems E xtensive analysis and simulation results are provided to show that the LDPC codes of block length 32400, improve the Bi t Error Rates (BER) by 28% even at a low SNR of 1 dB However, increase in block length is accompanied by higher memory requirement. A simple implementation of low memory LDPC codes in the form of Quasi Cyclic LDPC (QC LDPC) is also discussed. All simulati ons are run on 10 different real powerline channels with HPAV specifications.


13 CHAPTER 1 INTRODUCTION The ability to communicate using the existing power lines, has made Power Line Communication (PLC) an attractive topic for researchers and engineers from industry, universities and utility companies [1]. PLC is used in differ ent fields from smart grids and automatic meter reading to in home multimedia communication. Utility organ izations have historically given immense attention towards PLC. Power lines wer e initially used for load management. Lately, however, utility companies have started empl o ying power line communication to read electric meters from a distance Power lines can also be adopted and adapted to broadcast information to all users, selectively turn on and off certain networks, and gather statistics and other such applications. Many utility companies are invest ing their research attention on such areas which fall under the category of Home automation and intelligent homes are also a budding area in the field of PLC. Power lines serve as an ideal medium to turn on/off a burglar attention because of the ease it provides for a day to day life. For example, a refrigerator monitors the content s level of a beverage and once it nears emptiness it transmit s signal on the power line to order fresh supply. On the other hand power lines are also used for in home entertainment; mainly multimedia communication. Local area multi user gaming, High Definition (HD) video streaming are application s which demand high speed point to point communication inside a house/building. Data rates obtained by wireless routers are inadequate and laying new cables such as Cat5E or other Ethernet cables throughout the house becomes tedious. PLC serves as a viable alternative in such cases providing high


14 speed broadband data communication over existing infrastructure. For applications such as smart grids, power constraints and reliability play a major role as opposed to data rates; w hereas for mult imedia applications, high speed s are critical Different industry collaborations have tried to propose different standards for PLC. High Definition Power Line Communication (HD PLC), HomePlug P owerline Alliance (HPA), G.hn are some of the more popular ones. The International Telecommunication Union (ITU) adopted the G.hn/G.9960 as a standard powerline communication HD PLC uses Wavelet based OFDM for multi carrier modulation as opposed to the co nventional OFDM used by the HomePlug standards. The FEC encoding schemes applied by these two competing standards are also different. While the HD PLC uses LDPC codes for error correction, HomePlug systems employ Turbo codes for FEC. However, the standards developed by HPA have been the most successful so far. There are more than 100 million HomePlug modems deployed to date and these numbers are continuously increasing [2]. The efficient implementation of Turbo codes in HPAV systems prompted IEEE 1901 stand ards to incorporate them as FEC. HomePlug Green PHY (HPGP) addresses the low power needs of smart grids and yet provides speeds up to 10 Mbps [3]. On the other hand, HomePlug 1.0, HPAV and HPAV2 have provided data rates up to 1.5 Gbps catering to the needs of high speed applications such as in home multimedia communication HomePlug 1.0 released in 2001 by HPA achieved speeds of 14 Mbps. This used a small frequency range of 4.5 MHz 21 MHz and a concatenation of Viterbi and Reed Solomon codes for FEC [ 4 ] Data rates were significantly improved to about 200 Mbps in the


15 subsequent release HPAV in 2005 [ 5 ]. Similar frequency band was used (1.8 MHz 3 0 MHz) but improvements were made to support modulation schemes up to 1024 QAM. This helped in improving the data rates drastically. More recently, HPAV2 has been released, which uses a higher bandwidth from 2 80 MHz and provides speeds up to 1.5 Gbps. IEEE Communications Society (COMSOC) sponsored the P1901 project to define a globally compatible standard for high speed powerline communication [2]. The working committee selected a consolidated proposal from HPA and HD PLC Alliance and provided the IEEE 1901 standard which represents a compromise between the conventional OFDM based HPAV and Wavelet OFDM bas ed HD PLC PHY used in HD PLC products. IEEE 1901 specifies both PHYs as optional with an Inter System Protocol (ISP) which provides coexistence but not interoperability between the two realizations. There are various factors that affect the data rates pro vided by these systems. Modulation schemes used, error correction strategies employed and MAC protocols implemented determine the eventual throughput of the system. The modulation scheme used determines the number of bits that are transmitted in a given period of time. Higher the modulation scheme, higher is the bit rate. However, with increase in modulation scheme, the error rates also increase. Hence, the modulation schemes need to be chosen intelligently and adaptively such that the error rates are nea r static. Different adaptive bit loading algorithms that have been proposed are evaluated in Chapter 4. A new bit loading algorithm is also proposed based on the best performing state of the art bit loading algorithm to suit HPAV systems


16 One of the major factors assisting in the improvement of throughput and enhancing the reliability of data transmission is the FEC. Error correction codes can mainly be divided into two parts: 1. Block codes 2. Convolutional codes Block codes generate code words by consuming me ssage bits in blocks. The encoder encodes the message bits with redundant parity check bits, generally appended to the message, and produces the code words in blocks. Change in block length s usually results in change in the code word length s for static err or correction/detection performance. The size of the input block and the code word block is characterized by code rate. Code rate is the ratio of the redundant bits added by the encoder to the code word length. The number of redundant bits added can be cal culated by the difference of the codeword length and the length of the message. LDPC codes fall under this category of block codes A discussion and analysis of the effects of b lock lengths and code rates on error correction performance is presented in Cha pter 5 Since the block codes receive the message and generate code words in blocks, a buffer is generally required to store data at the input. However, there are applications which demand serial I/O of data and a buffer becomes undesirable [ 6 ]. The use of convolutional codes is most suitable in such cases. A convolutional encoder pursues the input bits serially as it enters the encoder. Most of the convolutional encoders are characterized by a generator polynomial This polynomial can be represented in ter ms of shift registers or delay elements. Turbo Convolutional Codes (TCC) used in the HPAV and IEEE 1901 standards fall under this category.


17 HomePlug 1.0 used a concatenation of Viterbi and Reed Solomon codes for FEC. However with increase in the number of OFDM sub channels and use of higher modulation schemes in HPAV there was a need to improve FEC. The state of the art FEC technologies were LDPC and Turbo codes. Turbo codes were chosen for HPAV systems since they provide better error rate performance at low SNRs, which are common in long er power line runs The latest release HPAV2 continues to adopt Turbo codes for FEC. However, the drawback of using TCC is the patent fees that are usually required to be paid for e very turbo code enabled device manufactured. The purpose of this project is to investigate whether LDPC codes are a viable alternative t o Turbo codes for HPAV systems. A review of basic encoding and decoding concepts and previous attempts at evaluating the performance of a HPAV system with LDPC codes are discussed in Chapter 2 The complete system model of HPAV is provided in Chapter 3 Chapter 4 focuses on the proposed modified adaptive bit loading strategy developed, and its comparative performance with the existing bit loading algorithms. Chapter 5 deals with the error rate comparison between LDPC and Turbo codes under powerline noise environment. The system performance with LDPC and Turbo codes for a HPAV system with real powerline channels and their as sociated noise is discussed in Chapter 6 A novel implementation of LDPC codes in the form of QC LDPC is shown in Chapter 7 Conclusions are given in Chapter 8 and the following chapter presents future work that could be carried out.


18 CHAPTER 2 LITERAT URE REVIEW HomePlug Powerline Alliance and HomePlug Standards HPA is the largest and the most established industry group in PLC with about 65 member companies in it. It was established in 2000 to develop and promote powerline communication solutions. HPA w as initially formed to address high speed in home PLC and networking applications. As of 2012, there are at least 6 vendors and close to 280 different HomePlug products in the markets with over 100 million products shipped worldwide [2]. HPA uses a well st reamlined process for the development of all its specifications much on the lines of major standards organizations like the IEEE. HPA first released the HomePlug 1.0 standards in June 2001 providing data rates of 14 Mbps and coded PHY Rates of 10 Mbps [4] Subsequent release of HPAV improved the data rates drastically to reach up to 200 Mbps with coded PHY of 150 Mbps. All the HomePlug products adhere to the FCC regulations by notching out carriers in the amateur radio band. The convergence of voice, data and video into a single device drives the constant need for higher speeds. HPAV2 is the latest release of HPA and it provides data rates of 1.5 Gbps [9] which is ideal for several high speed applications such as multimedia communication, HD video streaming etc. HPAV2 uses an additional extended bandwidth of 30 80 MHz along with the 2 30 MHz which HPAV uses. It also grants the use of higher modulation schemes of 4096 QAM and encoding schemes of larger code rates, which result in higher data rate s AV2 also uses Multiple Input Multiple Output ( MIMO ) beam forming, sending data bits on multiple streams, and thereby increasing the data rates as well as the reliability of the message.


19 While HPAV2 caters the need of high speed PLC providing data rates of 1.5 Gbps, HPGP addresses the needs of Smart Grid applications. HPGP is developed as a low power and low data rate version of HPAV. HPGP only supports the QPSK modulation scheme and uses a low rate Turbo code for FEC. The bandwidth and number of subcarriers u sed remain the same but since QPSK is the only supported modulation scheme, only the ROBO modes are permitted This curtails the data rates but the accomplished data rate of 10 Mbps is still 40 times faster than the Smart Grid requirements and 1000 times f aster than competing PLC technologies suc h as PRIME, or G3 which operate at lower frequencies of less than 500 kHz [3]. HPAV systems use 128 bit encryption for security in place of DES used by HP 1.0 thereby providing high level of security with the sate of the art encryption mechanism. A N etwork Encryption Key (NEK) is used to encrypt individual segments as the MAC Protocol Data Unit (MPDU) is created. All the products of HomePlug technology after HPAV use Turbo codes for FEC as opposed to the competing LDPC codes though both nearly approach Shannon limit [10]. Turbo codes provide better error rate performance when compared to LDPC at low SNRs which are common in longer PLC propagation runs. The technical merits and de merits of both the codes are discuss ed in the following two sections of this chapter. Low Density Parity Check Codes LDPC codes were first introduced by Robert Galleger in 1963 [11]. They are high core of the functioning of LDPC codes is the parity check matrix. This is obtained based on the code words formed using the message bits such that every row represents the equation used to form the code word and the columns of the matrix indicate the digits in the code


20 word. Only if the k th digit i s present in the i k, i ) is called a sparse matri x Also, the density the matrix is less, which is where LDPC gets its name from. LDPC codes can be classified as: Regular LDPC code Irregular LDPC code A regular LDPC code satisfies two properties: every digit in the code word is contained in the same number of g enerator equation s and every generator equation contains the same number of code symbols [1 1 ] An irregular LDPC code does not have to satisfy these properties. Encoding If u is the message sequence and v is the code word produced by using the generator m atrix G, we get v = u.G ( 2 1) The parity check matrix H is such that it satisfies the following relation v.H T = 0 (2 2 ) The codeword v is of length n and the message word is of length k Hence the number of redundant bits added by the encoder is n k. Such a code is said to be ( n, k ) code with a code rate of k/n and a code block length of n. Decodin g LDPC codes can be graphically represented using Tanner graphs [12]. Decoding process is completely and effectively defined by Tanner graphs. Tanner graphs are bipartite graphs with two different types of nodes, one called the variable nodes (v


21 nodes) and the other is the check nodes (c nodes). Every row in H is associated to one particular c node and a column is associated to one v node. A c node k is connected to a neighboring v node i if and only if hij Therefore, there are n v nodes and n k c nodes in a Tanner graph. The c node and v node information is iteratively updated and a decision is finally made. A Tanner graph of LDPC codes is shown in Fig ure 2 1. Fig ure 2 1: Tanner graph for an LDPC code The sample Tanner graph shown rep resents the parity check matrix, H = As mentioned in the previous sections, we can observe that every row of H represents the equation to get a code word and e very column represents the equations in which one particular message bit is involved in. For the example mentioned above, the


22 equations satisfied by the code words based on which the parity check matrix is characterized, are: c 2 + c 4 + c 5 + c 8 = 0 (2 3) c 1 + c 2 + c 3 + c 6 = 0 (2 4) c 3 + c 6 + c 7 + c 8 = 0 (2 5) c 1 + c 4 + c 5 + c 7 = 0 (2 6) These are c nodes and the v nodes that are used in the process of decoding. Turbo Codes Turbo codes are high performance codes which nearly approach the Sha nnon limit. They were first introduced in 1993 by French Telecom and find current applications in 3G mobile communications and satellite communication. Encoding Turbo encoding is carried out using simple shift registers or delay elements and adders (usual ly binary adders, or XOR elements) The shift registers are initially set to different binary values based on the encoding scheme and the parity check elements required. The number of shift registers present also decides the number of parity bits that are appended to the message bits to form the code word and hence dictates the code rate of the encoding scheme. Every message bit passes through various shift registers based on the structure of the encoder and the code word is generated. Decoding The decod er is built on the same lines as the encoder. Depending on the number of parity bits that are added at the encoder, the number of shift registers and streams through which the received bit has to pass, also changes.


23 The performance of turbo codes is high because of the randomness that the encoder brings in and the efficiency with which the decoder can read it back. This is extremely effective for very noisy channels such as the one we have under consideration, the power line channel. Thus we can now already see why the turbo codes perform at least theoretically better than the LDPC codes at noisy conditions or at lower SNRs. HomePlug System with LDPC Encoding The HomePlug 1.0 systems, released in 2001, used a concatenation of Viterbi and Reed Solomon codes f or FEC. This was about the time when high performance codes such as Turbo and LDPC codes were being practically implemented successfully. The performance of a HomePlug 1.0 system with LDPC encoding was tried out in [ 13 ] However, the system evaluation was done only for the ROBO transmission mode of HP1.0. Also, the simulation s were run on a channel modeled by multipath fading and impulse noise and not a real power line channel environment. The results showed a minor improvement in error rates over the FEC a lready in use by HP1.0 systems. Also, the implementation of codes with certain algorithms w as Because of this hurdle, shortened codes were used for simulations thereby reducing the performance of the proposed system. There are other research comparisons made in this topic but under different simulation environments. The paper [14] concludes that Turbo codes outperforms a (7200, 4797) regular LDPC code but the s imulations are carried out only under AWGN channel conditions. However, powerline channels are much sever e with cyclo stationary impulse noise affecting the data transmission. In [15] LDPC codes are shown to


24 perform better than the ir t urbo counterparts ba sed on ITU T specifications but not the HomePlug scenario. ITU T has already incorporated LDPC codes for FEC. LDPC and Turbo codes are shown to have similar performances according to [16] but this again considers a primitive case of AWGN and BPSK modulatio n for the communication system. A more detailed analysis of the performance of a Turbo code d system and LDPC coded system and the ir simulation s are shown in [17]. LDPC codes of different block lengths of 256, 512, and 1024 are considered and their perform ance is compared with a Turbo coded system and a system with no FEC. LDPC is seen to perform better at higher SNRs while Turbo codes slightly bettered LDPC codes at lower SNRs as we observed when we studied the Turbo codes in the previous section. It also showed that the performance of LDPC codes improved with increase in block length. Similar analysis was carried out with LDPC codes having code rates of 5/6, 2/3 and 1/2. It was shown that the performance of LDPC codes improves as the code rate decreases. As seen in the previous sections, lower code rate implies higher parity check bits. This allows better reliability to be achieved and hence the performance improves as more errors can be detected and corrected. In this project, the results of this work are used and higher block length LDPC codes are used for encoding. More details about the simulation environment are explained in Chapter 6 As the block length increases, complexity of implementation of the code also increases. This can be addressed with the use of QC LDPC codes explained in [17]. However, [17] does not use a HomePlug AV system with typical multicarrier modulation and carrier notching to comply with the FCC regulations. The results in [17] also show that Turbo codes are still a better choice


25 for low SNR applications. However, in this work, it is shown that LDPC codes with sufficient bloc ks lengths do outperform their t urbo counterparts even at low SNRs. The increase in memory requirements and processing time can be mitigated by using QC LDPC c odes explained in Chapter 7


26 CHAPTER 3 HOMEPLUG AV SYSTEM MODE L HomePlug AV system can be broadly divided into three layers: HPAV PHY HPAV MAC Convergence Layer The PHY layer executes tasks like Forward Error Correction (FEC), digital modulation, mappin g OFDM symbols, introducing guard intervals for the generated OFDM symbols, generation of time domain waveforms and other physical layer tasks. The MAC layer formats the data frames into fixed length frames for transmission and ensures that the data reach es safely (without errors) through Backward Error Correction (BEC) techniques such as Automatic Repeat Request (ARQ). The Convergence layer performs data delivery smoothing functions and makes sure that the MAC and PHY co exist with higher layers and the u ser interface. At the receiver end the same functions are carried out in reverse order. OFDM is chosen for multicarrier modulation because of its inherent resilience to frequency selectiveness of the communication channel. Harsh channels like the PLC cha nnel are highly frequency selective which can be seen in the channel frequency responses shown in Chapter 6 OFDM is also resistive to impulse noises which are also common in a PLC channel and can be seen in the noise samples used in the simulation in Cha pter 6 With the use of time domain pulse shapers to the OFDM symbols, deep frequency notches can be obtained without the use of complicated band stop filters. Deep notches are required to maintain FCC compliance, explained in Chapter 6 HPAV uses the ba ndwidth of 1.8 MHz 30 MHz with an FFT size of 3072. This provides a set of 1536 carriers in each of the positive and negative frequency bands out


27 of which 1155 carrier s fall in the bandwidth of 1.8 MHz 30 MHz range. Of these, 917 carriers are used for modulation and the rest are notched out as per FCC regulations such that they do not interfere with amateur radio bands. The carriers are all equally spaced and the carrier spacing is ratio of the sampling frequency to the total number of carriers. Thus c arrier spacing is 75 MHz / 3072 = 24.414 kHz. HPAV supports digital modulation schemes of Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), 16 Quadrature Amplitude Modulation (QAM), 64 QAM, 256 QAM and 1024 QAM. Different modu lation s chemes are chosen based on the channel conditions present Various bit loading algorithms assist in deciding the modulation scheme to choose. These are discussed in Chapter 4 A special signaling scheme called the ROBO mode or the Robust OFDM mode is also supported by HPAV where only QPSK is used for modulation. Such a scheme is employed when the channel condition reaches its negative limit. Figure 3 1 shows the basic block diagram of a HPAV communication system [ 5 ]. It can be seen that the FEC sch emes employed for a HPAV frame and HP1.0.1 are different. As mentioned bore, turbo codes were not used by HomePlug products before HPAV. In order to provide downward compatibility, provisions are made to encode HP 1.0.1 frames using a turbo product encoder The payload however makes no distinction between the two standards. HPAV systems do not used equalizers because of the use of conventional FFT OFDM for multi carrier modulation. Since is substituted by an Automatic Gain Control (AGC) to handle the channel attenuation.


28 Figure 3 1 : Block diagram of the HPAV PHY Layer The receiver performs the exact opposite of the operation s performed at the transmitte r end w ith an addition al AGC and time synchronizer. As discussed, the system is downward compatible and supports HP 1.0.1 frames as well. For a HP 1.0.1 payload, a 384 point FFT is used since HP 1.0.1 uses different frequency bands and lesser sub carriers When a HPAV payload is received a 3072 point FFT is performed at the OFDM modulator. An OFDM symbol is comprised of t prefix which gives the time duration of the added Guard Interval ( t GI ) as well as the roll off time ( t RI ) and the payload time. So the overall time duration of an OFDM symbol is t prefix + T where T is the payload time. Scrambler The data scrambler is used to obtain a random distribution to the message so that effects of impulsive noise are minimized. PLC channels often contain impulse


29 noises and scrambling avoids the distortion of a single chunk of the message by distributing the data randomly. The scrambler consists of a series of shift registers or serial ly input to it. Depending on the scrambler polynomial, the contents of this register are XOR ed at different locations and the output message is generated. The scrambler polynomial used for the simulation is as specified by HPAV specifications. Turbo Conv olutional Encoder Data from the scrambler is then fed to a turbo convolutional encoder. Turbo codes are licensed by French telecom and require a patent fee to be paid for every turbo code enabled manufactured device. Two Recursive Systematic Convolutional (RSC) constituent codes are used along with a turbo interleaver. These codes support sizes of 520, 136 and 16 octets. Code rates of 1/2 and 16/21 are available after puncturing. However, only code rate FEC is used for HAPV when it functions in ROBO mode since the channel conditions are harsh in such a scenario and more the number of parity bits, higher is the probability of detecting and correcting errors. But this also presents additional redundancy. ROBO Modes ROBO modes are used under harsh channel co nditions In such cases, getting some data is better than getting none and hence rate codes are used with minimal loss of efficiency ROBO mode s are also used for several other purposes such as: Data multicast and broadcast communication Session setup Management message exchange s ROBO modes use QPSK for digital modulation and rate codes for FEC as mentioned above. ROBO interleaver is different from the turbo interleaver since it introduces


30 additional redundancy to improve reliability. With the use of ROBO modes, information about the use should also be sent to the mapper to update the mapping to ROBO mode. Mapping The mapper decides what digital modulation scheme should be employed on the data. Based on the modes of transmission and the type of input frame, the mapper makes its decision. For frame control information, the modulation is always chosen to be QPSK. When the transmission mode is ROBO, the modulation scheme is again set to QPSK. For all other payload data, different modulation schemes are ch osen based on the channel conditions. The modulation scheme to be chosen is decided by bit loading algorithms which monitor the channel conditions and decide the number of bits to load for every symbol. The frequency selective nature of Power Line channel s results in different OFDM sub carriers having different attenuations which hinder the achievement of maximum efficiency with static bit loading over all carriers. By estimating the nature of the channel, the bit loading can be chosen in such a way that t he error rate remains constant while total number of bits transmitted increases. This helps in obtain ing higher data rates without increase in BER which will eventually result in a greater throughput Different bit loading algorithms have been proposed to effectively load bits on to different OFDM sub carriers such that static error rates are maintained with increase in the raw bit rate. The state of the art bit loading algorithms are studied in the next chapter and a modified bit loading algorithm is propo sed to best suit HPAV systems.


31 Multicarr ier Modulation U sing OFDM Channels such as a PLC channel are highly frequency selective in nature. Frequency selective channels provide different levels of attenuation at different frequencies making it tedious for efficient transmission and reception. Hence the available bandwidth can be divided into v arious sub channels and data transmission can be carried out on each of those sub channels simultaneously so that each of these sub channel have flat fading (constant attenuation across the bandwidth) This is called Frequency Division Multiplexing (FDM). With each sub channel a specific sub carrier is associated ( usually it is the center frequency so that it has equal frequency space on either side to spread out) Th e terms sub channel and sub carriers are often interchangeably used. These sub channels often need to be separated by a certain frequ en cy called the guard band so that they do not roll off into each other and cause Inter Carrier Interference (ICI). Orthogo nal Frequency Division Multiplexing or OFDM abolishes the need for this guard band by allowing overlap of adjacent sub channels thereby providing better bandwidth efficiency. Consider a message signal X(f) with data points associated with every and a carrier signal of frequency f c which can be represented as a complex sinusoid of e fct The modulated signal therefore becomes X(f) j such sub carriers, the eventual modulated signal is (3 1) This turns out to be the equation for Inverse Discrete Fourier Transform (IDFT) with a scaling factor. Extracting the message can be done similarly by performing the


32 inverse of it, which is the Discrete Fourier Transform (DFT) of the received signal. The message signal estimate can be recovered from the received signal using (3 2) DFT implementation on hardware and in simulations is carried out using efficient algorithms called Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT). Algorithm etc can be found in [18]. The carrier signal can therefore be modulated using IFFT and the message can be extracted at the receiver by FFT, thereby achieving OFDM modulation. Since the sub carriers are all orthogonal to each other, overlap of sub carrier s can be permitted with no loss of information. The FFT and IFFT equations help in understanding why the overlap of sub carriers can be permitted without losing any data. Tone Mask As seen from the calculations at the beginning of the chapter, there are 1155 available carriers in the 1.8 MHz 30 MHz of frequency range. But all these carriers cannot be used for OFDM. FCC r egulations prohibit the use of all sub carriers as some of these interfere with the HAM bands. Tone mask defines the sub carriers that lie in this region which are required to be notched. These regulations hold well throughout North America and different r egions have various such regulations. I nformation regarding carrier notch outs is held by the Tone Mask and HPAV system provides support to any kind of Tone Masks depending on the region in which the products are intended to be marketed.


33 CHAPTER 4 MODIF IED ADAPTIVE BIT LOADING ALGORITHM Review of Existing Bit Loading Algorithms Powerline channels typically exhibit frequency selective fading which results in different OFDM sub carriers suffering different values of attenuation. This results in over modula tion or under modulation when constant bit loading is executed on all sub carriers. Over modulation is the condition where a bad sub carrier with high attenuation is given a greater modulation scheme causing high Bit Error Rate (BER) and under modulation i s when a good sub carrier with low attenuation is given a low modulation scheme resulting in under utilization of the sub carrier. Adaptive Bit Loading (ABL) exploits this frequency selective fading prevalent in powerline channels to load different bits/sy mbol (modulation schemes) on different sub carriers based on the sub channel SNR the general block diagram of a HomePlug AV PHY layer in Figure 3 1 There are several ABL algorithms which can broadly be classified into two sections: 1. Adaptive bit loading with adaptive energy profile 2. Adaptive bit loading with constant energy profile The FCC restrictions levied on powerline communications require the maximum transmit Power Spectral Density (PSD) in 1.8 30 MHz frequency band to be 50 dBm/Hz. This rules out the choice of the first class of ABL algorithms which give an adaptive power allocation based on the sub carrier SNR. In this class of ABL algorithms, the data transmitt ed on sub carriers with high SNRs are allocated low transmit power and the bit loading is done subsequently. Similarly, the data transmitted on sub carriers with low SNRs are given higher transmit power and the bit loading is done based on this


34 power alloc ation. However, in powerline communications this cannot be performed in this frequency band due to the FCC regulations mentioned above. This limits the choice of ABL algorithms to the second class of algorithms. The two most widely known ABL algorithms are considered and it is shown that the Wyglinski Labeau Kabal ( WLK ) algorithm outperforms the traditional water filling algorithm. Furthermore, the drawbacks in a powerline communication system with WLK algorithm are analyzed and a modified WLK algorithm is proposed to better suit the HomePlug AV and other powerline communication systems. Water Filling Algorithm The water filling algorithm is a primitive bit loading scheme which chooses the digital modulation scheme based on the threshold BER. Once the thresh old BER is set, the algorithm tries to select different modulation schemes for different sub carriers to achieve an average BER which is lesser than the threshold BER. However, it does not iteratively adapt based on the calculated BER. Once the bit loading scheme is set, it does not change it until there is a change requested due to either a change in channel condition or a load change. The BER is calculated from the channel SNR which in turn is calculated using the channel frequency response using the foll owing relation: (4 1) corresponds to the energy and H corresponds to the PSD of the channel with H being its complex conjugate indicates the noise variance present. Using this value of SNR, the bit loading scheme is decided using the equation: (4 2)


35 is the SNR gap, which indicates how far the system is away from the maximum is the number of bits/symbols loaded on the sub carrier Once the bit loading is done, the BER is not computed again to check if a better loading scheme can be performed. The loading once done is assumed to be the ideal one. Though the BER obtained from such a scheme will be well within the threshold BER limit the bit loading can possibly be improved for certain sub carriers depending on how far away from the SNR threshold they are WLK Algorithm The WLK algorithm was proposed by Alexander Wyglinski, Fabrice Labeau and Peter Kabal in July 2005 [19] This was a n adaptive bit loading scheme applicable to any general multi carrier communication system. The adaptive bit loading is done such that the resultant BER is smaller than the threshold BER. The maximum allowable modulation scheme is first chosen for all the available carriers. In the case of HomePlug AV systems, this is 1024 QAM. The BER of the individual sub carriers are then calculated using the theoretical BER es timation expression [20 ]. Using these individual BERs, the average BER of all the sub carrier s is calculated and compared with the threshold value. If the value is lesser than the threshold, the algorithm ends and the bit loading scheme is obtained as 1024 QAM on all carriers. However, for powerline channels, this case is highly unlikely. If the average BER is greater than the threshold value, the sub carrier with the highest BER is identified and the bit loading is reduced by 2. This implies that the worst sub carrier is chosen and the modulation scheme of that carrier is lowered. The reduction is done in steps of 2 as the obtained constellation points are desired to be equidistant. Once the reduction is done, the average BER is recomputed and compared with the threshold.


36 This process is repeated until the average BER goes below the threshold. In cases where such a bit loading scheme cannot be achieved, the transmission is done in HomePlug AV ROBO mode where the bit loading on all sub carriers is set to 2 (i.e. QPSK on all carriers). T he WLK algorithm is as follows: 1. Initialization: S et the modul ation scheme of all the subcarriers to 1024 QAM a) Determine P i i = 1, . N for every sub channel, from the subcarrier SNR values [20] where P i i with a constellation size M i using the relation (4 3) For a BPSK modulation (4 4 ) Where is the SNR of the i th sub channel. 2. Co mpute weighted ave rage P using t he expression: (4 5 ) where N = total subcarriers 3. Compare with the threshold BER. If P < threshold BER, configuration is retained and the algorithm ends. 4. Search for the subcarrier w ith the worst P i and reduce the bit loading by 2 If b i = 1, null the subcarrier (i.e., set b i = 0), where b i is the number of bits/symbol i 5. Recompute P i of all subcarriers with changed allocations and return to Step 3. Drawb acks for PLC Implementation The WLK algorithm works as expected for a clean wireless channel which can be modeled as a channel with AWGN. However, it cannot be directly incorporated into a powerline communication system. The calculation of BER from the sub carrier SNR as shown in ( 4 3) and [ 20 ] holds true only when the noise present in the entire


37 communication system is limited to AWGN. A powerline channel noise, however, is characterized by high attenuation, multipath, random impulsive noise and frequency selective fading [2]. This makes it impractical to use the WLK algorithm for powerline communication systems. Modified Adaptive Modulation Algorithm A modification to the WLK algorithm is proposed such that it can be used effectively for powerline systems The drawback that was identified was the exclusive consideration of AWGN noise in the estimation of the sub carrier BER. This can be addressed by including the powerline noise effects that are present in the system. It can be accomplished in two ways: 1. Th e BER v/s SNR curves can be obtained for a typical HomePlug AV system by building the PHY layer of the system. The procedure is explained in later sections. From this plot, a Look Up Table (LUT) can be generated to get different values of BER and SNR for a particular channel. For simulation simplicity, a new expression relating the BER and the SNR can be determined. This expression or the LUT can be used to ascertain the bit loading estimate in all the iterations. 2. The second way of achieving this is by acco mmodating the powerline noise while determining the value of SNR. The determination of SNR in the WLK algorithm is done by considering the ratio of the signal power and the AWGN noise power. In this expression, the powerline noise power can also be added s uch that the resultant SNR includes the effect of the powerline noise present. In this simulation study, the second approach is chosen as it possesses lesser implementation complexity. The rest of the algorithm remains the same, as explained in the previou s section. Simulation Results and P erformance E valuation The primary step in evaluating the performance of ABL algorithms is to build a basic HomePlug AV communication system, the block diagr am of which is shown in Figure 3 1 Ten different powerline chann els and their corresponding noise samples


38 were provided by Qualcomm Atheros [ 8 ]. The impulse responses of the channels and their noise samples were captured inside a house in a powerline circuit connected to various home appliances such as refrigerator, te levision, electric lamps, microwave oven, coffee makers and personal computers. The LUT of BER and SNR values are obtained by simulating the PHY layer model of Figure 3 1 The simulation environment and implementation procedure is explained in Chapter 6 T his can also be substituted by following the second procedure of implementation explained in the previous section. The ABL algorithms are implemented using the algorithms that were explained in the previous three sections. The performance evaluation is don e in terms of data rates obtained. In an OFDM transmission, the symbol period is equal to the inverse of the frequency spacing of the orthogonal sub carriers [ 21 ] to maintain orthogonality With the available 917 carriers for data transmission, the data ra te is calculated as follows: Data Rate = 917 m 24414 bps (4 6) represents the number of bits/symbol used, which is dependent on the number of bits loaded by the ABL algorithm. The highest modulation scheme that HomePlug AV ca n support is 1024 QAM, for which, m = 10. With this value, we get the Data Rate = 917*10*24414 = 220 Mbps. This is the theoretical maximum raw data rate that HomePlug AV systems can provid e. With the help of this equation we can evaluate the performance of the three different ABL algorithms For a given channel (Channel 5 shown in Chapter 6 ) and a static BER of 10 2 the following bit allocation is obtained using the water filling algorithm.


39 Figure 4 1: Bit loading profile using water filling algorithm It can be seen that the water filling algorithm chooses only the modulation schemes of 16 QAM and QPSK to achieve the required BER for this channel. The data rate obtained for thi s scenario was 34.44 Mbps. Figure 3 also shows the frequency response of t he channel after the transmit mask is applied. The bit allocation obtained by the WLK algorithm with the same simulation environment is shown in Figure 4 2


40 Figure 4 2: Bit loading profile using WLK algorithm It chooses 256 QAM and 64 QAM for modula tion depending on the sub carrier SNR. The data rate obtained was 89.7 Mbps. It can be noticed that the data rate has almost doubled when compared to water filling algorithm. However, this does not imply that the eventual throughput is also doubled since t he efficiency drops as the data rate increases when no action is taken at higher layers. To make best use of the increase in Physical layer data rates, care should be taken to maximize the length of the PHY payload in the MAC layer to make sure the efficie ncy does not drop with increase in data rates. Higher layers should also take appropriate measures to make sure efficiency does not drop so that the increase in PHY data rate can be effectively reflected in the eventual throughput.


41 The proposed modified WL K algorithm, for the same channel conditions and error rates, gives the following bit allocation: Figure 4 3: Bit loading profile using modified WLK algorithm The data rate obtained in this case was 49.39 Mbps. Though the bit loading profile is not as l arge as WLK, this provides a better estimate for the given powerline communication system since it considers the powerline noise and the channel attenuation present in the powerline channel. Though the WLK algorithm outperforms the proposed algorithm, the bit loading profile obtained from the WLK algorithm is an erroneous one which can be accepted for only a system with AWGN environment. However, it can be noticed that the data rate obtained is higher than the water filling


42 The three different algorithms are simulated for all the 10 powerline channels (to be seen in Chapter 6 ) with three different un encoded BER values of 0.1, 0.01 and 0.001. The data rates (in Mbps) obtained in all these cases are tabulated in Table 1. Table 4 1: Da ta rates for different algorithms and error rates BER = 0.1 BER = 0.01 BER = 0.001 WF M WLK WF M WLK WF M WLK Channel 1 80.91 117.8 34.9 0 51.85 29.60 45.38 Channel 2 80.86 110.9 34.72 49.48 29.56 44.75 Channel 3 80.86 111.4 34.84 49.63 29.56 44.75 C hannel 4 80.86 111.1 34.79 49.53 29.56 44.75 Channel 5 80.86 110.6 34.44 49.39 29.56 44.70 Channel 6 80.86 110.8 34.44 49.44 29.56 44.76 Channel 7 80.86 110.7 34.44 49.44 29.56 44.70 Channel 8 80.86 110.7 34.44 49.39 29.56 44.70 Channel 9 80.86 111.6 34.84 49.37 29.56 44.80 Channel 10 80.86 111.4 34.84 49.39 29.56 44.75


43 CHAPTER 5 LDPC AND TURBO CODES WITH REAL POWERLINE NOISE LDPC System Implementation The encoding procedure for LDPC is discussed in Chapter 2 The encoding is done based on the Ta nner graphs and every v node generates a code based on the c nodes connected to it. For decoding, the widely used iterative decoding algorithm called Sum Product Algorithm (SPA) is used. It is used to iteratively update the information of the c node and th e v node. A posteriori probability (APP) is applied for decision making and the log likelihood ratio is given by (5 1) where y is the received wo rd. The position of LDPC encoder can be determined by observing Figure 3 1 The turbo encoder used in a traditional HPAV system needs to be replaced by an LDPC encoder. The system of turbo encoder and the set of interleaver blocks are replaced by the LDPC encoder which is built. The rest of the system model remains the same and similar changes are made at the receiver. The Turbo decoder and the set of de interleaver blocks are replaced by the corresponding LDPC decoder. Turbo Encoding and Decoding There ar e two structures of turbo codes that are present: Parallel Concatenated Convolutional Codes (PCCC) Serial Concatenated Convolutional Codes (SCCC) Based on the choice of HPAV and IEEE 1901 [2], the PCCC is incorporated in the simulations for encoding using the turbo codes. Turbo codes are essentially two or more convolutional encoders connected with a pseudo random interleaver. The encoder is


44 configured with RSC encoders as discussed in Chapter 2 with an N bit pseudo random interleaver. Generally, the two R SC encoders used are similar to each other, i.e., have the same generator polynomial functions For the decoding of turbo codes, the iterative soft decision algorithm is used. The Bahl Cocke Jelinek Raviv (BCJR) algorithm [22] is applied for the decoding process using the Maximum A posteriori Probability (MAP), which is done iteratively. Performance E valuation of L DPC and Turbo Codes W ith Real Powerline Noise The performance evaluation of LDPC and Turbo codes are carried out with LDPC codes of different b lock lengths of 256, 512 and 1024 along with a turbo coded system and a system with no FEC. The simulations are carried out with real powerline noise samples provided by Qualcomm Atheros. The noise samples are as shown below in Figure 5 1 It can be seen f rom the noise samples that the powerline noise is characterized by impulse noise, phase noise, transient noise and other type of noise. The 10 different noise samples captured all the variants of noise possible in a powerline. For example, noise present in Channel 7 contains consistent impulse noise possible due to the use of equipment such as a hair dryer. On the other hand, nearly constant but high amplitude noise is present in Channel 1. Noise present in Channel 6 for example, is constant and low amplitu de and possibly easier to mitigate. Efficient error correction should be employed to make sure these noise values do not have adverse affect on the transmitted data.


45 Figure 5 1: Noise samples seen on powerline channels The PCCC turbo encoders are simu lated based on the choice made by HPAV and IEEE 1901 standards. The LDPC encoder and decoder are implemented as discussed in Chapte r 2 The BER simulation result for the system is shown in Figure 5 2


46 Figure 5 2: Error rate performance of LDPC and Turbo codes under powerline noise environment It can be seen that although the turbo codes perform slightly better than LDPC codes at low SNRs the LDPC codes begin to outperform as the signal power increases. Also, it can be seen that the LDPC codes with highe r block lengths are higher performance codes as compared to the smaller block length ones. This serves as a motivation to evaluate the performance of LDPC codes with high block lengths for a standard HPAV system and examine if it can serve as a viable alt ernative to the licensed turbo codes that are in use in the current HPAV products. But the complexity of implementation and the requirement of memory increases with increase in block lengths. This can be addressed by using Quasi Cyclic LDPC (QC LDPC) cod es.


47 The next chapter discusses the implementation of a HPAV system model and the use of LDPC codes as FEC for such a system. The performance of the system with high block lengths of LDPC codes for FEC is compared to a traditional HPAV system with turbo co des.


48 CHAPTER 6 LDPC AND TURBO CODES ON A REAL POWERLINE CHANNEL AND HOMEPLUG AV STANDARDS The block diagram of a standard HPAV system is shown in Figure 3 1 The AV payload entering from the MAC layer passes through the scrambler defined in the HPAV specifications and then enters the turbo encoder and interleaver blocks. The turbo codes provide the necessary FEC for the system and are traditionally known to provide better error rates than LDPC codes at low SNRs. This i s also seen in [17] and Figure 5 2 However Figure 5 2 also reve a ls that LDPC codes begin perform better as the block length increase s This serves as a motivation to investigate if LDPC codes with sufficient block lengths can provide better error performance when compared to turbo code s. Successful implementation of such a system would provide an alternative to the licensed turbo codes which require a patent fee to be paid for every turbo code enable device. The increase in block length of LDPC codes is accompanied by two major obstacl es : Increase in implementation complexity Increase in memory requirement Both these issues can be addressed with the use of QC LDPC codes, which provide a simpler implementation structure in terms of generation of the parity check matrix and the generator matrix. The memory required is also substantially reduced since matrices are formed by permutations of a base matrix, explained in detail in the next chapter.


49 Encoding and Decoding Process for LDPC The process of encoding and decoding using LDPC codes ar e explained in Chapter 2 and in Chapter 5. Similar steps are followed for a HPAV system model. The data scrambled by the pseudo random scrambler is passed through the LDPC encoder. The block length of the encoder is decided based on the error rate performa nce required In Figure 5 2 it can been seen th at, although the LDPC codes of b lock length 8640 perform better than turbo codes at high SNRs, the additional complexity of LDPC codes are being wasted at low SNRs, common for long propagation runs of powerlin e channels, where the simpler to implement turbo codes still outperform their LDPC counterparts. This forces the use of LDPC codes of higher block length. For simulation purposes, a quantum leap in the block length of LDPC codes is employed and a 32400 siz ed LDPC code is used for initial simulation. Unlike convolutional coding where the data is encoded serially, LDPC codes are block codes which require the data to be buffered until the block length is satisfied. This places a memory requirement overhead and the overhead increases with increase in block lengths. Depending on the performance of this system, the block lengths can further be reduced or increased. The parity check matrix is first built based on the message bits and the corresponding code word to be generated. The encoding procedure is explained in Chapter 2 and is graphically shown in Figure 2 1. At the receiver, the signal after demodulation is admitted i n to the LDPC decoder. The parity check matrix, H, should also be stored at the decoder si nce every row of H is associated to every c node and columns with the v nodes. The iterative decoding algorithm, SPA is used for decoding. At the decoder, based on the signal that the v nodes receive, it sends information to the connected c nodes. M essages from all


50 v nodes are collected and the c nodes estimate based on the information it gets from all v nodes it is connected to. These estimates are sent back to the corresponding v nodes. The information sent from one c node to a v node is based on the inf ormation that the c node receives from all other v nodes except the one that it is sending the estimate to. One set of message and estimate exchange between the c node and v nodes form s one iteration. These iterations continue until the correct codeword is estimated or until the maximum number of iterations is reached. At the end of the iterations, a codeword is finally estimated. Simulation Environment and System Implementation System Parameters Specified by HPAV Simulation constants for a HPAV system are the system parameters that are defined in the HPAV specifications. Sampling Frequency: The sampling frequency used throughout the system is 75 MHz and is especially required to interpret the channel transfer function from the impulse response. FFT Size: The FFT size used by HPAV systems is 3072. These are the total number of carriers available for OFDM multicarrier modulation, but include the frequencies in the negative spectrum as well. This divides the available spectrum into 3072 equally space orthogo nal sub carriers. Sub carrier size: This value contains the total number of sub carriers that are used for data modulation. Out of the 3072 total carriers, half of them lie in the negative spectrum. Hence the total useful carriers are 1536. However, only 1 155 of these lie in the bandwidth (1.8 MHz 30 MHz) available for HPAV operation. Of these, there are carriers which lie in the HAM bands and are required by the FCC regulations to be notched out. Hence for North America, the total useful sub carriers ava ilable for data transmission are 917. Bits per OFDM symbol: One OFDM symbol is the total number of symbols on each of the OFDM sub carriers. Since there are 917 sub carriers that are used, there are 917 symbols per OFDM symbol for the primitive case of BPS K modulation. When higher modulation schemes are used, this number would increase based on the bit loading used.


51 Sub carrier spacing: Based on the FFT size and the sampling frequency the sub carrier spacing can be evaluated. The 3072 point FFT provides 3 072 equally spaced carriers in a bandwidth if 75 MHz; hence the sub carrier spacing would be 75 MHz / 3072 = 24.414 kHz. Symbol duration: For the OFDM sub carriers to preserve orthogonality, the sub carrier spacing should be equal to the inverse of the sy mbol duration. Consider two carriers of frequencies f 1 and f 2 For them to be orthogonal to each other, (6 1) is the phase difference between the signals and the integral is over the time period T, which is also the symbol duration. Assuming to be an integer, the solution of the integral simplifies to (6 2) T he solution of this equation requires where k is any positive integer. The minimum value of k is 1 and hence we get the condition, This gives the frequency spacin g of 1/24.414 kHz = 40.96 us. Carriers in the HAM band: FCC regulations require certain carriers in the 1.8 MHz 30 MHz band to be notched off so that they do not interfere with the amateur carriers. These notching often require certain guard bands as wel l, to make sure there is no carrier roll off. Windowed OFDM provides deep notches which remove the requirement of use of complex band stop filters. The information about the se carriers that required to be notched off is stored in this field. Scrambler poly nomial: The scrambler polynomial is stored as a 1 D vector the corresponding bit in the scrambler polynomial vector is turned to accordingly. Modulation order: This chooses the bit loading that is performed on the different sub carriers based on the channel conditions. Based on the bit loading scheme given by the adaptive bit loading algorithm, the modulation order is set. Different modulation order is s et for different sub carriers based on the attenuation present in that sub carrier. OFDM aids in viewing every sub channel as a flat fading channel even though the spectrum shows a frequency selective nature the powerline channel. The channel condition is fed to the adaptive bit loading packets that are sent at regular intervals.


52 Whenever there is a change in the channel condition, the adaptive bit loading algorithm gives a new bit loading scheme which changes the modulation order of the different sub carriers. Implementation of Forward Error Correction Coding Based on the FEC scheme that is employed, a tu rbo or an LDPC encoder block is built. For an LDPC encoder, the parity check matrix is used, the generation of which is explained in Chapter 2. The encoder builds a generator matrix for the parity check matrix that it receives The parity check matrix is formed based on the block length and the code rate that is require d For simulation purposes, the message that needs to be transmitted is generated as a random set of equally likely 1 s a nd 0 s. This data is then multiplied with the generator matrix constructed by the LDPC encoder. For a system with turbo codes as FEC, the message bits are passed through the turbo encoders and interleaver built as discussed in Chapter 5. The same turbo en coder is used in a HPAV system as well. For the LDPC encoder the message bits enter a buffer serially and are grouped into initial blocks of length 32400. The block length can then be varied based on the robustness required. The message is then supplied se rially to the digital modulator. Digital Modulation The modulator operates on the signal based on the modulation scheme chosen by the modified adaptive bit loading algorithm developed and studied in Chapter 4. The bit loading algorithm provides modulation schemes for all sub carriers based on the individual sub channel SNR. The message data is divided into several groups of 917 bits each. Each of these 917 bits is further loaded on to the available 917 sub carriers at the OFDM modulator.


53 Carrier N otching f or FCC Compliance As per FCC regulations 238 out of the available 1155 carriers in the range 1.8 MHz 20 MHz are notched off and the remaining 917 carriers are loaded with blocks of data divided into various blocks of length 917 each. OFDM OFDM is used fo r multicarrier modulation as the 917 bits in each block are loaded on to the 917 available carriers using IDFT. This is accomplished on hardware and simulations using one of the FFT algorithms discussed in Chapter 2. Guard Intervals (GI) OFDM requires GI t o be prefixed before every symbol in each of the 917 carriers to prevent or reduce Inter Symbol Interference (ISI). The size of GI to be added is dependent on the channel impulse response. Ideally, the GI should be greater than the delay spread of the chan The length of GI is also dependent on the type of information being sent. For payload data lesser GI is used and for frame control data, higher length GIs are used. For OFDM, the GI is the las t few bits which are prefixed to the beginning of an OFDM symbol to make sure the circular convolution in DFT still holds va lid and is hence called cyclic prefix (CP). Signal Power The maximum allowable signal power spectral density (PSD) for transmission over powerlines in the given frequency range is also specified by the FCC to be 50dBm/Hz. It should ensured that the generated signal has a PSD lesser than or equal to this value.


54 Receiver The exact opposite processes are carried out at the receiver to re cover the message signal. The GIs are removed based on the data that is being processed. The GI lengths are higher for frame control data and are generally lesser for regular payload data. OFDM de modulation is performed using one of the FFT algorithms men tioned in Chapter 3 The OFDM de modulation expression is shown in (3 2). The data on the orthogonal sub carriers are extracted using FFT. Based on the Tone Mask, the data is obtained from the corresponding carriers by ignoring the notched out carriers in the amateur radio band The data is then demodulated using the bit allocation provided by the adaptive bit lo a ding algorithm and is then sent to a decoder block. The decoder is either an LDPC decoder which uses the SPA for decoding or a standard turbo deco der used in HPAV systems. The message recovered is then compared to the originally generated message to check the error rates. PLC Channel and Noise Effects For this simulation 10 different powerline channels and their corresponding noise values are consi dered. The impulse responses and noise samples were captured on a real powerline circuit connected to various appliances such as electric lamps, coffee makers, televisions, refrigerator, microwave oven and personal computers. Figure 6 1 shows the network configuration with 5 nodes and 10 different channels. The five nodes A, B, C, D and E are access points inside the house.


55 Figure 6 1: PLC network configuration for channel measurement The 10 different noise samples that were used are shown in Figure 5 1 It can be seen that most of the channels are characterized by impulse and various other types of noises, thereby making it a very harsh communication channel. The impulse responses and the frequency responses of the channels are shown in Figure 6 2 and Figure 6 3 respectively. I t can be observed from Figure 6 3 that all the powerline channels are frequency selective in nature and the use of OFDM is quintessential for the successfu l transmission of data. Figure 6 2 shows the high latency and delay sprea d associated with each of the powerline channels.


56 Figure 6 2: Impulse responses of the PLC channels


57 Figure 6 3: Frequency responses of the PLC channels


58 Simulation Results and Performance Evaluation Figure 6 4 shows the PSD of the transmitted and t he received signal which has passed through Channel 1 of th e 10 channels shown in Figure 6 3 It ca n be observed that the flat PSD portions of the transmitted signals are distorted to look like the channel frequency response. This can be explained in the f requency domain ; the received spectrum is the product of the channel frequency response and the transmitted signal spectrum. Figure 6 4: Power Spectral Density of the transmitted and the received signal The error rates obtained with different block leng ths of LDPC codes, the turbo codes and an un encoded system are compared using the simulation model described above. The results can be seen in Figure 6 5 and Table 6 1.


59 ` Figure 6 5: BER performance of LDPC and Turbo codes on a real powerline channel Ta ble 6 1: Error rates for different FEC schemes SNR (dB) 0 1 2 3 4 5 6 Un encoded 0.07496 0.03282 0.01981 0.00498 0.000817 0.000117 0 Turbo, Rate 0.07413 0.0300 0.00718 0.00113 0.00012 3.26e 06 0 LDPC 16200, Rate 0.07465 0.03549 0.01475 0.00186 4. 13e 05 0 0 LDPC 32400, Rate 0.07465 0.02169 0.00466 0.00054 0 0 0 The simulation results support the theory that the turbo codes provide better error rates as opposed to low block length LDPC codes at low SNRs The LDPC 16200, rate codes cross over the turbo code, rate curves at 3 dB until which the turbo codes perform better; after which, the LDPC 16200 rate codes provide 65% improvement in


60 error rates at 4 dB and a sharp decline in the curve from there on. However, the biggest outcome from the se results is the error rates of the LDPC codes with high block length (32,400). The error rates of these are consistently better than the ones provided by the system with turbo codes. Even at low SNRs of 1 dB, LDPC 32400 rate codes provide 28% decreas e in error rates when compared to turbo codes, followed by a steep decline as SNRs improve further. However, increase in block length is accompanied with increase in implementation complexity and memory requirement. This encourages the need to investigate better implementation of LDPC codes to reduce the complexity and memory required.


61 CHAPTER 7 QUASI CYCLIC LOW DENSITY PARITY CHECK CODES (QC LDPC) An ( n, k ) Quasi Cyclic (QC) code C qc is a linear block code over GF(2) when n = t*b, where b, t and k are positive integers with the constraint k < tb. There are two conditions levied on every QC code. Every codeword should contain t sections of b bits each After a cyclic shift in C qc every code word should be another new codeword in C qc [23] In order to pro duce efficient QC LDPC codes, two methods based on circulant permutation matrices and finite geometries are investigated in [24], [25] and [26]. The parity check matrices for these codes can be obtained by using circulant permutation of a base matrix. Henc e the parity check matrix H can be obtained by column permutation of a permutation matrix which is initially defined. This provides a major advantage for the QC LDPC codes over randomly generated LDPC codes. Since H can be generated by permutations of a base matrix, the memory requirement is reduced. Also, the permutation implementation is simpler than the complex LDPC parity check matrix that is to be built. For QC LDPC encoding, consider a base permutation matrix P of order qxq The parity check matrix H is generated by the circulant permutations of P It requires the term q to be a prime number [27] The first row of H is first filled and the remaining rows are filled based on the permutations of P Hence it can be seen that the memory requirement is gr eatly reduced and the complexity of building H is also simplified


62 For the decoding process either the SPA or a Bit Flipping Algorithm (BFA) can be used. BFA is a hard decision decoding unlike the SPA. The parity check matrix H and the received vector y ar e considered and the term H.y T is computed. The non zero elements in this new computed vector are identified. After every bit node resolves the c nodes, the largest number of the unsatisfied c nodes is found out. The bits of y involving this c node are all This process is carried on until the term H.y T = 0 or until the maximum number of iterations is reached. But during this process, some of the bits which were rightly estimated mi ght also be flipped. To avoid this [28] proposed that only one bi t should be flipped in every iteration. But this increases the number of iterations to get acceptable results. Based on these factors either of the two decoding algorithms has to be chosen for effective decoding. Thus QC LDPC codes provide simpler implantatio n of LDPC codes and also reduce the memory requirement. This enables the use of high block lengths LDPC codes for HPAV systems.


63 CHAPTER 8 CONCLUSIONS AND FUTURE WORK The adaptive bit l oading and FEC schemes of a traditional HPAV system were modified in the course of this work to obtain higher bit rates and lower error rates respectively. The adaptive modulation scheme currently used by HPAV system decide s the bit loading scheme based on the channel SNR and adaptively modulate s every sub carrier correspondingly, in a single shot. However, the proposed adaptive bit lo ading algorithm iteratively updates the bit loading on each of the sub carriers to reach an optimum bit loading such that th e data rates are maximized under a threshold error rate. Simulation results indicated a 43% improvement in data rates from 34.44 Mbps to 49.39 Mbps for a real powerline channel with a threshold un encoded BER of 10 2 Adaptive bit loading can be better ap preciated and tested when the channel conditions are continuously changing, such as a real world PLC channel. Such a system model can be simulated to test the performance of different adaptive modulation algorithms. The proposed bit loading scheme requires a significant number of iterations before it provides the optimum bit loading profile. Future work can involve reducing the number of iterations by choosing a lower starting point instead of the 1024 QAM chosen for HPAV systems. The algorithm can start fr om the profile provided by the water filling algorithm and then proceed to optimize the bit loading scheme. This can significantly reduce the number of iterations and the algorithm converges faster. T he BER performance of a conventional HPAV system was als o compared with that of a modified HPAV system with LDPC encoding scheme. The choice of turbo codes for HPAV and IEEE 1901 standards was because of their effective error rate performance at low SNRs. The simulations results showed that rate turbo codes


64 o utperform rate LDPC codes with block length of 16200 at low SNRs of less than 3dB. However, with increase in block length to 32400, rate LDPC codes provide 28% lower error rates even at a low SNR of 1 dB. LDPC codes of high block lengths also present additional implementation complexity and memory requirement. A r ate , 32,400 block length LDPC code, for example, requires storage of parity check matrices of the order 32400X16200. Such high memory requirements and implementation complexities are address ed by QC LDPC codes which provide an efficient parity check matrix generation scheme using cyclic permutations of a base permutation matrix. With the use of LDPC codes of high block lengths, the BER was reduced by 28% when compared to a turbo coded HPAV s ystem even at SNRs as low as 1 dB. This presented LDPC as a viable alternative for the licensed turbo codes for HPAV systems Future research would include implementing this system across all products of HPA including HPAV2 and HPGP. Although HPGP provides data rates sufficiently larger than the current smart grid requirements, LDPC codes present an open source alternative to the existing turbo codes. For simulation purposes, QC LDPC and regular LDPC codes provide similar results However, the implementati on simplicity and lower memory requirement can be greatly appreciated by developing hardware for such an encoder decoder system Future research could include hardware development for a QC LDPC enable d HPAV system. LDPC encoded HPAV systems would present a compatibility issue with the already e xisting turbo code enabled HomePlug products. This requires a design of an


65 Inter System Protocol which would provide interoperability between the HomePlug products with the two different FECs.


66 LIST OF REFERENCES [1] H. C. Ferreira, L. Lampe, J. Newbury, T. G. Swart, Power Line Communications: Theory and Applications for Narrowband and Broadband over Power Lines, John Wiley & Sons, West Sussex, UK, 2010 [2] H. A. Latchman, S. Katar, L. W. Yonge III, S. Gavette, HomePlug AV and IEEE 1901 A Handbook for PLC Designers and Users 1 st ed, IEEE Press, NJ, 2003 [3] HomePlug Green PHY White Paper http://www.homeplug.org [4] HomePlug 1.0 White Paper http ://www.homeplug.org [5] HomePlug AV White Paper http://www.homeplug.org [6] Simon Haykin, Digital Communications Wiley, 1988 [7] Communications with L International Telecommunications Energy Conference, 2006, Providence, RI [8] www.atheros.com [9] http://www.homeplug.o rg [10] Proc of the IEEE, Vol. 95, pp. 1150 1177, June 2007 [11] Gallager, R. G., Low Density Parity Check Codes, Monograph, M.I.T. Press, 1963 [12] IEEE Trans. Inform. Theory vol IT 27, pp. 533 547, Sept 1981 [13] International Telecommunca tions Energy Conference, pp 1 7, Sept 2006 [14] Proc. IEEE ISPLC Jeju, Korea, pp 394 399, Apr. 2008 [15] Proc. IEEE Internatio nal Conf. Comm., pp 1 6, May 2010 [16] European Journal of Scientific Research Vol. 54, No. 3, pp 465 472, 2011


67 [17] e International Symposium on Power Line Communications, April 2014 [18] Pearson, 2007 [19] t Loading with BER Constraint for IEEE Transactions on Wireless Communications Vol 4, No. 4, July 2005 [20] J. G. Proakis, Digital Communications, 3rd ed. New York: McGraw Hill, 1995 [21] Understanding an OFDM Transmission, http://www.dsp log.com/2008/02/03/und erstanding an ofdm transmission [22] Academic, New York, NY, 1999 [23] Press, 2009. [24] Y IEEE Trans. Inform. Theory, Vol. 47, pp. 2711 2736, 2001 [25] a IEEE Trans. Inform. Theory, Vol 50, No. 12, pp. 2966 2984, 2004 [26] Cyclic Low Density Parity Check Codes from Circulant Matrices, IEEE Trans. Inform. Theory, Vol. 50, pp. 1788 1794, 2 004 [27] LDPC Codes to Enable Ph.D dissertation, Dept. ECE, Univ. of Florida, Gainesville, FL, 2013


68 BIOGRAPHICAL SKETCH Gautham Prasad completed his Bachelor of Engi neering at the Visvesvaraya Technological University, Belgaum, India from the Department of Electronics and Communication Engineering in 2012. He obtained his Master of Science degree at the University of Florida, Gainesville from the Department of Electri cal and Computer Engineering in 2014. His current research interests are smart grids and high speed data communication over power l ines.