This item is only available as the following downloads:
1 WAFER LEVEL FABRICATION OF POWER INDUCTORS IN SILICON FOR COMPACT DC DC CONVERTERS By JIPING LI A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 201 3
2 2013 Jiping Li
3 To my parents and family
4 ACKNOWLEDGMENTS First of all, I am grateful for the continuous encouragement and support from Dr. Huikai Xie throughout my Ph.D. study. With his professional knowledge and methodology in MEMS and other engineering research fields, Dr. Xie always provided assistance and guidance to help me overcome obstacles. He exhibits great intelligence in problem locating and solving which is indispensible for our lab and also helps us hone research skills for future career s I also appreciate my Ph.D. committee members, Dr. Jenshan Lin Dr. Yong Ky u Yoon and Dr. Peng Jiang for their profound comments and advice s which ha ve helped me clarify concepts and improve my research. Dr. Yoon s group and our lab are in the same IMG group and we have a lot of pleasant cooperation in device fabrication and cha racterization. Dr. Lin and Dr. Jiang are always kind and generous and their professionalism provides a good model for me to learn from. I would like to extend my appreciation to all other IMG members and NRF staff s since they provided all the instruments a nd facilities necessary to finish my research experiments. It is only through their training and assistance that I am able to move on and finish all of my projects. My special thanks to all the group members in the Biophotonics and Microsystem Lab The valuable experiences shared from Mingliang, Lei, Kemiao, Sagnik, Yiping and Hongzhi are important for my career The discussion and cooperation with Victor, Xiaoyang, Lin, Jingjing, Wenjun, Sean, Can and John were necessary to conquer all the difficulties and I cherish all of my friendships with them.
5 I also thank Shannon Chillingworth, the department graduate advisor for her continuous help and tireless assistance in my graduate life Thanks to my family and parents for their constant suppor t that I wil l always rely on Their endless love and encouragement helped me to complete my Ph.D. study.
6 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ .. 4 LIST OF TABLES ................................ ................................ ................................ ............ 9 LIST OF FIGURES ................................ ................................ ................................ ........ 11 LIST OF ABBREVIATIONS ................................ ................................ ........................... 15 ABSTRACT ................................ ................................ ................................ ................... 16 CHAPTER 1 INTRODUCTION ................................ ................................ ................................ .... 19 1.1 Modern DC DC Converters ................................ ................................ ............... 19 1.2 Integrated DC DC Converters and Their F abrication Methods ......................... 23 1.2.1 Integrated DC DC Converters ................................ ................................ 23 1.2. 2 CMOS MEMS Processes ................................ ................................ ........ 24 1.2. 3 Wafer Level Packaging ................................ ................................ ............ 26 1.2. 4 System in Package Vs System on Chip ................................ .................. 28 1.3 The Trend for High Frequency Power Conversion ................................ ............ 29 1.4 The Challenges for Integrated Inductors at High Frequencies .......................... 32 1.5 Proposed Solution ................................ ................................ ............................. 33 1. 6 Outlines of This Dissertation ................................ ................................ ............. 35 2 STATE OF THE ART OF INTEGRATED POWER INDUCTORS ........................... 36 2.1 Board Package and Wafer Level Integration of Power Inductors ................. 36 2.1.1 Board Level Integration of Power Inductors ................................ ............ 37 2.1.2 Package Level Integration of Power I nductors ................................ ........ 42 2.1.3 Progress of the Commercialized Wafer Level Integration of Power Inductors ................................ ................................ ................................ ....... 46 2.1. 4 On Silicon Wafer Level Integration of Power Inductors ........................... 49 2.1. 5 In Silicon Wafer Level Integration of Power Inductors ............................. 57 2.2 Challenges of Power Inductor Integration ................................ ......................... 60 2.2.1 MEMS Implementation of Coils ................................ ............................... 61 2.2.2 MEMS Implementation of Magnetic Core ................................ ................ 65 2.2.3 Trade Offs of Power Inductor Integration ................................ ................ 69 3 WAFER LEVEL INTEGRATION OF IN SILICON POWER INDUCTORS .............. 72 3 .1 Proposed Integration Methods ................................ ................................ .......... 72 3 2 Process Flow ................................ ................................ ................................ .... 73 3 3 Size Matching Investigation for Wafer level Integration ................................ .... 76
7 4 DESIGN AND MODELING OF POWER INDUCTORS/TRANSFORMERS ............ 83 4 .1 Topology Designs ................................ ................................ ............................. 83 4 .1.1 Spiral Versus Toroidal Designs ................................ ............................... 83 4 .1.2 Constant Flux Inductors and Transformers ................................ ............. 95 4 .1.3 Stacked Windings V ersu s Parallel Windings ................................ ......... 100 4 .2 Analytical Model s of Power Inductors ................................ ............................. 102 4 .2.1 Lumped Parameters of Power Inductors ................................ ............... 103 4 .2.2 Determination of the Series Resistance ................................ ................ 106 4 .2.3 Determination of the Stray Capacitance ................................ ................ 110 4 .2.4 Converter Performance Degradation f rom Resistances and Capacitances ................................ ................................ .............................. 112 4 .3 Sizing Analysis Based on Analytical Model s ................................ ................... 112 5 WAFER LEVEL FABRICATION AND CHARACTERIZATION OF POWER INDUCTORS ................................ ................................ ................................ ........ 120 5 1 In Silicon Fabrication of Power Inductors/Transformers ................................ 120 5 1 .1 Three Key Steps ................................ ................................ .................... 121 5 1 .2 Mate rial S election ................................ ................................ .................. 124 5.2 First Generation: Circular Spiral Inductors ................................ ...................... 127 5 2 1 Fabrication Process of Circular Spiral Inductors ................................ .... 127 5 2 2 Characterization of Circular Spiral Inductors ................................ ......... 128 5 2 3 Fabrication Challenges and Discussion ................................ ................. 129 5. 3 Second Generation: T oroidal Inductors ................................ .......................... 130 5 3 1 Fabrication Process of Toroidal Inductors ................................ ............. 130 5 3 2 Characterization of Toroidal Inductors ................................ ................... 131 5 3 3 Fabrication Challenges and Discussion ................................ ................. 133 5. 4 Second Generation: Square Spiral Inductors ................................ .................. 136 5 4 1 Fabrication Process of Square Spiral Inductors ................................ .... 136 5 4 2 Characterization of Square Spiral Inductors ................................ .......... 138 5 4 3 Current Carrying Capability ................................ ................................ ... 141 5 4 4 Fabrication Challenges and Discussion ................................ ................. 143 6 DEMONSTRATION OF COMPACT DC DC POWER CONVERTERS ................. 146 6. 1 A Compact DC DC Buck Converter with Circular Spiral Inductor ................... 146 6. 2 A DC DC Buck Converter Assembly with Squ are Spiral Inductor ................... 148 6 2 1 The Buck Converter Demo Circuit ................................ ......................... 148 6 2 2 Characterization of the Converter Assembly ................................ ......... 150 7 SUMMARY AND FUTURE WORKS ................................ ................................ ..... 153 7 .1 Summary ................................ ................................ ................................ ........ 153 7 .2 Future Works ................................ ................................ ................................ .. 155 7 .2.1 Die level Assembly of the Square Spiral Inductor ................................ 155 7 .2.2 Fully Integrated Boost Converter ................................ ........................... 155
8 7 .2. 3 Integration of In Silicon Inductors for High Power POL Converter ......... 156 APPENDIX A COMMERCIAL POWER COMPONENTS UNDER INVESTIGATION .................. 157 B BUCK CONVERTER MEASUREMENT DATA ................................ ..................... 164 LIST OF REFERENCES ................................ ................................ ............................. 166 BIOGRAPHICAL SKETCH ................................ ................................ .......................... 172
9 LIST OF TABLES Table page 2 1 Commercial POL converters with integrated inductors ................................ ....... 43 2 2 Performance comparison of different integration techniques .............................. 61 2 3 Properties comparison of different structural materials ................................ ....... 64 2 4 Typical commercial and research magnetic materials for HF power conversion ................................ ................................ ................................ .......... 68 2 5 Competing factors for inductor/transformer implementation ............................... 70 3 1 Typical specifications for POL converter components in wafer level integration ................................ ................................ ................................ ........... 81 4 1 Performance comparison of toroidal and spiral topologies ................................ 94 4 2 FEM simulations of several constant flux transformers ................................ ...... 99 4 3 Optimization results of a toroidal ind uctor for 3.6 to 1.8V, 6MHz, 0.5A buck converter (a) ................................ ................................ ................................ ..... 115 4 4 Optimization results of a toroidal inductor for 3.6 to 1.8V, 6MHz, 0.5A buck converter (b) ................................ ................................ ................................ ..... 115 5 1 Copper electroplating bath composition ................................ ........................... 122 5 2 Spiral inductor reliability tests ................................ ................................ ........... 129 5 3 Comparison of f requently u sed Polymers ................................ ......................... 135 6 1 Electrical components of the demonstration buck converter integrated with square spiral inductor ................................ ................................ ....................... 149 7 1 Objective specifications of the fully integrated boost converter ........................ 156 A 1 Typical synchronous buck converters for 2.7 5.5V input voltage, 1.8V output voltage, and 500 600mA output current. ................................ .......................... 157 A 2 Smallest regulators under investigation ................................ ............................ 157 A 3 Regulators at highest switching frequency from vendors ................................ 158 A 4 Regulators with highest power density from vendors ................................ ....... 159 A 5 Capactors from vendors ................................ ................................ ................... 161
10 A 6 Inductors from vendors ................................ ................................ ..................... 162 B 1 TPS62621 buck converter assembly PWM mode test data .............................. 164 B 2 TPS62621 buck converter assembly PFM/PWM mode test data ..................... 164 B 3 TPS62621 buck converter assembly efficiency Vs temperature data ............... 165
11 LIST OF FIGURES Figure page 1 1 A typical power architecture of laptop ................................ ................................ 20 1 2 Three kinds of DC/DC converters ................................ ................................ ...... 21 1 3 A post CMOS buck converter with on chip LC filter ................................ ............ 26 1 4 Typical synchronous buck converters for 2 .7 5.5V input voltage, 1.8V output voltage, and 500 600mA output current. ................................ ............................ 31 1 5 Loss breakdown for a 4MHz buck converter. ................................ ..................... 32 1 6 A fully integrated power converter with in silicon spiral inductor ......................... 34 2 1 PCB based Inductors and capacitors for a 60W DC DC converter. ................... 38 2 2 Half v iew of a PCB based inductor ................................ ................................ ..... 38 2 3 3D explosive views of Mn Zn Ferrit e/Polyimide based inductors ........................ 39 2 4 LTCC for power inductor integration. ................................ ................................ .. 40 2 5 LTCC spiral inductor. ................................ ................................ .......................... 41 2 6 LTCC toroidal inductor. ................................ ................................ ....................... 41 2 7 Packaging chips ................................ ................................ ................................ 44 2 8 Enpirion fully integrated converters. ................................ ................................ ... 44 2 9 Fuji FB6831J micro DC DC converter. ................................ ............................... 45 2 10 Photograph of a fully integrated buck converter with bond wire ind uc tor ........... 46 2 11 Integration approaches of the Enpirio n EL700 family buck converter s ............... 47 2 12 Enpirion developing roadmap for WLM converters. ................................ ............ 48 2 1 3 Photograph of a fully integrated buck converter with CMOS inductor ................ 50 2 1 4 SEM image of a toroidal spiral on low resistivity substrate ................................ 50 2 1 5 SEM image of a suspended spiral inductor on CMOS ................................ ....... 51 2 1 6 Close up photograph of the polysilicon shield ................................ ................... 51
12 2 1 7 Sequential plating process for spiral windings with thick conductors. ................. 52 2 1 8 Thin film inductor with sputtered CoHflaPd core ................................ ................. 53 2 1 9 Bar type inductor with e lectroplated NiFe permalloy ................................ ......... 53 2 20 A 12 turn toroidal winding with laminated core ................................ ................... 54 2 21 Spiral inductor with Zn ferrite and Fe based amorphous/polyimide core. ........... 55 2 2 2 TEM micrograph of two magnetic nanocomposite pastes. ................................ 56 2 2 3 The prototype inductor with ferromagnetic nanopaticles into polymer matrix. .... 57 2 2 4 Schematic of the in silicon SU8 core toroidal. ................................ .................... 58 2 2 5 Schemat ic of the V groove inductor ................................ ................................ .... 58 2 2 6 Circular spiral Inductor in Silicon. ................................ ................................ ....... 59 2 2 7 Surface vi ew for Von Mises Stress in the c opper windings ................................ 63 2 2 8 Slice view of Von Mises Stress for copper/polymer/magnetic interfaces ............ 63 3 1 Schematic of t he same wafer integration of power inductor with ICs. ................. 73 3 2 Schematic of t he stacked wafer integration of power inductor with ICs. ............. 73 3 3 Process flow for wafer level integration of MEMS inductors/transformers .......... 74 3 4 Post CMOS MEMS integration of passives on the same wafer .......................... 75 3 5 Schematic of t he bonded wafer integration of power inductor with ICs. ............. 76 3 6 Smallest regulators investigation ................................ ................................ ........ 77 3 7 Power levels from different suppliers at the highest switching frequency. .......... 77 3 8 Highest power density from the suppliers. ................................ .......................... 78 3 9 Available capacitance density from suppliers. ................................ .................... 79 3 10 Inductor performances from the suppliers. ................................ ......................... 81 4 1 Spiral and Toroidal inductors/transformers ................................ ......................... 84 4 2 The surface traces in toroidal windings. ................................ ............................. 87 4 3 S imulation results for spiral and toroidal windings ................................ .............. 89
13 4 4 Primitive elements of the spiral and toroidal windings with flux contours. ........... 90 4 5 Frequency responses of the conductor resistances in Fig ure 4 4 ...................... 91 4 6 cross section and top views of the magnetic field distribution pattern for toroidal and spiral windings. ................................ ................................ ............... 92 4 7 Frequency responses of t oroidal and spiral inductor s. ................................ ....... 93 4 8 Basic matrix inductor/transformer design. ................................ .......................... 95 4 9 One constant flux transformer design. ................................ ................................ 98 4 10 Second constant flux transformer design. ................................ .......................... 99 4 11 Cross section views of stacked windings and parallel windings. ...................... 100 4 1 2 ................................ ........................... 102 4 1 3 Analytical estimation of the winding resistance ................................ ................. 109 4 14 Analytical estimation of the core resistance ................................ ...................... 110 4 1 5 Inductance/resistance measurement and estim ation of one spiral sample ....... 111 4 1 6 Optimization process for sizing analysis ................................ ........................... 114 4 1 7 Range quality for a toroidal inductor ................................ ................................ 117 4 1 8 Torus performance with different dimensions ................................ ................... 117 4 1 9 Inductance vs. innermost/outermost radius for constant flux inductors ............ 118 4 20 A constant flux inductor design ................................ ................................ ......... 119 5 1 SEM picture of a through wafer via with a negative slope sidewall ................... 121 5 2 An example of pulse reverse electroplating ................................ ...................... 122 5 3 Surface polishing for a 2 8 0m Si wafer embedded with 6 0 /40 m width/spacing square spiral coils ................................ ................................ ...... 123 5 4 SEM picture of the magnetic composite. ................................ .......................... 125 5 5 B H curve of the 89wt% NiZn ferri te and 11wt% PDMS composite .................. 126 5 6 Frequency response of c omplex permeability ................................ ................. 126 5 7 Cross section view of fabrication processes for circular spiral inductor ............ 127
14 5 8 Inductance, Q and AC resistance verse frequency of the 10 turn circular spiral inductor. ................................ ................................ ................................ .. 128 5 9 Photographs of the placing of solder balls or converter regulator. .................... 130 5 1 0 Cross section view of fabrication processes for toroidal inductors/transformers ................................ ................................ ...................... 131 5 11 Top views of the fabricated inductor and transformer. ................................ ...... 132 5 12 Cross section view of fabricated 4 Cu layers. ................................ ................... 132 5 13 Inductance, Q and AC resistance verse frequ ency of the 36 turn toroidal inductor ................................ ................................ ................................ ............. 133 5 14 Cross section view of Polyimide filling issues. ................................ .................. 134 5 15 Cross section view of fabrication processes for square spiral inductor ............ 137 5 16 Photographs for the fabricat ion steps of square spiral inductor ........................ 139 5 17 T he fabricated square spiral inductor. ................................ .............................. 140 5 18 Inductance, Q and AC resistance verse frequency of the 10 turn square spiral inductor ................................ ................................ ................................ ... 140 5 19 Magnetic flux density map with 3A and 6A current injection ............................ 142 5 20 Stress accumulation after photoresist baking ................................ ................... 145 5 21 Cross section view of a 10 turn square spiral inductor ................................ ..... 145 6 1 Buck converter with integrated circular spiral inductor ................................ ...... 146 6 2 Efficiency vs. load current circular spiral ................................ ........................ 147 6 3 Efficiency vs. temperature at different load current circular spiral ................. 147 6 4 Demo circuit for the square spiral inductor and measurement system; ............ 149 6 5 A photograph of the buck converter demonstration assembly. ......................... 150 6 6 Efficiency vs. load current square spiral ................................ ......................... 151 6 7 Efficiency vs. temperature at different load current square spiral .................. 151 7 1 Schematic of t he die level assembly of power inductor with ICs. ..................... 155
15 LIST OF ABBREVIATIONS BCB Benzocyclobutene CMOS Complementary metal oxide semiconductor CMP Chemical mechanical planarization CTE C oefficient of thermal extension DRIE Deep reactive ion etching LTCC Low Temperature Co fired Ceramics MEMS Micro Electro Mechanical Systems MOSFET M etal oxide semiconductor field effect transistor PCB P rinted circuit board PDMS Polydimet hylsiloxane PECVD P lasma enhanced chemical vapor deposition PI P olyimide PIiS Power Inductors in silicon PMMA Polymethyl methacrylate POL P oint of load PR Photoresist PSiP Power system in packaging PSoC Power system on chip RIE R eactive ion etch SEM Scanning electron microscopic SiP System in Packaging SoC System on Chip WLP W afer level packaging
16 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the D egree of Doctor of Philosophy WAFER LEVEL FABRICATION OF POWER INDUCTORS IN SILICON FOR COMPACT DC DC CONVERTERS By Jiping Li December 2013 Chair: Huikai Xie Major: Electrical and Computer Engineering The miniaturization trend of modern DC DC converters emphasizes on the size cutting of bulky passive components and the reby demands smaller inductance and capacitance for compact and efficient power conversions that can only be attained by a significant increase of operating frequency towards mul timegahertz range However, higher switching frequencies also place more stringent challenges for efficient POL designs, which limit the further frequency increase over tens of megahertz I mproving the integration level of magnetic components for compact interconnection s and less spare volumes in a power package is another major approach besides the frequency increase There are three levels of integration. Board level integration is applied on organic or ceramic substrates They are capable for batch fabr ication but the modules are bulky and their processing is different from the semiconductor foundry that is not preferable for the miniaturization of power modules Package level integrat ion compromises system performance to support flexible integration and provide more selections on component chips and materials. Wh en the switching frequencies shift to MHz range, the inductance requirement and magnetic
17 volume decrease, and this enables the wafer level heterogeneous integration of all components. The waf er level MEMS integration techniques enjoy in house batch fabrication, testing and packaging in conventional semiconductor foundr ies as well as the size minimization and monolithic or heterogeneous integration of power components However, the introducti on of passives on the chip complicates the fabrication process Limited material selection s and many compatibility issues for the inductor implementation in general foundry IC processes challenge integration techniques in the ability to: 1) fabricate thick as well as thick magnetic core; 2) explore high resistivity, low hysteresis loss core materials with enough permeability up to megahertz frequency; and 3) apply inexpensive and IC compatible MEMS technologies. To address these challenges, in this dissertation a wafer level integration process is proposed based on silicon molding technique s, where an in silicon power inductor can be monolithically or heterogeneous ly integrated with IC circuitry to form a compact power converter. The major idea of the proposed in silicon power inductors is to embed the electroplated copper coils and vias into the substrate and replace most of the lossy substrate with high resistivity magnetic materials. A wafer level via first het erogeneous integration process between the IC circuitry and the MEMS inductor wafers can be achieved through solder or metal bump bonding with polymer underfill A 3*3*8.3mm 3 square spiral inductor was fabricated and characterized as R DC = 84 m L=4 3 0nH, R AC = 792 m and Q= 20 8 at 6 MHz. Copper vias and surface routings were also electroplated as circuit connection and mounting pads for other power components. This square spiral inductor was then assembled with TI TPS62621
18 buck converter for demonstration, and it successfully delivered 600mA at 1.8V with a maximum 83% efficiency at 6MHz.
19 CHAPTER 1 INTRODUCTION The goal of t his work is to demonstrate wafer level MEMS fabrication of high quality power inductors and transformers, and therefore to enable large throughput CMOS compatible integration of high efficiency, high frequency switch mode DC DC converters. This chapter introduces the background of this work. Section 1.1 introduces the applications and development trend of modern DC DC converters. Section 1 .2 discusses the main fabrication methods to manufacture integrated DC DC converters: (1) CMOS MEMS processes, (2) wafer level packaging, (3) System in Package (SiP) and System on Chip (SoC). Section 1.3 explains the trend towards high frequencies Section 1. 4 summarizes the remaining challenges of manufacturing DC DC converters. Section 1. 5 defines the objectives of this project and presents the propose d solutions Section 1. 6 outlines the organization of this dissertation 1.1 Modern DC DC Converters DC DC converters are voltage regulators that increase or decrease the voltage level s They are widely applied in power supply modules for portable electronics (PDA s laptop s GPS, and smart phone s ), computers, office equipment, DC motors, spacecraft power distribution systems, and telecom transmission systems [ 1 ] DC DC converter s time diversity and low cost. In practice, digital CMOS circuits are usually designed with versatile voltage lev els to balance system performance and efficiency since the lowest possible supply voltage is the way for less power operation [ 2 ] For example, Figure 1 1
20 illustrates the typical power architecture of a laptop. To minimize the routing losses starting from the primary power source and adapt to the various voltage requirements at the ends of power supply rails, Point of Load non isolated DC DC converters are designed, where diversified modulation tools are also equipped to accomm odate wide load current variations or long time idle periods. This approach is significantly more efficient and compact than simple addition of battery cells. Isolated DC DC converters with integrated transformers are also used in many power modules such a s fly back converters, where wide conversion ratio and galvanic isolation from coupled turns are necessary for efficient and safe circuit functionality [ 3 ] Figure 1 1. A typical power architecture of laptop There are basically three kinds of DC DC converters in the market as shown in Figure 1 2. Low dropout (LDO) linear regulator s have an efficiency of Vout/Vin with the simplest structure to implement, but their applications are limited by significant loss an d heat problems at large voltage conversion ratios.
21 Fig ure 1 2 Three kinds of DC/DC converters A ) LDO low dropout regulator B) Dickson charge pump C) Synchronous buck converter The second type, switched capacit or DC DC converters, also named as charge pumps or voltage multipliers, applies switching devices to charge or discharge the flying capacitors and then regulates the output voltages with controlled circuit connections. By removing bulky inductors, they exhibit obvious advantages of small f ootprint, low profile, high power density, and easy magnetic less integration with standard CMOS processes. However, their systems are hard to maintain high efficiency over a wide input voltage range wh ich the real world usually wants, especially for batte ry supply applications. Available voltage conversion ratios are determinative factors for maximum efficiency but they are inherently narrowed by circuit topologies. Moreover, for a large load current variation, applicable regulation approaches such as freq uency and duty ratio A B C
22 modulations may vary the effective output resistance to improve the total efficiency, but at the cost of much complex systems and additional loss sources [ 3 ] [ 4 ] The third and dominat ive DC DC converters have inductive architectures where power managements are we ll suited for DC DC power conversions with ideally lossless efficiency at the entire voltage conversion ratio range and less passive and switch elements are required in the whole topology. Miscellaneous and effective regulation mechanisms are applicable a nd efficient without degrading transient performances, such as Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), Dead time adjustment, Burst mode control, Discontinuous Conduction Mode (DCM), and so on [ 1 5 ] The major drawbacks to integrate inductors are their bulky volumes compared with capacitors at the same power handling level, and process compatibility of thick metal layers and magnetic materials with standard CMOS technologies. However, simple architectures, high efficiencies at various circumstances, and advanced integration techniques assure inductive DC DC converters as the major power supply module in the foreseeable fu ture. There are also some other types of DC DC converters under research. One type uses an active inductor for DC DC converter modules [ 6 ] which realizes the virtual inductor through gyrator C networks. While replacing the bulky inductor with volume efficient capacitors and/or MOSFET switches, this approach introduces large losses in the gyrator transconduct ances which significantly impair system efficiency [ 7 ] Another is the promising digital DC DC converters which try to apply digital methods such as digital signal processors (DSP), micro controllers, flash memories and fast A/D
23 converters into the power management archite ctures, similar to the things done to the digital cameras [ 8 ] The application of digital controls offers flexibility of circuit architectures and other attracting features like low cost, but the researc hers confront tremendous challenges from the tradeoffs between high digital resolution and maximum switching frequency, large component losses, or tight output voltage regulation. However, this digital approach opens a window for next generation of power m odules. Here is one commercial example for digital DC DC converters. ZL9101M power module from Intersil C orporation integrates a digital PWM controller (571KHz switching), power MOSFETs, an inductor and other passives together in a 15*15*3.5 mm 3 QFN packag e, and reaches a 95% efficiency at 5/3.3 V input/output voltages and 6 A output current. 1.2 I ntegrated DC DC C onverters and T h eir F abrication Methods 1.2.1 Integrated DC DC Converters As shown in Figure 1 2c, an integrated DC DC converter based on inductive architecture usually comprises three parts: a switching regulator with embedded drivers, controllers, MOSFETS and other IC circuits, a bulky inductor and several filter capacitor s. For a regular power converter module, s tandard CMOS pr ocesses will fabri cate the voltage regulator ICs and the fabrication of multilayer chip inductor s or capacitors usually involve s the processes of source sheet preparation, via hole drilling, Internal conductor printing, sheet stacking, lamination and cutting, high temperature sintering terminal electroplating, etc However, many MEMS processes are also available for the inductor and capacitor fabrication, and they need special concerns on the ir compatibility with standard CMOS processes.
24 Efficient i n tegration of all three components in a power converter module is important to achieve high performances, where various packaging approaches are available at the back end of production. T wo major integration groups are popular in semiconductor industry the System in Packaging (SiP) and the System on Chip (SoC) approaches And w afer level packaging (WLP) emerges and thrives as a compact SoC approach The basic concept of WLP is to implement the circuit routing s immediately after the wafer IC fabrication but before test, burn in and die singulation. The f ollowing sections discuss the corresponding fabrication processes. 1.2. 2 CMOS MEMS Processes The scaling of modern CMOS techniques targets to smaller, faster, cheaper and more efficient circuits under the ever demanding customer expectations from portable electronics to giant spacecrafts. Typically, the feature size of MOSFET decreases with a 0.7X linear scale factor for generations, and transistor density will double every two years which is known as Moore w However, from the system level perspective, chasing the scaling pace is not the only way for performance improvement, and advanced system integration and/or packaging techniques from different function components also significant ly contribute to p erformance enhancement. For example, a typical buck converter includes active (gate driver, analog controller, MOSFET switches, diodes) and passive components (inductor, being designe d is directly related to the minimization of parasitic effects ( such as resistive loss, electromagnetic interference, signal transmission delay, impedance mismatch, etc.) and whole system compactness (include footprint and profile) [ 9 ]
25 The upper two factors were defined as OS scaling and functionality integration trends, respectively, in the white paper report of the International Technology Roadmap for Semiconductors (ITRS 2011). And, Microelectromechanical systems (MEMS) techniques emerged as a young but powerful innovatio n from semiconductor industry to implement the integration of multidiscipline functionalities. MEMS processes are micro fabrication techniques working primarily on silicon substrate and combining mechanical structures, magnetic and electrical components, or transducers into a single device with certain engineering function s Under certain fabrication adaption, the MEMS techniques are inherently suitable for CMOS compatible integratio n of components since their process techniques evolved from integration with CMOS MEMS processes and dramatic cost cut of production lines. In fact, MEMS already gained ph enomenal growth in the last two decades and grew to a hot market of tens of billion dollars in recent years according to the Yole Typical MEMS processes include thin film deposition, pl ating, lithography, dry and wet etching, wafer dicing and other technologies capable of small features. For proper integration, these micromachining processes have to be adapted into standard CMOS sequences. Major concerns include the selection of compatib le materials ( such as substrate types), thermal budget (<=450 C), chemical or particle contamination (include plasma attacks), protection of fragile structures (residue stresses, mechanical and electrostatic stresses), and capability of facilities.
26 Pre or intra CMOS approaches require very stringent criteria for the production line to avoid impairment of CMOS circuitry and MEMS structures, and therefore limit the foundry availability. On the other hand, post CMOS processes do not or slightly influence the CMOS foundries by performing the micromachining processes at a dedicated MEMS foundry. This provides much more fabrication flexibility and the trade off is stringent thermal budget and careful process design to protect CMOS circuitry. Fig ure 1 3 is the ph otograph of one post CMOS buck converter with on chip LC filter. Fig ure 1 3 A post CMOS buck converter with on chip LC filter Note: 0.18m process, 1596*1916m 2 100MHz, 3.3/1.8V input /output voltage, 48.3% efficiency at 20 90mA output current [ 10 ] 1.2. 3 Wafer Level Packaging At the back end of production, wafer level packaging (WLP) is denoted as the process of interconnection and packaging on wafer level and prior to die singulation. Device pack aging and testing may consume up to 70% production cost of the CMOS MEMS devices (ITRS report, 2011 edition), and WLP provides a low cost and reliable
27 chip scale packaging (CSP) with the smallest device potential to match the IC scaling and also process al l the packaging, testing and burn in works on the wafer level. Effectively utilization of the reliable semiconductor infrastructures for IC and MEMS packaging is one major cost saving factor. Fortunately, the passives integration in power converters does n ot need hermetic cavity or other brittle structures, and many IC packaging techniques can be applied. The passives can be fabricated on the same substrate with IC circuitry and packed like a regular IC chip (fan in or fan out WLP), or on a separated substr ate and integrated with co packaging techniques (3D heterogeneous integration on wafer level, or most hybrid approaches) [ 3 11 ] On the other hand, the lim itation of processing temperature (typical < 450 C) still applies to protect the IC circuits, and some conventional MEMS processes and materials cannot be deployed including direct fusion bonding (>800 C) and LPCVD deposition of polysilicon, silicon diox ide and silicon nitride (> 600, 650 and 650 C, respectively for LPCVD) [ 12 ] Trends of the power semicondu ctor WLP techniques demand higher current carrying capability, higher power density and smaller footprint of power modules as well as passive s integration with analog circuitry. Until the preparation of this manuscript, EP5348UI and EP53F8QI from Enpirion incorporation was the most compact and the highest power density ones, respectively, in the commercial point of load (POL) DC DC converters integrated with inductors (EP5348UI: 2*1.75*0.9mm 3 QFN14 package, 9MHz switching, 2.5 5.5V input, 0.6 V minimum out put and 0.4A output current; EP53F8QI: 3*3*1.1mm 3 QFN16 package, 140mW/mm 2 power density, 4MHz switching, 2.4 5.5V input, 0.6 V minimum output and 1.5A output current). Passive s integration
28 with IC analog circuits can greatly improve the power transfer per formance with reduced parasitic effects, and also benefit higher switching frequencies (from several MHz to 100 MHz). Moreover, WLP techniques enable the batch implementation of micro channels on both active and passive areas, which is a significant improv ement of thermal dissipation [ 11 ] To summarize, benefits of WLP techniques include : true CSP techniques for size minimization, monolithic or wafer level heterogeneous integration with low parasitic packaging, testing and burn in processes, and hence lead ing to high performance and low cost packages. 1. 2. 4 System in Package Vs System on Chip Passive s integration with IC analog circuits can significantly improve the system performance. However, complete absorptio n of the passive components into the silicon wafer confronts many manufacturing difficulties, and the semiconductor industry have experienced a natural evolution of assembly techniques at the perspectives of facility availability and cost effectiveness. Fr om board level integration of discrete components, to package level integration of element chips, and then to the ultimate single chip integration of all components, IC power industry and researchers have developed two major fabrication techniques, namely, the System in Packaging (SiP) and the System on Chip (SoC) techniques [ 13 ] SiP power converters are actually hybrid approaches, where different functional chips are assembled together in a package or module i.e. packaging chips On the other hand, SoC power converters realize the heterogeneous integration of analo g circuits and passive components into a single chip (including packaging dies) where
29 numerous MEMS integration processes were implemented to be compatible with semiconductor industry. Both SiP and SoC approaches have shortcomings. For SiPs, the hybrid a pproaches enjoys shorter development time and more fabrication flexibility but at the cost of higher packaging cost and lower performance. The separate modular packaging to integrate different chips is lack of industrial standards, and internal parasitic e ffects (stray capacitances, stray inductances, stray resistances, heat transfer, etc.) in the ir assembl ies are the major defective factors of whole system performance. For SoCs, the monolithic or wafer level heterogeneous integration is superior on miniatu rization, interconnection density, low parasitic effects and high throughput. However, the introduction of passives on the chip complicates the fabrication process which is not cost and time effective for low volume production [ 11 ] [ 14 ] 1.3 The Trend for High Frequency Power Conversion Proliferation of high density V LSI techniques and advanced System on chip (SoC) packaging modules flourishes the complex power distribution systems where 2 to 6 power supply rails are usually deployed in a typical SoC module and up to 40 point of load (POL) converters may be integrated in a board level power distribution architecture. Higher switching frequencies for the physical implementation of lateral diffusion Metal Oxide Semiconductor (LDMOS) and chip scale integration of passives are prompted with the ever increasing demand s of hi gh efficiency, high power density, excellent noise immunity, compact form factor and low weight, robust and reliable solutions of POL DC DC converters [ 15 ] The prime drive for high frequency (HF, 3 30MHz) or even ultra high frequency (UHF, 30 300MHz) power conversion is not for the increase in and of itself but for the
30 miniaturization of magnetic components which are curren tly the largest single volume contributor in a POL power module. By t heoretically study ing Figure 1 2c and follow ing the general criteri a of inductor selection in this buck converter topology we can discuss with the following two equations [ 1 ] (1 1) And ; (1 2) Where, is the rated current ripple of inductor, usually 10% to 20% of the full load current ; are the input and output voltage; are duty ratio and switc hing period; , are inductance, energy handling level and peak current of inductor, respectively. From E quation 1 1, with a fixed voltage regulation condition, same duty ratio, and equal current ripple or peak current of the inductor, inductance is inversely proportional to the frequency which means the decrease of inductance with increased frequency. Mor eover, from E quation 1 2, energy handling requirement of the inductor in a switching cycle is proportional to the inductance with unchanged peak current and thereby inversely proportional to the frequency either. This means the minim ization chance of magnetic core for energy storage purpose. This work investigated typical synchronous buck converters in the market from major POL converter vendors, and data trend certifies the above summation as shown in the following graph The inducta nce values are not continuously decreasing with
31 respect to increasing frequencies, but roughly shifting to half value stages restricted by the mass production availability of inductor suppliers. Figure 1 4 T ypical synchronous buck converters for 2.7 5.5V input voltage, 1.8V output voltage, and 500 600mA output current. From this chart, it can be predict ed that, in the foreseeable future, the commercial POL converters for 1.8V applications will require a typical inductor with 0.1 2 H inductance and work in the high frequency range (3 30MHz). Besides the significant volume deduction of passives (both induct ors and capacitors) at higher switching frequenc ies the transient response to a load change is also improved a lot attributing to the lower energy storage in the inductors and capacitors. The response time is faster, and transient voltage over or under s hoot is lower due to the wider control bandwidth at higher frequencies, which is desirable for accurate voltage regulation [ 16 ]
32 1. 4 The C hallenges for I ntegrated I nductors at High F requencies Although higher switching frequencies are benefi cial for s ystem minimization and performances, they also place more stringent challenges for efficient POL converter designs, which limit the further increase of switching frequencies. The side effects of increased switching frequencies can be summarized as followin g [ 8 ] [ 15 ] [ 17 ] First, MOSFET related losses increase with higher frequencies. Switching loss is proportional to the frequency, including the charging and discharging losses of MOSFET parasi tic capacitances and overlap losses during switch transitions. A t light load conditions, this loss will be more significant as shown in Figure 1 5. Driver power is also proportional to frequency where a lossy linear regulator is usually the supplier. Advan ced MOSFET technique is the key to alleviate MOSFET related losses, such as the implementation of 3D Tri gate transistor. Figure 1 5 Loss breakdown for a 4MHz buck converter A) At 1.4A output current B) At 0.1A output current (3.6/1.2V input/output voltage, adapted from [ 8 ] ) Second, Con duction loss is larger due to frequency dependent resistances. There are skin and proximity effects, and topology design of inductors should consider the ripple current losses from AC resistance as well as the load current losses from DC resistance. A B
33 Third, p arasitic effects will introduce more losses at higher frequencies. These parasitic elements can be from the passive components or interconnections in a package, which seriously increase the switching or conduction losses. Clearly, advanced integration te chniques and high quality passives are preferred to work at several MHz to hundreds of MHz frequencies. Fourth, m agnetic losses limit the choices of magnetic materials at higher frequencies. The total core loss is a function of frequency with a typical ind ex in the range of 1 to 2. Major concerns of magnetic materials at high frequencies include the resistance, permeability, saturation flux density and availability for mass production. NiZn ferrite polymer and thin film alloy (CoNiFe) are currently availabl e materials for high switching frequencies. Fifth, n oise level is higher at increased switching frequency. Jitter noises occupy a big portion of switching pulses at large conversion ratio or small duty ratio. And electroma gnetic interference is higher for outer circuits. Careful integration of components is necessary for noise suppression. Sixth, t hermal dissipation becomes more critical at higher power density. Hot spots originate from loss components such as MOSFETs and inductors, and there fore clever dis sipating paths are required during the chip integration or packaging processes. T here are o ther performance deficiencies such as limited conversion ratios, higher dropout voltages applicability of synchronous rectification, and so on. 1.5 Pro posed S olutio n To cope with all the challenges at this high frequency age and still take advantages of the high throughput semiconductor infrastructures, this work propose s a wafer level integration method which can fabricate in silicon MEMS inductors or
34 transformers and thus realize high efficien cy high power and compact DC DC converters. The major benefits of this wafer level integration of in silicon MEMS inductors include: an IC compatible and mass production monolithical or heterogeneous integration of power converters, easy processing materials and fabrication sequences for low cost wafer level integration, full utilization of the substrate for large cross section, low resistance and small footprint windings, adequate inductance and low c ore losses at high switching frequencies, and excellent noise immunity and thermal dissipation performances. Figure 1 6 illustrates the concept of a fully integrated power converter. Figure 1 6 A fully integrated power converter with in silicon spiral inductor As the proposed objective, t he following tasks will be pursued: 1. Review literatures and e xplore the advantages of various in silicon or in substrate designs for CMOS compatible assembly of power converters. 2. Develop lumped element models of MEMS inductors
35 3. Develop the wafer level integration process of these power inductors for high 4. Fabricate high quality inductors /transformers. 5. Build power converter assemblie s to demonstrate the capability of this wafer level integration process. 1. 6 Outlines of T his D issertation Next c hapter will explore literatures for the state of the art integratio n techniques of power inductors and compare their advantages and disadvantages. Board level, package level, on silicon wafer level, and in silicon wafer level integration techniques will be introduced and discussed. Many challenges can be identified and performance trade off s are summarized and compared for better designs. Chapter 3 streamlines the wafer level integration process of power converter modules based on the in substrate winding techniques. Size matching between components is one major concern for successful integra tion Chapter 4 show s theoretical analysis of various in substrate windings, including spiral, toroidal, constant flux, stacked windings or parallel windings. Their performances are compared and discussed Chapter 5 describes key MEMS techniques and materials for fabrication, and presents the fabrication and characterization results of the spiral and toroidal inductor s Characterization shows good performances of them D ifficulties in the fabrication process are also de scribed for further improvement Chapter 6 demonstrate s integration approaches of power modules with the fabricated inductors, and several power converters are assembled and tested with compact size s and high efficienc ies C hapter 7 summarizes the completed works and lists future works
36 CHAPTER 2 STATE OF THE ART OF INTEGRATED POWER INDUCTORS This chapter introduces the state of the art integration techniques of power inductors. Various processes as well as material selections distinguish them from each other, and the in silicon approach exhibits obvious potential for compact and high ly efficien t inductor integration. Challenges of the MEMS implementation of coils and magnetic cores are discussed and a guideline for in silicon implementation of power inductors is pr oposed. 2.1 Board Package and Wafer Level I ntegration of Power I nductors of Power ICs intrigue the continuous CMOS scaling and successive integration of components for high efficiency, high power density and small form factor POL DC DC converters. C ompared with the ever shrinking analog and digital circuits, the bulky magnetic components have been the single largest volume contributor for a long period to further minimize power converter modules. In s emiconductor industry there are two major trends to tackle with this bottleneck. One is to increas e switching frequency for lower inductance requirement and lower energy storage per switching cycle and thereby cut the magnetic volume. Another is to improv e the integration level of magnetic components for compact interconnection and hence squeez e the spare volumes in a power package. Higher switching frequencies re quire smaller passives at the price of more integration challenges such as parasitic s noises and losses, which further prompts the monolithic o r wafer level heterogeneous integration of all components into a single chip.
37 Power IC industry has developed many SiP and SoC approaches for passive s integration. To emphasize the advantages of wafer level processing, this chapter divides all kinds of SiP and SoC approaches into three groups: board, package and wafer level integration of inductors. The wafer level approach can also be roughly classified as o n s ilicon and i n silicon integration based on the ir processes. All the board level integration s belong to SiP approaches since multi component chips are mounted on the board for assembly, while all the wafer level integration s of inductors belong to SoC approaches because there is only one chip required to enclose all the necessary functionalities. However, for package level integration, the scenario is different. Some manufactures explore available component chips and utilize an additional packaging process to assemble these chips together (SiP or packaging chips ), and others develop particular proc esses for multiple functional dies and also use a specific packaging process to integrate these dies into one single chip (SoC or packaging dies ). The following descriptions are based on the board, package and wafer processing to avoid this obscurity. 2.1 .1 Board L evel I ntegration of Power I nductors For board level cases, an organic or ceramic substrate was used to construct the magnetic components, and analog chips were mounted on the substrate for a power management module. PCB board is usually the firs t one that comes into mind as organic substrate. In Figure 2 1, several structured layers of integrated inductors, capacitors, resisters, magnetic and insulation materials were embedded into the PCB board. Spiral coils were formed through etching the embed ded copper layers, and two 1mm Ferrite Polymer Compound (FPC) layers were laminated without magnetic connection to act as the
38 magnetic core (relative permeability is 14.5). The integrated coils had 50 turns, 93.1 95.6 H with a size of 42*42*4mm 3 .The total size of the 60W demonstration circuit is 55*80*4 mm 3 as the size of a credit card [ 18 ] [ 19 ] A B Figure 2 1 PCB based Inductors and capacitors for a 60W DC DC converter A) 3D Explosive view B) Demo converter [ 18 ] Figure 2 2 Half view of a PCB based inductor [ 20 ] The magnetic material can also be applied with high permeable iron foils such as electroplated NiFe or CoNiFe alloys but at the price of large eddy current losses at high f requencies. Figure 2 2 illustrates another PCB based inductor with electroplated NiFe core, where a closed core structure was realized by defining the magnetic through holes
39 with the upper and bottom plates. The inductor had 20 turns, 4.7 H, with a size of 10*10*1.29 mm 3 [ 20 ] PCB board based power modules can fully utilize the standard PCB processes and hence gain the advantages of low cost mass fabrication. But clearly, they occupied too much volume and their performances were also compr omised at high frequencies, which is not suitable for modern portable electronics. Figure 2 3 3D explosive views of Mn Zn Ferrite/Polyimide based inductors [ 21 ] Figure 2 3 shows another kind of organic substrate for passive s integration, where a 15*15*1.4 mm 3 size, 140nH planar inductor were screen printed on the Mn Zn ferrite/Polyimide substrate (40% and 60% volume ratio Rdc=15m Q=30 at 4MHz ) [ 21 ] This approach had the same problems as the PCB board ones. Besides the organic bases, there are ceramic substrates to mount IC chips. The processing temperatures for ceramic substrates are usually higher (>200 C) compared with the organic substrates (<200 C), but they are more compatible with silicon ICs in the view of coefficient of thermal extension (CTE) mismatch, where the silicon, the Low Temperature Co fired Ceramics (LTCC) and the FR4 PCB board have the values of 2.6,
40 4 7, 17 ppm/ C respectively [ 13 ] Ceramic based substrate usually has much better thermal conductivity than PCB. And these advantages attribute better performances at high frequency conditions to ceramic based passives A B Fig ure 2 4 LTCC for power inductor integration A) Simplified process flow B) One turn inductor [ 22 ] LTCC has the potential to embed passive components into multiple laminated layers and achieve compact and reliable integration of power modules, which attracts wide attention for POL converters. Figure 2 4 illustrates a simplified LTCC process and an example of fabricated inductor (105.5nH, Rdc=2.67m 28*28*1.4 mm 3 size).Here, a cavity in the middle LTCC layer was formed through laser cut T he cavity was hence filled and dried with Ag/Pt conductor paste repeatedly to minimize the paste shrinkage and level the surface after solvent evaporation The similar process for the top LTCC Cavity drill Fill with Ag/Pt paste
41 layer was carried out to form the connect pads, and all layers were finally sintered at 450 and 885 C after being laminated together [ 22 ] Figure 2 5 LTCC spiral inductor A) 3D view B) SEM Cross section view [ 23 ] Figure 2 6 LTCC toroidal inductor A) Cross section view B) Top view [ 24 ] A B A B
42 Figure 2 5 and 2 6 show another two LTCC inductors. One is the spiral inductor (3H, Rdc=350m 5*5*0.6 mm3 size) with three Ni Zn based spinel ferrite layers and two parallel Ag winding sets, and the other is the toroidal one (5H, 7.1*7.1*0.4 mm 3 size) with NiCuZn ferrite layers and Ag or Au conductor structures [ 23 ] [ 24 ] Silver alloys or gold is generally used as the conductors in LTCC inductors because of their excellent physical and electrical properties, while copper is usually applied in the flexible substrate of PCB Board based passives. Copper metallization in LTCC requires a costly nitrogen process which limits its application. The properties for copper, silver and gold are 1083, 961, 1063 C for melting points, and 1 7. 2, 1 6. 3, 2 4. 4 n m for resistivity, respectively. Limitations for LTCC inductors include small cross section areas for screen printed conductors, additives with higher resistivity in the silver pastes limited LTCC profile (2mm) to avoid cracks during sintering process, and co firing disability with non ferrite materials [ 22 ] Besides, the co firing temperature is high (around 900 C), the fabrication process is totally incompatible with semiconductor industry (Laser drill, co firing, etc.), and passives have to be integrated into a power modules on a chip basis. 2.1. 2 Package Level Integration of Power I nductors For package level integration, IC dies or chips were co packaged with the magnetic components into one package or module (side by side or stacked assembly), and interconnection traces between them were im plemented in a specific packaging process. The implementation of more sophisticated interconnections and other packaging elements ( such as mechanical support, hermetic cover, or thermal paths) can be treated as the differences from board level approaches
43 Many commercial POL converters with integrated inductors belong to this category. Table 2 1 lists some compact POL converters from Linear, Texas Instrument (TI), Enpirion, Intersil and Fuji incorporations. Table 2 1.Commercial POL converters with integrat ed inductors Vendor Model Fsw (MHz) Vin/Vout (V) Iout (A) Size (mm) Package Linear LTM8020 0.45 4 36/1.25 5 0.2 6.25*6.25* 2.32 LGA 21 TI TPS82670 5.5 2.3 4.8/1.86 0.6 2.9*2.3*1 SiP 8 Enpirion EP5348UI 9 2.5 5.5/0.6 3.3 0.4 2*1.75*0.9 QFN 14 Intersil ISL8200M 1.5 3 20/0.6 6 10 15*15*2.2 QFN 23 Fuji FB6831J 2.5 2.7 5.5/0.8 4.8 0.5 2.95*2.4*1 Considering the immaturity and difficulties of wafer level met h ods to integrate inductors with IC circuits, package level approaches provide an investment protection approach because of the less development time and flexible fabrication choices T he component chips or dies can be fabricated separately and then integrated into one module at a specific packaging process. The fabrication, testing and burn in pr ocesses of component chips or dies are also independent from each other. This leads to low cost, quick prototyping, mass fabrication at the price of packaging cost and performance degradation. Figure 2 7a illustrates a schematic integration of components i n a power module, where different components are co packaged side by side, and Figure 2 7b is a fully integrated synchronous buck converter from Vishay company.
44 a b Figure 2 7 Packaging chips a ) A schematic module ; b ) Vishay FX5545G008 example. Note: A silicon die, B magnetic, C capacitors, resistors and diodes. [ 25 ] Figure 2 8 shows the 3D views of an Enpirion converter with integrated inductor. T he solenoid inductor is co packaged with MOSFETs, IC Controllers and capacitors together through a side by side implementation. Wire bon d ing is applied for flexible design of interconnections. This approa ch achieves higher current capability (up to 15 A for EN2300 family). The disadvantages of this package include electromagnetic interference from the solenoid inductor (topology is not designed for closed magnetic path learned from Figure 2 8 ), higher resi stance from the bonding wires, and larger footprint compare with stacked approaches (13*12*3 mm 3 size for 15A EN23F0QI) [ 26 ] Figure 2 8 Enpirion fully integrated converters EN2300 family [ 13 26 ]
45 For lower current applications, stacked profiles ca n be implemented to achieve more compact integration, as shown in Figure 2 9 of an example from Fuji incorporation (2.95*2.4*1 mm 3 size, 0.5 A for FB6831J 2 nd generation). Wire bonding is implemented in the 2 nd generation instead of flip chip bonding in th e first generation to allow flexible positioning of IC circuits and further shrink chip size with the price of higher interconnect resistances, and they applied multiple wires to lower resistance and improve d current capability to some degree. [ 27 ] Fig ure 2 9 Fuji FB6831J micro DC DC converter (2 nd generation) A) Top, bottom and side views B) Cross section view [ 27 ] Besides these typical packaging techniques for magnetic integration, some resea rchers explore the packaging technique itself for direct coil formation, such as wire bonding. Figure 2 10 shows a fully integrated 0.18 m CMOS buck converter with spiral bond wire inductor (1.5*1.5 mm 2 footprint, 18nH) on top. Polymer bonded magnetic can also be coated on the wires to boost inductance, such as the MgZn ferrite epoxy with 10 16 relative permeability [ 28 ] However, the inductances are still relative low compared with the size, and it is hard to control the wire shape to obtain accurate inductance though the implementation is easy. B A
46 Figure 2 10 Photograph of a fully integrated buck converter with bond wire ind uc tor [ 29 ] Package level integration of magnetic provide s adequate flexibility of industry production and hereby achieve s wide application in commercial market. However, the flexibility also poses problems such a s the lack of packaging standards to enhance investment values. This complicates the semiconductor infrastructures, especially the package partitioning. Besides, with more and more integrated functionalities the internal parasitic effects of interconnections and the whole thermal budget arrangement also prompt much more challenges than before. Actually, if the magnetic can be developed with CMOS processes and be at fast enough manner s to catch large volume mar kets, the wafer level approache s will be always cheaper, better and preferred. 2.1.3 Progress of the C ommercialized Wafer Level Integration of Power Inductors All packaging approaches target to an effective integration of high quality, small form factor and high power density inductors with the analog circuitry. However, Wafer level approaches provide better performance and smaller system size through more compact interconne ctions. The disadvantages of wafer level approaches are the long development time and sophisticated production line s which compromise the cost saving goal of suppliers. Multiple o n or i n s ilicon techniques are proposed to combine MEMS
47 techniques with CMOS processes. Besides the performances, the availability of corresponding processes in semiconductor industry and also the ability for monolithic or wafer level heterogeneous integration determine the develo pment time and production complexity of possible implementations, and hence distinguish the ir advantages or disadvantages Fig ure 2 11 Integration approach es of the Enpirion EL700 family buck converter s [ 30 ] A, Side by side packaging, fabrication and packaging sequence of the WLM buck converter; B, S tacked assembly. A good news from Enpirion, Inc. was announced in the end o f 2012 that they successfully launched the EL700 family DC DC buck converters based on the world s first wafer level magnetic (WLM) technology (source: www.enpirion.com ). Their WLM developed an electroplated amorphous iron cobalt alloy (FCA) which enable s the wafer level assimilation of magnetic components into integrated circuits. The WLM technique transfers the 3D construction of discrete magnetic to a 2D thin film planar deposition of A B Step 1; Electroplate FCA on Si wafer Step 2 ; Flip FCA on Cu spiral Step 3 ; Side by side package 1, Stacked package. 2, Cross section of the stacked package. FCA FCA Cu coil FCA magnetic IC FCA Magnetic IC LDMOS Die FCA carrier (Silicon) FCA thin film Cu spiral Wire bonds
48 standard CMOS processing on top of IC wafers, which is fully qualifi ed for large scale mass fabrication [ 30 ] Figure 2 11 illustrates the current packaging approach of the EL700 family converters, and Figure 2 12 shows the aggressive roadmap of Enpirion, Inc for the developmen t of WLM products. Fig ure 2 12 Enpirion developing roadmap for WLM converters [ 30 ] The FCA has easy axis and hard axis permeability at 700 and 300 respectively, resistivity larger than 120 cm, saturation B field larger than 1.5T, and low coercivity around 1Oe. Its permeability keeps stable over 20MHz. All these properties are suitable for multiple layer deposition of magnetic construction over tens MHz, as shown in the Enpirion s roadmap [ 30 ] C ross section of multilayer FCA magnetic 2012 FCA plated on silicon (20MHz) 2014 Adding Cu on FCA on silicon (20MHz) FCA FCA Cu coil FCA FCA Magnetic IC 2016 Multilayer FCA, thick Cu and dielectric on silicon (>40MHz) Cu coil Cu FCA IC on FCA magnetic FCA magnetic FCA magnetic FCA Power module FCA Power module
49 The released 3*4.5*0.9mm 3 EL711DI DC DC buck converter works at 18MHz switching frequency with low noises and 2.7 5.5V/>0.6V input/output voltages with a maximum 1A load current Beneficial from the high switching frequency, it achieves a high power density (about 140mW/mm 2 ) and very fast dynamic responses to support high speed digital loads. However, its maximum efficiency only approach es 8 0% at 3.6/1.8V input/output settings, which is the trade off for high switching speed. Currently, more wafer level integration approaches are still under research. Although these approaches have various obstacles to be implemented in semiconductor industry, the wafer level integration of magnetic is a major path for ultra compact and cost ef fective power modules. The following sections will introduce the on or in silicon approaches under research for the wafer level integration of inductors. 2.1. 4 On S ilicon W afer Level I ntegration of Power I nductors On chip magnetic basically comprises condu ctor coils and magnetic cores. The conductor can be formed through electroplating, and sometimes from CMOS metal layers or screen printing. And magnetic cores can be deposited through sputtering, electroplating or screen printing. Air core inductor is the easiest way to realize on chip inductors, especially for planar structures such as spiral and meander ones. Figure 2 1 3 shows a fully integrated buck converter switched at 170MHz. Two stacked spiral inductors were fabricated on the 130nm CMOS process in M and 2.1 quality values for primary and secondary, respectively, 0.6*0.6mm 2 footprint).There are also non planar structures such as toroidal and solenoid implementations. Figure 2 1 4 illustrates one elect roplated toroidal inductor on silicon substrate (1.4*1.4mm 2 footprint, 2.45nH, Q=22 at 1.5GHz) [ 31 ]
50 However, the CMOS substrate usually has low resistivity and suffers a lot of eddy current losses when exposed to the high frequency magnetic fluxes, especially for planar inductors. Multiple appro aches are available to resolve this issue, such as applying high resistivity silicon wafer, removing bottom substrate, or patterning a ground shield under the inductors [ 32 33 ] The fi rst two approaches are straightforward. Figure 2 1 3 Photograph of a fully integrated buck converter with CMOS inductor [ 34 ] Figure 2 1 4 SEM image of a toroidal spiral on low resistivity substrate [ 31 ] Figure 2 1 5 illustrates one suspended inductor fabricated by 0.35 m CMOS process with the bottom substrate being etched away (1.8nH at 1GHz, Q is 15 at 15GHz, 230*230*0.95 m 3 size).
51 On the other hand, the ground shield was designed to minimize the inductive coupling between inductor and substrate by particular patterns. Figure 2 1 6 illustrates one carefully patterned polysilicon shield which partially reduced the substrate loss of a square s hape spiral inductor. Figure 2 1 5 SEM image of a suspended spiral inductor on CMOS [ 32 ] Figure 2 1 6 Close up photograph of the polysilicon shield [ 33 ] Besides the substrate losses, the thin film deposition of conductors limits achievable conductor cross section areas and significantly impairs inductor qualities. The total CMOS regions are only up to tens of microns depth, and surface micromaching techniques are usually hard to develop thick metal layers over 100
52 microns. The larger cross section area and lower DC resistanc e are essential for high current handling capability of power modules. As shown in Figure 2 1 7 researchers developed one sequential plating process to build 4 layers of copper scaffolds up to 120 m height with maximum aspect ratio of 20:1 [ 35 ] A 90 m height spiral windings from 3 layer conductors was also fabricated (130nH, Rdc=695m Q=15 at 160MHz, 1*1*0.0 9mm 3 ). Later, it wa s coated with a polymer handler layer, and then wa s detached from the carrier wafer by etching away the underneath SiO2 layer for converter assembly. However, the backfilling of magnetic materials into the copper scaffolds to form closed flux path still remains problematic T he conductor profiles are hard to control for best performance, and the device handling after being detached from carriers is a big challenge for mass production. A B Figure 2 1 7 Sequential plating process for spiral windings with thick conductors A) Fins and slits with4 layer copper B) Air core inductor with 3 layer copper [ 35 ] Although, for very high frequency operation, air core inductors may become preferable, the implementation of right magnetic cores usually have better pow er conversion efficiency with closed flux paths and enhanced inductances [ 3 ] This stimulates the application of magnetic cores. Figure 2 1 8 reported a compact spiral inductor (960nH, Rdc=900m Q=4.3 at 3MHz, 4*4*0.53mm 3 ) being sandwiched
53 between two RF sputtered CoHflaPd thin films (9 m per layer, annealed at 400 C). The conductor layer (35 m thickness) was constructed by electroplating through photosensitive polymer molds. Figure 2 1 9 realized one bar type inductor with closed magnetic path (100nH, Rdc=300m Q<2.1 at 1MHz, 4*1*0.11mm 3 ). The NiFe c ore was electroplated with a CMOS compatible process. Figure 2 1 8 Thin film inductor with sputtered CoHflaPd core [ 36 ] Fig ure 2 1 9 Bar type inductor with electroplated NiFe permalloy [ 37 ] Sputtering deposition of magnetic material is slow and hard to achieve thick films whereas electroplating deposition is quick an d cheap to fabricate large cores. However, both of them are suffered from the low resistivity of magnetic materials which limits their application at high frequencies. Lamination can alleviate this problem to some degree, and sputtering or vapor deposition is more suitable for thin film laminations. Figure 2 20 illustrates one laminated NiFe/SiO2 core to reduce the eddy current losses. A toroidal
54 inductor (500nH, Q=20 at 2MHz, 5.6*5.6*0.2mm 3 ) with 95m DC resistance was constructed by sequentially depositio n of copper layers (electroplating), insulation layers (PECVD SiO2) and middle laminated core (PVD NiFe and SiO2). A B Figure 2 20 A 12 turn toroidal winding with laminated core A) Cross section view B) The toroidal inductor [ 38 ] Both large volume and high resistivit y of magnetic cores are important to enhance power handling ability at high frequencies, and many ferrite or ceramic based magnetic materials are commercially available, which has moderate permeability (10 1500) and high resistivity (>M *cm). However, proc essing these materials usually needs sintering at high temperatures (>700 C), which is not acceptable for regular CMOS ICs [ 39 ] There are generally two approaches to resolve this problem. One is applying non conventional wet processes such as the 10 m spin sprayed Zn ferrite film at 90 C through a aqueous plating process as shown in Figure 2 21 a, which had a relative permeability ( r ) around 80, saturation magnetization (Bsat) 0.57T [ 40 ] T he disadvantages for this approach are the possible chemical contamination during plating processes and extra infrastructure requirements. Another approach is to mix the ready magnetic powders with polymer or organic binders, and powder can be ferrites as well
55 as other metal based materials. Organic binders are usually commercially used for the fabrication of chip inductors by applying high sintering temperature (700 900 C) [ 41 ] and they are easily deteriorated under environment if not burn off. For polymer binders, the magnetic composite provides much more molding flexi bility, and also other mechanical or electrical benefits such as high resistivity, thermal stability, and resistance s to environmental deterioration. Figure 2 21 b illustrates a 35 m screen printed magnetic composite from Fe Si B Cr amorphous particles and polyimide with 50:50% volume ratios The magnetic composite was fired later at 300 C for higher permeability, r =11, Bsat=0.61T. The fabricated spiral inductors had 10nH, Rdc=50m Q=20 at 100MHz, and 0.85*0.85mm 2 footprint. [ 40 ] Figure 2 21 Spiral inductor with Zn ferrite and Fe based amorphous/polyimide core A) 10 m spin sprayed Zn ferrited film; B) 35 m screen printed 50 vol.% Fe based amorphous/polyimide composite; C) schematic view of the spiral inductor. [ 40 ] For high switching frequencies, ferrites are usually the choices to be mixed with the polymer binders. Without the post sintering process, they generally suffer from the low permeability (up to tens values of the relative permeability).This is a tr ade off A B C
56 between high permeability and process compatibility with CMOS. However, high permeability means large flux density even at medium current which may fall into early saturation of the magnetic cores. Thereby, lower permeability may provide better cha nce to improve current capability and balance the core and winding losses at high frequencies [ 3 ] A B Fig ure 2 2 2 TEM micrograph of two magnetic nanocomposite pastes A) Silica coated cobalt with BCB(50wt%); B) (NiZn)Fe2O4 nanoparticles with epoxy [ 41 ] Researchers also explored the opportunities from nano structures to improve the magnetic properties and also provide low temperature fabrication procedures capable for post CMOS proc ess ing Xiao et al developed two magnetic nanocomposite pastes capable for thick core loading as illustrated in Figure 2 2 2 [ 41 ] .The Co silica BCB and NiZn ferrite epoxy magnetic composites have 5 15 relative permeability at MHz frequencies. Yang et al embedded ferromagnetic nanoparticles (NiFeMo permalloy) into an ins ulating matrix (photoresist, or other polymers) to reduce core losses by suppressing the eddy current between magnetic particles [ 42 ] The calculated relative permeability was very high (up to 100 at 10MHz), but the relative im aginary permeability was also Boundary of two nanoparticles
57 high (up to 20 at 10MHz), for the 150nm particle diameter and 40nm spacing samples. The demo inductor achieved 0.47nH and highest quality factor of 20 at 8GHz. Clearly, there are trade offs between permeability and looses at h igh working frequencies. Figure 2 2 3 The prototype inductor with ferromagnetic nanopaticles into polymer matrix. 2.1. 5 In Silicon Wafer Level I ntegration of Power I nductors Compared with on silicon approaches, in silicon techniques well explored the bulky silicon substrate to improve the inductor performance, either for large cross section of conductors or for large volume of magnetic core s. Figure 2 2 4 illustrates one toroidal inductor with SU8 core, where large volume of silicon substrate was etched to embed the device into the wafer and form the electrical interconnection to outer circuitry. The toroidal inductor achieved 60nH, 399m DC resistance and a quality factor of 17.5 at 70MHz, in a 6*6*0.4mm 3 size [ 43 ] However, this toroidal indu ctor does not include a magnetic core, and the fabrication process is complicated with multiple special steps such as spray coated photoresist and dry film masks. On the other hand, Figure 2 2 5 show s one easy shape inductor with V type cross section. The fabrication started from the anisotropic etching of silicon substrate, and
58 then 3 m SiO2 was deposited to insulate the inductor from the substrate. Nanogranular magnetic material was sputtered on the side wall of groove, followed by thick copper electropla ting for conductor. A chemical mechanical planarization (CMP) process was carried out, and the nanogranular thin film was finally sputtered again on the wafer surface to close the magnetic path. This design leads to low resistance and high power density (p redicted 10W/mm 2 ) [ 3 ] Figure 2 2 4 Schematic of the in silicon SU8 core toroidal A) Bottom view; B)cross section view [ 43 ] Figure 2 2 5 Schematic of the V groove inductor [ 44 ] A B
59 The nanogranular magnetic thin film was composed from nano scale metal particles surrounded by dielectrics, which leads to relatively high resistivity (300 cm), good relative permeability (100) and saturation flux density (1T), and low hard axis coerci ve (1Oe). The demo V groove inductor achieved 3.4nH from 10 to 100MHz, 3.83m DC resistance, quality factor of 66 at 97MHz, with 10 m laminated core, in a 2*0.212mm 2 footprint. Obviously, the inductance is too small for high frequency applications and the V groove structure is not good for inductor coupling. The low inductance may be suitable for very high frequenc y application s but at that situation, it must confron t the challenges from air core inductors. Our group previously reported one spiral inductor embedded into the silicon substrate (Figure 2 26) and a 10 turn circular resistance, Q=10 at 6MHz, 3*3*0.6mm 3 ) was assembled later into a compact buck converter with maximum efficiency of 80%. The spiral winding with large cross section was filled and sandwiched by a magnetic composite from Nikel Zinc ferrite and PDMS. A B Fig ure 2 2 6 Circular spiral Inductor in Silicon A) Cross section view B) Front view of the coil and solder balls before magnetic filling [ 45 ] Copper coil Copper frame S older ball Magnetic core Surface routing Silicon residue Solder ball Cu winding Magnetic core
60 2.2 Challenges of Power Inductor I ntegration As discussed in section 2.1, the integration of passives can be divided into three groups: board, package and wafer level integration. Most commercial POL converters are based on the package level integration considering the fol lowing reasons. Board level integration works on organic or ceramic substrates, which is capable for batch fabrication. But the organic based modules are bulky and their performances are compromised. Ceramic processing is totally different from the semico nductor foundry which is not preferable. Wafer interconnections leading to high performance s Nevertheless, process compatibilities and long development time sacrifice the production f lexibility for quick implementation. Also, many on silicon or in silicon approaches cannot achieve large conductor cross section or large core volume for high power capability. Package level integrat ion compromises system performance to support flexible integration with more selections on component chips and materials. The time efficiency prompts quick response to market changes. However, handling individual chips or dies is not cost effective from the m anufacture point. While the switching frequencies shifting to MHz range, the inductance requirement and magnetic volume decrease, and this enables the wafer level heterogeneous integration of all components. The inductances of air core inductors are still not sufficient for high switching frequencies (3 30MHz), and on silicon approaches usually suffer the small cross section areas or significant substrate losses. Fortunately, i n silicon approaches pave one way to explore the substrate itself for high
61 perfor mance. And s imple processes and easy magnetic materials are required for batch fabrication. In this work, the author select s the in silicon approach for the inductor integration. The performance comparison of these integration techniques is summarized in T able 2 2, where wafer level integration is divided into o n and i n silicon techniques since i n silicon techniques are superior on performances. Table 2 2.Performance comparison of different integration techniques Board level Package level On silicon In silicon Size Large (tens mm) Medium (2 to tens mm) Small (<2 mm) Small (several) Inductance High ( H) High ( H) Low ( n H) Low ( n H) Core v olume (related to size) Large Large Small Medium Conductor c ross section ( m) Large (hundreds by hundreds) L arge (hundreds by hundreds) Small (tens by tens) Medium (tens by hundreds) Power density (mW/mm 2 ) Low (tens) Medium (<140) High (hundreds) High (up to thousands ) Magnetic material More options More options Limited Limited Packing cost High High Low Low Robustness High High Low Varies Note: () indicate s the level th is technique can usually achieve. And the core volume and conductor cross section are directly related to saturation current and DC resistance, respectively. 2.2.1 MEMS I mplementation of C oils For windings, there are several topologies available, such as spiral, toroidal, solenoid, meander, etc. However, the spiral and toroidal ones are usually preferred due to their capabilities for large mutual inductance between turns and for closed magn etic flux paths. Three layers deposition are required for implementation. Either the magnetic
62 core is sandwiched between two conductor layers (toroidal) or the conductor coil is sandwiched between two magnetic layers (spiral). Coil implementation requires large cross section, small form factor, more turns and simple fabrication process. The first challenge is small features with high aspect ratios. Smaller winding spacing or taller conductors are limited by the processes or materials. For in silicon winding s, DRIE are usually used for high aspect ratio trench etching where the conductors with large cross section are electroplated. DRIE is kind of a standard MEMS micromaching tool and can generally achieve 25:1 aspect ratio. On the other hand, for coil electr oplating on the wafer surface, high aspect ratio molding materials are required. General photoresists cannot achieve thick deposition with high aspect ratio (generally less than 8:1). And the negative SU8 may reach millimeter level deposition and up to 20: 1 aspect ratio. SU8 patterns can also be remained as structural materials after development. However, SU8 is kind of highly cross linked epoxy and the residues after development are hard to be cleaned [ 46 ] There are also other structural materials available, including PI (polyimide), PDMS (Polydimethylsiloxane), PM MA (Polymethyl methacrylate), BCB (Benzocyclobutene). All of them have photo patternable products, but the achievable aspect ratios are limited (generally around 2:1). Material selection should consider these limitations for reliable construction of coils. Coil construction must consider the electrical, mechanical or chemical stresses development under different environments. Device failure s may be caused by dielectric breakdown over heating, mechanical crack or delamination, and surface corrosion Silicon dioxide is a general MEMS dielectric material, however the achievable film thickness is limited in 2 3 m due to high residual stresses introduced during fabrication
63 processes. Polymer based structural materials are thick elastics with low Young s modulus to avoid coil cracking, but the mismatch of coefficients of thermal expansion (CTE) between conductor (or silicon or silicon dioxide) and polymers may cause delamination problems. Structural materials should be selected to balance these conflicts. Round co rners are usually recommended in the coil patterns to relieve thermal mechanical stresses under temperature rises. Figure 2 2 7 Surface view for Von Mises Stress in the c opper windings Figure 2 2 8 Slice view of Von Mises Stress for copper/polymer/magnetic interfaces Cu area 1 m SiO2 Cu area Magnetic material Stress buffer Cu windings Magnetic rings
64 Figure 2 2 7 &2 2 8 illustrate the stress concentration profiles for a particular MEMS structure under a 200 C temperature rise. From Figure 2 2 7, the lighter blue part has higher stress compared with the darker part, and we can clearly see that the stresses concentrate at the sharp corners of the copper lines. As shown in Figure 2 2 8, a PDMS stress buffer is employed under the straight copper lines where some light red region s show the stress concentration at the copper line corners. Th e 5 m thick PDMS buffer significantly reduces the stress down to the safe range around 400MPa Table 2 3.Properties comparison of different structural materials materials Young s modulus GPa CTE ppm/K Poisson s ratio Density Kg/m 3 Dielectric Strength (V/ m) Si 170 2.6 0.28 2329 SiO2 70 0.5 0.17 2200 1000 ( PECVD ) Cu 120 16.5 0.34 8960 PDMS 0.0026 ( Sylgard 184 ) 0. 16 ( WL5150 ) 0.37 ( WL5351 ) 325 ( Sylgard 184 ) 236 ( WL5150 ) 211 ( WL5351 ) 0. 48 1030 21 ( Sylgard 184 ) 39 ( WL5150 ) 83 ( WL5351 ) PI** 2.4 40 0.5 14 2 0 155 PMMA 3 70 0.4 1190 15 BCB 2.9 42 0.34 950 5300 SU8 4 5 21 50 0.22 1200 <40 All PDMS from DOW CORN I NG C orp ** Polyimide from HD Microsystems C orp PI, PDMS, BCB and PMMA are also general packaging materials to support and protect the devices from environmental corrosion, which are ideal structural materials to
65 relieve stress fatigue. The danger of delamination from CTE mismatches is the possible exposure to environmental corrosion, but these polymers are good coating materials to seal devices and hence resolve this problem Table 2 3 show s the comparison of diff erent structural materials. For MEMS implementation of coils, electroplating process is generally the first choice for thick conductor formation because of its capability for low cost and fast deposition. There also have wet etching baths for forming silic on trenches or removing extra conductors. All of these processes require the device being exposed to different chemical solutions, which may be dangerous for CMOS circuits or MEMS structures. Careful design and preparation are necessary to avoid chemical c ontamination and guarantee uniform outputs. CMOS and MEMS processes strongly require a flat wafer surface to work on. Conductor electroplating and magnetic filling may result in an uneven surface, which necessitate a reliable polishing step. Fortunately, c hemical mechanical planarization (CMP) on wafer level fabrication is already well developed in industry, where the combination of chemical etching and abrasive polishing is involved for wafer planarization. 2.2.2 MEMS Implementation of M agn etic C ore The implementation of right magnetic cores can usually boost the winding inductances and achieve better power conversion efficiency, and also provide closed flux paths to avoid extra substrate losses and electromagnetic interference s [ 3 ] This stimulates the application of magnetic cores even at very high fr equencies. Section 2.1 already introduced several implementation forms of magnetic core s such as sputtering,
66 electroplating, lamination, ferrites or ceramics sintering, spin spray, polymer bonding and nanogranular thin films. There are critical properties of magnetic cores to be concern ed The first one is the relative permeability of magnetic cores, which determines how much inductance can be boosted with the same topology. However, there are other limiting factors to apply high permeability magnetic core s. Let us check the following two equations for a typical inductor with ferrite core. (2 1) And Steinmetz model of core loss: (2 2) Where, is the relative permeability, and is the vacuum permeability; are the magnetic field and flu x density; are the turns, carrying current, length of flux path, and working frequency of the inductor coil; are the core loss and core volume; are the adapted parameters for the Steinmetz model. From Equation 2 1 with the same carrying current, higher permeability means higher magnetic flux density, which may lead to early saturation of magnetic cores. And from Equat i on 2 2, both higher frequency and higher magnetic flux density will resul t in more core losses, and magnetic flux density has more significant influence (generally, ). This is the reason why most magnetic cores try to lower the field to only 10mT and limit the working frequency in or below the high frequencies range [ 3 ]
67 From the physical view of the core losses, there are hysteresis, eddy current and residual losses at high frequencies. And these losses are originated from magnetic friction, induced voltage and domain wall da mping, respectively. The hysteresis loss is proportional to the frequency and the classical eddy current loss is proportional to frequency square [ 47 ] .Obviously, lower coercive force and higher resistivity of the magnetic materials are important to reduce these losses. All of above limitations indicate an ideal implementation of magnetic core with medium relative permeability (<100), adequate saturation flux density (>1T), low coercive force (<2Oe) and high resistivity (>1e 4 cm for thin film and >1e5 cm for thick film) for high switching frequencies. However practical materials can not satisfy all the specifications simultaneously, and there are trade offs to select the magnetic core materials. The availability of relative infrastructures and the processing complexity are also determinative factors for batch fabrication. Table 2 4 lists the typical commercial or research magnetic ma terials working for high switching frequencies, and their performances are compared. Commercial NiZn ferrites can obtain enough permeability, high resistance and low Coercive forces, which indicates their good performance at high frequency range. Bulk MnZ n ferrites suffer from the lower resistivity and are limited in the lower range of high frequency. Kool Mu powder and Iron powder have even lower resistivity. All these commercial products need sintering processes for powder preparation and cannot be direc tly integrated into CMOS or MEMS processes. For research materials, Ni 80 Fe 20 permalloy and CoNiFe alloy were well developed with high permeability, high saturation flux density and low coercive force. The
68 deposition processes can be electroplating or sputte ring. However, they suffer from the low resistivity. Although the lamination can be applied, the achievable cross section areas are still limited, and power density and efficiency were compromised. Table 2 4.Typical commercial and research magnetic materials for HF power conversion materials (MHz) (T) (Oe) ( cm) Process **NiZn [ 48 ] (Ferroxcube 4F1) 1 50 80 0.32 1.87 1e7 High temperature **MnZn [ 48 ] (Ferroxcube 3F5) 0.5 4 650 0.38 0.75 1e3 High temperature **Kool Mu [ 49 ] (Magn etics 60 ) 0.1 2 60 1 0.5* 1e 2* High temperature **Iron Powder [ 15 ] [ 48 ] [ 50 ] (Ferroxcube 2P) 0.1 0.5 40 90 0.95 1.6 11 25 1e 2* High temperature Permalloy (Ni80Fe20) [ 39 ] [ 51 ] 10 400 800 0.9 1 0.4 0.7 4e 5 Electroplating Nanogranular film (CoZrO) [ 3 ] [ 52 ] 1000 70 100 0.9 1.2 1 3.5 6e 4 1e 2 Sputtering Polymer bonded ferrite [ 18 ] [ 53 ] [ 54 ] 100 5 25 0.2 0.3 7 15 1e4 1e12 Screen printing Thin film alloy (CoNiFe) [ 55 ] 1 10 600 2.1 1.2 2e 5 Electroplating *By estimation. **Commercial products. Like the metal alloys, the sputtering deposition of CoZrO nanogranular films need an outer magnetic fi e l d to align the magnetic core to the desired anisotropy orientation. The hysteresis loop will exhibit hard axis and easy axis (energetically favorable di rection). And hard axis shows a much lower hysteresis loss which is preferred for high
69 frequency operation. Nanogranular thin film up to several micron thicknesses has demonstrated good performance up to several GHz [ 56 ] which promises their application in high and very high frequency range. Howeve r, the strong uniaxial in plane anisotropy limits the topology design of coils, and also further complicates the deposition system. Polymer bonded ferrite is a mixture of polymer and ferrite powder, which combines the favorable properties of the compo nen ts High resistivity and processing flexibility are their obvious advantages, which promise their implementation for high frequency power conversion and easy adoption for high throughput mass fabrication. Relative low permeability and saturation flux density are their disadvantages, but for high switching frequency, working at 10mT maximum flux density is usually preferred to lower the hysteresis loss, and hence a little lower permeability and saturation flux density are not determinative parameters. This wor k utilizes the polymer bonded NiZn ferrite for demonstration of the wafer level integration of passive inductors. 2.2.3 Trade Offs of Power I nductor I ntegration Inductor s or transformers with small size, low winding resistance, low core loss, high power ca pacity, high breakdown voltage, large coil inductances, and high coupling coefficient between turns are always favorable. However, there are some competing factor pairs. To have lower DC resistance, it needs more area for conductor paths. To have lower AC resistance, thin film conductor is preferred to limit the skin effect, and enough film spacing to limit the proximity effect. To gain high power capability, the saturation current needs to be improved at the expense of large magnetic core. To increase the inductance, more turns are needed which will reduce the saturation current and increase winding resistance. Increasing the permeability of magnetic core can
70 obtain higher inductance, but this will also reduce the saturation current with th e same physical size. More over larg er core thickness will introduce more eddy current losses. To ensure enough dielectric strength, thicker isolation layers are preferred but it will reduce the inductive coupling coefficient between windings Table 2 5 il lustrates these competing factors. Table 2 5. Competing factors for inductor/transformer implementation factors Small size Low loss High power density High breakdown V oltage High Inductance High Coupling Small size Low loss High power density High breakdown V oltage Large Inductance High Coupling Note: means there is competition between the two factors in the header column and header row. By considering all the competing factors and all the challenges described in the previous sections the following guidelines for the topology and material selection and process design must be followed: 1. Full utilization of the substrate area to construct conductors with large cross section area (>100m thickness) for low resistance and higher current capability, and also increase the magnetic core volume. 2. High aspect ratio conductor structures are preferred for lower resistance ing skin effects and limited space budget.
71 3. Closed or quasi closed magnetic path is required to avoid extra losses and electromagnetic interference s Large core volume for higher working current (>2A). 4. Materials should be chosen for multiple purposes. For e xample, a passivation layer can work as both electrical isolation and stress buffer And metal conductor can work as thermal dissipation paths. 5. Process design should be easy implementation and at low temperature and totally compatible with CMOS circuitry, level batch fabrication.
7 2 CHAPTER 3 WAFER LEVEL INTEGRATION OF IN SILICON POWER INDUCTORS This chapter introduces the integration methods and basic process of wafer level integration of MEMS inductors and transformers based on in silicon techniques Size match of components is one major concern for effective passive integration on wafer level, which is investigated to guide the selection of designs. 3 .1 Proposed Integration M ethod s As discussed in chapter 1 and 2, wafe r good device performances. This integration processing saves costs by applying batch fabrication, device packaging, modular testing and burn in proc esses on wafer level. Post CMOS techniques enable passive s integration to CMOS circuitries with minimal influences on semiconductor foundries, and these IC compatible procedures may be performed at a dedicated MEMS foundry with much more flexibilit ies How ever, process compatibilities and material availabilities are the major impediments for the wafer level integration. This work applies the in substrate fabrication of power inductors or transformers with easy processing materials such as the electroplated copper conductor and polymer bonded magnetic composites. Simple and IC compatible MEMS processes can fully utilize the substrate for large cross section windings and thick magnetic cores. Figure 3 1 and Figure 3 2 illustrate the same wafer and bonded wafer integration between CMOS power ICs and MEMS power inductors They are wafer level compact integrations. T he toroidal topology is more flexible for same wafer or stacked wafer integrations, while the spiral one is not suitable for the side by side integrat ion. Two
73 thick magnetic material layers are required to enclose the windings but not intended to cover the CMOS circuitries at the side by side integration of spiral inductors. A B Figure 3 1 Schematic of t he same wafer integration of power inductor with ICs A) Top view of toroidal inductor with power IC B) Cross section view of toroidal inductor with power IC A B Figure 3 2 Schematic of t he stacked wafer integration of power inductor with ICs A) 3D view of the six layers in a fully integrated converter B) 3D explosive view of a fully integrated converter with spiral inductor 3 2 Process Flow Figure 3 3 illustrates the proposed process flow for the wafer level integration of power inductors. CMOS circuitries are first implemented on the blank wafer in a regular semiconductor foundry, followed by the post CMOS MEMS fabrication of passives. The Substrate Magnetic core Cu routing CMOS IC Cu routing CMOS IC Magnetic core Cu coil
74 integration of passives can be on the same wafer or through the wafer to wafer bonding. In Figure 3 3 one toroidal inductor and one spiral inductor are drawn to show the same wafer integration (side by side) and bonded wafer integration (stacked), respectively. After the passive s integration, the device dies are sealed with redistribution layer and subseq uently tested on the wafer level packaging process. Burn in processes can also be carried out at this stage. The final devices are released at regular dicing process, and the whole process offers low cost, high volume throughput and compact system integrat ion. Figure 3 3 Process flow for wafer level integration of MEMS inductors/transformers The passive fabrications for same wafer integration or bonded wafer integration are similar, and the difference is that they start from different wafers with or without the CMOS circuitries. The bonded wafer integration is actually a wafer level heterogene ous
75 integration process where two component wafers are fabricated separately and bonded together with accurate alignment. Figure 3 4 show s the general process for side by side integration of toroidal inductors on the same wafer, which can also be applied for the preparation of spiral inductors in the bonded wafer integration. Via filling is the first step by DRIE substrate etching and copper electroplating. After the surface planarization by CMP, one side conductor deposition follows. Next, the trenches fo r magnetic core are formed by DRIE etching T here are two approaches available for the magnetic material filling O ne is by pressing the slurry mixture s from polymers and magnetic powders into trenches, and the other is by ink jet filling of th ese magnetic mixture s Both approaches require vacuum environments for void free filling of the trenches, and moldable magnetic composites are necessary for th is purpose Another surface planarization is carried out. And the last inductor segments and their i nterconnections to the CMOS circuitries can be implemented simultaneously on the top side, which finishes the inductor integration. Fig ure 3 4 Post CMOS MEMS integration of passives on the same wafer Figure 3 5 shows the wafer level bonding process for the bonded wafer integration, where the conductive pads on the inductor wafer can be solder balls or
76 metal pads. The solder balls or metal pads can also be on the CMOS wafer and the inductor wafer works as landing substrate. This heterogeneous integration process starts with the preparation of the conductive pads, either t h rough solder bonding, eutectic bonding, copper electroplating or CMOS process for thick metal pads. Then, the two wafers are integrated together by solder or eutectic bonding at suitable temperature condition. Finally, under fill polymer is injected into the wafer gap to strengthen the bonding and provide seal protection. Figure 3 5 Schematic of t he bonded wafer integration of power inductor with ICs A) Pads preparation B) Solder or eutectic bonding C) Polymer under fill The process flow only show s the concept for whole integration processes, and detail ed discussion s are in chapter 5 to enable the processes in real conditions. How well the passives should be designed to economically and effic iently match passives with CMOS circuitries? The following sections will answer these questions. 3 3 Size Matching Investigation for Wafer level Integration Chapter 1 has provided the basic schematic design of a buck converter with IC regulator, inductor, capacitors and resistors However, on what level the dimension sizes, inductances, or current capabilities should be designed for conventional high C Spiral inductor CMOS IC B A Conductive pads Landing pads Polymer underfill
77 frequency POL converters is still not answered. To build a real picture of product specifications from curr ent power management industry, this work investigated the POL converter products from 14 suppliers as shown in the following figures. Figure 3 6 illustrates the smallest regulators from suppliers, where a clear trend shows that higher frequency is a major drive for total volume or footprint deduction of regulators. The regulators can usually occupy 0.85 2mm dimensions in footprint and 0.4 1.1mm (limited by package) dimensions in profile. A B Figure 3 6 Smallest regulators investigation A) Regulators without inductor B) Regulators with inductor A B Figure 3 7 Power levels from different suppliers at the highest switching frequency A) Regulators without inductor B) Regulators with inductor
78 Figure 3 7 illustrates the power levels of the regulators which have the highest converter can be roughly estimated by the maximum output voltage and current. Although the power l evels do not change much or even become smaller, the total trend shows that power densities are higher with higher frequencies. The highest switching frequency under this investigation is 9 MHz from Enpirion EP5348UI POL converter. Observing the power densities only from the products at the highest switching frequency may be not accurate. Figure 3 8 illustrates the POL products with the highest power density from the suppliers (note: calculated from product specifications). The trend show s a similar result, where the calculated power densities per volume or per area are getting higher with increased frequencies. For POL converters with integrated inductors, 0.45 W/mm 3 or 0.65 W/mm 2 power density is the highest power density achievable in commercial products. A B Figure 3 8 Highest power density from the suppliers A) Regulators without inductor B) Regulators with inductor. N ote: calculated from product specifications Solely considering the CMOS regulator is not enough for the size matching between converter components. Besides the CMOS regulators and inductors, multiple input or output capacitors and resistors are also important for converter functionali ties.
79 This work also investigates the passive products from 10 major suppliers, including inductors, capacitors and resistors. There are standard packaging criteria for inductors and capacitors, and the smallest package is 0.4*0.2*0.2 mm 3 (01005 type) size On the other hand, the resistors do not have size limitation on theory, and their dimensions are mainly restricted by the equipment capabilities. Commercial resistors are from thin film depositions of TaN, SiCr, Ruthenium oxide, Tantalum nitride or Carbo n Resistive Element. A B Fig ure 3 9 Available capacitance density from suppliers A) Capacitance per area B) Capacitance per volume Figure 3 9 illustrates the achievable capacitance densities from different suppliers. From the statistic chart, tantalum electrolytic capacitors have the highest the risk of a fire hazard. In real applications, the ceramic or thin film capacitors are usually preferred for POL converters. High density MEMS capacitors are already available, which achieve 400nF/mm 2 density on high k MIM (TiN / Al2O3 / TiN) capacitors (IPDiA commer cial integrated capacitors). Compared with Figure 3 9 these MEMS capacitors obtain similar performances approaching the ceramic capacitors, and this indicates a good opportunity for wafer level integration of all passives in the POL
80 converter modules. As estimated in literature [ 57 ] at 10MHz, at least 600nF capacitors are needed, which corresponds to a 1.5mm 2 area requirement for the MEMS capacitor. Hence, based on the ceramic capacitors and MEMS capacitors, the capacitor sizes can be roughly estimated as 0.4 2mm in footprint dimensions and 0.2 0.5mm in height, and their capacitances are roughly in 0.2 10 F ra nge for the POL converters. Compact inductors are also investigated from the suppliers to compare with our in substrate inductors and predict their performances. Previous in substrate spiral inductor achieved 390nH on a 3 by 3 mm area, which is 43.3nH/mm 2 This inductance density is low, compared with the commercial ones, mainly due to the available permeability of the magnetic cores. Commercial chip inductors have flexible selection of magnetic materials (higher permeability) and winding methods (more laye rs or topologies). And they can also be small, around 1 by 0.5 mm area for several hundreds of nano henries. However, their fabrication is not compatible for the CMOS circuitries, and their DC resistances are also high (several ohms for hundreds of nano he nries). At larger dimensions, higher inductance density can be achieved and DC resistance can also be well controlled due to the equipment capability. For these compact commercial inductors, Figure 3 10 a shows that both the inductance density and DC resis tance are generally higher with increased inductances at small dimension ranges. And Figure 3 10 b illustrates that both the self resonant frequencies and rated current capabilities are also getting lower with increased inductances, which is not good for th e POL converter designs. The general high frequency POL converters require more than 0.4A output currents and over 100nH inductances. Therefore, dimensions under 1mm of the commercial inductors are not
81 sufficient for the POL converter applications, and the se dimension should be doubled to achieve the required performance (around 2mm dimensions in footprint, and 0.5 2mm in profile). A B Figure 3 10 Inductor performances from the suppliers A) Inductance density and DC resistance B) Self resonant frequency and current capability In section 1. 3 this work already predict that a typical inductor with 0.1 2 H inductance will be required to work in the high frequency range (3 30MHz).The designed MEMS inductors may be a little larger in footprint to accommodate the CMOS regulators and capacitors for fully integrated POL converters, and their heights are usually not strongly restricted. Hence, the inductor dies may be designed with 2 5mm dimensions in footprint, and regular wafers are chosen for in substrate inductors of a total height in 0.5 1mm range. To summar ize for the wafer level integration of passives, this work ha s the T able 3 1 for the typical s pecifications of the POL converter components. Table 3 1. Typical specifications for POL converter components in wafer level integration Components Items Value ranges Regulators Switching frequency 3 30MHz Footprint dimensions 0.85 2mm On 2mm dimensions
82 Table 3 1 C ontinued. Components Items Value ranges Regulators Height 0.4 1.1mm Power density (per volume) <0.45W/mm 3 Power density (per area) <0.65W/mm 2 Capacitors Capacitance 0.2 10 F Footprint dimensions 0.4 2mm Height 0.2 0.5mm Inductors/ transformers Inductance 0.1 2 H Current capability >0.4A Footprint dimensions of commercial ones >2mm Height of commercial ones 0.5 2mm Footprint dimensions of MEMS ones 2 5mm Height of MEMS ones 0.5 1mm
83 CHAPTER 4 DESIGN AND MODELING OF POWER INDUCTORS/TRANSFORMERS This chapter compares the topology designs of windings (spiral vs. toroidal, constant flux inductor, and parallel vs. stacked windings). Analytical model is proposed to explain the loss origins and illustrate the performance influenc es from inductor sizing factors, which will guide the inductor designs. 4 .1 Topology D esigns Topology selections include spiral, toroidal, solenoid, meander windings, etc. However, to achieve decent inductance and suppress the interference especially at hi gh working frequencies, the spiral and toroidal ones are usually preferred due to their capabilities for large mutual inductance between turns and for closed magnetic flux to average the flux distribution in the core rings, which is preferred to avoid early saturation of some portions and hence reduce the core losses. Moreover, for transformer designs, the primary and secondary windings can be stacked together or parallel ed to each other. This section will discuss these topology designs. 4 .1.1 Spiral Versus Toroidal D esigns Figure 4 1 illustrates the explosive views of power inductors in silicon with spiral or toroidal windings. Both of them have three interlinked layers, e ither two deposition layers of magnetic core or two electroplated layers of conductor. All the winding turns are closed to each other, which will boost the mutual inductances and hence enhance the total inductance. For the spiral inductor, the top and bott om magnetic layers enclose the winding and shield the magnetic flux against from escaping. For the toroidal inductor, the theory is different but with similar results. The evenly distributed turns are close to
84 each other and carry a same current. So the ma gnetic fields of these turns strengthen each other inside the magnetic ring and also cancel each other at the spacing between turns Therefore, little leakage fluxes result. A B Figure 4 1 Spiral and Toroidal inductors/transformers A) Spiral inductor B) Toroidal inductor / transformer There are basically three equations for the inductance, DC resistance and magnetic flux density calculations: Typical inductance ( ) calculation: ( 4 1) Typical average field calculation: ( 4 2) Typical DC resistance ( ) calculation: ( 4 3)
85 Where, are the relative permeability of magnetic material and the vacuum permeability, respectively; is turn number; are effective cross section area and effective flux path length of the magnetic core; is the winding current; is winding resistivity; and are the effective cross section area and effective to tal length of the winding conductor. For the spiral winding, the pot core case can be considered to simplify the problem. In a pot core structure most magnetic fluxes will wrap all the turns and only few fluxes pass through the winding spacing between tur ns. Then the effective values can be estimated as the following equations: Effective core cross section area: ( 4 4a) Approximate flux path length: ( 4 4b) Where, is the inner radius of the spiral winding; is outer radius; is the core layer thickness; is the silicon wafer height Calcu lating with the Equation 4 1 it will have a little over estimated inductance of the pot core inductor. But for a real spiral winding with magnetic materials between the turns, the actual inductance will be larger than the estimation, because the effective flux path length will be shorte r. For the spiral,
86 ( 4 5a) If large turns, ( 4 5 b) Cross section: ( 4 5 c) Where, is the pitch size between two winding turns, and is the winding width. For a typical toroidal winding with the same inner and outer radius as the spiral one, the effective core cross section area is: ( 4 6a) The effective flux path length is: ( 4 6b) For the DC resistance of toroidal winding, the winding can be separated as surface traces and in silicon vias as shown in Figure 4 2 For vias: ( 4 7a) ( 4 7b)
87 A B Fig ure 4 2 The surface traces in toroidal windings A) Front trace B) Return trace For front traces: ( 4 7c) For return traces:
88 Then, ( 4 7d) Where, are the resistances of one inner via, outer via, front tra ce and return trace, respectively; and is the winding spacing between turns. is the winding thickness, and can be selected as The total DC resistance for a toroidal winding is: ( 4 8a) Effective length: ( 4 8 b) Effective winding cross section: ( 4 8c) Then, we assume the spiral winding targets to one specific working frequency, and have the most compact distribution with minimum pitch size between turns at a specific inner radius. That is, the winding width can be roughly determined by the skin depth at the working frequency, and the spacing between turns can be assigned as the minimum value limited by th e facility capability. Let us assum e for 5 6MHz working frequency.
89 To compare the performances of spiral and toroidal windings, we assume the two windings share the same inductance, inner and outer radius, and hence have the same in ductance density per area. Then compare E quation 4 4 and 4 6 they achieve the following relationship: ( 4 9) Here, are turn numbers of the spiral and toroidal inductors, respectively. With Equation s from 4 1 to 4 8, for a fixed turn number, this work can calculate the inductances, average magnetic fields and DC resistances of the spiral and toroidal windings versus d ifferent inner radius. The selected conductor resistivity of copper is And by resolv ing these equations, this work has the results as shown in Figure 4 3 for the10 turns spiral and corresponding toroidal. Fig ure 4 3 S imulation results for spiral and toroidal windings
90 From Figure 4 3 the spiral resistance is always lower than the toroidal one, since the toroidal winding has to increase the turn number to match the same inductance. Remember the actual spiral inductance is large r than the values predicted by E quation 4 4. The average flux density of spiral winding may be a little larger, which approaches the value of toroidal one. Therefore, this work concludes the fo llowing statements for in silicon topology designs. 1. Spiral windings have smaller DC resistance than toroidal ones with the same footprint. 2. Spiral windings have larger inductance density per area than the toroidal ones with the same DC resistance. 3. The flux densities of both topologies are on the same level, and hence the power handling capabilities are similar for the same footprint. A B Figure 4 4 Primitive elements of the spiral and toroidal windings with flux contours A) Conductors in one plane B) Paralleled conductors. Note: both conductor lines are with 60*500*1200 m 3 size Studying the primitive elements of the spiral and toroidal windings, their windings are composed from the structures in Figure 4 4 The conductor lines from toroidal turns are in one plane as Figure 4 4 a, and the conductor lines from spiral coils are parall el to each other as Figure 4 4 b. The parallel pattern has higher coupling effects and hence
91 higher mutual inductance. This is the reason why the spiral topologies have higher inductance density. Skin and proximity effects are the major sources of conductor losses at higher frequencies. Inject the same 2A currents into the four conductor lines, and simulate the frequency sweep from 1K to 100MHz, then this work has the frequency responses of the coupled conductor lines as Figure 4 5 Fig ure 4 5 Frequency responses o f the conductor resistances in F ig ure 4 4 The simulation results show that the parallel conductor set has smaller resistances at higher frequencies compared with the set in one plane. This is because the major magnetic fluxes to create the proximity effects have smaller cross section to circulate the eddy current in the parallel conductor set. One may think the spiral windings might have smaller proximity effects at high frequencies from the simulation result, but actually the toroial ones have smaller proximity effects, which is interesting. The m ajor reason is that the combined magnetic fluxes in the toroidal windings are mainly parallel to the
92 conductor lines, and in the spiral windings, some portion of magnetic fluxes hit the conductor surface with inclined angles. This work designed one toroida l inductor (18 turns, inner/outer radius=300/1300 m, winding thickness/spacing=60/40 m, core height=500 m) and one spiral inductor (10 turns, inner/outer radius=300/1300 m, winding thickness/width/spacing= 200/60/40 m, thicknesses of two core layers=200 m) with the same magnetic material ( r=8, r=25, =0 without core loss) to illustrate the flux distribution patterns in toroidal and sp i ral windings as in Figure 4 6 The two inductors were injected with the same 2A currents and had similar inductance and v olume. A B C D Figure 4 6 cross section and top views of the magnetic field distribution pattern for toroidal and spiral windings A) Cross section for toroidal wi nding B) Cross section for spiral winding C) Top view for toroidal winding D) Top view for spiral winding
93 As a result, even the toroidal windings may have higher resistances at low frequencies, they will have lower resistances at high frequencies with the same inductance and size. The flux patterns in the toroidal and spiral topologies also show that the flux distribution in toroidal structures is more uniform than the spiral one, and the spiral structure has much larger flux density at inner core portion and conductor corners. The simulation results for inductances and resistances versus frequencies are shown in Figure 4 7 Figure 4 7 Frequency responses of t oroidal and spiral inductor s Note: a toroidal inductor ( 1 8 turns, 240/1320 m inner/outer radius, 620 m total height, 60 m winding thickness as shown in Fig ure 4 6 c) and a spiral inductor (10 turns, 300/1320 m inner/outer radius, 600 m total height, 60/200 m winding width/thickness as in Fig ure 4 6b Besides the inductance densities and resistive losses of the windings, the easiness of fabrication is also one important concern for t opologies. Toroidal inductors have two conductor layers and one magnetic layer, whereas spiral inductors need two magnetic layers to enclose the middle windings. The electroplated coppers are usually L inductance R resistance
94 selected as the conductors since they can be quickly dep osited with high quality. The ready infrastructures to develop finely patterned windings favor the easy realization of toroidal conductors. However, the toroidal designs require much more through substrate vias for connection, and low contact resistance is one major concern to ensure the toroidal quality. Moreover, many newly developed magnetic materials such as nanogranular thin films are anisotropic, and their depositions require external magnetic field for the orientation of the hard axis at magnetizati on. Otherwise, a lot of core losses will be incurred due to large hysteresis loops from the easy axis of magnetic anisotropy. The toroidal topologies are hard to realize this since the flux directions are not in one axis but along the circles. However, the spiral designs have most directions in one axis which simplifies the magnetic deposition. To summarize, the performance of the toroidal and spiral topologies can be shown in the following T able 4 1. Table 4 1. Performance comparison of toroidal and spiral topologies Toroidal Spiral Inductance density higher DC resistance lower Proximity effect better Flux distribution better Power handling similar similar Anisotropic orientation of magnetization easier Fabrication similar similar
95 4 .1.2 Constant F lux Inductors and T ransformers From Figure 4 6 a, for general toroidal designs, the flux density concentrates on the inner portion of the circular core and large core volumes are not fully utilized which is not efficient. One approach is to rearr ange the windings and design multiple core rings with different turns, which leads to the designs of constant flux inductors or transformers at the price of larger dimensions as shown in Figure 4 8 The basic theory here is to balance the flux density with more turns at the outer rings. Since the effective lengths of outer flux paths are longer, they have higher magnetomotive forces at the same flux density. Higher magnetomotive forces means more turns to intensify the magnetic field in the outer rings. In Figure 4 8 a, three core rings are drawn, and turns 2, 1 and 3 rings, respectively. A B Figure 4 8 Basic matrix inductor/transformer design A) Simplified turns arrangement 3 rings; B) A flux density pattern along the radius 5 rings Distance (mm) B (T)
96 ( 4 10 ) ( 4 1 1 ) This work obtain s the following equations for turns toroidal windings, and all the turns have inner radius and outer radius ( 4 1 2 ) ( 4 1 3 ) Where, are the relative permeability of magnetic material and the permeability of vacuum, respectively; are magnetic flux density and magnetic field strength; is the winding current; is effective flux path length of the magnetic core; is coil inductance; are time variable, time varying magnetic flux, time varying voltage and time varying curr ent of the coil; are the radius variable and core height, and is the corresponding cross section area. Hence, for the constant flux transformer in Figure 4 8 a, the secondary winding obtain s an inductance as :
97 where is the secondary turns, and are innermost and outermost radius of these turns. The primary windings form a constant flux inductor has the following inductance: or ( 4 1 4 ) Assume the magnetic fields at the middles of core rings are identical, and from Equation 4 10 this work has the following relationship between turn numbers: ( 4 1 5 ) From Equation 4 1 4 and 4 1 5 this work designed one transformer as shown in Figure 4 9 The transformer had five magnetic core rings with a total 40*40*1.5 mm 3 size. 32 turns of the primary winding are arranged on the five rings to construct the constant flux inductor. 4 turns of the secondary winding step over the five rings to sense all the varying magnetic fields in the five rings which were indu ced by the primary current. And both the primary and secondary windings are on the same structural layers primary turns at the outermost ring and the secondary turns at the innermost ring,
98 respectively, to form the interleav ing windings with only two conductor layers (70 m thickness). A B Figure 4 9 One constant flux transformer design A) Core rings and flux density pattern; B) The primary and secondary windings FEM simulation results of this transformer are listed in the first row of the T able 4 2, where the coupling coefficient between the primary and secondary windings is only 0.72. To improve the coupling effects, another design is proposed to arrange every tu rn of the primary and secondary windings side by side, and then parallel the 4 equivalent cells of the secondary in the middle portion, as shown in Figure 4 10 This approach reaches an enough coupling coefficient of 0.96 as well as a good control of both primary and secondary resistances, which is attributed to the special arrangement of paralleling 32 turns primary winding 4 turns secondary winding Core dimensions (mm) Flux distribution pattern
99 4 cells of the secondary windings in the middle. Its simulation results are also shown in the T able 4 2, line two. A B Figure 4 10 Second constant flux transformer design A) 32 turns primary winding B) 4 cells of the secondary windings Table 4 2. FEM simulations of several constant flux transformers Designs ( m) Secondary Primary ( H) ( H) ( H) (m ) ( H) (m ) ( H) Parallel 1 70 24.1 0.56 97.3 10.34 1.73 0.72 4.30 0.27 7.43 Parallel 2 120 6.5 0.65 102.2 10.44 2.51 0.96 4.00 0.049 10.04 Stacked 80 5.1 0.65 83.0 10.38 2.59 0.99 3.99 2.8e 3 10.38 Note: 5 rings core with dimensions listed in Figure 4 9 a; ,. is winding thickness, is effective turns ratio, and are leakage inductance and magnetization inductance, respectively.
100 The primary and secondary windings can also be stacked together, which will achieve lower resistances and higher coupling effects of both sides but more con ductor layers. For comparison, T able 4 2 also show s the simulation results with the secondary winding stacked on the primary winding, and this stacked design has similar 4 .1.3 Stacked Windings V ersu s Parallel W indings As discussed in the last section, there are basically two approaches to arrange the primary and secondary windings in toroidal transformers. The stacked approach achieves lower resistance and highe r coupling effects as shown in T able 4 2. If we apply the same winding thickness, the parallel windings will roughly double the DC resistances of the stacked design to achieve similar inductances and coupling effects. However, stacked structures increase the number of conductor and isolation la yers, and hence significantly complicate the fabrication process. Figure 4 11 illustrates the cross section views of these two designs, where the stacked one has 7 device layers and parallel one only has 3 layers. A B Fig ure 4 11 Cross section views of stacked windings and parallel windings A) Stacked structure B) Parallel structure
101 First, to achieve lower resi stances, the windings require thick conductor depositions at least tens of microns. This leads to deep trenches between turns. Thick film deposition and etching processes are required for the winding formation. And more device layers double or triple these processes. Second, the wafer level MEMS fabrication prefers flat surface to work on, and thereby, multiple polishing steps will be also required to obtain better process control. After so much deposition, polishing and etching steps, the wafers become brittle, which will significantly limit the throughput of wafer level fabrication. Third, for toroidal windings, there are many vias embedded into the substrate. Every device layer except outer coating layers requires one deposition of the connection vias, and multiple depositions will definitely suffer much more chemical contamination and hence increase the contact resistances between deposition layers. Forth, the deep trenches between turns need to be filled with isolation or dielectric materials which ar e usually from polymers. However, the deep trench filling is a great challenge for polymer deposition, especially at high aspect ratios. Experiments had shown serious corner coverage problems of the polymer depositions. Fifth and finally, the dielectric ma terials between turns need to be pattern able for structure definition. And these pattern able polymers such as the Polyimide usually require a little high temperature (around 300 C ) for curing, and prefer SiO2 as the mask for the etching process which ma y require over 300 C for the oxide deposition. High temperature process es directly lead to crack s and delamination problems of devices. The alternative design is the parallel case, where the windings share the space in the same structure level at the expe nse of higher winding resistance and a little lower mutual inductance. The obvious advantages are the much simpler structure with only 3
102 layers, much less polishing steps, elimination of polymer filling problems, and totally low temperature fabrication pro cess because there are no need of dielectric layers to isolate the stacked windings, and winding definitions on the same surface. Although the winding resistances are higher, the parallel design has more spaces for thicker conductor deposition to alleviate the resistive losses. Therefore, the simplified parallel design is more suitable for wafer level passive fabrication and commercialization. 4 .2 Analytical M odel s of Power I nductors Power inductors model shown in Figure 4 1 2 Ba sically, the inductors are formed from turns of conductor s and these turns introduce the series resistance and the stray capacitance besides the expected inductance The and are usually not preferred by the designer since they will consume power and distort electrical response. A B Fig ure 4 1 2 S impl ified lumped model for inductor A) Analytical model B) 3D section view for p hysical explanation T here also have substrate and magnetic core which will introduce the capacitive and inductive coupling effects. The capacitive coupling through the oxide capacitance
103 and substrate resistance mainly affects the self resonant frequency of inductors, and the substrate capacitance is absorbed into the here. More, the inductive coupling will impair the inductor quality by and especially when the substrate or magnetic core resistivity is low, since they represent the second order effects of the induced curren t by time varying electromagnetic fields 4 .2.1 Lumped P arameters of Power I nductors The Figure 4 1 2 model illustrates the origination of inductor losses: 1) the ohmic losses from skin and proximity effects of ; 2) the substrate or magnetic core losses through capacitive coupling by ; 3) the substrate or magnetic core losses through inductive coupling by At high frequencies, three major effects may distort the current distribution and degrade the inductor quality with increased winding resistances: skin, proximity and radiation effects. The skin effects reduce the effective conductor area by pushing the cu rrent to the border with varying electromagnetic field originated from the flowing current. The skin depth is defined as: ( 4 1 6 ) Where, are the relative permea bility of conductor material, the vacuum permeability, conductor resistivity and working frequency, respectively. For copper, the skin depths at 1, 10 and 1000MHz are 66, 21 and 2 m, respectively, which are already going into micro range.
104 The proximity e ffects of one conductor segment, on the other hand, add/reduce current density at the close/far edges of the nearby conductor traces by exerting its electromagnetic fields into them. Radiation losses originate from the electromagnetic wave radiation from t he inductors, which are very small at MHz range and are only considered over Radio Frequency (RF) frequencies. Capacitive coupling represents the penetration of electrical field into the substrate or other structure materials. At the case of low resistivity substrate in CMOS process, the skin depth reaches the order of substrate thickness and increases the ohmic losses of the substrate. Penetration of the magnetic field into the magnetic core or low resistivity substrate, i.e. inductive coupli ng, is significant at high frequencies, where the induced currents result in massive losses. And the eddy currents also lower the achievable inductance of the inductor. Industrial CMOS processes heavily rely on the highly doped silicon substrates with low resistivity in the order of 0.01 much substrate losses. To increase the resistances of magnetic core or silicon substrate is one way to reduce this loss without inhibiting the fluxes. However, this will limit the applicable subst rates or magnetic. Other approaches include patterned shield under the coils, or core lamination as discussed in section 2.1, which complicates the fabrication process. Most important, the first choice is a compact design to confine the fluxes and limit th e eddy losses Besides the losses, the self resonance point of inductor is characterized as their inductive reactance is totally cancelled by the parasitic capacitive reactance, and therefore the inductor acts like one resistor and lose its function. Obvio usly, this self
105 resonance phenomenon of inductors limits the operation region of frequency and deserves particular concerns on winding topologies such as turn number, line spacing and conductor widths. The self resonance frequency may also be tuned by redu cing oxide capacitance with low dielectric passivation layer or direct air gap in some cases. The adjustments of and are major approaches to delay the self resonant frequency. Although the Figure 4 1 2 a show s one simplified analytical model for the inductor, it is still difficult to determine all the circuit parameters since they all depend on working frequencies, currents and/ or geometries. Generally, to further simplify the problem, this work only take s the and for analysis. All the loss factors can be collected into the including the winding, substrate and core losses, and is used for characterizing the self resonant frequency. Quality factor (Q) is the most important characterization factor of inductors which reflects the energy transmission efficiency at a given frequency. Higher Q value means lower resistive losses with the same inductance level. The definition for quality factor is: ( 4 1 7 ) Where, the are angular and ordinary frequencies, respectively.
106 The inductance of toroidal and spiral inductors had been discussed in section 4 .1. Next will discuss the determination of series resistance and stray capacitance 4 .2.2 Determination of the Ser ies R esistance For illustration, this work take s the in substrate spiral inductor shown in Figure 2 26 as an example to illustrate the process. The measurements for this 10 turns spiral inductor are: total size=3*3*0.6 mm 3 inductance =390nH, DC resistance effective core cross section =1mm 2 effective magnetic flux length = 2.4mm, core volume= 2.4 mm 3 winding width/height/spacing =60/200/40m,winding inner/outer radius=300/1300m.This spiral inductor was designed for TI TPS62601 power converter and the converter specifications are: 6 MHz operation, 2.3 5.5 V input, and 1.8V/500mA output. For in substrate inductors, the redundant silicon substrate is thoroughly etc hed off and replaced with large cross section windings or high volume magnetic cores. Therefore, the can be split into two portions: winding resistance and core resistance respectively, w hich are in series with the ideal inductor The winding resistance will increase with higher frequencies due to the skin and proximity effects. Literatures investigation shows that there are several approaches h aving been proposed to estimate the AC resistance at a given frequency. However, the in literature [ 58 ] Approach in literature [ 59 ]
107 with some approximation, and the method in literatu re [ 60 ] used the curve fitting at a fo r resistance estimation, and lists the equations here. ( 4 1 8 ) ( 4 1 9 a) ; When , ( 4 1 9 b) Where, are winding DC and AC resistances; is correction factor for AC resistance; is intermediate parameter relying on skin depth winding thickness, width and spacing ( ); is layer number of conductors. And Equation 4 1 9 b is usually applied for one layer in substrate sp iral or toroidal windings. This basic equation assumes that the magnetic fluxes are parallel to the winding layer and hence is limited in some applications with relatively small spacing between windings. There are also other approaches have similar forms but different A representation as following [ 60 ] : ( 4 1 9 c )
108 This suggests that the parameter A can be adjusted for better curve fitting. This work still apply the Equation 4 18 and tune the parameter A as following to consider the winding width in the spiral inductor. For the spiral inductor ( 4 20 a) For the toroidal inductor in Figure 4 6 c, the parameter A is tuned as the following, where its performance is mainly controlled by the winding thickness: ( 4 20 b) Figure 4 1 3 compares the analytical results from the approaches in literatures [ 58 ] [ 59 ] [ 60 ] [ 61 ] with the COMSOL FEM simulation result. It shows that the Equation 4 1 9 a with 4 20 a have better approximation. At 6 MHz, the estimated correction factor is 5.74, and On the other hand, the core resistance will increase with higher frequencies due to the hysteresis and eddy current losses. However, the magnetic composite (89wt% NiZn ferrite and 11wt% PDMS) used in this work has low coercive force (15Oe). Moreover, the calculated peak B field from Equation 4 2 is 0.02457 T, which is much smaller than the saturation magnetic field (0.2 T).Therefore, the analysis may ignore the hysteresis loss at this small signal situation, and use the following equations for core loss estimation [ 58 ]
109 ; Then, ( 4 2 1 ) Where, is the loss tangent; are the real and imaginary parts of the re lative complex permeability. Fig ure 4 1 3 Analytical estimation of the winding resistance The relative complex permeability of the magnetic composites can be easily characterized by instruments, and hence the core resistance can be estimated. For =390nH, based on the Equation 4 21 and the complex permeability measurements of the magnetic composite (presented in Chapter 5), this work obtained the core resistance values versus frequency, as illustrated in Figure 4 1 4 The fitted trend line is: ( 4 2 2 ) EQ2,  EQ3,  EQ1  Comsol simulation EQ5,  EQ6,  This work
110 And at 6 MHz, Fig ure 4 1 4 Analytical estimation of the core resistance 4 .2.3 Determination of the Stray Capacitance For the estimation of parasitic capacitances, there are empirical formulas, analytical approximations, experiment based calculations and FEM approaches [ 61 62 ] [ 63 ] [ 64 ] .However, the empirical formulas usually deviate from the real values too much, and analytical models are troubled with various geometries and non uniform distribution of magnetic fields. FEM simulation is an effective approach with accurate numerical calculations, but every simulation corresponds to a specific model construction and long computing time is required. On the other hand, the measurement methods are simple and accurate since they reflect the real performances of devices. At resonance, the imaginary parts of the total impedance cancel each other, and hence the following relationship of components can be derived:
111 ( 4 2 3 ) Where, is the resonant angular frequency can be obtained from the analysis in last section, or ignored since in most cases. Fig ure 4 1 5 Inductance/resistance measurement and estimation of one spiral sample For example, one in substrate 10 turns spiral inductor as shown in Figure 2 26 achieves 360nH inductance,335m DC resistance and 18MHz resonant frequency (estimated is 3.85 at this frequency). The calculated stray capacitance is 216pF based on the measurement and resistance estimation. And applying these parameters to the three component anal ytical model ( ), the predicted and actually measured performances can be compared as in Figure 4 1 5
112 4 .2.4 Converter P erformance D egradation f rom Resistances and Capacitances Converter efficiency is definitely impaired by the parasit ic resistance and capacitance of inductors. The parasitic resistance directly consumes extra energy when current flowing through the inductor, and parasitic capacitance increase the charging or discharging losses at switching moments. The loss addition fro m parasitic capacitance relates to the circuit loop with MOSFETs and is hard to characterization. However, the loss addition from parasitic resistance can be easily characterized. Assume a real spiral inductor as used before (390nH, 140 80 capacitance ), and use the basic converter topology as Figure 1 2c ( 221 mA load current, 3.6/1.8 V input/output voltage, 6MHz switching frequency), the loss addition from the paras itic resistance can be estimated as following. From Equation 1 1, inductor current ripple is a triangle wave. ; Then the total loss from parasitic resistance is: 4 .3 Sizing Analysis B ased on A nalytical M odel s For wafer level integration of passives in POL converters, the bulky magnetic has been the single largest volume contributor for more than a decade. C ompared with the continuously shrinking analog circuits, the passive size is a critical factor to define t he
113 converter package. To investigate the relationships between inductor dimensions ( such as core size, winding thickness, turn numbers, etc) and performances ( such as resistance and quality factor), an analytical process is proposed to optimize different d esigns for compact passive integration with expected specifications. This optimization process is designed to reveal the basic performance impacts from different dimensions and provide first hand recommendations of inductor designs, which are based on the analytical analysis discussed in the previous sections. So, multiple simplifications are applied. First, the stray capacitances of inductors, usually on 0.1 100 pF level, are hard to be estimated, and their influences are only significant on or beyond the resonant point, then this optimization process ignores the stray capacitances which may be acceptable up to 20MHz. Some rectification based on experiments or FEM simulations can be applied later to consider the stray capacitances. Second, the process limi ts analysis in the inductor performances such as resistance, quality factor or size, and does not extend to the whole converter performances such as total losses and efficiency. The basic optimization flow is shown in Figure 4 16 And the analytical methods which have been discussed in previous sections are applied. For the sizing analysis, the first step of inductor optimization is to identify the initial values, variables, constrains, and optimization targets. This work tries to design optimized inductors/transformers for a typical POL converter. So, the initial values can be selected based on the available converter modules and materials: the target inductance (470nH), inductor ripple current at 6MHz working frequency (160mA), l oad current level (500mA), magnetic composite ( Bsat =0.2 ), silicon wafer
114 thickness (500 m), copper resistivity (17.24n m). The variables during the optimization process are: inductor dimensions such as core cross section, flux length, windin g cross section, winding width/length/spacing and turn numbers. The constrains are: inductance equation, magnetic field equation and core/winding loss equations. The optimization targets can be: minimum total loss, maximum quality factor, or maximum induct ance density. Fig ure 4 1 6 Optimization process for sizing analysis Starts with the torus inductor des ign, the first two rows of the T able 4 3 and 4 4 illustrate the optimized designs for highest quality factor and smallest volume, respectively, where the minimum winding spacing and width is set to be 40 m, minimum via dimension is limited to be 150 m for quick silicon etching during fabrication, maximu m surface deposition of copper is 100 m, maximum outer radius is 5mm
115 Table 4 3. Optimization results of a toroidal inductor for 3.6 to 1.8V, 6MHz, 0.5A buck converter (a) Targets L ( H ) Rdc winding (m ) Rac winding ( m ) Rac core ( m ) Quality ( @6MHz ) Ptot loss (mW) Highest Quality 0.48 56 105 28 133 15.2 Minimum volume 0.48 903 903 28 19 233.6 Combined loss and size 0.48 83 145 28 103 22.2 Min loss at limited size 0.49 72 129 28 113 19.4 Table 4 4 Optimization results of a toroidal inductor for 3.6 to 1.8V, 6MHz, 0.5A buck converter (b) Targets Turns Bavg (mT) T winding ( m ) Spacing ( m ) Rin ( m ) Rout ( m ) Highest Quality 26 5 100 40 1500 5000 Minimum volume 40 15 10 40 1200 1980 Combined loss and size 35 14 100 40 1050 2010 Min loss at limited size 28 11 100 40 890 2350 From the T able 4 3 and 4 4 the quality factor optimization has the maximum footprint with the big outer radius, and the volume optimization has the highest loss with the thin winding thickness and large turn numbers. Therefore, to balance the size and loss, this work do es a furthe r optimization considering both loss and size. Compared
116 with the quality optimization with the biggest 5mm outer radius, the total loss for the combined optimization is only 7mW higher with around 2mm outer radius. And increase the outer radius to 2.35mm, it only achieve 2.8mW loss reduction. The capability of inductors to maintain high quality through a large frequency span is also preferred by the converter designers, because the converters may work at pulse frequency modulation (PFM) mode and the inducto r ripple currents may include a bundle of frequency components. The standard deviation of the quality factor is defined as following: ( 4 2 4 ) ( 4 2 5 ) Where, are quality factor samples and their average over a frequency range (defined as 30% of the working frequency); is the standard deviation of the samples. Figure 4 1 7 illustrates the quality factors of the forth design in T able 4 3 and 4 4 The standard deviation is only 4.3 over a 4MHz frequency span. Based on the forth design in T able 4 3 an d 4 4 this work can also illustrate the impacts of various dimensions on the quality factor as shown in Figure 4 18 where bigger winding thickness and lower spacing achieve higher quality factor. However, when the winding thickness scales up to 2 times o f the skin depth, the quality factor only increases slowly with higher winding. This indicates a reasonable choice of 2 times or a little more of the skin depth for the winding thickness, not considering the DC resistance. Thicker windings definitely achie ve smaller DC resistance and therefore lower the
117 winding DC loss, but do not help to reduce the AC loss over this thickness. Beside s from T able 4 3 and 4 4 this work can also conclude that, with bigger size, both the DC resistance and AC resistance are l ower and therefore the total quality factor and efficiency are improved. Fig ure 4 1 7 Range quality for a toroidal inductor Fig ure 4 1 8 Torus performance with different dimensions Rin=890m Rout=2350m Turns=28
118 In section 4 .1.2, this work ever discussed the matrix design of toroidal inductors for constant flux distribution in magnetic rings. Assume a simple constant flux inductor with 3 magnetic rings and 4, 4, 8 turns distributed on these rings With the same magnetic core, and applying the equations in section 4 .1.2, this work has the following calculation results to show the relationship between the size and inductance in Figure 4 1 9 T he total inductance of the constant flux inductor is mainly limited by available turns and the inner most radius in a limited area of several millimeters Fig ure 4 1 9 Inductance vs. innermost/outermost radius for constant flux inductors Note: 3 magnetic rings, 4, 4, 8 turns distribution Clearly, 4,4,8 turns distribution for this 3 rings constant flux inductor is not enoug h to achieve 0.47 H inductance. This work change s the turns to 8, 10 ,14, and recalculate the inductance versus the outer radius as Figure 4 20 A 4*4 mm 2 footprint with reasonable turn distribution was gotten on the 3 rings constant flux inductor. Its inn ermost and outermost radius is 0.242 and 2mm, respectively. And the minimum turn
119 width is 190 m, which is sufficient for safe fabrication. Assume the winding thickness is 100 m, and it achieve s 62/112m DC/AC winding resistances and 16.8mW total loss at 0. 5A full load. Figure 4 20 A constant flux inductor design 3 rings (8, 10, 14 turns); 4*4mm 2 footprint.
120 CHAPTER 5 WAFER LEVEL FABRICATION AND CHARACTERIZATION OF POWER INDUCTORS This chapter describes details of the i n silicon enabling techniques and introduces t he process flows for spiral and toroidal windings Comprehensive characterization of devices exhibits good performance A nd process difficulties are discussed for further improvement. 5 1 In Silicon Fabrication of Power Inductors/Transformers The detailed IC compatib le MEMS procedures are the major kernel for the wafer level integration of power inductors or transformers. As discussed in Chapter 2, high aspect ratio and large cross section coils, construction materials capable for both stress buffer and dielectric iso lation layers and moldable magnetic materials are preferred in the wafer level integration process. Chapter 4 already describes the in substrate toroidal or spiral topologies in Figure 4 1. These in substrate inductors are well suitable for the wafer leve l integration and enjoy the following benefits. 1. The s ubstrate molded conductors can be electroplated as thick as the substrate (200 500 m thickness) which alleviates the competition between large inductance and lower winding resistance 2. Thick magnetic core is possible by thoroughly replacing the lossy substrate with high resistive and polymer bonded magnetic materials, and hence enables the high current capability (>2A). 3. Closed or quasi closed magnetic path is finished with the three device layers in spiral or toroidal topologies to avoid extra losses and electromagnetic interference s 4. Through substrate metal or vias can provide good thermal paths and bonding pads towards compact integration and packaging. 5. Polymer based dielectric m aterials are chosen for t he passivation and also for the stress buffer layers, which are all regular packaging materials. 6. The process flow works at low temperature (<150C) and is compatible with CMOS processes.
121 As a result almost every element in the final inductors/transforme r s is fully explored for the compact wafer level integration into the POL converters. The enabling techniques for the compact, low profile inductors/transformers are designed for process compatibility and material selection. 5 1 .1 Three Key Steps There are three key steps involved in the silicon molding technique. The f irst one is the etching of the through wafer silicon trenches in a STS DRIE system. DRIE can generally achieve 25:1 aspect ratio but a smaller aspect ratio is used to ease the silico n etching and copper filling process. Figure 5 1 show s the cross section view of a through silicon via after removing the original 10 m copper seed layer at the bottom There, the tapered sidewall s after DRIE silicon etching is for the following SiO2 confo rmal coating (by PECVD or other low temperature choices) and anisotropic RIE (Reactive ion etching) etching, where the oxide passivation is formed on the sidewall and the bottom copper seed layer is exposed to ensure the quality of following bottom up elec troplating in case no high resistivity substrate is available. Figure 5 1 SEM picture of a through wafer via with a negative slope sidewall Si Etch direction Thin SiO2
122 Figure 5 2 An example of pulse reverse electroplating Table 5 1 Copper electroplating bath composition Component V olume ratio Deionized water 600 ml/l CuSO4 5 H2O 75g/l Concentrated H2SO4 100ml/l HCL (38w/w%) 0.25ml/l *TECHNIC CU 3300 Brighter 5ml/l *TECHNIC CU 3300 Carrier 7.5ml/l *TECHNIC CU 3300 Polarizer 10 50ml/l Note: supplies from Technic Inc. The second key step is the through wafer copper electroplating in silicon molds. Pulse reserve electroplating is employed to improve the quality and uniformity of the electroplated metal layers. Its current density waveform is illustrated in Figure 5 2 Th e short reverse electroplating dissolves part of the electroplated metal which J(mA/cm 2 ) 30 Forward pulse 2ms Idle time 20ms t(ms) 1ms 90 Reverse pulse
123 compensates the consumed ions during the forward electroplating. Therefore it improves the uniformity of ion s distribution. Optimal settings vary with the target shape and expec ted plating time. For example, in high aspect ratio applications, larger reverse plating current or longer idle time is required for uniform ion distribution. B asically speaking, slower deposition rate yields better uniformity F or the electroplated copper r esistivity was characterized as 18.1 Table 5 1 lists the composition of plating bath. Fig ure 5 3 Surface polishing for a 2 8 0m Si wafer embedded with 6 0 /40 m width/spacing square spiral coils For t he third key step most MEMS processes rely on flat surface for good features control and this means a polishing step will be necessary after filling deep trenches Chemical mechanical planarization (CMP) on wafer level fabrication is already well developed in industry, where the combination of chemical etching and abrasive polishing is involved. In this wo rk a manual polishing process is used. The process use s wax to stick the wafer and dummy samples on a big iron stage, and then polishe s the samples on polishing clothes or the round glass platform of a mechanical polishing machine. The medi a applied are 5 m aluminum oxide slurry which can be easily rinsed Cu winding Si substrate Cu via Cracks
124 off by diluted sulfuric acid. Figure 5 3 show s one sample after polishing and some cracks appeared due to the rough manual polishing. Thicker copper seed layer is required to support whole wafer if appl ying manual polishing 5 1 .2 Material S election Basically, higher working frequency towards the multi megahertz range will alleviate the requirement for large inductance and lead to a smaller passive size but this also increase the frequency dependant losses from the skin and proximity effects of conductors and the hysteresis and eddy current phenomenon of magnetic cores. Hence, suitable materials in the megahertz range are also indispensable for high efficiency pow er conversion Copper is selected as the conductor material due to its low resistivity and good power handling properties. And the well developed copper electroplating processes in industry strengthen its application s Another important material selection is the magnetic material. Compact passive designs require high quality magnetic materials to attain enough inductance and minimize core losses at high frequencies. Many research samples were already proposed such as CoZrO g ranular film, NiZn ferrite, ferri te polymer material and thin film CoNiFe alloy as discussed in Chapter 2. In this work, a magnetic composite of fully sintered NiZn ferrite powder (FP350 from Powder Processing Technology, LLC, 89wt%) and a polymer (Sylgard 184 from Dow Corning, 11wt%) (Hc =15 Oe, Bsat =0.2 T, r=8) is used to obtain large inductance and maintain low core loss at megahertz frequenc ies The NiZn ferrite powder is milled down to 1 3m from the original 10m size before mix ed with the PDMS polymer as shown in Figure 5 4
125 Figure 5 4 SEM picture of the magnetic composite Note: 89wt% NiZn ferrite and 11wt% PDMS composite The measured permeability of the magnetic composite is around 6 8 with hand wound inductors. The m easured resistivity is as high as 2 G Its r elative permittivity is about 25 measured using test structures. The hysteresis loop measured by a Vibrating Sample Magnetometer (ADE T echnologies) and t he permeability frequency response obtained by a n Agilent 16454A Magnetic Mate rial Test instrument are showed in Figure 5 5 and Figure 5 6, respectively Besides power efficiency, there are also strong requirement s for robust devices. A s discussed in Chapter 2 t hrough substrate copper vias can provide good thermal paths for thermal dissipation, and round rather than sharp corners of the conductor windings have better thermal performance s Considering long term thermal/mechanical fatigue situations, a good materia l selection besides the copper conductor in device construction is also important f rom the view of device reliability. As indicated in T able 2 3 is mixed with NiZn ferrite powder to form the magnetic composite which work as magnetic core and stress buffer simultaneously. Actually, this magnetic composite has replace d most part of the rigid silicon substrate and wra p p ed the copper vias everywhere. Another common, safe and Si substrate
126 elastic material in electronic industry i s Polyimide, and PI 2574 may be selected as the dielectric layer between stacked windings for transformer s considering its relative ly high dielectric strength (155V/m). Figure 5 5 B H curve of the 89wt% NiZn ferrite and 11wt% PDMS composite. [ 39 ] Fig ure 5 6 Frequency r esponse of c omplex permeability Note: 89wt% NiZn ferrite and 11wt% PDMS compos ite. B (T) H ( Oe )
127 5.2 First G eneration : C ircular S piral I nductors For the circular spiral inductor, it was previously fabricated as first generation as shown in Figure 2 26 The author participated in the fabrication process and did most of the device characterization works. 5 2 1 Fabrication P rocess of Circular Spiral I nductors Fig ure 5 7 Cross section view of fabrication processes for circular spiral inductor Figure 5 7 illustrated t he detailed micro fabrication flow for circular spiral inductors. First through su bstrate silicon trenches with a copper seed layer exposed at the bottom are created by depositing 10 m Cu on the backside and etching through the 200 m thick Si substrate using DRIE (Deep reactive ion etching) (step 1). Cu is electroplated into the trenches to form 60/40 m width/spacing winding s with the over plated part being polished away (step 2). Then trenches are created again, which are filled by the PDMS/NiZn ferrite mag netic composite with the overfilled parts being polished (step 3). T here is an outer copper frame at the outermost border to hold magnetic core Then, solder balls (300 m diameter) are placed on the conductor pads for circuit connection (step 4 ). After the magnetic filling, the surface is polished to (1) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) Si SiO2 Cu Solder ball Magnetic
128 expose the solder balls (step 5 ). Same process is repeated on the backside, and one top circuit is deposited by copper electroplating to mount regulator and capacitors (step 6 ). 5 2 2 Characterization of Circul ar Spiral Inductors The circular spiral inductor is a 200 m thickness, 60 m width and 40 m spacing copper winding which was embedded into the silicon substrate, and both sides of the substrate were capped with a composite of magnetic powders and a polymer ( Figure 2 26 a). The measured inductance was 390 nH with a Q factor of 10 at 6 MHz. DC resistance was 140 m and AC resistance was 1.15 at 6 MHz. Large cross section conductors were achieved by the silicon molding technique, and the selection for 60m width of the embedded windings was mainly from the skin depth of copper conductors at 6MHz. Proximity effect between adjacent windings in this application was ignored because the targeted peak to peak AC current is small. Figure 5 8 Inductance, Q and AC resistance verse frequency of the 10 turn circular spiral inductor. Adapted from [ 45 ] ; L Q R Inductance (nH) Frequency (Hz) 200 10 4 10 5 10 6 10 7 3 00 4 00 5 00 0 4 8 12
129 Figure 5 8 illus trates its frequency response of the inductance, quality factor and resistance. Much more significant AC resistance was observed at higher frequencies. Besides the performances for low resistance, high inductance and high quality factor there are also str ong requirement for robust and compact devices. A series of reliability tests were carried out to verify the robustn ess of the spiral inductors in T able 5 2 During the test, a significant resistance increase at humidity test was observed. This is because no packaging material was applied for the bare inductor, and the corrosion occurred at via contacts. Table 5 2 .Spiral inductor reliability tests Test details L Rdc Drop from 1.03m height to steel ground for 10 times In/out plane vibration, 60Hz, 1G acceleration, 2hrs. Thermal shock between 20 and +105 C, tmax<15s for transition time, 10 cycles. >90% R.H, 40C, bared inductor, for 550hrs 5 2 3 Fabrication Challenges and Discussion For the spiral inductors, the copper windings were formed at an electroplating process and magnetic core were filled with three steps for upper, middle and lower layers. At least four polishing steps were required for the process. Solder ball ac ted as the interconnection to the outer circuitries, and their joint reliability were critical during the polishing steps. Fortunately, industry has reliable bump technologies for flawless
130 encasing of the solder balls with conductive supporters. In this wo rk, the silver epoxy was applied for this purpose with carefully placing of the solder balls. The better the solder balls are encased into the silver epoxies, the lower interface resistances are. Figure 5 9 shows three photographs of the setup for handling the solder balls or the converter regulator to be assembled with micro inductors. Fig ure 5 9 Photographs of the placing of solder balls or converter regulator A) The set up B) Holding solder ball C) Holding IC chip. Images courtesy of the author. 5. 3 Second Generation: T oroidal I nductors This work h as fabricated a toroidal inductor for demonstration. And stacked windings for 1:1 toroidal transformers were also tried to identify all the fabrication challenges and select suitable dielectric polymers for complicated structures. Their topologies are alre ady introduced in Figure 4 1. 5 3 1 F abrication P rocess of Toroidal I nductors As shown in Figure 5 10 f or the toroidal inductor, the first two steps are similar as in Figure 5 7 and through silicon trenches are etched by DRIE and filled with electroplated copper but with150 m via width (step 1, 2 ). The next process is also A B C Vacuum holder and its alignment Microscope Light source Solder ball, Silver epoxy and PCB chip Movable stage Micro alignment
131 similar to etch trenches and fill the magnetic materials (step 3 ). Next, 40 60 m thick copper lines are electroplated on the top of the substrate by using thick AZ9260 phot oresist mold s and etch back techniques (step 4). For the stacked winding case, a patterned 20 25 m Polyimide layer is deposited to work as a dielectric layer between the stacked windings (step 5), followed by another copper layer electroplating on it (ste p 6). Finally, the process es for two copper layers and one Polyimide dielectric layer are repeated on the backside (step 7). Figure 5 1 0 Cross section view of fabrication processes for toroidal inductors/transformers 5 3 2 Characterization of Toroidal I nductors Several toroidal inductors and transformers were fabricated on a 4 inch 200 m silicon wafer through the above processes as shown in Figure 5 11 .There is one ring of idle vias (150 m width) at the outer border of the inductor, which can be used to form the stacked windings in transformer case. The torodial windings have 13130.32 mm 3 size, 36 turns, and inner/outer radius is 3.1/6.3mm.The magnetic core height is around 200m and winding thickness in the 40 60m range. (1) ( 2 ) ( 3 ) ( 4 ) ( 5* ) ( 6* ) ( 7 ) Si SiO2 Cu Polyimide Magnetic Note: for transformer process
132 Fig ure 5 11 Top views of the fabricated inductor and transformer. A) Inductor B) Transformer Figure 5 12 show s the SEM (Scanning electron microscope) picture of the 4 copper layers in the transformer case, where the Polyimide works as the dielectric layer between the stacked windings and a layer of magnetic composite core is in the middle. Fig ure 5 12 Cross section view of fabricated 4 Cu layers. The DC resistance of one 36 turn inductor is measured by a four point probe station The measured DC resistance which may be caused by the following reasons: 1) thinner electroplated copper layer which is Cu Magnet ic core Polyimide Polyimide B Stacked Cu windings Cu windings Cu Vias A
133 less than 60 m used in the simulation ; 2) via contamination during the processes, and 3) higher resist ivity ( 18.1 ) of the electroplated copper compared to the bulk copper. The measured inductance, Q and AC resistance over frequency for the fabricated 36 turn inductor is shown in Figure 5 13 and the highest Q factor is 10.5 at 14 MHz. Fig ure 5 13 Inductance, Q and AC resistance verse frequency of the 36 turn toroidal inductor 5 3 3 Fabrication Challenges and Discussion For the toroidal inductor s the copper magnetic composite copper design is simple and can be well fabricated by the proposed silicon molding technique. However, there exist some challenges for the stacked windings in transformer case, mainly because of the Polyimide material that was chosen as passivation and stress buffer layer s ( low Y 3.1GPa ; and good d ielectric s trength 155V/m). First, the corner coverage problem was encountered when using Polyimide to fill the trenches (40 100m wide and 40 60m deep) between copper traces or to fill the
134 deeper silicon trenches (75 150m wide and 200 500m deep) between copper vias. Major problems were from the big volume loss through solvent evaporation when baking and stabilizing the Polyimide, and hence, non flat working surface and poor coverage at the trench corners resulted as shown in Figure 5 14 Also, to avoid voids, the technical limit of Polyimide for filling trench es is only about 2 in aspect ratio due to its high viscosity. Figure 5 14 Cross section view of Polyimide filling issues. Second, the non flat working surface led to many problems in the following steps such as large varia tion of the film thickness during polyimide etching steps, non uniform plating results due to poor base surface, and even short circuit between primary and secondary windings. Third high temperature (350 C ) was involved for curing or etching the Polyimide in the processes And SiO2 is verified to be the best etching mask for Polyimide and its deposition usually needs 300C if trying PECVD deposition To tackle these issues additional surface polishing may be necessary to fill the trench first and obtain planarization next, but th is may introduce new challenges since the wafer may become fragile after so many etching and filling steps. For the Copper via Thinner Polyimide at corner Bulk Polyimide
135 temperature issue s polymers with lower curing temperature (around 200C) can be chosen, and aluminum sputter ing to work as polymer etchi ng mask may avoid the high temperature. There are various types of polymers, most of which suffer from partial filling or delamination problems in the case of deep trench filling. Table 2 3 in Chapter 2 and the following T able 5 3 compare three frequently used polymers: PI (polyimide), SU8 (epoxy based negative photoresist) and BCB (Benzocyclobutene). And BCB sh ows to be a good alternative to the polyimide and it provides much higher dielectric strength and lower curing temperature. Photo patternable BCB p roducts are commercially available, such as Cyclotene 4024 40 series from Dow incorporation. Researchers have proven that three to four layers of BCB can fill 40 m deep U or V shaped trenches and BCB has a better trench filling performance than the P olyimi de polymer [ 65 ] Table 5 3 .Comparison of Frequently Used Polymers PI SU8 BCB Max thickness per layer (m) 12 >200 14 Relative dielectric constant 3.3 3 4.5 2.65 Dielectric Strength (V/m) 155 <40 5300 Curing Temperature (C ) 350 200 300 250 Anyway f rom the perspective of transformer design, the stacked windings may be replaced with parallel windings. This will significantly simplify the fabrication process
136 and exclude the need for dielectric layer s with minor sacrifice in winding resistance and coupling efficiency Via contamination d uring fabrication will also be reduced because of less process steps. 5. 4 Second Generation : Square S piral I nductors Square spiral designs are more space efficient than the circular ones, which leads to higher inductance density. A n improved fabrication process is performed to replace solder ball placement with copper post electroplat ing which significantly reduces the interface resistance and improves the quality factor. 5 4 1 Fabrication P rocess of S quare Spiral I nductors As shown in Figure 5 15 the device fabrication starts with a 2 inch (280 m) silicon wafer, and a 0.8 m SiO2 layer is first deposited by plasma enhanced chemical vapor deposition (PECVD) on the backside for electrical isolation. A 1 m Cu/Cr seed layer is sputtered on the backside, and then grows to 40 m thick through electrical plating which is sufficient to stand multiple polishing steps (step 1) The plating solution is shown in Table 5 1 Front side photoresist patterns are defined through AZ9260 lithography and the wafer is etched through with a slightly negative angle by deep silicon reactive ion etch (DRIE). After wafer cleaning, a 1 m conformal SiO2 coating is deposited by PECVD and then the bottom SiO2 in silicon trenches is etched away by an anisotropic rea ctive ion etch (RIE) to isolate the trench sidewall and expose the copper seed layer at the bottom (step 2) Then, silicon trenches are filled with copper through a long time electroplating process with a 20 30 m/hour deposition rate. Extra copper on the f ront side is manually polished away, and after every polishing step, the wafer is rinsed in diluted sulfuric acid (<10%) and de ionized water (step 3)
137 Fig ure 5 15 Cross section view of fabrication processes for square spiral inductor Next, the silicon between copper coils is thoroughly etched away through anisotropic DRIE etch followed by a short isotropic RIE etch. Fresh and soft PDMS bonded magnetic composites are manually pressed into the wafer and vacuum treatment is necessary to r elease trapped air between coils. After curing in oven at 120 degree Celsius overfilled magnetic composites are polished away (step 4) A sequential plating process is used for the important construction of high copper posts (>200 m) (step 5) First, 1 m Cu/Cr seed layer is sputtered on the wafer (step 5a) Although this layer introduces some interface resistance, it is necessary to shield thermal stresses originated from the PDMS bonded magnetic composite during the (1) ( 2 ) ( 3 ) ( 4 ) ( 5a ) ( 5b ) Si SiO2 Cu Magnetic AZ9260 ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 5c ) ( 5d ) ( 5e )
138 following lithography processes. Then, four layers of AZ9260 are spun and cured gradually on the wafer to a total thickness of 80 85 m, followed by a contact lithography for pattern exposure. The photoresist is immersed and developed in AZ 400K 1:2 developer for 6 7min (step 5b) This lithogra phy step is not a standard process for AZ9260 and better photoresist replacement may be as a substitute After the lithography, the electroplating for copper posts is timed so that the photoresist molds are just or a little over filled (step 5c) The seque n tial steps of the lithography and electroplating are then repeated until the copper posts reach the desired height (step 5d 5e) Later, the recent sputtered copper seed layer is etched away by ammoni um per oxydi sul f ate (APS) solution and Chromium Etch 1020 PDMS bonded magnetic composites are pressed and vacuum pumped into the wafer again, and over filled part is polished away to expose the electroplated copper posts (step 6) A 30 40 m top copper shield layer can be optionally pattered and electroplated th rough AZ9260 molds after another 1 m Cu/Cr seed layer sputtering and this seed layer can be etched away later (step 7) Then the previous steps for copper posts magn e tic core and copper shield layer are repeated on the back side to finish the MEMS inductor fabrication (step 8) Figure 5 16 (a f ) show s a series of photographs for the fabrication steps. 5 4 2 Characterization of Square Spiral Inductors Two kinds of square inductors are designed and fabricated O ne has 6 0 /2 8 0/ 40 m winding width/height/spacing (10 turns), and the other has 70/280/40 m dimensions (9 turns).
139 A B C D E F Fig ure 5 1 6 Photographs for the fabricat ion steps of square spiral inductor (9 or 10 turns) A) Step 3, Cu filling in Si trench and polishing B) Step 4, Si etch for magnetic filling C) Step 4, magnetic filling in substrate trenches and polishing D) Step 5, sequential electroplating for copper posts E) Step 6, magnetic filling and polishing F) Step 7, electroplating for copper routing Figure 5 17 (a) shows a completed inductor with mounting and shield copper layers on both sides, and Figure 5 17 (b) is the cross section view of a 9 turn inductor and the dicing line is shown in Fi gure 5 16(d) The total size of the fabricated inductor is Dicing line
140 3*3*0. 83 mm3 The thicknesses for the magnetic layers on two sides of the inductor are around 200 and 270 m and for the two copper routing layers are 40 50 m. A B Fig ure 5 1 7 T he fabricated square spiral inductor A) 45 angle view of the inductor B) Cross section view of the inductor Fig ure 5 1 8 Inductance, Q and AC resistance verse frequency of the 10 turn square spiral inductor No te: over 10MHz data are limited by instrument measurement capability The 10 turns fabricated inductor is characterized through an Agilent/HP 4294A precision impedance analyzer and a four point probe station. The measured DC resistance through four probe method is 84 m The inductance, resistance and quality Si Magnetic core Cu coil Cu Via Cu routing Cu routing Si Magnetic core
141 factor are 430nH, 792m and 20.8 at 6MHz The freq uency responses of the inductance, resistance and quality factor of this inductor are shown in Fig ure 5 1 8 Compared with the previously reported circular spiral inductor, the newly fabricated square inductors has similar sizes but with much less resistanc es and higher inductance. The inductance is higher because the square implementation of coil is more space efficient and real magnetic layer is thicker on one side (270 Vs 200 m ) And the resistances are lower because of four reasons F irst, the winding s a re higher (280 Vs 200 m) than previous circular spirals. Second, electroplating copper posts instead of placing solder balls reduces the interface resistances between the coil and copper post/solder bal l Third the resistivity of electroplated copper is l ower than the solder ball. Finally, there was one DRIE instrument error during fabrication process, and actual output power was higher than the values shown on its control panel. And this leads to a little expansion (around 5 m ) of the silicon trenches for the coil electroplating, which will get wider windings. 5 4 3 Current Carrying Capability Another important improvement of the square spiral inductor is its capability for higher power handling which means two things. One, i ts inductance does not drop or saturate too much at high current, and hence will keep functional at high power. The other is its current carrying capability for long term running. The previous circular spiral inductor failed when the current went up to 7A in an 1 s pulse width signal Investigation showed that delamination occurred at the copper /solder ball interface and silver epoxy was used to bond solder balls on to copper coils.
142 Fig ure 5 1 9 M agnetic flux density map with 3A and 6A current injection A) 3A current injection B) 6A current injection For the square spiral inductor, simulations have been done as shown in Figure 5 19 for the magnetic saturation evaluation. At 3A current injection, most area in the flux density map of the square spiral is below 0.2T, which is under the magnetic B saturation field and means the inductance is well kept at 3A current. When the carrying current exc eeds 3A, the flux density will keep increasing and more area will move to saturation range. As shown in Figure 5 5, magnetic permeability drops towards air permeability in saturation range. The applied magnetic core is a kind of powder core form PDMS/NiZn ferrite composite. Therefore, inductor inductance will drop gradually and not abruptly Magnetic core Cu routing B Cu routing Magnetic core A
143 when more area moves into saturation with higher carrying current. At 6A current injection, the middle part of the magnetic core already has over 0.2T flux density, but most of other area is still under 0.2T. This kind of Soft Saturation is preferable for electrical integration. This work injected into the square spiral inductor an over 30A current in 10 s The test showed that the inductor well survived from the surge current T h is work also injected a constant 3A current into the inductor for more than 15min after bonding it onto a PCB board. The whole inductor got heated over 160 degree measured by thermal camera, and still kept functional. The high temperature is due to losses generated from the silver epoxy bonding resistance (around 120m ) and inductor self resistance. If the inductor can be bond ed through soldering and be coated with thermal conductive packaging materials, it will handle more current for long term running. To summarize, the square spiral inductor can well handle long term 3A current without any inductance drop be soft saturated over 3A and stand over 30A short time current ripple. 5 4 4 Fabrication Challenges and Discussion The major improvement in the fabrication process is replacing the solder ball placement with the copper posts electroplating. Previously, there were several bonding contacts at coil/silver epoxy and silver epoxy/solder ball interfaces, and these bonding in terfaces introduce d more contact resistances. Now, the solder balls are replaced with the electroplated copper posts O n the backside, copper posts direct ly grow on the original seed layer just as the construction of copper coils which avoids structural i nterface s And o n the front side, one 1 m Cr/Cu seed layer is deposited before
144 electroplating copper posts for thermal stress control Following is the discussion for these process challenges. First, the deposition of the copper seed layer on the front si de is necessary to shield the thermal stresses originated from the magnetic material. W ithout this copper layer, stresses and cracks in the photoresist can accumulate when baking in the sequential lithography process and many bubbles will occur when coating another layer of photoresist as shown in Figure 5 20 For the copper seed layer sputtering the wafer should be baked thoroughly for 5 6 minutes at around 110 degree Celsius to remove any moisture residues on the coils before sputtering, which wil l reduce interface resistances and improve adhesion at the same time Literature s review also show s that sputtering 100 120 angstroms chrome first before copper deposition can usually get the best interface adhesion for robust seed layer However, if the AZ9260 photoresist can be replaced with other options such as SU8 to construct the 200 m deep molds with only one layer of photoresist coating, then the extra copper seed layer can be removed further and interface performance will be better. Second, air can be easily trapped between coils during the magnetic filling process, and vacuum treatment is necessary to remove them before curing the PDMS bonded magnetic composite. Because the magnetic composite is kind of soft sealing material, some bu mps may be observed during the period of vacuum pumping and the trapped air in it may not be released. Multiple vacuum pumping cycles are necessary and needle puncture can be an assistant approach for better air release. Figure 5 21 shows one cross view of a fabricated 10 turn square spiral with trapped airs.
145 Third, copper post is kind of soft and can be pushed inclined when finger pressing magnetic composites into trenches, as shown in Figure 5 21. Therefore, enough diameters of the copper posts should be remained after etching away seed layer to keep the posts strong and avoid inclination or even detachment. And careful control of the etching time is important as well as a good design of the diameters at the first beginning. Figure 5 20 Stress accumulation after photoresist baking Figure 5 21 Cross section view of a 10 turn square spiral inductor Trapped air Inclined Cu post Cu coil Si Trench for magnetic filling Cracks after P hot oresi s t baking
146 CHAPTER 6 DEMONSTRATION OF COMPACT DC DC POWER CONVERTERS In this chapter, several converter assemblies are introduced to demonstrate the integration capability of fabricated inductors for compact and high efficiency power modules. 6. 1 A C ompact DC DC B uck C onverter with C ircular Spiral I nductor Th e previously fabricated 330.6mm 3 circular spiral inductor was successfully integrated i nto one ultra compact DC/DC converter module through flip chip bonding as shown in Figure 6 1 There, the through silicon vias and copper interconnects worked as packaging pads for power ICs and capacitors The power IC was selected as the TI chip TPS62601 (500 mA, 6 MHz synchronous step down converter packaging) with 1.290 0.916 0.625 mm 3 dimensions. The working frequency and rated inductance of th is chip is 6MHz and 470nH, respectively Two controlling mechanisms are integrated into this converter regulato r for light load (PFM mode) and normal to heavy load (PWM mode) conditions. T he capacitors have 1.00 *0.50*0.55 mm 3 sizes, and their rated capacitances are 2.2 and 4.7 F, respectively. Finally, the whole power module was bonded on one PCB board for characterization tests. Fig ure 6 1 Buck converter with integrated circular spiral inductor [ 45 ] Power Inductor in Silicon Capacitor TI TPS62601 PCB board
147 This buck conver ter successfully delivered 500 mA at 1.8V with an 80% maximum efficiency (PWM mode) at 6 MHz. And Figure 6 2 and 6 3 illustrate one set of efficien cy measurement at different load currents and various temperature level s. Figure 6 2 Efficiency vs. load current circular spiral (3.6/1.8 input/output voltage) Figure 6 3 Efficiency vs. temperature at different load current circular spiral Note: 3.6/1.8 input/output voltage In Chapter 4 this work has analytically estimated the winding and core 0 10 20 30 40 50 60 70 80 90 0 100 200 300 400 500 Efficiency (%) Output Current (mA) PWM mode PFM/PWM mode 65 67 69 71 73 75 77 79 20 40 60 80 100 120 140 Efficiency (%) Temperature ( C) PWM 302mA PWM 382mA PWM 202mA PFM/PWM 360mA PFM/PWM 305mA PFM/PWM 197mA
148 This difference is from the analytical errors and parasitic influences, as well as the higher resistivity of the electroplated copper and the thickness reduction of copper windings during multiple polishing and etching steps. However, a rough breakdown of total loss can be performed for better understanding of the loss sources. At 1.8V, 195.7mA load condition, the measured efficiency is 79.6% which corresponds to 91mW total loss. The DC resistance loss is about 0.140*(0.1957) 2 = 6mW. The inductor ripple cur rent is about 193mA, and then the total AC winding and magnetic resistance is about 1.15*(0.193) 2 /3=14mW. In the total AC resistance, it may comprise 0. 4mW core loss (not include hysteresis loss) and 1 3.6 mW winding loss. One evaluation board of the TPS6260 1regulator from TI has been calibrated, and roughly 60mW resulted at this load condition. Adding up these component losses, the module ha s 80mW loss without considering the core hysteresis loss, losses from parasitic resistances on the board, and losses fr om the capacitor parasitic. This analysis indicate further efficiency improvement can be achieved by reducing the winding resistance and the ripple inductor current with better topology designs and higher inductance. 6. 2 A DC DC B uck C onverter Assembly with Square Spiral I nductor In this section, the square spiral inductor was successfully assembl ed with the TI TPS62621 inductor for demonstration Obvious performance improvement was observed compared with the circular spiral inductor. 6 2 1 T he Buck Converter Demo Circuit TI now recommends the TPS62621 or TPS62671 for the updated version of the TPS62601 chip which was previously used for the circular spiral inductor. For the
149 demonstration of the square spiral inductor, this work selected TPS62621 ( 600 m A 6 MH z high efficiency step down converter ). Compared with the old version TPS62601, the rated highest efficiency of TPS62621 is a little higher (90% Vs 89%), and the maximum load current is also higher (600mA Vs 500mA). The Smallest Solution Size App lication circuit is the same as before, and showed in Figure 6 4 The measurement system for the PCB assembly is also shown. Figure 6 4 Demo circuit for the square spiral inductor and measurement system ; [ 66 ] Table 6 1. Electrical components of the demonstration buck converter integrated with square spiral inductor Components Series# Size (mm 3 ) Description Regulator TPS62621 1.290*0.916*0.625 600 mA, 6 MHz 90% efficiency buck converter Cin ECJ 0EB0J225M 1.00 *0.50*0.55 X5R ceramic capacitor; 2.2 F 6.3V 20% Cout ECJ 0EB0J475M 1.00 *0.50*0.55 X5R ceramic capacitor; 4 7 F 6.3V 20% Square Spiral inductor 3.6*3.6*0.83 (with extra border) 84m Rdc, 430nH, 790 m Rac at 6MHz All the electrical components of the buck converter are listed in Table 6 1, and they are successfully assembled on to the designed PCB board through silver epoxy bonding (Epo Tek H20S) with the help of a flip chip bonding machine and the solder
150 ball/IC ch ip placing setup as illustrated in Figure 5 9. Jumpers are then soldered on to the PCB board. Figure 6 5 takes a photograph of the converter assembly without any jumper caps. Figure 6 5 A photograph of the buck converter demonstration assembly. Image courtesy of the author. 6 2 2 Characterization of the C onverter A ssembly This assembled buck converter module successfully delivered 6 00 mA at 1.8V with an 8 3 % maximum efficiency (PWM mode) at 6 MHz switching frequency At 0.6A load current, the power density of inductor reaches 120mW/mm 2 And Figure 6 6 and 6 7 illustrate the efficien cy measurements at different working modes, load currents and various temperature level s. The 3% loss cut compared with previous circular spiral inductor is mainly benefited from the lower DC and AC resistances, and higher inductance of the square spiral inductor. Attributing to the i mproved performances of TPS62621 regulator chip, the high efficiency range is also extended, 120 380mA load current with 80 83% efficiency of the square spiral assembly Vs 110 210mA load current with 74 77% efficiency of the circular spiral assembly. TPS62621 Cin Cout Square spiral inductor
151 Figure 6 6 Efficiency vs. load current square spiral (3.6/1.8 input/output voltage) Figure 6 7 Efficiency vs. temperature at different load current square spiral Note: 3.6/1.8 input/output voltage For the loss breakdown of the buck converter assembly with square spiral inductor, a t 3.6/ 1.8V, 129/214 mA input/output voltage and current settings the measured efficiency is 82.9 % which corresponds to 79 mW total loss. The Inductor DC resistance loss is about 0. 084 *(0. 214 ) 2 = 3.9 mW. The inductor ripple current is about ((3.6 1.8)/(2*430e 9))*(0.5/6e6)=174.4 mA and then the Inductor AC winding and magnetic resistance losses are about 0.790 *(0. 1744 ) 2 /3= 8 mW. The TPS62621
152 regulator has a rated efficiency of 90% which is about 46.5mW loss. Adding up these component losses, the module has 58.4mW losses without considering the core hysteresis loss, losses from parasitic resistances on the board, and losses from the capacitor parasitic
153 CHAPTER 7 SUMMARY AND FUTURE WORKS 7 .1 Summary Th e goal of th is project is to demonstrate in silicon wafer level in tegration of power inductors for high efficiency, high frequency and compact DC DC power converters. To achieve this goal, following tasks are performed Besides the frequency increase, i mproving the integration level of magnetic components in a power module was identified as one major approach to pave the way for the miniaturization trend of modern DC DC converter modules. Three levels of integration, i.e. b oard package and wafer level integration s were introduced and compared. Wh en the swi tching frequencies shift to MHz range, the inductance requirement and magnetic volume decrease, and this enables the wafer level heterogeneous integration of all components. Wafer level approaches provide better performance and smaller system size through compact interconnections. However, long development time and sophisticated production line compromise the cost saving goal of suppliers. A wafer level integration process is proposed based on silicon molding technique s, where an in silicon power inductor can be monolithically or heterogeneous ly integrated with IC circuitry to form a compact power converter. These i n silicon techniques well explore the bulky silicon substrate to improve the inductor performance, either for large cross section of conductors or for large core volume and still apply low temperature (<150 C ), in expensive MEMS integration processes compatible with full scale CMOS processing And a wafer level via first heterogeneous integration process
154 between the IC circuitry and MEMS inductor wafers can be achieved through solder or metal bump bonding with polymer underfill Several toroidal and spiral topologies were analyzed and compared. Spiral windings usually have smaller DC resistance and/or larg er inductance density than toroidal ones with the same footprint. And toroidal windings have better flux distribution and lower proximity effect and thereby have lower resistance at high frequenc ies over MHz. Preliminary circular spiral (330.6mm3, 390nH 140 m Q=10 at 6MHz) and toroidal (13130.32 mm3, 160nH, 265m Q=10.5 at 14MHz) inductors were fabricat ed and characteriz ed for process verification of the key silicon molding techniques. New fabrication process by replacing the solder ball s with elect roplated copper posts realized a 3*3*8.3mm 3 square spiral inductor with R DC =84 m L=430nH, R AC =792 m and Q=20.8 at 6MHz. This square spiral inductor was then assembled with TI TPS62621 buck converter for demonstration, and it successfully delivered 600mA at 1.8V with a maximum 83% efficiency at 6MHz. Copper vias and surface routings are also electroplated as circuit connection and mounting pads for other power converter components. Therefore, this high quality square in ductor is ready for fully integrated ultra compact power modules, and the whole fabrication procedure shows a promising future to be assimilated into Power ICs processing
155 7 .2 Future W orks 7 .2.1 Die level Assembly of the Square Spiral Inductor Besides the wafer level and board level integration, the die level assembly is also available for the square spiral inductors. The surface copper routing electroplated on both sides of the in silicon square spiral inductors can be used for landing pads of other converter components, such as power IC and capacitors. Flip chip bonding or manual soldering can be applied f or easy assembly of power converters, and this approach can still get compact power modules competitive to market products. Figure 7 1 illustrates the concept of die level assembly. One side integration or two side integration can be selected based on the sizing match of all components. The bottom solder balls in the one side integration approach can be used for PCB board bonding. A B Figure 7 1 Schematic of t he die level assembly of power inductor with ICs A) Two side integration B) One side integration 7 .2.2 Fully Integrated Boost Converter The proposed integration process can be demonstrated through a fully integrated boost converter which incorporates specially designed in silicon inductors and power ICs. Capacitors can be embedded into the IC circuitry on standard CMOS process, and Cu routing Solder balls Capacitors CMOS IC Spiral inductor Cu routing CMOS IC Spiral inductor Capacitors Solder balls
156 all converter components will be size matc hed for most compact and high efficient integration. Table 7 1 lists the objective specifications of the fully integrated boo s t converter. Now the square spiral inductors are already ready, and power IC is in the queue for fabrication. Once the Power IC is finished, assembly and characterization works are needed for the fully integrated boost converter. Table 7 1. Objective specifications of the fully integrated boost converter Parameter Value Parameter Value Switching frequency 4MHz Physical size < 4*4*2mm 3 Input voltage 4 8V Output voltage 12V Output Current >2.5A Efficiency 90% Inductance > 350nH DC resistance of inductor <120m Q of inductor >10 7 .2. 3 Integration of In Silicon Inductors for High Power POL Converter The previous power module with in substrate spiral inductor only achieved 6 00mA maximum output current. That is not sufficient to verify the higher current capability of the in substrate inductors. The 4MHz, 8A LTC3418 buck converter from Linear incorpora tion is one popular high power module in the market. And it requires one 0.2 H filter inductor, which is suitable for the current capability demonstration of in substrate inductors. The regulator is very large (5*7*0.75mm 3 size), and this leaves a lot roo m to design a low DC resistance and large cross section in substrate inductors. Excellent heat dissipation effects of the in substrate conductors will demonstrate their advantages at high power operation. For a 7*7mm 2 footprint with 2.5V and 8A power level it can reach 400mW/mm 2 which is much larger than the commercial ones (140mW/mm 2 ) of today.
157 APPENDIX A COMMERCIAL POWER COMPONENTS UNDER INVESTIGATION Table A 1. Typical synchronous buck converters for 2.7 5.5V input voltage, 1.8V output voltage, and 500 600mA output current. Products MFG. f (MHz) Vin/Vout/Iout (V/V/A) Package (mm 3 ) Rated L ( H) LTC3406 1.8 Linear 1.5 2.5 5.5/1.8/0.6 ThinSOT 5; 2.8*1.5*0.9 2.2 TPS62621 TI 6 2.3 5.5/1.8/0.6 6DSBGA; 1.25*0.88*0.4 0.47 AAT2749 Skyworks 3 2.3 5.5/1 1.8 /0.6 WLCSP 9L; 1.35*1.36*0.5 2.2 MAX8640Z MAXIM 4 2.7 5.5/1 1.8 /0.5 DFN/6; 1.45*0.95*0.65 1 ST1S12XX18 STM 1.7 2.5 5.5/1.8/0.7 TSOT23 5L; 2.9*1.6*1.1 2.2 Si9174 Vishay 2 2.7 6/ 0.44 3.83/0.6 MLP33 10; 3*3*0.8 2.2 NCP1523B ON 3 2.7 5.5/0.9 3.3 /0.6 Flipchip 8; 2.05*1.05*0.655 2.2 ISL9104 Intersil 4.3 2.7 6/0.8 6/0.5 6; 1.6*1.6*0.55 1 LM3677 TI 3 2.7 5.5/1.2 3.3 /0.6 5DSBGA; 0.49*1.11*0.6 1 mic2285a Micrel 8 2.7 5.5/1 Vin /0.6 10 Pin Thin MLF 2*2*0.55 0.47 Table A 2 Smallest regulators under investigation Products MFG. f (MHz) Vin/Vout/Iout (V/V/A) Package (mm 3 ) Inductor Integrated? LTC3410 Linear 2.25 2.5 5.5/0.8 5.5 /0.3 SC70 6; 1.8*1.15*1 not TPS62671 TI 6 2.3 4.8/1.8/0.5 6DSBGA; 1.25*0.88*0.4 not LM3677 TI 3 2.7 5.5/1.2 3.3 /0.6 5DSBGA; 0.49*1.11*0.6 not TPS62733 TI 3 1.9 3.9/2.3/0.1 6SON; 1.4*0.95*0.51 not AAT1149 AATI 3 2.7 5.5/1 Vin /0.4 WLCSP 5L; 1.235*0.91*0.58 not AAT1149A AATI 2.2 2.2 5.5/1.875 /0.4 WLCSP 5L; 1.235*0.91*0.58 not
158 Table A 2 Continued Products MFG. f (MHz) Vin/Vout/Iout (V/V/A) Package (mm 3 ) Inductor Integrated? IR3859M IR 1.5 1.5 21/ 0.7 18.9 /9 PQFN17; 4*5*0.8 not MC34713 F ree scale 1 3 6/0.7 3.6/5 QFN24; 4*4*1 not FA7701V Fuji 1 2.5 18/2.23/0.4 TSSOP 8; 3.1*4.4*1.3 not MCP16301 chip 0.5 4 30/2 15/0.6 6/SOT 23; 2.7*1.3*0.9 not NCP1523B On 3 2.7 5.5/0.9 3.3 /0.6 Flipchip 8; 2.05*1.05*0.655 not ISL9104 Intersil 4.3 2.7 6/0.8 6/0.5 6; 1.6*1.6*0.55 not TPS62660 TI 6 2.3 5.5/1.8/1 6DSBGA; 1.25*0.88*0.625 not MAX8640Y Maxim 2 2.7 5.5/1 2.5 /0.5 DFN/6; 1.45*0.95*0.65 not ST1S12XX STM 1.7 2.5 5.5/0.6 5 /0.7 TSOT23 5L; 2.9*1.6*1.1 not Si9174 Vishay 2 2.7 6/ 0.44 3.83 /0.6 MLP33 10; 3*3*0.8 not LTM8020 Linear 0.45 4 36/1.25 5 /0.2 6.25*6.25*2.32 yes TPS82670 TI 5.5 2.3 4.8/1.86 /0.6 8uSiP; 2.9*2.3*1 yes ISL8200M Intersil 1.5 3 20/0.6 6/10 15*15*2.2 yes EP5348UI EP 9 2.5 5.5/0.6 3.3 /0.4 uQFN14; 2*1.75*0.9 yes Note: All are buck converters Table A 3 Regulators at highest switching frequency from vendors Products MFG. f (MHz) Vin/Vout/Iout (V/V/A) Package (mm 3 ) Inductor Integrated? IR3859M IR 1.5 1.5 21/0.7 18.9 /9 PQFN17; 4*5*0.8 not MCP1603 chip 2 2.7 5.5/0.8 4.5 /0.5 TSOT 5; 2.9*1.6*1.1 not ISL9104 Intersil 4.3 2.7 6/0.8 6/0.5 6; 1.6*1.6*0.55 not LTC3605 Linear 4 4 15/0.6 14.85 /5 QFN 32; 4*4*0.75 not
159 Table A 3 Continued Products MFG. f (MHz) Vin/Vout/Iout (V/V/A) Package (mm 3 ) Inductor Integrated? ST1S12XX STM 1.7 2.5 5.5/0.6 5 /0.7 TSOT23 5L; 2.9*1.6*1.1 not SiP12101 Vishay 2 2.6 6 / /0.6 MSOP 10; 3*3*1.1 not LM8801 TI 6.4 2.3 5.5/ 1.8 1.85 /0.6 6DSBGA; 1.27*1.07*0.25 not AAT2113B AATI 3.3 2.7 5.5/1 2.5 /1.5 FTDFN 8L; 2*2*0.75 not MAX8805 Maxim 4 2.7 5.5/0.4 5.5 /0.65 WLP/16; 1.98*1.98*0.64 not MC34704 F ree scale 2 2.8 6.5/1.8 /0.55 QFN56; 7*7*1 not NCP6334 On 3 2.3 5.5/0.6 5/2 WDFN 8; 2*2*0.7 not FB6831J Fuji 2.5 2.7 5.5/0.8 4.8 /0.5 2.95*2.4*1 yes ISL8200M Intersil 1.5 3 20/0.6 6/10 15*15*2.2 yes LTM8025 Linear 2.4 3.6 36/0.8 24 /3 15*9*4.32 yes TPS82671 TI 5.5 2.3 4.8/1.8/0.6 8uSiP; 2.9*2.3*1 yes EP5348UI EP 9 2.5 5.5/0.6 3.3 uQFN14; 2*1.75*0.9 yes Note: All are buck converters Table A 4 Regulators with highest power density from vendors Products MFG. f (MHz) Vin/Vout/Iout (V/V/A) Package (mm 3 ) Inductor Integrated? LTC3879 Linear 2 4 38/0.6 34.2 /25 QFN 16; 3*3*0.75 not TPS54260 TI 2.5 3.5 60/0.8 58 /2.5 10SON; 2.9*2.9*0.8 not TPS54821 TI 1.6 4.5 17/0.6 15 /8 14QFN; 3.4*3.4*0.8 not LM34930 TI 2 8 33/2.5 30/1 12DSBGA; 1.77*2.08*0.6 not AAT1161 AATI 0.8 4 13.3/0.6 Vin /3 TDFN33 14L; 3*3*0.75 not AAT2687 AATI 0.49 6 24/1.5 5.5 /4.5 TQFN 24L; 4*5*0.75 not
160 Table A 4 Continued Products MFG. f (MHz) Vin/Vout/Iout (V/V/A) Package (mm 3 ) Inductor Integrated? ISL8500 Intersil 0.5 5.5 25/0.6 19 /2 DFN 12; 4*3*0.9 not ISL8560 Intersil 0.6 9 60/1.21 55/2 QFN20; 6*6*0.9 not L7981 STM 0.25 4.5 28/0.6 28 /3 VDFPN8; 3*3*0.8 not MC34713 Free scale 1 3 6/0.7 3.6/5 QFN24; 4*4*1 not FA7764 Fuji 0.4 9 45/3.1 5.5/1.5 SOP8E; 5*3.9*1.7 not IR3840AM IR 1 1.5 21/ 0.7 18.9 /14 PQFN; 5*6*0.8 not MAX15118 MAXIM 1 2.7 5.5/ 0.6 5.17 /18 WLP/28; 3.51*2.05*0.64 not MAX15066 MAXIM 0.5 4.5 16/0.6 14 /4 WLP/16; 1.98*1.98*0.64 not Si9174 Vishay 2 2.7 6/ 0.44 3.83 /0.6 MLP33 10; 3*3*0.8 not MCP16323 chip 1 6 18/0.9 5/3 QFN 16; 3*3*0.9 not ZL9117M Intersil 0.571 4.5 13.2/ 0.6 3.6 /17 QFN21; 15*15*3.5 y es LTM8026 Linear 1 6 36/1.2 24/5 11.25*15*2.82 yes LMZ10501 TI 2 2.7 5.5/0.6 3.6 /1 8POS; 3.0*2.5*1.2 yes TPS84620 TI 0.78 4.5 14.5/ 1.2 5.5 /6 47B1QFN; 9*15*2.8 yes TPS84250 TI 0.78 7 50/2.5 15 /2.5 41B1QFN; 9*11*2.8 yes EP53F8QI EP 4 2.4 5.5/0.8 3.3 /1.5 QFN16; 3*3*1.1 yes FB6831J Fuji 2.5 2.7 5.5/0.8 4.8 /0.5 2.95*2.4*1 yes ISL8200M Intersil 1.5 3 20/0.6 6/10 15*15*2.2 yes Note: All are buck converters
161 T able A 5 Capactors from vendors MFG. Series Material Min chip (NO.) (mm) Max C ( F) @100 KHz ESR Rated V (V) note AVX PMC SiON 0.25*0.25 0.0005 100 600V/m AVX PMC SiO2 0.25*0.25 0.0005 100 1000V/m AVX PMC BCB 0.5*0.5 5e 5 25 300V/m AVX NOJ Niobium Oxide 2.05*1.35 *1.50 22 3.8 2.5 NOJP226M0 02#WJ Vishay Thin film SiO2/Si3N4 0.51*0.51 *0.25(0202) 5 1 e 5 200 NC Series Vishay Thin film SiO2/Si3N4 1.52*1.52 *0.25(0606) 0.001 65 NC Series AVX TLC Tantalum 1*0.5*0.5 (0402) 15 15 2 TLCK156M00 2#TA Vishay Solid Tantalum Chip 1*0.5*0.6 (0402) 22 20 4 298W226X00 04K2T Kemet Tantalum High Rel COTS 2.54*1.27 *1.27 6.8 6 4 T497A685 Nichi con Solid tantalum electrolytic F98 Resin molded Chip 1.1*0.6*0.35 (U) 10 30 6.3 F980J106MU A Pana sonic POSCAP TPU 2*1.25*0.9 (S09) 100 0.15 2.5 ETPU100MSI Rohm Tantalum TCT 1*0.5*0.6 (0402) 15 2.5 TCTU0E156 M8R AVX Ceramic X5R 0.4*0.2*0.22 (01005) 0.01 6.3 010056D AVX Ceramic X5R 0.6*0.3*0.33 (0201) 1 4 02014D AVX PMC Ceramic X7R 0.5*0.5 0.4 5 100V/m Murata Ceramic X5R 0.4*0.2*0.2 (01005) 0.1 0.5 4 GRM022R60 G104ME15# Murata Ceramic X7R 0.38*0.38*0. 3(015015) 0.01 10 GMA0D3R71 A103MA01# Murata Ceramic X5R 1*0.5*0.5 (0402) 10 0.005 4 GRM155R60 G106ME44# Murata Ceramic X5R 0.6*0.3*0.3 (0201) 0.47 0.08 4 GRM033R60 G474ME90# Murata Ceramic X5R 0.5*0.5*0.35 (0202) 0.1 6.3 GMA05XR60 J104ME12# Murata Ceramic X5R 0.5*0.5*0.35 (0202) 0.1 6.3 GMA05XR60 J104ME12#
162 Table A 5 C ontinued MFG. Series Material Min chip (NO.) (mm) Max C ( F) @100 KHz ESR Rated V (V) note Murata Ceramic X5R 0.9*0.6*0.45 (0302) 1 6.3 GNM0M2R60 J105ME18# Murata Ceramic X5R 0.8*0.8*0.5 (0303) 0.47 6.3 GMA085R60 J474ME12# Vishay Ceramic X5R 0.6*0.3*0.33 (0201) 0.2 50 VJ.W1BC Ultra Small Series Vishay Ceramic Y5V 1*0.5*0.55 (0402) 1 50 VJ.W1BC Basic Commodity EPCOS Multilayer Ceramic 0.4*0.2*0.2 0.01 6.3 C0402JB0J1 03M(020BB) EPCOS Multilayer Ceramic 0.6*0.3*0.3 0.22 10 C0603JB1A2 24M(030BB) EPCOS Multilayer Ceramic 1*0.5*0.5 4.7 4 C1005JB0G4 75M(050BB) Kemet Multilayer Ceramic X8L 1*0.5*0.5 (0402) 0.047 10 High Temperature Kemet Multilayer Ceramic X5R 1*0.5*0.5 (0402) 4.7 4 Commercial Grade Kemet Multilayer Ceramic X5R 0.6*0.3*0.3 (0201) 0.1 6.3 Commercial Grade Nippon Multilayer Ceramic THC 2*1.25*1.25 0.68 0.04 25 KHC250E684 M21N0T00 Pana sonic Plastic film Stacked metallized PPS film chip 1.6*0.8*0.7 0.0027 16 ECHU1C272 Kemet CBR Series C0G 0.6*0.3*0.3 (0201) 0.0000 33 10 Ultra High Q, Low ESR Kemet CBR Series C0G 1*0.5*0.5 (0402) 0.0000 22 0.03 0.09 50 Ultra High Q, Low ESR T able A 6 Inductor s from vendors MFG. Series Material Min chip (NO.) (mm) Range ( nH ) Rdc SRF ( GHz ) Imax (A) AVX ACCU L 0603 1.6*0.81 *0.61 1.2 15 0.04 0.60 2.5 10 0.3 1 AVX HL02 0.98*0.58 *0.35 1 32 0.095 1.935 1.73 18.3 0.15 0.35
163 Table A 6 C ontinued MFG. Series Material Min chip (NO.) (mm) Range (nH) Rdc SRF (GHz) Imax (A) AVX L0402 1*0.85 *0.35 0.82 6.8 0.06 0.9 6.5 20 0.2 0.5 Murata LQM18F chip 1.6*0.8*0.8 (0603) 1e3 1e4 0.2 0.9 0.03 0.12 0.05 0.15 Murata LQG15H chip 1*0.5*0.5 (0402) 1 270 0.07 4.94 0.4 10 0.11 0.3 Murata LQW04A chip 0.8*0.4*0.4 (03015) 1.1 33 0.03 1.11 4 20 0.14 0.99 Murata LQP02T chip 0.4*0.2*0.2 (01005) 0.4 18 0.6 4.8 2.5 6 0.14 0.32 Vishay IFSC 0806AZ 01 power 2*1.6*1 1e3 2.2e4 0.096 2.840 >5e 3 0.43 1.88 Vishay IMC 0402 high frequency 1*0.5*0.5 1 100 0.05 5.5 1.2 6 0.09 0.4 Vishay IMC 1008 high frequency 2.5*2*1.6 3.3 4.7e4 0.06 12 0.017 6 0.045 1 Vishay IMC 0402 01, wirewound 1*0.55*0.5 1 120 0.045 2.660 1.1 6 0.1 1.36 EPCOS MLG0402Q, Multilayer/Q up 0.4*0.2*0.2 0.2 12 0.1 2.6 3 10 0.14 0.35 EPCOS MLG0603S, Multilayer/STD 0.6*0.3*0.3 0.3 180 0.1 8.5 0.56 10 0.05 0.6 EPCOS MLZ1005W, Multilayer/STD 1*0.5*0.5 470 2200 0.2 0.55 0.12 0.26 0.06 0.12 KOA Air core chip KQT0402 1*0.5*0.55 (0402) 1 120 0.045 2.32 1.5 11 0.12 1.36 KOA Air core chip KQC0402 1*0.5*0.55 (0402) 1.4 6.2 0.019 0.045 5.6 11 0.9 1.4 KOA Thin film chip KL731E 1*0.5*0.35 (0402) 0.56 33 0.1 5 1 14 0.15 0.7 Pana sonic Chip High f, non magnetic ELJRFR10FB 1*0.5*0.5 (0402) 100 5.5 1.2 0.09 Pana sonic LC Composite ELWCF850F 1*0.5*0.5 (0402) 99 10 0.85 0.09
164 APPENDIX B BUCK CONVERTER MEASUREMENT DATA T able B 1 TPS62621 buck converter assembly PWM mode test data (3.6/1.8 V input/output voltage) Iin (mA) Iout (mA) Efficiency (%) Iin (mA) Iout (mA) Efficiency (%) 348 518 74.4 138 228 82.6 309 471 76.2 129 214 82.9 301 461 76. 6 114 189 82. 9 289 445 7 7.0 103 170 82.5 280 434 77.5 98 161 82. 1 272 423 77. 8 93 153 82. 3 259 406 78. 4 86 140 81.4 242 383 79. 1 77 124 80.5 226 362 80. 1 64 101 78.9 213 342 80. 3 58 90 77. 6 203 329 81.0 48 71 7 4.0 191 310 81. 2 40 54 67.5 180 292 81.1 33 41 62.1 163 267 81.9 24 23 47.9 148 245 82. 8 20 13 32.5 T able B 2 TPS62621 buck converter assembly PFM/PWM mode test data (3.6/1.8 V input/output voltage) Iin (mA) Iout (mA) Efficiency (%) Iin (mA) Iout (mA) Efficiency (%) 8 12 75.0 78 123 78.8 16 24 75.0 91 146 80.2 25 37 74.0 105 169 80. 5 32 48 75.0 116 189 81. 5 41 62 75.6 132 214 81. 1 52 78 75.0 142 229 80.6
165 Table B 2 C ontinued Iin (mA) Iout (mA) Efficiency (%) Iin (mA) Iout (mA) Efficiency (%) 60 91 75.8 152 246 80.9 68 103 75.7 164 266 81. 1 179 291 81. 3 269 423 78.6 202 323 80.0 290 449 77.4 215 344 80 .0 297 460 77.4 226 361 79. 9 323 485 75. 1 247 393 79. 6 348 515 7 4.0 T able B 3 TPS62621 buck converter assembly efficiency Vs temperature data ( PWM mode, 3.6/1.8 V input/output voltage) TEMP. ( C) Iin (mA) Iout fixed (mA) Efficiency (%) TEMP. ( C) Iin (mA) Iout fixed (mA) Efficiency (%) 25 53.35 79 74.039 85 109.3 0 178 81.427 40 53.47 79 73.873 100 109.54 178 81.249 55 53.65 79 73.625 25 138.53 227 81.932 70 53.81 79 73.406 40 138.83 227 81.755 85 54.05 79 73.08 0 55 139.27 227 81.496 100 54.16 79 72.932 70 139.59 227 81.31 0 25 74.69 119 79.663 85 140.2 0 227 80.956 40 74.84 119 79.503 100 140.36 227 80.863 55 75.05 119 79.28 0 25 197.3 0 316 80.081 70 75.33 119 78.986 40 197.68 316 79.927 85 75.51 119 78.798 55 198.53 316 79.58 5 100 75.7 0 119 78.6 00 70 199.1 0 316 79.357 25 108.15 178 82.293 85 199.7 0 316 79.11 9 40 108.35 178 82.141 100 200.05 316 78.980 55 108.66 178 81.907 70 108.93 178 81.704
166 LIST OF REFERENCES  R. W. Erickson, Fundamentals of power electronics New York: Chapman & Hall, 1997.  A. J. Stratakos, "High efficiency low voltage DC DC conversion for portable applications," Ph.D. dissertation, University of California, Berkeley, United States -California, 1998.  C. R. Sullivan, "Inte grating magnetics for on chip power: Challenges and opportunities in IEEE Custom Integrated Circuits Conf.(CICC '09) 2009, pp. 291 298  M. D. Seeman, V. W. Ng, L. Hanh Phuc, M. John, E. Alon, and S. R. Sanders, "A comparative analysis of Switched Capacitor and inductor based DC DC conversion technologies," in IEEE 12th Workshop on Control and Modeling for Power Electronics (COMPEL) 2010, pp. 1 7.  M. Wens and M. Steyaert, Design and implementation of fully integrated inductive DC DC converters in standard CMOS Dordrecht ; New York, 2011.  E. Kaoutar and S. Khadija, "Integrated Circuit of CMOS DC DC Buck Converter with Differential A ctive Inductor," Int. J of Computer Science Issues, vol. 8, pp. 157 162, 11/30 2011.  A. Makharia and G. A. Rincon Mora, "Integrating power inductors onto the IC SOC implementation of inductor multipliers for dc dc converters," in The 29th Annu. Conf. o f the IEEE Industrial Electronics Society(IECON '03) 2003, pp. 556 561 vol.1.  X. Wang, "Power Efficiency Conscious Design and Implementation of High Frequency Integrated Synchronous Buck DC DC Converters for Portable Electronics Applications," Ph.D. Di ssertation, North Carolina State University, United States -North Carolina, 2010.  T. H. Ning, "Silicon VLSI trends what else besides scaling CMOS to its limit?," in 10th Int. Symp. on the Physical and Failure Analysis of Integrated Circuits(IPFA 20 03) 2003, pp. 1 4.  P. H. Lan, Y. J. Kuo, and P. C. Huang, "An area efficient CMOS switching converter with on chip LC filter using feedforward ripple cancellation technique," in Int. Symp. on VLSI Design, Automation, and Test (VLSI DAT) 2012, pp. 1 4  Y. Liu, "Trends of power semiconductor wafer level packaging," Microelectronics Reliability, vol. 50, pp. 514 521, 2010.  S. D. Senturia, Microsystem design Boston: Kluwer Academic Publishers, 2001.
167  Q. Li, M. Lim, J. Sun, A. Ball, Y. Ying, F. C. Lee et al. "Technology roadmap for high frequency integrated DC DC converter," in IEEE 6th Int. Power Electronics and Motion Control Conf. (IPEMC '09) 2009, pp. 1 8.  M. Esashi, "Wafer level packaging of MEMS," in Int. Solid State Sensors, Ac tuators and Microsystems Conf. (TRANSDUCERS 2009) 2009, pp. 9 16.  A. W. Lotfi, Q. Li, and F. C. Lee, "Integrated, High Frequency DC DC Converter Technologies Leading to Monolithic Power Conversion," in 7th Int. Conf. on Integrated Power Electronics S ystems (CIPS) 2012, pp. 1 8.  K. Yao, Y. Meng, and F. C. Lee, "Control bandwidth and transient response of buck converters," in IEEE 33rd Annu. Power Electronics Specialists Conf.(pesc 02) 2002, pp. 137 142 vol.1.  M. Gildersleeve, H. P. Forghani Zadeh, and G. A. Rincon Mora, "A comprehensive power analysis and a highly efficient, mode hopping DC DC converter," in IEEE Asia Pacific ASIC Conf. 2002, pp. 153 156.  E. Waffenschmidt, B. Ackermann, and J. A. Ferreira, "Design method and material t echnologies for passives in printed circuit Board Embedded circuits," IEEE Trans. Power Electron., vol. 20, pp. 576 584, 2005.  E. Waffenschmidt and J. A. Ferreira, "Embedded passives integrated circuits for power converters," in IEEE 33rd Annu. Power Electronics Specialists Conf.(pesc 02) 2002, pp. 12 17 vol.1.  M. Ludwig, M. Duffy, T. O'Donnell, P. McCloskey, and S. C. O. Mathuna, "PCB integrated inductors for low power DC/DC converter," IEEE Trans. Power Electron., vol. 18, pp. 937 945, 2003. [2 1] I. Kowase, T. Sato, K. Yamasawa, and Y. Miura, "A planar inductor using Mn Zn ferrite/polyimide composite thick film for low Voltage and large current DC DC converter," IEEE Trans. Magn., vol. 41, pp. 3991 3993, 2005.  M. H. Lim, J. D. Van Wyk, F. C. Lee, and K. D. T. Ngo, "A Class of Ceramic Based Chip Inductors for Hybrid Integration in Power Supplies," IEEE Trans. Power Electron., vol. 23, pp. 1556 1564, 2008.  T. Mikura, K. Nakahara, K. Ikeda, K. Furukuwa, and K. Onitsuka, "New substrate for micro DC DC converter," in 56th Electronic Components and Technology Conf. 2006, p. 5 pp.  R. Hahn, S. Krumbholz, and H. Reichl, "Low profile power inductors based on ferromagnetic LTCC technology," in 56th Electronic Com ponents and Technology Conf. 2006, p. 6 pp.
168  M. Conner, "IC LIKE MODULES SIMPLIFY SYSTEM DC/DC POWER DESIGN," EDN, vol. 56, pp. 29 34, 2011.  "Enpirion EN23F0QI and EP5348UI datasheets."  "Fuji A 2nd generation micro DC DC converter.."  J. Lu, "Embedded magnetics for power system on chip (PSoC)," Ph.D. Dissertation, University of Central Florida, United States -Florida, 2009.  M. Wens and M. Steyaert, "A fully integrated 0.18um CMOS DC DC step down converter, using a bondwire spiral i nductor," in IEEE Custom Integrated Circuits Conf. (CICC 2008) 2008, pp. 17 20.  T. Liakopoulos, A. Panda, M. Wilkowski, A. Lotfi, K. H. Tan, L. Zhang et al. "Introducing FCA, a new alloy for Power Systems on a chip and Wafer Level Magnetic applicat ions," in 13th Int. Conf. on Electronic Packaging Technology and High Density Packaging (ICEPT HDP) 2012, pp. 949 954.  W. Y. Liu, J. Suryanarayanan, J. Nath, S. Mohammadi, L. P. B. Katehi, and M. B. Steer, "Toroidal inductors for radio frequency inte grated circuits," IEEE Trans. Microw. Theory Tech., vol. 52, pp. 646 654, 2004.  M. Z. Yang, C. L. Dai, and J. Y. Hong, "Manufacture and Characterization of High Q Factor Inductors Based on CMOS MEMS Techniques," Sensors (Basel), vol. 11, pp. 9798 9806 2011.  C. P. Yue and S. S. Wong, "On chip Spiral Inductors With Patterned Ground Shields For Si based RF IC's," in Tech. Dig. Symp. on VLSI Circuits 1997, pp. 85 86.  J. Wibben and R. Harjani, "A High Efficiency DC DC Converter Using 2 nH Integrated Inductors," IEEE J. Solid State Circuits, vol. 43, pp. 844 854, 2008.  C. D. Meyer, S. S. Bedair, B. C. Morgan, and D. P. Arnold, "Ultra miniaturized power converter mod ules using micromachined copper scaffolds," IEEE Int. Conf. on Micro Electro Mechanical Systems (MEMS, Hilton Head), 2012.  Y. Katayama, S. Sugahara, H. Nakazawa, and M. Edo, "High power density MHz switching monolithic DC DC converter with thin film i nductor," in IEEE 31st Annu. Power Electronics Specialists Conf.(pesc 00) 2000, pp. 1485 1490 vol.3.  C. H. Ahn and M. G. Allen, "A comparison of two micromachined inductors (bar and meander type) for fully integrated boost DC/DC power converters," IE EE Trans. Power Electron., vol. 11, pp. 239 245, 1996.
169  B. Orlando, R. Hida, R. Cuchet, M. Audoin, B. Viala, D. Pellissier Tanon et al. "Low Resistance Integrated Toroidal Inductor for Power Management," IEEE Trans. Magn., vol. 42, pp. 3374 3376, 200 6.  M. Wang, "Integrated power inductors in silicon for compact DC DC converters in portable electronics," University of Florida, Gainesville, Fl, 2010.  H. Ito, A. Takeuchi, S. Okazaki, H. Kobayashi, Y. Sugawa, A. Takeshima et al. "Fabrication o f Planar Power Inductor for Embedded Passives in LSI Package for Hundreds Megahertz Switching DC DC Buck Converter," IEEE Trans. Magn., vol. 47, pp. 3204 3207, 2011.  T. D. Xiao, X. Q. Ma, H. Zhang, D. E. Reisner, P. M. Raj, L. Wan et al. "Magnetic Nanocomposite Paste: An Ideal High k and Q Nanomaterial for Embedded Inductors in High Frequency Electronic Applications," in 9th World Multi co nference on Systemics, Cybernetics and Informatics 2005, pp. 217 222.  C. Yang, K. Koh, X. Zhu, and L. Lin, "On chip RF inductors with magnetic nano particles medium," in 16th Int. Solid State Sensors, Actuators and Microsystems Conf. (TRANSDUCERS) 2011, pp. 2801 2804.  X. Yu, M. Kim, F. Herrault, C. H. Ji, J. Kim, and M. G. Allen, "Silicon embedded 3D toroidal air core inductor with through wafer interconnect for on chip integration," in IEEE 25th Int. Conf. on Micro Electro Mechanical Systems (MEMS) 2012, pp. 325 328.  D. Yao, C. G. Levey, R. Tian, and C. R. Sullivan, "Microfabricated V Groove Power Inductors Using Multilayer Co Zr O Thin Films for Very High Frequency DC DC Converters," IEEE Trans. Power Electron., vol. PP, pp. 1 1, 2011.  M. Wang, J. Li, K. D. T. Ngo, and H. Xie, "A Surface Mountable Microfabricated Power Inductor in Silicon for Ultracompact Power Supplies," IEEE Trans. Power Electron., vol. 26, pp. 1310 1315, 2011.  P. M. Dentinger, W. M. Clift, and S. H. Goods, "Removal of SU 8 photoresist for thick film applications," Microelectronic Engineering, vol. 61 62, pp. 993 1000, 2002.  D. Lin, P. Zhou, W. N. Fu, Z. Badics, and Z. J. Cendes, "A dynamic core loss model for soft ferromagnetic and power ferrite materials in transient finite element analysis," IEEE Trans. Magn., vol. 40, pp. 1318 1321, 2004.  "Fe rroxcube datasheets for 4F1, 3F5 and iron powder cores.."  "magnetics datesheet for Kool Mu powder cores."
170  L. P. Lefebvre, S. Pelletier, and C. Gelinas, "Effect of electrical resistivity on core losses in soft magnetic iron powder materials," J MA GN MAGN MATER, vol. 176, pp. L93 L96, 1997.  Y. Y. Park, S. H. Han, and M. G. Allen, "Batch fabricated microinductors with electroplated magnetically anisotropic and laminated alloy cores," IEEE Trans. Magn., vol. 35, pp. 4291 4300, 1999.  P. Dhaga t, S. Prabhakaran, and C. R. Sullivan, "Comparison of magnetic materials for V groove inductors in optimized high frequency DC DC converters," IEEE Trans. Magn., vol. 40, pp. 2008 2010, 2004.  J. Y. Park and M. G. Allen, "Low temperature fabrication an d characterization of integrated packaging compatible, ferrite core magnetic devices," in 12th Annu. Applied Power Electronics Conf.( APEC '97) 1997, pp. 361 367 vol.1.  J. Li, K. D. T. Ngo, G. Q. Lu, and H. Xie, "Wafer level fabrication of high power density MEMS passives based on silicon molding technique," in 7th Int. Conf. on Integrated Power Electronics Systems (CIPS) 2012, pp. 1 5.  T. Osaka, M. Takai, K. Hayashi, K. Ohashi, M. Saito, and K. Yamada, "A soft magnetic CoNiFe film with high satu ration magnetic flux density and low coercivity," Nature, vol. 392, pp. 796 798, 1998.  W. Li, Y. Sun, and C. R. Sullivan, "High frequency resistivity of soft magnetic granular films," IEEE Trans. Magn., vol. 41, pp. 3283 3285, 2005.  S. C. O. Math una, T. O'Donnell, N. Wang, and K. Rinne, "Magnetics on silicon: an enabling technology for power supply on chip," IEEE Trans. Power Electron., vol. 20, pp. 585 592, 2005.  W. j. Gu and R. Liu, "A study of volume and weight vs. frequency for high frequ ency transformers," in 24th Annu. IEEE Power Electronics Specialists Conf. (PESC '93) 1993, pp. 1123 1129.  E. C. Snelling, Soft ferrites: properties and applications London ; Boston: Butterworths, 1988.  W. B. Kuhn and N. M. Ibrahim, "Analysis o f current crowding effects in multiturn spiral inductors," IEEE Trans. Microw. Theory Tech., vol. 49, pp. 31 38, 2001.  M. Bartoli, A. Reatti, and M. K. Kazimierczuk, "High frequency models of ferrite core inductors," in 20th Int. Conf. on Industrial Electronics, Control and Instrumentation( IECON '94) 1994, pp. 1670 1675 vol.3.
171  G. Grandi, M. K. Kazimierczuk, A. Massarini, and U. Reggiani, "Stray capacitances of single layer air core inductors for high frequency applications," in IEEE 31st Industry Applications Society Conf.(IAS '96.) 1996, pp. 1384 1388 vol.3.  S. Wang, Z. Liu, and Y. Xing, "Extraction of parasitic capacitance for toroidal ferrite core inductor," in 5th IEEE Conf. on Industrial Electronics and Applications (ICIEA) 201 0, pp. 451 456.  Q. Yu and T. W. Holmes, "Stray capacitance modeling of inductors by using the finite element method," in IEEE Int. Symp. on Electromagnetic Compatibility 1999, pp. 305 310 vol.1.  P. Nilsson, M. Jonsson, and L. Stenmark, "Chip mou nting and interconnection in multi chip modules for space applications," J MICROMECH MICROENG, vol. 11, p. 339, 2001.  "TI TPS62621 datasheet," 2011.
172 BIOGRAPHICAL SKETCH Jiping Li received his B.S. degree in Electrical Engineering from Shandong U niversity, Jinan China in 1997, and M.S. degree in Electrical Engineering from North China Electric Power University Beijing, China in 200 0 respectively. He also holds a Ph.D. degree in Electrical and Computer Engineering from the University of Florida in 201 3 His research interests include the development of small form factor, high power efficiency integrated power converters for portable electronics and MEMS fabrication techniques compatible with CMOS processing