High Voltage Switched-Mode Step-Up DC-DC Converters in Standard CMOS Process

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Title:
High Voltage Switched-Mode Step-Up DC-DC Converters in Standard CMOS Process
Physical Description:
1 online resource (171 p.)
Language:
english
Creator:
Xue, Lin
Publisher:
University of Florida
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Gainesville, Fla.
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Thesis/Dissertation Information

Degree:
Doctorate ( Ph.D.)
Degree Grantor:
University of Florida
Degree Disciplines:
Electrical and Computer Engineering
Committee Chair:
BASHIRULLAH,RIZWAN
Committee Co-Chair:
ARNOLD,DAVID P
Committee Members:
FOX,ROBERT M
VU,LOC QUOC

Subjects

Subjects / Keywords:
boost -- dc-dc -- high-voltage -- power-converter -- step-up -- switched-mode
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre:
Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract:
Onchip integration of switched-mode step-up converters in CMOS can be attractive for portable devices powered from single-cell batteries. For instance, some autonomous microsystems, such as life-sized robotic insects that roll, crawl, jump, or fly, require specialized high voltage converters to electrically drive piezoelectric actuators for transforming power into locomotion. In such applications power converters must meet stringent mass and volume requirements,a reality that has led to increasing interest in onchip high-frequency step-up converters. This work begins with an overview of basic step up converter topologies and CMOS compatible high voltage tolerant device techniques. Analysis shows output voltage is limited by breakdown of critical devices. Three high voltage tolerant devices and two hybrid topologies are then presented, all in 1.2V CMOS. Without adding any extra masking steps, output voltage is extended to 10V, 8x larger than the input. Moreover, microfabricated inductors and transformers are also demonstrated with the two converters for comparable performance but much smaller footprint than commercial counterparts.  Performance of hybrid step-up converters are further analyzed with a general circuit model proposed which uses a theoretic network methodology to evaluate output impedance and to account for various sources of switching loss prevalent at high operating frequencies and in onchip implementations. Unlike previous approaches, ours divides dynamic switching loss into output unrelated and related. It then uses two equivalent input and output resistive loads to model them separately. Comparisons with SPICE simulations and experimental results demonstrate that the proposed approach is accurate for evaluating power efficiency and output voltage. A complete hybrid SI-SC step up converter with a 4-stage SC ladder multiplier and an inherently-stable hysteretic controller is developed in a 1.2V CMOS process with minimal post-process steps for piezoelectric microsystems. An optimal design procedure based on theoretic network analysis is also presented. Experimental results show the hybrid converter achieves maximum output of 35V at 200µA.Moreover, the hybrid converter is employed with a commercial microprocessor to form a smart piezoelectric microsystem demo for successfully driving a 25Hz resonant piezo fan.
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In the series University of Florida Digital Collections.
General Note:
Includes vita.
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Includes bibliographical references.
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Description based on online resource; title from PDF title page.
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This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility:
by Lin Xue.
Thesis:
Thesis (Ph.D.)--University of Florida, 2013.
Local:
Adviser: BASHIRULLAH,RIZWAN.
Local:
Co-adviser: ARNOLD,DAVID P.
Electronic Access:
RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2014-06-30

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Applicable rights reserved.
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lcc - LD1780 2013
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UFE0046132:00001


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1 HIGH VOLTAGE SWITCH ED MODE STEP UP DC DC CONVERTERS IN STANDARD CMOS PROCESS By LIN XUE A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGR EE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 201 3

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2 201 3 L in X ue

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3 To my Mom and Dad

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4 ACKNOWLEDGMENTS First of all I would like to thank my academic advisors, Dr. Rizwan Bashirullah for his valuable guidance over the course of the last six years. I would also like to thank Dr. David Arnold, Dr Robert Fox and Dr. Loc Vu Quoc for their advice and their willingness to be i n my dissertation committee. T hank s are also given to Brian Morgan and Army Research Laboratory for funding support. T hanks to UMC for chip fabrication S pecial thanks are given to Chris Meyer, Christopher M. Dougherty Deepak Bhatia, Pengfei Li and Qiuzhong Wu for having useful design related discussions. I would also like to thank Jikai Chen, Yan Hu, H o ng Yu, C hunming Tang Walker Turner, Zhiming Xiao, and Pawan Sabharwal for always being open to answer any question at any time, let it be day or night. Speaking about the classes at UFL, I would like to thanks Dr. Bashirullah for his excellent Advanced VLSI class, Dr F ox for his Bipolar and MOS design class, especially the simple design related approach and second order analysis, Dr O for his excellent Microwave IC design class. Finally, I would like to thank my mom, dad for all their love and support till date.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ .. 4 LIST OF TABLES ................................ ................................ ................................ ............ 8 LIST OF FIGURES ................................ ................................ ................................ .......... 9 LIST OF ABBREVIATIONS ................................ ................................ ........................... 15 ABSTRACT ................................ ................................ ................................ ................... 16 CHAPTER 1 INTRODUCTION ................................ ................................ ................................ .... 18 1.1 Research Background ................................ ................................ ...................... 18 1.2 Recent Progress towards Miniaturization of Step Up Voltage Converters ........ 20 1.2.1 High Voltage Step U p Converters U sing Discrete Components .............. 20 1.2.2 Integration of Step Up Voltage Converters in CMOS Processes ............. 22 1.3 Dissertation Organization ................................ ................................ .................. 24 2 REVIEW ON SWITCHING STEP UP VOLTAGE CONVERTERS .......................... 25 2.1 Introd uction of Switching Step Up Converters ................................ .................. 25 2.2 Basic Switching Step Up Converter Topologies ................................ ............... 25 2.2.1 SI Boost Converter ................................ ................................ .................. 25 2.2.2 Flyback Converter ................................ ................................ ................... 28 2.2.3 Switched Capacitor Step Up Converters ................................ ................. 31 2.2.3.1 Ladder (Cockcroft Walton) ................................ ............................. 32 2.2.3.2 Dickson charge pump ................................ ................................ .... 33 2.2.3.3 Fibonacci converter ................................ ................................ ........ 34 2.2.3.4 Series p arallel converter ................................ ................................ 36 2.2.3.5 Summary of SC converters ................................ ............................ 37 2.3 Averaged Swi tching Network ................................ ................................ ............ 37 2.3.1 Averaged L S D Network in CCM ................................ ............................ 37 2.3.2 Averaged L S D Network in DCM ................................ ............................ 39 2.3.3 Small Signal Analysis of SI Boost Converter in CCM .............................. 41 2.3.4 Small Signal Analysis of SI Boost Converter in DCM .............................. 42 2.4 Control Scheme of DC DC Converters ................................ ............................. 44 2.4.1 Voltage Mode Pulse Width Modulation (PWM) ................................ ........ 44 2.4.2 Curre nt Mode PWM ................................ ................................ ................. 45 2.4.3 Pulse Frequency Modulation (PFM) ................................ ........................ 47 3 CUSTOM HIGH VOLTAGE POWER DEVICES IN STANDARD CMOS PROCESS ................................ ................................ ................................ .............. 49

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6 3.1 Introduction of High Voltage Devices ................................ ................................ 49 3.2 Voltage Limit Effects in Standard CMOS Process ................................ ............ 49 3.2.1 Channel Hot Carrier Effects ................................ ................................ ..... 49 3.2.2 Gate Oxide Breakdown ................................ ................................ ........... 51 3.2.3 Avalanche Breakdown ................................ ................................ ............. 51 3.2.3.1 Planar junction edge effects ................................ ........................... 52 3.2.3.2 Layout improvement techniques ................................ .................... 54 3.2.3.3 Open base transistor breakdown ................................ ................... 56 3.2.4 Electromigration ................................ ................................ ...................... 57 3.3 Schottky Barrier Diodes ................................ ................................ .................... 57 3.3.1 Schottky Barrier Contact in CMOS ................................ .......................... 57 3.3.2 Guard Rings for SBDs ................................ ................................ ............. 58 3.3.3 Mea surement Results and Parameter Extraction ................................ .... 59 3.4 Power Switches ................................ ................................ ................................ 62 3.4.1 Extended Drain MOSFET ................................ ................................ ........ 63 3.4.2 Stacked MOSFET ................................ ................................ .................... 67 3.5 Performance Comparison ................................ ................................ ................. 72 4 50 100MHZ 8X HRBRID SI SC AND SI FLYBA CK CONVERTER IN 130NM CMOS PROCESS ................................ ................................ ................................ .. 74 4.1 Introduction of Hybrid Converters ................................ ................................ ..... 74 4.2 Hybrid Converter Topologies ................................ ................................ ............ 74 4.2.1 SI SC Converter ................................ ................................ ...................... 76 4.2.2 SI Flyback Converter ................................ ................................ ............... 78 4.3 Microfabricated Air Core Power Magnetics ................................ ....................... 80 4.3.1 Layout Design ................................ ................................ ......................... 81 4.3.2 Process Flow ................................ ................................ ........................... 82 4.4 Current Mode PWM Controller ................................ ................................ .......... 83 4.4.1 Voltage Feedback Loop ................................ ................................ ........... 83 4.4.2 Current Feedback Loop ................................ ................................ ........... 85 4.5 Experimental Results ................................ ................................ ........................ 89 4.5.1 Microfabricated Air Core Inductor and Transformer ................................ 89 4. 5.2 Hybrid SI SC Converter ................................ ................................ ........... 91 4.5.2.1 Open loop measurement results ................................ .................... 91 4.5.2.2 Close loop measurement results ................................ .................... 93 4.5.3 Hybrid SI Flyback Converter ................................ ................................ ... 95 4.6 Die Photo and Performance Summary ................................ ............................. 97 5 MODELING AND PERFORMANCE ANALYSIS OF HYBRID SI SC STEP UP CONVERTERS ................................ ................................ ................................ ..... 100 5.1 Introduction of Hybrid SI SC Converter ................................ ........................... 100 5.2 Hyb rid SI SC Step Up DC DC Converter ................................ ........................ 102 5.2.1 Generalized Hybrid SI SC Converter Topology ................................ ..... 102 5.2.2 Analysis Model ................................ ................................ ...................... 104 5.3 Model Validation ................................ ................................ ............................. 111

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7 5.4 Experimental Results ................................ ................................ ...................... 115 5.5 Modeling and Anal ysis Conclusions ................................ ................................ 122 6 MINIATURE HIGH VOLTAGE HYBRID STEP UP POWER CONVERTER FOR SMART PIEZOELECTRIC MICROSYSTEMS ................................ ...................... 123 6.1 Introd uction of High Voltage Converters in Microsystems ............................... 123 6.2 High Voltage Hybrid SI SC Step Up Converter ................................ ............... 125 6.2.1 Optimal Design P rocedure ................................ ................................ .... 127 6.3 Hysteretic Controller ................................ ................................ ....................... 132 6.4 Experimental Results ................................ ................................ ...................... 137 6.5 Preliminary Demo of a Smart Piezoelectric Microsystem ................................ 142 7 CONCLUSIONS AND FUTURE WORKS ................................ ............................. 145 7.1 Research Summary an d Contributions ................................ ........................... 145 7.2 Future Works ................................ ................................ ................................ .. 147 APPENDIX A D 2 DERIVATION FOR SI AND HYBRID SI SC CONVERTER IN DCM ............... 149 A.1 Derivation of D 2 for SI Step Up Converter in DCM ................................ ......... 149 A.2 Derivation of D 2 for Hybrid SI SC Converter (N SC Stage) ............................... 150 B SMALL SIGNAL AC ANALYSIS FOR SI BOOST IN CCM ................................ ... 152 C SMALL SIGNAL AC ANALYSIS FOR SI BOOST IN DCM ................................ ... 155 D MSP430L092 CODE FOR SMART PIEZO MICROSYSTEM DEMO .................... 157 LIST OF REFERENCES ................................ ................................ ............................. 164 BIOGRAPHICAL SKETCH ................................ ................................ .......................... 171

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8 LIST OF TABLES Table page 2 1 Summary of CCM DCM characteristics for the SI boost ................................ ..... 28 2 2 Summary of CCM DCM characteristics for the flyback converter ....................... 31 2 3 Summary of steady state characteristics for SC step up converters .................. 37 3 1 Extracted parameters for n and p type SBDs with and without guard rings in 130nm CMOS ................................ ................................ ................................ ..... 62 3 2 Summary of measured DC parameters for fabricated extended drain and stacked MOSFETs ................................ ................................ ............................. 71 4 1 Performance summary and comparison for implemented SI SC and SI flyback converter ................................ ................................ ................................ 98 4 2 Performance Summary and Comparison for t he hybrid SI SC converter ........... 99 5 1 Defined charge and duty cycle vector for the hybrid SI SC step up converter 108 5 2 Summary of steady state model equations for the hybrid SI SC step up converter ................................ ................................ ................................ .......... 110 5 3 Important device parameters used in SPICE simulation for SI converter (N SC =0) ................................ ................................ ................................ ............. 111 5 4 Important device parameters used in SPICE simulation for hybrid SI SC converter (N SC =1) ................................ ................................ ............................. 111 5 5 Important device parameters used in SPICE simulation for hybri d SI SC converter (N SC =4) ................................ ................................ ............................. 111 5 6 Characteristic summary of stacked NMOS switches ................................ ........ 116 5 7 Characteristic summary of schottky bar rier diodes ................................ ........... 116 6 1 Defined charge and duty cycle vector for the hybrid SI SC step up converter 129

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9 LIST OF FIGURES Figure page 1 1 Average power and energy required for mobile microsystems (<10W) [3] ......... 18 1 2 Power and voltage requirements for subsystems under development in MAST [3] ................................ ................................ ................................ ............ 19 1 3 CMOS process scaling trends ................................ ................................ ............ 20 1 4 A hybrid boost / switched capacitor converter and push pull high voltage driv er implemented on 3mil standard PC board for micro robotics ..................... 21 1 5 A bidirectional flyback converter for piezoelectric micro robots .......................... 21 1 6 A SoC implemented in a 0.13 m SiGe CMOS technology for a moving microrobot [13] ................................ ................................ ................................ .... 22 1 7 Envisioned power management platform for autonomous microsystems ........... 23 2 1 An ideal SI boost converter ................................ ................................ ................ 25 2 2 SI boost converter equivalent circuits and waveforms ................................ ........ 26 2 3 SI boost converter equivalent circuit and waveforms in DCM ............................. 27 2 4 An ideal flyback converter ................................ ................................ .................. 29 2 5 Flyback converter e quivalent circuits and waveforms ................................ ......... 30 2 6 Flyback converter equivalent circuit and waveforms in DCM when inductor current is zero ................................ ................................ ................................ ..... 30 2 7 An ideal SC ladder converter ................................ ................................ .............. 32 2 8 Equivalent circuits of the SC ladder converter ................................ .................... 32 2 9 An ideal Dickson charge pump ( n is even) ................................ ......................... 33 2 10 Equivalent circuits of the Dickson charge pump ................................ ................. 34 2 11 An ideal SC Fibonacci converter ( k is odd) ................................ ......................... 35 2 12 Equivalent circuits of the SC Fibonacci converter ( k is odd) ............................... 35 2 13 An ideal SC series parallel converter ................................ ................................ 36 2 14 Equivalent circuits of the SC series parallel converter ................................ ........ 36

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10 2 15 L S D network and its DC and AC averaged model in CCM .............................. 38 2 16 L S D network and its DC and AC averaged model in DCM .............................. 40 2 17 Small signal model of the SI boost converter in CCM ................................ ........ 41 2 18 Small signal model of the SI boost in DCM ................................ ........................ 42 2 19 Voltage mode PWM controller and waveforms ................................ ................... 45 2 20 Current mode PWM control for SI boost ................................ ............................. 46 2 21 Block diagram of PFM control loop for SI boost ................................ .................. 47 3 1 Channel hot carri er effects in the cross section of a saturated nMOS ................ 50 3 2 Typical bias lifetime behavior for minimum length MOS transistors [33] ............ 50 3 3 Electrical field and potential distribution for an abrupt parallel plane P+/N junction ................................ ................................ ................................ ............... 51 3 4 The planar junction created by diffusion through a window in a silicon dioxide mask [36] ................................ ................................ ................................ ............ 53 3 5 Breakdown voltages of cylindrical and spherical junctions normalized to the parallel plane junction [36] ................................ ................................ .................. 54 3 6 The plana r junction with a floating field ring ................................ ........................ 55 3 7 Comparison of the normalized breakdown voltages of cylindrical junctions with and without a single floating field ring [36] ................................ .................. 55 3 8 A planar junction with metal field plate over the edges ................................ ....... 56 3 9 A parasitic PNP transistor in CMOS process ................................ ...................... 56 3 10 Layouts and cross sections of n type and p type SBDs ................................ ..... 58 3 11 Layouts and cross sections of n type and p type SBDs with p + /n + guard rings .. 59 3 12 Measured current densities versus bias voltage for n type and p type SBDs with and without p + /n + guard rings (GR) ................................ ............................. 60 3 13 Extracted slopes an d zero bias current density for n and p type SBDs in 130nm CMOS ................................ ................................ ................................ ..... 61 3 14 Extracted piecewise linear model parameters V D R D for n and p type SBDs in 130nm CMOS ................................ ................................ ................................ 62

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11 3 15 The layout, cross section, symbol and cell parameters of tested thin oxide extended drain MOSFET ................................ ................................ .................... 64 3 16 Measured leakage current densities for tested thin oxide extended drain MOSFET cells with V GS =0V ................................ ................................ ................ 65 3 17 Measured current densities for tested thin oxide extended drain MOSFET cells with V GS =1.2V ................................ ................................ ............................. 65 3 18 The layout, cross section, symbol and cell parameters of tested thick oxide extended drain MOSFET ................................ ................................ .................... 66 3 19 Measured leakage current densities for tested thick oxid e extended drain MOSFET cells with V GS =0V ................................ ................................ ................ 66 3 20 Measured current densities for tested thick oxide extended drain MOSFET cells with V GS =3.3V ................................ ................................ ............................. 67 3 21 On state and off state gate biasing stacked NMOS switches ............................. 68 3 22 The layout and cross section of a switch stacking a thick oxide NMOS on the top of a thin oxide NMOS ................................ ................................ ................... 69 3 23 Measured on state and off state current density of the stacked switch with a 3.3V thick oxide NMOS on the top of a 1.2V thin oxide NMOS .......................... 70 3 24 The layout and cross section of a switch stacking a thick oxide NMOS on top of a thick oxide low V T NMOS in T WELL ................................ .......................... 70 3 25 Measured current density of the stacked switch w ith a 3.3V thick oxide NMOS on the top of a 3.3V thick oxide low V T NMOS ................................ ....... 71 3 26 The silicon limit and performance comparison for developed power devices ..... 72 4 1 Voltage conversion ratio of a SI boost converter considering inductor resistive loss [24] ................................ ................................ ................................ 75 4 2 A hybrid SI/SC converter implemented in 130nm CMOS ................................ ... 76 4 3 Representative waveforms for the hybrid SI/SC converter ................................ 77 4 4 Schematic of a hybrid SI/flyback converter implemented in 130nm CMOS ........ 78 4 5 Representative waveforms for the hybrid SI/flyback converter ........................... 80 4 6 General layout of fabricated inductors and transforme rs ................................ .... 81 4 7 Cross sectional view of the microfabrication process flow ................................ .. 82

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12 4 8 A current mode PWM controller for the hybrid SI/SC co nverter ......................... 83 4 9 Schematic of the error amplifier in the current mode controller .......................... 85 4 10 Demonstration of loop instability in a cu rrent mode controller ............................ 87 4 11 Schematic of the current sensing circuit ................................ ............................. 88 4 12 Schematic of the oscillator (OSC) and current ram p generator .......................... 89 4 13 Microfabricated inductor and measured characteristics [5 6 ] ............................... 89 4 14 Microfabricated transformer and measured characteristics ................................ 90 4 15 Measured waveforms of the hybrid SI/SC converter at 100MHz ........................ 91 4 16 Measured efficiencies with external d riving clocks and a 24nH commercial inductor ................................ ................................ ................................ ............... 92 4 17 Wire bonding for the 14nH microfabricated inductor on a custom PCB for the hybrid SI/SC converter ................................ ................................ ....................... 93 4 18 Measured time domain waveforms of the output voltage and switching node voltage V X when measured with the microfabricated inductor at ~100MHz ........ 93 4 19 Measured ef ficiencies for the close loop hybrid SI/SC converter with microfabricated and commercial inductor respectively ................................ ....... 94 4 20 Transient response for the SI/SC converter using a commercial 43nH induct or ................................ ................................ ................................ ............... 95 4 21 Measured waveforms of the SI/flyback converter using a commercial transformer ................................ ................................ ................................ ......... 96 4 22 Measured efficiencies using ext ernal driving clocks for the hybrid SI/flyback converter ................................ ................................ ................................ ............ 96 4 23 Die photo of the hybrid SI/SC and SI/flyback converter in a 130nm CMOS process ................................ ................................ ................................ ............... 97 5 1 Schematic of the generalized hybrid SI SC step up converter with an N SC stage SC ladder. ................................ ................................ ............................... 102 5 2 Ideal switching voltage and current waveforms in SI stage .............................. 103 5 3 A general circuit model that accounts for non ideal conduction and dynamic switching losses. ................................ ................................ ............................... 105 5 4 Simplified models of passive comp onents and high voltage devices. .............. 106

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13 5 5 Charge flows in the hybrid SI/SC converter ................................ ...................... 107 5 6 Power efficiency obtained from model and SPICE simulation for the three hybrid SI/SC converters ................................ ................................ .................... 112 5 7 Output voltage obtained from model and SPICE simulation for the three hybrid SI/SC converters ................................ ................................ .................... 114 5 8 Schematics of three fabricated hybrid SI SC converters ................................ .. 117 5 9 Die photos of three hybrid converters ................................ ............................... 119 5 10 Measurement and model results of the first hybrid converter (N SC =0) with V IN =1.2V and D 1 =0.8 ................................ ................................ ........................ 120 5 11 Measurement and model results of the second hybrid converter (N SC = 1) with V IN =1.2V and D 1 =0.8 ................................ ................................ ........................ 121 5 12 Measurement and model results for the third hybrid converter (N SC =4) with V IN =1.2V and D 1 =0.8 ................................ ................................ ........................ 121 6 1 Power requirements for various autonomous microsystems ............................ 125 6 2 Implementation detail of the high voltage hybrid SI SC step up converter ....... 127 6 3 A DC circuit model for performance analysis ................................ .................... 129 6 4 Charge flow analysis of the hybrid SI SC step up converter in the two switching phases ................................ ................................ .............................. 129 6 5 Optimal design procedure for the hybrid SI SC step up converter .................... 132 6 6 Hysteretic controller designed for the hybrid SI SC step up converter and its sample waveforms ................................ ................................ ............................ 135 6 7 Conditioning circuit for V BL and V BH and hysteretic comparator with programmable window ................................ ................................ ..................... 136 6 8 Onc hip linear regulator to generate internal power supply for the controller ..... 137 6 9 Testing board for the hybrid SI SC step up converter and zoomed in die photos of the hysteretic controller wit h stacked NMOS switch and the SC multiplier. ................................ ................................ ................................ .......... 138 6 10 Open loop measurement results with D=0.5 and V IN =3V and power loss distribution when f s =25MHz and L=1H ................................ ........................... 139 6 11 Measured close loop timing waveforms when the hybrid SI SC converter is tested with L=1H and V IN =3V ................................ ................................ ......... 141

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14 6 12 Measured timing waveforms of the hybrid ste p up converter for positive load transient response with L=1H and V IN =3V. ................................ ..................... 141 6 13 Measured timing waveforms with a pseudo piezo load of when the reference is modulated ................................ ................................ ...... 142 6 14 A smart piezoelectric microsystem using the hybrid SI SC step up converter and a commercial MSP and m easurement results ................................ ........... 144 A 1 Representative waveforms of the SI step up converter ................................ .... 149 A 2 Simplified circuit model for the hybrid SI/SC step up converter ........................ 151 B 1 The configuration of a SI boost converter and equivalent circuits in subinterval I and II when operating in CCM ................................ ...................... 152 B 2 Small signal circuit model and duty to output transfer function for the SI boost in CCM ................................ ................................ ................................ ............. 153 C 1 Derived small signal circuit model and duty to output transfer function for the SI boost in DCM ................................ ................................ ............................... 155

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15 LIST OF ABBREVIATION S CCM Continuous current mode D Duty cycle of the converter DCM Discontinuous current mode DPWM Digital Pulse width modulator ESR Equivalent series resistance FOM Figure of Merit MA Vs M icro A ir V ehicles PWM Pulse width modulator PFM Pulse frequency modulation RMS Root mean square SBD Schottky Barrier Diode SC Switched Capacitor SI Switched Inductor SoC System on Chip STI Shallow Trench Isolation TDDB Time Dependent Dielectric Brea kdown T S f s Switching time period and frequency UAV U nmanned A erial V ehicles V IN I IN Input voltage and input current of the converter V OUT I OUT Output voltage and output current of the converter VRM Voltage regulator module

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16 Abstract of Dissertati on Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy HIGH VOLTAGE SWITCH ED MODE STEP UP DC DC CONVERTERS IN STANDARD CMOS PROCESS By Lin Xue D ecember 201 3 Chair: Rizwan Bashirullah Major: Electrical and Computer Engineering On chip integration of switched mode step up converters in CMOS can be attractive for portable devices powered from single cell batteries. For instance, some autonomous micr osystems, such as life sized robotic insects that roll, crawl, jump, or fly, require specialized high voltage converters to electrically drive piezoelectric actuators for transforming power into locomotion. In such applications power converter s must meet s tringent mass and volume requirements, a reality that has l ed to increasing interest in on chip high frequency step up converters. This work begins with an overview of basic step up converter topologies and CMOS compatible high voltage tolerant device techn iques. Analysis shows o utput voltage is limited by breakdown of critical devices. Three high voltage tolerant devices and two hybrid topologies are then presented, all in 1.2V CMOS Without adding any extra masking steps, output voltage is exte nded to 10V, 8x larger than the input. Moreover, microfabricated inductors and transformers are also demonstrated with the two converters for comparable performance but much smaller footprint than commercial counterparts.

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17 P erformance of hybrid step up converters ar e further analyzed with a general circuit model proposed which uses a theoretic network methodology to evaluate output impedance and to account for various sources of switching loss prevalent at high operating frequencies and in on chip implementations. Unl ike previous approaches, our s divides dynamic switching loss into output unrelated and related. It then uses two equivalent input and output resistive loads to model them separately. Comparisons with SPICE simulations and experimental results demonstrate t hat the proposed approach is accurate for evaluating power efficiency and output voltage A complete hybrid SI SC step up converter with a 4 stage SC ladder multiplier and an inherently stable hysteretic controller is developed in a 1.2V CMOS process with minimal post process steps for piezoelectric microsystems An optim al design procedure based on theoretic network analysis is also presented Experimental results show the hybrid converter achieves maximum output of 35V at 200 A. Moreover the hybrid conve rter is employed with a commercial microprocessor to form a smart piezoelectric microsystem demo for successfully driving a 25Hz resonant piezo fan.

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18 CHAPTER 1 INTRODUCTION 1.1 Research Background B ug sized autonomous micro robots that crawl, jump, flap or fly have been developing for 20 years [1] [2] to provide a combination of stealth and accessibility to restricted areas, as well as improve portability and enable cooperative group behavior for su perior mission capability in possible tasks involv ing transportation, exploration, surveillance, guidance, inspection, etc Numerous challenge s have been introduced, one of which is to develop a suitable powering system, which at small scales poses a remar kably daunting task. Both a power source (battery) and voltage converter are necessary, and their size and mass are of critical importance to the overall system design. Figure 1 1 Average power and energy required for mobile microsystems (<10W) [3]

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19 Figure 1 1 graphically shows envisioned power and energy densit ies required for the three locomotion modalities, mobile crawling fixed wing flight, and hovering / flapping flight [3] T he targeted approximate power density range is estimated as 10 1000 W/kg by assuming ~25 50% of the power source to the total system weight and 50% of overall power delivery/tra nsmission efficiency. L ithium polymer (LiPo) batteries, fuel cells, and energy harvesters are demonstrated as attractive power source s for targeted microsystems [3] Figure 1 2 Power and voltage requirements for subsystems under development in MAST [3] Figure 1 2 shows the results of an informal survey (conducted by ARL) concerning the anticipated power and voltage needs for t he subsystems under development in the program In general high voltages are required to run piezoelectric [4] or dielectric elastomer [5] actuators for mobility towards the few grams & below range and low voltages from close to typical battery voltages (within 2 3X of a 3.7V LiPo battery) to as low as 0.2V are needed for very efficient sensing and processing approaches.

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20 T herefore b oth step up and step down volta ge converters are required in mm scale microrobots Extensive studies [6] [7] [8] have been done regarding monolithic step down b uck converters since they are intrinsically easier to be integrated in standard CMOS technologies, thus achieving better performance, smaller footprint, and lower cost as the CMOS technology scales down. Conversely, since the supply and breakdown voltage o f the CMOS technology are continuously decreasing as illustrated in Figure 1 3 integration and miniaturization of high voltage step up converters become a much more challenging problem. This dissertation is motivated to investiga te techniques of miniaturizing step up voltage converters. A B Figure 1 3 CMOS process scaling trends. A ) T echnology node B ) S upply voltage 1.2 Recent Progress towards Miniaturization of Step Up Voltage Converters 1.2.1 Hi gh Voltage S tep U p C onverters U sing D iscrete C omponents Several miniature high voltage step up converters have been developed using discrete components for micro robotic applications [4] [9] [10] As shown in Figure 1 4 a hybrid boost / switched capacitor converter and push pull high voltage driver were implemented on 3mil standard PC board utilizing a 22 H inductor, a controller of LT1615 1, 0402 22nF capacitors, high voltage transistors, and 0402 resistors [9] The

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21 converter achieves an output of 250V and efficiency of ~60%, and the total weight of two populated boards is ~854mg. Figure 1 5 shows another example, a bidirectional flyback converter implemented with a custom transformer [10] Although the weight is reduced to ~ 90mg with the same output and efficiency, the converter employs a large number of discrete components and a bulky transformer core, causing its power and energy density insufficient for the stringent power demands of flying micro robots. Figure 1 4 A hybrid boost / switched capacitor converter and push pull high v oltage driver implemented on 3mil standard PC board for micro robotics Figure 1 5 A bidirectional flyback converter for piezoelectric micro robots

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22 Figure 1 6 A SoC implemented in a 0.13 m SiG e CMOS technology for a moving microrobot [13] 1.2.2 Integration of S tep U p V oltage C onverters in CMOS P rocesses Step up voltage converters have been furthe r minimized by fabricating ASIC in high voltage CMOS processes [11] [12] P Basset et al. have implemented a Cockcroft Walton rectifier/quadruplor as well as digital control circuitry for capacitive actuators in a single die with total area of 5mm X 3mm in the 100V Alcatel Mietec I2T100 technology [11] The step up converter switches at 10 kHz and achieves a maximum output voltage of 100V. C.L. Bellew et al. have employed a HV SOI technology and integrated th e power source, solar cells, and buffers into a same die [12] which has be demonstrated successfully powering a jumping microrobot for a height of 1.2cm. R. Casanova et al.

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23 have realized a system on chip (SoC) by embedd ing all power electronics, buffers, ADCs, DACs, control unit, analog transducers, and an oscillator in a 0.13 m SiGe CMOS technology to manage sensors and actuators for a moving microrobot as shown in Figure 1 6 [13] The SoC converters the 1.4V generated by the solar cell to 3.6V to drive the actuators and sensors and takes area of 2.6mm X 2.6mm All above mentioned miniature powering systems require very expensive special CMOS technologies thereby economica lly not practical. Figure 1 7 Envisioned power management platform for autonomous microsystems This dissertation is motivated to investigate low cost techniques to implement miniature switching step up voltage converters in standard CMOS processes. The fine feature sizes of scaled CMOS technologies allow for leveraging high switching frequencies to further reduce the sizes of passives required in voltage converters. Moreover, a system on chip can be realized to include both s tep up and step down voltage converters, RF communication subsystems, and digital processing, all on the same die and helps reduce the total size and weight of an autonomous microrobot. The envisioned SoC platform is illustrated in Figure 1 7 which is projected to integrate CMOS compatible MEMS devices, microprocessors, low and high voltage converters on a single die

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24 1.3 Dissertation Organization The focus of t his dissertation is to investigate high voltage tolerant devices and m iniature switching step up converter s in a standard 0.13m CMOS process for possible applications in microrobots The dissertation is organized to seven chapters. Chapter 1 introduces research background and motivation for miniature switching step up conve rters. Chapter 2 presents a literature review of switching converter topologies and discuss es their possibilities and limitations when integrating in the standard CMOS technology. Chapter 3 describes voltage limits and breakdown mechanisms in CMOS and de velops three custom high voltage tolerant power devices, schottky barrier diodes (SBD) stacked NMOS switches, and extended drain MOS devices without adding any masking steps. The block voltage is extended to be 2 3X larger than the standard thick oxide de vices. Chapter 4 evaluates a hybrid switched inductor (SI) / switched capacitor (SC), and SI/flyback converter implemented in the 0.13m CMOS process and obtains a maximum output of 10V and maximum efficiency of 37% from 1.2V input Chapter 5 proposes a simplified steady state circuit model for hybrid SI SC DC DC step up converters for design oriented analysis. SPICE simulations and experimental results are then employed to demonstrate the proposed models are valid with average errors of <30%. Chapter 6 d escribes a hybrid SI SC step up converter implemented in a 1.2V CMOS process with minimal post process steps. An o ptim al design procedure and a hysteretic controller were also designed and presented. In the end, experimental results are provided to demonst rate that the fabricated converter generates output voltage up to 35V for driving a resonant piezo fan. F inally, conclusions and continuing work are presented in Chapter 7

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25 CHAPTER 2 R EVIEW ON S WITCHING S TEP UP V OLTAGE C ONVERTERS 2.1 Introduction of Swi tching Step Up Converters The key principle in switching voltage converters is energy conservation. A power source firstly stores some energy in an inductor, transformer, or capacitor in one phase, and then the same amount of energy will be transferred fro m those energy reservoir components to the output in the other phase thus allowing for generating a different voltage from the power source Switching step up voltage converters can be divided into three basic groups, switched inductor boost, flyback, and switched capacitor. This chapter will review some basic switching step up converter topologies, discussing their possibilities and limitations for miniaturizing and integrating in standard CMOS processes Moreover some basic control techniques will also be presented 2.2 Basic Switching Step Up Converter Topologies 2.2.1 SI Boost Converter Figure 2 1 An ideal SI boost converter Figure 2 shows an ideal SI boost converter (i.e. V OUT >V IN ). The stead y state waveforms and equivalent circuits are provided in Figure 2 2 When the active switch, N1, is turned on by the gating signal, V X is grounded providing a charging path from t he input power source through the inductor L to th e ground. T he inductor current level

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26 increases in this phase storing energy in L In Figure 2 2 (b), when the active switch N 1 is turned off during s =(1 D)T s the inductor resists its current changes thus charging V X to be equal to V OUT (neglecting diode forward voltage drop) and turning on the diode D1. The inductor transfers its stored energy to the output load. The inductor voltage v ind (t) becomes negative, and i ind (t) decreases continuously as shown in Figure 2 2 (c) A B C Figure 2 2 SI boost converter equivalent circuits and waveforms. A ) N1 is on, B ) N1 is off C ) V olta ge and current waveforms of the inductor L Figure 2 2 (c) shows that the n et change of the inductor current over a switching cycle is zero, lead ing to inductor volt second balance that is, t he net volt seconds applied to an inductor (i.e. the total area) must be zero in steady state. Therefore the output voltage can be derived as: (2 1 ) Figure 2 2 also shows the blocking voltage of the switch N1 and diode D1 when they are off (red color labels) which is e qual to V OUT The breakdown voltage of N1 and D1 must be greater than their blocking voltage.

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27 In Figure 2 2 (c), the inductor current is always positive (i.e. I IN > i ind ) which is called continuous conduction mode (CCM). However, when input current decreases (depending on the output load) and becomes equal to or smaller than the inductor current ripple peak amplitude i ind the inductor current will turn to zero for a short period of time as shown in Figure 2 3 which is then called discontinuous conduction mode (DCM). In DCM, both the switch N1 and diode D1 will turn off, and the equivalent circuits of the SI boost is shown in Figure 2 3 (a). A B Figure 2 3 SI boost converter equivalent circuit and waveforms in DCM. A ) I nductor current is zero, B ) V oltage and current waveforms of the inductor L The boundary between the CCM and DCM for the SI boost can be derived by calculating the average input current (I IN ) and the inductor current ripple peak amplitude ( i ind ). When the inductor current ripple is greater than the average input current, the converter is in DCM. Large ac conduction loss will be seen in DCM. But large output voltage can also be achieved in DCM. A dimensionless parameter K is defined as K=2L/R L T s and the mode boundary is given by for CCM (2 2 a) for DCM (2 2b)

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28 Here, R L is the load resistance, D is the duty cycle, and T s is the switching period. In DCM, the output voltage is larger than that in CCM, and the resulting value is then derived using the inducto r volt second balance as when K < K crit (2 3 ) The above results are summarized in Table 2 1 Table 2 1 S ummary of CCM DCM charact eristics for the SI boost SI b oost Condition K=2L/R L T S K crit =D(1 D) 2 V OUT Voltage stress for N1 Voltage stress for D1 CCM K>K crit V OUT V OUT DCM K < K crit V OUT V OUT 2. 2.2 Flyback Converter A flyback conve rter is developed from the buck boost topology to realize high voltage conversion ratio by utilizing large turns ratio transformers. Figure 2 4 shows an ideal flyback converter with a transformer equivalent circuit model. The magn etizing inductance L M functions as an energy storage element in the same manner as the inductor in boost or buck boost. During subinterval 1, while the transistor N1 conducts, the converter circuit reduces to Figure 2 5 (a). The in ductor voltage v ind (t) is positive, and the inductor current i ind (t) increases, as shown in Figure 2 5 (c). In this phase, the diode D1 is reverse biased, and the load current is provided by the load capacitor C L In subinterval 2, the transistor N1 is off, and the converter circuit is simplified as Figure 2 5 (b). The inductor voltage v ind (t) is negative, and the inductor current i ind (t) is decreasing.

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29 Energy stored in the magnetizing inductor is transferre d to the output. From the inductor volt second balance, the output voltage can be calculated as: (2 4 ) Figure 2 4 An ideal flyb ack converter Figure 2 5 only shows the blocking voltage when the transistor N1 and diode D1 are off. The voltage stress of D1 is V OUT +nV IN which is much larger than the voltage stress of N1. The expression of the output volta ge in equation (2 4) only applies to CCM. When the flyback converter works in DCM, the inductor current might decrease to zero, as shown in Figure 2 6 In subinterval 1, the inductor current can be written as: (2 5 a) (2 5b)

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30 In subinterval 2, the inductor current is derived as: (2 6 a) (2 6b) A C B Figure 2 5 Flyback converter equivalent circuits and waveforms. A ) N1 is on, B) N1 is o ff C ) voltage and current waveforms of the magnetizing inductor L M A B Figure 2 6 Flyback converter equivalent circuit and waveforms in DCM when inductor current is zero. A ) Equivalent circuits, B) V oltage and current wavefor ms of the magnetizing inductor

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31 The output current can be derived as: (2 7 ) From equation (2 7), the duty cycle D 2 can be derived as: (2 8 ) Here we define K=2L M /R L T s and K crit =(1 D) 2 /n 2 and we can know the output voltage is (2 9 ) The CCM DCM characteristics of the flyback converter are summarized in Table 2 2 Comparing to the SI boost, the flyback can realize a larger output voltage with the same duty cycle by using a transformer, and the voltage stress o f the switch N1 is decreased if the output voltage is the same. The drawback of the flyback converter is the voltage stress of D1 is enlarged. Table 2 2 Summary of CCM DCM characteristics for the flyback converter F lyback Con dition K=2L M /R L T S K crit = (1 D) 2 /n 2 V OUT Voltage stress for N1 Voltage stress for D1 CCM K>K crit V IN + V OUT /n n V IN + V OUT DCM K
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32 2.2.3.1 Ladder ( C ock c r o ft W alton) Figure 2 7 An ideal SC ladder converter A B Figure 2 8 Equivalent circuits of the SC ladder converter A ) S 1,1 S 3,1 S 2n 1,1 are on, S 2 2 S 4 2 2n 2 are off B ) S 1,1 S 3,1 2n 1,1 are off, S 2 2 S 4 2 2n 2 are on Figure 2 7 is an ideal two phase SC ladder comprised of (n 2) holding capacitors C 2 C 4 (2n 4) (n 1) flying capacitors C 1 C 3 (2n 3 ) and (2n) power switches S 1,1 S 2,2 2n,2 In phase I, switches with even subscript numbers conduct, and the input power source charges flying capacitors. In phase II, the flying capacitors supply charges

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33 to the output load. The equiv alent circuits of the SC ladder in phase I and II are described in Figure 2 8 Ideally, voltage across each capacitor is the same as V IN therefore the output voltage is derived as (2 10 ) Moreover, blocking voltages over non conducting switches are also shown in Figure 2 8 which are all equal to V IN 2.2.3.2 Dickson c harge p ump Figure 2 9 shows an ideal Dickson charge pump, which consists of (n 1) flying capacitors C 1 (n 1) and (n+4) switches S 1,1 n+4 2 The equivalent circuits of the Dickson charge pump is illustrated in Figure 2 10 where voltages across capacitors and non conducting switches in steady state are analyzed and labeled. Assuming n is even, the output voltage can derived as (2 11 ) And the maximum voltage stress for the capacitors and switches are 2V IN When n=2, the Dickson charge pump simplifies as a voltage doubler, which is the same as the SC ladder with n=2. Voltage doubler is the most commonly used charge pump in circuit community. Figure 2 9 An ideal Dickson charge pump ( n is even)

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34 A B Figure 2 10 Equivalent circuits of the Dickson charge pump A ) S 1,1 S 3,1 n +3 ,1 are on, S 2 2 S 4 2 n+4 2 are off B ) S 1,1 S 3,1 S n +3 ,1 are off, S 2 2 S 4 2 n+4 2 are on 2.2.3.3 Fibonacci c onverter Figure 2 11 shows an ideal k stage SC Fibonacci converter and Figure 2 12 shows its equivalent circuits The input power source fi rstly charges C 1 to V IN in phase I, and then in next phase, the power source in series with C 1 charges C 2 to 2V IN In the next switching cycle, the power source in series with C 1 and C 2 charges C 3 to 3V IN Therefore voltage over capacitor C k will be a Fibo nacci number F k +1 which is defined as: (2 12 ) The output voltage is then derived as

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35 (2 13 ) Figure 2 12 also illustrates blocking voltages of non conducting switches and the maximum voltage stress for switches is F k+1 V IN Fibonacci converter can real ize high step up ratio with few components, but large voltage stress is a drawback Fibonacci convert er is more suitable for implementation using high voltage discrete components. Figure 2 11 An ideal SC Fibonacci converter ( k is odd) A B Figure 2 12 Equivalent circuits of the SC Fibonacci con verter ( k is odd) A) S i,1 is on, B) S i,2

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36 2.2.3.4 Series p arallel c onverter Figure 2 13 An ideal SC series parallel converter A B Figure 2 14 Equivalent circuits of the SC seri es parallel converter A) S i,1 is on, B) S i,2 is Figure 2 13 shows an ideal SC series parallel converter including (n 1) capacitors and (3n 2) switches. The equivalent circuits of the series parallel converter in two phases are illustrated in Figure 2 14 The input power source firstly charges all capacitors in parallel, and then the capacitors are connected in series with the input and provide charges to the output. Therefore the output volt age is derived as (2 14 )

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37 Figure 2 14 also shows blocking voltages across non conducting switches, and the maximum voltage stress is ( n 1)V IN Power switches close to V OUT have to block large voltages. 2.2.3.5 Summary of SC c onverters Table 2 3 summarizes steady state characteristics of SC step up converters. For the same voltage conversion ratio, the ladder c onverter requires the maximum number of switches and capacitors, while the Fibonacci converter needs the least number of devices. The ladder and Dickson charge pump, voltage stresses are approximately equally distributed across switches and diodes, which m akes these two topologies more suitable for integration in deep submicron CMOS technologies. For the series parallel converter, voltage stress of capacitors is small but voltage stress of switches is the biggest. The Fibonacci converter has large voltage s tress for both capacitors and switches, which makes it the most difficult topology for integration. Table 2 3 Summary of stead y state characteristics for SC step up converters V OUT Voltage s tress over s witches Voltage s tress over c apacitors Ladder nV IN S 1,1 S 2n,2 C 1 C 2n 3 V IN V IN Dickson nV IN S 1,1 S 5,1 S 6,2 S n+4,2 C 1 C 2 C (n 1) V IN 2V IN V IN 2V IN Fibonacci F k+2 V IN S 1,1 S 3,1 S 4,2 S 5,1 S 6,2 S 3k 2 S 3k 1 S 3k S 3k+1 C 1 C 2 C 3 C k V IN 2V IN V IN F k+1 V IN F k V IN V IN 2V IN 3V IN F k+1 V IN Series Parallel nV IN S 1,1 S 3,1 S 4,1 S 5,2 S 3n 4 ,1 S 3n 3,1 S 3n 2,1 C 1 C (n 1) V IN 2V IN V IN V IN (n 1)V IN V IN 2.3 Averaged Switch ing Network 2.3.1 Average d L S D Network in CCM Various approaches have been proposed to facilitate a nalyzing switching DC DC converters [20] [23] such as state space averaging [20] averaged switching network

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3 8 [22] The averaged switching n etwork approach is physically more meaningful to circuit designers and will be introduced in this section. Figure 2 15 a shows the ideal L S D switching network that is common in switched inductor DC DC converters (buck, boost, buc k boost). The switch and diode in this network will be turned on and off alternatively, resulting in pulsating currents and voltages and introduc ing difficulties in DC and AC analys e s However, after these pulsating currents and voltages are averaged and l inearized over switching periods, they are converted to traditional continuous analog signals and can be analyzed easily. A B C D Figure 2 15 L S D network and its DC and AC averaged model in CCM. A ) Ideal L S D network that i s common in SI DC DC converters B ) I ts physical implementation example C ) DC and D ) AC averaged circuit for the ideal L S D switching network in CCM Assuming switches and diodes are ideal, the following large signal relationships can be obtained. (2 15 )

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39 Assuming small perturbations and ignoring higher order terms, the above equation can be linearized as follows. (2 16 ) Therefore, from equation 2 16, the ideal L S D switching network is identical to the DC averaged circuit shown in Figure 2 15 c and AC averaged circuit in Figure 2 15 d. However, the AC circuit is only accurate at low frequencies. 2.3.2 Average d L S D Network in DCM When the L S D switching network operates in DCM, it can be averaged in the same way that is done in section 2.3.1. However, since the duty cycle when the dio de is on is unknown, resulted averaged circuit is much more complicated. The following derivation was firstly discussed in [22] The peak inductor current is calculated as (2 17 ) The averaged switch and diode current can then be derived as (2 18 ) Voltage at the intermediate node X is (2 19 ) Therefore, the averaged voltages and are represented as

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40 (2 20 ) From 2 37, v oltages v DL and v LS can be represented using the averaged voltages and as follows (2 21 ) After applying perturbation and linearization, we have (2 22 ) A B C D Figure 2 16 L S D network and its DC and AC averaged model in DCM. A ) Ideal L S D network B ) I ts example voltage and current waveforms in DCM C ) DC and D ) AC averaged circuit f or the ideal L S D switching network in DCM

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41 From 2 19, DC and AC averaged circuits are then derived and illustrated in Figure 2 16 c and d. Parameters that are used in Figure 2 16 are defined as below. (2 23 ) (2 24 ) (2 25 ) (2 26 ) (2 27 ) 2.3. 3 Small Signal Analysis of SI Boost Converter in CCM The averaged switching network is applied to the SI boost converter, resulting in the small signal model as shown in Figure 2 17 From it, the duty to output transfer function c an be derived as (2 28 ) Figure 2 17 Small signal model of the SI boost converter in CCM.

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42 The transfer function contains a RHP zero and two LHP poles, which are represent ed as (2 29 ) (2 30 ) where (2 31 ) (2 32 ) 2.3.4 Small Signal Analysis of SI Boost Converter in DCM Figure 2 18 Small signal model o f the SI boost in DCM Applying the derived averaged switching network to the SI boost in DCM, the small signal model is obtained and described in Figure 2 18 From it, the duty to output transfer function is derived as

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43 (2 33 ) The duty to output transfer function contains a possible RHP zero and two LHP poles, which are represented as (2 34 ) (2 35 ) where (2 36 ) (2 37 ) The averaged L S D model is derived based on that the small signal ac voltage across the inductor is zero, meaning the model is only accurate in low frequencies. Therefore, the a bove transfer function can be simplified as follows (2 38 ) which contains a single pole. It means that the boost in DCM is easier to be stabilized that in CCM. More accu rate results [24] shows that the SI boost in DCM contains a low frequency dominant pole, a high frequency second pole, and a high frequency RHP zero. However, the second pole and RHP zero are higher than the switching frequency in general and can be neglected in stability analysis. (2 39 )

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44 (2 40 ) (2 41 ) Here M is the voltage conversion ratio M=V OUT /V IN 2.4 Control Scheme of DC DC Converters 2. 4 .1 Voltage Mode Pulse Width Modulation ( PWM ) Voltage mode PWM is the first use d approach for switching regulator design, and its configuration for a SI boost is shown in Figure 2 19 The control loop senses the output voltage V OUT through feedback resistors R 1 and R 2 and subtracts the feedback voltage V FB from a reference voltage V REF to establish an error signal (V ERR ). This error signal is then compared to a fixed frequency sawtooth waveform (V SAW ), resulting in a PWM clock to drive the power switch N 1 and generate a dc output V OUT This negative feedback loop regulates the feedback voltage V FB to be the same as V REF As shown in Figure 2 15 b, duty cycle of the driving clock from PWM generator can be calculated as (2 42 ) Voltage mode PWM control is easy to design and analyze, and has been used in industry for many years. The modulation is stable and provides a good noise margin. The feedback loop has low output impedance and allows better cross modul ation for multiple outputs. The drawback of this control scheme is its slow loop response. Moreover, complicated compensation circuit is often necessary for loop stability, which makes the loop dynamics even slower [20] When e mploying voltage mode PWM in boost converters, right half plane zero may further reduce the loop band width, causing

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45 transient response of boost converters very and very slow. Complicated compensation network is required especially for boost converters. A B Figure 2 19 Voltage mode PWM controller and waveforms. A ) B lock diagram B ) representative waveforms 2. 4 .2 Current Mode PWM Current mode PWM was proposed in history to alleviate the drawbacks of voltage mode PWM. As seen in the diagram of current mode PWM in Figu re 2 20 besides the voltage feedback loop, another loop which senses inductor current is added. An error voltage V ERR from the voltage feedback loop is compa red to the inductor current. As shown in Figu re 2 20 b, whenever the peak inductor current hits the value determined by

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46 V ERR pulses are created at R, turn off the switch N 1 and transfer energy from the inductor to the output. Duty cycle of the driving clock is modulated by both the error voltage and the inductor current, and t he loop frequency is determined by a fixed frequency pulse V pulse which set s the S R latch (PWM generator) constantly A B Figu re 2 20 Current mode PWM control for SI boost A ) B lock diagram B ) R epresentative waveforms Improvements in loop dynamics of the voltage mode PWM is impressive. The inductor current rises with a slope determined by V IN and V O UT the current feedback

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47 loop will respond immediately to line and load voltage changes. The error amplifier is used to modulate the output current rather than voltage, the effect of the inductor is minimized and the filter offers only a single pole [26] Therefore simpler compensation and high gain bandwidth can be achieved compared to voltage mode PWM. The drawback of current mode PWM is that an extra ramp V SAW is required for slope compensation as shown in Figu re 2 20 [26] 2. 4 3 Pulse Frequency Modulation ( PFM ) Figure 2 21 B lock diagram of PFM control loop for SI boost A v oltage or current mode PWM control ler employs a fixed switching frequ enc y and will cause large switching power loss and yield a low efficiency at light load To maintain good efficiencies over a wide load range, PFM control is usually used. Figure 2 21 shows block diagram of a simple PFM control l oop. The feedback voltage V FB is compared to the reference voltage V REF and the output EN determines the number of pulses passed to drive the switch N1. When ever V FB is greater than V REF EN turns to low and stops clocking the drivers. In general, some hyt eresis is designed with the comparator to provide better noise margin s

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48 PFM control is very simple to design, and i mproves efficiency at light load. But its loop response is very slow. Moreover, the constant duty cycle of V pulse limits the maximum output power, and is not usually utilized in heavy load. PFM is mo re commonly used for SC converters.

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49 CHAPTER 3 C USTOM H IGH V OLTAGE P OWER D EVICES IN S TANDARD C MOS P ROCESS 3.1 Introduction of High Voltage Devices When integrating switching step up voltage conve rters in a standard CMOS process, high voltage stresses will be seen across power switches and rectifiers and then induce v arious undesirable effects such as channel hot carrier effects, punch through breakdown, avalanche breakdown, gate oxide breakdown. T hese effects will cause degrad ation of the device characteristics or even destruct ion and therefore i nvestigati on of these effects is necessary to determine the voltage limit for the integrated converter s This chapter will first introduce the mechanisms o f the undesirable effects, and then present developed power rectifiers and switches in the standard 130nm CMOS process and investigate their voltage limits 3.2 Voltage Limit Effect s in Standard CMOS Process 3.2.1 Channel Hot Carrier Effects In MOSFETs, a s minority carrier s flow from the source to the drain along the channel they acquire a continuous increase in kinetic energy and become energetic in the high field region of the drain junction. These energetic carriers are known as channel hot carrier s At certain circumstances, the carriers may gain enough energy to cause impact ionization or even enter into the gate oxide performance Figure 3 1 illustrates the channel hot carrier effects in the cro ss section of a saturated NMOS [1] When impact ionization occurs, secondary electron hole pairs are generated and constitute the drain source current I ds and the substrate current I sub The substrate current will create a loca l ohmic voltage drop in t he substrate and forward bias the substrate source junction resulting in a snapback breakdown [1] When hot

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50 carriers have too much energy to overcome the energy barrier of the Si SiO 2 interface, they in ject into the gate oxide get trapped in the oxide or form the gate current I g The trapped carriers will shift the device thres hold, damage the gate oxide, reduce the lifetime of the transistors [30] [31] which is also called time dependent dielectric breakdown (TDDB) [32] Figure 3 1 Channel hot carrier effects in the cross section of a saturated nMOS Figure 3 2 Typical bias lifetime behavior for minimum length MOS transistors [33] Figure 3 2 is a typical hot carrier based lifetime versus biasing plot for a minimum length transistor [33] V dd,nom in the figure is the nominal supply voltage of the process.

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51 Longer transistors have larger lifetime. As an extremely crude rule of thumb, the ratio of gate voltage to oxide thickness must be kept under approximately 0. 7 V/nm to sat isfy the lifetime requirement of 10 year s at 125 C [34] 3.2.2 Gate Oxide Breakdown As CMOS technology node is developing smaller and smaller, gate oxides are getting thinner and secondary carriers will be more easily collecte d by the gate electrode rather than stay trapped in the oxide. TDDB is less severe and the gate voltage is primarily limited by gate oxide breakdown, which occurs for gate fields exceeding about 1V/nm, as another crude rule of thumb [3 4] Figure 3 3 Electrical field and potential distribution for an abrupt parallel plane P+/N junction 3.2.3 Avalanche Breakdown Maximum allowable voltage across a junction is mainly dete rmined by avalanche breakdown mechanism In a reverse biased junction, the high electric field sweeps out any electron or hol e in the depletion region. When the energy of the electron or hole is

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52 high enough to cause the impact ionization process reach an i nfinite rate, current increases rapidly and avalanche breakdown occurs. Take an abrupt one dimensional P+/N junction diode as an example. Figure 3 3 illustrates its electric field and potential distribution when reverse biased. From W D ) is derived as [36] : (3 1) wh ere V a is the applied reverse bias, is the dielectric constant for the semiconductor, q is the electron charge, and N D is the donor concentration in the uniformly doped N region. The maximum electric field at the junction is then obtained: (3 2) As the applied bias voltage increases, the maximum electric field approaches values at which significant impact ionization begins to occur. [36] analytical solutions for the breakdown voltage and the corresponding maximum depletion layer width can be derived for silicon: (3 3) and (3 4) 3.2.3.1 Planar j unction e dge e ffects In modern CMOS process, a planar junction is formed by the diffusion of impurities through a window in a silicon dioxide mask, as shown in Figure 3 4 As dopants migrate

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53 ver tically to produce a parallel plane junction, lateral diffusion creates cylindrical shaped junctions at the edges and spherical junctions at the corners of the diffusion window These edge curvatures reduce the breakdown voltage of the planar junction [37] Figure 3 4 The planar junction created by diffusion through a window in a silicon dioxide mask [36] Edge effects are very important in CMOS process. As shown in Figure 3 4 assume the junction depth is r J Analysis of the breakdown voltage BV CYL for the cylindrical junction and the breakdown voltage BV SP for the spherical junction give s the normalized results to the breakdown voltage BV PP for the parallel plane junction as follows [36] : (3 5) and (3 6) The normalized breakdown voltages predicted by equations (3 5) and (3 6 ) are plotted in Figure 3 5 as a function of the normalized radius of curvature [36] As seen in

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54 Figure 3 5 t he junction breakdown voltages increase with the radius of curvature. However, in reality, it is impractical to obtain a normalized radius of curvature of more than 0.4, making it difficult to raise the normalized breakdown voltage for the cylindrical junction to above 50% of the parallel plane case [36] Figure 3 5 Breakdown voltages of cylindrical and spherical junctions normalized to the parallel plane junction [36] 3.2.3.2 Layout i mprovement t echniques To improv e the breakdown voltage of planar junctions floating field rings can be employed to surround the junction window without additional process steps. The top view and the cross section of this technique are illustrated in F igure 3 6 Floating field rings must be placed within the depletion region of the main junction with an optimal spacing to perturb the electric field and provide an improvement in the breakdown voltage. Analysis shows the breakdown voltage of a cylindrical junctio n with a n optimal floating field ring BV FFR is obtained as [36] : (3 7)

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55 Analytical solutions calculated from equation s (3 5) and (3 7) are plotted in Figure 3 7 and the norm alized breakdown voltage of the planar junction with a floating field ring is 2X larger than that of the cylindrical junction. The breakdown voltage can even be further improved by using multiple floating field rings [36] F igure 3 6 The planar junction with a floating field ring Figure 3 7 Comparison of the normalized breakdown voltage s of cylindrical junctions with and without a single floating field ring [36]

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56 Figure 3 8 A planar junction with metal field plate over the edges Another layout technique to minimize the edge effects is by using field plate [36] which is illustr ated in Figure 3 8 for a P+/N diode. The contact metal for P+ region is extended to form a field plate at the edges. The negative potential in the metal field plate pushes extends the depletion region and the breakdown voltage of the planar junction is increased. Furthermore, floating field rings and field plates can be utilized together to achieve highest breakdown voltage s. Figure 3 9 A parasitic PNP transistor in CMOS process 3.2. 3.3 Open b ase t r ansistor b reakdown In modern CMOS processes, especially when multiple wells exist, power devices may contain parasitic back to back junctions. The breakdown voltage for the parasitic structure is further reduced because the impact ionization can be amplifi ed by the gain of the bipolar transistor, which is called open base transistor breakdown [38] Figure 3 9 shows a parasitic PNP structure in CMOS process with junctions J1 and J2. W N denotes the depth of the NWELL minus the depth of the P+ region, and W D

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57 is the width of the depletion region in NWELL. When W N is much big ger than the maximum depletion width when avalanche breakdown happens at J2, the breakdown voltage of this PNP structure is the same as the planar junction J2. However, if the depletion region reaches P+ region before avalanche breakdown happens, holes from P+ region enter the depletion region and are amplified to generate a big current flow, which is called reach through breakdown. The o pen base transistor breakdown voltage can be approximated by t he reach though breakdown voltage BV RT which is derived as (3 8) 3.2.4 Electromigration As current flows through a conductor, me tal atoms will be transported from one point to another creating voids and hillocks or extrusions in the conductor. This mechanism is called electromigration. Electromigration might induce short or open circuit if voids and extrusions are big enough. To pr event this mechanism, a width of 1 m per 1mA DC current for metal lines is used as a rule of thumb [45] 3. 3 Schottky Barrier Diodes Schottky barrier diodes (SBDs) are commonly utilized as rectifiers in switching power convert ers because of their high cut off frequency and low forward voltage drop [39] Silicon SBDs can be fabricat ed in standard CMOS process without extra process steps [41] thus leading to lower cost and monolithic integration SBDs with cut off frequency over 1THz have been demonstrated in standard 130nm CMOS process [42] 3.3.1 Schottky Barrier Contact in CMOS Schottky barrier contact is not generally available in standard C MOS process. However, salicidation, which is primarily used to improve the conductivity of poly and

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58 n + /p + regions, can be employed to form Schottky barrier contacts by blocking n + /p + impla n tation in the selected active regions (NWELL or PWELL). In 130nm CM OS process, Co is generally used as the transition layer for salicidation, therefore CoSi 2 Si schottky contacts can be formed. Figure 3 10 shows the layouts and cross sections of n type and p type SBDs that were fabricated in 130n m CMOS process. Shallow trench isolation (STI) around the schottky contacts are used to separate the two terminals and reduce the leakage currents. A B Figure 3 10 Layouts and cross sections of n type and p type SBDs A) SBD o f n type, B) SBD of p type 3.3.2 Guard Rings for SBDs At the perimeter of the schottky contacts, large electric fields will be induced due to small barrier height and the edge effects, and hence large reverse leakage currents exist. Diffused guard rings c an be employed to further reduce the reverse leakage currents and therefore the breakdown voltage can be improved. Figure 3 11 shows the

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59 layouts and corresponding cross sections of n type and p type SBDs with p + /n + guard rings tha t were fabricated in 130nm CMOS process. The presence of p+/n+ guard rings avoids formation of spherical junctions at the corners of the diodes and creates parasitic parallel P N junctions. To preserve the fast switching behavior, the SBDs with guard rings should not be biased above 0.6V so that the parasitic parallel P N junctions are not turned on and only majority carriers are injected into the drift regions. A B Figure 3 11 Layouts and cross sections of n type and p type SB Ds with p + /n + guard rings A) SBD of n type with p+ guard ring, B) SBD of p type with n+ guard ring 3.3.3 Measurement Results and Parameter E xtraction N type and p type SBD test kits with and without p + /n + guard rings have been fabricated in the standard 130nm CMOS process. Measured current densities versus bias voltage for them are plotted in Figure 3 12 As shown in Figure 3 12 measured reverse bias voltages at the reverse current density of 1A/cm 2 are 8.5V for n type and 0.1V for p type SBDs when no guard rings are presence. In contrast, the reverse bias

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60 voltages are improved to be 11.5V for n type and 12V for p type SBDs when guard rings are used. From the thermionic emission model, the current densi ty ( J ) for SBD with moderately doped semiconductor and forward bias voltage V F >3kT/q is [42] (3 9) where J is the current density, A* is the eff ective Richardson constant for metal semiconductor interface, T is the absolute temperature, q is the electron charge, k is the Boltzmann constant, BI is the barrier height, and is the ideality factor. From equation (3 9), the barrier height BI can be extracted as, (3 10) where J s is the extrapolated saturation current density at 0V bias. Figure 3 12 Measured current densities versus bias voltage for n type and p type SBDs with and without p + /n + guard rings (GR)

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61 Figure 3 13 shows extracted slopes and extrapolated current densities at 0V bias. From the extracted slopes, the ideality factors can be calculated as 1.05 and 1.75 for n type SBDs w/ o and w/ guard ring, 1.44 and 1.75 for p type SBDs w/ o and w/ guard ring. F urthermore, from equation (3 10) and the extrapolated current densities at 0V in Figure 3 13 the barrier heights are also derived as 608 mV and 659mV for n type SBDs w/ o and w/ guard ring, 393mV and 566mv for p type SBDs w/ o and w/ guard ring. Here, the effective Richardson constants used are assumed to be 1.12 A/ m 2 K 2 for electrons and 0.32 A/ m 2 K 2 for holes [43] Figure 3 14 shows extracted the specific on resistance R D for fabricated SBDs. Figure 3 13 Extracted slopes and zero bias current density for n and p type SBDs in 130nm CMOS Small signal capacitances of SBDs were also measured using Agilent network analyzer, from which cutoff frequency of the SBDs were calculated. All important DC and AC parameters for measured SBDs are summarized in Table 3 1 Genera lly, n type devices have higher cut off frequency than their p type counterparts due to electrons

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62 have large mobility than holes. Moreover, guard rings add parasitic capacitance to the devices, so that cut off frequency is lower. A commercial SBD from Diod es Inc. is also shown in Table 3 1 for comparison. Figure 3 14 Extracted piecewise linear model parameters V D R D for n and p type SBDs in 130nm CMOS Table 3 1 E xtract ed parameters for n and p type SBDs with and without guard rings in 130nm CMOS BV BI V D A R D f T Unit ( V @ 1A/cm 2 ) (mV) (mV@1A/cm 2 ) ( cm 2 ) (GHz) n type SBD w/o guard ring 8.5 1.05 608 200 3.2e 5 26 p type SBD w/o guard ring 0.1 1.44 393 3 0 5. 2e 5 15 n type SBD w/ guard ring 11.5 1.75 659 280 5.1e 5 12 p type SBD w/ guard ring 12 .0 1.75 566 22 0 6.7e 5 8 ZLLS410 [44] 10 .0 (@200 A) 285 (@10 m A) 6* Estimated from datasheet 3. 4 Power Switches In 130nm CM OS process, 1.2V thin oxide ( 3 nm ) and 3.3V thick oxide MOSFETs ( 7 3 nm ) are genuinely available and can be used as power switches. However,

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63 integration of step up voltage converters demands power switches with higher breakdown voltage. Lateral extended drai n MOSFETs and stacked MOSFETs have been investigated and demonstrated as two good candidates [29] [45] a nd m ore importantly, they can be integrated in standard CMOS process without extra masking ste ps thus can keep integration of low cost. This section investigates the layout techniques of these two devices and then presents measurement results in 130nm CMOS. 3. 4 .1 Extended Drain MOSFET Extended drain MOSFET is an asymmetric device which is realized by replacing the normal highly doped drain region with a lightly doped either pwell or nwell standard layer. Therefore the extended drain allows a large depletion region and reduced electric field across the gate oxide, which yield s a high breakdown volta ge while maintaining a low on resistance Extended drain MOSFETs can be realized with only standard mask layers Figure 3 15 illustrates the layout and cross section of a thin oxide extended drain NMOS A lightly dope drift regio n (nwell) is placed underneath the gate oxide with an overlap length of X The physical gate length is annotated as L STI is used between the gate and the drain contact and its length is denoted as D Testing cells with various dimensions of L, X, D are f abricated in 130nm and the variations are listed in Figure 3 15 Figure 3 16 shows measured leakage current densities ( J DS ) for the fabricated thin oxide EDMOS cells when V GS =0 Firstly, Figure 3 16 tells us that the leakage current density decreases with the increased gate length Secondly, the breakdown voltages for all testing cells are very c lose to each other, which is V BV =9.83V at the

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64 current density of 1A/cm 2 Figure 3 17 shows measured on state current densities for the thin oxide testing cells when V GS =1.2V from which the on resistances are obtained as 2.2e 4 cm 2 1.4e 4 cm 2 2.6e 4 cm 2 for EDMOS_1, EDMOS_2, EDMOS_3 respectively. Figure 3 15 The layou t, cross section, symbol and cell parameters of tested thin oxide extended drain MOSFET In contrast to the thin oxide EDMOSs in Figure 3 15 extend drain MOSFETs with thick gate oxide (7.3nm) are also designed and fabricated with the same dimensions of L, X, D Figure 3 18 shows the corresponding layout, cross section, symbol a nd the variations of the dimensions. Figure 3 19 plots measured leakage current densities for the testing cells. Compared to the thin oxide EDMOSs, smaller leakage current densities are observed for the thick oxide EDMOSs. Measure d breakdown voltages for the thick oxide EDMOSs are slightly higher, V BV =9.87V at the current density of 1A/cm 2 Figure 3 20 shows measured on state current densities for the thick oxide EDMOSs

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65 and the corresponding on resistances are extracted as 1.3e 4 cm 2 1.6e 4 cm 2 3.0e 4 cm 2 for EDMOS_4, EDMOS_5, EDMOS_6 respectively. Figure 3 16 Measured leakage current densities for tested thin oxide extended drain MOSFET cells with V GS =0V Figure 3 17 Measured current densities for tested thin oxide extended drain MOSFET cells with V GS = 1.2 V

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66 Figure 3 18 The layout, cross section, symbol and cell parameters of tested thick oxide extended drain MOSFET Figure 3 19 Measured leakage current densities for tested thick oxide extended drain MOSFET cells with V GS =0V

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67 Figure 3 20 Measured current densities for tested thick oxide extended drain MOSFET cells with V GS = 3.3V 3. 4 .2 Stacked MOS FET Stacked MOSFET, which means that the source of one transistor is connected to the drain of another, can reliably sustain a multiple of the nominal supply voltage by distributing the voltage stress across the chain of the MOSFETs Gate biasing is extremely important to maintain the lifetime of these devices. Figure 3 21 illustrates proper gate biasing when two and n NMOS are stacking. When the stacked switch in on, the drain and the source terminals are a l l connected to ground, and all the gates should be biased at V DD ; when the stacked switch is off, each NMOS blocks one V DD therefore the gate biases must increase from 0 for the lowermost NMOS to (n 1)VDD for the uppermost NMOS. Moreover, w hen PMOSs are stacking, the gates should be biased similar ly. In 130nm CMOS, two stacking structures have been investigated. The first structure consists of a 3.3V thick oxide NMOS stacking on the top of a 1.2V thin oxide

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68 NMOS and Figure 3 22 shows its representative layout and cross section. With a fixed bias for the top device, this composite switch only requires one single driving clock, thereby providing a better figure of merit in terms of gate capacitance per drain current. This structure also eliminates level conversion circuits and reduces the time delay in the control loop, thereby yielding faster transient responses. Minimum lengths of 340nm for thick oxide devices and 120nm for thin oxide devices are used to save area. The widths are chosen as 13 m, 14 m respectively and multiple fingers can be used in parallel to reduce its on resistance. A B Figure 3 21 On state and off state gate biasing stacked NMOS switches. A ) T wo stacked NMOS B ) S tacked NMOS with n >2 The bias voltage for the top NMOS has to be sel ected carefully to ensure 10 year life time at 125 C which indicates that the electrical field across the gate oxide must be less than 0.7 V/nm T herefore the gate oxide thickness of 2.5nm and 7nm for the bottom and the top NMOS results in the maximum gate drain voltage as ~1 7 V and ~ 5 V respectively. Considering the threshold voltage of 0.63V and the body effect for the top NMOS, the bias voltage is chosen as 2.5V Figure 3 23 plot s measured current

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69 densities when the stacked switch is on and off. As shown in Figure 3 23 the measured off state breakdown voltage is ~10V and the on state resistance is ~1.9e 5 cm 2 The total switched gate charge estimated via simulations to be ~25nC/mm 2 yields a figure of merit (FOM) [46] nC at V D = 6V. However, considering time dependent dielectric breakdown, the block voltage for this swi tch is recommended as ~6V and safe operation duration of ~1 month has been observed in our experiments. An improvement of roughly 1.8x over a standard 3.3V thick ox device is achieved. Compared to core 1.2V devices, voltage improvement is 5x. Figure 3 22 The layout and cross section of a switch stacking a thick oxide NMOS on the top of a thin oxide NMOS The second high voltage tolerant synchronous switch that has been investigated is shown in Figure 3 24 with representative layout and cross section. This switch is composed of a 3.3V thick ox NMOS in T WELL and a 3.3V thick ox low V T footer NMOS. Compared to the first stacking structure, the footer transistor is able to handle higher blocking voltages therefore a larger bias of 3V is chosen for the top transistor.

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70 This switch can also be directly driven by 1.2V clocks and turns on and off very quickly. Width/length ratios are chosen as 13 m/340nm for both transistors. A B Figure 3 23 Measured on state and off state current density of the stacked switch with a 3.3V thick oxide NMOS on the top of a 1.2V thin oxide NMOS. A ) O n state current density B ) O ff state current density Figure 3 24 The la yout and cross section of a switch stacking a thick oxide NMOS on top of a thick oxide low V T NMOS in T WELL Figure 3 25 shows measured on state and off state current densities for the second stacking switch. As shown in Figure 3 25 the measured off state breakdown

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71 voltage is also ~10V and the on state resistance is ~1.5e 4 cm 2 which is ~8x larger than the first switch. However, considering time dependent dielectric breakdown, the block voltage for th is switch is recommended as ~8V and safe operation duration of ~1 month has also been observed in our experiments, which achieves an improvement of roughly 2.5x over a standard 3.3V thick ox device. Table 3 2 gives the summary of the measured important parameters for the fabricated extended drain and stacked MOSFETs. A B Figure 3 25 Measured current density of the stacked switch with a 3.3V thick oxide NMOS on the top of a 3.3V thick oxide low V T NMOS. A ) O n state current density B ) O ff state current density Table 3 2 Summary of measured DC parameters for fabricated extended drain and stacked MOSFETs BV (V@1A/cm 2 ) A R ON ( cm 2 ) FOM (m nC) EDMOS 1 9.83 2.2E 4 EDMOS 2 9.83 1.4E 4 EDMOS 3 9.83 2.6E 4 EDMOS 4 9.87 1.3E 4 EDMOS 5 9.87 1.6E 4 EDMOS 6 9.87 3.0E 4 Stacked Switch w/ thin ox transistor 10 .00 1.9E 5 48 Stacked Switch w/ thick ox LVT transistor 10 .00 1.5E 4 345

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72 3.5 Performance Comparison For sil icon devices, there is always a tradeoff between the breakdown voltage and the specific on resistance, which is defined as the product of the on resistance and the area of the device. Theoretical analysis [46] gives a performan ce envelop for power devices, which is called the silicon limit and can be presented with the equation below: (3 11) where R on sp is the specific on resistance, V BV is the breakdown voltage. Fi gure 3 26 The silicon limit and performance comparison for developed power devices For illustrative purpose, the specific on resistance R on sp and the breakdown voltage V BV for developed power devices in this chapter are plott ed in Fi gure 3 26 Standard NMOS available in 130nm CMOS process and LDMOSs developed in [48] [49] are also included in Fi gure 3 26 for comparison. Firstly, developed power devices, stacked NMOSs, EDMOSs and SBDs have improved breakdown voltages (~8 10V) compared to standard NMOSs in 130nm CMOS; Secondly, the stacked NMOSs have

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73 better performance than the EDMOSs, which are further away from the silic on limit in Fi gure 3 26 ; Thirdly, by modifying the process parameters, LDMOSs could achieve better performances, closer to the silicon limit, as presented in [48] [49] Our developed stacked NMOS switches have comparable per formance with LDMOSs in [48] [49]

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74 CHAPTER 4 50 100MH Z 8X H RBRID S I SC AND SI F LYBACK C ONVERTER IN 13 0 NM C MOS P ROCESS 4.1 Introduction of Hybrid Con verters Numerous benefits exist for integrating switched mode step up converters in modern CMOS technologies. A highly integrated system, including power, RF communication subsystems, and digital processing, all on the same die, enables the development of microsystems for applications wherein scale and mass are of critical importance [3] By utilizing the fine feature sizes of modern processes, designers can leverage high switching frequencies, resulting in the desired minimizat ion of passives [7] The primary challenge then becomes that of creating and processing large voltages within an inherently voltage limited process. In this chapter we will introduce and evaluate two hybrid boost converter t opologies SI/SC and SI/flyback, which are capable of sustaining nearly 8x the rated voltage using custom high voltage devices developed in a standard 130nm CMOS process without additional process masks or modifications. These two topologies have been chos en to leverage the increased voltage handling capability of developed Schottky diodes (~10V) and stacked NMOS switches (~7V) when compared to standard and thick oxide MOS switches with 1.2V and 3.3V ratings, respectively. These architectures also limit the maximum voltage stress across the switches, diodes, and passive components while still allowing for large output voltages. 4.2 Hybrid Converter Topologies Conventional SI boost and flyback converters are not suitable for integration in low voltage process es due to large voltage stresses imposed on switches and diodes. The output voltage will be limited by the rating voltage of the process. Moreover, step up

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75 ratio may be further limited by realizable duty cycles and parasitic losses of the inductor and powe r stage [24] Figure 4 1 shows calculated voltage conversion ratio of a SI boost converter considering inductor resistive loss. As R IND /R L increases, the maximum conversion ratio drops significantly w hich is ~5 when R IND /R L =0.01 Larger conversion ratio may be realized using c ascaded switched inductor boost converters [50] However, this method requires two sets of power devices and typically places large voltage levels acr oss rectifiers nearest to the output, complicating or removing the possibility of full integration in standard CMOS processes. Figure 4 1 Voltage conversion ratio of a SI boost converter considering inductor resistive loss [24] One promising solution for onchip high voltage generation is using SC converter topologies [51] [52] Voltage stress in SC converters is minimized and distributed t hereby enabl ing integration in low voltage processes. However, power efficiency of SC converters will drop significantly when voltage conversion ratio is non intege r, which complicates control loop design and voltage regulation. Hybrid converters which co mbine the benefits of SI boost, flyback and SC converters have been demonstrated using discrete components [53] [54] However, their

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76 integration in CMOS technologies has not been done before. This se ction will evaluate them in a 130nm CMOS technology and discuss their challenges and benefits 4.2.1 SI SC Converter Figure 4 2 shows the configuration of a hybrid SI/SC converter composed of a switched inductor (SI) stage follow ed by a switched capacitor (SC) voltage doubl er. In the SI stage, a custom stacked switch comprised of a 3.3V thick oxide and 1.2V thin oxide footer transistor is used. Measurement has shown the blocking voltage of the stacked NMOS switch can be ~7.5V. In the SC stage, n type SBDs with a guard ring and metal in metal (MIM) capacitors with density of ~1fF/ m 2 are used. Breakdown voltage of the SBDs and capacitors are >10V. Total capacitance in the SC stage is ~ 54pF. Figure 4 2 A hybrid SI/SC converter implemented in 130nm CMOS An Agilent 81250 Parallel Bit Error Ratio Tester is employed to create an external clock CLK EX with variable frequency and duty cycle The external clock is then fed in to the driver for the synchronous s tacked switch. As shown in Figure 4 3 w hen the composite switch is on, the inductor voltage is equal to V IN and the inductor current rises with a slope of V IN /L. When the composite switch is off, the inductor voltage turns

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77 to be negative as V IN V C Here V C is the voltage over the capacitors, and can be calculated as V IN /(1 D) when the inductor is continuous. Ideally, a square wave with magnitude of V C will be seen at V X which drives the voltage doubler. The square wave first cha rg es C1 to the peak voltage of VX (ignoring diode drops), charg es C2 in the subsequent phase, and finally plac es the boosted voltage on output capacitor C L when V X peaks at the start of the next cycle. C3 assists in maintaining the output voltage, function ing similarly to C L I n CCM, the output voltage is derived as (4 1) And v oltage stress es for the stacked NMOS switch and SBDs are all equal to V OUT /2 which is a half of that for a t raditional SI boost. The voltage doubler could be replace d by other n stage SC converters, which increases the output voltage nX larger while maintain ing the same voltage stress for switches and diodes. Figure 4 3 Representa tive waveforms for the hybrid SI/SC converter

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78 4.2.2 SI Flyback Converter A B Figure 4 4 Schematic of a hybrid SI/flyback converter implemented in 130nm CMOS. A ) Real Schematic, B) Schematic with transformer model for analysi s Figure 4 4 shows the schematic of a hybrid SI/flyback converter that has been designed and fabricated in a 130nm CMOS process. A transformer (L1:L2) is utilized and its model with magnetizing inductance of L M =L 1 and turns ratio of n is represented in Figure 4 4 b. This hybrid topology can be viewed as stacking a flyback converter on a SI boost thus realizing high conversion ratio with reduced voltage stress when comparing to flyback and SI boost. Figure 4 5 illustrates representative waveforms of

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79 the SI/flyback converter in steady state. In subinterval I, the synchronous switch turns on by the external clock CLK EX and V X1 is connected to ground. The voltage v ind (t) across the primary inductor is V IN which is amplified by the transformer and causes V X2 to be equal to V C1 nV IN Here we assume voltages over capacitors C1 and C2 are steady and annotated as V C1 and V C2 Both diode D1 and D2 are re ve rse biased, and energy is stored in the magnetizing inductance L M In subinterval II, the synchronous switch turns off, the magnetizing inductance L M starts charging V X1 and V X2 up and turns on diode D1 and D2. Voltage V X1 and V X2 in this subinterval are then derived as (4 2a) (4 2b) Voltage v ind (t) in this subinterval becomes negative as V IN V C1 as shown in Figure 4 5 From inductor volt second balance, we can get: (4 3a) (4 3b) (4 3 c ) Bl ocking voltages for the stacked NMOS switch (N1, N0) and diode D1 are calculated as V C1 while voltage stress for the diode D2 is bigger as V C2 +nV IN Comparing to flyback and SI boost, maximum voltage stress is reduced. Both D1 and D2 are implemented using n type SBDs. Since larger voltage stress is seen over D2, guard rings are used for D2 to reduce its leakage. C1 and C2 are implemented using onchip MIM capacitors as 120pF re s pectively

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80 Figure 4 5 Representative waveforms for the hybrid SI/flyback converter 4. 3 Microfabricated Air Core Power Magnetics Integration of power magnetics is generally more difficult than other components in switched mode power converters due to their large physical area and low quality factor. A 2nH o nchip spiral inductor with diameter of 600 m and quality factor of 4.6 at 170MHz has been demonstrated for a buck converter [55] High performance d iscrete inductors and transformers are more commonly used in tradition ho wever their bulky footprints are not suitable for applications such as flying microrobots where high power density is critical. How to improve power density and how to decrease the footprint of passives are becoming more and more important. A microfabrcat ion process aimed for implement ing air core inductors and transformers with high inductance density and moderate quality factors in the range of 10MHz 1GHz was developed [56] This process utilizes three dimensional molding of thick copper traces for low resistance and high mutual coupling and manipulates

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81 photolithographic techniques to use photoresist as an insulating structural support element. This microfabrication process enables system in package integration with silicon electronics e.g., via wire bonding or flip chip attach ment 4.3.1 Layout Design A B Figure 4 6 General layout of fabricated inductors and transformers. A ) I nductors B ) T ransformers Figure 4 6 show s general layout design for fabricated air core inductors and transformers. Square spiral layout and layer stacking were chosen for inductance density maximization and quadratic gains through mutual coupling [57] [58] As shown in Figure 4 6 a, inductor layout consists of upper and lower planar spiral winding layers stacked on top of each other with vias for electrical connection between the windings. The copper windings of de signed inductors are nominally 50 m in width and 10 m in height and have a lateral separation of 10 m. Transformer layout design follows that of inductors as illustrated in Figure 4 6 b. The two outermost windings of the primary an d secondary spirals are laterally interleaved on each layer in a bifilar manner, and the secondary spiral additionally contains nine inner nested turns on each layer for voltage gain. Outer dimension of designed transformer is 1.5mm X 1.5mm, and the copper traces are nominally 30 m in width, 10 m in height, and 10 m in lateral separation. These two design masks have been used in microfabrications.

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82 4.3.2 Process Flow Figure 4 7 Cross sectional view of the microfabrication proc ess flow The microfabrication process, as illustrated in Figure 4 7 consists of two main steps: 1) the build up of a four layer stack copper electroplated within photoresist molds, followed by 2) removal of the molds to release the devices. Copper seed layers were each deposited 200 nm thick and served as the conductive starting surface onto which thicker copper layers would be electroplated. Positive tone photoresist was patterned on top of the seed layer to form the plating mol d. These photoresist molds were each spun to a thickness of 10 m per layer. After all layers of copper were electroplated, the final multilayer structure was released in photoresist developer. The function of the developer was to selectively etch certain exposed regions of photoresist while leaving unexposed regions in the structure as structural elements separating the upper and lower copper windings.

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83 4. 4 Current Mode PWM Control ler Figure 4 8 A current mode PWM controller f or the hybrid SI/SC converter Figure 4 8 illustrates the block diagram of the current mode PWM controller designed for the hybrid SI/SC converter. The current mode PWM has two feedback loops: a voltage feedback loop to regulate t he output voltage V OUT and a current feedback loop to regulate the inductor current i ind (t) In this current mode PWM, the inductor current modulates the control signal CLK directly through comparator A2 for a faster transient response compared to the con ventional voltage mode PWM [59] 4.4.1 Voltage Feedback Loop The voltage feedback loop, which is composed of resistive divider R 1 R 2 compensator (A1), modulator (A2), and RS latch, is stabilized using the classical type II co mpensation network (i.e. C P C Z R Z ) with voltage error amplifier shown in Figure 4 9

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84 The transfer function for the compensated error amplifier can be approximated as [60] [61] : (4 4) The compensated amplifier introduces a pole at dc for high dc gain and a single pole zero pair with the zero and non origin pole given by ZC =1/R Z C Z and PC =1/(R Z (C Z //C P )), respectively. The pole zero pair provides a constant gain and a ZC PC The loop gain of the hybrid SI /SC converter in DCM operation can be approximate d as [62] [63] : (4 5 ) where =R 2 /(R 1 +R 2 ), V PP_RAMP is the amplitude of the voltage ramp, M=V OUT /V IN is the voltage conversion ratio, and R L is the output l oad resistance. P1 is the pole introduced the boost converter operated in DCM, which can be written as P1 =1/(R L C L (M 1)/(2M 1)) where C L is the load capacitance. To ensure stability, the ZC P1 which corres ponds to the lightest load or when R L is largest [63] The error amplifier A1 consists of a two stage design, as shown in Figure 4 9 The input stage combines two folded cascode amplifiers with NMOS an d PMOS differential input for rail to rail input common mode range, and is followed by an active loaded differential pair for a total gain of ~50dB and 3dB bandwidth of ~21MHz. A R 3 R 4 voltage

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85 divider (see Figure 4 8 ) is inserted at the output of A1 to limit the maximum value of V ERR to ~ 0.8V DD This ensures that V SEN crosses V ERR when the hybrid SI/SC converter turns on for proper system start up. The modulator/comparator A2 was designed for higher gain and bandwidth of ~55dB and ~100MHz, respectively, to process V SEN from the current sensor. It employs the same input structure as A1 with additional gain provided by two differential amplification stages and an output buffer inverter. Figure 4 9 Schem atic of the error amplifier in the current mode controller 4.4.2 Current Feedback Loop The current mode feedback loop is composed of a current sensor, ramp generator, modulator A2 and RS latch. This current feedback loop is open loop unstable for duty cyc les greater than 50% (D>0.5), regardless of the state of the voltage feedback loop a well known problem with the current mode PWM [24] Figure 4 10 illustrates the inductor current i ind (t) controlled by the error voltage V ERR to detect the

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86 0 will decrease over time when D<0.5 ( Figure 4 10 a) and increase when D>0.5 ( Figure 4 10 b). This duty cycle instability in the current loop causes sub harmonic oscillations of the converter, as shown in Figure 4 10 c. In this case, the inductor current error affects the output voltage and the error voltage via the voltage feedback. As a result, the error voltage V ERR oscillates at one half the switching frequency, showing a duty cycle harmonic problem, a linear ramp signal with slope m c >0.5m 2 can be applied to the error voltage to force the duty cycle error to decrease over time, as shown in Figure 4 10 d. This slope compensation may either be added to the current waveform or subtracted from the error voltage [64] In this design, the linear slope compensation signal is generated by an on chip oscillator (OSC) and ram p generator, and added to the sensed inductor current output of the current sensor. By adding the slope compensation, inductor current ripple and output voltage ripple will become much cleaner to avoid noise coupling and performance degradation to other ci rcuits The current sensor operates by sensing the power switch N0 drain current (see Figure 4 8 ) to emulate the rising slope of the inductor current [65] As shown in Figure 4 11 N 0 is the 1.2V thin gate power switch, while N 2 is a sensing transistor whose size is K N times smaller than that of N 0 When the control signal CLK turns on the switch N 0 N 2 and N 3 simultaneously due to the balanced signal path design, the switches N 4 and N 5 are turned off. Since the current I MIN is very small, the drain voltage of N 3 can be neglected, letting the drain voltage of N 0 (V S ) almost equal to V The drain voltage of the sensing transistor N 2 (V+) also equals to V due to the high gain c omparator A0.

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87 Therefore, with the same drain voltages, N 2 current is K N times smaller than N 0 drain current I N0 and equal to i ind /K N This emulated inductor current is then reproduced by the P 0 P 1 current mirror with a factor K P and generates a s ense voltage V SEN =R SEN I SEN =R SEN i ind K P /K N During the OFF period of CLK, N 2 and N 3 are turned off to disconnect the current sensing circuit from the power switch. Switches N 4 and N 5 are turned on, supplying P 0 MIN thereby setting the sensing voltage as V SEN =R SEN I MIN K P Moreover, since both input nodes of A0 have low impedance due to the low on resistances of switches N 2 N 5 there is only one high impedance node at the output of A0. Stability is therefore easily achieved using slightly large sizes for P 0 and P 1 to provide dominant pole compensation. A B C D Figure 4 10 Demonstration of loop instability in a current mode con troller A) D>0.5, B ) D<0.5, C ) S ubharmonic oscillation D ) D>0.5 with slope compensati on An RC oscillator based on [65] is modified for digital control and high frequency operation to generate a trigger signal (V pulse ) and compensation slope (I RAMP ), as shown in Figure 4 12 A digitally programmable current source generates V RAMP on the

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88 capacitor C F When V RAMP reaches a threshold set by the R H R L divider, A1 outputs a short pulse to reset V RAMP to ground with switch N 1 An inverter chain is inserted before N 1 to set the desired pulse wi dth of ~500ps, and N 2 adds a hysteresis to the comparator A1 for stable operation. The frequency of the short pulses V pulse (i.e. the frequency of the switching converter) is designed to range from 40MHz to 200MHz, and controlled by F[1:5] to vary the risi ng slope of V RAMP A current ramp generator translates V RAMP in OSC to I RAMP which provides slope compensation to V SEN the output from the current sensing circuit. A voltage follower comprised of A2, P 2 and R A recreates the ramp voltage on R A thus P 2 current is V RAMP /R SEN by setting R A =R SEN P 1 and N 3 are used for fast discharge of the ramp signal to enable high frequency operation. The resulting current is copied via a programmable current mirror S[1:4] to generate and control the slope of I RAMP whic h is added to I SEN for slope compensation. Figure 4 11 Schematic of the current sensing circuit

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89 Figure 4 12 Schematic of the oscillator (OSC) and current ramp generator 4.5 Experimental Result s 4.5.1 Microfabricated Air Core Inductor and Transformer Figure 4 13 a shows a SEM image of a microfabricated fully released inductor [56] Its dc resistance was measured with four point probes using a n HP 3478A multimeter, and ac behavior was characterized using an Agilent E8361A network analyzer. Measured scattering parameters were then transformed to complex impedance parameters from which inductance and quality factor were obtained over a wide range of frequencies A B Figure 4 13 Microfabricated inductor and measured characteristics. A ) SEM perspective image B ) M easured inductance and quality factor [56]

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90 A B Figure 4 14 Microfabricated transformer and measured characteristics. A ) SEM perspective image B ) M easured inductance and resistance values of each element maximum current capacity of ~450 mA. Figure 4 13 b shows its measured ac characterization. Measured ac inductance value was ~14 nH from 10 MHz 1 GHz and peak quality factor was >30 at around 1.5 GHz. At a frequency of 100 MHz (the tested switching frequency of the converter), the quality factor of the inductor was 8. The area of the inductor measured to be 0.5 mm 0.5 mm, which corresponded to an inductance density of 56 nH/mm 2 Figure 4 14 a shows a SEM image of a microfabricated t ransformer [56] Inductance and resistance were extracted from each element of the impedance matrix and plotted in Figure 4 14 b. At frequencies much lower than the resonant frequency, the plots show L 1 1 =46 nH for the primary, L 22 =500 nH for the secondary, and L 21 = L 12 =96 nH for the mutual inductance equivalently expressed as a coupling coefficient of 0.63. The equivalent turns ratio, expressed as SQRT( L 22 /L 11 ), was calculated at 3.3 and indicated

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91 the nom inal voltage gain of the transformer. Operating frequency of these two microfabricated devices were designed between 10 100MHz. 4.5.2 Hybrid SI SC Converter 4.5.2.1 Open l oop m easurement r esults External driving clocks with variable frequency and duty cycl e were employed in open loop measurements for the hybrid SI/SC converter Time domain waveforms when using a 24nH air core inductor from coilcraft and switching at 100MHz are illustrated in Figure 4 15 for 7V and 10V output respec tively. A B Figure 4 15 Measured waveforms of the hybrid SI/SC converter at 100MHz A ) 7V output and 0.96mA load when D= 37.3% B ) 10V ou tput and 0.58mA load when D=83% As shown in Figure 4 15 a, the V X waveform is not an ideal square wave but a relatively complex waveform with ringing in between which means the converter was operating in DCM First, when the clock voltage is small enough such that the stacked switch turns off, the inductor voltage spik es, activating D1 and transferring charge to the SC stage. The inductor current, and thus diode current, immediately and sharply falls, depleting the stored energy in the inductor (for DCM operation) and causing the diode to turn off, leaving the V X node f loating. During this time, V X behaves similarly to an RLC circuit and rings from ~0V up to nearly half the peak voltage, limited by dampening

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92 through various leakage paths and series resistance. The output voltage is ~7V. For Figure 4 15 b the hybrid SI/SC operates in continuous conduction mode (CCM) and the output is ~10V. The peak voltage of V X is proportionally higher and the large amplitude ringing is no longer present since the inductor current is continuous and either the diod e or the stacked NMOS switch is always active. A smaller amplitude and higher frequency ringing behavior still occurs, possibly due to parasitic inductance of devices, package, and PCB traces. Figure 4 16 shows the corresponding measured efficiencies for 7V and 10V outputs and 50MHz and 100MHz switching frequencies. T he hybrid SI/SC converter exhibits a higher efficiency at 100MHz for both 7V and 10V output voltages. This behavior indicates that the SC stage operates in the slow switching limit and would therefore benefit from larger pump capacitors to increase overall efficiency [66] Peak efficiency for this converter is 42% at 1.9mA of load current for a 7V output, and 17.5% at 2.4mA for a 10V outpu t. Figure 4 16 Measured efficiencies with external driving clocks and a 24nH commercial inductor

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93 4.5.2.2 Close l oop m easurement r esults A B Figure 4 17 Wire bonding for the 14nH microfabricated i nductor on a custom PCB for the hybrid SI/SC converter A) Real photograph, B) Envisioned PCB connection A B Figure 4 18 Measured time domain waveforms of the output voltage and switching node voltage V X when measured with the microfabricated inductor at ~100MHz A ) V OUT =7V B ) V OUT =10V The microfabricated inductor was packaged and assembled using wire bonding on a custom printed circuit board for testing within the current mode PWM controlled hybrid boost converter circuit. Figure 4 17 shows the pictures of the packaged inductor with bonding wires. Envisioned PCB connection of the microfabricated inductor is also shown in Figure 4 17 b for better illustration. The bonding wi res introduce extra inductance, which causes measured total inductance 25nH after wire bonding. Figure 4 18 show s measured time domain output voltage (V OUT ) and switching node voltage (V X )

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94 waveforms for 7V and 10V output, respecti vely. A high impedance probe was utilized to measure voltage V X in order to minimize any noise or extra load brought in by the probe. For 7V output, the converter operates in discontinuous conduction mode (DCM) since voltage ringing is seen. The switching frequency is ~115MHz. Similar waveforms are obtained for 10V output except the converter operates in continuous conduction mode (CCM) and the switching frequency is ~100MHz. Figure 4 19 Measured efficiencies for the close lo op hybrid SI/SC converter with microfabricated and commercial inductor respectively Figure 4 19 shows the measured power efficiency versus load current for the hybrid SI/SC converter with the microfabricated inductor (25nH after wire bonding) and a commercial inductor (43nH) With the microfabricated inductor, t he hybrid converter delivers a maximum load current of ~3 mA and a peak efficiency of 37% at 1.6 mA for 7 V output, while for 10 V output, the converter can only deliver a maximum current of ~1

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95 mA and a peak efficiency of 15%. The lower maximum current at 10 V is a consequence of the duty cycle reaching its extreme boundaries at lower current for higher voltage. Comparing to the commercial inductor, the microfabricated indu ctor achieves comparable efficiencies while having a much smaller footprint Fi gure 4 20 shows the transient response for a 50% load step. In all cases the worst case voltage variation caused by current step is less than 7%. Fi gure 4 20 Transient response for the SI/SC converter using a commercial 43nH inductor 4.5.3 Hybrid SI Flyback Converter The hybrid SI/flyback converter was tested with a commercial transformer ( 25nH/200nH ) and the microfabrica ted transformer ( 47nH/496nH shown in Figure 4 14 ) sep a rate ly. Primary and secondary DC resistances of the commercial and microfabricated transformer are measured as 0.12 / 0.31 and 2.9 / 10.18 respectively External driving clocks were used. Figure 4 21 shows time domain waveforms of the SI/Flyback converter using the commercial transformer with 7V and

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96 10V outputs. Ringing at the switching node V X is observed from Figure 4 21 b, wh ich means the SI/Flyback converter operates in DCM for 10V output and 0.58mA load. A B Figure 4 21 Measured waveforms of the SI /flyback converter using a commercial transformer A ) 7V output and 0.97mA load when D=43.5% B ) 10V ou tput and 0.58mA load when D=61% A B Figure 4 22 Measured efficiencies using external driving clocks for the hybrid SI/flyback converter A ) Tested with the microfabricated transformer, B ) Tested with a commercial transform er The efficiency of the SI/flyback converter configured with the microfabricated and commercial transformer is shown in Figure 4 22 With the microfabricated transformer, a peak efficiency of 20% is achieved for a 7V output and a 1.9mA load at 50MHz. The maximum output voltage is 9V for both 50MHz and 100MHz switching frequencies. When the converter is tested with the commercial transformer, a t 100MHz, peak

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97 efficiency of 57% is achieved for a 4.3mA load current and 7V output, whe reas a 32% peak efficiency at 4.3mA load current is seen for an output of 10V. The microfabricated transformer has much higher DC resistances, causing lower efficiencies at shown in Figure 4 22 4. 6 Die Photo and Performance Summ ary Figure 4 23 Die photo of the hybrid SI/SC and SI/flyback converter in a 130nm CMOS process Figure 4 23 shows the chip micrograph fabricated in UMC 130nm CMOS process. The area of the SI/SC conve rter is 0.2mm 2 while that of SI/flyback is 2.25mm 2 including onchip 240pF decoupling capacitors. Table 4 1 illustrates performance summary of the hybrid SI/SC and SI/flyback converter with the microfabricated and commercial inductor / transformer. Compare d to the fully integrated boost converter in [67] the hybrid SI/SC and SI/flyback converter achieve larger voltage conversion ratio of ~9 and higher

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98 efficiency of 37% and 57% for 7V output respectively. When microfabricated in ductors and transformers are employed, the hybrid SI SC converter achieves a larger output voltage and a better power efficiency, which the hybrid SI flyback has a worse efficiency due to the large resistance of the transformer. In terms of power density, the hybrid SI SC converter with the microfabricated inductor is the best and its power density is 47mW/mm2, which accounts for both the area of the converter and the microfabricated inductor. More up to date converters are shown in Table 4 2 for performance comparison with our hybrid SI SC converter. Thoug h the SI boost converter in [68] achieves the same output voltage, ~10V, with a very good power efficiency of ~81%, it uses a discrete diode and a ver y large decoupling capacitor. Table 4 1 Performance summary and comparison for implemented SI SC and SI flyback converter Topology SI SC SI Flyback [67] Technology 13 0n m 13 0n m 180nm Rectifier SBD SBD PN junction Input Range 1.2V 1.2V 1.8V Converter Area 0. 2 mm 2 0.4mm 2 2.7mm 2 (w/ coil) Output Capacitor 4.4nF 240 .0 pF (onchip) N/A Output Range 7V 10V 7V 10V 7V 9V 7V 10V 6V 9V Coil Area 0.25mm 2 N/A 2.25mm 2 N/A N/A Total Area 0.45mm 2 N/A 2.65mm 2 N/A 2.7 0 mm 2 Frequency 50/100MHz 45MHz 50/100MHz 50/100MHz 60MHz Coils 25 nH (w/ bonding wires) 43nH 49nH/496nH (micro fabricated) 25nH/ 200nH 20nH Output Ripple <400mV <80mV N/A N/A 450mV Max. Power ~ 21 .0 m W 17.5mW 14 .0 mW 63 .0 mW N/A Max. P ower Density 47mW/mm 2 N/A 5 mW/mm 2 N/A N/A Max. Step Up Ratio ~9 .0 @ 10 .0 mW ~9 .0 @ 10 .0 mW ~7.5 @ 11 0 mW ~9 .0 @ 56 0 mW 5 .0 @ 0.8 mW Peak Efficiency 37% @ V out =7V 15% @ V out =10V 37% @ V out =7V 15% @ V out =10V 19% @ V out =7V 1 0 % @ V out = 9 V 57% @ V out =7V 31 % @ V ou t =10V 28% @ V out = 6 V

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99 Table 4 2 Performance Summary and Comparison for the hybrid SI SC converter [67] [68] [52] this work Topology SI SI D ickson Hybrid SI SC Node (nm) 180 180 180 130 Rectifier PN Junction Discrete MOS SBD V IN (V) 1.8 3.3 1.8 1.2 V OUT (V) 6~9 .0 9.9 6 ~ 10 .0 4 ~ 10 .0 Freq. (MHz) 60 1 50 150 25 L (nH) 20 4700 N/A 820 C O (nF) N/A 10000 .00 0.03 2.2 0 A (mm 2 ) 1. 7 1.4** N/A 0. 2* Max. V OUT /V IN (@mW) 5@0.8 3@1500 .0 5.6@4 .0 8 .0 @6.7 peak (@mW) 28% @3.6 81% @1500 .0 50% @3.5 41%@8.6 P out peak (mW/mm 2 ) 0.5 ~1000 .0 N/A 43 .0 Level of Integration Full Offchip L &C Full Offchip L& C Excluding pad area ** Estimated area

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100 CHAPTER 5 M ODELING AND P ERFORMANCE A NALYSIS OF H YBRID SI SC S TEP U P C ONVERTERS 5.1 I ntroduction of Hybrid SI SC Converter Autonomous micro systems [3] [69] such as life sized robotic insects that roll, cra wl, jump, or fly require specialized high voltage converters to electrically drive the piezoelectric actuators that transform power into locomotion. These power converters must meet stringent mass and volume requirements, a reality that has led to increase d interest in hybrid switched inductor switched capacitor (SI SC) step up converters [9] [72] Hybrid SI SC converters are good at generating large voltage conversion ratio while distributing large v oltage stress across many of its constituent devices. Since no high voltage devices are required, hybrid SI SC converters could be potentially integrated in a low voltage CMOS process. Doing this allows the power module, RF communication subsystem, and dig ital processor to reside all on a single die, thus enabling extremely small scale and low mass microsystem implementations. The primary challenge then becomes how to analyze and design a high performance hybrid SI SC step up converter Performance analysi s and design of a hybrid SI SC step up converter is usually more complicated than a single SI or SC converter. The main reason is because a hybrid SI SC converter usually involves many constituent devices including both inductors and capacitors. Moreover, device current in different switching phases (i.e. charging or discharging) might b e highly nonlinear causing conventional analysis method s (i.e. state space averaging) inaccurate and less applicable [14] Though some hybrid s tep up converter examples have been presented and analyzed in [72] [70] [71] important

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101 parasitic resistive and capacitive losses in performance analysis. Thus th ose results are less accurate and less optimal in real applications To deal with the difficulties above, section II of this paper firstly presents a generalized hybrid SI SC converter and th en proposes a revised DC circuit model that consists of a DC transformer and several equivalent resistances to represent all important non ideal losses for accurate performance analysis. More specifically, this paper uses a theoretic network methodology ba sed on charge multiplier vectors, expanding on previous work [66] [73] [74] to evaluate important model parameters such as the output impedance and to account for variou s sources of switching loss which are prevalent at high operating frequencies and in on chip implementations. Unlike previous approaches, ours divides dynamic switching loss into output unrelated (i.e. gate drive loss) and output related (i.e. capacitive l oss of diodes) contributions. Accordingly in addition to the conventional output resistance, two equivalent resistive loads are included in the modified circuit model to separately represent the two forms of dynamic loss. Moreover, device metrics are also incorporated in deriving those important model parameters so that the proposed circuit model is more straightforward and friendly to circuit designers. The rest of this chapter is or ganized as follows: Section III employ s SPICE simulation to examine the accuracy of the proposed DC circuit model for three specific hybrid converter design examples with N SC =0, 1, and 4 and various design parameters swept. Section IV describes three real hybrid converters that are implemented in a 1.2V CMOS process and shows open loop experimental results of each topology for comparison with their respective model results for further evaluation and verification. Finally, section V offers some concluding remarks and design guidelines

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102 5.2 Hybrid SI SC Step Up DC DC Converter 5 .2.1 Generalized Hybrid SI SC Converter Topology Figure 5 1 illustrates a generalized SI SC step up converter that is selected in this paper for further performance analysis and circuit modeling. The hybrid converter is composed o f a SI stage with an N SC stage SC ladder multiplier (N SC multiplier could also be implemented using other topologies such as Dickson, serial parallel, etc. [66] The SC ladder multiplier is employed over others because large voltage stress is equally distributed across all power devices so that the whole power converter could be implemented in a single low voltage process. In addition, the generalized hybrid converter involves 1 power switch (M), 2N SC +1 power di odes (D1, SC )), N SC flying capacitors ( C 2 C 4 ( 2N SC )), and N SC holding capacitors ( C 1 C 3 ( 2N SC 1 )). When N SC =0, the hybrid converter simplifies the same as a SI boost converter. Figure 5 1 Schematic of the generalized hybrid SI SC step up converter with an N SC stage SC ladder The generalized hybrid SI SC converter works as follows: Firstly when the power switch (M) is on, the input power source stores energy in the inductor; then when the switch is off, the inductive energy transfers to the holding capacitor C 1 Ideally if C 1 is

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103 large enough, a boosted square wave is generated at node V X with its amplitude determined by the inductor volt second balance [24] Then the square w ave at node V X propagates along the SC ladder multiplier in every each switching and places the boosted voltage from the SI stage to all flying and holding capacitors. After reaching steady state, the output voltage of the generalized hybrid SI SC converte r is N SC +1 times larger than a single SI boost. Voltage stress for the power switch and diodes are the same as V OUT /(N SC +1). A B Figure 5 2 Ideal switching voltage and current waveforms in SI stage A) CCM, B) DCM One importan t thing that needs to be mentioned here is that the SI stage of the hybrid SI SC converter may work in continuous conduction mode or discontinuous conduction mode, depending on the value of the inductor and resistive load. Figure 5 2 illustrates the difference of switching voltage and current waveforms in these two modes. Here, D 1 is the duty cycle when the switch M is on, and D 2 is the duty cycle when there is a current going through the diode D 1 When the hybrid converter works i n

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104 DCM, there is an addition subinterval III when the inductor current is always zero, and its duty cycle is represented as D 3 as in Figure 5 2 Conventionally, two sets of equations are utilized to model the performance at these t wo modes for SI boost. However, analysis shows that during the additional subinterval III, the voltage at switching node V X drifts to input voltage level and charge stops flowing within the hybrid topology except the decoupling capacitor at the load end. T hus power loss related to this additional subinterval in DCM could be ignored. Therefore we could conclude that considering subintervals I and II only is enough to analyze the hybrid converter regardless of its mode of operation and to determine its perfor mance using a single set of equations. More details will be described in the following section. 5.2.2 Analysis Model Figure 5 3 illustrates the revised DC circuit model that will be used for performance analysis of the generalize d hybrid converter. The model employs a DC transformer ( 1:N ) to represent the ideal DC voltage conversion function [24] N is the ideal voltage conversion ratio when circuit load is open. Conduction loss generated by device on resistances and diode turn on voltages are modeled by an equivalent output resistance ( R O ) and an equivalent output voltage drop V DE respectively. High frequency dynamic switching loss traditionally viewed as output independent [66] [73] is divided into output unrelated (i.e. gate drive loss) and output related loss (i.e. capacitive loss of diodes), which we model using two equivalent resistive loads R SWI and R SWO as shown in Figure 5 3 Using the DC circuit model, the output voltage V OUT can be written as ( 5 1 )

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105 The power efficiency is then calculated as ( 5 2 ) wh ere R L is the load resistance Figure 5 3 A general circuit model that accounts for non ideal conduction and dynamic switching losses. The model parameters (R O V DE R SWI R SWO ) shown in Figure 5 3 are used to represent the non idealities generated by device and component parasitic resistances and capacitances. To help derive these m odel parameters, Figure 5 4 shows the non ideal device models with important resistive and capacitive losses. As Figure 5 4 illustrates, inductor L has a parasitic series resistance (R IND ) which is genera lly modeled by R IND Here The storage capacitors (i.e. C 1 ( 2N SC )) are assumed ideal in Figure 5 4 since they have relatively high quality factors For the diodes, we model them by using turn on voltage V D on resistance R D and parallel parasitic capacitance C D For a given technology, the cutoff frequency f T of the diodes could be assumed to be constant, thus diode capacitance C D can be expressed as ( 5 3 a)

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106 The MOSFET switch in Figure 5 4 is modeled by on resistance R M and gate to source, gate to drain, and drain to source parasitic capacitances C GS C GD C DS For a given technology, if assuming C G D ~C G S the figure of merit (FOM) [46] of the MOSFET can be expressed as FOM~(1+n)C GS V GS R N where n =V DS /V GS and where V GS and V DS are the gate and drain to source voltages, respectively. Because V GS for the proposed switch equals V DD C GS can be expressed as ( 5 3b) and C DS can be written in terms of C GS as ( 5 3c) 1) [75] Figure 5 4 Simplified models of passive components and high voltage devices. By an alyzing all the important conduction and switching losses of the devices in the generalized hybrid SI SC converter, all analysis model parameters in Figure 5 3 can be derived. Firstly, the ideal voltage conversion ratio can be eas ily analyzed by assuming all devices are ideal. Considering inductor volt second balance for the SI

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107 stage and assuming small voltage ripple on capacitors, the total ideal voltage conversion ratio is then derived as ( 5 4 ) where N SC is the stage number of the SC ladder. D 2 is the duty cycle of subinterval II in Figure 5 2 which can be approximately expressed as ( 5 5 ) Appendix A gives further details about D 2 in DCM. When N SC =0, the hybrid converter is the same as the SI boost converter. Analysis has proved that equation (5) applies to SI boost as well (N SC =0) [24] A B Figure 5 5 Charge flows in the hybrid SI/SC converter A ) S ubinterval I B ) S ubinterval II

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108 When analyzing the conduction loss for the generalized hybrid converter, charge vectors can be employed for simpl ifying equations, as used for SC converter in [6 6] [73] Following the same analysis procedure, charge flows through each element in subintervals I and II are illustrated in Figure 5 5 for the hybrid SI SC converter. Charge and duty cycle vectors a r and d r for the resistive loss elements can be defined. A charge vector a c is 2N SC ) as with [66] [73] Table 5 1 lists the elements of the defined vectors. Table 5 1 Defined charge and duty cycle vector for the hybrid SI SC step up converter R IND R M R D1 R D2 R D3 R D(2NSC) R D(2NSC+1) a ri ( N SC +1) (D 1 +D 2 ) /D 2 ( N SC +1) D 1 /D 2 + N SC 1 1 1 1 1 d ri D 1 +D 2 D 1 D 2 D 1 D 2 D 1 D 2 C1 C2 C(2N SC 1) C(2N SC ) a ci N SC N SC 1 1 As analyzed for SC converters in [66] the equivalent output resistance R O is estimated separately at low and high switching limits. The output resistance at the slow and fast switching limits is given by ( 5 6 a) and ( 5 6b) respectively. R O is then approximated as ( 5 6c) The equivalent output voltage drop V DE for the hybrid SI/SC converter is given by ( 5 7 )

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109 unrelated AC conduction loss, which can be approximated by ( 5 8 a) Here the peak to peak inductor current ripple IND is ( 5 8b) where the averaged inductor current is I IND = ( N SC +1) I OUT /D 2 The equivalent resi stance R SWI represents the output unrelated losses and includes the inductor ripple AC conduction loss P A and the gate drive losses due to C GS Switching loss due to C SW (i.e. the switched parasitic capacitances in the diodes and at the drain of the s witch ) contributes to both the output unrelated and output related loss terms, but not necessarily equally if analyzing carefully. For simplicity (and supported by simulation results), we assume equal contributions (0.5) to each. Different distribution val ues (i.e. 0.8) might be used for different other topologies to achieve better estimate since switching loss might affect input and output differently. The voltage swings of the parasitic capacitances represented by C SW are approximately V IN (D 1 +D 2 )/D 2 th us R SWI can be expressed as ( 5 9 a ) where (5 9b)

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110 Here n=V DS /V GS and V DS and V GS are drain to source and gate to source voltage of the NMOS swi tch. Table 5 2 Summary of steady state model equations for the hybrid SI SC step up converter V OUT Hybrid SI SC with N SC SC ladder D 2 N R O V DE R SWI P C R SWO C SW And the equivalent resistance for the output related loss R SWO can be w ritten as ( 5 10 )

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111 Table 5 2 summarizes the model parameters and equations for the generalized hybrid SI/SC step up converter. 5.3 Model Validati on Table 5 3 Important d evice p arameters u sed in SPICE s imulation for SI c onverter (N SC =0) Inductor Switch (n=V DS /V GS =5) Diode Topology L R IND @50MHz R M C GS C DS R D V D C D N SC =0 820nH 1.8pF 1.7pF 0.24V 1.5pF Table 5 4 Important d evice p arameters u sed in SPICE s imulation for hybrid SI SC c onverter (N SC =1) Inductor Switch Diode (1x) Topology L R IND @50MHz R M C GS C DS R D V D C D N SC =1 820nH 0.3pF 5pF 0.5 3.2pF Dio de/Cap D1 D2 C1 C2 Size 1x 1x 17pF 17pF Table 5 5 Important d evice p arameters u sed in SPICE s imulation for hybrid SI SC c onverter (N SC =4) Inductor Switch Diode (1x) Topology L R IND @50MHz R M C GS C DS R D V D C D N SC =4 390nH 1.8pF 1.7pF 0.24V 100fF Diode D1 D2 D3 D4 D5 D6 D7 D8 D9 Size 10x 5x 10x 5x 10x 5x 8x 4x 6x Cap C1 C2 C3 C4 C5 C6 C7 C8 Size 180pF 180pF 180pF 160pF 160pF 140pF 140pF 120pF The accuracy of the proposed circuit model is verified aga inst SPICE using the simplified device model shown in Figure 5 4 Table 5 3 5 list the corresponding simulation parameters of three specific hybrid converter examples (N SC =0, 1 and 4) employed in this sec tion. These device parameters are employed based on power devices implemented in a 1.2V CMOS process. The dc output voltage (V OUT ) were simulated against load resistance (R L ) and switching frequency (f S ) and across duty cycles D 1 =0.2 and 0.8, without restrictions on DCM or

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112 CCM operation. For these simulations, R L was varied from and the switching frequency from 1MHz to 400MHz. A B C D E F Figure 5 6 Power efficiency obtained from m odel and SPICE simulation for the three hybrid SI/SC converters A ) N SC =0 and f S =50MHz, B ) N SC =1 and f S =50MHz, C ) N SC =4 and f S =50MHz, D ) N SC =0 and R L E ) N SC =1 and R L F ) N SC =4 and R L The efficiency vs R L and f S for the switched inductor top ology (N SC =0) shown in Figure 5 6 a and 6d is in good agreement with SPICE with an average model error of

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113 <20%. For the SI SC topologies (N SC =1 and 4), the average model error is <35%, which is primarily due to : (a), current nonlin earity in the SC stages that is not captured by the equivalent output resistance approximation in Eq. 6; (b), slow turning on/off transitions resulted from large switching loss and their effects on effective duty cycle and conduction loss calculation. The model exhibits improved accuracy for larger R L or f S values mainly due to small current nonlinearity in these conditions. As one would expect, efficiency degrades as R L is increased for fixed f S ( Figure 5 6 a c) and/or as f S is inc reased for fixed R L ( Figure 5 6 d f). To highlight the importance of switching losses, also included in Figure 5 6 are the model results when these losses are neglected altogether, showing a noticeable dro p in power efficiency at lighter loads and higher switching frequencies. Importantly, the model predicts desirable operating switching frequency range for optimal efficiency. Moreover, the proposed model does not make any assumptions of DCM or CCM operatio n. Conventional models [66] [73] [74] which only employ R SWI to incorporate the effect of the switching loss, are less accurate especially in DCM. As with the power effic iency, plots of output voltage vs R L and f S for the three simulated converters are also shown Figure 5 7 In simulations, maximum output voltages are ~7V, ~11V, and ~35V for the three converters respectively at 50MHz. Average mod el error is <20% for the switched inductor topology (N SC =0), <30% for the hybrid SI/SC topologies (N SC =1, 4). Dashed lines of analysis results without including switching loss are also shown to demonstrate the effects of switching loss on output voltage. C onventional models [66] [73] [74] which only employ R SWI to incorporate the effect of the switching loss result in huge model error especially in deep DCM.

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114 A B C D E F Figure 5 7 Output voltage obtained from model and SPICE simulation for the three hybrid SI/SC converters A ) N SC =0 and f S =50MHz, B ) N SC =1 and f S =50MHz, C ) N SC =4 and f S =50MHz, D ) N SC =0 and R L E ) N SC =1 and R L F ) N SC =4 and R L Moreover, the plots in Figure 5 7 show increased model error at large R L for fixed f S ( Figure 5 7 a, 7b, 7c) or at large f S for fixed R L ( Figure 5 7 d, 7e, 7f) for all three converters. The reason is because switching loss becomes dominating at large R L or at large f S resulting in slow switching transition and inaccurate calculation of duty cycle D 2 in eq. 5. Switching behavior beco mes extremely complicated especially when both

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115 inductor and capacitor are present and may also involve energy oscillating. Referring to Figure 5 6 power efficiency drops quickly at these regions and designers should avoid operati ng converters near these regions for performance consideration. 5.4 Experimental Results To provide more proof for the proposed analysis model as well as to demonstrate ultra miniature high voltage powering system, three hybrid SI SC converters with resp ective N SC =0, 1, and 4 have been fabricated in a 130nm 1.2V CMOS process Since the baseline CMOS process only provides 1.2V thin oxide and 3.3V I/O transistors, in order to create large output voltages, some custom high voltage tolerant devices such as st acked NMOS switch and schottky barrier diodes were developed and utilized in the three hybrid converters. Device testing kits including two types of stacked NMOS switch and four types of schottky barrier diodes were fabricated without using any extra maski ng and process steps. And measurement results have shown that breakdown voltage of these customized devices could be extended to ~10V which is 3x larger than the operating voltage of the standard 3.3V devices [39] For stacked NMOS switch, the first composite structure is stacking a 3.3V thick ox transistor on top of a 1.2V thin ox transistor, and the second one is stacking two 3.3V thick ox transistors while using a low threshold footer device. These two composite structures w ere chosen since they have good tradeoff between large block voltage and low on resistance while they are driven by 1.2V switching clocks. Gate bias of the top transistor in each composite structure was selected as 2.5V and 3V respectively for life time re quirement of the footer transistor considering time dependent dielectric breakdown (TDDT) [34] Measurement shows that specific on resistance of these two composite structures are 1.9e 5 cm 2 and 1.5e 4 cm 2 respectively Sw itching gate

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116 charges which are useful for switching loss estimate were approximated through SPICE simulation when assuming 6V (n=6/1.2=5) block voltage from the top drain to the bottom source. Thus from these estimated switching gate charges, FOMs of the t wo stacked NMOS switches are then calculated as 48 m nC and 345 m nC (for V D =6V). Table 5 6 Characteristic summary of stacked NMOS switches A R ON ( ) FOM (m nC) Stacked Switch w/ thin ox transistor 1.9E 5 48 Stacked Switch w/ thick ox LVT transistor 1.5E 4 345 Table 5 7 Characteristic summary of schottky barrier diodes V D (mV) AR D f T (GHz) n type SBD w/o guard ring 380 3.2e 5 26 p type SBD w/o guard ring 270 5.2e 5 15 n type SBD w/ guard ring 495 5.1e 5 12 p type SBD w/ guar d ring 460 6.7e 5 8 For schottky barrier diodes, testing structures of n and p type with and without p+/n+ guard rings were implemented by selectively blocking the n+/p+ implants in desired diffusion areas or by directly contacting the N /P well with me tallization [39] [76] On state current density was measured and their specific on resistance ( A R D ) and turn on voltage (V D ) were extracted using first order piecewi se linear model. To evaluate their switching behavior, cutoff frequency was also measured using network analyzer from which their switching loss could be modeled and estimated. Table 5 6 and Table 5 7 summarize electric characteristics of implemented custom high voltage devices. Schematics of the three hybrid SI SC converters with respective N SC =0, 1, and 4 are illustrated in Figure 5 8 The first two converters in Figure 5 8 a (N SC =0) and 8b (N SC =1) use the same stacked NMOS switch (with thin ox footer transistor) but different n type schottky barrier diodes. The diode in Figure 5 8 a has guard rings for less reve rse

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117 leakage current, while the second diode in Figure 5 8 b does not have guard rings for low on resistance and low turning on voltage. The second converter also has three 17pF onchip capacitors for voltage doubling. Among them, th e third capacitor C3 can be lumped with the external load capacitor C L thus it is not included in analysis model. All onchip capacitors were implemented using Metal insulator Metal (MIM) with capacitance density of ~1fF/m 2 Die photo of the first two hyb rid converters in Figure 5 8 a and 8b is shown in Figure 5 9 a, in which the first one takes ~ 500x380m 2 and the second one takes ~ 500x400m 2 The high voltage devices (i.e. NMOS switch and S chottky diode s ) occupy ~ 43% of the total area in both design s A B C Figure 5 8 Schematics of t hree fabricated hybrid SI SC converters A ) N SC =0 (SI boost) B ) N SC =1 C ) N SC =4 Schematic of the third hybrid SI SC converter with N SC =4 is s hown in Figure 5 8 c. It employs the second stacked NMOS switch which uses both thick oxide devices but

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118 the footer transistor has low threshold voltage to reduce on resistance. The SC ladder multiplier utilizes p type schottky barr ier diodes for even less on resistance and the capacitors are all onchip MIM caps. One important thing to mention here is that as the number of the SC stage increases, though voltage stress on each device is small, large output voltage may cause some paras itic junctions to break down. To avoid junction breakdown, post process step was implemented to create isolation trenches between each SC islands as outlined with dashed lines in Figure 5 8 c. Since the cost of the post process ste p is low, this could be a potential low cost approach for generating very large voltages for autonomous microsystems. Die photo of the converter after post processing is shown in Figure 5 9 c, where the SI stage is 1.2mm*1mm and th e SC stage is 1.2mm*2.4mm with isolation trenches shown between SC islands. Isolation trenches were done by using dicing saw with width of ~35 m. The bottom of the die was attached to a pyrex wafer for electrical insulation. To verify the analysis model p resented in section II, the three hybrid SI SC step up converters were open loop tested using external drive clocks with constant duty cycle of D=0.8 and input voltage of 1.2V. Figure 5 10 11, and 12 plot their measured output vo ltage s and efficienc ies alongside their respective analysis model results for comparison. As shown in Figure 5 10 and 11, the first two converters were evaluated over a variety of load s at 25MHz and 50MHz respectively when c oilcra ft chip inductors of 390nH with quality factor Q=22 at 50MHz and of 820nH with Q=18 at 25MHz were employed While in Figure 5 12 the third hybrid converter was measured using chip inductors of 390nH, 1H, and 2.7H at 25MHz, 12.5 MHz, and 6.25MHz respectively. Inductor quality factors Q are estimated from datasheet as 10, 20, and 25 at their

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119 respective switching frequency. Different inductor values and switching frequencies picked for each topology in measurements were to maximize output voltage while keeping power efficiency as high as possible. A B Figure 5 9 Die photo s of three hybrid converters A) SI (N SC =0) and hybrid SI SC (N SC =1), B) hybrid SI SC (N SC =4) In Figure 5 10 the first hybrid SI SC converter with N SC =0 (also called SI converter) achieves a peak output voltage of and peak efficiency of ~61% at when switching at 50MHz with an inductor of 390nH in measurement. Similar output voltage are obtain ed for a switching frequency of 25MHz with an 820nH inductor. In Figure 5 11 maximum output voltage of the second converter is ~10V at 15k which is ~1.7x larger than that of the first hybrid converter. Measurement shows output voltage of the second hybrid

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120 converter could not go higher than 10V. The reason for that is because NWELL PSUB junction breaks down at ~10V. Thus by using post processing, as shown in Figure 5 12 the third hybrid converter with four stage SC ladder (N SC =4) achieves a maximum outp ut voltage of ~30V in measurement, which is 3x larger than that of the second converter. Maximum power efficiency of the second and third hybrid converters in measurement is similar, ~40% as shown in Figure 5 11 and 12. Analysis model results after accounting for conduction and switching loss based on electric characteristics of utilized inductors and those custom high voltage devices in Table 5 6 and 5 7 were plotted as gray lines in Figure 5 10 11, and 12. For output voltage, these plots show that modeling error increases with load resistance. Possible reasons include: firstly, as voltage increases, reverse leakage current of power devices increases, which has n ot been included in the model presented in section II; secondly, as load resistance increases, each hybrid converter intends to move from CCM where conduction loss dominates to DCM where switching loss dominates. The calculation equation of duty cycle D 2 i n Table 5 2 only accounts resistive elements and becomes less accurate as load resistance increases. A B Figure 5 10 Measurement and model results of the first hybrid converter (N SC =0) with V IN =1.2V and D 1 =0.8. A) Output voltage, B) Efficiency

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121 A B Figure 5 11 Measurement and model results of the second hybrid converter (N SC =1) with V IN =1.2V and D 1 =0.8. A) Output voltage, B) Efficiency A B Figure 5 12 Measurement and model results for the third hybrid converter (N SC =4) with V IN =1.2V and D 1 =0.8. A) Output voltage, B) Power e fficiency For power efficiency, comparison between measurement and analysis model results show that modeling error is relatively large when load resistance is small (large output current). Possible explanation for this behavior is that when load current is large, capacitor voltage varies significantly causing charging and discharging current highly nonlinear. Thus the equ ation for approximating output resistance (R O ) using its slow switching limit and fast switching limit in Table 5 2 becomes less accurate and induces large modeling error at low load resistance condition. However, considering the entire load resistance range, average modeling percent error between analysis model and

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122 measurement results is reasonable, which is ~20%, ~30%, and 35% for the first (N SC =0), second (N SC =1), and third (N SC =4) hybrid SI SC step up converter respectively. 5.5 Modeling and Analysis Conclusions This chapter presents a generalized hybrid SI SC step up DC DC converter that is good at generating large voltage conversion ratio for driving high voltage actuators in autonomous microsystems. To accurately analyze i ts performance, a modified circuit model is proposed by accounting for all important non ideal conduction and switching losses. Different from other approaches, ours divides dynamic switching loss into output unrelated and output related contributions and utilizes two additional resistive loads to separately model them All these model parameters including equivalent output resistance are then derived using a theoretic network methodology based on charge multiplier vectors SPICE simulation and experimental results of three specific hybrid SI SC converter examples are provided for comparison with the proposed analysis model. Good agreement on output voltage and power efficiency is demonstrated. Therefore the proposed circuit model could be used to guide circ uit designers to analyze and optimize the performance of hybrid SI SC converters when designing a suitable high voltage powering unit in autonomous microsystems.

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123 CHAPTER 6 M INIATURE H IGH V OLTAGE H YBRID S TEP U P P OWER C ONVERTER FOR SMART P IEZOELECTRIC M ICROSYSTEMS 6.1 Introduction of High Voltage Converters in Microsystems Bug sized robotic platforms that crawl, jump, flap or fly [2] [77] have been actively pursuing miniature high voltage power converters for driving actuators (i.e. piezoelectric) to realize locomotion. For example, a power survey on tiny platforms that are under development in MAST [3] has been illustrated in Figure 6 1 fro m which we could see most actuators require driving voltage >10V. To address these design concerns, power converters not only need to have large voltage conversion ratio, but also need to be highly efficient and ultra compact, which at small scales posts a remarkably daunting task. Additionally, to meet the stringent mass and volume requirements, the necessary digital motion control and communication system should be integrated on the same die with the power conversion blocks. To date, little work has been introduced that combines the functionality of these blocks in a highly integrated form using a standard fine line CMOS process. This chapter is aimed to fill this gap by presenting a hysteretic controlled hybrid SI SC step up converter in a 130nm CMOS pro cess for creating large driving voltages and using it with a TI commercial DSP to create a smart piezoelectric micro flapper for demonstration. Traditional ly, high voltage power converters in micro robots are usually realized by using either a large numbe r of discrete components [9] or a bulky transformer [10] result ing in large system volume and low power density. P. Basset, et al. demonstrated a miniature 10kHz 100V Cockcroft Walton step up conve rter with digital control circuitry integrated in a 100V CMOS technology with total area of 5mm x 3mm for actuators [11] However, the relatively low cutoff frequency of the high voltage process restricts

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124 achievable switching f requency employed for the step up converter, thereby causing big passives large area and low efficiency. K. Ishida, et al. presented a 20 30MHz 1.8V to 20V switched inductor (SI) boost converter using a 0.18m CMOS and 20V NAND flash process [78] resulting in a much smaller footprint. But the utilization of a n extra high voltage process to implement power switches and rectifiers for handling large voltage stress intrinsically imposed by the SI boost topology causes this soluti on expensive. M. Innocent, et al. [79] and R. Pelliconi, et al. [52] reported fully integrated 50 100MHz 10 15V high voltage generators in 0.18m CMOS technologies by using switched capacitor (SC) t opologie s which are superior in distributing large voltage stress across switches and diodes comparing to the SI boost thereby allowing their monolithic integration in low voltage processes. The main drawback for SC converters is that efficiency drops sig nificantly at heavy loads or non integral conversion ratios causing line/ load regulation poor. Moreover, SC converters suffer from large input current ripple, demanding big decoupling capacitors at the input. The above drawbacks of SC converters could be m itigated by using different techniques such as quasi SC [80] or hybrid topology [39] The hybrid SI SC topology reported in [39] combines the benefits of both SI and SC converters, keeping reduced voltage stress across devices, thereby allowing exploration of fine feature size, large transistor density, and high switching frequency of advanced CMOS technologies to realize ultraminiaturized onchip high voltage step up conv erters. E. Stelz, et al. [9] also present that the hybrid topology is one of the best solutions for powering high voltage actuators. This chapter utilizes the hybrid SI SC topology and customized high voltage tolerant devices in a 1.2V standard CMOS process to generate large driving voltages up

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125 to 35V from a 3V input with minimal post process steps and external components as well as demonstrates a smart piezoelectric flapper using the implemented hybrid step up converter with a TI commercial DSP. The structure of this chapter is as follows: Section II presents the converter schematics and discusses a design methodology for optimizing area and power efficiency. Section III then introduces a high frequency hysteretic controller an d a serial parallel interface for programming and communicating to the hybrid converter with minimal external wires. Section IV provides experimental results of the stand alone hybrid step up converter and section V describes the details of the demo, a sma rt piezoelectric flapper and its testing results. Figure 6 1 P ower requirements for various autonomous microsystems 6.2 High Voltage Hybrid SI SC Step Up Converter Implementation of a h y brid SI SC step up converter in an advanced CMOS process is challenging for reliability reasons due to large voltage stress. The potential strategy for enabling voltages beyond the maximum voltage rating of a CMOS process

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126 consists of distributing the output voltage of the step up converter across multiple of its constituent devices so that the blocking voltage seen by any single device never exceeds its safe operating limit. Thus power transistor trains [39] [45] especially low side NM OS are good solutions to realize high voltage tolerant power switches in a low voltage CMOS process without using extra process steps as well as to keep the fabrication cost low. For high side PMOS switch, however, power transistor trains require complicat ed floating driving circuitry. Thus in this chapter schottky barrier diodes are chosen over PMOS as high side switches since they have low voltage drop and fast transition time and could also genuinely block any reverse current flow which is very common wh en the converter works in discontinuous conduction mode for large conversion ratio situations. Figure 6 2 illustrates the implementation details of the high voltage hybrid SI SC step up converter using the two specialized high vo ltage tolerant devices fabricated in a standard 130nm CMOS process. The low side stacked NMOS switch is made with a 3.3V 70 thick oxide nMOS stacked on a low V T thick oxide nMOS device A 1.2V switching clock is selected to drive the bottom device while t he top transistor is biased at a fixed gate voltage. In this way, switching loss is reduced and conductivity is kept high. Measurement results show that its specific on conductance is 1 .5E 4 /cm 2 with breakdown >10V. Moreover, with the aid of SPICE simula tion, gate charge of the stacked NMOS switch is estimated from which its FOM (figure of merit) is calculated as [46] For high side rectifiers, p type s c hottky diodes are used which are fabricated in isolated p wells (enclosed in deep n well) by selectively blocking p+ implants in desired diffusion areas [39] M easured forward turn on voltage

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127 conductance and cutoff frequency of the SBD are 280 mV 5.2E 5 /cm 2 and 15GHz respectively T h e hybrid SI SC converter is composed of a SI stage and a 4 stage SC ladder multiplier. As with the SI boost converter, the SI stage creates a large amplitude square wave at node V X Assuming the driving clock has a duty of D, the generated wave amplitude i s V IN /(1 D). This large amplitude square wave is then multiplied and rectified four times by the SC ladder thus ideally creating an output voltage up to 5V IN /(1 D). Here the ladder multiplier topology is chosen over Dickson charge pump [81] and other SC architectures [66] since large voltage stress is equally distributed across each diode and capacitor which makes it more suitable for integration in low cost low voltage CMOS technology In the SC la dder multiplier, all capacitors are implemented using onchip MIM capacitors with total capacitance of 1.4nF and density of 1fF/um 2 Each MIM capacitor has a breakdown voltage >15V. Figure 6 2 Implementation detail of the hig h voltage hybrid SI SC step up converter 6.2.1 Optim al Design Procedure To help analyze the performance of the hybrid SI SC step up converter, a DC circuit model using an ideal DC transformer to represent power conversion [66] as

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128 shown in Figure 6 3 could be used. In this DC circuit model, conduction and switching loss is lumped and modeled using output and input impedance R O and R I respectively. Additionally, since diodes are used in the hybrid topol ogy, power loss related to their turn on voltages is modeled using a lump voltage source V DE as shown in Figure 6 3 Thus, from the DC circuit model, the performance of the hybrid converter could be represented using the followin g two equations: ( 6 1 a) ( 6 1b) L is load resistance. Regarding the circuit parameters in Figure 6 3 for the hybrid SI SC step up converter, a theoretic network methodology based on charge m ultiplier vectors [66] can be employed. By analyzing charge flow in the two switching phases in Figure 6 4 a and 4b when the stacked NMOS is turned on and off, a charge vector a r and duty cycle vector d r for all switches and the inductor, and a charge vector a c for all capacitors could be defined to represent output normalized charge flowing through each device over one switching period. The defined vector values are listed in Table I. Here D 1 and D 2 are duty cycles when the stacked NMOS is on and off respectively. In continuous conduction mode, D 2 =1 D 1 And V D is the turn on voltage of the diodes. Additionally, the charge flow through C h5 is negligible when output capacitor C L is large enough thus C h5 i s not modeled in later analysis.

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129 Figure 6 3 A DC circuit model for performance analysis Table 6 1 Defined charge and duty cycle vector for the hybrid SI SC step up converter R i L NMOS D1 D2 D3 D 4 D5 D6 D7 D8 D9 a ri 5D 1 /D 2 +5 5D 1 /D 2 +4 1 1 1 1 1 1 1 1 1 d ri D 1 +D 2 D 1 D 2 D 1 D 2 D 1 D 2 D 1 D 2 D 1 D 2 C i C h1 C f1 C h2 C f2 C h3 C f3 C h4 C f4 C h5 a ci 4 4 3 3 2 2 1 1 A B Figure 6 4 Charge flow analysis of the hybrid SI SC s tep up converter in the two switching phases A ) W hen the stacked NMOS is on B ) When the stacked NMOS is off As analyzed for SC converters in [66] the equivalent output resistance R O is estimated separately at low and high s witching limits. Assuming the switching frequency

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130 is f s the output resistance at the slow and fast switching limits (SSL and FSL) is given by ( 6 2 a) and ( 6 2b) respectively. R O is then approximated as ( 6 2c) The equivalent output voltage drop V DE for the hybrid SI/SC converter is given by ( 6 3 ) To optimally design the hybrid SI SC step up converter for target specs on V OUT P OUT Figure 6 5 could be employed. Firstly, from target output power and efficiency, total allowed power loss can be calculated as P loss =P OUT (1 loss P SW and conduction loss P cond be defined to represent the ratio of conduction loss to total loss. Thus P cond =P loss SW =P loss *(1 conduction loss are balanced. Secondly, the conduction lo ss of the hybrid converter can be derived by using the circuit model in Figure 6 3 from which we have the equation P cond =V DE *I OUT +I OUT 2 *R O Since conduction loss has already been known from efficiency, output impedance R O is the n calculated. After R O is known, based on the DC circuit model in Figure 6 3 ideal voltage conversion ratio N is then obtained as

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131 N=(V OUT +V DE +I OUT *R O )/V IN Assuming the hybrid converter is in continuous conduction mode, duty cy cle of the switching clock is then calculated as D 1 =1 5/N. For a selected switching frequency f s IND /I IND inductor value could be obtained, which is L=V IN IND *D 1 T s H ere IND is the peak to peak inductor curren t ripple, and I IND [82] for small inductor and little ac current loss. After L is known, its equivalent serial resistance could then be calculated as R IND s L /Q w here Q is the quality factor of the inductor L at frequency f s Thirdly, as shown in equation (6 2), the output impedance is estimated using its slow and fast switching limit which represents capacitive loss at low frequency and resistive loss at high fre split the conduction loss to R OSSL =R O O F SL =R O (1 usually suggested as 0.5 [66] When R OSSL and R OFSL are known, Lagrange optimi zation could be used to obtain the optimal size of each capacitor and switch by minimizing their total area [73] Optimization results are then obtained as follows: (6 4 a) ( 6 4b) where a ri a r j d ri d r j a c i and a c j are the i th or j th element of the vectors defined in table I. After on resistance of each switch and capacitance of eac h capacitor are obtained, SPICE simulation could be used to check the output voltage, output power, and

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132 efficiency of the designed hybrid converter. If simulation results are off target, f s could be tweaked to optimize the c onverter design again following the procedure in Figure 6 5 until the simulation results are on target. Figure 6 5 Optimal design procedure for the hybrid SI SC step up converter 6.3 Hysteretic Con troller The hybrid SI SC step up converter could be regulated the same as the SI boost converter by controlling the duty cycle of its driving clock. Thus conventional voltage mode or current mode PWM control schemes [24] could be used. However, small signal analysis shows that the hybrid SI SC converter, if operating in CCM, exhibits two poles and one right half plane (RHP) zero in its loop gain transfer function. Appendix B and C show some analysis details. Stability frequency compensation has to compromise the

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133 loop bandwidth to mitigate the influence of the RHP zero, thus resulting in slow transient response [83] To overcome the drawback above, hysteretic control scheme could be employed, which as a nonlinear control method is advantageous in avoiding frequency compensation and achieving large bandwidth and fast transient response. Hysteretic control has been widely used in switching buck converters [6] [7] However, most hysteretic controllers designed for buck converters could not be directly used for boost converters due to their very different loop characteristics. In buck converters, inductor current ripple is in phase with output volta ge rip ple, while in boost converters, the two ripples are out of phase. To resolve this difficulty, several hysteretic approaches which adopt extra control variables have been proposed [84] [85] and demonstrated good transient response. However, adopted extra control variables introduce extra design complexity. In this chapter use any extra control variable is presented and designed for the hybrid SI SC step up co nverter. Compared to other approaches, the hysteretic controller is easier and simpler to design since no extra control variable is used. The switching on time of the controller is fixed during transient response. Though it is not optimal, the constant on time could keep inductor energy always under control so that no unpredicted large voltage stress during transient response will be seen on the specialized stacked NMOS switch to ensure lifetime requirement in real applications. Details of the designed hy steretic controller with the SI stage of the hybrid converter are illustrated in Figure 6 6 a. The hysteretic controller has two comparator loops, one for output voltage and one for inductor current. The first comparator loop consi sts of the resistor voltage divider R f1 R f2 and the hysteretic comparator HC1. R f1

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134 R f2 sense the output and send the divided down voltage V FB to HC1. HC1 compares V FB to V REF and asserts signal EN whenever V FB is smaller. The asserted signal EN then keep s the hybrid SI SC converter constantly pumping energy to the output until HC1 de asserts it. The second comparator loop includes the lossless inductor current sensing network R 1 C 1 R 2 C 2 and hysteretic comparator HC2 to regulate inductor current. As sh own in Figure 6 6 a, R 1 C 1 as a pseudo integrator, sense the inductor current I IND and creat e a voltage in proportion to I IND with inverted polarity, which is then coupled to sense node V S through high pass filter C 2 R 2 R 2 C 2 is 1 C 1 V BL and V BH are bias voltages conditioned through a start up circuit with V BL setting the center of HC2 hysteretic window V H V BH is set slightly higher than the hysteretic window of HC2 to make sure the low side NMOS will be always turned on w henever signal EN is asserted. To better illustrate the working principle of the hysteretic controller, s ample waveforms during start up and in steady state are shown in Figure 6 6 b When the hybrid converter is initially turned on V FB is below V REF and EN is high To avoid large inrush inductor current, V BL is initially set higher than V BH so that I IND remains zero until the start up sequence ends with V BH crossing the top of the hysteretic window of HC2. The conditioning circui t for this purpose is shown in Figure 6 7 a which generates the rising V BH and the falling V BL during start up V BHDC and V BLDC are bias voltages that V BH and V BL will settle at after start up. Then sensing voltage V S inversely cha nges with I IND until V S hits the limits of the hysteretic window. CKS toggles and keeps the hybrid converter continuously pumping energy to output until V OUT reaches the target. During this process, the slope of V S and hysteretic window V H of HC2 together determine the on time of the driving clock which is expressed as t on =V H /V IN *R 1 C 1 Since V IN V H R 1 C 1

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135 are fixed, t on is nearly constant. After EN is low, the controller stays idle and V S drifts to V BH until V OUT hits the lower hysteretic window of HC1 a nd asserts EN. Moreover, to improve the testing capability of the controller, a MUX is added to allow for bypassing with external clock CLK E A serial interface is also included to digitally program C 1 R 2 and hysteretic windows of HC1 and HC2 for flexibi lity A B Figure 6 6 Hysteretic controller designed for the hybrid SI SC step up converter and its sample waveforms. A ) Block diagram of the h ysteretic controller B ) sa mple waveforms Figure 6 7 b shows the design of the hysteretic comparator shared by HC1 and HC2. It consists of a pre amplification stage, a cross gate decision stage with

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136 hysteresis, and an output stage, all realized using 1.2V h igh speed devices. The preamplifier uses both NMOS and PMOS input pairs to achieve rail to rail input voltage range. In the decision stage, NMOS pairs M1/M3 and M2/M4 use cross gate connection to realize positive feedback and hysteresis. By adjusting the s ize ratio of these pairs, hysteresis window V H could be programmed and five digital bits are employed for this purpose. DC simulation shows the maximum hysteresis window is ~100mV and the program step is ~3mV. Quiescent current of the comparator is ~350 A and transient simulation shows the delay is ~1ns. A B Figure 6 7 Conditioning circuit for V BL and V BH and hysteretic comparator with programmable window. A ) Conditioning circuit B ) H ysteretic comparator An onchip voltage regulator is also included in this controller design to generate an internal 1.2V supply from the 3V input for powering the two comparators and control logics. Figure 6 8 shows its schemati c [86] which is composed of a high slew rate error amplifier and a pass PMOS. The pass PMOS is a thick oxide transistor with a size of

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137 20m/0.34m. The error amplifier employs two common gate differential input pairs M1/M2 and M3/M4 with bias currents (I bias ) set as 5A. Two 4x current mirrors then sum the input differential current at the output as a push pull stage. Since the slew rate is not limited by the bias current, very fast slew rate is achieved with low quiescent curr ent. Simulation shows the error amplifier has a total quiescent current of ~50A. And loop bandwidth of the regulator is ~20MHz and phase margin is 45 degree. Figure 6 8 Onchip linear regulator to generate internal power su pply for the controller 6.4 Experimental Results The hysteretic controlled hybrid SI SC step up converter was fabricated in a standard 1.2V 130nm CMOS process as two chips. As shown in Figure 6 9 the first chip integrates the hy steretic controller and the stacked NMOS switch together with a size of 1.2mm x 1mm, and the second one contains the 4 stage SC multiplier with a size of 1.2mm x 2.4mm. Measurement shows that parasitic substrate junction in the SC multiplier has a breakdow n voltage of ~10V. To generate output greater than 10V, a post process step was employed to create three substrate isolation trenches inside the SC multiplier. Four isolated islands were then formed inside the second chip and wire bonding was used to conne ct them. After the post process step, both chips were mounted onto a testing board directly without using any packages to minimize footprint.

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138 Wire bonding was used again to connect the I/O pads of the silicon dies to the PCB board. Other discrete component s such as inductor, feedback resistors, and decoupling capacitors are also mounted onto the same board using solder paste as shown in Figure 6 9 Figure 6 9 Testing board for the hybrid SI SC step up converter and zoomed in die photos of the hysteretic controller with stacked NMOS switch and the SC multiplier. The hybrid SI SC step up converter was firstly evaluated with the hysteretic controller bypassed. External switching clocks of 50MHz, 25MHz, and 12.5MHz with duty cycle of D=0.5 were explicitly selected to drive the hybrid converter with V IN =3V when three chip inductors L=390nH, 1H, 2.7H were consecutively employed. These testing parameter combinations were chosen for achieving maximal outpu t voltage for the hybrid converter. Measured output voltage and power efficiency are plotted in Figure 6 10 As shown in Figure 6 10 the hybrid conver ter achieves a maximal output voltage of ~35V for all testing cases. In Figure 6 10 b, the peak power efficiency for L=390nH and f s =50MHz is the lowest,

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139 ~33%, while for L=2.7H and f s =12.5MHz, the peak efficiency is ~45%. Though th e efficiency difference is ~12%, the latter inductor is 7x larger. Considering the tradeoff between inductor size and power efficiency, L=1H and f s =25MHz is the best. A B C Figure 6 10 Open loop measurement results with D=0. 5 and V IN =3V and power loss distribution when f s =25MHz and L=1H. A ) Measured output voltage B ) P ower efficiency C ) Power loss distribution To better understand the performance of the hybrid converter, a power loss distribution for the testing case with L=1H and f s =25MHz was done and illustrated in Figure 6 10 c. The total power loss are broken down through simulation and analysis as six parts including inductor resistive loss, NMOS on resistance loss, diode on resistance loss, diode turn on voltage loss, charging and discharging loss of capacitors in SC

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140 multiplier, and parasitic capacitive switching loss. When load resistance R L hybrid converter achieves the maximal output voltage, but 62.9% of total power loss is due to parasitic switching loss. When R L efficiency of 43% with an output voltage of 24V. In this condition, 45.9% of total power loss is due to charging and discharging loss of capacitors in SC multiplier. From t hese pie charts, we could see that, in order to improve power efficiency at large output voltages, utilizing lower switching frequency or larger capacitors in SC multiplier could be used. However, low switching frequency requires large inductor value and l arge capacitors will consume too much silicon dies. Therefore, later measurements will continue using the testing setup with L=1H and f s ~25MHz. Close loop testing results of the hybrid step up converter with its hysteretic controller enabled are plotted in Figure 6 11 13. All results were obtained with L=1H and V IN =3V. Shown in Figure 6 11 are measured timing waveforms of the output and the switching voltage at node V X which connects the SI stage and th e SC multiplier as shown in Figure 6 2 Figure 6 11 a shows when output is 30V with a maximal load current of 270A, peak voltage at V X is ~7V and the close loop switching frequency is ~18MHz. When the out put increases to 35V, maximal output current decreases to 190 A. And measured timing waveforms in Figure 6 11 b show that peak voltage at V X increases to ~8V with a switching frequency of ~19MHz. Moreover, analysis and measurement show that peak voltage at node V X should be kept no greater than ~8.5V to avoid time dependent dielectric breakdown and hot carrier effects on those specialized high voltage tolerant devices When peak voltage at V X is >8.5V, device life time might be red uced, or permanent damage may be observed.

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141 A B Figure 6 11 Measured close loop timing waveforms when the hybrid SI SC converter is tested with L=1H and V IN =3V. A ) V OUT =30V and I OUT =270A B ) V OUT =35V and I OUT =190A A B Fig ure 6 12 Measured timing waveforms of the hybrid step up converter for positive load transient response with L=1H and V IN =3V. A ) V OUT =30V B ) V OUT =35V. Shown in Fig ure 6 12 are measured timing wavefo rms of the hybrid step up converter when positive 50% load step occurs for 30V and 35V outputs. These waveforms demonstrate that the hysteretic controller is stable and could respond to load step immediately by pumping more energy to the output to keep V OU T of the hybrid converter within spec. Transient response for negative 50% load step was also captured but not plotted here since the response is slow due to the hybrid converter could not

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142 sink current from the output. Moreover, Figure 6 13 plots the output waveform of the hybrid step up converter with a modulated reference when a pseudo piezo actuator load reaches 15V output at 0.9 s and 35V at 15 s. For a sine o r triangular reference, the output follows V REF to generate 500Hz sineish and triangular waves. Figure 6 13 demonstrates that the hybrid converter successfully generates 35V 500Hz driving voltage for the pseudo piezo actuator. A B C Figure 6 13 Measured timing waveforms with a pseudo piezo load of when the reference is modulated A) S tep, B ) 500Hz sine, C ) 500Hz triangular wave 6.5 Preliminary Demo of a Smart Piezoelectric Microsystem The miniature high voltage hybrid power converter was employed with a commercial microprocessor (TI M SP430L092) to form a smart piezoelectric microsystem as a preliminary demo for driving a resonant piezoelectric fan (#RFN1 005). Figure 6 14 a shows a picture of the demo which consists of a laptop, a custom power supply board, a T I microprocessor, a high voltage hybrid step up converter, and a resonant piezo fan. The laptop provides both power and communication signals via a USB interface to the whole microsystem. Since the USB voltage is 5V, a custom power

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143 supply board was designe d using commercial voltage regulators to generate 3V and 1.2V supplies for powering the hybrid step up converter and the microprocessor respectively. The low voltage microprocessor then generates specific configuring sequences (CLK, DAT) and a voltage refe rence (VREF) to control and program the high voltage hybrid step up converter for creating large driving signals for the resonant piezo fan. Appendix D shows the code that could be loaded in IAR software to generate the required sequences (CLK, DAT, VREF). Here TI MSP430L092 was selected since it uses a supply of 1.2V and could be potentially integrated with the hybrid power converter on the same die using the standard 1.2V CMOS process. Moreover, the hybrid power converter and the piezo fan were mounted to gether inside a black box for easy measurement and protection from hazardous damage. In the end of the piezo fan, a custom wing was also attached for visual demonstration and its resonant frequency was measured as ~25Hz. The high voltage hybrid power conve rter and the microprocessor were programmed to generate 35V 25Hz driving signals. After the microsystem was enabled, real time displacement of the custom wing was measured using a laser displacement sensor and the testing results are plotted in Figure 6 14 b. It shows that peak output voltage of the hybrid power converter is ~35V and the piezo fan resonates at 25Hz with a maximum displacement of 1.5mm. One more thing to be mentioned here is that the output voltage waveform has a ver y slow falling slope since the hybrid step up converter could not sink current for its load. Therefore, when a high frequency actuator with a large load capacitance is needed to be driven, a DC AC inverter has to be inserted between the hybrid step up conv erter and the actuator to generate accurate AC driving

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1 44 waveforms [87] The preliminary demo shown in this section is only applicable to low frequency actuators due to the slow falling slope. A B Figure 6 14 A smart piezoelectric microsystem using the hybrid SI SC step up converter and a commercial MSP and measurement results A) Microsyste m photo, B) Measurement results.

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145 CHAPTER 7 C ONCLUSIONS AND F UTURE W OR KS 7 .1 Research Summary and Contributions The focus of this dissertation is on highly integrated switching mode step up DC DC converters in advanced CMOS processes for portable devices and microsystem applications These applications have strict design req uirements, such as large voltage conversion ratio, miniaturized footprint, light weight, and high power density. Utilizing the fine feature size in advanced CMOS processes, step up voltage converters could be miniaturized. Additionally, advanced CMOS proce ss es allow integrating those step up voltage converters with digital signal processing and RF communication circuits on a single die, thus enabling an extremely small electronic solution for portable or microsystem applications. Implementing step up voltag e converters in advanced CMOS process es introduces d esign challenges on device reliability and system performance which are investigated in different chapters through this dissertation. Device reliability issue is dealt with by developing specialized devi ce structures in chapter 3 and utilizing hybrid topolo gy techniques in chapter 4. The first contribution is that t hree high voltage tolerant power devices, namely schottky barrier diodes (SBD), stacked NMOS switches, and extended drain MOS devices are dev eloped in a standard 1.2V 130nm CMOS process without adding any masking steps. These specialized devices extend the maximum block voltage to be 2 3X larger than the standard thick oxide devices in the process The second contribution is that this disse rtation evaluates two 50 100MHz hybrid step up converter topologies, namely hybrid switched inductor (SI) switched capacitor

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146 (SC) and hybrid SI flyback converter, in the standard 1.2V 130nm CMOS process. These two hybrid topologies are able to distribute l arge voltage stress across many of constituent devices to mitigate the device reliability concern. Experimental results show that by using specialized high voltage tolerant devices and a 24nH commercial air core inductor (Q=30@100MHz), the SI SC converter achieves a maximum output of 10V from 1.2V input and a maximum efficiency of 42% at 1.9mA of load current for a 7V output The hybrid SI flyback converter was tested a t 100MHz with a commercial transformer ( 25nH/200nH ). It achieves a peak efficiency of 57 % for a 4 .3mA load current and 7V output. Moreover, a micro fabrication technique is also demonstrated to further reduce the sizes of passive components C ustom high inductance density air core inductors and transformers were fabricated and employed with t hese two hybrid converters in measurements Experimental results show that compared to commercial counterparts the micro fabricated components achieve comparable performance with much smaller footprints. To deal with the performance concern of step up vo ltage converters, a general circuit model is proposed in chapter 5 for performance analysis of hybrid SI SC step up converters, which is the third contribution of this dissertation. The proposed circuit model us es a theoretic network methodology to evaluat e the output impedance and account for various sources of switching loss prevalent at high operating frequencies and in on chip implementations. Unlike previous approaches, this approach divides dynamic switching loss into output unrelated (i.e. gate drive loss) and output related (i.e. capacitive loss of diodes) It then uses two equivalent input and output resistive loads to model them separately. Comparisons with SPICE simulations and experimental

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147 results demonstrate that for the three specific hybrid co nverters examined in chapter 5 the proposed approach is accurate for evaluating the power efficiency and the output regulation as a function of load. A complete hybrid SI SC step up converter with a hysteretic controller and an internal voltage regulator i s demonstrated in a 1.2V CMOS process with minimal post process steps An optim al design procedure based on theoretic network analysis is also presented to minimize design cost Experimental results show that the fabricated hybrid converter generates outp ut voltage up to 35V from a 3V input. Moreover the hybrid converter is employed with a commercial microprocessor to form a preliminary demo as a smart piezoelectric microsystem which successfully drives a 25Hz piezo fan 7 .2 Future Works This dissertatio n has explored some high frequency (10 100MHz) step up voltage converters in a standard 1.2V 130nm CMOS process. Maximum output voltages of 10V and 35V have been demonstrated with commercial and micro fabricated passives without and with extra post proces s steps A potential research dire ction is using the hybrid SI SC converter to achieve a n even lar ger output voltage with better performance for autonomous microsystems The hybrid SI SC converter is one of the best solutions since device voltage stress is equally distributed and the output voltage can be increased without adding more voltage stress on power devices. One possible direction is using a SOI process which eliminates the N well to substrate junction. Another possible direction is using microfabr ication techniques to isolate the high voltage N wells. Possible techniques include back side etching to remove the substrate in selected regions. With all these techniques, >35V

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148 output voltages or even higher can be achieved in the standard 1.2V CMOS proc ess for driving piezoelectric actuators

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149 APPENDIX A D 2 DERIVATION FOR SI AND HYBRID SI SC CONVERTER IN DCM A 1 Derivation of D 2 for SI S tep U p C onverter in DCM For a non ideal SI step up converter, when calculating the current and voltage across the ind uctor, the on resistances of the switch and diode have to be considered. With the aid of the current and voltage waveforms depicted in Figure A 1 the peak to peak inductor current ripple I IND can be derived as follows. A B Figure A 1 Representative waveforms of the SI step up converter A ) CCM B ) DCM In subinterval I, (A 1) and in subinterval II, (A 2) The total charge supplied to the load during one period Q is given by (A 3) and the output voltag e V OUT is

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150 (A 4) To solve for D 2 we first substitute (A 3) into (A 4) and the resulting V OUT expression is substituted back into (A 2). Then we solve for I IND in (A 1) and substitute into (A 2) to obtain (A 5) Solving (A 5 ) for D 2 yields (A 6) where (A 7) and (A 8 ) In DCM, D 2 (1 D 1 ) and K D 1 (1 D 1 ) 2 A 2 Derivation of D 2 for Hybrid SI SC C onverter (N SC S tage ) The SI/SC converter can be viewed as a SI conver ter cascaded with a SC converter, as shown in Figure A 2 The effective load of the SI stage is R L +R OSC where R OSC is the equivalent output resistance of the SC stage. Applying the same derivation procedure as in Appendix A1 to t he hybrid SI/SC step up converter, D 2 in DCM can be expressed as (A 9)

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151 where (A 10) and (A 11) Figure A 2 Simplified circuit model for the hybrid SI/SC step up converter

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152 APPENDIX B SMALL SIGNAL AC A NALYSIS FOR SI B OOST IN CCM The configuration of a SI boost under investigation is s hown in Figure B 1 To apply state space averaging to this topology, only parasitic resistances are considered. Derived results based on the above assumption will apply when the converter is highly efficient where capacitive switc hing losses are insignificant. Figure B 1 The configuration of a SI boost converter and equivalent circuits in subinterval I and II when operating in CCM In subinterval I (0 t d T T s ), (C 1) (C 2) In subinterval II ( d T T s t s ) (C 3)

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153 (C 4) Through state space averaging, we have equations (C 5) (C 6) A B Figure B 2 Small signal circuit model and duty to output transfer function for the SI boost in CCM. A ) S mall signal circuit model B ) duty to output transfer function Assuming small low freq uency perturbations as

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154 and ignoring higher order terms, DC and low frequency AC equations can be obtained. ( C 7) (C 8) where R INDeq =R IND +D R N +(1 D) R D V OUTeq =V OUT +V D I IND (R N R D ) From C 8, a small signal circuit model for the SI boost converter in CCM is derived and illustrated in Figure B 2 From the derived small signal circuit model, duty to output transfer fu nction T p can be derived which is also shown in Figure B 2 (C 9) The right half plane zero is (C 10) The corner frequency is (C 11) The quality factor is (C 12)

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155 APPENDIX C S MALL S IGNAL AC A NALYSIS FOR SI B OOST IN D CM Averaged switch model in DCM has been derived and described clearly in [x]. Here the derived model is applied to the SI boost, resulting in a small signal circuit model as shown in Figure C 1 A B Figure C 1 Derived small signal circuit model and d uty to output transfer function for the SI boost in DCM. A) Small signal circuit model, B ) Duty to output transfer function Parameters used in Figure C 1 are detailed as follows. (in DCM) (D 1) (D 2) (D 3) (D 4)

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156 (D 5) (D 6) (D 7) Figure C 1 b shows the duty to output transfer function, which includes a possible RHP zero and two poles. (D 10) (D 11) (D 1 2 ) (D 1 3 ) (D 1 4 )

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157 APPENDIX D MSP 430 L 092 CODE FOR SMART P IEZO MICROSYSTEM DEM O //****************************************************************************** // Code for utilizi ng the MSP430L092 microprocessor to generate the digital // sequences of (CLK, DAT) for controlling the hysteretic hybrid SI SC converter // Built with IAR Version 5.10.4 ocessor //**************************************************************************** #include "msp430l092.h" //int Output; //unsigned int out1, out2; int DACup; int i, j; int loop; //data pattern for SCBoost Control ler unsigned char CLKcell=0xC3; //[11000011] unsigned char DATHeader=0xF0; //[11110000] unsigned char DATEnder=0x0F; //[00001111] //Q[32:29]=0,Q[28:25]=0,Q[24:21]=0,Q[20:17]=[0001], //Q[16:13]=[1111],Q[12:9]=[0000],Q[8:5]=[1010],Q[4:1]=[0011], unsigned lon g DATcell=0xC50F8000; void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer

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158 // Set P1.0, P1.1 output P1DIR |= BIT0 + BIT1; //Setup of the A POOL module for DAC output APCNF = DBON+CONVON +APREFON; // Configure A POOL elements APCTL |= ODEN+OSEL; // A POOL Comparator/Saturation Based Stop Enable and Running APINT=0; /************************/ /* Setup CCS */ /******* *****************/ CCSCTL0 = CCSKEY; // Unlock CCS while (SFRIFG1 & OFIFG) // Oscillator Flag(s)? { CCSCTL7 = 0; // Clear HF & LF OSC fault flags SFRIFG1 = 0; // Clear OFIFG } CCSCTL4 = SELA_0 + SELM_0 + SELS_0; // Select HFCLK/DCO as the source for ACLK, MCLK, and SMCLK CCSCTL5 = DIVA_0 + DIVM_0 + DIVS_0; // Set the Dividers for ACLK to 1, MCLK to 1, and SMCLK to 1 CCSCTL0_H |= 0xFF; // Lock CCS

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159 /* Lock by writing to upper byte */ // Setup of TimerA0 Capture Compare Register 0 TA0CCTL0 = CCIE; // TA0CCRO Interupt Enable TA0CCR0 = 1; // Setup of TimerA0 Contro l Register TA0CTL = TASSEL_2 + MC_1 + TACLR; // SMCLK, Up Mode __bis_SR_register(LPM0_bits + GIE); // Enter LPM0 w/ interrupts enabled while (loop < 1000) { //loop++; if(APIN T<0x01) DACup=1; else{ if(APINT>0xFE) DACup=0; } //header for(i=1;i<9;i++){ if(DACup){ if(APINT<0xFF){ APINT=APINT+0x1E; } else APINT=0xFF; }

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160 else{ if(APINT>0x00){ APINT=APINT 0x1E; } else APINT=0x00; } if(BIT0 & CLKcell){ P1OUT |= BIT0; //set CLKcell = (CLKcell >> 1) | (CLKcell << 7); } else{ P1OUT &= ~BIT0; //reset CLKcell = (CLKce ll >> 1) | (CLKcell << 7); } if(BIT0 & DATHeader){ P1OUT |= BIT1; //set DATHeader = (DATHeader >> 1) | (DATHeader << 7); } else{ P1OUT &= ~BIT1; //reset DATHeader = (DATHeader >> 1) | (DATHeader << 7); } }

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161 //data pattern for(j=1;j<33;j++){ for(i=1;i<9;i++){ if(BIT0 & CLKcell){ P1OUT |= BIT0; //set CLKcell = (CLKcell >> 1) | (CLKcell << 7); } else{ P1OUT &= ~BIT0; //reset CLKcell = (CLKcell >> 1) | (CLKcell << 7); } // if(BIT0 & DATcell){ P1OUT |= BIT1; //set } else{ P1OUT &= ~BIT1; //reset } } DATcell = (DATc ell >> 1) | (DATcell << 31); } //ender for(i=1;i<9;i++){

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162 if(BIT0 & CLKcell){ P1OUT |= BIT0; //set CLKcell = (CLKcell >> 1) | (CLKcell << 7); } else{ P1OUT &= ~BIT0; //reset CLKcell = (C LKcell >> 1) | (CLKcell << 7); } // if(BIT0 & DATEnder){ P1OUT |= BIT1; //set DATEnder = (DATEnder >> 1) | (DATEnder << 7); } else{ P1OUT &= ~BIT1; //reset DATEnder = (DATEnder >> 1) | (DA TEnder << 7); } } } } #pragma vector=TIMER0_A0_VECTOR __interrupt void Timer_A (void) {

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163 if(APINT < 0x01) DACup = 1; else { if (APINT > 0xFE) DACup = 0; } if(DACup){ while(APINT < 0xEF) APINT=APINT+0x1 0; APINT = 0xFF; } else{ while(APINT > 0x10) APINT=APINT 0x10; APINT = 0x00; } TA0R = 0x0000; //??? for(loop=0;loop<500;loop++){} }

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164 LIST OF REFERENCES [1] l flying dissertation, Dept. EECS, U.C. Berkeley, CA, 2006. [2] R. Intelligent Robots and Systems, pp. 1889 1894 2007. [3] B. Morgan, S.S. Bedair et al. Power c onsiderations for MAST p latforms Proc. of the SPIE Defense, Security, & Sensing 2010 Workshop, Orlando, FL, v ol 7679, pp.76790V 1 12, Apr. 2010 [4] M. Karpelson, G Y. Wei, R. J. Wood, A review of actuation and power electronics options for flapping wing robotic insect s, 2008 IEEE Int Conf on Robotics & Automation, Pasadena, CA, USA, p p 779 786, May 2008 [5] Y. Bar Cohen, Electroactive P olymer (EAP) A ctuators as A rtificial M uscles Second Edition, SPIE Publications, 2004, p p 26. [6] P. Hazucha, G. Schrom et al. MH z 80% 87% efficient four phase DC DC converter utilizing air State Circuits, vol. 40, no. 4, pp 838 845, 2005 [7] P. Li, L. Xue et al. delay locked loop synchronization scheme for high frequency multiphase hystere tic dc dc converters Circuits, vol 44, no 11, pp. 3131 3145, Nov. 2009. [8] P. Li, D. Bhatia, L. Xue, R. Bashirullah, "A 90 240MHz h ysteretic c ontrolled DC DC b uck c onverter with d igital p hase l ocked l oop s ynchronization ," IEEE J. Solid State Circuits, vol. 46, no. 9, pp. 2108 2119, Sept. 2011. [9] E. Steltz M. Seeman, S. Avadhanula, choice fo IEEE/RSJ Int. Conf. on Intelligent Robots and Systems, pp. 1322 1328, 2 006. [10] M. Karpelson, G. scale high voltage power electronics for piezoelectric microrobots Automation, pp. 2217 2224, 2009. [11] P. Basset, A. Kaiser, B. Stefanelli, M. Walenne, D. Collard L. Buchail IC for the remote powering and control of a microrobot using an electrostatic ciliary 1713 2003 [12] C. L. Bellew, S. Hollar K.S. 1079 2003

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166 [26] power supply topology v oltage mode vs. current mode TI Unitrode Design Note DN 62. [Online]. Available from http://www.ti.com/sc/docs/psheets/abstract/apps/slua119.htm [Accessed July 201 3 ]. [27] U. Kartha integrated passive UHF RFID transponder IC with16 .7 minimum RF input power State Circuits, vol .38, no .10, pp. 1602 1608, Oct. 2003. [28] enhanced electrical characteristics dissertat ion, Dept. Materials Sci. Eng., Univ. of Toronto, Toronto, Canada, 2009. [29] voltage devices and circuits in standard CMOS technologies Ph.D. dissertation, Dept. Elect. Eng., EPFL, Lausanne, Switzerland 1997. [30] empir ical model for device degradation due to hot carrier injection IEEE Electron Device Lett. vol. 4, pp. 111 113, Apr. 1983. [31] description of hot carrier induced interface states Proc. Int. Electron Devices Meeting pp. 535 538 1992 [32] injection SiO 2 breakdown model for very low voltage lifetime extrapolation IEEE Trans. On Electron Devices vol. 41, no. 5, pp. 761 767, May 1994. [33] /O in a 2.5V 0.25 m CMOS technology State Circuits, vol. 36, no. 3, pp.528 538, Mar. 2001. [34] R. Moazzami 1650, Jul 1990. [35] power amplifiers The Design of CMOS Radio Frequency Integrated Circuits 2 nd ed. UK: Cambridge Univ. Press, 2004, ch.15, pp. 493 555. [36] voltage Fundamentals of Power Semiconductor Devices New York: Sp ringer, 2008, ch.3, pp. 91 167. [37] junction curvature on breakdown voltage in semiconductors Solid State Electronics vol. 9, pp. 910 916, 1975. [38] maximum blocking capability of silicon thyristors Solid State Electronics vol. 8, pp. 655 671, 1965. [39] P. Li, L. Xue et al. Digitally a ssisted d iscontinuous c onduction m ode 5V/100MHz and 10V/45MHz DC DC b oost c onverters with i ntegrated s chottky d iodes in s tandard 0.13um CMOS ISSCC Tech. Dig. Papers, pp.206 207, F eb. 2010.

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171 BIOGRAPHICAL SKETCH Lin Xue received the B.S. degree in mechanical engineering and the M.S. degree in microelectronics from Tsinghua University, Beijing, China, in 2005 and 2007, respectively. He received his Ph.D. degree in electrical and computer engineering at the University of Florida, Gainesville, FL in the fall of 2013 His research interests include integrated high performance analog power management circuits including switched inductor boost and buck converters, switched capacitor voltage converters, and hybrid switched inductor switched capacitor step up converters