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Ultra Low Power Passive Transponders for Biomedical Microsystems

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Title:
Ultra Low Power Passive Transponders for Biomedical Microsystems
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1 online resource (130 p.)
Language:
english
Creator:
Tang, Chunming
Publisher:
University of Florida
Place of Publication:
Gainesville, Fla.
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Thesis/Dissertation Information

Degree:
Doctorate ( Ph.D.)
Degree Grantor:
University of Florida
Degree Disciplines:
Electrical and Computer Engineering
Committee Chair:
Bashirullah, Rizwan
Committee Members:
Harris, John Gregory
Lin, Jenshan
Batich, Christopher D

Subjects

Subjects / Keywords:
biomedical -- low-power -- multiplier -- rf-dc -- rfid -- transponder
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre:
Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract:
This dissertation examines several aspects of designing high-efficiency and low-power building blocks for passive microsystems used in biomedical applications. To reduce losses in the power conversion in voltage multiplier, the architecture implements several types of Schottky diodes on standard CMOS processes. The Schottky diode provides a lower turn-on voltage, which minimizes the losses associated with the forward biased voltage drop. Utilizing the diode’s measured I-V characteristics, this dissertation proposes a new RF-DC voltage multiplier design procedure. This design method provides an overview of the voltage multiplier’s design parameters, including the diode sizing, number of stages, the RF-DC voltage multiplier’s input impedance, matching between antennas, and power conversion efficiency. A new calibration-free low-power clock generator is also presented. This clock generation scheme provides a clock frequency that is more stable against process, temperature, and voltage variations. This allows more reliable data decoding and encoding. Additionally, this dissertation also proposes a dual power supply RF-DC power management unit to minimize the clock generator’s power consumption and to improve the overall DC-DC voltage conversion efficiency. A novel passive transponder architecture is proposed, which minimizes overall chip area. All building blocks in the proposed transponder are designed to be operated from an AC power supply. With this architecture, the AC power supply not only powers the transponder but also provides a clock signal for the chip. This allows the architecture to eliminate area-consuming building blocks, such as an RF-DC multiplier, a decoupling capacitor, a voltage regulator, and a power-on-reset circuit. Finally,a battery-assisted transponder is presented. The transponder can use take the DC voltage at the input to improve the sensitivity. A radio transmitter is used in this proposed transponder to improve the communication range. The transponder can also operate by harvesting energy from electromagnetic wave if the DC voltage is not available at the input. The proposed transponder has both advantages of the active and passive transponder architectures.
General Note:
In the series University of Florida Digital Collections.
General Note:
Includes vita.
Bibliography:
Includes bibliographical references.
Source of Description:
Description based on online resource; title from PDF title page.
Source of Description:
This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility:
by Chunming Tang.
Thesis:
Thesis (Ph.D.)--University of Florida, 2013.
Local:
Adviser: Bashirullah, Rizwan.

Record Information

Source Institution:
UFRGP
Rights Management:
Applicable rights reserved.
Classification:
lcc - LD1780 2013
System ID:
UFE0045886:00001

MISSING IMAGE

Material Information

Title:
Ultra Low Power Passive Transponders for Biomedical Microsystems
Physical Description:
1 online resource (130 p.)
Language:
english
Creator:
Tang, Chunming
Publisher:
University of Florida
Place of Publication:
Gainesville, Fla.
Publication Date:

Thesis/Dissertation Information

Degree:
Doctorate ( Ph.D.)
Degree Grantor:
University of Florida
Degree Disciplines:
Electrical and Computer Engineering
Committee Chair:
Bashirullah, Rizwan
Committee Members:
Harris, John Gregory
Lin, Jenshan
Batich, Christopher D

Subjects

Subjects / Keywords:
biomedical -- low-power -- multiplier -- rf-dc -- rfid -- transponder
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre:
Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract:
This dissertation examines several aspects of designing high-efficiency and low-power building blocks for passive microsystems used in biomedical applications. To reduce losses in the power conversion in voltage multiplier, the architecture implements several types of Schottky diodes on standard CMOS processes. The Schottky diode provides a lower turn-on voltage, which minimizes the losses associated with the forward biased voltage drop. Utilizing the diode’s measured I-V characteristics, this dissertation proposes a new RF-DC voltage multiplier design procedure. This design method provides an overview of the voltage multiplier’s design parameters, including the diode sizing, number of stages, the RF-DC voltage multiplier’s input impedance, matching between antennas, and power conversion efficiency. A new calibration-free low-power clock generator is also presented. This clock generation scheme provides a clock frequency that is more stable against process, temperature, and voltage variations. This allows more reliable data decoding and encoding. Additionally, this dissertation also proposes a dual power supply RF-DC power management unit to minimize the clock generator’s power consumption and to improve the overall DC-DC voltage conversion efficiency. A novel passive transponder architecture is proposed, which minimizes overall chip area. All building blocks in the proposed transponder are designed to be operated from an AC power supply. With this architecture, the AC power supply not only powers the transponder but also provides a clock signal for the chip. This allows the architecture to eliminate area-consuming building blocks, such as an RF-DC multiplier, a decoupling capacitor, a voltage regulator, and a power-on-reset circuit. Finally,a battery-assisted transponder is presented. The transponder can use take the DC voltage at the input to improve the sensitivity. A radio transmitter is used in this proposed transponder to improve the communication range. The transponder can also operate by harvesting energy from electromagnetic wave if the DC voltage is not available at the input. The proposed transponder has both advantages of the active and passive transponder architectures.
General Note:
In the series University of Florida Digital Collections.
General Note:
Includes vita.
Bibliography:
Includes bibliographical references.
Source of Description:
Description based on online resource; title from PDF title page.
Source of Description:
This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility:
by Chunming Tang.
Thesis:
Thesis (Ph.D.)--University of Florida, 2013.
Local:
Adviser: Bashirullah, Rizwan.

Record Information

Source Institution:
UFRGP
Rights Management:
Applicable rights reserved.
Classification:
lcc - LD1780 2013
System ID:
UFE0045886:00001


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1 ULTRA LOW POWER PASSIVE TRANSP ONDERS FOR BIOMEDICA L MICROSYSTEMS B y CHUN MING TANG A DISSERTATION PRESE NTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL F ULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORID A 201 3

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2 2013 Chun Ming Tang

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3 To my family

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4 ACKNOWLEDGMENTS I would like to first thank my advisor Dr. Rizwan Bashiru llah for giving me this great opportunity to work toward a Ph.D degree under his supervision. His constant guidance and encouragement provided me a clear path for my study, and I have truly enjoyed working with him over the se years of acquiring knowle dge I would also like to thank Dr. John Harris Dr. Jenshan Lin and Dr. C hristopher Batich for their valuable time and for being on my Ph.D committee. I feel very fortunate to have worked together with all my colleagues, especially Zhiming Xiao, Qiuzhong Wu Chris Dougherty Walker Turner Jikai Chen, Lin Xue, and Edgar Garay of the ICR group The helpful discussion, suggestion and friendship I have shared with my all my colleagues ha ve improved the quality of my work and without them I would not have been able to complete this project. Finally, I would like to acknowledge the love and continuou s encouragement I have received from my parents Ms Mei Hsin Fan and Mr. Kuo Chu Tang and my wife Dr. Qing Yang

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5 TABLE OF CONTENTS Page ACKNOWLEDGMENTS ................................ ................................ ................................ ............... 4 LIST OF TABLES ................................ ................................ ................................ ........................... 7 LIST OF FIGURES ................................ ................................ ................................ ......................... 8 CHAPTER 1 INTRODUCTION ................................ ................................ ................................ .................. 14 1.1 Motivation ................................ ................................ ................................ ........................ 14 1.2 Research Goals ................................ ................................ ................................ ................. 16 1.3 Thesis Organization ................................ ................................ ................................ .......... 16 2 OVERVIEW OF PASSIVE TRANSPONDERS FOR BIOMEDICAL APPLICATIONS ... 20 2.1 Biomedical Applications ................................ ................................ ................................ .. 20 2.2 Passive Transponder Building Blocks for Biomedical Applications ............................... 20 2.3 Powering Strategies ................................ ................................ ................................ .......... 22 2.3.1 Near Field Inductive Link ................................ ................................ ....................... 24 2.3.2 Far Field Wireless Power Link ................................ ................................ ............... 26 2.3.3 Capacitive Coupling ................................ ................................ ................................ 28 2.3.4 Galvanic Coupling ................................ ................................ ................................ ... 28 2.4 Communications ................................ ................................ ................................ ............... 29 2.4.1 Back scattering ................................ ................................ ................................ ......... 29 2.4.2 Active Transmitting ................................ ................................ ................................ 29 2.4.3 Signaling ................................ ................................ ................................ .................. 30 2.5 Regulati on ................................ ................................ ................................ ......................... 32 2.5.1 ISM Bands ................................ ................................ ................................ ............... 33 2.5.2 Power Regulation ................................ ................................ ................................ .... 33 3 POWE RING CIRCUTIS ................................ ................................ ................................ ........ 43 3.1 Motivation ................................ ................................ ................................ ........................ 43 3.2 Rectifier Circuits ................................ ................................ ................................ .............. 44 3.3 Diode Devices ................................ ................................ ................................ .................. 45 3.3.1 P N Diodes ................................ ................................ ................................ .............. 45 3.3.2 Diode Connected MOS ................................ ................................ ........................... 45 3.3.3 Schottky Diode ................................ ................................ ................................ ........ 46 3.4 RF DC Voltage Multiplier ................................ ................................ ............................... 47 3.4.1 Basic Operations ................................ ................................ ................................ ...... 47 3.4.2 Analysis and Design Procedure ................................ ................................ ............... 48 3.5 Antenna Consideration ................................ ................................ ................................ ..... 52 3. 6 Transponder Sensitivity ................................ ................................ ................................ .... 53

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6 3.7 Experiments ................................ ................................ ................................ ...................... 53 3.7.1 Schottky Diodes ................................ ................................ ................................ ...... 53 3.7.2 HF Voltage Multiplier ................................ ................................ ............................. 55 3.7.3 RF DC Multiplier ................................ ................................ ................................ .... 55 4 A 0.3 V, 200 NW DIGITAL PHASE LOCKED LOOP AND A DUAL SUPPLY OUTPUT RF DC VOLTAGE MULTIPLIER FOR UHF PASSIVE TRANSPONDERS .... 72 4.1 Motivation ................................ ................................ ................................ ........................ 72 4.2 System Arc hitecture ................................ ................................ ................................ ......... 74 4.3 Circuit Implementation ................................ ................................ ................................ ..... 75 4.3.1 Sub Threshold Digital PLL ................................ ................................ ..................... 75 4.3.2 RF DC Power Management Unit ................................ ................................ ............ 77 4.3.3 Demodulator ................................ ................................ ................................ ............ 79 4.4 Experimental Results ................................ ................................ ................................ ........ 81 5 A SUPPLY MODULATED TRANSPONDER ................................ ................................ ..... 92 5.1 Motivation ................................ ................................ ................................ ........................ 92 5.2 System Architecture ................................ ................................ ................................ ......... 92 5.3 Circuit Implementation ................................ ................................ ................................ ..... 94 5.3.1 AC Logic Circuit ................................ ................................ ................................ ..... 94 5.3.2 Frequency Divider ................................ ................................ ................................ ... 94 5.3. 3 Oscillator Design ................................ ................................ ................................ ..... 95 5.3.4 Transmitter ................................ ................................ ................................ .............. 96 5.4 Antenna Design ................................ ................................ ................................ ................ 98 5.5 Experimental Results ................................ ................................ ................................ ........ 98 6 A BATTERY ASSISTED TRANSPONDER ................................ ................................ ...... 109 6.1 Motivation ................................ ................................ ................................ ...................... 109 6.2 System Architecture ................................ ................................ ................................ ....... 110 6.3 Circuit Implementation ................................ ................................ ................................ ... 110 6.3.1 AC/DC DC Converter ................................ ................................ ........................... 110 6.3.2 Receiver Circuit ................................ ................................ ................................ ..... 111 6.3.3 Transmitter ................................ ................................ ................................ ............ 112 6.4 Experi mental Results ................................ ................................ ................................ ...... 112 7 CONCLUSION ................................ ................................ ................................ ..................... 122 7.1 Summary ................................ ................................ ................................ ......................... 122 7.2 Future Work ................................ ................................ ................................ .................... 123 LIST OF REFERENCES ................................ ................................ ................................ ............. 125 BIOGRAPHICAL SKETCH ................................ ................................ ................................ ....... 130

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7 LIST OF TABLES Table page 2 1 Maximum permissible exposure ................................ ................................ ........................ 42 2 2 MPE for the general public for dif ferent frequiencies ................................ ....................... 42 3 1 Summary of measured Schottky diode performance in AMI C5 process ......................... 71 3 2 Summary of measured Schottky diode p erformance in UMC 130 nm CMOS process .... 71 4 1 PLL performance comparison ................................ ................................ ............................ 91 4 2 Chip performance summary ................................ ................................ ............................... 91 4 3 On c hip clock performance comparison ................................ ................................ ............ 91 5 1 Summary of supply modulated transponder performance. ................................ .............. 108 6 1 Summary of the proposed transponder performance. ................................ ...................... 121

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8 LIST OF FIGURES Figure page 1 1 A wireless passive microsystem for neurosignal measurement. ................................ ........ 19 1 2 Functional block diagram of a wireless passive microsystem. ................................ .......... 19 2 1 Simplified schematic of an inductive link and equivalent circuit. ................................ ..... 35 2 2 Simplified schematic of far field powering link and equivalent circuit. ........................... 36 2 3 Body transmission systems for external devices using capacitive coupling. ..................... 36 2 4 Body transmission systems for external devices using galvanic coupling. ....................... 36 2 5 A simplified block diagram of a backscattering system. ................................ ................... 37 2 6 A simplified blo ck diagram of an active transmitting system. ................................ .......... 37 2 7 The waveform of ASK modulation. ................................ ................................ ................... 38 2 8 The constellation diagram of OOK modulation. ................................ ................................ 38 2 9 The waveform of FSK modulation. ................................ ................................ ................... 38 2 10 The constellation diagram of FSK modulation. ................................ ................................ 39 2 11 The waveform of PSK modulation. ................................ ................................ ................... 39 2 12 The constellation diagram of PSK modulation. ................................ ................................ 40 2 13 The waveform of OOK PWM modulation. ................................ ................................ ....... 40 2 14 The waveform of OOK PIE modulation. ................................ ................................ ........... 41 2 15 The waveform of OOK PPM modulation. ................................ ................................ ......... 41 3 1 Re ctifier circuits. ................................ ................................ ................................ ............... 58 3 2 Block diagram of a typical wireless power interface frontend for biomedical implants. ................................ ................................ ................................ ............................. 58 3 3 Cross sect ion and layout of n type Schottky di ode with guard ring and n type Schottky diode without guard ring. ................................ ................................ .................... 59 3 4 One stage voltage doubler. ................................ ................................ ................................ 59 3 5 The schematic of three stage full wave RF DC converter. ................................ ............... 60

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9 3 6 The analysis of N stage RF DC multiplier. ................................ ................................ ....... 60 3 7 Charge conservation in steady state. ................................ ................................ .................. 61 3 8 Measured I V of P type Schottky diode. ................................ ................................ ........... 61 3 9 RF DC multiplier design for V OUT =1 V and I OUT =2 A. ................................ ................. 62 3 10 RF DC multiplier design for V OUT =0.5 V and I OUT =4 A. ................................ ............... 62 3 11 Schottky diode layout and measured Schottky diode current density vs. bias voltage in AMI 0.6 m CMOS process. ................................ ................................ ......................... 63 3 12 Schottky diode layout and measure d Schottky diode current density vs. bias voltage in UMC 130 nm CMOS process. ................................ ................................ ....................... 63 3 13 Die photo of the three stage full wave HF voltage multiplier. ................................ .......... 64 3 14 The measured multiplier output voltage vs. frequency. ................................ ..................... 64 3 15 RF DC multiplier design for V OUT = 1 V and RLOAD = 217 k ................................ ... 65 3 16 Die photo of the 16 stage half wave RF DC multiplier. ................................ ................... 65 3 17 The measured and simulated multiplier output voltage vs. input power. .......................... 66 3 18 Input impedance vs. input power. ................................ ................................ ...................... 66 3 19 Input impedance vs. input frequency. ................................ ................................ ................ 67 3 20 Input impedance vs. input frequency on Smith chart. ................................ ....................... 67 3 21 Matching network design. ................................ ................................ ................................ .. 68 3 22 The RF DC multiplier with input matching network. ................................ ....................... 68 3 23 Input impedance vs. input frequency with input matching network o n Smith chart. ........ 69 3 24 Input impedance vs. input power for 10 dBm input power at 217 k ............................ 69 3 25 The measured multiplier output voltage vs. input power. ................................ ................. 70 3 26 The measured multiplier output power conversion efficiency vs. input power. ................ 70 4 1 Functional block diagram of RFID transponder. ................................ ............................... 83 4 2 Simplified block diagram of the demodulator and the timing waveform of operation. .... 83 4 3 Functional block diagram D PLL and DCO. ................................ ................................ ..... 84

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10 4 4 Power management unit. ................................ ................................ ................................ .... 84 4 5 Functional schematic of the proposed RF DC power management unit. .......................... 85 4 6 Functional schematic of the voltage reference and voltage regulator L DOL ...................... 85 4 7 Functional schematic of the ASK demodulator. ................................ ................................ 86 4 8 Functional schematic of the proposed data slicer. ................................ ............................. 86 4 9 Die photo of the proposed RFID transponder. ................................ ................................ ... 87 4 10 The measured jitter performance with battery supply. ................................ ...................... 87 4 11 The measured jitter performance of free running DCO with battery supply. .................... 88 4 12 The measured jitter performance with RF source powered. ................................ .............. 88 4 13 The measured phase noise of the DPLL with RF source powered. ................................ ... 89 4 14 Measured recovered clock and DPLL output. ................................ ................................ ... 89 4 15 Measured backscattering modulated sideband spectrum for M*N = 64. ........................... 90 4 16 The measured unregulated output, VDD H and regulated VREG H and VREG L voltages of the PMU versus input power. ................................ ................................ .......... 90 5 1 Conventional passive transponder building blocks diagram. ................................ .......... 100 5 2 Proposed supply modulated transponder input and output waveform. ............................ 100 5 3 Proposed AC supply modulated transponder building block diagram. ........................... 100 5 4 Schematic of AC inverter. ................................ ................................ ................................ 101 5 5 The schematic of the AC supply RS register. ................................ ................................ .. 101 5 6 AC supply RS register design. ................................ ................................ ......................... 102 5 7 Simulated results of the AC supply RS register. ................................ .............................. 102 5 8 Schematic of NMOS transistor cross coupled ring oscillator. ................................ ......... 103 5 9 Simulation results of the oscillator frequency with AC supply voltage. ......................... 103 5 10 Schematic of class D power amplifier. ................................ ................................ ............ 104 5 11 Class D power amplifier sizin g. ................................ ................................ ...................... 104 5 12 The 3 D drawing of the proposed supply modulated tag. ................................ ................ 105

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11 5 13 The 3 D plot of the antenna on the Pyrex substrate. ................................ ........................ 105 5 14 Simulated antenna impedance. ................................ ................................ ......................... 106 5 15 The simulated antenna radiation pattern. ................................ ................................ ......... 106 5 16 Chip microphotograph of the supply modulated transponder. ................................ ........ 107 5 17 The measurement setup for the proposed transponder. ................................ ................... 107 5 18 Measured time domain waveforms on an oscilloscope. ................................ .................. 108 5 19 Measured output signal using signal analyzer. ................................ ................................ 108 6 1 Functional block diagram of the proposed transponder. ................................ .................. 115 6 2 Schematic of the proposed ac/dc dc converter and voltage level detector. ..................... 115 6 3 Schematic of t he receiver circuit. ................................ ................................ ..................... 115 6 4 Timing diagram of the input signal and recovered clock from the clock recovery block in two modes. ................................ ................................ ................................ ......... 116 6 5 Schematic of the transmitter. ................................ ................................ ........................... 116 6 6 The photograph of the proposed transponder. ................................ ................................ 117 6 7 The measurement setup for the proposed transponder. ................................ ................... 117 6 8 Measured input power vs. output voltage of the proposed AC/DC DC converter. ......... 118 6 9 Measured reverse leakage current vs. output voltage of the proposed AC/DC DC converter. ................................ ................................ ................................ ......................... 118 6 10 Measured timing waveforms of the output voltage of the converter and transponder. ... 119 6 11 Measured input signal, envelope output, output data pattern and transponder output using inductive couple powering. ................................ ................................ .................... 119 6 12 Measured input signal, envelope output, output data pattern and transponder output using battery powering. ................................ ................................ ................................ .... 120 6 13 Measured output signal using signal analyzer. ................................ ................................ 120 6 14 M easured number of output pulses vs. battery voltage ................................ .................... 120

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12 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial F ulfillment of the Requirements for the Degree of Doctor of Philosophy ULTRA LOW POWER PASSIVE TRANSPONDERS FOR BIOMEDICAL MICROSYSTEMS By Chun Ming Tang August 2013 Chair: Rizwan Bashirullah Major: Electrical and Computer Engineering This dissertation examines several aspects of designing high efficiency and low power building blocks for passive microsystems used in biomedical appli cations To reduce losses in the power conversion in voltage multiplier, the architecture implements s everal types of Schottky diodes on standard CMOS processes. The Schottky diode provides a lower turn on voltage which minimizes the loss es associated with the forward biased voltage drop. V characteristics, this dissertation p roposes a new RF DC voltage multiplier design procedure This design method provides a n overview of the voltage design par ameters includi ng the diode sizing number of stages, the RF DC voltage input impedance, matching b etween antenna s and power conversion efficiency. A new calibration free low power clock generator is also presented. This clock generation sch eme provides a clock frequency that is more stabl e against process temperature, and voltage variation s This allow s more reliable data decoding and encoding. Add itionally, this dissertation also proposes a dual power supply RF DC power management unit to minimize the clock generator power consumption and to improve the overall DC DC voltage conversion efficiency.

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13 A novel passive transponder architecture is proposed which minimize s overall chip area All building blocks in the proposed transponder are designed to be ope rated from an AC power supply With this architecture, the AC power supply not only powers the transponder but also provides a clock signal for the chip This allows the architecture to eliminate area consu mi ng building blocks such as an RF DC multiplier, a decoupling capacitor, a voltage regulator, and a power on reset circuit Finally, a battery assisted transponder is presented. The transponder can use take the DC voltage at the input to improve the sensitivity A radio transmitter is used in this proposed transponder to improve the communication range. The transponder can also operate by harvesting energy from electromagnetic wave if the DC vol tage is not available at the input The proposed transponder has both advantages of the active and passive transponder architectures.

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14 CHAPTER 1 1 I NTRODUCTION 1.1 Motivation A dvance s in m icroelectronics have allowed wireless system s to perform compli ca ted tasks while minimizing power consumption To date, researches have explored using wireless microsystems mainly in healthcare and biomedical applications. Applications have included implantable devices, medication compliance improvement, neuromuscular stimu lation, and biological signal monitoring [1, 2, 3, 4, 5, 6] Devices for these uses must meet strict technical parameters, such as requirements on physical size, power consumption, heat generat ion, and operational lifetime Because of these constraints, m icrosystem s for biomedical appl ication s must have low power consumption, high power conversion efficiency long life span and they must be small F i gure 1 1 shows an example of a wireless microsystem for neurosignal measurement. The device is powered by an inductive link T he recorded d ata from the electrode array is amplified by a low noise ampl ifier digitized by an Analog to Digital converter and transmitted via a transmitter through the antenna to the external reader Wireless microsystems usually share many basic components and features. The basic components include a high efficiency externa l reader, an antenna (coil), a communication module, a power management module, a digital control unit, an analog frontend, and a sensor interface. Wireless transponders are classified into two categories depending on the power source they use: active and passive. An active transponder incorporates a battery into the microsystem, which provides the power necessary to perform the communication function to the reader and for the analog and digital blocks. A passive transponder harvests energy from the carrier transmitted microsystem has several advantages over active ones. For example, a passive microsystem is

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15 battery. The size of an active transponder is constrained due to the inclusion of a battery into the microsystem because the size of the battery has not been miniaturized to the micro scale. Moreover, passive microsystems provide a less invasive alternati ve for wireless implant devices, and thus reduce the risk of infection. All things considered, passive microsystems are more cost effective overall and more suitable for biomedical applications. However, passive microsystems do suffer from several fundamen tal performance issues, including low power conversion efficiency in the energy harvest circuit and clock drifting of the on chip clock generator due to process, voltage, and temperature variations (PVT). The power efficiency of a passive microsystem is cr ucial [7] Consider powering a passive not only increases the tissue temperature but also requires a denser electromagnetic field th rough the tissues for power up. To avo id damage due to heat and electromagnetics, the device needs a passive microsystem with high power efficiency. To achieve this, the energy harvester must provide high power conversion efficiency, and the power consumpt ion of building blocks in the microsystem must be minimized. To provide reliable communication between the reader and the passive transponder, the 1 generation 2 RFID protocol requir es the frequency drift and short term frequency variation to be less +/ 2.5% during backscattering [8] However, the on chip generator suffers process, voltage, and temperature (PVT) variations that can result in frequency variation as large as +/ 20% [9, 10] A higher clock frequency lowers the bit error rate, but thi s results in increased power consumption.

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16 The challenges to clock generator design are how to achieve low power consumption and free of trimming process to tune the target frequency to reduce the cost. 1.2 Research Goals For certain biomedical applications pas sive microsystems have several advantages over active approaches. This research focuses on passive microsystems. The first research goal is to provide a power efficient RF frontend for the passive microsystem that minimizes the system size for biomedical a pplications. Figure 1 2 d by the power consumption achieve high power conversion efficiency, the optimization procedure of the RF DC multiplier for a given power load needs to be developed The voltage regulator that follows after the RF DC multiplier must also be efficient. To minimize the losses associated with the rectifying diode in the RF DC multiplier, different diode structures that can be implemented in a standard CMOS process will be investigated. The second goal of this research is to provide a stable clock signal on the transponder while minimizing power consumption. Different commonly used clock generators for passive microsystems are surveyed. A clock generator architecture that can use a wirelessly received reference clock is investigated. The third goal of this research is to minimize the size of the passive microsystem. The advantages of a small passive transponder chip are low cost and small form package. 1.3 Thesis Organization In Chapter 2, we review passive transponders used for biomedical applications and study the basics of building blocks. Next we investigate communication channels, including free space

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17 and in body. After this, we present various powering strategies: far fil ed powering, inductive coupling, capacitor coupling, and galvanic coupling. Finally, we examine the uplink and downlink communications between reader and tag. We compare the active transmission and backscattering modulation for uplink communication. For do wnlink, we review other modulation methods. Chapter 3 discusses the design methodology for the diode based RF DC voltage multiplier and describes key specifications for the passive microsystem. For a given loading specification, the proposed design proce dure can provide the required diode and capacitor size while achieving high power conversion efficiency. Chapter 3 also presents the implementation of Schottky diodes in a standard CMOS process. Several types of Schottky diodes are designed, fabricated, an d measured. We then measure and compare the performances of RF DC voltage multipliers with different rectifying diodes. Chapter 4 presents a scheme to efficiently generate dual regulated supply voltages from a single RF DC converter block, supporting a low voltage for the digital processing at V REGL ~260 mV and a higher voltage for the analog circuits at V REGH ~725 mV. We also demonstrate a ~200 nW on chip clock generator, which is based on a digital phase locked loop (DPLL) operating in the subthreshold region. This clock synchronizes communication functions between the reader and the passive transponder. Chapter 5 describes a novel passive transponder architecture that minimizes the chip area. We propose and implement a supply modulated passive microsys tem for medication compliance. The input AC signal powers the proposed chip directly, thus avoiding the need for area consuming blocks such as a RF DC multiplier, a decoupling capacitor, power on reset circuitry, and voltage regu lator. The system uses a lo w frequency carrier (125 kHz) as the power supply

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18 and system clock, and it transmits data through a high frequency carrier (915 MHz) when the transponder, such as the A C logic, the voltage divider, and the low power UHF oscillator, are designed and measured. Chapter 6 presents a new transponder architecture Th e proposed chip can provide AC/DC or DC/DC conversion in the energy harvester It can us e a coil to receive data and system clock, and uses DC voltage to power the chip It also can harvest energy from the electromagnetic waves. d results are shown in chapter to demonstrate the idea. Chapter 7 summari zes this work and lists the future work necessary to complete this dissertation.

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19 F i gure 1 1 A wireless passive microsystem for neurosignal measurement. Figure 1 2 F unctional block diagram of a wireless passive microsystem

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20 CHAPTER 2 2 OVERVIEW OF PASSIVE TRANSPONDERS FOR BIO MEDICAL APPLICATIONS P assive wireless transponders provide more advantages than active transponder s in biomedical applications. In this chapter, we review the published passive transponder s that are used in various biomed ical applications. Here we discuss several widely used powe ring methods of powering passive transponders: near field inductive couplin g, far field electromagnetic coupling, capacitive coupling and galvanic coupling. We also review the most widely adopted communications schemes used in passive transponders. The se modulation methods provide different characteristics for powering and power consumption of the demodulator and modulator. Finally, safety must also be considered for passive transponder used in biomedical applications This chapter presents two exposure limitations from IEEE standards. 2.1 Biomedical Applications Passive transponders have found a broad range of uses in bio medical applications including neural signal recording [11] tear glucose measurement [12] body temperature monitoring [13] and retinal prosthe tic devices [14, 15] Different applications employ different power ing and communication methods depending on the where the transponder is located and the channel characteristics. 2.2 Passive Transponder Bu ilding Blocks for Biomedical Applications The building blocks of the passive transponder for biomedical application s include an energy harvest er voltage regulator, voltage limiter, demodulator, clock generator, modulator, analog to digital converter, sensor interface, and antenna. To obtain the power necessary to operate the transponder, the energy harvester converters the external AC carrier to DC voltage on a c apacitor. Several factors determine the amount of

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21 power the transponder receives: the amoun t of power transmitted from the reader, the channel loss, the transponder antenna gain, the matching between antenna and transponder, and the power conversion efficiency. In near field coupling, a diode bridge rectifier is widely used du e to the large power transfer it provides In far field coupling the received signal amplitude is usually smaller than near field coupling When the input signal amplitude is close to the turn on voltage, a diode bridge rectifier encounters high voltage conversion loss that causes the transponder to have very low sensitivity. To avoid this, a RF DC multiplier is widely employed in far field passive transponder s At the output of the energy har vester, output l oad and input power level affect the output voltage ripple Although the decoupling capacitor can be increased to reduce the output voltage ripple, this increase s c hip area and cost. Moreover, building blocks, such as a clock generator, sensor analog frontend, and ADC, are required precise supply voltage to maintain operation To meet this requirement, we incorporate t he voltage reference and voltage regulator into the passive transponder design. A linear series regulator can provide several advantages over the switching mode voltage regulator, such as low er noise, a small area, and high speed. The linear series regulator is widely used in passive transponder s [16, 17] The demodulator and modulator are used to communicate betwee n the reader and transponder Their functions include data decoding, data encoding calibration and synchronization. Their power consumptio n and circuit complexity depend on the modulation scheme. The on off keying enables the use of a simple demodulator and modulator design an approach that is widely used in passive wireless transponder s [18] The clock generator provides the clock for the baseband unit data decoding and encoding function for downlink and uplink. The

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22 An LC tank oscillator provides an accurate clock and less sensitivity to PVT variation s but it requires a larger area For applications that require a small area and low power consumption, both the c urrent starved ring oscillator and the relaxation oscillator are widely used However, these types of oscillators are prone to PVT variation s The sensor analog frontend provides the input signal conditioning. The building block depends on the type of sens or and application. A low noise amplifier is a typical choice for neural signal recording application s There is a tradeoff between noise performance and power consumption. To achieve low power while providing required noise performance in the amplifier, s everal techniques have been explored [19, 20, 21] including time multiplexing, bias current reuse, and supply current modulation. For biomedical applications, the ADC is essential It convert s the input signal to digital format for the modulator. In passive transponder s which ADC architecture to use is usually limited by the stringent power budget. Because of this, successive approximation register (SAR) ADCs are widely used for biomedical app lications [22, 23] P ipeline converters may be required for some high speed biomedical systems. As for the antenna, it converts captured electromagnetic w aves to AC voltage for the energy harvester and converts AC signal s to electromagnetic waves for the external reader. The dimension s of the antenna impose a challenge on the passive transponder design If the antenna is electrically small, very inefficient however its maximum size is limited by the operating carrie r frequency, the size of the implant site, and impedance matching 2.3 Powering Strategies Passive microsystem s harvest power from electromagnetic waves transmitted by the reader. Two widely used power ing approaches are near field inductive coupling and far field

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23 electromagnetic coupling If the antenna size is compatible with the wavelength (UHF/Microwave RFID) the boundary between near field and far field is given by r = 2D 2 / where D is the maximum antenna size and r is the wavelength. However, for e lectrically small antennas (LF/HF RFID and biomedical applications), t he boundary between near field and far field is defined as where is wavelength [24, 25] The near field frequency usually ranges from one hundred kHz to ten Mhz. Near field coupling is less susceptible to absorption by human body tissue than the far field coupling. As a result near field coupling is widely used in wireless implant. Far field coupling is used more often with ultra high frequencies (UHF) and microwave frequencies, such as ISM 900 MHz and 2.4 GHz bands. Nevertheless studies of bioelectricity show useful alternatives to both near field magnetic coupling and far field RF powering as a means of energiz ing a passiv e device inside the body (Galvani, Volta, Faraday, etc. ). The human body supports current flow via the intra cellular and cellular membranes, and the resulting impedance between two points in the body is a complex function of frequency, tissue type, organ s, geometry and distance. A significant amount of literature studies and assesses bioelectricit y and equivalent tissue models [26, 27, 28] Gabriel [29] gives a very thorough review of tissue permittivity and conductivity While these models and studies provide excellent explanations of the pathways electrical current takes through the human body, the most relevant information for establishing the human body as a direct transmission c hannel between two or more devices within or on the body is the frequency dependent signal attenuation characteristics among these nodes. These characteristics, in turn, depend both on the method of coupling the signals into the body and the human body cha nnel characteristics. The remainder of this section presents and studies the various powering strategies

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24 2.3.1 Near F ield Inductive Link The near field link can be modeled using two closely spaced inductively coupled coils. The primary coil is in the external reader and the secondary coil is in the implant device. U sually the two are several millimeters to tens of millimeters apart. In this approach, normally both sides of the coil are tuned to the same resonant frequency to maximize the power transmission effi ciency. To maximize the power conversion efficiency from the DC power supply to magnetic fields, designers often use the Class E power amplifier to drive the reader coil. If the magnetic field on the primary coil (L 1 ) induces an AC voltage on the secondar y coil (L 2 ) then the AC voltage can be rectified and regulated to supply the implanted device. Assume the coils are parallel and center aligned. The induced AC voltage is determined by the coils coupling coefficient (k), where is k is 0 < k < 1 and dimen sionless. k can be defined by (2 1) w here M is the mutual inductanc e. Figure 2 1 shows a simplified schematic of an inductive link and the equivalent RLC network. The resistor R 1 is the combination of the effective series resistor (ESR) of L 1 and the output resistor of the power amplifier T he resistor R 2 is the effective series resistor (ESR) of L 2 RL represents the loading effect from the rectifier, the LDO, and the output load. The capacitor s C1 and C2 are used to resonate the primary and secondary coil at frequency f 0 The frequency f0 is given by (2 2 ) The entire system efficiency can be presented as in an equivalent RLC circuit. The entire inductive link efficiency IND is given by

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25 (2 3 ) w PA T is the primary coil power conversion R RECTIFIER is the LDO is the LDO power conversion efficiency. R is given by (2 4 ) w here Q 2 = 0 L 2 /R 2 is the quality factor of the unloaded secondary coil and Q L = 0 L 2 C 2 Next we find the primary coil power conversion efficiency W e can convert the weak coupling between the primary and secondary coil as an ideal transformer and two inductors L T1 and L T2 [30] L T1 and L T2 can be expressed as L 1 (1 k 2 ) and L 1 k 2 respectively. Then reflecting the R and C into the ideal transformer, the C REFL and R REFL are expressed as C REFL =(C 2 / k 2 )(L 2 /L 1 ) and R REFL =( k 2 L 1 / L 2 )(R L //Q 2 2 R 2 ). L T2 and C REFL are resonated, and then the equivalent circuit can be simplified to Figure 2 1 T is given by (2 5 ) where Q 1 = 0 L 1 /R 1 If a full RECTIFIER is given by ( 2 6 ) w here V RECT is the rectifier output voltage and V DIODE is the diode voltage drop. LDO is given by

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26 ( 2 7 ) As a result, t he efficiency of the inductive power link IND is presented as a simple form by given the required load of t he implanted device. To improve the overall frequency, equation 2 3 and 2 4 should be maximized. If Q L increases, T decrease s and R increase s By differentiating equation 2 4 and 2 5 there is an existing optimum Q L which maximizes the overall efficiency. From equation 2 6 to 2 7 to maximize the overall efficiency the diode drop voltage V DIODE should be minimized and the dropout voltage in the LDO should be reduced. 2.3.2 Far Field Wireless Power Link Far field powering occu rs at high frequencies. The path loss in the air is inversely proportional to the distance between the transponder and the reader. Because of this, at high frequencies, the system can have small antenna size and long communication link (several meters). Ho wever, unlike near field coupling, far field coupling usually generates less than a couple hundred millivolts. A RF DC multiplier is usually used to generate the DC voltage required for the IC. The communication distance is determined by the maximum power transmitted from the reader, the antenna radiation resistance, input matching, and tag sensitivity. The incident power captured by the antenna is given by [31, 32, 33] (2 8 ) where P READER is the amount of power the reader delivers to the antenna, G READER is the gain of the reader, r is the distance, and is wavelength of the carrier. Figure 2 2 shows a simplified schematic of far field powering and the equivalent circuit of the antenna and the RF DC

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27 multiplier. If the antenna and RF DC multiplier are conjugat e matched, the input power available for the RF DC multiplier is P TAG /2. The efficiency of the RF DC multiplier can expressed as (2 9 ) where P OUT is the DC output load power of the RF DC multiplier. By given P OUT P READER G READER and G TAG from equation 2 7 and 2 8 the higher RF DC efficiency and conjugate matching can increase the communication distance. If the required input voltage for the RF D C multiplier based on a given load is V IN then we can derive the distance at which the transponder can be powered. The induced open circuit voltage on the antenna is given by (2 10 ) where R A is radiation resistance. If the input of the RF DC multiplier can be modeled as resistor R IN this condition assumes the reactance components are cancelled by matching. V IN is expressed as (2 11 ) From equation 2 10 and 2 1 1 we see that a high radiation resistance of the antenna is favored. If we want maximum power delivery, R IN must equal R A To conclude, the communication distance of a far field passive transponder can be increased by a lower output power P OUT a conjugate matching network, a high radiation resistance of the tag antenna, and high input impedance of the RF DC multiplier.

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28 2.3.3 Capacitive Coupling Figure 2 3 shows a simplified schematic of the capacitive body transmissions methods. Capacitively coupled body transmission systems exploit the capacitive coupling between the body and its environment to establish signal pathways between a source and a detector in close proximity to the body [34] The transmitter and receiver, each with two electrodes, are coupled via electric field lines generated by the transmitter and ter minating at the receiver. Transmission predominantly uses the surface of the body as the propagation medium. Return pathways are established by the second electrode of each unit and the surrounding environment (or ground). Since the field lines generated b y the transmitter electrode escape through the body to ground and are partially cancelled by the localized return pathways and stray fields, only a small portion of the fields couple to the receiver. In addition, since the return pathways via ground play a n integral role in the overall transmission system, the signals detected at the receiver depend not only on the human body but also on its surrounding environment, which is subject to changing conditions. 2.3.4 Galvanic Coupling An alternative to capacitive cou pling is to directly couple signals into the body using a galvanic method, as shown in Figure 2 4 [35, 36] Similar to the capacitive approach, galvanic transmission relies on a transmitter and receiver, each with two electrodes, coupled via transmission of alternating currents through the body and/or over the body surface using electrodes in direct contact with the skin. Current flow, generated by a differential alternating voltage across the transmitter electrodes, is primarily between these electrodes. A portion of the current, however, reaches the receiver to create a detectable differential voltage acro ss the receiver electrodes. This method of transmission depends primarily on the human body channel

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29 instead of the surrounding environment (ground) or air to couple the transmitter and receiver via electrical conduction supported by ionic fluids within the body. 2.4 Communications The downlink communication uses data modulation schemes into the carrier. Three modulation schemes are widely used, ASK, FSK, and PSK. The uplink communication between the reader and the tag is based two methods: one is backscatterin g and the other is to use different frequency carrier transmitting the data. This section discusses the communication between the reader and tag. 2.4.1 Backscattering Backscattering switches the state of the matching between the antenna and the tag to communicat e with the reader. The tag and antenna are designed to be conjugate matched to deliver maximum power. During matched condition, there is no power being reflected. On the other hand, if there is a switch shorted the antenna to ground. The power is reflected and part of power is reflected to the reader antenna. This backscattering method has very low power consumption in the modulator because it reflects power back and can use a low frequency clock generator to modulate the switch [37 ] limited range. The reflected signal experiences the same path loss as incoming signal. As a the re ader receiver sensitivity. The clock frequency is a tradeoff between power and the channel receiver selectivity. Figure 2 5 shows a simplifie d block diagram of a backscattering system. 2.4.2 Active Transmitting This active transmitting architecture uses a higher frequency oscillator and transmitter to deliver signal out of the tag. The modulator employs a simple modulation scheme (OOK) to

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30 directly mo dulate the oscillator and minimize power consumption. In this case, the oscillator turns on or off based on the baseband data. The uplink frequency can be different from the downlink carrier frequency. The advantage of this approach is that it has a longer range than the backscattering approach since the uplink signal only encounter one way path loss. However, it has higher power consumption because the high frequency oscillator resides in the tag. One way to reduce the average power consumption is to send the output signal at very short time and then to accumulate energy on a large capacitor. Figure 2 6 shows a simplified block diagram of an active transmitting system. 2.4.3 Signaling This section reviews the modulation schemes for passive transponder systems. Complex modulation schemes, such as quadrature phase shift keying (QPSK), minimum shift keying (MSK), and Gaussian MSK (GMSK) [38] are widely used in RF communication to improve the bit error rate and data rate. However, the strict power restrictions on passive transponders prevents compatibility with complex modulation scheme s. 2.4.3.1. Amplitude shift keying (ASK) symbol of an ASK digital bit stream can be expressed as (2 12 ) C is the carrier frequency. The modulation index M in given by (2 13 )

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31 where A 1 is the amplitude when the data is 1 and A 0 is the a mplitude when the data is 0. If M is equal to 1, then the modulation is on off keying. Figure 2 7 shows the waveform of ASK modulation. Figure 2 8 shows the constellation dia gram of OOK. The OOK method is most widely used modulation scheme in passive transponders due to the simple modulator and demodulator and its low power consumption. 2.4.3.2. Frequency shift keying (FSK) The FSK method modulates the amplitude of the carrier with th e digital date stream. The symbol of an FSK digital bit stream can be expressed as (2 14 ) C Figure 2 9 shows the waveform of F SK modulation. Figure 2 10 shows the constellation diagram of FSK. FSK less popular than the OOK scheme because it requires a more complicated modulator and demodulator. This increases the power consumption of the pass ive transponder. FSK, however, provides continuous power to the tag unlike OOK, which provides power only when the data symbol is 1. 2.4.3.3. Phase shift keying (PSK) The PSK method modulates the amplitude of the carrier with the digital date stream. The symbol of an FSK digital bit stream can be expressed as (2 15 ) C is the carrier frequency. The is 0 when the data is 0, and is a constant phase wh en the data is 1. Figure 2 11 shows the waveform of PSK modulation. Figure 2 12 shows the constellation d iagram of PSK. PSK is less popular than the OOK scheme because, like FSK, PSK requires a more complicated modulator and demodulator.

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32 This increases the power consumption of the passive transponder. Also like FSK, PSK provides continuous power to the tag un like OOK, which provides power only when the data symbol is 1. 2.4.3.4. OOK with pulse width modulation (PWM) This modulation scheme uses different duty cycles, on time and off time, to encode data. A non coherent demodulation scheme can be implemented to further l ower the power consumption in the modulator. OOK PWM, unlike regular OOK, can encode the clock information into the carrier. A simple clock and data recovery circuit can exact the clock and data for the passive transponder. However, this scheme also suffer s from non continuous power transfer. Figure 2 13 shows the OOK PWM waveform. 2.4.3.5. OOK with pulse interval encoding (PIE) OOK PIE is similar to PWM. The modulation uses the same off time but different on time to encode the data 0 and data 1. This modulation scheme is widely used in the EPC protocol. This scheme also suffers from non continuous power transfer. Figure 2 14 shows the OOK PIE waveform. 2.4.3.6. OOK with pulse position modulation (PPM) This modulation scheme uses a short pulse with different locations to encode data. Adding in PPM provides a better continuous power delivery, which is beneficial to the passive transponder. Figure 2 15 shows the OOK PPM waveform. 2.5 Regulation In this section, we discuss some power regulations and frequency bands for biomedical applications.

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33 2.5.1 ISM Bands The communication for the tag and the reader usually use ISM (industrial, scientific, and medical) bands. The widely used ISM bands are 13.553 13.57 MHz, 902 928 MHz, 2.4 2.485 GHz, and 5.725 5.850 GHz [39] 2.5.2 Power Regulation In order not interfere with other communication protocols, Part 15 of the FCC Rules regulate the maximum power that can be transmitted by the reader. There are three limits: Maximum transmitter output is 1 W (30 dBm). Maximum EIRP is 4 W (36 dBm), i.e. for every dB of antenna gain above 6d Bi, transmitter output must be reduced by 1 dBm; per this rule, a 24 dBi antenna limits the output power to 12 dBm which is 16mW. For fixed point to point operation in ISM2.4, peak output need only be reduced by 1 dBm for every 3 dBi of antenna gain above 6, i.e. per this rule, a 24 dBi antenna may be fed by 24 dBm or 250 mW. In ISM5.8, The gain can apply all the antenna gain with no reduction in output power. Electromagnetic fields generated by the telemetry system can lead to heat generation in body tissu e and cause damage. Hence, there is a limit on the maximum power a human body can be exposed to. One well known and widely used IEEE standard fixes the level of human exposure to radio frequency electromagnetic fields as safe from 3 kHz to 300 GHz. For fre quencies between 100 kHz and 3 GHz, frequencies widely used in passive transponders, basic restrictions (BRs) are expressed in terms of specific absorption rate (SAR). The SAR is primarily determined by the E field and is related it to by (2 1 6 )

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3 4 3 ), and E is the rms electric field strength (V/m) in tissue [40] In situations where calculating the SAR is difficult, the maximum permissible exposures (MPE S ) are provided in the IEEE standards. Two issues need to be addressed. First, sometimes even when the SAR limited is met, the MPEs can still be exceeded. Second, in some environments when the body is close to an RF source, the MPEs may not ensure the SARs limits are complied with. Both standards are required to ensure safety.

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35 Figure 2 1 Simplified schematic of an inductive link and equivalent circuit

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36 Figure 2 2 Simplified schematic of far field powering link and equivalent circuit. Figure 2 3 Body transmission systems for external devices using capacitive coupling. Figure 2 4 Body transmission systems for external devices using galvanic coupling.

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37 Figure 2 5 A simplified block diagram of a backscattering system. Figure 2 6 A simplified block diagram of an active transmitting system.

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38 Figure 2 7 The waveform of ASK modulation. Figure 2 8 The constellation diagram of OOK modulation. Figure 2 9 The waveform of FSK modulation.

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39 Figure 2 10 The constellation diagram of FSK modulation. Figure 2 11 The waveform of P SK modulation.

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40 Figure 2 12 The constellation diagram of P SK modulation. Figure 2 13 The waveform of OOK PWM modulation.

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41 Figure 2 14 The waveform of OOK PIE modulation. Figure 2 15 The waveform of OOK PPM modulation.

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42 Table 2 1 M aximum permissible exposure General public SAR (W/Kg) In control led environments SAR (W/Kg) Whole body exposure Whole body average 0.08 0.4 Localized exposure Localized (peak spatial average) 2 10 Localized exposure Extremities a and pinnae 4 20 a The extremities are the arms and legs distal from the elbows and knees. Table 2 2 MP E for the general public for different frequiencies Frequency Range (MHz) RMS electric field strength (E) (V/m) RMS magne tic field strength (H) (A/m) 0.1 1. 34 614 16.3/f 1. 34 3 823.8 /f 16.3/f 3 30 823.8/f 16.3/f 3 0 100 27.5 158.3/f 1 00 4 00 27.5 0.0729

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43 CHAPTER 3 3 POWERING CIRCUTIS 3.1 Motivation Low power biomedical implant microsystems such as those used in drug delivery, glucose sensing neural recording and in stimulation devices are often p owered using close proximity low frequency inductive links or far field powering [41, 42, 43] Wireless sensors can be divided into three categories: active, semi passive, and passive sensors. Active and semi passive sensors are powered by a battery which increases the cost and size of sensors. I mplantable biomedical sensor s are usually constrained limited in their size and cost. Moreover, batter ies must be suitable for implant devices. P assive sensors are more attractive for these applications since they can operate without a battery. Instead, the DC power required to ope rate the passive sensor is generated by an integrated rectifier which converts the incident RF signal to DC supply. Most power interfaces for integrated biomed ical implants operating in the W to mW range employ RF DC converters based on p n junction diod es and diode conn ected MOS transistors Schottky barrier diodes offer an alternative to the p+ n well junc tion diodes or diode connected P MOS devices fabricated in a standard n well CMOS process. These Schottky devices exhibit higher oper ating frequencies and lower for ward voltage drop and have been extensively used in micro wave applications for rectification/detection and voltage mu ltipliers for RFID systems [44, 45] Unlike the standard p n junction based diodes, the S chottky barrier diode is a majority carrier device suffer from minority carrier storage effects and can therefore be switched faster. The fabrication of these diodes in a standard foundry CMOS process is of interest as it allows monolit hic integration with both analog and digital processing circuits.

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44 In this chapter we discuss the implementation of a S chottk y diode based RF DC multiplier for a wirele ssly powered analog front end 3.2 Rectifier Circuits The rectifier circuit convert s AC signal from transformer or power source into pulsating DC voltage. This circuit is generally classified into two types : Half wave rectifier: This circuit type is simply implemented by a diode as shown in Figure 3 1 (A) The diode allows one direction current to flow into the capacitor while blocking the other direction current flow. Full wave rectifier: This circuit type require s at least two diodes to perform full wave rectification as shown in Figure 3 1 (B) The full wave rectifier manipulates the incoming AC signal so that both halves are used to generate the output current flow in one direction. The full wave rectifier is more efficient than the half wave rectifier, because the half wave rectifier uses only half of the incoming ac cycle and wastes all of the energy availabl e in the other half. Rectifier circuits are widely used in inductive coupled circuits for wireless implants, because the magnetic field penetrates the biological tissue very well. However, the coupling distance is short (~ 10 50cm) because the magnetic fie ld strength is attenuated third power of distance in near field. The implant device operates by capturing AC signal from the external transmitter, which is amplified using a passive resonant tank and converted into useful DC power using an AC DC converter or rectifier. For a fixed reading distance, the efficiency of this converter is crucial in determining the overall system efficiency and power requirements. As shown in Figure 3 2 these wireless powering interfaces share a common framework that consists of a high efficiency external transmitter, a wireless link, and a full wave bridge rectifier, which is often followed by a linear regulator an d DC voltage limiter to ensure stable supply

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45 voltage and over voltage protection for the downstream on chip electronics in the presence of amplitude variations due to coil or antenna misalignments. 3.3 Diode Devices D iode devices are used to rectify the voltag e in the voltage multiplier. Ideally, w h en the diode is forward biased, the current flows from anode to cathode. W hen the diode is negative biased, it blocks the current flowing back. As the RF DC converter uses diodes, the voltage drop across them induces loss. Moreover, the rectifying devices have parasitic capacitances to the substrate, and those capacitances cause power loss, especially at high frequencies. The rectify ing devices can be implemented by different types of diodes in a CMOS process This section introduces and compares three commonly used rectify diodes. 3.3.1 P N Diodes A p n diode can be fabricated by doping opposite impurities to form the p and n region of the diode. The p n junction diode is widely used in rectifier design and is available in most CMOS processes without extra masks. However the p n junction diode is known as a minority carrier device since the current conduction is controlled by the diffusion of minority carriers (i.e. electrons in the p region and holes in the n r egion) in a p n junction diode. Therefore the p n diode exhibits slow switching speed. 3.3.2 Diode Connected MOS Another widely used method in CMOS is to connect the gate and drain of the MOS transistor and use it as a diode. There is one drawback to the diode c onnected NMOS, which is that it suffers body effect when the RF DC multiplier has multiple stages. This problem can be resolved by using PMOS. However, the choice to use NMOS or PMOS depends on the process.

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46 For instance, the NMOS transistor suffers body ef fect, but the threshold voltage can still be smaller than the PMOS transistor. 3.3.3 Schottky Diode Schottky contact barrier diodes are used to implement a rectifier, as Schottky devices exhibit higher cutoff frequencies and lower forward voltage drop than p n junction based diodes. Unlike standard p n junction based diodes, the S chottky barrier diode is a majority carrier device, meaning it avoids the minority carrier storage effects and can therefore be switched faster. By selectively blocking the n+/p+ implan ts in desired diffusion areas or by directly contacting the n well/p well with metallization, integrated S chottky barrier diodes can be fabricated in a standard CMOS process [46, 47] Fabricating the S chottky contact do es not require any process enhancements and can be designed entirely with available process layers. A Schottky diode can be designed with a p n junction guard ring that terminate s the perimeter with a diffused p+ region. Figure 3 3 shows the two types of Schottky diode layouts and cross sections. The guard ring reduce s the reverse leakage current due to sharp electrode edge effects [48] Usi ng a guard ring can increase the reverse breakdown voltage and reduce the reverse leakage current. However, guard ring s also reduce the forward current due to the alleviated edge effect. Depending on an application requirements, thinking of these design features as tradeoffs can help determine whether a guard ring is appropriate when designing Schottky diodes. For example, a DC/DC boost converter requires a diode featuring a low forward voltage drop but a large reverse breakdown voltage In this case a S chottky diode with a guard ring structure would be preferable In a UHF RFID application, the RF DC multiplier in the transponder uses Schottky diodes without guard ring structures, because the input amplitude is

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47 limited and the multiplier favors less parasitic capacitance to minimize the power lost to the substrate. 3.4 RF DC Voltage Multiplier For those biomedical applications that require longer operation ranges (> 1m), ultra high frequency (UHF) transponders are preferable with far field region. The one stage rectifier for the UHF transponder is not usually used because the input amplitude coupling from the antenna is very small. Unlike the inductive coupled transponder, which can provide induced amplitudes of several volts, the amplitudes induced in inp ut of the UHF transponder is usually less 200 mV. The RF DC multiplier is required to provide sufficient DC voltage for the UHF transponder. 3.4.1 Basic Operations Figure 3 4 shows a basic one stage voltage doubler, which consists of two diodes and two conducts current that charges the capacitor. One stage of the voltage doubler consists of a clamping circuit and a rectifying circuit. The clamping circuit is used to build DC voltage across the coupling capacitor when the input signal is in the negative cycle In the positive cycle, the voltage amplitud the DC voltage generated across the coupling capacitor. At the same time, the rectifying circuit is on and passing current to charge the storage capacitor. Ideally the output DC voltage amplitude of a one stage rectifier is two times the peak amplitude of the input signal, but the voltage is on voltage and reverse leakage current and due to capacitor parasitics. If there is no loading in the output, the maximum output DC voltage for one stage voltage doubler is approximately (3 1)

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48 The RF DC multiplier cascades multiple one stage voltage doublers to generate higher output voltage while reducing the required input amplitude, which improves the passive transponder sensitivity. This is a key building block in the passive transponder. The major challenge is to increase the efficiency while providing t he minimum DC voltage and current to operate the integrated circuit on the transponder. Figure 3 5 shows a schematic of a three stage full wave RF DC converter The full wave rectifier uses both the positive and negative cycles of the differential signal thereby decreasing the minimum required input power to generate a certain DC output level. To decrease the power loss to the substrat e, a metal to metal flux capacitor is utilized. Rectifier design is of significant importance to low input sensitivity To minimize the output voltage ripple, the capacitor in last stage is sized large enough so that the time constant is much larger than t he input signal period. 3.4.2 Analysis and Design Procedure The RF DC multiplier is similar to the AC DC charge pump proposed by Dickson in 1976. DC charge pump is given by [49] (3 2) where N is number of diodes, V IN is the amplitude of input voltage, C C is the coupling capacitor, C P L is the load current, a nd f is the input frequency. E quation 3 2 considers the voltage drop of each diode is constant that is true when the input voltage is much larger than the turn on voltage or threshold voltage of the diodes. Moreover, the reverse current and the substra te power loss are ignored in equat ion 3 2. The input amplitude is usually smaller than the turn on voltage for the RF DC multiplier for a UHF transponder. As a result, equation 3 2 is less accurate. This section develops a new design procedure for RF DC multipliers.

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49 To achieve a higher voltage conversion efficien cy, equation 3 2 indicates that we should select a coupling capacitor (C C ) that is larger than the parasitic capacitor (C P ). As a result, in the high frequency analysis, the coupling capacitors are considered short circuits. The refore, the diodes are arranged in parallel or anti parallel to the input of the RF DC converter. On the other hand, the diodes are in series with the output because the coupling capacitors are open circuits in DC analysis. Assuming the input signal is sin usoidal. Given the required output DC voltage (V OUT ), the voltage (v D ) across each diode in a full wave RF DC multiplier is given by [50, 51] (3 3) Figure 3 6 shows the analysis of N stage RF DC multiplier. Using the given output voltage is a resistive lo ad. So to complete the design, we must also specify the load current. As we can see when the multiplier reaches steady state, the total charge generated from a diode in one clock period cycle equals the total charge delivered to the load in one clock cycle That behavior is given by (3 4) The diode current is expressed in (3 5) S is the saturation current density, and V T is the thermal voltage. Equation 3 4 is valid for a pn or Schottky diode. If we use a diode connected MOS, then equation 3 4 n eeds to be modified. By combining equation 3 3, 3 4, and 3 5, equation 3 4 can be expressed as

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50 (3 6) From equation 3 2, vd is a function of the input amplitude, number of stages, and output voltage. Moreover, the current is a function of vd and the area of the diode. Therefore, to meet the load constraints, V OUT and I OUT the three design variables are diode area A, number of stages N, and input voltage amplitude V IN W e seek to derive an expression relating the minimum input amplitude as a function of these three design variables. Figure 3 7 illustrates the charge conservation for a one stage voltage doubler. The analysis considers two current components: the forward current and the reverse current. To accurately present the diod measured or simulated I V characteristics of the diode to replace the left side term in the integral in equation 3 6. Then we can develop a MATLAB code to do a numerical iteration to find the req uired number of stages and diode area for a given load. As shown in equation 3 3, the voltage drop of the diode is a function of the number of stages and the input amplitude. The frequency and output voltage are already specified. The process sweeps the tw o variables, input amplitude and number of stages, to find the current associated with the voltage drop across the diode from the measured I V data. The derived current needs to satisfy the charge conservation as shown in equation 3 6. In this way we can f ind the required area for each diode. However, the results can give several solutions that satisfy the load requirement. To find the minimum transponder sensitivity, we need to consider the input matching in the interface, so the input impedance of the mul tiplier is derived in the design procedure. The RF The power PD consumption on ea ch diode can be presented as equation 3 7, and the total input

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51 power, which is equal to total power consumption on the diodes and load in one period, can be presented as equation 3 8. The factor 4 in equation 3 8 is for the full wave rectifier. Therefore we can find the chip input resistance R IN as shown in equation 3 9 (3 7) (3 8) (3 9) The input capaci tance consists of parasitic capacitance (C P ) associated with the coupling capacitor and the capacitance (C D ) associated with the depletion region. (3 10) The total capacitance of the multiplier is given by (3 11) and the input impedance is given by (3 12) Therefore, the induced input voltage can expressed as (3 13) where V ANT is the open circuit voltage in the antenna, Z ANT IN The voltage multiplier power conversion efficiency is defined as (3 14)

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52 A design example of a full wave RF DC multiplier for 915 MHz ISM band with a given output load voltage V OUT = 1V and I OUT = 2 A. This example uses an antenna impedance of 50 Ohm, and a P type Schottky diode. Figure 3 8 shows the measured I V of the P Schottky diode with area 7.2 m 2 The proposed design procedure can be applied to any diode device with the measured or simulated I V data. Figure 3 9 demonstrates the required diode area, number of stages, efficiency, and power the antenna receives. The red line represents the input voltage amplitude V IN for 70mV. Each blue line represents V IN when increased by 10mV. The result shows a minimum sensitivity of 27.1 W for 14 stages of multipliers to meet the required output specification. Figure 3 10 presents another design example. With the same load power 2 W and a load voltage of 0.5 V, the load current is 4 A. As in the example in Figure 3 9 the input amplitude starts from 70 mV and increases by 10mV. Although the output load power is the same in both examples, the required diode area, minimum sensitivity, and efficien cy are different. The design where V OUT = 1 Volt and I OUT = 2 A is more sensitive than the design where V OUT = 0.5 Volt and I OUT = 4 A. This is because a larger diode area is required to deliver the load current. Moreover, the first case shows a better powe r conversion efficiency. 3.5 Antenna Consideration A wireless passive transponder uses an antenna to receiver power and converter to AC voltage to RF DC multiplier. The antenna impedance consists of a resistive component and a reactance component. Since the in put impedance of the RF DC multiplier is usually capacitive, resistive component consists of a radiation resistor and a loss resistor. The radiation resistance is modeled the radiation behavior in the antenna. When electrons are accelerated in the antenna, the

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53 electrons generate electromagnetic fields radiating outward. The electromagnetic waves take energy from the electrons. The loss of energy is analogous to ohmi c resistance. When the antenna is used to capture power, the higher radiation resistance gives a larger induced open circuit voltage, which is more desirable. The loss resistance presents the power loss as heat in the antenna. Therefore, the efficiency of the antenna is given by (3 15) where R r is the radiation resistance and R l is the loss resistance. 3.6 Transponder Sensitivity As shown in the design example, the RF DC multiplier requires a minimum input power to operate the IC by a given load power. The minimum input power is defined as the chip sensitivity. Since the transponder consists of an antenna and chip, the transponder sensitivity ance, the input match, and the chip sensitivity. (3 16) 3.7 Experiments Here, we present the measured results of the Schottky diode and multiplier. 3.7.1 Schottky Diodes To evaluate the I V characteristics of the Schottky diode, several diodes of different cross sections were laid out in a 0.6m n well and a 130nm twin well standard CMOS process. The AMI 0.6m n well CMOS process is a titanium p

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54 the UMC 130nm, this process is silicide process. On top of the silicon, there is silicide compound layer, and th is layer forms the Schottky barrier contact with the lightly doped silicon. The effective area of Schottky diode is the lightly doped area. Diodes are fabricated with small Schottky contact areas [52] as this yields a higher cu toff frequency, and multiple cells are placed in parallel to improve the current handling capability. The measured forward current and reverse current density voltage (J V) curves for the Schottky barrier diodes in AMI C5 process are shown in Figure 3 11 Two shapes of Schottky diodes are fabricated to explore the performance. The first one is laid out by following the design rule, so the standard sized contacts form the Schottky diode. The s econd one provided by the foundry is laid out with design rule violation. As shown in Figure 3 12 is laid out in a rectangle shape. When the effective Schottky contact area is the same, the first case consumes more area. However, the first shows better forward current density and small reverse current leakage. The parameters of the fabricated Schottky diode can be e xtracted from the measured J V characteristics. The barrier height is computed using the Richardson Dushman equation for the thermionic current [53] (3 17) and the ideality factor is calculated with ( 3 18) In equation 3 17 B is the barrier height, V T is the thermal voltage, A* is the effective Richardson constant, J SO is the zero bias current density, and T is the absolute temperature. In equation 3 18 n is B S are the measured differences in forward

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55 bias voltage and current density. From euqation 3 17 and 3 18, the calculated barrier height is 0.72 eV for Vendor design rule and 0.64ev for the Standard design rule. The idealit y factor is 1.12 for Vendor design rule and 1.08 for the Standard design rule. Table 3 1 summaries the calculated Schottky diode parameters from the measured J V characteristics. Due to the availability of the triple well process on a UMC 130nm CMOS proces s, we implement 4 types of Schottky diodes: P type Schottky diode without guard ring, P type Schottky diode with guard ring, N type Schottky diode without guard ring, and N type Schottky diode with guard ring. Figure 3 11 shows the layout and measured J V characteristics of the 4 types of Schottky diodes. The Schottky diode effective area is the area of the active region on the lightly doped area. From the measured results, the Schottky diodes with guard rings have better reverse breakdown voltage performan ces for both types of diodes. Table 3 2 summaries the calculated Schottky diode parameters from the measured J V characteristics. 3.7.2 HF Voltage Multiplier To evaluate the performance of different Schottky diodes, four three stage full wave LF multipliers are fabricated, each of which is implemented in a UMC 130nm CMOS process using one of the four Schottky diodes. The area of the Schottky diode is 144 m2 and the coupling capacitor is 3.5 pF. Figure 3 13 shows the die photo of the multiplier. Given input power 5 dBm and load 1 M Figure 3 14 shows the measured multiplier output voltage vs. frequency. The rectifier with the P type Schottky diode without guard ring provides the highest voltage output, because it has the largest forward current density of these four Schottky diod es. 3.7.3 RF DC Multiplier In this section, a RF DC half wave multiplier chip is designed. It provides a 1 Volt DC output voltage at 217 k resistive load, and the source resistance is 50 Fig ure 3 15 presents

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56 the optimized results, and the RF DC multiplier uses 16 stages. A test chip was designed and manufactured in a 130 nm CMOS process with the low V T diode connected MOS to evaluate the design procedure for UHF RFID applications. Figure 3 16 shows the micrograph of the half wave multiplier. The overall test chip size is 1610 m x 520 m, while the area of the RF DC multiplier is 1610 m x 520 m. The half wave RF DC converter con sists of 16 stages of voltage doublers. The aspect ratio of the low V T diode connected MOS is 60 m/0.12 m and the coupling capacitor is 2.714 pF. Although the design results show that 47 m/0.12 m for a 16 stage RF DC multiplier, the Spectre simulation shows 60 m/0.12 m can meet the output requirements. This design procedure provides design tradeoffs among diode size, the number of design still needs to be simulated with CAD tools. The chip is directly measured by a probe with a single tone continuous wave (CW) 50 source at 915 MHz, and there is no any matching network between the chip and RF signal generator. Figure 3 17 shows both the simulated and measured results for the rectifier output voltage vs. input power at 915 MHz. Figure 3 18 shows the measured input impedance vs. different input power at 915 MHz with an output load of 217 k Figure 3 19 presents the measured input impedance vs. different frequency at 10 dBm input power with an output load of 217 k To provide maximum power transfer, the input impedance needs to be transformed to ma tch the source impedance of 50 Figure 3 20 shows the measured input impedance vs. frequency. In Figure 3 21 the matching network design starts from the load impedance 33 j73 and is in series with an 8 nH inductor that models the bonding wire. We use an L matching network to bring the load impedance to 50 The L matching network is a 10 nH shunt inductor and then a

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57 33 pF series capacitor. Figure 3 22 shows the test board with the RF DC multiplier chip and input matching networ k. After the matching network, the measured input impedance is 48.2 + j5.8, which is close to the source impedance as shown in Figure 3 23 Figure 3 24 presents the input impedance vs. input power both with and wi thout the matching network a t 10 dBm input power and 217 k load resistance. From Figure 3 25 the output voltage of RF DC multiplier is in creased using the input matching network. To reach the output voltage 1.1 volt at 217 k load, the sensitivity improves from 11.02 dBm to 12.65 dBm. The measured power conversion efficiency for 1.1 V olt at 217 k load is 10.3% with the matching network and 9.03% for without it.

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58 A B Figure 3 1 Rectifier circuits. A) Half wave rectifier B) Full wave rectifier. Figure 3 2 Block diagram of a typical wireless power interface frontend for biomedical implants.

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59 A B Figure 3 3 Cross section and layout of A ) n type Sc hottky diode with guard ring. B ) n type Schottky diode without guard ring. Figure 3 4 One stage voltage doubler.

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60 Figure 3 5 The schematic of three stage full wave RF DC converter. Figure 3 6 The analysis of N stage RF DC multiplier

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61 Figure 3 7 Charge conservation in steady state. Figure 3 8 Measured I V of P type Schottky diode.

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62 Figure 3 9 RF DC multiplier design for V OUT =1 V and I OUT =2 A. Figure 3 10 RF DC multiplier design for V OUT =0.5 V and I OUT =4 A.

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63 Figure 3 11 Schottky diode layout and measured Schottky diode current density vs. bias voltage in AMI 0.6 m CMOS process. Figure 3 12 Schottky diode layout and measured Schottky diode current density vs. bias voltage in UMC 130 nm CMOS process.

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64 Figure 3 13 Die photo of the three stage full wave HF voltage multiplier. Figure 3 14 The measured multiplier output voltage vs. frequency

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65 Fig ure 3 15 RF DC multiplier design for V OUT = 1 V and RLOAD = 217 k Figure 3 16 Die photo of the 16 stage half wave RF DC multiplier.

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66 Figure 3 17 The measured and simulated multipl ier output voltage vs. input power Figure 3 18 Input impedance vs. input power.

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67 Figure 3 19 Input impedance vs. input frequency. Figure 3 20 Input impedance vs. input frequency on Smith chart.

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68 Figure 3 21 Matching network design. Figure 3 22 The RF DC multiplier with input matching network.

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69 Figure 3 23 Input impedance vs. input frequency with input matching network on Smith chart. Figure 3 24 Input impedance vs. input power for 10 dBm input power at 217 k

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70 Figure 3 25 The measured multiplier output voltage vs. input power. Figure 3 26 The measured multiplier output power conversion efficiency vs. input power.

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71 Table 3 1 Summary of measured Schottky diode performance in AMI C5 process Schottky diode Vendor rule design rule Schottky diode Standard design rule Ideality factor 1.12 1.08 Zero bias current (A/cm 2 ) 0.000136 0.000987 Barrier height (eV) 0.72 0.64 Reverse breakdown (V) 13.5 13.4 Reverse leakage current @1V (A/cm 2 ) 12.05 13.6 Table 3 2 Summary of measured Schottky diode performance in UMC 130 nm CMOS process P Schottky diode without guardring N Schottky diode without guardring P Schottky diode with guardring N Schottky diode without guardring Ideality factor 1.54 1.4 1.24 1.04 Zero bias current (A/cm 2 ) 0.0215 0.0082 0.0095 0.0066 Barrier height (eV) 0.52 0.54 0.536 0.546 Reverse breakdown (V) 0.5 5.2 11.7 11.5 Reverse leakage current @1V (A/cm 2 ) 4.11 0.0083 0.0023 0.0077

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72 CHAPTER 4 4 A 0.3 V, 200 NW DIGITAL PHASE LOCKED LOOP AND A DU AL SUPPLY OUTPUT RF DC VOLTAGE MULTIPLIE R FOR UHF PASSIVE TR ANSPONDERS 4.1 Motivation Passive RF transponders have been used in a variety of ways in many applications, for instance biosignal recording and wireless sensor node s A clock generator is required in th e passive transponder to decode the downlink data modulate the baseband data, and clock analog and digital building blocks. The major challenges are the frequency stability and power consumption. The clock f requency drifts with process, voltage, and temperature (PVT) variation, which results in synchronization failure between the tag and the reader. Thus, the reader is unable to recover the backscattered data and the tag its elf cannot decode tag parameter instructions. Published solutions to deal with this variation include temperature compensation, injection locking, post fabrication trimmi ng, and preamble training. [54] uses an injection lock di vider which derives MHz); however, the power consumption of this clock generator is 7 which is unsuitable for passive transponder applications. In [55] the proposed solution uses a VCO accompanied by a digital calibration circuit, which together consume nearly 31 series of pulses from the reader. Each pulse has enough long time period than the on chip oscillator output clock period. The on chip clock counts each pulse and then adjust s the current of the current starved oscillator to change the frequency. However, over time the transponder clock frequency may drift from the calibrated point It requires recalibration, which is inefficient A training process (12.5 s delimiter) was proposed after calibration in [56] however, like other approaches the clock frequency is prone to environmental variation. Several RFID protocols, such as EPC Gen2, use a higher clock frequency to resolve the timing difference between data 0

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73 and data 1 without calibration or compensation processes. The EPC Gen2 protocol uses a reader to tag calibration symbol (RT c al) as a ref erence for the signal processor to differentiate between data 0 and data 1. To successfully decode the downlink data, the requi red clock frequency to resolve RT c al /2 is 1.28MHz. This protocol provides a calibration free solution, but the required high fre quency is proportional to the data rate, so this protocol consumes more power and [57] the proposed FLL continuously calibrates the clock generator frequency wit h EPC Gen2 standard by counting Tari to counter the clock frequency drift. However during the PW period in Tari symbol s there is no power available to the transponder. The width of PW is 0.5 Tari for data 0 and is normally around 0.25 Tari for data 1 T his put s stringent power constraints on the transponder. As a consequence, for power stringent application s the approaches presented above are unsuitable We propose a ~200 nW on chip clock generator based on a digital phase locked loop (DPLL) operating in the subthreshold region. The reference clock is extracted from the small duty cycle on off keying ( OOK ) RF carrier and therefore the available power to the transponder is more continuous. This clock also synchro nizes communication functions between the reader and the passive transponder. To further minimize the clock generator power consumption, we propose a new power management strategy to maximize efficiency. To improve the RF DC conversion efficiency, the RF DC mult iplier can use Schottky diode or low VT MOS. In addition, the efficiency of the DC DC converter after the RF DC multiplier must be high. As the complexity of RFID systems increases w ith the addition of digital pro cessing and supplementa ry analog blocks, th e power con straints for each subsystem become more stringent. I n a bi o signal application, the analo g modules require a higher volt age to operate. On the other hand, digital modules can use

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74 subthreshold logic to operate at lower voltages to reduce power co nsumption. There ar e two traditional ways to simul taneously deliver these separate output voltages. One option is to use a charge pump circuit that boosts the low output voltage from an RF DC multiplier to a higher voltage for the analog block with the dig ital blocks directly using the low voltage. Alternatively, an RF DC multiplier can generate the high voltage level for the analog supply, which is then stepped down to the lower voltage using a buck converter. However, both methods degrade the overall RF D C conversion efficiency. Thus, it is desirable to use a single RF DC converter efficiently deliver multiple supply voltages so as to independently optimize the power consumption of the digital and analog supply modules. In this chapter we propose a power management block that efficiently generate s dual regulated supply voltages from a single RF DC convert er block, supporting low voltage digital processing blocks at V REGL ~29 0mV and analog circuits at V REGH ~760 mV. 4.2 System Architecture Figure 4 1 shows a block level drawing of the proposed transponder architecture, including the proposed power management unit ( PM U) with dual re gulated supply, a power level detector, an envelope detector with embedded modulator charge injection and clock feed through cancelling switch and filter, the subthreshold clock multiplier unit (DPLL), and a backscattering modulator with on chip PRBS. The DC power supplies are generated by rectification and boosting of the RF carrier through a diode multiplier with corresponding storage capacitors. The design uses l inear regulators and a DC voltage limiter to provide stable DC voltages to the analog and dig ital blocks with protection from system over voltage damage. T he proposed transponder employs the DPLL as the on chip clock generator. The reference clock for the DPLL is derived from a low

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75 frequency a mplitude modulated signal (5 20 k Hz) embedded in the RF carrier which the reader continuously sen ds The power detector block continuously monitors the voltage level across each storage capacitor. Once this voltage reaches a pre programmed threshold, both the DPLL and backscattering modulator are enabled, all owing for data communication between the transponder and the reader. By enabling the backscattering switch only after receiving sufficient power, we can ensure the DPLL output frequency operat es w ithin the designated range (385 k Hz 1.54 MHz) This minimiz e s power supply activation and system start up times while also eliminating the possibility of system failure when the backscattered signal is at a similar frequency to that of the modulated reference. Under these conditions, the system may never capture en ough energy to be properly powered. During backscattering, the PRBS data modulates the DPLL output clock I f no measures are taken, this modulation will pass through the envelope detector and change the reference frequency of the PLL causing it to lose its lock. This is highly undesirable and to address this issue, we use a sense amplifier flip flop (SAFF) to sto re the state of the envelope de tector output each time the backscattering switch closes. Thus, when the modulator output is high or the antenna po rt is shorted, the SAFF holds the previous value, keeping the received DPLL reference clock ( CKRX ) stable. Figure 4 2 shows the proposed block diagram of the demodulator and the timing waveform of operation. 4.3 Circuit Implementation 4.3.1 Sub Threshold Digital PLL There are several reasons to use a D PLL over its analog counterpart. For low input frequencies, the time constant or the RC product of the filter should be high, thus an analog filter will occupy a large chip area. Also analog charge pump based PLLs are m ore power hungry since they require complex current generation and voltage to current conversion circuitry.

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76 Besides allowing for power saving techniques, such as voltage scaling, digital circuits are inherently more immune to noise. Most high performance D PLLs incorporate time digital converter (TDC) that works as the resolution TDC generates the digital codes proportional to the phase error between the divided down clock and reference clock. Unlike the bang bang phase and frequency detec tor (BB PFD), the TDC in the loop can better linearize the PFD response. However, the TDC consumes more power and chip area. Therefore, to minimize the power consumption is to use a binary phase and frequency detector (BB PFD) where the phase/frequency dif ference is a single bit signal. Figure 4 29 (A) shows the functional block diagram of the sub threshold D PLL operated from a 260 mV supply. A BB PFD compares the divided down clock from the digitally controlled oscillator (DCO) and the extracted refer ence clock from the envelope detector to generate a single bit early/late signal. A digital loop filter with programmable proportional (KP) and integral (KI) path gains is updated every reference clock cycle producing a 10 bit output based on the early/la te signal. Out of these 10 bits, the 3 least significant bits are used by a sigma delta sampled at 1/M of the output clock frequency to produce a bit stream which along with the remaining 7 bits from the loop filter output form an 8 bit control word for the DCO. Figure 4 3 (A) can be analyzed as a second order system, where KP and KI control the damping factor and loop bandwidth. The system needs a high damping factor and a high loop bandwidth to mitigate th e effect of noise at the output. This is even more crucial for ring oscillator based PLLs since they are susceptible to noise when operated at low voltages. Increasing the value of KP also increases the damping factor, but an increase in KI can make the system oscillatory since KI affects the loop bandwidth as well as the damping factor. Thus by

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77 choosing a high KP / KI ratio the system can be made more stable. However, a higher KP will increase the jitter in the DPLL, because the control words change (2K p+1) when the BB PFD toggles. A DCO topology with tunable coarse and fine delay stages, shown in Figure 4 3 (B), was chosen over a re laxation oscillator topology for all digital operation at very low supply voltages. The coarse tuning stage is implemented as a 32 to 1 delay select path architecture with tristate buffers acting as selection switches. We use the five most significant bits of the control word for tuning the coarse delay stage through a 5 to 32 bit decoder (COARSE[31:0]). The fine tuning stage has tristate buffers connected in parallel with the inverters and is activated by an 8 bit thermometric control word (FINE[7:0]), whi ch is based on the remaining 3 bits of the control word. Overall, by compressing 3 bits of the loop filter output by a sigma delta we achieve an increased dithering resolution. Also as shown in Figure 4 1 the output of the envelope detector and input reference clock to the D PLL i s sampled by a SAFF using the D PLL output clock frequency to eliminate glitches that can result when the back scattering switch is enabled. Although this increases the jitter, it ensures the input clock frequency is stable. This architecture meets the tunable frequency range requirements while operating in sub threshold region at very low pow er levels. All modules, except for the PFD and DCO, were synthesized using custom low power standard cells with P/N ratio of one. 4.3.2 RF DC Power Management Unit Figure 4 4 illustrates the conventional and proposed RF DC PM U architecture s for delivering dual V DD for digital and analog modules. In the conventional topology, the regulated voltage for the digital blocks is generated by stepping down the 1V supply which wast es the power used in the RF DC multiplication process only to regulate back down with a large

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78 dropout. I n the proposed approach the voltage conversion efficiency can be improved becaus e the regulated voltage is obtained from a n earlier stage of the RF DC converter, thus requiring only a few ten s of mV s of dropout voltage However, if the error amplifier and bias circuitry were to be connected to this voltage, the function of these block s would be compromised and the necessary drop out voltage of the regulator would increase. To alleviate this problem, the two error amplifier s, which consume minuscule current, are connected to a higher power supply The error amplifier of the analog block regulator is powered by the 16th stage output of the RF DC converter while the error amplifier of the digital block takes its power from the LDO analog supply output. Thus, the supply sensitive delay cells of the subthreshold DPLL benefit from the improve ment in ripple rejection; only the pass transistor at the output stage where any error is reduced by the loop gain is powered by an unregulated supply. By using this proposed arrangement in the RF DC voltage generation block, the efficiency of the linear voltage regulator improve s from 2 2.5 % to 71.2 %. Moreover the power required from the RF DC converter falls from 9 2 5nW to 36 5nW In such a config uration, power efficiency of PMU and thus RFID activation range, can be maximized. Figure 4 5 shows the functional schematic implementing the RF DC voltage generation block. The RF DC converter is composed of sixteen stages. The diodes in the multiplier ar e implemented with low V T NMOS devices, minimizing forward voltage drop T he flying capacitors are metal metal (MIM) capacitors to reduce substrate loss. The schematic of the voltage reference and LDO L block, excluding the start up circuit, is shown in Figure 4 6 The error amplifier for LDO L is a PMOS differential amplifier with active NMOS load and the error amplifier for LDO H is a NMOS differential amp lifier with active PMOS load This accommodate s the different input common mode voltage requirements of each block. T he

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79 current and voltage reference circuits are composed of bootstrap current mirror and weighted V GS voltage reference s [58] The power consumption of the voltage reference and the LDO L are 105 nW and 75 nW, respectively. M 3 and M 4 are biased in the subthreshold region In order to minimize the sensitivity of the bias current to power supply variation, M 1 and M 2 are sized with large length s and operate in strong inversion for improved matching by minimizing channel length modulation in the PMOS current mirror. T he minimum voltages required for each of the outputs of the diode multiplier can be defined in terms of the voltage headroom requirements of the various blocks For instance, V DDL is determined by the minimum voltage of the pass transistor in LDO L and V DDM and V DDH are imposed by the error amplifier of LDO L and reference circuit respective ly. Thus the minimum voltages V DDL V DDM and V DDH required f rom the RF DC converter are given by (4 1) (4 2) (4 3) Based on the required voltages, the RF DC converter is designed to meet three different output voltages at maxi mum conversion efficiency. The multiplier is tapped at stages five, fourteen, and sixteen, providing DC voltages of ~3 3 0, 800, and 116 0 mV respectively These voltages are stored on three separate MOS capacitors. The first stage is regulated down to 2 9 0 mV and functions as the digital supply (V REGL ) and the second is regulated down to 725 mV (V REGH ) to power the analog blocks. 4.3.3 Demodulator The proposed architecture uses a DPLL as the on chip clock generator. DPLL requires a reference clock, and the most common implementation is to use a crystal oscillator. However,

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80 the crystal oscillator is usual ly bulky in size and power hungry, which is unsuitable for this application. In the proposed chip, the reference clock is extracted from the modulated transmitted signal from the external reader. ASK modulation is used in this application, since FSK modula tion requires a mixer and high frequency local oscillator, which are power hungry blocks. The proposed ASK demodulator, as shown in Figure 4 7 consists of a three stage RF DC converter, DC voltage limiter, low pass filter, and positive edge trigger register. The three stage RF DC converter extracts the envelope signal with an addit ion of RC load When the input signal amplitude drops, the resistor provides a discharge path. The time constant is selected change of amplitude. A DC limiter is added in the output of the RF DC converter to prevent the input common mode voltage of the data slicer from exceeding the range. The low pass filter corner frequency is set at 200 kHz to accommodate input clock frequencies from 5~20 kHz while f iltering out the high frequency carr ier and backscattering signals. Figure 4 8 shows the proposed data slicer which extract s the reference clock for the DPLL. The objective is to use a higher frequency clock and DCO output to sample the low frequency extracted envelope signal and then digitize it to the CMOS logic level. T o minimize power consumption, the data slicer employs a preamp fol lowed by a sense amplifier flip flop [59] In this configuration, the preamp provides a small enough gain to resolve the voltage difference between the envelope voltage and filtered voltage T he SAFF then u ses positive feedback amplified to the CMOS logic level. The preamplifier provides 12.5 dB g ain while consuming 110 nA DC current. The SAFF uses a cross cou pled inverter pair T he inverter pair swing s to its stable state based on the value of the input. When the DCO output is low, PMOS transistors

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81 precharge the output node of the latch to high. In this way t he NAND flip flop is able to hold the previous outpu t state. 4.4 Experiment al Results This chip was fabricated in a UMC 0.13 m CMOS process. T he ch ip micrograph is shown in Figure 4 9 T he chip is 2.12 mm 2 and the DPLL is 0. 0 17 mm 2 We tested the DPLL alone to evaluate the jitter performance with battery supply. The reference clock for the DPLL is fed from a signa l generator. Figure 4 10 presents the measured jitter performance, which shows the deterministic jitter in this DPLL design when the DPLL is locked. This is due to the nature of the BB PFD DPLL. Moreover, the determi nistic jitter is dependent on the delay of delay cell in DCO. The measured jitter of the free running VCO with battery supply is shown in Figure 4 11 Th e chip is fed with 915 MHz signal, powered by the RF DC converter, and the reference clock is extracted from the OOK signal. Figure 4 12 presents the mea sured jitter performance while Figure 4 13 shows the measured phase noise. There are several spurs in the measurement due to the reference clock coupling and mismatches in the loop filter. This increases the phase noise significantly. The table summarizes the proposed DPLL performance and compares it with other low power PLL designs. The FOM [60] is used to evaluate the overall performance. A lower number indicates a superior PLL design. (4 4) Although the proposed DPLL has the highest FOM, the DPLL has smallest area and lowest power consumption in the Table 4 1

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82 Measurements were set up using an arbitrary waveform generator (AWG) to generate a low frequency that was feed into RF signal generator set at 915 MHz. A folded dipole antenna connects to the output of the RF signal generator. The fabricated chip is tested on PCB with a folded dipole antenna connected to its input. Figure 4 14 sh ows the wir elessly measured D PLL timing waveforms. The reference clock is extracted from a 915 MHz RF carrier input that is ASK modulated with a 20 kHz signal. The waveforms show the extracted envelope (V ENV ) properly phased aligned and locked with the sampled input reference (CK TX /64) and the PLL output clock frequency (CK TX ) of ~1.28MHz (M*N=64). In Figure 4 15 the backscattered modulation sidebands for wireless read er tag operation were measured at 915.64, 915.96, and 916.28 MHz with corresponding reference clock frequencies of 10, 15, and 20 kHz ( PLL multiplier set to 64). Figure 4 16 s hows the measured unregulated output, V DDH and the regulated V REGH and V REGL voltages of the PMU versus input power. Once the RF input power reaches 12 dBm, the regulated output voltages r em ain constant with a line regula tion of 2.07 mV/V at 1 uA load for V REGL and 3.7 mV/V at 3 uA load for V REGH Table 4 2 shows a performance summary and Table 4 3 with relevant published works The RF transponder shows a measured sensitivity of 12 dBm, and the D PLL dissipates ~200 nW from a 260 mV supply at 1.54 MHz.

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83 Figure 4 1 Functional block diagram of RFID transponder Figure 4 2 Simplified block diagram of the demodulator and the timing waveform of operation.

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84 A B Figure 4 3 Functional block diagram. A) D PLL, B) DCO. A B Figure 4 4 Power management unit A ) c onventional B ) proposed.

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85 Figure 4 5 Functional schematic of the proposed RF DC power management unit Figure 4 6 Functional schematic of the voltage reference and voltage regulator L DOL

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86 Figure 4 7 Functional schematic of the ASK demodulator Figure 4 8 Functional schematic of the proposed data slicer

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87 Figure 4 9 Die photo of the proposed RFID transponder. Figure 4 10 The measured jitter performance with battery supply.

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88 Figure 4 11 The measured jitter performance of free running DCO with battery supply. Figure 4 12 The measured jitter performance with RF source powered.

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89 Figure 4 13 The measured phase noise of the DPLL with RF source powered. Figure 4 14 Measured recovered clock and DPLL output.

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90 Figure 4 15 Measured backscattering modulated sideband spectrum for M*N = 64. Figure 4 16 The measured unregulated output, VDD H and regulated VREG H and VREG L voltages of the PMU versus input power.

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91 Table 4 1 PLL performance comparison [61] [62] [63] [64] This work Technology 90 nm 130 nm 90 nm 130 nm 130 nm Power consumption (mW) 10 1.25 0.4 0.44 0.000181 Power supply (Volt) 0.6 1.2 0.5 0.5 0.5 0.29 Output frequency (MHz) 5000 550 400 400 433 1.28 Area (mm^ 2 ) 0.1 0.04 0.074 0.736 0.0107 RMS jitter (ps) 0.62 8.01 9.62 5.5 16980 P P jitter (ps) N / A 56.36 77.78 49.1 72730 Phase noise @1MHz offset (dBc/Hz) 115 95 87 91.5 102 Jitter/cycle (%) 0.31 0.44 0.38 0.24 2.18 FOM 0.0754 0.3718 0.1927 0.0338 1 Table 4 2 Chip performance summary O verview Technology 0.13 Tag sensitivity 12 dBm Modulation method ASK RF DC PM U efficiency 12.54% RF DC output power 6.96 W RF DC output voltages 260 mV/725 Mv Backscattering frequency 384 kHz 1.54 MHz Chip area 2. 12 mm 2 Table 4 3 On c hip clock performance comparison [65] [57] This work Circuit topology Relaxation OSC. FLL D PLL Power consumption (nW) 302 1800 200 Power supply (Volt) 0.8 1 0.26 Output frequency (MHz) 1.52 2.56 0.384 1.54 Frequency deviation of fosc <2% (over supply) +1.2/ 3.2 +1.5/ 1.5% Active area (mm 2 ) 0.134 N/A 0. 0 17

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92 CHAPTER 5 5 A SUPPLY MODULATED T RANSPONDER 5.1 Motivation Medication non compliance costs a large amount of money in developing drugs during clinical trial s and results in high patient fatality Currently, t he most reliable method to improve medication compliance is direct observation therapy which requires pat ients report to the health provider after they take medicine However, this method becomes unrealistic when attempted on a large scale. This chapter presents a novel method and device that can be used to improve the medicat ion compliance. The proposed meth od u se s the RFID technology which attaches a tiny transponder to a bio compatible antenna printed on a small substrate Once the patient swallow s the transponder and the device reaches the stomach, it activate s and begins transmit ting UHF signal to an external reader which confirms that the transponder has been taken into the GI tract The transponder can be programmed with a set of ID numbers each of which represent s a specific medicine. By reading out the transmitted IDs from the patients or subject s automatically, t his method achieves low cost and reliable direct observation therapy for va lidating medication compliance. In this proposed method, the size of transpo nder is a critical factor A lar ge chip area has the po tential to cause damage to the G I tract so it is crucial to minimize the size of tagging device in whenever possible This chapter proposes a new transponder architecture that achieves a smaller chip area than a conventional transponder by removing the AC DC converter, DC voltage conditioning blocks and low frequency clock generator 5.2 System Architecture A passive transponder u se s an antenna to interact with electromagnetic wave s sent from an interrogator It conv erts the waves to AC voltage across the AC DC converter input. Then t he

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93 AC DC multiplier converters the AC voltage to DC voltage on a storage capacitor an d provides the DC power to the circuit blocks. In this way it avoids the problem s associated with using a battery. When the transponder is activated it can communic ate data to the reader. Figure 5 1 present s the building blocks diagram of the conventional passive transponder A passive tr ansponder chip consists of an AC DC multiplier, on chip storage capacitor, demodulator, clock generat or, power on reset circuit, and digital baseband circuit. The AC DC multiplier consists of diode s and capacitor s the size s of which are determined mainly by the input signal frequency and the load current requirement and output DC voltage. The AC DC multiplier and demodulator consu me a large percent of the chip area especially when the carrier frequency is low like in HF or LF bands. Moreover, minimiz ing the rectifier output voltage ripple requires an on chip storage capacitor with a large value, whi ch consumes a lot of chip area T he rectifier output voltage also must be regulated in order to provide a stable DC voltage for the analog building blocks, and hence a series voltage regulator is normally required. To ensure that the digital logic starts a t a known state when power is first applied, t he transponder employs a power on reset block. Minimizing the chip area in RFID chip can be challenging To do so, the transponder archite cture must eliminate the RF DC c onversion block and the on chip storage capacitor since their areas are larger than the other building blocks in RFID This chapter proposes a novel passive transponder architecture that can operate directly from an AC power supply A ll building blocks in the proposed transponder are designed to be ope rate d at AC power supply voltage In addition, the AC power supply voltage not only power s the transponder but also clock s the digital blocks in the chip In this way, we can also remove the low frequency clock generation block from th e proposed tra nsponder. W hen the amplitude of the AC supply voltage reaches the designated voltage level the transponder sends an 8 b it OOK modulated signal at 902 MHz ISM

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94 band to the reader as shown in Figure 5 2 The input voltage clamp blo ck provides two functions First, the clamper can li mit the input voltage to protect the building blocks from over voltage damage. Second, the voltage clamper provides trapezoid like supply voltage profile that minimizes the variation in supply voltage. T his transponder shown in Figure 5 3 consists of the input voltage clamping circuit, frequency divider, decoder, ROM and modulator. 5.3 Circuit Implementation In this section, the circuit building blocks in the proposed AC supply modulated transponder are presented including the basic AC logic circuit, frequency divider, 915 MHz oscillator and transmitter. The AC logic circuit is used in all digital blocks to pe rform the function f r om an AC supply voltage. 5.3.1 AC Logic Circuit Figure 5 4 illustrates the AC inverter schematic [66] [67] The AC inverter consists of two identical inverters and two transmission gates. The power and ground nodes of the two inverters are connected in opposite direction s f rom each other. For instance the source s of the uppe r PMOS and NMOS connect to V+ and V respectively. O n the bottom path, the source s of the PMOS and NMOS connected to V and V+, respectively. When the supply voltage V+ is larger than V the upper path is active and the bottom path is off. Th e bottom inverter is active only when V is larger than V+. In this way the two paths can process the signal during both positi ve and negative supply voltage. 5.3.2 Frequency Divider Complicated digital logic cells can be implemented using the idea of a basic AC logic inverter. The AC supply Reset S et register is shown in Figure 5 5 The AC supply voltage is also

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95 the clock frequency for the frequency divider. The frequency divider is built by cascading AC supply RS registers. The design challenge for this RS register com es when the supply voltages (V+ and V ) are close to zero Here, the charge needs to be large enough to maintain the corresponding state on the output of the previous stage. When the supply voltage is close to zero, the transmission gate and the inverter f orm a discharge path from the output node to the power supply as shown in Figure 5 6 nction of frequency division fails. This problem becomes worse when the clock frequency is low, because the charge can be completely discharge d in a short time. To resolve this problem, a capacitor can be added to the output node to increase the discharge time. In this design, the capacitor size is 75 fF for a minimum 100 kHz clock frequency. Figure 5 7 shows the simulation results of the frequency divider with and without the additional capacitor. In (A), the voltage of Q is discharged to zero. (B) shows the state of Q is held. (C) and (D) illustrate the frequency divider function with and without the additional c apacitor. 5.3.3 Oscillator Design The transponder use s the ISM 900 MHz frequency band as the uplink frequency T he transponder operates from an AC power supply. This requirement makes o scillating frequency less se nsitive to power supply voltage variation. Using a cross coupled LC oscillator makes the frequency less sensitive to supply voltage variation, but it requires passive elements like inductor and capacitor. Also, c ompar ed to a ring oscillator, the cross coupled LC oscillator consumes more area and power. T his proposed transponder uses the cross coupled ring oscillator with a constant bias ing technique to minimize the frequency sensitivity to power supply variati on.

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96 Figure 5 8 shows the schematic of the proposed oscillator. The oscillator consists of three differential delay cells and a bias voltage generator. Th e delay cell s employ NMOS transistors to achieve high speed operation and use PMOS transistors as current source s The oscillator u se s a bias circuit to control the gate to source voltage of the PMOS in the delay cell reduce the bias current less sensitiv ity to supply voltage variation. When the supply voltage increases, the ring oscillator frequency increases due to more bias current being injected into the delay cell. To offset the positive supply voltage coefficient, the PMO gate source voltage needs to remain constant. This minimizes the current variation with supply voltage. Figure 5 9 presents the simulation results of the oscillator frequency at AC supply voltage. The gate to source voltage of the PMOS in the delay cell ranges from 301 mV to 303 mV T he voltage variation results in oscillation frequency changes from 902 to 916 MHz wh ich still remain s in the ISM 900 MHz band. 5.3.4 Transmitter Figure 5 10 shows the schematic of the transmitter. The transmitter consists of a differential t o single converter and a class D power amplifier. This transponder use s a class D amplifier because of its potential ly high power conversion efficiency and its small chip area size. The class D power amplifier is a switching amplifier, so the switch is either fully on or fully off. The power loss, therefore, can be significantly reduced which leads to high er power efficiency. The class D amplifier design u se s two static switches, which can be implemented as an inverter, to generate square wav e. Following the inverter, a series tuned filter passes the fundamental frequency to the load. The parasitic capacitor from the inverter and inductive antenna can be used as LC filter.

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97 Figure 5 10 shows the schematic of the class D power amplifier, which consists of inverters and a series tuned filter. In reality, the switches have parasitic capacitor s and finite turn on resistor s, so the design procedure needs to consider the power loss from the se The output power of the transmitter is expressed in equation 5 1 (5 1) w here V DD is the supply voltage ( which equals V+ V ) R ANT is the load resistance, and R ON is the on resistor. Given the required output power and specified V DD from equation 5 1 the necessary load resistance can be found in equation 5 2 [68] (5 2) The design procedure is to find the aspect ratio of the inverter size that maximizes the power conversion efficiency. The required antenna resistance can then be found in equation 5 2. Figure 5 11 presents the design procedure for this transmitter. In (A), the aspect ratio of NMOS is found to be 175. As a result, the required antenna resistance can be determined as shown in (B). From Figure 5 11 the aspect ratio of the NMOS in the class D power amplifier can be found 175. For the inverter, we use a minimum gate length 0.1 2 m and the corresponding width 21 m. Given the driver size, the class parasitic capacitance can be found from simulation. The value of capacitor is 0.275 pF which means the antenna has to have 114 nH in order to resonate at 915 MHz at the output. The corresponding antenna resistance can be determined from (B). As a result, the antenna requires of resistance. The required resistor

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98 and inductor values are the antenna impedance needed to be met to achieve the highest power conversion efficiency. 5.4 Antenna Design To implement the inductive antenna, a loop antenna is employed. Loop antennas are usually classified as either electrically large or electrically small based on the circumference of the loop. If the circumference is less than or equal to /10 the antenna is considered electrically small antenna. is the wavelength of the output frequency. The coil and antenna w ere fabricated on a Pyrex wafer with a 1 m thick electroplating cooper layer. T he copper layer was coated with a gold layer to facilitate the wire bonding process. Figure 5 12 shows the 3 D drawing of the proposed tagging system for medication compliance. The size of the substrate is 11 mm*4.5 mm which fits into a standard OOO capsule. Figure 5 13 shows the 3D plot of the antenna structure. The simulated impedance of the antenna is shown in Figure 5 15 The impedance is 15.6 + 696i at 920 MHz and the inductance is 120 nH. Figure 5 15 presents the simulated radiation patterns of the antenna 5.5 Experimental Results This chip was fabricated in a 130 nm 1P8M CMOS process from UMC. A chip microphotograph is shown in Figure 5 16 The total chip area is 380 m340 m. The electrical performance of the chip was measured by housing the chip on a glass slide and testing it on a probe station. The input signal was fed by a custom designed low frequency balun to generate 125 kHz differential input signal. Figure 5 17 shows the measurement setup for the proposed transponder. T he signal generator outputs a 125 kHz AC voltage to the Balun to generate a differential signal across the input of the transponder. The MXA analyzer captures the burst Figure 5 18 shows the measured waveform on an

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99 oscilloscope. The input signal amplitude is 1 Volt from the signal generator output and the differential input signal amplitude is limiting around 200 mV by usin g the input clamp circuit. The output signal of the transponder shows an 8 bit data pattern with 15 mV peak amplitude on a 50 load. At 0.4 Volt DC voltage, t he measured power consumption is 245 A without the input clamp circuit and 843 A with it The output waveform is measured by a signal analyzer as shown in Figure 5 19 The output signal level is 68 dB V which is equal to 48.89 dBm on 50 Table 5 1 summarizes the performance of the proposed suppl y modulated tag.

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100 Figure 5 1 Conventional passive transponder building block s diagram. Figure 5 2 Proposed supply modulated transponder input and output wave form Figure 5 3 Proposed AC supply modulated transponder building block diagram.

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101 Figure 5 4 S chematic of AC inverter. Figure 5 5 The s chematic of the AC supply RS register.

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102 Figure 5 6 AC supply RS register design. Figure 5 7 Simulated results of the AC supply RS register.

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103 Figure 5 8 Schematic of NMOS transistor cross coupled ring oscillator. Figure 5 9 Simulation results of the oscillator frequency with AC supply voltage

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104 Figure 5 10 Schematic of class D power amplifier. A B Figure 5 11 C lass D power amplifier sizing: A) Inverter size vs. conversion efficiency, B) The corresponding antenna resistance by given aspect ratio of Inverter size.

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105 Figure 5 12 The 3 D drawing of the proposed supply modulated tag. Figure 5 13 The 3 D plot of the antenna on the Pyrex substrate.

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106 Figure 5 14 Simulated antenna impedance. Figure 5 15 The simulated antenna radiation pattern.

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107 Figure 5 16 Chip microphotograph of the supply modulated transponder Figure 5 17 The measurement setup for the proposed transponder.

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108 Figure 5 18 Measured time domain waveform s on an oscilloscope. Figure 5 19 Measured output signal using signal analyzer. Table 5 1 Summary of supply modulated transponder performance This work Technology 130 nm CMOS technology Supply voltage (V) 0.4 Down/Up link frequency 125 kHz/915 MHz Input power (W) 338.4 Output power (dBm) 48.89 Chip area (mm 2 ) 0.1292

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109 CHAPTER 6 6 A BATTERY ASSIST ED TRANSPONDER 6.1 Motivation There is an increasing demand for ultra low power transceiver for biomedical applications. For those applications that do require high data rate transmission, a RFID transponder is a good candidate for ultra low power applications. There are three types of transponder s : active transponder s semi passive transponder s and passive transponder s The p as sive tag has no battery to power the circuitry in the tag and has no radio transmitter. Passive tags depend on rectification of the received powe r from the reader to power the circuitry in the tag and they modulate the impedance between the antenna and the chip to send information back to reader Because of this last feature the communication range is normally less than in active transponders. However, passive transponder can be smaller than the a ctive ones and require minimum maintenance of the tag which is far more preferable for biomedical applications. This chapter presents a new transponder architecture It can us e a coil to receive data and system clock, and use s a DC voltage at the input to power the chip. In this way, the transponder to harvest energy from the electromagnetic waves The transponder sensitivity can be improved. The transponder can also use a coil to harvest the energy from electromagnetic wave to power the chip T his proposed tran sponder has advantages of bo th the active and passive transponder approaches W ith the battery assisting and radio transmitter, the communication range is improved. This transponder find an application as applied in the medicine electronic identification and in medication compliance. The proposed transponder can be attached to a standard sized capsule. When the capsu le requires to be programmed ID, the transponder can be activated and written in the air through ind uctive coupling. When used in the body for improving medication compliance,

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110 the excellent s ensitivity of the battery assist ed mode helps deal with the high loss that occurs in human body. 6.2 System Architecture Figure 6 1 shows the functional block diagram of the proposed transponder which consists of an AC/DC DC converter, a receiver module, a storage capacitor, digital logics and a transmitter module. The downlink frequency is 13.65 MHz and the uplink frequency 915 MHz B oth frequencies are located in the ISM bands. The energy harvester in the proposed transponder can take either AC or DC input voltage and output DC voltage. An energy detector is used to m onitor the DC voltage across the storage cap, and it actives the transmitter when the voltage level reaches the designed value. The receiver module can decode the data and provide system clock for the baseband circuit in the transponder. A 256 bit p seudo r andom b inary s equence (PRBS) generator is built in for test purpose. The transmitter consists of an LC tank oscillator and a class D amplifier to provide excellent output power efficien cy. 6.3 Circuit Implementation 6.3.1 AC/DC DC Converter The challenge associated with the proposed transponder is that the energy harvested needs to be able to work under both AC and DC voltage. In order to work for DC voltage input, another signal path for DC voltage input can be added to the AC DC voltage multiplier as sho wn in Figure 6 2 During AC voltage input, the diode in the DC path functions as a half wave multiplier. On the other hand, the multiple stage AC DC voltage converter multiplies the input signal amplitude to a higher DC voltage level at the output. In this mode, the diode in the DC

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111 path presents an energy loss for the conversion process because the output voltage of the converter imposes a large reverse voltage across the diode. There are tradeoffs in the AC/ DC DC converter between the input sensitivity for AC signal input and voltage conversion efficiency for DC input. In the DC input, the voltage drop is not constant when the forward current is small. Especially in the passive transponder applications, the l oad current is usually less than a micro ampere. In the DC input, the larger diode size is better. However, in the AC input the larger diode size introduce a larger reverse leakage current, because the reverse leakage current is proportional to the diode s ize. The converter consists of five stages of voltage doubler s and a diode for the DC input path. Low Vt diode connected MOS transistors are used to implement the rectifying device in the converter, and metal to metal capacitors are chosen for the couplin g capacitor s The voltage detector continuously monitors the supply voltage and set s the transponder in standby or the enable d mode. In standby mode, the system waits and dissipates very little power. When the voltage across the capacitor exceeds 0.85 V, t hen it enter s the enable d mode. 6.3.2 Receiver Circuit The receiver consists of an envelope detector, a clock recovery circuit, and a 256 bit p seudo r andom b inary s equence (PRBS) generator, as shown in Figure 6 3 In this chip, a one stage voltage doubler and two non inverting buffers with different bandwidths are used to extract the envelope from the downlink signal. When the transponder operates in inductive coupling logic level of the output flips. After the modulated signal, the output logic level flips again. However, when the transponder operates in DC input (battery assist ing mode) the output of the envelope detector is low. As a result, the clock recovery is designed to generate two pulses

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112 whenever the envelope signal toggles so that the initial state of envelope detector does not cause clock signa l recovery error. Figure 6 4 shows the proposed timing diagram of the received signal and recovered signal. 6.3.3 Transmitter The transmitter consists of an LC os cillator and a class D power amplifier, as shown in Figure 6 5 Compared to the ring oscillator, the LC tank oscillator is less sensitive to power supply voltage variation. The design uses an LC tank oscillator to generate an ISM band 915 MHz signal output due to the higher quality factor of the LC tank oscillator and the lower sensitivity to supply voltage variation. When the transmitter is enabled, the os cillator and the power amplifier draw a large current from the storage capacitor, which causes the power supply to vary. If a ring oscillator is used, the oscillating frequency varies enough to possibly cause the output frequency to move out of the ISM ban d, which degrades the class D power amplifier to supply voltage variation is crucial for this proposed transponder. Although the area of the LC tank oscillat or is larger than the ring oscillator, the LC tank oscillator provides stable frequency vs. supply voltage. The oscillator is activated only when the output voltage is at least 0.85 V and the clock and data are high. 6.4 Experimental Results This chip is measu red on a test board to verify its electrical characteristics. The chip was fabricated in a UMC 0.13 m CMOS process, and t he ch ip micrograph is shown in Figure 6 6 with the area of the chip measuring 0.9375 mm 2 Figure 6 7 shows the measurement setup for the proposed transponder. The input is fed OOK modulated 13.65 MHz carrier with a

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113 DC voltage through a bias tee ured by an Agilent MXA signal analyzer or an oscilloscope. Figure 6 8 shows the measured input power vs. output voltage of the proposed AC/DC DC converter fo r 210 k Figure 6 9 shows the AC/DC leakage comes from the reverse leakage of the diode in the DC path. Testing of the voltage level detector is shown in Figure 6 10 The top trace is the output of the AC/DC DC converter taken through on chip wafer probing while the bottom trace shows the output signal of the transponder output. An additional zoom in wind 4 0 mV. Measurement s of the function of the proposed transponder communication are shown in the following figures Tests were performed using an arbitrary wavef orm generator (AWG) for the clock and routing the 1 kHz clock to the modulation input of the signal generator set at 13.65 MHz. Figure 6 11 shows the input signal and the resulting clock and data. The top trace shows the modulated input waveform using 1% pulse width amplitude modulation. The second trace is the envelope output, a nd the third trace is the output data pattern of the PRBS. The bottom trace Figure 6 12 shows the same output waveforms except here using battery power instead of inductive coupling. The top trace shows the output of AC/DC at 1 kHz clock rate. Figure 6 13 shows the measured burst using a mixed signal analyzer. The measured voltage level is 52 dBV, which equals The number of burst pulses during data 1 also depends on the DC voltage level across the storage capacitor. Figure 6 14 shows the number o f pulses versus the input DC voltage during battery assisting mode.

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114 The minimum sensitivity is 6. 4 dBm for inductive couple powering. The minimum required battery voltage is 840 mV for battery assisting mode and 39 dBm for the input modulated signal. If the chip input power is more than the minimum sensitivity in inductive coupling mode or if the battery voltage is higher than the minimum voltage required, the chip is able to transmit more than one burst in one clock cycle. Table 6 1 summarizes the performance of the proposed tag.

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115 Figure 6 1 F unctional block diagram of the proposed transponder. Figure 6 2 S chematic of the proposed ac/dc dc converter and voltage level detector Figure 6 3 S chematic of the receiver circuit

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116 Figure 6 4 Timing diagram of the input signal and recovered clock from the clock recovery block in two modes. Figure 6 5 Schematic of the transmitter.

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117 Figure 6 6 The photograph of the proposed transponder. Figure 6 7 The measurement setup for the proposed transponder.

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118 Figure 6 8 M easured input power vs. output voltage of the proposed AC/DC DC converter. Figure 6 9 Measured reverse leakage current vs. output voltage of the proposed AC/DC DC convert er.

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119 Figure 6 10 Measured timing waveforms of the output voltage of the converter and transponder. Figure 6 11 Measured input signal, envelope output, output data pattern and transponder output using inductive couple powering

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120 Figure 6 12 Measured input signal, envelope output, output data pattern and transponder output using battery powering. Figure 6 13 Measured output signal using signal analyzer. Figure 6 14 Mea sured number of output pulse s vs. battery voltage.

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121 Table 6 1 Summary of the proposed transponder performance. This work Technology 130 nm CMOS technology Power scheme: Near field 13.56 MHz carrier Battery assisted Built in battery Sensitivity: Near field coupling 6.4 dBm Battery assisted 39 dBm Data transmission MOD. OOK Die area 625 1500 m 2

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122 CHAPTER 7 7 CONCLUSION 7.1 Summary This dissertation presents the challenges and benefits of using passive microsystem s for biomedical applications. To maximize the power conversion efficiency, the energy harvester design is crucial. In chapter 3 we present an RF DC multiplier design method that utiliz es the I V curve from the simulation or measuremen t. This method can quickly show the diode size the required number of stage s for the multiplier, and the minimum sensitivity to deliver the output load specifications. The rectifying diode s voltage loss is also very important to the multiplier design. T he Schottky diode provides lower turn on voltage which minimizes the loss associated with the voltage drop. We designed and implemented several types of Schottky diode s in a standard CMOS process. The HF multipliers are designed to evaluate the performanc e of the implemented Schottky diodes. A UHF RF DC multiplier is implemented by using the proposed method, and the simulation results and measured results are presented and discussed. In order to provide reliable communication between the reader and transpo nder, the on chip clock needs to be stable. Moreover, the clock generator consumes most of the power for the passive microsystem. In chapter 4 we present a new architecture of clock generator that us es DPLL. A new calibration free low power clock generato r is presented. A 200 nW DPLL is designed and implemented in a CMOS 130 nm process, and this DPLL is used as a clock generator for the passive transponder. Generating the clock in this way provides a stable clock frequency against process, temperature, and voltage variations, allowing reliable data decoding and encoding. Chapter 5 presents a transpon der that operates under AC input without any AC DC conversion block and DC voltage conditioning block Because the AC DC and DC signal

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123 conditioning blocks consume a large area, b y using th e proposed architecture, th e chip area can be decreased. Moreover this proposed chip u se s the input AC signal as the clock signal for system clock, thus a clock generator is not required for this transponder. In this chip, all the digital circuit s are implemented us ing the AC logic The advantages of this chip are the low cost and small die size The die size of this proposed chip including pads is 0.1292 mm^ 2 The uplink and downlink frequencies are 125 kHz and 915 MHz, res pectively Finally the chapter 6 presents a transponder that can be wirelessly programmed and used for medicine ID and can also be employed in medication compliance. The prototype of the transponder has advantages of both passive and active transponders While this invention is extremely useful for applications that require a chip inside human body, the human body introduces higher loss than in air. The chip utilizes 13.56 MHz for the input carrier frequency and the 915 MHz for the output carrier frequency. The high output frequency can help minimize the antenna size. The transponder has 6.4 dBm sensitivity for near field coupling and 39 dBm for the battery assisting mode, respectively. Since the chip burst rate depend s on the voltage on the converter output, the number of output pulses is proportional to the input power or DC voltage of the chemical battery. Because of this unique characteristic of th e transponder, the vol tage information of the input power level or the DC voltage level of the battery can be wirelessly acquired. 7.2 Future Work This dissertation presents several novel architectures of the transponder and shows the ir applications in the biomedical field While d eveloping and researching the RFID architecture and circuit blocks, several interested topics were discovered which are suitable for future research in

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124 this field. Moreover, RFID transponders are widely used and in the future will be used in biomedical app lications. The following is a list of topics for future research 1. 2. 3. 4. 5. 6.

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125 LIST OF REFERENCES [1] M. Ghovanloo and K. Najafi, "A wide band frequency shift keying wireless link for inductively powered biomedical implants," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 12, pp. 2374 2383, Dec. 2004. [2] T. Akin, K. Najafi and R. M. Bradely, "A wireless implantable multichannel digital neural recording system for a micromachined sieve electrode ," IEEE J. Solid State Circuits, vol. 33, no. 1, pp. 109 118, Jan. 1998. [3] Y. Hang, C. M. Tang and R. Bashirullah, "An asymmetric RF tagging IC for ingestible medication compliance capsules," in IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Bo ston, June 2009. [4] D. Yeager, F. Zhang, A. Zarrasvand, T. Daniel, N. T. George and B. P. Otis, "A 9 uA, addressable gen2 sensor tag for biosignal acquisition," IEEE J. Solid State Circuits, vol. 45, no. 10, pp. 2198 2209, Oct. 2010. [5] B. Ziaie, M. D. Nardin, R. Coghlan and K. Najafi, "A single channel implantable microstimulator for functional neuromuscular stimulation," IEEE Trans. Biomedical Engineering,, vol. 44, no. 10, pp. 909 920, 1997. [6] G. Wang, W. Liu, M. Sivaprakasam and G. A. Kendir, "Design and analysis of an adaptive transcutaneous power telemetry for biomedical implants," IEEE Trans. Circuits and Systems I: Regular Papers, vol. 52, no. 10, pp. 2109 2117, 2005. [7] M. Ghovanloo and S. Atluri, "A wide band power efficient inductive wireless link for implantable microelectronic devices using multiple carriers," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 10, pp. 2211 2221, 2007. [8] EPC radio frequency identity protocols class 1 generation 2 UHF RFID protocol for communi caions at 860MHz 960MHz,version 1.0.9, EPCglobal Inc., 2005. [9] F. Cilek, K. Seemann, G. Holweg and R. Weigel, "Impact of the local oscillator on baseband processing in RFID transponder," in Int. Symp. Signals Systems Electron, Aug. 2007. [10] V. Pi llai, H. Heinrich, D. Dieska, P. V. Nikitin, R. Martinez and K. V. S. Rao, "An ultra low power long range battery/passive RFID tag for UHF and microwave bands with a current consumption of 700 nA at 1.5 V," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 5 4, no. 7, pp. 1500 1512, 1500 1512. [11] Z. Xiao, C. M. Tang, C. Dougherty and R. Bashirullah, "A 20uW neural recording tag with supply current modulated AFE in 0.13um CMOS," in IEEE ISSCC Dig.Tech. Papers, 2010.

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126 [12] Y. T. Liao, H. Yao, A. Lingley B. Parviz and B. P. Otis, "A 3 uW CMOS glucose sensor for wireless contact lens tear glucose monitoring," IEEE J. Solid State Circuits, vol. 45, no. 10, pp. 2198 2209, Jan. 2012. [13] A. Vaz, A. Ubarretxena, I. Zalbide, D. Pardo, H. Solar, A. Garca Al onso and R. Berenguer, "Full passive UHF tag with a temperature sensor suitable for human body temperature monitoring," IEEE Trans. Circuits and Systems II: Express Papers, vol. 57, no. 2, pp. 95 99, Feb. 2010. [14] R. Bashirullah, L. Wentai, J. Ying, A. Kendir, M. Sivaprakasam, W. Guoxing and B. Pundi, "A smart bi directional telemetry unit for retinal prosthetic device," in IEEE International Symposium on Circuit and System, 2003. [15] W. Liu, K. Vichienchom, M. Clements, S. DeMarco, C. Hughs, E. McGu cken, M. Humayun, E. Juan, J. Weiland and R. Greenber, "A neuron stimulus chip with telemetry unit for retinal prosthetic device," IEEE J. Solid State Circuits, vol. 35, no. 10, pp. 1487 1497, Oct. 2000. [16] G. K. Balachandran and R. E. Barnett, "A 110 nA voltage regulator system with dynamic bandwidth boosting for RFID systems," IEEE J. Solid State Circuits, vol. 41, no. 9, pp. 2019 2028, 2006. [17] G. De Vita and G. Iannaccone, "Ultra low power series voltage regulator for passive RFID transponders w ith subthreshold logic," IEEE Electronics Letters, vol. 42, no. 23, pp. 1350 1351, 2006. [18] D. M. Dobkin, The RF in RFID: Passive UHF RFID in Practice, Newnes, 2007. [19] R. R. Harrisonan and C. Charles, "A low power low noise CMOS amplifier for neur al recording applications," Solid State Circuits, IEEE Journal of, vol. 38, no. 6, pp. 958 965, Jun. 2003.. [20] Z. Xiao, T. Chun Ming, C. C. Peng and R. Bashirullah, "A 190W 915MHz active neural transponder with 4 channel time multiplexed AFE," in IEEE Symposium on VLSI Circuits, 2009. [21] S. Rai, J. Holleman, J. N. Pandey, F. Zhang and B. Otis, "A 500W neural tag with 2Vrms AFE and frequency multiplying MICS/ISM FSK transmitter," in IEEE ISSCC Dig.Tech. Papers, 2009. [22] A. P. Chandrakasan, N. Verma and D. C. Daly, "Ultralowpower electronics for biomedical applications," Annual Review of Biomedical Engineering, vol. 10, pp. 247 274, 2008. [23] X. Zou, W. S. Liew, L. Yao and Y. Lian, "A 1V 22W 32 channel implantable EEG recording IC," in IEEE ISSCC Dig.Tech. Papers, 2010. [24] C. A. Balanis, Antenna theory: analysis and design, John Wiley & Sons, 1997.

PAGE 127

127 [25] S. L. a. P. Combes, "On radiating zone boundaries of shor, lambda/2, and lambda dipoles," IEEE Antennas and Propagation Magazine, vol. 46, no. 5, pp. 53 64, 2004. [26] H. P. Shawn, "Electrical properties of tissue and cell suspensions," Advances in Biological and Medical Physics, vol. 5, pp. 147 209, 1957. [27] K. R. Foster and H. P. Schwan, "Dielectric properties of tissues and biolo gical materials: A critical review," Critical reviews in biomedical Engineering, vol. 1, pp. 25 104, 1989. [28] D. C. Barber and B. H. Brown, "Applied potential tomography," Journal of Physics E: Scientific Instruments, vol. 17, pp. 723 733, 1984. [29] S. Gabriel, R. W. Lau and C. Gabriel, "The dielectric properties of biological tissues: II. Measurements in the frequency range 10 Hz to 20 GHz," Phys. Med. Biology, vol. 41, pp. 2251 2269, 1996. [30] R. Harrison, "Designing Efficient Inductive Power Li nks for Implantable Devices," in IEEE International Symposium on Circuit and System, 2007. [31] Friis, "A note on a simple transmission formula," Pro. IRE, vol. 34, pp. 254 256, 1946. [32] J. D. Kraus and D. A. Fleisch, Electromagnetics, McGraw Hill, 1 999. [33] D.M.Pozar, Microwave Engineering, Wiley, 1998. [34] M. S. Wegmuller, "Intra body communication for biomedical sensor networks," PhD dissertation, ETH No.17323, 2007. [35] T. G. Zimmerman, "Personal area network (PAN)," Master thesis, Massac husetts Institute of Technology, 1995. [36] K. Hachisuka, A. Nakata, T. Takeda, Y. Terauchi, K. Shiba, K. Sasaki, H. Hosaka, and K. Itao, "Development and performance analysis of an intra body communication device," in International Conference on Transdu cers, Solid State Sensors, Actuators and Microsystems, 2003. [37] J. R. Tuttle, "Traditional and emerging technologies and applications in the radio frequency identification (RFID) industry," in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 1997. [38] J. Proakis, Digital Communications, McGraw Hill, 2000. [39] K. Finkenzeller, RFID handbook, 2nd ed., Wiley, 2003. [40] IEEE C95.1 2005, IEEE Standard for Safety Levels with Respect to Human Exposure to Radio Frequency Electromagnetic Fields, 3 kHz to 300 GHz, New York: The Institute of Electrical and Electronics Engineers Inc., 2006.

PAGE 128

128 [41] W. H. Ko, S. P. Liang and C. D. Fung, "Design of radio frequency powered coils for implant instruments," Med. Biol. Eng. Comput 15, pp. 634 640, 1977. [42] K. D. Wise, D. J. Anderson, J. F. Hetke, D. P. Kipke and K. Najafi, "Wireless Implantable Microsystems: High Density Electronic In terfaces to the Nervous System," IEEE Proceedings, vol. 92, no. 1, pp. 76 97, 2004. [43] M. Nagata, A. Saraswat, H. Nakahara, H. Yumoto, D.M. Skinlo, K. Takeya and H. Tsukamoto, "Miniature pin type lithium batteries for medical applications," J. of Power Sources, vol. 146, no. 1, pp. 762 765, 2005. [44] U. Karthaus and M. Fischer, "Fully integrated passive UHF RFID transponder IC with 16.7 State Circuits, vol. 38, no. 10, pp. 1602 1609, 2003. [45] R. Barnett, G. Balachandran, S. Lazar, B. Kramer, G. Konnail, S. Rajasekhar, and V. Drobny, "A passive UHF RFID transponder for EPC Gen 2 with 14dBm sensitivity in 0.13um CMOS," in IEEE ISSCC Dig.Tech. Papers, 2007. [46] V. Milanovic; M. Gaitan; J. C. Marshall and M. E. Zaghloul, "CMOS foundry implementation of Schottky diodes for RF detection," IEEE Trans. Electron Devices, vol. 43, no. 12, pp. 2210 2214, 1996. [47] S. Sankaran and K. K. O, "Schottky barrier diodes for millimeter wave detection in a foundry CMO S process," IEEE Electron Device Letters, vol. 26, no. 7, pp. 492 494, 2005. [48] S. I. Cha, Y. H. Cho, Y. I. Choi and S. K. Chung, "Novel Schottky didoe with selfaligned guard ring," Electronics Letters, vol. 28, no. 13, pp. 1221 1223, 1992. [49] J. F Dickson, "On Chip High Voltage Generation in MNOS Integrated Circuits," IEEE J. Solid State Circuits, Vols. SC 11, no. 3, pp. 374 378, 1976. [50] J P Curty, N. Joehl, C. Dehollain, and M. Declercq, "Remotely powered addressable UHF RFID integrated syst em," IEEE J. Solid State Circuits, vol. 40, no. 11, pp. 2193 2202, 2005. [51] G. De Vita and G. Iannaccone, "Design criteria for the RF section of UHF and microwave passive RFID transponders," IEEE Trans. Microwave Theory and Techniques, vol. 53, no. 9, pp. 2978 2990, 2005. [52] S. Sankaran and K. K. O., "Schottky diode with cutoff frequency of 400 GHz fabricated 508, 2005. [53] M. Shur, Physics of Semiconductor Devices, Prentice Hall, 199 0. [54] L. K. L. a. H. C. Luong, "A 7 uW clock generator in 0.18 um CMOS for passive UHF RFID EPC G2 tags," in Europe Solid State Circuit Conference, Sep. 2007.

PAGE 129

129 [55] J W. Lee and B. Lee, "A Long Range UHF Band Passive RFID Tag IC Based on High Q Desig n Approach," IEEE Trans. Industrial Electronics, vol. 56, no. 7, pp. 2308 2316, 2009. [56] V. Najafi, M. Jenabi, S. Mohammadi, A. Fotowat Ahmady, and M. B. Marvasti, "A dual mode EPC gen 2 UHF RFID transponder in 0.18m CMOS," in Proc. IEEE Int. Conf. El ectron. Circuits and Systems, Aug. 2008. [57] C. F. Chan, K. P. Pun, K. N. Leung, J. Guo and L. K. L. a. C. S. Chiu, "A Low Power Continuously Calibrated Clock Recovery Circuit for UHF RFID EPC Class 1 Generation 2 Transponders," IEEE J. Solid State Circ uits, vol. 45, no. 3, pp. 587 599, Mar. 2010. [58] CMOS low dropout linear regulators," Solid State Circuits, IEEE Journal of, vol. 38, no. 1, pp. 146 150, Jan. 2003. [59] J M. Rabaey and A. C. a. B. N. Digital Integrated Circuits (2nd Edition), 2003. [60] W. H. Chen; W. F. Loke and B. jung, "A 0.5 V, 440 Implantable Medical Devices," Solid State Circuits, IEEE Journal of, vol. 47, no. 8, pp. 1896 1907, 2012. [61] P. Raha, "A 0.6 4.2 V low power configurable PLL architecture for 6 GHz 300MHz applications in a 90 nmCMOS process," in Proc. Symp. VLSI Circuits, Jun. 2004. [62] Y. L. Lo ; W. B. Yang and K. H. Cheng "Designing ultra lowvoltag e PLL using a bulk driven technique," in Proc. European Solid State Circuits Conf., Sep. 2009. [63] K. H. Cheng, "A 0.5 V 0.4 2.24 GHz inductorless phase locked loop in a system on chip," IEEE Transactions on Circuits and Systems I: Regular Papers vol. 58, no. 5, p. 849 859, May 2011. [64] W. H. Chen; W. F. Loke and B. jung, "A 0.5 V, 440 Implantable Medical Devices," IEEE J. Solid State Circuits, vol. 47, no. 8, pp. 1896 1907, 2012. [65] R. Barnett and J. Liu, "A 0.8V 1 .52MHz MSVC Relaxation Oscillator with Inverted Mirror Feedback Reference for UHF RFID," in IEEE Custom Integrated Circuits Conference, 2006. [66] S. Briole, C. Pacha, K. Goser, A. Kaiser, R. Thewes and W. Weber, "AC Only RF ID Tags for Barcode Replacement," in IEEE ISSCC Dig.Tech. Papers, 2004. [67] Y. Ye and K. Roy, "QSERL: Quasi Static Energy Recovery Logic," IEEE J. Solid State Circuits, vol. 36, no. 2, pp. 239 248, 2001. [68] M. K. Kazimier czuk, RF Power Amplifiers, Wiley, 2008.

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130 BIOGRAPHICAL SKETCH Chun Ming Tang was born in Taipei, Taiwan. He received his b degree from the National Central University, Chung Li, Taiwan, in 2000, and degree in e lectronics from Nation al Tsing Hua University, Hsin C hu, Taiwan, in 2002. From 2002 to 2005, he was an analog IC design engineer with FrontAnD tec hnology in Hsin Chu, Taiwan, where he worked on limiting amplifiers and laser diode drivers for optical fiber communication applications. Since 2006, he has been working as a research assistant at the Integrated Circuits Research (ICR) Lab under the guidan ce of Dr. Rizwan Bashirullah His research interests include low power and energy harvesting circuits for wireless sensors and RFID applications. Since 2013, he has been part of the circuit design division of the image sensor group at OmniVision working o n various low power circuits for CMOS image sensors.