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Determination of Semiconductor Device Reliability through Electrical and Optical Characterization and Stressing

Permanent Link: http://ufdc.ufl.edu/UFE0044885/00001

Material Information

Title: Determination of Semiconductor Device Reliability through Electrical and Optical Characterization and Stressing
Physical Description: 1 online resource (146 p.)
Language: english
Creator: Cheney, David James
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2012

Subjects

Subjects / Keywords: gan -- hemt -- optical -- reliability -- semiconductor
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The traditional industry-accepted method of determining the lifetime of a semiconductor is based-on acceleration aging through elevated operating temperatures. As the semiconductor technology advances, the determination of device lifetime have yielded unrealistic mean time to failure (MTTF) measurements. High temperature testing does not necessarily manifest all the failure mechanisms that reduce reliability. In order to understand defects that are indeed failure mechanisms requires special tools and different ways of testing. To further the understanding and identification of failure mechanisms in semiconductor devices we introduced the combination of electrical and optical characterization and stress testing. A new tool has been designed and realized that not only performs a suite of electrical tests, but adds optical pumping capabilities. The band-gap of materials like GaN is wide enough that light from the visible spectrum can pump trap energies within the band-gap providing the opportunity to identify defects that have below band-gap energy levels. By employing optical pumping as an excitation method, the response can be measured electrically resulting in a flexible tool to characterize defects. Since some defects merely affect performance and not necessarily reliability, the ultimate goal is to provide a tool that will help identify the correlation between defects and reliability. AlGaN/GaN High Electron Mobility Transistors (HEMTs) were electrically stressed under on-state (VG = 0), off-state (VG TH) and semi-on conditions (VG = -2V) and characterized using optical pumping methods that are indicators of a change in trap density as a result of electrical stressing, since the energy from a specific wavelength of light fills traps whose activation energies are less than or equal to that of the light source. Changes in trap densities were minimal after both off-state and on-state stressing but significant trap creation was observed in HEMTs exhibiting gradual degradation during stressing. Additional testing on transmission line modules yielded no degradation, suggesting the degradation in the HEMTs is related to the gate’s interaction with the channel. From the optical pumping characterization data, using a sum-of-exponential curve fitting algorithm and Arrhenius analysis, the activation energy of traps can be determined by photoexciting with sub band-gap illumination. Specifically, we found traps at 0.14eV, 0.92eV and 0.96eV relative to EC that correspond to substitutional point defect CGa (0.14eV), and antisite NGa (~0.92eV) and the VNH complex (~0.96eV).
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by David James Cheney.
Thesis: Thesis (Ph.D.)--University of Florida, 2012.
Local: Adviser: Pearton, Stephen J.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2012
System ID: UFE0044885:00001

Permanent Link: http://ufdc.ufl.edu/UFE0044885/00001

Material Information

Title: Determination of Semiconductor Device Reliability through Electrical and Optical Characterization and Stressing
Physical Description: 1 online resource (146 p.)
Language: english
Creator: Cheney, David James
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2012

Subjects

Subjects / Keywords: gan -- hemt -- optical -- reliability -- semiconductor
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: The traditional industry-accepted method of determining the lifetime of a semiconductor is based-on acceleration aging through elevated operating temperatures. As the semiconductor technology advances, the determination of device lifetime have yielded unrealistic mean time to failure (MTTF) measurements. High temperature testing does not necessarily manifest all the failure mechanisms that reduce reliability. In order to understand defects that are indeed failure mechanisms requires special tools and different ways of testing. To further the understanding and identification of failure mechanisms in semiconductor devices we introduced the combination of electrical and optical characterization and stress testing. A new tool has been designed and realized that not only performs a suite of electrical tests, but adds optical pumping capabilities. The band-gap of materials like GaN is wide enough that light from the visible spectrum can pump trap energies within the band-gap providing the opportunity to identify defects that have below band-gap energy levels. By employing optical pumping as an excitation method, the response can be measured electrically resulting in a flexible tool to characterize defects. Since some defects merely affect performance and not necessarily reliability, the ultimate goal is to provide a tool that will help identify the correlation between defects and reliability. AlGaN/GaN High Electron Mobility Transistors (HEMTs) were electrically stressed under on-state (VG = 0), off-state (VG TH) and semi-on conditions (VG = -2V) and characterized using optical pumping methods that are indicators of a change in trap density as a result of electrical stressing, since the energy from a specific wavelength of light fills traps whose activation energies are less than or equal to that of the light source. Changes in trap densities were minimal after both off-state and on-state stressing but significant trap creation was observed in HEMTs exhibiting gradual degradation during stressing. Additional testing on transmission line modules yielded no degradation, suggesting the degradation in the HEMTs is related to the gate’s interaction with the channel. From the optical pumping characterization data, using a sum-of-exponential curve fitting algorithm and Arrhenius analysis, the activation energy of traps can be determined by photoexciting with sub band-gap illumination. Specifically, we found traps at 0.14eV, 0.92eV and 0.96eV relative to EC that correspond to substitutional point defect CGa (0.14eV), and antisite NGa (~0.92eV) and the VNH complex (~0.96eV).
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by David James Cheney.
Thesis: Thesis (Ph.D.)--University of Florida, 2012.
Local: Adviser: Pearton, Stephen J.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2012
System ID: UFE0044885:00001


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DETERMINATION OF SEM ICONDUCTOR DEVICE RE LIABILITY THROUGH ELECTRICAL AND OPTIC AL CHARACTERIZATION AND STRESSING By DAVID J CHENEY A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL F ULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2012

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2 2012 David J Cheney

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3 To m y d earest Tana and beloved friend Kye

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4 ACKNOWLEDGMENTS I sincerely thank Dr. Brent Gila and Distinguished Professor Stephen Pearton for their guidance, brilliance, patience, and generosity. Brent has been a good friend for a long time and having this opportunity to work so closely with him h as been not only a whole lot of fun but a real gift. Few people are able to be in the present of genuine brilliance as I have experienced with Dr. Pearton. I also thank Professor Mark Law and my long time friend Professor Toshi Nishida. I appreciate their support, precious time, and effo rt as well as their willingness to be a member of my committee. I am not sure I would have ever finished had it not been for the support of the boy wonder, Rick Deist. T hey cannot possible know how comforting it was to have them build, analyze, program, and run experiments. At times it was over whelming to see how much needed to be done, but it turned out to be not so bad, when we shared the load. I would also like to t hank the other graduate students who journeyed and supported me, Dr. Erica Douglas, Patrick Whiting, T sung S heng K ang, and Liu Lu I extend my appreciation to the staff at the Nanoscale Research Facility for their support and company, Bob Hurt, Scott Gapin ski, Al Ogden, and especially to Paula Mathis. Paula encouraged, supported, planned travel, handled numerous purchases, and just knows! I thank the College of Electrical and Computer Engineering for their patience and willingness to see me through this de gree. Without the graciousness of the department, Shannon Chillingworth and Professor s Gijs Bosman, Mark Law, and John Harris, I probably would not have come back to finish what I started so long ago What were issue s.

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5 I would be remiss if I did not thank those in my life that keep me sane, Fr. Edward McCarthy, Dr. Herb Steier, and John Zokovitch III They help me see that most often it s just If it were not for the support of family, I would not be here my parents, Ra ymond and Betty, my sisters, Cynthia Dor othea and Andrea, my bothers Ray mond Jr. Robert, and Daniel, my nieces and nephews Kyle, Carlyle, Daniel, Ora Rae, Parker, Jack, Ruby, Steven, and Sammy. I save the most important for th e finale, my wife, Dr. Tana Nicholson. She endured this journey long before me and had she not done it with such grace, I probably would have given up. Thank you for your endless patience, support, encouragement, empathy, and love.

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6 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ .. 4 LIST OF TABLES ................................ ................................ ................................ ............ 9 LIST OF FIGURES ................................ ................................ ................................ ........ 10 LIST OF ABBREVIATIONS ................................ ................................ ........................... 12 ABSTRACT ................................ ................................ ................................ ................... 13 CHAPTER 1 INTRODUCTION ................................ ................................ ................................ .... 15 Motivation ................................ ................................ ................................ ............... 15 Research Objectives ................................ ................................ ............................... 16 Disse rtation Outline ................................ ................................ ................................ 17 2 BACKGROUND ................................ ................................ ................................ ...... 18 Gallium Nitride HEMTs ................................ ................................ ........................... 18 Cont act Degradation ................................ ................................ ........................ 19 Inverse Piezoelectric Effect ................................ ................................ .............. 19 Hot Electron Effects ................................ ................................ .......................... 20 Charge Trapping ................................ ................................ ................................ ..... 21 Trap Detection Techniques ................................ ................................ .............. 22 DLTS ................................ ................................ ................................ .......... 22 Lag measurements ................................ ................................ .................... 23 Double pulse technique ................................ ................................ ............. 24 Current transients ................................ ................................ ...................... 24 Luminescence ................................ ................................ ............................ 25 Trap Energies ................................ ................................ ................................ ... 27 3 ELECTRICAL CHARACTERIZATION AND ACCELERATED AGING .................... 31 Characterization and Aging Overview ................................ ................................ ..... 31 Electrical Characterization ................................ ................................ ................ 31 Typical Accelerated Stress Protocols ................................ ............................... 32 DC stress Types ................................ ................................ ............................... 33 Traditional Test Equipment ................................ ................................ ............... 35 Re liability Test Station ................................ ................................ ............................ 38 System Specifications ................................ ................................ ...................... 38 Electrical characterization ................................ ................................ .......... 39 Stress testing ................................ ................................ ............................. 40

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7 Result data storage ................................ ................................ .................... 41 System configuration ................................ ................................ ................. 42 Calibration ................................ ................................ ................................ .. 42 Hardware Subsystems ................................ ................................ ..................... 43 Data acquisition ................................ ................................ ......................... 43 Temperature control ................................ ................................ ................... 46 Optical illumination ................................ ................................ ..................... 47 Gate pulsing ................................ ................................ ............................... 48 Test Station Configurations ................................ ................................ .............. 48 High speed, high voltage configuration ................................ ...................... 49 Long term test configuration ................................ ................................ ...... 49 Optical pumping configuration ................................ ................................ .... 50 Probe station configuration ................................ ................................ ........ 50 Software ................................ ................................ ................................ ........... 50 User interface and control ................................ ................................ .......... 51 Analysis DataViewer and OptFilter ................................ ......................... 60 Device Packaging ................................ ................................ ................................ ... 62 Measurement Circuits ................................ ................................ ...................... 62 DUT Test Boards ................................ ................................ .............................. 63 Summary ................................ ................................ ................................ ................ 63 4 ACCELERATED AGING OF AlGaN/GaN HEMTs ................................ .................. 84 Device Testing Overview ................................ ................................ ........................ 84 AFRL Devices ................................ ................................ ................................ ......... 84 Experimental ................................ ................................ ................................ .... 84 Results ................................ ................................ ................................ ............. 86 Abrupt failures ................................ ................................ ............................ 86 Gradual failures ................................ ................................ .......................... 87 Off state tests ................................ ................................ ............................. 88 Transm ission line modules ................................ ................................ ......... 88 Discussion ................................ ................................ ................................ ........ 89 Vendor A Devices ................................ ................................ ................................ ... 90 5 OPTIC AL PUMPING CHARACTERIZATION ................................ ....................... 102 Overview ................................ ................................ ................................ ............... 102 Related Work ................................ ................................ ................................ .. 103 Tr ap Determination with Current Transients ................................ ................... 104 Optical Pumping ................................ ................................ ................................ ... 105 Visible Light Illumination ................................ ................................ ................. 107 Proof of Concept Experiments ................................ ................................ ........ 108 Trap Detection Experiments ................................ ................................ ........... 109 Experimental setup ................................ ................................ .................. 109 Results ................................ ................................ ................................ ..... 110 Discussion ................................ ................................ ................................ 113 Activation Energies ................................ ................................ ......................... 114

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8 Summary ................................ ................................ ................................ .............. 116 6 CONCLUSION ................................ ................................ ................................ ...... 128 Summary ................................ ................................ ................................ .............. 128 Reliability Test Station ................................ ................................ .................... 128 AlGaN/GaN Device DC stressing ................................ ................................ ... 129 Optical Pumping ................................ ................................ ............................. 131 Future Work ................................ ................................ ................................ .......... 131 APPENDIX A DATABASE SCHEMA ................................ ................................ .......................... 133 B SOFTWARE CLASSES ................................ ................................ ........................ 134 User Interface and Control Application ................................ ................................ 134 Device Drivers ................................ ................................ ................................ 134 GUI ................................ ................................ ................................ ................. 134 Characterization and DC stress ................................ ................................ ...... 135 Device ................................ ................................ ................................ ............ 135 System Hardware ................................ ................................ ........................... 136 Results ................................ ................................ ................................ ........... 136 Optical Pumping Filtering Application ................................ ................................ ... 136 LIST OF REFERENCES ................................ ................................ ............................. 137 BIOGRAPHICAL SKETCH ................................ ................................ .......................... 146

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9 LIST OF TABLES Table page 3 1 Characterization test suite used at MIT for stressing PHEMTs ........................... 64 3 2 Bias Changes for the Different Test Bias States. ................................ ................ 65 3 3 Specifications for the High speed, High Vo ltage Set ................................ .......... 65 3 4 Specifications for the long term test set ................................ .............................. 66 3 5 Temperature control system specifications ................................ ........................ 66 3 6 Lasers incorporated in the optical subsystem of the reliability test system. ........ 66 4 1 DC stress bias conditions for AlGaN/GaN HEMTs supplied by the Air For ce Research Labs ................................ ................................ ................................ ... 92 4 2 Summary of results for AFRL devices that failed the DC stress test with an abrupt change in drain current ................................ ................................ ............ 92 4 3 Summary of results for AFRL devices that did not fail or failed the DC stress test with a gradual change in drain current ................................ ......................... 93 4 4 Summary of results from off state (V G < V TH ) DC stress tests of AFRL devices ................................ ................................ ................................ ............... 94 4 5 DC stress bias conditions for AlGaN/GaN TLMs supplied by the Air Force Research Labs. ................................ ................................ ................................ .. 94 4 6 Summary of results f rom on state (V G = 0) DC step stress tests of vendor A devices ................................ ................................ ................................ ............... 94 5 1 Optical pumping results of AFRL devices that did not show electrical degradation. ................................ ................................ ................................ ...... 117 5 2 Optical pumping results of AFRL devices that failed abruptly. .......................... 11 7 5 3 Optical pumping results of AFRL devices that degraded gradually. ................. 118

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10 LIST OF FIGURES Figure page 2 1 Structure of the bulk and channel in a typical AlGaN/GaN HEMT ...................... 29 2 2 Transition levels for native defects in GaN ................................ ......................... 30 3 1 The I V plot is a basic semiconductor characterization technique ...................... 67 3 2 The four bias states for DUT aging have distinct stress conditions .................... 68 3 3 Three alternatives to a continuous DC stress. ................................ .................... 69 3 4 Temperature control system consisti ng of a PID controller and a thermal electric module. ................................ ................................ ................................ .. 70 3 5 Optical setup showing four lasers mounted on modified x y micro positioners .. 71 3 6 High speed, high voltage test station ................................ ................................ 72 3 7 Long term test station ................................ ................................ ......................... 73 3 8 Optical pumping test station ................................ ................................ ............... 74 3 9 Probe station ................................ ................................ ................................ ...... 75 3 10 Software user interface showing I V plots ................................ .......................... 76 3 11 Software GUI s howing DC stress ................................ ................................ ....... 77 3 12 DUT selection GUI. ................................ ................................ ............................. 78 3 13 Optical Pumping interface. ................................ ................................ ................. 79 3 14 Screen capture of the DataViewer application ................................ .................... 80 3 15 Package schematic for AFRL devices ................................ ................................ 81 3 16 Photographs of the AFRL device wire bonding. ................................ ................. 81 3 17 Measurement Board ................................ ................................ ........................... 82 3 18 DUT Boards with bias tees and with 50 ohm terminations on the gate and drain ................................ ................................ ................................ ................... 83 4 1 Load line test conditions for AlGaN/GaN HEMTs. ................................ .............. 95 4 2 Typical degradation patterns for stressed devices ................................ .............. 96

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11 4 3 Typical pre and post characteristic curves for devices that fail abruptly ............. 97 4 4 Drain current response of device 1330D at two base plate temperatures .......... 98 4 5 Typical pre and post characteristic curves for devices that fail gradually ........... 99 4 6 Typical pre and post characteristic curves for devices that underwent DC stress in the off state (V G < V TH ) ................................ ................................ ....... 100 4 7 P re and post characteristic curves for Vendor A devices ................................ 101 5 1 Drain I V response of an earlier design AlGaN/GaN HEMT (circa 2004) when exposed to a mercury arc lamp. ................................ ................................ ....... 119 5 2 Schematic of the effect that blue light has on traps in the band gap of GaN .... 119 5 3 Effect on traps in the GaN bandgap when exposed by different wavelengths of light. ................................ ................................ ................................ .............. 120 5 4 Absorption coefficients of GaN measured by photothermal deflection spectroscopy ................................ ................................ ................................ .... 121 5 5 Flow graph of the optical pumping procedure. ................................ .................. 121 5 6 Typical response of a AFRL device e xhibiting abrupt degradation. .................. 122 5 7 Typical response of an AFRL device exhibiting gradual degradation ............... 122 5 8 Typical response of a vendor A device ................................ ............................. 123 5 9 Decay of drain current after device was exposed to blue light. ......................... 123 5 10 Amplitudes of exponential determined f rom the waveform decay shown in Figure 5 9 at four of the ten temperatures measured. ................................ ...... 124 5 11 Arrhenius plot of the time constants shown in Figure 5 10 The resultant activation energy was 0.14e V. ................................ ................................ .......... 125 5 12 Decay of drain current after device was exposed to green light. ...................... 125 5 13 Amplitudes at three temperature of exponential de termined from the waveform decay shown Figure 5 12. ................................ ................................ 126 5 14 Arrhenius plot of the time constants shown in Figure 5 12 ............................... 127

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12 LIST OF ABBREVIATION S 2DEG Two dimens ional electron gas AFRL Air Force Research Labs DCLT DC lifetime tests DUT Device Under Test FIB F ocused I on B eam HEMT High E lectron M obility T ransistors LED Light Emitting Diode MTTF M ean T ime to F ailure PAE Power Added Efficiency PID Proportional, Integr al, and Derivative RF Radio Frequency RFLT RF Lifetime Test SPA Semiconductor Parameter Analyzer STEM S canning T ransmission E lectron M icroscopy TEM Thermal Electric Module TLM Transmission Line Module

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13 Abstract of Dissertation Presented to the Graduate S chool of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy DETERMINATION OF SEMICONDUCTOR DEVICE RELIABILITY THROUGH ELECTRICAL AND OPTICAL CHARACTERIZATION AND STRESSING By David J Cheney December 2012 Chair: Stephen J Pearton Major: Electrical and Computer Engineering The traditional industry accepted method of determining the lifetime of a semiconductor is based on acceleration aging through elevated operating temperatures. As the semiconductor technology advances, the determination of device lifetime have yield ed unrealistic mean time to failure (MTTF) measurements. H igh temperature testing does not necessarily manifest all the failure mechanisms that reduce reliability. I n order to understand defects that are indeed failure mechanisms require s special tools and different ways of testing. T o further the understanding and identification of failure mechanisms in semiconductor devices we introduced the combination of electri cal and optical characterization and stress testing. A new tool has be en designed and realized that not only performs a suite of electrical tests, but adds optical pumping capabilities. The band gap of materials like GaN is wide enough that light from th e visible spectrum can pump trap energies within the band gap providing the opportunity to identify defects that have below band gap energy levels. By employing optical pumping as an excitation method, the response can be measured electrically resulting i n a flexible tool to characterize defects. Since some defects merely affect performance and not

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14 necessarily reliability, the ultimate goal is to provide a tool that will help identify the correlation between defects and reliability. AlGaN/GaN High Electro n Mobility Transistors (HEMTs) were electrically stressed under on state (V G = 0), off state (V G < = V TH ) and semi on conditions (V G = 2 V) and characterized using optical pumping methods that are indicators of a change in trap density as a result of elect rical stressing since the energy from a specific wavelength of light fills traps whose activation energies are less than or equal to that of the light source. Changes in trap densities were minimal after both off state and on state stressing but significa nt trap creation w as observed in HEMTs exhibiting gradual degradation during stressing. Additional testing on transmission line modules yielded interaction with the channel. From the optical pumping characterization data using a sum of exponential curve fitting algorithm and Arrhenius analysis, the activation energy of traps can be determined by photoexciting with sub band gap illumination. Specifically we found traps at 0.1 4eV 0.92eV and 0.96 eV relative to E C that correspond to substitution al point defect C G a ( 0.14eV) and antisite N Ga (~0.9 2 eV) and the V N H complex (~0.96eV)

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15 CHAPTER 1 INTRODUCTION Motivation Semiconductor devices have arguably made the most significant contribution to technology in the past fifty years. Advances in technology have provided not just bigger better faster/smaller lighter easier, but more reliable and consistently functioning things: cars almost always start on first turn of the key; telev isions provide beautiful images instantly time and again. A large part of these improvemen ts in reliability can be attributed to the associated improvements in semiconductor device reliability As the understanding of semiconductor materials advance, we must consider the feasibility, capability, and finally its reliability. With regards to the feasibility, does the physics allow us to make it? If the physics allow it, can it actually be realized with the state of the art tools? If we have the technolo gy to create it, can it be made to work consistently, constantly, and reliably? The capability of growing and characterizing GaN material dates back into the 1960s [1] with the first reported light emitting diode (LED) fabricated in 1971 by Pankove et al. [2] The utility of GaN was proven with the maturation of LED technology in the 1 990s [3] an d is now considered to be reliable enoug h to be used in many applications, including visible/white lighting and Blu ray DVDs. The high power, high frequency and high temperature capabilities of GaN as a transistor is currently limited by the fact it has n ot yet reached the reliability of other semiconductor materials such as silicon or gallium arsenide [3 25] The industry accepted method of determining the lifetime of a semico nductor is based on accelerated aging through elevated operating temperatures. This method has

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16 been used for many years in the silicon industry but numerous accelerated stress tests at 200C on AlGaN/GaN high electron mobility transistors (HEMTs) have yielded a mean time to failure (MTTF) exceeding 10 6 hours [8] which does not correspond to actual e xperience. Evidently, high temperature testing does not necessarily reproduce the mechanisms controlling reliability in AlGaN/GaN HEMTs, and since AlGaN/Ga N HEMTs function with many defects, it is a challenge to draw a connection between specific defects and reliability. The reported research has yet to concl usively determine the dominant degradation mechanisms of the devices that result in failure under specific operating conditions in the field. In order to understand the role of defects in AlGaN/GaN HEMT failure mechanisms will require special tools and different ways of testing. Research Objective s The purpose of this research is to further the understanding and identification of failure mechanisms in GaN based transistors using a combination of el ectrical and optical characterization and stress testing. In order to do this, a new tool has be en designed and realized that not only performs the full suite of electrical tests, but adds optical pumping capabilities. The band gap of GaN is wide enough that light from the visible spectrum can pump trap energies within the band gap providing the opportunity to identify defects that have below band gap energy levels. With the availability of diode laser sources at different wavelengths in the visible spec trum, these new methods can be based on readily available components. By employing optical pumping as an excitation method, the response can be measured electrically resulting in a flexible tool to characterize defects. Since some defects merely affect performance and not

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17 necessarily reliability, the ultimate goal is to provide a tool that will help identify the correlation between defects and reliability. Dissertation Outline The main focus of this work is to investigate trapping effects in GaN based HE MTs and how traps affect reliability. The investigation begins in Chapter 2 with a discussion providing background on traps trap detection methods, and how the generation of traps degrades reliability. Chapter 3 describes the development of the system t hat was realized for electrically and optically characteriz ing and stress ing devices. In Chapter 4 the focus is on the devices that were electrical ly stressed using the developed system Optical pumping characterization of the devices stressed in Chapter 4 is presented in Chapter 5 Chapter 6 concludes this body of work, and presents ideas for on going work.

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18 CHAPTER 2 BACKGROUND Gallium Nitride HEMTs The first reported GaN HEMT dates back to 1993 by Kahn [4] after sufficiently high quality heteroepitaxial films were realized, but these devices did not reach the commercial market until 2006 [26] Developments have continued mainl y driven by the need for high power co mmunication systems at microwave frequencies for telecom, military, and aerospace applications GaN is an attractive material for such applications because of its high powe r and high temperature capabilities, its wide band gap (3.4eV ), large breakdown fie ld ( ~ 5x10 6 V/cm) excellent electron transport properties (mobilities greater than 2000 cm 2 /V s), and its thermal stability. The HEMT is a field effect transistor incorporating a junction between two materials with different band gaps, the heterojunction, creating a two dimensional electron gas (2DEG), as the channel Its invention is attributed to Takashi Mimura in 1980 [27] using a n As/AlGaAs device The spontaneous polarization in III V nitrides not present in other III V materials, allows for much larger 2DEG formation than GaAs without additional doping. As a result, the mobility increases since there is no scattering of electrons by ionized dopants. Figure 2 1 shows the most common heterojunction in GaN HEMTs is created between the GaN bulk and a thin layer of Aluminum Gallium Nitride (AlGaN) Similar to a traditional FET, the HEMT is comprised of a gate, a drain, and a source contact. Current flows from drain to source (electron flow is source to drain) and is controlled by the voltage bias on the gate, which uses de pletion to pinch off the channel limiting electron flow in the channel. The contacts on the drain and source are

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19 O hmic allowing for bi directional current flow and are often comprised of metals such as gold and titanium. The gate is a Schottky contact, p reventing outward current flow beyond a threshold voltage when breakdown occurs. The gate contact is generally comprised of a stack of metals including gold, platinum, and nickel. As the device design and material processing technology for AlGaN/GaN HEMTs has matured over the years, several failure mechanisms that limited device lifetime have been addressed and improved. These mechanisms can be grouped together into three main categories that affect lifetime: contact degradation, inverse piezoelectric eff ect and hot electron effects Contact D egradation Both Schottky and Ohmic contacts have shown excellent stability below 300C. Piazza et al. have reported an increase in contact resistance and passivation cracking due to Ga out diffusion and Au inter diff usion after a 100 hour thermal storage test stress at 340C [28] Nickel based Schottky contacts have been shown to form nickel nitrides on GaN at annealing temperatures as low as 200C, resulting in a significant decrease in Schottky barrier height [3] Inverse P iezoelectric E ffect Because of the piezoelectric nature of AlGaN and GaN the lattice mismatch between the material interfaces results in si gnificant tensile strain. If the applied electric field exceeds a critical voltage the strained layer will relax through crystallographic defect for mation. It is possible that the defects could be electrically active and result in device degradation [29], [30] When the electric fiel d is applied under reverse bias conditions and exceeds a critical voltage, typically V DG greater than 20V, Joh et al. show ed degradation in the

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20 drain current with an increase in gate leakage current [31] The degradat ion includes a remarkable increase in source and drain resistance and a positive shift in the th re shold voltage. Because of variation s in epi layer and growth uniformity the critical voltage can vary across a wafer. Chowdhury et al. reported TEM cross sections of devices after stressing with a drain voltage of 40 V and an initial drain current of 250 mA/mm at various base plate temperatures correspond ing to junction temperatures of 250 C, 285 C, and 320 C derived from device modeling [32] Although u nstressed devices showed no evidence of pits or cracks near the edge of the Schottky contact, all stressed devices showed evidence of pit like defects on the drain side of the gate. With a typical depth of about 10nm t he se pits did not extend beyond the AlGaN layer Additionally c rack like defects were found in some of the stressed devices, which appeared t o originate at the bottom of the pit defect, extending to the heterointerface of the AlGaN/GaN layer and occasionally into the GaN buffer. Hot E lectron E ffects GaN HEMTs typically operate at very high drain voltages. Since these devices utilize very sma ll gate geometries (sub micrometer), extremely high electric field values result. Hot electrons are those that have been accelerated in a large electric field, resulting in very high kinetic energy. The impact of these hot electrons can result in trap for mation Creation of traps can occur in both the AlGaN layer and the buffer, leading to reversible degradation of transconductance and saturated drain current [3] T raps under the region between the gate and drain (ungated region) are formed by hot carrier bombardme nt and can be charged negatively. In addition, the electrons may be trapped at the interface between the AlGaN (or GaN cap layer if grown on top) surface and

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21 passivation film. Thus, negative charges can be built up in the ungated region between the gate an d drain and result in an increased surface depletion and a decreased channel carrier density, causing reduction in I D [33] I t is widely accepted that high electric fie lds may limit the reliability of GaN HEMTs, due to the generation of traps or lattice defects induced by hot electrons [34] Charge Trapping An important aspect in determining reliability is the identification of defects in the semicon ductor devices. Since there is not a commercial source of large area, cheap and uniform bulk GaN substrates, AlGaN/GaN HEMTs are typically grown on Si, SiC, or sapphire wafers, resul ting in lattice mismatches that lead to significant biaxial strain and high densities of extended defects. These defects are in some cases, electrically active Trapped el ectron s change the electrostatics and may deplete the channel carrier concentration in the extrinsic drain, resulting in a reduction of the drain current [35 ] Point defects can be in the form of a substitutional (O on a Ga or N site), interstitial (O between a Ga and N site), or vacancy (a missing Ga or N atom in the crystal) and complexes thereof. Examples of structural defects include stacking faults and e dge dislocations. A perfect crystal structure consists of a valence band, a conduction band and no energy levels within the band gap. Energy levels that appear within the band gap are commonly known as traps that are deep level impurities or defects Tr aps may act as recombination centers when there are excess carriers in the semiconductor and as generation centers when the carrier density is below its equilibrium level. In HEMTs, traps are undesirable and can affect device performance and reliability. As a result it is important to detect traps and track their creation. If a trap

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22 type can be identified as affecting reliability, then opportunities to eliminate it can be explored. Trap Detection Techniques Since the focus of this work concerns charge tr apping, different trap detection techniques are reviewed. The most widely used techniques for the characterization of trapping phenomena in GaN HEMTs are discussed [34] DLTS Deep Level Transient Spectroscopy (DLTS) is a popular m ethod that provides insight into the electrical character of point defects [36 39] This method biases a p n junction or a Schottky barrier into depletion causing defects above the Fermi level to release their electrons. A charging pulse that reduces the reverse bias across the junction fill s some of the previously emptied traps and increases the junction capacitance. Once the charging pulse ends, trapped el ectrons are freed at a rate dependent on the energy level of the trap and this reflected the rate at which the capacitance returns to eq uilibrium. The change in capacitance over time is measured over a temperature range. An Arrhenius plot is generated from the collected measurements and activation energies of the traps can be determined. There have been several enhancements to the origi nal DLTS method developed by Lang in 1974 [39] The refinements ra nge from Double Correlation DLTS (D DLTS) where two charge pulses are applied [40] to constant capacitance DLTS (CC DLTS) where the capacitance is held constant during the carrier emission measurement by varying the voltage [41] and to isothermal DLTS where the temperatur e is held constant and the sampling time is varied [42]

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23 Other improvements utilize computer driven signal processing techniques. Since the entire transient is captured by a computer, only one temperature sweep is required. The sampled waveform is processed to det ermine if the signal is exponential with fast Fourier transforms [43] Laplace transforms [44] and other pattern matching techniques. These improvements can have an order of magnitude (depend ent on signal to noise ratio) increase in energy resolution (a few meV) over conventional DLTS, thus the ability to distinguish very similar signals. C DLTS Capacitance deep level transient spectroscopy is based on the analysis of the gate capacitance tra nsient induced by a steep voltage variation. This technique provides information on the properties of the traps located under the gate of the transistors. The main disadvantage of C DLTS is that it cannot be used when the gate area of the devices is too sm all for standard capacitance measurements. I DLTS Drain current deep level transient spectroscopy analy ze s the drain current transients as a function of the channel temperatur e [38] This technique can provide very accurate information on the activation energy and cross section of the trap levels that limit the performance of GaN based transistors. Lag m eas urements Lag measurements involve the delayed response of the drain current due to the presence of trap states Gate lag measurements utilize a gate voltage variation whereas drain lag employ a drain voltage variation. Results of gate or d rain lag measur ements can provide information on the time constants of surface or buffer trapping phenomena There are cases when surface trap s can exhibit the same response as buffer traps when using the capacitive methods and additional measurement is necessary to

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24 make the distinction [45], [46] Faqir et al. [45] used isothermal capacitance transient spectroscopy (ICTS) [42] in addition to DLTS to determine the trap locations. Alter natively, gate lag measurements determine surface trap densities [47] by indicating the recharging of traps as a result of variation of the gate voltage and has been associated with the ionized donor states located on the surface between gate and drain electrodes [35] Gate lag is responsible for the delayed response of the drain current with respect to the gate voltage variation. The gate lag technique involves pulsing the gate voltage from a level below pinch off (V G < V pinch off ) to an on state, typically V G =0 in GaN, while measuring the drain current response. The amplitude and duration of the pulse correlated with the drain current re sponse indicates different trap energies. Consider the case where V G << V pinch off then electron tunneling effects increase with the higher field, filling more traps and decreasing the current flow through the channel. As the V G pulse decreases in dura tion, the trap emission time decreases and fewer traps empty. Mitrofanov [47] demonstrated when using trans ient current spectroscopy (TCS) that observing the emission rates can identify different energies of traps that do not have broad e missions. Double p ulse t echnique The d ouble pulse technique is based on pulsed I D V D measurements, which are carried out by synchronously pulsing the gate and drain voltage of the transistors [3] By double pulse measurements, it is possible to quantitatively evalua te the current collapse in HEMT devices and to compare different devices in terms of charge trapping. Current t ransients An alternative to capacitance transient spectroscopy methods is Photoinduced Current Transient Spectroscopy (PITS o r PICTS). In this me thod the device under test

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25 is stimulated by light, above or below the band gap, and the current is measured as a function of time [48] Its strength is in its ability to characterize conducting as well as semi insulating substrates Luminesc ence As the b r oad suite of electrical characterization methods discussed above would suggest, identifying traps un ambiguously is challenging and other techniques are needed Because GaN and GaAs are direct band gap materials, optical characterization of t rap energy levels and densities through luminescence is an attractive alternative to electrical methods because they are generally non contacting, non invasive, and v ery sensitive. Most of these approaches have become easy to use with automated measuremen ts. L uminescence methods detect the photon emissions of electron hole recombination after light absorption The type of stimulation differentiates the l uminescence technique, but they all collect light emitted by recombination as a result of the stimulati on and have the limitation of not measuring phonon energy due to indirect recombination. Cathodoluminescence CL uses a stream of electrons with a spatial resolution do wn to 1nm. It is particularly useful for III V materials due to their high radiative recombination rate. CL data is acquired by cooling the sample and collecting the light that is emitted [37] The emission of light is due to the impinging electron beam exciting an electron into the conduction band, leaving behind a hole in the valence band. When the electron and hole recombine either across the band gap or between the band edge and a deep level, a photon is emitted. The recombination sites can be from direct band to band, dopant to band, donor acceptor, or from defect transitions in the material.

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26 Radiative recombination sites in III V materials are typi cally extremely high, particularly in GaN, due to high defect densities [49] An advantage of CL over PL is the ability to vary the penetration depth of the incident electrons by varying the electron energy. Photoluminescence PL irra diating the sample with a light source with a wavelength that is larger than the band gap of the material under study. The incident light generates electron hole pairs, which then recombine and emit photons with various energies dependent up on the process of recombination. For PL, these processes can range from intraband transition, free exciton, neutral donor and exciton, ionized donor bound exciton, neutral acceptor bound exciton, donor acceptor pair, Auger transition, phonon emission, etc. Emission of p hotons, observed as luminescence, occurs during these processes except for non radiative recombination sites A variation of photoluminescence is micro photoluminescence (PL) which is simply PL with spatial resolution (down to the wavelength of the stimul ation light) for the study of small areas. Electroluminescence EL is a technique similar to PL and CL in that photon emission is used for characterization of radiative recombination in order to determine trap formation and defect sites. However unlike P L and CL, there is not an incident electron or photon beam that creates electron hole pairs f or recombination. EL uses electrical contacts on the semiconductor material and an applied bia s. Injection of carriers results in electron hole pair formation, wh ich can in turn lead t o photon emission. This is particularly useful for III V materials in order to determine regions of a device that have high densities of radiative recombination sites within the active region.

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27 Trap Energies Luminescence is a powerfu l tool in detectin g and identifying p oint defects in semiconductors, particularly in wide band gap devices in which electrical characterization is limited because of large activation energies that are beyond the reach of thermal excitation P oint defect s in GaN include native isolated defects ( vacancies, interstitial, and antisites ) intentional or unintentional impurities, as well as complexes involving different combin ations of the isolated defects. Several groups using luminescence techniques have iden tified the activation energies of a large number of different defects. Reshchikov and Morko [50] presented a comprehensive and critical analysis of point defects in GaN summarized in Figure 2 2 Guerr a [51] identified deep acceptors containing V Ga as the cause of the yellow band centered around 2.26 eV and 2.07 eV and additionally report s a C N substitutional related emission between 3.2 and 3.108 eV. Lui et al. [52] find that stacking faults on the basal plane are responsible for the strong emission at 3.14 eV a plane stacking faults at 3.33 eV and partial dislocations at 3.29 eV. It has been reported that possible sources of surface stat es in GaN based materials are electrically active states at threading dislocations, and nitrogen vacancies (V N ) and oxygen impurities as shallow surface donors [50] Th e literature can assist in determining the type of defect based on its activation energy [47], [53 67] A surface layer of silicon nitride is the most typical technique to passivate electrically active surface states [3], [35], [54], [68 71] with s ome groups report ing th e surface passivation reduces electron trapping near the AlGaN surface [71 73] The passivation of surface traps has generally meant removal of the trap states to prevent

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28 charge trapping causing the current dispersion because current level s incre ase after passivation indicating that the 2DEG density increases

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29 Figure 2 1 Structure of the bulk and channel in a typical AlGaN/GaN HEMT (A) Heterojunction between the AlGaN and GaN layers (B) Band diagram of AlGaN/GaN heterostructure with 2DEG induced in GaN ( shaded area ).

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30 Figure 2 2 Transition levels for native defects in GaN [68] The colored boxes correspond to the energy range for the wavelength of the displayed color (light pink delineates IR).

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31 CHAPTER 3 ELECTRICAL CHARACTER IZATION AND ACCELERA TED AGING Characterization and Aging Overview The definitive tes t in determining the reliability of a device is to put a statistically valid population of devices into operation and simply wait until they fail. This is not practical if the desired life of a device is 100 or even ten years, so techniques have been crea ted to accelerate aging and predict lifetim es. A desired outcome of the aging process should expose design weaknesses, allowing for improvements. A comprehensive reliability system must include d evice characterization an important aspect of device testi ng and the accelerated aging process Typically devices are first characterized to ensure that they function as designed as well as establish ing baselines for comparison during the aging process Characterization tests could include electrical, thermal, and optical stimulus. Electrical C haracterization Electrical characterization of a semiconductor typically begins with current voltage measurements ( I V ) on both the drain and the gate. A drain I V test holds the gate voltage constant, sweeps the drain v oltage across a range, and the resulting drain current is measured. Figure 3 1 A shows a drain I V plot where the drain is swept from 0 to 5 volts and is repeated four times for gate voltages of 0, 1, 2, and 3V. From this plot saturation currents are observed for each of the gate voltages. As a device degrades, this plot can change showing decreasing saturation currents or an increased drain voltage before the current saturates (a flatter curve). To generate a transconductanc e I V plot, the drain voltage is held constant while measuring the gate voltage as shown in

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32 Figure 3 1 B where V DS =3V and the gate voltage is swept from 2 to 7 volts. A transconductance I V plot reveals important information about a device under test (DUT) : drain leakage current for V G < V TH threshold voltage, V T H maximum transconductance The gate I V provides information about the gate. For Schottky gate s under reverse bias conditions (V G <0) the gate leakage is measured, where an ideal contact has no leakage. Under forward biased the diode characteristics can be determined as current flows into the gate. Typical Accelerated Stress Protocols Typical reliability studies have use the so called three temperature test where devices are tested at different temperatures and an act iv ation energy (E a ) extracted from the relationship ( 3 1 ) where t 1 and t 2 are time to failure at temp erature s T 1 and T 2 constant. To overcome the limitations of the Arrhenius extrapolation to determine a electrical enhancement must be added at realistic operating temperatures. If temperature is the only accelerant, serious errors in estimating device lifetime are not only possible but are likely If more than one degradation mechanism is present, testing at high t emperature and then extrapolating back to the normal device operating temperature may miss the real mechanism that limits the device lifetime at that particular temperature. Additionally, actual failures from the fiel d could be because

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33 of other factors, i n cluding ESD, capacitor defects, assembly and packaging issues, rather than device degradation DC stress T ypes A device can degrade when it is biased under electrically stressful conditions. Figure 3 2 graphically indicates the four testing states that are defined by d ifferent bias conditions [8] 1. High power State. B iased at high current and high voltage. Large vertical and lateral fields 2. ON state B iased to saturation with high current and low voltage. Small vertical and latera l fields 3. OFF state B iased at very small current and high voltage. Large vertical and lateral fields 4. V DS =0 state L arge negative gate voltage with the source and drain shorted at V D =V S =0 High vertical field through the barrier and small fields in the channel The last two states have the advantage of negligible power dissipation and therefore self heating and the complications of evaluating the junction temperature are mitigated. A DC stress test applies a continuous bias for a pre defined period or unt il a level of degradation is achieved. The biases can also be applied in periodic fashions as shown in Figure 3 3 step stress stress recovery, and step stress recovery experiments [8] The step stress test increase s the stress i n a step manner over time allow ing for the observ ation of degradation The str ess recovery experiment applies the stress for a specified time and then the device is allowed to rest for a certain period which is useful in situations of prominent trapping. The step stress recovery experiments is a

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34 combination of the first two experiments in which stress is applied, then the device is allowed to rest, and then the stress is resumed at a higher level. This is useful when evaluating trap formation as a result of the stress. Certain metrics determine when a DUT has reached a level of degradation and can include the following conditions: A drop in drain current A rise in the gate leakage current Changes in source or drain resistance. Shifts in threshold voltage V T While under stress, the above conditions can be monitored so that the test ends if a specified threshold is exceeded. This allows for incremental investigation to observe changes as the DUT degrades. In order to monitor the degradation, measurements o f the DUT are tracked, specifically the voltages and currents on both the gate and drain and the temperature of the device. Other values such as contact resistances, threshold voltage, and transconductance are calculated based on these measurements, expan ding the parameters that can be monitored during a stress test. An example of the parameters that can be used is the characterization suite developed at MIT [74] used when stressing PHEMTs, described in Table 3 1 The test suite is considered benign since it produces reliable and reproducible measurements without affecting the DUT. These measureme nts are made every one to two minutes at specific bias points that are unique to the DUT and must be determined for each device type. With a suite of parameters, degradation can be evaluated beyond the simple measurements of just drain or gate voltage and current. Additional work at MIT reflects a refinement in the characterization suite [8] The measurements are broken into two groups, a coarse characterization and a fine

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35 characterization. The course characterization runs quickly and frequently, every o ne to two minutes. The measurements include V T I DMAX R D and I Goff The fi ne characterization adds complete I V characteristics and run s at the beginning and at the end of an experiment about every 20 min utes, or at other signi fi cant times during an experiment. In addition to exclusive DC testing, radio frequency (RF) signals can be added to the DC bias. RF signals used on AlGaN/GaN HEMTs are generally in the gigahertz frequency range and testing with RF greater than 100 GHz is being performed [3], [75] The measurement taken during RF tests is generally some form of the DUT s power added efficiency (PAE), which is defined as the ratio of the RF power gain over the DC power supplied ( 3 2 ) Discerning the results of RF lifetime tests (RFLT) is difficult since the decrease in RF power output can be the results of many factors [76] unlike DC lifetime tests (DCLT) that can specifically stress different parts of the transistor. The necessity of RFLT is somewhat controversial, since DC tests can be applied to the power and voltage ranges of an RF test [77] and understanding the sources and levels of degrad ation is often ambiguous. Traditional T est E quipment In order to run experiments as previously described, the testing hardware must supply stable voltages at high currents Additionally, c ontrol software coordinate s the hardware and save s the measurements Semiconductor parameter analyzers (SPA) available through companies like Keithley and Agilent are designed for to make

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36 measurements on semiconductors and meet the demands for high power. A high power device can draw a couple of amps at voltages that ma y exceed 100V. Conversely, the gate current measurement requires precision in the nano amp range. controlling the hardware for most any test type as well as collecting and s aving the measurement. These precision instruments are expensive and not economical for long term DC stress tests, because this equipment can only test a single device at a time and many of the test routines can last several days, weeks, and even months. An alternative to using the SPA is a system designed with the sole purpose of testing and aging semiconductors. The industry standard for DCLT and RFLT stations is made by Accel RF the only commercial provider of fully integrated RF accelerated life test /burn in test systems for compound semiconductor devices. Their fully automated turnkey systems determine RF and DC performance degradation with aging to predict life expectancy. The RF Automated Accelerated Reliability Test Station (AARTS) systems are de signed to stress devices with RF, DC, and temperature with each channel having independent control. The RF systems offer the following key features: Up to 36 channels in a 3 bay rack Individual control of each DUTs allows software control of channel temp erature without requiring constant power dissipation Innovative fixture design that support millimeter wave operation High RF power capability (up to 20W per channel) Wide range of DC power designs (60W to 400W) The DC AARTS systems are designed to maximiz e channel density. The DC only systems can accommodate a larger number of channels in the same

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37 footprint (up to 96 channels maximum) and is lower in cost because expensive RF components are not required. In addition to their turnkey systems, Accel RF offer s a wide range of standard and custom fixture designs. The fixtures provide a rich test environment for a DUT including independent temperature control, gate and drain pulse capabilities, and are sealed for environmental/atmospheric isolation (block light and can accommodate N 2 ). They require external DC bias and RF signals. The RF fixtures support millimeter wave up to 96GHz. The system control software called LifeTest performs the following functions: Calibration of RF, DC, and temperature System confi guration d ata storage maintenance, GUI parameters Manual control of RF, DC, and temperature Automatically executes the typical steps an operator might perform to get a device biased up at temperature and ready for the life test run AutoSequencing controls a variety of complex test sequences. For instance, SPA or RF Gain Compression sweeps may be performed automatically at user defined intervals set into an infinite loop, allowing control data to be captured during the elapsed time aging process. Life Test Monitoring c onfigures life test runs, supporting different operating paradigms for controlling the life testing process, from manual to fully automated control. Aggregate a nalysis t ools are data management tool s to extract and process data. It has incorpor ated standard failure models (e.g. Lognormal, Weibull, and Exponential) so that failure and Arrhenius plots can be created, as well as calculate activation energy values directly from the LifeTest data. Accel RF offers a complete test system for manufactur ers of semiconductors who need to test large populations to satisfy the statistics. Researchers who would like to explore alternative ways of testing could be constrained by the pre programmed testing

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38 methods. To incorporate new methods, Accel RF would ha ve to assess the economic consequences before investing in the non recurring engineering costs. Reliability Test Station In order to accomplish the goal of creating new methods for optically and electrically characterizing and stressing semiconductor devic es, a unique tool has been developed An in house design from off the shelf parts such as power supplies and data acquisition and control equipment, wa s preferred over trying to customize a commercially available tool. This in house design provides the n ecessary flexibility to make adjustments as understanding matures The reliability test station can test several DUTs simultaneously and is scalable ranging from a single channel, where one channel controls a single DUT, to a virtually unlimited number of channels through expansion with additional hardware. The hardware consists mostly of commercially available biasing sources (typically DC power supplies), data acquisition equipment, and optical components. The custom control software that works in conju cohesive system. System Specifications A goal of the system was to be able to do all the traditional testing, the electrical characteristic and stress testing as described in the previous section. This means it has to characterize a device, electrically stress it, and measure test results. Periodic measurements must be analyze d in real time during collection to a ss ess the degradation status, as well as, store them for future analysis. All of the DUT biases and taking measurements of the gate voltage V G the gate leakage

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39 current, I G the drain voltage V D the drain current I D and the temperature of the DUT. Its imp ort to note that it is assumed a ll DUTs are tested in a common source configuration Electrical c haracterization E lectrical characterization consists of drain gate and transconductance I V plots, from which key measurements like saturation drain current (I DSS ), transconductance (g m ), and threshold voltage (V T H ) can be determined Measuring the data needed to plot I V curves requires either voltage sweep s of either the drain or the gate under benign conditions (low voltages and low power for very short pe riods of time). In order to maintain benign conditions, the time needed to set the voltage and measure it has to be fast enough to minimize the time under any potentially stressful bias conditions. This can be a challenge when using computer controlled p ower supplies from third party suppliers whose worst case response times to remote commands can be as long as 500ms. For instance, a drain voltage sweep from 0 to 5 volts in 0.1 increments (50 voltage set commands) could take as much as 25 seconds and if this is performed for five gate voltages, the entire test can take over two minutes. A SPA typically perform s these sweeps in a few seconds. Fortunately, the system expedite s the process by using the data acquisition equipment to read the voltage outputs from the power supplies to determine when the set point is reached, since most voltage settings take tens of milliseconds, much less than the worst case specification. A pulsed I V test is similar to gate and drain I V tests, but instead of applying a con tinuous DC voltage when sweeping the bias is modulate d with a pulse at a specified frequency and duty cycle. If the gate voltage is pulsed and the drain voltage held constant a gate lag measurement can be made by observing the delayed response of

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40 the ch annel current. As described in the previous Chapter the gate lag measurement is indicative of the presence of surface traps [47] It also has the added benefit of decreasing self heating, since the DUT is only on for the specified duty cycle. A typical value for duty cycle is ten percent at frequency of 100 kHz, generating a 1S gate pulse. In a similar fashion, t he presence of bulk traps can be measured by holding the gate voltage constant and pulsing the drain voltage, and observing the drain current response. Stress t esting a device will under go the aging process using electrical stress tests in one of the four bias states: ON state, OFF state, High Power state, and V DS =0 state (see Figure 3 2 ). In order to do comprehensive testing, the system must be able to test in all the states and meet the criteria outlined in Table 3 2 Both the High Power and ON states can test under constant voltage or constant current bias conditions Constant drain current requires adjust ment of the gate voltage. A stress test complete s when it has run for a specified amount of time or until a level of degradation is achieved. The system regularly measures, calculates, and compares in order to determine the current degradation status The maximum run time, and the degradation metrics and their levels (deviation from a baseline or absolute value) are specified as part of a tes t definition, such that when exceeded, the stress test stop s Temperature control and measurement is a crucial aspect of DUT accelerated aging. Since activation energies are determined from Arrhenius data, the temperature has to be stable and accurate. W hen dealing with power devices, self heating has a

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41 significant influence on temperature, so the controller must continually monitor and adjust for it. Since temperature is a test parameter, it too can be applied like a bias control: constant, step stress, stress recovery, and step stress recovery. In order to increase flexibility, a reliability test is broken down into a sequence of example of a sequenced stress test is li sted below : Step 1: Temperature set 100C Wait until steady state temperature is reached Step 2: Gate I V : V G S = 6 to 2 in 0.1 incr., V DS = 4 Step 3: Drain I V : V G S = 0 to 4 in 1 incr., V DS = 0 to 10 in 0.1 incr. Step 4: Drain I V Pulse: V GS = 0 to 4 in 1 incr., V DS = 0 to 10 in 0.1 incr., 1MHz @ 10% with V OFF = 5 Step 5: DC Step stress V G S = 0, V DS = 0 to 50 in 1 incr. @ 1hour/incr. Fail @ I D =30% with baseline=5minutes Fail @ R D =10% Result data storage DC stress test measurements are taken every s econd and stored at a user defined interval (minimum of a second) in a S QL database for future analysis, whereas characterization tests require data points to be measured and stored at the fastest rate the system will allow. Large amounts of data during a stress test can quickly accumulate at a rate of 3600 measurements of each point per hour over several days or even weeks. Although large quantit ies of data allow for precise analysis, it is often a burden on computers to process, but through SQL statemen ts data can be reduced by averaging or decimating. O ptical pumping requires the data acquisition hardware to stream readings so there are not any time discontinuities. Data from these tests are not stored in the SQL

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42 database, but in comma separated text files. This is a format that is more suitable for post processing and analysis that is not done in an SQL environment. Since the data streams are transferred from the data acquisition equipment to the host computer in blocks, the data are put into stacks and processed and stored one reading at time. System configuration Because the system is scalable from one channel up to four, the SQL database stores system information. This information is saved in tables which the system control software retrieves prov iding the necessary configuration information. The system configuration is not hard coded in the software, so making changes to the system hardware is as simple as reflecting the changes in the database tables. Appendix A is a diagram of the database sch ema and shows the system configuration tables and fields. Calibration In order to compare the performance of devices the system must accurately measure voltage and current. Since the data acquisition hardware measures voltages, voltage calibration is don e at the hardware level. T he only necessary software calibration is the conversion of current to voltage. Current is determined by measur ing the voltage drop across an in line shunt resistor There is a trade off in the size of the in line resistor. Sma ller resistances are desirable to reduce power loss and voltage drop as currents increase, consequently the small voltage drops across the shunt resistors can fall below system noise levels, making it difficult to measure very small currents. Using differ ential amplifiers as current sensors reduces the noise factor significantly, but will introduce a common mode error, e.g. as the voltage of the drain rises to 60V, the current sensor will have a higher output for the same current measurement made at 5V. Additionally, the current sensors

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43 introduce a measurement error. Calibrating the system against a known measurement at different bias points corrects for the common mode and the measurement error. For this system, the known measurement is read from an Ag ilient 34401 Multimeter with a DC current accuracy of 0.01% of reading. The offsets are stored in the SQL database and applied to each reading. Two correction factors are applied to each drain current reading. The first corrects for the common mode volta ge and the second is an accuracy correction, ensuring that every measurement is the same as the known measurement standard. G ate current readings correct o nly for the common mode error. Some of the data acquisition equipment, the USB oscilloscopes were f ound to have repeatable but not accurate voltage measurements. The measurements were factors to make these devices acceptable for measurement in the system. Syste ms configurations that use this data acquisition equipment have a third level of correction applied. Hardware Subsystems The overall system is comprised of several different subsystems. The system software ties the subsystems together to create the multi channel, multi function accelerated aging test system. Data acquisition The data acquisition system measures the DUT voltages, which includes the drain and gate voltages and the voltage outputs of the current sensing amplifiers. The system is flexible eno ugh to support several different commercially available data

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44 acquisition units. This flexibility provides for the variations in the different test stations described in the next section. Most of the data acquisition hardware is manufactured by National In struments (NI). NI is widely accepted as a leader in the industry and delivers a robust unit with excellent software drivers that integrate into the custom system software. NI CDAQ The CDAQ is a customizable rack of modules. The racks are configured w ith the following hardware: NI 9224 16 analog output module (10V @ 20mA): V G bias NI 9205 32 analog voltage input module (10V 16bit, 250kSa/s ): V G I D I G NI 9229 4 analog voltage input module ( 6 0V 24bit, 50kSa/s ): V D From a software perspective, th e entire rack is sampled as a single unit. The system software queries the CDAQ and reads simultaneously V D V G the voltage output of the drain current sensor (V I D ), and the voltage output of the gate current sensor (V I G ). Although each module has its o wn maximum sampling rate, the combined sampling rate of the rack is limited by the slowest module. The drain voltage module has the slowest sampling rate at 50 kSa/s, but does not limit the rack because it has simultaneous sampling of all four channels wh ereas the other modules use a time division multiplexing (TDM) sampling scheme using a single analog to digital converter This TDM method limits the sampling rate of multiple channels because of the setup time between channels. The tradeoff is between a fast sampling rate and accuracy. NI USB 6259 This unit is monolithic with the following capabilities: 4 analog outputs (10V @ 20mA): V G bias 32 analog voltage inputs (10V, 16bit): V D V G I D I G 48 digital input/output controls (5V):

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45 It has a maximu m sample rate of 1.5 MSa/s for a single channel or 1 MSa/s/channel, i.e., the maximum rate for four channels is 1M 4 or 250 kSa/s. Like the CDAQ, the NI USB 6259 has a TDM sampling scheme which drastically reduces the sampling rate. Because the maximum voltage input is only 10V an external voltage divider is used to reduce the drain voltage input by a factor of eleven. NI USB 6 366 The NI USB 6366 is also monolithic with the following specifications: 2 analog outputs (10V @ 20mA): V G bias 8 analog vo ltage inputs (10V, 16bit): V D V G I D I G 24 digital input/output controls (5V): Because t his unit has simultaneous sampling a dedicated A/D f o r each channel the setup timing issues with the time t o sample each channel at the maximum rate of 2 MSa/S Because the maximum voltage input is only 10V an external voltage divider is used to reduce the drain voltage input by a factor of eleven. HS4 USB oscilloscope In order to perform lag measurements, the voltages and currents must be sampled at a very high rate since the gate is modulated with a 1s pulse. It is desirable to sample the drain current response at least ten times for each pulse, which would require a 10MHz sampling rate. These devices have four analog voltage inputs (80V) which is adequate to measure a single channel of V D V G I D and I G This unit can be configured as a trade off between sample rate and precision. If high a high precision sample (16 bits) is desired, the maximum sample rate is 195.3125 kHz This mode is used when measuring during a DC stress test or

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46 electrical characterization. When using this to measure during a lag test, the unit is configured for high speed (50 MHz) but at only 12 bits of precision. Although this unit claims to stream data, it was determined that it has discontinuities in that it fails to measure while sending data back to the host computer. As a result, these units can not be used when making optical pumping characterization measurements. A continuous response is important when applying curve fitting algorithms to the data as described in Chapter 5. This unit is not linear in its measurements across its voltage ranges. This required software calibration to adjust the readings for accuracy. Temperature control Each channel has a dedicated, autonomous, PID temperature controller (Oven Industries 5R7 002) that reads the temperature of the DUT and maintains the temperature using a thermal electric modules (TEMs). The schematic in Figure 3 4 is an overview diagram of the system and the specifications are outlined in Table 3 5 The TEM is a Peltier device manufactured by Laird Technologies ( Series HT4,12,F2,3030 ). The temperature is measured with a thermistor (Oven Industries TR165 ) mounted on the aluminum test block. The proportional, integrative, and derivative parameters are programmable on this controller and are specific to the application. The trade off is the time it takes th e controller to reach the set point and how close the temperature fluctuates once it reaches the set point. The controller regulates the temperature by pulse width modulating the voltage across the TEM If the settings allow the controller to reach the s et point too quickly, stability is sacrificed and the controller allows the temperature to run away. The final settings allowed a 150 C set point to be reached in less than 15

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47 minutes, with a 0.25 C fluctuation. At lower temperatures, 40 C and lower, th e controller needed the assistance of a fan on the device to maintain temperature stability. The software would also monitor the temperature and would shut down the controller if there as a run away scenario, typically if the temperature exceeded 2 C abov e the set point. Optical illumination A unique part of the system is the addition of the optical capabilities that enable s optical characterization and stressing Table 3 6 lists the light sources used for these experiments, with the corresponding energy and intensity level s T he lasers in the visible range ar e modified off the shelf laser pointers. The batteries are replaced with a DC power supply to maintain constant power output over long period s of time. Shutters are attach ed to each laser as shown in Figure 3 5 and are controlled by the system, allowing for control as part of an automated test sequence. To enable precise positioning t he visible spectrum lasers we re inserted into modified x y tr anslation mounts normally used for lenses The HeCd UV laser wa s permanently mounted and stationary on an optical table, along with the x y translation mounts The DUT is set vertically on an x y z micro positioner It is important to note that the inten sity of each laser is different, so direct comparison of the response of devices to one particular laser cannot be made to another laser of different wavelength. For example, the drain current response of the HEMTs to the violet laser are typically less t han that of the blue laser even though the there is more energy in violet light. Since the blue laser has a much higher intensity (5

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48 10x more power), it affects traps more effectively within the layer structure. Comparisons are only valid for the same wa velength on pre and post stressed HEMTs. Initially the lasers were controlled by switching their power sources. Some of the higher power lasers have a warm up time and their output intensities are inconsistent for the first several minutes. To overcome this issue, shutters were added to each laser and are controlled by the system. Gate pulsing Chapter 2 discusses the value of lag measurements in understanding traps. The system interfaces with an arbitrary waveform generator to create gate pulses. Meas uring the response of the drain current requires high speed data acquisition in order to retrieve enough samples for a consistent measurement. Using a 50MHz USB oscilloscope, the drain current is measured across a 50 power resistor [12], [47] with a differential probe as shown in Figure 3 6 The system averages the last 20 sample s prior to the falling edge of the gate pulse over 50 pu lses to calculate the drain current reading. Test Station Configurations Although there are variations, fundamentally, the test system is either control ling or acqui ring data. Each channel has a temperature control unit and two DC power source s, one for biasing the gate and the other for the drain. The data acquisition equipment measures the voltage and current of the gate and drain, as well as, the temperature. The system is scalable, with each instance of the software controlling at most four c hannels to accommodate more than one stress test at a time and to allow for specialized testing through variations in hardware

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49 High speed, high voltage configuration The high speed, high voltage variation shown in Figure 3 6 disp lays the hardware, comprised of two power supplies, a pico ammeter, and a USB oscilloscope. This combination of the different commercially available off the shelf instruments creates a robust system with accurate measurement, large bias voltages, and high speed measurement. All voltage measurements are made directly by the USB oscillo scope and can handle voltages as high as 80 volts. As the specifications in Table 3 3 s how, the USB scope is multi ranged with three different samp ling precisions (12 bit, 14 bit, and 16 bit) that adjust to accommodate the sampling rate : higher sampling rates have lower precisions During long term DC stress tests, the system samples every second so it takes advantage of the higher precision 16 bit sampling This wider sampling precision is also applied during characterization measurements since the sample speed is dependent on how quickly the power supplies can sweep voltages and not on sample rate of the measurement. When performing gate lag test s with a narrow gate pulse (1 s) the USB scope samples at the maximum speed (up to 50MHz) using the reduced sample precision t o 12 bit s The 50MHz sample rate enables the gate pulse widths to decrease by orders of magnitude into the nanosecond pulse wid th range Since the gate current is measured with a Pico ammeter that has a sample time of 15mS, any readings during gate lag tests are inaccurate and ignored Long term test configuration The long term test s et can stress four devices at a time. This se tup does not have all the capabilities of the high speed, high voltage set, lacking high voltage gate control with a 10 volt range and also the data acquisition is limited to 50k samples per

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50 second. Figure 3 7 shows the hardwar e, comprised of an Instek DC power supply for the drain bias, a National Instruments (NI) analog output module serving as the gate bias supply, an NI high voltage input module (60 volt) that measures the drain voltage, and an NI input module to read gate voltages, gate current and the drain current measurement. Optical pumping configuration The optical pumping station shown in Figure 3 8 has a unique requirement to stream continuously at high speeds. This requirement precludes the data acquisition equipment in the long term station because the TDM sampling is too slow. The USB oscilloscope in the high speed, high voltage station is not able to stream continuously and sacrifices too much precision to sample fast enough The co mpromise is the NI USB 6366 that has 16 bit simultaneous sampling up to 2 MHz. It use s the Instek power supply as the drain bias source. The NI USB 6366 has digital output controls that are used to switch shutters on the different lasers. Probe station c onfiguration The probe station Figure 3 9 is a version of the high speed, high voltage configuration without the gate pulsing capabilities, using a USB oscilloscope for data acquisition. The voltage inputs V D and V G are connect ed to probes on a probe station allowing unpackaged parts to be tested on the system. Software The control software that works in conjunction with the hardware is one of the unique aspects of this tool. The control software is PC based, written in C# usi ng the Microsoft Visual Studio development environment, and will run on any operating system

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51 that supports the Microsoft .NET framework. Since it is developed in house there is considerable flexibility in tailoring the system to perform a specific task. The control software consists of all the drivers for the control and data acquisition hardware, the user interface, and data storage. The NI control and data acquisition hardware comes with a robust set of drivers that seamlessly integrate into the enviro nment. Custom drivers were written from the remote communication command sets for the drain bias power supplies, the USB scopes, and the temperature controllers. An instance of the software controls a maximum of four channels. Each channel tests a single DUT independently with its own set of test parameters. Every set of the software has hardware dedicated to it, specified by the command line and defined by a table in the database. The control software accesses a Microsoft SQL Server database where the t est results DUT information, and the hardware definitions of each channel are stored. All instances of the application interface with the same database, so all results and setup information are stored in one location. Appendix A shows a diagram of the d atabase schema for data storage and system configuration tables. User interface and control The control software is the most complex and largest part of the system. It has been in development for nearly four years with over 15,000 lines of code. It is co mposed of several classes which are described in Appendix B. It executes code in a multi there are as many as seven user threads running: display thread, storage thread, up to four channel threads, data acquisition thread.

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52 An intuitive and accessible user interface is necessary for any level of flexibility. I V plots shown in Figure 3 10 and DC stress results shown in Figure 3 11 are displayed graphically and in real time. The graphical data displayed during a long term DC stress test allow s the user to view the trends of any of the measured or calculated values, such as voltages, currents, contact resistances, etc. The p resent temperature, voltage and current readings are updated every second. Figure 3 12 is an example how a user maps a DUT to a channel by selecting one from a drop down list. Once the data acquisition system starts, the system configures itself based on the test hardware and the selected DUTs. Since the database stores the constraints of each DUT as well as the test equipment, the software can enforce limits so nothing is inadvertently damaged. Over current and over voltage li mits are programmed into the power supplies, which react to damaging conditions instantly. The control software interfaces with the bias power supplies and reads the data acquisition equipment. Because each channel is independently controlled, the communi cations have to be either independent or coordinated so they do not interfere. Each of the drain bias power supplies and each temperature controller is equipped with serial communications capabilities, which allows the computer to communicate with a dedic ated point to point configuration. In order to accomplish this in a system with many channels, the control computer needs many serial ports. Fortunately, there are USB peripherals that expand the number of serial ports, thus enabling each channel thread t o act independently without coordination or concern about interference. For equipment that cannot accommodate one to one communication, coordination is mandatory to eliminate conflicts. For example, the gate bias control on

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53 the NI analog output control mo dule controls the gates for all the channels, so it has to be coordinated in the case where two or more channels are attempting to set a gate bias, so they do not interfere with each other. Coordination of data acquisition requires a separate communication s thread that continuously reads the data acquisition equipment for each of the autonomous channel threads. When a channel needs data it retrieves the data from the communication loop as it becomes available. Devices Tab. Figure 3 12 is a screen capture of the device tab. The screen is divided into four sections one for each channel, since they are individually controlled in a separate software thread. The DUT is selected from a drop down list of devices stored in the databas e. The database tracks the device type and additional information about the device. Once a device is selected from the list, the channel is enabled and measurements are taken with the data acquisition equipment. A channel can be disabled by deselecting the enabled check box next to the device list. Since each device is tested independently, a specific DC stress is defined per device The system is currently designed for three different DC bias conditions: 1. Constant V D and V G Drain and gate voltages are held constant while currents are measured 2. Constant V D and I D Drain voltage and current are held constant while the gate voltage changes to maintain constant drain current. 3. Constant P CH and V G The gate voltage is constant while V D changes to maintain constant channel power dissipation. The power value is specified by the value in the ower The system determines t he DC stress type ( constant bias, step stress, step recovery, or cyclic see Figure 3 3 ) based on which v alues are entered in the test definition.

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54 Constant DC stress Values entered: V START = V END On(s) If a entry the test is divided into the number of specified increments. The length of the increment is d etermined entry By specifying these two values, the characterization tests selected in entry will be performed at every interval. For example in Figure 3 12 on channel one, a gate IV a transconductance, and a drain IV test will be performed on device 1123C every hour for 24 hours. Step stress Values entered: V START V END Incr, On(s) The bias voltage entered in the V START entry and then incremented b END is reached The c Step r ecovery stress Values entered: V START V END Incr, On(s) Off(s), V OFF The bias voltage entered in the V STAR T entry followed by the voltage entered in the Voff entry seconds The on voltage is then increment ed The test ends when the on voltage reaches V END The characterization tests be performed at every interval. Cyclic stress Values entered: V START = V END Off(s) V OFF The bias voltage entered in the V START entry is applied for seconds followed by the voltage entered in the Voff entry This continues for at every interval. A stress test ends either when all the intervals have been performed or when drain current or the gate current cross a specified thr eshold. If a threshold is enabled a baseline measurement is taken after elapsed after the test begins A comparison of the present measurement to the baseline is made every second. The test stops if the current measurement exceeds the The percent change can be either an increase or decrease, but must last for the number By specifying the durati on, a single erroneous measurement will not unintentionally stop the test.

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55 Enable DAQ button begins a data acquisition thread for each enabled channel. Bias power supplies are initialized and the data acquisition equipment is configured. The system then takes measurements every second for each enabled channel and displays them. These measurements include V D I D V G I G and temperature. Data are stored in the database only during characterization and stress tests. If a new device is entered into the database while the software is running, it will not appear in the drop down list D C Stress Tab. Figure 3 11 shows the graphs on the DC stress tab. These strip chart style graphs show the progress of a DC test. The four different graphs can simultaneously show the data from any of the four channels. The data on the graph is selected from the radio buttons: Id, Ig, Vd, Vg, Power, and Temp. A dditional ly on the DC stress tab is a five deep sequence of DC tests. The tests apply to all enabled channels and cannot be assigned to individual channels. A sequence allows a device to be tested in five different ways sequentially. Future plans will deprecate this function with a more robust and flexible scripting capability. Characterization Tab. Figure 3 10 shows the interface for performing characterization tests. Selecting the test using the radio buttons enables the parameters f any of the tests will run. To perform a drain I V characterization test, the gate and drain voltage sweep parameters are entered. The test is performed on an individual device basis, by clicking the button in the upper right hand corner of the graph for the DUT listed in the caption

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56 above the graph. Drain I V tests first sets the gate voltage and then sweeps the drain voltage, while measuring the drain current, before incrementing to th e next gate voltage. Transconductance entered while holding the drain voltage constant. Gate I V tests set the drain bias to zero while sweeping the gate voltage on the characterization tab and measuring the gate leakage current. Puls (gate, drain, or both) is pulsed and the definition of the pulse. The information for the drain and dual pulse is for f uture implementation. The frequency and duty cycle define the pulse width as well as the time between pulses. The off voltage is the bias applied between pulses. The pulsing function only applies to drain I V and transconductance tests. Bias Tab. The DUT can be biased without having to run a test. allows t he drain and gate voltage s to be individually applied for each channel. Calibration Tab. In order to ensure accuracy, the measurement equipment must be calibrated. The calibration is performed and applied at three different levels. 1. Current z eroing. Common mode errors arise when measuring the voltage across a shunt resistor. The common mode voltage is the voltage of t he resistor relative to 2. Drain c urre nt a ccuracy. To correct any errors when measuring current, an offset is applied to every current meas urement. The offsets are determined by applying a known current through a shunt resistor and comparing the systems measurement with an very accurate digi tal multimeter 3. HS4 v oltage a ccuracy. The Handyscope HS4 USB Oscilloscopes fail s to meet the accuracy specifications of the system but has repeatable, correctable measurements By applying a known voltage and comparing the HS4 measurement to a very accu rate digital multimeter, an offset is calculated. The offset is stored in the system database and applied to every reading.

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57 When performing the current zeroing calibration the bias voltage is swept from a specified start to end voltage with a n increment that is selected from a list. The bias circuit is open, thus any current flowing during this calibration would not flow through the DUT Consequently, any measurement is a n error due to the common mode voltage or is current that is flowing into the measu rement circuitry. At every voltage during the sweep, the current measurement is saved into an offset table that will later be subtracted from the total current measurement when a DUT is in the circuit. The drain accuracy test employs a high power resistor as the DUT. The current is swept from zero to the specified max value using the selected increment A very accurate ammeter is included in the circuit and is read by the calibration software. Measurements from the ammeter and system are compared, savin g the difference between the two measurements into an offset table. Whenever a current measurement is made, the offset for that measurement is located in the look up table and applied to correct the inaccuracy. When the common mode voltage (zeroing) off set and the are the same as the high accuracy ammeter. In order to make the accuracy of the measurements made by the Handyscope HS4 USB oscilloscopes acceptable to the system, an offset has to b e applied to each read ing During this calibration, all four inputs of the HS4 are connected to a power supply controlled by the system and swept from 60V to +60V in increments of 0.1 volts. The measurement is compared to a highly accurate voltage meter and the difference for each channel is saved in an offset table. This offset is applied to every measurement made by the HS4 and applied before any common mode or accuracy offsets are

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58 applied. The other data acquisition equipment from National Instrumen ts proved to have the necessary accuracy without needing the application of any correction factors Optical Pumping Tab. Optical pumping tests are performed differently than characterization and DC stress tests. These tests save every raw sample for po st processing and accumulate massive amounts of data very quickly when sampling at rates of 100kHz or more Since the stored samples are raw data and require post processing, it was expedient to not store the results in the SQL database but in separate te xt files. This prevented the database from having to manage the excess data and allowed the results from these tests to be saved on external USB drives. Figure 3 13 shows the optical pumping interface. Optical pumping tests op erate on only one device at a time, so the desired channel is selected from the interface. The gate, drain, and temperature bias conditions are specified, as well as parameters that determine how the drain current is displayed on the graph. The width of the graph is the most current number of minutes with the older data scrolling off the left of the graph. The data displayed on the graph must be averaged to remove ran dom noise T Once the bias conditions and the graphing parameters are specified, the bias can be applied to the DUT. The graph displays the drain current as a strip chart. The optic s can now be adjusted before performing any tests. Since the shutters assigned to the different lasers are controlled by the system, the test mode is set to manual, allowing the shutter to be controlled by the respective butt on on the interface

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59 Because t he system has full control over the recording, biasing, and shuttering, the testing can be automated. T he pre shutter, shutter open, and the post shutter intervals are configurable. When a test begins the system initially prompts the user to the location where the file with the results will be stored on the hard disk. The system begins saving the pre shutter data to the specified file until the pre shutter time elapses. The system opens the shutter for the specified time and then closes it, but continues to save data until the post shutter period has elapsed. Two files are created. The raw samples of V D I D V G I G and temperature, are stored in a comma separated value (CSV). A text file records the events that happen during the recording, marking when the shutter open and closed. In this text file, the user can add tags with a time stamp to indicate when something of significance may have happened. Notes entered in the description box are stored in the text file. To enhance the testing automation, the optical pumping tests are configurable by selecting the testing mode from a list. Simultaneous. When in simultaneous mode, all lasers that have been selected are illuminated at the same time during a recording. Sequenc e The sequence mode allows lasers to be illuminated one at time starting with the longest wavelength selected and ending with the shortest. For example, if Red, Blue, and UV were selected, the sequence would record the pre shutter response, then enable t he red laser and disable it after the specified shutter on time. After completing the post shutter time, the system would do the same thing for blue, then UV. Three different recordings would be stored in this example. Step up. The step up mode function s very similarly to the sequence mode, on time has elapsed. In previous example red would be enabled, then red and blue would be enabled, followed by red, blue, and UV all simultaneou sly enabled.

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60 Step down. The step down mode operates opposite of the step up mode beginning with the shortest wavelength and working towards the longest. Manual. Manual mode allows users to operate the shutters by clicking the respective button. This is generally used to align the device to the optics. Baseline I This mode ignores any buttons selected and will not enable any of the shutters. The baseline current is usually recorded before the DUT has been exposed to any illumination. Error reporting. W hile performing a test many anomalies in the system can occur that may affect the outcome of the test or report problems in the system. Since many of these conditions are inconsequential to the test they may still be of interest for system maintenance. S imply reporting the message to the screen is not useful unless someone is able to view it, and since the system is designed to run long term tests with no user intervention, it is unlikely the message will be seen. As a result, all anomalies are recorded in the Windows logs available from the computer management administrative utilities on called MURI exists to store any messages that the system reports. Analysis DataViewer and OptFilter Because all test results are stored in a SQL database, the user needs a tool to easily retrieve and view the results without having to paste an SQL query result into a plotting program. The Dataviewer provides a graphical interface where a user selects the device and the test to view the results. The user selects the device from the drop down and all the tests that pertain to that device a re listed in the test dropdown. Once a test is displayed, it can be deleted or exported to a comma separated value format so it can be imported into a professional plotting program.

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61 This application also provides a cursor so particular data points can be identified. It also calculates the maximum transconductance value, Gm and graphically determines V TH from the selected Gm v alue as show n in Figure 3 14 Since this is separate independent application, data from tests can be viewed as they are being executed. This is useful on long term stress tests when a user wants to compare initial characteri sti c test results with the latest results to determine changes. A second application was developed to post process data from optical pumping tests. When optically pumping all the raw measurements are stored; a record is created in a comma separated value fil e for each sample. Each record has a time stamp, drain voltage, drain current, gate voltage, gate current, and base plate temperature. The typical sample rate when performing these tests is 100 kSa/S, so files grow large very quickly. Because the store d data are raw and unprocessed, post processing is The OptFilter application, reads the raw data files and averages the data over time. Two parameters determine the data averaging. The first parameter is the destinatio n sampling rate, where blocks of data are averaged to a single sample, e. g., if the raw data sampling rate was 100k Sa/S and the averaged rate is 1k Sa/S, the application averages a block of 100 raw sample into a single sample. The second sample is a box car average similar to the technique used in the original DLTS measurement [39] where current sample is averaged over the previou s number of specified samples, e. g., if this value is 500, the first 500 samples are averaged to determine the first sample, the second sample is the average of the 2 nd through 501 st

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62 sample, the third sample is the average of the 3 rd and the 502 nd sample, etc. This has a smoothing affect. The decision t o save the raw data of the optical pumping tests was made to allow for variation in filtering and post processing. This becomes important wh en applying curve fitting applications to the data. High frequency components in abrupt changes in the signal can be averaged out. Since the raw data are available, different filtering techniques can be utilized. Device Packaging The devices received fro m the AFRL came as diced, quarter wafers. At this stage, t he only way these devices can be tested was on a probe station. The electrical conductance between the probes and the contacts on the devices can be unreliable over a long time. The alternative i s to mount each device into a package and make permanent connections to the DUT. This is the preferred scenario for long term stress testing. Per the recommendation of the AFRL, the parts were mounted in a Stratedge package (pn 580286) and wire bonded us ing 50 ohm strips to improve device stability. The center pins on this package, those used for the gate and drain connections, maintain the 50 ohm transmission line impedance. Measurement Circuits All electrical measurements are taken from the measurement board that connects directly to the DUT board. Measurements of current are made with differential sensors that amplify the differential voltage across shunt resistors located on the measurement board. The connector on the left side of Figure 3 17 is where the DUT

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63 board is attached to the system and all cabling from the bias supplies and the data acquisition equipment connect on the right side. DUT Test Boards Since devices are packaged differently with unique pin definitions, th e test boards are unique to the DUT. Figure 3 18 shows the board, designed by Cobham Sensor Systems, used to test the AFRL HEMTs and has special circuitry to create a bias tee with 50 terminations to maintain device stability. By separating the DUT board from the measurement board, there is flexibility allowing for al most any device layout and keeps the measurement calibration consistent. Summary A comprehensive, yet flexible, semiconductor reliability system has been designed a nd realized. It is multi functional in its ability to perform device characterization tests and gate lag measurements, as well as several different methods of DC stressing, but its ability to optically characterize and stress makes this a unique system. The SQL database stores test results providing flexibility in how data are queried. It also maintains the system configuration information allowing for several different system configurations: high speed/high voltage, long term stress, probe, optical, and portable. By utilizing commercially available data acquisition and power supply equipment, the system is open and scalable.

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64 Table 3 1 Characterization test suite used at MIT for stressing PHEMTs Parameter Definition I Dmax Drain Current @ V DS =5V and V GS =2V R S Source Resistance measured @I G =20mA/mm R D Drain Resistance measured @I G =20mA/mm R TOT Total Resistance between drain and source with gate floating R CH Channel Resistance R TOT R D R S V T V GS 0.5V DS when I D = 1mA/ mm at V DS = 0.1V SS Sub threshold slope at V DS = 0.1V and I D = 1mA/mm DIBL V T |V DS =0.1V V T |V DS =5V g mpk Peak Transconductance dI D /dV GS at V DS =5V V Gpk Gate voltage where g m is maximum at V DS =5V g mpk2 Peak Transconductance dI D /dV GS at V DS =0.1V I Dmin Mi nimum drain current in sub threshold curve at V DS =0.1V V Gmin Gate voltage where I D is minimum at V DS =0.1V I GVT Gate current at V GS = V T and V DS =0.1V V Gon Gate voltage where I D = 1A/mm I Goff Gate current at V GS = 0.5V and V DS =0.1V I Dss Drain current at V DS = 5V and V GS =0V

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65 Table 3 2 Bias Changes for the Different Test Bias States. State Constant Bias Degradation Metric Comment High Power V DS V GS I D I G Constant lateral field V DS I D V GS I G Constant channel power dissipation ON V DS V GS I D I G Constant lateral field V DS I D V GS I G Constant channel power dissipation OFF V GS 0 I G I D Large vertical and lateral fields V DS =0 V DS =0 I G High vertical field through the barrier and small fields in the channel Table 3 3 Specifications for the High speed, High Voltage Set DC Biasing Drain: V D 0 to 60 V DC @ I D 6A DC 300Wmax Gate: V G 40 to 40 V DC @ I G 20A DC Measurement DC stress and characterization 16 bit, 195.31 25 kHz Gate: voltage resolution 6.1V to 2.4mV current resolution 100 fA Drain: voltage resolution 6.1V to 2.4mV current resolution 61 A Gate pulse measurement 12bit, 50 MHz Gate: voltage resolution 97.7V to 39mV current resolution NA Drain: vo ltage resolution:97.7V to 39mV current resolution: 977 A

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66 Table 3 4 Specifications for the long term test set DC Biasing Gate: V G 10 to 10 V DC @ I G 20A DC Drain: V D 0 to 60 V DC @ I D 6A DC 300Wmax Measurement Gate: 16 bit 50kSa/s voltage resolution: 305 V current resolution: 31 nA Drain: 24 bit, 50kSa/s voltage resolution: 7.15 V current resolution: 153 A Table 3 5 Temperature control system specifications Range Up to 200 C Resolutio n 0.01 Stability 0.01C Control PID or Deadband Table 3 6 Lasers incorporated in the optical subsystem of the reliability test system Wavelength (nm) Power (mW) Energy (eV) Red 650 100/300 1.91 Green 532 30/100/300 2 .33 Blue 445 500/1000 2.79 Violet 408 100 3.04 HeCd 325 100 3.81

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67 A ) B ) C ) Figure 3 1 The I V plot is a basic semiconductor characterization techniqu e A ) An example of the drain I V B ) An example of t he transcond uctance plot. C ) An example of t he gate I V plot

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68 Figure 3 2 The four bias states for DUT aging have distinct stress conditions

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69 Figure 3 3 Three alternatives to a continuous DC stress A) Ste p stress incrementally increases the stress conditions. B) The cyclic stress includes periods of recovery. C) Step stress recovery is a combination of the other two. B) C) A)

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70 Figure 3 4 Temperature control system consisting of a PID controller and a thermal electric module.

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71 Figure 3 5 Optical setup showing four lasers mounted on modified x y micro positioners. The DUT and measurement board are on the left side mounted vertically

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72 Figure 3 6 High speed, high voltage test station

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73 Figure 3 7 Long t erm test station

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74 Figure 3 8 Optical pumping test station

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75 Figure 3 9 Probe station

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76 Figure 3 10 Software user interface showing I V plots

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77 Figure 3 11 Software GUI showing DC stress

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78 Figure 3 12 DUT selection GUI.

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79 Figure 3 13 Optical P umping interface

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80 Figure 3 14 Screen capture of the DataViewer application. Users select a device and the test to view results. The test can be exported into formats ready for professional plotting programs.

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81 Figure 3 15 Package schematic for AFRL devices Figure 3 16 Photographs of the AFRL device wire bonding.

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82 Figure 3 17 Measurement Board

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83 A ) B ) Figure 3 18 DUT Boards with bias tees and with 50 ohm terminations on the gate and drain A ) The schematic of DUT board. B ) The physical board.

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84 CHAPTER 4 ACCELERATED AGING OF A l G a N / G a N HEMTS Device Testing Overview Accelerated aging is an important proces s in determin ing the reliability and lifetime of a device The test system described in Chapter 3 was used to electrically and optically stress and characterize devices. Devices from two different vendor s were used in this study. Eight een HEMTs and six t ransmission line modules (TLM) from the Air Force Research Labs (AFRL) underwent accelerated aging. In addition, there were two devices from an undisclosed vendor, called vendor A AFRL Devices Experimental The parts from the Air Force Research Labs that were DC stressed are listed in T able 4 1 with a description of the stress condition. The HEMT layer structures used in these experiments were grown by metal organic chemical vapor deposition (MOCVD) on 6H SiC semi insulating substrates with an unintentio nally doped 3 nm GaN cap, 15nm Al 0.28 Ga 0.72 N barr ier and 2.25m Fe doped GaN buffer. Plasma enhanced chemically vapor deposited SiN was used for device passivation On wafer Hall measurements showed a sheet carrier concentration, sheet resistance, and mob ility of 1.06 10 13 cm 2 /Vs, respectively. The HEMTs had dual submicron Ni/Au gates with dimensions of 0.125 0.14 or 0.17 x 150 m Th e HEMTs employed a Ti/Al/Ni/Au O hmic metallization with a gate periphery of 300 m, source to g ate and gate to drain distances of 2 m with SiNx passivation. The devices w ere packaged and wire bonded as described in Chapter 3.

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85 The devices underwent accelerated aging by DC stress ing at 150 C at three different bias points along the one watt load cu rve, shown in Figure 4 1 : V G = 0 (on state), V G = 2 (semi on) V G < V TH (off state). The bias points were chosen with the expectation of d evices stressed i n the on state mostly experiencing stress on the channel, while gate defects would manifest themsel ves as V G approaches pinch off and V DG approaches the dev [8] Devices that are biased between the on state and off state experience stress on both the channel and the gate. Since a gate bias of V G = 2 is closer to the operating poin t of a transistor in a circuit and because this bias point has the potential to show more interesting results, most of the devices are stressed under this bias condition. To maintain a constant power dissipation of one watt in the channel, V D was adjusted based on the measured I D except in the off state case, where V D was set to constant volt age The stress tests were interrupted when either a 10% change in the drain current or an order of magnitude change in gate current were observed. The initial qu alit y of the devices varied wide ly with less than 20% actually being suitable for stressing post packaging. Devices were initially screen ed on a probe station to determine gate and drain leakage. Parts whose gate leakage was above 0.5 A or with drain leaka ge more than 500 A were not considered for packaging. Once package and wire bonded the devices were screened again. The very first parts to under go stressing exhibited high gate leakage simply because adequate screen ing levels were not yet determined

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86 Results Of t he devices that did degrade, they tended to fail in one of two ways either an abrupt sharp drop D > 10%) or a gradual decline in this current Figure 4 2 is representative of both types of degradation over time. Abrupt failures Table 4 2 lists t he devices that failed abruptly al ong with the difference between the pre to post measurements of I D at V G = 0 and V D = 5, Gm MAX V TH and the gate leakage at V G = 6 and V D =0 The threshold value is graphically determined from the y intercept of the tangent of Gm MAX Figure 4 2 A show s t he typical degradation pattern of an abrupt change while Figure 4 3 shows the typical characteristic results of a device that failed abruptly. The dc characteristic s show little to no change as a result of the DC stress test. This suggest s the degradati on observed was possibly due to contact degradation Since contact failure has been shown to be temperature dependent [3] [10] and t o further support the hypothesis that this is contact failure, the fluctuations in current reduced dramatically as the test base plate temperature was lowered For example device 1330D exhibited abrupt swings in drain current at 150C but when the base plate temperature was reduced to 75 C, the device s stable as shown in Figure 4 4. Typically, these devices will eventually experience another abrupt fa ilure even at the lower base plate temperatures. Although the failure is permanent, the device may recover for a short time. When stressed 24 hours after experiencing abrupt failure, device 1131C began the second stress test at the pre failure drain curre nt, but within a few seconds dropped to the same failure l evel Within an hour during the second test, the device experienced a second

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87 abrupt failure. Furthermore, devices that experience contact failure are often difficult to characterize both opticall y and electrically after they fail. They can recover long enough to get reliable data but it is not predictable. Two devices, 2124C and 2218B both experienced abrupt failure after they had shown some gradual degradation. Device 1622D actually improved before the abrupt failure. Gradual f ailures Most all of the d evices th a t did not exhibit the abrupt drop in current drop tended to have a similar d egradation pattern to that shown in Figure 4 2 B with an initial drop in drain cur rent for the first 1 0 minutes. This has been suggested as resulting from the device reaching a new steady state a s trapping and de trapping reach equilibrium [8] In several of the devices, the current increased before gradually declining to the 10% thresho ld where the test stopped This steady decline in drain current appears to be the result of new trap creation as the optical pumping characterization data in Chapter 5 suggests Figure 4 5 s hows the typical pre and post electric al characteristic I V plots which are indicative of permanent degradation. It is interesting to note that the gate pulse transconductance plot in Figure 4 5 D shows no difference between pre and post stress. Although there are s urface traps present, the magnitude of their effect does not change as a result of the DC stress. This suggests there are not any newly created surface traps and the passivation layer appears unaffected O nly slight changes in reverse gate current w ere me asured, thus there is no trap assisted tunneling leading to leakage paths as a result of newly created traps in the AlGaN [3], [55], [70], [78], [79] Chou [80] reported a s imilar outcome as a result of accelerated stressing and suggested the gate metal is probably not the origin of the

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88 degradation. We disagree with this assertion, based on r esults l ater in this chapter involving TLM stress testing, since it appears the gate is indeed responsible for the degradation. Off state t ests To fully exploit the optical pumping characterization described in Chapter 5, it is important to include device s degraded under off state (V G < V TH ) conditions. Table 4 4 lists the results of the tests. These devices degraded similar ly to the semi on state devices with the except ion of a substantial incre ase in the gate leakage current as the characterization data in Figure 4 6 shows. T ransmission line modules Each sub reticle of the AFRL parts contained several test devices including transmission line modules (TLMs) with spacings of 5m, 10m, 15m, 20m, 25m, and 30m and a 90m width These structure s are essentially a HEMT without a gate, so testing them provides the opportunity to understand and investigate the source gate conduction path. Four different spacings were tested as listed in Table 4 5 ed no degradation until t hey reached a catastrophic bias voltage completely destroying the structure. Three different 10m TLMs were tested. The first structure underwent a step stress, increasing the voltage by one v olt every hour. At 40V, the part was destroyed. To investigate time dependenc ies a second device was stressed at 38 V, two volts below the destructive level of the previously tested device. After 26 hours th is structure failed catastrophically.

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89 Discuss ion We did not observe any of the contact issues wh en testing the TLM structures as we did where the drain current fluctuated or abruptly dropped. Since the TLM structures are on the same reticle with the same O hmic contact metals as the H EMTs, we can conclude that the channel, the source drain conduction path and the O hmic contacts are not the source of degradation of the HEMTs. The degradation appears to be related to the interaction of the gate with the channel. Our expectations of th e semi on tests (V G = 2) to see degradation in both gate and channel, seems to be mostly correct. The addition of the gate appears responsible. When the gate has a bias voltage the devices tended to degrade much more quickly than the devices stressed u nder on state tests which did not degrade as much but exhibited more obvious current fluctuations Because while maintaining constant power dissipation in the channel, the drain voltage increased as the device degraded and the dra in current decreased The drain voltage continued to rise as the device degraded reaching a voltage between gate and drain as high as 17 volts (V GS = 2 and V DS = 15) The voltage did not exceed the critical voltage for these devices under reverse gate bia s step stress conditions determined by Douglas in [29] Consistent with her findings, the gate leakage current did not change This is also consistent in findings from del Alamo [8] under on state conditions where V DG did exceed the devices off state V CRIT levels. T hey concluded that that current by itself is not an accelerating factor [81] but increasing the drain current not only does not enhance degradation, it actually mitigates it On the other hand, we did see device degradation that appears to be gate related with increasing current shown in Figure 4 6 B before degradation begins,

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90 suggesting the degradation we are seeing is a pre cursor to V CRIT The trap creation may indeed lead to the pits and cracks reported by several groups several groups [29 32], [34], [82] From these tests, it is also appears evident that the power dissipated in the channel does affect reliability, since both the devices tested under the on state and the semi on state were tested at the same level of P CH = 1W and degraded very differently. Vendor A Devices Only a total of eight devices were available for testing and of those eight only one met the criteria of low gate and drain leakage currents. A second device was also tested although its initial gate leakage was considered high 52 A versus 1.9 on the first device Very little information was provided with the parts. The devices were AlGaN/GaN with a similar structure as the AFRL parts: dual finger gate whose width of 167 microns (gate width is unknown). They were packaged for high power applications. As a result of the lack of information the parts were stressed under on state conditions (V G = 0), where the drain volt age was increased by a half volt per hour until the drain current decreased by 10% of the initial drain current or if the gate current increase d by an order of magnitude. Unlike the AFRL HEMTs which showed little current collapse while tested in the on sta te, b oth vendor A devices showed substantial degrad ation as the drain voltage increased as outlined in Table 4 6 These parts experienced a minimal shift in the threshold voltage of nearly a quarter volt in the positive direction as show n in the I V plots in Figure 4 7 Interestingly, the gate leakage current improved on both devices

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91 with a substantial reduction of 44 A on device 2 and a micro amp reduction on device 1.

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92 Table 4 1 DC stress bias conditions for AlGaN/GaN HEMTs supplied by the Air Force Research Labs T BASEPLATE V G Drain DUT IDs On s tate 150C 0 P CH =1W 2218C 2318C Semi on 150C 2 V D =9.5V 1622D P CH =1W 1125C 1126C 1131C 1330D 1622D 1623C 2224C 2124C 2218B 2220B 2220C 2419C Off state 150C 5 V D =20V 2320D 1930C 7 V Dstep = 6 to 20V 1128C *Multiple tests T BASEPLATE < 1 5 0C due to contact noise Table 4 2 Summary of results for AFRL devices that failed the DC stress test w ith an abrupt change in drain current. The values are the difference between the pre and post DC stress test. Device Test State Test Hours I D (mA) V G = 0, V D = 5 max (mS) TH I G (A) V G = 6 Comment 2218C On 68 3 3 0.26 0.12 N ois e throughout the test 2318C On 12 4.5 1 0.05 0.22 N ois e begins after 7 hours 1330D Semi on 9 11 5 0.14 .06 Noise T > 75 C 6 6 1 0.19 3.5 1622D Semi on 14 2 38 0.11 25 I D abrupt failure 2124C Semi on 23 32 4 0.09 0.2 I D 8% decrease then abrupt failur e 2218B Semi on 23.6 15 0 0.01 0.07 I D 7.5% decrease then abrupt failure Fully recovers in 3 days. 1131C Semi on 2.5 1 4 0.04 0.06 I D abrupt failure

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93 Table 4 3 Summary of results for AFRL devices that did not fail or failed the DC stress test with a gradual change in drain current. All devices were stress ed in the semi On state (V G = 2). The values are the difference between the pre and post DC stress test. Device Test Hours I D (mA) V G = 0, V D = 5 max (mS) TH I G (A) V G = 6 Comment 1330D 19.3 24 1 0.03 0.13 Noise T <= 75 C 10 NA NA NA NA Minimal 2224C 14.7 84 24 0.35 0.36 I D 10% decrease 2126D 1 3 21 20 0.27 0.61 I D 25% decrease 3 67 18 0.13 0.05 I D 30 % decrease 8 53 17 0.23 0 I D 40 % decrease 2 419C 3.2 64 11 0.62 0.46 I D 10% decrease 1623C 6 5 7 1 0.01 1.8 Minimal 2220C 46.6 35 8 0.02 0.09 I D 10% decrease 2220B 46 29 5 0.15 0.003 I D 10% decrease 2124C 23 32 4 0.09 0.2 I D 8% decrease then abrupt failure 2218B 23.6 15 0 0.01 0.07 I D gradual 7.5% decrease then abrupt failure Fully recovers in 3 days. 112 5 C 3 .67 46 13 0.08 0 I D 10% decrease 1126C 13.3 39 8 0.11 0.06 I D 10% decrease

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94 Table 4 4 Summary of results from off state ( V G < V TH ) DC stress tests of AFRL devices The values s h ow the change as a result of the DC stress test. Device Test Hours I D (mA) V G = 0, V D = 5 max (mS) TH I G (A) V G = 6 Comment 2320D 15.75 18 4 0. 17 1 I G doubles in 6.75 hours 1930C 4.4 58 11 0.46 725.9 Very high g ate leak age 1128C 10.2 20 6 0.02 48.25 V G = 7, V D step 1hr =15 to 16 Table 4 5 DC stress bias conditions for AlGaN/GaN TLMs supplied by the Air Force Research Labs All devices failed catastrophically. Device T BASEPLATE (C) Spacing (m) TTF (hours) V FAILURE (V) E @FAILURE (kV/mm) 2213B Room 5 8.25 15 3 1718B 15 0 10 33 40 4 0629B 150 10 26.6 38 3.8 1627B 150 10 9.8 38 3.8 2211B Room 15 2.4 30 2 2219C Room 20 6.5 45 2.25 Table 4 6 Summary of results from on state ( V G = 0 ) DC step stress tests of vendor A devices The values show the change as a result of the DC stress test. Device Test Hours I D (mA) V G = 0, V D = 5 max (mS) TH I G (A) V G = 6 Comment 1 41.2 34 7 0.25 1.47 I D gradual 1 5 % decrease 2 34.4 55 16 0.31 44.2 I D gradual 10% decrease

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95 Figure 4 1 Load line test conditions for AlGaN/GaN HEMTs.

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96 A ) B) Figure 4 2 Typical degradation patterns for stress ed devices A ) A device that has an abrupt drop in drain current. B) The gradual device d egradation over several hours

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97 A) B ) C) Figure 4 3 Typical pre and post characteristic curves for devices that fail abruptly A ) The d rain I V plot B ) The t ransconductance plot. C) Gate I V plot.

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98 A ) B ) Figure 4 4 Drain current response of device 1330D at two base plate temperatures. A ) At 150 C the fluctuations that appear to be contact failure. B ) At 75 C showing a stable response

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99 A) B ) C) D) Figure 4 5 T ypical pre and post characteristic curves for devices that fail gradually A ) D rain I V plot B ) T ransconductance plot. C) Gate I V plot. D) Pulse Transconductance plot

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100 A) B) C) Figure 4 6 Typical pre and post characteris tic curves for devices that underwent DC stress in the off state (V G < V TH ). A) Drain I V plot. B) Transconductance plot. C) Gate I V plot.

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101 A ) B ) C ) D) Figure 4 7 P re and post characteristic curves for Vendor A device s A ) Device 1 d rain I V plot B ) Device 1 t ransconductance plot. C) Device 2 drain I V plot. D) Device 1 transconductance plot.

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102 CHAPTER 5 OPTICAL PUMPING CHAR ACTERIZATION Overview By exposing AlGaN/GaN HEMTs to below band gap light changes in drain current can be observed that correspond to the trapping and de trapping of carriers within the band gap. These changes in drain current are indicators of trap density, since the energy from a specific wavelength of light pumps trap states whose activatio n energies are less than or equal to that of the light source. To further understand the role traps play in degradation, the energy from sub band gap light of different wavelengths is used to illuminate a device to compare the change in drain current befo re and after electrical stressing [83 88] By limiting the photo energies to below band ga p (visible light), the optical excitation is the result of sub band gap trap states, since no new electron hole pairs are generated as would be the case with illumination at or above band gap. When a device is optically pumped, electrons from the valence band fill traps to the energy level of the illuminated light and empt ies traps that are in the upper half of the band gap into the conduction band. By electron capture, donor traps are neutralized allowing for more current to flow As a result, changes in drain current due to illumination are proportional to the density of traps with energies that correspond to the photon energy of the source light By illuminating the device with progressively shorter wavelengths of light (increasing in energy), the ef fects can be measured incrementally and the energy levels of the effected traps can be determined. Optical pumping techniques have been used extensively to identify traps in AlGaN/GaN HEMTs [47], [53 59], [61 67], [89 95]

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103 Related Work Klein et al. [59 61], [89] reported a method to extract the signatures of specific trap levels that are responsible for current collapse in FET structures. The metho d uses light to photo ionize trapped carriers that are responsible for current collapse. The spectral dependence of this effect should reflect the photo ionization spectrum of the ue characteristic of a specific defect, and uses it to identify a particular trapping center. Their technique begins with exposure to above band gap light to empty traps, followed by application of a high drain source field to fill the traps and induce cu rrent collapse. At this point the device is exposed to sub band gap light. By measuring the optical absorption spectrum associated with the photoionization process that releases the trapped carriers, photoionization spectroscopy provides a method for iden tifying the unique spectral signature associated with each defect responsible for the collapse and a means for acquiring information about the concentrations, photo ionization cross sections, locations and possible chemical identities of the defects involv ed. Their findings resulted in two traps with activation energies at 1.8 and at 2.85 eV As this measurement technique is based upon the reversal of current collapse, it is specifically sensitive to the traps responsible for this phenomenon, but also lim ited to only those traps. Wolter et al. [65], [66] performed similar experiments seeking d eep level defects and surface state s. For doped and undoped HEMTs, the same two defect levels with excitation ene rgies of 3.2 eV and 2.9 eV were determined. Baykan [96] investigated trap energy levels by increment ally photo exciting traps with a monochromator and measuring the drain current response. An increase in the

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104 drain current corresponds to photo ionized trapped electrons, while neutral hole traps with a smaller activation energy than the incoming photon en ergy decreases the drain current. Trap Determination with Current Transients Two groups have recently employed current transient spectroscopy methods to determine trap activation energies [17], [81], [97], [98] in GaN HEMTs. Joh et al. [81] presented a methodology to analyze the trapping and detrapping behavior in GaN HEMTs that is amenable to integration with long term stress experiments. The technique determines the layer location, energy level, and trapp ing/detrapping time constants of the dominant traps. In the trapping experiments, a bias voltage is applied, and the drain and/or gate currents are sampled at certain points in a logarithmic time scale to monitor the carrier trapping. Different bias poi nts are used in order to induce different modes of trapping and at different locations in the device. These bias points include the ON state (high I D and relatively high V DS ) and V DS = 0 state (relatively high negative V GS with V DS = 0). In the detrapping experiments, a trapping pulse in which both the drain and gate voltages are synchronously pulsed is first applied in order to induce carrier trapping. Immediately after removing the trapping pulse, the recovery transient of the current is captured and is analyzed through a curve fitting procedure that extracts the dominant time con stants. et al. [98] employed a similar method using a curve fitting procedure that extracts t he dominant time constants but has a different process of trapping and detrapping. Drain current transients were measured at V GS =1 V and V D S =0.5 V after a one second filling pulse of V GS = 10 V and V D S =0 V. Before any measurements were

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105 made the device under test was illuminated with above band gap light as trap clearing technique. Optical Pumping One of the unique aspects of this research is the information on traps obtained from the use of sub band gap light to photoexcite the traps within the GaN ban d gap. When a device is exposed to sub band gap light, traps in the lower half of the band gap are filled while traps in the upper half are emptied. Figure 5 2 illustrates how the photon energy of blue light (2.7 eV) illuminatio n affects traps within the band gap of GaN When illuminated, traps in the upper half of the band gap, between the conduction band (3.4 eV in GaN) and the dotted line (0.7 eV) in Figure 5 2 have enough energy from the light to de trap the carrier into the conduction band. At the same time traps between the valence band and the solid line (2.7 eV) are filled with carriers from the valence band Figure 5 3 illustrates the impact on traps in the band gap with four different wavelengths of light: red (650nm, 1.91eV), green (532nm, 2.33eV), blue (445nm, 2.79eV), and violet (408nm, 3.04eV). When GaN is illuminated with red light, traps below 1.91eV are filled with electrons from the valence band, while traps with activation energies above 1.91eV empty trapped electrons into the conduction band. When the GaN device is subsequently exposed to green light, only traps between 1.91eV and 2.33 eV are affected. Under these excitation conditions, they will be filled instead of emptied. The same effect occurs for green to blue wavelengths, with traps between 2.33eV to 2.79eV no longer emptied but filled, and likewise for Illumination from blue to violet, affecting traps between 2.79eV and 3.04eV. B y recording the ch ange in drain current between illuminations the effects of traps filled to by each wavelength is measured

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106 In addition to sub band gap light, UV light, whose energy is above the GaN band gap, is used to clear the entire band gap of trap as well as induc e photoconductivity. The role traps play in the response of the drain current to UV energy is less discernible than sub band gap light simply because it is the combination of emptied traps and photoconductivity. For example, if the post stress drain curre nt response to red and green light decreased, but blue and violet increased, then the trap creation occurred in the blue range. The red and green illumination would have an emptying effect on the newly created traps, making them electrically active and de creasing the drain current, while blue and violet would fill the newly created traps, thus removing their effect on the channel and increasing the drain current. active energy of newly created traps can be determined. Throughout the literature, several different types of line and point defects have been observed with a ra nge of mid gap energies [50 52], [69], [99 102] By using light sources of different wavelengths and recording the drain current response to their illuminations, mid gap traps are pop ulated and identified. Not only are energies of mid gap energies determined but an understanding of the trap type may be identified. Once the traps and defects associated with poor device performance and reliability are identified, a correlation of traps created by particular device stressing conditions can be realized. Eventually it is hoped this will lead to optimization in growth recipes and processing for more reliable device structures achieving the goal of identifying traps in AlGaN/GaN HEMT s that adversely affect device reliability

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107 An important goal of this research is bringing together optical and electrical characterization techniques to determine the reliability of devices. The current state of the art reliability testing, described in Chapte r 3, electrically measures and characterizes, calculating several different metrics which can be used to determine a form of degradation during lifetime tests. By incorporating a UV and visible light sources to the reliability test station, new opportunit ies for testing and measuring become available. To add optical characterization to an existing electrical system requires a minimal investment in light sources. The system used for this research, employed commercially available laser pointers. Since it was important to automate the control of the light sources into the system, additional control hardware and software support were incorporated. Additionally, because precise positioning was important, mounting equipment became part of the investment. Be cause of the simplicity of the technique, it does not require a substantial investment. Visible Light Illumination As the devices are illuminated it is important to understand how much of the device is affected. The ideal condition would to entirely expos e the device and affect all traps in all locations. Empirical data suggests that the devices are not fully pumped. As the intensity of the lasers increased, the drain current response increased accordingly. In addition to absorption, contact metals refl ect a large amount of the source illumination. The only exposed surface of the HEMT is the spacing between the source and drain pads less the gate metal and there is further obstruction if a field plate is used. We have experienced penetration of the sou rce contact when it was exposed by a four micron spot from the green laser in a PL system.

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108 For the light able to penetrate the material, the Beer Lambert law suggests the absorption is dependent on the properties of the material through which the light tr avels. ( 5 1 ) Benno [103] studied the properties of GaN using photothermal deflection spectroscopy (PDS) to measure absorption coefficients Figure 5 4 the shorter wavelengths are absor bed in the material while UV, which is off the scale in the figure, has very little penetration into the material. As a result, normalizing the intensity of each wavelength is a challenge is left for future work. Instead, comparisons will be made solely on wavelength basis, i.e., red pre and post stress can be made, but not the comparison of red with blue. Since traps absorb energy, light will not penetrate as deeply when new traps are created. Normalization would then include both absorption in the mate rial and absorption by traps. To ideally normalize the intensity, trap densities would have to be made a priori, on a measurement that is trying to determine trap density. The only solution is to ensure that each wavelength of light has enough excess int ensity to both penetrate and pump all traps. Proof of Concept Experiments [86] a simple 2004 design with gate size of 0.75 x 150 micron similar in st ructure to the AFRL devices described in Chapter 4. The devices were exposed to the full bandwidth of photon energy from a mercury arc lamp which includes IR, visible and UV light, and the devices responded with an order of magnitude increase in drain cur rent. Most of the current increase came from the electron hole generation of the above band gap energy for the

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109 light source, but also had the effect of emptying all traps within the band gap. From Figure 5 1 the device has not recovered from the exposure after 24 hours. This extended recovery time to the pre exposure state indicates numerous traps with time constants longer than 24 hours. The presence of slow traps with time constants on the order of days has been experienced in other devices [95] These originate from traps influenced a measurement occurred when a device was exposed to above band gap light (UV 3.81eV) and all the traps in the band gap are emptied. Once exposed to UV, a device containing these traps would not recover for at least two to three days. Trap Detection Experiments The results of the proof of concept experiments led to more sophisticated experiments with higher intensity lasers that detect changes in traps after a device was stressed. The details of the hardware and software used in these experiments are described in detail in Chapter 3. Experimenta l setup Figure 5 5 is a flow graph of the experimental process. Before the optical response data are collected, the light sources have to be aligned to the device. A light source i s considered aligned when the drain current resp onse is maximized. Alignment begins with the permanently mounted UV source and then each individual light source on the x y translation mounts are adjusted. Measurements of drain source voltage ( V D ), drain source current ( I D ), gate bias ( V G ), gate curren t ( I G ) and temperature are sampled at a rate of either 10 kHz or 100 kHz up to 1MHz, and saved to a file for post processing The devices are biased in the on state while the device is in saturation. The typical bias point is V G =0 and V D = 5 at 30 C. Re cordings in these experiments

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110 include d ten seconds of data prior to exposure, one minute of illumination of the side and several minutes of post exposure to capture the decay to the steady state values. The device temperature is regulated us ing Peltier modules and a PID controller, since temperature stability is critical to minimize thermal effects. then electrically stressed. Post stressed measurements ar e compared to the baseline to determine if new traps have formed, along with their activation energies, derived from the photon energy of the pump wavelength. Since many trap activation energies have been studied and identified [50 52], [69], [99 102] the different trap types such as point defects (vacancies, interstitials, su bstitutional defects and complexes thereof), stacking faults, and edge dislocations can be identified based on the photon energy applied. Identifying the development and persistence of trap types while going through accelerated aging allows for the correl ation of trap types and device reliability. Results AFRL Devices The devices listed in Table 4 2 were characterized before and after stressing. The stress res u lts fall into three categories no degradation, gradual degradation, and abrupt failure. T he devices that showed degradation as a result of electrical stressing had two different responses to subsequent optical pumping As expected devices that did not degrade (see Table 5 1 ) showed no differen ces between the baseline optical pumping results and the post stress tests. D evices that failed abruptly had minimal changes between the baseline and post stress test optical pumping response (see T able 5 2 ), which supports the h ypothesis the failure mechanism in these devices is contact related whereas devices that gradually

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111 degraded had remarkable responses to the optical pumping characterization (see Table 5 3 ) In order to get a sense of how traps a ffect carriers in the channel, Table 5 1 T able 5 2 and Table 5 3 include the number of carriers affected by the change in traps. The number of carriers can be determined by ca lculating the resistivity of the channel from R ON which in this case is the drain voltage divided by the drain current. (5 2) The area, A, is the channel width (300 microns) and the channel height (3 nm). The length, l, is the source drain spacing of 4 microns. Once the resistivity is known, then n, the number of carriers can be calculated, assuming the mobility, is the same and using the average value for these devices, 1907 cm 2 /Vs. The mobility of a device is expected to change as the device degrades with the addition of newly formed scattering points. Although this change in mobility affects the calculation, its effect is minimal with respect to the order of magnitude. ( 5 3 ) The shaded area of the optical pumping plots in Figure 5 6 and Figure 5 7 delineates the response of the drain current when the device was illuminated with a specific wavelengt h of light. The figures show the superposition of all the responses to the individual wavelength exposures. The plots in Figure 5 6 compare the optical pumping response of a typical device that failed abruptly where t he drain c urrent remains relatively stable for a couple of hours and then decline s in a short period of time. The corresponding response to the

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112 optical pumping is unremarkable, with the pre test and post tests almost identical. Some of the devices that failed in t his fashion showed a gradual decline before the abrupt change and the optical pumping also reflected minimal changes. The typical response of a device that gradually is shown in Figure 5 7 t he drain current response to the optic al pumping shows a remarkable change when illuminated with blue and violet light, showing the creation of new trap states. Generally, the most dramatic chang es during optical pumping occurr ed when the devices were illuminated with blue, violet, and UV ligh t In these cases, the drain current response to green and red illumina tion actually decreased after the DC stress. This indicates the creation of new traps in the blue or violet energy ranges, since red and green illumination would empty the newly creat ed traps, thus making them active and lowing the drain current response. Since the blue laser is the most powerful at 500mW, it produces the strongest response, followed by green, violet, and then red wavelengths Although violet has the shortest waveleng th and the highest photon energy, it does not have the same intensity as the blue laser and would be more readily absorbed by the GaN lattice (see Figure 5 4 ) As mentioned in the experimental section, the intensities of the lase rs are not normalized to the same level, so comparisons cannot be made between the different wavelengths, but only of the same wavelength from pre to post stressing. Vendor A Devices The two devices stressed in chapter four also underwent optical pumping characterization. The responses from these two devices were distinctly different than that of the AFRL devices as shown in Figure 5 8 Both devices responded nearly identically in that the only change occurred during UV illumin ation.

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113 This result suggests the device did not degrade as a result of the creation of new traps but from other mechanisms. Discussion The optic al pumping technique shows trap changes in the HEMTs as a result of DC stress ing The devices that degrade slow ly have remarkable changes in the response to optical pumping between the baseline test and the post stress test. This suggests these devices have existing traps in the as grown layer structure or created during processing and the density of these is incre ased by the electrical stressing until they affect the channel carrier density. As described in detail earlier in this chapter, i lluminating a GaN device with sub band gap light energy causes traps within the band gap to fill up to the energy level of th e wavelength that is pumping, e. g., blue light will fill traps up to 2.79eV. For devices that showed little or no increases during green illumination, traps above the energy of green light 2.33eV, have increased suggesting traps that have activation ener gies between the energy levels of green and blue light have increased and affect the device performance. Reshchikov and Morkoc [50] rep ort that point defects with formation energies in the energy range between blue and green light include Ga N substitional and N Ga substitional defects, as well as Ga interstitial point defect s The optical pumping technique indica tes these defects increase as a result of electrical stressing and are delete rious to device performance. The devices that failed quickly did not show much change when optically pumped before and after the DC stress test. Because of the nature of the sudden failure, it appears the devices did not fail due to the increase in trap densities but for other reasons, including increased contact resistance. When these devices are compared

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114 before and after stress using typical I V characterization techniques, they show ed little degradation as describ ed in the previous chapter. The optical pumping response for devices that did not show any electrical degradation also showed little or no changes in trap response as indicated by their optical pumping characterization. Activation Energ ies The previously described characterization method determines energy ranges and trap densities, but with further analysis of the post illumination decay, precise activation energies can be derived. Figure 5 9 shows ten minutes of trap emissions from an AFRL device after the device was illuminated by blue light. Since the decay is exponential in nature, we used a similar technique as in [81] to fit the curve. (5 3) I ss is the steady state current. is the individual time constants of each trap and is the amplitude of the individual exponent for the time constant By assigning an equally spaced arithmetically numbe r of to minimize the error as compared to the measured waveform. As n increases, becomes more accurate and precise, but a typical value of 100 has yielded very good results. Once the curve is fitted and time constant s determined, the process is repeated for several temperatures to determine activation energies from an Arrhenius plot. This process is repeated for different wavelengths of light allowing different traps to manifest themselves based on the different energ y stimuli. Because the decay is believed to be a result of trap emissions and as a form of current transient spectroscopy, the activation energies derived from this process are relative to the conduction band [47]

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115 Figure 5 10 show the amplitudes solved from the curve fitting algorithm. By inspection, the same peak appears at the different temperatures. By extracting the amplitudes for the time constants at each temperature and plotting them on an Arrhenius plot the slope of the data is the activation energy Figure 5 11 shows the results of the analysis determining a trap with a time constant of 260 seconds at 30 C and an activation energy 0.14eV, based on the curve fitting of the wav eform decay in Figure 5 9 From the literature [104] an activation energy of 0.14eV corresponds to a carbon on a gallium site (C G a ) Carbon is a common impurity in MOCVD grown GaN Likewise the process is repeated for green illumination, as shown in Figure 5 12 Figure 5 13 is the amplitude of the exponentials and Figure 5 14 shows the Arrhenius plot, re sulting in two distinct time constant s of 35 and 1 6 2 seconds at 30 C with activation energ ies of 0.92eV and 0. 96 eV respectively It is interesting to note that two defects can have similar activation energies with different time constants. Figure 2 2 shows several point defects that have the same activation energies. Limpijumnong Neugebauer and Van de Walle [68], [69], [102] have estimated the energy levels of the main point defects in GaN through first principles total energy calculations based on densit y functional theory relevant to nitrides From their work, possible point defects in this energy range include antisite Nitrogen and Gallium (N Ga ) and antisite Nitrogen and Gallium ( Ga N ) The high formation energy of the Ga N antisite in n type GaN is ener getically unfavorable, suggesting th ese defect s at 0.92eV and 0. 96 eV are antisite N Ga Szcs [105] et al., performed similar energy calculations when studying hydrogenated defects in group III nitrides. From this research, the V N H complex in GaN

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116 is expected to have a 2+ /0 transition level at about 2.5 eV above the valence band. Reshchikov [50] notes that the hydrogenated vacan cies may lose their hydrogen after the sample is grown, either during cooling down or during postgrowth annealing. Summary Opti cal pumping is a useful non destructive characterization technique for studying traps in electrically stressed AlGaN/GaN HEMTs. From the experiments, we see d evices that failed due to increased trapping showed remarkable changes in the optical pumping responses particularly in the blue wavelength energy level. Traps in the blue energy level include Ga N N Ga Ga I and suggest the se traps are directly related to device performance and reliability. In addition to determining the trap densities and types from the change in drain current while under illumination, we derived trap time constants and activation energies from the return of drain current decay as it returns to its equilibrium. This decay is a result of trap emitting electrons that were filled during illumination. Optical pumping is a simple, easy to implement, inexpensive, non destructive trap detection technique. It sh ows promise in complementing other transient spectroscopy methods like DLTS.

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117 Table 5 1 Optical pumping results of AFRL devices that did not show electrical degradation. Device DC stress Condition Comment R G B V UV 2218C On State V G = 0, P CH = 1W 0 0 1.38 8.04 2.04 11.9 0.94 5.48 NA Pre stress noisy 2318C On State V G = 0, P CH = 1W 0.01 0.06 0.44 2.56 1.24 7.22 0 .03 5.74 NA 2320D Off State V G = 5, V D = 20 0.1 0.6 0.86 5.0 1 1.3 7.57 1.36 7.92 NA Green traps created 1330D Semi on State V G = 2, P CH = 1W 0.7 4.08 0.54 3.15 0 .56 3.26 0 .02 0.12 NA 1623C Semi on State V G = 2, P CH = 1W 0.15 0.87 1.68 9.79 1.93 11.24 0.88 5.13 3.74 21.8 Green traps created T able 5 2 Optical pumping results of AFRL devices that failed abruptly. Device DC stress Condition Comment R G B V UV 1622D On State V G = 0, P CH = 1W 0.85 4.95 1. 67 9 73 0.87 5.07 1.32 7.69 NA 2124C On State V G = 0, P CH = 1W 1.12 6.53 2.87 16.7 0.34 1.98 1.76 10.3 NA Both gradual and abupt failure 2218B Off State V G = 5, V D = 20 0.38 2.21 1.89 11.0 1.76 10.3 1.17 6.82 0.24 1.40 Both gradual and abupt failure 1330D Semi on State V G = 2, P CH = 1W 0.3 1.75 1.18 6.87 1.74 10.1 0.79 4.6 NA 1131C Semi on State V G = 2, P CH = 1W 0.15 0.87 1.68 9.79 1.93 11.24 0.88 5. 13 3.74 21.8 Green traps created

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118 Table 5 3 Optical pumping results of AFRL devices that degraded gradually. Device DC stress Condition Comments R G B V UV 1930C Off State V G = 5, V D = 20 3.32 19.3 5.8 33.8 0.8 4.66 2.84 16.6 NA violet traps created 1128C Off State: V G = 7, V D step 1hr =15 to 16 0.87 5.07 0.22 1.28 0.65 3.79 2.82 16.4 NA blue, violet traps created 2224C Semi on State V G = 2, P CH = 1W 0.3 1.75 2.69 15.7 8.74 50.9 6.41 37.4 NA green, blue, violet traps created 2126D Semi on State V G = 2, P CH = 1W 0.59 3.44 2.14 12.47 6.62 38.6 5.4 31.5 NA traps of many energies created 1330D Semi on State V G = 2, P CH = 1W 1.2 7.0 1.14 6.64 2.66 15.5 3.29 19.2 NA blue, violet traps created 2220C Semi on State V G = 2, P CH = 1W 0.48 2.8 2.28 13.28 3.74 21.8 4.46 26.0 NA traps of many energies created 2220 B Semi on State V G = 2, P CH = 1W 0.52 3.03 1.29 7.52 1.37 7.98 2.86 16.7 7.64 44.5 violet traps created 112 5 C Semi on State V G = 2, P CH = 1W 0.88 5.13 2.95 17.2 4.29 25.0 6.1 35.5 18.0 105 traps of many energies created 1126C Semi on State V G = 2, P CH = 1W 1.12 6.53 1.86 10.8 0.25 1. 46 2.35 13.7 13.1 76.4 violet traps created 2419C Semi on State V G = 2, P CH = 1W 1.5 8.74 1. 7 9.9 5.8 33.8 4.8 28.0 NA traps of many energies created

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119 Figure 5 1 Drain I V response of an earlier design AlGaN/GaN HEM T (circa 2004) when exposed to a mercury arc lamp Figure 5 2 Schematic of the effect that blue light has on traps in the band gap of GaN

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120 Figure 5 3 Effect on traps in the GaN bandgap when exp osed by different wavelengths of light.

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121 Figure 5 4 A bsorption coefficients of GaN measured by photothermal deflection spectroscopy (the green trace) [103] The lasers used in this study are marked by color traces. Figure 5 5 Flow graph of the optical pumping procedure.

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122 Figure 5 6 Typical response of a AFRL device exhibiting abrupt degradation The shaded areas indicate the response when the device was exposed to light. A) T he pr e test response B ) T he post test response Figure 5 7 Typical response of an AFRL device exhibiting gradual degradation The shaded areas indicat e the response when the device wa s exposed to light. A) The pre test resp onse. B) The post test response.

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123 Figure 5 8 Typical response of a vendor A device. The shaded areas indicate the response when the device is exposed to light. A) The pre test response. B) The post test response. Figure 5 9 Decay of drain current after device was exposed to blue light.

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124 Figure 5 10 Amplitudes of exponential determined from the waveform decay shown in Figure 5 9 at four of t he ten temperatures measured.

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125 Figure 5 11 Arrhenius plot of the time constants shown in Figure 5 10 The resultant activation energy was 0.14eV. Figure 5 12 Decay of drai n current after device was exposed to green light.

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126 Figure 5 13 Amplitudes at three temperature of exponential determined from the waveform decay shown Figure 5 12

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127 A) B) Figure 5 14 Arrhenius plot of the time constants shown in Figure 5 12 A) The resultant activation energy is 0. 9 2 eV. B) The resultant activation energy is 0. 96 eV.

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128 CHAPTER 6 CONCLUSION Summary W e have built a characterization a nd electrical stressing system with optical pumping capabilities for use in reliability studies of advanced transistors W e have DC stressed AlGaN/GaN devices under different bias conditions with this system and proven the validity of the optical pumping t echnique. Reliability Test Station O pti cal pumping is a useful non destructive technique for studying traps in electrically stressed AlGaN/GaN HEMTs. In order to demonstrate it s capabilities, a novel, versatile, multi functional tool using off the shelf power supplies, data acquisition, and measurement equipment has been designed, developed, and realized The tool can be used in several configurations, as listed below: Multi channel long term DC stress station High speed, high voltage, pulse measurements station Probe station Optical characterization and stressing station Portable unit It has been used for different device structures including FETs, TLMs and analog switches and with devi ces made from different semiconductors such as Si, GaAs, and GaN O ne aspect that differentiates it from commercial reliability stress systems is its optical capabilities allowing us to use various optical pumping approaches to further understand the role of traps and current on reliability of semiconductor devices T he control software in the tool wa s designed and implemented in house using Microsoft C # and the .NET framework, giving it a high degree of flexibility. The components of the system include:

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129 RS 232 DC power supplies USB data acquisition and control equipment USB oscilloscopes RS 422 temperature controllers USB switching control The results of characterization and stress tests are stored into a SQL database. The ability to access data using SQL has proven to be invaluable when analyzing data. S upport tools to access the data from the SQL database have also been developed. The Data Viewer utility provides a user interface to the test results It has the ability to plot characterization data as I V graphs as well as the strip chart results from DC stress tests. It also calculates V TH from transconductance data. Finally, it has an export funct ion that formats the data for plotting in graphical software applications like Origin and Excel. A filtering utility was needed to handle of the large quantities of data g enerated during optical pumping characterization The application processes raw samples and filters them to reduce the amount of data a nd remove noise from the signal. AlGaN/GaN Device DC stressing Although many more devices were tested as the tools and t echniques were developed, this research includes data from 2 7 devices, 2 1 AlGaN/GaN HEMTS and 6 TLMs. The AlGaN/GaN HEMTs came from three different sources: 1 Sandia Labs, 1 8 AFRL, and two from an undisclosed vendor The Sandia Labs device helped with bas ic understanding as we conducted proof of concept experiments. Using these devices, w e were able to demonstrate the use of opti cal pumping during reliability testing was feasible

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130 The AFRL devices were th e subject of most of the research. The two dominant failure mechanisms during DC stressing were gate contact failure and trap creation beyond threshold electric field strengths The devices that exhibited gate failure did not show any current collapse but always manifested rapid and sharp fluctuations in drain current. They usually failed with an abrupt drop in drain current. Other devices that failed did so because of trap creation and experienced a gradual and permanent drain current collapse. The TLM structures all failed in catastrophic ways without showing any sign of degradation b efore the device failed We were able to observe a time dependent critical vol tage for the 10 m structure. For example, these devices failed instantaneous ly at 40V (4kV/mm) but laste d between 10 and 27 hours at 38V (3.8k V/mm) Similarly, Douglas [79] tested a 5 m structure that failed catastrophically at 27V (5.4kV/mm) with a base plate temperature of 100 C Because the TLM structures did show any indication of deg radation before catastrophic failure we can conclude that the failures experienced in the HEMTs were not a result of the channel portion of the HEM T, includ ing the Ohmic contacts. T he failure appears to be related to the gate and its interaction with the channel. A s reported by several groups [29 32], [34], [82] the bias on the gate leads to crack s and pits in the AlGaN layer below the gate edge on the drain side The cracks are caused by the piezoelectric nature of AlGaN and GaN, and the relaxa tion of the strained layer through crystallographic defect formation. We hypothesize the cracks develop from pits, and pits begin with a void due to the migration of vacancies in the crystallin e

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131 structure. By detecting trap formation, we can see the beg inning of this chain of degradation using the optical pumping technique Optical Pumping The optical pumping characterization confirmed d evices that failed the DC stress ing as a result of increased trapping (gradual degradation) showed remarkable changes i n the before and after optical pumping characterization responses particularly at blue light wavelengths. The literature shows that t raps at these energies include Ga N N Ga Ga I and suggest these types of traps are directly related to device performance and reliability. Devices that did not fail the DC stress or failed with a gate contact failure show ed minimal differen ces in the optical pumping experiments, showing that trap creation was not the cause of failure We also investigat ed the decay rates o f the drain current after the device was illum inated. When the light energy was removed, carriers we re emitted from deep traps with l ong time constants, causing a delay in the drain current returning to equilibrium Using a sum of exponential curve fitti ng technique, we analyzed the decay rates and activation energies of two traps. Using the blue laser as our source, we extracted an activation energy of 0.14eV, corresponding to carbon on a gallium site (C G a ) The green laser yielded an activation energy of 0. 96 eV, corresponding to Gallium and Nitrogen antisite ( N Ga ) and the V N H complex [50] Future Work The current optical pumping setup has limitations that need to be addressed in on going work. One of the challenges in the current setup is the alignment of light source s wher e each laser is individually adjusted on a fixed device The process of adjusting the optics to maximize the current response affects baseline measurements

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132 where the filling of slow traps can caus e a delay of several days as a device return s to its dark e quilibrium. If all of the light sources can be permanently aligned to a single point, then only the device needs to be adjusted. Ideally, all light sources sh ould be perpendicular to the device. Another limitation is the inability to fully pump devices w ith light sources that have different intensities. Without the normaliz ation of intensities, it is difficult to determine the contribution of each wavelength. Often times we observed the effect of traps from blue and violet light but could not discern t he contribution of each source. If the intensities were normalized and were able to fully pump the device, we would be able to determine the contributions. Normalizing the intensities is a challenge, since different wavelengths are absorbed differently an d the creation of new traps will require more photon energy In the current technique we need ed to use other characterization tools such as lag measurements to determine the spatial location of the traps. By incorporating illumination while making the lag measurement, spa tial information may be obtained In this work we began investigating using illumination as an ac celerated aging stressor, but did not have enough devices to gather the systematic data needed to understand how the traps were being affected by the different wavelengths of light. Future work can continue this investigation and understand how continual illumination during stressing affects existing traps and the creation of new traps. Since illumination affects the drain current, stressing w hile optically pumping can lead to the understanding of how increased current affects reliability at the same bias voltages.

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133 APPENDIX A DATABASE SCHEMA

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134 APPENDIX B SOFTWARE CLASSES User I nterface and C ontrol Application Device Drivers Agilent8114 Class Reference Device driver for an Agilent 8114A High Power Pulse Generator Agilent34401 Class Reference Device driver for an Agilent 34401 Digital Multimeter HandyScope.HS4Diff Class Reference Device driver for the Handyscope HS4Diff USB oscilloscope HandySco pe.HS4Settings Class Reference Contains the c urrent settings for a Handyscope HS4Diff USB oscilloscope PA9103 Device driver for RBD Instruments PA9103 picoammeter PSM6003 Device driver for Instek PSM6003 DC power supply DG1022A Device driver for the Rigol DG1022A arbitrary waveform generator gate pulsing TCtrl5C7_200 Device driver for Oven Industries 5C7_200 temperature controller DDS3005 Device driver for Hantek DDS3005 arbitrary waveform generator gate pulsing DDSCon Dynamic link library for Hantek D DS3005 arbitrary waveform generator GUI FormRelSys Main Form Class DC_PLOTDATA DC stress results that will be displayed on the GUI stripchart DC_GRAPH Plots DC stripcharts

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135 GraphKeyHelp Opens help form to show key shortcuts for graphs Characterization and D C stress GATE_IV Performs gate I V characterization tests DRAIN_IV Performs gate I V characterization tests GatePulse Initializes the gate pulse hardware for gate I V characterization tests PULSE_IV Initialize for a pulse I V characterization test IV_PARAM S Parameters for a drain I V characterization test Gm_PARAMS Parameters for a transconductance I V characterization test PULSE_PARAMS Parameters for a pulse I V characterization test DC_PARAMS Parameter for a DC stress test DEVICE_LIMITS Maximum and minimu m limits for a device RESULT_RECORD Results of a test, containing timestamp, V D I D V G I G temperature LogError.ErrorHandler Class Reference Global error handler Device DUT Device under test contains test parameters and t est hardware information DUT_THRESHOLD Thresholds that defines when a device has failed OPT_PUMP Optical pumping object

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136 System Hardware DAQ Channel hardware object DAQ_CHANNEL Data acquisition settings for a hardware channel DAQ_HW Channel data acquisition hardware settings DAQ_READINGS Raw readings from the data acquisition CALIBRATION System calibration object: I D and I G OPT_PUMP_HW Hardware used for optical pumping Results SampleData2File Controls result stack for data to be stored during optical pumpin g SQLdb Saves tests results to SQL database OPT_PUMP_RECORD Result record from a sample during an optical pumping test Optical Pumping Filtering Application AvgData Averages input data OptPumpFilter Applies boxcar filtering PLOTDATA Sends averaged and filt ered data to GUI

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146 BIOGRAPHICAL SKETCH David Cheney was born and raised in Orlando, Florida. After receiving his BSEE from the University of Florida he began his professional career as a logic designer designing semi custom ECL gate arrays for the CPU on mini supercomputers in San Diego, CA. Returning to UF for further education he received a Master of Engineering specializing in computer graphics. Continuing to live and work in Gainesville as member o f a family business with his mother, father, and brother he began his pursui t of a PhD as time and finances permitted. In the family business he participated in technical sales and consulting to the electric power industry, computer systems and applicat ion design