<%BANNER%>

An Instrumentation-Grade Differential Capacitive Mems Shear Stress Sensor System for Wind Tunnel Applications

Permanent Link: http://ufdc.ufl.edu/UFE0044511/00001

Material Information

Title: An Instrumentation-Grade Differential Capacitive Mems Shear Stress Sensor System for Wind Tunnel Applications
Physical Description: 1 online resource (302 p.)
Language: english
Creator: Meloy, Jessica Caitlin
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2012

Subjects

Subjects / Keywords: mems
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation describes the development of a differential capacitive MEMS shear stress sensor, the associated packaging, and interface electronics required for operation as an instrumentation-grade sensing system.  The sensor is a floating element possessing a differential comb drive designed to meet the spatial and temporal requirements for use as a measurement tool for turbulent boundary layers.  The capacitive sensing interface circuitry is an analog synchronous modulation/demodulation system that enablesthe system to make time resolved measurements of both mean and dynamic flow characteristics.  The packaging of thesensor creates a hydraulically smooth surface with a small footprint to enable array design and non-intrusive installation.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Jessica Caitlin Meloy.
Thesis: Thesis (Ph.D.)--University of Florida, 2012.
Local: Adviser: Sheplak, Mark.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2014-12-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2012
System ID: UFE0044511:00001

Permanent Link: http://ufdc.ufl.edu/UFE0044511/00001

Material Information

Title: An Instrumentation-Grade Differential Capacitive Mems Shear Stress Sensor System for Wind Tunnel Applications
Physical Description: 1 online resource (302 p.)
Language: english
Creator: Meloy, Jessica Caitlin
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2012

Subjects

Subjects / Keywords: mems
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation describes the development of a differential capacitive MEMS shear stress sensor, the associated packaging, and interface electronics required for operation as an instrumentation-grade sensing system.  The sensor is a floating element possessing a differential comb drive designed to meet the spatial and temporal requirements for use as a measurement tool for turbulent boundary layers.  The capacitive sensing interface circuitry is an analog synchronous modulation/demodulation system that enablesthe system to make time resolved measurements of both mean and dynamic flow characteristics.  The packaging of thesensor creates a hydraulically smooth surface with a small footprint to enable array design and non-intrusive installation.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Jessica Caitlin Meloy.
Thesis: Thesis (Ph.D.)--University of Florida, 2012.
Local: Adviser: Sheplak, Mark.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2014-12-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2012
System ID: UFE0044511:00001


This item has the following downloads:


Full Text

PAGE 1

1 AN INSTRUMENTATION GRADE DIFFERENTIAL CAPACITIVE MEMS SHEAR STRESS SENSOR SYSTEM FOR WIND TUNNEL APPLICATIONS By JESSICA CAITLIN MELOY A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIA L FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2012

PAGE 2

2 2012 Jessica Caitlin Meloy

PAGE 3

3 To my mother

PAGE 4

4 ACKNOWLEDGMENTS After so many years, there are many people to thank. If I were to list all of the thin gs that I am thankful for that have become part of my life due to my time at the Interdisciplinary Microsystems Group (IMG) this section would rival my third chapter. I will do my best to narrow this list down. M ark Sheplak. The encouragement, freedom, and humility he offers as an advisor is unique. His fierce dedication to his students inspired me to be the best student, leader, and researcher possible. I will miss his technical guidance as well as the energy he carries with him. My committee members, varied in expertise, have guided me in equally varied and enthusiasm are contagious. I am lucky to have been able to have so much of his time an attention. I appreciate Lou Cattafe and high expectations. I hold myself to a higher standard due to his input. to thank Henry Zmuda for his discussions and always encouraging words. recipient of a NASA Graduate Student Researchers Program fellowship I have been given the opportunity to collaborate with some amazing people. At NASA Langley Research Center (LaRC) I was able to work with Cathy McGinley, Luther Jenkins, Latunia Melton, a My colleagues at IMG have shap ed me as a researcher and as a person. When I first arrived at IMG Vijay Chandrasekharan immediately became a mentor. Even after leaving for industry his focus and passion continued to influence me Jeremy Sells

PAGE 5

5 served as a creative and ca lm counterbalan ce to Vijay and me His kindness and optimism continues to be something I strive to implement in my own life. The three of us together brought this dissertation further than I think any of us thought possible. Early on ined with his unique brand of humor, intelligence, and warmth i nspired me to stay for a Ph D received my Masters. There have been two critical points of severe self doubt and exhaustion for me during this process; the proposal and the dissertati on. During my proposal Ben Griffin and Matt Williams were my guardrails They both possess an endless supply of both patience and knowledge. I am extremely lucky to have had the opportunity to work with them and to call them friends. During the last fe w months several people have served as endless sources of encouragement and assistance. Anup Parikh is an amazing student and has an enviable ability to solve extremely open ended problems and built a fantastic calibration system. Dylan Alexander David Mills, and Daniel Blood are the three that have carried me across the finish line both through their technical contributions as well as their camaraderie Outside of MEMS, I owe thanks to Miguel Palaviccinni, John Griffin, and Brandon Bertolucci for their assistance in all things ever met. I am truly lucky to have worked with him. Aside from his help with fluid dynamics Brandon Bertolucci has been an amazing sou nding board during the dissertation process. I am fortunate to have him as a colleague going through the last few months and as a friend moving into industry. Finally, Barnard. He is the future of this dissertation and his enthusiasm and fearless nature renewed my sense of wonder in what I do just as fatigue was setting in

PAGE 6

6 Paul. gracious in dealing with the ups and downs of this process. If I ende d up with half of the resilience and heart that my mother has then fine.

PAGE 7

7 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ .. 4 LIST OF TABLES ................................ ................................ ................................ .......... 12 LIST OF FIGURES ................................ ................................ ................................ ........ 13 ABSTRACT ................................ ................................ ................................ ................... 24 CHAPTER 1 INTRO DUCTION ................................ ................................ ................................ .... 26 1.1 Research Objectives ................................ ................................ ..................... 26 1.1.1 Research Contributions ................................ ................................ ....... 27 1.1.2 Dissertation Organization ................................ ................................ .... 27 1.2 Boundary Layers and Wall Shear Stress ................................ ....................... 28 1.2.1 Laminar Boundary Layers ................................ ................................ ... 30 1.2.2 Turbulent Boundary Layers ................................ ................................ 31 1.3 Shear Stress Measurement Requirements ................................ ................... 34 1.3.1 Physical Sensor Structure ................................ ................................ ... 34 1.3.2 Transducer Properties ................................ ................................ ......... 36 1.4 Existing Shear Stress Measurement Techniq ues ................................ .......... 36 1.4.1 Indirect Shear Stress Sensors ................................ ............................ 37 1.4.2 Direct Shear Stress Sensors ................................ ............................... 39 1.5 Summary of Existing Floating Element Capacitive Shear Stress Sensors .... 42 1.6 Summary ................................ ................................ ................................ ....... 46 2 SENSOR MODE LING ................................ ................................ ............................. 48 2.1 Quasi Static Mechanical Model ................................ ................................ ..... 48 2.2 Electrostatic Model ................................ ................................ ........................ 51 2.2 Dynamic Modeling ................................ ................................ ......................... 59 2.2.1 Lumped Element Model for a Shear Input ................................ ........... 61 2.2.2 Lumped Element Model for a Pressure Inpu t ................................ ...... 65 2.3 Summary ................................ ................................ ................................ ....... 68 3 INSTRUMENTATION DESIGN FOR CAPACITIVE TRANSDUCERS .................... 69 3.1 Impact of Interface Circuitry on Transducer Performance ............................. 69 3.2 Amplifiers ................................ ................................ ................................ ...... 70 3.3 Basic Noise Models and Non Ideal ities ................................ ......................... 73 3.3.1 General Noise Characterization ................................ .......................... 73 3.3.2 Noise in Passive Components ................................ ............................ 75 3.3.3 Amplifier Noise ................................ ................................ .................... 78

PAGE 8

8 3.3.4 Other Non Idealities ................................ ................................ ............ 79 3.4 Interface Circuits ................................ ................................ ........................... 80 3.4.1 Unity Gain Voltage Buffer ................................ ................................ .... 80 3.4.2 Charge Amplifier ................................ ................................ ................. 84 3.4.3 Comparison of Voltage and Charge Amplifiers ................................ ... 87 3.4.3.1 Comparison with smallest device capacitance ............................ 88 3.4.3.2 Comparison with intermediate device ca pacitance ..................... 91 3.4.3.3 Comparison with largest device capacitance .............................. 97 3.4.3.4 Conclusions and practical considerations ................................ 102 3.5 Open loop Interface Circuitry Topologies ................................ .................... 102 3.5.1 Continuous Time Implementation ................................ ..................... 103 3.5.2 Discrete Time Implementation ................................ .......................... 104 3.6 Closed loop Interface Circuitry Topologies ................................ .................. 10 5 3.6.1 Continuous T ime Implementation ................................ ..................... 105 3.6.2 Discrete Time Implementation ................................ .......................... 105 3.7 Synchronous Modulation/Demodulation ................................ ...................... 106 3.7.1 Mixer Based Implementation ................................ ............................. 106 3.7.2 Envelope Detector Implementation ................................ ................... 107 3.8 Ge neralized Interface Circuit ................................ ................................ ....... 112 3.8.1 Modulation ................................ ................................ ........................ 114 3.8.2 Demodulation ................................ ................................ .................... 117 3.8.2.1 Signal conditioning before rectification ................................ ..... 118 3.8.2.2 Rectification ................................ ................................ .............. 119 3.8.2.3 Demodulation control ................................ ................................ 122 3.8.2.4 Signal conditioning after rectification ................................ ........ 123 3.8 Generalized Noise Model ................................ ................................ ............ 123 3.9 First Generation Synch MOD/DMOD ................................ .......................... 124 3.9.1 Modulation ................................ ................................ ........................ 124 3.9.2 Demodulation ................................ ................................ .................... 129 3.9.2.1 Signal conditioning before rectification ................................ ..... 129 3.9.2.2 Rectification ................................ ................................ .............. 133 3.9.2.3 R ectification control ................................ ................................ .. 136 3.9.2.4 Signal conditioning after rectification ................................ ........ 137 3.9.3 Summary of the First Generation Synch MOD/DM OD ...................... 138 3.10 Second Generation Synch MOD/DMOD ................................ ..................... 139 3.10.1 Modulation ................................ ................................ ........................ 140 3.10.1.1 Oscillator design ................................ ................................ ...... 140 3.10.1.2 Bias generation ................................ ................................ ........ 144 3.10.2 Demodulation ................................ ................................ ................... 145 3.10.2.1 Signal conditioning before rectification ................................ ..... 146 3.10.2.2 Rectification ................................ ................................ .............. 147 3.10.2.3 Demodu lation control ................................ ................................ 148 3.10.2.4 Signal conditioning after rectification ................................ ........ 148 3.10.3 Integrated Power Management ................................ ........................ 149 3.10.4 Summary of the Second Generation Synch MOD/DMOD ................ 150 3.11 Summary ................................ ................................ ................................ ..... 151

PAGE 9

9 4 OPTIMIZATION ................................ ................................ ................................ .... 153 4.1 System Level Optimization Objectives ................................ ........................ 153 4.2 Optimization Constraints ................................ ................................ ............. 156 4.2.1 Bandwidth ................................ ................................ ......................... 156 4.2.2 Pressure Rejection ................................ ................................ ............ 157 4.2.3 Mechanical Linearity ................................ ................................ ......... 159 4.2.4 Pull In Voltage ................................ ................................ ................... 159 4.2.5 Summary of Constraints and Design Variables ................................ 160 4 .2.6 Design Targets ................................ ................................ .................. 162 4.3 Optimization Results ................................ ................................ ................... 163 4.3.1 Optimization Bounds and Impact on Design Selection ...................... 163 4.3.2 Optimization Trends and Designs Selected for Fabrication .............. 165 4.4 Summary ................................ ................................ ................................ ..... 166 5 SENSOR FABRICATION AND PACKAGING ................................ ....................... 168 5.1 Fabrication Process Flow ................................ ................................ ............ 168 5.2 Fabrication Results ................................ ................................ ..................... 169 5.2.1 Through Silicon Via Validation ................................ .......................... 170 5.2.2 Floating Element Fabrication ................................ ............................ 171 5.2.3 Floating Element Release ................................ ................................ 173 5.3 Silicon on Pyrex Devices ................................ ................................ ............ 175 5.4 Sensor Packaging ................................ ................................ ....................... 176 5.4.1 First Generation Packaging Concept ................................ ................ 177 5.4.2 Second Generation Packaging Concept ................................ ........... 181 5.5 Summary ................................ ................................ ................................ ..... 182 6 EXPERIMENTAL CHARACTERIZATION ................................ ............................. 183 6.1 Experimental Setup ................................ ................................ ..................... 183 6.1.1 Electrical Characterization ................................ ................................ 184 6.1.2 Fluidic Characterization ................................ ................................ ..... 185 6.1.2.1 Mean flow characterization ................................ ........................ 185 6.1.2.2 Dynamic flow characterization ................................ ................... 187 6.1.3 Environmental Characterization ................................ ........................ 190 6.1.4 Wind Tunnel Facilities ................................ ................................ ....... 191 6.1.4.1 Facilities at the University of Florida ................................ .......... 191 6.1.4.2 Experimental characterization at NASA LaRC ........................... 193 6.1.4.2 Experimental characterization at GALCIT ................................ .. 194 6.1.5 Experimental Uncertainty ................................ ................................ .. 195 6.1.5.1 Random error in mean measurements ................................ ...... 195 6.1.5.2 Random error in spectral estimation ................................ .......... 196 6.1.5.3 Bias Error in the Laminar Flow Cell Experiments ....................... 197 6.1.5.4 Bias Error in the Plane Wave Tube Experiments ....................... 198 6.1. 5.5 Error Analysis of PIV Based Shear Stress Estimation ............... 199

PAGE 10

10 6.1.5.6 Error Analysis of Hotwire Profile Based Shear Stress Estimation ................................ ................................ .................. 199 6.1.5.7 Monte Carlo Analysis of Measured Sensitivities ........................ 200 6.2 Experimental Results ................................ ................................ .................. 200 6.2.1 First Generation Synch MOD /DMOD ................................ ................ 200 6.2.1.1 Electrical properties ................................ ................................ ... 200 6.2.1.2 Mean flow characterization ................................ ........................ 201 6.2.1.3 Dynamic flow characterization ................................ ................... 204 6.2.1.4 UF wind tunnel comparisons ................................ ...................... 208 6.2.1.5 LaRC wind tunnel com parisons ................................ ................. 210 6.2.1.6 GALCIT wind tunnel comparisons ................................ ............. 214 6.2.2 TSV Sensor Characterization ................................ ............................ 215 6.2.3 Second Generation Synch MOD/DMOD Characterization ................ 217 6.2.3.1 Dynamic flow characterization ................................ ................... 217 6.2.3.2 Environmental characterization ................................ .................. 222 6.3 Summary ................................ ................................ ................................ ..... 227 7 CONCLUSIONS AND FUTURE WORK ................................ ............................... 230 7.1 Conclusions ................................ ................................ ................................ 230 7.2 Recommendations for Future Work ................................ ............................ 232 7.2.1 Sensor Design ................................ ................................ .................. 232 7.2.2 Sensor Fabrication ................................ ................................ ........... 232 7.2.3 Third Generation Synch MOD/DMOD and Packaging ...................... 233 APPENDIX A LUMPED ELEMENT MODEL FOR SHEAR STRESS INPUT .............................. 235 A.1 Lumped Elements for Shear Stress ................................ ............................ 235 A.1.1 Lumped Mecha nical Compliance ................................ ..................... 235 A.1.2 Lumped Mechanical Mass ................................ ................................ 238 A.2 Two Port Model ................................ ................................ ........................... 240 B LUMPED ELEMENT MODEL FOR PRESSURE INPUT ................................ ...... 244 B.1 Lumped Element Parameters ................................ ................................ ...... 244 B.1.1 Lumped Mechanical Compliance ................................ ..................... 245 B.1.2 Lumped Mechanical Mass ................................ ................................ 247 B.1.3 Lumped Acoustic Compliance ................................ .......................... 247 B.1.4 Lumped Acoustic Dissipation ................................ ........................... 248 B.2 Two Port Model ................................ ................................ ........................... 248 C DERIVATION OF PARASITIC CONTRIBUTIONS FOR UNITY GAIN AM PLIFIER ................................ ................................ ................................ ........... 251 D DERIVATION OF NOISE EQUATION FOR UNITY GAIN AMPLIFIER ................ 254

PAGE 11

1 1 E PARTS LIST AND FULL SCHEMATIC FOR FIRST GENERATION SYN CH MOD/DMOD ................................ ................................ ................................ ......... 257 F PARTS LIST AND FULL SCHEMATIC FOR SECOND GENERATION SYNCH MOD/DMOD ................................ ................................ ................................ ......... 263 G PROCESS TRAVELER FOR FABRICATION OF T SV DEVICES ........................ 267 H Boundary Layer Profiles and Near Wall Data from NASA LaRC .......................... 278 H.1 Traversing Hotwire Profiles ................................ ................................ ......... 278 H.2 Monte Carlo Results for the Traversing Hotwire Study ............................... 282 H.3 Near Wall Hotwire Spectra ................................ ................................ .......... 285 H.4 Near Wall Hotwire Spectra with an Upstream Cylinder ............................... 289 LIST OF REFERENCES ................................ ................................ ............................. 293 BIOGRAPHICAL SKETCH ................................ ................................ .......................... 302

PAGE 12

12 LIST OF TABLES Table page 1 1. Parameters of Blasius' exact solution for a laminar boundary layer (adapted from [5] ). ................................ ................................ ................................ ............ 30 1 2 Existing MEMS based floating element methods ................................ ................ 47 3 1 Op Amp parameters for parametric study of interface amplifier topologies. ....... 87 4 1 Design variables used in optimization. ................................ ............................. 162 4 2 The various floating element sizes selected for optimization and their associated friction velocitie s and bandwidths from the scaling analysis presented in Section 1 3. ................................ ................................ .................. 162 4 3 The optimized geometries chosen for fabrication. ................................ ............ 167 6 1 The sampling parameters used with the flow cell. ................................ ............ 201 6 2 The sampling parameters used with the PULSE system. ................................ 204 6 3 The s ampling parameters used for the UF wind tunnel entry ........................... 209 6 4 The sampling parameters used for the NASA LaRC study. .............................. 210 6 5 The s ampling parameters used for the acquisition of the frequency response function ................................ ................................ ................................ ............. 217 6 6 The sampling parameters used with the environmental chamber ..................... 223 6 7 Results of the environmental calibration. ................................ .......................... 223 7 1 Comparison of this work with selected prior MEMS floating element based shear stress measurement methods ................................ ................................ 231 E 1 Parts list for the first generation Synch MOD/DMOD circuitry. ......................... 257 F 1 Parts list for the second generation Synch MOD/DMOD circuitr y. .................... 263 H 1 Results of hot wire profiles at NASA LaRC. ................................ ...................... 278

PAGE 13

13 LIST OF FIGURES Figure page 1 1 A schematic of the velocity profile for a flow over a solid surface. ...................... 28 1 2 An example of the velocity profile of a turbulent boundary layer normalized by freestream velocity, where acquired using a traversing hotwire probe at NASA LaRC ................................ ................................ ........................ 32 1 3 The velocity profile in Figure 1 law to determine the fric tion velocity for non dimensionalization. ....................... 33 1 4 A schematic view of a single micropillar where the pillar displacement is indicated by a hashed outline. Image adapted from B. Nottebrock, asuring the Two Dimensional, Two Directional Temporal Wall Shear Stress Distribution with the Micro Pillar Shear 3 Figure 1(c)) 48th AIAA Aerospace Sciences Meeting no. January, 2010 ...... 39 1 5 A generalized floating element sensor with the displacement under an input shear stress shown in dashed outlines. ................................ .............................. 40 1 6 A cross section of the photodiode floating element sensor fabricated by Padmanabhan, et al. Figure adapted from A. Padmanabhan, H. Goldberg, Bonded Floating Element Shear 308, Figure 2) Journal of Microelectromechanical Systems vol. 5, no. 4, pp. 307 315, 1996. ................................ ................................ ................................ ... 42 1 7 A cross section of the capacitive shear stress sensor with integrated electronics fabricated adapted from M A. Schmidt, R. T. Howe, S.D.Senturia, Element Shear IEEE Transactions on Electron Devices vol. 35, no. 6, pp. 750 757, 1988. ................................ ......... 43 1 8 A schematic of a capacitive comb drive based shear stress sensor implementing force feedback, adapted from T. Pan, D. Hyman, M. S 72, 1999. ................................ ................................ ................................ .................. 44 1 9 A schematic of a proof mass based floating element shear stress sensor implementing force feedback, adapted from J. Zhe, V. Modi, and K. R. Stress Sensor with Capacitative Journal of Microelectromechanical Systems vol. 14, no. 1, pp. 167 175, 2005. ................................ ................................ ...... 45

PAGE 14

14 1 10 A schematic of the capacitive shear stress sensor designed by Chandrasekharan, et al. with an inset view of the asymmetric capacitor gaps. Figure adapted from V. C handrasekharan, J. Sells, J. Meloy, D. P. Arnold, Shear Journal Of Microelectromechanical Systems vol. 20, no. 3, pp. 622 635, 2011. ................................ ...................... 46 2 1 A schematic of sensor geometry, not to scale, indicating the design variables of the floating element width, W e and length, L e the hole diameters, d h the finger width, W f Length, L f and overlap, L o and the gaps between the fingers g 01 and g 02 ................................ ................................ ............................. 49 2 2 A schematic simplifying the floating element sensor to a clamped clamped beam under an input shear force. ................................ ................................ ....... 50 2 3 Sensor structure with the capacitances associated with the comb fingers, the tethers, and the floating element, shown with dashes, dots, and dashes and dots, respectively. ................................ ................................ ........... 53 2 4 The physical structure of capacitor showing the asymmetric gaps between comb fingers. ................................ ................................ ....................... 54 2 5 The electrical equivalent circuit for ................................ ................................ 55 2 6 Physical structures of the floating element capacitance, and the tether capacitance, ................................ ................................ ................................ .. 55 2 7 The half bridge circuit representation of all variable capacitances on the sensor structure. ................................ ................................ ................................ 56 2 8 The simplified half bridge representation of the complete floa ting element structure. ................................ ................................ ................................ ............ 57 2 9 Circuit representation of the LEM for a shear force input where the mechanical domain is on the left, the electrical domain is on the right, and the electromecha nical coupling is represented by lossless transformers. ................ 64 2 10 Circuit representation of the LEM for a pressure input where the mechanical domain is on the left, the electrical domain is on t he right, and the electromechanical coupling is shown by lossless transformers. ......................... 67 3 1 The model of an operational amplifier showing input referred noise current and voltage noise sources and finite input impedances. ................................ .... 70 3 2 Frequency response of the open loop gain of an operational amplifier. ............. 72

PAGE 15

15 3 3 A noisy resistor an d the equivalent Thevenin and Norton equivalents showing the noise as an independent voltage or current source. ................................ ..... 76 3 4 The circuit model for analysis of the effect of a parallel capacitance on the thermal noise of a resistor. ................................ ................................ ................. 77 3 5 The spectral density of the thermal noise of a resistor shaped by a parallel capacitance plotted against normalized frequency to demonstrate the spectr al shaping of the RC product. ................................ ................................ ... 78 3 6 The operational amplifier noise model, showing the overall noise of the amplifier as an input referred voltage and current source. ................................ .. 79 3 7 A visualization of A) linear amplifier operation and B) clipped amplifier operation. ................................ ................................ ................................ ........... 80 3 8 The circuit schematic of a unity gain operational amp lifier. ................................ 81 3 9 The circuit model of the sensor and a unity gain amplifier including parasitics associated with the amplifier and sensor packaging. ................................ .......... 82 3 10 The small signal model of the sensor and a unity gain amplifier including noise sources. ................................ ................................ ................................ .... 83 3 11 The circuit schematic of a charge amplifier interfaced with the sens or, including parasitic capacitances. ................................ ................................ ........ 85 3 12 The schematic of the sensor interfaced with a charge amplifier including small signal noise sources. ................................ ................................ ................. 86 3 13 The noise contributions and total noise for interfacing with a 0.1 pF capacitor with a signal of interest at 1 MHz using an OPA129 configured as a A) a voltage amplifier and B) a charge amplifier. ................................ ....................... 89 3 14 The noise spectra of the OPA129 configured as a voltage amplifier and current amplifier for multiple bias resistances to interface with a transducer with a nominal capacitance of 0.1pF. ................................ ................................ 90 3 15 The comparison of the signal to noise ratio of multiple configurations. ............... 91 3 16 The noise spectra of an AD8022 for a nominal capacitance of 1pF at 1 M Hz A) configured as a charge amplifier and B) configured as a voltage amplifier. ... 93 3 17 The noise spectra of the AD8022 configured as a voltage amplifier and current amplifier for multiple bi as resistances to interface with a transducer with a nominal capacitance of 1pF. ................................ ................................ .... 94

PAGE 16

16 3 18 The noise spectra of the OPA129 configured as a voltage amplifier and current amplifier for multiple bi as resistances to interface with a transducer with a nominal capacitance of 1pF. ................................ ................................ .... 94 3 19 The noise spectra of an OPA129 for a nominal capacitance of 1pF at 1 MHz configured as A) a charge ampl ifier and B) a voltage amplifier. ......................... 95 3 20 The signal to noise ratio for all configurations when interfanced with a device of 1 pF nominal capacitance using A) an AD8022 and B) an OPA 129. ............. 96 3 21 The noise spectra of an AD8022 interfaced with a nominal capacitance of 10pF at 1 MHz configured as A) charge amplifier and B) a voltage amplifier. .... 98 3 22 The noise spectra of an OPA129 interfaced with a nominal capacitance of 10pF at 1 MHz configured as A) charge amplifier and B) a voltage amplifier. .... 99 3 23 The noise spectra of the AD8022 configured as a voltage amplifier and current amplifier for multiple bias resistances to interface with a transducer with a nominal capacitance of 10pF. ................................ ................................ 100 3 24 Th e noise spectra of the OPA129 configured as a voltage amplifier and current amplifier for multiple bias resistances to interface with a transducer with a nominal capacitance of 10pF. ................................ ................................ 100 3 25 The signal to noise ratio for multiple implementations of interface circuitry constructed to interface with a transducer with a nominal capacitance of 10pF with A) the AD8022 and B) the OPA129. ................................ ................. 101 3 26 An amplitude modulated signal with 100% modulation depth and the corresponding output of a passive rectification scheme. ................................ .. 108 3 27 An amplitude modulated signal with 150% modulation depth and the corresponding output of a passive rectification scheme. ................................ .. 109 3 28 An amplitude modulated signal with modulation depth of 150% and the corresponding output of active rectification with no phase error. ...................... 110 3 29 An amplitude modulated signal with modulation depth of 150% and the corresponding output of active rectification with a 90 degree phase error. ....... 112 3 30 A high level block diagram of the active rectifier based synch MOD/DMOD system for use with the capacitive shear stress sensor. ................................ ... 1 13 3 31 A generalized schematic of the bias generation for modulation indicating the original sinusoid at the input and resulting in two out of phase sinusoids at each sensor bias node. ................................ ................................ .................... 114

PAGE 17

17 3 32 The ci rcuit representation of the sensor for an analysis of the errors associated with the modulation block. ................................ .............................. 115 3 33 A block diagram of the demodulation portion of the Synch MOD/DMOD system, with s ub sections indicated in dashed boxes. ................................ ..... 117 3 34 The block diagram of the signal conditioning before rectification block demonstrating the construction of a band pass filter through the series combination of a low pass filter and a high pass filter. ................................ ..... 119 3 35 The block diagram of the rectification block including a phase inversion stage and a DPST switch. ................................ ................................ .......................... 120 3 36 An illustration of switch timing showing the various time scales used as metrics for switch selection. ................................ ................................ .............. 121 3 37 A block diagram representation of t he demodulation control circuitry. .............. 122 3 38 A schematic of the modulation portion of the Synch MOD/DMOD system showing the phase adjustability and gain control to eliminate offset in the senso r output. ................................ ................................ ................................ ... 125 3 39 Equivalent noise circuit of an inverting amplifier including the input referred noise of the amplifier as well as thermal noise sources associated with resistances. ................................ ................................ ................................ ...... 126 3 40 Equivalent noise circuit of a phase adjust block where the amplifier noise is represented by differential input current and voltage sources. ......................... 127 3 41 Modulation circuit with labeled components for use in noise analysis. ............. 129 3 42 Detailed drawing of the signal conditioning path before rectification in the demodulation block. ................................ ................................ .......................... 130 3 43 The demodulation before rectification block with components labeled for noise analysis. ................................ ................................ ................................ .. 131 3 44 A detailed draw ing of the rectification portion of the demodulation block. ........ 133 3 45 The rectification portion of the demodulation circuit with the components labeled for noise analysis. ................................ ................................ ................ 134 3 46 The circuit schematic of a transmission gate showing the parallel nMOS and pMOS transistors. ................................ ................................ ............................. 135 3 47 The demodulation control block. ................................ ................................ ....... 137 3 48 A schematic of the final low pass filter in the Synch MOD/DMOD system. ....... 138

PAGE 18

18 3 49 The measured noise floor of the first generat ion Synch MOD/DMOD. ............. 139 3 50 A circuit schematic of the Colpitts oscillator. ................................ ..................... 140 3 51 Simplified model of the Coliptts oscillato r shown as A) a small signal model and B) a parallel RLC circuit. ................................ ................................ ............ 142 3 52 A schematic of the total oscillator circuit including the amplification of the bias signal for increased bias voltage s. ................................ ................................ .... 144 3 53 A schematic of the modulation circuitry for the second generation of the Synch MOD/DMOD circuit. ................................ ................................ ............... 145 3 54 A schemati c of the signal conditioning before rectification block in the second generation Synch MOD/DMOD. ................................ ........................... 146 3 55 A schematic of the rectification block of the second generation Synch MOD/DMOD system. ................................ ................................ ........................ 147 3 56 A schematic of the rectification control block. ................................ ................... 148 3 57 The measured noise floor of the second generation Synch MOD/D MOD system compared to the noise floor of the first generation. .............................. 150 3 58 A photograph of A) the Synch MOD/DMOD system with a pen as a reference of the final size and B) the internal circuitry. ................................ ..................... 151 4 1 A visualization of the operating space for the sensor. ................................ ...... 154 4 2 An exaggerated view of the frequency response functions of the shear and pressure LEMs in terms of displacement due to a unit input force. .................. 158 4 3 The physical sensor structure with optimization labels identified. ..................... 161 4 4 The results of the study of bandwidth on the minimum detectable signal for the optimized floating element sizes. ................................ ................................ 164 4 5 The sensitivity of the optimized design on the design variables. ...................... 165 5 1 Step by step fabrication process. ................................ ................................ ...... 169 5 2 A cross section of a properly fabricated TSV. ................................ ................... 170 5 3 A cross section of a TSV that is not connected properly. ................................ 171 5 4 A demonstration of the RIE lag seen on a representative tether structure during the fabrication of the capacitive shear stress sensor where the large gap is 15 and the small gap is 3.5 ................................ ..................... 172

PAGE 19

19 5 5 A cross section of an unreleased tether showing the footing in the base of the tether structure with symmetric 3.5 gaps. ................................ .................. 173 5 6 A cleaved view of the released f loating element, showing partial cross sections of the floating element perforations. ................................ ................... 174 5 7 Residual material between the comb fingers following the release etch. .......... 175 5 8 The silicon on Pyrex process used to fabricate the capacitive shear stress sensor, adapted from [35]. ................................ ................................ ................ 176 5 9 A non scale schematic showing the ass embly of the PCB end cap for flush mounting silicon on Pyrex devices. ................................ ................................ .. 178 5 10 Sensor tube package design (not to scale). ................................ ..................... 179 5 11 First generation package (left) and the package in Chandrasekharan et al. (right) [79] shown with a US quarter for reference. ................................ ........... 180 5 12 Second generation end cap components (foreground) and an assembled end cap (background). ................................ ................................ ............................. 181 6 1 A schematic of the sensor structure with the probe points for the impedance characterization indicated on A) a TSV device and B) a silicon on Pyrex d evice. ................................ ................................ ................................ .............. 184 6 2 Laminar flow cell schematic (not to scale), demonstrating the control of airflow through the channel. ................................ ................................ ............. 186 6 3 Dyn amic shear stress sensor calibration experimental setup using an acoustic plane wave tube with a sound hard boundary to set up a standing wave pattern in the tube. ................................ ................................ .................. 188 6 4 A schematic of the m ovable back plate PWT configuration for acquisition of frequency response functions, courtesy of Anup Parikh and Daniel Blood. ...... 189 6 5 Experimental setup for a combined shear and pressure resp onse testing using an acoustic plane wave tube with an anechoic termination. .................... 190 6 6 Dimensioned schematic of the flat plate model for use in UF facilities [79]. Figure courtesy of John Griff in. ................................ ................................ ......... 192 6 7 .................... 193 6 8 The sensitivity of the first generation S ynch MOD/DMOD with a silicon on Pyrex sensor acquired using the laminar flow cell. ................................ ........... 202

PAGE 20

20 6 9 The results of the Monte Carlo simulation of the sensor sensitivity determined by the flow cell exper iments. ................................ ................................ ............. 202 6 10 The normalized sensitivity of the shear stress measurement system compared with the incident angle of mean flow across the sensor. .................. 203 6 11 Dynamic calibration of the first generation Synch MOD/DMOD system with a silicon on Pyrex sensor as tested in the acoustic plane wave tube with a sound hard boundary. ................................ ................................ ....................... 205 6 12 Combined static and dynamic calibration plots indicating nominally the same sensitivity. ................................ ................................ ................................ ......... 206 6 13 Normalized sensitivity of the first generation Synch MOD/DMOD sensor system as us ed for further characterization. ................................ ..................... 206 6 14 The combined shear and pressure frequency response function of the shear stress measurement system. ................................ ................................ ............ 207 6 15 Comparison of the estimated shear stress produced by the shear stress sensor system and velocity profile estimates measured using PIV [79]. .......... 209 6 16 Comparison of sensor output to the shear stress determined by a traversing hotwire study with a solid line indicating unity. ................................ ................. 211 6 17 The result of the Monte Carlo analysis for the determination of shear stress f or a freestream velocity of 43 m/s demonstrating the distribution of error in the shear stress estimate as well as the finite difference between two velocity profile based estimation methods. ................................ ................................ .... 211 6 18 The estimated autospectra of wall shear stress determined by the capacitive shear stress sensor system (blue) and a near wall hotwire (black). ................. 213 6 19 The estimated autospectra of wa ll shear stress determined by the capacitive shear stress sensor system (blue) and a near wall hotwire (black) for downstream shedding off of a cylinder. ................................ ............................ 214 6 20 The velocity profile measured at GALCIT shown in wall units. ......................... 215 6 21 The impedance of a floating element TSV device after the TSVs are removed by dicing. ................................ ................................ ........................... 216 6 22 The shear stress sensitivity acquired using the variable back plate. ................ 218 6 23 The measured frequency response function of the sensor system to an input shear stress using the variable back plate plane wave tube set up. ................. 219 6 24 The sensitivity of the sensor to dynamic pressure. ................................ ........... 220

PAGE 21

21 6 25 The measured frequency response function when the sensor is placed at a velocity minimum and pressure maximum. ................................ ....................... 221 6 26 Temperature calibration of Pyrex device. ................................ ......................... 224 6 27 Temperature calibration of TSV device. ................................ ........................... 225 6 28 Humidity calibration of Pyrex device. ................................ ................................ 226 6 29 Humidity calibration of TSV device with 95% confidence intervals shown. ....... 227 7 1 A proposed sensor structure to avoid the issues found during TSV device fabrication. ................................ ................................ ................................ ........ 233 A 1 Full lumped element model of the floating element response to an input shear stress ................................ ................................ ................................ ...... 235 A 2 Generalize circuit representation for a two port transducer model ................... 241 B 1 Circuit representation of the lumped element model for the out of plane response of an H bar structure. ................................ ................................ ........ 244 C 1 Contribution of positive bias to output ................................ ............................... 251 C 2 Contribution of negative bias to output ................................ ............................. 252 D 1 Total noise model for a unity gain amplifier with bias resistor ........................... 254 D 2 Noise circuit for amplifier voltage noise. ................................ ........................... 254 D 3 Noise circuit for ampl ifier current noise. ................................ ............................ 255 D 4 Noise circuit for resistor thermal noise. ................................ ............................. 256 E 1 Schematic for the first generation Synch MOD/DMOD circuitry. ...................... 26 2 F 1 Schematic for the second generation Synch MOD/DMOD circuitry. ................. 266 G 1 The process flow for fabricating the c apacitive shear stress sensors with TSVs (not to scale). ................................ ................................ .......................... 268 H 1 The hotwire profile and relevant fits for a freestream velocity of 16 m/s. .......... 279 H 2 The hotwire profile and relevant fits for a freestream velocity of 22 m/s. .......... 279 H 3 The hotwire profile and relevant fits for a freestream velocity of 28 m/s. .......... 280 H 4 The hotwire profile and relevant fits for a freestream velocity of 33 m/s. .......... 280

PAGE 22

22 H 5 The hotwire profile and relevant fits for a freestr eam velocity of 38 m/s. .......... 281 H 6 The hotwire profile and relevant fits for a freestream velocity of 43 m/s. .......... 281 H 7 The results o f the Monte Carlo analysis for a freestream velocity of 16m/s. ..... 282 H 8 The results of the Monte Carlo analysis for a freestream velocity of 22 m/s. .... 283 H 9 The results of the Monte Carlo analysis for a freestream velocity of 28 m/s. .... 283 H 10 The results of the Monte Carlo analysis for a freestream velocity of 33 m/s. .... 284 H 11 The results of the Monte Carlo analysis for a freestream velocity of 38 m/s. .... 284 H 12 The results of the Monte Carlo ana lysis for a freestream velocity of 43 m/s. .... 285 H 13 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 16m/s. ................................ ................................ ............ 286 H 14 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 22 m/s. ................................ ................................ ........... 286 H 15 The spectral estimates of the she ar stress sensor and near wall hotwire for a freestream velocity of 28 m/s. ................................ ................................ ........... 287 H 16 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 33 m/s ................................ ................................ ........... 287 H 17 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 38 m/s. ................................ ................................ ........... 288 H 18 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 43 m/s. ................................ ................................ ........... 288 H 19 The spectral estimates of the shear stress sensor and near wall hotwire f or a freestream velocity of 16m/s when the cylinder is installed. ............................. 289 H 20 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 22 m/s when the cylinder is installed. ............................ 290 H 21 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 28 m/s when the cylinder is installed. ............................ 290 H 22 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 33 m/s when the cylinder is installed. ............................ 291 H 23 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 38 m/s when the cylinder is installed. ............................ 291

PAGE 23

23 H 24 The spectral estimates of the she ar stress sensor and near wall hotwire for a freestream velocity of 43 m/s when the cylinder is installed. ............................ 292

PAGE 24

24 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Parti al Fulfillment of the Requirements for the Degree of Doctor of Philosophy AN INSTRUMENTATION GRADE DIFFERENTIAL CAPACITIVE MEMS SHEAR STRESS SENSOR SYSTEM FOR WIND TUNNEL APPLICATIONS By Jessica Caitlin Meloy December 2012 Committee Chair : Mark Sheplak Major : Electrical and Computer Engineering This dissertation describes the development of a differential capacitive microelectromechanical systems ( MEMS ) shear stress sensor, the associated packaging, and the interface electronics required for operation a s an instrumentation grade sensing system The sensor is a floating element possessing a differential comb drive designed to meet the spatial and temporal requirements for use as a measurement tool for turbulent boundary layers. The capacitive sensing in terface circuitry is an analog synchronous modulation/demodulation system that enables the system to make time resolved measurements of both mean and dynamic wall shear stress events The packaging of the sensor creates a hydraulically smooth surface for moderate Reynolds numbers with a small footprint to enable array design and non intrusive installation. The calibration of the sensor is extended to include a new method in estimating the frequency response function of shear stress sensors and a new test bed to quantify the impact of varying humidity and temperature in the ambient environment. The sensor system is demonstrated in three wind tunnel facilities against a variety of comparative measurement techniques and in many flow conditions. The final s ystem

PAGE 25

25 exhibits a sensitivity of 6.5 m V/Pa, a bandwidth of 4.7 kHz, and is the first MEMS based shear stress system to successfully demonstrate both mean and dynamic measurements in multiple wind tunnel facilities.

PAGE 26

26 CHAPTER 1 INTRODUCTION Quantification of skin friction drag is an area of research with immediate impact on consumer markets as well as emerging technologies. In consumer applications the quantification and study of skin friction drag can as sist in the design of more fuel efficient automobiles and airplanes. In a multi billion dollar industry [1] reduction in fuel consumption would have enormous economic impact. In scientific research, t he fi eld of flow control would benefit greatly from the ability to make a time resolved, directional measurement of wall shear stress in order to detect and perhaps predict separation. As a feedback mechan ism, the sensor would enhance the ability of a controll er to suppress and prevent separation [2] Beyond separation, the ability to make direct time resolved measurements of mean and dynamic wall shear stress will help elucidate complex flow fie lds, where traditional fluid measurement techniques used to estimate wall shear stress fail. The goal of this dissertation is to create an instrumentation grade sensor system for the quantification of shear forces at the fluid solid boundary. This include s design and fabrication of a shear stress sensor, design and implementation of interface circuitry packaging of the sensor and interface circuitry and characterization including calibration and proof of concept deployment into several wind tunnel s 1.1 Re search Objectives Given the need for time resolved measurements of wall shear stress, this dissertation outlines the development and characterization of a differential capacitive MEMS shear stress sensor system, including sensor packaging, and the developm ent of appropriate instrumentation. The aim of this work is a full sensor characterization,

PAGE 27

27 including characterization of environmental and cross axis sensitivities to provide a system capable of benchmark measurements in flow facilities at the University of Florida and NASA Langley Research Center. 1.1.1 Research Contributions The contributions from this dissertation are as follows P ackaging, development of interface electronics and characterization of sensor system smooth to within Sensor system optimization, including prediction and reduction of cross axis sensitivity Transition of a shear stress sensor system to a government wind tunnel facility 1.1.2 Dissertation Organization This dissertation is comprised of seven cha pters. First t he concept of a boundary layer is briefly discussed, along with a review of the traditional measurement techniques and an introduction to the MEMS capacitive shear stress sensor. The second chapter discusses the sensor modeling and the thi rd the electronics that are required in order to interface with the sensor. The fourth uses models and constraints developed in chapters two and three to perform a formal optimization of the mechanical sensor design. The fifth chapter discusses the fabri cation and packaging of the sensor system. The sixth discusses the test beds at the University of Florida and NASA Langley Research Center that serve to characterize the sensor, and presents results of the system in its entirety. The seventh chapter outl ines some conclusions and recommends some concepts to extend this work The remainder of this chapter introduce s the concept of wa ll shear stress, discuss es the physical phenomena that determine the length and time scales of interest

PAGE 28

28 for different flow con ditions that drive the design of the sensor and provides a general outline of the remainder of this dissertation. 1.2 Boundary Layers and Wall Shear Stress In order to measure shear stress the foundations of the physics that produce it must be understood. Flow at a contact interface is characterized by two conditions; normal velocity at the interface and tangential velocity at the interface. Given a fluid solid interface in a continuum flow the normal velocity component must be zero by definition [3] At the flu id/solid boundary viscosity forces the local fluid velocity to match seen in Figure 1 1 Figure 1 1 A schematic of the v elocity profile for a flow over a solid surface. For a Newtonian fluid the wall s hear stress is ex pressed as

PAGE 29

29 ( 1 1 ) where is the dynamic visc osity, is the streamwise velocity of the fluid, and is nor mal to the wall [4] The region between the wall and the freestream, where viscous forces dominate, is known as the boundary layer. The boundary layer is characterized by sev eral metrics. The simplest description is boundary layer height and is defined as the height from the boundary where the local fluid velocity reaches 99% of the free stream velocity. While this metric is important, particular ly when discuss ing measurement techniques, greater physical insight is gained by examining the displacement thickness, and the momentum thickness, The displacement thickness is a measure of how vis cous effects displace inviscid flow from the boundary and is defined for incompressible flow by the integral ( 1 2 ) Similarly, momentum thickness represents the momentum lost to interactions with the wall and is defined as ( 1 3 ) In the case of flow over a flat plate with zero pressure gradient these metrics can relate a mean velocity profile to the coefficient of friction and thus wall shea r stress [3] as ( 1 4 )

PAGE 30

30 There are two wall bounded shear flows used as a basis in this work; laminar boundary layers and turbulent boundary layers. Laminar boundary layers are characterized by smooth flow molecular transport, and zero frequency content while turbulent boundary layers are characterized by a highly unsteady, multi scale mixing via turbulent eddies [4] The magnitude spatial size, and freque ncy content of the shear stresses in these two flows will ultimately set the requirements for sensor design 1.2.1 Laminar Boundary Layers Laminar flow is characterized by smooth streamlines a nd is generally observed at low Reynolds numbers Reynolds nu mber is a dimensionless number representing the ratio of inertial forces to viscous forces and is given by ( 1 5 ) where is the density of the fluid, is the freestream velocity of the fluid, and x a characteristic dimension. Table 1 1. Parameters of Blasius' exact solut ion for a lamina r boundary layer (adapted from [5] ). Parameter Blasius Solution 0.664 1.721 5.0 0.664 1.328 In the case of laminar boundary layers this dimension is the distance from the leading edge of the wall. Ther e are several similarity solutions that reduce the system

PAGE 31

31 of partial differential equations used to describe a laminar boundary layer to an ordinary diff erential equation. For incompressible laminar flow with a zero pressure gradient over a flat plate, the Blasius solution describes the velocity profile of the boundary layer [5] The parameters for this solution are shown in Table 1 1. By definition there is no frequency content in a l aminar boundary layer. 1.2.2 Turbulent Boundary Layers At high Reynold s number flows, small disturbances in the surface or flow conditions result in the transition to turbulent flow [6] Turbulence is a dynamic process that is described in statistical terms. Although turbulent boundary layer flows do not possess a closed form analytical solution, empirical relations exist to estimate mean wall shear stress and the relative frequency content as functions of Reynolds number. In general the mean shear stress in a turbule nt flow is higher than in a laminar flow due to Reynolds stress es and turbulent mixing Figure s 1 2 and 1 3 below show an example of a fully developed two dimensional turbulent boundary layer acquired with a traversing hot wire Flow Control tunnel at the NASA LaRC facility where A turbulent boundary layer is traditionally decomposed into four major sections; the viscous sublayer, the buffer layer, the logarithmic region (inertial sublayer), and the wake shown in Figure 1 3 T hese regions are defined by non dimensionalizing the parameters into viscous wall units, ( 1 6 ) where is the friction velocity given by

PAGE 32

32 ( 1 7 ) and dimensionless velocity ( 1 8 ) Figure 1 2 An example of the velocity profile of a turbulent boundary layer normalized by freestream velocity where acquired using a traversing hotwire probe at NASA LaRC The regions of a turbulen t boundary layer are clearly seen in Figure 1 3 The black line indicates the region in where It spans from to approximately defining the viscous sublayer. The r ed lin e indicates the region where

PAGE 33

33 ( 1 9 ) where and via experiment The data follows this curve defining the log layer from to The region in between these two areas is the buffer region and the region beyond the log l ayer is the wake. S [7] provides a composite formula accounting for all regions except for the wake ( 1 10 ) Figure 1 3 The velocity profile in Figure 1 2 converted into wall units law to determine the friction velocity for non dimensionalization. Given t hese canonical flows the requirements to make a quantitative shear stress measurement and the current measurement techniques are discussed in Section 1. 3

PAGE 34

34 1.3 Shear Stress Measurement Requirements The basic considerations in shear stress sensor design are; t he measurement methods the physical sensor structure, and the transduction properties. In this section the constraints on physical sensor size and the influence of transduction mechanism are discussed. The measurement meth ods are discussed in Section 1. 4 along with a review of current measurement methods. 1.3 .1 Physical Sensor Structure The physical structure of the sensor must be able to provide accurate spatial resolution, be forgiving to alignment errors, and be hydraulically smooth. The spatial an d temporal requirements for the measurement of a turbulent boundary layer are best described by the empirical study from Hutchins et al. [8] In this study, the effects of probe size on the measurement of velocities in a turbulent boundary layer are parametrically studied. While this is not a direct analog to the measurem ent of wall shear stress, it is the best estimation of the size and frequency of the structures that in duce a wall shear stress. If a sensing element is too physically large, the smaller structures in the flow will be spatially averaged. Insight is provided by non dimensionalizing the length of the sensing element and the temp oral response of the sensor using viscous units ( 1 11 ) and ( 1 12 )

PAGE 35

35 quirements for measurement accuracy and is smaller than the characteristic eddy size for bandwidth of the turbulence then the turbulence statistics should be reasonable. According to Hutchins et al. reliable statistics are produced when the non dimensiona l length is less than or equal to 20, ( 1 13 ) and the non dimensional timescale is less than or equal to 3, ( 1 14 ) Given a known shear stre ss, and thus a known the maximum sensor length and timescale, and therefore frequency, are given by ( 1 15 ) ( 1 16 ) and ( 1 17 ) Along with sensor size restrictions for adequate ba ndwidth and resolution, sensor height into the flow and surface gaps must be limited so the sensor will not act as an additional source of turbulen ce. A sensor height of less than five viscous wall units ( ) is considered hydrauli cally smooth and be considered unobtrusive to the flow. Viscous dissipation within is dominant and thus any perturbation resultant from the sensor is suppressed [9]

PAGE 36

36 1.3 .2 Transducer Properties A t ransducer converts a signal from one energy domain to another, in this case it will transfer energy from the mechanical domain to the electrical domain by measuring a physical quantity in the flow field and converting it into an electrical signal [10] There are a variety of mechanisms to achieve this conversion. The output of an ideal sensor would only be sensitive to an input wall shear force. The transducer should be able to provide both mean and fluctuating information with a frequency range suitable for capturing the dynamics of the flow. In order to measure wall shear forces the transducer must be open to the flow environment. This lack of hermetic packaging means that any other force or change in the env ironment will act directly on the sensor in addition to the desired shear force Any pressure input or changes in ambient conditions, such as temperature, humidity, or gas composition should not be fed through to the output signal. N o transduction mechan ism is truly ideal and a sensor that is open to the environment can react to a multitude of inputs but through careful design the sensitivity to these inputs are reduced. Rejection of cross axis inputs is achieved through manipulation of the transducer me chanics or through signal conditioning. Understanding how cross axis sensitivities effect the measure ment of shear stress requires knowledge of existing measurement techniques. 1 4 Existing Shear Stress Measurement Techniques This second provides a brie f overview of existing shear stress measurement techniques. The primary focus of this work is to leverage existing technology developed at the University of Florida, discussed in Section 1.5, so the breadth of this review is limited. There are a large nu mber of existing methods used to either qualitat ively or quantitatively measure wall shear stress Despite the large number of tools available,

PAGE 37

37 the ability to perform a time resolved quantitative mean and dynamic shear stress measurement is still unavaila ble [11] Shear stress measurement techniques have historicall y been divided into two general categories, indirect measurement and direct measurement. Indirect measurement techniques measure a physical quantity other than shear stress and then relate the behavior of that physical quantity back to wall shear stress. Direct measurement measures the shear force at the wall. Within each of these categories there are methods that can measure mean shear stress alone and methods that can measure time resolved mean and dynamic shear stress. The indirect methods that rely on relationships between other quantities and shear stress are discussed in Section 1.4 .1. T he direct methods that do not rely on correlations or relationshi ps are discussed in Section 1.4 .2. Ultimately the direct microscale sensors have the greatest pr omise for use as a quantitative time resolved measurement of wall shear stress. 1 4 .1 Indirect Shear Stress Sensors Indirect measurement techniques rely on underlying correlations between a measured parameter and shear stress to estimate mean or dynamic shear stress values Comprehensive reviews have been made by Haritonidis [12] Winter [13] Naughton and Sheplak [11] Sheplak et al. [14] Chandrasekharan et al. [15] and Schetz [16] Methods that are not capable of dynamic measurement include those that are based on surface obstacles or velocity profiles. Surface obstacle measurements, such as Preston tubes, Stanton tubes, razor blades, or fences rela te a measured pressure to wall shear str ess by empirical correlations. Additionally, the probe for these methods must be contained within the viscous sublayer of the boundary layer. This limits either

PAGE 38

38 the flow conditions to include a thick boundary layer or the probes to be very small [12] V elocity profile based measurements, such as a velocity profile acquired usi ng a traversing Pitot probe [13] particle image v elocimetry (PIV), or low speed laser D oppler velocimetry (LDV) [17] are also limited to mean measurement but as the determination of wall shear stress is based on a n empirical [7] over the whole profile the probe size and proximity to the surface are not as critical. The lack of resolution in near wall data affects the uncertainty of the estimated value of mean shear stress, but an estimate is still available. In direct time resolved measurement methods include heat transfer based devices and high speed optical methods. Heat transfer based devi ces, like hot wire anemometer s [18] hot film sensor s [11] or more recently carbon nanotube based heat transfer devices [19] relate the exchange of heat a nd mass flux from the device to the flow to velocity through an in situ calibration. While these devices possess high sensitivity and small size, the tedious and constantly changing calibration prevent them from being a reliable quantitative measurement t echnique. High speed optical methods are limited by the near wall seeding and are not capable of measurement over geometries with separation as seeing cannot access those areas [17] Micropillars are short compliant structures t hat extrude into the viscous sublayer. As flow moves across the pillars they displace proportional to the input velocity profile The displacement of the pillar is imaged, like seed particles in PIV, or sensed using a n electromechanical transduction sche me. Additionally, the pillars must be compliant enough to make a measurement while still being small enough to remain in the viscous sublayer [20 22] Micropillars are categ orized generally as indirect as the state of the

PAGE 39

39 flow must be assumed in order to determine the relationship between wall shear stress and pillar displacement A pillar immersed in the viscous sublayer of a turbulent boundary layer is shown in Figure 1 4. For non linear velocity gradients the pillar displacement will be dependent on the pressure gradient so there is no universal calibration for a micropillar and the result given by a micropillar relies on an assumption of the state of the flow. Figure 1 4. A schematic view of a single micropillar where the pillar displacement is indicated by a hashed outline. Image adapted from B. Nottebrock, Dimensional Two Directional Temporal Wall Shear Stress Distribution with the Micro Pillar Shear (page 3 Figure 1(c)) 48th AIAA Aerospace Sciences Meeting no. January, 2010 In all cases as the final determination of wall shear stress is based on empirical relationships These empirical relationships rely on the flow having a fully developed two dimensional turbulent boundary layer. Characterization of three dimension al or separated flows is not possible with these methods 1 4 .2 Direct She ar Stress Sensors Direct measurement sensors measure shear force on the wall directly without relying on assumptio ns about the larger flow field. These direct methods will again be

PAGE 40

40 decomposed into methods capable of making time resolved measurements and t hose that are not. Direct mean measurement is achieved using liquid crystal or oil film techniques. In a liquid crystal application the surface is coated with a liquid crystal display that displaces under shear stress. When illuminated the liquid crystal display will appear to have a gradient related to the input shear stress. Oil film techniques are similar as an oil is applied to the surface and is displaced with an input shear stress [11] Both of these techniques require large optical access and require significant post processing in order to achieve quantitativ e results. The benefit of this technique is that it is a field measurement and is able to make measurements in a three dimensional flow. Figure 1 5. A generalized floating element sensor with the displacement under an input s hear stress shown in dashed outlines.

PAGE 41

41 Floating element shear stress sensors are direct methods that both have the capability of making mean and dynamic shear stress measurements. Microscale floating element sensors show the greatest promise in being able to make mean and time resolved measurements of wall shear stress. A generalized floating element is shown in Figure 1 5. The floating element and tethers are released and are free to move. As flow moves across the sensor the floating element displaces, as shown in the hashed outlines. The tethers act as restoring springs to move the floating element back to a nominal location when the flow input is removed. As discussed by Winter [13] favorable scaling, monolithic fabrication, and minimal cross axis sensitivity indicate that MEMS is an enabling techn ology for shear stress measurement. The success of the floating element measurement technique is the ability to detect the motion of the floating element. An example of a microscale floating element shear stress sensor is an optical shutter sensor develop ed by Padmanabhan, et al. in 1996 [23] The floating element was suspended over two photodiodes. An incoherent light source is placed opposite the sensor and the floating element acted as an optical shutter. The output of the two photodiodes is read as a differential photocurrent. The structure of the photodiode based floating element sensor is shown in Figure 1 6. While demonstrating a sensitivity and was calibrated in both ac and dc shear stress bench top experiments, it had several drawbacks which preven ted extension into wind tunnel testing. The largest source of error was the requirement of an external light source. The placement of this light source relative to the sensor was a large source of error and in a wind tunnel environment vibrations and the rmal gradients are expected. The

PAGE 42

42 mechanical motion of the light source and sensor relative to each other prevent this from being a robust measurement technique. Figure 1 6. A cross section of the photodiode floating element s ensor fabricated by Padmanabhan, et al. Figure adapted from A. Padmanabhan, H. Goldberg, K. Bonded Floating Element Shear (page 308, Figure 2) Journal of Microelectromechanical Systems vol. 5, no. 4, pp. 307 315, 1996. Since the 1980s many attempts have been made to realize a MEMS floating element sensor for quantifying wall shear stress using various transduction schemes [23 29] The focus of this work is capacitive transducers. 1 .5 Summary of Existing Floating Element Capacitive Shear Stress Sensor s Capacitive sensors ar e comprised of two electrodes, one attached to the floating element and one to the fixed substrate. The first micromachined direct shear stress sensor was a capacitive transduction based sensor deve loped by Schmidt, et al. [24] in 198 8. A schematic of t h is device is shown in Figure 1 7 The sensor relied on a change in overlap between an electrode in the floating element and two electrodes beneath a gap b elow the floating element. As the floating element was made from polyimide the sensor suffered from drift as the in plane stress of polyimide changes with

PAGE 43

43 cycling temperature and humidity. In addition to the embedded electrodes two p MOS transistors were embedded in the substrate of the sensor. This set a precedent for integrated electronics. However, due to a polyimide layer in the fabrication process, the device suffered significant drift due to moisture accumulation F igure 1 7 A cross section of the capacitive shear stress sensor with integrated electronics fabricated adapted from M. A. Schmidt, R. T. Howe, S.D.Senturia, Element Shear Stress Se (page 753, Figure 4) IEEE Transactions on Electron Devices vol. 35, no. 6, pp. 750 757, 1988. Comb drive based capacitive shear stress sensors have been developed by researchers at Case Western [30], [31] In Hyman et al. [31] work the sensor output was overwhelmed by parasitics and undetectable. Pan et al. hoped to improve upon this by using a structure similar to an accelerometer and by implementing force feedback with on board circuitry to avoid the p arasitics seen in the first generation sensor A schematic of the floating element with force feedback e lectrodes is shown in Figure 1 8 The force feedback was found to be insufficient at high shear inputs so the dynamic range of the sensor was lower th an predicted [30]

PAGE 44

44 Figure 1 8 A schematic of a capacitive comb drive based shear stress sensor impl ementing force feedback, adapted from T. Pan, D. Hyman, M. (Page 68, Figure 5) AIAA Journal, vol. 37, no. 1, pp. 66 72, 1999. A cantilever based shear stress sensor was developed by Zhe et al. [32] where the lateral movement of a proof mass was detected using capacitive transduction. The beam suspending the floating element was designed with a high aspect ratio in order to reject out of plane motion of the proof mass. The interface electronics consisted of a commercially available MS3110 Capacitive Readout IC. The MS3110 utilizes a charge amplifier and on chip trimming capacitors to detect aF of capacitance change. The charge amplifier is limited to a 1.5 pF minimum feedback capacitance and the bandwidth of the hip is limited to a maximum of 8 kHz. The minimum detectable signal was measured to be 0.04 Pa, but the sensor was only demonstrated in mean flow. The proof mass floating element shear stress sensor, along with the sense and actuate electrodes, is shown in Figure 1 9.

PAGE 45

45 Figure 1 9. A schematic of a proof mass based floating element shear stress sensor implem enting force feedback, adapted from J. Zhe, V. Modi, and K. R. Stress Sensor with Capacitative (page 169, Figure 1) Journal of Microelectromechanical Systems vol. 14, no. 1, pp. 167 175, 2005. Taking note of the shortcomings of these previous efforts Chandrasekharan et al. [29] designed and calibrated a monolithically fabricated floating element sensor with minimal parasitic contributions [33] The sensor possessed a normalized sensitivity of for ac shear stress, but was not able to achieve a reliable dc calibration due to a strong cro ss axis sensitivity to humidity and insufficient interface circuitry Sell s expanded on the design in Chandrasekharan et al. and implemented a wireless detection sche me. The capacitive sensor was used in a single ended fashion as one half of a passive resonant circuit. Due to an additional Teflon like coating the

PAGE 46

46 humidity sensitivity appeared to be mitigated and Sells was able to attain a static calibration [34] Again, a lack of instrumentation prevented dynamic measurement and static measurements were only achieved using large bench top spectrum analyzers. Figure 1 10 A schematic of the capacitive shear stress sensor designed by Chandrasekharan, et al. with an inset view of the asymmetric capacitor gaps. Figure adapted from V. Chandrasekharan, J. Sells, J. Meloy, D. P. Arnold, croscale Differential Capacitive Direct Wall Shear (page 623, Figure 1) Journal Of Microelectromechanical Systems vol. 20, no. 3, pp. 622 635, 2011. 1.6 Summary In this chapter the state of shear stress measurement is described and the tec hnical challenges of making a time resolved direct measurement using a MEMS based system are outlined. To da te the most successful attempts at time resolved direct measurement are floating element based MEMS sensors, outlined in Table 1 2, however no exi sting MEMS shear stress sensor system has been demonstrated in a wind tunnel facility. This work will expand upon the most successful attempts at shear stress measurement, the capacitive sensors by Chandrasekharan [29] and Sells [35] im proving on the sensor packaging, supporting system and calibration in order to make mean and dynamic shear stress measurements in multiple wind tunnel facilities. In addition, the sensor modeling is expanded and an additional fabricatio n process is

PAGE 47

47 outlined and the technical challenges of improving the overall smoothness of the sensor are described. Table 1 2. Existing MEMS based floating element methods Sensor System Element Size [mm] Shear Stress Range [Pa] Sensitivity [mV/Pa] Cali bration Type Sells [35] 1 4e 3 3.9 2729 ppm/Pa dc Chandrasekharan [29] 2 14.9e 6 1.9 7.66 ac Zhe [32] 3.2 0.04 .16 337 dc Padmanabhan [23] 0.5 1.4e 3 10 320 ac/dc Schmidt [24] 0.5 0.01 13 0.47 dc

PAGE 48

48 CHAPTER 2 SENSOR MODEL ING A capacitive shear stress sensor is an electromechanical transducer used to make time resolved mean and dynamic measurements of wall shear stress. The quasi static electrical and mechanical behavior along with the coupled dynamic behavior must be understood before the sensor is fabricated. This work will expand upon models that describe the in plane response of the floating element structure to include an ad ditional description of the out of plane response of the sensor The performance of the sensor is predicted using quasi static models, ultimately resulting in a lumped element representati on of the sensor dynamics that are used for optimization. This chapt er is divided into three sections; the quasi static mechanical model, the electrostatic model, and the resulting multi domain lumped element model for the dynamic response due to an input shear force and the resulting lumped element model for the dynamic r esponse due to an input pressure force. 2.1 Quasi Static Mechanical Model The sensor consists of a perforated rectangular floating element suspended over a cavit y by four tethers, as shown in Figure 2 1 As flow moves across the sensor, the floating elemen t will move in plane, changing the distance between the comb fingers. This change in distance is detected electrically by capacitive transduction that is discussed in Section 2.2. When the flow stops, the tethers, serve as restoring springs, move the flo ating element back to its nominal position. Ideally the displacement of the floating element, and thus the change in distance between the sets of comb fingers, is linear.

PAGE 49

49 Figure 2 1 A schematic of sensor geometry, not to scale indicating the design variables of the floating element width, W e and length, L e the hole diameters, d h the finger width, W f Length, L f and overlap, L o and the gaps between the fingers g 01 and g 02 In order to predict the range of input forces where the displacement is linear Euler Bernoulli beam theory is used to anal yze the behavior of the sensor for both small and large deflections. The non linear behavior is characterized by an energy model that accounts for in plane strain in the tethers [36] By assuming that the tether length is much larger than its width and thickness, that the silicon that is used to produce the floating element is isotropic and linearly elastic, and that the floating element and fingers move as a rigid ma ss the structure is represented by a clamped clamped beam The beam has a length width and a distributed force, where ( 2 1 ) The floating element is represented as a point load including the forces of the floating element where the element length and width are and respectively, and the force

PAGE 50

50 on the fingers, that have width and length This point load, ,applied to the cente r of the beam is ( 2 2 ) This simplified structure of the mechanical model with applied forces is shown below in Figure 2 2. Figure 2 2 A schematic simplifying the floating element sensor to a clamped clamped beam under an input shear force For the case of in plane deflection the moment of inertia is about the x axis is ( 2 3 ) T he deflection of the beam is, ( 2 4 ) that is reduced by substituting in for the moment of inertia,

PAGE 51

51 ( 2 5 ) where the [110] direction of silicon [10] The deflection at represents the displacement of the floating eleme nt and is ( 2 6 ) Given the mechanical d isplacement of the floating element as a function of input shear force the potential or kinetic energy of the system under a physical force is described. As the sensor converts energy from the mechanical domain to the electrical domain its performance in the electrical domain must also be characterized before a full model is developed. 2.2 Electrostatic Model The mechanical motion of the floating element is transferred into a voltage signal by capacitive transduction. When a bias is applied across the sens or floating element and substrate, charge accumulates on the comb fingers. These comb f orm a parallel plate capacitor and the change in the capacitance will be a function of the change in distance between the comb fingers and is measured electrically Ca pacitance is defined as ( 2 7 ) where is the charge on the plates and is the potential difference between the two plates. By examining the electric field between the plates t he cap acitance between these plates is

PAGE 52

52 ( 2 8 ) where is the permittivity of the material separating the plates, is t he area of the plates that overlap, and is the gap between them. Due to the aspect ratio of the tether structures the field is assumed to be contained in the gap between the two fingers and fringing f ields are assumed to be negligible therefore the parallel plate assumption is applied. The validity of this assumption has been discussed in prior work by both Sells [34 ] and Chandrasekharan [37] In those studies the capacitance due to fringing fields is approximately of the total capacitance of the finger or tether structure. The total change of the fringing capacitance is approximately of the total capacitance change. The parallel plate assumption greatly simpl ifies the electrostatic modeling of the transducer while only serving to underestimate overall performance slightly. As a plate is charged, the source of that charge is expending energy to distribute that charge and is stored in the form of electrostatic p otential co energy, The electrostatic potential energy is defined as [3 8] ( 2 9 ) This ene rgy is related to the force acting on the plates du e to the attraction or repulsion of the charges on the plates by [38] ( 2 10 ) For the one dimensional case of parallel plates this simplifies to ( 2 11 )

PAGE 53

53 It is important to note that for a change in voltage or a change in gap the force acti ng on the plates will change. Now considering the sensor structure, there are three sources of capacitance on the sensor structure; the comb fingers, the tethers, and the floating element, Each of thi s is indicated below on Figure 2 3 the contributions to outlined with dashes with dots and with dashes and dots Figure 2 3 Sensor structure with the capacitances associated with the comb fingers, the tethers, and the floating element, shown with dashes, dots, and dashes and dots, respectively As the floating element moves the gap of each capacitor is changed as a function of input shear as ( 2 12 ) where is in the direction indicated by the flow direction.

PAGE 54

54 Capacitor is between the moving comb fingers on the floating element and the fixed comb fingers on the substrate. In total three electrodes indicated as and in Figure 2 3, are involved and four capacitors are formed. Looking at a close up of the fin ger structure in Figure 2 4 the formation of two of the capacitors is seen. Figure 2 4 The p hysical structure of capacitor showing the asymmetric gaps between comb fingers This means for each set of comb fingers two capaci tances are formed creating ; ( 2 13 ) and ( 2 14 ) where is the thickness of the device layer and is the overlapping distance of the fingers shown in Figure 2 4 As there is a symmetric structure between electrodes and the total impedance due to the comb fingers is represented as a cap acit ive half bridge seen in Figure 2 5. The arrows represent the trend of the capacitance under a flow in the direction indicated in Figure 2 1.

PAGE 55

55 As is designed to be much larger than the effects of should be much smaller than in order to concentrate the electric field across resulting in a larger nominal capacitance and fewer parasitics. Figure 2 5. The e lectrical equivalent circuit for Capacitor is between the moving floating element and the fixed substrate. In total three electrodes, indicated as and in Figure 2 3, are involved and two capacitors are formed. Capacitor is formed between the moving tether and the fixed substrate. All three electrodes are involved and in total eight capacitors are formed. Looking at a close up of the corner of the element structure in Figure 2 6 the formation of three of the capacitors is shown Figure 2 6 Physical structures of the floating element capacitance, a nd the tether cap acitance,

PAGE 56

56 Due to the symmetry of the structure two capacitances are formed; one on each side of the floating element. This floating element capacitance, is ( 2 15 ) Four sets of capacitors are formed by the interaction of the tethers with the substrate. This tether ca pacitance, is composed of two parallel capacitances ( 2 16 ) and ( 2 17 ) where is the length of the tether that is approximated as a parallel plate capacitor when the tether is displaced and is approximated as ( 2 18 ) Figure 2 7 The half bridge circuit representation of all variable capacitances on the sensor structure. Combining all of these capacitances together, including the direction of change when under the influence of an applied force indicated in Figure 2 1, produces the

PAGE 57

57 equ ivalent circuit in Figure 2 7. This is simplified to a smaller structure by grouping terms dependent on each of the gaps resulting in Figure 2 8 where ( 2 19 ) Figure 2 8 The s implif ied half bridge representation of the complete floating element structure When the floating element is displaced the capacitances and are no longer be equal. The capacitance associated with the left side of Figure 2 1, becomes ( 2 20 ) or ( 2 21 ) The capacitance associated with the right side of Figure 2 2, becomes ( 2 22 )

PAGE 58

58 or ( 2 23 ) assuming that the direction of is positive in the directio n shown in Figure 2 1. Assuming that a voltage is applied to and a voltage is applied to the voltage at via superpos ition is ( 2 24 ) Substituting in for and produces ( 2 25 ) Reducing and assuming the di splacement is much smaller than the primary gap this becomes ( 2 26 ) The second term in the product is

PAGE 59

59 ( 2 27 ) and is associated with atte nuation due to the secondary gap. Just as the primary gap creates a sensing capacitance, the gap caused by the proximity of the next set of comb fingers will create an additional parallel electric field. As the relative motion of this secondary gap is op posite that of the primary gap it will be an undesired parasitic to the measurement. Now that the mechanical response of the sensor to an input shear force and the corresponding change in impedance due to a change in sensor position have been described, a dynamic model coupling the two domains is developed in order to predict sensor performance. Under an input pressure force ideally the voltage change at electrode is zero, however process variation and the resulting mismatch bet ween the two differential capacitors will allow for generation of an attenuated pressure signal. 2.2 Dynamic Modeling The technique of lumped element modeling (LEM) is used in order to bridge the domains and provide a computationally simple model to pr edict the dynamic behavior of the system [10] In order for LEM to be a valid approximation the wavelength of the physical quantity being measured must be much larger than the size of the sensor, allowing for d ecoupling of the spatial and temporal effects being measured. In this

PAGE 60

60 case, it means that the spatial variations in shear stress mu st be larger than the f loating element. While this approach is used for many domains, this work will focus on the transfer of energy between the mechanical and electrical domains. A lumped element model is comprised of elements that can either store or dissipate energy. is represented by passive circuit elements; a resistor representing the dissipati on of energy, a capacitor representing the storage of potential energy, and an inductor representing the storage of kinetic energy. In the electrical domain these three elements would make up a second order system. In the mechanical domain these three el ements could represent a spring mass damper system. The sources in both systems are represented by conjugate power variables. In the electrical domain a voltage source would produce a current that moves through the RLC circuit. In the mechanical domain a force produces a velocity Generally these are response of both systems using traditional techniques the analogy is obvious. The floating element structure is appro ximated as a mass spring damper system, where the mass is made up of the floating element and the distributed masses of the fingers and tethers, the tethers act as restoring springs, and the damper is a combination of fluidic damping of the air around the floating structure and internal friction of the tethers. In order to predict the electrical response to movement in the system the mechanical and electrical domains are coupled together using a transformer. A lumped element model is used to predict the dy namic system performance to both in plane and out of plane forces up to just beyond the first resonance of the

PAGE 61

61 structure The following sections will construct both models given the floating element structure. 2.2.1 Lumped Element Model for a Shear Input Given an input shear stress the floating element will translate in plane. As the floating element displaces the tethers act as restoring springs and the floating element as a mass, storing kinetic and potential energy respectively. By lumping around the point of maximum displacement a lumped mass and lumped compliance is extracted given the sensor geometry. energy of the system must be evaluated. To determine the lumped compliance th e potential energy and co energy of the system are evaluated. The displacement, associated with effort, is examined resulting in the potential energy ( 2 28 ) and co energy ( 2 29 ) The lumped compliance represented the storage of potential energy in the system. As this is a linear time invariant system the potential energy and co energy are equal. The potential energy of the system is ( 2 30 ) Using E quati on 2.28 the lumped compliance, through the derivation shown in Appendix A, is

PAGE 62

62 ( 2 31 ) To determine the lumped mass, the kinetic energy and co energy of the system are evaluated. The momentum, associated with flow, is examined resulting in the kinetic energy ( 2 32 ) and co energy ( 2 33 ) The lumped mass represents the kinetic energy of the system For a linear time invariant system the energy and co energy are equal. The total kinetic energy of the system is ( 2 34 ) Using E q uation 2.3 4 the lumped mass is fully derived in Appendix A is ( 2 35 )

PAGE 63

63 The mechanical na tural frequency of the sensor is predicted by assuming a second order system as ( 2 36 ) Assuming that the system is under d amped, the natural frequency approximates the resonant frequency Relating these mechanical parameters to an output electr ical signal is done using a two port transformer, as described in Appendix A. The parameter that determines how the two domains couple together is represented by the turns ratio of the transformer and is represented as ( 2 37 ) These lumped parameters are represented as a generalized circuit using impedance and inertance analysis. Lumped compliance can also be viewed as ( 2 38 ) where is compliance, is displacement, is effort, and is flow. Lumped mass is viewed as ( 2 39 ) where is mass and is momentum. C ombining all of these parameters together into a single circuit model produces Figure 2 7. As a constant charge b iasing scheme has been chosen for the transducer, the voltage across the sensor capacitance can change. When considering a two port

PAGE 64

64 impedance, meaning there is not a fixe d potential across the sensor. In order to capture the changing sensor voltage while coupling to the mechanical system, the impedances are transformed into the free impedances indicated with the prime superscript. The complete details of this are availab le in Appendix A. Figure 2 9 Circuit representation of the LEM for a shear force input where the mechanical domain is on the left, the electrical domain is on the right, and the electromechanical coupling is represented by lossless transformers. Using circuit analysis techniques the expected voltage at the sensor output is ( 2 40 ) where is the force acting on the floating element. The method used to predict sensitivity and dynamics for response to an in plane force is extended to out of plane forces as well.

PAGE 65

65 2.2.2 Lumpe d Element Model for a Pressure Input Given a dynamic pressure force, the floating element will act as a diaphragm and will move in plane. The loading of the beam will be the same as derived in 2.2.1 except that the beam is now moving in the y direction an d the moment of inertia of the beam changes to ( 2 41 ) w ith a resultin g transverse displacement of ( 2 42 ) The lumped mass and compliance of the floating element structure are expressed as ( 2 43 ) and ( 2 44 ) The full derivation of these elements is present in A ppendix B. Unlike the shear stress case, the acoustic properties of the cavity will now contribute t o the mechanics of the system. As the floating element moves the air in the

PAGE 66

66 cavity will act as a spring. The squeeze film damping and viscous losses of the fluid moving und er, around, and through the perforations in the floating will act as a resistive element. Following the procedure used to develop a perforated di aphragm capacitive microphone that uses models developed by Skvor [39] and Homentcovschi and Miles [40] to predict the resistance due to viscous losses as, ( 2 45 ) where is the number of holes in the element is the ratio of the area of the holes to the area of the floating element and is the viscosity of air The resistance due to squeeze film damping is predicted by Skvor as ( 2 46 ) where is the height of the back cavity and ( 2 47 ) The total acoustic resistance is the sum of these two resistive elements ( 2 48 ) The lumped approximation for cavity compliance is [41] ( 2 49 ) wh ere is the volume of the cavity. As the motion of the element has changed the way that motion creates a change in capacitance has changed. While the change in capacitance due to an input shear force was due to a change in the gap between electrodes an input pre ssure will cause a

PAGE 67

67 change in the overlapping area of two electrodes that will change the coupling coefficient and the conclusion of the electrostatics discussion. The coupling coefficient is found using the two port model derived in A ppendix B as ( 2 50 ) The full model is shown below in Figure 2 10. Figure 2 10 Circuit representation of the LEM for a pressure input where the mechanical domain is on the left, the electrical domain is on the right, and the electromechanical coupling is shown by lossless transformers. The prediction of the output voltage is difficult because ideally pressure is ideally a common mode signal to both sides of the bridge. In the ideal equation for output voltage the tether thickness term drops out. In reality, process variation creates a mismatch between the two cap acitors and the common mode rejection is imperfect. The output voltage is

PAGE 68

68 ( 2 51 ) Assuming that this term would be zero meaning there is no output due to a pressure input. Assuming a mismatch, such that and a pressure force acting on the sen sor, the output becomes ( 2 52 ) This mism atch is estimated using the fabrication in Chandrsekharan, et al. [29] as 0.91 where the capac itance values and were measured as and respectively [37] which resulted in a 64 dB overall rejection to an input pressure 2.3 Summary In this chapter the models used to predict the static and dynamic response of the sensor to an input shear stre ss sensor are outlined and additional models for the dynamic response to pressure are developed. Using these models sensor mechanical performance given shear and pressure inputs is predicted. Before overall sensitivity is determined the interface between the sensor and the electronics must be examined in order to determine what impact the electronics have on sensor performance.

PAGE 69

69 CHAPTER 3 INSTRUMENTATION DESIGN FOR CAPACITIV E TRANSDUCERS In order to predict the system response, the characteristics of the interface circuitry and the corresponding effects on sensor performance must be der ived This chapter will first outline the need for an interface circuit, then the building blocks for circuit modeling, and finally discuss two common interface circuits. Larger circuit topologies will then be discussed in the context of prior work using them as an interface with capacitive sensors. Finally the chosen system will be described in detail. 3.1 Impact of Interface Circuitry on Transducer Performance In order for a transducer to be used in any kind of system, it must ultimately interface with a data acquisition system or a component that will attempt to read the output signal, whether that is a voltage or current, of the transducer. For the capacitive shear stress sensor this will be an output voltage present at the middle node of the different ial capacitor as shown in Figure 2 8 Ideally, the interface will not alter the signal in any way. There are two primary considerations when analyzing how an interface circuit will influence the measurement; additional noise sources that can change the overall signal to noise ratio of the system, and parasitic impedances that can act as a source of signal attenuation. Higher order effects, such as the dynamic response of the circuit, will also impact design but are less gener alized and are left to the discussion of specific interface topologies in Section 3.4. Section 3.2 discuss es amplifiers, the most common building block for interface circuitry, and the sources of attenuation including parasitic impedances of common interf ace circuits and other sources of signal attenuation within

PAGE 70

70 amplifiers. Section 3.3 discuss es the major noise sources in an interface circuit and how they contribute to the output of a sensor system. 3.2 Amplifiers An operational amplifier is a basic acti ve component that is configured to provide gain in a system or simply provide an impedance buffer. T here are five ideal operational amplifier assumptions that must be examined for validity before building an amplifier; (1) the input impedance is infinite, (2) the output impedance is zero, (3) rejection of common mode signals is infinite, (4) open loop gain is infinite, and (5) the bandwidth of the amplifier is infinite. The input impedance of the operational amplifier is particularly important when int erfacing with any kind of transducer as this impedance will be in parallel with any device attached to the amplifier. An ideal operational amplifier is shown in Figure 3 1 with impedances at the inputs to account for non ideal op amp input properties. Figure 3 1 The model of an operational amplifier showing input referred noise current and voltage noise sources and finite input impedances.

PAGE 71

71 In Figure 3 1 the common mode input impedances are shown as and and the differential input impedance as The voltage supply to the amplifier is shown as for the positive supply voltage and as the negative supply voltage. The magnitudes of these impedances are given in the electrical specifications portion of an operational amplifier datasheet and are largely dependent on the technology used to manufacture the amplifier and the amplifier topology [42] The output impedance assumption is important when considering the load that the amplifier will be driving [43] Assuming moderate cable lengths and small scale installations the assumption of zero output impedance should not be an issue for this the capacitive sensor application. Common mode signal rejection is most easily described by a fully di fferential transducer. Taking the example of a fully active Wheatstone bridge any signal that affects all of the elements of the bridge equally will not propagate to the output of the sensor [44] Amplifiers are capable of this same rejection from signal s that are either common to bot h the inverting and non inverting amplifier inputs or to the power supply inputs. The ability of an amplifier to reject a common mode signal is dependent on the architecture of the amplifier and the tolerance of the process used to fabricate the amplifier Given that the capacitive transducer is not fully differential meaning that only one amplifier input will be utilized only the power supply rejection will be of interest and should be considered when the final system noise model is constructed. The op en loop gain of an operational amplifier is determined by its architecture. Finite open loop gain impacts frequency performance when the operational amplifiers are configured into high gain amplifiers or when amplifiers are operated at high

PAGE 72

72 frequencies by attenuating at higher frequencies. At low frequencies, keeping in mind that an amplifier cannot produce an output voltage that exceeds the voltage level that it is biased with, the output of the amplifier is limited based on the sensitivity of the transd ucer that it is being interfaced with. In most instances, the closed loop gain required to keep the sensor output within the rails of the amplifier is low enough so the open loop gain is considered comparably infinite [44] Figure 3 2. Frequency response of the open loop gain of an o perational amplifier. The final assu mption considers the amplifier bandwidth. Most operational amplifiers rely on an internal compensation circuit to stabilize the internal feedback loop [45] The capacitance required in this stabilization circuit is usually chosen such that it creates a dominant pole in the amplifier, generating a low pass response. The open loop gain is express ed as a general single pole system ( 3 1 )

PAGE 73

73 w here is the open loop gain and is the 3dB frequency. The open loop gain of such a single pole system rolls off at 20dB/decade. The frequency where the response reaches 0dB is defined as the unity gain bandwidth, These frequencies are labeled in Figure 3 2 The roll off in open loop gain with increasing frequency will eventually cause the assumption that the open loop gain is much larger than the closed loop gain to fail. This will a ttenuate the a mplifier output. This effect is normally describe d as the gain bandwidth product ( GBWP ) 3.3 Basic Noise Models and Non Idealities This section will present the noise models and other non ideal characteristics of passive components, how they combine, and f inally the noise characteristics of operational amplifiers 3.3.1 General Noise Characterization Generally, noise is defined as any unwanted disturbance in a signal and the characterization and minimization of noise is critical to the success of any system. E lectronic noise is expressed in terms of a power spectral density and is a function of frequency. To characterize the propaga tion of noise through a system individual noise sources are modeled as voltage or current sources [46] There are many categories of noise, however i n this work the dominant noise sources are thermal noise and low frequency noise. Thermal noise is characterized by flat spectral density content across the frequencies of interest. It is caused by random therma l carrier excitation In a bulk material th e electrons vibrate in Brownian motion. While the net current through the

PAGE 74

74 bulk material due to this random motion is zero the random charge fluctuations create a time varying voltage across the material. The total available noise power of a conductor is represented as ( 3 2 ) ture in Kelvin, and is the bandwidth that the noise is measured over One of the goals of this work is to perform a dc measurement, the behavior of both of these theoretical noise types at zero frequency is also important. Low frequency noise, also called or flicker, is a noise characterized by large low frequency content that decreases in power proportional ly to an increase in frequency It is present in almost all electronic systems, including tr ansistors, diodes, and some resistors. Flicker noise is largely a property of the surface of the material that a device is made from due to the random recombination and generation of carriers due to bulk or surface charges, such as those present at the in terface between silicon and silicon dioxide. Low frequency noise should be infinite by definition at dc. While the level of noise is constantly decreasing as frequency increases, the total noise power contained within each frequency decade is constant. This restriction on total power per decade combined with the time scales of actual equipment usage constrains the noise power from going to infinity at dc. In all cases, a specific device will have some combination of thermal and noise, resulting in a shaped noise spectrum Given multiple uncorrelated noise sources in a linear system, the source spectra will add in power, resulting in an overall noise spectrum for the system. Every passive and active component contains multiple noise

PAGE 75

75 sources. The representations for commonly used components follow in Section s 3 3 .2 and 3 3 .3. 3.3.2 Noise in Passive Components There are two types of passive components used in this system, resistors and capacitors. This section will discuss the nois e characteristics of both independently and then their combined effect on the noise spectrum. Resistors are made using many different technologies. In this work they will be generalized into two kinds of resistors, metal film and polysilicon (poly) [46] In CMOS integration resistances are realized using polysilicon strips of a given sheet resistance. By manipulating the geometry of the poly the resistance is changed however low resistances require very thick or wide films with higher doping concentrations Metal film re sistors are implemented with metal strips of varying geometry. Given the sheet resistances of metals, lower resistances are easier to achieve using metal film technology. While both technologies result in theoretical thermal noise levels, the low frequen cy performance varies greatly depending on the fabrication technology. Poly resistors generally have higher noise [46] Theoretically metal film resistors should have no noise, but in practice some low frequency noise i s observed due to non idealities in packaging. The available noise power, shown in 3.3.1, is the total available power that is sourced by a noisy resistor to a noiseless load resistor. For maximum power transfer the load resistance is equivalent to the s ource resistance and thus t he power spectral density of noise in a resistor is given by ( 3 3 )

PAGE 76

76 where is the absolute temperature of the resistor, is the resistance value, and is Boltzma n This is represented as a voltage source or e quivalent current source given by ( 3 4 ) and ( 3 5 ) A noisy resistor is decomposed into the equivalent noise voltage source and a noiseless r esistor, or into a noiseless resistor and a Norton equivalent curr ent source, as shown in Figure 3 3 [46] per the fluctuation dissipation theorem An ideal air gap parallel plate capacitor has no mechanism for noise generation, as there are no carriers to vibrate and no dire ct charge transfer. Many capacitors ar e made with a ceramic insulator, so that the dielectric properties are manipulated to achieve a larger range of c apacitance values. These ceramic materials have a finite resistance that can result in a parallel resis tance, that is then subject to noise induced by a resistor. Figure 3 3 A noisy resistor and the equivalent Thevenin and Norton equivalents showing the noise as an independent voltage or current source The noise characteristi c across the parallel combination of a resistor and capacito r, known as noise, is a shaped spectrum dependent on the values of

PAGE 77

77 and Given a parall el circuit, shown in Figure 3 4 the thermal noise of t he resistor is low pass filtered Figure 3 4 The circuit m odel for analysis of the effect of a parallel capaci tance on the thermal noise of a resistor As the product changes, the shape of the noise at the output will change as ( 3 6 ) To illustrate this shaping, assume an initial product of 0.1, the effect varying the value of from 1 to 9 is shown i n Figure 3 5 versus normalized frequency As the product increases the corner of the low pass filter moves lower in frequency, resulting in higher noise at low frequencies but lower noise values as frequency increases. While va rying the resistance changes the shape of the noise, it does not change the root mean square value. The total noise power is given by ( 3 7 ) Using change of variables, letting results in ( 3 8 ) Substituting in for gives

PAGE 78

78 ( 3 9 ) This is interesting in that the total output root mean squared noise is not dependent on the thermal noise source being shunted, but rather solely the parallel capacitance. This wil l become important as more complex circuit systems are constructed using RC combinations. Figure 3 5 The spectral density of the thermal noise of a resistor shaped by a parallel capacitance plotted against normalized frequency to demonstrate the spectral shaping of the RC product. 3.3.3 A mplifier Noise The most common method in instrumentation design to create an amplifier is to use external feedback with an operational amplifier to perform a specific function. As an operational amplifier is constructed using multiple transistors and passive components, it is more useful to combine all of the individual noise sources to the input of the

PAGE 79

79 amplifier. Operational a mplifier noise is characterized by two sources, a voltage noise source at the input of the amplifier and a current source in parallel with the inputs. This model is shown in Figure 3 6 [47] The voltage supply to the amplifier is shown as for the positive supply voltage and as the negative supply voltage, while and represent the input referred voltage and current noise sources respectively. Figure 3 6 The o perational a mplifier noise model showing the overall noise of the amplifier as an input referred voltage and current source Usually the amplifier manufacturer will produce a plot describing the low frequency noise char acteristics of the amplifier. 3.3.4 Other Non Idea lities One of the most basic constraint s on amplifier performance is the output swing. An amplifier cannot physically produce a voltage larger than what it is supplied from its power inputs, and in many cases is restricted to some incremental value below these power inputs depending on the operational amplifier architecture. The resulting output 7

PAGE 80

80 (A ) (B ) Fi gure 3 7 A visualizati on of A ) linear amplifier operation and B) clipped amplifier operation. 3.4 Interface Circuit s In this section two basic interface circuits are discussed. The noise characteristics and transfer functions are explained and the applications that they are well suited for use in are outlined. 3.4.1 Unity Gain Voltage Buffer The simplest non inverting operational amplifier implementation is the unity gain voltage follower, shown in Figure 3 8 Simple circuit analysis shows that meaning t hat if this circuit is interfaced with a transducer the output voltage of the transducer would be translated, but the impedance of the transducer would be decoupled from anything attached to the output node

PAGE 81

81 Figure 3 8 The circuit schematic of a u nity g ain o perational a mplifier To interface the capacitive transducer with a voltage amplifier, a constant charge biasing scheme is used. In this case, two signals of opposite phase are placed on either end of the capacitive hal f bridge as shown in Figure 3 9 Interfacing the capacitive transducer with the small signal noise and parasitic model of the voltage buffer provides meaningful insight into its behavior and the metrics that should be examined when choosing the amplifier Through analysis shown in detail in Appendix C the output when considering parasitics is ( 3 10 ) This shows the output voltage has a high pass characteristic based on device capacitance and bias resistance. Past the system cut on, the output voltage reduces to ( 3 11 )

PAGE 82

82 Figure 3 9 The circuit model of the sensor and a unity gain am plifier including parasitics associated with the amplifier and sensor packaging. Next, considering that and are described as and E quation 3 .10 is further reduced to ( 3 12 ) or ( 3 13 ) In this simplification the frequency term drops out, however it is important to note that as the impeda nce of a capacitor is infinite at dc This means that when sensing a mean capacitance change when a dc bias is applied the output voltage will be undefined. The noise performance of the voltage buffer is also important in determining its usefulness in int erfacing with capacitive transducers. In A ppendix D the output referred noise characteristic is derived in detail. From the schematic shown in Figure 3 1 0 the total output referred noise is

PAGE 83

83 ( 3 14 ) where ( 3 15 ) as indicated in Figure 3 12. For simplicity, consider operation and performance above the system cut on, where The output referred noise from E quation 3 13 then reduces to ( 3 16 ) It is important to note that two of the thr ee noise contri butions are shaped by frequency. First, the current noise of the amplifier is scaled by the impedance of the capacitive elements Second, thermal noise of the bias resistor is shaped by the impedance of the capacitive elements. Figure 3 1 0 The s mall signal model of the sensor and a unity gain amplifier including noise sources.

PAGE 84

84 The relative order of magnitudes of the three noise sources will allow for further simplification in this expression. As reported in C handrasekharan [29] m easured values for the device capacitance, including parasitics associated with the device, are on the order of A nominal value for an off the shelf amplifier with a low capacitance input is around This produces a total c apacitance of around In order to quantify all o f the noise sources, the bias resistance must be determined. As shown in Figure 3 11, the device capacitance and bias resistance form a high pass filter network. This creates a cut on frequency and eliminates the possibility of measuring an input voltage with at low frequencies or dc. As the value of the bias resistance increases, it will approach the input impedance of the amplifier and inhibit the proper functioning of the input stage of the amplifier. The selection of the bias resistance becomes a bal ancing act between voltage noise, amplifier input impedance, and desired frequency of operation. As the frequency of operation of the sensor is increased the bias resistance value can decrease and the overall performance of the circuit will improve. 3.4.2 Ch arge Amplifier The second simple interface circuit topology is the charge amplifier shown in Figure 3 1 1 Again, this circuit serves as a means to decouple the transducer from the output node while maintaining signal integrity and is commonly used in low signal application such as accelerometer interface circuitry This dif fers fundamentally from the voltage amplifier as a gain is introduced by changing the feedback impedance. Using superposition, similar to the derivation shown in Appendix C, the output voltage of this system assuming and is

PAGE 85

85 ( 3 17 ) Assuming that the system is operating beyond the high pass cut on set by the feedback impedance the output is simpl ified to ( 3 18 ) Figure 3 11. The circuit schematic of a charge amplifier interfaced with the sensor, including parasitic capacitances. The important thing to notice is that the output is independent of any parasitic contributions. This relaxes packaging requirements as the interface electronics no longer have to be co located with the sensor. Again, as in the case of the voltage buffer in this simpli fication the frequency term drops out however as the impedance of a capacitor at dc is infinite this simplification is invalid at dc The dc operation of the circuit is defined by the bias and feedback resistances and the amplifier. This means that with out a frequency component the output voltage will be undefined. T he noise characteristics of a charge amplifier are examined using Figure 3 1 2

PAGE 86

86 Figure 3 1 2 The schematic of the sensor interfaced with a c harge amplifier incl uding small signal noise sources Again using superposition, following the analysis in Appendix D for the voltage amplifier case the output referred noise is ( 3 19 ) w here ( 3 20 ) as shown in Figure 3 14 and ( 3 21 ) The feedback impedance while providing a source of gain also serves as a low pass filter for the interface circuit. If the transducer output has frequency content above the filter cutoff it will be attenuated, making charge amplifiers more suited for low frequency applications.

PAGE 87

87 Given these basic interface building blocks the overall circuit topology is chosen. U sing the noise and impedance characteristics developed in this section, the overall performance is predicted. 3.4.3 C omparison of V oltage and C harge A mplifiers Given the models developed in 3.4.1 and 3.4.2 the performance of voltage amplifiers and charge amplifiers are compared in this section so that the chosen interface topology has the largest possible signal to noise ratio (SNR) For this study two amplifiers will be chosen as representative examples of op amps. The first is the AD8022 from Analog Devices and is an example of a low voltage noise, low input capacitance amplifier [48] The second is the OPA129 from Texas Instruments and is an example of a low current noise, low input capacitance amplifier [49] The parameters for each are shown in Table 3.1. Table 3 1. Op Amp parameters for parametric study of interface amplifier topolo gies. Part Number Input Capacitance Input Referred Current Noise Input Referred Voltage Noise AD8022 0.8 pF 1 2.3 OPA129 1 pF 0.1 15 The comparison is made for several nominal capacitances ( and ) and bandwidths of interest ( and ) in order to determine scaling trends in overall SNR. In all cases the assumed bias voltage is and the change in capacitance is T he charge amplifier is configured such that there is no gain i n order to compare the performance directly to the volt age amplifier. If gain is programmed into the charge amplifier, the signal to noise ratio will be effected only if the bias resistance is the dominant noise contribution. As the feedback capacitance

PAGE 88

88 decreases, the resistances will have to increase in ord er to maintain the same cut on frequency and thus the noise floor will change. The bias resistance is assumed to be equivalent between the two topologies The results are categorized by nominal device capacitance, where the amplifier and bandwidth are s wept for each device. The metrics that are examined are the total noise and the signal to noise ratio. 3.4.3.1 Comparison with smallest device capacitance For a device with a nominal capacitance of the bias resistances in orde r to hit the bandwidths of interest are and respectively. Realistically, these impedances are too large to be implemented with the AD8022 as they are on the order of the input resistance The OPA1 29 would still be able to function with input resistances on this order so only it is considered for this nominal capacitance As the lowest bias resistance is associated with the 1 MHz bandwidth it is used to examine the magnitudes of the voltage noise current noise, and resistor noise in a given configuration. The total noise and the considered contributions are shown in Figure 3 1 3 for the total noise of a charge a mplifier and voltage amplifier. The total noise for the different configurations and all bandwidths are shown in Figure 3 1 4 From this figure it is clear that in all configurations the OPA129 in the voltage amplifier configuration has the lowest noise floor. While at this point in the analysis the obvious choice is the voltage amplifie r configuration the impact of parasitic capacitance on signal attenuation has not yet been considered.

PAGE 89

89 (A) (B) Figure 3 1 3 The noise contributions and total noise for interfacing with a 0.1 pF capacitor with a signal of interest at 1 MHz usin g an OPA129 configured as a A) a voltage amplifier and B) a charge amplifier.

PAGE 90

90 Figure 3 1 4 The noise spectra of the OPA129 configured as a voltage amplifier and current amplifier for multiple bias resistances to interface with a transducer with a nomina l capacitance of 0.1pF. The metric that these effects are evaluated is the overall signal to noise ratio of the system. The signal to noise ratio is determined by the power of the output signal when the total capacitance change is and the power of the noise. The results of this analysis are shown in Figure 3 1 5 While the voltage amplifier has the lower noise floor, the small nominal capacitance is completely overwhelmed by the parasitic input capacitance of the amplifier and so the overall signal to noise ratio is very small. The charge amplifier configuration, while having higher noise, has much higher signal and thus has a much better overall performance. For small nominal capacitances the overall signal to noise ratio is improved by using a charge amplifier. When the nominal device capacitance changes the trends in signal to noise ratio also change.

PAGE 91

91 Figure 3 1 5 The comparison of the signal to noise ratio of multiple configurations. 3.4.3.2 Comparison with intermedia te device capacitance For a device with a nominal capacitance of the bias resistances in order to hit the bandwidths of interest are and respectively. At the lower bias resistances the AD8022 is now functional For this case both the AD8022 and OPA129 are considered. First, the AD8022 is examined. The AD8022 is chosen as a representative amplifier for low input capacitance and low voltage noise. As in Section 3.4.3.1, t he noise contributions and resultant total spectrum is shown for the AD8022 configured as a charge and voltage amplifier in Figure 3 1 6 As this amplifier has relatively high current noise, the current noise becomes the dominant term in the overall noise equation. Examining all of the output referred noise plots again it appears that the voltage amplifier configuration has lower overall noise, as the current noise of the amplifier is shaped by an overall lower

PAGE 92

92 impedance than in the charge amplifier config uration. The compiled noise spectra are shown in Figure 3 17 As the OPA129 is chosen as a representative of a low current noise amplifier the noise spectra are shaped by the bias resistance rather than this cur rent noise, as shown in Figure 3 20. Also, the overall noise spectra for varying bandwidths also appear to have trending as seen in 3.4 .3.1, as seen in Figure 3 18 where the voltage amplifiers have overall lower noise floors and all spectra are shaped with respect to the magnitude of the bias resi stance. The view of system performance through noise floor is again only part of the total picture. The signal to noise ratio is the final evaluation of overall system performance. The signal to noise ratios for all configurations are shown for the AD802 2 and OPA129 in Figure 3 19. In the case of the AD8022 the overall signal to noise ratio is roughly equivalent in all implementations. For the OPA129, however, the signal to noise ratio demonstrates that the charge amplifier is the more appropriate imple mentation at high frequencies. It is important to note, however, than the AD8022 implementations have overall higher signal to noise ratios but the signal to noise ratio is also greatly frequency dependent. This is due to the heavy shaping of the domina nt current noise and the difference in fundamental noise level between the OPA129 and AD8022 that is a result of the dominant noise mechanisms in both cases. This is seen in Figure 3 20, where the signal to noise ratio for all implementations is plotted a gainst frequency.

PAGE 93

93 (A) (B) Figure 3 1 6 The noise spectra of an AD8022 for a nominal capacitance of 1pF at 1 MHz A) configured as a charge amplifier and B) configured as a voltage amplifier

PAGE 94

94 Figure 3 17 The noise spectra of the AD8022 configu red as a voltage amplifier and current amplifier for multiple bias resistances to interface with a transducer with a nominal capacitance of 1pF. Figure 3 1 8 The noise spectra of the OPA129 configured as a voltage amplifier and current amplifier for mul tiple bias resistances to interface with a transducer with a nominal capacitance of 1pF.

PAGE 95

95 (A) (B) Figure 3 19 T he noise spectra of an OPA129 for a nominal capacitance of 1pF at 1 MHz configured as A) a charge amplifier and B) a voltage amplifier.

PAGE 96

96 (A) (B) Figure 3 20 The signal to noise ratio for all configurations when interfanced with a device of 1 pF nominal capacitance using A) an AD8022 and B) an OPA 129

PAGE 97

97 3.4.3.3 Comparison with largest device capacitance For a device with a nomina l capacitance of the bias resistances in order to hit the bandwidths of interest are and respectively. At the lower bias resistances the AD8022 is now functional. For t his case both the AD8022 and OPA129 are considered. First, the AD8022 is examined. The noise spectra for the AD8022 configured as a charge amplifier and voltage amplifier are shown in 3 2 1 As seen in 3.4.3.2 the dominant noise source is the amplifier c urrent noise and the overall noise shape and level tracks the bias resistance. The corner of the noise, however, is being pushed to higher frequencies making the overall noise level higher. The output referred noise for all configurations is shown in Fig ure 3 2 3 Next, the OPA129 is again considered. The noise spectra for the OPA129 configured as a charge amplifier and voltage amplifier are shown in Figure 3 2 2 It is interesting to note that at this lower bias resistance the shaping of the resistor n oise is greatly decreased and the overall level of the resistor noise is now approaching the amplifier voltage noise. The total noise spectra is a combination of these two effects, but is reduce overall in magnitude compared to the implementations in Sect ions 3.4.3.1 and 3.4.3.2. The output referred noise for all configurations is shown in Figure 3 2 4 Again, the signal to noise ratio is the ultimate determining factor for choosing an interface topology. The signal to noise ratio for the AD8022 implement ations and the OPA129 implementations are shown in Figure 3 2 5

PAGE 98

98 (A) (B) Figure 3 2 1 The noise spectra of an AD8022 interfaced with a nominal capacitance of 10pF at 1 MHz configured as A) charge amplifier and B) a voltage amplifier.

PAGE 99

99 (A) (B) Figure 3 2 2 The noise spectra of an OPA129 interfaced with a nominal capacitance of 10pF at 1 MHz configured as A) charge amplifier and B) a voltage amplifier.

PAGE 100

100 Figure 3 2 3 The noise spectra of the AD8022 configured as a voltage amplifier and cu rrent amplifier for multiple bias resistances to interface with a transducer with a nominal capacitance of 10pF. Figure 3 2 4 The noise spectra of the OPA129 configured as a voltage amplifier and current amplifier for multiple bias resistances to interf ace with a transducer with a nominal capacitance of 10pF.

PAGE 101

101 (A) (B) Figure 3 2 5 The signal to noise ratio for multiple implementations of interface circuitry constructed to interface with a transducer with a nominal capacitance of 10pF with A) the AD802 2 and B) the OPA129.

PAGE 102

102 While it appears that charge amplifiers again are the correct choice, the lowest bias resistance implementation of the voltage amplifier gains ground to again be comparable to a charge amplifier. This demonstrates the fundament al tipping point of the tradeoff between parasitic insensitivity and lowered noise floor. The same trade offs are seen in Figure 3 2 6 showing the signal to noise ratio for the OPA129. 3.4.3.4 Conclusions and p ractical considerations From Section s 3.4.3. 1 through 3.4.3.3 ther e are demonstrated instances where both topologies are required. For cases where the nominal sensor capacitance is much lower than the parasitic i nput impedance of an amplifier a charge amplifier is the appropriate interface. If the nominal sensor capacitance is on the order of or greater than the parasitic input impedance of an amplifier, then the choice of interface topology is highly dependent on the amplifier current noise and the frequency of interest. There are also practical implications that can drive the choice of interface topology. The passive components required to implement either of these topologies and the physical implementation of the circuit greatly impact the overall performance. If implemented in a printed circu it board stray capacitance in layout and the tolerance of the external passive capacitors and resistors must be considered. For simplicity in implementation and given prior efforts resulting in a nominal capacitance varying between and a voltage amplifier implemented with an AD8022 and a bias frequency of is the appropriate interface. 3.5 Open loop Interface Circuitry Topologies There are two distinct categories of interfac e circuitry, continuous time, also referred to as analog and discrete time. Discrete time systems are characterized by

PAGE 103

103 the presence of one or more clock signals that are used to discretize the signal being processed by the interface circuit before it rea ches a traditional data acquisition system. Realistically, all signals are discrete time at some point, as any measurement system includes a digital analysis component, but a continuous time system refers to the signal conditioning before digitization dur ing data acquisition. 3.5.1 Conti nuous Time Implementation There a re two approaches to continuous time implementation of capacitive interface circuitry direct interface and synchronous modulation and demodulation (synch MOD/DMOD). Direct interface, as the na sensor output, while synch MOD/DMOD involves at least one stage of frequency translation. This section will discuss the tradeoffs of both approaches. Direct interface is achieved by interfacing the capacitive tran sducer with either a voltage follower or charge amplifier, as shown in 3 .2.1 and 3 .2.2 respectively. T he choice between a voltage amplifier and charge amplifier is reliant on the nominal capacitance of the system and whether that nominal capacitance will be overwhelmed by the inherent parasitic capacitances Additionally, the noise characteristics must be considered given the signal level at the output of the transducer and the required system signal to noise ratio. The largest drawback of a direct interf ace system is the system output g iven a mean capacitance shift. As discussed in 3 .2.1 and 3 .2.2 the output of a capacitive half bridge is undefined if there is no frequency content and therefore does not function at dc If the bias signal provided to th e bridge is a dc voltage then any fluctuating input will be directly transduced. Assuming a voltage buffer configuration is used, due to the

PAGE 104

104 bias resistor, a mean displacement will have a transient output voltage that will decay with the time constant fo rmed by the bias resistance and device capacitance ( 3 22 ) The solut ion to this is to apply an ac bias to the bridge making the output signal ( 3 23 ) where is a sinusoidal signal. This produces an amplitude modulated (AM) signal at the output, where the bias frequency is what is traditionally referred to as the carrier frequency. This process of translating to a h This technique is referred to as synchronous modulation/demodulation (synch MOD/DMOD) and will be fully outlined in Section 3 .7 While the up converted sensor output is adequate some applications, such a s feedback for flow control require the base band sensor information. This requires a down conversion stage that will translate the information back to the frequencies of the flow dynamics. This approach has been used previously in the development of mi crophones for infrasound accelerometers, and other low frequency acoustic applications [50 53] 3.5.2 Discrete Time Implementation Integrated circuits are implemented t o measure capacitance using digital techniques without using feedback switched capacitor [54 56] Due to the noise characteristics of MOS switches continuous time sensing, particularly of small capacitan ce values, has better overall system noise characteristics [57] These noise sources is mitigated by correlated double sampling or chopper stabilization [58], [59]

PAGE 105

105 3.6 Closed loop Interface Circuitry Topologies In a closed loop system the output is fed back to the input and acts as a restoring force on the capacitive transducer to move it back into its nominal position for a given displacement. The restoring voltage required to maintain the equilibrium position is a function of the input shear stress. The application of the restoring force and the system read out must be multiplexed in time in order to p revent the force feedback from a ffecting the measurement. The result implementing a closed loop is increased linearity and possible manipulation of sensor mechanics. 3.6.1 Continuous Time Implementation In continuous time a closed loop system is implemente d by a baseband feedback signal. The separation of the feedback signal and the sensor output is achieved in freq uency in order to prevent signal contamination. These are most commonly implemented in capacitive accelerometer interface circuits or capacitive microphone interfaces to improve device linearity and increase bandwidth [60 62] 3.6.2 Discrete Time Implementation The most common discrete time closed loop system is the sigma delta ( ), also sometimes referred to as delta sigma, system. Widely available in analog to digital conversion schemes [63] the benefit of a system is the low frequency noise performance. Through oversampling and decimation the low frequency noise of the system is up converted away from the baseband. This has become standard in data acquisition systems as it improves dynamic range at low frequencies. Systems using a topology require careful timing to ensure proper operation and control of trace lengths as they require high sampling rates in order to achieve adequate oversampling, particularly for high er bandwidth applications. As they have largely been

PAGE 106

106 implemented as application specific integrated circuits (ASICs) systems have been extended to post CMOS MEMS applications due to ease of integration [64], [65] The design and implementation of a system for interf ace with a capacitive transducer was approached by Kadirvel [66] in a discrete component based implementation. The overwhelming parasitics and power supply noise, issues that could be mitigated in an ASIC application, were two of the items Kadirvel found to require improvement. While a system level optimization, including an ASIC interface, would be an interesting contribution, it is outside of the scope of this dissertation 3.7 Synchronous Modulation/Demodulation With favorable design tolerances allowing for discrete implementation without compromi sing circuit performance a synch MOD/DMOD system, such as those implemented in low frequency microphone and accelerometer applications [50], [51], [53], [67] will be constructed. There are two basic synch MOD/DMOD approaches; a mixer based system and an envelope detector. 3.7.1 Mixer Based Implem entation Mixers are non linear devices that enable frequency translation through the effective multiplication of two sinusoids [68] For example, if the sensor is biased with a signal and the sensor output is where and r epresents the frequency that t he sensor is physically excited The mixer will multiply and resulting in ( 3 24 ) Recalling the trigonometric identity ( 3 25 )

PAGE 107

107 E quation 4.20 is expanded to ( 3 26 ) Substituting in the definition of the baseband information is extracted from higher order effects using analog filtering as the frequency separation between the two signals is twice the original carrier as seen in ( 3 27 ) As mixing is inherently non linear, higher order harmonics will also be generated, however with careful frequency planning they can fall outside of the signal bandwidth and be removed using analog filters. In the first generation of this sensor [37] a mixer based approach was attempted using the AD835 4 Quadrant Multiplier however an apparent dc dri ft was noticed during experimentation Analog D evices, the manufacturer of the AD835, has since moved away from mixers derived from the Gilbert Cell mixer architecture, because the Gilbert Cell contains inherent phase and amplitude errors that propagate to the output of the mixer, manifesting as dc errors [69] For applications where dc information is not required, where the signals are inherently phase locked, or where multiple frequency translations are required a mixer is an elegant solution. 3.7.2 Envelope Detector Implementation An alternate approach to demodulatio n is t he e nvelope detector [70] An envelope detector is made up of t wo main blocks; a rectification block and a filtering block. The

PAGE 108

108 frequency translation that occurs during multiplication in the mixer case is achieved through rectification. Considering an amplitude modulated signal ( 3 28 ) where represents a dc shear response combined with any inherent dc offse t of the sensor due to mismatches in the bridge is the ac wall shear stress response, and is the carrier frequency. The time series of this signal is shown in Figure 3 2 6 where the modulated signal is in blue and the signal that is to be recovered is in red Figure 3 26. An amplitude modulated signal with 100% modulation depth and the corresponding output of a passive rectification scheme. Envelope detection is not without design constraints. At the simplest level, rectification is thought of as taking the absolute value of the modulated signal. As the amplitude of the signal being modulated approaches that of the carrier signal errors in

PAGE 109

109 the rectified signal may result. This is quantified by the modulation index, also referred to as modulation depth [71] ( 3 29 ) Figure 3 27. An amplitude modulated signal with 150% modulation depth and the corres ponding output of a passive rectification scheme. As modulation depth increases beyond 1 00% rectification will fail to capture the phase inversion, and amplitude and dc error s will occur. Figure 3 26 shows a signal with 100% modulation depth and the resu lting rectification output both in blue, superimposed with the original message signal in red. At this limit the message is preserved. Considering a purely oscillating input to a perfectly matched capacitive half bridge the modulation depth would be infin ite Realistically there are imperfections in the capacitive half bridge that result in a static dc offset. This re sults in defined, albeit high, modulation depths. Figure 3 2 7 demonstrates that at a modulation depth of 150% the

PAGE 110

110 modulated signal with th e original message superimposed in red. In order to preserve the phase inversion, the rectification mechanism must also be phase locked to the signal. This means that an active rectification scheme must be implemented. Active rectification is the multip licatio n of an amplitude modulated wave, with a phase locked square wave, The resulting multiplication is ( 3 30 ) Implementing the trigo nometric identity given in 3 .21, E quation 3 .27 becomes ( 3 31 ) Figure 3 28. An amplitude modulated signal with modulation depth of 150% and the corresponding output of active rectification with no pha se error.

PAGE 111

111 The result is similar to the result given by the mixing case in that the baseband signal is separated out from the rest of the modulation by at least If the example of 150% modulation depth from Figure 3 28 is recti fied using an active rectification scheme the result is shown in Figure 3 2 9 where the modulated signal is again shown in blue, the message in red, and the rectification signal in black. As a phase mismatch is introduced between the rectification s ignal a nd the modulated signa l the rectified harmonics are being generated and fed through. The worst case occurs when the rectification signal and modulated signal are 90 degrees out of phase with one another. A t this point the signal does not appear to be rectified at all. This is shown m athematically this makes sense from E quation 3. 26 by substituting in a phase shift ( 3 32 ) I nstead of the multiplication of two cosine functions, the result is the multiplication of a sine and cosine. Using the trigonometric identity ( 3 33 ) E quation 3 .29 reduces to ( 3 34 ) T he message signal is still recoverable, however the filtering requirements will be more stringent due to larger harmonic content and the time series is much less intuitive as

PAGE 112

112 seen in Figure 3 29 Intermediate phase mismatches result in a decreased sensitivity as it results in an attenuating dc offset. Figure 3 29. An amplitude modulated signal with modulation dep th of 150% and the corresponding output of active rectification with a 90 degree phase error. 3.8 Generalized Interface Circuit Given the tradeoffs discussed in this chapt er, the system shown in Figure 3 3 0 has been designed and implemented. At the points along the signal path th e color coding used in Section 3 .5 has been preserved, so a blue shape means that is a modulated signal, a red shape means that is the message of interest. The signal has been shown at multiple points along the circuit for further illustration.

PAGE 113

113 Figure 3 30 A high level block diagram of the active rectifier based s ynch MOD/DMOD system for use with the capacitive shear stress sensor The voltage follower will be co located with the sensor die in order to reduce the parasitics associated with cabling going to and from the die and to condition the sensor impedance down to mitiga te electromagnetic interference The rest of the circuitry is located an arbitrary distance from the sensor in order to reduce res trictions on its size. An active rectifier was chosen due to its robust response to phase errors. This chosen topology isolates the majority of the circuitry from interfacing directly with the sensor. The only point where the sensor is loaded by the ci rcuit is at the node between the common electrode of the sensor and the input to the voltage follower. As described in Section 3 .2.1 the voltage follower will have finite input impedance that is modeled as a parallel resistance and capacitance. In this c ase, the parallel input capacitance will act as an attenuation factor to the sensor, as derived in A ppendix C. Combini ng these effects with E quation 2.3.2 derived in Section 2 .3.1 the expected output voltage given an input shear force becomes ( 3 35 )

PAGE 114

114 where and are the no minal device capacitances, are the device parasitics, is the input capacitance of the amplifier, is the bias voltage applied to the sensor, is the at tenuation due to the secondary gap between comb fingers, is the coupling coefficient, is the dimension of the primary gap, and is the deflection of the floating element due to an input shear stress. The circuit is broken up into three main blocks; modulation, demodulation, and demodulation control. The specifics of each block are discussed in Section s 3.8.1, 3.8.2, and 3.8.3. 3.8.1 Modulation The modulation block creates two out of phase sinusoids for biasing the sensor and provides the basis of the demodulation control signal. The details associated with the demodulation control are discussed in Section 3.8.3. Figure 3 31. A generalized schemat ic of the bias generation for modulation indicating the original sinusoid at the input and resulting in two out of phase sinusoids at each sensor bias node. In order to evaluate the system performance the intended functionali ty of the block and the noise c onsiderations of the block must be evaluated. The primary function of creating two out of phase sinusoids is achieved by two blocks ; one for inversion and one for buffering This nominally creates a phase shift between the two bias signals applied to the sensor such that and

PAGE 115

115 as shown in Figure 3 3 1 Applying these biases to the generalized sensor impedance bridge seen in Figure 3 33 the output voltage of the sensor is ( 3 36 ) Assuming that and this becomes ( 3 37 ) As the inverter and buffer may have sli ght phase offsets, the impact of phase error must be considered. To account for phase errors in bias generation the second bias becomes The resulting sensor output is ( 3 38 ) Simplifying and assuming that is very small E quation 3.37 becomes ( 3 39 ) showing that while the sensitivity of the device is not affected a dc offset is generated. Figure 3 3 2 The circuit representation of the sensor for an analysis of the errors associated with the modulation block.

PAGE 116

116 The addition of a variable resistor in the inverting amplifier driving Sensor Bias 2 allows for some compensation for dc signals generated by non ideal sensor impedances. Consider and in Figure 3 3 2 E quation 3.36 becomes ( 3 40 ) This shows a dc offset term generated by the impedance mismatch along with a slight attenuation in device sensitivity. If the bias is chang ed such that and equation 3.39 is now ( 3 41 ) or ( 3 42 ) Comparing this result to E q uation 3.36, where the capacitances are balanced, the nominal sensitivity is produced without additional dc offset. The danger of having this adjustability available to the end user of the instrument is that changing this gain beyond this nominal point re sults in a change in device sensitivity. Ideally this gain value will be selected during calibration and then set for the lifetime of the sensor system. As the circuit topology fits the needs of the system, the implementation of this topology will decid e the ultimate system performance, specifically the noise contributions of this design. There are three noise sources in the modulation portion of the circuit; noise associated with the bias sinusoid, noise associated with the buffering block, and noise

PAGE 117

117 associated with the inverting block. The noise associated with the bias sinusoid is negligible as it is a common mode signal to the output of the capacitive bridge. The noise of the inverting and buffering blocks is uncorrelated and will combine at the o utput of the sensor. The noise due to circuitry at the output of the sensor is ( 3 43 ) 3.8.2 Demodulation For the purposes of this work, the demodulation block contains the signal path from the output of the sensor to the read out of the base band signal. This includes signal conditioning pre demodulation and the demodulation i tself. Figure 3 3 3 A block diagram of the d emodulation portion of the Synch MOD/DMOD system with sub sections indicated in dashed boxes The chosen demodulation technique i s envelope detection that is realized using an act ive rectifier [72] For simplicity, the demodulat ion block as a whole is split into separate sections; signal conditioning before rectification, rectification, and signal conditioning after rectification. Then the noise model of each section is outlined and combined for a total noise model of the demodu lation block. A high level block diagram

PAGE 118

118 of the demodulati on circuitry is shown in Figure 3 3 3 with indications of the separation between the operational sections. 3.8.2.1 Signal c onditioning b efore r ectification As the sensor is a high impedance device immediate impedance buffering is critical to prevent electromagnetic interference and signal attenuation. A unity gain amplifier, discussed in 3.4.1, is implemented and co located with the sensor die. The rest of the demodulation block is then located on a PCB away from the testing area. The incoming signal is ac coupled onto the board and then band pass filtered with the pass band centered at the carrier frequency. The unity gain amplifier and band pass filter make up the signal conditioning before rec tification block. The band pass filter is realized using a low pass filter and high pass filter in series. The details of the filters result from the selection of bias frequency, however generally the low pass filter needs to be of sufficiently high orde r to filter out the second harmonic of the bias frequency and the high pass filter is of lower order as it is meant to filter out dc offsets or noise associated with electromagnetic interference from speakers, fan drivers, or other wind tunnel related sour ces. A generalized block diagram of th is block is shown in Figure 3 3 4 In this case the low pass filter portion of the band pa ss filter is shown as the first. The high pass filter portion could also come first. The implications of this choice will be explained in Section s 3.8.4 and 3.8.5. There are three sources of noise associated with this block; the noise from the unity gain amplifier, the noise from the low pass filter, and the noise from the high pass filter. There is also the opportunity to add gain to the system at each of the filter blocks, that are represented as and The implementation of the filter stages will set the

PAGE 119

119 noise contributions, for simplicity they will be assumed to be volta ge noise dominated and are represented by and for the low pass and high pass portions, respectively. The noise at the input to the rectification is ( 3 44 ) From this it is seen that t he initial gain stage of the demodulation has the greatest impact on the overall signal to nose ratio of this stage as it is further amplified by the second gain stage, and changes the magnitude of the noise contributed by the modulation section, the buffer, and the first filter stage Figure 3 3 4 The block diagram of the signal conditioning before rectification block demonstrating the construction of a band pass filter through the series combination of a low pass filter and a high pass filter 3.8.2. 2 Rectification Rectification is achieved by switching between two out of phase versions of the filtered sensor output. The switching is synchronized to one of the bias signals T he implementation of this synchron ization is discussed in 3.8.2.3 that preserves the phase of the original flow information. Two out of phase versions of the source signal are generated using inverter and buffer blocks, like those used in Section 3.8.1 as shown in Figure 3 3 5 The rectification is of the signal is perfo r med by an analog double pole single th row switch This switch based demodulation i s explained in Section 3.7.2.

PAGE 120

120 This frequency translation works in two ways; it demodulates the high frequency sensor data back down to the baseband and additionally is up converts the low frequency noise of th e system to the modulation frequency. Up until this point the low frequency noise contributions have been neglected in the analysis of noise due to this effect The noise of the inverter block, buffer block, and switch will be subject to this but all sta ges from the output of the switch on will have low frequency noise contributions. The noise associated with the inverter block is higher than the noise of the buffer block, as they use the same base amplifier, so for simplicity the noise of the inverting channel will be considered as the noise added by the buffer and inverter blocks. The noise at the output of the switch is ( 3 45 ) where is the voltage noise of the inverter block and is the voltage noise of the switch. Ideally the control signal is completely decoupled from the switch signal path, so any noise on the demodulation control signal is not considered in the final noise formulation. This assumption will be re evaluated when the real switch is selected as part of Section s 3.9 and 3.10 The derivation of the control signal is described in Section 3.8 .2 .3. Figure 3 35. The block diagram of the rectification block including a phase inversion stage and a DPST switch

PAGE 121

121 While the noise of the switch is fairly straight forward it is not the sole driver for switch selection The dominant non ideality in a switch is the non zero switching time, meaning the period between the triggering of the switch and the switch being fully conducting or non conducting. There are two metrics associated with this effect; the time it takes for the switch to turn on, and the time it takes for the switch to turn off, Each of these are defined as the delay between the logic input reaching of the maximum logic voltage and the output voltage of the switch reaching of the maximum output voltage on that switch [73] This timing is demonstrated in Figure 3 3 6 Figure 3 3 6 An illustration of switch timing showing the various time scales used as metrics for s witch selection These timing considerations impact switch choice more profoundly than the noise of the switch. In the active envelope detector the switch will change states at two times the bias frequency. If the combined switch transition times approac h the total time the switch needs to be on then the rectified signal is attenuated by the switch.

PAGE 122

122 In general, t his switching time is dependent on the size of the transistor used to implement the switch and the load on the output of the switch. The larger the transistor used as the switch path, the larger the capacitance associated with the transistor, and the longer this transition period is. At the same time, the resistance of the switch is inversely proportional to transistor size. With these competin g requirements there are trade offs between bias frequency selection and the noise contribution of the switch. Ultimately, order of magnitude of the switch noise is not a dominant source of noise in the system. 3.8.2.3 Demodulat ion c ontrol The demodul ation control block provides a transistor transistor logic (TTL) signal to the switch that rectifies the incoming sensor signal. This TTL signal is derived from one of the sensor bias signals in order to simplify the synchronization between modulation and demodulation. This signal derivation is broken into three blocks; a buffer, a regulator to step down the voltage, and an inverte r. This is shown in Figure 3 3 7 The first buffering stage is to decouple the bias signal from the conversion to a TTL level signal, preventing feedback into the sensor bias. The regulator stage then steps the bias signal down by clipping it into a TTL square wave. Finally the square wave is buffered by a logic inverter to drive the rectification switch Figure 3 3 7 A block diagram representation of the demodulation control circuitry. Following rectification, the signal passes through one additional circuit section in order to reclaim the baseband flow information.

PAGE 123

123 3.8.2. 4 Signal c onditioning a f ter r ectification After rectification the signal is low pass filtered to complete the demodulation The order of this filter is dependent on the difference between the sensor bandwidth and choice of bias frequency. The noise characteristics of this port ion of the circuit are dependent solely on the component chosen to implement the low pass filter. The noise at the output of this stage is ( 3 46 ) where is the voltage noise associated with the low pass filter implementation. This concludes the noise added by the direct signal path and now the to tal noise model is completed. 3.8 Generalized Noise Model The final noise model of the generalized system is broken into two components, the noise from the modulation and the noise from the demodulation. These are expressed as ( 3 47 ) and ( 3 48 ) respectively. As the sensor is differential, noise sources that are common to both bias signals are rejected The remaining noise is fed through in to the demodulation and is represented as There is no differentiation in the demodulation stages, so the power of each noise source feeds through to the output. Assuming that each stage has a noise contribution of equal order the dominant sources are those that are multiplied by the most gain, being the noise of the buffer amplifier that follows the sensor and the

PAGE 124

124 noise of the first filter stage. Though this filter is identified as the low pass filter stage in this equation, recall that the order of the low pass and high pass stages that make up the band pass filter is not important and they may be switched in order to minimize total noise based on the final parts chosen for implementation. The synch MOD/DMOD system was real ized in two stages. Initially the synch MOD/DMOD system is constructed alone as a proof of concept. Bench top power supplies and function generators are used for the various required bias voltages. Finally the synch MOD/DMOD system is realized with the majority of these external sources built in so only a single power supply is required for system support. The proof of concept construction and final system are described in Section s 3.9 and 3.10, respectively. 3.9 First Generation Synch MOD/DMOD Initially the system is constructed on a single printed circuit board (PCB) requiring a dual voltage bench top power supply and bench top function generator to run. The bias frequency is set at that is more than a decade above the sens or resonance of but still low enough to be monitored on spectrum analyzers and oscilloscopes available in the laboratory. The circuitry is again broken into multiple subsections; modulation, demodulation, rectification, and rect ification control. Each subsection is described in detail before a final parts list and conclusions are presented. 3.9.1 Modulation The sensor bias circuit consists of an external sinusoidal generator, two phase shift circ uits, a buffer, and an inverter configured as shown in Figure 3 38 The buffer and inverter portions of the circuit provide the phase shift between the two bias

PAGE 125

125 signals. Realistically the phase between the buffer and inverter blocks will not be exactly The phase adjust circuitry was used to compensate for this small offset, however unmatched cabling and impedance mismatches in the sensor generated during fabrication will also contribute in the same manner. The phase adjust circuitry is only used to g iv e the best case signal at the Synch MOD/DMOD circuit board output. In order to characterize the noise performance of the modulation block a noise model for each component is derived and then cascaded. The equivalent noise circuit and output referred nois e for a buffer is explained in 3.4.1. This section provide s equivalent noise circuits and analysis for the phase adjust and inverter components and provide an expression for th e noise of the entire block. Figure 3 38 A sche matic of the modulation portion of the Synch MOD/DMOD system showing the phase adjustability and gain control to eliminate offset in the sensor output Following the analysis outlined in 3.4.1, the noise circuit of an inverting a mplifier is shown in F igure 3 3 9 The resulting output referred noise is

PAGE 126

1 26 ( 3 49 ) The analysis of the phase adjust block is complicated by the differential topology of the circuit. Instead of lumping the amplifier voltage and current noise sources the differential inputs must each have their own associated noise network. In this case, and are associated with the invert ing input to the amplifier while and are associated with the non inverting input. They are related to the generalized noise mo del [46] as ( 3 50 ) and ( 3 51 ) Figure 3 3 9 Equivalent noise circuit of an inverting amplifier including the input referred noise of the amplifier as well as thermal noise sources associated with resistances The full noise circuit, including this differential noise source approach, is shown in Figure 3 40 The output referred noise in this configuration is ( 3 52 ) where

PAGE 127

127 ( 3 53 ) and ( 3 54 ) The noise added by the function generator is not considered in this model as it is not a designed portion of the Synch MOD/DMOD system. Additionally, as it is a source to two paths that are then differe nced, it is considered a common mode source. The final output due to noise at the function generator is a function of the gain stage of the modulation circuit and the sensor imbalance. Assuming a perfectly matched sensor the output noise due to function generator non idealities is zero. Figure 3 40 Equivalent noise circuit of a phase adjust block where the amplifier noise is represented by differential input current and voltage sources The total noise model of the modulatio n block is the summation of uncorrelated noise sources due to each component of the modulation block The full circuit, with labeled co mponents, is shown in Figure 3 4 1 The voltage is the cascade of a phase adjust block with a voltage inverter with gain and is expressed as

PAGE 128

128 ( 3 55 ) The voltage is the cascade of a voltage buffer with a phase adjust block and is ( 3 56 ) where ( 3 57 ) and ( 3 58 ) These two noise models will the propagated through to the sensor output to give ( 3 59 )

PAGE 129

129 Figure 3 41. Modulation circuit with labeled components for use in noise analysis. For the purposes of this chapter inherent transducer noise is neglected. This equivalent noise model for the output of the sensor is used as an input noise signal for the demodulation sections. 3.9.2 Demodu lation Again, the demodulation block is broken down into several smaller blocks; signal conditioning before rectification, rectification, rectification control, and signal conditioning after rectification. Each section is described individually in the fo llowing sections. 3.9.2.1 Signal c onditioning b efore r ectification For this proof of concept implementation, the demodulation block is constructed as outlined in Section 3.8, meaning that before modulation the band pass filter is constructed by cascading a low pass filter with a high pass filter. The band pass filter is

PAGE 130

130 realized by using two different analog filters, a single pole high pass filter and a fourth order low pass Chebyshev filter. The justification for the imbalance of the two halves of the f ilter lies in the predicted harmonic content of the system. The bandwidth of the high pass filter slightly exceeds the sensor bandwidth to ensure that the entirety of the sen sor output signal is within the flat band region of the filter. A detailed block diagram of this block is shown in Figure 3 4 2 Below the carrier frequency spurious frequencies are generated primarily by electromagnetic interference, whether that be 60Hz line noise, a mechanical fan in a wind tunnel, or any other power based low freque ncy source. As the carrier is ideally in the hundreds of kilohertz or higher the frequency separation is significant, relaxing the requirements on the filter order of this stage. The low pass portion of the band pass filter has significantly more stringe nt requirements. Figure 3 4 2 Detailed drawing of the signal conditioning path before rectification in the demodulation block. Any nonlinearities in the modulation frequency or higher order mixing products will appear abov e the carrier frequency, starting at the second multiple of the carrier

PAGE 131

131 frequency. The higher order low pass filter ensures that regardless of the harmonic content of the oscillator chosen as a modulation signal, the harmonics will be sufficiently rejecte d before demodulation. The chosen component, the LT1563 by Linear Technologies, was selected as due to its configurability and low noise floor It also allows for the addition of gain by a single resistor selection. Adding gain immediately after the sig nal is read in will increase the overall signal to noise ratio of the system by making the noise to this point dominant over the other noise sources in the demodulation signal path. This concept is seen by examining the noise characteristics of this demod ulation block section In this case, there are three sections that make up this block; a unity gain amplifier, a low pass filter, and a high pass filter. These are shown in Figure 3 4 3 along with component labels. Figure 3 4 3 The demodulation before rectification block with components labeled for noise analysis The noise contributions of a unity gain amplifier are fully described in Section 3.4.1. The noise contribution due to the unity gain amplifier is repeated here for

PAGE 132

132 s implicity. The input parasitics of the amplifier are considered though they are not shown in 3 27. The noise at the output of the unity gain amplifier block is ( 3 60 ) The noise of the low pass filter block is largely dependent on the filter implementation. As described in Section 3.8.2.1 the chosen component is an LT1563 by Linear Technologies. It has a specified voltage gain, G, and input voltage noise, given by the manufacturer datasheet. Considering the addition of the noise in the system from previous sources and the filter gain the noise at node is ( 3 61 ) The final portion of th is section is the single pole high pass filter. The noise of this filter has four components; the thermal noise of the feedback resistance, the thermal noise of the resistance at the inverting input to the amplifier, the amplifier voltage noise, and the a mplifier current noise. The total noise added by the high pass filter block is ( 3 62 ) The total noise up to this point in the system is ( 3 63 )

PAGE 133

133 3.9.2.2 Rectification Signal rectification is achieved by using a single pole double throw (SPDT) solid state switch that alternates between the filtered signal and an inverted version of the filtered signal. The details of the switch control will be discussed in Section 3.8 .2 .3, for the purposes of this section assume that the switch control is a 50% duty cycle square wave that is phase locked to Sensor Bias 1. A schematic of this section of the demodulation block is shown in Figure 3 44 Figure 3 44. A detailed drawing of the rectification portion of the demodulation block. Following the initial signal conditioning section the signal is fed into a unity gain buffer, creating the signal that will be passed through the rectifier during the positive portion of the demodulation control signal. The initial signal conditioning section also feeds into an inverter followed by a unity gain buffer, creating the signal that will be passed through the rectifier during the negativ e portion of the demodulation control signal. The resulting output is a rectified version of the input signal where the rectification direction, whether the signal is rectified in the positive direction or negative

PAGE 134

134 direction, depends on the phase relation ship between the input signal and the demodulation control. In this case, the signal is split into two pathways with different noise characteristics. The worst case for noise is the inverting signal path so that will be considered the sole signal path f or the purposes of analysis for simplicity. This means that noise contributions due to A7, shown in Figure 3 4 5 will be neglected, assuming it is implemented using the same components as A9. The total noise from this rectification portion is subdivided i nto three noise sources; noise due to the inverting amplifier implemented with A8, the noise due to the buffer amplifier A9, and noise associated with the switch. Figure 3 45. The rectification portion of the demodulation circ uit with the components labeled for noise analysis. The noise associated with the inverting amplifier is a combination of the inherent noise of the op amp, A8, and the thermal noise of the two resistors. The noise at the output of the inverting amplifier is

PAGE 135

135 ( 3 64 ) The noise contributions of the buffer amplifier, A9, have a lready been outlined making the noise at the input to the rectifying switch ( 3 65 ) The noise associated with the switch is significantly more complicated as it requires knowledge of both the way the switch is implemented and the effect of switching on noise characteristics. The switch is implemented using CMOS for maximum isolation of the drive signal from the sensor signal path. In order to achieve switching of both negative and positive voltages a CMOS switch, also called a transmission gate, is used [72] Transmission gates are typically used in sample and hold circuits or switched capacitor filters and are implement ed by parallel nMOS and pMOS tra nsistors as shown in Figure 3 46 Figure 3 4 6 The c ircuit schematic of a transmission gate showing the parallel nMOS and pMOS transistors The noise of a MOSFET is made up of two components, a low frequency noise component and a thermal noise floor. This is expressed as an input referred noise for the FETs use as an amplifier component and ( 3 66 )

PAGE 136

136 where is the FET transconductance, is a property of the gate oxide, and describe the physical gate size, and is the oxide capacitance [74] In this case the flat band noise of the switch is the contributing term, so the noise at the output of the switch is ( 3 67 ) Any noise contributions present in the drive signal are significantly attenuated due to the MOS implementatio n of the switch, however they are described for completeness. 3.9.2.3 Rectification c ontrol A detailed diagram of the rectification control circuitry is shown in Figure 3 4 7 Functionally, Sensor Bias 1 is pulled from the modulation block and fed throu gh a unity gain buffer, creating an isolated version of this sinusoid to generate the TTL control signal. This buffered signal then passes through a phase adjustment circuit allowing for user control of the rectification. The phase shifted sinusoid is th e input into a comparator, creating a 10V/ 10V square wave. The comparator output is then tied to a Zener regulator that regulates these voltages down to 0V and 5V. Functionally, when the sinusoid is negative, the combination of comparator and Zener regu lator outputs 0V, when it is positive it outputs 5V. This ideally creates a 50% duty cycle square wave. Finally, the square wave is fed th rough a standard logic inverter. The logic inverter provides an additional level of noise rejection, as the input t o the inverter acts as a switch control, where the switch selects between the 5V rail and the ground of the system rather t han using the derived signal directly trigger the demodulation switch.

PAGE 137

137 Figure 3 4 7 The demodulation co ntrol block. The rectified signal that is produced by this control and the circuitry described in the previous section passes into a final signal conditioning block in order to reclaim the baseband flow information. This final rectification block is descr ibed in the next section. 3.9.2.4 Signal c onditioning a fter r ectification As described in 3.8.2.4 in order to reclaim the baseband information the rectified signal is low pass filtered. The chosen filter is an LTC1563 configured for a cutoff frequency of This sets the total available sensor system bandwidth for this implementation but is extendable by changing the supporting resistor values The LTC1563 is chosen as the cutoff frequency is determined by a single resistor, so it is adjustable without reconfiguring multiple components or layout after it is implemented. The LTC1563 has low dc offset and when configured as a fourth order low pass filter has pass band ripple, making it ideal for baseba nd applications. The noise contributed by this portion of circuitry is the noise of low pass filter. No gain is added at this point, as it would provide no benefit in terms of signal to noise ratio. The schematic of the low pass filter is shown in Figur e 3 48 Combined with the previous sections, a full schematic, parts list, and noise model is constructed and is shown in A ppendix E.

PAGE 138

138 Figure 3 4 8 A schematic of the final low pass filter in the Synch MOD/DMOD system. 3.9.3 S ummary of the First Generation Synch MOD/DMOD Following the first generation circuitry fabrication the system is characterized. In order to see the impact of noise sources in the modulation portion of the synch MOD/DMOD system, the noise floor of the syst em is characterized with a sensor attached. The noi se floor is shown in Figure 3 49 There is a clear low frequency component, that is dominated by the final low pass filter stage. The overall noise floor is relatively high. In comparing the resulting noise characteristics to the noise model constructed in Section 3.8.3, implementing the models for the specific construction in 3.9.1 3.9.2, the dominant source is associated with the band pass filter stage of the demodulation. The low pass stage of the f ilter block is of higher order and therefore has higher noise than the high pass filter stage. By altering the order of these filters and adding gain at the lower noise high pass stage, the overall noise floor is lowered easily.

PAGE 139

139 F igure 3 49 The measure d noise floor of the first generation Synch MOD/DMOD. Otherwise the overall approach proved feasible and further integration in order to lower the noise floor and remove the dependence on other lab equipment can move into a second generation Synch MOD/DMOD design. 3.10 Second Generation Synch MOD/DMOD The second generation aims to include an on board oscillator, power management circuitry, and mitigate some of the noise issues seen in the first generation In addition to these changes, the bias frequency is shifted to This bias frequency moves the sensor signal into the lower noise flat band portion of the immediate interface amplifier. The original 100 kHz bias frequency was only chosen in order to aid in the development in the system, as most of the diagnostic equipment available in a standard fluid dynamics laboratory does not extend into the MHz frequency range. As the overall synch MOD/DMOD topology has been demonstrated the same diagnostic capability is

PAGE 140

140 not required. The design changes to the Synch MOD/DMOD in this second generation are outlined by section. 3.10.1 Modulation There are two changes to the modulation portion of the Synch MOD/DMOD system in this generation; the addition of an on board oscillator and the s implification of the bias signal generation. 3.10.1.1 Oscillator d esign In order to reduce reliance on bench top equipment, an on board oscillator is designed. In designing an oscillator there are two main considerations; phase noise and harmonic genera tion. In both cases the quantities are to be minimized and are reliant on the overall Q of the oscillator. The frequency in the first generation was restricted by the availability of diagnostic equipment in the laboratory. As the topology has been prove n viable, t he bias frequency is increased. Figure 3 50. A circuit schematic of the Colpitts oscillator.

PAGE 141

141 To reduce the requirements on the required in package bias resistor, the bias frequency is increased by an order of mag nitude to A Colpitts oscillator is chosen due to preferential phase noise performance and ease of implementation [68] The full oscillato r circuit is shown in Figure 3 50 The oscillator is comprised of two sections of circuitry; the bias circuitry and the tan k circuit. The bias circuitry, consisting of and set the large signal transconductance, and small signal transconductance, of the transistor. The tank circuit, consisting of and sets the oscillation frequency of the circuit. The bias circuitry is co nfigured such that when a dc bias voltage is applied the collector current moving through the 2N222 bipolar junction transistor (BJT) is The small signal transconductance, of the BJT is set by the threshold voltage of the amplifier and the collector current as ( 3 68 ) where is the dc collector current and is the thermal voltage and is approximately at room temperature. The large signal transconductance, is also set by the bias conditions and is ( 3 69 ) where is the dc base voltage. The base voltage is set by the voltage divider between resistances and as ( 3 70 )

PAGE 142

142 The collector current is set by the selection of the 2N222 BJT, that has a base to collector voltage of This sets the collector current as ( 3 71 ) The first concern in oscillator design is oscillator start up. Oscillators work on the premise that the noise of the system is gained and filtered into a sinusoid by the transistor and tank circuit. In order for the noise to be amplified at start up, the overall loop gain o f the circuit must be greater than one. To achieve this, the small signal transconductance is set to set to satisfy [75] ( 3 72 ) The BJT is replaced by a large signal transistor model as shown in Figure 3 50. Figure 3 51. Simplified model of the Coliptts oscillator shown as A) a small signal model and B) a parallel RLC circuit.

PAGE 143

143 In analyzing the simplified model in Figure 3 51 the oscillation frequency and amplitude are found. The frequency of the oscillator is determined largely by the inductor and capacitive divider and is ( 3 73 ) The amplitude of oscillations is expressed as ( 3 74 ) This approximation relies on the assumption that the Q of each component is high. It is important to note that while this equation indicates that increasing the tank res istance will improve the oscillator performance by increasing the output voltage, the tank resistance is also a driving factor of the oscillator Q. This means that if the tank resistance is high, the overall Q of the oscillator is low, and the oscillator performance is degraded. The oscillator is simulated using PSPICE in order to verify that oscillations will start up and to predict the order of magnitude of the oscillator output. With the component values listed in Appendix F the oscillation start up t ime is approximately the frequency and amplitude of the resulting sinusoid are and respectively. In order to more carefully control the bias amplitude, an op amp based gain stage is cascaded with the oscillator. The addition of a gain stage with a trimming resistor allows for the bias voltage to be set at calibration. A coupling capacitor is put at the

PAGE 144

144 output of the oscillator in order to remove the dc offset that is i nherent in the oscillator output The total oscillator block is shown in Figure 3 5 2 Figure 3 5 2 A schematic of the total oscillator circuit including the amplification of the bias signal for increased bias voltages 3.10.1 .2 Bias g eneration In the first generation bias generation was implemented with a buffer, inverter, and phase adjust circuitry. As the system is ultimately calibrated the addition of the phase adjust circuitry is an aspect that is overdesigned. The phase errors in the bias signal generation will alter the system sensitivity H owever, as shown in 3.8.1 th e gain on the bias signals alters the sensitivity more significantly. In the second generation the gain adjust is maintained but the phase adjust portio n is removed. The phase adjust circuitry was only as useful as the packaging is perfect. The mismatch in cable lengths leading to the sensor along with path lengths of leads to the die all contribute to additional phase offsets, that were not accounted f or in the original implementation of the bias circuitry

PAGE 145

145 Figure 3 5 3 A schematic of the modulation circuitry for the second generation of the Synch MOD/DMOD circuit. This simplified diagram for bias generation, including the C olpitts oscillator and associated gain stage, is shown in Figure 3 5 3 With the change in bias frequency the GBWP of the amplifiers chosen for the modulation circuitry must be considered. In the case of amplifier A1 the largest feasible gain is +10 as th e output of the oscillator is expected to be on the order of 1 V. The GBWP of the amplifier A1 must exceed 10 MHz in order to guarantee that the output signal is not distorted. This change in bias frequency will have a larger impact on the demodulation p ortion of the circuitry. 3.10.2 Demodulation To accommodate the bias frequency the first two sections of the demodulation circuitry; the input band pass filter and the demodulation switch, must change significantly. In addition to the new bias frequency the input filter stage is altered in

PAGE 146

146 order to reduce the overall noise floor of the system, as outlined in 3.9.3. Again, the demodulation block is broken down into several smaller blocks; signal conditioning before rectification, rectification, rectifica tion control, and signal conditioning after rectification. Each section is described individually in the following sections. 3.10.2.1 Signal c onditioning b efore r ectification The first stage of the demodulation circuitry is still a band pass filter, howe ver the order of the low pass and high pass stages has been reversed with respect to the first generation. Immediately following the in package buffer amplifier is a single pole high pass filter with gain adjustability. The corner frequency is increased to that is still a decade down from the bias frequency. The low pass compone nt is constructed using a fifth order elliptic filter in the LT1560 from Linear Technologies. The change in filter components also reduced the compl exity of the circuit board layout, as the LT1560 is pre programmed for a bandwidth of and does not require external components. Additionally, the rms noise of the LT1560 is a factor of two lower than the LT1563 from the first g eneration A schematic of this new circuitr y is shown in F igure 3 5 4 Following this band pass filter stage the signal is again fed into an active rectifier. Figure 3 5 4 A schematic of the signal conditioning before rectifi cation block in the second generation Synch MOD/DMOD.

PAGE 147

147 3.10.2.2 Rectification Figure 3 55. A schematic of the rectification block of the second generation Synch MOD/DMOD system As with the band pass stage, the active rectifie r components also need to be chosen to accommodate the bias frequency. The signal is split into two paths, one that is inverted and one that is simply buffered. As there is no gain in either path, the GBWP of the amplifiers simply needs to exceed The switch that performs the rectification has more stringent requirements in this generation, as the on time for each switch path is reduced from to that is on the order of some low resistance switc h transition times. A DG419L high speed SPD T switch is used to rectify the signal. Additionally, a buffer is added between the inverting channel and the switch so that each switch path loads the switch equally and the switching time is nominally symmetri c. The demodulation control signal is also re evaluated for higher frequency performance.

PAGE 148

148 3.10.2.3 Demodulation c ontrol The rectification control for this generation is identical in topology to the control in the first generation however the implementa tion is changed in order to meet the timing requirements of the higher bias frequency. The topology is shown in Figure 3 56 Figure 3 56 A schematic of the rectification control block. The buffer, phase adjust, and comparator must all have GBWP greater than The component that is change between the first and second generation of the Synch MOD/DMOD circuitry is the inverter, shown in Figure 3 46 as A13. The low output capacitance and high speed performance of the SN74AHCT1G14 make it appropriate for the second generation The rectified signal that is produced by this control and the circuitry described in the previous section passes into a final signal conditioning block in order to reclaim the baseband flow information. This final block is describe d in the next section. 3.10.2. 4 Signal c onditioning a fter r ectification As described in 3.8.2.4 in order to reclaim the baseband information the rectified signal is low pass filtered. The chosen filter is again the LTC1563 and is configured for a cutoff frequency of The cutoff frequency is changed with a single resistor to accommodate larger bandwidth designs.

PAGE 149

149 3.10. 3 Integrated Power Management There are four different voltage potentials required in the system, and These voltages are derived from a single ac adapter with a output. Three active voltage regulators derive the additional required potentials. The outpu t of the ac adapter is used to source the regulators that create the and potentials. The created rail then goes on to source the potential. The rail is created using several LTC1144 switched capacitor voltage inverters from Linear Technology. This switched capacitor topology is chosen for ease of implementation and lack of external inductors. Limitations on the o utput current require that several of these converters be used in parallel to source enough current to supply the electronics operating with a potential as well as the regulator to crate the potential and source the electronics on it. The and potentials are created using the LM7905C and LM7805 linear voltage regulators, respectively. These linear regulators source the entire demodulation chain rather than the switching supplies in order to prevent the feed through of power supply noise into the ultimate sensor system output. Combining the circuitry described in 3.10.1 through 3.10.3 the second generation of the synch MOD/DMOD system is constru cted. The performance of this new generation is compared to the first generation in order to verify that the overall noise has been reduced.

PAGE 150

150 3.10.4 Summary of the Second Generation Synch MOD/DMOD Following the second generation circuitry fabrication the system is characterized. In order to see the impact of noise sources in the modulation portion of the synch MOD/DMOD system, the noise floor of the system is characterized with a sensor attached. The noise floor is shown in Figure 3 5 7 Figure 3 5 7 The measured noise floor of the second generation Synch MOD/DMOD system compared to the noise floor of the first generation. As seen in 3.9.3 there is again a clear low frequency component that is dominated by the final low pass filter stage however in the flat band region the overall noise level is reduced from 20 nV at 1 kHz in the first generation to 0.01nV at 1 kHz in the second generation due to the alteration in overall topology. A large peak is present at approximately 4kHz. This is a switching fre quency associated with the power regulation circuitry. Recommendations for eliminating this peak are given in C hapter 7. The integration of the oscillator and power distribution allows for the circuitry to be packaged into a form factor becoming of a piec e of laboratory equipment. It is encased

PAGE 151

151 in an aluminum box approximately with external BNC connectors to support the sensor as shown in Figure 3 5 8 While the system in its entirety is described within this section the porti on of interface circuitry that is used to define the sensor performance during the device optimization. (A) (B) Figure 3 5 8 A photograph of A) the Sync h MOD/DMOD system with a pen as a reference of the final size and B) the internal circuitry 3.11 Summary In this chapter the technical challenges of interfacing with a capacitive transducer in order to make a measurement of mean and dynamic capacitance change are outlined. A synchronous modulation/demodulation scheme is chosen and implemented in two generations reducing the noise floor by two orders of magnitude in one generation of development An additional advantage to the synchronous modulation/demodulation design shown in Section 3.8 is that only the immediate voltage follower, that is co loca ted with the sensor, directly impacts the transducer. The noise characteristics of the subsequent demodulation stage will impact the overall signal to noise ratio of the system, but is adjustable as new technology comes onto the market.

PAGE 152

152 The immediate in terface with the transducer is included in the optimization problem formulation, as the parasitics and noise characteristics will impact the optimization objective function. Specifically, the noise characteristics of this amplifier, evaluated at the bias frequency, will be used to calculate the minimum detectable shear stress. T he AD8022 manufactured by Analog Devices is chosen for its low input capacitance noise characteristics as outlined in Section 3.4.3

PAGE 153

153 CHAPTER 4 OPTIMIZATION In this chapter, a formal optimization problem is constructed in order to achieve the best possible de signs for the physical geometry of the shear stress sensor given the application of fundamental turbulence measurements in a low speed wind tunnel facility The optimization uses th e minimum detectable signal as an objective function, while fabrication, a pplication, and design based constraints are imposed The models and constraints have been expanded in order to provide a quantification and optimization of rejection to an input pressure signal to the sensor. In this chapter, the goals of sensor performa nce are outlined and translated into an optimization objective with constraints. Several design spaces are generated, studied, and the final designs for fabrication are determined. 4.1 System Level Optimization Objectives Using a built in MATLAB function, fmi ncon sequential quadratic programming minimizes the objective function, that is minimum detectable shear stress. Sequential quadratic programming uses a direction seeking algorithm to minimize or maximize a given function. The chosen function, fmincon uses the Lagrangian formed using the objective and constraint functions [76] The benefits of this local optimizatio n implementation are convergence speed and accuracy. Multiple initialization points will be chosen in order to ensure that a global optimum has been reached. There are two overall goals for this optimization; a minimization of minimum detectable shear str ess and a maximization separation of the operational spaces for sensing pressure and shear. Instead of formulating a multi objective optimization, a single objective optimization is used, with the secondary goal of pressure mitigation

PAGE 154

154 implemented as a con straint. The response of the sensor to a pressure input is mitigated in two ways; by altering the frequency response function of the sensor due to a pressure input to effectively filter out the response to pressure in the bandwidth of its operation as a s hear stress sensor, or to increase the minimum detectable pressure above the levels expected given the application of turbulent boundary layer measurements. This separation of design spaces is visualized in Figure 4 1. Figur e 4 1 A visualization of the operating space for the sensor. The primary goal of the optimization is to minimize the minimum detectable shear stress. Minimum detectable signal is defined as ( 4 1 )

PAGE 155

155 where is the voltage noise described in 3.8.2 given by ( 4 2 ) and is the total sensitivity to a shear stress input given by ( 4 3 ) that is derived from E quation 3 33. As Chandrasekharan et al. did not implement a synch MOD/DMOD scheme the noise characteristics used in the initial optimization were based on low frequency amplifier performance In this generation the synch MOD/DMOD bias frequency will set the point where the noise of the amplifier will be considere d. This is advantage ous as noise is avoided. Given an AD8022 buffer amplifier, manufactured by Analog Devices, and a bias frequency of the voltage noise is and the current noise is [48] As the noise of the synch M OD/DMOD system is a fixed quantity and does not impact the mechanical design of the sensor it will not be included in the optimization for simplicity, though it does impact the overall minimum detectable signal of the system. This impact is evaluated befo re designs are chosen in order to verify that the output of the sensor is above the overall noise floor of the electronics. In order to achieve the secondary goal of separating the shear and pressure operating spaces a constraint is placed on the ratio of element displacement due to shear and the displaceme nt due to the expected pressure This estimate of pressure rejection is an underestimation of the total rejection of the pressure signal as it neglects the common mode signal rejection that is due to th e device symmetry. If the initial capacitances were perfectly matched, any input pressure signal would result in zero

PAGE 156

156 output signal. The mismatch that is created due to process variation induces an output voltage per input pressure. Estimating using the displacements rather than an estimated mismatch may limit the design space overall, but is a more conservative design technique. In previous generations [29] the mechanical ratio was of tether width to tether thickness. Considering a mismatch of approximately the measured pressure rejection was This data will serve as a check on the optimization results and a metric quantifying the efficacy of the holes is developed This constraint will be changed and the optimization re run in order to determine the maximum achievable pressure rejection. 4.2 Optimization Constraints In order to define the design space for the optimization, there are several constraints that are implemented. Some of the constraints are fabrication based, such as the design variables described in Section 4.2.5, some are applic ation specific, such as bandwidth in 4.2.1 and linearity in 4.2.3, and some are required to ensure proper operation of the transducer, such as pressure rejection in 4.2.2 and pull in voltage in 4.2.4. This section will outline and describe all of the cons traints and motivate the necessity for each. 4.2.1 Bandwidth The bandwidth of the sensor in its operation as a shear stress sensor is determined by the sensor resonance. The bandwidth required for the sensor depends on the application where it will be used as d iscussed in Section 1. 2 .2. The sensor resonance and sensor size are related through the sensor mass and compliance, so placing a bandwidth constraint on the optimization will impact the design space. This will also affect the way that the pressure reject ion is evaluated.

PAGE 157

157 4.2.2 Pressure Rejection As explained in Section 2.2.2, the exact voltage output due to a pressure input is difficult to predict as it is dependent on process variation. In order to quantify the pressure rejection achieved by a given design th e ratio of in plane and out of plane displacements will be used as a metric. The displacement is linearly related to the output voltage in both sensor operation as a shear stress sensor and as a pressure sensor. In the case of a pressure sensor the actua l voltage generated by this displacement will be mitigated somewhat by common mode rejection, and in shear the output voltage will be doubled due to device symmetry. C omparing the displacements will be an underestimation of the total rejection of pressure signals from the desired shear stress signals but should still allow for a minimization The frequency where this constraint is evaluated will also impact i s efficacy in separating the operating spaces. Examining the full LEM circuit models, the press ure response has a zero formed by the lumped compliance of the cavity and lumped resista nce of the venting structures and a resonance formed by the compliance and mass of the floating element. The shear response has only a resonance formed by the complian ce and mass of the floa ting element. As the pressure resonance will be higher than the shear resonance due to the tether geometry and will have a cut on, as seen in Figure 4 2. The separation in operating spaces is exaggerated in order to show each frequ ency response function clearly. The separation between the response to a shear force and a pressure force is evaluated near the shear resonance, as that determines the bandwidth of the system. It is important to note that the choice of estimating the pres sure rejection at a frequency

PAGE 158

158 Figure 4 2. An exaggerated view of the frequency response functions of the shear and pressure LEMs in terms of displacement due to a unit input force. near resonance is not necessarily a good estimate of the ultimate vol tage output of the sensor due to a pressure input for two reasons First, e stimates of the frequency conten t of a turbulent boundary layer, specifically the Kolmogorov scales, provide more information at low frequencies [3] Secondly, as pressure is a common mode input to the differential capacitive bridge meaning that i n order to calculate an output voltage a mismatch in the bridge impedances is assumed. The implementation of this constraint is simply to minimize the response of the mechanical structure of the sensor to a pressure input. As the pressure model indicates there is a frequency roll on the magnitude of the response of the sensor structure to pressure will be greater at higher frequencies, so the mechanical displacement of the sensor due to a pressure input compared to the displacement of the sensor due to a shear input is evaluated at this

PAGE 159

159 relative maximum. This metric is understood to be an under estimation of the pressure rejection in terms of ultimate output voltage. 4.2.3 Mechanical Linearity As discussed in Section 2.1, the lumped element model assumes a smal l deflection. As the deflection becomes larger, it will no longer be a linear function of the input force. The static deflection will be constrained such that the maximum deflection is 3% less than the non linear deflection for a maximum input force. Ma thematically this is expressed as ( 4 4 ) where is described in Section 2.1 and is found using the Rayleigh Ritz method a s described in [77] and [37] work and is expressed as ( 4 5 ) 4.2.4 Pull In Voltage As capaci tive transduction is reciprocal the bias voltage must be constrain ed in order to ensure that the bias does not actuate the sensor. Specifically, the voltage providing the bias must not create a field so large the mechanical force that restores the floating element is overwhelmed, pulling the floating element to one side and short circuiting the sensor. For a differential capacitance scheme the dynamic pull in voltage is [78] ( 4 6 )

PAGE 160

160 where is the smallest ga p between two electrodes. For the sensor in this work the pull in voltage is ( 4 7 ) During optimization, the bias voltage will be constraine d to 85% of the magnitude under where pull in occurs. As the bias is required to have frequency content, the frequency of that bias voltage must also be determined. The constraint on this portion of the bias is simply that the frequency must avoid a structural resonance. Lumped element modeling only predicts the system behav ior up to the first resonance, and cannot be used to predict appropriate bias frequencies. Additional modeling such as finite element modeling, must be implemented in order to determine what frequencies are appropriate. As the frequency does not play a part in the determination of minimum detectable shear stress, and instead only allows for dc measurement, it is not an important parameter in the optimization of the mechanical structure and is left out of the optimization variables. 4.2.5 Summary of Constraints and Design Variables In addition to the constraints listed in Section s 4.2.1 through 4.2.4 the different geome tries are by traditional MEMS micromachining techniques. In total there are 1 1 design variables, their upper and lower bounds are s hown in T able 4 1. For clarity, the variables are indicated in Figure 4 3. Variables and are not included in the figure and represent the sensor bias voltage and number of holes perforating the sensor floating element respectively.

PAGE 161

161 Missing from the above table are the perforating hole diameter, width of the floating element, and the length of the floating element, Leaving the number and diameter of perforating holes caused the optimization to find multiple local minima and obfuscated the g lobal minimum. In order to constrain the problem and simplify fabrication the diameter of the holes is fixed at and the number of holes is left as an optimization variable. Figure 4 3. The physic al sensor structure with optimization labels identified. The dimensions of the floating element are dependent on the scaling analysis outlined in Section 1.1.3, that is justified by an empirical hotwire study [8] While there are significant differences between hotwires and floating element shear stress sensors there is no existing work studying the scal ing for floating element sensors in a turbulent boundary layer. The ho twire study is used here to provide a basis for design generation.

PAGE 162

162 Table 4 1 Design variables used in optimization. Bound Lower 5 100 10 45 5 4 3.5 3.5 10 Upper 25 1000 40 50 150 20 15 15 1000 4.2.6 Design Targets Four different upper bounds for the element width and length are used to generate designs; and The design performance is comparable to previous floating element work [79] and the is chos en for scaling purposes. The element size meets the scaling requirements of the largest facility where a floating element shear stress sensor has been successfully installed [80] The element size matches the smallest hotwire used in the scaling study. Table 4 2 The various floating element sizes selected for optimization and their associa ted friction velocities and bandwidths from the scaling analysis presented in Section 1 3. Floating Element Size Friction Velocity Bandwidth The scaling based design targets are shown in Table 4 2. The size of the floating element sets the friction velocity where it is appropriate. The bandwidth is then derived using that friction velocity.

PAGE 163

163 4.3 Optimization Results While the primary goal of this optimization i s to create optimized designs meeting the theoretical scaling requirements for smaller floating element sizes lower bandwidth designs prove useful for model verification The ultimate designs for fabrication are then presented in this chapter along with t he justification for each design chosen 4.3.1 Optimization Bound s and Impact on Design Selection As shown in Table 4 2, the commensurate bandwidth for a sensor is Previous generations have fabricated flo ating elements of this size with a bandwidth of In order to compare performance directly with previous generations the optimization is performed with a bandwidth of Design 1 in Table 4 3 is the resulting design of this opt imization. T he commensurate bandwidth for a sensor is as shown in Table 4 2 To capture this frequency, an optimization is performed with a bandwidth constraint of Desi gn 2 in Table 4 3 is the resulting design of this optimization. As the floating element size shrinks to the commensurate bandwidth grows to As the bandwidth is now an order of magnitude larger than any demonstrated devices, multiple optimizations are performed in order to determine the effect of the increased bandwidth on device performance. At an element size of and a bandwidth of the predicted minimum detectable shear stress is At a bandwidth of the minimum detectable shear stress grows to In order to see the trend of the bandwidth constraint on minimum detectable shear stress multiple design spaces are genera ted and the resulting minimum detectable shear stress values are plotted against the bandwidth constraints that

PAGE 164

164 generated them. The results are shown in Figure 4 4. When the bandwidth constraint is set at or below the minimum detectable shear stress is below In this case, two devices are selected for fabrication, one with a bandwidth of to produce a relatively low minimum detectable shear stress and another with a bandwidth of to approach the ap propriate scaling for the element size. Figure 4 4 The results of the study of bandwidth on the minimum detectable signal for the optimized floating element sizes The final element size chosen for optimization is that match es the smallest hotwire currently presented in literature. The commensurate bandwidth at this element size is The optimization does not converge for bandwidths above Again a bandwidth study is conducted and the results ar e also shown in Figure 4 4 When the bandwidth constraint is set at or below the minimum detectable shear stress is below In this case, two devices are selected for fabrication, one with a bandwidth of to produce a relati vely low minimum detectable shear stress and resonance to assist in model verification and another with a bandwidth of to maximize the bandwidth while still using the formulated optimization.

PAGE 165

165 4.3.2 Optimization Trends and Designs Sele cted for Fabrication Despite the multiple design spaces many trends held across all of the finalized designs. First, the nominal capacitance is always maximized This influences the overlap of fingers, the gaps, and and the width of the fingers, Additionally, the sensitivity of each design to variations in the design variables hold across all design spaces. The sensitivity of the device per formance to these design variables is shown in Figure 4 5 assuming a 1 mm floating element size, and illustrates that the device performance is most reliant on the g aps and the tether geometries. Figure 4 5 The sensitivity of the optimized design on th e design variables. The behavior of the optimization with regards to the pressure constraint manifests in several ways As the height of the cavity is largely set by the geometries of the material that the sensor is constructed out of there were two chann el heights where the

PAGE 166

166 optimization was performed. The cavity height is either or that is set by the geometry of the raw materials At a cavity height of the pressure rejection constraint forces th e design to increase the area of the sensor. The pressure rejection constraint is implemented as a ratio of displacement due to shear to pressure based displacement. The expected response to this constraint is a manipulation of the pressure cut on that w ould manifest in an optimal perforation of the floating element. With such a large cavity height the compliance of the cavity overwhelms any possible changes in resistance The optimization then begins maximizing overall sensor area in an attempt to maxi mize deflection due to shear stress. When the cavity height is set to the optimization begins to alter the hole structures in order to change the pressure cut on. The optimization also used the holes to remove mass from the floating element in order to manipulate the resonant frequency. After changing the cavity height the pressure constraint was not active and the design was bounded by the fabrication bounds and resonant frequency. While the designs produced are predicted to have better rejection of pressure inputs, the sensor cannot be called optimized with respect to the LEM developed for pressure. In order for this to happen a true multi objective optimization would need to be formulated, that is outside of the scope of this work. The details of each of the designs selecte d for fabrication are shown in T able 4 3. 4.4 Summary This chapter presented a system level optimization of the shear stress sensor structure while attempting to minimize the out of plane motion of the floating element structu re through the use of an optimization constraint. The operating space of this

PAGE 167

167 optimization is not large enough to implement all of the desired pairs of element size and bandwidth, but a parametric set of designs is available for study of the validity of t he scaling analysis presented in C hapter 1. Following design selection sensors are fabricated as described in C hapter 5. Table 4 3. The optimized geometries chosen for fabrication. Design Parameters Design 1 Design 2 Design 3 Design 4 Design 5 Desig n 6 Bandwid th 22 25 25 25 25 25 1000 500 200 200 62.5 62.5 1000 500 200 200 62.5 62.5 1000 1000 1000 1000 1000 1000 15 16 11.5 25 10 10 45 45 45 45 45 45 150 150 150 150 150 150 20 4 4 4 5 4 3.5 3.5 3.5 3.5 3.5 3.5 20 7.7 7.6 7.6 6 6 1296 625 100 100 0 9 10 10 10 10 10 10 MDSS 0.1 0.45 2.4 14.9 2.9 15.9 1.25 0.86 0.43 0.40 0.26 0.24

PAGE 168

168 CHAPTER 5 SENSOR FABRICATION A ND PACKAGING Given an optimized sensor design from C hapter 4, the sensor die is fabricated and packaged The fabrication process is a silicon bulk micromachining process with six masks. The process flow is outlined in Section 5.1 with fabrication results presented in Section 5.2. The developed sensor package is then discussed in Section 5.3. The packaging leverages existing printed circuit board technology and a laser machined shim cap to achieve a hydraulically smooth surface capable of interface with additional circuit boards. This shim cap is combined with additional mechanical supports to create a robust package suitable for use in wind tunnel facilities as described in Section 5.4 5.1 Fabrication Process Flow The MEMS sensor structure will be fabricated using six masks using bulk micromachining techniques with pre processed silicon on in sulator (SOI) wafers. The final product will be the capacitive floating element structures with metalized backside contacts. Figure 5 1 gives an outline of the process flow. The wafers have a thick highly doped p type device layer and a thick buried oxide layer Polysilicon through silicon vias (TSVs) are distributed through the wafer, fabricated by IceMos Technology, Ltd as shown in Figure 5 1(a) The first two masks make contact to the pre fabr icated TSVs creating the pads for the backside contacts and passivating the backside of the device with a nitride coating, as shown in Figure 5 1(b i) The next two masks make contact with the top side of the TSVs, as shown in Figure 5 1(j o). The final mask define s the floating element structur e, shown in Figure 5 1(p q) The cavity is formed by removing the BOX layer through the holes placed in the floating element

PAGE 169

169 for enhanced pressure rejection shown in Figure 5 1(r s) Appendix G contains the deta iled process traveler for this process flow. Figure 5 1 Step by step fabrication process 5.2 Fabrication Res u lts There are two points to evaluate the fabrication through the process flow; first is the validation of the throug h silicon vias, secondly is the deep reactive ion etch (DRIE) that forms the floating element structure. These are discussed in Section s 5.2.1 and

PAGE 170

170 5.2.2, respectively. The final point of failure for the sensor is the release, that is discussed in Section 5.2.3. 5.2.1 Through Silicon Via Validation After the front and back side of the TSVs are metallized, step ( o ) in Figure 5 1, they are electrically tested to verify that they conduct through the wafer and that the interface between the deposited aluminum silico n and polysilicon TSV is ohmic. During electrical testing, there was great variability from TSV to TSV. Some TSVs appeared nearly ohmic while others were diodes or even open circuits. By cleaving a portion of an unprocessed TSV wafer the variation in el ectrical testing is explained. In Figure 5 2, a properly formed TSV is shown. The device layer is at the top of the image, and the buried oxide layer (BOX) is the glowing portion in the middle. Figure 5 2 A cross section of a properly fabricate d TSV Device Layer Bulk Silicon Polysilicon Silicon Dioxide

PAGE 171

171 The polysilicon fill that creates the conductive TSV is shown connecting through the BOX. In an adjacent TSV the cross section is vastly different, as shown in Figure 5 3. Figure 5 3 A cross section of a TSV that is not connected proper ly. Some TSVs are non conductive as the front and back polysilicon fills to not meet at the interface between the handle and the BOX. Devices in this state can still be wire bonded, as in previous generations, are not able to be flip chip bonded into the smooth package. 5.2.2 Floating Element Fabrication The performance of the device is primarily dependent on the device geometry, thus the definition of that geometry is of critical performance. The floating element structure is etched using deep reactive ion etc hing (DRIE) into the device layer of the SOI wafer, step (q) in Figure 5 1, using the BOX layer as an etch stop. Silicon Dioxide B ulk Silicon Polysilicon Polysilicon

PAGE 172

172 DRIE is an anisotropic method of etching silicon that an isotropic etchant, in this case is alternated with a pa ssivation layer in an reactive ion etch process. The result is an overall isotropic etch, with the degree of isotropy defined by gas flow rates and cycle times. The DRIE process is highly dependent on exposed area, meaning th at areas with larger exposure will etch faster than relatively small features. This phenomena is referred to as RIE lag [81] and is shown in Figur e 5 4 This lag is particularly troublesome as the basis of the capacitive transducer structure is a highly asymmetric gap, so by definition there are nearly adjacent areas to be etched with vastly different exposed areas. Figure 5 4 A demonstration of the RIE lag seen on a representative tether structure during the fabrication of the capacitive shear stress sensor where the large gap is 15 and the small gap is 3.5 The result of etching beyond r eaching the BOX layer is that the anisotropic etchant begins to remove the passivation layer at the interface between the device layer and the

PAGE 173

173 BOX and begins to etch isotropically. This is commonly referred to footing. While anti footing capabilities exi st, they are not currently available at the facilities used for fabrication in this work. As the structure is modeled as beams with a rectangular cross section the etch that defines the floating element must be as anisotropic as possible and footing shou ld be minimized. Some footing did occu r during the final etch process however the beam is for the most part as designed, as shown in Figure 5 5 Following the definition of the floating element, the cavity is created to release the device. Figure 5 5 A cross section of an unreleased tether showing the footing in the base of the tether structure with symmetric 3.5 gaps 5.2.3 Floating Element Release The cavity is formed by removing the BOX layer in a buffered oxide etchant (B OE) bath. The holes in the floating element serve as a pathway for the wet etchant to react with the oxide beneath the relatively large floating element. The result is a released Silicon Dioxide Device Layer Tether Cross Section

PAGE 174

174 structure with a cavity beneath it. A cleaved view of a floating element after the release etch is shown in Figure 5 6 In Figure 5 6 it appears that the oxide has been cleared from beneath the floating element structure, releasing it. From a top down view, however, it is clear that not all of the material between the fingers has been removed, even after over etching the oxide by a factor of three and the silicon by several DRIE cycles This is shown in Figure 5 7 In this figure the top surface of the floating element is visible, but out of focu s, as the remaining strings of material are at the bottom of the trenches between comb drive fingers. Figure 5 6 A cleaved view of the released floating element, showing partial cross sections of the floating element perforations. Following devi ce manufacture they are electrically characterized, as described in Section 6.1, to determine nominal capacitance and to verify they are fully released. The residual material between the comb fingers restricts the motion of the floating element Floating Element Cross Section Bulk Silicon Cavity Perforating Hole

PAGE 175

175 and as a r esult Silicon on Pyrex devices, fabricated by Sells [35] and described in Section 5.3 are used to validate the performance of the system Figure 5 7 Residual material between the comb fingers following the release etch. 5.3 Silicon on Pyrex Devices As part of the fabrication of sensors for use in wireless devices, as described in Sells, et al. [35] several designs outlined by Chadrasekharan [37] were also fabricated. The sensors fabricated in this process are used in Chapter 6 to validate the packaging and circuitry developed in this wo rk. The process flow for this sensor is available in [34] and is repeated here for completeness. This two mask process is shown in Figure 5 8 The process begins with depositing and patterning chrome on a Pyrex wafer (A B). A cavity is etched into the Pyrex and the chrome is removed (C D). An SOI wafer is anodically bonded to the Pyrex wafer and the bulk silicon and BOX layer are removed (E F). Finally the floating element structure is defined using DRIE (G). Floating Element Residual Material Comb Fingers

PAGE 176

176 Figure 5 8 The silicon on Pyrex process used to fabricate the capacitive shear stress sensor, adapted from [35] 5.4 Sensor Packaging Packaging a MEMS sensor requires all of the same considerations given to integrated circuit packaging, but with added complexity requiring that t he sensor is exposed to the environment. These stringent constraints mean the sensor package can account for up to 95% of the total sensor cost [82] Most of the development in sensor packaging has been directed towards low frequency pressure sensors and actuators [83 86] as those applications require an exposed die but the rest of the package dimensions are no t particularly constrained. These applications also leverage older integrated circuit packaging technologies, such as TO cans, to create singular packaged die. While stacked die and integrated packaging techniques assist in the interconnection of a senso r with its interface

PAGE 177

177 electronics, the custom molded or ceramic packages that are required to realize such packages are expensive and incur large non recoverable engineering costs. The four major considerations that shape the package are induced stress, h ydraulic smoothness, sensor installation density, and the proximity of interface electronics. The package concept, in order to keep non recoverable engineering costs low and still produce a robust and effective package will mimic current packaging techniq ues for microphones or MEMS pressure transducers, such as Kulites. The transducer will be separated from the interface electronics on an end cap. That end cap will then connect to interface electronics contained within a metal tube, keeping the footprint of the sensor small without sacrificing signal integrity. The sensor packaging is initially demonstrated using sensors fabricated by Sells using a silicon on Pyrex fabrication and front side wirebond connections [35] This version of the package is described in 5.3.1. In order to accommodate TSV connections the packaging concept is expanded and described in Section 5.3.1. 5.4.1 First Generation Packaging Concept In order to realize a robust package capable of accurate measurement of shear stress with minimal materials and engineering costs, a printed circuit board (PCB) based approach is implemented. Hydraulic smoothness is achieved by milling a recess to the dimensions of the sensor die in order to flush mount it into a PCB. The sensor is then wire bonded to features on the top of the circuit board. A non scale schematic is shown in Figure 5 9 Thi s PCB forms an end cap that is then placed on an aluminum tube containing the immediate interface circuitry, as shown in Figure 5 10 The aluminum tube is inches in outer diameter and has an inner diameter of inches. This inner diameter is large enough for a single FR4 circuit board populated

PAGE 178

178 with the interface buffer and supporting passives, described in C hapter 3, to be placed in close proximity to the sensor die. Figu re 5 9 A non scale schematic showing the assembly of the PCB end cap for flush mounting silicon on Pyrex devices. In order to minimize any induced stress from being transferred from the package to the sensor both the cavity the epoxy used to hold the sens or die in to the cavity and the method used to fix the end cap to the rest of the package must be carefully selected. For the package used by Chandrasekharan et al. in the initial sensor characterization a large PCB was press fit into a Lucite plug. This was effective but quite large and unstable. The thermal properties of Lucite are not favorable for high tolerances and as a result the security of the press fit circuit board changed with the ambient temperature and humidity. The sensor was affixed to t he PCB board using Dualbond 707 epoxy that required thermal cycling to cure. The mismatch of the coefficient of thermal expansion of the sensor die and PCB may have caused additional stresses on the sensor die The current package sought to avoid these i ssues by epoxying the sensor die using a room temperature curing epoxy and by minimizing the areas where the sensor die is connected to the PCB while still maintaining a secure

PAGE 179

179 fixture. This will allow the sensor die and PCB to expand and contract with te mperature while minimizing the stress at the epoxy contact points. Additionally, instead of a press fit to the supporting structure for the PCB the sensor plug is instead fit to the end cap by matching the outer diameters and applying epoxy. A picture of the current package and the package used in Chandra sekharan et al. are shown in Figure 5 11 Figure 5 10 Sensor tube package design (not to scale).

PAGE 180

180 Figure 5 11 F irst generation package (left) and the package in Chandrase kharan et al. (right) [79] shown with a US quarter for reference The sensor density and proximity to electronics trade off with one another within the package design In order to minimize overall sensor footprint while still maintaining close proximity to the buffer electronics, the interface board will be placed such that it is perpendicular to the end cap. This increases the depth of the package but decreases the overall outer dimensions dramatically. The interface circuitry board is then placed into a gro unded aluminum tube in order to shield the electronics from EMI. A schematic of t his interface is shown in Figure 5 8 While this generation packaging is an improvement over the design in Chandrasekharan et al. there are still several deficiencies. First the surface wire bonds are exposed to the flow. This is not ideal as not only does this prevent the sensor from being truly hydraulically smooth but it also provides a point of failure for the device as they are delicate. In order to accommodate the TS V fabrication described in C hapter 4 the end cap, shown in Figure 5 8 is redesigned and a second gen eration of tube based packaging is fabricated.

PAGE 181

181 5.4.2 Second Generation Packaging Concept A similar approach to packaging was taken in order to accommodate the TS V devices. Instead of a recess being milled into an end cap instead the sensor die is flip chip bonded onto a PCB and a precision laser machined plastic shim cap is used to make the surface of the sensor package flush. The PCB end cap has several small g old pads that fan out to vias, allowing for connection to the circuitry inside of the tube, as in Section 5.3.1. Figure 5 12 Second generation end cap components (foreground) and an assembled end cap (background). The plastic shim cap is manufactured using an Oxford J 355 PS Laser Micromachining system. Plastic is a preferable material to metal due to the exposed sensor electrodes. While ideally there is no physical contact between the shim cap and the side of the die, manufacturing the shim cap out of a non conductive material allows for some flexibility in the tolerance of the cap dimensions and placement. The shim cap, circuit board, and a die are shown assembled and in an exploded view in Figure 5 1 2 Following the as sembly of this new end cap onto the first generation aluminum tube with enclosed electronics the sensor system is able to be characterized. The overall roughness of the interface between the plastic shim cap and sensor die was

PAGE 182

182 measured using a Dektak prof ilometer and registered a smoothness of approximately 70 5.5 Summary In this chapter a fabrication of optimized sensor designs from Chapter 4 implementing through silicon vias was attempted. Due to errors in the fabrication of th e TSVs and the difficulty in the final floating element release the through silicon via devices are not functional as shear stress sensors. Recommendations for improving this fabrication are given in Chapter 7. Devices designed by Chandrasekharan [29] but fabricated in a silicon on Pyrex process [35] also outlined in this chapter, are used for validation of the support circuitry, packaging, and t o demonstrate the sensor performance in bench top and wind tunnel experime nts. Also i n this chapter two generations of sensor packagi ng were constructed. The first generation flush mounted a sensor die into a printe d circuit board, enabling front side wirebond connections. The second generation employed a laser micromachined s him cap to flush mount the sensor. The shim cap and sensor die are bonded onto an FR4 substrate that is compatible with both TSV sensors and sensors requiring front side wirebonds. Following packaging, the sensor system is calibrated and tested in severa l wind tunnel facilities.

PAGE 183

183 CHAPTER 6 EXPERIMENTAL CHARACT ERIZATION In this chapt er, the sensor system is characterized through a series of bench top and wind tunnel experiments. There are two general categories of characterization for the bench top characterization of the sensor system electrical and mechanical. Electrical characte rization is used to validate the quasi static electrical model and mechanical characterization is used to validate the mechanical models developed in C hapter 2 and provides a device sensitivity and bandwidth. After bench top characterization the sensor sy stem is tested in three wind tunnel facilities enabling a comparison between the performance with respect to traditional mean and dynamic shear stress estimation techniques. This chapter is broken into two main sections, the first describes the methods tha t the sensor is characterized and the second presents the results determined by these characterization methods. The parameters used for data acquisition are grouped with the results. 6.1 Experimental Setup Prior to packaging the sensors are electrically t ested. This prevents the packaging of die that are defective. The impedance measurement technique is described in Section 6.1.1. After packaging, the sensors are tested in two fluidic characterization test beds, described in 6.1.2. The first set up sim ulates mean flow across the sensor and the second simulates dynamic flow across the sensor. The sensor is tested for environmental sensitivities, described in 6.1.3, before being installed into three different wind tunnels. The wind tunnel facilities use d to validate the sensor performance are described in Section 6.1.4. Finally the approach to the estimation of experimental uncertainty is described in Section 6.1.5.

PAGE 184

184 6.1.1 Electrical Characterization Prior to packaging the impedance of the sensor is measured. The impedance is measured using a Cascade M150 probe station with two MPH Series MicroProbe manipulators and tungsten probe tips. The probe manipulators are configured for four point measurement up to the point of the attachment of the probe tip. Figure 6 1 A schematic of the sensor structure with the probe points for the impedance characterization indicated on A) a TSV device and B) a silicon on Pyrex device In a four point measurement the four probes are labeled as indicating two measurement points, H and L, with both potential and current

PAGE 185

185 measurements, indicated by the subscripts P and C, respectively. An Agilent 4294A Impedance An alyzer is used to make the four point impedance measurement. The predicted contributions to the imped ance measurement, including an indication of the configuration of the probes with respect to the sensor electrodes are shown in Figure 6 1. The two capacitances that make up the sensor differential half bridge are measured separately T he first measurement is indicated by the probes with the subscript 1 and the second measurement is indicated by the probes with the sub script 2. Following electrical characterization the sensor is packaged and the mechanical perfor mance of the sensor is evaluated. 6.1.2 Fluidic Characterization There are a total of four testing facilities that will be used in order to characterize the sensor system performance Two bench top characterizations will test three aspects of sensor performance ; static sensor response using a flow cell, dynamic sensor performance using an acoustic plane wave tube, and the response of the sensor to an acceleration input. The other facilities used to characterize system performa nce are wind tunnels; one small sca le wind tunnel available at the University of Florida one large r wind tunnel available at NASA Langley Research Center (LaRC) and a tunnel at the Graduate Aeronautical Laboratories at the California Institute of Technology (GALCIT) Each set up, along w ith the measured sensor property, are described in Section s 6.1.2.1 through 6.1.2.4. 6.1.2.1 Mean flow characterization The static characterization is achieved using a flow cell. The flow cell is constructed of two aluminum plates separa ted by a shim forming a channel long and wide The shim height is varied if desired. A n Aalborg

PAGE 186

186 MFC mass flow controller is used to set the flow rate through the channel and pressure taps, separat ed by 76.2 mm and monitored by a Heise pressure module, are c entered on the sensor location measuring the pressure drop along the channel Figure 6 2 Laminar flow cell schematic (not to scale) demonstrating the control of airflow through the channel The flow through the channel is assumed to be steady, fully developed, two dimensional flow [87] where the shear stress is ( 6 1 ) where is the channel height and is the pressure drop across a known length of the channel, as shown in Fi gure 6 .1. This relationship holds regardless of the state of the flow as long as it is fully developed and incompressible [88] In addition to characterizing the dc response of the sensor, the effects of pressure gradients across the sensor can also be studied by changing the shim height but mai ntaining t he same wall shear stress

PAGE 187

187 6.1.2.2 Dynamic flow characterization The ac response of the sensor is estimated using an acoustic plane wave tube (PWT) The PWT is a n aluminum square duct with a cross section. The cut on of higher order mo des in air for this geometry is The acoustic source is a BMS 4590P compression driver with a passive crossover circuit [89] As an acoustic wave propagates down the PWT under the restriction of the no slip boundary condition at the wall a frequency dependent boundary layer, and thus frequency dependent shear stress, is generated. By changing the acoustic termination at the end of the PWT and the orientation of the sensor many different ac characteristics of the sensor are tested in this setup including dynamic sensitivity, frequency response, and pressure sensitivity. D ynam ic sensitivity is tested by generating an ac shear stress through Stoke layer excitation in an acoustic PWT with a sound hard boundary A speaker is mounted at one end of the PWT and the other end will be terminated with a sound hard boundary. When the speaker is on a standing wave pattern is developed. The sensor is plac ed at a known location along the wave pattern and the sound pressure level of the excitation signal is swept. The shear stress acting on the sensor is related to the sound pressure levels at both the sensor location and at the arbitrary boundary by ( 6 2 ) where is the distance between the sensor and the boundary shown on Figure 6 2, is the distance between the sensor and the reference microphone, that in this case is equivalent to k is the acoustic wave number, and is the r eflection

PAGE 188

188 coeffici ent of the boundary For this set up, an aluminum plate which is a minimum of 1 inch thick is used so that the reflection coefficient is assumed to be 1 [90] This same configuration is used to determine the pressure sensitivity of the sensor. By changing the excitation frequency such that the sensor is located at a half wavelength instead of a quarter wavelength the sensor will see only a dynamic pressure input Increasing the sound pressure level within the tube and recording the sensor output a sensitivity curve to dynamic pressure input is generated. Figure 6 3 Dynamic shear stress sensor calibration experimental setup using an acoustic plane wave tube with a sound hard boundary to set up a standing wave pattern in the tube This PWT configuration is limited as the geometry of the tube limits the number of frequencies that meet the half or quarter wave length requi rement. In order to construct a frequency respons e function of the sensor to a shear or pressure input the frequency that excites the PWT is varied. Using this configuration, the resolution of any constructed frequency response function is poor. In orde r to improve frequency resolution, a movable sound hard boundary is installed. This movable boundary allows

PAGE 189

189 for any frequency within the operational range of the plane wave tube is usable and the sensor will be at the desired pressure or a shear minimum. Figure 6 4 A schematic of the movable back plate PWT configuration for acquisition of frequency response functions courtesy of Anup Parikh and Daniel Blood The movable back plate has an integrated motor and motor controller to ensure that the back plate is placed appropriately. The motor controller is programmed using an Arduino Uno microcontroller interfaced with LabVIEW LabVIEW is used to implement a gradient descent algorithm to minimize the pressure at the sensor loca tion and determine the optimal location for acquiring shear stress data The position of the back plate is determined by a proximity sensor and is reported. In order to place the sensor at a pressure maxima, shear minima, the control loop runs to minimiz e shear stress and then the frequency is doubled before data acquisition. An alternate way of obtaining the frequency response function is by attaching an anechoic termination to the end of the PWT, shown in Figure 6 5 The resulting sensor output is a co mposite sensitivity of shear and pressure, but is tested over the frequency range of the plane wave tube. Th e result is an approximation of the frequency response

PAGE 190

190 function of the sensor performance with respect to a shear stress input, and is a predecesso r to the setup shown in 6 4. This experiment is quicker and much simpler to perform as there is no active control of the termination. In this case progressive plane wave s create an input shear stress given by ( 6 3 ) Figure 6 5 Experimental setup for a combined shear and pressure response testi ng using an acoustic plane wave tube with an anechoic termination In either termination case, the frequency response function of the shear stress measurement system is expressed as ( 6 4 ) where is estimated by E quation 3.84 or 3.83, depending on the measurement method, V is the output voltage of th e sensor, and is the magnitude of the sensitivity determined in the e xperiment shown in Figure 6 3. 6.1.3 Environmental Characterization As the sensor is exposed to the flow during characterization and ultimately use it is important t o understand how the sensor reacts to changes in the ambient environment.

PAGE 191

191 To characterize the response of the sensor to changes in ambient temperature and relative humidity an Espec ESX 3CA Platinous Chamber with an SCP 220 controller is used to cycle thr ough different environmental conditions. The chamber is capable of temperatures from to and relative humidities from to In order to decouple the effects of each environmental input two tests are conducted. First the temperature is cycled at a static relative humidity. After determining sensitivity to temperature the chamber is held at a given temperature and relative humidity is cycled. Given a full characterization of the static and dynamic sensitivities of the sensor and an estimation of the sensor performance in varying ambient environments the next stage of verification is installation into characterized flows. This is achieved at the Un iversity of Florida in a small scale faci lity, described in Section 6.1.4 in a large r scale facility at NAS A LaRC, described in Section 6.1.5 and finally at the Graduate Aeronautical Laboratories at the California Institute of Technology ( GALCIT ) in Sect ion 6.1.6 6.1.4 Wind Tunnel Facilities Once the mean and dynamic characteristics of the sensor have been tested independently the sensor is placed into a well characterized flow, like laminar or turbulent flow over a flat plate, and compared with other flow mea surement techniques to further verify its performance. 6.1.4.1 Facilities at the University of Florida A n existing flat plate model is installed at the University of Florida in an Aerolab low speed, open circuit wind tun nel. The flat plate, shown in Fig ure 6 6 has an elliptic leading edge and blunt trailing edge with a Plexiglas body to enable laser based

PAGE 192

192 measurements at the surface [79] The model also contains static pressure taps in order to verify the pressure gradient across the model. Figure 6 6 Di mensioned schematic of the flat plate model for use in UF facilities [79] Figure courtesy of John Griffin. The UF facility is capable of freestream velocities of to with a test section cross section of by The flow over the model remains laminar up to freestream velocities of around 20 m/s and then becomes transitional. In order to test turbulent flow conditions trip tape is placed near the leadi ng edge. The resulting shear stress values that are measured in this facility range from to for Laminar flow and to for turbulent or transitional flow. Comparative measurements available in the facility are currently limited to laser based techniques, such as PIV or LDV. While the UF facility is an appropriate test bed for initial sensor integration a larger facility would be more appropriate for the final stages of testing before deployment into more complicated flow fields and models. The Shear Flow Control Facility at NASA Langley Research Center (LaRC) is an appropriate next step in testing.

PAGE 193

193 6 1.4.2 Experimental c haracterization at NASA LaRC T he Shear Flow Control Facility at LaRC is a low speed open circuit tunnel with a by cross section capable of free stream velocities of to corresp onding to shear stress values up to A picture of the LaRC tunnel is shown in Figure 6 7 Installation into the LaRC tunnel is complicated by the overall size of the tunnel an d can better characterize the sensor performance as many additional flow measurement techniques have already been implemented in the tunnel. Due to the larger test section the volume of air required to maintain a particular free stream velocity means that non conditioned air is pulled into the room from th e surrounding garage areas. The instability of the ambient environment test s the sensor sensitivity to factors such as relative hum idity and temperature in a fully characterized flow field. Figure 6 7. hear f low c ontrol f a cility at LaRC.

PAGE 194

194 The large tunnel size also restricts the types of flow fields that are accurately generated. As the sensor is placed far downstream of the leading edge only turbulent flows are capable of being generated It is difficult to maintain l ami nar flow on such large scales. A benefit to the large tunnel size is that if the flow is tripped far upstream of the sensor the resulting turbulent boundary layer has a long region to grow so the resolution requirements on the downstream measurement equip ment is relaxed. An additional benefit to testing in the LaRC tunnel is the wide range of measurement capabilities available. While PIV provides a reasonable estimate of the flow field, it is limited by seeding particle size and cannot be performed while the sensor is installed because of the requirement to have a seeding fluid. At LaRC a traverse is installed at the sensor location with the capability of producing profiles acquired using a Pitot static p robe or hotwire probe Additionally Preston tube m easurements are available as a comparative measurement matching flow conditions. In this dissertation velocity profiles acquired using a traversing hotwire and near wall hotwire data are considered. Following evaluation of the performance of the sensor in well characterized flows, the sensor is transitioned to GALCIT At GALCIT the sensor is integrated into a model specifically designed for the characterization of non equilibrium turbulence [91] 6.1.4.2 Experimen tal c haracterization at GALCIT Finally the sensor is tested in the Merrill tunnel at GALCIT In this set of experiments, the sensor is installed into a flat plate with a trip wire near the leading edge to induce turbulence and an additional downstream tim e varying trip structure. Comparative measurements are taken with a traversing Dantec type 55 hotwire that

PAGE 195

195 extends from the wall on a sting balance The flat plate is made of Perspex, an optically clear plastic. 6.1.5 Experimental Uncertainty There are two general categories of data within these experiments; mean data and spectral estimates. The random uncertainty for each type of data is presented in Section s 6.1.5.1 and 6.1.5.2 for mean and spectral estimation data, respectively. The bias errors are described by test bed in Section s 6.1.5.3 and 6.1.5.4 The total error, as these sources are all uncorrelated, is a root sum square of the individual error contributions. 6.1.5.1 Random error in mean measurements T he output of the Synch MOD/DMOD system i s a dc voltage for an input mean sh ear stress, and thus the error in mean measurement is important. Regardless of the distribution of the random error in a voltage signal, the random error in the sample mean is Gaussian as the number of samples used to ca lculate the mean approaches infinity [92] The bounds o n the estimation of the mean value, is given by ( 6 5 ) where is the sample mean, N is the number of samples, the interval for the estimate is t is given by the t distribution, and s is given by ( 6 6 )

PAGE 196

196 6.1.5.2 Random error in spectral estimation The random error associated with the estimation of spectral estima tion is used to demonstrate the uncertainty in dynamic sensor calibration. Generally the error estimate in a spectral estimation is given by ( 6 7 ) where is the effective number of averages and based on the windowing applied during estimation. The dynamic sensor sensitivity and frequency response function are acquired using single tones and are estimated using uniform windowing making the random error in the estimate ( 6 8 ) For the frequency response function there is an additional source of error associated with the coherence between the input and output signals. This error manifests in both the magnitude of the f requency response function as well as the phase. These errors are ( 6 9 ) and ( 6 10 ) where is t he ordinary coher ence function estimated as ( 6 11 )

PAGE 197

197 The ordinary coherence function is a lso a metric where the relation between two signals is represented. The coherence function varies between zero and one where a coherence of zero indicates that the two measurements are unrelated and a coherence of one indicates perfect correlation. 6.1 .5.3 Bias Error in the Laminar Flow Cell Experiments There are many sources of bias error associated with measurement in a flow cell. The error analysis presented by Chandrasekaran [93] is adapted for the case of pressure driven flow in a channel. Mean shear stress is related to a pressure drop in fully developed, steady, pressure driven f low in a channel by ( 6 12 ) There are two sources of geometric error th at contribute to errors in the estimated shear stress, variations in the channel height, h, and variations in the distance between pressure measurements, dx. The total error in shear stress measurement is expressed as a root mean square addition of these individual error sources as ( 6 13 ) In both cases the error in the dime nsion is 0.005 inches, or 0.127 mm, and is the machining tolerance of the flow cell. The height of the flow cell is 0.5 mm and the distance between pressure taps is 76.2 mm. The error in the estimate of mean shear stress due to variations in these geomet ries is 25.4%. This is most likely an overestimation of the error due to geometry and is used to generate a conservative estimate of sensor performanc e.

PAGE 198

198 6.1.5.4 Bias Error in the Plane Wave Tube Experiments There are several sources of bias error associa ted with measurement in the plane wave tube. The error analysis presented by Chandrasekaran [93] is again adapted for the case of ac shear stress resulting from a standing wave pattern. Given the relationship between input pressure and output shear stress, ( 6 14 ) the error in the estimation of wall shear stress is induced by two dimensions, the dimension of the duct and the distance from the sensor to the s ound hard boundary. This equation simplifies as to ( 6 15 ) These errors are expressed as the sensitivity to the dimension multiplied by the expected value of the dimension, as ( 6 16 ) The sensitivity to the dimensions are given by ( 6 17 ) and ( 6 18 ) T he total error in the estimation of shear stress becomes

PAGE 199

199 ( 6 19 ) The er ror in the dimensioning of the duct is assumed to be 0.005 inches. The duct cross section is 1 inch. The resulting error is a maximum of 7.07% of the estimated value of wall shear stress 6.1.5.5 Error Analysis of PIV Based Shear Stress Estimation The un certainty in the shear stress derived from PIV measurements uses a Monte Carlo simulation with 10,000 iterations where the average velocities and distance from the wall are perturbed based on the uncertainty of the PIV data. The resulting boundary layers are fit to estimate wall shear stress. The uncertainty in the wall normal distance i s the spatial resolution of the PIV data. The uncertainty in the velocity includes both bias and random uncertainty. The bias uncertainty is also a uniform probability den sity function where the magnitude of the bounds is determined [94] The random uncertainty in the streamwise velocity is assumed to be normal ly distribu ted as shown in [95] 6.1.5.6 Error Analysis of Hotwire Profile Based Shear Stress Estimation As was done in the PIV error analysis previously, Monte Carlo techniques are used to perturb the components of the boundary layer measureme nt. The velocities and distance from the wall are perturbed independently within the standard deviation of the acquired data 10,000 times creating 10,000 unique velocity profiles. The perturbed equation for a turbulent boundary layer and the errors are propagated to an error in shear stress.

PAGE 200

200 6.1.5. 7 Monte Carlo Analysis of Measured Sensitivities Given the error sources associated with the deduction of shear stress a Monte Carlo simulation is perf ormed to establish the bounds of the sensitivity of the sensor system. The Monte Carlo assumes a Gaussian profile for the uncertainty at each measured value and performs 50,000 iterations within the 95% confidence intervals. This assumes that the errors in each point are uncorrelated. The resulting confidence interval of the sensitivity is reported. 6.2 Experimental Results This section outlines the results of the characterization experiments described in Section 6.1. The results are broken down into two ca tegories; the results associated with the first generation of synch MOD/DMOD circuitry, Section 6.2.1, and the res ults associated with the second generation of synch MOD/DMOD circuitry in Section 6.2. 3 The results of the fabricated TSV sensor electrical characterization are shown in Section 6.2.2. 6.2.1 First Generation Synch MOD/DMOD The first generation of the synch MOD/DMOD system is demonstrated with previously fabricated sensors in order to demonstrate the viability of the interface circuitry and packaging techniques. As the sensors in this generation were not built as a part of this work, their electrical properties are described for completeness. The characterization of this generation consists of mechanical properties and wind tunnel demonstrations. 6.2.1.1 El ectrical properties The sensor used in this section of testing is fabricated using a silicon on Pyrex fabrication in conjunction with the effort to demonstrate a passive wireless shear stress

PAGE 201

201 sensor [35] In this case the parasitic capacitances associated with the structure supporting the sensor are practically eliminated; however the sensor still s uffers from the requirement of front side wirebonds. The sensor capacitance is approximately the nominal [34] The sensor is packaged with a bias resistance and then mechanically characterized. 6.2.1.2 Mean flow characterization The laminar flow cell described in Section 6.1.2.1 is used for two purposes in this installation; the determination of the sensor sensitivity to a mean shear stress input, and the sensitivity of the sensor to angular misalignment. The flow cell is configured with a tall shim machined to a tolerance of 0.127 mm The flow through the flow channel is controlled via an Aalb org GFC47 mass flow controller, allowing the flow rate to be set via an analog voltage. The control signal is generated via a LabVIEW controlled dc power supply. The sensor output is split into two channels and is acquired using a NI PCI 6034E data acqu isition system with a BNC 2110 breakout box. U sing LabVIEW the first is an ac coupled version of the sensor output, and the second is the sensor output passed through an SRS560 low noise amplifier with unity gain and two pole low pass filter The sensor data is taken using the sampling parameters shown in Table 6 1. The data is heavily over sampled as an unfiltered channel is simultaneously acquired for spectral analysis for use in debugging the Synch MOD/DMOD system. Table 6 1 The sampling parameters used with the flow cell. Parameter Value Sampling frequency 100 kHz Number of samples per block 100,000 Number of blocks acquired 5

PAGE 202

202 Figure 6 8. The sensitivity of the first generation Synch MOD/DMOD with a silicon on Pyrex sensor acquired using the laminar flow cell. Figure 6 9. The results of the Monte Carlo simulation of the sensor sensitivity determined by the flow cell experiments.

PAGE 203

203 After acquisition, the data is further down sampled to an effective sampling rate of 50 Hz and only one block of data is used. The control voltage to the Aalborg Mass Flow Controller is swept from 0 V to 3 V in 0.25 V increments, resulting in 13 flow conditions spanning shear stress values from 0 Pa to 3.2 Pa. The results of this static calibration are s hown in Figure 6 8. It is clearly shown that the large uncertainty in the flow cell measurement technique decreases the confidence in the sensitivity determined using this method. Using the Monte Carlo techniques described in 6.1 .5.7 the sensitivity is determined to be 4.6 mV/Pa at an 8Vac bias T he large error in the estimation of mean shear stress results in a large spread of R 2 values and thus large uncertainty in the estimation of sensitivity as shown in Figure 6 9. Figure 6 10. The normalized s ensitivity of the shear stress measurement system compared with the incident angle of mean flow across the sensor.

PAGE 204

204 Following static calibration, the sensor plug is rotated relative to the mean flow direction in order to ascertain the error induced by misal ignment. A sensitivity to mean shear stress is measured for each relative angle. The sensitivities are then normalized against the 180 degree case and plotted in Figure 6 10 The sensor alignment has a geometrically predicted cosine dependence on sensit ivity, indicating that alignment is not critical during installation into wind tunnel facilities. Small variations in angle around the nominal position do not result in large changes in sensor sensitivity. Following this demonstration of mean performance, the sensor is moved to the plane wave tube where the dynamic sensitivity and frequency response function are measured. 6.2.1.3 Dynamic flow characterization Using the PWT excitation described in Section 6.1.2.2 the sensor is calibrated using two different bias ex citations and the Synch MOD/DMOD system described in Section 3.6. Table 6 2 The sampling parameters used with the PULSE system. Parameter Value FFT mode Zoom Window Uniform Overlap Span FFT lines Acquisition Time Bin Width Number of linear spectral averages

PAGE 205

205 Figure 6 11. Dynamic calibration of the first gen eration Synch MOD/DMOD system with a silicon on Pyrex sensor as tested in the acoustic plane wave tube with a sound hard boundary. The resulting calibration for an 8 Vac bias case is shown in Figure 6 10. Comparing this calibration to the mean calibration the sensitivities are nominally the same, as seen in Figure 6 12 This sensitivity, however, is not optimal given the performance of the Synch MOD/DMOD circuitry. By adjusting the balance of the bias voltages, as described in Section 3.8.1, and the rec tification control signal, as described in Section 3.9.2.3, the sensitivity is increased from the observed in Figure s 6 10 and 6 11 to as shown in Figure 6 1 3 This improved sensitivity is the confi guration the sensor is used in for the duration of the first generation Synch MOD/DMOD tests, including the wind tunnel entries. The normalized sensitivity of the whole system, including the Synch MOD/DMOD gain and noise contributions, is The sensor i s run at a bias voltage of the sensitivity of the system is

PAGE 206

206 Figure 6 12 Combined static and dynamic calibration plots indicating nominally the same sensitivity. Figure 6 1 3 Normalized sensiti vity of the first generation Synch MOD/DMOD sensor system as used for further characterization.

PAGE 207

207 Figure 6 14. The combined shear and pressure frequency response function of the shear stress measurement system. The PWT is terminated in an anechoic wedge to estimate the frequency response function of the system prior to the construction of the moving backplate The results are shown in Figure 6 1 4 While the resonance of the sensor system is identifiable in phase and magnitude, the lack of a true flat band region indicates that the pressure input to the sensor is not negligible and this combined measurement results in a combined output. In this case, the pressure at the sensor location is on the order of 100 Pa while the shear stress input is on the order of 1 Pa. As seen in Chandrasekharan, et al. [29] the pressure sensitivity is several orders of magnitude lower than the she ar sensitivity, however for this experiment the estimated incident shear stress is on the order of pascals while the input pressure is on the order of hundreds of pascals. The resulting

PAGE 208

208 output signals will be within an order of magnitude of each other res ulting in a combined output voltage. While this cannot be called a true frequency response function of the sesnor output with respect to an input shear stress, it can provide an estimate in order to use the sensor in a real flow environment. Following mea n and dynamic calibration, the first generation sensor system is tested in three wind tunnel facilities, the first at the University of Florida, the second at NASA Langley Research Center, and the third at GALCIT 6.2.1.4 UF w ind tunnel comparisons As discussed in Section 6.1.4.1 the UF Aerolab tunnel is equipped with a flat plate model capable of Laminar and turbulent flows. The tunnel was characterized using PIV for comparison with the mean component of the sensor output. The sampling parameters used for the acquisition of the sensor data are shown in Table 6 3. The sensor data was acquired using The mean shear stress is estimated in three ways; in solution [96] is used, in the case of a [97] for a [98] The estimated shear stress for a ll cases is shown in Figure 6 15 The PIV based velocity profile estimation of shear stress was performed by John Griffin along with the error analysis described in 6.1.2.5, that is used to generate the error bars on the PIV data. Within this figure the true advantage to the sensor is illustrated. For a given freestream condition, the sensor is capable of distinguishing a turbulent bo undary layer from a laminar boundary layer. Indirect measurement techniques require the flow state to be known a priori and are unable to make this distinction.

PAGE 209

209 Figure 6 15. Comparison of the estimated shear stress produced by the shear stress sensor sy stem and velocity profile estimates measured using PIV [79] Table 6 3. The sampling parameters used for the UF wind tunnel entry Parameter Value Sampling frequency 50 kHz Number of samples per block 5 0,000 Number of blocks acquired 5 In the lamin ar case the velocity profile based estimate and shear stress sensor estimate have very good agreement. In the case of the turbulent velocity profiles not only is there noticeable disagreement between the sensor data and either the estimates provided by Mu sker or those provided by Spalding, but there is disagreement between those two estimates. The comparative m easurement in this case is PIV that relies on seeding particles in order to calculate a velocity field. Physically the seeding does not transport to the wall easily and thus the amount of near wall data is limited such that the closest point to the wall that is measured is at a height of 23 mm This is further limited

PAGE 210

210 by the 0.12 mm spatial resolution of the PIV data. In order to obtain time resol ved near wall data and to better resolve the velocities near the wall a larger facility is used. 6.2.1.5 LaRC wind tunnel comparisons Following the promising results in the small scale UF facility, an entry at the NASA conducted. The flow conditions spanned values from 5,100 to 13,000 with freestream speeds spanning to Table 6 4 The sampling param eters used for the NASA LaRC study P arameter Value Sampling Frequency 25.6kHz Number of Samples per Block 128,000 Number of Blocks 50 Window Hanning Overlap 75% The sensor data is acquired with an Agilent E1432A VXI bus with VXI 1394 cards. The sampling parameters are show n in Table 6 4. A traversing hotwire were used to estimate the velocity profile used to estimate mean shear stress. The shear stress is elucidated from the resulting velocity profile for a turbulent boundary lay er are shown in Figure 6 1 6 There is larger disagreement in both the fits and betw een the velocity profile based shear stress estimate and the sensor output as frestream velocity increases. Another way to view this information is in terms of the coeffic ient of friction against the boundary layer height based Reynolds number. The spread of shear stress values determined by the Monte Carlo error analysis are shown in Figure 6 17. The profiles are given in A ppendix H.

PAGE 211

21 1 Figure 6 1 6 Comparison of sensor o utput to the shear stress determined by a traversing hotwire study with a solid line indicating unity Figure 6 17 The result of the Monte Carlo analysis for the determination of shear stress for a freestream velocity of 43 m/s demonstrating the distrib ution of error in the shear stress estimate as well as the finite difference between two velocity profile based estimation methods

PAGE 212

212 In order to verify the ac performance of the sensor, a near wall hotwire with an active area of the same approximate size as the floating element was installed. A near wall hotwire is used to estimate wall shear stress by placing it within the viscous sublayer of the boundary layer at a known height from the wall. When in the viscous sublayer the velocity is related to the wa ll shear stress by ( 6 20 ) where u is the measured velocity, h is the h eight from the wall, and is kinematic viscosity. The output of the hotwire system is simultaneously acquired with the sensor output and processed using the parameters in Table 6 4. Again varying freestream velocity the output of the hotwire and the output of the sensor displayed similar trends This is shown in Figure 6 18 for a freestream velocity of 40 m/s with additional cases given in A ppendi x H. Moving to a larger facility where the boundary layer is thicker and more nea r wall data is available, the estimates provided by velocity profile fits improve and the agreement with the sensor improves as well. Ideally the hotwire is placed from the wall, translating to a maximum of 2. By using the boundary layer profile to estimate the y intercept using the no slip condition the real height from the wall is estimated to vary from to or from of 5 to 110. In this case, the upper bounds clearly lie outside of the viscous sublayer leading to additional errors in this estimation technique. There are several sources of error associated with the nature of a temperature based measurement [99] in this estimate that could account for the difference in magnitude. First, the exact height of the hotwire is unknown. While the traverse was set to a specific height, slip in the traverse drive is a cause of uncertain ty. Additionally,

PAGE 213

213 the plate itself is made of metal. As the wire approaches the plate, heat transfer to the cold metal wall would induce a perceived velocity change [10 0] Figure 6 1 8 The estimated autospectra of wall shear stress determined by the capacitive shear stress sensor system (blue) and a near wall hotwire (black). Following these measurements, a 3.5 inch diameter cylinder is installed upstream of the senso r and hotwire. The shedding off of the cylinder has a characteristic frequency based on the Strouhal number of the flow where ( 6 21 ) where D is the diameter of the cylinder and the Strouhal number is 0.2 [5] The resulting spectra of the shear stress sensor and near wall hotwir e are shown in Figure 6 19 While the hotwire and shear stress sensor agree, the frequency is slightly lower than what is predicted by the Strouhal analysis. While imperfect, this demonstrates the abil ity of the sensor to see a well characterized oscillating phenomenon in a wind tunnel environment.

PAGE 214

214 Figure 6 1 9 The estimated aut ospectra of wall shear stress determined by the capacitive shear stress sensor system (blue) and a near wall hotwire (black) for downstream shedding off of a cylinder. After demonstrating the sensor performance in a mean and dynamic sense, the sensor is in stalled into a facility at CalTech in order to demonstrate the application of the sensor to measure a complex, time varying shear stress field. 6.2.1.6 GALCIT wind tunnel comparisons In the Merrill tunnel at GALCIT the sensor is compared to traversing and near wal l hotwires. The traversing hotwire probe is initially placed at a height of 450 from the wall and the freestream velocity is set to 24 m/s. The hotwire is traversed to a final height of 50 mm. The resulting boundary layer is fi equation for a turbulent boundary layer resulting in mean shear stress values of 1. 1 1 Pa and 1.06 Pa, respectively. These fits are shown in Figure 6 20 The sensor reports a mean wall shear stress of 1.1 Pa. Unfortunatel y, the first generation Synch MOD/DMOD system was destroyed during testing due to a faulty power supply, so no dynamic roughness boundary layer measurements were completed.

PAGE 215

215 Figure 6 20 The velocity profile measured at GALCIT shown in wall units. 6.2.2 TSV Sen sor Characterization Due to the fabrication issues discussed in C hapter 5, the TSV sensors cannot be mechanically characterized, however the electrical properties are still of possible interest. The structure is shown in Figure 6 2 1 with predicted impeda nces indicated. Ideally, an impedance measurement when the electrodes are shorted together would result in an approximation of the parasitic impedances of the TSVs. On each TSV die are sixteen TSVs. While not all of these TSVs are intended for use in th e final structure the numerous TSVs per die increase the chance that one was faulty as shown in C hapter 5. A TSV that is not fabricated correctly creates an additional conduction path to the handle wafer that is at worst resistive and at best a diode. I n order to make truly meaningful measurements to characterize the TSV performance, a new set of TSV wafers must be fabricated. To validate the design, TSVs are dice off of a

PAGE 216

216 floating element design, and the resulting impedance is measured. The results of that measurement are shown in Figure 6 21. Figure 6 21 The impedance of a floating element TSV device after the TSVs are removed by dicing The impedance measurement is conducted by exciting the s ensor with a 500 mV sinusoid of varying frequency in order to build up this C f curve. The sensor is measured over a bandwidth of 0.5 MHz to 10 MHz as the modulated sensor output will fall within that frequency range. In the results, the mis match due t o fabrication inaccuracies is clearly seen and is 0.1 pF. Additionally, the impedance appears to roll off with frequency. This phenomenon was previously noted by Chandrasekharan [37] and was confirmed by Sells [34] as a phenomenon relating to the presence of the bulk s ilicon beneath the sensor structure.

PAGE 217

217 6.2.3 Second Generation Synch MOD/DMOD Characterization While the fabrication of the TSV devices was not useful for integration into a completely new sensor system, the previous generation of sensors are integrated with the new packaging technology and Synch MOD/DMOD in order to validate those portions of the design work. 6.2.3.1 Dynamic flow characterization The sensor is again installed into the acoustic plane wave tube in order to determine the dynamic sensitivity and frequency response function of the sensor. The data is acquired using a n NI PXI 5122 analog to digital converter housed in an NI PXI 1045 chassis. The sensor and microphone data are simultaneously acquired and the spectra of the ac shear stress is estimated u sing the parameters in Table 6 5 The movable backplate configuration described in Section 6.1.2.2 is used to measure sensitivity of the sensor system to both shear stress and dynamic pressure as well as estimate the frequency response function of the sensor t o shear stress and separately to pressure. Table 6 5 The sampling param eters used for the acquisition of the frequency response function Parameter Value Sampling Frequency 20 kHz Number of Samples per Block 20,000 Number of Blocks 100 Window Uniform Overlap 0% The sensitivity to shear stress is measured by using the gradient descent algorithm to set the backplate such that the sensor is located at a pressure minimum when the tube is excited at The sound pres sure level is increased in order to

PAGE 218

218 build up a sensitivity, shown in Figure 6 2 2 as is 6.5 mV/Pa. The bias is set by the on board o scillation and gain circuit to 8 Vac. Figure 6 22. The shear stress sensitivity acquired using the variable back plate. Th e frequency response function of the sensor with respect to an input shear stress is determined by sweeping the excitation frequency from to in steps. For each frequency, the plane wave tube is excited with a single tone and the termination is moved using the gradient descent algorithm. The transfer function between the shear stress predicted by the pressure seen by the microphone in t he travelling boundary and the shear s tress seen by the shear stress sensor usin g the sensitivity in Figure 6 22 is estimated. This transfer function is shown in Figure 6 2 3 in magnitude and phase along with the coherence between the sensor and microphone signals. The expected resonance is d emonstrated by the peak in the output magnitude of the sensor and the phase shift. While there is expected to be large error

PAGE 219

219 around resonance [89] the improved coherence (>0.98) between the sensor output and microphone signals estimate little error. Figure 6 23. The measured frequency response function of the sensor system to an input shear stress using the variable back plate plane wave tub e set up The sensitivity and frequency response function for a dynamic pressure input are tested using the same experimental setup. The same gradient descent algorithm is used in order to place the wall such that the sensor is located at a pressure null and then the frequency is doubled in ord er to change the standing wave pattern such that the sensor is at a pressure maxima and a velocity minimum. The estimated pressure sensitivity is shown in Figure 6 2 2 Comparing Figure s 6 2 2 and 6 2 4 it is clear th at the minimum detectable pressure is orders of magnitude higher than the minimum

PAGE 220

220 detectable shear stress. The sensitivity to pressure is however this may also be due to additional error sources observed in floating element se nsors [99] Figure 6 2 4 The sensitivity of the sensor to dynamic pressure. The frequency response function of the sensor output with respect to a pressure input can also be determined using this method, but is more limited. Again, the termination is set using the control algorithm and then doubled in order to set the sensor at a pressure maximum instead of a pressure minimum. The coherence reduction near the first resonant mode of the sens or provides a large estimate of error around the primary resonance of the structure. Additionally, t he frequency respon se function shown in Figure 6 25 does no t align with the expected first order system described in C hapter 4. There are two likely expla nations for this behavior. First, the sensitivity of the device acting as a pressure sensor is significantly lower than the device as a shear stress sensor. In order to exceed the minimum detectable signal in pressure the plane wave tube is driven to at the

PAGE 221

221 termination This high drive signal creates harmonic distortion in the tube at the harmonics of the excitation signal, so while the sensor is at a pressure maxima for a given frequency f, it is at a velocity maxima for the second harmonic of that frequency. Particularly as the sensor approaches resonance the motion of the sensor is not purely out of plane. This also explains why the coherence remains near unity, as the microphone will see this non linearity as well. An ad ditional source of acoustic error is scattering. As the sensor is a released structure there are finite gaps in the sensor surface. These gaps possibly result in acoustic scattering and transverse forces. Figure 6 25. The measured frequency response fu nction when the sensor is placed at a velocity minimum and pressure maximum.

PAGE 222

222 Secondly non idealities in the mechanical sensor structure could lead to coupled motion. The DRIE etch does not result in perfectly straight tether side walls. Given imperfect tethers out of plane displacement results in slight in plane motion. 6.2.3.2 Environmental characterization The sensor system is designed to be implemented in multiple flow facilities ranging from flow cells sourced with clean dry air to a large tunnel in a garage environment Therefore, the impact of changes in the ambient environment on the sensor performance must be quantified. In an attempt to decouple environmental parameters, the sensor is first placed in an environment with nominally controlled humidity an d swept temperature, and then in an environment with nominally controlled temperature and swept humidity. Prior to both tests, the sensor is held at and relative humidity for 30 minutes before each t est begins. The sensor, packaged in the aluminum housing with the immediate interface electronics attached, is placed into the chamber, and cabling is run out of a port to the Synch MOD/DMOD circuitry. The Synch MOD/DMOD box is not intended to be co loca ted with the sensor therefore it is not placed in the chamber. Both Pyrex and TSV devices are tested with the second generation Synch MOD/DMOD circuitry. The ESPEC environmental chamber is controlled using GPIB and reports the chamber temperature and rel ative humidity. The sensor data is acquired using a NI PCI 6034E data acquisition system with a BNC 2110 breakout box. The sampling parameters and timing is shown in Table 6 6 First, the temperature sweep is performed from to in increments, while controlling the relative humidity at 30%. In the case of the Pyrex sensor and the TSV sensor there is little dependence on changes in temperature, as shown in Figure s

PAGE 223

223 6 26 and 6 27, respectively. Horizontal error bars are also plotted indicating the 95% confidence interval of the data. Table 6 6. The sampling parameters used with the environmental chamber Parameter Value Sensor s ampling frequency 50 Hz Number of samples per block 50 Dwell between blocks 30 seconds Acquisition time at a given condition 10 minutes Following temperature calibration, the sensor is exposed to varying relative humidity. The same sampling parameters are used and the temperature is held at while the humidity is swept from to The results for the Pyrex device and the TSV device are shown in Figure s 6 28 and 6 29, respectively. The error in shear stress mea surement due to environmental drift is quantified as ( 6 22 ) The predic ted full scale output is generated by using the sensitivity of the Pyrex sensors in the second generation packaging and interfaced with the second generation synch MOD/DMOD and the predicted full scale shear stress input of 5 Pa. The errors are quantified in Table 6 7. Table 6 7. Results of the environmental calibration. Measured Quantity Maximum dc Error [mV] Error [dB] Pyrex. Temperature 0.6 0.16 Pyrex. Humidity 0.7 0.19 TSV. Temperature 0.5 0.13 TSV. Humidity 0.8 0.22

PAGE 224

224 Figure 6 2 6 Temperatu re calibration of Pyrex device.

PAGE 225

225 Figure 6 2 7 Temperature calibration of TSV device.

PAGE 226

226 Figure 6 2 8 Humidity calibration of Pyrex device.

PAGE 227

227 Figure 6 2 9 Humidity calibration of TSV device with 95% confidence intervals shown 6.3 Summary In this chapter, the sensor system was built and tested in two generations. First a silicon on Pyrex sensor was interfaced with the first generation synch MOD/DMOD system and calibrated using a laminar flow cell to estimate mean sensitivity, an acoustic

PAGE 228

228 plane wave tube with a sound hard boundary to estimate dynamic sensitivity, and an acoustic plane wave tube with an anechoic termination to estimate frequency response function. The sensor system demonstrated a sensitivity of 10.9 mV/Pa and a resonance of 4.7 kHz. After calib ration the silicon on Pyrex sensor and first generation synch MOD/DMOD was demonstrated in three wind tunnel facilities one at the University of Florida, one at NASA LaRC, and one at GALCIT In the second generation of testing, two new sensor calibratio n techniques were demonstrated and a new generation of synch MOD/DMOD was constructed. The first new calibration technique was designed to improve estimation of the frequency response function of the sensor and the second to extend sensor calibrations int o the higher order effects of environmental impacts on sensor performance The second generation synch MOD/DMOD was then constructed and interfaced with a silicon on Pyrex sensor for fluidic and environmental characterization The sensitivity of the sensor system was demonstrated as 6.5 mV/Pa. An improved frequency response function estimate was also acquired using the new variable back plate set up demonst rating a sensor resonance of 4.9 kHz and a phase shift of 180 degrees The sensitivity of the sensor system to changes in ambient temperature or relative humidity was estimated to be less than 0.2dB full scale. Additionally, the second generation synch MOD/DMOD was interfaced with the TSV sensors in order to validate that the humidity sensitivity of th e device was eliminated by the hydrophobic coating deposited during the floating element definition. The resulting sensitivity to changes in relative humidity was estimated as 0.22 dB full

PAGE 229

229 scale, indicating that the hydrophobic coating was effective in mi tigating changes in sensor output due to environmental changes. While the second generation synch MOD/DMOD was overall successful, there are many opportunities for improvement in the current state of the senso r system as well as advancement. In the next chapter some design changes are presented for the next generation of sensor systems.

PAGE 230

230 CHAPTER 7 CONCLUSIONS AND FUTU RE WORK This final chapter summarizes the contributions of this work and provides some recommendations for future efforts with this sensor. 7 .1 Conclusions The time resolved direct measurement of mean and dynamic wall shear stress remains one of the most elusive but important measurements in fluid dynamics. By extending upon two previous generations developed at the University of Florida, as described in C hapter 1, a shear stress measurement system capable of use in a wind tunnel environment was realized. The design of the sensor die was extended in two ways and the fabrication of the newly designed sensor die was attempted. First, the mechanical model of the sensor was extended to include the response to out of plane forcing. Secondly, the floating element size and bandwidth were scaled in order to meet scaling requirements for a turbulent boundary layer. These additional components o f the sensor modeling were fed into an optimization, resulting in multiple designs for fabrication. The fabrication of these optimal designs, including through silicon vias, was attempted and while unsuccessful resulted in a greater understanding of the t echnical challenges of this sensor production. In order to enable the use of the sensor in a wind tunnel facility robust packaging and interface circuitry were developed. The new packaging minimizes packaging stress while decreasing the overall size of th e installation to a 0.5 inch diameter, 0.75 inch long cylinder. The interface circuitry was developed making the sensor system a stand alone instrument.

PAGE 231

231 Two new calibration techniques were demonstrated in this work. The first enables a better estimation of the frequency response function of the shear stress sensor as compared to previous techniques. Additionally, the environmental impact on the sensor was characterized. The sensor system was then demonstrated in three different wind tunnel facilities The mean sensor data was compared to multiple velocity profile based estimations of mean shear stress and the dynamic data was compared to near wall hotwires. Finally the sensor was demonstrated in three different wind tunnel facilities. The ability of the sensor to discern between laminar and turbulent flow conditions for the same freestream velocity emphasized the importance of direct measurement. Additionally, the dynamic response of the sensor was demonstrated beyond the application of broad band tu rbulence and is able to detect the shedding frequency of a cylinder upstream of the sensor. The multitude of comparative measurements and flow facilities also demonstrated the success of the sensor packaging and circuitry as an adoptable wind tunnel instr ument. The performance of this sensor system compared to prior work is shown in Table 7 1. Table 7 1 Comparison of this work with selected prior MEMS floating element based shear stress measurement methods Sensor System Element Size [mm] Shear Stress R ange [Pa] Sensitivity [mV/Pa] Calibration Type Meloy 1 6.5e 3 3 6.5 11 ac/dc Sells [35] 1 4e 3 3.9 2729 ppm/Pa dc Chandrasekharan [29] 2 14.9e 6 1.9 7.66 ac Zhe [32] 3.2 0.04 .16 337 dc Pa dmanabhan [23] 0.5 1.4e 3 10 32 0 ac/dc Schmidt [101] 0.5 0.01 13 0.47 dc

PAGE 232

232 These results demonstrate that use of floating element shear stress sensors in government and academic wind tunnel environments is feasible as an instrument grade shear stress measurement system is feasible. There are still several points of the sensor and circuitry design that need improvement. 7.2 Recommendations for Future Work There are several areas that would enhance the senso r system performance greatly. Improvements in the sensor design, fabrication, and interface circuitry are discussed in the following sections. 7.2.1 Sensor D esign To improve the sensor design, t he modeling for the pressure sensitivity of the sensor and th e optimization should be reevaluated. The pressure models that were developed were adapted from microphone studies [86] an d do not capture the extent of the perforation of the floating element structure. This may lead to an under prediction of the efficacy of the perforation of the element as a pressure rejection mechanism. The addition of the pressure constraint did not va ry the design space of the sensor significantly. This could be due to the models used, but could also demonstrate that a single objective function does not provide enough control over the design. A multiple objective function optimization would be more c apable of mapping the design space and producing truly optimal designs. 7 .2.2 Sensor F abrication There were two major points of failure; the through silicon vias and the device release. The issue with the through silicon vias is the difficulty of aligning the TSVs through the device layer to the bulk silicon. As the device layer is configured as electrodes, there is no need for the TSVs to continue completely through the wafer.

PAGE 233

233 Instead, the TSVs can extend through the BOX layer during SOI fabrication and the TSVs can simply make contact with the bottom of the device layer. Additionally, the BOX layer in this work was set at which is excessively large. Thinning this oxide layer to or less and using traditional TSV fabrication techniques would also be an improvement. This bonding approach will also assist in the release, as the cavity is formed before bonding the device layer, that will contain the sensor structure, and the bulk silicon that contains TSVs. A cross section of the final structure is shown in Figure 7 1. The difficulty in this design lie s in the quality of the interface between the TSVs and the device layer and in the deep e tch to form the TSVs and minimizing the uncertainty in their p lacement. Figure 7 1 A proposed sensor structure to avoid the issues found during TSV device fabrication. 7 2. 3 Third G eneration S ynch MOD/DMOD and P ackaging As shown in C hapter 3, there is a large source of contamination ass ociated with the power regulation circuitry, though the overall noise floor of the system is reduced from the first generation to the second generation This peak is removed through a redesign of the power distribution circuitry. The second generation of the Synch MOD/DMOD proved that this in package power regulation is required as the design of the system moves forward, however a more optimized power section is needed.

PAGE 234

234 The packaging also requires additional design and consideration. While the cylindrica l aluminum housing is a good initial point, most models and actual applications require thinner form factors. By moving to a smaller form factor buffer amplifier and possible a planar package design this thickness is minimized, but at the expense of possi ble sensor density.

PAGE 235

235 APPENDIX A LUMPED ELEMENT MODEL FOR SHEAR STRESS INP UT Lump ed element modeling provides a computationally simple method of predicting the dynamic response of mechanical structures. In this appendix, the details for the dynamic response of an H bar floating element structure are derived. A.1 Lumped Elements for Sh ear Stress This section will derive in detail the in plane response of an H bar floating element structure. First, the mechanical compliance will be found, followed by the mechanical mass. Finally additional components of the model will be derived, inclu ding the coupling coefficient that describes the transfer of energy from the mechanical structure into the electrical domain. A circuit diagram of the model is shown in Figure A 1. Figure A 1 Full lumped element model of the floating element response t o an input shear stress A.1.1 Lumped Mechanical Compliance The mechanical compliance of the structure is lumped by evaluating the total potential energy of the system,

PAGE 236

236 ( A 1 ) w here e is effort, or the total force, F, acting on the beam and q is displacement, w(x). The to tal force acting on the beam is ( A 2 ) The potential energy of one te ther can then be represented as ( A 3 ) or ( A 4 ) Substituting in for ( A 5 ) or ( A 6 ) To remove the w(x) dependence combine and equate in terms of shear to produce

PAGE 237

237 ( A 7 ) This is used to simplify the integration to give ( A 8 ) and an i ntegration over x results in ( A 9 ) The total system potential energy will be four times the above as until now only one tether has been considered. The total potential energy is described by ( A 10 ) From this the compliance is found,

PAGE 238

238 ( A 11 ) A.1.2 Lumped Mechanical Mass The mass of a system is lumped by evaluating the total kinetic energy of the moving beam and equating it to the kinetic energy stored in a mass ( A 12 ) where p represents momentum and f represents flow. For this floating element sensor, kinetic energy is stored in both the tethers and the floating element. The total lumped mass is found by finding the kinetic energy stored in each structure T his is achieved by finding the lumped element associated with the floating element and the tethers seperately by the above equation and then s umming those two masses ( A 13 ) The flow in this is velocity that is represented as ( A 14 ) and the velocity at is ( A 15 ) C ombining these to remove dependence on shows

PAGE 239

239 ( A 16 ) Considering a differential element of the tether that has a differential mass ( A 17 ) t he momentum of that differential element is ( A 18 ) The differential kinetic co energy is therefore ( A 19 ) or ( A 20 ) or ( A 21 ) Subst ituting for v(x) ( A 22 ) or ( A 23 ) Equating this to the generalized form for kinetic co energy the lumped mass of the tethers is ( A 24 )

PAGE 240

240 Again, this is only considering one tether. In order to fin d the total kinetic co energy the above value is multiplied by 4 to give ( A 25 ) The kinetic co energy of the floating element is more straight forward as ( A 26 ) Combining these two masses the total lumped mass of the system is ( A 27 ) Substituting for w(L t ) and evaluating the integral using MATLAB ( A 28 ) A.2 Two Port Model In this section, the method where transduction is accounted for in the lumped element model is discussed. The characteristic equations of a linear transducer are ( A 29 ) In a reciprocal transducer In a direct transducer

PAGE 241

241 These equations are represented as a transformer with either an open mechanical impedance and free electrical impedance or a blocked electrical impedance and a shorted mechanical impedance as seen in Figure A 2. The impedances are r elated by ( A 30 ) and ( A 31 ) where ( A 32 ) Figure A 2 Generalize circuit representation for a two port transducer model For this implementation, the sensor is modeled as a parallel plate capacitor with varying gap, g. Nominally the gap is and the change in gap is represented as ( A 33 ) The capacitance as a function of time can therefore be represented as ( A 34 )

PAGE 242

242 where is the capacitance when the plate has zero displacement. The total force on the movable plate is the sum of the electrostatic for ce and the mechanical restoring force ( A 35 ) The electrostatic fo rce of two plates with constant charge is ( A 36 ) The voltage due to this charge is expressed by ( A 37 ) The mechanical restoring fo rce is related to the compliance of the system as ( A 38 ) This bri ngs the total force to ( A 39 ) The equations for force and voltage are linearized by assuming a small perturbation and then representing the resulting equations as a two port network in terms of Fourier components to ( A 40 ) This shows that the transducer is reciprocal, but not direct. For a reciprocal transducer the impedance transformation factor is

PAGE 243

243 ( A 41 ) or ( A 42 ) In order to fit to the two port chosen must be transformed to a blocked electrical impedance by the electromechanical cou pling factor ( A 43 ) So C EB is trans formed into a series impedance as ( A 44 )

PAGE 244

244 APPENDIX B LUMPED ELEMENT MODEL FOR PRESSURE INPUT Lumped element modeling provides a computationally simple method of predicting the dynamic response of mechanical structures. In this appendix, the details for the dynamic response of an H bar floating element structure are derived. B.1 Lumped Element Parameters This section will derive in detail the out of pla ne response of an H bar floating element structure. First, the mechanical compliance will be found, followed by the mechanical mass. Finally additional components of the model will be derived, including the coupling coefficient that describes the transfe r of energy from the mechanical structure into the electrical domain. A circuit diagram of the model is shown in Figure B 1. Figure B 1 Circuit representation of the lumped element model for the out of plane response of an H bar structure

PAGE 245

245 B.1.1 Lumped Mechanical Compliance The derivation of the lumped compliance given a pressure input closely follows the method used to derive the response to shear. Under pressure, as under shear, the floating element is considered perfectly rigid. This means that each pair of tethers are viewed as a clamped clamped beam with the floating element motion represented as a point force in the middle. The force on one set of tethers with respect to pressure, p, is represented as a distributed force, Q, and a point force, P, that is the result of the floating element ( B 1 ) From the analysi s of beam deflection the total displacement equation with respect to pressure is ne arly identical to that of shear ( B 2 ) w ith the exception that the expression for the moment of inertia changes to ( B 3 ) Making the displacement equation with respect to pressure ( B 4 ) w here maximum displacement occurs at x=L t ( B 5 ) The displacement equation in terms of this maximum displacement is

PAGE 246

246 ( B 6 ) Pressure in terms of the displacement equation is ( B 7 ) In order to find the lumped mechanical compliance of the structure with respect to incident pressure the potential co energy is evaluated as was done in the case for a response to shear. Following the same procedure results in ( B 8 ) Substituting in for pressure sho ws ( B 9 ) Integrating over and simplif ying produces ( B 10 ) and integrates to ( B 11 ) or

PAGE 247

247 ( B 12 ) The negative sign is just a function of the sign convention chosen when choosing the deflection direction and is disregarded. By comparing thi s to the original expression for potential energy ( B 13 ) B.1.2 L umped Mechanical Mass The lumped mass of the sensor response with respect to pressure directly follows the derivation for that of shear. The final solution for lumped mass is repeated below for thoroughness. ( B 14 ) B.1.3 Lumped Acoustic Compliance The lumped approximation for cavity compliance is [41] is ( B 15 )

PAGE 248

248 w here V is the volume of the cavity. B.1. 4 Lumped Acoustic Dissipation The squeeze film damping of the fluid moving through the perforations in the floating element and the spaces between the comb fingers will act as a resistive element. Following the procedure used to develop a perforated diaphragm capacitive microphone that uses models developed by Skvor [39] and Homentcovschi [40] to predict the resistance, ( B 16 ) where is the number of holes in the element and is the ratio of the area of the holes to the area of the floating element. B. 2 Two Port Model The characteristic equations of a li near transducer are ( B 17 ) In a reciprocal transducer In a direct transducer For this implementation, the sensor is modeled as a parallel plate capacitor with varying overlapping area Nominally the area is and the change in area is r epresented as ( B 18 ) Where is the width of the overlapping area and is the height of the overlapping area, that is what is changing in time. The capacitance as a function of time is

PAGE 249

249 ( B 19 ) where is the capacitance when the plate has zero displacement. The total force on the movable plate is the sum of the electrostatic force and the mechanical restoring force ( B 20 ) The electrostatic force of two plates with constant charge is ( B 21 ) The voltage due to this charge is expressed by ( B 22 ) The mec hanical restoring force is related to the compliance of the system as ( B 23 ) This brings the total force to ( B 24 ) The equations f or force and voltage are linearized by assuming a small perturbation and then representing the resulting equations as a two port network in terms of Fourier components to ( B 25 )

PAGE 250

250 This shows that the transducer is reciprocal, but not direct. For a reciprocal transducer the impedance transformation factor is ( B 26 ) In order to fit to the two port chosen must b e transformed to a blocked electrical impedance by the electromechanical coupling factor ( B 27 ) s o C EB is trans formed into a series impedance as ( B 28 )

PAGE 251

251 APPENDIX C DERIVATION OF PARASI TI C CONTRIBUTIONS FOR UNITY GAIN AMPLIFIER The output voltage of this system is found using superposition. The effects of the amplifier parasitics will become evident in this analysis. In this representation represents parasitic capacitances of bondpads, packaging, and any other capacitance that does not contribute to the sen sor or is due to the amplifier input stage, represents the input capacitance of the chosen op amp and is specified by the manufac turer, and is a discrete resistance value that is required in order for the op amp to define a quiescent point around where it operates. First, consider the contribution of the positive bias voltage on the output voltage. Con sidering the positive bias only results in ( C 1 ) Figure C 1 Contribution of positive bias to output

PAGE 252

252 Now considering contributions from the negative bias voltage Figure C 2 Contribution of negative bias to output ( C 2 ) Combining these equations results in ( C 3 ) or ( C 4 ) This shows the output voltage has a high pass characteristic based on device capacitance and bias resistance. Past the system cut on, the output voltag e simplifies to ( C 5 )

PAGE 253

253 Now considering that and is described as and equation C.5 is further reduced to ( C 6 ) or ( C 7 )

PAGE 254

254 APPENDIX D DERIVATION OF NOISE EQUATION FOR UNIT Y GAIN AMPLIFIER There are three noise sources present; the thermal noise of a required external bias resistor, the input referred voltage noise of the amplifier, and the current noise of the amplifier. Again, superposition is used to determine the contr ibution of each source. Figure D 1 Total noise model for a unity gain amplifier with bias resistor First, consider the voltage noise of the amplifier. Figure D 2 Noise circuit for amplifier voltage noise

PAGE 255

255 In this case th e impedance at the input of the amplifier does not contribute to the output and Next, consider the current noise of the amplifier. Figure D 3 Noise circuit for amplifier current noise In this cas e, will shape the output voltage of the amplifier due to the input noise source. The noise current, flows through the impedance seen at the input of the op amp, ( D 1 ) creating a voltage at the non inverting op amp input. T he output due to the current noise of the op amp is ( D 2 ) The final noise source is the therm al noise of th e bias resistor and is ( D 3 )

PAGE 256

256 Figure D 4 Noise circuit for resistor thermal noise

PAGE 257

257 APPENDIX E PARTS LIST AND FULL SCHEMATIC FOR FIRST GENERATION SYNCH MOD/DMOD Table E 1 Parts list for the first generation Synch MOD/DMOD circuitry. Designator Description Value Digikey Part No Radj_RH po tentiometer 100k 3310Y 001 204L ND Radj_SENSOR potentiometer 100k 3310Y 001 204L ND LTC1563_1 low pass filter 4 th order LTC1563 2CGN#PBF ND LTC1563_2 low pass filter 4 th order LTC1563 2CGN#PBF ND LTC1563_3 low pass filter 4 th order LTC1563 2CGN#PBF ND LTC1563_4 low pass filter 4 th order LTC1563 2CGN#PBF ND HC04 Inverter Inverter 568 3948 5 ND D1 Zener Diode Vz = 4.7V 568 3832 1 ND D2 Zener Diode Vz = 4.7V 568 3832 1 ND AD8022_1 2 Channel Op Amp AD8022 AD8022ARZ ND AD8022_2 2 Channel Op Amp A D8022 AD8022ARZ ND AD8022_3 2 Channel Op Amp AD8022 AD8022ARZ ND AD8022_4 2 Channel Op Amp AD8022 AD8022ARZ ND AD8022_5 2 Channel Op Amp AD8022 AD8022ARZ ND AD8022_6 2 Channel Op Amp AD8022 AD8022ARZ ND AD8022_7 2 Channel Op Amp AD8022 AD8022ARZ ND A D8022_8 2 Channel Op Amp AD8022 AD8022ARZ ND AD8022_9 2 Channel Op Amp AD8022 AD8022ARZ ND ADG1633 SPDT IC switch ADG1633 ADG1633BCPZ REEL7CT ND 5Vregulator 5V fixed pos. regulator LM7805 LM7805ACT ND 5Vregulator 5V fixed neg. regulator LM7905 LM7905 CTFS ND C+ Electrolytic Cap 10uF P5134 ND C Electrolytic Cap 10uF P5134 ND +10V BNC to PCB 50ohm A33798 ND 10V BNC to PCB 50ohm A33798 ND Output_SENSOR BNC to PCB 50ohm A33798 ND Input_SENSOR BNC to PCB 50ohm A33798 ND Input_RH BNC to PCB 50ohm A3 3798 ND Output_RH BNC to PCB 50ohm A33798 ND +Bias BNC to PCB 50ohm A33798 ND Bias BNC to PCB 50ohm A33798 ND +Bias_RH BNC to PCB 50ohm A33798 ND Bias_RH BNC to PCB 50ohm A33798 ND Input_Sine BNC to PCB 50ohm A33798 ND Cadj_RH Variable Cap 10 120p F 490 1957 ND

PAGE 258

258 Table E 1. Continued Designator Description Value Digikey Part No Cadj_SENSOR Variable Cap 10 120pF 490 1957 ND Cadj1 ceramic cap 100pF 478 3141 1 ND Cadj2 ceramic cap 100pF 478 3141 1 ND C1 0805 surface mount ceramic cap 0.1uF 490 173 4 1 ND C2 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C3 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C4 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C5 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C6 0805 surface mount cerami c cap 0.1uF 490 1734 1 ND C7 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C8 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C9 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C10 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C11 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C12 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C13 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C14 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C15 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C16 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C17 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C18 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C19 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C20 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND

PAGE 259

259 Table E 1. Continued Designator Description Value Digikey Part No C22 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C23 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C24 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C25 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C26 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C27 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C29 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C30 0805 su rface mount ceramic cap 0.1uF 490 1734 1 ND C31 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C32 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C33 0805 surface mount ceramic cap 0.1uF 490 1734 1 ND C34 0805 surface mount ceramic cap 0.1uF 49 0 1734 1 ND C21 0805 surface mount ceramic cap 1.9nF 478 5546 1 ND C28 0805 surface mount ceramic cap 1.9nF 478 5546 1 ND R5 0805 surface mount metal film resistor 100 P100DACT ND R6 0805 surface mount metal film resistor 100 P100DACT ND R16 0805 surf ace mount metal film resistor 100k P100KDACT ND R17 0805 surface mount metal film resistor 100k P100KDACT ND R18 0805 surface mount metal film resistor 100k P100KDACT ND R22 0805 surface mount metal film resistor 100k P100KDACT ND R1 0805 surface mount metal film resistor 10k P10KDACT ND

PAGE 260

260 Table E 1. Continued Designator Description Value Digikey Part No R2 0805 surface mount metal film resistor 10k P10KDACT ND R3 0805 surface mount metal film resistor 10k P10KDACT ND R4 0805 surface mount metal fil m resistor 10k P10KDACT ND R11 0805 surface mount metal film resistor 10k P10KDACT ND R12 0805 surface mount metal film resistor 10k P10KDACT ND R13 0805 surface mount metal film resistor 10k P10KDACT ND R14 0805 surface mount metal film resistor 10k P 10KDACT ND R15 0805 surface mount metal film resistor 10k P10KDACT ND R19 0805 surface mount metal film resistor 10k P10KDACT ND R20 0805 surface mount metal film resistor 10k P10KDACT ND R21 0805 surface mount metal film resistor 10k P10KDACT ND R25 0805 surface mount metal film resistor 10k P10KDACT ND R30 0805 surface mount metal film resistor 10k P10KDACT ND R39 0805 surface mount metal film resistor 10k P10KDACT ND R44 0805 surface mount metal film resistor 10k P10KDACT ND R32 0805 surface mou nt metal film resistor 150k P150KDACT ND R34 0805 surface mount metal film resistor 150k P150KDACT ND R36 0805 surface mount metal film resistor 150k P150KDACT ND R46 0805 surface mount metal film resistor 150k P150KDACT ND R48 0805 surface mount metal film resistor 150k P150KDACT ND R50 0805 surface mount metal film resistor 150k P150KDACT ND

PAGE 261

261 Table E 1. Continued Designator Description Value Digikey Part No R7 0805 surface mount metal film resistor 1k P1.0KDACT ND R8 0805 surface mount metal film resistor 1k P1.0KDACT ND R9 0805 surface mount metal film resistor 1k P1.0KDACT ND R10 0805 surface mount metal film resistor 1k P1.0KDACT ND R29 0805 surface mount metal film resistor 10k P10KDACT ND R43 0805 surface mount metal film resistor 10k P10 KDACT ND R23 0805 surface mount metal film resistor 20k P20KDACT ND R26 0805 surface mount metal film resistor 20k P20KDACT ND R27 0805 surface mount metal film resistor 20k P20KDACT ND R28 0805 surface mount metal film resistor 20k P20KDACT ND R37 08 05 surface mount metal film resistor 20k P20KDACT ND R40 0805 surface mount metal film resistor 20k P20KDACT ND R41 0805 surface mount metal film resistor 20k P20KDACT ND R42 0805 surface mount metal film resistor 20k P20KDACT ND R31 0805 surface mount metal film resistor 250k P240KDACT ND R33 0805 surface mount metal film resistor 250k P240KDACT ND R45 0805 surface mount metal film resistor 250k P240KDACT ND R47 0805 surface mount metal film resistor 250k P240KDACT ND R24 0805 surface mount metal f ilm resistor 90k P91KDACT ND R35 0805 surface mount metal film resistor 90k P91KDACT ND R38 0805 surface mount metal film resistor 90k P91KDACT ND R49 0805 surface mount metal film resistor 90k P91KDACT ND

PAGE 262

262 Figure E 1 Sch ematic for the first generation Synch MOD/DMOD circuitry.

PAGE 263

263 APPENDIX F PARTS LIST AND FULL SCHEMATIC FOR SECOND GENERATION SYNCH MOD/DMOD T able F 1 Parts list for the second generation Synch MOD/DMOD circuitry. Function ID Value Supplier Supplier PN Colpi tts Oscillator AD8009 AD8009 Digikey AD8009ARZ ND R1 1k Digikey P1.00KCCT ND R2 2k Digikey P2.00KCCT ND C1 10n Digikey 490 1664 1 ND C2 10n Digikey 490 1664 1 ND L 5u Digikey 513 1482 2 ND C3 .1u Digikey 490 1673 1 ND C4 .1u Digikey 490 1673 1 ND Oscillator Gain Stage AD8022_1 AD8022 Digikey AD8022ARZ ND R3 10k Digikey P10.0KCTR ND R4 10k Digikey P10.0KCTR ND Pot1 100k Digikey 3386P 103LF ND C5 .1u Digikey 490 1673 1 ND C6 .1u Digikey 490 1673 1 ND Buffer/Inverter w Gain Adjust ADA 4004 4_1 ADA4004 4 Digikey ADA4004 4ARZ ND R5 1k Digikey P1.00KCCT ND R6 1k Digikey P1.00KCCT ND Pot2 10k Digikey 3362P 103LF ND C7 .1u Digikey 490 1673 1 ND C8 .1u Digikey 490 1673 1 ND Switch Control AD8022_2 AD8022 Digikey AD8022ARZ ND R7 1 00 Digikey P100CCT ND R8 1k Digikey P1.00KCCT ND R9 100 Digikey P100CCT ND R10 10k Digikey P10.0KCTR ND R11 3k Digikey P3.0KCCT ND R12 10k Digikey P10.0KCTR ND Cadj 10p 120p Digikey 490 1957 ND D1 4.7V Zener Diode Digikey 568 3832 1 ND inv SN74AHCT1G14 Digikey 296 1114 1 ND C9 .1u Digikey 490 1673 1 ND C10 .1u Digikey 490 1673 1 ND

PAGE 264

264 Table F 1. Continued Function ID Value Supplier Supplier PN HP filter w/adj gain, LP filter, buffer/inverter for switch ADA4004 4_2 ADA4004 4 Digikey ADA40 04 4ARZ ND R13 100 Digikey P100CCT ND R14 100 Digikey P100CCT ND Pot3 1k Digikey 3362P 102LF ND C11 18nF Digikey 490 1657 1 ND R15 100 Digikey P100CCT ND R16 100 Digikey P100CCT ND C12 .1u Digikey 490 1673 1 ND C13 .1u Digikey 490 1673 1 ND LTC1560 LTC1560 Linear LTC1560 C14 .1u Digikey 490 1673 1 ND C15 .1u Digikey 490 1673 1 ND C16 .1u Digikey 490 1673 1 ND switch DG419L DG419L Mouser 781 DG419LDY E3 C17 .1u Digikey 490 1673 1 ND C18 .1u Digikey 490 1673 1 ND Low Pass Filter LTC1563 LTC1563 Digikey LTC1563 2CGN#PBF ND R17 249k Digikey P249KCCT ND R18 249k Digikey P249KCCT ND R19 150k Digikey P150KCCT ND R20 150k Digikey P150KCCT ND R21 90.9k Digikey P90.9KCCT ND R22 150k Digikey P150KCCT ND C19 .1u Digikey 490 16 73 1 ND C20 .1u Digikey 490 1673 1 ND +5Vdc LM7805 LM7805 Digikey LM805CT ND Cp1 1u Digikey 445 1589 1 ND Cp2 1u Digikey 445 1589 1 ND 5Vdc LM7905 LM7905 Digikey LM7905CTFS ND Cp3 1u Digikey 445 1589 1 ND Cp4 1u Digikey 445 1589 1 ND

PAGE 265

265 Table F 1. Continued Function ID Value Supplier Supplier PN 12Vdc switching MC34063A MC34063A Digikey 296 17765 1 ND Cp5 1000u (polar) Digikey 718 4016 1 ND Cp6 1500pF Digikey 490 3245 1 ND Cp10 100uF (polar) Digikey 718 1128 1 ND Dp1 1N5819 Digikey 1N8 19HW FDICT ND Lp1 88u Mouser 704 CMS3 4 R Rp3 0.24 Digikey 311 .24SCT ND Rp1 953 Digikey P53CCT ND Rp2 8.2k Digikey P8.20KCCT ND 12VDC LDO LT1964 LT1964 SD Digikey LT1964ES5 BYP#TRMPBFCT ND Cp7 1u Digikey 445 1589 1 ND Cp8 1000u (polar) Digik ey 718 4016 1 ND Cp9 0.01u Digikey 490 1664 1 ND Rp4 880 Digikey P887CCT ND Rp5 100 Digikey P100CCT ND +12VDC Power Brick PSAA18U 120 R Mouser 552 PSA A18U 120 dc jack ac/dc converter PJ 002AH SMT Digikey CP 002AHPJCT ND metal box aluminium box L1 04 ND Digikey L104 ND bncs (x7) panel mount 227754 1 Digikey A30562 ND headers (x9) headers 2x1 Digikey A31112 ND wire red wire 20g, multi strand Digikey A1856R 100 ND black wire 20g, multi strand Digikey A1856B 100 ND standoffs (x4) F F stand off 3/ 16" OD, 4 40 thread Digikey 2027K ND M F stand off hex, 4 40 thread Digikey 8714K ND

PAGE 266

266 Figure F 1 Schematic for the second generation Synch MOD/DMOD circuitry.

PAGE 267

267 APPENDIX G PROCESS TRAVELER FOR FABRICATION OF TSV D EVICES In this appendix, the details of device fabrication, including a description of the raw materials used, is given. Each step is shown in Figure G 1 and indicated by a letter a s, which corresponds to a specific step in the process traveler. This fabrication was performed at the Nanoscale Research Facility at the University of Florida. Wafer Details Processing begins with diameter SOI wafer with overall thickness of The devi ce layer is thick and doped with Boron for a resistivity of The buried oxide layer (BOX) is a thick thermal oxide grown on the handle. The handle wafer is thick and doped with Boron for a resistivity of The wafers are purchased from Ultrasil Corporation and shipped to Icemos Technology for fabrication of the TSVs. Following this fabrication there is a oxide on the front side of the wafers and a oxide on the back side of the wafer. The fabrication included in this section assumes wafers at this state of development. Masks 1) Back side Oxide Etch 2) Back side Aluminum Etch 3) Back side Nitride Etch 4) Front side Oxide Etch 5) Front side Aluminum Etch

PAGE 268

268 6) Floating Element Etch Figure G 1 The process flow for fabricating the capacitive shear stress sensors with TSVs (not to scale). Process Steps 1) Clean W afers (a) a. S C1 clean for 10 minutes followed by a triple rinse in deionized (DI) water.

PAGE 269

269 b. SC2 clean for 10 minutes followed by a triple rinse in DI water. 2) Define Back Side Aluminum Pads a. Remove native o xide over TSVs (b) i. Protect front side of wafer 1. HMDS coat wafer. a. 3 minute dehydration bake on hot plate. b. 30 second HMDS vapor dispense. c. 2 minute post bake on hot plate. 2. Spin Shipley 1813 photoresist using Delta 80 on front of waf er 3. Hard bake at 120C for 20 minutes in Despatch oven ii. Spin Photoresist 1. HMDS coat wafer a. 3 minute dehydration bake on hot plate. b. 30 second HMDS vapor dispense. c. 2 minute post bake on hot plate. 2. Spin Shipley 1813 photoresist usin g Delta 80 3. Soft bake photoresist on hot plate for 2 minutes. iii. Align and Expose with Mask 1 1. Front to back alignment to Icemos alignment marks 2. Expose using EVG620 for 2.6 seconds. 3. Develop for 1 minute in AZ 300MIF developer.

PAGE 270

270 iv. Etch oxide. 1. Etch in 6 1 Buffere d Oxide Etch (BOE) for 8 minutes. v. Strip Photoresist. 1. Place in PG Photoresist Remover at 75 C for 15 minut es. 2. Triple Rinse in DI water. b. Deposit and pattern metal pads. i. Protect front side of wafer (c) 1. HMDS coat wafer. a. 3 minute dehydration bake on hot plate. b. 30 second HMDS vapor dispense. c. 2 minute post bake on hot plate. 2. Spin Shipley 1813 photoresist using Delta 80 on front of wafer. 3. Hard bake at 120C for 20 minutes in Despatch oven. ii. HF Dip to remove native oxide 1. Dip in for 30 seconds. iii. Deposit aluminum/silicon 2% (d) 1. Deposit Al/Si 2% using recipe G4_200_5 on the KJL CMS 18 Sputter Deposition tool. iv. Strip Photoresist. 1. Place in PG Photoresist Remover at 75 C for 15 minutes. 2. Triple Rinse in DI water. v. Pattern Aluminum pads (e)

PAGE 271

271 1. Spin Photoresist. a. HMDS coat wafer. i. 3 minute dehydration bake on hot plate. ii. 30 second HMDS vapor dispense. iii. 2 minute post bake on hot plate. b. Spin Shipley 1813 photoresist using Delta 80. c. Soft bake photoresist on hot plate for 2 minutes. 2. Align and Expose with Mask 2. a. Front to back alignment to Icemos alignment marks. b. Expose using EVG620 for 2.6 seconds. c. Develop for 1 minute in AZ 300MIF developer. 3. Etch Al/Si 2%. a. Etch in Transene 80 Type A for 8 minutes while agitating bath vi. Strip Photoresist. (f) 1. Place in PG Photoresist Remover at 75 C for 1 5 minutes. 2. Triple Rinse in DI water. c. Deposit and pattern nitride passivation on back side of wafer i. Deposit of SiN using mn500a.set on the STS 310PC PECVD. (g) ii. Spin Photoresist. 1. HMDS coat wafer. a. 3 minute dehydration bake on hot plate.

PAGE 272

272 b. 30 second HMDS vapor dispense. c. 2 minute post bake on hot plate. 2. Spin Shipley 1813 photoresist using Delta 80. 3. Soft bake photoresist on hot plate for 2 minutes. iii. Align and Expose with Mask 3. (h) 1. Front to front alignment t o alignment marks in bottom metal. 2. Expose using MA6 for 2.6 seconds for a final dose of 3. Develop for 1 minute in AZ 300MIF developer. 4. Hard bake in Despatch oven for 20 minutes at 120C. iv. Etch nitride. (i) 1. Clean edges of wafer usin g acetone 2. v. Strip Photoresist. (j) 1. Place in PG Photoresist Remover at 75 C for 15 minutes. 2. Triple Rinse in DI water. 3) Define Front Side Aluminum Pads a. Remove native oxide over TSVs (k) i. Protect back side of wafer 1. HMDS coat wafer. a. 3 minute dehydration bake on hot plate. b. 30 second HMDS vapor dispense. c. 2 minute post bake on hot plate.

PAGE 273

273 2. Spin Shipley 1813 photoresist using Delta 80 on back of wafer. 3. Hard bake at 120C for 20 minu tes in Despatch oven. ii. Spin Photoresist. 1. HMDS coat wafer. a. 3 minute dehydration bake on hot plate. b. 30 second HMDS vapor dispense. c. 2 minute post bake on hot plate. 2. Spin Shipley 1813 photoresist using Delta 80. 3. Soft bake photoresist on hot plate for 2 minutes. iii. Align and Expose with Mask 4 1. Front to back alignment to Icemos alignment marks. 2. Expose using EVG620 for 2.6 seconds. 3. Develop for 1 minute in AZ 300MIF developer. iv. Etch oxide. (k) 1. Etch in 6 1 Buffered Oxide Etch (BOE) for 8 minu tes. v. Strip Photoresist. 1. Place in PG Photoresist Remover at 75 C for 15 minutes. 2. Triple Rinse in DI water. b. Deposit and pattern metal pads. i. Protect back side of wafer 1. HMDS coat wafer. a. 3 minute dehydration bake on hot plate.

PAGE 274

274 b. 30 second HMDS vapor dispense. c. 2 minute post bake on hot plate. 2. Spin Shipley 1813 photoresist using Delta 80 on back of wafer. 3. Hard bake at 120C for 20 minutes in Despatch oven. ii. HF Dip to remove native oxide (l) 1. Dip in for 30 seconds. iii. Deposit aluminum/silicon 2% (m) 1. Deposit Al/Si 2% using recipe G4_200_5 on the KJL CMS 18 Sputter Deposition tool. iv. Pattern Alumin um pads 1. Protect back side of wafer a. HMDS coat wafer. i. 3 minute dehydration bake on hot plate. ii. 30 second HMDS vapor dispense. iii. 2 minute post bake on hot plate. b. Spin Shipley 1813 photoresist using Delta 80 on back of wafer. c. Hard bake at 120C for 20 minutes in Despatch oven. 2. Spin Photoresist. a. HMDS coat wafer. i. 3 minute dehydration bake on hot plate. ii. 30 second HMDS vapor dispense.

PAGE 275

275 iii. 2 minute post bake on hot plate. b. Spin Shipley 1813 photoresist using Delta 80. c. S oft bake photoresist on hot plate for 2 minutes. 3. Align and Expose with Mask 5 (n) a. Front to back alignment to alignment marks in backside aluminum b. Expose using EVG620 for 2.6 seconds. c. Develop for 1 minute in AZ 300MIF developer. 4. Etch Al/Si 2%. (o) a. Etch in Transene 80 Type A for 8 minutes while agitating bath. v. Strip Photoresist. 1. Place in PG Photoresist Remover at 75 C for 15 minutes. 2. Triple Rinse in DI water. 4) Electrical test and anneal a. Electrically characterize TSV connections using an Agilent 4155C. b. Anneal at 450C in forming gas until ohmic. 5) Define and release f loating e lement a. Protect back side of wafer and attach carrier wafer i. HMDS coat blank test wafer. 1. 3 minute dehydration bake on hot plate. 2. 30 second HMDS vapor dispense. 3. 2 minute post bake on hot plate.

PAGE 276

276 ii. Spin AZ 9260 on test wafer iii. Attach back side of processed wafer to test wafer and bake on a hotplate at 112C for 5 minutes. b. Pattern floating elements i. Spin Photoresist. 1. HMDS coat wafer. a. 3 minute dehydration bake on hot plate. b. 30 second HMDS vapor dispense. c. 2 minute post bake on hot plate. 2. Spin Shipley 1813 photoresist using Delta 80. 3. Soft bake photoresist on hot plate for 2 minutes. ii. Align and Expose with Mask 6 (p) 1. Front to front alignment t o alignmen t marks in aluminum. 2. Expose using MA6 for 19.5 seconds 3. Develop for 1 minute in AZ 300MIF developer. 4. Hard bake in Despatch oven at 120C for 20 minutes 5. Ash hard baked wafer in Anatech barrel asher for 60 seconds at 300W and 300 sccm. c. Etch floating element ( q) i. DRIE for 66 cycles using recipe MELOY_FE ii. Inspect and proceed in increments of 5 cycles if additional etching is needed. d. Floating element release

PAGE 277

277 i. Etch oxide. (r) 1. Etch in 6 1 Buffered Oxide Etch (BOE) for 180 minutes. ii. Strip Photoresist. (s) 1. Place in PG Photoresist Remover at 75 C for 15 minutes. 2. Triple Rinse in DI water. 3. Gently blow dry with nitrogen gun and place in oven at 120 C for 20 minutes to remove additional water from released structures. 4. Ash wafer in Anatech barrel asher for 60 seconds at 300W and 300 sccm. 6) Die separated using ADT dicing saw.

PAGE 278

278 APPENDIX H BOUNDARY LAYER PROFI LES AND NEAR WALL DA TA F ROM NASA LARC In this appendix, all of the turbulent boundary layer data acquired as part of the experiments conducted at NASA LaRC is shown. Sectio n H.1 shows the traversing Hotwire Results, H.2 the Monte Carlo error results for the traversing Hotwire st udy and H.3 the near wall hotwire results. The relevant tunnel conditions for each freestream velocity are given in Table H 1. There are several sources of error associated with the nature of a temperature based measurement [99] in this estimate that could account for the difference in magnitude. First, the exact height of the hotwire is unknown. While the traverse was set to a specific height, slip in the traverse drive is a cause of uncer tainty. Additionally, the plate itself is made of metal. As the wire approaches the plate, heat transfer to the cold metal wall would induce a perceived velocity change [100] Table H 1. Res ults of hot wire profiles at NASA LaRC. [m/s] [c m] [m/s] (Musker) [m/s] (Spalding) C f (Musker) [*1e 3] C f (Spalding) [*1e 3] [*1e4] [*1e3] 16 43.6 0.59 0.61 2.7 2.8 0.76 4.37 1.72 22 46.8 0.78 0.79 2.5 2.6 0.78 6.22 2.45 28 47.2 0.96 0.99 2.4 2.5 0.79 8.04 3.16 33 44.8 1.16 1.18 2.4 2.5 0.69 9.18 3.61 38 44.3 1.33 1.35 2.4 2.5 0.67 10.6 4.17 42 43.4 1.47 1.50 2.4 2.4 0.66 11.9 4.7 H.1 Traversing Hotwire Profiles To obtain these profiles, a Dantek Type 150 hot wire is fouled to the metal plate at LaRC. The hot wire is then moved to a height of using a traverse and attached to an anemometer system. The hot wire probe is then traversed through the boundary layer to a final height of 98 mm. U sing the boundary layer profile to estimate the y

PAGE 279

279 intercept using the no slip condition the real height from the wall is estimated to vary from to or from of 5 to 110. Figure H 1 The hotwire profile and relevant fits for a freestream velocity of 16 m/s. Figure H 2 The hotwire profile and relevant fits for a freestream velocity of 22 m/s.

PAGE 280

280 Figure H 3 The hotwire profile and relevant fits for a freestream velocity of 28 m/s. Figure H 4 The hotwire profile and relevant fits for a freestream velocity o f 33 m/s.

PAGE 281

281 Figure H 5 The hotwire profile and relevant fits for a freestream velocity of 38 m/s. Figure H 6 The hotwire profile and relevant fits for a freestream velocity of 43 m/s.

PAGE 282

282 H.2 Monte Carlo Results for the Traversing Hotwire Study In order to determine the spread in shear stress values given a specific freestream velocity a direct Monte Carlo simulation is used. In this process the velocities within an acquired profile are perturbed within the 95% confidence intervals independently. The re boundary layer. The spread of the resulting shear stress values are plotted against each other for each freestream velocity. Figure H 7 The results of the Monte Ca rlo analysis for a freestream velocity of 16m/s.

PAGE 283

283 Figure H 8 The results of the Monte Carlo analysis for a freestream velocity of 22 m/s. Figure H 9 The results of the Monte Carlo analysis for a freestream velocity of 28 m/s.

PAGE 284

284 Figure H 10 The result s of the Monte Carlo analysis for a freestream velocity of 33 m/s. Figure H 11 The results of the Monte Carlo analysis for a freestream velocity of 38 m/s.

PAGE 285

285 Figure H 12 The results of the Monte Carlo analysis for a freestream velocity of 43 m/s. H.3 N ear Wall Hotwire Spectra As was done in the case of the profiles, a Dantek Type 150 hot wire is fouled to the metal plate at LaRC. The hot wire is then moved to a height of using a traverse and attached to an anemometer system. Near wall data is acquired. Following that acquisition, the hot wire probe is then traversed through the boundary layer to a final height of 98 mm. Using the boundary layer profile to estimate the y intercept using the no slip condition the real height from the wall is estimated to vary from to or from of 5 to 110.

PAGE 286

286 Figure H 13 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 16m/s. Figure H 14 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 22 m/s.

PAGE 287

287 Figure H 1 5 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocit y of 28 m/s. Figure H 16 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 33 m/s.

PAGE 288

288 Figure H 17 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 38 m/s. Figure H 18 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 43 m/s.

PAGE 289

289 H. 4 Near Wall Hotwire Spectra with an Upstream Cylinder After installation of the upstream cylinder, a Dantek Type 150 hot wi re is fouled to the metal plate at LaRC. The hot wire is then moved to a height of using a traverse and attached to an anemometer system. Near wall data is acquired. No profile is acquired while the cylinder is installed and the spread in actual y values is assumed to be similar to the cases without the cylinder. Figure H 19 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 16m/s when the cylinder is installed.

PAGE 290

290 Figure H 2 0 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 22 m/s when the cylinder is installed. Figure H 21 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 28 m/s when the cylinder is installed.

PAGE 291

291 Figure H 22 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 33 m/s when the cylinder is installed. Figure H 23 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 38 m/s when the cylinder is installed.

PAGE 292

292 Figure H 24 The spectral estimates of the shear stress sensor and near wall hotwire for a freestream velocity of 43 m/s when the cylinder is installed.

PAGE 293

293 LIST OF REFERENCES [1] [Online]. Available: http://www.eia.gov/steo/#Global_Crude_Oil_And_Liquid_Fuels. [Accessed: 08 Jan 2012]. [2] M. Gad el Cambridge, MA: Cambridge University Press, 2000, pp. 209 210. [3] R. L. Panton, Incompressible Flow, Chapter 20 3rd ed. Hoboken, N.J.: John Wiley & Sons, Inc, 2005, pp. 498 56 8. [4] J. A. Schetz, Boundary Layer Analysis 1st ed. Englewood Cliffs: Prentice Hall, 1993, pp. 9 16, 176 201. [5] F. M. White, Viscous fluid flow 2nd ed. New York: McGraw Hill, 1991, p. 223. [6] A. D. Young, Boundary Layers 2nd ed. Washington DC: Ameri can Institute of Aeronautics and Astronautics, 1989, p. 269. [7] Journal of Fluid Mechanics vol. 18, pp. 117 143, Ma r. 1964. [8] wire spatial resolution issues in wall Journal of Fluid Mechanics vol. 635, pp. 103 136, Sep. 2009. [9] A. L. Braslow and E. C. Knox, NACA Technical Note 4363: Simplified Method for Determination of Critical Height of Distributed Roughness Particles for Boundary Layer Transition at Mach Numbers from 0 to 5 Langley Field, VA: 1958, pp. 1 19. [10] Academic Publishers, 2001, pp. 125 145. [11] stress Progress in Aerospace Sciences vol. 38, pp. 515 570, 2002. [12] Advances in Fluid Mechanics Measurements pp. 229 261, 1989. [13] Progress in Aerospace Sciences vol. 18, pp. 1 57, 1977.

PAGE 294

294 [14] M. Sheplak, L. 24th AIAA Aerodynamic Measurement Technology and Ground Testing Conference 2004, pp. 1 13. [15] ess Encyclopedia of Aerospace Engineering John Wiley & Sons, Ltd., 2010. [16] 48th AIAA Aerospace Sciences Meeting 2010, no. January, pp. 1 28. [17] B. C. Khoo, Y. Turbulence Measurements in the Very Near Experiments in Fluids vol. 22, pp. 327 336, 1997. [18] f Turbulence in the Viscous Sublayer Using Subminiature Hot Experiments in Fluids vol. 5, pp. 407 417, 1987. [19] Sensors and Actua tors vol. 133, no. 2, pp. 431 438, 2007. [20] Experiments in Fluids vol. 39, no. 2, pp. 464 474, 2005. [21] Shear Stress Measurements Using the Micro Pillar Shear Measurement Science and Technology vol. 19, no. 1, pp. 1 12, 2008. [22] Dimensional, Two Directional Tempor al Wall Shear Stress Distribution with the Micro Pillar Shear 48th AIAA Aerospace Sciences Meeting no. January, 2010. [23] Bonded Floating Element Shear Stress Mic rosensor with Optical Position Sensing Journal of Microelectromechanical Systems vol. 5, no. 4, pp. 307 315, 1996. [24] Calibration of a Micromachined Floating El ement Shear IEEE Transactions on Electron Devices vol. 35, no. 6, pp. 750 757, 1988.

PAGE 295

295 [25] J. Shajii, K. Stress Sensor Using Wafer Journal of Microelect romechanical Systems vol. 1, no. 2, pp. 89 94, 1992. [26] S. Horowitz, T. Chen, V. Chandrasekaran, K. Tedjojuwono, T. Nishida, and L. bonded, floating element shear Technical Digest, Solid State Sensor, Actuator, an d Microsystem Workshop 2004, pp. 13 18. [27] S. Horowitz, T. Chen, V. Chandrasekaran, T. Nishida, L. Cattafesta, and M. 42nd AIAA Aerospace Sciences Meetin g and Exhibit, 2004 1042 2004. [28] Y. Li, V. Chandrasekharan, B. Bertolucci, T. Nishida, L. Cattafesta, D. P. Arnold, Solid State Sensor, Actuator, and Microsystems Workshop State Sensor, Actuator, and Microsystems Workshop 2008, pp. 304 307. [29] Microscale Differential Capacitive Direct Wall Shear Journal Of Microelectromechanical Syste ms vol. 20, no. 3, pp. 622 635, 2011. [30] T. Pan, D. Hyman, M. Mehregany, E. Reshotko, and S. Garverick, AIAA Journal vol. 37, no. 1, pp. 66 72, 19 99. [31] AIAA Journal vol. 37, no. 1, pp. 73 78, Jan. 1999. [32] Str ess Sensor Journal of Microelectromechanical Systems vol. 14, no. 1, pp. 167 175, 2005. [33] a MEMS n 27th AIAA Aerospace Sciences Meeting 2009, no. January, pp. 1 11. [34] 2011. [35] J. Sells, V. Chandrasekharan, J. Meloy, M. Sheplak, H. Zmuda, and D. P. Arnold, ated Silicon on IEEE Sensors 2011, pp. 77 80.

PAGE 296

296 [36] implanted piezoresistive shear stress sensor for turbulent boundary [3 7] [38] F. Ulaby, Fundamentals of Applied Electromagnetics, Chapter 4 4th ed. Prentice Hall Pearson, 2004, pp. 139 184. [39] Z. Skvor, Acoustica vol. 19, pp. 295 299, 1967. [40] Planat Microstructures. Applications in Journal of the Acoustical Society of America vol. 116, no. 5, pp. 2939 2947, 2004. [41] Wiley, 2000, pp. 144 156. [42] Op Amp Applications Jung, Ed. Analog Devices, 2002, pp. 1.1 1.128. [43] Op Amp Applications Jung, Ed. Analog Devices, 2002, pp. 3.1 3.54. [44] A. S. Sedra and K. C. Smith, Microelectronic Circuits, Chapter 2: Operational Amplifiers Fifth. New York: Oxford University Press, 2004, pp. 63 138. [45] D. A. Johns and K. Martin, Analog Integrated Circuit Design, Chapter 5 1st ed. New York: John W iley & Sons, Inc, 1997, pp. 221 253. [46] C. D. Motchenbacher and J. A. Connelly, Low Noise Electronic System Design, Chapter 1 First. New York: John Wiley & Sons, Inc, 1993, pp. 5 32. [47] mp Noise Op Amps for Everyone 2nd ed., R. Mancini, Ed. Texas Instruments, 2003, pp. 10.1 10.25. [48] Datasheet 2005. [Online]. Available: http://www.analog.com/static/imported files/data_sheets/AD8 022.pdf. [Accessed: 03 Jan 2012]. [49] Datasheet 2007. [Online]. Available: http://www.ti.com/lit/ds/symlink/opa129.pdf.

PAGE 297

297 [50] Hardware Design Docume nt for the INFRASOUND Prototype for a CTBT IMS [51] S. T. Hansen, A. S. Ergun, W. Liou, B. A. Auld, and B. T. Khuri Journal of the Acous tical Society of America vol. 116, no. 2, pp. 828 842, 2004. [52] Cost, High Precision Measurement System for Measurement Science and Technology vol. 9, pp. 510 517, 1998. [53] M. Tavakoli, S. Member, an Canceling Low Noise Lock IEEE Journal of Solid State Circuits vol. 38, no. 2, pp. 244 253, 2003. [54] Axis Micromachined Accelerometer with a CMOS Pos ition Sense Interface and Digital Offset IEEE Journal of Solid State Circuits vol. 34, no. 4, pp. 456 468, Apr. 1999. [55] IEEE J ournal of Solid State Circuits vol. 30, no. 12, pp. 1367 1373, 1995. [56] Resolution Capacitive Sensors and Actuators A vol. 21, no. 1 3, pp. 278 281, Feb. 1990. [57] J. Wu, G. K. Fedder, Noise Low Offset Capacitive IEEE Journal of Solid State Circuits vol. 39, no. 5, pp. 722 730, 2004. [58] rinciple of Chopper IEEE Transactions on Circuits and Systems vol. 50, no. 8, pp. 975 983, 2003. [59] IEEE Journal of Solid State Circuits vol. SC 16, no. 6, pp. 745 748, 1981. [60] R. P. van Kampen, M. J. Vellekoop, P. M. Sarro, and R. F. Wolffenbuttel, Sensors and Actuators A: Physical vol. 43, no. 1 3, pp. 100 106, May 1994.

PAGE 298

298 [61] Solid State Sensor and Actuator Workshop 2002, pp. 202 205. [62] IEEE Proceedings Circuits, Devices and Systems vol. 145, no. 5, pp. 325 331, 1998. [63] Sigma Modulation in Fractional IE EE Journal of Solid State Circuits vol. 28, no. 5, pp. 553 559, 1993. [64] Y. Dong, M. Kraft, C. Gollasch, and W. Redman Performance Accelerometer with a Fifth Order Sigma Journal of Micromechanics and Microengineering vo l. 15, no. 7, pp. S22 S29, 2005. [65] Sensors and Actuators A vol. 68, pp. 466 473, 1998. [66] Loop Interfa ce Circuits for Capacitive Florida, 2008. [67] Channels pp. 1 7. [68] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits: Chapter 13 Second. New York: Cambridge University Press, 2006, pp. 404 437. [69] http://www.analog.com/en/other products/an alog multipliersdividers/adl5391/products/product.html. [Accessed: 06 Mar 2012]. [70] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits: Chapter 2 Second. New York: Cambridge University Press, 2006, pp. 40 86. [71] B. P. Lathi, Modern Digi tal and Analog Communication Systems: Chapter 4 5th ed. Oxford University Press, 1998, pp. 151 207. [72] D. A. Johns and K. Martin, Analog Integrated Circuit Design: Chapter 10 First. New York: John Wiley & Sons, Inc., 1997, pp. 394 445. [73] Texas Instr Datasheet 2004. [Online]. Available: http://www.ti.com/lit/ds/symlink/sn74ls04.pdf.

PAGE 299

299 [74] C. D. Motchenbacher and J. A. Connelly, Low Noise Electronic System Design, Chapter 6 First. New York: John Wi ley & Sons, Inc., 1993, pp. 140 171. [75] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits: Chapter 17 Second. New York: John Wiley & Sons, Inc., 2006, pp. 610 658. [76] R. T. Haftka and Z. Grdal, Elements of Structural Optimization 3rd rev. a. [77] optimization of a side Proceeding of SPIE 13th Ann ual International Symposium on Smart Structures and Materials 2006. [78] Micromachined Dual Backplate Capacitive Microphone for Aeroacoustic 1302 2007. [79] J. Meloy, J. Griffin, J. Sells, V. Chandrasekharan, L. N. Cattafesta, and M. 41st AIAA Fluid Dynamics Conference and E xhibit 2011, no. June, pp. 1 18. [80] J. Meloy, J. Sells, V. Chandrasekharan, J. Griffin, L. N. Cattafesta, D. P. Arnold, Stress Sesnor for Low in Hilton Head Solid State Sensors, Actuators, and Microsystems Workshop 2012, pp. 303 306. [81] Journal of The El ectrochemical Society vol. 146, no. 1, pp. 339 349, 1999. [82] Sensors and Actuators A: Physical vol. 25, no. 1 3, pp. 63 71, Oct. 1990. [83] fects with Regard to Sensors and Actuators A: Physical vol. 60, no. 1 3, pp. 37 39, May 1997. [84] Cost, High Volume Packaging Techniques for Silicon Sensors and Ac Solid State Sensor and Actuator Workshop 1988, no. 1 3, pp. 123 124. [85] Cost Plastic Sensor Packaging Using the Open Sensors and Actuators A: Physical vol. 67, no. 1 3, pp. 185 190, May 1998.

PAGE 300

300 [86] Backplate [87] ess [88] R. W. Fox and A. T. McDonald, Introduction to Fluid Mechanics 5th ed. New York: J. Wiley, 1998. [89] analysis to frequency r Journal of Sound and Vibration vol. 305, no. 1 2, pp. 116 133, Aug. 2007. [90] Calibration of a Shear Stress Sensor Using Stokes Layer Excitation Introducti AIAA Journal vol. 39, no. 5, pp. 5 9, 2001. [91] Journal of Fluid Mechanics vol. 677, no. April 2011, pp. 179 203, Apr. 2011. [92] J. S. Bendat and A. G. Piersol, Random Data Analysis and Measurement Procedures 3rd ed. New York: John Wiley and Sons, 2000, pp. 300 310. [93] versity of Florida, 2000. [94] Experiments in Fluids vol. 42, pp. 79 91, 2007. [95] Experiments in F luids vol. 22, no. 6, pp. 129 136, 1996. [96] Z. Angew. Math. Phys. vol. 56, pp. 1 37, 1908. [97] Turbulen AIAA Journal vol. 17, no. 6, pp. 655 657, 1979. [98] Journal of Applied Mechanics vol. 28, pp. 455 457, 1961. [99] e Measurements of Progress in Aerospace Sciences vol. Vol. 18, pp. 1 57, 1977.

PAGE 301

301 [100] Wire Anemometer Journal of Fluid Mech anics vol. 122, pp. 411 431, Apr. 1982. [101] Calibration of a Microfabricated Floating IEEE Transactions on Electron Devices vol. 35, no. 6, pp. 750 757, 1988.

PAGE 302

302 BIO GRAPHICAL SKETCH Jessica Caitlin Meloy was born in 1983 in Brandon, Florida, a suburb of Tampa. She graduated from Tampa Preparatory School in 2002 and then began her time at the University of Florida (UF) in Gainesville, Florida. Jessica received her ba chelor of science in electrical engineering at UF in May 2007. After joining IMG in January 2008 she received her master of science in electrical engineering in May 2009. In June 2009 she received a Graduate Student Researchers Program Fellowship from NA SA Langley Research Center. She completed her doctoral degree in 2012 and relocated to Seattle, Washington to begin a career at The Boeing Company.