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Design Optimizations of Spiking Hardware Neurons

Permanent Link: http://ufdc.ufl.edu/UFE0044055/00001

Material Information

Title: Design Optimizations of Spiking Hardware Neurons
Physical Description: 1 online resource (124 p.)
Language: english
Creator: Rastogi, Manu
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2012

Subjects

Subjects / Keywords: adc -- analog -- analog-to-digital -- asynchronous-analog-to-digital -- comparator -- current-conveyor -- current-limit -- energy-harvesting -- integrate-and-fire -- low-power -- neuron
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Over millions of years of evolution, biology has optimized the neuron structure and the interconnects for energy consumption and communication. Inspired by biology many research groups would like to build large arrays of neurons in hardware for efficient solutions to engineering problems. The purpose of this research is to provide a framework and design methodology for improving the energy efficiency of existing silicon neurons. Although there exist extremely complex silicon implementations of biologically realistic models, it is debatable whether or not using a biologically realistic model has any significant advantage over other models for solving realistic engineering challenges. Thus, as part of this work, design optimizations are performed the integrate and fire (I&F) model. In the past it has been shown that the I&F model can be used for encoding continuous time signals into asynchronous pulse trains. Under certain ideal conditions the original signal can be mathematically reconstructed perfectly from these pulse trains. We use the error introduced by the silicon neuron in the timing of the pulse trains and subsequently the error in the reconstructed signal as the benchmark for optimizing the neuron design. We build a framework for estimating the error introduced in reconstruction due to the timing jitter in the pulses. The model is verified using a simulated I&F circuit. This estimate serves as the maximum attainable signal reconstruction accuracy. Based on these estimates circuit topologies with the most favorable speed-resolution trade-off are selected. Several sine waves of varying frequency and amplitude were encoded through the fabricated I&F circuit. Pulses were recorded and the signal was reconstructed, based on the range of SER values recovered we estimate the optimum bias current at 750 nA at 3.3 V of power supply. These circuit parameters result in a energy/pulse of 100 pJ for a pulse rate of roughly 1 K/sec. In order to further reduce the static power dissipation two novel circuit topologies are proposed. The proposed circuits were fabricated in AMI 0.6 um technology and measured results indicate an improvement of roughly 80 times over this I&F circuit's predecessors developed at CNEL. The average energy/pulse is roughly 10 pJ for a pulse rate of 200 pulses/sec, the best published neuron circuit consumes roughly 267 pJ. Since, an analog-to-digital converter (ADC) also encodes continuous time signals into discrete samples, the efficiency of the I&F sampler is compared to that of conventional ADCs . Using traditional estimates such as effective number of bits (ENOB) and figure-of-merit (FOM) the I&F sampler is compared against conventional ADCs and a new class of converters known as asynchronous ADCs (AADCs). We find that the the I&F sampler with a FOM of 0.6 pJ outperforms the other ADCs in its technology node. However, as semiconductor technology advances, conventional ADC designs would naturally outperform the existing circuit implementations of the I&F circuit in 0.6 um technology. Thus, the performance of the sampler is simulated using the well-accepted predictive technology models (PTMs) from the Arizona Sate University. I&F circuit achieves a FOM of 9.8 fJ/conversion in the 45 nm technology node. Thus indicating that the I&F circuit scales favorably with technology scaling. We present a analysis that estimates that the minimum energy required for generating a pulse is in the order of a few tenths of fJs. In estimating this number the static power consumed in between spike times was ignored. At lower pulse rates the static power dissipation (power consumed in between the pulses) is high resulting in a higher energy/pulse for lower pulse rates. As the pulse rate increases, the inter-pulse interval becomes shorter and resulting in a lower static power dissipation. Thus for extremely high pulse rates the energy/pulse tends to reach this limit. Whether the I&F circuit is used an ADC or used as part of a large array of hardware neurons running a computational algorithm, power consumption is a key criteria. In order to further improve the energy efficiency of the I&F circuit, we present an energy harvesting circuit. The energy harvesting circuit harnesses some of the energy used by the I&F circuit for generating an output pulse and uses that energy to power itself. The I&F circuit generates an output pulse by comparing the capacitor voltage to the threshold, once the pulse is generated the capacitor is discharged. The energy stored in the capacitor is lost each time an output pulse is generated, instead a smarter scheme has been developed where in the capacitor discharges by transferring its stored energy to another circuit as compared to simply discharging to ground. The energy is harvested each time an output pulse is generated, higher the pulse rate higher would be the energy harvested. The overall efficiency of the energy harvesting setup is around 25%.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Manu Rastogi.
Thesis: Thesis (Ph.D.)--University of Florida, 2012.
Local: Adviser: Harris, John G.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2012
System ID: UFE0044055:00001

Permanent Link: http://ufdc.ufl.edu/UFE0044055/00001

Material Information

Title: Design Optimizations of Spiking Hardware Neurons
Physical Description: 1 online resource (124 p.)
Language: english
Creator: Rastogi, Manu
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2012

Subjects

Subjects / Keywords: adc -- analog -- analog-to-digital -- asynchronous-analog-to-digital -- comparator -- current-conveyor -- current-limit -- energy-harvesting -- integrate-and-fire -- low-power -- neuron
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Over millions of years of evolution, biology has optimized the neuron structure and the interconnects for energy consumption and communication. Inspired by biology many research groups would like to build large arrays of neurons in hardware for efficient solutions to engineering problems. The purpose of this research is to provide a framework and design methodology for improving the energy efficiency of existing silicon neurons. Although there exist extremely complex silicon implementations of biologically realistic models, it is debatable whether or not using a biologically realistic model has any significant advantage over other models for solving realistic engineering challenges. Thus, as part of this work, design optimizations are performed the integrate and fire (I&F) model. In the past it has been shown that the I&F model can be used for encoding continuous time signals into asynchronous pulse trains. Under certain ideal conditions the original signal can be mathematically reconstructed perfectly from these pulse trains. We use the error introduced by the silicon neuron in the timing of the pulse trains and subsequently the error in the reconstructed signal as the benchmark for optimizing the neuron design. We build a framework for estimating the error introduced in reconstruction due to the timing jitter in the pulses. The model is verified using a simulated I&F circuit. This estimate serves as the maximum attainable signal reconstruction accuracy. Based on these estimates circuit topologies with the most favorable speed-resolution trade-off are selected. Several sine waves of varying frequency and amplitude were encoded through the fabricated I&F circuit. Pulses were recorded and the signal was reconstructed, based on the range of SER values recovered we estimate the optimum bias current at 750 nA at 3.3 V of power supply. These circuit parameters result in a energy/pulse of 100 pJ for a pulse rate of roughly 1 K/sec. In order to further reduce the static power dissipation two novel circuit topologies are proposed. The proposed circuits were fabricated in AMI 0.6 um technology and measured results indicate an improvement of roughly 80 times over this I&F circuit's predecessors developed at CNEL. The average energy/pulse is roughly 10 pJ for a pulse rate of 200 pulses/sec, the best published neuron circuit consumes roughly 267 pJ. Since, an analog-to-digital converter (ADC) also encodes continuous time signals into discrete samples, the efficiency of the I&F sampler is compared to that of conventional ADCs . Using traditional estimates such as effective number of bits (ENOB) and figure-of-merit (FOM) the I&F sampler is compared against conventional ADCs and a new class of converters known as asynchronous ADCs (AADCs). We find that the the I&F sampler with a FOM of 0.6 pJ outperforms the other ADCs in its technology node. However, as semiconductor technology advances, conventional ADC designs would naturally outperform the existing circuit implementations of the I&F circuit in 0.6 um technology. Thus, the performance of the sampler is simulated using the well-accepted predictive technology models (PTMs) from the Arizona Sate University. I&F circuit achieves a FOM of 9.8 fJ/conversion in the 45 nm technology node. Thus indicating that the I&F circuit scales favorably with technology scaling. We present a analysis that estimates that the minimum energy required for generating a pulse is in the order of a few tenths of fJs. In estimating this number the static power consumed in between spike times was ignored. At lower pulse rates the static power dissipation (power consumed in between the pulses) is high resulting in a higher energy/pulse for lower pulse rates. As the pulse rate increases, the inter-pulse interval becomes shorter and resulting in a lower static power dissipation. Thus for extremely high pulse rates the energy/pulse tends to reach this limit. Whether the I&F circuit is used an ADC or used as part of a large array of hardware neurons running a computational algorithm, power consumption is a key criteria. In order to further improve the energy efficiency of the I&F circuit, we present an energy harvesting circuit. The energy harvesting circuit harnesses some of the energy used by the I&F circuit for generating an output pulse and uses that energy to power itself. The I&F circuit generates an output pulse by comparing the capacitor voltage to the threshold, once the pulse is generated the capacitor is discharged. The energy stored in the capacitor is lost each time an output pulse is generated, instead a smarter scheme has been developed where in the capacitor discharges by transferring its stored energy to another circuit as compared to simply discharging to ground. The energy is harvested each time an output pulse is generated, higher the pulse rate higher would be the energy harvested. The overall efficiency of the energy harvesting setup is around 25%.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Manu Rastogi.
Thesis: Thesis (Ph.D.)--University of Florida, 2012.
Local: Adviser: Harris, John G.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2012
System ID: UFE0044055:00001


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DESIGNOPTIMIZATIONSOFSPIKINGHARDWARENEURONS By MANURASTOGI ADISSERTATIONPRESENTEDTOTHEGRADUATESCHOOL OFTHEUNIVERSITYOFFLORIDAINPARTIALFULFILLMENT OFTHEREQUIREMENTSFORTHEDEGREEOF DOCTOROFPHILOSOPHY UNIVERSITYOFFLORIDA 2012

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c r 2012ManuRastogi 2

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Tomyparents,myfamilyandmyteachers 3

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ACKNOWLEDGMENTS IamgreatlyindebtedtomyadviserDr.JohnG.Harrisforgivi ngmetheopportunity toworkinhislab.Hehasbeenaveryunderstandingandapatie ntmentor.Itisfrom himthatIlearnttobeanalytical,thinkcreatively,explor enewideasandexploresimple solutionsforcomplexproblems.Iamverygratefultohimfor givingmetheopportunity toattendconferencesandworkshops.Iamgratefultohimfor trustingmewiththe responsibilityofdeningthescopeofmyprojects,courses andresearchwork.Asa goodcoachhewasalwaystheretocriticallypointouttheaw sinmydecisionmaking processandtoencouragemewheneverIdidmanagetoputthing sinplaceintime. IwouldliketothankmycommitteemembersDr.Jos eC.Principe,DrRobertM.Fox andDr.SachinTalathifortakingthetimetoprovidemewithv aluablefeedbackonmy research.IwouldliketospeciallythankDr.Foxforteachin gmeanalogcircuitdesign. Dr.Principehasprovidedmefeedback,ideasandhelpedmebr oadenmyhorizonsat variousjuncturesofmyresearchatCNEL.Mydiscussionswit hDr.Talathiduringhis classonneuro-dynamicsandonmyresearchworkgavemeauniq ueperspective.Iam alsothankfultoDr.JustinSanchezforhiscommentsandsugg estionswhichsignicantly shapedmyresearchwork. VaibhavGargandRaviShekharhavebeenverypatientfriends ,criticsand condantesthroughout.IamalsoverythankfultoVaibhavGa rgforshowingmethe waytoCNEL.Ihavegainedimmenselyfrommyintensediscussi onswithJieXu andAlexanderSingh-Alvaradowhichgaverisetonewideas.W ithouttheirtechnical expertise,helpandsupportIpossiblywouldnothavebeenab letocompletethiswork. CNELlabmates,especiallySavyasachiSingh,ErionHasanbe lliu,JeremyAnderson SohanSethandSteveYen,havebeenaconstantsourceofsuppo rt,motivationandfun duringmytimeatCNEL. Iamindebtedtomyparentsandmyfamilyforprovidingmewith bestpossible educationandopportunities.Iamthankfulthattheyengrai nedintomethevalueof 4

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educationandself-reliance.Theyhavebeenaconstantsour ceofencouragement, supportandenlightenment. Finally,IwouldliketoacknowledgemyfundingsourceNatio nalInstituteof NeurologicalDisordersandStroke(NINDS)whichsupported myresearchpartially throughgrantNumberNS053561. 5

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TABLEOFCONTENTS page ACKNOWLEDGMENTS .................................. 4 LISTOFTABLES ...................................... 8 LISTOFFIGURES ..................................... 9 ABSTRACT ......................................... 11 CHAPTER 1INTRODUCTION ................................... 14 1.1Motivation .................................... 14 1.2Outline ...................................... 20 2INTEGRATE-AND-FIREASANADCREPLACEMENT .............. 21 2.1Introduction ................................... 21 2.2BackgroundandPriorWork .......................... 22 2.2.1Integrate-And-Fire(I&F)Sampler ................... 27 2.2.2ReconstructionAlgorithm ....................... 29 2.3Signal-To-NoiseRatio ............................. 31 2.3.1PerformanceMetrics .......................... 33 2.4Summary .................................... 35 3LOWPOWERINTEGRATE-AND-FIRECIRCUIT ................. 36 3.1CircuitDesign .................................. 36 3.1.1Comparator ............................... 36 3.1.1.1Comparatortopology .................... 37 3.1.1.2Hysteresis .......................... 42 3.1.2RefractoryComponent ......................... 44 3.2ComparatorDelay ............................... 46 3.3PowerConsumption .............................. 50 3.3.1SourcesofPowerConsumption .................... 50 3.3.2OptimumComparatorBiasCurrent .................. 52 3.3.3ReducingStaticPowerConsumption ................. 55 3.4ResultsandDiscussion ............................ 64 3.5Summary .................................... 72 4LIMITONINTEGRATE-AND-FIREENERGYDISSIPATION ........... 74 4.1Introduction ................................... 74 4.2LimitonInverterPowerConsumption ..................... 74 4.3LimitonSingleStageComparator'sPowerConsumption .......... 77 4.4LimitonI&FCircuit'sPowerConsumption .................. 83 6

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4.5Summary .................................... 89 5ENERGYHARVESTING .............................. 91 5.1Introduction ................................... 91 5.2EnergyHarvestingArchitecture ........................ 91 5.2.1EnergyHarvestingCircuit ....................... 92 5.2.2EnergyUtilization ............................ 94 5.2.3FiniteStateMachine(FSM)BasedControlLogic .......... 96 5.3ResultsandDiscussion ............................ 105 5.4ConclusionandFutureWork ......................... 110 6CONCLUSION .................................... 112 REFERENCES ....................................... 115 BIOGRAPHICALSKETCH ................................ 124 7

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LISTOFTABLES Table page 3-1ComparisonofthethisI&Fimplementationwiththepasti mplementations. ... 68 3-2ComparisonofFOMwithotherADCs. ....................... 70 3-3TechnologyscalingfortheI&Fcircuit. ....................... 72 5-1Resultsfortheenergyharvestingcircuit ...................... 110 8

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LISTOFFIGURES Figure page 1-1Possible”tweaks”tothecurrenthumanbrainandtheirre spectivetrade-offs. .. 16 2-1Acomparisonoftheoutputdataratesoftheconventional ADCandtheI&F .. 22 2-2ConventionalIntegrateandFire(I&F)sampler .................. 27 2-3BiphasicIntegrateandFiredataconverter ..................... 28 2-4PositiveandNegativechannelpulseoutputsforasinewa ve. .......... 28 2-5SNRvs.theclockperiodusedforquantizingthesampleti mes. ......... 34 3-1SingleVoltageAmplierandthecorrespondingsmallsig nalmodel ....... 39 3-2Latch-basedpositivefeedbackcomparatoranditsequiv alentsmallsignalmodel. 39 3-3AcascadeofNidenticalsinglestageampliers .................. 40 3-4Latch-basedpositivefeedbackcomparatorwithoutputs tage. .......... 41 3-5Normalizedcomparatordelayvs.stepinputsize ................. 41 3-6Measured V + trip vs. I bias ............................... 43 3-7Twopossibleimplementationsoftherefractorycompone nt ........... 44 3-8ThecompleteschematicofthepositivechanneloftheI&F circuit. ....... 45 3-9Measuredcomparatordelayvs.biascurrent ................... 48 3-10SimulatedblockwisepowerconsumptionoftheI&Fforth epulseinterval ... 51 3-11Measuredenergy/pulseofthecomparatorasafunctiono fpulserate ...... 53 3-12Timevaryingdelayofthecomparator ....................... 54 3-13SERvs.ComparatorBias .............................. 55 3-14Dynamicallybiasedcomparatorarchitecture. ................... 57 3-15SimulatedI Bias asafunctionofV in ......................... 58 3-16SimulatedI Bias asafunctionofV in forvaryingvaluesofV cntrl .......... 59 3-17Measuredenergy/pulseofthecomparatorasafunctiono fpulserate ...... 60 3-18Simulatedblockwisepowerconsumptionofthedynamica llybiasedI&F. .... 61 3-19Measurednodevoltagesforthecurrentlimitcircuit. ............... 62 9

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3-20Twoimplementationsofthecurrentlimitingandsource followercircuit. ..... 64 3-21Dynamicallybiasedcomparatorwithsourcefollower. ............... 65 3-22Simulatedpowerconsumptionofthedynamicallybiased I&F. .......... 66 3-23MeasuredSNRvs.powerconsumptionoftheI&Fsampler. ........... 67 3-24Measuredenergy/pulsevs.pulseratefortheI&Fcircui t ............. 68 3-25MeasuredENOBandpowerconsumptionvs.sinewaveampli tude. ....... 69 4-1Simulatedinvertervoltagetransfercurvesforvarying V dd ............ 77 4-2Simulatedinverterdelayandpowerconsumptionforvary ingV dd ........ 78 4-3Simulatedinverterpower-delayproductforvaryingV dd ............. 79 4-4SingleVoltageAmplierandthecorrespondingsmallsig nalmodel ....... 79 4-5Analyticalevaluationoftheminimumsupplyvoltageasa functionofbiascurrent. 81 4-6Power-delayproductofthecomparatorvs.V dd fordifferentI bias ......... 82 4-7Singlestagecomparatordelayvs.V dd forvariousvaluesofI bias ........ 83 4-8MeasuredandanalyticalminimumsupplyvoltagefortheI &Fcircuit ...... 84 4-9SchematicofthepositivechanneloftheI&Fcircuit. ............... 85 4-10Equation4–29vs.V dd fordifferentbiascurrents. ................. 89 5-1BlocklevelschematicofthebiphasicI&Fcircuit. ................. 92 5-2SecondgenerationCurrentConveyorcircuitandI&Fcirc uit. ........... 93 5-3Amplierbiascontrolusingthedigital-likepulseoutp utfromtheI&Fcircuit. .. 94 5-4CurrentConveyorcircuitwiththeswitchesandtheI&Fci rcuit. .......... 95 5-5Algorithmforcontrollingtheenergyharvestingloop ............... 98 5-6FSMrepresentationofthealgorithmow ..................... 99 5-7ThecontrolloopFSMwithdigitalagsandcontrolsignal s. ........... 101 5-8TimingdiagramoftheFSM ............................. 102 5-9Thecompleteharvestingarchitectureschematic. ................ 106 5-10Measurementresultsfortheenergyharvestingarchite cture. ........... 107 10

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AbstractofDissertationPresentedtotheGraduateSchool oftheUniversityofFloridainPartialFulllmentofthe RequirementsfortheDegreeofDoctorofPhilosophy DESIGNOPTIMIZATIONSOFSPIKINGHARDWARENEURONS By ManuRastogi May2012 Chair:JohnG.HarrisMajor:ElectricalandComputerEngineering Overmillionsofyearsofevolution,biologyhasoptimizedt heneuronstructure andtheinterconnectsforenergyconsumptionandcommunica tion.Inspiredbybiology manyresearchgroupswouldliketobuildlargearraysofneur onsinhardwarefor efcientsolutionstoengineeringproblems.Thepurposeof thisresearchistoprovidea frameworkanddesignmethodologyforimprovingtheenergye fciencyofexistingsilicon neurons.Althoughthereexistextremelycomplexsiliconim plementationsofbiologically realisticmodels,itisdebatablewhetherornotusingabiol ogicallyrealisticmodelhas anysignicantadvantageoverothermodelsforsolvingreal isticengineeringchallenges. Thus,aspartofthiswork,designoptimizationsareperform edtheintegrateandre (I&F)model.InthepastithasbeenshownthattheI&Fmodelca nbeusedforencoding continuoustimesignalsintoasynchronouspulsetrains.Un dercertainidealconditions theoriginalsignalcanbemathematicallyreconstructedpe rfectlyfromthesepulsetrains. Weusetheerrorintroducedbythesiliconneuroninthetimin gofthepulsetrainsand subsequentlytheerrorinthereconstructedsignalasthebe nchmarkforoptimizingthe neurondesign. Webuildaframeworkforestimatingtheerrorintroducedinr econstructiondueto thetimingjitterinthepulses.Themodelisveriedusingas imulatedI&Fcircuit.This estimateservesasthemaximumattainablesignalreconstru ctionaccuracy.Basedon theseestimatescircuittopologieswiththemostfavorable speed-resolutiontrade-offare 11

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selected.Severalsinewavesofvaryingfrequencyandampli tudewereencodedthrough thefabricatedI&Fcircuit.Pulseswererecordedandthesig nalwasreconstructed, basedontherangeofSERvaluesrecoveredweestimatetheopt imumbiascurrentat 750nAat3.3Vofpowersupply.Thesecircuitparametersresu ltinaenergy/pulseof 100pJforapulserateofroughly1K/sec.Inordertofurtherr educethestaticpower dissipationtwonovelcircuittopologiesareproposed.The proposedcircuitswere fabricatedinAMI0.6 m technologyandmeasuredresultsindicateanimprovementof roughly80timesoverthisI&Fcircuit'spredecessorsdevel opedatCNEL.Theaverage energy/pulseisroughly10pJforapulserateof200pulses/s ec,thebestpublished neuroncircuitconsumesroughly267pJ[ 1 ]. Since,ananalog-to-digitalconverter(ADC)alsoencodesc ontinuoustime signalsintodiscretesamples,theefciencyoftheI&Fsamp leriscomparedtothat ofconventionalADCs.Usingtraditionalestimatessuchase ffectivenumberofbits (ENOB)andgure-of-merit(FOM)theI&Fsampleriscompared againstconventional ADCsandanewclassofconvertersknownasasynchronousADCs (AADCs).We ndthatthetheI&FsamplerwithaFOMof0.6pJoutperformsth eotherADCsinits technologynode.However,assemiconductortechnologyadv ances,conventionalADC designswouldnaturallyoutperformtheexistingcircuitim plementationsoftheI&Fcircuit in0.6 m technology.Thus,theperformanceofthesamplerissimulat edusingthe well-acceptedpredictivetechnologymodels(PTMs)fromth eArizonaSateUniversity. I&FcircuitachievesaFOMof9.8fJ/conversioninthe45nmte chnologynode.Thus indicatingthattheI&Fcircuitscalesfavorablywithtechn ologyscaling. Wepresentaanalysisthatestimatesthattheminimumenergy requiredfor generatingapulseisintheorderofafewtenthsoffJs.Inest imatingthisnumber thestaticpowerconsumedinbetweenspiketimeswasignored .Atlowerpulseratesthe staticpowerdissipation(powerconsumedinbetweenthepul ses)ishighresultingina higherenergy/pulseforlowerpulserates.Asthepulserate increases,theinter-pulse 12

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intervalbecomesshorterandresultinginalowerstaticpow erdissipation.Thusfor extremelyhighpulseratestheenergy/pulsetendstoreacht hislimit. WhethertheI&FcircuitisusedanADCorusedaspartofalarge arrayofhardware neuronsrunningacomputationalalgorithm,powerconsumpt ionisakeycriteria.In ordertofurtherimprovetheenergyefciencyoftheI&Fcirc uit,wepresentanenergy harvestingcircuit.Theenergyharvestingcircuitharness essomeoftheenergyused bytheI&Fcircuitforgeneratinganoutputpulseandusestha tenergytopoweritself. TheI&Fcircuitgeneratesanoutputpulsebycomparingtheca pacitorvoltagetothe threshold,oncethepulseisgeneratedthecapacitorisdisc harged.Theenergystoredin thecapacitorislosteachtimeanoutputpulseisgenerated, insteadasmarterscheme hasbeendevelopedwhereinthecapacitordischargesbytran sferringitsstoredenergy toanothercircuitascomparedtosimplydischargingtogrou nd.Theenergyisharvested eachtimeanoutputpulseisgenerated,higherthepulserate higherwouldbethe energyharvested.Theoverallefciencyoftheenergyharve stingsetupisaround25%. 13

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CHAPTER1 INTRODUCTION 1.1Motivation Thehumanbrainisanengineeringmarvelofnature.Timeanda gainengineers andresearchershaveturnedtonatureforinspirationatvar iouslevelsofabstractionto solvecomplexengineeringproblems.Thereisagrowinginte restinbuildingspike-based systemsinspiredbybiologyinsucheldsasspeechrecognit ion,facerecognitionand autonomousroboticsystems.Inspirationtostudysuchsyst emsstemsfromthefact thatthebestengineeredalgorithmswiththemostpowerfulc omputinghardwaredonot comeclosetomatchingtheperformanceachievedbythehuman brain.Thehuman brainconsumesabout12wattsofpower[ 2 ],aboutatenthofwhatthelatestcomputer processorsconsume,andisabletoperformnumeroustaskssu chasrobustspeech recognition,processingimagesandevendrivingacartasks thatmachineshavetrouble accomplishing. Thebrainachievesthesecomputationalfeatsthroughadens elyinterconnected systemofspecializedcellscalledneurons.Neuronsareele ctricallyexcitablecellsthat processandtransmitinformationbyelectrochemicalsigna lsbetweenthemselves viaconnectionscalledsynapses.While,thepreciseinform ationrepresentation andprocessingmechanismsinthebrainathigherlevelsofab stractionarenotwell understood,itiswellknownthattheneuronsatthelowestle velcommunicateamongst themselvesthoughsomekindofatemporalcodebygenerating spikes.Theinformation isgenerallycontainedinthetimebetweenthespikesandnot intheirsizeorshape. Overtime,naturehasoptimizedthebrainofdifferentspeci esforenergyefciency andcomputation.Herculano-Houzeletal.[ 3 ]examinecellularscalingrulesforprimate brainsandrodentbrains.Theyshowthatprimatebrainsscal elinearlywiththenumber ofneuronsincontrasttotherodentbrainswhichscalefaste rinsizethaninnumber ofneurons.Asaconsequenceoftheselinearcellularscalin grules,primatebrains 14

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havemoreneuronsthanrodentbrainsofsimilarsize,presum ablyendowingthem withgreatercomputationalpowerandcognitiveabilities. RothandDicke[ 4 ]pointout thatbrainsofthehoneybee,theoctopusandthecrowandothe rintelligentmammals looknothingalikeontherstglance,howeverneuralcircui tsfortaskssuchasvision, smellandnavigationhavethesamebasicarrangement.Theau thorsclaimthatsuch evolutionaryconvergencesuggeststhatananatomicalorph ysiologicalsolutionhas beenreachedandtheremaybeverylittleroomforimprovemen t.Arecentarticlein ScienticAmericanbyDouglasFox,speculatesthatthemaxi maforintelligencefor specieshasbeenreached.Foxexploresfourpossible”tweak s”thatcanbeapplied tothehumanbrainforenhancingintelligence.Therstobvi ouschangewouldbeto increasethebrainsizeswhilekeepingtheneuronsizethesa me,thiswouldrequire longeraxons.Alargenumberofneuronsmeanmoreenergycons umptionandlonger axonsmeanlargercommunicationtimebetweenneuronsresul tinginanoverallslower processing.Thesecondtweakwouldbetoincreasethenumber ofsynapsesbetween neuronsenablingafasterandmorereliablecommunicationb etweenneuronsatthecost ofincreasedenergyandspacerequirements.Thethirdpossi blechangeistoincrease thewidthofthesynapsesinordertomakethecommunicationm orereliableandfaster. However,asinthepreviouscasethickersynapseswouldneed moreenergyandmore space.Thenaltweakistoincreaseneurondensitywhilekee pingtheoverallbrainsize thesame.Makingsmallerneuronsmeanssmallercellularmem braneswhichwould resultinunreliableringoftheneuronthusresultinginhi gherenergyconsumption andunreliablecommunication.Fox'sargumentisbestsumma rizedbyFigure 1-1 from hisarticle[ 5 ].Asimilaroptimizationanalysisshouldbesimplerforele ctronicspiking hardware. Inspiredbythewaythebrainrepresentsinformationintime therehasbeen signicantinterestinencodingcontinuous-timesignalsi ntoasynchronouspulsetrains. Thesepulsescanthenbeprocessedtogetauniformlysampled signalequivalentto 15

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Figure1-1.Possible”tweaks”tothecurrenthumanbrainand theirrespectivetrade-offs. ThegureisfromanarticlebyDouglasFoxinScienticAmeri can[ 5 ] whatwouldhavebeenobtainedthroughaconventionalAnalog -to-Digitalconverter (ADC).Thesebiologicallyinspiredsamplersgenerallyhav elowerpowerconsumption, lesssiliconarea,reducedcircuitcomplexityascomparedt oconventionalADCs. Examplesofsuchencodersincludethetime-basedADCbyYang andSarpeshkar[ 6 ] andaHodgkin-HuxleybasedvideoencoderbyLazarandZhou[ 7 ]andAghagolzadeh etal.[ 8 ].Onesuchasynchronoustimebasedsamplerhasalsobeendev elopedat CNELusingtheintegrate-and-re(I&F)neuronmodel.Thest ructureoftheI&Fsampler 16

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hasbeenmodiedtoencodethepositiveandthenegativepart softheinputsignalinto twoseparateoutputdatachannels.TheI&Fcircuitautomati callyadjuststheoutputdata rateaccordingtothesignalamplitude,unlikeconventiona lADCsthatignoretheinput signalcharacteristics.TheI&Fsamplerachieveslowerpow erandlowerbandwidthat thecostofacomputationallyexpensivereconstructionmet hod.Thesimplicityofthe sampleralongwiththepowerandbandwidthsavingshasmadei tmoresuitablefor biomedicalsensors.TheI&Fsamplerhasbeendemonstratedf orencodingneuraldata forbrainmachineinterfaces[ 9 ].Thetheoreticalboundsonthereconstructionaccuracy forbandlimitedsignalshavealsobeenpresented[ 10 ]. Apartfromencodingcontinuous-timesignals,thereisalso aninterestinbuilding circuitsthatmimicbiologyandperformtaskssuchasvision ,auditionandcognitive functions.Buildingbrain-inspiredhardwareisadvantage ousascomparedtosoftware simulationschieyduetoreal-timeoperation.Manyresear chgroupsandengineers aretryingtobuildhardwareneuronarrayswithcongurable synapticweightsand connectionsthatcanbeusedforexploringbasiccomputatio ntechniquesofthebrain. Thecircuitsaredesignedtocloselymodeltheresponsesofb iologicalneuronsand synapses.Biologicallyplausiblecircuitdesignsrequire timeandsubstantialeffort. Yearsago,CarverMeadandotherresearchersrealizedthesi milaritybetweenthe biologicalneuronsandtransistordevicephysics.Thisled toanumberofnewanalog circuitsinspiredbybiology.Thesecircuitscanstillbefo undinsomeoftheneuronarrays beingbuiltbyresearchgroups.Themotivationtobuildanal ogcircuitscamefromtwo facts.First,analogcomputationinthelate80sandearly90 swasmorepowerand areaefcientascomparedtodigitalcomputation.Secondth esubthresholdoperation ofthetransistorcloselyresemblesthecharacteristicsof realneurons.However,as semiconductortechnologyhasadvancedfrommicro-meterto nano-metergatelengths, ithasbecomemoreandmorechallengingforanalogcomputati ontokeepupwith itsdigitalcounterpart.Digitalcircuitsarepower,area, mismatchandnoiseefcient 17

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alongwithshorterdesigntimesandeaseofrecongurabilit y.Researchgroupsare increasinglyshiftingtodigitaldesignsforbuildingneur onarrays.Thisshiftfromanalog todigitalneuronarraysissimilartotheevolutionofhardw arearticialneuralnetworksin thelate90s. Biologyoptimizedtheneuronsize,theinter-connectivity betweenneuronsand thebrainsizeforoptimumcomputationandenergyconsumpti on.Evenwithmost optimizations,thehumanbrainat2percentofourbodyweigh tconsumesclose to20percentoftheenergy[ 5 ].Sincetheneuronsformthebuildingblocksofthe brain,therehasbeenconsiderableworkdoneinthedesignan dfabricationofneuron models.Variousresearchgroupsbuildlargearraysofhardw areneuronsforabetter understandingofthebrainandtondbiologicallyinspired solutionstocomplex engineeringproblems.Attheheartofthesearraysisusuall ysomekindofabiologically inspiredneuronmodel.Alargesetofneuronmodelsareavail ableintheliterature rangingfromtheverysimpleintegrateandremodeltothemo rebiologicallyplausible Hodgkin-Huxleymodel.Faisaletal.[ 11 ]showthatshrinkingthesizeofneurons makestheirspikingnoisyandunreliableandleadstoconseq uentlyoverallhigher energyconsumption.Itisofinteresttoexplorethenoise,r eliabilityandoverallenergy consumptionasafunctionoftransistorandtechnologyscal ingandcompareitto biologicalneurons. Aspartofthisworkwepresentthedesignoptimizationofthe I&Fcircuit.Theaim istolowertheenergyconsumptionoftheI&Fcircuitwhilema intainingitsperformance asasampler.Webeginbyconstructingatheoreticalframewo rkandexperimental resultsforevaluatingtheI&FcircuitasanADC.Performanc eoftheI&Fcircuitasan ADCisusedasthekeymetricforevaluatingtheenergyoptimi zationsperformed.Using gure-of-merit(FOM)asacriteriaweshowthatI&Fcircuito utperformsseveralexisting ADCarchitectures.Thegure-of-meritfortheI&Fsampleri s0.6pJ/conversiondespite thefactthatexistingI&Fhasbeenimplementedinamucholde rtechnology.However, 18

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assemiconductortechnologyadvances,conventionalADCde signswouldnaturally outperformtheexistingcircuitimplementationsoftheI&F circuitin0.6 m technology. Thus,theperformanceofthesamplerissimulatedusingthew ell-acceptedpredictive technologymodels(PTMs)fromtheArizonaStateUniversity .I&Fcircuitachievesa FOMof9.8fJ/conversioninthe45nmtechnologynode.Thusin dicatingthattheI&F circuitscalesfavorablywithtechnologyscaling. SourcesofenergyconsumptionintheI&Fcircuitarecareful lyevaluated.Based onthisevaluation,novelcircuit-basedschemesforreduci ngenergyconsumptionare presented.Theproposedcircuitshavebeenfabricatedandm easuredresultsindicate animprovementofroughly80timesoverthisI&Fcircuit'spr edecessorsdevelopedat CNEL. InordertofurtherincreasetheenergyefciencyoftheI&Fc ircuit,anovelenergy harvestingschemeispresented.Weshowthattheenergyharv estingscheme whenusedwithanarrayofI&Fcircuitcanpresentsignicant energysavings.The energyharvestingsetupwithanefciencyofroughly26%has beenpresentedand implementedonchipinAMI0.6 m technology.Thebasicideabehindharvesting energycomesfromtherealizationthatthechargeheldinthe membranecapacitoris wastedtogroundaftereverypulse. Usingaverysimplemathematicalanalysisweestimatethatt heminimumenergy requiredforgeneratingapulseisintheorderofafewtenths offJs.Inestimatingthis numberthestaticpowerconsumedinbetweenspiketimeswasi gnored.Atlowerpulse ratesthestaticpowerdissipation(powerconsumedinbetwe enthepulses)ishigh resultinginahigherenergy/pulseforlowerpulserates.As thepulserateincreases,the inter-pulseintervalbecomesshorterandresultinginlowe rstaticpowerdissipation.Thus forextremelyhighpulseratestheenergy/pulsetendstorea chthislimit. 19

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1.2Outline Chapter2reviewspriorworkdoneintheareaofasynchronous ADCdesign. ItreviewssomeoftherecentlypublishedasynchronousADCs andthetrade-offs associatedwiththem.Also,thischaptersurveyssomeofthe priorworkdoneonthe I&Fsamplerandthereconstructionalgorithmisreviewed.T hechapterendswitha discussionoftheperformancemetricsfortheI&Fsampler.C hapter3describesthe circuitdesignphilosophyfortheI&Fsampler.Thechapterb eginsbyreviewingthe speed-resolutiontrade-offassociatedwithvariousanalo gcomparators.Practical implementationissuesforthecomparatorsandtheirimpact onthereconstructedsignal arediscussed.SourcesofpowerconsumptionintheanalogI& Fcircuitalongwithcircuit methodologiesforreducingthepowerconsumptionarediscu ssed.Thechapterends withresultsanddiscussionfollowedbythesummaryofthewo rk.Chapter4presents themathematicalframeworkforevaluatingthefundamental limitsofenergyconsumption oftheI&Fcircuit.Theeffectofcircuitnoise,powersupply andbiascurrentareevaluated againsttheperformanceofthecircuitasanADC.Chapter5pr esentsanovelenergy harvestingarchitectureforfurtherincreasingtheoveral lenergyefciencyoftheI&F circuit.Chapter6summarizestheworkalongwiththecontri butions. 20

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CHAPTER2 INTEGRATE-AND-FIREASANADCREPLACEMENT 2.1Introduction Conventionalanalog-to-digitalconverters(ADCs)encode continuous-timesignals intoauniformlysampleddiscrete-levelrepresentation.O ncethesesignalsareconverted theycanbestoredand/orprocessedusingconventionalsign alprocessingtools. Theaccuracyoftheencodedsignal,speed,costandpowerare themaincriteriafor choosingADCarchitecture.Certainapplicationscantoler atesomedegradationinthe recoveryofthesignalaslongasthepowerconsumption,size andbandwidthconstraints aremet.TheoutputdatarateofaconventionalADCisindepen dentofthebandlimited signalcharacteristics,aslongasthesamplingrateobeyst heNyquistfrequency.As anexampleiftheinputsignaliszero,theADCwouldcontinue togeneratesamples ataxedoutputrate.ConventionalADCsfailtoutilizethes ignalinformationresulting inunnecessarypowerandbandwidthconsumption.Figure 2.1 illustratesthispoint.A comparisonoftheoutputdata-ratesoftheconventionalADC andtheI&Fcircuitwith respecttotheinputsignalamplitudeareshown.Theconvent ionalADCcontinuesto generateaxedoutputdatarateirrespectiveofthesignala mplitudewhereastheI&F adjuststheoutputdatarateaccordingtotheinputsignalam plitude. Owingtotheseshortcomingstherehasbeenasignicantinte restinexploring novelschemesforanalog-to-digitalconversion.Apopular approachistouseirregular samplerssuchasasynchronousADCs(AADC)[ 12 ].AADCshavenoclocksorxed outputdatarate.Anoutputsampleisgeneratedwhenthesign alpropertieschange, potentiallyleadingtosignicantpowerandbandwidthsavi ngs.Forexample,alevel crossingAADC[ 13 ]generatesanoutputsamplewheneverthesignalcrossesa quantizationlevel.someotherapproachessuchasreferenc ecrossing[ 14 ],asynchronous deltaconverters[ 15 ],andlevelcrossingwithexponentiallevelspacing[ 16 ]havealso beenimplementedforvarioustargetapplications. 21

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0 10 20 30 40 50 60 70 80 0 200 400 600 800 1000 1200 1400 Pulse Rate (KSamples/sec)Sinewave Amplitude (nA) IF Conventional ADC Figure2-1.Acomparisonoftheoutputdataratesoftheconve ntionalADCoutputand theI&F.Eventhoughtheinputsignalisaroundzeroandthesi gnalcontains noinformationtheconventionalADCwastesbandwidthandpo werwhereas theI&Fcircuitadjuststheoutputdatarate. AADCstradeoffbandwidthandpowerforcomplexrecoverymec hanismsand precisioninsampletimes.Areviewofrecoverymechanismsa ndtheireffectonthe AADCscanbefoundin[ 16 ].AADCsareamorefavorableapproachoverconventional ADCswhenexploitingthespecicfeaturesoftheinput.Fore xample,AADCsleadto powerandbandwidthsavingforapplicationssuchasremotes ensingandbiomedical implants[ 14 17 ]wherethesignalisslowlychangingandsparseintime.Inth ischapter wepresentthebackgroundworkrelatedtotheI&Fsampler. 2.2BackgroundandPriorWork Shannon'ssamplingtheoremprovidesbothauniformsamplin gschemeusedin conventionalADCaswellasareconstructionalgorithmbase donthe`sinc'function basis.Thetheoremistypicallyexplainedintermsofthefre quencydomain.Itisalso intuitivehowdistortionsmanifestwhenthesamplingratei sbelowtheNyquistbound. However,recoveryisnolongerstraightforwardfornon-uni formsampling.Nevertheless, 22

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therearemanyadvantageswhensamplingonanon-uniformset .Techniquesbased onnon-uniformsamplinghavegivenrisetoresearchareassu chasaliasfreesampling [ 18 ].Ingeneraltermsanonuniformsamplesethasthealiasedfr equenciesthroughout thebasebandinsteadofconcentratingatasinglefrequency .AswillbeseenfortheI&F model,higherthefrequencyofthealiasedsignallowerthea mountofaliasing. Thecurrentliteraturefornonuniformsamplingandreconst ructionisbasedonframe theory[ 19 ].Therecoveryalgorithmscanbeexplainedintermsoflinea ralgebrainthe caseofnitedimensionalspaces.Thereconstructionalgor ithmisnothingmorethan ndingthesolutiontoaleastsquaresproblem.Thefundamen taldifferencebetweenthe conventionalliteratureandrecoverymethodsforadaptive samplers,isthat,inthelatter, thesamplesprovideuswithmoreinformationthansimplythe irlocationorpointwise value.Inthecaseoflevelcrossingsamplers,forinstance, wecanboundthevariationof theinputbetweenconsecutivesamplessinceifithadcrosse dalevelthesamplesset wouldhavebeendifferent.Thereforedependingonsignalpr operties,samplingschemes canbeadaptedsuchthateachsamplehasmaximuminformation content.Different samplingschemesrequiredifferentarchitecturesandthus basedontheimplementation irregularsamplerscanbroadlybeclassiedas:LevelCross ingSampler(LCS),Time VariantThresholdCrossingSamplers(TCS),Delta-SigmaSa mplers(DSS)andthe IntegrateandFiresampler(I&F).Inthissectionwedescrib ethefundamentalsampling conceptandreviewthepriorworkdoneineachofthecategori es. AnasynchronouslevelcrossingADC(LCS)[ 20 ]isthesimplestkindofan asynchronousADCandisstructurallysimilartothesynchro nousashADC[ 21 ]. BoththeLCSandtheashADCcomparetheinputsignaltoNequa llyspacedvoltage quantizationlevelsandreportswhenthereisachange.Afew LCS-likearchitectures withadaptivequantizationlevelshavealsobeenreportedb yAgarwaletal.[ 22 ]andby Guanetal.[ 23 ].TheashADCgeneratesoutputsamplesataxeddatarate,t heLCS generatesasampleifandonlyifthesignalcrossesathresho ldlevel.Theasynchronous 23

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outputsampletimesarediscretizedusingasynchronousint erpolator,forrecoveryofthe signalthesamplesareltered. ThesynchronoussuccessiveapproximationADChasbeencust omizedfor asynchronousoperationbyKinnimentetal.[ 24 ]andContietal.[ 25 ].Theasynchronous implementationeliminatesbiterrorsresultingduetometa stabilityinthesynchronous architecture.Allieretal.[ 13 ]havepresentedthecompletedesignphilosophyalong withtheimplementationofanovelasynchronoussuccessive approximationADC usinganasynchronoussignalingscheme.Theauthorshavecl aimedthatthegureof merit(FOM),denedlaterinthechapter,oftheADCisanorde rofmagnitudehigher thanthatoftheconventionalADC.AnenergyefcientADCarc hitecturebasedonthe principlesofsuccessiveapproximationwasalsoproposedb yYangandSarpeshkar [ 6 ].AnimprovementoverAllier'sADC[ 13 ]wasproposedbyAkopyanetal.[ 26 ]by usingprinciplesofdeltamodulationfrom[ 27 ]andusingthemonanasynchronouslevel crossingADC.Intheproposedimplementation,theinputsig nalisencodedasa1oras a0dependingonwhetherthesignalisincreasingordecreasi ngresultinginafurther decreaseincircuitactivity.Priorknowledgeofthesystem delayeliminatestheexplicit needforatimekeeper.Anothervariationtotheconventiona lLCSwasproposedby JungwirthandPoularikas[ 28 ].InJungwirth'sscheme,acosineditherwasaddedtothe inputsignalresultinginareducedoddharmonicdistortion ascomparedtoSayiner's ADC[ 20 ].TheideaofaddingdithertothesignalwasextendedbyHurs tetal.[ 29 ]by usinga30KHztriangularditheralongwithasixth-orderpol ynomialinterpolator( f clk =500MHz)itwasshownthat10-bitresolutioncanbeachieved byusingjustseven comparators.TheadvantagethattheI&FhasovertheLCScome sfromthefactthat theI&FcircuithasnoquantizationandtheI&Fcanbeimpleme ntedwithjusttwo comparators,theexistingLCSinliteratureneedacomparat orforeveryquantization level. 24

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Anotherpopularclassofirregularsamplersistheasynchro noustime-varying thresholdcrossingsamplers(TCS).Theinputsignaliscomp aredtoasinglethreshold (orjustonequantizationlevel)andanoutputsampleisgene ratedwhentheinput signalcrossesthisthreshold.Asimpleexampleofthisisth ezerocrossingcircuit. Atimevaryingthresholdsamplercomparestheinputsignalt oathresholdfunction, ( t ) .Examplesofthesethresholdfunctionsincludeasinusoida lfunctionortriangular wave[ 18 ].Alowpowerneuralrecordingsystemhasbeendemonstrated byYinand Ghovanloo[ 30 ]byusingatriangularthresholdfunction.Theoutputofthe TCSispulse widthmodulated(PWM)signal,andtheinformationissavedi npulsewidths.Thepulse widthmodulationcircuitsarealsoknownasvoltage-to-fre quencycircuits[ 31 ]andare verywellstudiedincommunicationsystems.Theoutputofth eI&Fcircuitmayseem similartothePWM.However,theyarefundamentallydiffere ntsincetheoutputofthe I&FisasynchronouswhereastheoutputofthePWMissynchron ous.Needlesstosay thisleadstodifferentimplementationsaswell.WhiletheI &Fcircuitneedsjusttwo comparatorswithxedthresholds,thePWMcircuitstypical lyneedanonboardoscillator forgeneratingthetimevaryingthresholdcircuit.Theseos cillatorstendtobepower hogs.Anotherissuewithvaryingthresholdsisthat,output dataratetendstobemuch higherascomparedtotheI&F.TheadvantageofusingaPWMcir cuitovertheI&Fis thattheoutputdatacanbesynchronizedwiththeoscillator clock,whichleadstoamuch simplertransmissionandstorageoftheoutputsamples. Anotherapproachtoachievehighresolutionanalog-to-dig italconversionusing pulsedensityprinciplesisknownasdeltasigmamodulation [ 32 ].Inadelta-sigma modulatortheanaloginputsignalisintegratedandcompare dtoapredenedthreshold. Oncetheintegratedsignalexceedsthethresholdanoutputi sgenerated.Thisdigital outputisconvertedbacktoananalogsignalusingaDACandis subtractedfromthe integratedsignal.Moreadvancedversionsofthefeedbackl oop,knownashigher-order sigmadeltamodulators,areoftenusedtoachieveahigheref fectiveresolution.The 25

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mainstrengthofsigmadeltaconvertersisthatbyoversampl ingtheinputsignal thusnoiseshapingthequantizedsignal(thequantizationn oiseismovedtoahigher frequencybandascomparedtothedesiredsignalbandwidth) ,ahighereffective quantizationlevelcanbeachievedthantheactualnumberof quantizationlevelsinthe circuitarchitecture.Thedeltasigmaconvertersachievet hisfeatatthecostofahigher datarateascomparedtotheNyquistrate,largerchiparea,h igherdesigncomplexity andmuchhigherpowerconsumption.Fullyasynchronousandp artialasynchronous versionsoftheconventionalsigmadeltamodulatorshavere centlygatheredalotof attentionintheresearchcommunity[ 33 – 36 ].Fullyasynchronousversionshaveno clocksatall,whereasthepartialDSS,alsopopularlycalle dcontinuous-timedeltasigma converters,havesomeformofclock;eitherinthefeedbackl ooporinthefeedforward quantizationprocess[ 37 ]. Whiletheconceptsofnoiseshapingandquantizationarefai rlywellunderstood andestablishedforthesynchronousDSS,itisanactivearea ofresearchforthe asynchronoussamplers.AsynchronousDSShasbeenstudieda nddevelopedatCNEL byDazhiWeiinhisPh.D.work[ 38 ].Aspartofhisdissertationworkhedemonstrated thattheasynchronousDSSissuperiortoitssynchronouscou nter-partintermsof powerconsumption,outputdatarateandsimplicityofdesig nforthesameeffective numberofbits.AvariationoftheDSSknownasthedeltasampl erhasbeenproposed byCulurcielloetal.[ 15 ]forneuralrecordings,asthenamesuggeststhereisno integrationoftheinputsignal,anoutputpulseisgenerate dwhenthesignalexceeds apredenedthreshold, ,resultingintheinputsignalbeingreset.Sinceanoutput sampleisgeneratedeverytimetheinputsignalcrosses andisresettozerothereafter, thisimplementationcanbealsobevisualizedasaverysmart levelcrossingsampler. Thereasonforthisisthattheoutputsamplesaregenerateda tintegermultiplesof 26

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+ Vdd C m V thtV m I in Delay V mid V out Figure2-2.ConventionalIntegrateandFire(I&F)sampler. ThisstructurefortheI&F anditsvariationshavebeenusedinvariousneuromorphicci rcuitdesigns [ 40 – 49 ] 2.2.1Integrate-And-Fire(I&F)Sampler TheblocklevelschematicoftheI&Fsampler,proposedin[ 39 ],isshowninFigure 2-3 .Theinputsignal, I in ,isintegratedonthecapacitor, C m ,resultinginavoltage, V m whichiscomparedagainstpositiveandnegativethresholds V th ,usingtwoanalog comparators.Whenoneofthetwothresholdsisreached,theo utputoftherespective comparator, V out ,goeshigh,generatinganoutputpulseandresetting V m to V mid Thecapacitorvoltageisthenheldat V mid forapredenedtime, r afterwhichthe processrepeats.TheI&Farchitecture,proposedin[ 39 ],isdifferentfromsomeofthe otherimplementationsoftheI&F[ 40 41 ].Thisimplementationusestwocomparators forseparatelyencodingthepositiveandthenegativeparts ofthesignalwhereasthe popularapproachistouseonlyonecomparator.Usingonecom paratormaybemore biologicalbutitimpliesthatthesignalneedstobeDCshift edtorepresentsigned signals,whichleadstoanon-zerominimumoutputpulserate .Thelimitationofthis structureisthattheinputsignalwouldhavetobeeitherabo veorbelow V mid implying thataDCshiftwouldhavetobeaddedtotheinputsignal.ADCs hiftwouldresultin pulsesbeinggeneratedeveniftheinputsignaliszeroresul tinginwastedbandwidthand power.AsolutiontothiswasproposedbyDuChenin[ 39 ].Itusestwocomparatorsto generateseparatepositiveandanegativeoutputdatastrea m,hencecalledtheBiphasic I&F.TheblockleveldiagramisshowninFigure 2-3 .Thepositiveandnegativeoutput 27

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+ Vdd C mtI in Delay V mid + tV m Delay V mid V th + V thV out + V outV outV out + Figure2-3.BiphasicIntegrateandFiredataconverterprop osedby[ 39 ]. -0.1 -0.05 0 0.05 0.1 Amplitude in VoltsSine Wave Input and the Measured Output Pulses from the Biphasic neuron chip -1 0 1 2 3 4 5 6 7 8 x 10 -3 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 Time in SecondsAmplitude in Volts (AC coupled) Positive Channel Negative Channel Figure2-4.PositiveandNegativechannelpulseoutputsfor asinewaveinputas measuredfromthechipoutput. pulsesaregeneratedbythetopandbottomcomparatorsrespe ctivelyasshownin Figure 2-3 .Thetopcomparatorhasapositivethreshold V th + andthebottomcomparator hasanegativethreshold V th andbothhavetheirrespectiverefractoryperiod.Figure 2-4 showsthepositiveandthenegativechannelpulsesoutputs, forasinewaveinput. AsevidentfromFigure 2.1 thebiphasicI&Fcircuitadjuststheoutputdatarateasa functionoftheinputsignalamplitude.Avariationtothebi phasicI&Fcircuitcalledasthe TimeDerivativeNeuron(TDN)[ 50 ]wasproposedbyJieXu,atCNELaspartofPhD research.TheTDNexploitstheslopeoftheinputsignaltoge neratetheoutputsample. AnadaptivecircuitwasaddedtothebiphasicI&FbySteveYen aspartofhisresearch 28

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workatCNEL[ 51 ].TheadaptiveI&Fadaptsthethresholdofthecomparatorst ofurther reducetheoutputdatarate.2.2.2ReconstructionAlgorithm Ithasbeenshownthattheoriginalsignalcanbereconstruct edperfectlyfrom theseasynchronouspulsetrains[ 52 – 54 ].Thesignalreconstructionisbuiltonthe frameworkpresentedbyLazarandTothin[ 55 ]linkingmathematicalframetheoryand reconstructionforthecaseofasynchronoussigma-deltaco nverters.Forcompleteness thereconstructionalgorithmproposedbyDazhiWeiasparto fhisdissertation[ 38 ]is presentedbelow. ThesignalreconstructionfromtheI&Fpulsescanbetreated asanon-uniform samplingproblem.Itcanbeshownthatanybandlimitedsigna lcanbeexpressed asalow-passlteredversionofanappropriatelyweighteds umofdelayedimpulse functions[ 56 57 ].Thusasignal x ( t ) bandlimitedto [ n s ,n s ] canberepresentedas: x ( t )= h ( t ) X j w j ( t s j ) = X j w j h ( t s j ) (2–1) where: 1. w j arescalarweights 2. h ( t )= sin (n s t ) = (n s t ) ,theimpulseresponseofthelowpasslter 3. *denotesconvolution 4. s j 'sarethetimingsoftheimpulsetrain. 5. Itisassumedthatthemaximumadjacentsampletimingisless thantheNyquist period T = = n s TheringtimesofthepulsesfromtheI&Fcircuitmustsatisf ythefollowing: Z t ie t ib x ( t ) dt = 8 i (2–2) 29

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where isdenedas( V th + C m )or( V th C m )dependingifthespikewasredbythe positivecomparatororthenegativecomparatorand t ib and t ie denotethebeginningand theendoftheintegrationperiod.Assumingthatthemaximum adjacentintervalbetween thepulsesislessthantheNyquistperiod T = = n s i.e. ( t ( i +1) b t ib < T ,( t ( i +1) e t ie < T ).Thenx(t)canbeexpressedasinEquation 2–1 SubstitutingEquation 2–2 into Equation 2–1 i = Z t ie t ib x ( t ) dt = Z t ie t ib X j w j h ( t s j ) dt = X j w j Z t ie t ib h ( t s j ) dt = X j w j c ij (2–3) where c ij areconstantsthatcanbenumericallycomputedwith: c ij = Z t ie t ib h ( t s j ) dt (2–4) Theresultingsetoflinearequationsgivenby CW = isinthematrixformwhereWisa columnvectorwith w j asthe j th rowelement, C isasquarematrixwith c ij asthe i th row and j th columnelementand isacolumnvectorwith i asthe i th rowelement.Usually Cisill-conditionedandsomewell-knowntechniquesmustbe employedtostabilizethe computation.Thustheweightvectorcanbeestimatedusing: W = C 1 (2–5) 30

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ThusEquation 2–5 canbesubstitutedintoEquation 2–1 tonumericallyreconstructthe signalfrompulses.Thus x ( t ) canberepresentedas: x ( t )=[ h ( t s j )][ c 1 ji ][ i ] =[ X j h ( t s j )[ c 1 ji ][ i ] =[ h i ( t )][ i ] = X i h i ( t ) i (2–6) where [ c 1 ji ] isthe j th rowand i th columnelementoftheinversematrix C 1 and h i ( t )= X j h ( t s j ) c 1 ji (2–7) 2.3Signal-To-NoiseRatio Althoughanalyticallywehaveshownthatthesignalcanbere coveredperfectly undercertainconstraints,therearesomeimplementationi ssuesthatdegradethe recoveredsignal.Inordertoquantifythequalityoftherec overedsignalweuse signal-to-noiseratio(SNR)astheperformancemetric.SNR isdenedas: SNR =10log SignalPower = NoisePower (2–8) Oneoftherstimplementationissuesisthatforstoring/pr ocessingtheseasynchronous samplesinthedigitalformatrequiresthatthesampletimes bequantized.Time quantizationimpliesthattheoutputsampletimeswillnolo ngerbeconstrainedby Equation 2–2 .Thejitterinsampletimesorthejitterin i dependsontheinputsignaland thequantizationclockleadingtodegradationintheSNR.Ta kinganapproachsimilarto theonepresentedin[ 12 13 ]weestimatetheSNRasafunctionofthetimequantization andsignalproperties.InaconventionalADC,thenoisepowe riseasilydeterminedsince wehavedirectaccesstotheestimatedsampleaswellastothe originalvalue.Inthe caseoflevelcrossingsamplersortheI&F,wedonothavedire ctaccesstotheerrorat 31

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eachsampleandthereforeitisnotasstraightforward.Inth iscase,theerrorateach samplepointisgivenasthedifferencebetweentheoriginal functionandtherecovered signal.Thetimingerrorduetothequantizationisassumedt obeauniformlydistributed randomvariableintheinterval[ T clk = 2, T clk = 2 ]where T clk istheclockperiodofthetime quantizer.Furtherassumingthattwoconsecutivesamplesa ttime t i t i +1 arequantized to ^ t i ^ t i +1 suchthat ^ t i =( t i + i ) and ^ t i +1 =( t i +1 + i +1 ) .Theerrorduetoquantization canbeexpressedasanerrorinestimating i inthereconstructionequation: e ( t k )= x ( t k ) ^ x ( t k ) (2–9) = X i g i ( t k )( i ^ i ) (2–10) Where x ( t k ) ^ x ( t k ) aretheoriginalandthereconstructedsignalsrespectivel yand signals t k correspondstoaspecicsamplepoint.Weassumethesignali sconstant duringtimeintervals f t i ^ t i g and f t i +1 ^ t i +1 g .Thereforethedifference i ^ i canbe writtenas [ i x ( t i )+ i +1 x ( t i +1 )] .Thevarianceoftheerror,orquantizationnoisecanthen bedenedby: P quant = E X i g i ( t )( i ^ i ) 2 (2–11) = E X i g i ( t )( i x ( t i )+ i +1 x ( t i +1 )) 2 Sincetheerrorisalsodeterminedbytheevaluationof g i ( t ) and x ( t ) ,theexpectation isover g i ( t ) x ( t ) i .Weassumeallofthesetobeindependentofoneanother. Furthermore f i i +1 g arezeromeanindependentrandomvariablesuniformly distributedintheinterval[ T clk = 2, T clk = 2 ]and E f g i g i +1 g =0 .Equation 2–11 can 32

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berearrangedandsimplied: P quant = X i E f g 2 i ( t ) g ( E f 2 i g E f x 2 ( t i ) g + (2–12) E f 2 i +1 g E f x 2 ( t i +1 ) g ) = 1 6 X i E f g 2 i ( t ) g ( T 2 clk P s ) Notethatthepowerofthesignalcanbewrittenas: P s = E f x ( t ) g = X i E f g 2 i ( t ) 2 i g (2–13) Thesignaltonoiseratio(SNR)canthenbewrittenasfollows wherewehaveassumed j i j = 8 i : SNR quant =10log P s 1 6 P i E f g 2 i ( t ) g ( T 2 clk P s ) (2–14) =10log 6 2 T 2 clk P s Thusfor x ( t )= A sin( in t ) Equation 2–14 canberewrittenas: SNR quant =10log 12 2 T 2 clk A 2 (2–15) Insummary,Equation 2–14 istheSNRoftheI&Fsamplerasafunctionofthe quantizationclockandtheinputsignalundertheassumptio nthat and r areprecisely knownanddonotvarywithtime.ThevariationoftheSNRwith T clk forasimulatedI&F samplerandEquation 2–15 areshowninFigure 2-5 .TheSNRforthesimulatedI&F followsEquation 2–15 andplateausnear100dBduetolimitedprecisionofthemachi ne. TheslightdifferencebetweenthesimulatedI&Fand 2–15 athighertimeperiodsstems fromtheassumptionthattheerrors f i i +1 g areindependent. 2.3.1PerformanceMetrics SNRisoneofseveralmetricsforevaluatingtheperformance ofthesampler. HoweversynchronousADCshavetraditionallybeenevaluate donthebasisofthe 33

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0 20 40 60 80 100 120 140 160 180 200 220 1e-009 1e-008 1e-007 1e-006 1e-005 SNR (dB)T clk (sec) Matlab simulation of the IF sampler with time quatization. Numerical evaluation Figure2-5.SNRvs.theclockperiodusedforquantizingthes ampletimes.TheSNR aboveiscalculatedfora 750 nA sin(2000 t ) withthethresholdsetat0.4V and C m =20pF effectivenumberofbits(ENOB).TheENOBrepresentstheeff ectiveresolutionofa conventionalADC[ 58 ]: ENOB = SINAD 1.76 6.02 (2–16) WhereSINADisthemeasuredSNRplusdistortionandincludes allthenon-idealeffects ofapracticalconverter.SincetheI&Fsamplerdoesnothave xedquantizationlevels andwearequantifyingitsperformanceintermsofaconventi onalADCweuseEquation 2–16 forconvertingbetweentheSNRofthereconstructedsignala ndtheENOB.ENOB isafunctionofbothamplitudeandfrequency[ 59 ].Withaxednumberofquantization levels,foraconventionalADC,ENOBislimitedbytheminimu mquantizationnoisefor lowamplitudesignalsanddistortionsathigheramplitudes .Asanexample,aninput signalwhichislessthantheleastsignicantbit(LSB)wast obegiventoanADC,the outputwouldbezero.Similarlyiftheinputsignalwastobeh igherthanthemaximum quantizationleveltheADCoutputwouldsaturateandleadto distortions.Sincethere 34

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arenoquantizationlevelsintheI&F,asmalleramplitudesi gnaljustproducesfewer pulsesandthesignalcanstillberecovered.Similarlyahig heramplitudesignalmeans higherpulseratewhichmeansamuchbetterrecoveryofthesi gnal.Also, V th and r canbevariedtomanipulatethepulserateaccordingtothein putsignalcharacteristics. Forexampleforalowamplitudesignal V th and r canbeloweredforattainingahigher pulserate.AmorecomprehensivemeasureofsynchronousADC performanceisthe gureofmerit(FOM),denedas[ 58 ]: FOM = Power 2 ENOB min( f sample ,2 BW ) (2–17) where f sample isthesamplingrateandBWisthesignalbandwidth,theminim umofthe twoistakentoaccommodateoversamplingdataconverters.U nliketheconventional ADCs,theasynchronousADCs,donotgeneratesamplesataxe dratehenceweuse BWinsteadof f sample inestimatingtheFOMfortheI&Fsampler. 2.4Summary Inthischapteranoverviewoftheworkdoneintheeldofasyn chronousdata converterswaspresented.Wealsopresentedthepriorworkd oneonI&Falongwitha reviewofthereconstructionalgorithm.Ananalyticalmode lisdevelopedforanalyzing theeffectoftime-quantizationoftheoutputsamples.Them odelisveriedwiththe measurementresults.Existingperformancemetricsforthe ADCsarediscussed. 35

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CHAPTER3 LOWPOWERINTEGRATE-AND-FIRECIRCUIT InthischapterthecircuitimplementationoftheI&Fcircui tispresented.Various comparatorarchitecturesareexploredandanalyzedinterm softhespeed-resolution trade-off.SourcesofpowerdissipationintheI&Fcircuita realsoanalyzedanda methodologyforreducingthepowerconsumptionispresente d.Somenovellowpower circuitdesignsarepresented.Towardstheendofthechapte rsimulatedandmeasured resultsarepresentedfollowedbyabriefsummaryandpropos edfuturework. 3.1CircuitDesign AsshowninFigure 2-3 theI&Fcircuitconsistsofjustcomparators,delayelement s andresettransistors.AsdiscussedinChapter2,thekeymot ivationforusingasynchronous samplersislowerpowerconsumptionascomparedtoconventi onalsamplers.Wewill seelaterinthischapterthemajorsourcesofpowerconsumpt ionintheI&Fsamplerare thecomparators.Thus,inthissectionthecomparatordesig nisdiscussedindetail.The speed-resolutiontrade-offofexistingcomparatortopolo giesisdiscussed. 3.1.1Comparator Thecomparatorisusedtodetectwhetherthevoltageontheca pacitor V m is largerorsmallerthanthethreshold V th andthenrepresenttheoutcomeasalogic0 (if V m < V th )oralogic1(if V m > V th ).Theinputsignalisintegratedonthecapacitor, whentheintegratedsignalbecomesgreaterthanthereferen cevaluethecomparator generatesoutputlogic1.Thecapacitoristhenresetafters omedelaycalledthe refractoryperiod,theoutputofthecomparatoragaingoest ologic'0'andtheprocess isrepeated.Foranidealcase,thecomparisontakesplaceat theprecisethreshold voltageandtheoutputrisesinstantaneously.However,for arealcomparatorthe comparisontakesplaceatavoltageslightlyhigherorlower thanthesetthresholdvalue duetofabricationprocessrelatedmismatches,resultingi naxedoffset.Also,areal comparatorhasnitegainandbandwidththeoutputrisesonl yaftersomedelayknown 36

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asthepropagationdelay.Thechoiceofthecomparatordesig nrestsonhowoffset, speedandpowerconsumptionaffecttheendapplication[ 60 ]. Fixedorsystematicoffsetcanbeaccountedforintherecons tructionalgorithmby usingtheactualthresholdvalue,i.e. V th oset ,inEquation 2–5 .Thepropagationdelay, ontheotherhand,dependsontheinputsignalrepresentingi tselfasasignal-dependent jitterorthresholdvariation[ 61 ].Thissignaldependentreferencevariationishardto estimateandcorrectforinthereconstructionalgorithmsi nceitnotknownbefore-hand 1 TheI&Fencodesthesignalinformationintimethereforesig naldependentjitterintiming wouldshowitselfasanerrorinthereconstructedsignal.He nceitisessentialthatthe comparatorisdesignedforminimumsignaldependentjitter 3.1.1.1Comparatortopology Thespeedofthecomparatorisinuencedbydesignparameter ssuchastransistor sizesandthebiascurrentanditalsodependsonthecircuitt opology[ 62 ],henceit isessentialtoexaminecomparatortopologiesindetail.Co mparatorsareessentially voltagegaincircuitswhichamplifythedifferentialinput voltage( V in V th )togivean outputoflogiconeoralogiczero.Thusanyop-amparchitect urecanbeusedasa comparator,howevertheresolutionofasingleop-ampislim itedbythestaticgainof theamplier[ 63 ].Thegainoftheamplierscanbeincreasedbycascadinganu mber oftheseop-ampsresultinginamultiplicativeincreaseint heoverallgain.Anotherclass ofcomparatorsemployspositivefeedbacktobuildaveryfas tandaveryhigh-gain aroundthetrippoint( V in V th 0 ).Figures 3-1 3-3 and 3-2 showtheschematicand correspondingthesmallsignalmodelofasinglevoltageamp lier,cascadeofampliers, andalatchbasedpositivefeedbackcomparator.Thegeneral speed-resolutiontradeoff 1 Weareexploringaniterativeschemeofrepeatedlyreconstr uctingandestimating thedelay 37

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foreachofthecomparatorarchitecturesissummarizedbelo w,moredetailscanbe foundin[ 62 – 64 ]: Singlevoltageamplier T p c V oh in (3–1) Nidenticalvoltageampliers T p c N V oh in 1 N (3–2) Latchbasedpositivefeedbackcomparator T p c log V oh gm latch in gm in (3–3) where: 1. T p isthepropagationdelayofthecomparator. 2. c =1 =! c where c isthe-3dBfrequencyofthecomparatorandisgivenby gm in = C o 3. T p = c isthenormalizeddelay. 4. in isthestepinputtothecomparatorgivenby V in ( t ) V th 5. V oh isoutputvoltageleveloflogic'1' 6. InordertosimplifytheresultinEquation 3–1 itisassumedthat ( gm in r out ) in V oh ;( gm in r out isthestaticgainoftheamplier) 7. InordertosimplifytheresultinEquation 3–2 itisassumedthat ( g m r out ) N in V oh ;( gm in r out isthestaticgainofasingleamplier) 8. InEquation 3–3 gm latch isthetransconductanceofcross-coupledtransistor M 5 as showninFigure 3-2 9. InEquation 3–3 itisassumedthat gm latch gm diode isthetransconductanceof diodeconnectedtransistor M 3 asshowninFigure 3-2 10. InFigure 3-2 itisassumedtransistorpairs M 1 M 2 M 3 M 4 and M 5 M 6 are identicalwitheachotherrespectively. 38

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Vdd Vdd V in V th V bias g m D in r out C out V out V out Figure3-1.SingleVoltageAmplierandthecorrespondings mallsignalmodel Vdd Vdd Vdd Vdd Vss V bias M 1 M 2 M 3 M 4 M 5 M 6 V in V th V o1 V o2 g m1 V in 1/gm 3 g m5 V o2 C o V o1 1/gm 3 C o g m1 V th g m5 V o1 Latch Diodes Diodes V o2 Figure3-2.Latch-basedpositivefeedbackcomparatorandi tsequivalentsmallsignal model.Transistorpairs M 1 M 2 M 3 M 4 M 5 M 6 areidenticalhence g m 1 = g m 2 ; g m 3 = g m 4 ; g m 5 = g m 6 aroundthetransitionpoint. 39

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+ + + ...... + N V in V th C o Figure3-3.AcascadeofNidenticalsinglestageampliersa reusedforamore favorablespeed-resolutiontradeoff. Thespeed-resolutiontradeoffissummarizedinFigure 3-5 fora V oh valueof1.65 V 1 .Figure 3-5 showsthepropagationdelaynormalizedwithrespecttothet ime constantoftheamplier, T p = c ,vs.thestepinputvoltage, V in ( t ) V th ,fortheabove mentionedcomparatortopologies.Asitisevidentfromthee quationsandthesingle amplierhastheworstnormalizeddelay,multipleamplier sprovideamorefavorable speed-resolutiontradeoffhoweveratthecostofincreased powerandarea.Also,further analysisofthespeed-resolutiontradeoffpresentedin[ 60 62 ]showsthatfordifferent valuesofthestepinputtheoptimumnumberofampliersinth ecascadearchitecture, N,varies.Thelatchbasedcomparatorsontheotherhandpres entthebestspeed resolutiontrade-offamongstthethree.Figure 3-5 showsthenormalizeddelayforalatch basedcomparatorvs.thestepinputvoltagefordifferentva luesoftheratio gm latch = gm in Thelowerthevalueoftheratio,thefasteristhecomparator .Amoredetaileddiscussion, analysisandthederivationoftheaboveresultsonvariousc omparatorarchitecturescan befoundin[ 62 64 65 ].Theoutputsfromthelatchneedtobeconvertedtocorrectl ogic levelsthusanoutputstageisrequired.Figure 3-4 showsthecompleteschematicofthe latchbasedcomparatorwiththeoutputstage. 1 Assumingthatthecomparatordrivesaninverterwithatripv oltageof1.65V 40

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Vdd Vdd Vdd Vdd Vss V bias M 1 M 2 M 3 M 4 M 5 M 6 V in V th V o1 V o2 Vdd Vss Vdd Vss M 7 M 8 M 9 M 10 Figure3-4.Latch-basedpositivefeedbackcomparatorwith outputstage.Transistors M 7 M 10 areneededtoconverttheoutputofthelatchtoequivalentlo gic levelvoltages. 10 -1 10 0 10 1 10 2 10 3 10 4 0 10 20 30 40 50 60 70 80 90 100 Normalized Delay Vinput (mV) Single Step Comparator Multi Step Comparator N = 2 Multi Step Comparator N = 6 Multi Step Comparator N = 10 Latch based Comparator gm latch /gm in = .1 Latch based Comparator gm latch /gm in = .3 Latch based Comparator gm latch /gm in = .5 Latch based Comparator gm latch /gm in = .7 Figure3-5.Normalizedcomparatordelayvs.stepinputsize inmVfordifferent comparatortopologieswiththesamebiascurrent. 41

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3.1.1.2Hysteresis InEquation 3–3 itwasassumedthat gm latch gm diode (inFigure 3-2 and 3-4 gm 5 gm 3 ),thisresultsinastrongerpositivefeedbackduringthetr ippointthereby increasingthetransitionslopeofcomparator.However,it introduceshysteresisinthe comparatorresponse.Theresponseofanormalcomparatorwi thouthysteresiscanbe summarizedas: V out = 8><>: Logic0for V i n ( t ) < V th Logic1for V i n ( t ) V th (3–4) Theresponseforacomparatorwithhysteresisis: V out = 8>>>><>>>>: Logic0for V in ( t ) < ( V ref V trip ) Preservesthepreviousoutputfor ( V ref V trip ) < V in ( t ) < ( V ref + V + trip ) Logic1for V in ( t ) > ( V ref + V + trip ) (3–5) Usingthesquarelawmodel,forthecircuitschematicinFigu re 3-2 ,theexpressionfor V + trip and V trip canbewrittenas: V trip = V + trip = 2 i 1 1 1 = 2 + V T 1 2 i 2 2 1 = 2 V T 2 (3–6) UsingtheEKVmodel[ 66 ]andthedesignequationspresentedin[ 67 ], V + trip and V trip can beexpressedas: V trip = V + trip =2 nu T log( e p IC 1 1)+ V T 1 2 nu T log( e p IC 2 1) V T 2 (3–7) where: 1. ( i 1 V T 1 ) and ( i 2 V T 2 ) arethesmallsignalcurrentandthresholdvoltageof transistors M 1 and M 2 respectively. i 1 and i 2 canbewrittenas: i 1 = I bias 1+[( W = L ) 5 = ( W = L ) 3 ] (3–8) i 2 = I bias I bias 1+[( W = L ) 5 = ( W = L ) 3 ] 42

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30 40 50 60 70 80 90 1e-008 1e-007 1e-006 1e-005 Vtrp+ (mV)IBias (A) Measured Hand Calculation Figure3-6.Measured V + trip andEquation 3–7 vs. I bias .( W = L ) 5 = (6.75 m = 3 m ),( W = L ) 3 =(3.0 m = 3.0 m ),( W = L ) 2 =(9 m = 3 m ) 2. n =( C OX + C DEP ) = C OX ,itisthecapacitivedivisionbetweengate,surfaceand body, C OX isthegateoxidecapacitanceperunitareaand C DEP isthedepletion capacitanceperunitarea. 1 = n isalsoknownasthesubthresholdslopefactor. 3. u T isthethermalvoltagegivenbykT/qandapproximatelyequal s25mVatroom temperature. 4. IC 1 IC 2 aretheinversioncoefcientsfortransistors M 1 M 2 respectivelyandare denedas: IC 1 = i 1 2.8 C OX ( W = L ) 1 u 2 T = i 1 I on ( W = L ) 1 IC 1 = i 2 2.8 C OX ( W = L ) 2 u 2 T = i 2 I on ( W = L ) 2 (3–9) Figure 3-6 comparesthemeasured V + trip andEquation 3–7 asafunctionofI bias .Thereis anapproximatescalingfactorof1.25betweenthemeasureda ndthehandcalculation. Also,if1.4isusedinsteadof2.8inthedenominatorofEquat ion 3–8 thenthetwo curvesalign.Sincethecomparisonhappensatavoltagediff erentthanV th ,inthe 43

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V delay Vdd Vss V in V in V out tt Refractory in rising edge V delay Vdd Vss V in V out V in V out tt Refractory in the falling edge M 1 M 3 M 3 V out M 1 M 2 M 2 Figure3-7.Twopossibleimplementationsoftherefractory component.Therefractory periodcaneitherbeontherisingedgeoftheoutputvoltageo ronthefalling edgeoftheoutputvoltage. reconstructionalgorithm V th + V + trip isusedinsteadof V th .Since V + trip dependsonly onthebiascurrentandthetransistorgeometries,itcanbee stimatedbeforehandand accountedforinthereconstructionalgorithm.Aslongasth emembranevoltageisreset ataveryfastrateand V mid < V th V trip apulsewillnothaveanyeffectofthepreceding pulse. Note: Fromthispointonwards V th isassumedtoincludethehysteresisvoltage. 3.1.2RefractoryComponent Thedelayelementservesthepurposeofreducingthebandwid th,itdoessoby keepingthecapacitorvoltageat V mid forapre-determinedtimeafterthecomparator hasredapulse.Thecircuitimplementationforthedelayel ementisshowninFigure 3-7 .Thecircuitwasproposedin[ 68 ]andhasbeensuccessfullyusedforlimitingthe pulserateoftheI&Fcircuitby[ 52 69 ]andotherneuronimplementations[ 40 ].The circuitisessentiallyanasymmetriccurrent-starvedinve rter.Thecircuitoperateslikea normalinverterforthehigh-to-lowinputtransitionwith M 1 fullyturnedonandcharging theoutputnode,howeverforalow-to-highinputtransition thecurrentthroughtransistor M 2 islimitedbythecurrentthroughtransistor M 3 whichissetbythevoltage V delay Thislimitedcurrentthroughthistransistorresultsinade layindischargingtheoutput node,resultinginanextendedpulsewidth.Thedelaycanbec ontrolledbyappropriately 44

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changing V delay .Thedelaycanbeapproximatedas: fall = C load Vdd C ox ( W 3 = L 3 ) V 2 delay (3–10) Vdd Vdd Vdd Vdd Vss V bias M 1 M 2 M 3 M 4 M 5 M 6 V in V th V o1 V o2 Vdd Vss Vdd Vss M 7 M 8 M 9 M 10 Vdd Vss Vdd Vss Vdd Vss M 11 M 12 M 13 M 14 M 15 M 16 M 17 M 18 Vdd C m V mid M 19 V delay V out+ I in V reset+ C o2 C o1 V oc2 V oc1 C oc2 C oc1 Figure3-8.Thecompleteschematicofthepositivechannelo ftheI&Fcircuit.The negativechannelissymmetrictothepositivechannel,itis notshownin ordertosimplifytheschematicshownhere.Selectparasiti ccapacitances areshownindottedline. ThecompleteschematicforthepositivechanneloftheI&Fci rcuitisshowninFigure 3-8 .Thecircuitshownisdifferentfromthepreviouslypropose dbiphasicI&Fcircuit [ 52 70 71 ].Inadditiontothechangeinthecomparatorschematic,the ORgateinthe resetloophasbeenremovedandthepositionoftherefractor ycomponenthasbeen changed.Thevalidoutputstatesforpositiveandthenegati vechannelsofthebiphasic I&Fcircuitare f 00,10,01 g ,sincetwochannelsareindependentbythevirtueofdesign anddenition.ThereforeanORoperationoftheoutputsofth etwochannelsisnot requiredandhencehasbeenremovedfromthedesignproposed by[ 52 70 71 ].The seconddifferenceisthattherefractorycomponentwasprev iouslyinthe'ON'periodof 45

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theoutputpulsewhichimpliedthattherefractorycomponen twoulddriveaninverter. Thiswouldresultinanincreasedshort-circuitpowerofthe inverterbeingdrivenbythe refractorycomponent,thustherefractorycomponenthasbe enplacedsuchthatthe refractoryperiodisinthe'OFF'period. 3.2ComparatorDelay Inthissectionthedelayingeneratingthespikeduetothen itegainofthe comparatorisanalyzedalongwiththeimpactontherecovere dsignal.First,the comparatordelayismodeledthentheimpactofthisdelayont hereconstructionis analyzedbybuildingananalyticalmodelfortheimpactofde layonthesignal-to-noise ratio(SNR).Themodelisveriedcomparingagainstthecirc uitsimulationsfrom Cadence.Figure 3-4 showstheschematicofthecomparator.Thepropagationdela y, T pd ,isdenedasthetimetakenforthelow-to-hightransitiona ttheoutputoftheI&F thatisthetimeittakesfortheI&Ftogeneratethepulsewhen V mem V th .Inthe equationsbelow,subscriptsHLandLHindicateHigh-to-Low andLow-to-Hightransitions respectively. T pd canbeexpressedasthesumoftheindividualdelays(amoreac curate andcomplicatedanalysiswouldbetocalculatethecombined delayusingtransfer functionsforindividualcircuitblocks): T pd = T comp + T inv 1 LH + T inv 2 HL + T ref LH (3–11) where: 1. T comp isthetimeittakesforthecomparator(transistorsM 1 -M 11 )inFigure 3-8 )to resolvethedifferentialinput.Thiscanbeestimatedbyrs twritinganexpression forV oc2 ,inFigure 3-8 ,intermsofV in andV th andthensolvingforthetimeittakes forV oc2 toreachtheinvertertripvoltage. V oc 2 [ gm 7 R out (1 e t R out C oc 2 )] gm 1 gm 5 ( V in V th ) e gm 5 t C o 1 (3–12) where: 46

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(a) R out istheequivalentoutputresistanceatnode V oc 2 andisgivenby( r 8 jj r 10 ). Wherer 8 andr 10 arethesmallsignaloutputresistancesofthetransistorsM 8 andM 10 (b) C o 1 istheparasiticcapacitanceatnodeV o1 andcanbeestimatedas: C o 1 =2 C gd 2 + C db 2 + C gs 4 + C db 4 + C gs 8 +2 C gd 8 +2 C gd 6 + C gs 6 +2 C gd 5 + C db 5 C gol (2 W 2 + W 4 +3 W 8 +3 W 6 +2 W 5 )+ C jb ( W 2 L 2 + W 4 L 4 + W 5 L 5 ) +2 C jbsw (( L 2 + W 2 )+( L 4 + W 4 )+( L 5 + W 5 )) + 2 C OX 3 ( W 4 L 4 + W 8 L 8 + W 6 L 6 ) (3–13) (c) C oc 2 istheparasiticcapacitanceatthenode V oc 2 andisgivenby: C oc 2 = C db 8 +2 C gd 8 +2 C gd 10 + C db 10 + C gs 12 +2 C gd 12 + C gb 12 + C gs 13 +2 C gd 13 C gol ( W 10 L 10 + W 12 L 12 )+ C jb ( W 8 L 8 + W 10 L 10 + W 12 L 12 ) + C jbsw (2( W 8 + L 8 )+2( W 10 + L 10 )+2( W 12 + L 12 )) + 2 C OX 3 ( W 12 L 12 + W 13 L 13 ) (3–14) (d) gm 1 ,gm 5 andgm 7 arethetransconductancesoftransistorsM 1 ,M 5 andM 7 respectively.UsingtheEKVequationsfrom[ 72 73 ]transconductancecanbe expressedas: gm i = I i 1 e p IC i nU T p IC i 8 i 2f 1,5,7 g (3–15) I i andIC i arethedraincurrentandtheinversioncoefcientofthei th transistor. TheinversioncoefcientisdenedbyEquation 3–9 .Thedraincurrentfor transistorsM 1 andM 5 equalsI bias /2.Inabsenceofaxedbiascurrentthrough transistorsM 7 -M 10 ,I 7 iscalculatedusingV o1 aroundthetrippoint.The effectiveV o1 forthiscalculationistakenmid-waybetweentheresulting voltage whentheentirebiascurrentowsthroughtransistorM 3 andtheresulting voltagewhentheentirebiascurrentowsthroughM 4 i.e.nocurrentows throughM 3 UsingaTaylorseriesexpansionfortheexponentialtermsin Equation 3–12 ,using onlyrstthreesignicanttermsfromeachexpansionandsol vingtheresulting quadraticequationgivesthefollowingexpressionforT comp : T comp 2 1 1+ 1 4 2 1 1 V oc 2 K s ( V in V th ) 1 2 2 ( 2 1 ) (3–16) (a) 1 =C co1 /gm 5 47

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0 1 2 3 4 5 6 7 8 9 10 0.01 0.1 1 10 Delay (usec)I bias (uA) Measured Delay Equation 3-19 Figure3-9.MeasuredT comp andequations 3–16 3–17 3–18 vs.I bias .Thecomparator overdrivevoltagewassetat1mVi.e.V in -V th =1mV. (b) 2 =R out .C oc2 (c) K s =(gm 7 .R out .gm 1 )/gm 5 Equation 3–16 istoocomplicatedtouseinfurtheranalysis.Itcanbesimpl ied furtherbyrealizingthat 2 1 ,sinceforaCMOSdevice1/gds 1/gm.Therefore approximating 2 1 2 Equation 3–16 canbesimpliedto: T comp 1 2 1 + 2 1 4 1 2 V oc 2 K s ( V in V th ) 1 2 (3–17) 1 2 2 1 4 1 2 V oc 2 K s ( V in V th ) 1 2 (3–18) 1 2 V oc 2 K s ( V in V th ) 1 2 (3–19) Figure 3-9 comparesequations 3–16 3–17 3–18 ,, 3–19 andthemeasured delayversusthebiascurrentfora1mVoverdrivevoltage(V in -V th =1mV).Itis evidentfromthegurethatEquation 3–18 isareasonableapproximationforthe comparatordelay. 2. T inv 1 LH T inv 2 LH T ref LH arethecorrespondingpropagationdelaysofthe 1 st inverter(transistors M 12 M 13 ), 2 nd inverter(transistors M 14 M 15 )andthe refractory(transistors M 16 M 18 )respectively.Usingprinciplesoflogicaleffort[ 74 48

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75 ]thecombineddelayoftheinverterandtheoutputstagecanb eapproximated as: T inv 1 LH + T inv 2 HL + T ref LH 0.2 L min 2 W 19 W 12 + W 13 +3 (3–20) (a) 0.2 L min = 2 isthetechnologydelayinpico-secondsand L min istheminimum channellengthinnanometers[ 74 ]. Note: Itisevidentfromequations 3–18 and 3–20 thatthedominantdelayisthe comparatordelay. Similartotheaboveanalysis,theI&Ftakestimetoreset,re sultinginanite pulse-width, T pw : T pw = T discharge + T comp + T inv 1 HL + T inv 2 LH + T ref HL (3–21) where: 1. T discharge isthetimetakentodischargethemembranecapacitor, C m andcanbe approximatedas: T discharge = W 19 R on nmos ( C m + C p )log V th V mid (3–22) (a) R on nmos isthe”ON”resistanceperunitlengthofaNMOStransistorfo ragiven technology. (b) C p istheparasiticcapacitanceinparalleltothemembranecap acitance C m 2. Theexpressionfor T comp issimilartothedelayexpressedinEquation 3–16 .Delay associatedwiththeinverters,( T inv 1 HL + T inv 2 LH ),canalsobeestimatedusing Equation 3–20 3. T ref HL isgivenbyEquation 3–10 Note: Inabsenceofarefractoryperiodtheminimumpulsewidthist heoreticallygiven bythesumofthemembranecapacitordischargetime,thecomp aratordelayand theinverterdelay.However,forapracticalcircuitimplem entationinabsenceofthe refractoryperiod,assoonasthecapacitorgetsdischarged ,(suchthat V in isslightly lowerthan V th ), V reset goestozerobeforethecapacitorhasthechanceofdischargi ng 49

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completelyto V mid .Hencetherefractoryperiodhastobegreaterthanthedisch arge timeofthecapacitorgivenbyEquation 3–22 3.3PowerConsumption OneofthechiefmotivationsofusingasynchronousADCsislo werpowerconsumption ascomparedtotheconventionalADCs.Inthissectionvariou sapproachestowards reducingthepowerarepresented.First,thesourcesofpowe rconsumptionare analyzedfollowedbycircuitapproachestowardsreducingp owerconsumption. 3.3.1SourcesofPowerConsumption ThetotalpowerconsumptionoftheI&Fcircuitcanbeclassi edintotwoparts: staticanddynamicpowerconsumption.Thedynamicpowerisd enedasthepower consumedduringthegenerationofthepulses.Thestaticpow eristhebasepower consumedwhetherornottheI&Fcircuitisgeneratingthepul ses.Figure 3-10 shows thepowerconsumptionoftheI&Fcircuitfortwoconsecutive pulsesandthetime betweenthem.Theoutputstageandtheinverters(sub-graph 3and4)consume negligiblepowerinbetweenpulsesbuthavehigherpowercon sumptionduringthe pulses,whereasthelatchconsumespowerirrespectiveofth epresenceorabsenceof thepulse.Thepowerconsumedbytheoutputstageandtheinve rtersishighduring thepulseedges,howeverthispowerisconsumedforaverysma lldurationoftime (hundredsofnano-seconds)makingtheoverallenergyconsu medbytheseblockslow ascomparedtothecomparator. ThemainadvantageofasynchronousADCsovertheconvention alADCsistheir loweroutputdatarates.AsshowninFigure 3-10 ,ifthetimebetweenthepulseswere tobeextended,therebyloweringtheaveragedatarate,thep owerconsumptionper pulseforthecomparatoroutputstageandtheinverterswoul dremainunaffectedsince theyconsumepoweronlyduringthepulseedges,howevertheo verallpower/pulse ofthecomparatorlatchwoulddominatetheoverallpowercon sumption.Thisimplies thateveniftheoveralldataratefortheI&Fweretobereduce dtheoverallenergy 50

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-10 0 10 20 30 40 50 60 70 80 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 Inverter Power in uWTime in microseconds -2 0 2 4 6 8 10 12 14 16 18 20 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 Comp. Output Stage Power in uWTime in microseconds 3 4 5 6 7 8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 Comp. Latch Power in uWTime in microseconds -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 IF Output VoltageTime in microseconds Figure3-10.SimulatedblockwisepowerconsumptionoftheI &Ffortwoconsecutive pulsesandtheinter-pulseinterval.Thetopgraphshowsthe pulseoutput, thesecondgraphshowsthepowerconsumptionofthelatchfor thepositive andthenegativechannels(transistorsM 1 -M 6 inFigure 3-8 ),thethird graphsshowsthepowerconsumptionoftheoutputstage(tran sistorsM 7 M 10 inFigure 3-8 )andthelastgraphshowsthepowerconsumptionofthe inverters(transistorsM 12 -M 18 inFigure 3-8 ).Forthisgraphthecomparator biascurrentwasarbitrarilychosenas1 A. 51

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consumptionperpulsewouldincreaseorinotherwordsatlow erdataratesmore energyiswastedinthebackgroundthaningeneratingthepul ses.Figure 3-11 shows theenergyconsumptionperpulsefordifferentcircuitbloc ksasafunctionofaverage pulserate.Asmentionedpreviously,theoutputstageandth einverterpowerremain relativelyconstant.However,powerconsumedbythelatchb ecomesthedominant sourceofpowerconsumptionatlowerpulseratesandathighe rpulseratessince thecomparatorislessandlessidle,thepowerutilizationi shighandthereforethe energyconsumedperpulsebythelatchislow.Astheasynchro nousADCsgetbetter atloweringtheoutputdatarates,thestaticpowerwouldcap thepowersavings.One ofthemotivationsofusingatimebasedencodingschemeislo wpowerapplications andthecomparatorbiascurrentisthedominantfactorindet erminingthepower consumption,henceitisessentialthatthevalueofthebias currentischosencarefully. Insummary,thedominantsourceofpowerconsumptionisthec omparator,sincethe biascurrentisalwaysowingthroughthecomparatorwhethe rornotapulseisbeing generated.Also,fromsection 3.2 ,equations 3–11 through 3–19 ,itcanbeinferredthat thecomparatordelay(hencetheSER)isastrongfunctionoft hebiascurrent.Owing tothisdependenceoftheSERandthepowerconsumptiononthe biascurrenttheir relationshipneedstobeexploredindetail.3.3.2OptimumComparatorBiasCurrent Asdiscussedintheprevioussectionitisimperativethatth evalueofthebias currentbecarefullychosen.FromEquation 3–18 itisevidentthatthedelaydepends ontheinputsignalrate.Thisinputsignaldependenceisdet rimentalnotjustfortheI&F systembutalsofortheADCs(chapter11in[ 58 ]).Thisisbestexplainedbyconsidering thatifasinewaveweretobeappliedasaninputtotheI&F.Sin cetheslopevariesas afunctionoftime,thedelayalsovariesasafunctionoftime .Thisslopedependent delaywouldresultinsamplesshiftedintimeascomparedtoa nidealcomparator. Thisshiftofpulsescanactlikeadominoeffectloweringthe SERandwouldbevery 52

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10 -17 10 -16 10 -15 10 -14 10 -13 10 -12 10 -11 10 -10 10 -9 0.1 1 10 100 1000 Energy Consumed / pulse (J)Pulse Rate in Kpulses/sec Comparator energy Comp. output stage energy Inverter energy Figure3-11.Measuredenergyconsumptionofthecomparator latch,outputstageand theinvertersasafunctionofpulserate.Inordertoillustr atetheEnergy consumptionasafunctionofpulseratethecomparatorbiasc urrentwas arbitrarilychosenas1 A. difculttoestimateandcompensate.Thisisillustratedby Figure 3-12 .Thetopgraph inthegureshowsthecapacitorvoltageforoneperiodofa1K Hzsinewaveandthe bottomgraphshowsthecapacitorvoltagezoomedaroundther eferencevoltage.If thecomparatorisslowerthantheinputsignalaroundtheref erencevoltagethenby thetimeapulseisgeneratedandthecapacitorvoltageisres ettheinputsignalhas alreadybecomelargerthanthereferencevoltage.Asshowni nthebottomgraph,the delaycanbeequivalentlyvisualizedasaninputsignaldepe ndentshiftinthereference voltage.Lowerbiascurrentsleadtohigherdeviationofthe effectivereferencevoltage fromthepredenedreferencevoltage.Thereconstructiona lgorithmusesthepredened 53

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-400 -300 -200 -100 0 100 200 300 400 0 0.2 0.4 0.6 0.8 1 V m (mV)Time (ms) 330 340 350 360 370 380 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 V m (mV)Time (ms) Figure3-12.Timedependentthresholdvariationforasinew aveinput.Thetopgraph showsthesimulatedcapacitorvoltageofI&Fcircuitfora1K Hzsinewave input.Thebottomgraphshowscapacitorvoltage,fromtheto pgraph, zoomedaroundthecomparatorreference.Note:thereisatim edependent delay. comparatorreferencevoltageforrecoveringthesignal.Ho wever,asinferredfromFigure 3-12 ,theactualthresholdvarieswiththeinputsignalresultin gintheSERdegradation. ThemeasuredSERvs.thebiascurrentforthecomparatorissh owninFigure 3-13 Itcanbeinferredthatthethreecurvessaturatearound500n A.However,tobeonthe safesideabiascurrentvalueof750nAwaschosen.Inthetest setup,thehysteresis voltagefordifferentbiascurrentswasestimatedusingEqu ation 3–7 whereasthe refractoryperiodforthesamewasmeasured. Tosummarize,thesignaldependentvariationinthecompara torreferenceisthe chiefreasonforSERdegradation.Atlowerbiascurrentsthe effectivereferencevoltage deviatesalotfromthesetreferencevoltageandhencetheSE Rdecreasesatlowerbias currents.Howeveriftheactualreferencevoltage,asseeno ntheoscilloscopeisused, thentheSERforlowercurrentsimprovessignicantly.This impliesthatifacalibration 54

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5 10 15 20 25 30 35 40 45 50 1.0e-008 1.0e-007 1.0e-006 1.0e-005 SER (dB)Comparator Bias Current (uA) 750n sin(5K t) 600n sin(2K t) 750n sin(4K t) Figure3-13.MeasuredSERvs.comparatorbiasfordifferent sinewaves. setupweretobeusedwiththeI&FcircuitthentheSERcanposs iblybeimprovedeven atlowerbiascurrents.3.3.3ReducingStaticPowerConsumption ItcanbeinferredfromFigure 3-11 atlowerpulseratesthecomparatorbias becomesthedominantfactorsincetheyarebiasedwhetheror notapulseisbeing generated.Whilethepowerconsumptionwouldbelowerascom paredtosomeof theotherasynchronousADCsproposedin[ 12 16 26 28 76 ],becauseI&Fuses twocomparatorswhereastheothersuseindividualcomparat orforeveryquantization level.ThesynchronousADCssaveonstaticpowerconsumptio nusingaverypopular techniquecalledasdynamicbiasingproposedbyCopelandan dRabaey[ 77 ],Monticelli [ 78 ]andHosticka[ 79 ].Thecomparatorbiascurrentisdisabledduringtheoffper iodof 55

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theclockandisenabledduringtheonperiodoftheclock[ 80 – 82 ].Thedynamicbiasing workswellforthesynchronousADCsduetotworeasons.First ,thepresenceofthe clockwhichactsastheenable/disablesignalandseconddue tothefactthatoutput samplesfromthesynchronousADCsaregeneratedonlyduring theonphaseofthe clock.UnfortunatelyfortheasynchronousADCsneitheroft hesefactorsapplies. MotivatedbythenumbersinFigure 3-11 andthedynamicbiasingschemethe bestcasescenariowouldbeifnopowerwasconsumedduringth einterpulseinterval andthepowerisconsumedonlyforpulsegeneration.Thedigi talcircuitsarenota signicantsourceofpower,neglectingtheleakagepower,w henthepulsesarenot beinggenerated.Since,thestaticpowerconsumptionisdom inatedbythecomparator, inordertohaveanearzeropowerconsumptioninbetweenspik esthecomparatorbias currentwouldhavetoturnonwhenV in V th andbeturnedoffatallothertimes.Thus, abiasvoltageorcurrentcontrolblockisdesiredthatwillt urnononlywhentheinput voltageisnearthethresholdandwouldturnoffatallothert imes,whichessentially impliesthatacomparatorisrequired.Therequirementofac omparatorsortofdefeats thepurposesinceitwillneedtobebiasedaswell. Themoststraightforwardsolutionwouldbetouseaself-bia sedcomparator.A self-biasedcomparatorcontrolsitsbiascurrentusingthe input.Thereareseveral variationsofself-biasedcomparatorsinliterature.Majo rityoftheasynchronous self-biasedopampsorcomparatorshaveabaseDCcurrentand nearcomparison voltagealargetransientcurrentowsthroughthem[ 63 65 83 ].Theproblemwithusing thesearchitecturesisthestaticbiascurrentthatowsthr oughthem,whichwouldagain defeatthepurpose. Keepingtheseinmind,averysimpleself-biasedcomparator structureisproposed asshowninFigure 3-14 .I Bias asafunctionofV in canbeestimatedfromtherootsofthe followingequation: x k +1 x k x +(1 exp )=0 (3–23) 56

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Vdd Vdd Vdd Vdd M 1 M 2 M 3 M 4 M 5 M 6 V in V th V o1 V o2 Vdd Vss Vdd Vss M 7 M 8 M 9 M 10 V in M b1 M b2 I bias V cntrl Figure3-14.Dynamicallybiasedcomparatorarchitecture. where: 1. k 2 =( W = L ) b 2 = ( W = L ) b 1 2. x = exp p IC b 2 whereIC b2 istheinversioncoefcientoftransistorM b2 givenby Equation 3–9 3. =( V in V cntrl 2 V t ) = (2 nU T ) wherenisthesubthresholdslopeand U T isthe thermalvoltage. theaboveequationreducestothefollowingfork=1: x 2 2 x +(1 exp )=0 ) I bias = W L b 2 I on (log(1+ p exp )) 2 (3–24) Figure 3-15 comparesEquation 3–24 andtheCadencesimulationforvaryingV in .As expectedthecurrentrisesexponentiallyasafunctionofV in ,itcontinuestorisetillthe inputbecomesequaltothereferenceandthecapacitorvolta geisreset.Thisisvery differentfromthedesiredapproach,itwasdesiredthatthe biascurrentwouldsaturate aroundthereferencevoltage,thiscurveisindependentoft hereferencevoltage.The 57

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0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 I Bias (uA)Vin (V) Simulated Hand Calculation Figure3-15.SimulatedI Bias asafunctionofV in .ThegraphcomparestheCadence simulationvs.Equation 3–24 factthatthebiascurrentisindependentofthereferencevo ltageraisesissueslikethe smallsignalparameters,g m s,hysteresisvoltageetc.varyingwiththereferencevalue Thereferencedependentvariabilityinthesecircuitparam etersmakesitdifcultto characterizethecircuitandwillresultinSERdegradation Thebiascurrentisafunctionofthetransistorgeometriesw hichcannotbechanged afterfabrication,fromEquation 3–24 itisevidentthatthecurrentisalsodependenton whichinturnisdependentonV cntrl ,whichcanbechanged.Withslightmodication ofV cntrl ,sinceitisraisedtoanexponential,theI bias curvecanbeshiftedtotherightor theleft.Asexplainedbefore,everyreferencevoltagehasi ts xed biascurrent,sinceV in risestothereferencevoltageafterwhichitsreset,sofora givenreferencevoltagethe currentalsorisestoavaluegivenby 3–24 andthendropstozero.Bysuitablychanging V cntrl thecurveshownin 3-15 canbeshiftedtotheleftortheright.Thisimpliesthatthe 58

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0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 I Bias (uA)Vin (V) V cntrl = 1.5 V V cntrl = 1.56 V V cntrl = 1.62 V V cntrl = 1.65 V V cntrl = 1.68 V V cntrl = 1.74 V V cntrl = 1.80 V Figure3-16.SimulatedI Bias asafunctionofV in forvaryingvaluesofV cntrl .Byvarying V cntrl inFigure 3-14 thebiascurrentcanbevaried,thisimpliesthatthe currentcanbevariedforagivencomparatorreferencevolta ge. currentcorrespondingtoagivencomparatorreferencevolt agecannowbeincreased ordecreasedaccordingly.Figure 3-16 showsI Bias curvesfordifferentV cntrl voltages asafunctionofV in .Asitisevidentfromthegurethisexibilitycomesatthec ostof increasedstaticpowerdissipation.Figure 3-22 showstheblockwisesimulatedcurrent consumptionfortwoconsecutivespikesandthedurationbet weenthem.Figure 3-17 showstheenergyconsumptionasafunctionthepulseratefor theI&Fcircuitusingthe dynamicallybiasedcomparatorshowninFigure 3-14 Sinceitisthevaryingcurrentforeachreferencevaluethat istheproblemthe solutionistouseacurrentlimitingcircuit,whichconsume snearzero-dccurrent.The circuitshowninFigure 3-20 canbeused.Forthecircuitshownontheleft,whenV in isnearV ss ,M 2 isincutoff,sincethereisnocurrentthroughthecircuit,a ndV out is 59

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10 -17 10 -16 10 -15 10 -14 10 -13 10 -12 10 -11 10 -10 10 -9 0.1 1 10 100 1000 10000 Energy Consumed / pulse (J)Pulse Rate in Kpulses/sec Comparator energy Comp. output stage energy Inverter energy Figure3-17.Measuredenergyconsumptionofthecomparator latch,outputstageand theinvertersasafunctionofpulseratefortheI&Fcircuitw iththe dynamicallybiasedcomparatorshowninFigure 3-14 V ss andV int isnearV dd .AsV in increasescurrentstartstoowthroughthecircuit subsequentlyincreasingV out .SinceV out increasesinordertosupportthecurrent throughthecircuitV int startstodecrease.Theoutputvoltagecontinuestoincreas ewith anincreasingV in butitcannotincreasetoV dd ,sincethatwouldturnofftransistorM 3 andthecurrentwouldgotozero,insteadthecircuitreaches astablepoint.Thisstable pointisreachedwhenV ds acrossM 1 100mvortransistorM 1 isneartheedgeoftriode region.AfterthisstablepointincreasingV in hasnoeffectandtheoutputvoltageand thecurrentsaturate.Thecircuitontherightcanbeexplain edinasimilarfashion.The outputvoltage,V out ,canbeusedforcontrollingthebiasvoltageforthecompara tor. Usingthiscurrentlimitingcircuitasabiascontrolallevi atestheproblemofavariable biascurrentforvaryingcomparatorreferencessincetheou tputvoltagewouldget 60

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-20 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 180 200 220 Inverter Power in uWTime in microseconds 0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 140 160 180 200 220 Comp. Output Stage Power in uWTime in microseconds 0 0.5 1 1.5 2 2.5 0 20 40 60 80 100 120 140 160 180 200 220 Comp. Latch Power in uWTime in microseconds -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 20 40 60 80 100 120 140 160 180 200 220 IF Output VoltageTime in microseconds Figure3-18.Simulatedblockwisepowerconsumptionofthed ynamicallybiasedI&Ffor twoconsecutivepulsesandtheinter-pulseinterval.Theto pgraphshows thepulseoutput,thesecondgraphshowsthepowerconsumpti onofthe latchforthepositiveandthenegativechannels(transisto rsM 1 -M 6 in Figure 3-8 ),thethirdgraphsshowsthepowerconsumptionoftheoutput stage(transistorsM 7 -M 10 inFigure 3-8 )andthelastgraphshowsthe powerconsumptionoftheinverters(transistorsM 12 -M 18 inFigure 3-8 ). 61

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-1.5 -1 -0.5 0 0.5 1 1.5 2 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Current Limit Circuit Response (V)Vin (V) Vint Vout Figure3-19.Measurednodevoltagesforthecurrentlimitci rcuit. saturatedafterthetrippointofthecircuitsetbytransist orgeometries.Usingthiscircuit wouldalsoleadtosignicantpowersavingsforsomeoftheot herasynchronousADCs, forexampletheasynchronouslevel-crossingADC[ 84 ],whichusesacomparatorfor everyquantizationlevel.Sincethereferencevoltagefora quantizationleveldoesnot change,thetransistorgeometriesofthecurrentlimitingc ircuitcanbetailoredforevery quantizationlevel.Figure 3-19 showsthemeasurednodevoltagesforthecircuitshown inFigure 3-20 (a).AsfarastheI&Fisconcernedthecircuitstillneedstob emodied. AsseeninFigure 3-19 therearetwokeyparametersthatdenetheresponseofthe currentlimitingcircuit.Theseparametersaretheslopeof V out andthesaturationpoint. UsingEKVdesignequationsV out canbeestimated(forthecircuitshowninFigure 3-20 62

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(a))bythefollowingtwodesignequationsfortransistorsM 1 andM 2 respectively: V out = V ss + V t 2 +2 n ut log(exp p IC 2 1) (3–25) V out = V in V t 1 2 n ut log(exp p IC 1 1) SubtractingtheabovethetwoequationstoeliminateV out andsolvingforI out weget: V in V t 1 V t 2 V ss 2 n ut =log((exp p IC 2 1)(exp p IC 1 1)) (3–26) exp V in V t 1 V t 2 V ss 2 n ut =(exp p IC 2 1)(exp p IC 1 1) Substitutingtheexponentonthelefthandsideintheabovee quationas andtaking theTaylorseriesexpansionfortheexponentialtermsonthe righthandsignwiththerst threesignicantterms,theaboveequationreducesto exp = IC 1 IC 2 (3–27) ThususingEquation 3–9 I out canbeexpressedas: I out = exp W L 1 W L 2 I 2 on 1 2 (3–28) Usingthisexpressionfortheoutputcurrentandsubstituti ngitbackintoEquation 3–25 tosolveforV out : V out = V ss + V t 2 + n ut 2 log exp ( W = L ) 1 ( W = L ) 2 (3–29) Theexpressionabovedoesnotreectthesaturationofthevo ltage.Asmentioned previously,thecircuitsaturatesbecausetransistorM 1 movesintothetrioderegion.This pointcanalsobeestimatedbyrealizingthataroundthesatu rationpointV ds1 100mV. ThususingtheEKVequationsandassumingthattransistorM 3 isinsaturation(V ds3 > 100mV)thesaturationvoltageforthecircuitcanbeestimat edasfollowing: V sat =0.1+ Vdd 1.5 2 ut s I out I op ( W = L ) 3 +.25 (3–30) 63

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V in V in Vss Vss Vdd Vdd M 1 M 2 M 3 M 1 M 2 M 3 V out V out V in Vss Vdd M 1 M 2 V ref Vss Vdd M 1 M 2 V ref V in (a)(b) Figure3-20.(a)Twopossibleimplementationsofthecurren tlimitingcircuit.(b)Two possibleimplementationsofthesourcefollower. Astheexpressionaboveshowsoneofthekeyproblemsofthisc urrentlimitingcircuitis itsdependenceonV dd forthepeakvalueofthecurrent. Thebiascurrentgeneratedbythecurrentlimitingcircuiti sindependentofthe I&Freferencevoltage.Adynamicallybiasedsinglestageco mparator(essentiallya differentialamplier)canbeusedforgeneratingthediffe rencebetweenV in andV ref andthisdifferencecanbegiventothecurrentlimitingcirc uit.Anotherpossibilityisto usetheoutputofthesourcefollowercircuitasaninputtoth ecurrentlimitingblock.The sourcefollowercircuit(showninFigure 3-20 )hasbeenusedinseveralneuromorphic circuitimplementations[ 40 42 47 – 49 ].Figure 3-21 showsthecompleteschematicof thecomparatorwiththecurrentlimitcircuit,transistors M c1 -M c3 andthesourcefollower M sf1 -M sf2 3.4ResultsandDiscussion ThreeversionsoftheI&Fsampler,xedbiasI&F,dynamicall ybiasedI&Fand dynamicallybiasedI&Fcircuitwithcurrentlimitingweref abricatedinAMI0.6 m technologyandtested.Someoftheresultsfromthechiparep resentedinthissection. Sincepowerefciencyisofinterest,theeffectofvaryingt hecomparatorbiascurrent ontheSNRwasanalyzed.TheSNRvs.PowerplotisshowninFigu re 3-23 forasine 64

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Vdd Vdd Vdd Vdd M 1 M 2 M 3 M 4 M 5 M 6 V in V th V o1 V o2 Vdd Vss Vdd Vss M 7 M 8 M 9 M 10 M b1 M b2 I bias V cntrl V th Vdd V in M c1 M c2 M c3 M sf1 M sf2 V cntrl2 Figure3-21.Positivechanneldynamicallybiasedcomparat orwiththesourcefollower andcurrentlimitingcircuit. waveinput.Theinputsignal, ,andtherefractoryperiodwerekeptconstant,toensure aconstantpulserate,whilethebiascurrentofthecomparat orswasvariedresulting inavariablepowerconsumption.Themeasurementofpowerin thissetupworkstoa disadvantagefortheI&Fsincetheinputsignalisnotsparse andthesamplergenerates pulsesataxedrate. Theoverallenergy/pulseforthethreeversionsoftheI&Fci rcuitisshowninFigure 3-24 .I&Fwithdynamicallybiasedcomparatorconsumesroughlya tenthofwhatits counterpartwithxedbiascurrentconsumes.Whereastheen ergyconsumedbythe currentlimitedI&Fisonlyonefthofthatconsumedbythedy namicallybiasedI&F.The energysavingswiththecurrentlimitedbiasingschemearel essthanwhatisexpected. Thereasonforthisisthateventhoughthecurrentconsumedb ythecomparatorsin betweenthepulseshasdecreased,thesourcefollowertends toconsumeenergy therebyreducingtheoverallsavings.Table 3-1 comparesthisI&Fimplementationwith 65

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0 100 200 300 400 500 600 700 800 900 20 30 40 50 60 70 80 90 Mb1-Mb2 current (nA)Time in microseconds -5 0 5 10 15 20 25 30 35 40 45 20 30 40 50 60 70 80 90 Msf1-Msf2 current (uA)Time in microseconds -5 0 5 10 15 20 25 20 30 40 50 60 70 80 90 Mc1-Mc3 current (nA)Time in microseconds 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 20 30 40 50 60 70 80 90 Vmem VoltageTime in microseconds Figure3-22.Simulatedblockwisecurrentconsumptionofth edynamicallybiasedI&F fortwoconsecutivepulsesandtheinter-pulseinterval.Th etopgraph showsthecapacitorvoltage,thesecondgraphshowsthecurr ent consumptionofthecurrentlimitercircuit(transistorsM c1 -M c3 inFigure 3-21 ),thethirdgraphsshowsthecurrentconsumptionofthesour ce follower(transistorsM sf1 -M sf2 inFigure 3-21 )andthelastgraphshowsthe currentconsumptionofthecomparatorbias(transistorsM b1 -M b2 inFigure 3-21 ). 66

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30 35 40 45 50 55 0 2 4 6 8 10 12 SNR (dB)Power (uw) Figure3-23.MeasuredSNRvs.powerconsumptionoftheI&Fsa mpler.Theinputto thesamplerwas 750 nA sin(2000 t ) ,thethresholdwas0.4Vand C m =20 pF.Thepulseratewaskeptconstantwhilevaryingthebiascu rrentsofthe comparatorsresultinginvariablepowerdissipation. someofthepreviousimplementationsoftheI&FdoneatCNEL. Tokeepthecomparison fairthepowerconsumptionandenergy/pulsewereestimated forthesamevalueof SERatsimilarpulserates.TheimplementationoftheI&Fcir cuitaspartofthiswork80 timesaspowerefcientascomparedtoitspredecessorsatCN EL.Theenergy/pulse oftheI&Fcircuithasimprovedroughlybythreeordersofmag nitude.Theaverage energy/pulseisroughly10pJforapulserateof200pulses/s ec,thebestpublished neuroncircuitconsumesroughly267pJ[ 1 ]. ThenextresultistheENOB(describedinsection 2.3.1 )andthecorresponding powerconsumption.AverageENOBandthecorrespondingaver agepowerconsumption measuredfromthechipareshowninFigure 3-25 .ENOB(leftsidey-axis)andthe 67

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10 -17 10 -16 10 -15 10 -14 10 -13 10 -12 10 -11 10 -10 10 -9 0.1 1 10 100 1000 10000 Energy Consumed / pulse (J)Pulse Rate in Kpulses/sec Dynamically Biased I&F Fixed Bias I&F Current Limited Bias I&F Figure3-24.Measuredenergy/pulseasafunctionofpulsera tefortheI&Fcircuits showninFigure 3-8 3-14 and 3-21 Table3-1.ComparisonofthethisI&Fimplementationwithth epastimplementations. Reference PulseRate SER PowerConsumption Chenetal.[ 39 ] 47K 50dB 92 W Wei[ 38 ] 33K 50dB 90 W Rogers[ 71 ] 36K 50dB 100 W thiswork 40K 50dB 1.2 uW powerconsumption(rightsidey-axis)areplottedforincre asingpeak-to-peakamplitude ofa1KHzsinewave.TheI&Fsamplergeneratesahigheroutput datarateasthe inputsignalamplitudeincreases.Moreoutputpulsesimpli esabetterreconstruction accuracytherebyresultinginhigherENOB.TheENOBwasesti matedfromtheSNR usingEquation 2–16 ,theamplitudewasvariedfrom25nAto2.25 A with V th + and V th xedat300mVand-300mVrespectively, C m was20pF.Asmentionedpreviously, I&Fcircuitadjuststheoutputdatarateproportionaltothe signalamplitude.FromFigure 68

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0 2 4 6 8 10 12 0 500 1000 1500 2000 2500 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Effective Number of Bits Power consumption (uW)Peak-to-Peak input signal amplitude in nA Effective number of bits Power Consumption Figure3-25.MeasuredaverageENOBandaveragepowerconsum ptionvs.increasing sinewaveamplitude.10measurementsweremadeateverypoin tandthe averagevalueisplotted. 3-25 ,wenotethatasthesignalamplitudeincreasestheENOBimpr ovesduetohigher numberofsamplesfordatarecovery.TheENOBgraphsaturate saround10bitsof resolutionandincreasingtheoutputsamplingratehaslitt leeffect,thisresultsfromthe timequantizationoftheoutputdatasampleswhilerecordin g. Nevertheless,asmentionedpreviouslyamorecomprehensiv emeasureof synchronousADCperformanceisthegureofmerit(FOM).The FOMtiestogether thepower,ENOBandtheinputsignalbandwidthandisdeneda s[ 58 ]: FOM = Power 2 ENOB min( f sample ,2 BW ) (3–31) where f sample isthesamplingrateandBWisthesignalbandwidth,theminim umofthe twoistakentoaccommodateoversamplingdataconverters.U nlikeconventionalADCs, theasynchronousADCs,donotgeneratesamplesataxedrate henceweuse2BW insteadof f sample inestimatingtheFOMfortheI&Fsampler.Usingthenumbersf or 69

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Table3-2.ComparisonofFOMwithotherADCs. Reference FOM(pJ/conv.step) Technology(nm) Kozminetal.[ 16 ] 1.9 350 Akopyanetal.[ 26 ] 10.7 180 Allieretal.[ 13 ] 1.09 250 vanElzakkeretal.[ 85 ] .004 65 Naraghietal.[ 86 ] 0.1 90 Scottetal.[ 87 ] 5.2 250 YangandSarpeshkar[ 6 ] 1.17 350 CraninckxandvanderPlas[ 88 ] 0.065 90 HongandLee[ 89 ] 0.065 180 thiswork 0.6 600 ENOBandpowerconsumptionfromFigure 3-25 alongwithEquation 2–16 ,theFOM fortheI&FsampleriscalculatedandlistedinTable 3-2 alongwiththeFOMforother asynchronousADCs.Basedonreportedresultsintable 3-2 wehaveshownthatour I&FsystemprovidesthebestpublishedADCFOMforitstechno logynode. However,assemiconductortechnologyadvances,conventio nalADCdesignswill naturallyoutperformtheexistingcircuitimplementation oftheI&Fin0.6 m technology. Thus,itisofinteresttoestimatetheperformanceoftheI&F circuitwithtechnology scaling. Predictivetechnologymodels(PTM)madeavailablebyNanos caleIntegrationand ModelinggroupattheArizonaStateUniversityhavebeenuse dbyseveralresearchers forverifyingcircuittechniquesinscaledtechnologies.T hesemodelshavebeenused forpredictingperformanceofSRAMcellsinnanometertechn ologies[ 90 ],foraccurate estimationofcircuitleakagepower[ 91 ],muli-coreprocessorarchitectures[ 92 ]and manyothers[ 93 – 95 ].UsingthePTMwehavesimulatedtheI&FcircuitinCadence. The I&Fcircuitwasre-designedforeverytechnologynodebyrs tselectingthetransistor sizesforthemostfavorablespeed-resolutiontradeoff,fo llowedbyestimatingtheoptimal biascurrentforeachtechnologynode.Basedonthebiascurr entvaluethedynamic biasingschemewasdesignedandsimulationsweredonetoest imatetheENOBandthe 70

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correspondingpowerconsumptionleadingtotheestimatedF OM.Thisdesignprocessis describedinchapter 3 forAMI0.6 m technology. TheresultsforscalingaresummarizedinTable 3-3 .ThesimulatedENOBsfor varioustechnologynodesareslightlyhigher(ascomparedt othemeasurement resultsfortheI&Ffabricatedin0.6 m technology),thereasonforthisisthatthese aresimulationresultswithatimequantizationofpicoseco ndsandarewithoutany measurementinaccuracies. Thepowerdissipationofthelogicgateswithtechnologyand supplyvoltagescaling isrelativelyeasiertoestimateascomparedtothatofanalo gcircuits[ 96 ].Thereason forthisisthatwithtechnologyandsupplyvoltagescalingo fanalogcircuitsthereare severalcontradictoryeffectsthatcomeintoconsideratio n.Thesemaylowerthepower consumptionorincreaseit,suchisthecaseofcircuitnoise .Ithasbeenshownthatas technologyandsupplyvoltagesscaledownthereisanincrea seintheoverallcircuit noise,whichcanbedecreasedbyincreasingthebiascurrent [ 97 ].Increasingthe biascurrentnegatestheeffectofloweringthesupplyvolta geandresultsinlessthan expectedpowersavings.Abenetoftechnologyscalingisth atparasiticloadingatthe intermediatenodesdecreases,resultinginfastercompara torsinnewertechnologies foragivenbiascurrent.Also,varioussecondordereffects suchasgateleakageand non-zeroofftransistorcurrentleadtoahigherpowerdissi pationthanexpected[ 73 ]. Finally,newertechnologiesdeliverahigherg m /I D ascomparedtotheoldertechnologies [ 97 ],sincethecomparatordelayisinverselyproportionaltot hisratio(Equation 3–19 the comparatorresponseimproveswithtechnologyscaling.Weo bservetheseeffectsin playinthesimulationresultsinestimatingtheoptimumbia scurrentfortheI&F.Initially withtechnologyscalingthebiascurrentscalesalmostline arly,howeverbelow180nm thebiascurrentdoesnotscaledownmuch.Theoverallpowerc onsumptiondecreases (althoughpercentagesavingstendtosaturate),sincethep oweroftheinvertersin thecircuitgoesdownsignicantlyinnewertechnologies.T hus,withsuchopposing 71

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Table3-3.TechnologyscalingfortheI&Fcircuit. Tech.(nm) Ibias(nA) Vdd(V) Power(uW) ENOB FOM(pJ) 350 600 3.3 0.9632 11.82 0.133 250 400 2.5 0.5160 11.50 0.089 180 325 1.8 0.3378 11.81 0.047 130 275 1.1 0.1531 11.93 0.019 65 225 1.1 0.1064 11.65 0.0165 45 200 1.1 0.0726 11.84 0.0098 andcomplexeffectsitbecomesdifculttoderiveauniedan alyticalexpressionfor technologyandsupplyvoltagescalingfortheI&Fsampler,h oweversimulationsresults showthattheI&Fcircuitwillperformfavorablywithtechno logyscaling. 3.5Summary InthischapterthedesignmethodologyfortheI&Fcircuitis presentedandveried throughsimulationresults.Followingabottom-upapproac h,thecomparatorarchitecture withthemostfavorablespeed-resolutiontradeoffwaschos en.Inordertobuilda fastcomparator,hysteresishadtobeintroducedinthecomp aratorresponse.Since, hysteresisresultsinashiftinthethresholdvoltage,itwa smodeledandcomparedto themeasurementresults.Eventhoughthebestpossiblecomp aratorarchitecturewas chosen,signaldependentdelaytendstodegradetheSNRofth erecoveredsignal. Inordertobetterunderstandthecircuitparametersthataf fecttheI&Fresponse, thepropagationdelayofthecomparatorwasestimated.Base dontheanalytical expressions,itwasrealizedthatthecomparatoristhedomi nantsourceofdelayandis stronglyaffectedbythebiascurrent.Theanalyticalmodel wasvalidatedbycomparing themeasureddelayandtheestimateddelayasafunctionofth ebiascurrent. Thebiascurrentalsoeffectsthespeedofthecomparatorand theoverallpower consumption.Theoptimumbiascurrentwasestimatedbyenco dingsinewaves ofdifferentamplitudesandfrequenciesusingthefabricat edcircuitfordifferent biascurrents.Thesinewaveswerereconstructedfromthepu lsesandtheSNR wasestimatedtogettheoptimumbiascurrent.Inordertobet terunderstandthe 72

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powerconsumptionoftheI&Fcircuit,measurementsweremad efortheenergy consumption/pulseofthecomparator,invertersandthedel ayelementfordifferent pulserates.Sincethecomparatoristhedominantsourceofp owerconsumption.A dynamicallybiasedcomparatorarchitecturewasproposeda ndfabricatedin0.6 m technologytolowertheenergyconsumptionoftheexistingc omparator.Acomparisonof themeasuredenergy/pulseofthedynamicallybiasedcompar atorandtheconventional comparatorfordifferentoutputpulserateswasdone.Theco mparisonindicatesthatthe dynamicallybiasedcomparatorreducestheenergy/pulseby afactorof10ascompared tothecomparatorwithaxedbias. TheENOBandFOMweremeasuredfromtheI&Fcircuitfabricate din0.6 m technology.TheFOMshowsthattheperformanceoftheI&Fcir cuitasanADCis comparableandevenbetterinsomecasesthantheperformanc eofotherADCsand AADCsinthesameCMOStechnologybracket.Inordertoshowth attheI&Fcircuit wouldscalefavorablywithtechnologyscaling,theI&Fcirc uitwasredesignedusingthe designmethodologyexplainedaboveforeachtechnologynod e.UsingthePTMtheI&F circuitwassimulatedforgatelengthsfrom350nmto45nm.Ba sedonthesimulation results,theoptimumbiascurrentwasestimated,powercons umptionoftheI&Fwith thedynamicallybiasedcomparators,ENOBandtheresulting FOMforeachofthe technologynodes.TheestimatedFOMnumbersindicatethatt heI&Fcircuittendsto scalefavorablywithtechnologyscaling.Insummary,theI& Fsamplerprovidesasimple andefcientalternativeforultra-lowpoweranalog-to-di gitalconversionforapplications requiringlimitedprecisionandlowbandwidth. 73

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CHAPTER4 LIMITONINTEGRATE-AND-FIREENERGYDISSIPATION 4.1Introduction Thereareanumberofresearchgroupsworkingonbuildinglar gearraysof neuronsandvariouskindsofneuronmodelsinhardware.Thes eimplementations rangefrombiologicallyrealisticmodelssuchasHodgkin-H uxley[ 98 ]tosimplied modelssuchastheI&F.Thesesiliconneuronsformthecoreof largearrayson whichvariouscomputationalalgorithmsaretested.Thenum berofneuronsonthese arraysvariesfromtens[ 40 ],tothousands[ 99 ]andevenamillion[ 100 ].Overthe yearsvariouscircuitandmodelleveloptimizationsaremad eforloweringtheenergy consumptionofthehardwareneurons.Researchershaveeval uatedandbuiltcomplex communicationprotocolsfortheneuronstotalktoeachothe rinwithinachipaswellas inmulti-chiparchitectures[ 101 ].Withsuchalargescaleeffortinoptimizingthecircuit implementationsforneurondesignitisofinteresttoask:” Whatisthefundamentallimit toenergyconsumptionofasiliconneuron?”Thisquestionis difculttoanswerwith greatprecisionbutinthischapterwebuildamethodologyto getafeelforwherewe standintoday'stechnologyandexistingimplementations. Since,adigitalinverterisafairlysimplecircuittoanaly zewebeginbyexamining itspowerconsumptionlimits.Analyzingtheinverterprepa resthegroundworkfor estimatingthepowerlimitsoftheintegrate-and-recircu itusingasinglestage comparator.ThisanalysisisextendedfortheI&Fcircuitwi ththeregenerativecomparator presentedinChapter 3 4.2LimitonInverterPowerConsumption Therearethreemajorsourcespowerconsumptionofinadigit alCMOSinverteras presentedbyChandrakasanandBrodersen[ 102 ]: P avg = P switching + P short circuit + P leakage (4–1) = 0 1 C L V 2 dd f clk + I sc V dd + I leakage V dd 74

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Thersttermrepresentstheswitchingcomponentofpower,w hereC L istheload capacitance,f clk istheswitchingfrequencyand 0 1 isthetransitionactivityfactor. Thesecondtermisduetothedirect-pathshortcircuitcurre ntI sc whichariseswhenboth NMOSandPMOStransistorsaresimultaneouslyactiveconduc tingcurrentdirectlyfrom V dd toground.Thelasttermistheleakagecurrentwhichisdeter minedbyfabrication technology.Foraninvertercircuit,theenergydrawnfromt hepowersupplyduring0 1 transitionis C L V 2 dd .Halfofthisenergyisstoredintheoutputcapacitorandthe otherhalf isdissipatedinthePMOStransistor.Duringtheduring1 0theenergystoredinthe capacitorisdissipatedthroughtheNMOSdevice[ 96 ].Usuallytheswitchingcomponent isthedominantsourceofpowerconsumptionfortheinverter [ 103 ]. BasedonEquation 4–1 reducingthepowersupply, V dd willhaveaquadraticeffect ontheoverallpowerconsumption.Reducingthepowersupply increasesthedelay oftheinverter.However,ifthesystemissuchthatitcanope rateataconsiderably lowerfrequencythenwhatistheminimumsupplyvoltageatwh ichtheinvertercanbe operated?Inotherwordswhatisthelimittopowerconsumpti onoftheinverter. Assumingthatthebothtransistorsareoperatingintheweak inversionregionand thetrippointoccurswhenthecurrentthroughthePMOSequal thecurrentthroughthe NMOS[ 104 ].Usingthefollowingweak-inversioncurrentequationfor thetransistors[ 97 ]: I D =2 n 0 C ox U 2 T W L e ( V gs V t ) = nU T 1 e V ds = U T (4–2) Where U T isthethermalvoltagegivenbyKT/qand V t isthethresholdvoltage. isthe effectivemobility, C ox istheoxidecapacitanceandnisthesubthresholdslopefact or. ThenequatingthePMOSandtheNMOScurrents: I D =2 n n 0 n C ox U 2 T W L n e ( V in V tn ) = n n U T 1 e V out = U T =2 n p 0 p C ox U 2 T W L p e ( V dd V in V tp ) = n p U T 1 e ( V dd V out ) = U T (4–3) 75

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Solvingtheaboveequationsfor V in andassumingthe n n = n p weget: V in = U T log n p 0 p n n 0 n 1 e ( V dd V out ) = U T 1 e V out = U T + V tn V tp + V dd (4–4) Differentiatingtheaboveequationto V out togetanexpressionfortheinverseofthegain weget: dV in dV out = n n e ( V dd V out ) = U T 1 e ( V dd + V out ) = U T + e V out = U T 1 e V out = U T (4–5) Themaximumgainfortheinverteroccursat V out = V dd = 2 andisgivenby: Gain 1 n n e Vdd = 2 U T 1 2 = 1 n n e Vdd q = 2 KT 1 2 (4–6) Basedontheequationabovetheinvertergainrollsoffquick lywithadecreasing supplyvoltage.Usingasimilaranalysis,Swanson[ 105 ]estimatesthattheminimum V dd shouldbegreaterthan3-4kT/qfortheinvertertobeusable. Thisresultisalso conrmedfromsimulatedtransfercurvesoftheinverterinC adenceasshowninFigure 4-1 .Atsuchlowvoltagestheoutputandtheinputnoisemarginso ftheinverterare separatedbyafewmillivolts.Circuitnoiseorambientnois ecantriptheinverterorresult infalseinverteroutput. Instronginversiontheinverterdelaydoesnotdependonsup plyvoltage.Whereas exponentiallydecreasingcurrentwithadecreaseinvoltag eleadstoexponentiallyhigher delays.Inverterdelayforthesubthresholdregioncanbeex pressedas: t d = C load V dd 2 n 0 C OX U 2 T ( W = L ) e ( V dd V t ) = nU T (4–7) Thesimulateddelayandpowerconsumptionoftheinverteras afunctionofV dd areshowninFigure 4-2 .Reducingthesupplyvoltagewoulddecreasethepower consumptionoftheinverter,howeveritalsoincreasesthed elay.Thus,itisessential toexploretheenergyconsumedinonetransitionasafunctio nofV dd .Thisenergyper 76

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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Vout (V)Vin (V) Vdd = 980 mV Vdd = 700 mV Vdd = 500 mV Vdd = 350 mV Vdd = 250 mV Vdd = 180 mV Vdd = 130 mV Figure4-1.Simulatedinvertervoltagetransfercurvesfor varyingV dd .Theslopeofthe transfercurveisthegainoftheinverter.Invertergainred ucesconsiderably forV dd near100mV. transitionisalsoknownasthepower-delayproduct.Figure 4-3 showsthesimulated power-delayproductasafunctionofV dd 4.3LimitonSingleStageComparator'sPowerConsumption Inthissectionweexplorethelimitstopowerconsumptionof asinglestage comparatordescribedinSection 3.1.1.1 .Thesinglestagecomparatorisshownagain ingure 4-4 [ht]Unliketheinverter,derivingaclosedformexpression fortheminimum supplyvoltageforthedifferentialamplierisfairlycomp licated.Howevertheboundson thesupplyfortheampliercanbeexpressedbyrealizingtha talltransistorshavetobe saturatedforsufcientgainasshownbyLiuetal.[ 48 ]andIsmailandFiez[ 47 ].Thus 77

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0.0001 0.001 0.01 0.1 1 10 100 1000 10000 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 1e-007 1e-006 1e-005 0.0001 0.001 Delay in us Power consumption (uW)Vdd (V) Delay Power Consumption Figure4-2.Simulatedinverterdelayandpowerconsumption forvaryingV dd theexpressionforthesupplyvoltagecanbeexpressedas: V dd V ds sat 5 + V ds sat 2 + j V gs 3 j (4–8) TheequationaboveusesV ds sat5 ,thatistheminimumV ds requiredforkeepingtransistor M 5 insaturation.TheabsolutevalueofV d5 isdeterminedbytheinputvoltagesV 1 and V 2 .V ds sat5 alsodeterminestheinputvoltagerangeoftheamplier.Usi ngtheEKV designequations V ds sat canbeexpressedas: V ds sat = U T [ p IC +0.25+1.5] 4 U T Inweakinversion 2 U T p IC ( V GS V t ) Instronginversion (4–9) 78

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1e-014 1e-013 1e-012 1e-011 1e-010 1e-009 1e-008 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Power-Delay Product (pJ)Vin (V) Figure4-3.Simulatedinverterpower-delayproductforvar yingV dd Vdd Vdd V in V th V bias g m D in r out C out V out V out Figure4-4.SingleVoltageAmplierandthecorrespondings mallsignalmodel 79

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whereICistheinversioncoefcientofatransistorasdene dbyEquation 3–9 .Using theEKVdesignequationsparentedbyBinkley[ 73 ],thegateoverdrivevoltagecanbe expressedas: V gs Vt =2 nU T log[ e p IC 1] nU T log[ IC ] Inweakinversion 2 nU T p IC Instronginversion (4–10) SubstitutingEquation 4–9 and 4–11 inEquation 4–8 togetanexpressionforthe minimumsupplyvoltageweget: V dd U T s I bias I on ( W = L ) 5 +0.25+ s I bias 2 I on ( W = L ) 2 +0.25+3+2 n log[ e p IC 3 1] # (4–11) Sincetheminimumsupplyvoltageisdependentonthebiascur rent,Figure 4-5 shows theminimumsupplyasafunctionofbiascurrentforagivensi zingofthetransistors. TheI&FcircuitencodestheinformationintimeandtheSERre duceswithanincreasein thecomparatordelay.Hence,itisofinteresttoinvestigat etheeffectsofreducingsupply voltageonthecomparatordelay.AsdescribedinSection 3.1.1.1 thecomparatordelay isdependentonthebiascurrentofthecomparator.Usingthe resultsfromtheanalysis presentedinsection 3.2 ,thedelayofthesinglestagecomparatorcanbeexpressedas : T p = V oh in gm 1 C o (4–12) WhereV oh istheoutputvoltageleveloflogic'1'(V dd /2), in isthestepinputto thecomparatorgivenby V in ( t ) V th ,C o istheloadcapacitanceandgm 1 isthe transconductanceoftheinputstagegivenbyequation 3–15 AsseenfromEquation 4–13 ,thedelaydependsonthegmoftheinputstageand therequiredoutputvoltageswing.Aslongasallthetransis torsaresaturatedreducing thesupplyvoltageshouldreducethedelaysincetheV oh alsoscaleswithV dd .The 80

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1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Minimum VddIbias (uA) Figure4-5.Analyticalevaluationoftheminimumsupplyvol tageasafunctionofbias current. dynamicpowerrequiredforasinglecomparisonissimplygiv enbytheproductofV dd andI bias .Thusthepower-delayproductforagivenbiascurrentcanbe expressedas: PowerDelay = V dd min I bias V dd min 2 in gm 1 C o (4–13) Figure 4-7 showsthedelayvs.V dd forvariousbiascurrentsforthecomparator.Figure 4-6 showsthepower-delayproductvs.V dd forvariousbiascurrents.Therearetwo interestingobservationstomemadefromFigures 4-6 .Firsttheminimumdynamic power-delayproductoccursaround1pJ.Thesecondthington otebasedonthegraphs isthatthecircuitofferstwodegreesoffreedomnamelytheV dd andI bias toachievenear minimumpower-delayproduct.Dependingonthesystemlevel constraintseitherahigh 81

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0 10 20 30 40 50 60 70 80 90 100 110 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Power Delay (pJ)Vdd (V) Ibias = 0.3e-6 Ibias = 0.8e-6 Ibias = 1.3e-6 Ibias = 1.8e-6 Ibias = 2.1e-6 Figure4-6.Analyticalevaluationofthepower-delayprodu ctofthesinglestage comparatorvs.V dd forvariousvaluesofI bias V dd withhighbiascurrentcanbechosenorlowbiascurrentwithl owV dd canbechosen foraminimumpower-delayproduct. Intheaboveanalysisandthegraphsthedynamicpowerconsum ptionofthe comparatorwasconsideredandthestaticpowerconsumption wasignored.Theoretically inordertomakeacomparisononlydynamicpowerisrequiredw hereasstaticpoweris justwastedinbetweencomparisons.Thus,theabsolutemini mumpowerconsumption ofacomparatoristhepowerrequiredonlyduringthetimethe inputvoltagegoesabove thereferencevoltage.However,asithasbeenpreviouslysh owninFigure 3-17 fora practicalcomparatorstaticpowercannotbeignoredsincei tisvirtuallyimpossibleto completelyturn-offacomparatorinbetweenpulses. 82

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0.1 1 10 100 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Delay (us)Vdd (V) Ibias = 0.3e-6 Ibias = 0.8e-6 Ibias = 1.3e-6 Ibias = 1.8e-6 Ibias = 2.1e-6 Figure4-7.Analyticalevaluationofthesinglestagecompa ratordelayvs.V dd for variousvaluesofI bias 4.4LimitonI&FCircuit'sPowerConsumption TheschematicfortheI&FcircuitpresentedinSection 3.1.1.2 isshownagainin Figure 4-9 .Usingtheapproachsimilartothatofthesinglestageampli er.Thelimiton thepowersupplyforthecircuitcanbeexpressedas[ 106 ]: V dd V ds sat 11 + V ds sat 1 + j V gs 3 j (4–14) Figure 4-8 comparesthemeasuredminimumvoltageandequation 4–14 .Themeasured minimumvoltagefollowsthetrendpredictedbyEquation 4–14 .Thepossiblereasons forthedifferencebetweenthemeasuredandthepredictedmi nimumvoltagecanbe duetothefactthatinsolvingtheequationapproximatevalu esofthethresholdvoltages 83

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0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Minimum VddIbias (uA) Analytical Measured Figure4-8.Measuredandanalyticalminimumsupplyvoltage fortheI&Fcircuitasa functionofbiascurrent. wereusedandthefactthatthesamesubthresholdslopevalue wasusedfortheallthe transistorsirrespectiveoftheirrespectiveregionofope ration. Basedontheenergyanalysispresentedintheprevioussecti on,itseems thattheestimatingtheminimumenergyrequiredforgenerat ingapulseshouldbe straightforward.Theobviousapproachwouldbetoexpresst hecombineddelayof thecomparatorthethreeinvertersandmultiplyitbythepow erconsumptionofthe respectivecircuitblocks.Estimatingthedelay,thepower consumptionandsubsequently theenergyofaninverterchainoperatinginstronginversio nisfairlysimpleusing principlesoflogicaleffort.However,duetotheexponenti aldependenceofthecurrent ongatevoltageitisalothardertoestimatethepowerandthe delayforaninverter chainoperatinginsubthresholdregion[ 103 ].Anotherissuewiththissimplisticapproach 84

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Vdd Vdd Vdd Vdd Vss V bias M 1 M 2 M 3 M 4 M 5 M 6 V in V th V o1 V o2 Vdd Vss Vdd Vss M 7 M 8 M 9 M 10 Vdd Vss Vdd Vss Vdd Vss M 11 M 12 M 13 M 14 M 15 M 16 M 17 M 18 Vdd C m V mid M 19 V delay V out+ I in V reset+ C o2 C o1 V oc2 V oc1 C oc2 C oc1 Figure4-9.Thecompleteschematicofthepositivechannelo ftheI&Fcircuit.The negativechannelissymmetrictothepositivechannel,itis notshownin ordertosimplifytheschematicshownhere.Selectparasiti ccapacitances areshownindottedline. isthatfromgure 4-3 werealizethatthereisanoptimumvalueofthesupplyvoltag e fortheinverterforminimumenergyconsumption.Thusthemi nimumvoltagethatthe comparatorcanoperateatmaynotbetheoptimumvoltagefort heinverterchain. Theenergyconsumedbyaninverterchainoflength len canbeexpressedas[ 106 ]: E Total = len E switching + P leakage t d = len 1 2 C L V 2 dd + len Vdd I leak ( len t p ) (4–15) istheactivityfactor, t d isthedelayoftheoverallinverterchainand t p isthedelayofa singleinverter.Intheaboveequationtheshort-circuiten ergyhasbeenignored.Since ithasbeenshownin[ 107 ]and[ 106 ]thatforinverterchainsoperatinginsubthreshold regimetheleakagepoweraccountsforlessthan5%oftheover allpowerconsumption. Inequation 4–15 t p needstobeestimatedaccurately.Let t p step denotetheideal inverterdelaywithastepinputand t p actual denotetheactualinverterdelayforaninput 85

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witharisingtimeof r t p step canbeestimatedasZhaietal.[ 106 ] t p step = 1 2 C L V dd I sub (4–16) where I sub isthesubthresholdcurrentasdescribedinEquation 4–2 .Similarlythestep delaycanbeextendedtotheactualdelayas[ 104 ]: t p actual = r t 2 p step + r 2 2 (4–17) [ 104 ]showsthatforaslowrisinginputsuchthattheinputriseis slowerthantheinverter delayi.e. r > t p actual ,theactualdelaycanbeestimatedas: t p actual =0.84 r ) t p actual =1.2 t p step (4–18) Substitutingthisresultinequation 4–15 weget: E Total = len 1 2 C L V 2 dd + len V dd I leak len 1.2 1 2 C L V dd I sub = 1 2 lenC L V 2 dd +1.2 len I leak I sub (4–19) I sub isgivenbyEquation 4–2 I leak istheoff-currentofatransistor.Off-currentis characterizedwhenthegate-sourcevoltageisatzeroandth ethereisanitedrain-source voltageresultinginaleakagecurrent. i leak canbeestimatedfromEquation 4–2 by substitutingV gs as0andV ds asV dd .Thustheratioofleakagecurrenttosubthreshold currentcanbeexpressedas: I leak I sub = e ( V tn ) = n n U T 1 e V dd = U T ( e ( V dd V tn ) = n n U T )( 1 e V dd = U T ) = e ( V dd ) = n n U T (4–20) Thusthetotalenergy/transitionoftheinverterchaincanb eexpressedas: E total = 1 2 lenC L V 2 dd +1.2 len e ( V dd ) = n n U T (4–21) 86

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Inordertoestimatetheminimumenergyoftheinverterchain ,theaboveequationis differentiatedwithrespecttoV dd andsettozerotogettheminima[ 108 ]. dE total dV dd = lenC L V dd +0.6 len 2 C L 2 V dd e V dd = nU T + V 2 dd e V dd = nU T 1 nU T 0= +0.6 len e V dd = nU T 2+ V dd 1 nU T e V dd = nU T 0.6 len = 2+ V dd 1 nU T (4–22) Aclosedformsolutiontotheaboveequationhasbeenpresent edbySwanson[ 105 ]. V opt =( nU T )[(1.58) log 0.6 len 2.35] (4–23) Usingtheaboveanalysiswecannowestimatetheenergyofthe I&Fcircuit.As mentionedinSection 3.2 thecomparatordelaycanbeexpressedas: T comp 1 2 V co 2 K s ( V in V th ) 1 2 (4–24) where 1 = C oc 1 = gm 5 2 =( r 8 jj r 10 ) C oc 2 and K s =( gm 7 ( r 8 jj r 10 ) gm 1 ) = gm 5 .Thereforethe energyrequiredtogenerateasinglepulseisgivenby: Energy IF = Energy comparator + Energy comp output stage + Energy inverter chain (4–25) Sinceweareconsideringonlytheenergyrequiredforgenera tionofasinglepulse(in otherwordsthestaticpowerdissipationisignored),theen ergyofthecomparatorcanbe expressedas: Energy comparator = V dd I bias t delay (4–26) Similarlytheenergyconsumedbytheoutputstagecanbeexpr essedas: Energy comp output stage = V dd 2 n p 0 p C ox U 2 T W L 8 e ( V dd V o 2 = 2 V tp ) = n p U T t delay (4–27) 87

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Here t delay isthepropagationdelayoftheI&Fcircuit.Itisthesumofth ecomparator delayandthedelayoftheinverterchain.Inderivingtheexp ressionfortheenergyfor theinverterchainitwasassumedinEquation 4–18 thattheinputsignaltotheinverter chainisslowrising.However,fortheI&Fcircuitthatmayno tbethecasedependingon thebiascurrentvalue.Thevalueof r istherisetimeoftheinputsignaltotheinverter, whichisessentiallytherisingtimeofthecomparator.Henc eusingEquations 4–24 and 4–17 thedelaycanbeestimatedas: t delay = T comp + t delay inverter = 1 2 V co 2 K s ( V in V th ) 1 2 + vuut t 2 p step + 1 2 1 2 V co 2 K s ( V in V th ) 1 2 2 = 1 2 V co 2 K s ( V in V th ) 1 2 + vuut 1 2 C L V dd I sub 2 + 1 2 1 2 V co 2 K s ( V in V th ) 1 2 2 = 1 2 V dd 2 K s ( V in V th ) 1 2 + vuut 1 2 C L V dd I sub 2 + 1 2 1 2 V dd 2 K s ( V in V th ) 1 2 2 (4–28) Thustheenergyrequiredtogenerateasinglepulsecanbeexp ressedas: Energy IF = V dd I bias t delay + V dd I comp stage t delay +3 1 2 C L V 2 dd +9 V dd I leak t delay inverter (4–29) Sinceweareestimatingtheenergyofonepulseintheequatio nabovetheactivity factorhasbeensubstitutedas1andthelengthoftheinverte rchainhasbeensetat 3.Figure 4-10 evaluatesEquation 4–29 fordifferentbiascurrentsasafunctionofV dd Asexpectedtheenergycontinuestodropwithadecreaseinth esupplyvoltage,since Equation 4–29 isastrongfunctionofV dd .However,afterapointtheenergystopsto furtherdropwithadecreaseinthesupplyvoltage.Atthispo inttheinverterenergystarts todominatetheoverallenergyconsumption. 88

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0 2e-016 4e-016 6e-016 8e-016 1e-015 1.2e-015 1.4e-015 1.6e-015 1.8e-015 1 1.5 2 2.5 3 3.5 4 4.5 5 Energy Consumed (J)V dd (V) I bias = 0.05 uA I bias = 0.25 uA I bias = 0.50 uA I bias = 1.00 uA I bias = 2.50 uA I bias = 5.00 uA Figure4-10.Equation 4–29 vs.V dd fordifferentbiascurrents. 4.5Summary Inthischapterthefundamentallimittopowerconsumptiono ftheI&Fcircuitwas presented.Westartedbyexploringthelimitstopowerconsu mptionofasimplestatic CMOSinverter.Sinceananalogcircuitpresentstwodegrees offreedomforacircuit, abasicsinglestageamplierwasanalyzedforpowerconsump tion.Basedonthe simulatedenergyvs.supplyvoltagegraphswerealizedthat theenergyconsumed convergestoavaluefordifferentbiascurrents.Sincethee nergyconsumption convergesanditappearsasifthecomparatorcanbebiasedfo rwithalowerbias currentatlowsupplyvoltages.Howevercloselyexaminingt hedependenceofdelayon thesupplyandbiascurrent,werealizethatthedelayisastr ongerfunctionofthebias currentthanthesupplyvoltage.Usingalowvoltageandlowb iascurrentensuresthat 89

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theoverallstaticpowerconsumptionislessparticularlyi fthenumbersofcomparisons perunitoftimearelow.Howeverpenaltyispaidintermsofth edelay.Ontheother handbiasingthecomparatorwithahigherbiasandsupplyvol tagewouldensurethat theoveralldelayisatitsminimumatthecostofahigherstat icpowerconsumption.In somewaystheenergyvs.supplygraphcanbedividedintofour quadrantsnamelyhigh-biashigh-supply/high-biaslow-supply/low-biashi gh-supply/low-biaslow-supply. High-biashigh-supplywouldgivethebestdelayatthecosto fahighstaticanddynamic powerconsumption.Low-biashigh-supplywouldgivelowsta ticpowerdissipationfora higherdelaycost.Low-biaslow-supplygivesthelowestpow erconsumptionhoweverat thecostofhighdelay.High-biasatalow-supplyseemstobet hemostfavorableitgives reasonablylowdelaysatmoderatepowerconsumption. Usingsomeoftheinsightsgainedfromanalyzingthelimitst opowerconsumption oftheinverterandthedifferentialamplier,theI&Fcircu itwasanalyzedforpower consumptionlimits.Boththeinverterandthesinglestagec omparatorwereanalyzedas independentcircuits.TheI&Fcircuitontheotherhandisma deupofacomparator,a comparatoroutputstageandaninverterchain.Sincetheene rgyconsumptiondepends ontheoveralldelayofthesystemabasicframeworkhadtobeb uiltforanalyzingthe energyconsumptionatasystemlevel.Usingthisframe-work ,wepresentedtheanalysis forestimatingtheoptimumvalueofsupplyvoltageforminim umenergyconsumptionfor achainofinverters.Usingthemethodforanalyzingthechai nofinvertersweusedthe comparatordelaymodelfromChapter3andusedittoestimate theenergyconsumption oftheI&Fcircuitasafunctionofbiascurrentandbiasvolta ge.Simulatingtheequation werealizethatdependingonthebiascurrentthereisanopti mumsupplyvoltageforthe I&Fcircuitforminimumenergyconsumption.Unlikethecase oftheinverterchainthe resultingequationisquitetedioustoderiveanelegantsol utionforthesupplyvoltagein termsofotherparameters. 90

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CHAPTER5 ENERGYHARVESTING 5.1Introduction WhethertheI&Fcircuitisusedasanencoderformicro-senso rapplicationsorused forbuildinglargearraysofspikingneuronnetworks[ 45 109 ],energyefciencyisakey criteria.Intheprecedingchapterswehavedevelopedsever alkeyenergyoptimizations totheexistingI&Fcircuit.Inordertofurtherimprovethee nergyefciencyoftheI&F circuit,weproposeanovelenergyharvestingcircuit. TheI&Fcircuitgeneratesanoutputpulsebycomparingtheca pacitorvoltageto thethreshold,oncethepulseisgeneratedthecapacitorisd ischarged.Theenergy storedinthecapacitorislosteachtimeanoutputpulseisge nerated,insteadasmarter schemecanbedevelopedwhereinthecapacitordischargesby transferringitsstored energytoanothercapacitorascomparedtosimplydischargi ngtoground.Theenergyis harvestedeachtimeanoutputpulseisgenerated. 5.2EnergyHarvestingArchitecture TheblocklevelschematicfortheI&FcircuitisshowninFigu re 5-1 .Theinputsignal, I in ,isintegratedonthecapacitor, C m ,resultinginavoltage, V m ,whichiscomparedto thethreshold, V th ,usingtwoanalogcomparators.Whenthethresholdisreache d,the outputofthecomparator, V pulse ,goeshigh,generatinganoutputpulseandresetting V m to V mid .Thecapacitorvoltageisthenheldat V mid forapredenedtime, r ,after whichtheprocessrepeats.Thechargeintegratedonthecapa citoriswastedevery cycle.Theessentialideaistorecyclethischargeandutili zeitinsomeway.Thecharge storedoncapacitor C m isdischargedascurrentthroughtheresettransistor.Thec urrent throughtheresettransistorcanbeusedtochargeanotherca pacitorwhilekeepingthe voltage V mid nearconstant.Oncesufcientchargehasbeentransferreda ndstoredin theharvestingcapacitor,itcanbeusedtoeitherpoweracir cuitonthechip[ 110 ]orthe chargecantransferredbacktothebattery[ 111 ]. 91

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Likemostenergyharvestingsystems,thesystemdescribeda spartofthiswork canalsobebroadlydividedintothreecomponents[ 111 ]namely:theenergyharvesting loop,thecontrollogicandtheenergyutilization.Theharv estingpartencompasses thebasicanalogcircuitfortransferringthechargefromth emembranecapacitortothe harvestingcapacitor.Thecontrollogicmonitorsandmanag estheenergyharvesting processandtheenergyutilizationcircuitusestheharvest edchargetopowerbackthe I&Fcircuit.Thissectiondescribesthedesignprocessofdi fferentcomponentsofthe energyharvestingarchitecture. + Vdd C mtI in Delay V mid + tV m Delay V mid V th + V thVpulse+VpulseVpulseVpulse+ Figure5-1.BlocklevelschematicofthebiphasicI&Fcircui t. 5.2.1EnergyHarvestingCircuit Asmentionedpreviouslytheessentialideabehindenergyha rvestingintheI&F circuitistotransferthechargefromthemembranecapacito rtoanotherreservoir capacitor.Thechargetransfermustoccurduringthepulset imesincethatiswhenthe membranecapacitordischarges.Themembranecapacitordis chargesthroughthedrain currentoftheresettransistor.Thisdischargecurrentcan beusedtochargeanother capacitorwhilekeepingthesourceoftheresettransistors teadyatV mid .Thisimplies thatthedraincurrentoftheresettransistorneedstobecon veyedtoanothercapacitor whilemaintainingaxedvoltage.Asecondgenerationcurre ntconveyorcircuit(CCII) essentiallyperformsthisoperation[ 112 113 ].ThebasicarchitectureofaCCIIisshown 92

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+ V mid Vss P 1 C int + Vdd C mtI in Delay + tV m Delay V th + V thVpulse+VpulseV pulse V pulse ~V pulse Figure5-2.SecondgenerationCurrentConveyorcircuitand I&Fcircuit. inFigure 5-2 .InthepastthisarchitectureofCCIIhasbeenimplementeda tCNELfor differentapplications.ItwasrstusedbyHarpreetNarula forimplementingatime-based potentiostatforioncurrentmeasurements[ 114 ].Thisarchitecturewasalsousedby JieXuasapossibleanalogfront-endforrecodingcurrentin steadofvoltagesinneural implants. Theessentialoperationoftheharvestingloopisverysimpl e.Initiallycapacitor C int isresettoV ss .WhentheI&Fcircuitgeneratesanoutputpulse C m dischargesandthe currentowsthroughtheresettransistortoC int .Sincetheamplierisconnectedina negativefeedbackcongurationthesourceoftheresettran sistorisheldat V mid .As moreandmorepulsesaregeneratedthecapacitorC int chargesanditsvoltagerises. Oneoftherstconcernswiththisapproach,isthepowercons umptionofthe amplier.Apossiblesolutioncomesfromtherealizationth atthecurrentconveyoris requiredonlyduringtheresetphase,thustheampliercanb edisabledin-betweenthe pulses.SincemostimplementationsoftheI&Fcircuitgener ateboth V pulse andtheir invertedvalues,thesearedigital-likepulsestheycanbeu sedtocontroltransmission gatesforenablinganddisablingtheamplierbiascurrent. Figure 5-3 showsthe amplierbias-controlschematic.TheoutputoftheI&Fcirc uitisusedasdigitalcontrol forenablinganddisablingtheamplier. 93

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V bias Vss Vss I bias Vdd Vss ~V pulse ~V pulse V pulse Figure5-3.Amplierbiascontrolusingthedigital-likepu lseoutputfromtheI&Fcircuit. Turningofftheamplierbiascurrentwillnolongerensurea voltagecloseto V mid atthesourceoftheresettransistor M r inFigure 5-1 .Thisproblemcanalsobe circumventedbyagainrealizingthatwecanrewirethesourc eoftheresettransistor totheV mid in-betweenpulsesandcanreconnectittotheamplierloopd uringthe pulsetimes.Turningtheamplieroffinbetweenthepulsesc anresultinthePMOS transistorturning-onanddischargingthecapacitor.Thus ,theswitchesareusedagainto disconnectthecapacitorfromtheloopwhiletheamplieris disabled.Figure 5-3 shows theresultingCCIIcircuitschematic. Asdescribedlater,theareaandpowercostusingjustoneCCI IloopperI&Fcircuit isfairlyhigh.TherealsavingsoccurwhenanarrayofI&Fcir cuitsutilizethesameCCII loop.OnceanarrayofI&Fcircuitsisconnectedtotheharves ter,theoutputpulsesof theindividualI&FcircuitsarelogicallyOR-edtogenerate thecontrolsignalsforthe switches.5.2.2EnergyUtilization Asmentionedpreviously,duringinitializationthecapaci torvoltageisresetto V ss andwitheverypulsethecapacitorvoltagerises.However,t hecapacitorvoltagecan riseonlycloseto V mid .Thereasonforthisisthatanyvoltagegreaterthanthiswil lresult inthePMOStransistor P 1 inFigure 5-2 turning-offtherebyresultinginnonegative feedback.Inabsenceofsufcientnegativefeedbackvoltag eatthesourceofthereset 94

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] + V mid Vss P 1 Vss + + Vdd C mtI in Delay + tV m Delay V th + V thVpulse+VpulseV pulse V pulse ~V pulse ~V pulse V pulse ~V pulse V pulse C 0 Figure5-4.SecondgenerationCurrentConveyorcircuitwit htheswitchesandtheI&F circuit. transistorwouldnolongerbeclosetoV mid .Oncethecapacitorvoltagehasraisedclose toV mid theharvestingloopneedstobedisabledandtheharvesteden ergyneedstobe utilized.Theharvestedenergycaneitherbeusedtocharget hebatteryorcanbeused topowerbackanon-chipcircuit. Usuallyenergyharvestingsystemsusesomeformofapowerco nverterscheme toconvertthevoltageonthecapacitor[ 115 ].Thepowerconverterbooststheoutput voltageoftheenergytransducertoasuitablelevelthatena blesutilizationoftheenergy harvested.Therearetypicallytwoschemesusedforpowerco nversioninharvesting systemsnamelyboostconversionorachargepump.Aboostcon verterrequiresan inductor,whichincreasesthesystemcostandsize.Ontheot herhand,chargepumps useonlyswitchesandcapacitorsaremoreareaandcostefci ent.Chargepumpcircuits essentiallyuseswitchingonthetwoplatesofthecapacitor toeffectivelygenerate ahighervoltage.Fortheabovedescribedschemetheobvious choiceistousea charge-pumpcircuitinsteadofaboost-converter.Thereas onforthischoiceisthat theharvestingcapacitorchargesupuntilroughlyV mid .TheV mid voltageliesmid-way betweenV dd andV ss forreasonsexplainedinChapter 2 .Thusoneverysimplescheme 95

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forboostingthevoltageontheharvestingcapacitorcanbet oconnectthenegative plateofthecapacitor(theplateconnectedtoV ss inFigure 5-4 )toV mid afterithasbeen disconnectedfromtheharvestingloop.Thiswouldboostthe voltageonthecapacitorto nearV dd EnergyharvestingarchitecturesuseaDC-DCconverterorar egulatorafterthe up-conversionoftheharvestedenergytopowerloadcircuit s[ 116 ].Thisistypicallydone toensurethataconstantvoltageissuppliedtotheloadcirc uits.Sincetheaimofthis workistoillustrateenergyharvestingasafeasibleoption forI&Fcircuits,weusethe capacitorstodirectlypowerbackthecircuitswithoutthei mplementationofaregulator. 5.2.3FiniteStateMachine(FSM)BasedControlLogic Asmentionedabovethevoltageontheharvestingcapacitorc annotexceedV mid thustheharvestingcapacitorneedstobedisconnectedfrom theharvestingloopand theharvestingneedstobedisabled.Inordertomaximizethe energyefciencyofthe harvestingloopinsteadofusingjustoneharvestingcapaci tortwocapacitorscanbe usedasanalogping-pongbuffers.Analogping-pongbuffers implythatoncetherst capacitorisfullychargesasecondcapacitorcanbeswapped inplaceoftherstone intheharvestingloop.Duringthistimewhiletherstcapac itorpowersthecircuitthe secondcontinuestoharvestenergy. Inordertomanagetheharvestingcapacitorsasping-pongbu ffersanefcient digitalcontrolisessential.Thebasicalgorithmformanag ingtheping-pongbuffersis fairlystraightforwardandisshowninFigure 5-5 .Duringtheinitializationstepthecircuit ispoweredthroughthesupplywhiletherstcapacitorcharg esthroughtheharvesting loop.Oncetherstcapacitor,C 0 ,chargesallthewaytoV mid ,itisdisconnectedfromthe harvestingloopandthesecondcapacitor,C 1 ,isconnectedinplaceofC 0 .Meanwhile thesupplyisdisabledandC 0 isusedtopowerthecircuit.C 0 continuestopower thecircuitandstartstodischarge.Theprocesscontinuest illeitherC 0 discharges signicantlybelowV dd orC 1 chargesclosetoV mid .IfC 1 managestochargebeforeC 0 96

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hasdischargedfullythentheharvestingloopisdisabledan dthesystemwaitstillC 0 getsdischargedsothatnowharvestingcanoccuronC 0 andC 1 canpowerthesystem. OntheotherhandifC 0 dischargesbeforeC 1 isfull,thenthepowersupplyisenabled andthesystemwaitsforC 1 togetfullsothatitcanbeusedtopowerthecircuitand harvestingcancontinueonC 0 Insummaryonecapacitorharvestsenergywhiletheotherone powersthecircuit. Ifthecapacitorpoweringdischargesbeforetheothercapac itorhasfullycharged thenthepowersupplyisenabledandthesystemwaitsfortheh arvestingcapacitor tochargefully.Inthescenario,thattheharvestingcapaci torchargesfullywhilethe circuitispoweredbythecapacitorthentheharvestingloop isdisabledsinceboththe capacitorsarenowfullycharged.Theharvestingloopisreenabledonlywhenoneof themdischarges. Sincethecontrolalgorithmneedstobeimplementedasadigi talcircuitanitestate machine(FSM)forthecontrolowhastobedesigned.Theequi valentFSMforthe controlalgorithmisshowninFigure 5-6 .TheshownFSMrequiresacombinationoffour basicconditionalstatementstochangestates.Thesecondi tionsare: (a). Vcap0 V mid (b). Vcap0 < V dd (c). Vcap1 V mid (d). Vcap1 < V dd Implementingthefourconditionsrequirestheuseoffouran alogcomparators.Use ofmultipleanalogcomparatorsincreasestheareaandpower costoftheharvesting system.Asmarterapproachistomultiplextheanalogcompar ators.Themultiplexing logiccanbedesignedbyrealizingthattheharvestingcapac itor'svoltageneedstobe comparedtoV mid whereasthecapacitorpoweringthecircuitneedstobecompa redto V dd .Thustheabovefourconditionscanbeimplementedusingamu ltiplexerandjust twocomparators.Inordertofurtherimprovetheenergyefc iencyofthesystemthe 97

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Harvest on Cap0till it fully charges Enable Power Supply Harvest on Cap1till Cap1 is full Power circuit using Cap0 till Cap0 discharges Disconnect power supply Once Cap0 is full Cap0 still fulland Cap1 also full Disable harvesting Continue powering using Cap0 till it is empty Cap0 dischargedCap1 still not full and Enable Power Supply Continue harvesting onCap1 till its full Cap 1 full Cap0 discharged and Cap1 full Start harvesting on Cap0Power circuit using Cap1 till Cap0 is full till Cap1 is empty Cap0 empty Cap1 still fulland Cap0 still not full Reset Cap1 still full and Cap0 also full Cap1 discharged and Cap0 still not full Cap1 discharged and Cap0 full Cap0 still fulland Cap1 still not full Disable harvesting Continue powering Using Cap1 till it is empty Cap1 empty Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Goto Step 4Goto Step 4 Goto Step 3Goto Step 1 Goto Step 3 Figure5-5.Thebasicalgorithmmanagingtheenergyharvest ingloopwithtwo capacitorsasping-pongbuffers. comparatorscanbealsoisenabledanddisabled.Thecompara torfortheharvesting capacitorcanbeenabledduringthepulse-times,sincethec hargeontheharvesting capacitorincrementsonlyduringpulsetimes.Alsothecomp aratorformonitoringthe powersupplyingcapacitorcanbedisabledwhenthepowersup plyisusedtopowerthe circuit. TheconceptualFSMshowninFigure 5-6 stillneedstobeimplementedasadigital circuit.Inordertodosothestatesandthetransitioncondi tionsneedtoberepresented aslogicvalues.TheequivalentFSMwiththecontrolsignals andthedigitalagsis showninFigure 5-7 .Thetransitiontimingdiagramforthecontrolsignalsandv arious 98

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Enable P.SupplyHarvest on Cap 0 Harvest on Cap 1 Enable P. Sup Vcap 0 > Vdd Vcap1VddVcap1~Vmid & Disable Harvesting Power Circuit by Cap1 Vcap0VddVcap0Vdd Vcap1>Vdd & Vcap0 ~=Vmid Vcap1>Vdd Vcap0
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S-Rlatchesareusedinsteadofip-opstorepresenttheag ssincethesystemis asynchronous.Logicinputof0-0fornandgateS-Rlatchesre sultsinanillegaloutput statehencenor-gateS-Rlatchesareused.Twoanalogcompar atorsarerequiredto monitorthevoltageoftheharvestingcapacitorandthesupp lycapacitorrespectively. Thesegeneratetwodigitalcontrolsignalsnamely 1. V c hc Theoutputofthecomparatormonitoringharvestingcapacit or'svoltage. Thiscomparator'ssignaloutputgoeshighiftheharvesting capacitor'svoltage becomesapproximatelyequaltoV mid .Theoutputofthecomparatormonitoringthe powersupplyingcapacitor'svoltage.Inordertomakethesy stempowerefcient thiscomparatorisenabledonlyifEn HishighandtheI&Farrayhasgenerateda spike. 2. V c sc Thiscomparator'ssignaloutputgoeshighifthesupplycapa citor'svoltage goesbelowthedesiredsupplyvoltage.Thiscomparatorisen abledonlyiftheEn S isresetandiftheI&Fcircuitgeneratesaspike. ThetimingdiagramshowninFigure 5-8 isalsodescribedbelow: 1. Duringtheinitializationstepharvestingandsupplyareen abled(En H=1and En S=1),boththecapacitoragsareempty(C0 F=0andC1 F=0),theharvesting capacitoragindicatesthattheC0istheharvestingcapaci tor(H C=0)andthe supplycapacitoragindicatesthatC0willpowerthesystem whenthesupplyis disabled(S C=0). 2. Aftertheresetphase,thesystemstartstoharvestonC0till thevoltageonC0 (V cap0 )reachesclosetoV mid whichresultsinthecomparatorsignalV c hc going high. 3. V c hc goinghighin-turnsetstheC0 FagtoindicatethattheC0bufferisfulland togglestheH Ctologic1toindicatethattheharvestingcapacitorisC1.A high C0 Fdisablesthepowersupply(En S=0)andconnectsC 0 asthepowersource forthecircuit.Thenegativeplateofthesupplycapacitor( whichwaspreviously connectedtoV ss )isnowconnectedtoV mid thuspumpingV cap0 tonearV dd 4. TheharvestingnowoccursonC1andthevoltageontheharvest ingcapacitor (V cap1 )ismuchlowerthanV mid thusthecomparatorsignalV c hc isautomatically pulledlow. 5. CapacitorC0continuestopowerthecircuittillV cap0 fallsbelowasetthreshold voltage.ThisresultsinthecomparatorsettingthesignalV c sc high. 100

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Vc_hc = 1 Vc_sc=1 &Vc_hc = 0 Vc_sc =0 &Vc_hc = 0 Vc_sc=1 &Vc_hc = 1 Vc_hc = 0 Vc_sc=1 & Vc_hc = 0 Vc_hc = 1 Vc_sc =0 &Vc_hc = 0 Vc_sc =0 &Vc_hc = 1 Vc_sc =0 Vc_hc = 1 & Vc_sc=1 Vc_sc=1 Vc_sc=1 Vc_sc =0 & Vc_hc = 0 Vc_sc =0 En_S =1En_H=1C0_F=0C1_F=0H_C=0S_C=0 H_C=1 En_S=0En_H=1C0_F=1C1_F=0S_C=0 En_S=1S_C=1 H_C=1 C1_F=0 C0_F=0 En_H=1 En_S=0En_H=1C0_F=0C1_F=1H_C=0S_C=1En_S=0C0_F=1 H_C=1C1_F=1 En_H=0S_C=1 En-S=0En_H=0S_C=0C1_F=1C0_F=1H_C=0 Reset Figure5-7.TheFSMrepresentationofthecontrolloopwithd igitalagsandcontrol signals. 6. V c sc goinghightogglestheS Cagtologic1indicatingthatwheneverthepower supplyisdisablednext,capacitorC1wouldpowerthecircui t.V C sc alsoresetsthe C0 FagtologiczeroindicatingthatcapacitorC0isnowempty. 7. V c sc stayshightillC1becomesfullandstartstopowertheI&Farr ay.OnceC1 startstopowerthecircuitV c sc isautomaticallypulledlow. 8. OnceC1isfulltheprocesscontinuesfromstep2inasimilarf ashion.Ifthe harvestingcapacitorbecomesfullwhilethecircuitispowe redbythecapacitor energyharvestingisdisabledande-enabledoncethesupply capacitorbecomes emptyi.e.V C sc goeshigh. Basedontheabovedescriptionofthecontrolowsomeofthel ogicexpressionsfor En HandEn Sarefairlystraightforwardandcanbederivedasfollowing : 101

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Vc_hc Vc_sc H_C S_C C0_FC1_FEn_SEn_H Figure5-8.Expectedtimingbehavioranddependenciesofva riouscontrolags representingtheworkingoftheFSM. SetEn H = C 0 F C 1 F ResetEn H = ( C 0 F + C 1 F ) SetEn S = C 0 F + C 1 F ResetEn S = ( C 0 F C 1 F ) AsmentionedpreviouslyagH Cindicateswhichcapacitorshouldbeused intheharvestingloop.Alogicalvalueof0indicatescapaci torC 0andavalueof 102

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1indicatesthatharvestingshouldoccuroncapacitorC 1.Asthevoltageonthe harvestingcapacitorgoesnearV mid andV c hc goeshighandagH Cshouldtoggle. ThismeansthatiftheharvestingcapacitorwasC0whenV c hc wenthigh,theagshould nowindicateC1astheharvestingcapacitorandvice-versa. Basedonthislogicsetting andresettingtheagH Cseemseasyandtheobviouslogicalexpressionseemstobe: SetH C = H C V c hc ResetH C = H C V c hc Theproblemwiththelogicaboveisthatinabsenceofaclocki twillleadtoH C oscillatingbetween0and1.Insteadofimplementinganasyn chronoushandshake protocolacleversolutionistouseapositiveedgetriggere dtoggle-ipop(TFF)with V c hc connectedtoitsclockandthetogglesignalsetasalwayshig h.Theoutputofthis TFFcanbeusedasH Cinstead.SincetheTFFispositiveedgetriggeredonceV c hc goeshighittoggles,thischangestheharvestingcapacitor andsubsequentlyV c hc goes low. SimilarlytheS Cagindicateswhichcapacitorispowering(orwillpower)t he circuit.V c sc goinghighindicatesthatthecapacitorthatwaspoweringth ecircuithasrun belowtheacceptablethresholdandthevalueofS Cshouldtoggle.IfS Cwassetat 0andC0 Fwassetat1thisimpliesthatcapacitorC0waspoweringthec ircuit.When V c sc goeshighitimpliesthatC0 FshouldbepulledlowandS Cshouldtoggleto1, indicatingthatC1willpowerthecircuitnextwheneveritge tsfullandvice-versa.Based onthistheobviouslogicalexpressionsforS Care SetS C = S C V c sc ResetS C = S C V c sc 103

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AsisthecaseforH Cusingtheexpressionsabovewouldleadtooscillations.He nce apositiveedgetriggeredTFFisalsousedforS CagwithV c sc astheclockforthe ip-op. ThelastsetsofagsareC0 FandC1 F,whichindicatewhetherornotcapacitors C0andC1arefull.LogicallyC0 FshouldgohighwhenH Ctransitionsfromlogic 0tologic1andC1 FshouldgohighwhenH Ctransitionsfromlogic1tologic0. ThisimpliesthatusingapositiveedgetriggeredTFFforC0 Fandanegativeedge triggeredTFFforC1 Fshouldsufce.TheproblemarisesfromthefactthatagsC0 F andC1 FaresetbythetransitionsofH C(whichisin-turnsetthroughalow-to-high transitionofV c hc )howevertheyshouldresetthroughthelow-to-hightransit ionsofV c sc AstraightforwardapproachtosetC0 FwouldbetoologicallyandV c hc with H C .The challengeusingthisapproachisthatH Cbeingadigitalcircuitwilltogglemuchfaster thanthecomparatorwouldbeabletopullitssignallowandwo uldresultinsettingboth C0 FandC1 Fsimultaneously.SinceH CtogglesatthepositiveedgeofV c hc andV c hc ispulledlowoncetheharvestingcapacitorhaschanged,asm arterapproachwouldbe tosetC0 FandC1 FatthefallingedgeofV c hc sincebythenH Cwouldhavealready settled.Thus,weuseanegativeedgetriggeredTFFwithV c hc asit'sclocktogenerate asignalcalledasH C temp,andusethistosetC0 FandC1 F.Thelogicalexpressions wouldthenderiveto SetC 0 F = H C temp V c hc SetC 1 F = H C temp V c hc Thecaseofresettingthecapacitoragsissimilarinnature assettingthem.Since, theresetoperationissupposedtooccurwhenV c sc goeshighanddependingonwhat thevalueofS Cwastheappropriateagistobereset.S Cbeingadigitalcircuitit changesmuchfasterthanV c sc canpullthesignallow,henceanegativeedgetriggered signalcalledS C tempisagainrequiredandthelogicalexpressionsforreset tingthe 104

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agsareasfollowing ResetC 0 F = S C temp V c sc ResetC 1 F = S C temp V c hc InsummaryasophisticatedFSMbasedcontrolloopisnecessa ryformanaging theharvestingcapacitorsasanalogping-pongbuffers.Alt houghthealgorithmseems fairlystraightforward,inabsenceofaclocksignalmanagi ngthetransitionsbecomes challenging.Thechoiceoflogic-gateshastobesuchthatth epowerandareaover headistotheminimum.Whereevernecessarylogicexpressio nsareconvertedsuch thatresultingexpressionscanbeimplementedusingonlyNA NDandNORgates. Theanalogcomparatorsrequiredforgeneratingthecontrol signalsV c hc V c sc arevery simplesinglestagecomparatorsasdescribedinSection 3.1.1.1 inChapter 3 .As mentionedpreviouslyenergysavingsaresignicantwhenmu ltipleI&Fcircuitsharvest energythroughthesamearchitecture.IncaseofmultipleI& FcircuitstheFSMremains thesame,theonlychangethatoccursisthatthepulsesfroma lltheI&Fcircuitsare logicallyOR-edandisusedinplaceofasingleV pulse .Thecompleteenergyharvesting architectureisshowninFigure 5-9 5.3ResultsandDiscussion Theabovedescribedenergyharvestingsystemwasdesigneda ndfabricatedin AMI0.6 m technology.EightbiphasicI&Fcircuitsalongwiththeener gyharvesting schemewereimplementedonthechipwhereastheharvestingc apacitorswereoff-chip. Formeasurementeightdifferentsinusoidalwaveformswere givenasinputtotheeight channels.Theamplitudeofsinusoidalwaveformsoneachcha nnelwasintherange of500nAto1.5uAwhereasthefrequencywassetat2KHzoneach channel.The refractoryperiodwaskeptintherangeof4 S to15 S andthethresholdwaskeptin therangeof400mVto700mV.Thetwo100nFharvestingcapacit orswereoff-chip. 105

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I&F Array .... .... V pulse ~V pulse V mid TFF TFF H_C H_C_temp ~H_C_temp Vc_hc ~Vc_hc SR Latch S R Q ~Q C0_F ~C0_F SR Latch S R Q ~Q C1_F Set_C0_FSet_C1_F ~C1_F TFF TFF Vc_scS_C ~Vc_scS_C_temp~S_C_temp Reset_C0_F Reset_C1_F Reset_C0_FReset_C1_F Reset_En_S Set_En_S SR Latch S R Q ~Q En_S ~En_S SR Latch S R Q ~Q En_H ~En_H Set_En_H Reset_En_H C0_FC1_F ~C0_F~C1_F~C0_F~C1_F M U X sel 0 1 En_S M U X sel 0 1 ~H_C H_C V_cap M U X sel 0 1 ~En_S~S_C Vss Vmid M U X sel 0 1 ~En_S Vss S_C Vneg_C1 Vneg_C0 Vcap1 Vcap0 M U X sel 0 1 S_C Power_Supply Vcap_sup V_supply + P 1 Vss + ~V pulse V pulse ~V pulse V pulse Vneg_C0 Vneg_C1 + Vcap_sup Vc_sc Vsup_th + Vc_hc Enable Comp = ~En_S Vpulse Enable Comp. = En_H V_pulse Vmid Vmid V_cap Figure5-9.Thecompleteharvestingarchitectureschemati c. ThemeasuredcapacitorvoltagesforC 0 andC 1 andthedigitalagsareshowninFigure 5-10 TherstsubplotofFigure 5-10 showsthevoltageofcapacitorC 0 andthesecond subplotshowsthevoltageonC 1 .Thethirdsubplotshowsthevoltageoftheharvesting capacitor.Thefourthsubplotshowsthevoltageofthepower supplyingcapacitor (Vcap supinFigure 5-9 ).ThesystemstartsbyharvestingenergyoncapacitorC 0 andcontinuestillthevoltagerisesclosetoV mid .Atthispointthenegativeplateof thecapacitorisickedupfromV ss toV mid whichisindicatedbythesuddenjumpin Vcap0around500ms.Thisresultsinthestartofharvestingo nC 1 alsoindicatedby theH Cgoingtologic1.C 0 powersthecircuitalbeitforaverynegligibleduration 106

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-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 C0FTime in ms -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 C1FTime in ms -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 EnSTime in ms -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 HCTime in ms -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 SCTime in ms -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 V sup capTime in ms -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 V harv capTime in ms -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Vcap1Time in ms -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Vcap0 Time in ms Figure5-10.Measurementresultsfortheenergyharvesting architecture. 107

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ofapproximately3msafterwhichS CtogglesindicatingthatC 1 isnextinqueueto powerthecircuit.DuetotimescalesitseemsthatH CandS Coccursimultaneously, howeverthechangeinH CprecedesthechangeinS Cbyroughly3ms.S Cgoing tologic1icksthenegativeplateoftheC 0 toV ss thusVcap0suddenlydrops.Since thecomparatormonitoringthesupplycapacitorwassettoV dd -150mV,C 0 doesn't dischargeallthewaytoV ss .TheprocessrepeatsforC 1 inthesamemanner.Once harvestingstartsagainonC 0 ittakeslesstimeforittochargeuptoV mid sinceitwasnot dischargedcompletely. Theratioofenergytransferredfromthemembranecapacitor totheharvesting capacitorisroughly88.7%.Sincethedischargecurrenthas onlyonepathfromthe membranecapacitortotheharvestingcapacitoritisexpect edthattheratiowouldbe closeto100%,howeversomeofthecurrentisdissipatedthro ughthebody-source connectionofthetransmissionswitches.Theenergyconsum edbytheFSMisnegligible whenthecapacitorsarechargingupsinceitisactiveonlydu ringthetransitions i.e.whenVcap0orVcap1exceedV mid ortheyfallbelowV dd .Theaverageenergy consumedbythedigitalpartoftheFSMisextremelylowascom paredtotheanalog parts,sincetheFSMconsumesenergyonlyduringthestatetr ansitions.Oncepossible waytoreducetheaverageenergyconsumedbythedigitalpart oftheFSMistolimit frequenttransitionsbetweenvariousstates.Frequenttra nsitionscanbelimitedbyusing largerharvestingcapacitors.Theanalogcomparatorsused togeneratethecontrol signalsareadaptivelybiasedwithapeakbiascurrentof100 nAandasmentioned previouslythecomparatorbiascurrentsareturnedoffdepe ndingonthelogicconditions. Aswewillseethesignicantsourceofpowerconsumptionist heamplieraspartofthe currentconveyor,theamplierisbiasedat1 A AssumingC m as20pFandV th as650mVtheenergytransferredtotheharvesting capacitorwithanefciencyof88.7%canbeestimatedas E trans = 1 2 C m V 2 th 0.887=5.64 pJ (5–1) 108

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Asmentionedpreviouslytheamplierisenabledonlyduring thepulsetimes.Assuming arefractoryperiodof4 Stheenergyconsumedbytheamplierforconveyingthe currentfromC m totheharvestingcapacitorC 0 canbeestimatedas: E amp =( V dd Vss ) I bias t ref (5–2) =3.3 500 10 9 10 4 6 =6.6 pJ Basedonthenumbersaboveitwouldtake6.6pJofenergytotra nsferanenergy of5.64pJ.Ittakesroughly1.1timesasmuchenergytotransf eraswhatisbeing transferred.Thusthesystemisnotenergyefcientasfaras transferringthecharge fromasingleI&Fcircuitisconcerned.However,iftherewer emultipleI&Fcircuits connectedtothesameenergyharvestingcircuitandthepuls esweretooverlap,then theefciencyofthesystemwouldbehigher. Theenergyharvestingcircuitconsistsofthecomparatorsa ndtheFSMwhich alsoconsumeenergyduringdifferentphasesofoperation.I nordertogainabetter understandingoftheoverallenergyconsumptionoftheharv estingcircuittheenergy consumptionofthecircuitneedstobeanalyzedduringthese phases.AsseeninFigure 5-10 ,initiallythecapacitorstakealongtimetochargetoV mid .Oncethecapacitors powerthecircuittheydonotdischargeallthewaytoV ss butareroughly150mVbelow V mid (withthenegativeplateofthecapacitorxedatV ss ).Fromtheperspectiveof energyconsumptionduringvarioustransitionstatesthegr aphsasshowninFigure 5-10 canbedividedintothefollowingtimedurations: 1. t 0 -t 1 :Systeminitializesattimet 0 andatinstantt 1 capacitorC 0 chargesfully. 2. t 1 -t 2 :Powersupplyisdisabledandsystemispoweredusingthehar vested energythroughC 0 .EnergyisharvestedoncapacitorC 1 3. t 2 -t 3 :Powersupplyisre-enabledsincecapacitorC 0 isdischarged.Energyis harvestedcontinuesoncapacitorC 1 4. t 3 -t 4 :Powersupplyisdisabledandsystemispoweredusingthehar vested energythroughC 1 .EnergyisharvestedoncapacitorC 0 109

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Table5-1.Energyconsumptionofvariouscomponentsofthee nergyharvestingcircuit fordifferenttimedurations. timesegment t 0 -t 1 t 1 -t 2 t 2 -t 3 t 3 -t 4 timeduration 562ms 2.8ms 550ms 3ms Numberofpulses 45K 300 43K 300 CurrentConveyor 91.542nJ 0.3237nJ 93.0607nJ 0.3506nJ FSM 0.03031nJ 0.0287nJ 0.0398nJ 0.0324nJ Comp(V c hc ) 11.793nJ 0.1182nJ 12.1863nJ 0.1055nJ Comp(V c sc ) 0.6786nJ 0.1209nJ 0.8320nJ 0.1049nJ EnergyHarvestedonC0 137.12nJ 0nJ 0nJ 0.7415nJ EnergyHarvestedonC1 0nJ 0.7407nJ 138.21nJ 0nJ EnergyUtilizedfromC0 0nJ 1.3778nJ 0nJ 0nJ EnergyUtilizedfromC1 0nJ 0nJ 0nJ 1.3802nJ TotalEnergyHarvested 136.12nJ 0.7407nJ 138.71nJ 0.7415nJ TotalEnergyOverhead 107.3167nJ 0.5815nJ 106.1188nJ 0.5934nJ EnergyEfciency 24.13% 21.49% 23.49% 19.97% 5. t4-end:thestatesrepeat. Themeasuredresultsfromeachoftheabovedurationsaresum marizedinTable 5-1 Asitisevidentfromthetableinanygivencyclethemajorene rgyoverheadcomes fromtheamplierinthecurrentconveyoreventhoughitisdi sabledduringin-between pulses.Duringthersttimedurationtheenergyoverheadof thecomparatormonitoring supplycapacitorisnegligibleandismainlyduetoleakagec urrentssinceitisdisabled. IntheseconddurationwhenC 0 powerstheI&Farrayboththecomparatorsareenabled andaremonitoringtherespectivecapacitors,thisresults inahigherenergyoverhead. Althoughtheoverallenergyefciencydrops,theI&Farrayi snowpoweredthrough theenergyharvestedduringthersttimeduration.Theener gyutilizedthroughC 0 is notaccountedforwhilecalculatingthepercentageefcien cy.Asexpectedtheoverall energyconsumptionoftheFSMremainsrelativelyconstants incetheFSMiscomprised mainlyofdigitalblockswhichconsumeenergyonlyduringth estatetransitions. 5.4ConclusionandFutureWork Inthischapteranovelenergyharvestingschemewaspropose danditsfeasibility explored.ThecircuitwasimplementedinAMI0.6 mtechnology.Measurementresults 110

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indicatethattheover-allefciencyofthesystemisonanav erageroughly23%.The energyoverheadcanbereducedbyeitherpackinginmoreI&Fc ircuitsinonechip orbymakingimprovingtheamplierstructure.Poweringbac kthecircuitbydirectly connectingthecapacitorresultsinsuddenvoltagedrops.T hus,eventhoughthe capacitorcanpossiblypowerthecircuitforalongerperiod ,suddendropinvoltage resultsinaninefcientstate-change.Thereforeavoltage regulatorisessentialfor effectiveutilizationoftheharvestedenergy. 111

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CHAPTER6 CONCLUSION Inthisthesis,designoptimizationsofthesiliconI&Fcirc uitshavebeenpresented. Therearemanyresearchersthatdesignneuronmodelsinhard ware.Alotofeffortis spentindesigningthesecircuitssothattheirresponsemat chescloselywithbiological neurons.Aspartofthisthesis,weoptimizetheI&Fcircuitw iththegoalofminimizingthe pulse-timejitter.Inordertoquantifythisfurther,weuse thesepulsetimestoreconstruct thestimulusgiventothecircuit.Theerroroftherecovered signalisusedasthemetric. SomeofthepriorworkdoneinI&Fdesignisreviewed.AtCNEL, theI&Fcircuit hasbeenusedtoencodecontinuoustimesignals.Areviewoft hereconstruction algorithmispresented.TheI&Fcircuitisusedtoencodethe signalinasynchronous pulsetimes.Thereexistsacommunityofresearchersdevelo pingnovelasynchronous analog-to-digitalconvertersandtheI&Fcircuitcanbeuse dforencodingandthen reconstructingsampledcontinuoustimesignal.Someofthe relevantconceptsof asynchronousADCsandrecentarticlespublishedarereview ed.Aspartofthiswork, aformalframeworkfortheevaluationoftheI&Fcircuitasan ADCispresented.Using asynchronouspulsestoencodeasignalpresentssomechalle nges.Usingstandard metricsforevaluatingADCsweshowthattheI&Fcircuitoutp erformsseveralexisting ADCarchitectures.ThegureofmeritfortheI&Fsampleris0 .6pJ/conversiondespite thefactthatexistingI&Fhasbeenimplementedinamucholde rtechnology.However, assemiconductortechnologyadvances,conventionalADCde signswouldnaturally outperformtheexistingcircuitimplementationsoftheI&F circuitin0.6 m technology. Thus,theperformanceofthesamplerissimulatedusingthew ell-acceptedpredictive technologymodels(PTMs)fromtheArizonaStateUniversity .I&Fcircuitachievesa FOMof9.8fJ/conversioninthe45nmtechnologynode.Thusin dicatingthattheI&F circuitscalesfavorablywithtechnologyscaling. 112

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WhethertheI&FcircuitisusedanADCorusedaspartofalarge arrayofhardware neuronsrunningacomputationalalgorithm,powerconsumpt ionisakeycriteria.A bottom-upapproachistakentoevaluateI&F'scomponentsan dtheirrespectiveimpact onthepowerandenergyconsumption.Keycircuitoptimizati onsalongwithnovelcircuit architecturesarepresentedforloweringtheenergyperpul se.Theproposedcircuits havebeenfabricatedandmeasuredresultsindicateanimpro vementofroughly80times overthisI&Fcircuit'spredecessorsdevelopedatCNEL. Since,alotofeffortgetsputintodesigningandoptimizing largearraysof neuronsforenergyconsumption,itisofinteresttoknowwhe relaysthelimittoenergy consumptionoftheI&Fcircuit.Alotofworkhasbeendonetoe xplorethelimitsofpower andenergyconsumptionofdigitalcircuits.Weexplorethel imitsofpowerandenergy consumptionfortheI&Fcircuit.Inconstructingthestagef oranalyzingtheI&Fcircuitwe exploretheinterplayofpower,delayandenergyforadigita landanalogcircuit.Based ontheanalysisdoneandpresented,theminimumenergyrequi redforgeneratinga pulseseemstobeintheorderofafewtenthsoffJs.Inestimat ingthisnumberthestatic powerconsumedinbetweenspiketimeswasignored.Atlowerp ulseratesthestatic powerdissipation(powerconsumedinbetweenthepulses)is highresultinginahigher energy/pulseforlowerpulserates.Asthepulserateincrea ses,theinter-pulseinterval becomesshorterandresultinginalowerstaticpowerdissip ation.Thusforextremely highpulseratestheenergy/pulsetendstoreachthislimit. Severalcircuitdesigntechniqueshavebeenexploredandim plementedfor preventingtheI&Fcircuitfromconsumingexcessivepowera nd/orenergy.Aspart ofthiswork,weproposetouseanenergyharvestingschemeto furtherincreasethe energyconsumptionoftheI&F.Anovelenergyharvestingset upwithanefciencyof roughly26%hasbeenpresentedandimplementedonchip.Theb asicideabehind harvestingenergycomesfromtherealizationthatthecharg eheldinthemembrane capacitoriswastedtogroundaftereverypulse.Wefabricat edaspeciallydesigned 113

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energyharvestingcircuitwithminimumareaoverhead.Thec ircuitusestwooff-chip capacitorsaspingpongbuffersforincreasingtheharveste denergy. InsummarytheI&Fcircuithasbeenoptimizedthroughvariou smeanspossiblefor minimumenergydissipationwhilepreservingthespiketime s. 114

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BIOGRAPHICALSKETCH ManuRastogiwasborninDelhi,Indiain1982toKapilaandRam akantRastogi.He hasoneyoungersister,NehaRastogi.ManureceivedaBachel orofTechnologydegree inInformationandCommunicationTechnologyfromtheDhiru bhaiAmbaniInstituteof InformationandTechnology(DAIICT),Gandhinagar,Indiai nMay2005.Heworkedas aresearchengineerfortheVLSIgroupatDAIICTfromJuly200 5tillJuly2006.Since Fall2006,ManuhasbeenaresearchassistantintheComputat ionalNeuroEngineering Laboratory(CNEL)attheUniversityofFloridaworkingwith Dr.JohnG.Harrisonlow powertechniquesforneuralrecording.Hisresearchintere stsincludespikebased computation,lowpowerandmixedsignalcircuitdesign.Hei salsointerestedinwriting softwareandlikestolearnnewcomputerlanguagesandtechn ologies.Manureceived hisMasterofScience(MS)degreeinelectricalengineering fromtheUniversityof Floridain2008andhisPh.D.degreeinelectricalengineeri nginMay2012alsofrom UniversityofFlorida.HenowworksforQualcommCorporateR &Dasacircuitdesigner intheirneuromorphicmachinesgroup. 124