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Advanced Device Reliability Study of GaN HEMTs Using Low Frequency Noise Spectroscopy

Permanent Link: http://ufdc.ufl.edu/UFE0043977/00001

Material Information

Title: Advanced Device Reliability Study of GaN HEMTs Using Low Frequency Noise Spectroscopy
Physical Description: 1 online resource (93 p.)
Language: english
Creator: Rao, Hemant P
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2012

Subjects

Subjects / Keywords: gallium -- low-frequency -- nitride -- noise -- reliability -- semiconductor
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: AlGaN/GaN HEMTs have entered commercial production from 2005 and have demonstrated excellent performance levels for high power RF applications like cellular 3G and WiMax base transceiver stations (BTS). To realize the full potential of this material technology it is imperative to gain a deeper understanding of the failure mechanisms which are not fully understood yet. This work uses low frequency noise as a defect spectroscopic tool and microwave noise spectroscopy for studying hot-carrier effects. A baseline is established by identifying key noise sources in the AlGaN/GaN HEMT gate stack and channel region.The channel is found to be stable showing only interface defect related 1/f type noise. The gate stack shows vulnerability with the presence of mobile point defect centers and the existence of dislocations very close to the gate metal. The role of the inverse-piezoelectric effect as a failure mechanism is explored by systematic gate step stress. New permanent defect centers are generated right under the gate metal contact along with the activation of mobile point defects. The channel is found be to immune to the stress. The role of impurity diffusion as a precursor to catastrophic degradation is also pointed out. Key bias points are identified which result in permanent trap creation at the AlGaN/GaN channel interface. The role of hot-carriers as a failure mechanism is discussed by measuring electron temperature profiles in the channel. Finally degradation of the gate stack under RF overdrive stress is studied and the activation energy and the trap location of a point defect center in the AlGaN barrier is extracted.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Hemant P Rao.
Thesis: Thesis (Ph.D.)--University of Florida, 2012.
Local: Adviser: Bosman, Gijs.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2012
System ID: UFE0043977:00001

Permanent Link: http://ufdc.ufl.edu/UFE0043977/00001

Material Information

Title: Advanced Device Reliability Study of GaN HEMTs Using Low Frequency Noise Spectroscopy
Physical Description: 1 online resource (93 p.)
Language: english
Creator: Rao, Hemant P
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2012

Subjects

Subjects / Keywords: gallium -- low-frequency -- nitride -- noise -- reliability -- semiconductor
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: AlGaN/GaN HEMTs have entered commercial production from 2005 and have demonstrated excellent performance levels for high power RF applications like cellular 3G and WiMax base transceiver stations (BTS). To realize the full potential of this material technology it is imperative to gain a deeper understanding of the failure mechanisms which are not fully understood yet. This work uses low frequency noise as a defect spectroscopic tool and microwave noise spectroscopy for studying hot-carrier effects. A baseline is established by identifying key noise sources in the AlGaN/GaN HEMT gate stack and channel region.The channel is found to be stable showing only interface defect related 1/f type noise. The gate stack shows vulnerability with the presence of mobile point defect centers and the existence of dislocations very close to the gate metal. The role of the inverse-piezoelectric effect as a failure mechanism is explored by systematic gate step stress. New permanent defect centers are generated right under the gate metal contact along with the activation of mobile point defects. The channel is found be to immune to the stress. The role of impurity diffusion as a precursor to catastrophic degradation is also pointed out. Key bias points are identified which result in permanent trap creation at the AlGaN/GaN channel interface. The role of hot-carriers as a failure mechanism is discussed by measuring electron temperature profiles in the channel. Finally degradation of the gate stack under RF overdrive stress is studied and the activation energy and the trap location of a point defect center in the AlGaN barrier is extracted.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Hemant P Rao.
Thesis: Thesis (Ph.D.)--University of Florida, 2012.
Local: Adviser: Bosman, Gijs.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2012
System ID: UFE0043977:00001


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1 ADVANCED DEVICE RELIABILITY STUD Y OF GAN HEMTS USING LOW FREQUENCY NOISE SPECTROSCOPY By HEMANT P. RAO A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2012

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2 2012 Hemant P. Rao

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3 Dedicated t o my parents

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4 ACKNOWLEDGMENTS First and foremost I would like to e xpress my sincere gratitude to my advisor Prof. Gijs Bosman for his constant support, encouragement and guidance throughout my graduate research I appreciate the opportunity he provided me for doing two fruitful internships during my PhD I would like to thank Profs Mark Law, Toshi Nishida and Tim Anderson for s erving on my committee. I would also like to thank Prof. Ant Ural for giving me an opportunity to work on some of his research projects I appreciate the financial support provided by the Air Force Office of Scientific Research I would like to thank my c urrent and former colleagues in the lab Yige Hu, Weikai Xu, Yanbin An and Ramya Shankar for the numerous discussions and the time spent together. I would like to thank Erica Douglas for providing me wire bonded TLM and AFRL HEMTs. Finally I owe my deepest thanks to my wife Neha who always stood by me and kept me in high spirits for the last 4 years.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ .. 4 LIST OF FIGURES ................................ ................................ ................................ .......... 7 ABSTRACT ................................ ................................ ................................ ..................... 9 CHAPTER 1 GALLIUM NI TRIDE HIGH ELECTRON MOBILITY TRANSISTORS ...................... 11 Introduction ................................ ................................ ................................ ............. 11 Noise Mechanisms in Devices ................................ ................................ ................ 13 Organization ................................ ................................ ................................ ........... 15 2 NOISE SOURCES IN UNSTRESSED GAN HEMTS ................................ .............. 17 Motivation ................................ ................................ ................................ ............... 17 Devices under Stud y ................................ ................................ ............................... 17 DC Characterization ................................ ................................ ................................ 19 Drain Current Noise ................................ ................................ ................................ 20 Gate Current Noise ................................ ................................ ................................ 21 1/f Noise ................................ ................................ ................................ .......... 22 RTS Noise ................................ ................................ ................................ ........ 23 3 HIGH GATE ELECTRIC FIELD STRESS EXPERIMENT ................................ ....... 33 Motivation ................................ ................................ ................................ ............... 33 Device Description and Experimental Details ................................ ......................... 34 Stress Characterization Results ................................ ................................ .............. 35 DC Characterization ................................ ................................ ......................... 35 Drain Cu rrent Noise Characterization ................................ ............................... 36 Gate Current Noise Characterization ................................ ............................... 37 Discussion ................................ ................................ ................................ .............. 37 4 HIGH CHANNEL ELECTRIC FIELD STRESS EXPERIMENT ............................... 49 Motivation ................................ ................................ ................................ ............... 49 Experimental Setup and Results ................................ ................................ ............. 49 Experimental Setup and Stress Methodology ................................ ................... 49 Results and Discussion ................................ ................................ .................... 50 5 HOT CARRIER EFFECTS AND NOISE TEMPERATURE SPECTROSCOPY ...... 56 Motivation ................................ ................................ ................................ ............... 56

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6 Experimental Details ................................ ................................ ............................... 56 Results and Discussion ................................ ................................ ........................... 57 6 RF R ELIABILITY OF GAN HEMTS ................................ ................................ ........ 62 Motivation ................................ ................................ ................................ ............... 62 Experimental Details ................................ ................................ ............................... 63 Experimental Setup and Stress Methodology ................................ ................... 63 Experimental Results ................................ ................................ ....................... 64 Discussi on and Model ................................ ................................ ............................. 66 Channel Noise Analysis ................................ ................................ .................... 66 Gate Noise Analysis ................................ ................................ ......................... 66 Failure Mechanism ................................ ................................ ........................... 69 7 CONCLUSI ONS ................................ ................................ ................................ ..... 83 Summary of Results ................................ ................................ ................................ 83 Future Work ................................ ................................ ................................ ............ 85 LIST OF REFERENC ES ................................ ................................ ............................... 87 BIOGRAPHICAL SKETCH ................................ ................................ ............................ 93

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7 LIST OF FIGURES Figure page 2 1 Experimental setup for low frequency noise characterization.. ........................... 27 2 2 Device cross section of GaN HEMTs used in this study. ................................ .... 28 2 3 Normalized drain current noise (S ID /I D 2 ) as a function of increasing (indicated by arrow) gate bias ................................ ................................ ............................. 29 2 4 Normalized drain current noise (S ID /I D 2 ) at 200 Hz as a function of gate overdrive voltage V G V T ................................ ................................ ...................... 30 2 5 H on the sheet carrier concentration n s (cm 2 ) ................................ ................................ ................................ .................. 30 2 6 Compact model of noise sources in the channel (S IRS, S IRCH S IRD ) and gate region (S IRG ) of the device ................................ ................................ .................. 31 2 7 Gate current noise spectra as a function of decreasing (indicated by arrow) gate bias ................................ ................................ ................................ ............. 32 3 1 Illustration of prominent failure mechanisms in AlGaN/GaN HEMTs as a function of physical effects ................................ ................................ ................. 41 3 2 Reverse gate voltage step stress protocol ................................ .......................... 42 3 3 Threshold voltage changes during and after stress ................................ ............ 43 3 4 The evolution of the gate leakage current ................................ .......................... 44 3 5 Normalized drain current spectra (S ID /I D 2 ) for pre and post stress cases ............ 45 3 6 Normalized gate current noise (S IG /I G 2 ) for pre and post stress cases ............... 46 3 7 Gate current noise (S IG ) measured at 77 K for two DC biasing in triode region and saturation. ................................ ................................ ................................ .... 47 3 8 Conduction band diagram of the cross section at the gate drain edge ............... 48 4 1 Experimental setup f or performing electrical stress and LFN characterization ... 53 4 2 Summary map of stress effects ................................ ................................ .......... 54 4 3 Normalized drain current noise as a function of gate overdrive voltage ............. 55 5 1 Device noise temperature measurement system ................................ ................ 59

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8 5 2 I D V DS map showing the effect of hot carrier and self heating ............................ 60 5 3 The channel noise temperature measured at 2.20 GHz as a function of drain voltage ................................ ................................ ................................ ................ 61 5 4 The relative sensitivities of device noise temperature to a change in power dissipation (squares) and drain voltage ................................ .............................. 61 6 1 Experimental setup to perform DC characterization, RF stress and LFN measure ments. ................................ ................................ ................................ ... 71 6 2 RF power measurement at 3 GHz ................................ ................................ ...... 72 6 3 Degradation of RF output power for 3 dB (green) and 8 dB (brown) gain compression ................................ ................................ ................................ ....... 73 6 4 DC gate I V for V DS =0 are shown for pre stress (blue), post 3 dB compression stress (green) and post 8 dB compression stress (red). ................ 74 6 5 DC I D V GS for V DS =80 mV is shown for pre and post 8 dB compression stress. 74 6 6 Relative channel current noise before stress (blue) and after 8 dB compression stress (red) ................................ ................................ .................... 75 6 7 Relative gate current noise before RF stress (blue), after 3 dB RF stress (red) ................................ ................................ ................................ .................... 76 6 8 Mean capture (triangle) and emission times (square) determined from RTS noise data as a function of gate voltage (above threshold voltage) .................... 77 6 9 Relative gate current noise before stress (blue) and after 8 dB RF stress (red) ................................ ................................ ................................ .................... 78 6 10 Conduction band diagram under the gate ................................ ......................... 79 6 11 The ratio of mean time switching constants ................................ ........................ 80 6 12 Conduction band diagram under the gate for V GS = 2 V ................................ ..... 81 6 13 Gate diode I V characteristics ................................ ................................ ............. 82

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9 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy ADVANCED DEVICE RELIABILITY STUD Y OF GAN HEMTS USING LOW FREQUENCY NOISE SPECTROSCOPY By Hemant P. Rao May 2012 Chair: Gijs Bosm an Major: Electrical and Computer Engineering AlGaN/ GaN HEMTs have entered commercial production from 2005 and have demonstrated excellent performance levels for high power RF applications like cellular 3G and WiMax base transceiver stations ( BTS ) To realize the full potential of this material technology it is imperative to gain a deeper understanding of the failure mechanisms which are not fully understood yet. This work uses l ow frequency noise as a defect spectroscopic tool and microwave noise spect roscopy for studying hot carrier effects. A b aseline is established by identifying key noise sources i n the AlGaN/GaN HEMT gate stack and channel region The channel is found to be stable showing only interface defect related 1/f type noise. The g ate stac k shows vulnerability with the presence of mobile point defect centers and the existence of dislocations very close to the gate metal The r ole of the inverse piezoelectric effect as a failure mechanism is explored by systematic gate step stress New permanent defect centers are generated right under the gate metal contact along with the activation of mobile point defects The c hannel is

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10 found be to immune to the stress. The role of impurity diffusion as a precursor to catastrophic degradation is also point ed out. Key bias points are identified which result in permanent trap creation at the AlGaN/GaN channel interface. The role of hot carriers as a failure mechanism is discussed by measuring electron temperature profiles in the channel. Finally degradat ion of the gate stack under RF overdrive stress is studied and the activation energy and the trap location of a point defect center in the AlGaN barrier is extracted.

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11 CHAPTER 1 GALLIUM NITRIDE HIGH ELECTRON MOBILITY TR ANSISTORS Introduction High electron mobility transistors (HEMT) based on the III Nitride AlGaN/ GaN heterostructure have shown immense potential. The wide bandgap (3.4 eV) and high saturation velocity (~ 3 10 7 cm/sec) of gallium nitride makes it useful for both high power and high frequency applications. A performance metric often used to compare RF power transistor potential of various material technologies is the Johnson Figu re of Merit (JF o M) It is the product of the critical breakdown electric field and the carrier saturation velocity. Among the existing semiconductor technologies GaN shows the highest JFoM of ~ 50 THz.V which is 2 higher than 4H SiC, 10 higher than InP, 2 0 higher than GaAs and 100 higher than Silicon [1] In real world scenarios these d evices demonstrate good performance initially but start to degrade as soon as they are operated for prolonged duration. In fact, in many cases these devices degrade in a very short period of time This device technology is fairly new and processes are still not mature leading to low yields and pre matu re breakdown. In spite of this it is important to thorough ly investigate the mechanisms which cause degradation and affect not only short term but long term reliability as wel l. The motivation thus, becomes to understand failure mechanisms and the physics of device degradation in these III Nitride HEMTs which can be used to optimize device structure and develop process es to unleash the full potential of this technology In soli d state devices the primary cause of degradation is always in some way linked to generation and/or migration of defects in critical locations inside the device. Common MOSFET failure mechanisms like hot carrier injection (HCI), gate oxide

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12 breakdown (GOB) and negative bias temperature instability (NBTI) are typically associated with defect generation which changes threshold voltage, transconductance, series resistance etc. Defects can be characterized by techniques such as Pulsed I V, Charge pumping and DLT S Most of these methods require special test structures F or instance capacitances of the order of a few pico F arads are needed for an accurate capacitance based DLTS measurement. Large gate leakage currents can reduce the accuracy of impedance based measurements like charge pumping Most realistic devices have low gate capacitance due to small feature sizes and relatively high gate leakage currents. Low frequency noise (LFN) measurements can be performed on fully processed advanced sub micron devices Unlike other techniques low frequency noise measurements are the most benign way of performing defect spectroscopy. D efects which actually affect charge transport in the device show up in the noise spectra More precisely defects which are located within a fe w kTs around the Fermi level participate in noise generating process Traps which are far above the Fermi level are nearl y empty and the ones located far below the Fermi level are almost filled. Defect energies and their physical locations can be determined by scanning the Fermi level through the bandgap by changing the gate bias, drain bias and /or temperature. This enables a component defect level analysis by looking at noise from each of part of the system like interconnects, contacts, channel or the gate stack. L ow frequency noise is therefore a powerful defect spectroscopy tool for semiconductor devices particularly suit able for reliability studies A brief introduction to the theory of noise in electron devices is presented next

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13 Noise Mechanisms in Devices Electrical noise in semiconductor devices and materials has many physical origins. It is a steady state spontaneous fluctuation in either the electric current or voltage in the time domain measured at the contacts of a device. According to t he instantaneous current measured at the contact is given by the following relation, (1 1) Where N(t) is the number of carriers, v k (t) the instant carrier velocity, and L the contact spacing. In the frequency domain thes e fluctuations show up in the low and high frequency regimes depending on the type of mechanism. The fluctuations in the high frequency regime viz. shot noise and thermal noise are typically associated with instantaneous velocity fluctuation of charge carr iers and exhibit flat spectra. These noise sources are fundamental ly linked to the kinetic s of the electron gas Typically the short circuit thermal current noise spectral density is given by, (1 2 ) Where Re(Y) is the real part of the small signal AC admittance of the device k B is the Boltzmann constant and T N is the noise temperature At low biases the carriers are in thermal equilibrium with the lattice since the dominant scattering mechanism is nearly elastic with longi tudinal acoustic (LA) phonons. E nough scattering event s randomize the electron momentum or the electron velocity giving rise to velocity fluctuation noise. In this case T N equals the lattice temperature (T L ) which is typically the ambient temperature of the measurement environment. However, when higher electric fields are applied the carriers gain kinetic energy and are not in thermal equilibrium with the lattice. In polar semiconductors like the GaN the dominant scattering mechanis m at high

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14 fields is the polar optical phonon (POP) scattering. Hence the electrons loose energy by emitting l ongitudinal optical (LO) phonon s and in the process exchange both momentum and energy. When there are large numbers of carriers and electric fields are uniform in the device the electron momentum distribution function is fairly uniform and can be approximated by a Boltzmann function with an effective spread given by the electron temperature (T E ). In this case T N equals the hot electron temperature (T E ). Thus, by measuring high frequency noise temperatures in the device one can determine the nature of these hot electron processes quantified by the electron temperature profiles. In the low frequency part of the spectra the carrier number fluctuation dom inates. This component is very sensitiv e to the microscopic environment that the charge c There are three types of noise which form the low frequency spectra Generation Recombination (GR) noise is a fluctuation in the conduc tance due to trapping and de trapping of free carriers (electron or hole) between the continuum states and discrete local levels. A single trap level leads to a Lorentzian noise spectrum which has a characteristic frequency equal to the reciprocal effectiv e trapping time constant. GR noise underlies one of the well known methods of performing defect spectroscopy in modern devices [2] [3] Random telegraph switching (RTS) noise is a discrete two level switching of the conductance in the time domain. It is generally a single electron event often found in modern nano devices with a small number of free carriers. It is again a powerful spec troscopic tool since it provides information of both capture and emission time constants associated with the trap [4] [5]

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15 1/f noise is the most ubiquitous of noise sources but one of the least understood physically. Two competing models are used to explain the mechanism. The number proposes that elastic tunneling of channel carriers into the oxide layer at the Fermi level in the channel of a MOS structure produces an exponential distribution of time constants. Thi s leads to 1/f noise in the fluctuation s ). The random acoustic scattering events are said to produce this noise. Presently the most accepted model for MOS structures is the so ca lled correlated number mobility fluctuation [6] Although there is no consensus on the mechanism there is strong evidence of the process dependence of 1/f noise [7] The Hooge value is an excellent figure of merit for the crystallographic quality of the bul k material or inverted channel region. It has been known to have a strong correlation with the quality of the SiO 2 /Si interface [8] Organization This work is a comprehensive account of five investigations performed in a systematic way to unravel the gate stack and channel reliability by a combination of different DC and RF stresses. Chapter 2 shows the novel low frequency noise setup that w e developed to perform simultaneous defect spectroscopy of the gate stack and the channel region. It is used to demonstrate the instability that exists in the gate stack due to mobile point defect centers right under the gate metal. The channel i s found to be stable with only 1/f type i nterface defect noise dominating. In Chapter 3 the gate stack is probed in more detail. Inverse P iezo electric stress is invoked by a step stress experiment. Transient and p ermanent effects are separated. Transient effects are due

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16 to trapping and de trappi ng of carriers in the existing trap states in the AlGaN barrier New defect centers are created under the gate metal along with the activation of mobile point def ect centers. The c hannel was found to be immune to the whole stress regime. Very early stages of the gate stack degradation are well captured which point to defect creation and migration as a precursor to catastrophic gate breakdown In Chapter 4 the attention is turned to the channel region by applying a combination of gate and drain voltages to p robe hot carrier and self heating effects. Key region s in the bias range are identified where permanent degradation occurs in the channel due to an increase of AlGaN/GaN interface defect density. In Chapter 5 microwave electron temperature spectroscopy is used to understand the kinetics of the hot carrier effects which cause this degradation in the channel. From the electron energies it is found that hot carriers are fairly well confined in the AlGaN/GaN interface and are responsible for creating new interf ace defects. In Chapter 6 large signal RF reliability of GaN HEMTs is discussed by applying RF overdrive stress New defect centers are created in the gate stack at higher compression levels. Finally the a ctivation energy and the physical location of an un stable point defect center is extracted

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17 CHAPTER 2 NOISE SOURCES IN UNSTRESSED GAN HEMTS Motivation A large part of the current research effort in AlGaN/GaN HEMT reliability is concentrated on the poor gate contact and associated high leakage currents leading to problems such as drain current collapse, virtual gate effect etc [9] The gate leakage current has been shown to significantly enhance the drain noise in the AlGaN/GaN transistors and therefore, defect spectroscopy using drain noise alone becomes difficult [10] As a result an independent study of gate and drain noise simultaneously is s knowledge has not been performed till date. This chapter demonstrates a comprehensive experimental setup developed to perform these simultaneous measurements on drain and gate noise as a fun ction of respective bias ( Figure 2 1). The results of these measurements are used to identify individua l noise sources in the vertical and lateral regions of gate stack and channel, respectively. Devices under Study In reliability studies it is often important to differentiate between process induced defects from stress induced defects which are typically generated during device failure of the devices can be reduced by a more mature device process which gives high yielding devices. Therefore, this study is mainly focused on industrial grade fully processed advanced AlGaN/GaN HEMTs grown on Silicon substrate. The device under st udy ( Figure 2 2) consisted of an 800 nm GaN buffer layer grown on a high resistivity Si substrate by metal organic chemical vapor deposition (MOCVD). A transition layer of AlN is employed for stress mitigation. The buffer is semi insulating with the Fermi level

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18 in GaN at around E C 0.5eV. On top of this buffer an 18 nm of unintentionally doped (UID) Al 0.26 Ga 0.74 N barrier layer is grown by MOCVD and finally capped by 1.5 nm of Ga N. All the layers are undoped. d by depositing Ni/Au followed by a rapid thermal anneal (RTA). Ohmic contacts are created for drain and source regions by depositing Ti/Al followed by RTA. A SiN fingers corre spondi ng to a gate periphery of 2 mm. The setup for measuring the voltage drain noise uses a low noise voltage pre amplifier (SRS560) connected at the drain terminal and a drain bias resistor at least 10 times higher than the small signal channel resistanc e. The gate noise setup required a done with a gate bias resistor. The gate current noise gets ref lected to the drain noise via a voltage drop across the gate bias re sistor and is subsequently enhanced by transconductance in the linear regime. Therefore, an ultra low noise op amp AD797 was used to create an AC short circuit at the gate terminal and to convert gate current to voltage which in turn was amplified by a low noise voltage amplifier. Both these signals were simultaneously measured using the 2 channel Agilent 35670A spectrum analyzer as shown in Figure 2 1. It should be mentioned here that the main idea behind this approach is to create an AC short circuit at t he gate terminal thus, preventing any circuit induced fluctuation to show in the drain noise. Interestingly most AlGaN/GaN HEMTs currently suffer from the problem of high gate leakage current and therefore, even a single channel drain noise measurement wil l show noise features of gate current if the gate is not properly AC shorted. A time domain noise measurement of both the

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19 channels or a spectral correlation measurement can determine if this problem exists. Time domain random telegraph switching (RTS) nois e was measured using an Agilent HP4145B parameter analyser and was limited to gate and drain I V, and transconductance measurements. A C V characterization using HP 4275A was also performed for the gate to source drain diode to extract various device parameters of interest. DC Characterization The e ffective mobility of the channel was extracted from a combination of DC transconductance and CV profiling measurements. The mo bility of the FET in the linear regime was deduced using, ( 2 1 ) Where, L G W G are gate length and periphery respectively and R CH is the channel resistance. Sheet carrier densities were extracted from the C V characterization of the reverse bias gate to source drain diode at 100 kHz using, (2 2 ) Where V P is taken below the threshold voltage. The calculated mobility values were between 180 415 cm 2 /V s for sheet concentrations of 10 11 to 10 12 cm 2 and agreed well with results from other groups [11] It was found that the field effect mobility was a function of sheet carrier density which is also reported extensively [12] Here, the effect of source and drain access series resistance was neglected which needs to be taken into account to accurately extract the channel mobility

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20 Drain Current Noise The device under test was biased in a common source configuration at a co nstant low dra in to source voltage of 80 mV. Drain current noise measurement is conducted by sweeping the gate voltage from 1.32 V to 1.0 V at a constant V DS = 80mV. The gate sweep was always over threshold voltage V T 1.38 V. The FET was kept in the l inear regime and the resulting noise spectra were measured for the frequency range of 1 Hz to 51.2 kHz at 300K. The noise spectra were of the 1/f ~ 0.9 0.85 varying inversely with the gate overdrive voltage shown in inset of Figur e 2 2. No distinct generation recombination (GR) noise components could be seen. In the triode region, the channel consists of a gated part and un gated part of source, drain access regions. If the noises originating from these regions are assumed to be un correlated then the s hort circuited drain noise is, (2 3) Where S RCH S RS and S RD represent the uncorrelated resistance noise of the channel, source and drain access regions respectively. Only the channel noise is dependent on the gate bias and this feature is exploited to determine which term dominates in Eq. ( 2 3). Figure 2 3 shows a plot of normalized drain current versus gate overdrive voltage (V G V T ). Two distinct regions of S ID V G 1 and V G 3 dependence are observed in low and high gate voltage respectively. This is a clear indicator that only the gated part of the channel noise is the dominant source [13] Having determined the noise source, a Hooge parameter was calculated using the classical phenomenological equation,

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21 ( 2 4) As seen in Figure 2 4 the Hooge parameter associated with the gated part of the 3 to 10 4 and shows an inverse dependence with the sheet carrier concentration. These values indicate that the noise from the access regions is still lower indicating the maturing of ohmic contact technology in nitride based materials. Also the temporal stability of the noise indicates a good quality of AlGaN/GaN interface. H with the sheet carrier concentration has been attributed to number fluctuations of carriers by thermally assisted tunneling in and out of the GaN donor states [11] A temperature based measurement was not performed which is essential to verify this claim. Also, the effect of series resistance needs to be decoupled in the analysis. T he fr 1/V G dependence (see inset of Figure 2 2) is another indication of a number fluctuation phenomena. Band bending changes the trap distribution at the Fermi level thereby altering t he dynamics of carrier trapping and de trapping process [14 ] Gate Current Noise Gate current noise is measured simultaneously with the drain noise as a function of gate overdrive voltage at constant V DS of 80 mV. Therefore, the inverted channel exists for t he complete gate bias range of V G from 1.3 V to 1.0 V. In the DC case the gate metal semiconductor junction is reverse biased and vertical tunneling of electrons, Figure 2 5, is expected to be the dominant current leakage mechanism in this regime [15] Considering this, the electron transport is predominantly from gate to the channel region, and therefore the low frequency noise of the leakage current is directly probing the metal semiconductor contact quality and space charge region traps in the AlGaN

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22 ise sources in the device are uncorrelated, the compact noise model of the device can be constructed as shown in Figure 2 5. The gate current flows from drain to gate through the channel therefore, the short circuit current fluctuation measured at the gate terminal is, ( 2 5) Where, S rg S RCH and S RD represent the noise of gate, channel and drain regions respectively. Channel and drain resistances R CH D G 1.3V were determined from the differential transconductance characteristics of the FET. Differential gate resistance R G G 1.3V and V DS = 80 mV was determined from the reverse gate to source I V characteristics. Since R G >> (R CH + R D ) E q. ( 2 5) reduces to ( 2 6) This indicates that the gate noise originates mainly from the gate stack region and channel noise is negligible. 1/f N oise Gate current noise power spectra of the same device under identical bia s conditions but carried out at different time instances are shown in Figure 2 6. In each case the spectrum has the form of 1/f noise with a visible Lorentzian noise component on top of it. No high frequency roll off of noise was observed at any of the gate voltage in the measured frequency range of 1Hz to 51.2 kHz. As an indicator, the measured noise is at least 3 orders of magnitude higher than the shot noise (2qI G ) at 51.2 kHz,

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23 observed in the time domain which manifested as a Lorentzian component in the frequency domain. The nature of the Lorentzian noise component is discussed i n the next section. The 1/f noise component of S IG is extracted from the spectrum and plotted as function of gate direct current (I G ). A dependence of S IG proportional to square of I G is seen in Figure 2 7. This S IG I G 2 dependence is typical of a trap d ensity fluctuation in the space charge region of the Schottky junction [16] This 1/f noise component was found to be temporally stable and reproducible. Therefore it may be argued that the gate Schottky contact is of high quality and does not degrade at l east under normal bias conditions V DS < 0.1 V and V T < V G < 0. Also, since the absolute magnitude of the 1/f noise component remained the same the interface defect density does not change. RTS N oise As mentioned previously a non repeatable Lorentzian comp onent was observed in the gate noise spectra when measured at different time instants under identical biasing conditions. Inset in Figure 2 6 (c) and (d) show the measured RTS noise in the time domain. The corner frequencies and respective time constants a re different for both RTS. It was observed that repeating the same measurement at different time instances led to a change in the Lorentzian characteristic frequency (f C ) and magnitude. It region of the spectra and no specific trend in the frequency drift could be observed. On the contrary, the background 1/f noise in all those measurements remained stable and showed the same I G dependence. This non repeatable Lorentzian and a repeatable 1/f noise showed up in all the measurements. It is concluded that the gate fluctuation is actually a

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24 sum of uncorrelated 1/f and RTS noise sources. RTS noise in my measurements mainly consisted of discrete two level fluctuations. These f luctuating current states are a direct indicator of a single electron trapping and de trapping at a point defect center. The time an electron spends at the defect site determines the high and low current times. The dynamics of the process is governed by th e principle of detailed balance but since stati sti cal process it shows a P oisson distribution given by this relation, (2 7 ) I t was found that the measured high and low current times exhibited these Po isson distribution confirming that electron trapping and de trapping at point defect centers in the gate stack was responsible for the observed RTS noise. RTS noise is also observed in confined Si MOSFET channels when the defect is located at a strategic location inside the device whereby it can modulate the complete channel current for instance in the SiO 2 oxide region near the source side where electron injection takes place. Even a small change in the local potential due to electron trapping at that loc ation can signi fi cantly affect the channel current. In our device the gate leakage current shows large relative two level fluctuations. If the gate leakage current wa s due to a homogenous electron injection across the whole gate area (N fingers W G L G ) then it is very unlikely that a single electron would modulate the whole DC gate leakage current. This indicates that the DC gate leakage current mechanism in our device is physically localized whereby a single electron trapping and de trapping can electro statically modulate the whole leakage current if it is located very close to the leakage pathway. The other interesting result is that these RTS high and low current states show a different mean time constant when the same measurement is performed on diffe rent

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25 days. However d uring the noise measurements which typically last for an hour the time constants are stable and do not change showing only gate bias dependence This indicates that the defect center responsible for trapping and de trapping a single ele ctron is unstable and exhibits defect migration at room temperature in the time frame of a few days It is known that even in an unbiased device high electrical fields of the order of a few MV/cm are present in the AlGaN/GaN heterostructure due to spontane ous and piezoelectric polarization which are not present in silicon MOSFETs [17] These electric fields are further enhanced by the applied gate bias during device operation. Also it is known that the AlGaN barrier is mechanically strained on top of GaN buf fer and exhibits inverse piezo electric properties [18] Therefore, it can be easily proposed that an unstable defect center in AlGaN barrier layer can migrate under the influence of these factors or by a complex interplay of them like electric fi eld induced mechanical strain. On one of the days the defect can be physically very close to the localized region of DC gate current and it captures and emits an electron from the gate metal thereby modulat ing the complete current pathway and show s up as a RTS noise as seen in Figure 2 7 (c) and (d) On other days it can be physically away from the localized regions of DC gate current and when it captures and emits an electron it does not modulate the complete current pathway thereby showing only Lorentzian in the frequency domain as seen in Figure 2 7 (a) and (b) due to weaker electrostatic coupling with the gate leakage current It is widely reported that the dominant gate leakage mechanism in these devices is via dislocation spots [19] [20] [21] [22] often a defect center located close to these dislocations will enable electron trapping and de trapping which will modulate the current and create large

PAGE 26

26 relative RTS noise. In all other cases it will lead to a Lorentzian component in the noise spe ctra. It was observed that most times the RTS noise showed a relative large G /I G between 20% to 40%. If it is assumed that the defect center leakage pathway in that region, then a crude estimate of dislocation density can be extracted from the relative amplitude of the RTS noise. In this case, a dislocation density of less than 10 6 cm 2 is deduced which is being reported in current state of the art AlGaN/GaN H EMT devices [23] In summary t he gate noise analysis point s to two key effects that are observed in the gate stack There are localized regions of gate leakage current in the device possibly linked to threading dislocations and extended defects under the gate stack. Also there are unstable point defect centers under the gate stack which show room temperature defect migration in the time frame of a few days In the next chapter I study the effect of systematic reverse gate voltage step stress which stresse s the gate stack with high electric fields and mechanical strain via the inverse piezo electric effect.

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27 Figure 2 1 Experimental setup for low frequency noise characterization. An ultra low noise Op Amp (AD797) is employed as an I V converter for gate current noise. Two SRS560 low noise voltage amplifiers are used to amplify gate and drain noise.

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28 Figure 2 2 Device cross section of GaN HEMTs used in this study

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29 F igure 2 3 Normalized drain current noise (S ID /I D 2 ) as a function of increasing (indicated by arrow) gate bias (V G ) of 1.32V to 1.01V at V DS = 80 mV. noise varies from 0.9 to 0.85 as a function of increasing gate bias. Inset show function of gate overdrive voltage (V G V T ). The solid line is a theoretical best fit.

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30 F igure 2 4 Normalized drain current noise (S ID /I D 2 ) at 200 Hz as a function of gate overdrive voltage V G V T Solid lines are V G 1 and V G 3 fits on the measured data points for 0 < V G overdrive < 0.1 and V G overdrive > 0.1 respectively. F igure 2 5 H on the sheet carrier concentration n s (cm 2 ). Solid line is a theoretical best fit for the me asured data points; it shows 1/n s dependence.

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31 Figure 2 6 Compact model of noise sources in the channel (S IRS, S IRCH S IRD ) and gate region (S IRG ) of the device. The dashed line indicates the channel region at the AlGaN/GaN interface. The dotted line i ndicates the electron current leakage path for strong inversion and low drain bias.

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32 Figure 2 7 Gate current noise spectra as a function of decreasing (indicated by arrow) gate bias (V G ) of 1. 01 V to 1. 32 V and V DS = 80 mV measured at four different time instances. A Lorentzian noise component without a time RTS noise is seen in (a) and (b). The insets in (c) and (d) show the corresponding RTS noise. The characteristic frequencies of all Lorentzians are different.

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33 CHAPTER 3 HIGH GATE ELECTRIC F IELD STRESS EXPERIME NT Motivation Many prominent degradation mechanisms have been identified in GaN HEMTs by various groups which cause temporary and permanent changes in the electronic and material structure of the de vice [24 26] Figure 3 1 shows a classification of these mechanisms in these devices as a function of physical effect. Except polarization most of these effects have been well studied in other III V HEMTs and are relevant for nitride tra nsistors as well. Lattice mismatch induced strain in the AlGaN barrier via inverse piezoelectric effect has been identified as one of key cause of degradation at high electric fields under the gate stack [18] RF devices experience high gate reverse bias important to probe this effect in more detail. Low frequency noise is known to be an extremely sensitive tool for studying reliability and changes in e lectronic structure due to degradation [27] [28] A few reliability studies have been performed in these devices using drain current noise to understand changes in the channel region [29 32] Most of these groups have concluded that off This work on the other hand reveals t hat interesting things are happening right below To gain a detailed understanding, a simultaneous measurement of gate and drain current noise is necessary to isolate deg radation in the gate stack and/or the heterostructure interface [33] This work demonstrates the results of DC and low frequency noise characterization of gate and drain currents in AlGaN/GaN HEMTs

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34 which were stressed to high reverse gate biases with source and drain connected to ground. Noise and IV measurements were performed during and after stress in both frequency and time dom ain. Temporary and permanent changes in the electronic structure of the device are delineated and physical locations of degradation are identified. Device Description and Experimental Details The devices under test are the same used in the previous study. T he devices are fully packaged to avoid any ambient optical instability to affect electrical measurements. A fully automated characterization suite is developed for performing stress, DC and noise measurements. A semic onductor parameter analyzer HP4145B is configured for performing both electrical stress and IV measurements. Figure 3 2 shows the stress protocol and time instances when a measurement is performed. The gate is stressed by applying a stepped reverse bias fr om 5 to 20V with 5V increment for 10 minutes each. After each cycle, stress is stopped and DC transconductance, drain and gate current noise are measured. Both drain and gate DC currents are measured at low V DS of 80 mV. Low frequency noise of gate and drain currents is measured at a constant V DS and V GS of 80 mV and 1.23 V, respec tively, using a setup which was demonstrated in the last chapter As will be shown later, threshold voltage itself changed during stress and the chosen value of gate voltage for measuring noise was found to be appropriate for keeping the device in strong inversion. It should be mentioned here that DC and noise measurem ents were carried out also several weeks after the stress was applied which was useful for isolating transient trapping and de trapping effects from permanent changes in the device electrical properties.

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35 Stress Characterization Results DC Characterization The focus of this work was to understand changes in the low frequency noise characteristics of the device which undergoes systematically applied electrical stress. Therefore, the DC parameters which were monitored during the stress were mainly chosen for convenience to extract the relevant noise p arameters The noise measurements were conducted at low drain current and voltage levels which were significantly smaller than the stress conditions making the measurements electrically benign so as not to alter t he device characteristics. The inset in Figure 3 3 (a) shows the measured drain current transfer characteristics before and after stress respectively. A large positive shift can be seen in the threshold voltage which forces a drift in the transfer characte ristics. The peak value of the transconductance (gm) was found to be constant with an overall positive voltage shift before and after stress indicating that no major changes took place in the channel region. As mentioned earlier DC characterization was als o carried out several weeks after the stress was removed to isolate transient trapping de trapping effects. Figure 3 3 (a) and (b) show the changes in the threshold voltage of the device during and after stress respectively. It can be clearly seen that a l arge positive V T shift is induced during stress changing it from 1.36 V to 1.17 V in a span of 40 minutes. This recovers back to pre stress levels several days later. In subsequent sections it will be seen that drain current noise also changes in accorda nce with this large V T shift due to a change in sheet carrier concentration in the channel. Gate leakage current was also measured simultaneously with drain current in the transfer characteristics. Figure 3 4 shows the evolution of gate leakage current

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36 dur ing stress. It shows a constant decline and exhibits large relative fluctuations contributing to large gate current noise in the frequency domain. Drain Current Noise Characterization Drain current noise is very sensitive to the defect states affecting ch arge transport in the channel and access regions making it an excellent indicator of the channel quality. Normalized drain current noise was measured as a function of gate bias to identify the dominant noise sources from different parts of the channel. It was found that the gated part of the channel was the main source of drain current noise as found previously in unstressed devices A DC gate voltage of 1.23 V was chosen for noise measurement since both channel noise and resistance dominate in that region Figure 3 5 shows the drain current noise before and after stress at the same DC bias level. An increase by a factor of 4 is visible in the spectra. It was observed that this increase was temporary and the noise recovered completely to its pre stress leve ls a few weeks later. A Hooge equation of the normalized drain current noise can be written as, ( 3 1) Where, S RCH R CH and A CH represent the resistance noise, resistance of the gated part of the channel and area of the channel respectively. In the triode region at low drain voltages, the sheet carrier concentration in the channel (N CH ) is directly proportional to the gate overdrive voltage given by, ( 3 2) Where C AlGaN is the capacitance per unit ar H remains the same and noise is measured at a constant V GS A change of V T of around

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37 0.2 V causes a change of the channel carriers which in turn changes S ID /I D 2 by a factor of around 4. This explains the noted shift in the drain current noise both during and after stress. Therefore, it can be concluded that the channel is immune to any degradation due to high gate reverse biases. Gate Current Noise Characterization Figure 3 6 shows the pre and post stress normalized gate current power spectra. An increase by a factor of 10 is seen in the spectra. On the other hand the DC gate leakage current measured at V GS = 1.23 V increased only by a factor of 2. Initially it seemed that this was analogous to the drain noise increase wh ich would recover once the stress was removed. It was found that this increase was permanent and no recovery could be obtained even several weeks later. Furthermore, it showed a temporal instability with Lorentzians shifting positions in the frequency doma in. Two level switching was also observed in the time domain with varying characteristic times. This phenomenon was observed in a previous work and was linked to an electrical activation of mobile defect centers In order to get a better understanding of t hese changes a low temperature noise measurement was performed to reduce the temporal instability of the Lorentzians. The device was cooled to 77K and noise was measured. Interestingly, in the triode region at V DS = 80 mV a 1/f type spectra was obtained b ut when the device was biased in saturation at V DS = 2 V a large Lorentzian emerged in the gate noise spectra ( Figure 3 7). This same behavior was seen when the source and drain were swapped. Discussion In this part a critical analysis of the physical ori gins of the results is performed. The results suggest that two dominant mechanisms are at play. First are the transient effects

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38 due to existing defects which affect DC device characteristics and drain current noise. Second are the permanent changes in the material structure which changes the gate current noise in a significant way. Earlier it was shown that threshold voltage shifted positively during stress and later recovered to pre stress levels. The threshold voltage is typically determined by the gate m etal semiconductor barrier height, band discontinuity at AlGaN/GaN interface, polarization charges and fixed defect states in the barrier [34] It was found that forward biasing of the gate to source drain diode led to a faster recovery of t hreshold voltage to pre stress levels. Studies performed on similar devices (GaN on Si) by other groups have shown that threshold voltage also recovers by optical excitation via UV light illumination with a frequency comparable to the band gap of the barri er [35] The band discontinuity and polarization charges would be invariant to both optical excitation and forward biasing of the gate to channel diode. Furthermore, a change in these parameters during stress would be permanent in nature and would be irreversible unlike what was observed. Therefore, it can be assumed that threshold voltage shift is due to the charging and discharging of fixed defect states in the AlGaN umed that a fixed sheet charge is located in the AlGaN barrier near the channel, (3 3) A positive shift of 0.2 V corresponds to an effective trap density (N T ) of 5 x 10 11 cm 2 This value is smaller than the typical polarization charges at the interfaces [36] It has been shown that in AlGaN/GaN HEMTs at high reverse gate voltages (V GS << V T ) the electrons predominantly tunnel from the gate edges [36 ] Some of these electrons

PAGE 39

39 can get trapped in the existing defect states in the AlGaN layer which will cause an increase of the threshold voltage. This is shown in process P2 in Figure 3 8. This event will also lead to a change in the potential profile in the AlGaN barrier. Charged defect states decrease the band bending which in turn increases the barrier width as seen by the tunneling electrons from the gate metal. The tunneling probability of electrons will thereby decrease resulting in reduced gate l eakage current. Both these effects were visible in the measurement results. When the stress is removed the trapped electrons beneath the gate slowly de trap which leads to a recovery of the threshold voltage. Shown in process P1 in Figure 3 8. Gate current noise results demonstrated that a permanent change took place in the environment seen by the electrons tunneling from gate to semiconductor. In a previous work it was noted that 1/f component of the spectra is due to the trap state fluctuation at the met al semiconductor Schottky interface [33] Since it increased by a factor of 10 it can be concluded that near interface defect de nsity increased at the metal semiconductor junction and additional trap states were created. Low temperature measurements pointed out that when the device was biased at V DS = 2V where the DC drain current was saturated, the gate noise increased dramaticall y. The same measurement was performed when source and drain terminals were swapped and a similar increase was observed. In the former experiment the vertical fields at the gate drain edge become larger than fields at the center. In the latter case, the ver tical fields at the gate source edge become larger than fields at the center. This leads to an increase in tunneling probability at the edges and more electrons at the Fermi level of the metal can access the trap states in the AlGaN leading to discrete swi tching noise. It is proposed that during stress new trap states were generated in the

PAGE 40

40 AlGaN barrier beneath both the gate edges which are most probably located above the metal Fermi level. Although it has been shown that inverse piezoelectric breakdown not only degrades the AlGaN barrier but also the channel region in the GaN buffer [18] The results presented in this work do show degradation of the AlGaN barrier but not the channel. This could be due to relatively low stress voltages used in this work and/or a smearing down of peak electric field due to source field plate. Also the degradation is wn. This demonstrates that low frequency noise is an insightful tool to predict early degradation at relatively low stress levels which eventually leads to large performance degradation at higher voltages. This large degradation not only affects noise but also change the DC characteristics drastically.

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41 Figure 3 1. Illustration of prominent failure mechanisms in AlGaN/GaN HEMTs as a function of physical effects. This work limits its study to the electric field driven state

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42 F igure 3 2 Reverse g ate voltage step stress protocol. The solid line indicates the step voltage stress from 5V to 20V applied to the gate terminal wher e source and drain are connected to ground (Biasing shown in the inset). The measurements are performed at the end of the 10 min stress period (indicated by dashed line) by measuring I DS I GS v/s V GS drain current noise and gate current noise.

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43 F igure 3 3 Threshold voltage changes during and after stress. Top figure (a) shows the increase of threshold voltage during stress. The inset in (a) depicts the pre and post stress drain current transfer (I DS V GS ) characteristics at V DS =80 mV. The slow threshold voltage recovery is shown in bottom figure (b).

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44 F igure 3 4 The evolution of the gate leakage current measured at V DS = 80 mV during stress is shown at each stress step. An overall decrease is seen (indicated by the arrow) as stress is increased.

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45 F igure 3 5 Normalized drain current spectra (S ID /I D 2 ) for pre and post stress cases. An increase by a factor of 4 is seen indicated by the arrow. This increase was found to temporary and it fully recovered to its pre stress levels a few weeks later as th e DC threshold voltage recovered.

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46 F igure 3 6 Normalized gate current noise (S IG /I G 2 ) for pre and post stress cases. An increase by a factor of 10 can be seen (indicated by the arrow). This shift was found to be permanent and did not recover.

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47 F igure 3 7 Gate current noise (S IG ) measured at 77 K for two DC biasing in triode region and saturation. A drastic increase of noise is seen in saturation with a distinct Lorentzian at a corner frequency of 30 Hz.

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48 F igure 3 8 Conduction band diagram of the cross section at the gate drain edge (shown in the device structure on the right). Electrons tunneling in and out (shown in solid arrows) contribute to the increased DC gate leakage current and gate current noise. New trap states are created (indicated by dashed circle) in the AlGaN barrier which are above the metal Fermi level (E F M ). P1 (dash dot arrow) shows the de trapping of electrons from the existing traps which contribute to recovery of threshold voltage after stress. P2 (dotted arrow) shows the tr apping of electrons which tunnel from the gate terminal during stress. They lead to an increase of the threshold voltage.

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49 CHAPTER 4 HIGH CHANNEL ELECTRI C FIELD STRESS EXPER IMENT Motivation In the previous chapter it was reported that the channel is stable and does not degrade under high gate electric field stress. Now the focus is on the channel. A set of different stress conditions were applied to the device to isolate physical mechanisms viz. hot carrier injection (HCI), inverse piezo electric effect, self heating effect and a combination of self heating and HCI. The focus of this study has been limited to only short term stresses. In each case the noise was measured before and after stress respectively. A low bias (V DS =80 mV) transconductance measurement was also performed during and after stress. Experimental Setup and Results Experimental Setu p and Stress Methodology The devices used for this study have the same structure as the ones that were used in previous experiments. An experimental setup was developed to perform automated electrical stressing, DC I V characterization and drain and gate c urrent LFN characterization (see Figure 4 1) using the Agilent VEE instrument control program An Agilent E5252A is used to switch between a high power power supply unit (PSU) and a parameter analyser. For DC characterisation, transconductance I D V GS and I G V GS were monitored. This was measured in the triode region at a low V DS =80 mV. LFN measurements were also performed in the triode regime of the HEMT via a 2 channel Agilent 35670A. The noise measurement setup is same as shown in chapter 2. The DC bias vo ltages were chosen in such a way that during noise measurements low currents

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50 (I D <25 mA) and low voltages (V DS =80 mV) are present in the device. Thus, the measurements were from a stress point of view electrically benign and non destructive. Four different types of stress conditions were applied to the devices which are mapped to the typical I D V DS load line DC biasing shown in Figure 4 2. The four points invoke a combination of physical failure mechanisms like high self heating (P D =I D V DS ), hot carrier injection (E CH ~V DS ) and inverse piezoelectric effect. The four points can be expressed as four quadrants starting anti clockwise from the top right. Quadrant I: V DS = 20 V at V GS = 1.7 V, I DS = 0.115 A/mm for 5 minutes. The device is stressed at constant voltage and channel current is monitored during stress. Quadrant II: V DS = 2 V at V GS = 2 V, I DS = 0.2875A/mm for 30 minutes. Again, constant voltage is applied. Quadrant III: V DS = 0 V at V GS = 0 to 20V ( 5 V increment), 10 minutes each step. Here, the constant voltage is stepped after 10 minutes of stressing. Quadrant IV: V DS = 10 to 30 V (5 V increment) at V GS = 4 V. The channel current (I DS ) at 30V stress was ~ 15 A/mm.. Here again, constant voltage is stepped after 20 minutes of stress. Figure 4 2 shows also the key changes in LFN in either drain or gate currents for each quadrant. Also shown is the corresponding change in the transconductance of the device in the triode region. Results and Discussion The results indicate that there are two mecha nisms at play. One is a transient effect like a threshold voltage shift due to electron trapping at deep levels in the AlGaN barrier layer during stress and de trapping subsequently. Second is a permanent change due to trap creation and/or migration which may lead to effects like permanent

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51 degradation of the low field mobility and gate leakage currents. To isolate these phenomena, noise and DC measurements were carried up to several weeks after the stress procedures outlined above. Quadrant I test conditio ns were equivalent to a high self heating and hot carrier injection environment for the device. It was observed that the drain current noise drastically degraded after the stress by almost one order of magnitude. This also resulted in a factor of two reduc tion in peak transconductance in the linear region. Both these changes were found to be permanent and did not show any recovery. It is interesting to point out here that right after stress, there was a positive shift in the threshold voltage of the device which later recovered to the pre stress level. Therefore, this V T shift was found to be a transient effect due to electron trapping and subsequently detrapping in existing trap states in the AlGaN barrier layer. By measuring channel noise as a function of gate bias it was determined that this degradation occurred in the gated part of the channel ( Figure 4 3). A Hooge parameter was calculated using the classical phenomenological equation, (4 1) Here, I D is the DC drain current at a gate bias of 1.3 V where the noise measurement is also performed It is important to point out here that the DC channel current also decreased after stress. This effect is instrinsically cancel led out since the Hooge parameter is dependent on the dra in current normalized channel noise spectral density ( / ) and therefore, it is an indicator of the AlGaN/GaN channel interface trap density. The number of electrons in the channel (N) was determined by measuring t he C V characteristics of the ga te to H = 1.5 10

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52 2 is calculated which is higher than the pre H of ~ 10 3 indicating a 15 increase of trap density at the AlGaN/GaN interface The gate current noise did not show any major changes in this regime. It is interesting to observe that such a large degradation can occur at such short duration. Most HCI related degradation mechanisms in these devices have shown relatively long time ra tes viz. few hours [37] Therefore, hot carriers alone cannot lead to this large degradation. The role of localized temperature increase leading to defect diffusion cannot be ruled out. More insights into these mechanisms are probed in the n ext chapter Quadrant II test conditions were predominantly self heating effects and the drain noise characteristics showed a slight decrease due to the threshold voltage decrease. This later recovered to pre stress levels when the threshold voltage reco vered. It was concluded that no permanent degradation took place during this condition. The channel temperature is fairly uniform in this regime thus; most of the heat is spread out uniformly in the channel. It is therefore, not surprising that self heatin g alone does not cause any degradation. Quadrant III is a situation where only the gate stack was stressed since the source and drain are grounded. This is the same experiment that was performed in chapter 3. The final quadrant (IV) stresses the device i n the hot carrier regime without self heating. Threshold voltage shifts occurred during stress but no net shift occurred after stress. Both drain and gate noise characteristics did not show any post stress change. Again no permanent degradation occurred in this regime. It seems that not enough hot carriers were generated i n the channel to cause changes.

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53 Fig ure 4 1. Experimental setup for performing electrical stress and LFN characterization. The thick solid black lines show the GPIB connection to the computer. Thin solid lines show the electrical connections between instruments. Dashed arrow lines show the device connection to either noise setup (Agilent 35670A) or stress/I V setup via a swit ch matrix (Agilent E5252A).

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54 Fig ure 4 2 Summary map of stress effects. Quadrants I, II and IV show pre and post stress normalized drain noise spectra (S ID /I D 2 ) in blue and red lines respectively. The insets in quadrant I and II are the transconductance and I D V G in the linear region for pre and post stress (blue and red lines respectively). Quadrant III shows normalized gate noise spectra (S IG /I G 2 ) before and after stress.

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55 Fig ure 4 3 Normalized drain current noise as a function of gate overdrive voltage. Square dots are the measured values. Solid and dashed lines are the V G 1 and V G 3 fits respectively. This dependence is a clear indicator of noise originating from the gated channel [33]

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56 CHAPTER 5 HOT CARRIER EFFECTS AND NOISE TEMPERATURE SPECTROS COPY Motivation Earlier i t was found that in the channel region, the combined effect of self heating and hot carrier stress creates a permanent increase of the defect density at the AlGaN/GaN interface. Also it has been recently pointed out that this regime of operation becomes im portant at higher RF power levels for a device biased in the power amplifier mode [38] High frequency noise measurements are known to give physical insights into hot carrier and self heating effects [39] [40] but very few studies have been performed on gated devices under realistic bias conditions. This chapter shows the results of using both low frequency and high frequency noise as a spectroscopic tool to study device degradation and failure mechanisms at typical bias regimes in actual devices. Experimental Details Figure 5 1 shows the experimental setup to measure the high frequency device noise which is based on the circulator method developed by Gasquet [41] The noise was measured at 2.20 GHz beyond the spectral range where the 1/f like noise observed at low frequencies has a contribution. The dev ice is biased at a typical class AB mode of operation with the gate voltage greater than the threshold voltage to induce a channel at a constant drain bias. The measurements were not performed under pulsed condition thereby allowing the lattice temperature to reach steady state at each bias. The gate terminal was AC open circuited with the help of a tuner to minimize the impact of both induced gate noise and thermal noise associated with gate resistance on the channel noise. It was found that at high drain biases the drain noise mainly stemmed from the channel electrons since the transconductance of the device was relatively constant

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57 while the measured device noise temperature increased with bias. The low frequency noise was measured by the same setup shown in chapter 2 Results and Discussion Figure 5 2 shows the effect of various bias points of the I D V DS load line on degradation in the channel and the gate stack. This work concentrates on the channel region and two important failure mechanisms based on self heating and hot carrier are explored in more detail. The methodology that is adopted here is to sys tematically probe each region of the load line by increasing gate and drain bias. Increasing the gate bias at a constant drain voltage will increase only the self heating effect by allowing more carriers in the channel thereby changing the lattice temperat ure via increased phonon scattering. On the other hand, increasing the drain bias at a constant gate voltage will increase the channel electric field and result in an increased electron temperature. Figure 5 3 shows the measured noise temperature of the ch annel at 2.20 GHz for three different gate biases as a function of drain voltage ranging from the triode to the saturation regime. Although a precise quantitative relation between the channel electron temperature and the measured noise temperature is lacki ng at this time, qualitative trends can be readily seen in the measurements. Figure 5 4 shows the effects of self heating and channel voltage on the measured noise temperature in the saturation regime of device operation. The effect of power dissipation wa s measured by keeping the drain voltage constant at 22V and changing the gate bias from 1.2 V to 1.0 V which resulted in a drain current change from 50 mA to 100 mA. To observe the effect of drain voltage on device noise temperature the drain voltage was varied between 10 and 22V at a constant gate bias of 1.1V. The noise temperature shows a strong correlation to the channel electric field as opposed to the power dissipation. For an increase of 100% in

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58 the drain voltage at V GS = 1.1 V, the noise temperat ure increases by ~ 70% indicating that it is correlated to the hot electron temperature of the channel. On the other hand, a similar increase in the power dissipation (P D =I D x V D ) in the channel raises the noise temperature by only ~ 20%. Now that a correl ation between noise temperature and channel hot electron temperature has been established one can understand the physical mechanisms at play which cause the dramatic degradation of LFN characteristics at high drain current and voltage as shown in Figure 5 2. At high drain voltage and low channel current it was observed that no permanent degradation occurs in the channel region. Noise temperature measured in this regime pointed out that hot carriers do indeed exist and show a correlati on to the channel electric field. Thus, it can be concluded that hot drain bias and currents exist in the channel, the LFN shows a permanent degradation. The Hooge parameter i ncreased 15 times from its pre stress value. In this regime, the Joule heating in the channel is significantly higher. Therefore, it can be inferred that the observed degradation in the LFN characteristics at high drain bias and current is linked more clos ely to the self heating effect which enhances the rate of degradation at the interface than the hot electron effect alone. This has also been pointed out by other groups [9]. These results point to the role of thermally activated degradation processes in t he high power regime.

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59 Figure 5 1 Device noise temperature measurement system. DC bias is applied via a parameter analyser and a high power PSU. The gate is kept AC open with the help of a tuner. The drain noise at 2.20 GHz is measured as a function of drain bias at three different gate biases.

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60 Figure 5 2 I D V DS map showing the e ffect of hot carrier and self heating. The measured low frequency noise characteristics are shown for pre and post stressed GaN HEMTs at different stress bias points [42] The channel is stressed with hot carrier and self heating stress by varying drain or gate bias, respectivel y, keeping the other variable constant.

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61 Figure 5 3 The channel noise temperature measured at 2.20 GHz as a function of measured at V GS = GS = 1. 1V and GS = 1.0V. Figure 5 4 The relative sensitivities of device noise temperature to a change in power dissipation (squares) and drain voltage (circles) are shown. The channel noise temperature is more strongly correla ted to the drain voltage than to power dissipation.

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62 CHAPTER 6 RF RELIABILITY OF GA N HEMTS Motivation As device designs are optimized for achieving higher RF power levels there is an increased need to assess their long term reliability in actual oper ating conditions. DC stress tests are typically performed to determine RF reliability but this approach has its own challenges For instance some of the failure mechanisms which are active under DC stress may not be the same under RF operation [3 8] But the relative simplicity of the tests renders them useful. A better experiment is the RF operating life time test which is performed to extrapolate RF reliability of the device. But high temperatures used in the stress accelerate thermally activa ted processes more than the electric field driven processes [43] In this regards one practical test than can be performed readily and mimics RF failure mechanisms more closely is the RF overdrive stress. Power amplifiers are typically biased for higher g ain saturation to optimize both efficiency and output power [44] Also, since these devices are biased at the edge of gain compression levels, a slight change (transient or permanent) in the device characteristics can lead to impedance mism atch and thus, drive the device into higher gain compression levels or generate spurious device oscillations. This type of stress not only enables a study of RF failure mechanisms but can also give insights into the limits of the device to withstand high R F power levels [45] T his work uses low frequency noise measurements as a reliability characterization tool to systematically probe microscopic degradation in the electronic structure of the gate stack and the channel region under high RF overdrive conditi on. Although similar studies have been done on GaAs devices, very few studies exist on GaN HEMTs [46] [47] [38]

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63 Experimental Details Experimental Setup and Stress Methodology A semi automated experimental setup is develope d to perform RF stressing, DC characterization and low frequency noise (LFN) measurements ( Figure 6 1). A circulator is utilized on the RF generator side to measure reflected power from the gate terminal. It gives the ability to monitor changes in the powe r gain of the device during stress due to variation in the input impedance due to possible trapping or self heating effects. An Agilent 35670A spectrum analyzer is used to simultaneously measure gate and drain current LFN. The details of the noise setup ar e in chapter 2 The complete setup is computer controlled via Agilent VEE. The device was biased in a class AB mode of operation at V DS = 28 V and I DQ = 25 mA/mm. The static DC power dissipation in the device was significant, with package temperatures reac hing 65 C during operation. A channel temperature of 100 C was determined based on a thermal resistance of 23 C/W which is a reasonable approximation for this device. The device test fixture was kept at the ambient temperature of 25 C throughout the st ress duration. RF power gain of the device was characterized before stress to determine the 3 dB and 8 dB gain compression points ( Figure 6 2). A small signal linear gain of 13 dB was measured at 3 GHz. At 3 dB compression the input power is around 6 dBm and at 8 dB compression the input power is around 18 dBm. The source and load impedances were initially tuned for maximum gain in the linear regime and then kept fixed for the duration of the stress. RF stress at 3 dB and 8 dB gain compression at 3 GHz wa s applied for 60 minutes ( Figure 6 3). The device was left to stabilize for few minutes to reach thermal quasi equilibrium then the input RF power (P IN ), output RF power (P OUT ) and quiescent drain

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64 current (I DQ ) were monitored as a function of time. Before stress application, a complete set of DC and LFN characteristics of the gate and channel were measured. It is important to point out here that RF stress with no gain compression was also performed and it was found that no degradation of the output RF power (P OUT ) occurred. The DC characteristics V T g m and gate leakage current did not change. Gate and channel noise chara cteristics were also unchanged. Only higher levels of gain compressions resulted in degradation of device characteristics. After stress, DC characteristics like threshold voltage, gate leakage current, transconductance and Gate and Drain current LFN were measured repeatedly for several weeks to differentiate between temporary and permanent effects. Experimental Results Figure 6 3 shows the ch ange of RF output power during stress of 1 hour for 3 dB and 8 dB compression. Despite that these are very short term stresses they result in significant reduction in power levels. Therefore, a systematic study of degradation can give new insights into the se failure mechanisms. A significant (~ 1.5 dB) power loss takes places in the first 10 minutes of stress for high gain compression of 8 dB and thereafter the power remains relatively steady. On the other hand a 3 dB gain compression stress causes much les s degradation which almost recovers to pre stress levels in 60 minutes. It should be mentioned here that the measured RF power gain followed similar trends since the input power did not change much during stress. Figure 6 4 shows the DC I V characteristics of the gate before and after stress. DC gate leakage current degraded significantly after stress. In the reverse bias the gate leakage current increased 10 times for 8 dB compression and 2.5 times for 3 dB compression RF stress. Figure 6 5 shows the transconductance of the device before and after 8 dB

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65 compression stress. The peak transconductance does not change. However, there is a negative threshold voltage shift which was found to be permanent. After 3 dB compression stress the channel characteristics (not shown here) remained the same without a change in peak transconductance and threshold voltage. The microscopic origin of the degradation was studied via gate and channel current LFN measurements. Figure 6 6 shows the evolution of the r elative channel noise before and after 8 dB compression stress. The quantitative decrease of the noise agrees well with the threshold voltage shift. For the 3 dB compression stress (not shown here) the relative channel noise magnitude remains the same. The Hooge parameter ( H ) was found to be ~ 10 3 for both stress conditions. This is also a common value for unstressed GaN HEMTs [48] Figure 6 7 shows the relative gate noise characteristics of the device after 3 dB compression stress. It can be seen that po st 3 dB compression stress the gate 1/f noise increases slightly but also induces temporally unstable Lorentzians indicated in the figure by the dashed ellipsoids. These Lorentzians sometimes also manifested as random telegraph switching (RTS) noise in the time domain. RTS noise is a powerful tool to study single defects [5] [4 9] During one of the measurements a stable RTS was found which lasted for several hours before it disappeared. RTS noise measurements were performed as a function of gate voltage to extract mean up and down time constants from the Poissonian statistics given by, ( 6 1) Where up/down is the mean up/down time constant. Figure 6 8 shows the extracted up and down time constants as a function of gate voltage. It can be seen that one of

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66 these time constants labelled as the capture time is exponentially dependent on the gate voltage whereas the other time constant is not. The details of the mechanism are explained in the next section where the trap characteristics are determined by analyzi ng this data. Figure 6 9 shows the gate noise characteristics before and after 8 dB compression stress. It can be observed that the 1/f noise increases drastically after stress. Furthermore, no distinct Lorentzian components are visible in the spectra afte r 8 dB compression stress unlike the 3 dB compression stress which resulted in temporally unstable Lorentzians. Discussion and Model Channel Noise Analysis It is clear from the channel noise characteristics that microscopic degradation does not occur in the channel region of the device. After the 3 dB compression stress there is no net change in the relative channel noise characteristics and its 1/f type characteristic is intact. However, for 8 dB compression stress a net decrease of channel noise occurs which was found to be permanent. This was explained by the threshold voltage shift which became more negative after stress as pointed out earlier. The Hooge parameter ( H ) remained unchanged after both stresses confirming the immunity of channel region to the applied RF stress at the microscopic level. Gate Noise Analysis Gate leakage current, gate noise and relative gate noise increased after 8 dB compression stress. 1/f noise is typically linked to interface trap states close to the gate metal/semiconduc tor interface [46] [42] A permanent increase of 1/f noise indicates that trap density near this interface increased and new defect states were generated during stress. The exact mechanism of DC gate leakage current in GaN HEMTs is still

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67 unclear. There is however a consensus that trap states in the AlGaN barrier are responsible for high leakage currents [15] [50] Therefore, one can conclude that the trap density indeed increased at the interface which explains the gate noise increase. One more interestin g aspect of the study was the activation of temporally unstable Lorentzians which gave RTS noise in the time domain after 3 dB compression stress ( Figure 6 8 ) It is known that a 2 level switching RTS is a single electron event with a single defect partici pating in the process [5] .The large observed relative gate current fluctuations point to a localized nature of gate leakage current. So instead of all the 10 fingers equally participating in the DC gate leakage current only 1 or 2 fingers participate. Furthermore, one can extract the physical location of this defect along the gate to channel direction by studying its gate bias dependence. For a single defect the principle of detailed balance requires, ( 6 2) Where E T i s the trap energy level, E F is the Fermi energy level, k B is the Boltzmann constant, g is the trap degeneracy and T is the temperature. Figure 6 10 shows the 1 D energy conduction band diagram along gate to GaN buffer simulated using a self consistent Pois son Schrodinger solver [51] Analytically E T E F can be evaluated from the band diagram, ( 6 3) W here B is the metal/semiconductor Schottky barrier height, k 1 V G is the electric field component in the GaN capping layer resulting from applying V G E PGaN is the electric field in the GaN capping layer due to spontaneous polarization, E C is the conduction band discontinuity between GaN capping and AlGaN barrier, x T i s the

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68 distance of the trap location along the gate to GaN buffer direction from the GaN capping/AlGaN barrier interface, k 2 V G is the electric field component in the AlGaN barrier layer resulting from applying V G and E PAlGaN is the electric field in the AlGaN barrier layer due to net spontaneous and piezoelectric polarization. Assuming g = 1 and differentiating eq. 3 with respect to the gate voltage, ( 6 4) Is the slope which gives the location of the defect (x T ) and the intercept of E q. (6 3 ) gives the energy of the defect (E C E T ) if the values of k 1 k 2 B E C E PGaN E PAlGaN are known. Figure 6 11 shows the measured RTS data and simulated C / E from the band diagram. An excellent agreement between the measured and simulated values is obtained for a trap located 4.5 nm from the metal/semiconductor interface and 0.9 eV below the conduction band edge of the AlGaN barrier. The experimentally measured RTS time constants wer e the mean values of more than hundred up and down current transitions, therefore, for uncertainty analysis they can be neglected. The energy band parameters and polarization coefficients of nitride materials exhibit very less uncertianity as seen in the l iterature. Therefore, the trap location (x T ) is accurate. The main source of uncertainity in Eq. (6 3) is the Schottky barrier height ( B ). Here we assume a Schottky barrier height ( B ) of 0.8 eV. If the uncertainty in the barrier height is taken into account then the extracted trap activation energy (E C E T ) becomes 0. 9 0.2 eV This value agrees very well with what is reported in the literature as dislocation/extended defects related complexes or point defects loos ely bound to dislocations [52 55] It has been postulated in the literature that point defects aggregate around dislocations which act as

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69 stepping stones for defect assisted tunnelling [15] Also these defects are located close to the Fermi level making them accessible from the gate terminal. It can be argued that the overall increase of the trap density in the gate stac k observed at high RF stress (8 dB compression) is a result of an overall increase of these individual point defects. Failure Mechanism The device experiences elevated temperatures due to static and dynamic current in the channel. It has been shown in the literature that thermo elastic stress counteracts the effect of inverse piezo electric stress thereby increasing the robustness of the gate stack at higher temperatures [56] This brings attention to a failure mechanism which is particularly relevant for high RF overdrive conditions. During large RF positive voltage swings on the gate, high forward currents flow through the gate Schottky junction. Figure 6 12 shows the simulated 1D conduction band diagram at a positive gate voltage of 2V along the gate to GaN buffer layer direction without solving the transport equations. clear from the diagram that most of the potential drop takes place very near to the metal/semiconductor interface and GaN capping layer due to large opposite buil t in piezoelectric polarization electric field in the AlGaN barrier. Thus, carriers which are injected from the 2DEG channel dissipate most of their energy into the gate metal/semiconductor junction and GaN capping layer thereby the probability of degradat ion increases in this region. This agrees well with the gate noise characteristics which confirmed degradation right under the gate metal. To further corroborate this, the authors performed a forward gate DC voltage stress. Figure 6 13 shows the results of DC forward voltage stress on the gate diode characteristics with source and drain grounded. It can be seen that gate leakage current degrades irreversibly after V G =1V

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70 DC stress. The threshold voltage (not shown here) also shifted towards more negative val ues. These two effects are well correlated to the DC degradation effects observed after the 8dB compression RF stress. Furthermore, noise measurements were also carried out on DC stressed devices which agreed well with results from RF stress. Thus, confirm ing the role of forward gate bias as a primary failure mechanism in this study.

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71 Fig ure 6 1 Experimental setup to perform DC characterization, RF stress and LFN measurements.

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72 Fig ure 6 2 RF power measurement at 3 GHz. Power gain (diamond) and output power (squares) on the left axis. DC quiescent current (triangles) is shown on the right axis. The 3 dB and 8 dB gain compression occurs at an input power of 6 dBm and 18 dBm respectively.

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73 Fig ure 6 3 Degradation of RF output power for 3 dB (green) and 8 dB (brown) gain compression is shown.

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74 Fig ure 6 4 DC gate I V for V DS =0 are shown for pre stress (blue), post 3 dB compression stress (green) and post 8 dB compression stress (red). Fig ure 6 5 DC I D V GS for V DS =80 mV is shown for pre and post 8 dB compression stress.

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75 Fig ure 6 6 Relative channel current noise before stress (blue) and after 8 dB compression stress (red).

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76 Fig ure 6 7 Relative gate current noise before RF stress (blue), after 3 dB RF stress (red). Noise after DC inverse pie zo electric stress (OFF state) is shown in green. More details of that work can be found in a previous work [ 47 ]

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77 Fig ure 6 8 Mean capture (triangle) and emission times (square) determined from RTS noise data as a function of gate voltage (above threshold voltage). Inset shows the relative gate current fluctuation in the time domain.

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78 Fig ure 6 9 Relative gate current noise b efore stress (blue) after 8 dB RF stress (red). Noise after inverse piezo electric stress (OFF state) is shown in green. More details of that work can be found in a previous work [ 47 ]

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79 Fig ure 6 10 Conduction band diagram under the gate for two increasing (black dashed arrow) gate voltages V G1 and V G2 (above the threshold voltage).

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80 Fig ure 6 11 The ratio of mean time switching constants (dots) is plotted as a function of gate voltage. The dashed line shows the simulated value of this ratio eq uation relation ( 6 2) and ( 6 3).

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81 Fig ure 6 12. Conduction band diagram under the gate for V GS = 2 V. Most of the voltage drop occurs very near to the gate metal/GaN capping semiconductor interface and GaN capping layer. The dashed line shows the Fermi l evel in the GaN channel layer. The arrow shows the direction of electron motion for forward gate current.

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82 Fig ure 6 13 Gate diode I V characteristics for increasing (arrow direction) forward DC gate voltage stress from 1V to 3V of 5 minutes each.

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83 CHAPTER 7 CONCLUSIONS Summary of Results The objective of this study was to understand the nature of defects which negatively impac t the reliability of GaN HEMTs using low frequency noise measurements A defect map of l ocation, density and activation energy of defects is a powerful instrument for increasing device reliability via device geometry and material choice optimization. In chapter 2 fundamental noise sources are identified in AlGaN/GaN HEMTs. It is found that th ere is an extremely weak correlation between gate and drain current noise. Drain current mainly stems from the gated channel region and shows a stable 1/f noise without distinct GR noise components. A low value of Hooge parameter 10 4 is determined for it. On the other hand, gate current noise also exhibits a 1/f noise with S IG I G 2 dependence but shows in addition distinct Lorentzian components. Often these Lorentzians are so dominant that they show up as RTS noise in the time domain. These Lorentzian s are found to be temporally unstable and their noise sources migrate under device operation whereas the background 1/f noise is stable. It is proposed that the Schottky contact is of high quality and does not degrade under device operation but factors li ke high electric fields, low defect migration barriers, high mechanical strain via inverse piezo electric effect in the AlGaN/GaN system create a possibility whereby, defect centers in AlGaN barrier evolve spatially or change their energy locations. The e xact nature of this migration needs to be explored further possibly by studying low frequency noise under systematically applied electrical stress to the gate stack. This

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84 makes the study of low frequency noise an extremely sensitive tool to study device re liability under realistic bias conditions. In chapter 3 the gate is stressed by applying reverse bias voltage. Temporary and permanent degradation of device characteristics were identified in stressed AlGaN/GaN HEMTs. It wa s found that existing traps in th e AlGaN barrier layer contribute to the threshold voltage instability and change the drain current noise. The DC and channel noise characteristics of the device fully recover ed after several days indicating that no microscopic degradation occurred in the c hannel region of the device On the other hand gate current noise show ed a permanent change which does not recover once the stress is removed. It wa s proposed that new defect states were created at gate edges via inverse piezoelectric effect below the so c [18] The activation of mobile defects point ed to a defect movement or diffusion related mechanism at these early stages of degradation In chapter 4 the failure mechanisms in the channel were probed in more detail. It was found that h ot carrier injection combined with self heating was a dominant cause of degradation in the channel for ON state stress conditions by increasing the trap density at the AlGaN/GaN interface. In c hapter 5 the kinetics of the hot carriers in GaN HEMTs was studied in detail by performing microwave noise spectroscopy. It was found that hot electrons which exist in the channel are confined at the AlGaN/GaN interface b ut have enough energies to generate new interface defects responsible for the obser ved degradation in ON state stress. In c hapter 6 the effect of short term high power RF stress on AlGaN/GaN HEMTs is characterized. It was found that degradation occurs right under the gate in the gate

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85 metal semiconductor interface and GaN capping layer wi thout affecting the channel. Gate noise measurements pointed out that an increase of the trap density near the metal semiconductor interface occurred after high gain compression RF stress. A point defect located at 4.5 nm under the gate and activation ener gy (E C E T ) of 0.9 0.2 eV was extracted from gate RTS noise measurements. These defects have been often reported to be related to the core of the dislocations or point defects loosely bound to dislocations [52 55] These unstable point defects were activated after low RF power stress. The role of forward gate biasing as a failure mechanism was discussed. This also po ints out that when the reliability of the gate stack at high RF compression levels is considered a simpler gate forward biased DC stress test can replace the high gain compression RF stress measurement Future Work The m ajority of my research was concentrated on short term reliability studies since most of the devices did not survive long enough under applied stresses. However, it would be useful to study lower stress levels but applied for long durations to understand the role of time. The i nverse piezo electric stress in our study used voltages which did not exceed the so [18] It would be beneficial to study the effect of full breakdown of the gate stack over critical voltage That would give insights into the natu re of the breakdown pathway and the nature of defects responsible for that It is similar to a study of Soft and Hard Breakdown of oxides in silicon MOSFETs. I t would be valuable to develop a more quantitative estimation of interface defects both at the g ate metal semiconductor interface and AlGaN/GaN channel interface which can be used as an input parameter for reliability simulations and lifetime estimations

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86 Finally, this work should be expanded to study more devices to improve the statistical significa nce of the results. This would also enable a better correlation of the results to material characterization techniques to study defects such as the transmission electron microscopy.

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87 LIST OF REFERENCES [1] [2] recombination noise in p Sol id State Electronics vol. 25, no. 4, pp. 273 280, Apr. 1982. [3] M. J. Deen, M. E. Levinshtein, S. L. Rumyantsev, and J. Orchard Webb, Semiconductor Science and Technology vol. 14, no. 3, pp. 298 304, Mar. 1 999. [4] Microelectronics Reliability vol. 42, no. 4 5, pp. 573 582, May 2002. [5] state microstructures: A new perspective on individual defects, interface states and low Advances in Physics vol. 38, no. 4, p. 367, 1989. [6] K. K. Hung, P. K. Ko, C. Hu, and Y. C. C in metal oxide semiconductor field IEEE Transactions on Electron Devices vol. 37, no. 3, pp. 654 665, Mar. 1990. [7] Phys. Rev. Lett. vol. 17, no. 18, pp. 956 958, Oct. 1966. [8] Z. Celik SiO2 interface trap density IEEE Transactions on Electron Devices vol. 35, no. 10, pp. 1651 165 5, Oct. 1988. [9] collapse and gate leakage currents in AlGaN/GaN heterostructure field effect Papers from the 30th Conference on the Physics and Chemistry of S emiconductor Interfaces Salt Lake City, Utah (USA), 2003, vol. 21, pp. 1844 1855. [10] S. L. Rumyantsev, N. Pala, M. S. Shur, R. Gaska, M. E. Levinshtein, M. A. Khan, A J. Appl. Phys. vol. 88, no. 11, pp. 6726 6730, Dec. 2000. [11] S. L. Rumyantsev, N. Pala, M. S. Shur, R. Gaska, M. E. Levinshtein, P. A. Ivanov, he 1/f Semiconductor Science and Technology vol. 17, no. 5, pp. 476 479, 2002.

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89 [23] D. J. Ewing, M. A. Derenge, P. B. Shah, U. Lee, T. S. Zheleva, and K. A. Jones, on in J. Vac. Sci. Technol. B vol. 26, no. 4, pp. 1368 1372, Jul. 2008. [24] IE EE Transactions on Electron Devices vol. 48, pp. 560 566, Mar. 2001. [25] of High Electric Electron Devices, IEEE Transactio ns on vol. 55, no. 7, pp. 1592 1602, 2008. [26] Gaudenzio Meneghesso, Fabiana Rampazzo, Peter Kordos, Giovanni Verzellesi, Electric Field Reliability of Electron Devices, I EEE Transactions on vol. 53, no. 12, pp. 2932 2941, 2006. [27] IEEE Transactions on Electron Devices vol. 41, pp. 2176 2187, Nov. 1994. [28] E. Simoen Semiconductor Science Technology vol. 14, p. 61, Aug. 1999. [29] ise Evolution the NOISE AND FLUCTUATIONS: 20th International Conference on Noise and Fluctuations (ICNF 2009), Pisa (Italy), 2009, vol. 1129, pp. 625 628. [30] A. Curutchet, N. Malbert, N. Labat, A. Touboul, C. Gaquire, A. Minko, and M. Microelectronics Reliability vol. 43, no. 9 11, pp. 1713 1718. [31] D. K. Sahoo, field Electron Devices, IEEE Transactions on vol. 50, no. 5, pp. 1163 1170, 2003. [32] A. Sozza, C. Dua, E. Morvan, B. Grimber, and S. L. De Microelectronics and Reliability vol. 45, no. 9 11, pp. 1617 1621.

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90 [33] frequency noise characterization of J. Appl. Phys. vol. 106, no. 10, p. 103712, 2009. [34] U. K. Mishra and J. Singh, Semiconductor Device Physics and Design Springer, 2007. [35] Microelectronics Reliability vol. 50, no. 6, pp. 758 762, Jun. 2010. [36] D. IEEE Transactions on Electron Devices vol. 54, no. 10, pp. 2614 2622, Oct. 2007. [37] A. Sozza, C. Dua, E. Morvan, M. A. diForte Poisson, S. Delage, F. Rampazzo, A. Tazzol i, F. Danesin, G. Meneghesso, E. Zanoni, A. Curutchet, N. Malbert, N. Labat, B. Grimbert, and J. GaN/AlGaN/GaN HEMTs after a 3000 hour on state and off state hot electron Electron Devices Meeting, 20 05. IEDM Technical Digest. IEEE International 2005, p. 4 pp. 593. [38] Electron Devices Meeting (IEDM), 2010 IEEE International 2010, pp. 20.2.1 20.2.4. [39] L. Ardaravi?ius, J. Liberis, A. Matulionis, L. F. Eastman, J. R. Shealy, and A. phys. stat. sol. (a) vol. 201, no. 2, pp. 203 206, Jan. 2004. [40] based two dimensi onal channels: hot electron fluctuations J. Phys.: Condens. Matter vol. 21, no. 17, p. 174203, Apr. 2009. [41] measurement of noise temperature of one port network Sixth International Conference on noise in Physical Systems 1981, vol. 614, p. 305. [42] mobility transistors under high gate and channel electric fiel ds via low frequency Microelectronics Reliability vol. 50, no. 9 11, pp. 1528 1531. [43] A. M. Conway, M. Chen, P. Hashimoto, P. J. Willadsen, and M. Micovic, Reliability physics symposium, 2007. proceedings. 45th annual. ieee international 2007, pp. 472 475.

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93 BIOGRAPHI CAL SKETCH Hemant P. Rao was born in New Delhi, India in 1985. He received the B.Tech. degree in e lectronics and c ommunication e ngineering from the National Institute of Technology, Bhopal, India in May 2007. In fall 2007 he joined the University of Florida for his graduate education where he received the MS degree in e lectrical and c omputer e ngineering in December 2008 and receive d his PhD in e lectrical and c omputer e ngineering in May 2012 He interned with the Non Volatile Memory group at the Intel Corporation, Santa Clara in the fall of 2011 where he worked on the characterization and modeling of Phase Change Memories. He also interned with the SPICE modeling group at the National Semiconductor Corporation, Santa Clara in the summer of 20 10 where he developed compact model for L DMOS devices His research interests include low frequency noise spectroscopy semiconductor device reliability and modeling. Upon graduation he will begin working as a Process Technology Development Engineer at the Intel Corporation in Boise, ID.