TCAM-Based Low Power Routers and Packet Classifiers

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Title:
TCAM-Based Low Power Routers and Packet Classifiers
Physical Description:
1 online resource (234 p.)
Language:
english
Creator:
Banerjee Mishra, Tania
Publisher:
University of Florida
Place of Publication:
Gainesville, Fla.
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Thesis/Dissertation Information

Degree:
Doctorate ( Ph.D.)
Degree Grantor:
University of Florida
Degree Disciplines:
Computer Engineering, Computer and Information Science and Engineering
Committee Chair:
Sahni, Sartaj
Committee Members:
Ranka, Sanjay
Chen, Shigang
Xia, Ye
Ahuja, Ravindra K

Subjects

Subjects / Keywords:
duo -- low-power -- packet-classification -- packet-forwarding -- pc-duos -- pc-trio -- petcam -- router-architecture -- tcam -- updates
Computer and Information Science and Engineering -- Dissertations, Academic -- UF
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Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract:
Ternary Content Addressable Memory (TCAM) is a hardware device which can support high-speed table lookups and is an attractive solution for applications such as packet forwarding and classification. A major drawback of TCAMs is that they are power-hungry. We investigate various TCAM architectures and propose PETCAM for TCAM power and memory reduction in packet forwarding and show that far better power and memory performance is possible when we use an optimal prefix set for the given forwarding table. To keep up with the changes on the Internet, it is necessary to adopt efficient update algorithms for the TCAMs. Our dual TCAM architecture, DUO, and new memory management schemes for the TCAMs supports efficient control-plane incremental updates without delaying data-plane lookups. Compared to other TCAM architectures such as CAO OPT that support incremental updates without delaying lookups, DUO offers reduction in power consumption. We present methodology CONSIST for constructing a consistent sequence of updates to be applied incrementally to packet classifiers when the updates arrive in a cluster, where consistency is with respect to the next hop/action returned from a packet forwarding table/ classifier during lookup. The sequence of updates, built using our strategy, is free from redundancies in update operations and produces a near minimal increase in table size. We prove the existence of a consistent update sequence for any given rule table and a cluster of updates. Our experiments validate our methodology and demonstrate a minimal increase in intermediate table size as a cluster of updates is applied. For TCAMs storing packet classifier rules, we propose PC-DUOS, and its enhanced version PC-DUOS+, for distributing the classifier rules to two TCAMs and for incrementally updating the TCAMs. The update and lookup performance is compared against the prevalent scheme of storing classifier rules in a single TCAM in priority order. While PC-DUOS reduces the number of TCAM writes by up to 2.82 times, PC-DUOS+ reduces the number by up to 3.72 times, compared to a single TCAM architecture. Lookup speed in PC-DUOS and PC DUOS+ improved by up to 48% compared to a single TCAM architecture. Finally, we propose an indexed TCAM architecture, PC-TRIO, for packet classifiers. PC-TRIO uses wide SRAMs and index TCAMs and supports low power lookups and incremental updates.
General Note:
In the series University of Florida Digital Collections.
General Note:
Includes vita.
Bibliography:
Includes bibliographical references.
Source of Description:
Description based on online resource; title from PDF title page.
Source of Description:
This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility:
by Tania Banerjee Mishra.
Thesis:
Thesis (Ph.D.)--University of Florida, 2012.
Local:
Adviser: Sahni, Sartaj.
Electronic Access:
RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2014-05-31

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Applicable rights reserved.
Classification:
lcc - LD1780 2012
System ID:
UFE0043973:00001


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TCAM-BASEDLOWPOWERROUTERSANDPACKETCLASSIFIERSByTANIABANERJEE-MISHRAADISSERTATIONPRESENTEDTOTHEGRADUATESCHOOLOFTHEUNIVERSITYOFFLORIDAINPARTIALFULFILLMENTOFTHEREQUIREMENTSFORTHEDEGREEOFDOCTOROFPHILOSOPHYUNIVERSITYOFFLORIDA2012

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c2012TaniaBanerjee-Mishra 2

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Idedicatethistoeveryonewhomotivatedandhelpedmecompletethethesis. 3

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ACKNOWLEDGMENTS Firstandforemost,IwouldliketothankmyadvisorProf.SartajSahniforhisguidanceandsupportthroughoutthecourseofmystudiesforPhD.IwouldalsoliketothanktheProfessorsinmyPhDcommittee,Prof.ShigangChen,Prof.SanjayRanka,Prof.YeXiaandProf.RavindraAhuja.IamgratefultotheU.S.AirForceforfundingmyresearchandtoDr.GunasekaranSitharaman,inparticular,forreveiwingandprovidingfeedbackonmypapers.IwouldalsoliketoexpressmygratitudetoErnest,PaulandDanforsupportingallmysystemrequirementsoverthistimeandtograduateadvisorsJohnandJoanforclarifyingthenumerousqueries.Thankstomyfriends-Shibdas,Xinyan,JunjieandRadhikafortheirsupport.Iameternallygratefultomyparents,myhusband,andourlittlesonAhanfortheloveandsupportwhichmadethisdissertationpossible. 4

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TABLEOFCONTENTS page ACKNOWLEDGMENTS .................................. 4 LISTOFTABLES ...................................... 9 LISTOFFIGURES ..................................... 11 ABSTRACT ......................................... 17 CHAPTER 1INTRODUCTION ................................... 19 1.1RoutersandPacketClassiers ........................ 19 1.2PacketForwarding ............................... 20 1.3ControlandDataPlanesinRouters ..................... 20 1.4PowerConsumptioninRouters ........................ 22 1.5TernaryContentAddressableMemories ................... 23 1.6Contributions .................................. 23 1.7ThesisOverview ................................ 25 2PETCAM:APOWEREFFICIENTTCAMFORFORWARDINGTABLES .... 26 2.1BackgroundandRelatedWork ........................ 26 2.2DecienciesinPrexPreprocessing ..................... 29 2.2.1IssuesRelatedtoMethodsofLiu ................... 29 2.2.2IssuesRelatedtoEaseCAM ...................... 30 2.2.2.1Prexaggregation ...................... 30 2.2.2.2Prexexpansion ....................... 31 2.3PETCAM .................................... 31 2.3.1CompactionofPrexSet ........................ 32 2.3.2RepresentationusingTernaryTries .................. 36 2.3.3CarvingTrietoCreateSufxNodes .................. 39 2.3.3.1Sufx-nodestructure .................... 40 2.3.3.2Ourcarvingheuristic .................... 44 2.3.4StoringandUpdatingPrexesinTCAM-SRAM ........... 46 2.3.4.1PETCAMstructure ...................... 46 2.3.4.2PETCAMupdates ...................... 48 2.4ExperimentalResults ............................. 48 2.4.1CompactionEfciency ......................... 49 2.4.2PowerEfciency ............................ 50 2.4.3AreaEfciency ............................. 55 2.4.4PETCAMLite .............................. 57 2.4.5ImplementationofNexthopComputation ............... 58 2.4.6PerformanceAnalysis ......................... 60 5

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3DUO:DUALTCAMARCHITECTUREFORFORWARDINGTABLESWITHINCREMENTALUPDATE .............................. 62 3.1BackgroundandRelatedWork ........................ 62 3.2SimpleDualTCAMDUOS .......................... 65 3.2.1DUOSIncrementalUpdateAlgorithms ................ 69 3.2.1.1Insert ............................. 69 3.2.1.2Delete ............................. 72 3.2.1.3Change ............................ 74 3.2.2ITCAMAlgorithms ........................... 74 3.2.3LTCAMAlgorithms ........................... 75 3.2.4ITCAMMemoryManagement ..................... 75 3.2.4.1Memorymanagementscheme1 .............. 76 3.2.4.2Memorymanagementscheme2 .............. 80 3.2.4.3Memorymanagementscheme3 .............. 83 3.2.4.4Scheme4 ........................... 88 3.3WideDualTCAMDUOW ........................... 92 3.4IndexedDUOWIDUOW ............................ 99 3.4.1MemoryManagementforDLTCAMandILTCAM .......... 99 3.4.21-12Wc ................................. 106 3.4.3M-12Wb ................................. 108 3.5ExperimentalResults ............................. 112 3.5.1EvaluationofMemoryManagementSchemes ............ 113 3.5.2EvaluationofDUOS .......................... 118 3.5.3EvaluationofDUOW .......................... 122 3.5.4EvaluationofIDUOW .......................... 124 3.5.5ComparisonwithMIPSandCAO OPT ................ 126 4CONSIST:CONSISTENTUPDATESFORPACKETCLASSIFIERS ....... 137 4.1BackgroundandRelatedWork ........................ 137 4.2ConsistentUpdates .............................. 142 4.2.1DenitionsandProperties ....................... 142 4.2.2BatchConsistentSequences ..................... 151 4.2.2.1Graphrepresentationofupdates .............. 151 4.2.2.2Constructinganear-optimalbatchconsistentsequence 152 4.2.3IncrementalConsistentSequences .................. 158 4.3Experiments .................................. 160 4.3.1Benchmarks ............................... 160 4.3.2Results ................................. 163 4.3.2.1Forwardingtables ...................... 163 4.3.2.2Packetclassiers ....................... 164 6

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5PC-DUOS:FASTTCAMLOOKUPANDUPDATEFORPACKETCLASSIFIERS 168 5.1BackgroundandRelatedWork ........................ 168 5.2PC-DUOS:Methodology ............................ 171 5.2.1StoringRulesinTCAMs ........................ 172 5.2.1.1Representingclassierrules ................ 172 5.2.1.2StoringrulesintheLTCAM ................. 173 5.2.1.3StoringrulesintheITCAM ................. 175 5.2.2UpdateAlgorithms ........................... 176 5.2.2.1Updatethetrie ........................ 177 5.2.2.2Othercontrol-planeoperationsforupdates ........ 178 5.3ExperimentalResults ............................. 180 6PC-DUOS+:ANENHANCEDDUAL-TCAMARCHITECTUREFORPACKETCLASSIFIERS .................................... 186 6.1PC-DUOS+:Methodology ........................... 186 6.1.1StoringRulesinTCAMs ........................ 186 6.1.1.1Representingclassierrules ................ 187 6.1.1.2StoringrulesintheLTCAM ................. 187 6.1.1.3StoringrulesintheITCAM ................. 187 6.1.2UpdateAlgorithms ........................... 188 6.1.2.1Updatetheprioritygraphandthetrie ........... 189 6.1.2.2UpdatingtheTCAMs .................... 195 6.2ExperimentalResults ............................. 198 6.2.1Setup .................................. 198 6.2.2LookupPerformance .......................... 198 6.2.2.1Updateperformance ..................... 200 7PC-TRIO:ANINDEXEDTCAMARCHITECTUREFORPACKETCLASSIFIERS 206 7.1BackgroundandRelatedWork ........................ 206 7.1.1PacketClassiers ............................ 206 7.1.2ProblemsinStoringaClassierinanIndexedTCAM ........ 207 7.1.3OvercomingtheProblems ....................... 209 7.2PC-TRIO .................................... 209 7.2.1TheArchitecture ............................ 209 7.2.2StoringRulesinTCAMs ........................ 211 7.2.2.1Representingclassierrules ................ 211 7.2.2.2StoringrulesintheLTCAM1 ................ 212 7.2.2.3StoringrulesinLTCAM2 .................. 217 7.2.2.4StoringrulesintheITCAM ................. 217 7.2.3IncrementalUpdates .......................... 217 7.2.3.1Updatingtheprioritygraph ................. 217 7.2.3.2Updatingthetries ...................... 218 7.2.3.3Updatingthetriecarving .................. 218 7

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7.2.3.4UpdatingtheTCAMs .................... 219 7.3DifferencesamongPC-DUOS,PC-DUOS+,PC-DUOS+WandPC-TRIO 220 7.4ExperimentalResults ............................. 221 7.4.1Setup .................................. 221 7.4.2Datasets ................................. 222 7.4.3Results ................................. 224 7.4.3.1NumberofTCAMentries .................. 224 7.4.3.2Power ............................. 224 7.4.3.3Lookupperformance ..................... 225 7.4.3.4Spacerequirements ..................... 226 7.4.3.5Updateperformance ..................... 226 7.4.3.6CharacteristicsofthelogicthatprocesseswideSRAMwords ............................. 227 8CONCLUSION .................................... 229 REFERENCES ....................................... 230 BIOGRAPHICALSKETCH ................................ 234 8

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LISTOFTABLES Table page 1-1Anexample6-prexforwardingtable ........................ 20 2-1Routingtablewithgeneralizedprexes ....................... 36 2-2Anexample6-prexforwardingtable ........................ 40 2-3NumberofroutingtableprexesinPETCAM ................... 50 2-4TCAMpower(inmW)forthedifferentschemes .................. 51 2-5SRAMpower(inmW)forthedifferentschemes .................. 53 2-6TCAMarea(inmm2)forthedifferentschemes .................. 54 2-7SRAMarea(inmm2)forthedifferentschemes .................. 55 2-8TCAMsize(inKB)forthedifferentschemes .................... 56 2-9SRAMsize(inKB)forthedifferentschemes ................... 57 2-10ExecutiontimeinsecondsforSteps1and2ofCompact ............. 58 2-11Timingandpowerresultsforadditionalhardware ................. 59 3-1Datasetsusedintheexperiments ......................... 112 3-2NumberofmovesforthesimpleTCAM ...................... 115 3-3AveragenumberofmovesforthesimpleTCAM .................. 116 3-4MaximumnumberofmovesforthesimpleTCAM ................. 117 3-5StandarddeviationinnumberofmovesforthesimpleTCAM .......... 118 3-6NumberofwaitWritesforthesimpleTCAM .................... 119 3-7NumberofScheme3movesforinserts ...................... 120 3-8Distributionofprexes,inserts,anddeletesforDUOS .............. 121 3-9NumberofmovesforinsertsanddeletesintheITCAMofDUOS ........ 122 3-10NumberofwaitWritesintheITCAMofDUOS ................... 123 3-11NumberofLTCAMmovesandwaitWritesforDUOS ............... 124 3-12NumberofprexestobestoredintheLTCAMandassociatedwideSRAM .. 125 3-13NumberofwaitWritesintheLTCAMofDUOW .................. 126 9

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3-14NumberofwaitWritesfortheILTCAMofIDUOWusing1-12Wc ......... 127 3-15StatisticsfortheDLTCAMofIDUOWusing1-12Wc ................ 128 3-16StatisticsfortheILTCAMofIDUOWusingM-12Wb ................ 129 3-17StatisticsfortheDLTCAMofIDUOWusingM-12Wb ............... 130 3-18TotalnumberofTCAMwaitWriteoperations .................... 131 3-19MaximumnumberofTCAMwritesforasinglerawinsert/delete ......... 132 3-20AcomparisonofpowerconsumedbyMIPS,CAO OPTandDUOinperformingTCAMsearch ..................................... 134 4-1Datasetsusedintheexperiments ......................... 163 4-2Syntheticclassiersandupdatetracesusedintheexperiments ......... 164 4-3Totalnumberofupdatesbeforeandafterapplyingreductionandthemaximumincreaseintablesize ................................. 165 4-4Maximumincreaseinintermediateclassierruletablesize ........... 166 5-1Syntheticclassiersandupdatetracesusedintheexperiments ......... 181 5-2NumberofTCAMwritesinPC-DUOSandSTCAMusingprexrepresentationscheme ........................................ 183 5-3NumberofTCAMwritesinPC-DUOSandSTCAMusingDIRPE[ 18 ] ...... 183 6-1NumberofrulesinITCAMandLTCAMofPC-DUOS+andimprovementinlookuptimerelativetoSTCAM ........................... 199 6-2AverageandworstcaseTCAMwritesforPC-DUOS+ .............. 204 6-3TotalTCAMwritesinPC-DUOS+,PC-DUOSandSTCAM ............ 204 7-1NumberofTCAMentries,ITCAMentriesandTCAMpowerandlookuptimeinPC-DUOS+,PC-DUOS+W,PC-TRIO ...................... 223 7-2Timingandpowerresultsforadditionalhardware ................. 227 10

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LISTOFFIGURES Figure page 1-1Controlanddataplanesinrouters ......................... 21 1-2Routerarchitecturewithbatchupdatingpolicy ................... 21 1-3Routerarchitecturewithincrementalupdatingpolicy. ............... 22 2-1TrieforexampleprexsetC=f000,001,010,011,00g.Packetwithaddress000*isforwardedtonexthopH1. ..................... 29 2-2TrieforprexsetinFigure 2-1 ,afterlogicminimization.Packetwithaddress000*isforwardedtonexthopH2! .......................... 30 2-3FlowdiagramforPETCAMconstruction ...................... 32 2-4Algorithmforcompactionofaprexset ...................... 33 2-5Ternarytriefortherouting-tableofTable 2-1 .................... 37 2-6Ternarytrieaftermergingofthex-childofroot .................. 38 2-7Normalizedternarytrie ............................... 38 2-8Algorithmtonormalizeaternarytrie ........................ 39 2-9Algorithmtomergeanx-subtree .......................... 39 2-10Sufxnodeof[ 21 ]witha5-bitmatchstartpositioneldandrepresentationoftherstsufx. ..................................... 40 2-11SixrulesofTable 2-2 storedinTCAM+SRAM .................. 41 2-12Sufxnodeexample ................................. 41 2-13TypeIsufxnode ................................... 41 2-14TypeIIsufxnode .................................. 42 2-15(numP,xNumP,size)fornodesoftrieinFigure 2-7 ................ 45 2-16Visitfunctionforsubtreecarvingheuristic[ 21 ] ................... 46 2-17PETCAMstructure .................................. 47 2-18Relativeefciencyfortablecompaction ...................... 48 2-19Comparisonoftotalpower(TCAM+SRAM)amongdifferentschemes ..... 52 2-20Pipelineprocessingsufxnodewithvariablesufxlengths ............ 59 11

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2-21Tradeoffgraph .................................... 60 3-1Insertionoftherootprexinto(a)requirestheinsertionof4newindependentprexesintotheTCAM.Similarly,thedeletionoftherootprexfrom(b)requiresthewithdrawalofthese4prexesfromtheTCAM ................ 65 3-2DualTCAMwithsimpleSRAM ........................... 67 3-3DUOSforanexample4-prexforwardingtable.NotethatprexesinITCAMarestoredinlengthorder,whereasthoseinLTCAMarestoredarbitrarilysincetheprexesaredisjoint. ............................... 68 3-4Tableofcontrol-planetriefunctions ......................... 68 3-5Tableoffunctionsusedforincrementalupdate .................. 70 3-6AlgorithmtoinsertintoDUOS ............................ 70 3-7InsertruleP5-f1*,H5gtotheinitialtableinFigure 3-3 .P5isaleafandhenceisaddedtotheLTCAM ................................ 71 3-8InsertruleP6-f011*,H6gtotheprexesinFigure 3-7 .P6isaddedtotheLTCAM,whileP3,whichisnolongeraleaf,isdeletedfromLTCAMandaddedtoITCAM. ....................................... 71 3-9InsertruleP7-f0*,H7gtotheprexesinFigure 3-8 .P7isaddedtotheITCAMsinceitinvolvesanintermediateprex. ....................... 71 3-10AlgorithmtodeletefromDUOS ........................... 72 3-11DeleteruleP7-f0*,H7gfromtheprexesinFigure 3-9 .P7isdeletedfromITCAM. ........................................ 73 3-12DeleteruleP4-f000*,H4gfromtheprexesinFigure 3-11 .P4isdeletedfromLTCAM.P2isinsertedtoLTCAManddeletedfromITCAMasP2isnowaleaf. ......................................... 73 3-13DeleteruleP5-f1*,H5gfromtheprexesinFigure 3-12 .P5isdeletedfromLTCAM. ........................................ 73 3-14AlgorithmtochangeanexthopinDUOS ..................... 74 3-15ITCAMalgorithms .................................. 75 3-16LTCAMalgorithms .................................. 76 3-17MovefromITCAM[src]toITCAM[dest] ....................... 76 3-18PrexarrangementinITCAMforScheme1forIPv4.Thefreespacepoolisindicatedbyhatchedlines.Numbers1,2bythecurvedarrowcorrespondtotherstandsecondmove,respectively. ...................... 77 12

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3-19Scheme1algorithmtogetafreeslottoinsertaprexwhoselengthislen ... 78 3-20Scheme1algorithmtofreeaslotpreviouslyoccupiedbyaprexoflengthlen 79 3-21ITCAMlayoutforScheme2(DFS PLO) ...................... 80 3-22Scheme2algorithmtogetafreeslottoinsertaprexwhoselengthislen ... 81 3-23Scheme2algorithmtofreeaslot .......................... 81 3-24SupportingalgorithmsusedbythealgorithmofFigure 3-22 ........... 82 3-25ITCAMlayoutforScheme3,withmovesforinsertanddelete.Thecurvedarrowsontherightshowtheforwardlinksinthelistoffreespaces. ........... 84 3-26Scheme3algorithmtogetafreeslottoinsertaprexwhoselengthislen ... 85 3-27Scheme3algorithmtofreeaslot .......................... 85 3-28Algorithmstobringinaslottoatargetblockfromabove(loweraddressesoftheTCAM).ThesealgorithmsareusedbygetSlotofFigure 3-26 ........ 86 3-29Algorithmstobringinaslottoatargetblockfrombelow(higheraddressesoftheTCAM).ThesealgorithmsareusedbygetSlotofFigure 3-26 ........ 87 3-30Scheme4getSlotalgorithm ............................. 89 3-31Scheme4freeSlotalgorithm ............................ 90 3-32SupportingcontrolplanetriealgorithmsusedbytheScheme4getSlotandfreeSlotalgorithms .................................. 91 3-33Carvingusingthemethodof[ 21 ]andourmethod ................. 93 3-34AssignmentofprexesofFigure 3-7 toTCAMsinthedualTCAMarchitecture 95 3-35AlgorithmtocarvealeaftrietoobtaindisjointQ(N)s ............... 96 3-36DUOWalgorithmtoinsertaprexintotheLTCAM ................ 96 3-37AlgorithmtoaddasufxtoawideLSRAMword ................. 96 3-38Deleteprexes .................................... 97 3-39AlgorithmtosplitawideLSRAMwordintotwo .................. 97 3-40DUOWalgorithmtodeletealeafprex ....................... 98 3-41DUOWalgorithmtochangethenexthopofaleafprex ............. 98 3-42DLTCAMinsertalgorithm .............................. 101 3-43AddasufxtoaDLSRAMword .......................... 102 13

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3-44SplitaDLSRAMword ................................ 103 3-45Deletealeafprex .................................. 104 3-46Changethenexthopofaleafprex ........................ 105 3-471-12Wccongurationin[ 21 ] ............................. 106 3-48Our1-12Wcconguration .............................. 107 3-49Assignanewbucketin1-12Wc ........................... 108 3-50M-12Wbcongurationin[ 21 ] ............................ 108 3-51Visitalgorithm .................................... 110 3-52Splitanode ...................................... 110 3-53Assignanewbucket ................................. 110 3-54Incrementanddecrementroom ........................... 111 3-55Comparisonofperformancebetweendifferentmemorymanagementschemes 116 3-56ComparisonofTCAMperformanceandpowerconsumptionbetweenMIPS,CAO OPT,DUO ................................... 129 4-1Prexesinforwardingtablebeforeandafterapplyingupdates .......... 138 4-2Prexesasupdatesarebeingappliedintwodifferentsequences ........ 139 4-3Notationusedinthischapter ............................ 143 4-4Flowdiagramforcreatingaconsistentsequenceofupdates ........... 144 4-5Actualandreducedupdatesequences ....................... 146 4-6Tj+1foraforwardingtable.Fisnewlyinserted/changedprex,fisthedestinationaddressonapacket. ................................. 148 4-7AbadexampleforsequenceofTheorem 4.1 ................... 149 4-8AnexampleforsequenceofTheorem 4.3 onforwardingtables ......... 150 4-9Areducedupdatesequenceanditsprecedencegraph .............. 152 4-10Algorithmtocomputeanear-optimaltopologicalorder .............. 153 4-11Adigraphforwhichourheuristicproducessub-optimalordering ........ 157 4-12Adeletestar ..................................... 158 4-13Someofthecomplexdigraphcomponentsofthetraceupdatedata. ...... 159 14

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5-1FlowdiagramforstoringpacketclassiersinTCAMs ............... 172 5-2Exampleofatwo-dimensionaltriestoringthreerules:R1,R2andR3 ..... 173 5-3SelectingrulesforinsertionintoLTCAM ...................... 175 5-4Findoverlappingrulesbytrietraversal ....................... 177 5-5Tableofcontrol-planetriefunctions ......................... 178 6-1FlowdiagramforstoringpacketclassiersinTCAMs ............... 187 6-2Tableofcontrol-planetriefunctions ......................... 189 6-3Settinghprionanewvertexinaprioritygraph .................. 190 6-4InsertaruleintheITCAM .............................. 191 6-5MovingdescendantsdownwardintheITCAM ................... 192 6-6Decisiondiagramsforpriorityadjustmentofdescendantsvs.ancestors .... 194 6-7InitialITCAMlayout ................................. 196 6-8PercentageofrulesstoredintheLTCAMandpercentageimprovementinlookuptimecomparedtoSTCAMarchitecture ....................... 198 6-9NumberofTCAMwriteswithrespecttoPC-DUOS+ ............... 200 6-10RuntimenormalizedwithrespecttoPC-DUOS+ ................. 200 6-11Ratioofedgestoverticesofgraph ......................... 201 6-12Maximumchainlengthingraphbeforeprocessingupdates ........... 202 6-13Asmallgraphrepresentingtestipc3 ........................ 202 6-14Percentageofupdatesthatrequire1write,3and10writes ......... 202 7-1Anexampleclassier ................................ 208 7-2ClassierrulesstoredinaindexedTCAM ..................... 208 7-3PC-TRIOArchitecture ................................ 210 7-4Selectingprotocolnodesforleavesofleavesset ................. 212 7-5DataencodinginawideSRAMword ........................ 212 7-6Nodesinasourcetrieisbeingcarved. ....................... 214 7-7Prexesinforwardingtablebeforeandafterapplyingupdates .......... 216 15

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7-8Differencesamongthearchitectures ........................ 221 7-9Comparisonofcompactionratio,totalpower,lookuptimeandarea ....... 225 7-10TCAMwrites ..................................... 227 16

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AbstractofDissertationPresentedtotheGraduateSchooloftheUniversityofFloridainPartialFulllmentoftheRequirementsfortheDegreeofDoctorofPhilosophyTCAM-BASEDLOWPOWERROUTERSANDPACKETCLASSIFIERSByTaniaBanerjee-MishraMay2012Chair:SartajSahniMajor:ComputerEngineeringTernaryContentAddressableMemory(TCAM)isahardwaredevicewhichcansupporthigh-speedtablelookupsandisanattractivesolutionforapplicationssuchaspacketforwardingandclassication.AmajordrawbackofTCAMsisthattheyarepower-hungry.WeinvestigatevariousTCAMarchitecturesandproposePETCAMforTCAMpowerandmemoryreductioninpacketforwardingandshowthatfarbetterpowerandmemoryperformanceispossiblewhenweuseanoptimalprexsetforthegivenforwardingtable.TokeepupwiththechangesontheInternet,itisnecessarytoadoptefcientupdatealgorithmsfortheTCAMs.OurdualTCAMarchitecture,DUO,andnewmemorymanagementschemesfortheTCAMssupportsefcientcontrol-planeincrementalupdateswithoutdelayingdata-planelookups.ComparedtootherTCAMarchitecturessuchasCAO OPTthatsupportincrementalupdateswithoutdelayinglookups,DUOoffersreductioninpowerconsumption.WepresentamethodologyCONSISTforconstructingaconsistentsequenceofupdatestobeappliedincrementallytopacketclassierswhentheupdatesarriveinacluster,whereconsistencyiswithrespecttothenexthop/actionreturnedfromapacketforwardingtable/classierduringlookup.Thesequenceofupdates,builtusingourstrategy,isfreefromredundanciesinupdateoperationsandproducesanearminimalincreaseintablesize.Weprovetheexistenceofaconsistentupdatesequenceforany 17

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givenruletableandaclusterofupdates.Ourexperimentsvalidateourmethodologyanddemonstrateaminimalincreaseinintermediatetablesizeasaclusterofupdatesisapplied.ForTCAMsstoringpacketclassierrules,weproposePC-DUOS,anditsenhancedversionPC-DUOS+,fordistributingtheclassierrulestotwoTCAMsandforincrementallyupdatingtheTCAMs.TheupdateandlookupperformanceiscomparedagainsttheprevalentschemeofstoringclassierrulesinasingleTCAMinpriorityorder.WhilePC-DUOSreducesthenumberofTCAMwritesbyupto2.82times,PC-DUOS+reducesthenumberbyupto3.72times,comparedtoasingleTCAMarchitecture.LookupspeedinPC-DUOSandPC DUOS+improvedbyupto48%.Finally,weproposeanindexedTCAMarchitecture,PC-TRIO,forpacketclassiers.PC-TRIOuseswideSRAMsandindexTCAMsandsupportslowpowerlookupsandincrementalupdates. 18

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CHAPTER1INTRODUCTION 1.1RoutersandPacketClassiersInternetroutersaredevicesthatconnectseveralpacketswitchednetworkstoallowcommunicationandresourcesharingamongalargegroupofusers.Arouterimplementsthepacketforwardingandroutingfunctionsofnetworklayerwhichisthethirdlayeroftheseven-layerOSImodelofcomputernetworking.Arouterhasseveralinputandoutputportsthroughwhichitreceivesandsendspackets.Apacketarrivingataninputportofarouteristransferredtoanappropriateoutputportandfromheretoitsnexthoponthepathtoitsdestination.Aroutermaintainsalistofrulesinaforwardingtablethatisusedtodeterminethenexthopsforpacketsduringpacketforwarding.ArouterupdatesitsforwardingtablecontinuouslyinresponsetochangesintheInternet.Alltheroutersinanetworkcommunicatewitheachotherusingroutingprotocolstoremainupdatedofthechangesandtoselectthebestpathstoreachabledestinationaddresses.Thedatapacketsreceivedbyarouterareoftencategorizedintodifferentowsusingatableofrulesinwhicheachruleisoftheform(F,A),whereFisalterandAisanaction.Thisispacketclassication.Whenanincomingpacketmatchesaruleintheclassier,itsactiondetermineshowthepacketishandled.Forexample,thepacketcouldbeforwardedtoanappropriateoutputlink,oritmaybedropped.Ad-dimensionallterFisad-tuple(F[1],F[2],,F[d]),whereF[i]isarangespeciedforanattributeinthepacketheader,suchasdestinationaddress,sourceaddress,portnumber,protocoltype,TCPag,etc.ApacketmatcheslterF,ifitsattributevaluesfallintherangesofF[1],,F[d].Sinceitispossibleforapackettomatchmorethanoneoftheltersinaclassiertherebyresultinginatie,eachrulehasanassociatedcostorpriority.Whenapacketmatchestwoormorelters,theactionofthematchingrulewiththelowestcost(highestpriority)isappliedonthepacket.Itisassumedthatlters 19

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thatmatchthesamepackethavedifferentpriorities.Packetclassicationisakeystepinroutersforvariousfunctionssuchasrouting,creatingrewalls,loadbalancinganddifferentiatedservices. 1.2PacketForwardingPacketforwardingisaspecialcaseofpacketclassicationinwhichaone-dimensionallterisused.Inparticular,thedestinationaddressonapacketisusedtodeterminethenexthopforthepacket.Aforwardingtableoftencontainshundredsofthousandsofrules.Apacketforwardingrule(P,H)comprisesaprexPwhichactsasthelterandanexthopH,whichcorrespondstotheactionofforwardingthepackettoH.Thus,apacketwithdestinationaddressdisforwardedtoHwhereHisthenexthopassociatedwiththerulethathasthelongestprexmatchingd.Table 1-1 showsasmallforwardingtablewith6prexes.TheprexassociatedwithruleR5is100(the*attheendindicatesasequenceofdon'tcarebits)andtheassociatednexthopisH5.RuleR5matchesalldestinationaddressesthatbeginwith100.Thelengthoftheprex100associatedwithR5is3.Adestinationaddressthatbeginswith100ismatchedbyrulesR1,R3,andR5.Amongtheserules,R5istheonewiththelongestprex.So,H5isthenexthopforpacketswithadestinationaddressthatbeginswith100. Table1-1. Anexample6-prexforwardingtable PrexesNextHop R1*H1R200*H2R310*H3R411*H4R5100*H5R6111*H6 1.3ControlandDataPlanesinRoutersFigure 1-1 showsablockdiagramoftheinternalsofarouter.Thepartofarouterthatdealswithpacketforwardingiscalledthedataplaneandthepartthatcommunicateswithotherroutersandselectsthebestroutestodifferentdestinations 20

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Figure1-1. Controlanddataplanesinrouters andkeepstheforwardingtableupdatediscalledthecontrolplane.Thecontrolplaneupdatestheforwardingtableeitherinabatchorincrementally.Whentheupdatesaredoneinabatch,twocopiesoftheforwardingtablearemaintainedasshownintheFigure 1-2 .Whileonecopyisusedfordataplanelookups,theothercopyismade Figure1-2. Routerarchitecturewithbatchupdatingpolicy up-to-datebythecontrolplane.Whentheupdatingiscomplete,thedataplaneswitchestothefreshlyupdatedcopyforlookups,andtheoutdatedcopyisupdatedbythecontrolplane.Thusbatchupdatesrequiretwicethememoryforstoringtwocopiesoftheforwardingtableandintroducealatencybetweenarrivalofanupdaterequestandthe 21

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timetheupdateisincorporated.Incontrast,whentheupdatesareappliedincrementally,lookupsandupdatesaredoneonthesametableasshowninFigure 1-3 Figure1-3. Routerarchitecturewithincrementalupdatingpolicy. 1.4PowerConsumptioninRoutersWiththerapidgrowthoftheInternet,thenumberofroutersbeingusedisincreasingdramatically.Whileroutersusedathomesconsumeabout5-10W,edgeroutersconsumeabout4kWofpowerandthecoreroutersabout10kWofpowerperrack[ 51 ].ItwasmeasuredthatinJapan,ICTequipmentin2006consumedabout45TWhor4%oftheelectricitygeneratedand1%ofthetotalenergyconsumptionofthecountry[ 23 ].Approximately,25%oftheICTequipmentenergyisconsumedbyrouters.Thepacketforwardingengineofarouterneedsalotofenergytoperformhigh-speedlookupsandpacketswitching.Forexample,tokeepuptoalinerateof40Gbps,apacketforwardingenginemustperform125millionsearchespersecond,assumingtheminimumIPv4packetsizeof40bytes.Itwasfoundthatabout62%oftherouterpowerconsumptionhappensinthepacketforwardingengine.Withthegrowingtrendofnetworkusage,thetotalenergyconsumptioninroutersisonlygoingtogetworse.Forexample,withthecurrentgrowthrateofInternettrafcat40%peryearinJapan,itisprojectedthatbytheyear2022,theenergyconsumptionwillexceed10,000TWhwhichwasthetotalenergyproducedinJapanin2005[ 40 ].Thus,unlesswecanmakeroutersfarmoreenergyefcient,routersmaysoonconsumemostoftheproducedenergy.Thismakesthedesignoflowpowerpacketforwardingenginesessential. 22

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1.5TernaryContentAddressableMemoriesOurresearchisfocussedonreductionofenergyconsumptioninapacketforwardingenginethatusesaparticulartypeofmemorycalledTCAMwhichistheacronymforTernaryContentAddressableMemory.ATCAMisdifferentfromaconventionalmemoryinthat,eachbitmaybesettooneofthethreestatesnamely,0,1,andx(don'tcare).Thismakesitparticularlyconvenienttostorethedestinationprexesalongwiththeirtrailingsequenceof`x's.ATCAMhasanassociatedSRAMwhichisusedtostorethenexthops.ATCAMoftenhasapriorityencodertochoosethebestmatchamongmultiplematches.TCAMsareattractiveforuseinedgeandcorerouters,becauselikeanassociativememory,TCAMsenableaparallelsearchacrossalltherulesandcompleteatablelookupinoneclockcycle.EventhoughTCAMssupporthigh-speedlookups,theyarepowerhungry.So,alotofresearchhasbeendonetoreducethepowerconsumptionbothinthehardwareandsoftwaredomains. 1.6ContributionsThisthesispresentslowpowerdesignstrategiesforpacketforwardingandclassicationinTCAMbasedrouters.Specically,therearefourmaincontributions,asdescribedbelow.1.WeproposeamethodologyforpacketforwardingtablesthatcompactsthetableandthenstorestheprexesinTCAM,leadingtosignicantreductioninTCAMpowerandspaceconsumption.WeproposetheuseofaminimumsetofrulesequivalenttothoseinthegivenforwardingtablecoupledwiththewideSRAMstrategyof[ 21 ].WeintroducethenotionofaternarytrietorepresentthelogicallyminimizedprexesandalsopresentalgorithmstonormalizeandcarvethetrietollupatwolevelTCAMarchitectureusingwideSRAMwords.Sinceinourschemewegetsufxeswith`x'bitsinthemweproposeanewformatforstoringtheseternarysufxesintheSRAM.Weperformbatchupdatestothesetofrulestoaccommodatetheincoming 23

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routeadvertisements.Thelowpowerlookupschemesaregenerallynotsuitableforincrementalupdates.2.WedevelopanewdualTCAMarchitecture,generallyreferredtoasDUO,forpacketforwardingtablesalongwithadvancedmemorymanagementschemesfortheTCAMs.TheadvantageofDUOisthatitsupportsincrementalupdateswhilestillsupportinglowpowerTCAMlookup.ThememorymanagementschemesresultinfewermovescomparedtoexistingTCAMmemorymemorymanagementschemes.3.Weformalizetheconsistencypropertiesofincrementallyupdatedpacketclassierswhenupdatesarriveinclusters.Theupdatesarrivinginaclusterarearrangedinaconsistentsequencethatleadstoproperpacketforwardingandclassication,withthesameresultsasiftheupdateswereappliedallatatimeinabatch.Wedeneandanalyzerequirementsandpropertiesfortwotypesofconsistency,namely,batchconsistencyandincrementalconsistency.Werepresenttheclusterofupdatesusingaprecedencegraphandobtainbatchconsistentsequencesastopologicalorderingsofverticesoftheprecedencegraph.Weshowthatitisnotpossibletoconstructaprecedencegraphrepresentationforallincrementalconsistentsequences.Wealsopresentaheuristictoobtainanearoptimalbatchconsistentsequenceasatopologicalorderingoftheprecedencegraph.Here,optimalityisdenedwithrespecttotheincreaseinsizeoftheintermediateruletable,whereanoptimalsequenceguaranteesminimumincreaseinthemaximumtablesize.4.WedevelopadualTCAMarchitectureandalgorithmsforstoringpacketclassiers.TheadvantageofusingtwoTCAMsinsteadofoneissupportforefcientincrementalupdatesandlowpowerTCAM-lookups.5.Wedevelopanindexed,tripleTCAMarchitectureaugmentedwithwideSRAMsforpacketclassiersthatleadtolowpowerlookups,inadditionto,efcientincrementalupdates.TheusageofwideSRAMsalleviatestherangeexpansionproblemforclassierstoalargeextent. 24

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1.7ThesisOverviewTheremainderofthisthesisisorganizedasfollows.Chapter2describeshowvariousexistingtechniquesforpowerreductioninTCAMssuchasreductioninforwardingtablesize,usinganindexTCAMandwideSRAMs,maybecombinedeffectivelytoresultinPETCAM,withsignicantreductioninTCAMpowerduringprexlookupinpacketforwarding.Proofsforequivalenceoforiginalprexsetandreducedprexsetaregiven.Chapter3presentsDUO,whichisadualTCAMarchitectureforstoringincrementallyupdatablepacketforwardingtables.Detailedmemorymanagementalgorithmsforincrementalupdatesarepresentedinthischapter.Theupdateperformanceandpowerconsumptionarecomparedwithexistingtechniques.Chapter4presentsascheme,CONSIST,forapplyingupdatesconsistentlyonpacketclassiersandforwardingtables.Thisresultsinfewerpacketsbeingsub-optimallyclassiedandfewerpacketsbeingforwardedtosub-optimalnexthops,aslookupsandincrementalupdateshappensimultaneously.Chapter5presentsPC-DUOS,aTCAMarchitecturesforpacketclassiersandtheassociatedupdatealgorithms.AnotablefeatureofPC-DUOSisitsefcientincrementalupdatealgorithms.Chapter6presentsanenhancedversionofPC-DUOS,PC-DUOS+,whichemploysmoreefcientincrementalupdatealgorithms.AdetailedcomparisonbetweenPC-DUOSandPC-DUOS+ismadeinthischapter.Chapter7presentsPC-TRIO,whichisthetripleTCAMarchitectureaugmentedwithwideSRAMs,forpacketclassiers.Finally,weconcludeinChapter8. 25

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CHAPTER2PETCAM:APOWEREFFICIENTTCAMFORFORWARDINGTABLESThemainchallengeofusingTCAMsinroutersisthepowerconsumptioninthesememorychipsduringalookup.Thischapterpresentsamethodologytoprocessandstoreforwardingtablesinarouterinamannerthatleadstoaverylowpowerconsumptionperlookup.Thechapterisorganizedasfollows.InSection 2.1 ,wewilllookattheexistingtechniquesusedforcoolerTCAMsandpresentdenitionsfortermsusedhere.Later,inSection 2.2 wewillpresentdecienciesinexistingschemesandinSection 2.3 weshowhowourPETCAMmethodologysolvestheseissuesandhelpstobringdownthepowerconsumptioninTCAMs,andnallyconcludeinSection??. 2.1BackgroundandRelatedWorkAlotofresearchhasbeendonetoimprovethepowerefciencyofTCAM-basedroutingtables[ 2 20 21 32 35 54 55 ].Shahetal.[ 41 ]proposetwoalgorithmsforincrementalupdatestotheTCAMtablewhilekeepingthenumberofprexmovessmallintheworstcase.Wangetal.[ 54 ]presentanalgorithmforconsistentandincrementalupdatestoTCAMs.Dravesetal.[ 14 ]andSurietal.[ 49 ]haveproposeduseofdynamicprogrammingtoremoveredundanciesinaforwardingtablebycomputingequivalentforwardingtablewithminimalnumberofprexes.Wedescribetheresultsreportedin[ 20 21 35 55 ]inthissectionasthesearemostrelevanttotheworkwereportinthischapter.Wedenefourtermsthatwillbeusedforouranalysis. Denition1. P1P2iffaddr(P1)addr(P2),whereaddr(P)isthesetofaddressesmatchedbyprexP.NotethatP1P2iffP2isaproperprexofP1. Denition2. Arule(P1,H1)isTypeIredundantiff(a)thereexistsarule(P2,H2)suchthatP1P2andH1=H2and(b)thereisnorule(P3,H3)suchthatP1P3P2andH36=H1. 26

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Denition3. Ageneralizedprexisasequencecomprisedofthesymbols0,1,and`x'(don'tcare)andpossiblyterminatedbythesymbol*(1ormoredon'tcares).Asimpleprex(orsimply,prex)isageneralizedprexthathasnooccurrenceofthesymbol`x'.(Alternatively,wemaylimittheoccurrenceofthesymbol`x'totherightendofthesequence.Notethat`x'sattherightendofasequencemaybereplacedbya*sothatthesequence10xxxmayberegardedasasimpleprexbyrewritingitas10*.)Forexample,xx1xx0*andxx100x11*aregeneralizedprexes.Inroutingtableapplications,ageneralizedprexmaybestoredinawordofTCAMbyreplacing*withasuitablenumberof`x's. Denition4. Twosetsofgeneralizedprexesareequivalentifftheymatchthesameaddresses.Liu[ 20 ]proposestwoschemespruningandmaskextensiontocompacttherulesofaroutingtable.Inpruning,ruleswithtypeIredundantprexesareeliminatedfromtheruletable.ItiseasytoseethattheeliminationoftypeIredundantprexesdoesnotchangethenext-hopdecisionforanydestinationaddress.Followingthepruningprocess,eachset,S,ofprexesthathavethesamelengthandthesamenexthop,issubjectedtomaskextensioninwhichSisreplacedbyasetofgeneralizedprexesTsuchthatjTjjSj.ThiscompactionprocessmayleadtoinaccuratebehaviorasdescribedinSection 2.2.1 .Ravikumaretal.[ 35 ]extendtheworkof[ 20 ]andproposethe2-levelEaseCAMarchitectureforroutingtables.ForanIPv4routingtable,therstlevelstores8-bitsub-prexes.Prexesthathavethesamerst8bitsdeneaprexcluster.Pruning,prexaggregation,andprexexpansionareusedtoreplacethesimpleprexesineachclusterwithasmallersetofgeneralizedprexeswiththepropertythatasearchoftheTCAMsegmentthatcontainsthissmallersetofgeneralizedprexesresultsinthesamenexthopasdoesasearchintheTCAMsegmentfortheoriginalclusterofsimpleprexes.Sincethegeneralizedprexesinaclusterhavethesamerst8bits, 27

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itisnecessarytostoreonlytheremaining24bitsofeachgeneralizedprexinthesecond-levelTCAM.Consequently,second-levelTCAMwordsare25%smallerthantheTCAMwordsinthedesignof[ 20 ].Prexesshorterthan8bitsarestoredinaseparatebucket.Section 2.2.2 describeshowthismethodcanleadtoincorrectpacketforwarding.Zaneetal.[ 55 ]proposetwoschemestoachievepowerreduction.Intherst,afewbitsofeachprexareusedtopartitiontheprexsetsothateachpartitionagreesontheseselectedbits.Thebitsarecalledthepartitionselectorbits.Prexesinthesamepartitionarestoredtogetherindecreasingorderoflength.Tosearchforthelongestmatchingprexforagivendestinationaddressd,thepartitionselectorbitsareextractedfromdandusedtodeterminewhichpartitionistobesearched.AlthoughallprexesofanuncompactedroutingtablearestoredintheTCAM,powerreductionresultsfromhavingtosearchonlyonepartition1.ThesecondstrategyproposedbyZaneetal.[ 55 ]isa2-levelTCAMarchitectureinwhichtherstlevelTCAMisanindextothepartitionsinthesecondlevelTCAM.Thepartitionsandindexareconstructedbydecomposingthebinarytrierepresentationoftherouting-tableprexes.ThemostrecentworkonTCAMpowerreductioninthecontextofroutingtablesappearstobethatofLuandSahni[ 21 ].Theyaugmentthetraditional1-levelTCAMlookupstructureaswellasthe2-levelTCAMstructureofZaneetal.[ 55 ]withwideSRAMsandstorethesufxesofseveralprexesinasinglewideSRAMword.ThisenablesareductioninbothpowerconsumptionandtotalTCAMmemoryrequirement.Ourproposedapproachcansignicantlyimprovebothareaandpowerrequirementscomparedtoexistingtechniques. 1ThepowerrequiredbyaTCAMlookupisproportionaltothetotalnumberofbitsintheTCAMpartitionthatissearched. 28

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2.2DecienciesinPrexPreprocessingThissectionillustratesthedecienciesintwoofthecloselyrelatedapproachesthatmayleadtoincorrectpacketforwarding. 2.2.1IssuesRelatedtoMethodsofLiuAsnotedinSection 2.1 ,whenlogicminimizationisappliedtoasetofsame-hopsame-lengthprexes,wegetasetofgeneralizedprexes.TheplacementofthegeneralizedprexesintheTCAMisnotdirectlyaddressedin[ 20 ],andanincorrectplacementwillresultinreturnofincorrectnext-hop.Forexample,A=f000,001,010,011goptimizestoB=f0g.Whileitmaybenaturaltoassign0*alengthof1,suchalengthassignmentcanresultinanincorrectnexthopcomputation.Toseethis,supposethatthenexthopassociatedwiththeprexesofAisH1andthattheroutingtablehasanotherprex00whosenexthopisH2andH16=H2.WhenusingtheoriginalprexsetC=f000,001,010,011,00gasrepresentedbythetrieinFigure 2-1 ,packetswithdestinationaddressbeginningwith000aresenttoH1.Considerwhathappens Figure2-1. TrieforexampleprexsetC=f000,001,010,011,00g.Packetwithaddress000*isforwardedtonexthopH1. whenweapplythecompactionschemeofLiu[ 20 ].SinceChasnotypeIredundancy,pruningdoesnotweedoutanymemberofC.MaskextensioncompactsAtoB.So,thecompactedprexsetisD=f0,00gwith0*havingH1asitsnexthopand00*havingH2asshowninFigure 2-2 .UsingtheprexsetDandenteringprexesinTCAMinorderoflength,packetswithdestinationaddressesthatbeginwith000aresenttoH2! 29

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Figure2-2. TrieforprexsetinFigure 2-1 ,afterlogicminimization.Packetwithaddress000*isforwardedtonexthopH2! WhilethisissuecanbexedbyplacingthegeneralizedprexesintheTCAMinorderoflengthofthecorrespondinginputprexestomaskextension(so0*isassignedlength3andplacedintheTCAMbefore00*),wediscussinSection 2.3.1 astrategysuchthatmaskextensionwilloutputageneralizedprexsetthatisequivalenttotheinputprexsetwithanintuitivedenitionoflength,andhencethegeneralizedprexsetwillresultincorrectpacketforwardingwhentheprexesarearrangedinlengthorder. 2.2.2IssuesRelatedtoEaseCAMEaseCAM[ 35 ]hastwoimportantsteps:prexaggregationandprexexpansion.Theremainderofthissectiondescribeshoweachofthesestepscancausefunctionalinaccuracies. 2.2.2.1PrexaggregationInprexaggregation,prexesthathavethesamehopareaggregatedintoclusterswitheachclustercontainingprexesthathavethesamecommonsub-prex.Thecommonsub-prexlengthisconstrainedtobeamultipleof8.So,forexampleiftwoprexesthathavethesamenexthopagreeontheirrst18bitsonly,thentheywillbeinaclusterofsame-hopprexesthatagreeontheirrst16bits.Logicminimizationisthenappliedtoeachcluster.Sincetheprexesinaclusterhavedifferentlength,thereappearstobenoreasonablewaytodeterminewheretoplacethegeneralizedprexesthatresultfromlogicminimizationintotheTCAMsoastocorrectlyroutepackets. 30

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NeitherofthelengthresolutionmethodsproposedformaskextensioninSection 2.2.1 workwhenaggregationisemployed.Forexample,considertherulesetf(1*,A),(10*,B),(101*,A)g,wheretherst8bitsofeachprexareomittedandarethesame.Thereisnoredundantrule,sonoruleiseliminatedintheinitialpruningstep.Intheaggregationstep,1*and101*formaclusterand10*isinadifferentclusterasithasadifferentnexthop.Logicminimizationreducestherstclusterto1*andhasnoeffectonthesecondcluster.Thenewrulesetisf(1*,A),(10*,B)g.1*wasderivedfromaprexoflength1andoneoflength3.Neitherlengthassignment1or3for1*allowsthenewrulesettoworkliketheoriginalruleset.Forexample,withthenaturallengthassignmentof1to1*,packetsdestinedto101*addressesgetroutedtoBratherthantoA;withalengthassignmentof3,packetsto100*getsenttoAratherthantoB! 2.2.2.2PrexexpansionEaseCAM[ 35 ]proposesusingprexexpansionwithinanaggregatedclustertoimprovecompactionandruntimeperformanceoflogicminimization.Inprexexpansion,shortprexesinaclusterarereplacedbyasetofprexeswhoselengthequalsthatofthelongestprexinthecluster.So,followingprexexpansion,allprexesinaclusterhavethesamelength.Sincelogicminimizationisfasterwhentheinputprexesareofthesamesize,runtimeefciencyisachieved[ 35 ].Intheexampleclusterf1*,101*gofSection 2.2.2.1 ofprexeswithsamenexthopA,prexexpansionyieldstheclusterf100*,101*,110*,111*g,whichisreducedto1*bylogicminimization.Thenewrulesetisf(1*,A),(10*,B)g,which,asnotedinSection 2.2.2.1 cannotbemadetoworkthesameastheoriginalruleset. 2.3PETCAMFigure 2-3 showstheoverallowofourPETCAMconstructionalgorithm.TherstphaseistheprexcompactionphasewhichresultsinasetofgeneralizedprexesandisexplainedinSection 2.3.1 .Inthesecondphase,thesetofgeneralizedprexesisstoredinroutermemoryintheformofaternarytrie.Thisrepresentationisexplained 31

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inSection 2.3.2 .Thethirdphaseistheapplicationofacarvingheuristictocarveout1-bitsubtreesfromthetrie.Theinformationina1-bitsubtreeisstoredinaparticularstructurecalledthesufxnode.ThestructureofasufxnodeandourcarvingheuristicarepresentedinSection 2.3.3 .Finally,thefourthphasedealswithstoringandupdatingtheprexesandsufxnodesinaTCAMandSRAMsystemwhichisdescribedinSection 2.3.4 Figure2-3. FlowdiagramforPETCAMconstruction 2.3.1CompactionofPrexSetOurgoalhereistocompacttheprexset.Towardsthatend,werstapplyadynamicprogrammingalgorithm[ 14 ]whichcompactstheprexsettoaoptimalprexsetremovingallredundancies.Toobtainfurtherreductioninsize,weapplylogicminimizationusingmaskextension[ 20 ]ontheoptimalprexset.Acombinationofthesetwotechniquesreducestheprextablesizesignicantly,asisalsodemonstratedinourexperiments.AlgorithmCompactinFigure 2-4 showsthetwoimportantstepsincompactionofprexset.WewillprovethatthesetofgeneralizedprexesobtainedusingCompactisequivalenttotheinputprexsetintheoriginalroutingtableinthissubsection. 32

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Algorithm:CompactInput:OriginalPrexSetOutput:CompactedPrexSetStep1:Transformthegivenroutingtabletoanequivalentoptimalroutingtableusingthedynamicprogrammingalgorithmof[ 14 ].Step2:Usemaskextension[ 20 ]toreducethenumberofprexesintheoptimalroutingtableobtainedinStep1.ReturnCompactedPrexSetFigure2-4. Algorithmforcompactionofaprexset Denition5. Arule(P1,H1)isTypeIIredundantifftheroutingtablecontainsasetofrulesf(P2,H2),,(Pk,Hk)gsuchthatjP1j
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Forexample,R=f0*gisacanonicalequivalentsetforS=f01*,00*g.However,eventhoughR=f0001*,00x0*,0011*gandS=f000*,001*gareequivalent,RisnotacanonicalequivalentsetforS.Forexample,0001*isnotthesumofanysubsetoftheSqs. Theorem2.1. LetRandSbeasinDenition 6 .ThereexistsacanonicalequivalentsetforSthathasthesamenumberofgeneralizedprexesasdoesR. Proof. ConsideranRiinR.LetRi=Ri1+Ri2++Riq(i)betheGPDofRi.SinceRandSareequivalentandprexesofthesamelengtharedisjoint(i.e.,havenocommonmatchingaddress),thereisexactlyonef(i,j),1f(i,j)s,suchthatRijandSf(i,j)arenotdisjoint,1ir,1jq(i).Weconsider3cases. Case1:IfjRij=jS1j,Rij=Sf(i,j)foralljandsoRiisthesumofsomeoftheSqs. Case2:IfjRij>jS1j,letRibetherstjS1jbitsofRi.So,theaddressesmatchedbyRiareasubsetofthosematchedbyRi=Ri1+Ri2++Riq(i)=Sf(i,1)+Sf(i,2)++Sf(i,q(i)),whereRijisobtainedfromRijbytruncatingthelastjRij)-260(jS1jbits.SinceRimatchesnoaddressnotmatchedbyS,replacingRibyRiinRpreservestheequivalencebetweenRandSanddoesn'tincreasethenumberofRisinR.WemayusethisreplacementtransformationasoftenasneedtoreplaceallRisinRwhoselengthismorethanjS1jincreasethenumberofRisinR.WemayusethisreplacementtransformationasoftenasneedtoreplaceallRisinRwhoselengthismorethanjS1jwithRiswhoselengthequalsjS1j.FromCase1,itfollowsthateachofthereplacingRisisthesumofsomeoftheSqs. Case3:WhenjRij
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canonicalequivalentsetwiththesamenumberofgeneralizedprexes.So,henceforth,weassumethatminimizationalgorithmsreturncanonicalprexes. Theorem2.2. LetUbeasetofrulescomprisedofsimpleprexesthatisfreeoftypeIIredundancies.LetVbethesetofrulescomprisedof(canonical)generalizedprexesobtainedfromUbyapplyinglogicminimizationtotheequal-lengthsame-hopprexesofUasisdoneinmaskextension[ 20 ].LongestprexmatchinginUandVresultsinthesamenexthopforeverydestinationaddressA. Proof. SupposethereisanaddressAforwhichthelongestmatchingsimpleprexinUisU1withnexthopH1andforwhichthelongestmatchinggeneralizedprexinVisV2withnexthopH2andH16=H2.LetV21betheprexofGPD(V2)thatmatchesA.NotethatsinceallprexesinGPD(V2)havethesamelength,theyaredisjointandsoexactlyoneofthesematchesA.Further,letU2betheprexofCD(V21)thatmatchesA.Again,exactlyoneprexofCD(V21)matchesA.SinceU1isthelongestprexofUthatmatchesA,jU1j>jU2j.LetV1bethegeneralizedprexofVsuchthatV112GPD(V1)matchesAandU12CD(V11).SuchaV1mustexistinVbecauseofthewayVisconstructedfromUusinglogicminimization.SinceV2isthelongestmatchinggeneralizedprexforAinVandV1alsomatchesA,jV21j=jV2jjV1j=jV11j.Now,sincetwoprexesareeitherdisjointornestandsinceU1,U2,V11,andV21matchA,addr(U1)addr(U2)addr(V21)addr(V11)FromthisandtheobservationthatallprexesinCD(V11)areofthesamelengthandhencearedisjoint,itfollowsthatsomesubsetofCD(V11)thatincludesU1sumstoU2.Hence,U2istypeIIredundant. FromTheorem 2.2 ,itfollowsthatifwestartwithasetoforiginalprexesthatcontainsnotypeIIredundancy,applylogicminimizationtoobtaingeneralizedprexes,thenthesetofgeneralizedprexesisequivalenttothesetoforiginalprexes.ThusinthecontextofPETCAM,thesetofgeneralizedprexesisequivalenttotheset 35

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ofprexesintheoptimalroutingtable.Theprexesintheoptimalroutingtable,ontheotherhand,areequivalenttotheoriginalsetofprexes[ 14 ].Hence,thesetofgeneralizedprexesinPETCAMisequivalenttothesetofprexesintheoriginalroutingtable.Thus,whenthesegeneralizedprexesareenteredintoaTCAMindecreasingorderoflength,thenlookupsyieldthesamenexthopsaswhenweloadtheTCAMwiththeoriginalprexsetinlengthorder,wherethelengthofageneralizedprexisintuitivelydenedastheindexoftherightmostsymbolthatisnota`x'ora*.So,thelengthofxx01*is5andthelengthofxx00xx1*is7.Thisisconsistentwiththeaccepteddenitionofthelengthofasimpleprexwhere,forexample,thelengthof*is3.WeusethenotationjGjtodenotethelengthofageneralizedprex.InourexampleprexsetCinSection 2.2.1 andFigure 2-1 ,theprex00*isTypeIIredundantandhenceisremoved.ThenlogicminimizationisappliedtotheprexsetandnallyaprexsetB=f0gisobtainedthatisequivalenttoC. 2.3.2RepresentationusingTernaryTriesTomapthegeneralizedprexesthatresultfromsteps1and2ofourPETCAMconstructionalgorithmwerstconstructaternarytrie2.Table 2-1 showsanexampleroutingtablefollowingsteps1and2ofourPETCAMconstructionalgorithm.Figure 2-5 showsthecorrespondingternarytrie. Table2-1. Routingtablewithgeneralizedprexes AddressNextHop 1x0H1200x0H2300x1H341100H4511x1H5 2Aternarytriediffersfromabinarytrieinthateachnodeofaternarytriemayhaveupto3childrendependingonwhetherthebranchingbitisa0,1,or`x'. 36

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Figure2-5. Ternarytriefortherouting-tableofTable 2-1 Anormalizedternarytrieisaternarytrieinwhicheachnodethatisthex-child(i.e.,thedon'tcarechild)ofitsparenthasnosibling.So,inanormalizedternarytrie,thechildrenofdegree2nodesare0-and1-children,thechildofadegree1nodemaybea0-,1-,orx-child,andtherearenodegree3nodes.Aternarytriemaybenormalizedbyeliminatingthex-childofeachdegree3nodebymergingthesubtreerootedatthisx-childwiththesubtreesrootedatthetwosiblingsofthisx-child.Forexample,intheternarytrieofFigure 2-5 ,therootisadegree3nodeandthesubtreerootedatitsx-childmaybemergedwiththesubtreerootedattheroot's0-childaswellaswiththatrootedattheroot's1-childtoobtaintheternarytreeofFigure 2-6 .OnemayverifythattheternarytriesofFigures 2-5 and 2-6 areequivalentinthatbothrouteallpacketstothesamenexthop.ThetrieofFigure 2-6 isnotyetanormalizedternarytrieasitcontainsanx-childthathasasibling(i.e.,thex-childwithQ(R)=11x).Thissubtreerootedatthisx-childmaybemergedwiththatrootedatits0-siblinganditsempty1-siblingtoobtainthenormalizedternarytrieofFigure 2-7 .Figure 2-8 showsouralgorithmtonormalizeaternarytrie.Thisalgorithmassumesthateachnodeyofaternarytriehas3childreneldswithy.child[0]andy.child[1]pointingtothe0-and1-childrenofnodeyandy.child[2]pointingtothex-childofnode 37

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Figure2-6. Ternarytrieaftermergingofthex-childofroot Figure2-7. Normalizedternarytrie y.Thealgorithmemploystwootheralgorithmsdelete,whichdeletesasubtreegivenitsrootandmerge,whichmergestwosubtreestogether.Wedonotfurtherspecifydeleteasthisisasimplepostordertraversal.AlgorithmmergeisspeciedinFigure 2-9 .Inalgorithmmerge,oChildandxChildarechildrenofparent,where,xChildisthex-childwhileoChildistheoChildID-child.NoticethatwhenwestartwithaprexsetthathasnotypeIandIIredundanciesandperformmaskextension,atmostoneofoChildandxChildmayhaveanon-nullnexthop.Further,notethatanoptimalprexsetisdevoidoftypeIandtypeIIredundancies. 38

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Algorithmnormalize(root)fif(!root)return;if(root.child[2])fif(root.child[0]jjroot.child[1])fmerge(root,root.child[0],0,root.child[2]);merge(root,root.child[1],1,root.child[2]);delete(root.child[2]);root.child[2]=NULL;ggnormalize(root.child[0]);normalize(root.child[1]);normalize(root.child[2]);gFigure2-8. Algorithmtonormalizeaternarytrie Algorithmmerge(parent,oChild,oChildID,xChild)fif(!xChild)return;if(!oChild)foChild=newnode;oChild.nextHop=xChild.nextHop;parent.child[oChildID]=oChild;gelsefif(xChild.nextHop)thenoChild.nextHop=xChild.nextHop;gmerge(oChild,oChild.child[0],0,xChild.child[0]);merge(oChild,oChild.child[1],1,xChild.child[1]);merge(oChild,oChild.child[2],2,xChild.child[2]);gFigure2-9. Algorithmtomergeanx-subtree 2.3.3CarvingTrietoCreateSufxNodesOurcarvingheuristicstartswiththenormalizedternarytrieforthecanonicalprexesthatresultwhenmaskextensionisdoneonanoptimalprexset.Thecarvingofanodeinthenormalizedternarytrie,generatesaprex(representedbybitsinpathfromtheroottothecarvednode)anda1-bitsubtreeofsufxes.The1-bitsubtreeofsufxesisencodedinaformat,alsocalledthesufx-nodestructurewhichisexplainedbelow. 39

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Figure2-10. Sufxnodeof[ 21 ]witha5-bitmatchstartpositioneldandrepresentationoftherstsufx. Table2-2. Anexample6-prexforwardingtable PrexesNextHop R1*H1R20*H2R31*H3R401*H4R5010*H5R6111*H6 2.3.3.1Sufx-nodestructureOursufx-nodestructureismotivatedbythestructurein[ 21 ]andwedevelopnecessaryadaptationstoaccommodategeneralizedprexesandparallelsufxmatching.Forthis,weneedtomodifythestructureofasufxnodeaswellasdevelopanalgorithmtomapsufxesintosufxnodes.Beforedevelopingtheseadaptations,weprovideabriefoverviewofthethemotivationbehindcreatingsufx-nodesandthesufx-nodestructureitself.TheuseofwideSRAMsinconjunctionwithTCAMsreducespowerconsumptionandincreaseseffectiveTCAMcapacity.Whereasanexthopcanoftenbeencodedusing10to12bitswecanfetch,inasinglememoryfetchcycle,72bitsfromaQDRIISRAMindualburstmodeand144bitsinquadburstmode.Further,giventheordersofmagnitudediscrepancybetweenthetimeforanSRAMfetchcycleandthetimetoperformanarithmetic,itispossibletodosignicantprocessingofthedatastoredinawordofawideSRAMinmuchlesstimethanittakestofetchthatwordofdatafromtheSRAM.Tocapitalizeontheseobservations,thesufxesofseveralprexesthatareinthesamesubtreeofthebinarytriefortheforwardingtableprexesarepackedintoasufxnode,whichisthenstoredinoneormoreSRAMwordsinsuchawaythattheentiresufxnodemayberetrievedinasinglememorycycle.Figure 2-10 showsthe 40

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Figure2-11. SixrulesofTable 2-2 storedinTCAM+SRAM Figure2-12. Sufxnodeexample structureofthesufxnodeof[ 21 ].Wehaveaddeda5-bitmatchstartpositioneldwhichindicatethebitpositioninthedestinationprexfromwheresufxmatchingcanstartforallsufxesencodedinthesufxnode.Thesufxcounteldgivesthenumberofsufxespackedinthesufxnode.ForeachsufxSistoredinasufxnode,wekeepthesufxlength,len(Si),thesufx,Si,andthenexthopassociatedwiththesufx.Usingthesufxnodecreationscheme,eachsufxnodemusthaveexactlyonesufxoflength0.Thissufxcancomefromeitheraprexthatisstoredintherootofthesubtreethatiscarvedtoformthesufxnode,oracoveringprexwhichisinheritedfromthenearest Figure2-13. TypeIsufxnode 41

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Figure2-14. TypeIIsufxnode ancestorwithaprexincasetherootofthesubtreedoesnotstoreaprex.TooptimizeSRAMusagefurther,westorethissufxastherstsufxinthenode,andsinceithasalength0,wedropthesufxlengtheldfortherstsufx.Thusasufxoflength0appearsastherstsufxinasufxnode,andisrepresentedonlybyitsnexthop.Figure 2-12 showsthebinarytriefortheprexesofTable 2-2 togetherwithamappingoftheseprexesintoasimpleTCAMwithwideSRAM.Forthisexample,weassumeanSRAMwordwidthof32bitswith2bitsallocatedforthematchstartpositioneld(allowingprexestobeoflength5bits),2bitsallocatedforthecounteldofasufxnode(permittingupto4sufxestobestoredinanode),2bitsforthesufxlengtheld(permittingsufxesoflengthbetween0and3),and12bitsforthenext-hopeld(permittingupto4096differentnexthops).Intheworst-case,asufxnodestoresasinglesufxoflength0,forwhichanexthopeldof12bitsisusedalongwiththematchstartpositionandsufxcountelds,utilizingonly16ofthe32bits.Inthebestcase,wemaystoreasufxoflength0andoneoflength2resultingintheutilizationofall32bitsinthenode.Theallocationofsufxestosufxnodesisdonebycarvingoutsubtriesofthebinarytriefortheprexset.Forexample,fromthebinarytrieofFigure 2-12 ,werstcarveoutthebinarytrierootedatnodeA.ThepathfromtheroottoAisQ(A)=01.Q(A)isstoredintheTCAMandthesufxes*(length0)and0*(length1)thatresultfromeliminatingQ(A)fromthefrontofeachprexinthecarvedsubtriearepackedintoasufxnode.Thiscarving-packingprocessisrepeatedatnodesB,C,andDresultinginthesufxnodesofFigure 2-12 .Whencarvingisdoneatanode,sayR,whosesubtreedoesn'tcontainamatchingprexforeverydestinationaddressthatbeginswithQ(R)(thatis,thereisnonexthopstoredatthenodeR),weaddacoveringprexintothesufxnodeforthiscarving.ThecoveringprexfornodeR,whichisstoredasa 42

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sufxwhoselengthis0istheprexinthenearestbinarytrieancestorofR.Assumingthateachroutingtablecontainsthedefaultprex*,eachnodeofthebinarytriehasawelldenedcoveringprex.AnexampleofRinFigure 2-12 ,isthenodeB,sinceitdoesn'tcontainanexthop.Theremainingthreenodes:A,CandDwhicharecarved,eachhasanexthopspecied.Thus,coveringprexfornodeBofthebinarytrieofFigure 2-12 isprex1*thathasanexthopofH3.So,forexample,thenexthopforanaddress1101*willbeH3.Inpractice,westoreacoveringprexwhenevertherootofthecarvedsubtreedoesnotcontainaprex.Hence,everysufxnodehasaprex,itsrstone,whoselengthis0.TheQ(R)sandassociatedsufxnodesareassigned,respectively,toTCAMandSRAMwordsindescendingorderoflength.ForPETCAMweneedtodeneanewformatforasufxnodeaswellasformulateanalgorithmtopopulatesufxnodeswiththesufxesofgeneralizedprexes.Ournewsufx-nodestructurehasa1-bittypeeldthatpermitstheuseoftwovariants.AtypeIsufxnodeisusedtostoresimplesufxesexclusively(i.e.,allsufxesinatypeIsufxnodearecomprisedof0sand1s).Suchasufxnodeisstructuredthesameasthesufxnodeof[ 21 ]exceptfortheadditionofatypeeld(Figure 2-13 ).AtypeIIsufxnode(Figure 2-14 )storesamixofsimpleandnon-simplesufxes(i.e.,sufxesthathaveatleastonedon'tcarebit).Simplesufxesarestoredrstusingtriples(length,sufx,nexthop)asusedinFigure 2-13 .Thesetriplesarefollowedby4-tuples(length,sufx,mask,nexthop)thatrepresentnon-simplesufxes.Thesufxandmaskentriesareofthesamelengthandthe1sinthemaskidentifythedon'tcaresinthesufx.Forexample,thesufxx0x1mayberepresentedbythesimplesufx0001andthemask1010,forexample.Theindexeldgivestheindexoftherstnon-simplesufx.So,forexample,ifwehave2simplesufxesand3non-simplesufxesinatypeIIsufxnode,thecounteldwouldbe5andtheindexeldwouldbe3. 43

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BesideshavingtypeIIsufxnodestoaccommodategeneralizedprexes,oursufxnodestructuregroupsthelengthsofdifferentsufxestogether,sotheycanberetrievedparallelyduringlookup. 2.3.3.2OurcarvingheuristicTocarvethenormalizedternarytrieintosufxnodes,werstcomputethefollowingvaluesforeachnodeyofthenormalizedtrie. 1. y.numPnumberofprexesstoredinthesubtrierootedaty.Thisisequivalenttothenumberofnodesinthissubtriethathaveanon-nullnexthopeld.Lety.h=0ify.nextHopisnulland1otherwise.Itiseasytoseethaty.numPisthesumofthenumPvaluesforitsupto2non-emptysubtreesplusy.h. 2. y.xNumPnumberofnodesinthesubtreerootedatythathaveanon-nullnexthopstoredandthepathfromytoeachofthesenodesincludesatleastonex-childotherthany.Notethatifyhasanx-childitcanhavenootherchildandsoy.xNumPisthenumPvalueofthisx-child.Whenydoesnothaveanx-child,itsxNumPvalueisthesumofthexNumPvaluesofitschildren. 3. y.sizenumberofbitsneededtostorethesufxes(togetherwithsufxcount,nodetype,index(ifrequired),sufxlengths,masks(ifrequired),andnexthops)fortheprexesinthesubtreerootedaty.EachsuchsufxisobtainedbyremovingQ(p)fromthey.numPprexesinthesubtreerootedaty.Incasey.xNumP=0,atypeIsufxnodeisused.Otherwise,atypeIIsufxnodeisused.y.sizealsoincludesthebitsneededtostorethenexthopforthecoveringprexforyincasethisisneeded.Whenacoveringprexisneeded,westoreasufxoflength0alongwiththenexthopassociatedwiththiscoveringprex.Figure 2-15 givesthenumP,xNumP,andsizevaluesforeachofthenodesofthenormalizedternarytrieofFigure 2-7 ,wheresizehereincludesonlyanexthopandsufxbitsforsimplicity.Fortheleafnodesinthisexample,sizeis12sincethereisnosufxbitneededandundertheassumptionthatittakes12bitstostorethenexthop.Fortheparentnodestotheleaves,sizeisthesumofbitsrequiredtostorethenextHopsatthechildrenandasufxbitforeachchild.ThustheparametersnumP,xNumP,andsizearecomputedinabottom-upmanner.Toillustratethecomputationof(numP,xNumP,size)foraninternalnodeintheexampleofFigure 2-15 ,weconsiderthenodeNreachedfromtherootbybit0,andthe 44

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Figure2-15. (numP,xNumP,size)fornodesoftrieinFigure 2-7 subtreerootedatN.Therearethreeprexesinthesubtree(correspondingtonextHopsH1,H2,H3),sonumPis3.Outofthethreeprexes,theonescorrespondingtonexthopH2andH3havea`don'tcare'bitinthem,soxNumPis2.Nextwetakeeachprexonebyonetodeterminesize.ThesufxtobestoredatNfortheprexwithnexthopH1,is.So,numberofbitsneededforthisprexis12+1=13,where12bitsareneededtostorethenexthopH1.ThesufxtobestoredatNfortheprexwithnexthopH2isx0whichdegeneratestosufxbitsandmaskbits.SimilarlysufxandmaskbitsfortheprexwithnexthopH3areandrespectively.ThenumberofbitsneededforthetwoprexesH2andH3isthus:(12+3+3)2=36.Hence,thetotalnumberofbitsis36+13=49.Notethatinthissimpliedexample,wehaveomittedthebitsneededtorepresentthenumberofsufxes,thesufxlengthsorthetypeofthenodes-eachoftheseparametersareallotedaxednumberofbitsinreallife,asgivenbyFigures 2-13 and 2-14 .Tocarveanormalizedternarytrieintosufxnodesthatuseatmostwbitspernode,weperformapostordertraversalofthetrieusingthevisitfunctionofFigure 2-16 ,whichdiffersfromthatof[ 21 ]inthemannerinwhichsizeiscomputedsincecarvingisdoneongeneralizedprexes..Althoughthevisitfunction,asstatedinFigure 2-16 ,doesnotmakeexplicituseofnumPandxNumP,thesevaluesareindirectlyincludedinthe 45

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computationofsize,andthecarvefunctionusesxNumPofnodetobecarvedtodetectwhatkindofsufxnodeistobecreated,TypeIorII.NotethatinFigure 2-16 ,thevalueofy.sizeisitsvalueatthetimeyisvisitedandaccountsforthefactthatseveralofy'soriginalsubtreesmayhavebeencarvedoutbythistime. Algorithmvisit(y)if(y.sizewif(yhasasinglechildz)fcarve(z);return;g//zcouldbe0-,1-orx-child//yhasbotha0-childuanda1-childvif(u.sizev.size)fcarve(v);recomputey.size;if(y.sizev.sizethisissymmetrictothecaseu.sizev.sizeFigure2-16. Visitfunctionforsubtreecarvingheuristic[ 21 ] 2.3.4StoringandUpdatingPrexesinTCAM-SRAMTheprexesandsufxnodesgeneratedasaresultofcarvinganormalizedternarytriecouldbeinsertedinlengthorderina1-levelTCAM-SRAMsystemforlookuptoreturncorrectresults.However,PETCAMusesanadditionalindexlevelwhichreducespowerconsumptionduringlookupbyselectivelyactivatingapartitionofthedatalevelTCAM.WedescribeourPETCAMstructureandanupdateprocedurebelow. 2.3.4.1PETCAMstructureThestructureofPETCAMisillustratedinFigure 2-17 .PETCAMcomprisesa2levelstructure-theindexlevel(ITCAMandISRAM)andthedatalevel(DTCAMandDSRAM)asshownintheFigure 2-17 .TheentriesintheDTCAMaregroupedintoxedsizedpartitionsorbuckets,andtheboldlinesrepresentbucketboundaries.Both 46

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Figure2-17. PETCAMstructure ISRAMandDSRAMhavewidewordsandstoresufx-nodes.Whereasthesufx-nodesinDSRAMstorenexthopcorrespondingtoasufx,thesufx-nodesinISRAMstoreaDTCAMbucketindexfortheDTCAMbuckettobeactivated.WechoosetheM-12Wband1-12Wcprexlayoutschemesdiscussedin[ 21 ]toenterprexesinPETCAMandevaluatebothinourexperimentalsection.M-12Wbschemeisrecommendedin[ 21 ]foroverallmemoryandpoweroptimizationand1-12Wcschemeisrecommendedforpoweroptimization.In1-12Wcscheme,thereisaone-onerelationshipbetweenasufxinISRAMandaDTCAMbucketindex.InM-12Wbscheme,thereisamany-onerelationshipbetweensufxesinISRAMandaDTCAMbucketindex.ThusinM-12Wbscheme,allbucketsexceptthelastonearefullwithprexeswhichleadstobetterutilizationofspace,whereasinthe1-12Wcscheme,aDTCAMbucketmaynotbefulliftherearenotenoughDTCAMprexestollabucketcorrespondingtoanindexprex.Toperformalookup,aninputIPaddressisrstsearchedintheITCAM.ThebestmatchingentryisusedtoaccessthecorrespondingISRAMwordwhichcontainsmultiplesufxes.ThebestmatchingsufxintheISRAMwordisidentiedandtheDTCAMbucketpointedtobythesufxisactivatedforasearch.TheinputIPaddressissuppliedtotheDTCAMtondthebestmatchingprexintheactivatedbucket.TheDSRAMwordcorrespondingtothebestmatchingDTCAMprexisthenanalyzedto 47

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Figure2-18. Relativeefciencyfortablecompaction extracttheappropriatenexthop.Soforpowerconsumptioncalculationsweconsiderthefollowingcomponents:powertosearchthewholeITCAM,powertosearchabucketintheDTCAMwhichdependsonthebucketsizethatischosenbytheuser,powertoreadawordinbothISRAMandDSRAM.ItistobenotedthatITCAMisconsiderablysmallerinsize(fewerentries)comparedtoDTCAM.ThewordsizeoftheDTCAMinFigure 2-17 is32bitsforforIPv4prexes.FortheITCAM,weneedawordsizeof24bitsbasedon(1)thebitallocationschemetosufxnodesinFigure 2-14 ,(2)sufxnodesizeof144bitsfromQDRIISRAMinquadburstmodeand(3)ourchoiceofDTCAMbucketsizeof128prexesbasedonpowerconsumptionresultsin[ 21 ]. 2.3.4.2PETCAMupdatesPETCAMsupportsbatchupdatesratherthanincrementalupdates.Infact,batchupdatingstrategyismoresuitabletotherelatedarchitectures[ 20 21 35 ],noneofwhichprovideefcientsupportforincrementalupdates. 2.4ExperimentalResultsWeimplementedourPETCAMstrategyinC++andcompareditsperformancewiththepowerreductionschemesof[ 20 21 35 ].Thecomparisonwasdoneusing24IPv4 48

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routingtablesdownloadedfrom[ 6 ]and[ 37 ].DatasetsAS65000andrrc00arefromMay2008,AS6447isfromJuly2008,andthedatasetsAS1221andAS4637areearlierthan2008andwereusedin[ 21 ].TheremainingdatasetsarefromFebruary,2009.Table 2-3 showsthenumberofprexesineachofthedatasets.OurexperimentsaimtomeasuretherelativeeffectivenessoftheschemeofLiu[ 20 ](typeIredundancyremovalfollowedbymaskextension)andthePETCAMscheme(usingCompactinFigure 2-4 )tocompacttheroutingtableaswellastheoverallrelativeperformanceofPETCAM,EaseCAM,andthemethodofLuandSahni[ 21 ]withrespecttoTCAMpowerandmemoryreduction.ForourexperimentsweassumetheSRAMwordsize,andhencethesizeofasufxnode,is144bits. 2.4.1CompactionEfciencyThecompactionefciencyismeasuredbythenumberofprexesafterapplyingthecompactiontechniques.Figure 2-18 showsthetherelativeefciencyofprexsetcompactionusingPETCAM,Liu'scompactionscheme[ 20 ]andtypeIIredundancyremovalintegratedinLiu'scompactionscheme(afterremovingtypeIandtypeIIredundanciesandapplyingmaskextension).InPETCAM,Step1oftheCompactalgorithmreducesthenumberofprexesinthedatasetsbybetween45%and79%.Anotherapproximately5%reductionisachievedwhenStep2isexecutedontheoptimalsetofprexesobtainedinStep1.So,overallPETCAMreducesthenumberofprexesbyabout50%to84%.WedonotreporttheresultsofcompactionusingEaseCAM[ 35 ]because,asnotedinSection 2.2.2 ,theseenhancementsdonotguaranteecompactedprexsetsequivalenttotheinputprexset.Foreachofourdatasets,PETCAMismoreefcientintermsofprexcompaction,resultinginfewergeneralizedprexescomparedtothemethodof[ 20 ]. 49

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Table2-3. NumberofroutingtableprexesinPETCAM IndexDataSet#ofprexesIndexDataset#ofprexes 1AS122128151613rrc112771662AS463721011914rrc122784993AS644727550915rrc132849864AS6500025902616rrc142761705rrc0026618517rrc152840476rrc0127679518rrc162826607rrc0328375419rviews22941278rrc0428861020rviews42757379rrc0528004121rviews.eqix27573610rrc0627874422rviews.isc28109511rrc0727509723rviews.linx27819612rrc1027889824rviews.wide283569 2.4.2PowerEfciencyWecomparedthepowerefciencyobtainedusingPETCAMwiththatofEaseCAM[ 35 ]andtheschemesofLuandSahni[ 21 ].Althoughtheprexpreprocessingschemesin[ 35 ]arefaulty,thetwo-levelEaseCAMarchitecture,whichisaspecializationofthebit-selectionarchitectureproposedbyZaneetal.[ 55 ],maybeemployedinconjunctionwithanyprexsettoreduceTCAMpoweraswellastotalTCAMmemory.InEaseCAM,eachTCAMwordis24bitsastherst8bitsofeachprexareusedinthelevel-1indextotheTCAM.Prexesshorterthan8bitsarehandledinaseparatebucketandareignoredinourevaluationofEaseCAM.WestoreprexesinEaseCAMaftermodifyingtheprexpreprocessingschemeasfollows.First,weremovetypeIandtypeIIredundanciestoreducethesizeoftheprextable.Thegroupofprexeswiththesamerst8bitsisfurtherdividedintosubgroupsofprexeshavingthesamelengthandnexthop.EachsubgroupofprexesisthenminimizedusingEspresso.TheminimizedprexesareplacedintheTCAMaccordingtothelengthoftheprexesinasubgroup.Thuslogicminimizationisdoneusingthestrategyof[ 20 ].Thedifferencewith[ 20 ]isthatthelogicminimizationisappliedonsubgroupsofprexeswiththesamerstoctet,lengthandnexthop,whereasin[ 20 ]the 50

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Table2-4. TCAMpower(inmW)forthedifferentschemes DataSetPTMPTWLuMLuWEaseCAM AS122119.1713.534.0315.92041.62AS463713.4111.9328.4414.79391.27AS644719.6213.5732.7715.64662.38AS6500015.5512.5231.615.77528.43rrc0016.3212.7234.7415.7563.25rrc0116.7113.2429.2814.61710.7rrc0317.0912.9127.3514.6350.02rrc0416.8412.9127.614.53317.47rrc0516.5812.7827.5414.21304.09rrc0614.6412.3325.5413.76231.18rrc0715.1612.6526.1213.89285.82rrc1017.4213.128.5114.98346.31rrc1116.012.5226.1914.08290.65rrc1216.7712.9127.3514.15323.46rrc1314.7712.3926.3813.95286.08rrc1416.5112.9727.4114.4368.87rrc1514.3212.3325.3513.76230.79rrc1616.4512.7227.2814.15323.2rviews217.1613.0429.2814.66381.47rviews415.112.5226.0614.02297.97rviews.eqix15.4212.4625.9313.95316.76rviews.isc17.0912.6527.1514.15324.49rviews.linx16.1912.5926.2513.95337.09rviews.wide14.5212.3925.7413.76241.17 logicminimizationisappliedonsubgroupsofprexeswiththesamelengthandnexthop.TogeneratethedataforPETCAM,weemploysteps1and2ofthePETCAMschemeandstoretheresultinggeneralizedprexesina2-levelTCAMsystemusingtheM-12Wblayout.ThesizesofaDTCAMbucketandasufxnodeareset,respectively,to128TCAMprexesand144SRAMbitsforQDRIIquadburstSRAMs.Similarly,toobtaindatafortheschemesin[ 21 ],weusetheM-12Wblayoutor1-12WclayoutaftersettingaDTCAMbucketsizeto128prexesandasufxnodesizeto144bits. 51

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Figure2-19. Comparisonoftotalpower(TCAM+SRAM)amongdifferentschemes WeusedCACTI[ 30 ]andaTCAMpowerestimationtool[ 1 ]on70nmprocess,at1.12Vtoestimatepowerconsumption.Thememoriesareassumedtohaveasingleread-writeport.ThisassumptionworkswellforPETCAM,whichusestwocopiesoftheforwardingtable,oneforlookupandtheotherforupdates.EventhoughEaseCAMpermitsincrementalupdates,theassumptionisreasonablesincetheTCAMwillbeusedforeitherlookuporupdatesatanytime.Simultaneouslookupandupdateviadualportswillentailconsistencyissueswhichneedtobeaddressedseparately.Thusweconsidermemorieswithasingleread-writeport.Table 2-4 presentsthetotalpowerfortheTCAMs(e.g.ITCAMandDTCAMforPETCAM)assumingtheTCAMsarebeingoperatedat360MHz[ 36 ].ThecolumnsmarkedPTMandPTWgivethepowerconsumedbyPETCAMwhileusingprexlayoutschemesM-12Wband1-12Wcof[ 21 ],respectively.ThecolumnsmarkedLuMandLuWgivethepowerconsumedbytheschemesin[ 21 ]whileusingprexlayoutschemesM-12Wband1-12Wcrespectively.ForPTM,PTW,LuMandLuWthetotalTCAMpowerforaroutingtableisobtainedbysummingthedynamicandleakagepowerforasearchinbothITCAMandDTCAM.The 52

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Table2-5. SRAMpower(inmW)forthedifferentschemes DataSetPTMPTWLuMLuWEaseCAM AS122116.8811.1720.7313.2182.39AS463712.069.7319.4112.2719.1AS644717.2511.2322.9513.028.74AS6500013.8610.3519.4913.123.45rrc0014.510.5121.213.0524.84rrc0114.8210.9320.112.1169.51rrc0315.1410.6718.5112.1117.95rrc0414.9310.6718.7312.0615.76rrc0514.7110.5618.6711.7615.28rrc0613.110.1917.0411.3912.03rrc0713.5310.4617.5111.4914.49rrc1015.410.8319.4612.4317.75rrc1114.2310.3517.5611.6514.72rrc1214.8810.6718.5111.716.03rrc1313.2110.2517.7211.5514.49rrc1414.6610.7218.5711.9518.12rrc1512.8410.1916.8811.3912.03rrc1614.6110.5118.4611.715.99rviews215.1910.7820.112.1618.65rviews413.4810.3517.4611.615.0rviews.eqix13.7510.317.3511.5515.77rviews.isc15.1410.4618.3611.716.08rviews.linx14.3910.417.6211.5517.32rviews.wide13.010.2517.1911.3912.5 powerconsumptionisthesameforanylookup.ForEaseCAM,thetotalTCAMpowerforaroutingtableisobtainedbysummingthedynamicandleakagepowerforasearchintheTCAMattherstlevelandforasearchinthelargestpartitionintheTCAMatthesecondlevel,andthereforerepresentsworstcasepowerconsumption.BothschemesinPETCAMconsumedverylowpowercomparedtoEaseCAM.Table 2-5 presentsthetotalSRAMpowerconsumedbyareadaccessoneachSRAM.Figure 2-19 plotsthetotalpowerforeachroutingtable,obtainedbysummingtotalTCAMandSRAMpowerforalookup.Fromthesegures,ifwecompareEaseCAMwithPETCAMusingM-12Wbscheme(PTM),weget88%to98%reductionintotalpower.ComparingEaseCAMwithPETCAMusing1-12Wcscheme(PTW),weget90%to98%reductionintotalpower. 53

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BothTCAMandSRAMpowerconsumptioninPTWisbetween8%to20%ofthatofLuWorLu's1-12Wclayout.ThepowerconsumedbytheSRAMinPETCAMisat Table2-6. TCAMarea(inmm2)forthedifferentschemes DataSetPTMPTWLuMLuWEaseCAM AS12211.672.073.13.874.77AS46370.510.652.342.961.36AS64471.662.133.043.95.22AS650000.941.212.873.642.65rrc001.051.363.254.163.45rrc011.291.673.063.94.78rrc031.181.543.134.03.87rrc041.151.493.184.053.63rrc051.071.363.093.963.33rrc060.760.953.083.942.1rrc070.981.263.043.862.88rrc101.41.813.083.924.02rrc111.041.333.063.93.09rrc121.221.573.073.933.67rrc130.831.073.154.022.9rrc141.221.593.053.893.66rrc150.710.893.134.021.97rrc161.161.463.124.03.47rviews21.331.73.254.144.41rviews40.941.213.053.882.7rviews.eqix1.01.253.053.892.96rviews.isc1.11.453.113.973.21rviews.linx1.091.383.073.923.26rviews.wide0.81.013.134.022.23 most1.4timesmorethanthatofEaseCAM.Forsomeinstances,theSRAMpowerinPETCAMwasactuallysmallerthanthatofEaseCAM.Forexample,inAS1221.WefoundthatthisismainlyduetothelargenumberofSRAMbitsactivatedduringlookup,whichresultedinaveryhighleakagepowerinEaseCAM.Thus,PETCAMusing1-12Wclayout(PTW)isthemostpowerefcientschemeonourdatasets,thenextbestschemebeingPETCAMwithM-12Wblayout(PTM). 54

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Table2-7. SRAMarea(inmm2)forthedifferentschemes DataSetPTMPTWLuMLuWEaseCAM AS12214.896.018.9911.162.05AS46371.551.956.788.60.6AS64474.866.188.8311.252.24AS650002.793.578.3510.521.15rrc003.114.019.4111.991.49rrc013.824.886.748.412.05rrc033.54.516.147.881.66rrc043.414.376.27.931.56rrc053.174.015.877.541.44rrc062.272.814.816.040.92rrc072.923.715.196.71.25rrc104.125.276.778.651.73rrc113.113.915.366.861.34rrc123.614.615.847.571.58rrc132.483.175.386.911.25rrc143.594.655.877.681.57rrc152.132.654.625.790.86rrc163.424.295.747.481.5rviews23.914.976.728.61.9rviews42.793.575.196.621.17rviews.eqix2.973.695.256.751.28rviews.isc3.274.265.677.271.39rviews.linx3.234.045.547.051.41rviews.wide2.393.024.946.260.98 2.4.3AreaEfciencyWeobtainedtheareaforthememoriesasfollows.ForTCAMs,wehavefollowedtheTCAMareaestimationmethodusedbyHashmietal.in[ 16 ].TheareaofasingleTCAMcellistakenas3.59m2[ 31 ]forourcalculations.WemultiplytheareaofasinglecellbythenumberofTCAMcellsneededforstoringeachtableinourdatasetandthenscaleuptheresultingareaby30%totakeintoaccountadditionalroutingoverhead.Wescaledowntheareanumberfor70nmtechnologyusingalinearscalingmodel[ 7 ].ForSRAMs,weobtaintheareanumbersfromtheCACTIresults.Table 2-6 presentsthetotalTCAMarea,whichsumstheareaoccupiedbyallTCAMsusedinascheme.Table 2-7 presentsthetotalSRAMarea,whichisthesumofareaoccupiedby 55

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Table2-8. TCAMsize(inKB)forthedifferentschemes DataSetPTMPTWLuMLuWEaseCAM AS1221150.91186.6279.29349.21581.51AS463746.1558.53211.05267.16170.77AS6447149.93192.11274.25352.2635.41AS6500084.75109.06258.69328.71326.85rrc0094.28123.07292.82375.7422.38rrc01116.8150.59275.74352.2582.51rrc03106.82139.08282.76361.21472.74rrc04103.8134.58286.79365.72443.89rrc0596.29123.07278.79357.21408.14rrc0668.7185.55277.74355.69259.68rrc0786.98113.56274.25348.2354.5rrc10126.33163.08277.74353.71490.98rrc1194.27120.06276.22352.2379.38rrc12110.3142.08277.24354.21448.52rrc1375.2196.55283.79362.2355.95rrc14109.79143.58274.74351.2447.54rrc1564.1980.55282.77362.21244.41rrc16104.29132.07281.78361.21425.04rviews2119.82153.58292.82373.21537.81rviews484.73109.06274.75350.21333.0rviews.eqix90.24113.06274.74350.7363.63rviews.isc99.32131.06280.23357.71393.43rviews.linx98.28124.06277.25353.2400.25rviews.wide72.291.55282.25362.2276.3 allSRAMsusedinascheme.TheareaoccupiedbytheSRAMsinPETCAM(PTM)isatmost2.6timesthatinEaseCAM.PETCAMusesabouthalforsometimeslesserSRAMthaneitherofLu'sschemes.Tables 2-8 and 2-9 showthecostintermsofnumberofbytes.PETCAMusingM-12Wblayout(PTM)isthemostspaceefcientschemeonourdatasets.Thus,ifthemaindesignobjectiveispowerreduction,thenthePETCAMschemeusing1-12Wcprexlayoutshouldbeused.Ontheotherhand,foroverallpowerandspaceoptimization,PETCAMschemewithM-12Wbprexlayoutshouldbechosen. 56

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Table2-9. SRAMsize(inKB)forthedifferentschemes DataSetPTMPTWLuMLuWEaseCAM AS1221664.31839.291231.091570.59286.76AS4637201.93263.26930.461201.5781.39AS6447658.99864.041210.351584.08313.71AS65000372.79490.521140.491478.34159.42rrc00414.43553.531291.311689.83207.19rrc01514.13677.291216.11584.08287.26rrc03470.14625.531246.041624.59232.37rrc04455.15605.281265.971644.84217.95rrc05422.49553.531228.791606.59200.07rrc06301.85384.771223.691599.83125.84rrc07390.35510.781208.631566.08173.25rrc10557.26733.541224.81590.84241.49rrc11413.81540.021217.221584.08185.69rrc12486.13639.031224.221593.09220.26rrc13331.0434.271251.131629.08173.97rrc14482.82645.781212.61579.58219.77rrc15280.91362.271245.571629.09118.21rrc16459.95594.031240.91624.59208.52rviews2527.27690.781290.891678.59264.9rviews4373.19490.521210.741575.09162.5rviews.eqix398.03508.521211.041577.33177.82rviews.isc436.88589.531235.471608.84192.71rviews.linx432.45558.031222.041588.58196.13rviews.wide317.26411.771243.31629.08134.15 2.4.4PETCAMLiteSincetheStep2(maskextension)ofthealgorithmCompactforPETCAMisquitetimeconsuming,weinvestigatealightversion,PETCAMLite,ofPETCAMinwhichStep2isomitted.ThestructureofPETCAMLiteisthesameasPETCAMasgiveninFigure 2-17 .OurexperimentsindicatethatPETCAMLiterequires0%to6%moreTCAMpowerand0.5%to2%moreTCAMmemorythanrequiredbyPETCAM.So,ifStep2takesmorecomputationalresourcethanwewishtoinvest,wemayusePETCAMLiteandgainalmostthesamepowerandmemorybenetsasprovidedbyPETCAM.Table 2-10 showstheCPUtimeonaSun4uSparcSunOS5.8machineforexecutingsteps1and2.Thesteptomapthereducedsetofgeneralizedprexes2-levelTCAM 57

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takesbetween1and4seconds.So,ifaSun4uSparcisusedastherebuildengine,theintervalbetweensuccessiverebuildsoftheTCAMsystemwillneedtobeatleast700secondsforPETCAMbutonlyabout10secondsforPETCAMLite. Table2-10. ExecutiontimeinsecondsforSteps1and2ofCompact DataSetStep1(s)Step2(s)DataSetStep1(s)Step2(s) AS12215.38642.83rrc115.34502.73AS46373.7296.62rrc125.47442.99AS64475.14347.25rrc135.48348.49AS650004.57600.55rrc145.37458.24rrc004.78407.05rrc155.34680.52rrc015.45329.04rrc165.45565.99rrc035.56399.9rviews25.81290.39rrc045.71581.65rviews45.23753.43rrc055.42561.9rviews.eqix5.22656.25rrc065.22746.96rviews.isc5.5565.7rrc075.27591.65rviews.linx5.61507.44rrc105.461274.07rviews.wide5.31710.77 2.4.5ImplementationofNexthopComputationWedesignedacircuitusingVerilogthatimplementsamethodforextractingnextHopinformationfromawideSRAMword.Thisdesignisusedtoestimatetheassociatedcostsintermsoftiming,powerandgatecount.Thedesigntakesthefollowinginputs:awideSRAMword,thedestinationaddressbeingusedincurrentlookupandaclocksignal.ItoutputsthemostappropriatenextHop.Ifsufxmatchingfails,thenthedefaultnextHopisreturned.Thecircuitisathreestagepipeline,asillustratedintheFigure 2-20 .TherststagedeterminesthestartpositionofnextHopandthestartpositionofsufxes.Forexample,basedonFigure 2-13 ,thenextHopstartfrombitnumber5+4+1+12+4sufxCount,sinceitstartspasttheelds-Matchstartposition,Sufxcount,Type,nextHopofS1,andconsecutive4-biteldsdenotingthelengthsofthedifferentsufxes.Thisstagealsoextractsthedestinationbitsforsufxmatching.Thebitsareextractedfromthedestinationaddressstartingfrompositionindicatedbythe`Matchstartposition'eldinthesufxnodeuptoamaximumof15bits(sincewelimitsufxlengthtoamaximumof15bits).Asetof15-bitmasks 58

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Figure2-20. Pipelineprocessingsufxnodewithvariablesufxlengths isalsogeneratedatthisstage,oneforeachsufx,basedonsufxlengthandthismaskisusedduringsufxmatching.Forexample,asufxoflength4usesamask1111000000000000000formatchingwiththedestinationbits.SufxmatchingisdoneparallelyinthesecondstageforallsufxesintheSRAMword.Inthethirdstage,thenexthopcorrespondingtothebestmatchingsufxissenttotheoutput.WeusedSynopsysDesignCompilertosynthesizethelogicusinga0.18mlibrary[ 47 48 ]aswellasa45nmlibrary[ 46 ]andfoundthatourdesignsuccessfullymetthetimingconstraintswith500MHzand1600MHzclockrespectivelyforthetwotechnologies.TheresultsarepresentedintheTable 2-11 .Thethroughputisrepresentedintermsof Table2-11. Timingandpowerresultsforadditionalhardware ProcessTime(ns)Throughput(Msps)Voltage(V)Power(mW)GateCount 0.18m2.005001.817.40512445nm0.6216001.110.926560 millionsearchespersecond(Msps).AnexampleofaTCAMwithaspeedof143MHz(effectively,143Msps)canbefoundin[ 31 ],whichuses0.13mtechnology.Thoughwecouldn'tndatargetlibraryforsynthesisusing0.13m,itisexpectedthatthedelayoverheadandthroughputofourdesignwillimprovecomparedtothatwith0.18m 59

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technology.Inotherwords,ourpipelineddesigncanoperateatthesamespeedofTCAMandthereforeoursufxnodeprocessingwillnotintroduceanyadditionallookupperformanceoverhead.ThereisatradeoffbetweenTCAMusageandSRAMsearchtime/additionalhardwarecomplexityastheSRAMwordsizeisincreased.ThegraphinFigure 2-21 representsthistradeoff. Figure2-21. Tradeoffgraph 2.4.6PerformanceAnalysisPETCAMtakesoneclockcycleforaTCAMlookup(seeSection 2.4.5 )andhenceitspacketforwardingperformanceiscomparabletothatoftheexistingschemesusingTCAMs.Forcomparingupdateperformance,notethatLiu'sschemeandEaseCAMuseincrementalupdates,whereasPETCAMusesbatchupdatesandthelatterstrategyisalsoaptforLuandSahni'sschemesin[ 21 ].Incrementalupdates,ingeneral,aremoreefcientthanbatchupdates.However,incrementalupdatesarecomplexandinefcientforschemesusingprexcompaction.Forexample,itislikelythataprex(tobedeleted,say)maynotbepresentintheTCAMatallsincetheprexhadbeenoptimizedawayduringthecompactionprocess.Toensurecorrectprexmatching,TCAMlookupmustbestalledwhiletheupdatesareincorporated.Thisaffectslookupperformance.In 60

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contrast,schemesthatusebatchupdatesdonotneedtostalllookupsinceupdatesareincorporatedinparallelonadifferentcopyoftheforwardingtable.AsnotedinSection 2.4.4 ,updatetimeinPETCAMLiteisshorterbyordersofmagnitude,sowhenfasterupdatesareneededPETCAMLiteshouldbeused.Inthischapter,wehavepointedoutsomeoftheshortcomingsofthepowerreductionmethodsforTCAMlookuptablesproposedin[ 20 35 ].Bystartingwithanoptimalprexsetforthegivenroutingtableprexset,wecanachievemuchbetterpowerreductionandTCAMmemoryrequirementthanwhenweusethecompactionschemessuggestedin[ 20 35 ].ThisistrueregardlessofwhetherweusetheEaseCAM[ 35 ]architectureorthearchitectureof[ 21 ].ComparedtoEaseCAM,theworstcasepowerreducedbetween87%and98%whileTCAMmemoryisreducedbetween62%and73%.Thepowerandmemoryreductionrelativetothearchitectureof[ 21 ]are8%to20%and45%to78%respectively.AlthoughthereisanincreaseinSRAMusagecomparedtoEaseCAM,thereductioninTCAMusagehasgreaterimpactonareaandpowercharacteristics.PETCAM,justastheschemesin[ 21 ],requiresadditionalhardwaretoextractthemostappropriatenexthopfromawideSRAMword.WehaveproposedtwomemoryandpowerefcientTCAMlookupsystemsPETCAMandPETCAMLite.WhilePETCAMhasslightlybettermemoryandpowercharacteristicsthandoesPETCAMLite,therebuildtimeforPETCAMistwoorders-of-magnitudelargerthanthatforPETCAMLite.PETCAMLitesupportsacceptablerebuildtimesusingmodestcomputationalresources.Onourdatasets,thepowerandmemorypenaltyusingPETCAMLiteareatmost6%andatmost2%,respectively.Inthenextchapterwewillpresentanarchitecturethatletsusdevelopincrementalupdateswhilemanyofthepowersavingstrategiesdiscussedinthischapterarestillapplicable. 61

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CHAPTER3DUO:DUALTCAMARCHITECTUREFORFORWARDINGTABLESWITHINCREMENTALUPDATEInthischapter,wepresentthreeversionsofaTCAMarchitectureforpacketforwardingtablesalongwithadvancedmemorymanagementschemesforperformingefcientandconsistentincrementalupdatesarepresented.TherstversionofthearchitectureisDUOSdualTCAMwithsimpleSRAM,whereboththeTCAMshaveasimpleassociatedSRAMthatisusedforstoringnexthops.ThesecondversionofthearchitectureisDUOWdualTCAMwithwideSRAM,whereoneorboththeTCAMshavewideassociatedSRAMsthatareusedtostoresufxesaswellasnexthops.ThethirdversionisIDUOWindexeddualTCAMwithwideSRAM,inwhicheitherorbothTCAMshaveanassociatedindexTCAM.TheadvantagesofthedualTCAMarchitectureandthememorymanagementschemespresentedinthischapterare: 1. Supportforincrementalupdatesthatrequireveryfewrulemoves. 2. ReducedusageofTCAMmemoryandpower.Thechapterisorganizedasfollows.Section 3.1 presentsrelatedresearchwork.TheDUOSarchitectureandourmemorymanagementschemesaredescribedinSection 3.2 ,DUOWisdescribedinSection 3.3 ,andIDUOWisdescribedinSection 3.4 .AnexperimentalevaluationofDUOispresentedinSection 3.5 ,andweconcludeinSection?? 3.1BackgroundandRelatedWorkSinceourfocusinthischapteristodeveloprouterarchitecturesthathaveefcientsupportforincrementalupdates,wepresentworkrelatedtoTCAMincrementalupdatesinsomedetail.ShahandGupta[ 41 ]describeincrementalupdatealgorithmsforTCAMsusingtwodifferentstrategiestoplaceprexesintheTCAM.InPLO OPT,theprexesareplacedintheTCAMindecreasingorderoflength.UnusedTCAMslots/wordsareinthemiddleoftheTCAM.So,prexesoflengthW,,W=2+1areabovethefreeslotsandthe 62

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remainingprexesarebelowthefreeslots,whereW=32forIPv4.AninsertordeleterequiresatmostW=2prexmovesinPLO OPT.InCAO OPT,theprexesareplacedintheTCAMsothatiftwoprexesarenested,thelongerprexprecedestheshorterone.Ifwestartwiththebinarytrierepresentationoftheprexesoftheroutingtable,theprexesalonganypathfromthetrieroottoatrieleafarenested.So,everyroottoleafpathinthetriedenesachainofnestedprexes.InCAO OPT,theprexesoneverychainappearinreverseorderintheTCAM.ThisplacementensuresthattherstprexintheTCAMthatmatchesadestinationaddressisthelongestmatchingprex.TheTCAMfreeslotsareinthemiddleoftheTCAM.Ifthemaximumnumberofprexesinanestedchainisq,thenatmostdq=2eprexesofachainareabovethefreeslots.AninsertordeleteinCAO OPTrequiresatmostdq=2e=W=2moves.Sinceqisabout6inpracticalroutingtables,CAO OPTgivesaperformanceimprovementoverPLO OPTinpractice(thoughtheworst-caseperformanceofbothisthesame).Wangetal.[ 54 ]deneaconsistentruletabletobearuletableinwhichtherulematched(includingtheactionassociatedwiththerule)byalookupoperationperformedinthedataplaneiseithertherule(includingaction)thatwouldbematchedjustbeforeorjustafteranyongoingupdateoperationinthecontrolplane.Wangetal.[ 54 ]developaschemeforconsistenttableupdatewithoutlockingtheTCAMatanytime,essentiallyallowingasearchtoproceedwhilethetableisbeingupdated.ConsistencyisensuredbyavoidingoverwritingofaTCAMentry.TheirCoPTUAalgorithmcanbeappliedtothePLO OPTandCAO OPTschemesof[ 41 ]sothatruleupdatescanbecarriedoutwithoutlockingthetablefordataplanelookupsundersuitableassumptionsforTCAMoperation[ 54 ].WangandTzeng[ 53 ]alsoproposeaconsistentTCAMscheme.Theirscheme,MIPS,howeverdelaysdataplanelookupsthatmatchTCAMslotswhosenexthopinformationisbeingupdated.InMIPS,theTCAMstoresasetofindependentprexes(i.e.,disjoint).Thissetofindependentprexesisobtainedfromtheoriginalsetof 63

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prexesbyusingtheleafpushingtechnique[ 45 ]followedbyacompressionstep.SincetheprexesintheTCAMareindependent,atmostoneprexmatchesanygivendestinationaddress.Hence,theindependentprexesmaybeplacedintheTCAMinanyorderandwemaydispensewiththepriorityencoderlogicoftheTCAM,whichresultsinareductioninTCAMlookuplatencybyabout50%[ 3 ].Further,anewprexmaybeinsertedintoanyfreeslotoftheTCAMandanoldprexdeletedbysimplysettingtheassociatedslot'svalidbitto0.Whiletheuseofanindependentprexsetsimpliestablemanagement,leafpushingreplicatesaprexmanytimes.Intheworstcase,aninsertordelete,requireschangesto(n)TCAMentries,wherenthenumberofindependentprexesintheTCAM(Figure 3-1 ).Furthermore,thenumberofindependentprexesthatresultfromleafpushingandcompressioncanbequitelargeas,intheworst-case,thecompressionstepmayfailtodoanyreductionintheprexsetfollowingleafpushing.Experimentalresultspresentedin[ 53 ]suggest,however,that,onpracticalrulesets,leafexpansionandcompressionactuallyreducethenumberofprexesby20%to68%becauseoftheprevalenceofalargenumberofredundantprexesinpracticalrulesets.Further,eachupdateoperationresultsinbetweenoneandtwoaccessestotheTCAMonaverage.WangandZheng[ 53 ]donotuseanymemorymanagementschemetokeeptrackofthefreeslotsintheTCAMandinsteadrelyonaTCAMsearchoperationtondanemptyslotwhensuchaslotisneeded.SinceaTCAMcannotperformadataplanesearchconcurrentwithacontrolplanesearch,updateoperationsdelaydataplanelookups.Inpractice,sincethenumberofupdatespersecondisquitesmallandsinceeachroutingtableupdateresultsinonlyoneortwoTCAMupdateoperations(onaverage)thedelaycausedbycontrolplanelookupsondataplanelookupsisquitesmall.AsTCAMlookupsconsumeasignicantamountofenergyrelativetothatconsumedbyTCAMread/writeoperations,usinglookupstolocatefreeTCAMslotsincreasestotalenergyconsumptionforupdatessignicantly. 64

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A4-prextrie BInsert<=0,H0>Figure3-1. Insertionoftherootprexinto(a)requirestheinsertionof4newindependentprexesintotheTCAM.Similarly,thedeletionoftherootprexfrom(b)requiresthewithdrawalofthese4prexesfromtheTCAM Zaneetal.[ 55 ]proposeanindexedTCAMschemetoreducethetotalTCAMpowerusedtosearchroutingtablesofagivensize.TheindexedTCAMschemesof[ 55 ],however,increasethetotalTCAMsizeneededrelativetonon-indexedTCAMs.LuandSahni[ 21 ]coupleindexedTCAMswithwideSRAMstoreducebothpowerandTCAMmemorybyasignicantamount.Althoughthestrategiesof[ 21 ]arepowerandmemoryefcient,theyarenotwellsuitedtoincrementalupdate.Similarlytheprexcompactionmethodsof[ 14 20 27 ],whileresultinginpowerandmemoryreduction,donotlendthemselveswelltoincrementalupdate.Chang[ 9 ]proposesaTCAMpartitioningandindexingschemeinwhichtheTCAMindexisstoredinapivotprexSRAMandanindexSRAM.InChang'sscheme[ 9 ],theTCAMindexissearchedusingabinarysearchthatmakesO(logK)SRAMaccessestodeterminetheTCAMbucketthatistobesearched.Ontheotherhand,theschemeofZaneetal.[ 55 ]storesitsindexinaTCAMenablingthedeterminationofthebucketforfurthersearchbyaqueryontheindexTCAM.Asaresult,alookuptakes2TCAMsearcheswhentheschemeof[ 55 ]isusedandtake1TCAMsearchplusO(logK)SRAMaccesseswhentheschemeof[ 9 ]isused. 3.2SimpleDualTCAMDUOSDUOSusesanyreasonablyefcientdatastructuretostoretherouting-tablerulesinthecontrolplane.Forexample,asimpledatastructuresuchasabinarytrieor1-bit 65

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triestoredina100nsDRAM,permitsabout300KIPv4lookups,inserts,anddeletespersecond.Thisperformanceisquiteadequatefortheanticipatedtensofthousandsofcontrolplaneoperations.Forconcreteness,weassumethatabinarytrieisused,inthecontrolplane,tostoretherouting-tablerules.Additionally,DUOSusestwoTCAMseachwithanassociatedSRAM.TheTCAMsarelabeledITCAM(InteriorTCAM)andLTCAM(LeafTCAM)inFigure 3-2 .TheassociatedSRAMsaresimilarlylabeled.Prexesstoredinleaf(nonleaforinterior)nodesofthecontrolplanetriearestoredalsointheLTCAM(ITCAM)andtheirassociatednexthopsarestoredintheLSRAM(ISRAM).SincetheLTCAMstoresonlyleafprexes,theprexesintheLTCAMaredisjointandatmostonemaymatchagivendestinationaddress.Consequently,theLTCAMprexes,eventhoughofvaryinglength,maybestoredinanyorder.Further,theLTCAMdoesnotrequireapriorityencoderand,asaresult,thelatencyofanLTCAMsearchisupto50%lessthanthatofasearchinaTCAMwithapriorityencoder[ 3 ].Adataplanelookupisperformedbydoingasearchforthepacket'sdestinationaddressinbothITCAMandLTCAM.TheITCAMsearchyieldsthenexthopassociatedwiththelongestmatchingnon-leafprexwhiletheLTCAMsearchyieldsthenexthopassociatedwithatmostoneleafprexthatmatchesthedestinationaddress.AdditionallogicshowninFigure 3-2 returnsthenexthop(ifany)fromtheLTCAMsearch;thenexthopfromtheITCAMsearchisreturnedonlyiftheLTCAMsearchfoundnomatch.NotethatsincetheLTCAMhasnopriorityencoder,itssearchcompletessoonerthanthatintheITCAM.ThecombininglogicofFigure 3-2 cantakeadvantageofthisandaborttheITCAMsearchwhenevertheLTCAMsearchissuccessful,therebyreducingaveragelookuptime.Thecorrectnessofthelookupisreadilyestablished.Figure 3-3 showsa4-prexforwardingtabletogetherwithitscorrespondingbinarytriethatisstoredinthecontrolplaneaswellasthecontentofthetwoTCAMsandthetwoSRAMsofDUOS.Eachnodeofthecontrolplanetriehaseldssuchasprex,slot,nexthopandlengthinwhichtheprex(ifany)storedatthisnodeisrecordedalongwiththeITCAM 66

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Figure3-2. DualTCAMwithsimpleSRAM orLTCAMslotinwhichtheprexisstoredandthenexthopandlengthoftheprex.Functionsforbasicoperationsonthecontrolplanetrie(hereinaftersimplyreferredtoastrie)areassumed(seeFigure 3-4 ).AsthecontrolplanewillmodifytheITCAM,LTCAM,ISRAM,andLSRAMwhilethedataplaneperformslookups,theTCAMsneedtobedualported.Specically,wemakethefollowingassumptions: 1. EachTCAMhastwoports,whichcanbeusedtosimultaneouslyaccesstheTCAMfromthecontrolplaneandthedataplane. 2. EachTCAMentry/slotistaggedwithavalidbit,thatissetto1ifthecontentfortheentryisvalid,andto0otherwise.ATCAMlookupengagesonlythoseslotswhosevalidbitis1.TheTCAMslotsengagedinalookuparedeterminedatthestartofalookuptobethoseslotswhosevalidbitsare1atthattime.Changingavalidbitfrom1to0duringadataplanelookupdoesnotdisengagethatslotfromtheongoinglookup.Similarly,changingavalidbitfrom0to1duringadataplanelookupdoesnotengagethatslotuntilthenextlookup. 67

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AA4-prexforwardingtable BItsbinarytrierepresentation CDUOSrepresenta-tionFigure3-3. DUOSforanexample4-prexforwardingtable.NotethatprexesinITCAMarestoredinlengthorder,whereasthoseinLTCAMarestoredarbitrarilysincetheprexesaredisjoint. Function:Trie.insert(a,b)=Trie.insert(prex,length,nextHop);Thisfunctioninsertsaprexgivenitslengthandnexthopintothecontrol-planebinarytrie.Itreturnsthetrienodeawhichstoresthenewprexanda'snearestancestornodebthatcontainsaprex.Function:Trie.delete(a,b)=Trie.delete(prex,length);Thisfunctiondeletesaprexfromthecontrolplanetrieandreturnsthetrienodeathatusedtostoretheprexjustdeletedanda'snearestancestornodebthatcontainsaprex.Function:Trie.changea=Trie.change(prex,length,newHop);Thisfunctionchangesthenexthopassociatedwithaprexandreturnsthetrienodeathatcontainstheprex.Figure3-4. Tableofcontrol-planetriefunctions WeassumetheavailabilityofthefunctionwaitWriteValidatewhichwritestoaTCAMslotandsetsthevalidbitto1.IncasetheTCAMslotbeingwrittentoisthesubjectofongoingdataplanelookup,thewriteisdelayedtillthislookupcompletes.Duringthewrite,theTCAMslotbeingwrittentoisexcludedfromdataplanelookups1.Thisis 1Apossiblemechanismtoaccomplishthisexclusionistosetthevalidbitto0beforecommencingthewriteandtochangethisbitto1whenthewritecompletes. 68

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equivalenttotherequirementthatAfteraruleismatched,resettingthevalidbithasnoeffectontheactionreturnprocess[ 54 ],andtosettingthevalidentrytohit[ 53 ].Similarly,weassumetheavailabilityofthefunctioninvalidateWaitWrite,whichsetsthevalidbitofaTCAMslotto0andthenwritesanaddresstotheassociatedSRAMwordinsuchawaythattheoutcomeoftheongoinglookupisunaffected.WenotethatwaitWriteValidatemay,attimes,writetheprexandnexthopinformationintheTCAMandassociatedSRAMslotandvalidateit,withoutanywait.Thishappens,forexample,whenthewritingistobedonetoaTCAMslotthatisnotthesubjectoftheongoingdataplanelookup.ThewaitcomponentofthefunctionwaitWriteValidateissaidtobenullinthiscase.Figure 3-5 liststhevariousupdatealgorithmswedenelaterinthissectionforDUOSanditsassociatedITCAMandLTCAM.Theindentationrepresentsthehierarchyoffunctioncalls.Afunctionatonelevelofindentationcallsoneormorefunctionsbelowitatthenextlevelofindentationoratthesamelevelofindentation. 3.2.1DUOSIncrementalUpdateAlgorithms 3.2.1.1InsertFigure 3-6 givesthealgorithmtoinsertanewprexpoflengthlandnexthoph.Forsimplicity,weassumethatpis,infactnew(i.e.,pisnotalreadyintheruletable).First,pisinsertedintothetrieusingthetrieinsertionalgorithm,whichreturnsnodesmandn,wheremisthetrienodestoringpandnisthenearestancestor(ifany)ofmthathasaprex.Whenmisaleafofthetrie,thereisapossibilitythattheinsertionofptransformedaprexthatwaspreviouslyaleafprexintoanon-leafprex.Ifso,thisprexismovedfromtheLTCAMtotheITCAM.Regardless,pisinsertedintotheLTCAM.Whenmisnotaleaf,pisinsertedintotheITCAM.Figure 3-7 3-8 and 3-9 illustratetheinsertionofrulesP5,P6andP7respectivelystartingwiththeinitialprextrieinFigure 3-3 69

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Figure3-5. Tableoffunctionsusedforincrementalupdate Algorithm:insert(p,l,h)(m,n)=Trie.insert(p,l,h)ifmisaleafthenbeginifnexistsandn!prexwasaleafprexthenslot=ITCAM.insert(n!prex,n!nexthop,n!length);//n!prexisnolongeraleafLTCAM.delete(n!slot);n!slot=slot;endifm!slot=LTCAM.insert(p,h,l);elsem!slot=ITCAM.insert(p,h,l);endifFigure3-6. AlgorithmtoinsertintoDUOS 70

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Aupdatedtrie BupdatedDUOSFigure3-7. InsertruleP5-f1*,H5gtotheinitialtableinFigure 3-3 .P5isaleafandhenceisaddedtotheLTCAM Aupdatedtrie BupdatedDUOSFigure3-8. InsertruleP6-f011*,H6gtotheprexesinFigure 3-7 .P6isaddedtotheLTCAM,whileP3,whichisnolongeraleaf,isdeletedfromLTCAMandaddedtoITCAM. Aupdatedtrie BupdatedDUOSFigure3-9. InsertruleP7-f0*,H7gtotheprexesinFigure 3-8 .P7isaddedtotheITCAMsinceitinvolvesanintermediateprex. 71

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Algorithm:delete(p,l)(m,n)=Trie.delete(p,l)IfmisaleafthenLTCAM.delete(m!slot)Ifnexistsandnisnowaleafthenslot=LTCAM.insert(n!prex,n!nexthop,n!length)ITCAM.delete(n!slot,n!length)//sincenisnowaleafprexn!slot=slot;endifelseITCAM.delete(m!slot,m!length)endifFigure3-10. AlgorithmtodeletefromDUOS 3.2.1.2DeleteFigure 3-10 givesthealgorithmtodeletetheprexpfromDUOS.Forsimplicity,weassumethatpis,infact,presentintheruletableandsomaybedeleted.First,pisdeletedfromthetrie.Thetriedeletionfunctionreturnsnodesmandn,wheremisthetrienodewherepwasstoredandnisthenearestancestor(ifany)ofmthathasaprex.Ifmwasaleaf,thenpistobedeletedfromtheLTCAM.Inthiscase,theprex(ifany)innmaybecomealeafprex.Ifso,theprexinnistobemovedfromtheITCAMtotheLTCAM.Whenmisnotaleaf,pisdeletedfromtheITCAM.Figure 3-11 3-12 3-13 illustratethedeleteprocedureofprexesP7,P4andP5respectivelystartingwiththeprextrieinFigure 3-9 72

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Aupdatedtrie BupdatedDUOSFigure3-11. DeleteruleP7-f0*,H7gfromtheprexesinFigure 3-9 .P7isdeletedfromITCAM. Aupdatedtrie BupdatedDUOSFigure3-12. DeleteruleP4-f000*,H4gfromtheprexesinFigure 3-11 .P4isdeletedfromLTCAM.P2isinsertedtoLTCAManddeletedfromITCAMasP2isnowaleaf. Aupdatedtrie BupdatedDUOSFigure3-13. DeleteruleP5-f1*,H5gfromtheprexesinFigure 3-12 .P5isdeletedfromLTCAM. 73

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Algorithm:change(p,length,newH)m=Trie.change(p,l,newH)Ifmisaleafthenm!slot=LTCAM.change(p,m!slot,newH);elsem!slot=ITCAM.change(p,m!slot,newH,length);Figure3-14. AlgorithmtochangeanexthopinDUOS 3.2.1.3ChangeTochangethenexthopofanexistingprextonewH,werstchangethenexthopoftheprexinthetrieandreturnthenodemthatcontainsp.Then,dependingonwhethermisaleafornonleaf,weinvokethechangefunctionforthecorrespondingTCAM.Figure 3-14 givesthealgorithm. 3.2.2ITCAMAlgorithmsTheprexesintheITCAMarestoredinsuchamannerastosupportdeterminingthelongestmatchingprex(i.e.,inanytopologicalorderthatconformstotheprecedenceconstraintsdenedbythebinarytriep1mustcomebeforep2wheneverp1isadescendentofp2[ 41 ]).Decreasingorderoflengthisacommonlyusedordering.ThefunctiongetSlot(length)returnsanITCAMslotsuchthatinsertionofthenewprexintothisslotsatisestheorderingconstraintinuseprovidedthenewprexhasthespeciedlength;thefunctionfreeSlot(slot,length)freesaslotpreviouslyoccupiedbyaprexofthespeciedlengthandmakesthisslotavailableforreuselater.Thesefunctions,whicharedescribedinSection 3.2.4 ,areusedinourITCAMinsert,delete,andchangealgorithms(Figure 3-15 ),whichareselfexplanatory.Noticethatfollowingtherststepofthechangealgorithm,theprexwhosenexthopisbeingchangedisintwovalidslotsoftheITCAMoldSlotandslot.ThisduplicationdoesnotaffectcorrectnessofdataplanelookupsaswhicheveroneismatchedbytheITCAM,wereturnthenexthopthatisvalideitherbeforeorafterthechangeoperation.Ontheotherhand,ifweattemptedtochangethenexthopinISRAM[oldSlot]directly,anongoinglookupmayreturnagarblednexthop.Similarly, 74

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Algorithm:insert(prex,nexthop,length)slot=getSlot(length);ITCAM.waitWriteValidate(slot,prex,nexthop);returnslot;Algorithm:delete(slot,length)freeSlot(slot,length);Algorithm:change(prex,oldSlot,nexthop,length)slot=insert(prex,nexthop,length);delete(oldSlot,length);returnslot;Figure3-15. ITCAMalgorithms ifwedeleterstandtheninsert,lookupsthattakeplacebetweenthedeleteandtheinsertmayreturnanexthopthatdoesn'tcorrespondtotheroutingtablestateeitherbeforeorafterthechange.IfawaitWriteValidateisusedtochangeISRAM[oldSlot]tonexthop,oldSlotbecomesunavailablefordataplanelookupsduringthewriteoperationandinconsistentresultsarereturnedincasetheprexinTCAM[oldSlot]isthelongestmatchingprex. 3.2.3LTCAMAlgorithmsTheprexesintheLTCAMaredisjointandsomaybestoredinanyorder.Theunused(orfree)slotsoftheLTCAM/LSRAMarelinkedtogetherintoachainusingthewordsoftheLSRAMtobuildthischain.WeuseAVtostoretheindexoftherstLSRAMwordonthechain.So,thefreeslotsareAV,LSRAM[AV],LSRAM[LSRAM[AV]],andsoon.ThelastfreeslotontheAVchainhasLSRAM[last]=)]TJ /F4 11.955 Tf 9.29 0 Td[(1.TheLTCAMalgorithmstoinsert,delete,andchangearegiveninFigure 3-16 .Thesealgorithmsareselfexplanatory. 3.2.4ITCAMMemoryManagementInthissection,wedescribefourpossiblememorymanagementschemesforanITCAM.ThedescriptionofeachmemorymanagementschemeincludesanimplementationofthegetSlotandfreeSlotfunctionsusedinSection 3.2.2 togetandfreeITCAMslots.Theimplementationsemploythefunctionmove(Figure 3-17 ) 75

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Algorithm:insert(prex,nexthop,length)if(AV==)]TJ /F4 11.955 Tf 9.29 0 Td[(1)throwNoSlotException;slot=AV;AV=LSRAM[slot];LTCAM.waitWriteValidate(slot,prex,nexthop);returnslot;Algorithm:delete(slot)LTCAM.invalidateWaitWrite(slot,AV);//AVisstoredinLSRAM[slot]afterwaiting//foranongoinglookuptocompleteAV=slot;Algorithm:change(prex,oldSlot,nexthop,length)slot=insert(prex,nexthop,length);delete(oldSlot);returnslot;Figure3-16. LTCAMalgorithms Algorithm:move(src,dest)ITCAM.waitWriteValidate(dest,ITCAM[src],ISRAM[src]);Figure3-17. MovefromITCAM[src]toITCAM[dest] thatmovesthecontentofanin-useITCAMslottoafreeITCAMslotinsuchawayastomaintaindataplanelookupconsistency.OurmemorymanagementalgorithmsmaintaintheinvariantthatanITCAMslothasitsvalidbitsetto0iffthatslotwasn'tmatchedbytheongoingdataplanelookup(ifany);thatis,ifftheslotisn'tinvolvedintheongoingdataplanelookup. 3.2.4.1Memorymanagementscheme1Thisscheme,whichisthePLO OPTschemeof[ 41 ],isshowninFigure 3-18 (a),theITCAMslotsareindexed0throughN.TheprexesarestoredindecreasingorderoflengthintheTCAM,whichensuresthatthelongestmatchingprexisreturnedastherstmatchingprex.ThepooloffreeslotsiskeptatthelogicalcenteroftheTCAM,thatis,therstfreeslotinthepoolappearsafterallblocksofprexesoflengthW=2+1ormoreandthelastfreeslotappearsbeforeallblocksofprexesoflengthW=2orless,whereWisthewidthoftheIPaddress(32inthecaseofIPv4).Asnotedin[ 41 ],thisschemerequiresatmostW=2movesforeachgetSlotandfreeSlotrequest.Our 76

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contributionistoprovideanimplementationthatmaintainsconsistencyofdataplanelookups. AInitialarrange-ment BInsertp/30 CFreespaceavailableinblock30forinsert DDeletep/24 EFreespacere-turnedtopoolFigure3-18. PrexarrangementinITCAMforScheme1forIPv4.Thefreespacepoolisindicatedbyhatchedlines.Numbers1,2bythecurvedarrowcorrespondtotherstandsecondmove,respectively. OurlookupconsistentimplementationofgetSlotandfreeSlotemploythefollowingvariables:W=prexlength(32forIPv4)top[i]=rstslotusedbyblocki,1iW=2bot[i]=lastslotusedbyblocki,W=2+1iWThefollowinginvariantsaremaintained:top[i]=top[i-1]iffblockiisempty,1iW=2bot[i]=bot[i+1]iffblockiisempty,W=2+1iWInitially,allblocksareemptyandtop[0:W=2]=N+1andbot[W=2+1:W+1]=-1(recallthattheITCAMslotsareindexed0:N).Figures 3-19 and 3-20 ,respectively,givethegetSlotandfreeSlotalgorithmsforScheme1.Theircorrectnessandthefactthatdataplanelookupconsistencyispreservedareeasilyestablished.o 77

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Algorithm:getSlot(len)//len:lengthofprextobeinserted.//returnsfreeslotforprexinsertionif(bot[W=2+1]==top[W=2]-1)throwNoSpaceException;if(lenW=2+1)d=++bot[W=2+1];for(i=W=2+2;ilen;++i)if(bot[i]==d-1)//blocki)]TJ /F4 11.955 Tf 11.96 0 Td[(1isemptybot[i]=bot[i)]TJ /F4 11.955 Tf 11.96 0 Td[(1];else//movefromtopofi)]TJ /F4 11.955 Tf 11.96 0 Td[(1tods=++bot[i];move(s,d);d=s;endifelsed=\000top[W=2];for(i=W=2)]TJ /F4 11.955 Tf 11.96 0 Td[(1;i>=len;)-222()]TJ /F3 11.955 Tf 23.91 0 Td[(i)if(top[i]==d+1)//blocki+1isemptytop[i]=top[i+1];else//movefrombottomofi+1tods=\000top[i];move(s,d);d=s;endifendifFigure3-19. Scheme1algorithmtogetafreeslottoinsertaprexwhoselengthislen 78

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Algorithm:freeSlot(slot,len)//freeITCAM[slot]whichhadaprexoflengthlenif(lenW=2+1)//freespacefromthetophalf.if(slot!=bot[len])move(bot[len],slot);slot=bot[len];endifbot[len]\000;for(i=len)]TJ /F4 11.955 Tf 11.95 0 Td[(1;i>W=2;)-222()]TJ /F3 11.955 Tf 23.91 0 Td[(i)if(bot[i]!=slot)//blockiisnotemptymove(bot[i],slot);slot=bot[i];endifbot[i]\000;endforelse//freespacefromthebottomhalf.if(slot!=top[len])move(top[len],slot);slot=top[len];endiftop[len]++;for(i=len+1;iW=2;++i)if(top[i]!=slot)//blockiisnotemptymove(top[i],slot);slot=top[i];endiftop[i]++;endforITCAM[slot].valid=0;endifFigure3-20. Scheme1algorithmtofreeaslotpreviouslyoccupiedbyaprexoflengthlen 79

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3.2.4.2Memorymanagementscheme2ThisschemeisavariationofScheme1inwhichthefreeslotsareintheboundarybetweentwoprexblocks(Figure 3-21 ).ThisschemeisalsocalledDFS PLO(DistributedFreeSpacewithPrexLengthOrderingConstraint).AtthetimetheITCAMisinitialized,theavailablefreeslotsaredistributedinproportiontothenumberofprexesinablockwiththecaveatthatanemptyblockgets1freeslotatitsboundary.Inthisscheme,top[i]istheslotwheretherstprexoflengthiisstoredandbot[i]istheslotwherethelastprexoflengthiisstored,0iW(i.e.,thesevariablesdenethestartandendofblocki).Notethattop[i]bot[i]foranon-emptyblockiandtop[i]>bot[i]foranemptyblock.Forconvenience,wedenetop[0]=bot[0]=N+1andtop[W+1]=bot[W+1]=-1.ForanemptyITCAM,top[i]=N+1for1iW;bot[i]=-1for1iW. AInitialarrange-ment BInsertp/30 CFreespaceavailableinblock30forinsert DDeletep/24 EFreespacereturnedtoadjacentpoolFigure3-21. ITCAMlayoutforScheme2(DFS PLO) OurgetSlotalgorithm(Figure 3-22 )providesafreeslotfromeitherblockboundarywhenthereisafreeslotontheblockboundary.Otherwise,itmovesafreeslotfromthenearestblockboundarythathasafreeslot.Thealgorithmtofreeaslot(Figure 3-23 )simplymovestheslottobefreedtotheblockboundaryunlessthisslotisatthe 80

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Algorithm:getSlot(len)ma=movesFromAbove(len,&aPos);mb=movesFromBelow(len,&bPos);if(mabot[len])bot[len]=d;top[len]=d;elseif(mb==W+1)throwNoSpaceException;d=getFromBelow(len,bPos);if(top[len]>bot[len])top[len]=d;bot[len]=d;endifreturnd;Figure3-22. Scheme2algorithmtogetafreeslottoinsertaprexwhoselengthislen Algorithm:freeSlot(d,len)if(top[len]==d)ITCAM[top[len]++].valid=0;elseif(bot[len]==d)ITCAM[bot[len]\000].valid=0;elsemove(bot[len],d);ITCAM[bot[len]\000].valid=0;endifFigure3-23. Scheme2algorithmtofreeaslot boundarytobeginwith.Again,correctnessandconsistencyareestablishedeasily.Althoughtheworst-caseperformanceoftheScheme2algorithmsisthesameasthatoftheScheme1algorithms,weexpecttheScheme2algorithmstohavebetterperformanceonaverage.ThegetSlotalgorithmutilizesseveralsupportingalgorithmsthataregiveninFigure 3-24 .ThealgorithmmovesFromAbove(movesFromBelow)returnsthenumberofprexmovesthatarerequiredtogetthenearestfreeslotfromabove(below)theblockwhereitisneededandgetFromAboveandgetFromBelow,respectively,getthenearestfreeslotaboveorbelowtheblockwherethefreeslotisneeded. 81

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Algorithm:movesFromAbove(len,*pos)//returnsnumberofmovesneededtoacquirefreespacefromabovetheblockoflengthlenmoves=0;for(p=len;top[p]>bot[p];p\000);//ndmaxplensuchthatblockpisnotemptyfor(c=len+1;cW+1;c++)//ndminc>lenwithspacejustbelowitif(top[c]bot[c])//notemptyif(bot[c]+1bot[p];p++);//ndminp>=lensuchthatblockpisnotemptyfor(c=len-1;c>=0;c\000)//ndminc>lenwithspacejustbelowitif(top[c]bot[c])//notemptyif(top[c]-1>bot[p])*pos=p;returnmoves;endifmoves++;p=c;endifreturnW+1;Algorithm:getFromAbove(len,pos)//getfreespacefromaboved=top[pos]-1;for(c=pos;c>len;c\000)if(top[c]bot[c])d=bot[c];move(bot[c]\000,\000top[c]);endifreturnd;Algorithm:getFromBelow(len,pos)//getfreespacefrombelowd=bot[pos]+1;for(c=pos;c
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3.2.4.3Memorymanagementscheme3ThisisanenhancementofScheme2inwhichwemaintainadoubly-linkedlistoffreeslotswithineachblockinadditiontocontiguousfreeslotsattheblockboundaries(Figure 3-25 ).ThisschemeisalsocalledDLFS PLO(DistributedandLinkedFreeSpacewithPrexLengthOrderingConstraint).ThelistsoffreeslotswithinablockenableustoavoidthemovethatisdonebytheScheme2freeSlotalgorithmofFigure 3-23 .Theforwardlinks,callednext[],ofthedoubly-linkedlistaremaintainedusingtheISRAMwordscorrespondingtothefreeITCAMslotswithAV[i]recordingtherstslotonthelistfortheithblock.Thebackwardlinks,calledprev[],aremaintainedintheseISRAMwordsincaseanISRAMwordislargeenoughtoaccommodatetwolinksandinthecontrolplanememoryotherwise.Allvariables,includingthearrayAV[],are,ofcourse,storedinthecontrolplanememory.Thescheme3getSlotalgorithm(Figure 3-26 )rstattemptstomakeavailableaslotfromthedoubly-linkedlistforthedesiredblock.Whenthislistisempty,thealgorithmbehaveslikethegetSlotalgorithmforScheme2andthesupportingalgorithmsofThealgorithmtofreeaslot(Figure 3-27 )differsfromthatforScheme2inthatwhentheslotbeingfreedisinsideablockitisaddedtothedoubly-linkedlistoffreeslots.Again,correctnessandconsistencyareestablishedeasily.Althoughtheworst-caseperformanceoftheScheme3algorithmsisthesameasthatofthealgorithmsforthersttwoschemes,weexpecttheScheme3algorithmstohavebetterperformanceonaverage.Figures 3-28 and 3-29 aresimilartothecorrespondingsupportingalgorithmsforScheme3. 83

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AInitialarrange-ment BInsertp/30 CFreespaceavailable DDeletep/24 EDeletep2/24 FDeletep3/24 GInsertp/24Figure3-25. ITCAMlayoutforScheme3,withmovesforinsertanddelete.Thecurvedarrowsontherightshowtheforwardlinksinthelistoffreespaces. 84

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Algorithm:getSlot(len)aP=0;bP=0;aC=0;bC=0;if(AV[len]==-1)//AV[len]storestherstfreespaceinblockoflengthlenma=movesFromAbove(len,&aP,&aC);mb=movesFromBelow(len,&bP,&bC);if(mabot[len])bot[len]=d;top[len]=d;elseif(mb==W+1)throwNoSpaceException;//nospaced=getFromBelow(len,bP,bC);if(top[len]>bot[len])top[len]=d;bot[len]=d;endifelsed=AV[len];AV[len]=next[d];endifreturnd;Figure3-26. Scheme3algorithmtogetafreeslottoinsertaprexwhoselengthislen Algorithm:freeSlot(d,len)if(top[len]==d)ITCAM[top[len]++].valid=0;elseif(bot[len]==d)ITCAM[bot[len]\000].valid=0;elseITCAM.invalidateWaitWrite(d,AV[len]);//AV[len]isstoredinISRAM[d].if(AV[len]!=-1)prev[AV[len]]=d;AV[len]=d;endifFigure3-27. Scheme3algorithmtofreeaslot 85

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Algorithm:movesFromAbove(len,*pos,*cur)moves=0;for(p=len;top[p]>bot[p];p\000);//ndmaxplensuchthatblockpisnotemptyfor(c=len+1;cW+1;c++)//ndminc>lenwithspacejustbelowitif(top[c]bot[c])//notemptyif(bot[c]+1=0)*pos=c;*cur=c;returnmoves;endifp=c;endifreturnW+1;Algorithm:getFromAbove(len,p,c)if(top[p]>bot[c]+1)d=top[p]-1;c=p;elseif(!valid[bot[c]])d=bot[c]\000;if(d==AV[c])AV[c]=next[AV[c]];elsenext[prev[d]]=next[d];if(next[d]!=-1)prev[next[d]]=prev[d];endifelsed=AV[c];AV[c]=next[AV[c]];move(bot[c],d);d=bot[c]\000;endifc)-221()]TJ /F1 11.955 Tf 21.25 0 Td[(;endiffor(;c>len;c)-222()]TJ /F1 11.955 Tf 21.26 0 Td[()if(top[c]bot[c])move(bot[c]\000,\000top[c]);d=bot[c]+1;endifreturnd;Figure3-28. Algorithmstobringinaslottoatargetblockfromabove(loweraddressesoftheTCAM).ThesealgorithmsareusedbygetSlotofFigure 3-26 86

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Algorithm:movesFromBelow(len,*pos,*cur)moves=0;for(p=len;top[p]>bot[p];p++);//ndminp>=lensuchthatblockpisnotemptyfor(c=len-1;c>=0;c\000)//ndminc>lenwithspacejustbelowitif(top[c]bot[c])//notemptyif(top[c]-1>bot[p]jj!valid[top[c]])*pos=p;*cur=c;returnmoves;endifmoves++;if(AV[c]>=0)*pos=c;*cur=c;returnmoves;endifp=c;endifreturnW+1;Algorithm:getFromBelow(len,p,c)if(top[c]-1>bot[p])d=bot[p]+1;c=p;elseif(!valid[top[c]])d=top[c]++;if(d==AV[c])AV[c]=next[AV[c]];elsenext[prev[d]]=next[d];if(next[d]!=-1)prev[next[d]]=prev[d];endifelsed=AV[c];AV[c]=next[AV[c]];move(top[c],d);d=top[c]++;endifc++;endiffor(;c
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3.2.4.4Scheme4ThisistheCAO OPTschemepresentedin[ 41 ].Here,prexesarearrangedinchainorder,withthefreespacepoolinthemiddleoftheITCAM.Figures 3-30 3-32 givethenecessaryalgorithms.Theinterfacesaredifferentfromthoseusedbytherst3schemes.TheinputtogetSlotisp,whichisthenodeinthetriewheretheprexbeinginsertedisstored.Eachtrienodestoreswt,wt ptr,hcld ptr,lchild,rchild,whichareexplainedin[ 41 ].Inadditiontotheseweusethefollowingvariables:slot:addressofITCAMslotinwhichprexisentered.Ifprexhasnotyetbeenentered,thenthisvariableissetto-1.rstFree:rstfreespacelastFree:lastfreespaceshift[0:W/2]:temporaryarrayofnodesAlsoneededisanarrayofnodes,saynodeMap[0:N]forITCAM[0:N]thatcontainsthenodeaddressofeachvalidprexintheITCAM,sothattheycanbelocatedinthetrie. 88

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Algorithm:getSlot(p)d=isTopHeavy(p)?lastFree)-222()]TJ /F1 11.955 Tf 24.58 0 Td[(:rstFree++;if(parent(p)andp!parent(p)!slot=0;\000j)tmp=shift[j]!slot;move(shift[j]!slot,d);d=tmp;endforelseif(child(p)andchild(p)!slot>lastFree)//CaseII:Insertprexonbottom.c=child(p);i=0;while(candc!slot>lastFree)shift[i++]=c;c=child(p);endwhilefor(j=i-1;j>=0;j)tmp=shift[j]!slot;move(shift[j]!slot,d);d=tmp;endforendifreturnd;Figure3-30. Scheme4getSlotalgorithm 89

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Algorithm:freeSlot(d)if(dd)shift[i++]=c;c=child(c);endwhilefor(j=i-1;j>=0;j)tmp=shift[j]!slot;move(shift[j]!slot,d);d=tmp;endforrstFree)-221()]TJ /F1 11.955 Tf 21.25 0 Td[(;elsec=nodeMap[lastFree+1];i=0;while(candc!slot=0;j)tmp=shift[j]!slot;move(shift[j]!slot,d);d=tmp;endforlastFree++;endifITCAM[d].valid=0;Figure3-31. Scheme4freeSlotalgorithm 90

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Algorithm:isTopHeavy(p)top=bot=0;for(c=parent(p);c!=NULL;c=parent(c))if(c!slot>lastFree)bot++;elsetop++;for(c=p!wt ptr;c!=NULL;c=c!wt ptr)if(cstoresaprex)if(c!slot>)]TJ /F4 11.955 Tf 9.3 0 Td[(1)//prexisalreadyplacedinTCAMif(c!slot>lastFree)bot++;elsetop++;elsek++;endifendifn=top+bot+k;return(top>n/2)?1:0Algorithm:parent(p)c=p!parentNode;while(cand!c!valid)c=c!parentNode;returnc;Algorithm:child(p)c=NULL;//don'treturnaLTCAMprexaschild.if(p!hcld ptrandp!hcld ptr!tcam==1)c=p!hcld ptr;returnc;Figure3-32. SupportingcontrolplanetriealgorithmsusedbytheScheme4getSlotandfreeSlotalgorithms 91

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3.3WideDualTCAMDUOWInthissectionweextendourDUOSschemetothecasewhenwideSRAMs(say,144-bitwordsorlarger)areinuse.WedescribetheextensiononlyforthecasewhentheLSRAMiswide.ThecasewhentheISRAMiswideusestechniquesalmostidenticaltothoseusedin[ 21 ]whileforawideLSRAM,weneedtomodifythesetechniques.Asin[ 21 ],awideLSRAMwordisusedtostoreasubtreeofthebinarytrieofaforwardingtable.However,insteadofbeginningwiththebinarytrieforallprexesasisdonein[ 21 ],webeginwiththebinarytrie,leaftrie,foronlytheleafprexes.WhenasubtreeoftheleaftrieisstoredinanLSRAMword,thatsubtreeisremovedfrom(orcarvedoutof)theleaftriebeforeanothersubtreeisidentiedforcarving.LetNbetherootofthesubtreebeingcarvedandletQ(N)betheprexdenedbythepathfromtherootofthetrietoN.Q(N)isstoredintheLTCAM,andjPij)-270(jQ(N)jsufxbits,ofeachprexPiinthecarvedsubtreerootedatN,arestoredintheLSRAMword.NotethateachsufxstoredintheLSRAMwordisasufxofaleafprexthatbeginswithQ(N).Byrepeatingthiscarvingprocess,allleafprexesareallocatedtotheLTCAMandLSRAM.ToobtainthemappingofleafprexestotheLTCAMandLSRAM,weneedacarvingalgorithmthatensuresthattheQ(N)sstoredintheLTCAMaredisjoint.Sincethecarvingalgorithmof[ 21 ]doesnotensuredisjointedness,anewcarvingalgorithmisneeded.Asanexample,considerthebinarytrieofFigure 3-33 (a),whichhasbeencarvedusingacarvingalgorithmthatensuresthateachcarvedsubtreehasatmost2leafprexes.TheLTCAMwillneedtostoreQ(N1),Q(N2)andQ(N3).Eventhoughtheprexesinthebinarytriearedisjoint,theQ(N)sintheLTCAMarenotdisjoint(e.g.,Q(N1)isadescendantofQ(N2)andsoQ(N2)matchesallIPaddressesmatchedbyQ(N1)).ToretainmuchofthesimplicityoftheLTCAMmanagementschemeofDUOSitisnecessarytocarvetheleaftrieinsuchawaythatallQ(N)sintheLTCAMaredisjoint.Asin[ 21 ],wecarveviaapostordertraversalofthebinarytrie.However,weusethevisitalgorithmofFigure 3-35 todothecarving.Inthisalgorithm,wisthenumber 92

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ALucarving[ 21 ] BOurcarvingFigure3-33. Carvingusingthemethodof[ 21 ]andourmethod ofbitsinanLSRAMwordandx!sizeisthenumberofbitsneededtostore(1)thesufxbitscorrespondingtoprexesinthesubtrierootedatx,(2)thelengthofeachsufx,(3)thenexthopforeachsufx,(4)thenumberofsufxesintheword,and(5)thelengthofQ(x),whichisthecorrespondingprexstoredintheLTCAM.AlgorithmsplitNode(q)(notspeciedinthischapter)doestheactualcarvingofthesubtreerootedatnodeq.Thebasicideainourcarvingalgorithmistoforbidcarvingattwonodesthathaveanancestor-descendentrelationship.ThisensuresthattheQ(N)saredisjoint.Figure 3-33 (b)showsthesubtreescarvedbyouralgorithm.Ascanbeseen,Q(N1),Q(N2),Q(N3)aredisjoint.AlthoughourcarvingalgorithmgenerallyresultsinmoreQ(N)sthanwhenthecarvingalgorithmof[ 21 ]isused,ourcarvingalgorithmallowsustoretaintheexibilitytostoretheQ(N)sinanyorderintheLTCAMastheQ(N)sareindependent.TheLTCAMalgorithmstoinsert,delete,change,andnecessarysupportalgorithmsaregiveninFigures 3-36 3-41 .Thefunctioncarveisinvokedbyboththeinsertanddeletealgorithmsunderdifferentcontextsthatweanalyzebelow.Whenaprexisdeleted,theLSRAMwordstoringitssufx(correspondingtotheLTCAMwordforQ(cNode))mayhaveremainingsufxesthatcanbemergedwithanotherLSRAMword.Thismergeisaccomplished 93

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bythecarvefunction,bycarvingthetrieattNode,whichisthenearestancestorwithtwochildren,ofcNode.ThuscarvehelpstoreducetheLTCAMentriesbyone.Whenaprexisinserted,itmaybepossibletoaddthesufxbitsofthenewprexintheLSRAMwordthatcorrespondstotheLTCAMslotforQ(cNode).IfthereisnocNodeinthepathbetweenthenewprexnodeandtheroot,thenwetrytocarveattNode,whichisthenearestdegree2ancestorofthenewprexnode,andthereforeincludesthenewprexalongwithotherexistingprexes.So,inthiscase,usingcarvewepreventtheadditionofanewLTCAMentryforthenewprex.NextweshowthattNodeisindeedanappropriatenodetocarveandthealgorithmpreservesthepropertyofcarvingatonlyonenodealonganypathfromtheroot.tNodeiscarvedonlyifthenumberofbitsneededtostoreallsufxesinthesubtreerootedattNodeislessthanthesizeofanLSRAMword.InthiscasethereisasingleotherNodethatisadescendantoftNodeandforwhichQ(otherNode)isintheLTCAM.ToseethattherecannotbemorethanoneotherNode,supposethereareqsuchnodeswithQ(q)intheLTCAM.AlloftheseqnodesmustbeinthesubtreeoftNodethatdoesnotcontainthetargetnode,whichiscNodeforadeleteandthenewprexnodeforaninsert.Thisisbecause,iftherewasonecarvednodetamongtheqnodesinthesubtreeofcNode,foradelete,thentmustoccureitherinthepathbetweencNodeandtNode,orasadescendantofcNode,giventhattNodeisthenearestancestorofcNodewithtwochildren.Ineithercase,tviolatesthepropertyofasinglecarvingalonganypathfromtheroot.Similarlyforaninsert,iftherewereacarvednodetinthesamesubtreethatcontainedthenewlyaddedprex,thentwouldhaveservedasthecNodeandwewouldnothavestartedthecarvealgorithmintherstplace.SinceallqnodesmustappearinthesamesubtreerootedateithertheleftorrightchildoftNode,andthesumoftheirsizesissmallenoughtotinanLSRAMword,ourcarvingalgorithmwouldhavecarvedthatchildoftNode.ThusthereisonlyoneotherNode.SincewedeleteQ(cNode)and 94

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Q(otherNode)rightafteraddingQ(tNode),thepropertyofcarvingonlyoncealonganypathismaintained.Figure 3-34 showsapossibleassignmentofthe5-prexexampleinFigure 3-7 .TheintermediateprexesP1andP2arestoredintheITCAM,whiletheleafprexesP3,P4andP5arestoredintheLTCAMusingawideLSRAM.Thesufxnodesbeginwiththeprexlengtheldof2bitsinthisexamplefollowedbythesufxcounteldof2bits.Nextcomesthe(length,sufx,nexthop)tripletforeachprexencodedinthesufxnode,thenumberofallocatedbitsbeing(2bits,4bits,6bits)respectivelyforthethreeeldsinthetriplet. Figure3-34. AssignmentofprexesofFigure 3-7 toTCAMsinthedualTCAMarchitecture 95

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Algorithm:visit postorder(x)if(!x)return0;isSplit=visit postorder(y);isSplitj=visit postorder(z);if(isSplitjjx!size>w)thensplitNode(y);splitNode(z);//whereyandzarechildrenofxreturn1;elseif(x!size==w)thensplitNode(x);return1;endifreturn0;Figure3-35. AlgorithmtocarvealeaftrietoobtaindisjointQ(N)s Algorithm:insert(node,cNode,tNode)//node:nodeinleaftriefornewprextobeinserted.//cNode:nearestcarvedancestorinleaftrieofnode(maybeNULL).//tNode:nearestdegree2ancestorofnode.if(cNode)d=cNode!slot;addSufx(d,cNode,node);LTCAM.invalidateWaitWrite(d,AV);AV=d;elseif(!carve(tNode,node))//createnewsufxnodewith1suxd=AV;AV=next[d];LTCAM.waitWriteValidate(d,Q(node),sufx);node!slot=d;endifFigure3-36. DUOWalgorithmtoinsertaprexintotheLTCAM Algorithm:addSufx(slot,cNode,node)if(sufxdoesnottinLSRAM[slot])//needanothersufxnodesplit(cNode);cNode!slot=-1;else//addsufxtoLSRAM[slot]d=AV;AV=next[d];LTCAM.waitWriteValidate(d,LTCAM[slot],LSRAM[slot]+sufx);cNode!slot=d;endifFigure3-37. AlgorithmtoaddasufxtoawideLSRAMword 96

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Algorithm:deletePrexes(node)bucketIndex=node!bIndex;len=lengthofdeleteList;for(i=0;i
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Algorithm:delete(node,cNode,tNode)//node:nodeinleaftriecorrespondingtotheprextobedeleted//cNode:nearestcarvedancestorofnodecannotbeNULL//tNode:nearestdegree2ancestornodeofcNode.oldSlot=cNode!slot;p=numberofsufxesinLSRAM[oldSlot];if(p>1and!carve(tNode,cNode))//deletesufxfromitssufxnoded=AV;AV=next[d];LTCAM.waitWriteValidate(d,LTCAM[oldSlot],LSRAM[oldSlot]-sufx);cNode!slot=d;elsecNode!slot=-1;endifLTCAM.invalidateWaitWrite(oldSlot,AV);AV=oldSlot;Algorithm:carve(tNode,cNode)if(!tNode)return0;if(sufxes(tNode)tinasufxnode)//carveattNoded=AV;AV=next[d];LTCAM.waitWriteValidate(d,Q(tNode),sufxes(tNode));tNode!slot=d;otherNode=thecarvedNodeinsubtreerootedattNodethatisnotcNode;LTCAM.invalidateWaitWrite(otherNode!slot,AV);AV=otherNode!slot;otherNode!slot=-1;return1;endifreturn0;Figure3-40. DUOWalgorithmtodeletealeafprex Algorithm:change(prex,cNode,nexthop)oldSlot=cNode!slot;d=AV;AV=next[d];newWord=LSRAM[oldSlot]withnexthopforcNode!prexsettonexthop;LTCAM.waitWriteValidate(d,prex,newWord);cNode!slot=d;LTCAM.invalidateWaitWrite(oldSlot,AV);AV=oldSlot;Figure3-41. DUOWalgorithmtochangethenexthopofaleafprex 98

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3.4IndexedDUOWIDUOWZaneetal.[ 55 ]introducedtheconceptofanindexedTCAMthatreducessignicantlythepowerconsumedbyaTCAMlookup.ThisconceptwasrenedbyLuandSahni[ 21 ]toreduceboththeTCAMpowerandspacerequirementssubstantially.WeshowhowtoincorporateanindexTCAMinconjunctionwithanLTCAMthatusesawideLSRAM(i.e.,anindexfortheLTCAMofDUOW).AddinganindextotheITCAMofDUOWfollowseasilyfrom[ 21 ].WhentheLTCAMisindexed,wehavetwoTCAMsreplacingtheLTCAMadataTCAMreferredtoasDLTCAMandinindexTCAMreferredtoasILTCAM.TheassociatedSRAMsareDLSRAMandILSRAM.WeconsiderthetwomosteffectiveindexTCAMstrategiesof[ 21 ]-12WcandM-12Wb.TheformerisbestforpowerwhereasthelatteristhebestoverallschemeconsumingleastTCAMspaceandlowpowerforlookups[ 21 ].Both1-12WcandM-12WborganizetheDLTCAMintoxedsizebucketsthatareindexedusingtheILTCAMandILSRAM,whichalsoisawideSRAMthatstoressufxesandassociatedinformation. 3.4.1MemoryManagementforDLTCAMandILTCAMEachDLTCAMbucketisassignedauniquenumberbetween0andtotalSlots=bucketSize,wheretotalSlotsisthetotalnumberofDLTCAMslots.Theuniquenumbersoassignedtoabucketiscalleditsindex.Abucketindexisstoredinthetrienode(ineldbIndex)thatiscarvedandrepresentsanindexprexenclosingtheDLTCAMprexesinthebucket.ThefreeslotsinabucketarelinkedthroughtheassociatedDLSRAM.Therstseveralbits(32shouldbeenough)ofaDLSRAMwordstoretheaddressofthenextfreeDLTCAMslotinthesamebucket.Thelastfreeslotinabucketstores-1inbits0-31ofthecorrespondingDLSRAMword.Foreachbucketwekeeponefreeslotatalltimes.Thisfreeslotisusedforconsistentupdates,tocopythenewprexbeforedeletingtheoldone.TherstfreeslotinabucketisstoredinanarrayAVindexedbythebucketindex.ThearrayAVisinitializedandmaintainedinthecontrolplane.Alistof 99

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freebucketsismaintainedintheDLSRAMusingadditionalbitsofeachDLSRAMword(12bitsaresufcientwhenthenumberofbucketsisatmost4096).TherstavailableslotinafreebucketstoresthebucketindexofthenextfreebucketintheDLSRAMbitsandsoon.Thefreebucketchainisterminatedbya)]TJ /F4 11.955 Tf 9.3 0 Td[(1inthebitsusedtostoretheindexofthenextfreebucket.ThevariablebucketAVkeepstrackoftherstbucketonthefreebucketchain.InouralgorithmsweusethearraynextBuckettorepresenttheforwardlinksinthebucketlist.WhentheprexesinanILTCAMaredisjoint,wemayusethesimplememorymanagementschemeusedfortheLTCAMofDUOSandwhentheseprexesarenotdisjoint,theymustbeorderedandanyofthememorymanagementschemesproposedfortheITCAMofDUOSinSection 3.2.4 maybeused.Theupdatealgorithms(Figures 3-42 3-38 )arealmostidenticalfor1-12WcandM-12Wb.Weexplainthedifferencesinthenexttwosubsections. 100

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Algorithm:insert(node,cNode,tNode,isramNode,itcamNode,itNode)//node:nodeinleaftriefornewprextobeinserted.//cNode:nearestcarvedancestorinleaftrieofnode(maybeNULL).//tNode:nearestdegree2ancestorofnode.//isramNode:indexnodeenclosingcNode//itcamNode:nodewhoseprexexistsinILTCAM.//itNode:nearestdegree2ancestorofisramNode.if(cNode)bucketIndex=isramNode!bIndex;d=cNode!slot;addSufx(d,cNode,node,isramNode,itcamNode,itNode);DLTCAM.invalidateWaitWrite(d,AV[bucketIndex]);AV[bucketIndex]=d;elseif(!carve(tNode,node,bucketIndex))//createnewsufxnodewith1suxif(isramNode)thenbucketIndex=isramNode!bIndex;d=AV[bucketAV];AV[bucketAV]=next[d];if(AV[bucketAV]==-1)thensplitBucket(isramNode,itcamNode,itNode);if(node!slot==)]TJ /F4 11.955 Tf 9.3 0 Td[(1)//slothasnotbeenassignedinsplitBucketN=descendantofisramNodepointingtoaDTCAMbucketandenclosingnode.newd=AV[N!bIndex];AV[N!bIndex]=next[newd];AV[bucketAV]=d;d=newd;endifendifif(node!slot==)]TJ /F4 11.955 Tf 9.3 0 Td[(1)DLTCAM.waitWriteValidate(d,Q(node),sufx);decrementRoom(bucketIndex);endifelseassignNewBucket(node);d=AV[node!bIndex];AV[node!bIndex]=next[d];DLTCAM.waitWriteValidate(d,Q(node),sufx);node!slot=d;ILTCAM.insert(node,NULL,NULL);endifendifFigure3-42. DLTCAMinsertalgorithm 101

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Algorithm:addSufx(slot,cNode,node,isramNode,itcamNode,itNode)if(sufxdoesnottinDLSRAM[slot])//needanothersufxnodesplit(cNode,isramNode,itcamNode,itNode);cNode!slot=-1;else//addsufxtoDLSRAM[slot]bucketIndex=isramNode!bIndex;d=AV[bucketIndex];AV[bucketIndex]=next[d];DLTCAM.waitWriteValidate(d,DLTCAM[slot],DLSRAM[slot]+sufx);cNode!slot=d;endifFigure3-43. AddasufxtoaDLSRAMword 102

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Algorithm:split(cNode,isramNode,itcamNode,itNode)if(cNode!yandcNode!z)//carveatchildreny&zofcNodebucketIndex=isramNode!bIndex];if(next[AV[bucketIndex]]==-1jjnext[next[AV[bucketIndex]]]==-1)splitBucket(isramNode,itcamNode,itNode);//AV[bucketIndex]shouldgetresethereif(isramNodeisnotthesameascNode)thenif(cNode!y!slot==-1)thenN=descendantofisramNodepointingtoaDTCAMbucketandenclosingnode.cNode!y!slot=AV[N!bIndex];cNode!z!slot=next[AV[N!bIndex]];AV[N!bIndex]=next[next[AV[N!bIndex]]];decrementRoom(N!bIndex,2);endifincrementRoom(bucketIndex,1);elseif(cNode!y!slot==-1)cNode!y!slot=AV[isramNode!child[0]!bIndex];AV[isramNode!child[0]!bIndex]=next[cNode!y!slot];decrementRoom(isramNode!child[0]!bIndex,1);endifif(cNode!z!slot==-1)cNode!z!slot=AV[isramNode!child[1]!bIndex];AV[isramNode!child[1]!bIndex]=next[cNode!z!slot];decrementRoom(isramNode!child[1]!bIndex,1);endifincrementRoom(bucketIndex,1);endifelsecNode!y!slot=AV[bucketIndex];cNode!z!slot=next[AV[bucketIndex]];AV[bucketIndex]=next[next[AV[bucketIndex]]];decrementRoom(bucketIndex,1);endifDLTCAM.waitWriteValidate(cNode!y!slot,Q(cNode!y),sufxes(cNode!y));DLTCAM.waitWriteValidate(cNode!z!slot,Q(cNode!z),sufxes(cNode!z));elseif(cNode!y)split(cNode!y);elsesplit(cNode!z);endifFigure3-44. SplitaDLSRAMword 103

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Algorithm:delete(node,cNode,tNode,isramNode,itcamNode,itNode)//node:nodeinleaftriecorrespondingtotheprextobedeleted//cNode:nearestcarvedancestorofnode,cannotbeNULL//tNode:nearestdegree2ancestornodeofcNode.//isramNode:indexnodeenclosingcNode//itcamNode:nodewhoseprexexistsinILTCAM.//itNode:nearestdegree2ancestorofitcamNode.bucketIndex=isramNode!bIndex;oldSlot=cNode!slot;p=numberofsufxesinDLSRAM[oldSlot];if(p>1and!carve(tNode,cNode,bucketIndex))//deletesufxfromitssufxnoded=AV[bucketIndex];AV[bucketIndex]=next[d];DLSRAM[d]=DLSRAM[oldSlot]-sufx;DLTCAM[d].prex=DLTCAM[oldSlot].prex;DLTCAM[d].valid=1;cNode!slot=d;elsecNode!slot=-1;if(isramNode!size==0)then//bucketbecomesemptydeleteBucket(isramNode,itcamNode,itNode);endifdecrementRoom(bucketIndex);endifDLTCAM.invalidateWaitWrite(oldSlot,AV[bucketIndex]);AV[bucketIndex]=oldSlot;Algorithm:carve(tNode,cNode,bucketIndex)if(!tNode)return0;if(sufxes(tNode)tinasufxnode)//carveattNoded=AV;AV=next[d];DLSRAM[d]=sufxes(tNode);DLTCAM[d].prex=Q(tNode);DLTCAM[d].valid=1;tNode!slot=d;otherNode=thecarvedNodeinsubtreerootedattNodethatisnotcNode;DLTCAM.invalidateWaitWrite(otherNode!slot,AV[bucketIndex]);AV[bucketIndex]=otherNode!slot;otherNode!slot=-1;return1;endifreturn0;Figure3-45. Deletealeafprex 104

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Algorithm:change(prex,cNode,nexthop,isramNode)oldSlot=cNode!slot;bucketIndex=isramNode!bIndex;d=AV[bucketIndex];AV[bucketIndex]=next[d];newWord=DLSRAM[oldSlot]withnexthopforcNode!prexsettonexthop;DLTCAM.waitWriteValidate(d,prex,newWord);cNode!slot=d;DLTCAM.invalidateWaitWrite(oldSlot,AV[bucketIndex]);AV[bucketIndex]=oldSlot;Algorithm:deleteBucket(isramNode,itcamNode,itNode)bucketIndex=isramNode!bIndex;nextBucket[bucketIndex]=bucketAV;bucketAV=bucketIndex;isramNode!bIndex=-1;ILTCAM.delete(isramNode,itcamNode,itNode);Algorithm:splitBucket(isramNode,itcamNode,itNode)if(isramNode!yandisramNode!z)//carveatchildreny&zofisramNode//Wewanttomovethesplitchildthatcontainsfewerprexes.if(isramNode!ycontainsfewerprexes)isramNode!y!bIndex=isramNode!bIndex;assignNewBucket(isramNode!z);node=isramNode!z;elseassignNewBucket(isramNode!y);isramNode!z!bIndex=isramNode!bIndex;node=isramNode!y;endifILTCAM.insert(isramNode!y,itcamNode,itNode);ILTCAM.insert(isramNode!z,itcamNode,itNode);ILTCAM.delete(isramNode,itcamNode,itNode);deletePrexes(node);elseif(isramNode!y)splitBucket(isramNode!y,itcamNode,itNode);elsesplitBucket(isramNode!z,itcamNode,itNode);endifFigure3-46. Changethenexthopofaleafprex 105

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3.4.21-12WcThistwo-levelTCAMorganizationin[ 21 ]employswideSRAMsinassociationwithboththedataandindexTCAMsasshownintheFigure 3-47 .Thestrategyadoptedin[ 21 ]tolluptheTCAMsandtheSRAMsissummarizedasfollows.Firstly,sufx Figure3-47. 1-12Wccongurationin[ 21 ] nodesarecreatedforprexesinthe1-bittrie,asdescribedinSection 3.3 ,usingLu'scarvingheuristic.Secondly,everyQ(N)tobeenteredinthedataTCAM,istreatedasaprexandthesubtreesplitalgorithm[ 21 ]isappliedtocarveindexnodesinthetrie.ThecarvingisdonesothatthenumberofdataTCAMprexesenclosedbythenodebeingcarved,islessthanorequaltothesizebofadataTCAMbucket.Anewbucketisassignedtoeveryindexnode.AnencloseddataTCAMprexandthecorrespondingsufxnodeareenteredinanewentryinthebucket.Whenanindexnodeenclosesfewerthanbprexes,theremainingentriesinthebucketarepaddedwithnullprexes.Finally,theindexnodesaretreatedasprexes,thealgorithmtocreatesufxnodesisrunonthetriecontainingonlyindexprexes.ThenewlycarvedindexQ(N)prexesandthecorrespondingsufxnodesareenteredintheindexTCAMandtheassociatedwideSRAMrespectively.Usingthisstrategy,thebucketnumberscorrespondingtothesufxesinanindexSRAMsufxnode,happentobeconsecutive.Hence,theindexSRAMomitsthebucketnumberforallsufxesexceptthestartingsufx,asshownintheFigure 3-47 106

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Duringincrementalupdates,ifabucketoverowsthenassigninganewbucketimmediatelynexttotheoverowingbucketmayrequirealargenumberofmoves.HencethesufxnodeformatinIDUOWstoresthebucketnumberforeachsufx,whichmakesitpossibletoassignanyemptybucketincaseofanoverow.ThesufxnodeformatfortheILSRAMfor1-12WcisshowninFigure 3-48 .Also,inkeepingwiththemainideaof Figure3-48. Our1-12Wcconguration storingindependentprexesintheLTCAM,thevisit postorderalgorithmisusedinsteadofthesubtreesplitalgorithmin[ 21 ]whilellingouttheTCAMs.Theprexassignmentalgorithmfor1-12Wcisgivenbelow. 1. Sufxnodescorrespondingtoprexesintheforwardingtablearecreatedusingthevisit postorderalgorithmonthe1-bitleafprextrieasshowninSection 3.3 2. EachQ(N)prexresultingfromStep1istobeenteredintoDLTCAMandismarkedasaDLTCAMprexinthetrie. 3. Thevisit postorderalgorithmisappliedtocarvetheindexprexnodes.Thesymbolsusedinthevisit postorderalgorithmhaveslightlydifferentmeaningnow:x!sizerepresentsthenumberofDLTCAMprexesenclosedbynodex,andwisb)]TJ /F4 11.955 Tf 12.9 0 Td[(1,wherebisthesizeofaDLTCAMbucketwithonefreeslotforconsistentupdates.Asanindexnodeiscarved,theenclosedDLTCAMprexesareenteredinanewDLTCAMbucket,andthebucketindexisstoredinthetrienode,correspondingtotheindex,ineldbIndex. 4. EachQ(N),fortheindexnodescarvedinStep3,ismarkedasanindexprexinthetrie. 5. Sufxnodesarecreatedfortheindexprexesusingthevisit postorderalgorithmonthe1-bittriecontainingtheindexprexes.TheQ(N)prexescorrespondingtothecarvednodesareenteredintheILTCAM.Sufxesfortheindexprexesare 107

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Algorithm:assignNewBucket(node)node!bIndex=bucketAV;if(bucketAV==-1)throwNoBucketsException;bucketAV=nextBucket[bucketAV];Figure3-49. Assignanewbucketin1-12Wc enteredinILSRAMalongwiththeirbucketindexes,intheILSRAMsufxnodeformatasshownintheFigure 3-48 .ThefunctionsincrementRoomanddecrementRoomarenotrelevantfor1-12Wcandarenullfunctions.TheassignNewBucketfunctionisoutlinedinFigure 3-49 .The1-12WcschemelosesspaceefciencyaswecarveoutindependentindexprexnodesanduseasinglebuckettostoretheDLTCAMprexesenclosedbyasingleindexprex.TheM-12Wbschemedoesn'thavethisdeciencyasDLTCAMprexesfromindexprexesarestoredinthesamebucket. 3.4.3M-12WbThecharacteristicofthemany-1schemesin[ 21 ]isthatallDTCAMbuckets,exceptthelastone,canbecompletelylled.ThusmultipleindexnodesusethesamebuckettostoretheirencloseddataTCAMprexes.ThecongurationforM-12WbisshowninFigure 3-50 .Thealgorithmforcarvingandprexassignmentfollows: Figure3-50. M-12Wbcongurationin[ 21 ] 1. Step1:[SeedtheDLTCAMbuckets]RunfeasibleST2(T,b)]TJ /F4 11.955 Tf 12.06 0 Td[(1)dn=(b)]TJ /F4 11.955 Tf 12.06 0 Td[(1)etimes.//b)]TJ /F4 11.955 Tf 12.07 0 Td[(1,sinceonefreeslotisneededinabucketforconsistentupdates.EachtimecallsplitNodetocarvethefoundbestSTfromT(therebyupdatingT)andpackbestSTintoanewDLTCAMbucket. 108

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ThefunctionsplitNodeaddsoneormoreprexestotheILTCAM. 2. Step2:[Fillthebuckets]WhilethereisaDLTCAMbucketthatisnotfullandTisnotempty,repeatStep3. 3. Step3:[Addtoabucket]LetBbetheDLTCAMbucketwiththefewestnumberofprexes.LetsbethenumberofprexesinB.RunfeasibleST2(T,b)]TJ /F3 11.955 Tf 11.95 0 Td[(s).UsingsplitNodecarvethefoundbestSTfromT(therebyupdatingT)andpackbestSTintoB.ThefunctionsplitNodeaddsoneormoreprexestotheILTCAM. 4. Step4:[Useadditionalbucketsasneeded]WhileTisnotempty,llanewDLTCAMbucketbymakingrepeatedinvocationsoffeasibleST2(T,q),whereqistheremainingcapacityofthebucket.AddILTCAMprexesasneeded.TherearethreemaindifferencesbetweenthisalgorithmandthePS2algorithmin[ 21 ].Therstdifferenceisreectedinthevisit2algorithm(invokedbyfeasibleST2)inthatcoveringprexesarenotstoredintheTCAMs.Theseconddifferenceisinsupplyingb)]TJ /F4 11.955 Tf 13.22 0 Td[(1asavailablespaceinanemptybucketofsizeb,reservingonefreeslotforconsistentupdates.ThethirddifferenceisintheuseofcarvingfunctionsplitNodewhichhelpstocreateindependentprexesforIDUOW.Apartfromthedatastructuresalreadydenedforthetwo-levelindexingschemes,theM-12Wbrequiresadoublylinkedlistofusedbucketstokeeptrackofthebucketsandtheavailablespacesinthem.AninstanceofaclassBListismaintainedinthecontrolplanewhichcontainsthedoublylinkedlistofbucketsaswellasanarraytogettotherightbucketquicklyusingabucketindex.Eachbucketinthelisthaseldsroomtoindicateavailablebucketslotsandindextoindicatetheindexofthebucket.Theroominabucketdecreasesfromheadtotailofthelist.BListusesfunctionaddtoaddanewbuckettothelistandthearrayandgetBuckettogettheappropriatebucketbasedonbucketindex. 109

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Algorithm:visit2(x)d=count(x);//returnsthenumberofDLTCAMprexes.if(dqandd>bestCount)bestST=ST(x);bestCount=d;endif//checkT-ST(x)d=count(root(T))-count(x);if(dqandd>bestCount)bestST=T-ST(x);bestCount=d;endifFigure3-51. Visitalgorithm Algorithm:splitNode(N,NoN)NoNistrienodexifbestST=T-ST(x),otherwiseNoNispassedasNULL.if(!NjjN==NoN)return;if(N!istouched==0)N!istouched=1;N!bIndex=BList.head!index;llbucketwithDLTCAMprexesinN.Lets=numberofDLTCAMprexesinN.BList.head!room=BList.head!room-s.endifsplitNode(N!y);splitNode(N!z);Figure3-52. Splitanode Algorithm:assignNewBucket(node)Lets=numberofDLTCAMprexesinnode.if(s-1)node!bIndex=bucketAV;BList.add(bucketSize,bucketAV);BList.head!room-=s;bucketAV=nextBucket[bucketAV];elseif(BList.head!room==1)throwNoSpaceException;Runstep3inPS2whilenodestillhasaprex;endifFigure3-53. Assignanewbucket 110

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Algorithm:incrementRoom(bucketIndex)b=BList.getBucket(bucketIndex);b!room++;ifb!prevandb!room>b!prev!roomthenrelocatebtorestoreorder.Algorithm:decrementRoom(bucketIndex)b=getBucket(bucketIndex);b!room;ifb!nextandb!room
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3.5ExperimentalResultsWeevaluatedtheperformanceofthedifferentversionsofDUOusing21IPv4routingtablesandupdatesequencesdownloadedfrom[ 6 ]and[ 37 ].Table 3-1 givesthecharacteristicsofthesedatasets.Theupdatesequencesfortherst20routingtableswerecapturedfromlesstoringupdateannouncementsfrom12amonFebruary1,2009forthestatednumberofhours;theupdatesequenceforthelastroutingtablerrc00May20wascapturedfromlesstoringeighthoursofactivitystartingfrom12amonMay20,2008.Thecolumnslabeled#RawInserts,#RawDeletesand Table3-1. Datasetsusedintheexperiments DataSet#PrexesTime(hrs)#RawInserts#RawDeletes#RawChanges rrc0029409875.73955340051368013rrc0127679575.24169241988492315rrc0328375442.72770227914292454rrc0428861017.01608615977193392rrc05280041103.02027618285439647rrc06278744235.0157549157547289272rrc072750970.417247218179835rrc10278898105.02162022473326720rrc1127716680.25811558378290621rrc1227849962.33319633572410464rrc1328498657.82392023713284710rrc1427617083.65659856810203955rrc15284047134.09579093750183131rrc16282660672.033389378896route-views229412756.51388215552679100route-views427573795.06962769754526302route-views.eqix27573670.35110451066253693route-views.isc28109568.24428644444292323route-views.linx27819649.12313723413384344route-views.wide283569174.0101821103862372035rrc00May202661858.05392532245542 #RawChanges,respectively,givethenumberofinsert,delete,andchangenexthoprequestsintheupdatesequences.Usingconsistentupdates,anexthopchangerequestisimplemented(seeFigure 3-15 forexample)asaninsert(oftheprexwiththenewnexthop)followedbyadelete(oftheprexwiththeoldnexthop).Therefore,allresults 112

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henceforthareintermsoftheeffectiveinsertsanddeletes.Notethatthenumberofeffectiveinserts(#Inserts)anddeletes(#Deletes)isgivenbythefollowingequations. #Inserts=#RawInserts+#RawChanges;(3) #Deletes=#RawDeletes+#RawChanges;(3) 3.5.1EvaluationofMemoryManagementSchemesWerstranasetofexperimentsonthesimpleTCAM[ 21 ]tocompareourmemorymanagementschemesSchemes1-4.ThesimpleTCAMweinstantiatedfortheexperimentshas300,000slots.Tables 3-2 and 3-3 ,respectively,givethetotalandaveragenumberofprexmoves(i.e.,numberofinvocationsofmove())requiredforaninsert(includesrawinsertschangenexthopinserts)andadeleteinourtestupdatesequences(thedatainTable 3-3 isobtainedfromthatinTable 3-2 bydividingby#Insertsor#Deletes).Notethatthetheoreticalworst-casenumberofmovesforaninsert/deleteinIPv4forthefourmemorymanagementschemesis,respectively,16,32,32and16.Tables 3-4 and 3-5 ,respectively,givethemaximumnumberofmovesperinsert/deleteandthestandarddeviation.Fromourexperiments,wemakethefollowingobservations: 1. Scheme1(PLO OPT)requiredthemaximumnumberofmoves(sumofmovesforinsertsanddeletes)forallourtestsetsandScheme3requiredtheleast.Infact,thedisparityamongthe4schemesisverysignicantwithScheme3requiringatotalnumberofmovesthatisordersofmagnitudelessthanthatrequiredbytheremainingschemes.Schemes2iscomparabletoScheme4andScheme1requires10times(ormore)asmanymovesasrequiredbySchemes2and4. 2. ThenumberofmovesduetoinsertsinScheme2islowerthanthoseinScheme4(CAO OPT)byordersofmagnitude.Forsomeofourtestsets,insertsrequirednomoveswhenScheme2wasused. 3. ThenumberofmovesduetodeletesinScheme2iscomparabletothatinScheme4(CAO OPT). 113

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4. ThenumberofmovesduetoinsertsinScheme3islowerthanthatinScheme4(CAO OPT)byordersofmagnitude.Fortheinsertsinsomeofourtestsets,Scheme3requirednomovesatall. 5. Thenumberofmovesduetodeletesis0inScheme3becauseinthisschemetheslotwithinablock,freedbyadeleteissimplyappendedtothefreespacelistfortheblock. 6. Themaximumnumberofmovesperinsert/deleteaboutthesameforSchemes2,3and4,andabouthalfthatforScheme1.WenotethatScheme4hasabetterworst-caseperformanceforinsertsthanSchemes2and3butisworsefordeletes. 7. ThestandarddeviationisverysmallforSchemes2and3.Thenumberofmoves,neededforaninsertoperationusingScheme3,haslowaverageandstandarddeviationvalues.So,thenumberofTCAMmovesforanyinsertoperationis,withagoodprobability,verylowaswellwhenScheme3isused.Thenumberofmoves,neededforadeleteoperationusingScheme3,haszeroaverageandstandarddeviationvaluessinceScheme3doesnotinvolveanymoveforadeleteoperation.WealsonotethatforSchemes2and4,thenumberofmovesduetodeletesismuchmorethanthatduetoinserts.ForScheme4thisisbecauseadeleterarelyoccursadjacenttoeitherofthetwoboundariesofthefreespacepoolandnon-boundarydeletesrequireatleastonemovetoshifttheemptyslottothefreespacepool.However,sincetheprextrieisshallowandthefreespacepoolcutseachroottoleafpathinthemiddle,manyoftheinsertsinanupdatesequenceareexpectedtooccurataboundaryofthefreespacepool.So,insertstakemuchlessthan1move,onaverage,whenScheme4isused.Similarly,whenScheme2isused,mostdeletesarefromwithinablockratherthanatablockboundary.Thesenon-boundarydeletesrequire1moveeach.However,aninsertrequiresnomovesifthereisafreeslotatthetoporbottomofitsblock,alikelyoccurrence.Table 3-6 showsthenumberofwaitWrites(sumofinvocationsofwaitWriteValidate()andinvalidateWaitWrite()),whichistheequaltothesumofinserts,deletesandmovesforthesimpleTCAMandreectstheupdateperformanceforthefourmemorymanagementschemes.Asexpected,Scheme3requirestheleastnumberofoperations,duetothesmallnumberofmoves.ForScheme3,theaveragenumberofwaitWritesper 114

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insertanddelete(numberofwaitWrites/(#Inserts+#Deletes))rangedfromalowof1forrrc01,rrc07,rrc16,route-views.linxtoahighof1.0072forrrc03.Figure 3-55 (a)showsthenormalizedaveragenumberofmovesforeachschemeonalogarithmicscale.Forthisgure,wecomputedtheaveragenumberofmovesperInsert/Deleteforeachdataset.ThentheaverageoftheseaverageswascomputedandnormalizedbytheaverageofaveragesforScheme3.Figure 3-55 (b)showsthenormalizedaveragewaitWritesinvokedbythedifferentschemes.Forthisgure,wecomputedtheaveragenumberofwaitWritesperInsert/Deleteforeachdataset,thencomputedtheaverageoftheseaveragesforeachmemorymanagementschemeandnallynormalizedbytheaverageoftheaveragesforScheme3. Table3-2. NumberofmovesforthesimpleTCAM DatasetScheme1Scheme2Scheme3Scheme4 insertdeleteinsertdeleteinsertdeleteinsertdelete rrc0025278992938315395404839401028621405733rrc013106800364182705313970057619529312rrc031933994225445146223174454630035144321432rrc041260636146750202081422061507221368rrc0527658743210264543455214541048677461485rrc062785323322845084359978011452439501rrc07973836115371301799870035256206623rrc1020902632444704658347529671030037355326rrc1121002182449182266343898245017726342096rrc122657748310191646654387594659044243448979rrc13178454520901021035304541989053433560835rrc141517650177878542559644018265255381rrc151682880194030329862668852769022314286126rrc167186467329097770058011075route-views2414065348443421469124014092948697924route-views435841274177510141590235141039481586756route-views.eqix181305421158413330025933014235301296route-views.isc200332023384931233157012013537326232route-views.linx2440442284813804042760039136403168route-views.wide2918481340268414628011018559466695rrc00May203115883613231950512220638050946 115

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Table3-3. AveragenumberofmovesforthesimpleTCAM DatasetScheme1Scheme2Scheme3Scheme4 insertdeleteinsertdeleteinsertdeleteinsertdelete rrc006.207.200.0009690.99210.0009840.00.07020.994rrc015.86.80.00.99450.00.00.10780.9906rrc036.047.040.01440.99090.01450.00.10981.0033rrc046.017.010.00.99410.000010.00.2931.0573rrc056.017.010.001180.9940.001180.00.10581.0078rrc066.237.230.0000180.9760.000020.00.02560.9836rrc075.416.410.00.99960.00.00.19581.1476rrc106.007.000.001890.99520.001930.00.08621.0176rrc116.027.010.0007620.98540.00070.00.05080.9802rrc125.996.990.01050.98810.01050.00.09971.0111rrc135.786.770.003350.98740.00320.00.17311.0351rrc145.826.820.0000150.98160.0000150.00.07010.979rrc156.037.010.01070.9630.00990.00.081.0333rrc165.876.840.00.99430.00.00.04741.1263route-views25.976.970.000020.99510.000020.00.13411.0047route-views46.017.010.0002360.990.0002360.00.06630.9843route-views.eqix5.946.940.0001080.985230.0001080.00.04670.9886route-views.isc5.956.940.0000360.98460.0000360.00.04020.969route-views.linx5.986.980.00.99140.00.00.0960.9887route-views.wide6.157.150.0000020.97250.0000020.00.03920.9807rrc00May206.127.100.000370.993080.0004310.00.12531.0016 Figure3-55. Comparisonofperformancebetweendifferentmemorymanagementschemes 116

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Table3-4. MaximumnumberofmovesforthesimpleTCAM DatasetScheme1Scheme2Scheme3Scheme4 insertdeleteinsertdeleteinsertdeleteinsertdelete rrc001516818045rrc011516010035rrc031415717035rrc041415011055rrc051415717045rrc061112111045rrc071112010045rrc101516313036rrc111415515035rrc121516818035rrc131516818045rrc141516212035rrc151415717035rrc161413010025route-views21516212035route-views41314616026route-views.eqix1415212035route-views.isc1516111026route-views.linx1516011026route-views.wide1414111035rrc00May201516414036 EffectofTCAMSizeonMemoryManagementSchemes ThenumberofmovesrequiredbyanupdatesequenceisindependentofthesizeoftheTCAM(providedthereareenoughslotstoaccommodateallprexes)whenSchemes1and4areused.This,however,isnotthecaseforSchemes2and3.BecauseoftherelativelypoorperformanceofScheme2inourearliertest(Table 3-2 ),wedidnotstudytheimpactofTCAMsizeonthenumberofmovesusingthisscheme.Table 3-7 givesthenumberofmovesrequiredbytheinserts(effective)ineachofourtestupdatesequencesforvaryingTCAMsize.Thecolumnlabeled#Prexesgivestheinitialnumberofprexesintheroutingtablewhilethatlabeled#MaxPrexesgivesthemaximumsizeattainedbytheroutingtableduringthecourseoftheupdatesequence.TheTCAMoccupancyisdenedtobe#MaxPrexes/(TCAMsize)*100%.Forourexperiment,weselectedTCAMsizesoastohaveoccupanciesof80%,90%,95%, 117

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Table3-5. StandarddeviationinnumberofmovesforthesimpleTCAM DatasetScheme1Scheme2Scheme3Scheme4 insertdeleteinsertdeleteinsertdeleteinsertdelete rrc001.5821.5780.0640.0880.0640.00.2760.196rrc011.9571.9510.00.07350.00.00.3140.212rrc031.7501.7470.3110.0950.3110.00.3370.212rrc042.4342.4210.00.0760.0030.00.5540.276rrc051.6751.6690.0770.0770.0770.00.3330.170rrc061.4571.4530.0040.1540.0040.00.1630.274rrc072.1682.1680.00.0190.00.00.4120.407rrc101.8881.8820.0670.0690.0690.00.2880.246rrc111.6991.6970.040.120.03770.00.2230.262rrc121.8961.890.270.10830.270.00.3070.281rrc132.1442.13650.1170.1110.1140.00.4490.245rrc141.8341.8330.0050.1340.0050.00.2860.287rrc152.0662.04280.2160.1860.2120.00.2790.310rrc161.77221.83660.00.99430.00.00.2150.406route-views21.7461.7440.0050.070.0050.00.3710.14route-views41.7561.7540.0340.0980.0340.00.2510.218route-views.eqix1.7221.7200.01070.12060.01070.00.2130.243route-views.isc1.6911.6860.0060.12320.0060.00.19920.2627route-views.linx1.9331.9280.00.0920.00.00.3060.212route-views.wide1.5021.50.00150.1640.00150.00.1980.266rrc00May201.74791.72860.02840.08290.03130.00.34170.228 97%,and99%.Ascanbeseen,evenwithanoccupancyof99%,ourScheme3doesverywell.Infact,itsnearestcompetitor,Scheme4(CAO OPT),requiresbetween72and241879timesasmanymoves(forinsertsanddeletescombined)asrequiredbyScheme3(seeTable 3-2 forthenumberofmovesrequiredbyScheme4). 3.5.2EvaluationofDUOSInDUOS,eachprexintheforwardingtableoccupiesaslotineithertheITCAMortheLTCAM.Columns2and5ofTable 3-8 givetheinitialprexdistributionbetweenthe2TCAMsofDUOS.Columns3and6givethedistributionoftheinserts(i.e.,numberofnon-leafinsertsandnumberofleafinserts)whilecolumns4and7givethedistributionofthedeletes.Wenotethataleafinsert/deletemaytriggeradditionalinsertand/ordeleteoperationsontheTCAMSofDUOS.Theseadditionalinserts/deletesareaccountedforinTable 3-8 .Asaresult, 118

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Table3-6. NumberofwaitWritesforthesimpleTCAM DatasetScheme1Scheme2Scheme3Scheme4 rrc00628184412208648160311249984rrc017816937159970710683101655241rrc034828969962591645154997100rrc043146985626989418849701722rrc05689399313736129183961428017rrc06690741313296458936481344593rrc072487684540122360135602014rrc10523250010457206982041082896rrc11524713510418996979801057557rrc12664736013311208923551380918rrc134491700922629618042989752rrc143817753777286521322794964rrc154178985825673558571864242rrc16161260318442206733722route-views210372629207888813876482178506route-views48953622178236111921261818222route-views.eqix4538451909848609589925087route-views.isc501518910049586733881013145route-views.linx610381812195148152381257542route-views.wide727091814125559497541435007rrc00May20774709152329101820159124 ITCAM.#inserts+LTCAM.#inserts#Inserts(3)Itisinterestingtonotethatmorethan90%oftheprexesineachdatasetareleafprexesandthatmorethan90%oftheinsertsanddeletesineachupdatesequencearedirectedattheLTCAM.Giventhedistributionoftheprexesandinsertanddeleteoperations,weinstantiatedanLTCAMwith300,000slotsandanITCAMwith28,000slotsforourDUOSexperiments.SincetheperformanceofDUOSisdeterminedbythenumberofwaitWriteoperations,wemeasurethisquantityforourdatasets.Inaddition,sincethenumberofmovesdirectlyimpactsthenumberofwaitWriteoperations,wemeasuredthenumberofmovesseparatelysotocomparetheeffectofthefourmemorymanagementschemesforITCAM.Table 3-9 givesthenumberofITCAMmovesforinsertsanddeletes.The 119

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Table3-7. NumberofScheme3movesforinserts Dataset#Prexes#MaxPrexesOccupancy 80%90%95%97%99% rrc002940982943180096227554rrc0127679527700200031307rrc0328375428446434124311464147744916rrc0428861028891500251144rrc05280041282223180383584696810rrc0627874427920205111797rrc0727509727513000001rrc1027889828015838149079810441355rrc1127716627739139168362514668rrc1227849927915525884174496652125448rrc1328498628562112059297311071272rrc14276170276385021451146rrc1528404728646716522392273628382982rrc1628266028517000000rviews2294127294598000428rviews427573727603512106178201222rviews.eqix275736276230122997166269rviews.isc281095281430051420131rviews.linx27819627828300034348rviews.wide283569284569011119rrc00May202661852673441332101173430 numberofmovesshowninTable 3-9 includestheITCAMmovesresultingfromITCAMoperationstriggeredbyLTCAMinsertsanddeletesaswell(forexample,wheninsertingaleafprex,weinsertintotheLTCAManddeleteitsparentprex(ifany)fromtheLTCAMandreinsertthisparentprexintotheITCAM).Therelativeperformanceofthe4memorymanagementschemesforITCAMisquitesimilartothatobservedforasimpleTCAMorganizationandScheme3outperformstheremainingschemeshandily.Table 3-10 showsthenumberofwaitWritesgeneratedintheITCAMandwendthatScheme3isthebestforthismetricasexpectedfromthesmallernumberofmovesrequiredbyScheme3.Table 3-11 givesthenumberofLTCAMmovesrequiredbythe 120

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Table3-8. Distributionofprexes,inserts,anddeletesforDUOS DatasetITCAMLTCAM #Prexes#inserts#deletes#Prexes#inserts#deletes rrc00273812745427483266717388106388575rrc01247873979639789252008501753502056rrc03261163046130464257638296757296966rrc04251372054920535263473192299192204rrc05253753685236518254666426613424956rrc06252073651836453253537438945439008rrc07244411594615944250656164143164116rrc10248322636426520254066324914325611rrc11247872939929382252379328358328638rrc12248943572535713253605418259418647rrc13263203302532985258666282274282107rrc14244852745527428251685240669240908rrc15261842635625932257863267119265503rrc16255861368837257074112929422route-views2268836428564540267244633843635258route-views4245434977349750251194562837562987route-views.eqix244232818828137251313284179284192route-views.isc254593659536565255636311072311260route-views.linx250723624736280253124376990377233route-views.wide264103726637567257159456074457814rrc00May2024407373837222417784769647642 testupdatesequences.Asexpected,thenumberofLTCAMmovesiszero2.ThetotalnumberofmovesforthesimpleTCAMisbetween14-24timesthatforDUOSusingScheme1(PLO OPT),between9-15timesusingScheme2,7-227timesusingScheme3,and9-16timesusingScheme4(CAO OPT).Thusthereisareductionofmorethan90%inthetotalnumberofmovesforanyscheme.ThisisduetotheDUOarchitecture,asthereductionisobservedforPLO OPTandCAO OPTalso.NotethatthenumberofwaitWritesinanLTCAMequalsthenumberofinsertsanddeletesontheLTCAMandwaitWriteValidatesinanLTCAM,havenullwaitasnoinvalidslotisinvolvedinanongoinglookup.ThisisensuredbyusinginvalidateWaitWritetofreeaslot.Notethat 2Recallthat,inanLTCAM,aninsertmaybedoneinanyfreeslotandaslotfreedbyadeleteissimplylinkedtothefreespacelist. 121

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invalidateWaitWritewaitstillanongoinglookupiscompleteandtheninvalidatestheslot.Sinceupdatesaredoneseriallyinthecontrolplane,invalidateWaitWritesfromanLTCAMdeletemustcompletebeforethenextupdateoperationbegins. Table3-9. NumberofmovesforinsertsanddeletesintheITCAMofDUOS DatasetScheme1Scheme2Scheme3Scheme4 insertdeleteinsertdeleteinsertdeleteinsertdelete rrc001025291291021126064120118527826rrc0112538416400213841010201641086rrc03115788144517604276916140147030230rrc04570047686701968600159821880rrc0511942915377483540180193037533rrc0612481015619102982600306537407rrc07423365828301591900106317123rrc108540111194332589230173727999rrc1110473713162892612490103327615rrc12126858159951605316086270184035267rrc1311963515158573162790276234074rrc148159910703852479550213326717rrc1588563110812112231271020123225863rrc164502337407940084865route-views221307527684656242260259464460route-views413568918242804578800133048228route-views.eqix876531136904253494074026410route-views.isc1184091522215327034082134062route-views.linx13595617054033371850153735311route-views.wide13637517223503256300254837307rrc00May2013182166741634581901423479 3.5.3EvaluationofDUOWInevaluatingDUOW,weusedawideSRAMinconjunctionwiththeLTCAMonlyastheITCAMhasrelativelyfew(about10%)prexes.WeinstantiatedanLTCAMwith100,000slotsandusedthesamecongurationfortheITCAMasusedinourevaluationofDUOS.FortheDUOWevaluation,weusedonlyScheme3formemorymanagementintheITCAM.Table 3-12 givesthenumberofLTCAMprexescarvedbyLu'scarvingheuristic[ 21 ]andourcarvingheuristicofSection 3.3 .ThecarvingbybothmethodsisdoneonlyonthetrieofleafprexesasonlyleafprexesarestoredintheLTCAManditsassociatedwideSRAM.Surprisingly,thenumberofprexesthatresultwhen 122

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Table3-10. NumberofwaitWritesintheITCAMofDUOS DatasetScheme1Scheme2Scheme3Scheme4 rrc00286568810125494983948rrc0136897111799679586122687rrc03321230892206153992625rrc04174955607704108464562rrc0534657310877973378112833rrc0635397210279772971113443rrc07132509478093189050076rrc10250228787795288782620rrc11295146849145879087429rrc1235824710365172065108545rrc133372309764466019102846rrc14243520796835488883733rrc15251663755275239079383rrc1610081299922053154route-views2618746191252128831195879route-views441764014531199523149081route-views.eqix257668816785632983475route-views.isc34379010586873164108043route-views.linx37902310624872532109375route-views.wide38344310739674833114688rrc00May203731610934747911081 ourmethodisusedisfewerthanwhenthemethodof[ 21 ]isused.Thisissurprisingbecauseourmethodcarvesoutindependentprexeswhilethemethodof[ 21 ]maycarveanysetofprexes.Theapproximately1%dropinthenumberofprexeswhenourcarvingmethodisusedresultsfromtheobservationthatwhenourmethodisusedwedonotneedtosupplementthecarvingprexeswithcoveringprexeswhilecoveringprexesneedtobeaddedtothesetofcarvingprexesgeneratedbythemethodof[ 21 ].Sincecoveringprexesaccountforapproximately8%oftheprexesgeneratedbythemethodof[ 21 ],a1%dropinthetotalnumberofprexeswhenourmethodisusedimpliesaroughly7%increaseincarvingprexesbeforeaccountingforcoveringprexes.Table 3-13 givesthenumberofinsertsanddeletesappliedontheLTCAMofDUOWaswellasthenumberwaitWrites.WeobservethatthenumberofwaitWrites 123

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Table3-11. NumberofLTCAMmovesandwaitWritesforDUOS Dataset#moves#waitWrites rrc000776681rrc0101003809rrc030593723rrc040384503rrc050851569rrc060877953rrc070328259rrc100650525rrc110656996rrc120836906rrc130564381rrc140481577rrc150532622rrc16020714route-views201269101route-views401125824route-views.eqix0568371route-views.isc0622332route-views.linx0754223route-views.wide0913888rrc00May20095338 fortheLTCAMofDUOWismorethanthenumberofinsertsanddeletesdoneintheLTCAM.ThisisincontrasttoDUOSwherethenumberofwaitWritesisthesameasthenumberofinsertsanddeletes.ThisisbecauseadditionalwritesareneededinDUOWtomaintainlookupconsistencywhenthecontentsofanSRAMwordaresplitormergedorwhenasufxisaddedtoordeletedfromanexistingSRAMword.WenotethatthenumberofITCAMinsertsanddeletesaswellasthenumberofITCAMwaitWritesareunaffectedbythecouplingofawideSRAMtotheLTCAM.So,thenumbersshowninTable 3-9 arevalidfortheDUOWITCAMaswellasfortheDUOSITCAM. 3.5.4EvaluationofIDUOWAswasthecaseforourDUOWevaluation,forIDUOWtoo,weusedawideSRAMonlyinconjunctionwiththeLTCAM.Further,anindexTCAM(ILTCAM)with 124

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Table3-12. NumberofprexestobestoredintheLTCAMandassociatedwideSRAM DatasetLu[ 21 ]Our rrc006887668196rrc016506864672rrc036656766060rrc046789567327rrc056572665319rrc066541165014rrc076473764322rrc106556665199rrc116518764766rrc126556465133rrc136683266366rrc146495564575rrc156654465982rrc166635365859rviews26893968300rviews46483964435rviews.eqix6488164466rviews.isc6607965664rviews.linx6537264957rviews.wide6631965910rrc00May206263862014 anassociatedwideSRAMwasaddedonlytotheLTCAM.OurinstantiatedDLTCAMandILTCAMhad200,000and20,000slots,respectively.TheDLTCAMbucketsizewassetto512slotsforbothschemesdiscussedinSection 3.4 .Tables 3-14 and 3-15 givethenumberofinsertsanddeletesaswellasthenumberofwaitWritesfortheILTCAMandDLTCAMusing1-12WcwhileTables 3-16 and 3-17 givethesenumbersfortheM-12Wbindexingscheme.Ascanbeseen,the1-12Wcschemerequiredbetween203to227buckets,therebyusingupbetween103936and116224DLTCAMslots.Thenumberofmovesresultingfrombucketsplitsvariedfrom0to1085.TheM-12Wbschemeismorespaceefcientrequiringbetween128and153buckets,therebyusingupbetween65536and78336DLTCAMslots.However,thenumberofmovesisbetween800and16603whenM-12Wbisused.(Weshallseelaterthattheworst-casenumberofmovesforthesetwoschemesiscomparable).JustasinDUOW,thenumberofwaitWritesismore 125

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Table3-13. NumberofwaitWritesintheLTCAMofDUOW Dataset#inserts#deletes#waitWrites rrc00391398391867840029rrc015070765073791071516rrc03302359302568641880rrc04194212194117412859rrc05429065427408884675rrc064421454422081121870rrc07164213164186328698rrc10329469330166693637rrc11336674336954750563rrc12423898424286892330rrc13282676282509594906rrc14251034251273577811rrc15268558266942667692rrc1611297942723902route-views26352106366251290565route-views45726785728281252536route-views.eqix289812289825648771route-views.isc315905316093694299route-views.linx379967380210789002route-views.wide4664744682141070171rrc00May204803647982104402 thanthenumberofinsertsanddeletesandforDLTCAMthereisanadditionalsourceforwritesprexmovesresultingfrombucketoverows. 3.5.5ComparisonwithMIPSandCAO OPTMIPS[ 53 ]andanupdateconsistentversionofCAO OPT[ 41 ]obtainedusingthemethodof[ 54 ]arethecompetitorsofDUO.Inthissection,wecomparetheconsistentupdateTCAMschemesMIPS,CAO OPT,andDUO.InMIPS,adataplanelookupisdelayedifthelookupmatchesaTCAMslotwhosenexthopinformationisbeingupdated.Toavoidthisdelaywhilechangingthenexthopofaprex,werstinsertanewentrywithlatestnexthop,andthendeletetheexistingentry,inourexperimentsforMIPS.Thisensuresthatdataplanelookupsareconsistentandcorrectandarenotdelayedbycontrolplaneoperations.Alsoasnotedearlier,theMIPSschemeasdescribedin[ 53 ]usesnomemorymanagementschemeandfreeslotsaredeterminedusingTCAM 126

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Table3-14. NumberofwaitWritesfortheILTCAMofIDUOWusing1-12Wc Dataset#inserts#deletes#waitWrites rrc0010534rrc018428rrc034214rrc0410537rrc05000rrc0615748rrc07000rrc10217rrc116321rrc124215rrc13000rrc144215rrc156320rrc1610534route-views2216route-views4218route-views.eqix4215route-views.isc4215route-views.linx6320route-views.wide217rrc00May204215 lookupsthatdelaydataplanelookups.Toavoidthesedataplanelookupdelays,forourexperiments,weaugmentedtheMIPSschemeof[ 53 ]withthememorymanagementschemeemployedbyusfortheLTCAM(Section 3.3 ).FortheITCAMofDUO,memorymanagementisdoneusingScheme3.Sincetheperformanceofthe3TCAMschemesischaracterizedbythetotalnumberofthewaitWriteoperationsrequiredbyanupdatesequenceaswellasthemaximumnumberofoperationsforanindividualupdaterequest,ourexperimentsmeasuredthesequantities.Table 3-18 givesthetotalnumberofwaitWritesrequiredtoperformourtestupdatesequences.WeseethatourDUOarchitecturerequiresfewerwriteoperationsthanMIPSandCAO OPT.TheaveragenumberofwaitWritesperoperation(InsertorDelete)rangedfromalowof1.565toahighof6.72forMIPS,from1.505to6.51forCAO OPT,from1.000039to1.0641forDUOS,from1.00126to1.33705forDUOW,from1.00128 127

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Table3-15. StatisticsfortheDLTCAMofIDUOWusing1-12Wc Dataset#inserts#deletes#numBuckets#waitWrites rrc00391398391867221849709rrc015070765073792151081031rrc03302359302568215649739rrc04194212194117227417069rrc05429065427408214887978rrc064421454422082191151447rrc07164213164186209328706rrc10329469330166218696321rrc11336674336954215760370rrc12423898424286213902959rrc13282676282509215600789rrc14251034251273213585663rrc15268558266942218683039rrc1611297942721926241route-views26352106366252231295688route-views45726785728282111268931route-views.eqix289812289825213656627route-views.isc315905316093213705386route-views.linx379967380210215796007route-views.wide4664744682142181089092rrc00May204803647982203105453 to1.3702forIDUOWwith1-12Wcandfrom1.00583to2.3966forIDUOWwithM-12Wb.SincethevariousDUOschemesrequireasimilarnumberofwrites,M-12WbistobepreferredbecauseofitslowerTCAMmemoryandpowerrequirement.Figure 3-56 (a)showsthenormalizedaveragewaitWritesforthedifferentarchitectures.Forthisgure,werstcomputedtheaveragenumberofwaitWritesperInsert/Deleteforeachdataset.Then,theaverageoftheaverageswascomputedforeacharchitectureandnormalizedbytheaverageoftheaveragesforDUOS.Table 3-19 givesthemaximumnumberofwriteoperationsrequiredbyaninsertordeleteinourtestupdatesequences.Ascanbeseen,MIPSusesalargernumberofwritesintheworstcasethananyoftheremainingschemes.Wenoticethattheworst-casenumberofwritesforrrc00May20isparticularlylargeforMIPS.Thisisbecausetheupdatesequenceforrrc00May20containsannouncementsandwithdrawals 128

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Table3-16. StatisticsfortheILTCAMofIDUOWusingM-12Wb Dataset#inserts#deletes#waitWrites rrc0017085533rrc0117487550rrc0313467424rrc0417688564rrc05210105656rrc06284142893rrc07201063rrc1018291574rrc11214108673rrc1215075472rrc13224117693rrc1415477485rrc15298152936rrc16224112702route-views215879498route-views4276138868route-views.eqix270135848route-views.isc15678493route-views.linx260130816route-views.wide265134835rrc00May2010452323 Figure3-56. ComparisonofTCAMperformanceandpowerconsumptionbetweenMIPS,CAO OPT,DUO 129

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Table3-17. StatisticsfortheDLTCAMofIDUOWusingM-12Wb Dataset#inserts#deletes#numBuckets#waitWrites rrc00391398391867149867908rrc015070765073791421099815rrc03302359302568144664596rrc04194212194117148436057rrc05429065427408146912990rrc064421454422081491180372rrc07164213164186128330282rrc10329469330166142716458rrc11336674336954145784772rrc12423898424286142920560rrc13282676282509149624757rrc14251034251273140602928rrc15268558266942153714549rrc1611297942714749978route-views26352106366251491313783route-views45726785728281481299622route-views.eqix289812289825147685458route-views.isc315905316093142723400route-views.linx379967380210149823707route-views.wide4664744682141531120072rrc00May204803647982131117622 ofroutesforprexesofsmalllengths,suchas2and4.Eachofthesetranslatesintoaverylargenumberofinserts/deletesofindependentprexes.OurDUOSandDUOWarchitectureshavebetterworst-caseperformance(onaperupdatebasis)thanMIPS.DUOSisgenerallybetterthanCAO OPTandDUOW,whileinferiortoCAO OPT,isoftencompetitive.Eventhough,theworst-casenumberofwriteswithIDUOWismorethanthatforCAO OPT,thenumberofwritesisboundedbythesizeofabucket.Thus,theworst-casewritesmaybereducedbyusingasmallerbucketsizethanthe512sizeusedinourexperiments.Forexample,whenthebucketsizeas32,themaximumnumberofwriteoperationsinDLTCAMofIDUOWisalso32.Thisisbecausewhenanindexnodeissplit,werelocatethesplitnodethathasthesmallernumberofDLTCAMprexes.Thusatmost16prexesaremoved,andhencethereare32writeoperationsatmost. 130

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Table3-18. TotalnumberofTCAMwaitWriteoperations DatasetMIPS[ 53 ]CAO OPT[ 41 ]DUOSDUOWIDUOW(1-12Wc)IDUOW(M-12Wb) rrc0014420781249984831630894978904692923390rrc01179844516552411083395115110211606451179951rrc031159357997100655262703419711292726559rrc04887877701722425587453943458190477705rrc0514366101428017924947958053961356987024rrc0620743841344593950924119484112244661254236rrc07783637602014360149360588360596362235rrc1011689641082896703412746524749215769919rrc1113527581057557715786809353819181844235rrc1216023751380918908971964395975039993097rrc131191824989752630400660925666808691469rrc14993155794964536465632699640566658301rrc151208090864242585012720082735449767875rrc16458953372222919261072848052885route-views2224212321785061397932141939614245251443112route-views4230406518182221225347135205913684621400013route-views.eqix1278271925087624700705100712971742635route-views.isc11725421013145695496767463778565797057route-views.linx13062981257542826755861534868559897055route-views.wide19881521435007988721114500411639321195740rrc00May20683608663306102817111881112947125424 Theoretically,itispossibleforeachupdateinMIPStorequireanumberofTCAMwritesequaltothenumberofprexesinthetable.Thishappensforexamplewhenthereisatrieinwhichnoleafprexhasasiblingaftertheleafpushingandprexcompressionsteps,andtothattrieifadefaultprexoflength0isinsertedordeleted(seeFigure 3-1 ).Ontheotherhand,CAO OPTrequiresatmostW=2movesperupdate(W=32forIPv4).Hence,CAO OPTrequiresW=2writesperupdateintheworstcase.ForDUOS,theworstcasewritesoccurwhenaprexistobeinsertedtoLTCAMandthisrequiresaprexdeletionfromLTCAMandaprexinsertionatITCAM.ThetwoLTCAMoperationsrequire2writes,whereastheITCAMoperationrequiresWwritesintheworstcaseusingScheme3.ThusDUOSrequires(W+2)writesintheworstcase.ForDUOW,theworstcasescenarioissameasthatforDUOS,exceptthataLTCAMinsertcanrequire3writeswhenaSRAMwordissplit(1deletetoremovethesplitword 131

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and2insertsforthenewwords).Similarly,aLTCAMdeletecanalsorequire3writeswhenaSRAMwordismerged(2deletesforthetwowordsmergedand1insertforthenewword).Thus,DUOWrequires(W+6)writesintheworstcase.ForIDUOW,theworstcasecombinationinvolvestheITCAM,ILTCAMandDLTCAM.IDUOWrequiresatmostWwritesforITCAMand6writesforILTCAMandbucketSizewritesforDLTCAM,withamaximumof(W+bucketSize+6)writesforasingleupdate. Table3-19. MaximumnumberofTCAMwritesforasinglerawinsert/delete DatasetMIPS[ 53 ]CAO OPT[ 41 ]DUOSDUOWIDUOW(1-12Wc)IDUOW(M-12Wb) rrc00266569512512rrc01296537505505rrc0311865910505505rrc042682637505511rrc053835377500rrc061278537505505rrc0763895366368rrc10304647222503rrc11546547507507rrc12709961011505505rrc1310715377499rrc14306657505505rrc155938447510508rrc16198537507507route-views2568557399497route-views4377537505505route-views.eqix260747505505route-views.isc386537505505route-views.linx306637510508route-views.wide278437332503rrc00May20102249657378475 Table 3-20 givesthepowerconsumptioncharacteristicsofMIPS,CAO OPTandDUOintermsofthenumberofentriesenabledduringasearchoperation.TheTCAMentriesarecountedbasedontheinitiallayoutofprexesfortheinputroutingtable.MIPS,CAO OPT,DUOSandDUOWenableallvalidTCAMentriesduringasearchoperation.IDUOW,ontheotherhand,enablesallvalidTCAMentriesforITCAMandILTCAM,andonlyabucketofentriesforDLTCAM.Column2givesthenumberof 132

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enabledentriesforMIPS,whilecolumn3givesthenumberofenabledentriesforCAO OPTonthesimpleTCAMandalsoforDUOSwhichisobtainedbysummingupthenumberofITCAMandLTCAMentries.BothCAO OPTandDUOShavethesamenumberofentriesinTCAMsincetheystoreeachprexinasingleTCAMentry.Column4givesthenumberofenabledentriesforDUOW,whichisobtainedasthesumofvalidITCAMandLTCAMentries.Columns5and6givethenumberofenabledentriesforIDUOWwith1-12WcandM-12Wb,respectively.ThisnumberisobtainedasthesumofvalidentriesinITCAM,ILTCAMandthenumberofentriesinabucketinDLTCAM(xedto512forourexperiments).WeobservethatforMIPS,theleafpushingandprexcompressionstepshavereducedthenumberofTCAMentries,andhencethepowercomparedtoCAO OPTandDUOS.MIPSrequiresabout1.5to2timesthepowerrequiredbyDUOWforallthetests,exceptrrc06andrrc15.Inthecaseofrrc06,MIPSrequiresabout7%morepowerthanDUOWwhileitrequiresabout7%lesspoweronrrc15.MIPSconsumesbetween3to10timesthepowerconsumedbyIDUOW.Figure 3-56 (b)showsthenormalizedaveragepowerforthedifferentschemes.Forthisgure,werstcomputedtheaveragenumberofenabledentriesforeveryTCAMsearchforeacharchitecture.Then,theaveragewasnormalizedbytheaveragenumberofenabledentriesforIDUOWwith1-12Wc.NotethatthepowerrequirementforDUOWcanbereducedfurtherbyusingawiderSRAMthanthe144bitwideSRAMusedforourexperiments.ThepowerrequirementsforIDUOWmaybereducedbyincreasingSRAMwidthandbyaddinganindexTCAMandawideSRAMtotheITCAM.Forexample,thepowerconsumedbyDLTCAMandILTCAMofIDUOWwaslessthan560forthe1-12Wcschemeandlessthan630fortheM-12Wbscheme.WhenanindexTCAMandwideSRAMisaddedtotheITCAMtoourexperimentalIDUOW,thepowerrequirementfortheITCAMisexpectedtoapproximatethatfortheLTCAM(assumingthesamebucketsizeisused).So,theIDUOWpowerrequirementwoulddroptoabout1120for1-12Wcandabout1260forM-12Wb.So,withtheadditionofanindexTCAMandawideSRAM 133

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totheITCAMofIDUOW,thepowerrequiredbyMIPSisbetween68to248timesthatrequiredbyIDUOW. Table3-20. AcomparisonofpowerconsumedbyMIPS,CAO OPTandDUOinperformingTCAMsearch Dataset MIPS CAO OPTorDUOS DUOW IDUOW(1-12Wc) IDUOW(M-12Wb) rrc00 245875 294098 95577 27938 27989 rrc01 200733 276795 89459 25343 25387 rrc03 272046 283754 92176 26672 26714 rrc04 203375 288610 92464 25701 25759 rrc05 261067 280041 90694 25933 25987 rrc06 96479 278744 90221 25762 25839 rrc07 188373 275097 88763 24997 25055 rrc10 178987 278898 90031 25390 25434 rrc11 188527 277166 89553 25343 25399 rrc12 203440 278499 90027 25450 25493 rrc13 234053 284986 92686 26877 26935 rrc14 172096 276170 89060 25041 25084 rrc15 85463 284047 92166 26741 26813 rrc16 212282 282660 91445 26143 26198 rviews2 277560 294127 95183 27439 27502 rviews4 140962 275737 88978 25099 25145 rviews.eqix 175659 275736 88889 24980 25054 rviews.isc 193800 281095 91123 26018 26091 rviews.linx 202254 278196 90029 25631 25688 rviews.wide 150427 283569 92320 26966 27037 rrc00May20 220067 266185 86421 24961 25001 Inthischapter,wehaveproposedadualTCAMarchitecture-DUO-forroutingtables.FourmemorymanagementschemesalsohavebeenevaluatedextensivelyfortheITCAMofDUO.Ofthesememorymanagementschemes,Scheme2andScheme3aretheonesproposedbyus.OurexperimentsshowedthatScheme3isfarbetterthananyoftheotherschemesintermsofthenumberofmovesperupdateoperation.DUOprovidesincrementalupdatefacilitytothelowpowerlookupschemesin[ 21 ],withoutlockingtheTCAMatanytimeforperformingupdates.Supportingincrementalupdatestotheschemesin[ 21 ]wasproblematicsinceeachprexintheTCAMstoredacorrespondingcoveringprexinthewideSRAM,andsuchcovering 134

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prexescouldbesharedbyanumberofTCAMentries.Thecoveringprexesareasubsetoftheintermediateprexes,andbyputtingallintermediateprexesinaseparateTCAM(ITCAM)andenablingaparallelmatchonITCAMandLTCAM,asinDUO,wecompletelybypasstheproblemwithcoveringprexesintheperformanceofincrementalupdates.DUOisfastandpowerefcientwhenitcomestoincorporatingtheupdates.ThespeedandpowerefciencyofDUOareduetobothitsarchitectureanditsmemorymanagementschemes.Fromourdatasetswefoundthatover90%oftheupdatesaredirectedtotheLTCAMofDUO,whichstoreddisjointprexes.Thus,noprexmoveininvolvedformostoftheupdates.Thelessthan10%ofupdatesthataredirectedtotheITCAMinvolveverysmallnumberofmoveswhenthememorymanagementScheme3isused.MemorymanagementScheme3,proposedbyus,requiresbetween1/74000and1/93timesthenumberofmovesrequiredbyCAO OPT.ThelowaveragevaluesforthenumberofmovesusingScheme3arebackedbyverylowstandarddeviationforallthetestsinourdataset.OurDUOarchitectures,likethosebasedontheCoPTUA[ 54 ],provideforconsistentdata-planelookupsandincrementalcontrol-planeupdatesthatdonotdelaydata-planelookups.WhiletheMIPSarchitectureof[ 53 ]providesconsistentdata-planelookups,theselookupsmayencounterdelaysbyongoingcontrol-planeoperationsthat,forexample,changethenexthopassociatedwithaprex.Thesedelaysmaybeeliminatedbyimplementinganexthopchangeasaninsertfollowedbyadeleteassuggestedin[ 53 ].Delayscausedbycontrol-planeoperationsthatrequireafreeslottobefoundmaybeeliminatedusingoneofourproposedmemorymanagementschemes,preferablyScheme3.MakingthesetwomodicationstoMIPSresultsinadelay-freeMIPS.Experimentswithdelay-freeMIPSandaconsistentlookupversionofCAO OPTindicatethatthesetwoarchitecturesmake,onaverage,between1.5and5timesas 135

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manyTCAMwritesasmadebyanyourDUOarchitecturestoperformcontrol-planeupdates.Intermsoftheworst-casenumberofwritesneededforaninsertordelete,MIPSrequiresasmanywritesasprexesinthetablewhileCAO OPTrequires16forIPv4,DUOSrequires34,DUOWrequires38,andIDUOWrequires38+bucketSize.Onourtestdata,MIPSrequiredupto102,249writesforasingleinsert/deletewhileCAO OPTrequiredatmost7writes,DUOSrequiredatmost10writes,DUOWrequiredatmost11writes,andIDUOWrequiredatmost512writes.ThemaximumnumberofwritesforIDUOWmaybereducedbyreducingthebucketsize.Theverylargenumberofworst-casewritesforMIPSisaseriousproblemasthismakestherouterverysusceptibletomalicioususerswhoinjectastreamofworst-caseinserts/deletesintotheupdatestream.Whilethisalsoisanissue,thoughtoalesserextent,forIDUOW,IDUOWofferspoweradvantagesovertheremainingDUOschemes.Onourtestdata,MIPSreducedpowerconsumptionforaTCAMsearchby4%to69%relativetoCAO OPTandDUOS,whichtakethesameamountofpower.However,MIPSgenerallyrequiredbetween1.5and2timesthepowerrequiredbyDUOWandbetween3and10timesthatrequiredbyourexperimentalversionofIDUOW.However,byaddinganindexTCAMandawideSRAMtotheITCAMofIDUOW,thepowerrequiredbyMIPSisbetween68and248timesthatrequiredbytheenhancedIDUOW.FurtherreductioninpowerrequiredbyDUOWandIDUOWresultfromusingawiderSRAMthanthe144-bitwideSRAMusedinourexperiments.BetweenDUOWandIDUOW,IDUOWisrecommendedforleastpowerconsumptionduringlookupswhereasDUOWisrecommendedforalowerworst-casedelayinincorporatingtheupdatestotheforwardingtablewhilestillprovidingsignicantpowerbenetsduringaTCAMlookup.Inthenextchapter,wewillfurtheranalyzeconsistencyissuesinaverydetailedway. 136

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CHAPTER4CONSIST:CONSISTENTUPDATESFORPACKETCLASSIFIERSRulesinpacketclassiersandforwardingtablesarealwaysinauxofchange,withnewrulesbeingaddedandexistingrulesbeingdeletedorchanged.Inthischapter,weformalizetheconsistencypropertiesofincrementallyupdatedclassierswhenupdatesarriveinclustersandpresentaheuristictoobtainanearoptimalbatchconsistentsequenceasatopologicalorderingoftheprecedencegraph.Here,optimalityisdenedwithrespecttotheincreaseinsizeoftheintermediateruletable,whereanoptimalsequenceguaranteesminimumincreaseinthemaximumtablesize.WebeginwithSection 4.1 byreviewingbackgroundandrelatedwork.InSection 4.2 wepresenttheconsistencyrequirementsandanalysis.AnexperimentalevaluationwithupdatetracesforforwardingtablesatvariousroutersandsyntheticupdatetracesforpacketclassiersispresentedinSection 4.3 andweconcludethechapterwithSection??. 4.1BackgroundandRelatedWorkItisoftenfoundthatarouterorapacketclassierisfacedwithanumberofupdaterequeststhatarriveatthesametime.Forexample,ifweconsiderupdatemessagesreceivedbyarouterunderBorderGatewayProtocol(BGP)fromaBGPupdatele[ 6 ],weseemultiplerouteannouncementandwithdrawalnoticesinthesamemessage,andmanysuchmessageshavingthesametimestampofreceipt.Theannouncementandwithdrawalmessagesresultininsertion,deletionorchangesinrulesintheforwardingtableoftherouter.Theupdatesreceivedinaclustercanbeprocessedeitherincrementally,orinabatch.Mostroutersperformupdatesoneatatime(i.e.,incrementally)inthecontrolplaneconcurrentwithlookupoperationsinthedataplane.Byincrementallyperformingtheupdatesinaclusterinacarefullyselectedorder,itispossibleforanincrementallyupdatedroutertobehaveexactlylikeonethatisbatchupdated.Notethatinabatch 137

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updatedrouter,packetsareroutedtoanexthopdeterminedeitherbytheruletablebeforeanyupdateisdoneorbytheruletablefollowingtheincorporationofallupdates. Abeforeapplyingupdateshop(0010*)=H2 Bafterapplyingupdateshop(0010*)=H1Figure4-1. Prexesinforwardingtablebeforeandafterapplyingupdates Informally,aruletableisconsistentwheneverylookupreturnstheactionthatwouldbereturnedifthelookupweredonejustbeforeaclusterofupdatesisappliedorjustaftertheupdateclusteriscompleted.Forexample,supposeaforwardingtablecontainsrules:(00,H2),(,H0).Figure 4-1 (a)illustratestheserulesona4-bitaddressspace.Nowsupposethatthefollowingupdatesarereceivedinacluster:delete(00),insert(0,H1).Figure 4-1 (b)givestheprexesintheforwardingtableaftertheupdatesareapplied.Thenexthopforadatapacketwithdestinationaddress0010isshowninFigure 4-1 withaboldline.Ifnoupdatehasbeenprocessedyet,thenfromFigure 4-1 (a)nexthopH2isreturned,usingshortestrangematching(whichisequivalenttoLMP,asprex00matches).Ifontheotherhand,theclusterofupdatesiscompletelyprocessed,thenfromFigure 4-1 (b)thereturnednexthopisH1.Thus,asweapplytheupdateswemustensurethatthepacketsareforwardedtoahopfromthesetfH1,H2g.Forexample,ifweapplytheupdatesinthefollowingsequence:insert(0,H1),delete(00),thenconsistencyismaintainedateverystepasweseefromFigure 4-2 (a),sincethehopispickedfromsetfH1,H2gOntheotherhand,ifwe 138

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AbatchconsistentupdateswithhopsinsetH=fH1,H2g BbatchconsistencyviolatedashopsbelongtofH0,H1,H2gFigure4-2. Prexesasupdatesarebeingappliedintwodifferentsequences applytheupdatesastheycome,thenconsistencyisnotmaintained(seeFigure 4-2 (b))becausethereturnedhopisH0=2fH1,H2gfollowingtheoperationdelete(00).Thisexampledealswithbatchconsistency,whichwewilldenelater.Asupdatesarereceivedinclusters,itispossibletoarrangetheupdatesinsuchawaythatthesizeoftheintermediateruletableistheminimum.Ingeneral,weusefunctionsinsert,deleteandchangetorepresenttheinsertion,deletionandchange,respectively,ofarule.Forexample,considertheclusterofupdates:insert(rule10),insert(rule11),delete(rule3),delete(rule4),delete(rule5).Iftheupdatesaredoneinthisorder,thenthenumberofrulesinthetablerstincreasesbytwoduetotheinsertsandnallydecreasesasthedeletesareperformed.Ontheotherhand,ifthedeletesaredonerst,thenthereisnotemporaryincreaseinthenumberofentriesinthetable.Ifthetablesizeistightlyconstrainedthenpickingthedeletesrstcouldbehelpfulinavoidingoverowsituations.WiththeInternetbeingunderaconstantuxofchange,therehasbeenasignicantamountofworkintherecentpastdealingwithhowtoincorporatethechangestothe 139

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forwardingtableandpacketclassier.Thetwobroadcategoriesofworkinthisareaincludeoneinwhichtheupdatesareappliedincrementally[ 4 41 42 45 54 ]andtheotherinwhichtheupdatesareappliedinbatches[ 12 27 52 ].Toapplytheupdatesinbatches,typicallyaduplicatecopyoftheforwardingtableismaintainedsothatwhenonecopyisinvolvedinlookuptheothercanbeupdatedandaftertheupdateiscomplete,thelookupsaredoneintheupdatedcopy.Althoughbatchupdatesrequiredoublethememoryfootprint,theyareusefulforsituationswhenincrementalupdatesarecompute-intensive.Batchupdateshavebeenusedinhigh-performancerouterdesign[ 34 ].Incrementalupdates,ontheotherhand,areappliedtothesamecopyoftheforwardingtablethatisusedforlookups.Updateandlookupoperationscouldusetimemultiplexingtosharethecommonmemorythatstorestheprexdatabase[ 4 41 42 ].Thusthedatabaseislockedwhentheupdateoperationsarecarriedout,topreventalookupoperationfromtakingplaceatthesametime.Z.Wanget.alinCoPTUA[ 54 ]developedanapproachtoperformclassierupdateswithoutlockingthepolicylter(PF)table(storedinaTCAM)fromsearchkeymatchingwhileensuringthatthesearchesreturnconsistentandnon-erroneousresults.Theydeneaconsistentruletabletobearuletableinwhichtherulematched(includingtheactionassociatedwiththerule)duringasearchkeymatchingiseithertherule(includingaction)thatwouldbematchedjustbeforeorjustafteranyongoingupdateoperation.Wangetal.[ 54 ]developedaschemeforconsistenttableupdatewithoutlockingtheTCAMatanytime,essentiallyallowingasearchtoproceedwhilethetableisbeingupdated.Theconceptofconsistentruletableiseasilyextendedtoaforwardingtablesuchthatthetableisnotlockedwhileupdatesareprocessedandlookupsreturnnexthopsthatwouldbereturnedjustbeforeorjustafteranongoingupdateoperation.OtherTCAMdesignsthatsupportconsistentincrementalupdatesonaperoperationbasiswithoutlockingforlookupsare[ 26 53 ]. 140

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Theauthorsin[ 53 ]maintainaleaf-pushedprextrie.Asaresult,anyinsert,deleteorchangeoperationtoanon-leaftrienodecouldcausemultipleleafprexestobechanged,deletedorinserted.Infact,intheworstcase,whenthereisanoperationonthedefaultprex(tobeappliedtotherootnodeofthetrie)therecouldbeO(n)extraoperations[ 26 ].Theauthorsin[ 54 ]showhowmultiplepolicylterrulesgetaffectedbytheintroductionordeletionofalterruleandhowintheworstcaseNr=2rulemovesmayberequiredforupdatingaltertableconsistingofNrrules.Both[ 54 ]and[ 53 ]suggesthandlingaclusterofupdatesbydoingthedeletesrstandthentheinserts.Thisstrategy,however,doesnotensuretableconsistency.Comparedtotheexistingworks[ 54 ],[ 26 53 ],ourworkisdifferentinthatwefocusontheorderingoftheupdateoperationsthatcanbereadilyappliedtotheruletableatagiventime.Theorderingofupdatesmatterwhentheruletableisupdatedincrementally.Forexample,iftheupdatesareappliedinanyorder,itcouldresultinmatchingruleswithlowerpriorityduringlookupevenashigherpriorityrulesarewaitinginthequeuetobeincorporated.Basuetal.in[ 5 ]presentanalgorithmtoreducethenumberofwritestotheprextriebysuppressingtheredundantwrites.Aredundantwriteisonethatissucceededbyanotherwriteandafterthesucceedingwriteisapplied,thestateoftheprexdatabaseisthesameirrespectiveofwhethertheredundantwritewasapplied.Inthischapter,weofferadetailedalgorithmforcomputingareductionofagivenupdatesequencebasedontheinsert,deleteandchangefunctions. 141

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4.2ConsistentUpdatesFigure 4-4 showstheoverallowofourmethodologyforobtainingaconsistentsequenceofupdatesfromagivenclusterofupdatesthatleadstonear-optimalgrowthoftheintermediatetablesize.Therstphaseisthereductionphasewherereduction,inthecontextofupdateoperations,ispresentedinDenition 7 .Inthesecondphaseaprecedencegraphisbuiltwiththeupdateoperationsasthevertices.Section 4.2.2.1 discussesaboutthegenerationofthegraph.Thethirdphasedealswithgenerationofaconsistentupdatesequenceasatopologicalorderingoftheprecedencegraphthatleadstonear-optimalincreaseinintermediatesizeoftheruletable.Section 4.2.2.2 presentsaheuristicforthethirdphase. 4.2.1DenitionsandPropertiesWerstdenethefollowingterms:reductionofanupdatesequence,abatchconsistentsequenceandanincrementalconsistentsequence.Laterwestateandprovesomeoftheinterestingpropertiesofreduced,batchandincrementalconsistentsequences. Denition7. LetU=u1,,urbeanupdatesequence;eachuiisaninsert,delete,orchangeoperation.TheupdatesequenceV(U)(orsimplyV)derivedfromtheupdatesequenceUinthefollowingmanneriscalledthereductionofU. Examinetheupdateoperationsintheorderu1,u5,.LetFbetheeldtupleassociatedwiththeoperationuibeingexamined.IfFoccursnextinuj,j>i,dothefollowing: 1. Ifui=change(F,newA)anduj=change(F,newA'),removeuifromU.IfnewA'isthesameastheexistingactionforFintheruletable,thenremoveujfromUaswell. 2. Ifui=change(F,newA)anduj=delete(F),removeuifromU 3. Ifui=delete(F)anduj=insert(F,A),removeuifromUandreplaceujbychange(F,A).(ujmayalsoberemovedfromUwhenactionAequalsthecurrentactionassociatedwithFintheclassier.) 142

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F:asymbolforalterrepresentingad-tuple(F[1],F[2],...,F[d]),whereF[i]isarangespeci-edforanattributeinthepacketheadersuchasdestinationaddress,sourceaddress,sourceportrange,etc.Whentherearemultiplelters,theyarerepresentedasF1,F2,...f:atupleconstructedusingdestinationaddress,sourceaddress,sourceportrange,etc.val-uesfrompacketheader.A:actioncorrespondingtoalterF.Similarly,A0,A1,A2,...newA,newA':newaction(P,H):forwardingtablerule,wherePisaprexandHisthenexthopforP.LMP:longestmatchingprexHPM:highestprioritymatchingruleU:anupdatesequenceui:anoperation,whichcouldbeaninsert,deleteorchangethatisapartofU.V:areducedupdatesequence.vi:anoperationthatispartofthereducedsequenceV.S:areducedandbatchconsistentupdatesequence.Inanotherinstanceitisusedtorepresentanarbitrarysequence.Sisalsousedtorepresenttheoverlappingportionoftwolters.si:anoperationthatispartofsequenceS.r:numberofoperationsinoriginalupdatesequence.m:numberofoperationsinreducedupdatesequence.insert(F,A):insertoperation,representedalsoasI,I1,I2etc.delete(F):deleteoperation,representedalsoasD,D1,D2,etc.change(F,newA):changeoperation,representedalsoasC,C1,C2,etc.T0,R:packetclassierTi(U):packetclassierobtainedafterapplyingioperationsfromupdatesequenceU,startingfromtherstoperation.action(f,R):actioncorrespondingtothehighestprioritymatchingruleforlterfinpacketclassierR.priority(F,A):priorityofrule(F,A)inthepacketclassier.jT0j:numberofrulesinaclassiertableinitially.jTi(S)j:numberofrulesinclassiertableafteriupdatesfromsequenceShasbeenapplied.max0imjTi(S)j:maximumincreaseinruletablesizeaseachupdatenumbered0throughminthebatchupdatesequenceSisappliedontheclassiertable.optB(T0,U):maximumincreaseinruletablesizeasalltheupdatesnumbered0throughminanoptimalbatchconsistentupdatesequenceS(correspondingtooriginalupdatesequenceU)areappliedsequentiallytotheclassiertable.optI(T0,U):maximumincreaseinruletablesizeasalltheupdatesnumbered0throughminanoptimalincrementalconsistentupdatesequencecorrespondingtoUareappliedsequentiallytotheclassiertable.#inserts(U),#deletes(U):Numberofinsertsanddeletes,intheupdatesequenceU.G:precedencegraphfortheupdatesequenceV.E(G):setofdirectededgesofG.Q:setofpairsof(a,b)valuescorrespondingtodifferentupdatesequences.(Q):permutationof(a,b)pairs.B(i):Sumofbvaluesinapermutation(Q)of(a,b)pairs.A(i):Sumofbvaluestillthe(i-1)pairandtheavaluefortheithpair.:Increaseintablesizeastwosequencesaremerged.Figure4-3. Notationusedinthischapter 143

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Figure4-4. Flowdiagramforcreatingaconsistentsequenceofupdates 4. Ifui=insert(F,A)anduj=change(F,newA),removeuifromUandreplaceujbyinsert(F,newA). 5. Ifui=insert(F,A)anduj=delete(F),removeuiandujfromU.Notethattheremainingfourpossibilitiesforuianduj((change,insert),(delete,change),(delete,delete),and(insert,insert))areinvalid.Forexample,thereductionofU=insert(F1,A1),insert(F2,A2),delete(F1,A1)isV=insert(F2,A2).ItiseasytoseethataeldtupleFmaybeassociatedwithatmostoneoperationinthereductionofU. Denition8. LetU=u1,,urbeanupdatesequence;eachuiisaninsert,delete,orchangeoperation.LetT0beapacketclassierandletTi(U)bethestateofthisclassieraftertheoperationsu1,,uihavebeenperformed,inthisorder,onT0.LetT0(U)=T0andletaction(f,R)betheactionassociatedwiththehighestprioritymatchingruleforeldtuplefinpacketclassierR.LetS=s1,,smbeanother 144

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updatesequence.SisbatchconsistentwithrespecttoT0andUiffTr(U)=Tm(S)^8i8f[action(f,Ti(S)]2faction(f,T0),action(f,Tr(U))gSisincrementalconsistentwithrespecttoT0andUiffTr(U)=Tm(S)^8i8f[action(f,Ti(S)]2faction(f,T0),,action(f,Tr(U))gNotethattwotablesareequalifftheycontainexactlythesamerules.Further,althoughUisalwaysincrementalconsistentwithrespecttoitself,itisgenerallynotbatchconsistentwithrespecttoitself(i.e.,S=U)andatableT0.Forexample,supposeU=insert(F1,A1),delete(F1,A1)andT0=f(,A0)g,where`*'standsforthedefaultrulecontaining*foralleldsandwhichthereforeanyeldtuplewouldmatch.Further,letA06=A1andpriority(F1,A1)>priority(,A0).Then,T2(U)=T0andaction(f,T0)=action(f,T2)=A0forallf.However,eventhoughTr(U)=Tm(S),action(f,T1(S))=A16=A0foreveryfthatmatchesclassierrule(F1,A1).NotethatthereducedupdatesequenceV(U)maybeneitherbatchnorincrementalconsistentwithrespecttoUandT0.Forexample,supposethatT0=f,H0gandU=insert(00,H1),insert(0,H2),insert(000,H3),delete(00).Figure 4-5 (a)showsT0,T1(U),,T4(U).Batchconsistencyrequiresthenexthopsfordestinationaddressesmatchedby000*tobeinsetHb=fH0,H3gwhileincrementalconsistencyrequiresthesenexthopstobeinsetHi=fH0,H1,H3gasillustratedinFigure 4-5 (a).Figure 4-5 (b)showsT1(V)andT2(V)forthereducedsequenceV(U)=insert(0,H2),insert(000,H3).WeseethatnextHop(d,T1(V))=H2andH2=2Hb,H2=2Hiforaddressesdmatchedby000.So,V(U)isneitherbatchnorincrementalconsistentwithrespecttoUandT0. 145

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Aactualupdatesequence(in-crementalconsistent) BreducedupdatesequenceFigure4-5. Actualandreducedupdatesequences Theorem 4.1 establishestheexistenceofabatchconsistentupdatesequenceforeveryclassierT0andeveryupdatesequenceU.NotethattheexistenceofanincrementalconsistentupdatesequencefollowsfromourearlierobservationthatUisincrementalconsistentwithrespecttoitselfandeveryT0.ThisfollowsalsofromTheorem 4.1 aseverybatchconsistentupdatesequenceisincrementalconsistentaswell.Anincrementalconsistentsequencemaynot,however,bebatchconsistent. Theorem4.1. ForeveryclassierT0andupdatesequenceU,thereexistsabatchconsistentupdatesequenceS. Proof. LetS=s1,,smbederivedfromU=u1,,urasbelow. Step1LetV=v1,,vmbethereductionofU. Step2ReordertheoperationsofVsothattheinsertsareatthefrontandindecreasingorderofpriority;followedbythechangeoperationsinanyorder; 146

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followedbythedeletesinincreasingorderofpriority.CalltheresultingsequenceS.WeshallshowthatSisbatchconsistentwithrespecttoUandeveryT0.First,itiseasytoseethatTr(U)=Tm(V)=Tm(S).So,weneedonlytoshow8i8f[action(f,Ti(S))]2faction(f,T0),action(f,Tm(S))gTheproofisbyinductiononi.Fortheinductionbase,i=0,T0(S)=T0,andso8f[action(f,T0(S))=action(f,T0)].Fortheinductionhypothesis,assumethat8f[action(f,Tj(S))2faction(f,T0),action(f,Tm(S))g]forsomej,0j
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highestprioritymatchingruleforfortheactionassociatedwiththismatchingrule.So,HPM(f,Tm(S))=HPM(f,Tj+1(S))=F'andaction(f,Tj+1(S))=action(f,Tm(S)). Figure4-6. Tj+1foraforwardingtable.Fisnewlyinserted/changedprex,fisthedestinationaddressonapacket. FromtheproofofTheorem 4.1 ,weseethatforanupdatesequencetobebatchconsistent,itisnecessaryonlythatwheneveranoperationchangestheactionforatuplef,thatchangebereectedtotheactioninthenaltableTr(U).Usingthisobservation,itispossibletoconstructadditionalbatchconsistentupdatesequences.Forexample,wecouldpartitiontheoperationsinthereductionofUsothattheeldtuplesinonepartitionaredisjointfromthosecoveredbyotherpartitions.Then,foreachpartition,wecanordertheoperationsasintheconstructionofTheorem 4.1 andconcatenatetheseorderingstoobtainabatchconsistentupdatesequence.Differentbatchconsistentupdatesequencesmayresultinintermediateroutertablesofdifferentsize.Asanexample,considerthereducedupdatesequenceofFigure 4-7 foraforwardingtable.TheoutermostprexandallprexesmarkedDareinT0.ThosemarkedIareprexesthataretobeinsertedandthosemarkedDaretobedeleted.ThebatchconsistentsequenceconstructedintheproofofTheorem 4.1 willdoalltheinsertsrstandthenthedeletes.Ifthereareainserts,thetablesizeincreasesbyafollowingthelastinsertandthendecreasesbacktothesizeofT0asthedeletescomplete.Fortheupdatesequencetosucceed(wheninserts/deletesaredoneincrementally,i.e.,oneatatime),wemusthaveaunitsofadditionaltablecapacity.AnalternativebatchconsistentupdatesequencefollowseachinsertwiththedeletionofitsenclosedprexthatislabeledDinthegure.Usingthissequence,onlyoneadditionalunitoftable 148

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capacityisrequiredandthisisoptimalforthegivenexampleasitisnotpossibletodoadeletebeforeitsenclosinginsertandmaintainbatchconsistency(unless,ofcourse,thetableislockedforlookupfromthestartofadeletetothecompletionofitsenclosinginsert). Figure4-7. AbadexampleforsequenceofTheorem 4.1 WenextprovethatareducedsequenceobtainedusingtheDenition 7 hasthesmallestnumberofoperationsanditisnotpossibletoreduceitfurther. Theorem4.2. ForeveryclassierT0andupdatesequenceU=u1,,ur,thereducedsequenceV(U)hasthesmallestnumberofoperationsneededtotransformT0toTr(U). Proof. ConsideranysequenceSthattransformsT0toTr(U).LetV(S)bethereductionofS.Clearly,jV(S)jjSjandV(S)alsotransformsT0toTr.WeshallshowthatjV(U)jjV(S)j,therebyprovingthetheorem.Consideranyvi2V(U).Ifvi=insert(F,A),thenF62T0(followsfromthecorrectnessofUwithrespecttoT0andthedenitionofV(U))andF2Tr(U).Consequently,insert(F,A)'2V(S).SinceFappearsonlyonceinV(S),A'=A.So,vi2V(S).Ifvi=delete(F),thenF2T0andF62Tr(U).So,delete(F)2V(S).Similarly,whenvi=change(F,newA),vi2V(S).So,V(U)V(S)andjV(U)jjV(S)j. Denition9. Abatch(incremental)consistentsequenceS=s1,,smforUandT0isoptimaliffitminimizesmax0imfjTi(S)jgrelativetoallbatch(incremental)consistentsequences. 149

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WenextpresentatheoremthatestablishesarelationshiponthemaximumgrowthoftablesizeasabatchconsistentupdatesequenceisappliedandasanincrementallyconsistentupdatesequenceisappliedonruletableT0. Theorem4.3. LetSbeanoptimalbatchconsistentsequenceforUandT0.LetoptB(T0,U)=max0imfjTi(S)jg.LetoptI(T0,U)bethecorrespondingquantityforanoptimalincrementalconsistentsequence.optB(T0,U))]TJ /F3 11.955 Tf 12.82 0 Td[(m=2optI(T0,U)optB(T0,U)andbothupperandlowerboundsonoptI(T0,U)aretight. Proof. optI(T0,U)optB(T0,U)followsfromtheobservationthateverybatchconsistentsequencealsoisincrementalconsistent.Toseethatthisisatightupperbound,considerthecasewhenUiscomprisedonlyofchange(oronlyofinsertoronlydelete)operations.Now,optI(T0,U)=optB(T0,U). Figure4-8. AnexampleforsequenceofTheorem 4.3 onforwardingtables ToestablishoptB(T0,U))]TJ /F3 11.955 Tf 13.17 0 Td[(m=2optI(T0,U),wenotethatoptI(T0,U)jT0j+maxf0,#inserts(U))]TJ /F4 11.955 Tf 12.76 0 Td[(#deletes(U)gandoptB(T0,U)jT0j+#inserts(U).So,optB(T0,U))]TJ /F3 11.955 Tf 12.46 0 Td[(optI(T0,U)ismaximumwhen#inserts(U)=#deletes(U).Since,#inserts(U)+#deletes(U)m,optB(T0,U))]TJ /F3 11.955 Tf 13.19 0 Td[(optI(T0,U)ismaximumwhen#inserts(U)=#deletes(U)=m=2.Atthistime,optB(T0,U))]TJ /F3 11.955 Tf 12.57 0 Td[(optI(T0,U)=m=2.Hence,optB(T0,U))]TJ /F3 11.955 Tf 12.68 0 Td[(m=2optI(T0,U).Forthetightnessofthisbound,considerasequenceUofm=2deletesfollowedbym=2insertsasinFigure 4-8 (onedeletethatenclosesm/2insertsandm/2-1deletesallofwhichareindependent).SinceUisincrementalconsistentwithitself,optI(T0,U)=jT0j.BatchconsistencylimitsustopermutationsofUinwhichtheinsertsprecedeallthedeletes.So,optB(T0,U)=jT0j+m=2.Hence,optB(T0,U))]TJ /F3 11.955 Tf 11.96 0 Td[(m=2=optI(T0,U). 150

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4.2.2BatchConsistentSequencesWhenperformingtheupdatesU=u1,,urinabatchconsistentmanner,ourprimaryobjectiveistoperformthefewestpossibleinserts/deletes/changestotransformT0toTrandoursecondaryobjectiveistoperformthesefewestupdatesinabatchconsistentorderthatminimizesthemaximumsizeofanintermediatetable.TheprimaryobjectiveismetbyusingthereductionV(U)ofU(Theorem 4.2 ).Forthesecondaryobjective,weconstructaprecedencegraph.Section 4.2.2.1 showshowabatchconsistentupdatesequencecanbeobtainedfromaprecedencegraphandinSection 4.2.2.2 wedescribeaheuristicforproducingabatchconsistentupdatesequencethatresultsinnear-optimalgrowthinthesizeoftheintermediateruletable. 4.2.2.1GraphrepresentationofupdatesWeconstructanmvertexdigraphGfromV=v1,,vm.VertexiofGrepresentstheupdateoperationvi.Let(Fi,Ai)betheruleassociatedwithupdatevi,1im.Thereisadirectededgebetweenverticesiandjiff(a)alleldsintuplesFiandFjoverlap,thatisFi\Fj=S,S6=;,whereSisatuplebuiltfromeldsrepresentingoverlappingregionsofFiandFj,(b)thereisnorule(Fk,Ak)suchthatFk\S6=;andpriorityof(Fk,Ak)liesbetweenthoseofrules(Fi,Ai)and(Fj,Aj),and(c)oneofthefollowingrelationshipsbetweenviandvjholdgood,assumingwithoutlossofgeneralitythatpriority(Fi,Ai)>priority(Fj,Aj). 1. viandvjareinserts)(i,j)2E(G),whereE(G)isthesetofdirectededgesofG. 2. viisaninsertandvjisadelete)(i,j)2E(G). 3. viandvjaredeletes)(j,i)2E(G). 4. viisadeleteandvjisaninsert)(j,i)2E(G). 5. viisaninsertandvjisachange)(i,j)2E(G). 6. viisadeleteandvjisachange)(j,i)2E(G). 151

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Denition10. iisanimmediatepredecessorofjinGiff(i,j)2E(G).iisapredecessorofjiffthereisadirectedpathfromitojinG. Figure4-9. Areducedupdatesequenceanditsprecedencegraph Weassignaweightof1,0,or)]TJ /F4 11.955 Tf 9.3 0 Td[(1tovertexiofprecedencegraphGdependingonwhetherviisaninsert,change,ordelete.Figure 4-9 givesanexamplereducedupdatesetVanditscorrespondingdigraphG.OnemayverifythatapermutationofareducedupdatesetVisbatchconsistentiffitcorrespondstoatopologicalorderingoftheverticesofG.Further,foreverytopologicalordering,jTij)-259(jT0jequalsthesumoftheweightsoftherstiverticesintheordering. Denition11. Foragiventopologicalorder,wedenewitobethesumoftheweightsoftherstivertices.Themaxweightofatopologicalorderismaxfwig.Anoptimaltopologicalorderingisatopologicalorderingthathasminimummaxweight.Althoughwehavebeenunabletodevelopanefcientalgorithmtondanoptimaltopologicalorder,weproposeanefcientheuristic(Figure 4-10 ).Noticethatoursecondaryobjectiveismetbyanoptimaltopologicalordering. 4.2.2.2Constructinganear-optimalbatchconsistentsequenceWeproposeanefcientheuristicinFigure 4-10 inwhichatopologicalorderisconstructedinseveralrounds.Ineachround,oneoftheremainingdeletesisselectedtobethenextdeleteinthetopologicalorderbeingconstructed.IncasenodeleteremainsinG,anytopologicalorderingoftheremainingverticesmaybeconcatenatedtotheorderingsofarconstructedtocompletetheoveralltopologicalorder.Assumeat 152

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Algorithm:computeOrder(G)createcandidateDeletesfromG,bylistingallthedeleteverticesinGthathavenopredecessordeletes.foreachdeletevertexd2candidateDeletescompute(a(d),b(d))wherea(d)=numberofinsertpredecessorsofd;b(d)=a-1-numberofdeletesuccessorsofdwithoutinsertpredecessors;endfornextDelete=NULL;whilethereisadeleteincandidateDeletesifthereisonlyonedeletedincandidateDeletesnextDelete=d;elseb smallest=smallestbamongthebvaluesforalldeletesincandidateDeletes.ifb smallest<0thennextDelete=d2candidateDeletess.t.b(d)<0anda(d)issmallestelseifb smallest==0thennextDelete=d2candidateDeletess.t.b(d)==0elsenextDelete=d2candidateDeletess.t.a(d)-b(d)islargestendifendifappend(nextDelete);//appendtotopologicalorderanddeleteappendedverticesfromG.ifanynewdeletesarefoundwhosepredecessordeleteshavebeenappendedandhencetheyhavenoremainingpredecessordeletesthencompute(a,b)valuesforallsuchfreeddeletesandaddthemtocandidateDeletes.endifendwhileconcatenatetheremainingverticesinanytopologicalorderingFigure4-10. Algorithmtocomputeanear-optimaltopologicalorder leastonedeleteremainsinG.OnlydeletesthatremaininGandthathavenodeletepredecessorsarecandidatesforthenextdelete.Eachcandidatedeletedisassignedan(a,b)valuewhereaisthenumberofinsertpredecessorsofdandb=a-thenumberofdeletesuccessorsofd(includingd)thathavenoinsertpredecessorsthatarenotalsopredecessorsofd.Fromthecandidatedeletes,weselectoneusingthefollowingrule. 1. Iftheleastbislessthan0,fromamongthecandidatedeletesthathavenegativeb,selectonewithleasta. 2. Iftheleastbequals0,selectanyoneofthecandidatedeletesthathaveb=0. 153

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3. Iftheleastbismorethan0,fromamongthecandidatedeletes,selectonewithlargesta)]TJ /F3 11.955 Tf 11.95 0 Td[(b.Oncethenextdeleteforthetopologicalorderingisselected,weconcatenateitsremainingpredecessorinsertsandchanges(theseinsertsandchangesarerstputintotopologicalorder)tothetopologicalorderingbeingconstructedfollowedbytheselecteddeletedfollowed(intopologicalorder)bythedeletesuccessors(andtheremainingchangepredecessorsofthesedeletesuccessors)ofdthathavenoremaininginsertpredecessors.Allnewlyaddedverticestothetopologicalorderingbeingconstructed(togetherwithincidentedges)aredeletedfromGbeforecommencingthenextroundselection.Ourheuristicismotivatedbythefollowingtwotheorems. Theorem4.4. ForeveryG,thereexistsanoptimaltopologicalorderinginwhichbetweenanytwosuccessivedeletesdianddi+1wehaveonlythepredecessorinsertsandchangesofdi+1thatarenotpredecessorinsertsandchangesofanyofthedeletesd1,,di.Hered1,arethedeletesofVindexedintheordertheyappearinthetopologicalordering. Proof. ConsideranoptimaltopologicalorderingofG.Examinethedeleteslefttoright.Letdi+1betherstdeletesuchthatthereisaninsertorchangebetweendianddi+1thatisnotapredecessorofdi+1.Allinsertsandchangesbetweendianddi+1thatarenotpredecessorsofdi+1maybemovedfromtheirpresentlocationinthetopologicalordering(withoutchangingtheirrelativeordering)tojustafterdi+1.Thisrelocationoftheinsertsandchangesyieldsanewtopologicalorderingthatalsoisoptimal.Repeatingthistransformationanitenumberoftimesresultsinanoptimaltopologicalorderingthatsatisesthetheorem. Forthesecondtheoremthatmotivatesourheuristic,letSbeasequenceofinsertsanddeletestobeperformed(inthegivenorder)onaforwardingtable.TheavalueofthesequenceSisthemaximumincreaseintablesizewhenthesequenceofinsertsanddeletesisdoneinthegivenorderandbistheincreaseintablesizefollowing 154

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thelastinsert/deleteinS.Forexample,whenS=I1I2D1I3D2D3,a=2andb=0.SupposewearegivennsequencesS1,S2,,Snofinsertsanddeletesandwewishtoconcatenatetheseintoasinglesequence.EverypermutationofS1,S2,,Sndenesalegalconcatenation.However,differentpermutationshavedifferent(a,b)values.Forexample,whenn=2,S1=I1I2I3I4D1D2D3D4andS2=I5I6D5D6D7D8,thepermissibleconcatenations/permutationsareS1S2andS2S1.The(a,b)valuesforS1,S2,S1S2andS2S1are,respectively,(4,0),(2,)]TJ /F4 11.955 Tf 9.3 0 Td[(2),(4,)]TJ /F4 11.955 Tf 9.3 0 Td[(2)and(2,)]TJ /F4 11.955 Tf 9.3 0 Td[(2).ThepermutationS2S1resultinthesmallestincreaseintablesizeandisthereforetheoptimalpermutation.Weintroducethefollowingnotation: 1. Q=f(a1,b1),(a2,b2),,(an,bn)gisasetof(a,b)valuescorrespondingtonupdatesequencesS1,S2,,Sn. 2. (Q)isapermutationofthepairsofQand(Q,i)istheithpairinthispermutation.Forsimplicity,(Q)and(Q,i)willbeabbreviatedtoand(i). 3. B((Q),i)=Pij=1b(j).B((Q),i)willbeabbreviatedtoB(i).NotethatB(i)isthesumofthesecondcoordinates(orbvalues)oftherstipairsof. 4. A((Q),i)=max1jifB(j)]TJ /F4 11.955 Tf 11.96 0 Td[(1)+a(j)gandisabbreviatedA(i).(Q)isanoptimalpermutationiffitminimizesA(n).Next,westateandproveatheoremtoconstructanoptimalpermutationofacollectionofupdatesequences. Theorem4.5. Let(Q)besuchthat: 1. Thepairswithnegativebcomerstfollowedbythosewithzerobfollowedbythosewithpositiveb. 2. Thepairswithnegativebareinincreasing(non-decreasing)orderofa. 3. Thepairswithzerobareinanyorder. 4. Thepairswithpositivebareindecreasing(non-increasing)orderofa)]TJ /F3 11.955 Tf 12.62 0 Td[(b.(Q)isanoptimalsequence. Proof. First,weshowthatpermutationsthatviolateoneofthelistedconditionscannothaveasmallerA(n)thanthosethatsatisfyallconditions.Considerapermutationthat 155

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doesnotsatisfytheconditionsofthetheorem.Supposethattherstviolationoftheseconditionsisatpositioniofthepermutation(i.e.,pairsiandi+1ofthepermutationviolateoneoftheconditions).Let(ai,bi)betheithpairand(ai+1,bi+1)bethei+1stpair.Let=maxfai,bi+ai+1gand'=maxfai+1,bi+1+aig.Weshallshowthat'.ThistogetherwiththeobservationthatA(i+1)=maxfA(i)]TJ /F4 11.955 Tf 10.02 0 Td[(1),B(i)]TJ /F4 11.955 Tf 10.03 0 Td[(1)+ai,B(i)]TJ /F4 11.955 Tf 10.02 0 Td[(1)+bi+ai+1gimplythatswappingthepairsiandi+1doesnotincreaseA(i+1).Byrepeatedlyperformingtheseviolationswapsanitenumberoftimes,weobtainapermutationthatsatisestheconditionsofthetheoremandthathasanA(n)valuenolargerthanthatoftheoriginalpermutation.Hence,apermutationthatviolatesalistedconditioncannothaveasmallerA(n)thanonethatsatisesallconditions.Toshow',weconsiderthefourpossiblecasesforaviolationoftheconditionsofthetheorem(a)bi0andbi+1<0(violationofcondition1),(b)bi>0andbi+1=0(violationofcondition1),(c)ai>ai+1,bi<0,andbi+1<0(violationofcondition2),and(d)ai)]TJ /F3 11.955 Tf 10.91 0 Td[(bi0,andbi+1>0(violationofcondition4).Notethatcondition3cannotbeviolatedasthisconditionpermitsarbitraryorderingofpairswithzerob.Infact,weseethatwhenbi=bi+1=0,='=maxfai,ai+1gandswappingthepairsiandi+1doesnotaffectA(i+1).Case(a):Weseethatbi+ai+1ai+1andbi+1+ai0,wegetai0,andbi+1>0(tieincondition4).Thisiseasilyestablished. 156

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SincethevertexweightsinGare1,0,and)]TJ /F4 11.955 Tf 9.3 0 Td[(1,themaxweightofatopologicalorderingcannotexceedm,thenumberofverticesinGandcannotbelessthan)]TJ /F4 11.955 Tf 9.29 0 Td[(1.Themaximumnumberoftableentriesoccurs,forexample,whenallviareinsertsandtheminimumhappens,forexample,whenallviaredeletes.So,atopologicalorderingmayhaveamaxweightthatexceedstheminimummaxweightbyO(m).Ourheuristicmayproducetopologicalorderingswhosemaxweightis(m)morethanthatoftheoptimalordering.Forexample,considerthedigraphofFigure 4-11 thathastwocomponents.Therstcomponentiscomprisedofadeleted1thathasm=3)]TJ /F4 11.955 Tf 12.72 0 Td[(2 Figure4-11. Adigraphforwhichourheuristicproducessub-optimalordering insertsthatareimmediatepredecessorsandm=3)]TJ /F4 11.955 Tf 12.62 0 Td[(4immediatesuccessordeletes.Thesecondcomponenthasadeleted2thathas2immediatepredecessorinsertsandasuccessordeleted3thatalsohas2immediatepredecessorinsertsandm=3)]TJ /F4 11.955 Tf 12.94 0 Td[(1immediatesuccessordeletes.Deletesd1andd2arethecandidatedeletesduringtherstroundofourheuristic.Their(a,b)valuesare(m=3)]TJ /F4 11.955 Tf 12.2 0 Td[(2,)]TJ /F4 11.955 Tf 9.3 0 Td[(1)and(2,1),respectively. 157

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Deleted1isselectedbyourheuristicandthepartialtopologicalorderingconstructedhasm=3)]TJ /F4 11.955 Tf 12.15 0 Td[(2insertsfollowedbym=3)]TJ /F4 11.955 Tf 12.16 0 Td[(3deletes.Inthenextroundd2precededbyits2predecessorinsertsisaddedtotheordering.Finally,inthethirdround,d3precededbyits2predecessorinsertsandfollowedbyitsm=3)]TJ /F4 11.955 Tf 12.37 0 Td[(1successordeletesisadded.Themaxweightoftheconstructedtopologicalorderingism=3)]TJ /F4 11.955 Tf 12.15 0 Td[(2(assumem=34).Inanoptimalordering,therstcomponentappearsafterthesecondandthemaxweightis3.So,theheuristicorderinghasamaxweightthatism=3)]TJ /F4 11.955 Tf 11.96 0 Td[(5=O(m)morethanoptimal. Figure4-12. Adeletestar WhenevereachcomponentofGisadeletestarasinFigure 4-12 ,ourheuristicndsanoptimalordering.Notethatinadeletestar,wehaveadeletevertexallofwhosepredecessorsareinsertsand/orchangesandallofwhosesuccessorsaredeletesthathavenoadditionalpredecessorinserts.ThisfollowsfromTheorem 4.5 andtheobservationthateachcomponenthasonlyonedeletethateverbecomesacandidateforselectionbyourheuristic.Ingeneral,whenevernocomponentofGhastwodeletesthatbecomecandidatesforselection,ourheuristicobtainsanoptimaltopologicalordering.Althoughthispropertydoesn'tholdfortheGthatariseinpractice,theGthatariseinpracticehaveasufcientlysimplestructurethatourheuristicobtainsoptimaltopologicalorderings.Figure 4-13 showssomeofthemorecomplexcomponentsintheGsoftraceupdatedataforforwardingtables. 4.2.3IncrementalConsistentSequencesWhenperformingtheupdatesU=u1,,urinanincrementalconsistentmanner,theprimaryandsecondaryobjectivesarethesameasthoseforbatchconsistency.The 158

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Figure4-13. Someofthecomplexdigraphcomponentsofthetraceupdatedata. primaryobjectiveistoperformthefewestpossibleinserts/deletes/changestotransformT0toTr.Thesecondaryobjectiveistoperformthesefewestupdatesinanincrementalconsistentorderthatminimizesthemaximumsizeofanintermediatetable.TheprimaryobjectiveismetbyusingthereductionV(U)ofU(Theorem 4.2 ).NotethatsinceV(U)hasabatchconsistentordering,ithasalsoanincrementalconsistentordering.Forthesecondaryobjective,however,thereisnodigraphH(V)whosetopologicalorderingscorrespondtothepermissibleincrementalconsistentorderingsofV(U).Toseethis,consideraforwardingtableT0=f(,H0),(00,H1)gandU=u1,u2,u3=delete(00),insert(000,H2),insert(0,H3).Forthisexample,V(U)=Uandtheincrementalconsistentorderingsareu1u2u3,u2u1u3,u2u3u1,andu3u2u1.Theremainingtwoorderingsu1u3u2andu3u1u2arenotincrementalconsistent.Toseethatu1u3u2,forexample,isnotincrementalconsistent,notethatfollowingu3,thenexthopfordestinationaddressesthatareoftheform000*isH3whereasintheoriginalorderingu1u2u3thesedestinationaddresseshavenexthopH1initially,H0followingu1,andH2followingbothu2andu3. 159

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AnyH(V)thatdisallowsthetopologicalorderingu1u3u2musthaveatleastoneofthedirectededges(u3,u1),(u2,u1),and(u2,u3).However,thepresenceofanyoneoftheseedgesinH(V)alsoinvalidatesoneofthefourpermissibleorderings.So,noH(V),whosetopologicalorderingscoincideexactlywiththesetofpermissibleorderings,exists.Wecanformulatemeta-heuristic(e.g.,simulatedannealing,genetic,etc.)basedalgorithmstodeterminenearoptimalincrementalconsistentorderingsofV(U).However,giventherathersimplerelationshipsthatexistinourtestupdatesequences,itisunlikelythesewillprovideincrementalorderingsthataresignicantlysuperiortothebatchconsistentorderingsgeneratedbyouralgorithmofFigure 4-10 4.3ExperimentsThebenchmarksusedfortheexperimentsaredescribedinSection 4.3.1 andtheresultsarepresentedinSection 4.3.2 4.3.1BenchmarksWehaveappliedourheuristictoobtainnearoptimalbatchconsistentsequencesontwosetsofbenchmarks.Therstsetofbenchmarksconsistof21datasetsderivedfromBGPupdatesequencesofvariousrouters[ 6 37 ].Table 4-1 givesthedetailsofthesedatasets,withtherstandsecondcolumnsshowingthenameandthetotalnumberofprexesintheinitialforwardingtableforeachdataset.Thethirdcolumngivestheperiodforwhichthedatahasbeencollected.Columnsfourtoseven,respectively,givethenumberofinsert,deleteandchangeoperations,andthetotalnumberofoperationsforeachdataset.Allthedatasetsexceptrrc00Jan25werecollectedstartingfromthezerothhouronFebruary1,2009.Thelastone,rrc00Jan25,isforthe3hourperiodfrom5:30amto8:30amonJanuary25,2003,whichcorrespondstotheSQLSlammerwormattack[ 17 ].Theinsert,deleteandchangeoperationsinTable 4-1 arederivedfromBGPupdatemessagesreceivedbytherouter.BGPisessentiallyanincrementalprotocolin 160

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whicharoutergeneratesupdatemessagesonlywhenthereisachangeinitsroutingstate.Suchachangecouldbeinthenetworktopology(forexamplewhenarouterfailsorcomesupafterfailureorisaddedtothenetwork)orintheroutingpolicy.TheBGPupdatemessagesconsistingofrouteannouncementsandwithdrawalsaresentoversemi-permanentTCPconnectionstotheneighboringrouters.Arouteannouncementadvertisesanewroutetoaprex.Uponreceivinganannouncement,aroutercomparesthenewlyadvertisedroutewiththeexistingonesforthesameprexintheroutinginformationbase(RIBorroutingtable).IftherearenoexistingroutesthenanewprexisinsertedtotheforwardingtablealongwiththenexthopasIPaddressoftheBGPpeerfromwhichtheannouncementwasreceived.If,ontheotherhand,thereareexistingroutes,thenthenewrouteiscomparedwiththeexistingonesbyapplyingtheBGPselectionrules.Ifthenewrouteissuperiortothebestamongtheexistingroutes,thentherulecorrespondingtotherouteischangedintheforwardingtablebychangingthenexthoptopointtotheBGPpeerthatsentthenewrouteannouncement.Ifthenewrouteisinferiortothebestexistingroute,thentheannouncementhasnoeffectontheforwardingtableandhencetheroutingpolicy.ThenewrouteisstoredintheRIBinanycase.WegeneratedtheinsertandchangenexthopoperationscorrespondingtorouteannouncementsinourexperimentsinkeepingwiththeforwardingtableupdatestrategyofBGP.Aroutewithdrawalmessage,similarly,triggersanumberofactionsatarouter.TherouterremovestheroutefromtheRIB,andthenchecksifthereareexistingroutesfromdifferentpeerstothesameprex.Iftherearenosuchroutes,thentheforwardingrulefortherouteisdeletedfromtheforwardingtable.Ontheotherhand,iftherearemoreroutesandthewithdrawnroutewasthebestamongthem,thenthenextbestrouteispickedfromtheremainingroutesbyapplyingtheBGPselectionrulesandtheforwardingtableisupdatedbychangingappropriatelythenexthopoftherulecorrespondingtotheroute.Otherwise,ifthewithdrawnrouteisnotthebestamongtheexistingroutes,then 161

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theforwardingtableisleftunchanged.Justasforrouteannouncements,wegeneratedthedeleteandchangenexthopoperationscorrespondingtotheroutewithdrawalsinlinewiththeBGPupdatestrategyforforwardingtables.Therefore,someofthewithdrawalsmaynotleadtoanyoperations,justassomeoftheannouncements.WenotethattheIETFrecommendsthatBGProutersuseminRouteAdverwithatimervalueof30seconds.This,togetherwithrouteapdampeningmechanismswilleliminateredundanciesinBGPupdateclusters.Forupdatesequencesthatareguaranteedtobefreeofredundancies,theredundancyremovalstepofFigure 4-4 maybeeliminated.Notethatouralgorithmchangestheorderinwhichupdates(receivedinabatch)areappliedtotheforwardingtable.Thus,theforwardingtableistheonlyentitythatisaffected,whichinturn,affectspacketforwarding.Ouralgorithmsdonotaffecttheroutingtable(RIB)oranyBGPmessagebeingsentoutfromtherouter.Thus,ouralgorithmsdonotaffectthevariousnuancesofBGPincludingtheBGPconvergencetime.Thesecondsetofbenchmarksconsistof24syntheticclassiersgeneratedusingClassBench[ 50 ]asshowninTable 4-2 .Therstcolumninthisgurepresentsthenamesoftheclassiers,thesecondcolumnshowsthenumberofrulesineachoftheclassiers,andcolumnsthreetosixgivethenumberofinserts,deletes,andchangeoperationsintheupdatetracesaswellasthetotalnumberofupdateoperationsforeachdataset.Weused12seedlesbasedonaccesscontrollists(acl),rewalls(fw)andIPchains(ipc)togenerate24classiers.Eachruleconsistsoftheelds:sourceaddress,destinationaddress,sourceportrange,destinationportrange,protocol.Wecreatedanupdatetracefromtheclassiersbymarkingrulesforinsertion/deletion/changerandomly,andlaterremovingtherulesmarkedforinsertion.Thecorrespondinginsert,deleteandchangeoperationsareshufedandthenwrittentotheupdatele. 162

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Table4-1. Datasetsusedintheexperiments DataSet#PrexesTime(hours)#Inserts#Deletes#Changes#Total-updates rrc0029409875.73955340051368013447617rrc0127679575.24169241988492315575995rrc0328375442.72770227914292454348070rrc0428861017.01608615977193392225455rrc05280041103.02027618285439647478208rrc06278744235.0157549157547289272604368rrc072750970.417247218179835180300rrc10278898105.02162022473326720370813rrc1127716680.25811558378290621407114rrc1227849962.33319633572410464477232rrc1328498657.82392023713284710332343rrc1427617083.65659856810203955317363rrc15284047134.09579093750183131372671rrc16282660672.03338937889613171rv229412756.51388215552679100708534rv427573795.06962769754526302665683rv.eqix27573670.35110451066253693355863rv.isc28109568.24428644444292323381053rv.linx27819649.12313723413384344430894rv.wide283569174.0101821103862372035577718rrc00Jan251228013.01827519455272115309845 4.3.2ResultsThetwofollowingsubsectionspresenttheresultsofapplyingourmethodology(Figure 4-4 )onforwardingtablesaswellasonthesyntheticallygeneratedpacketclassiers. 4.3.2.1ForwardingtablesTable 4-3 givesthetotalnumberofupdateoperationsthatremainafterapplyingourreductionalgorithmtoeachupdatebatchofTable 4-1 .1.Allupdateswiththesametimestampdeneabatch.Whenreductionisappliedtobatchesofupdates 1Asnotedearlier,BGProutersimplementminRouteAdvertimerandrouteapdampeningmechanisms.Thusalthoughweseeredundanciesinourdataset,ideally,BGPupdatesequenceswillnothaveredundancies 163

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Table4-2. Syntheticclassiersandupdatetracesusedintheexperiments DataSet#Rules#Inserts#Deletes#Changes#Total-updates acl1 100k5152247839287031913595677acl1 200k156418421194211921059105297acl2 100k6027815835211141583552784acl2 200k100276204574091540915102287acl3 100k866101286821447857842893acl3 200k138046607567594615189151891acl4 100k6216537138278542785492846acl4 200k17545122902114512290257255acl5 100k88171955023871193823875acl5 200k147411525893505987649175297fw1 100k7694711185167782796355926fw1 200k106740506314050410126101261fw2 100k877578289414463315782892fw2 200k91664999803635645445181781fw3 100k4677036016130971637165484fw3 200k105870402355747917243114957fw4 100k608762295225502255051004fw4 200k98108679525285130201151004fw5 100k732021075323656860243011fw5 200k118636312554375750008125020ipc1 100k5213047103128462569285641ipc1 200k116826816342449057144163268ipc2 100k6006839932119792795279863ipc2 200k138945610554748727135135677 withthesametimestamp,thereductionofthenumberofupdatesvariedbetween0.1%(rrc07)and23%(route-views.linx)withanaverageof6.64%.Afterapplyingreductiontoremovetheredundantoperations,theremainingoperationsarearrangedinaconsistentsequenceusingournearoptimalheuristicinFigure 4-10 andthefthcolumninTable 4-3 givesthemaximumgrowthintheforwardingtable. 4.3.2.2PacketclassiersTheupdatetracesfortheclassierbenchmarks(Table 4-2 )weresyntheticallygeneratedtobefreefromredundancies.Table 4-4 givesthegrowthinthepacketclassierscomparedtotheinitialtablesize.Therstcolumnpresentsthenamesofeachdataset,whereastheothercolumnsindicatethemaximumincreaseinsizeofthe 164

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Table4-3. Totalnumberofupdatesbeforeandafterapplyingreductionandthemaximumincreaseintablesize DataSetsBeforereductionAfterreductionPercentdecreasein#updatesMaximumincreaseintablesize rrc004318673936918.84219rrc015748795179749.90206rrc0333924129414713.29709rrc042254542248480.27301rrc054731364366997.702181rrc066043676021350.37457rrc071801391799560.1032rrc103708063662351.231259rrc114031403823775.15224rrc1247584342233411.25655rrc133292003146524.42634rrc143174363085462.80214rrc153494693447061.362439rrc1612363122980.532534rv269033957022917.40470rv46535115938649.13305rv.eqix3180193043754.29493rv.isc38063033632811.64334rv.linx43035533134723.0186rv.wide5777155729630.82995rrc00Jan2553113499126.031158 classierastheupdatesareclusteredasindicated,andaresubjectedtoconsistentsequencingusingourheuristic.ThecomponentsoftheprecedencegrapharesimplisticandourheuristicinFigure 4-10 willproduceoptimalupdatesequencesforalltheclassierbenchmarksusedinourexperiments.Whenweapplyouralgorithmstotheentiresetofupdates,thenweseearemarkabledropinthemaximumgrowthtozeroformostdatasetsinTable 4-4 .Thiscanbeexplainedbythelargenumberofdeletesintheupdatesequencesandtheavailabilityofmoredeletesthatrequirenopriorinserts,asalltheupdatesareconsidered.Thesedeletesareputrstinthenewsequencefreeingupenoughspaceintheruletabletoholdthenewlyinsertedruleswithoutanyincreaseinthesizecomparedtotheinitialtable. 165

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Table4-4. Maximumincreaseinintermediateclassierruletablesize DataSetAfterapplyingheuristicinFigure 4-10 foreveryxupdates x=100x=200x=300x=400x=500 acl1 100k245240240234200acl1 200k411403407401403acl2 100k00000acl2 200k00000acl3 100k00000acl3 200k00000acl4 100k11211211290108acl4 200k00000acl5 100k8989688950acl5 200k154143139125143fw1 100k00000fw1 200k492492473450473fw2 100k00000fw2 200k00000fw3 100k22222200fw3 200k00000fw4 100k2727112726fw4 200k00000fw5 100k00000fw5 200k00000ipc1 100k233233176176141ipc1 200k00000ipc2 100k00000ipc2 200k1616161615 Amajorchallengeinefcientrouterdesignishowtoperformfastandconsistentupdates.Wepresentedamethodologyforperformingincrementalupdatesinclassiertables,whenupdatesarrivetogetherinclusters.Byorderingtheupdatesinaconsistentmanner,weensurethatthedatapacketsarehandledproperlyintermsofbeingforwardedtoappropriatenexthops,orbeingappliedtheproperaction(e.g.accept/deny/drop).InthenextchapterwewilldiscussaboutpowerefcientTCAMarchitecturesforpacketclassiers.Amajorchallengeinefcientrouterdesignishowtoperformfastandconsistentupdates.Inthischapter,wepresentedamethodologyforperformingincremental 166

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updatesinclassiertables,whenupdatesarrivetogetherinclusters.Byorderingtheupdatesinaconsistentmanner,weensurethatthedatapacketsarehandledproperlyintermsofbeingforwardedtoappropriatenexthops,orbeingappliedtheproperaction(e.g.accept/deny/drop).Twotypesofconsistency,namely,batchconsistencyandincrementalconsistencyhavebeenintroducedandareductionmethodispresentedwhichidentiesandremovestheredundantupdatesfromagivenbatchofupdates.Weshowedthattheinsert/delete/changeoperationsthatarriveinaclustermaybeconvenientlyrepresentedasaprecedencegraph.Everytopologicalorderingoftheverticesintheprecedencegraphgivesusabatchconsistentsequence.Amongallthebatchconsistentsequencesitisdesirabletohavetheonethatleadstominimumgrowthoftheruletableatthetimeofincorporatingtheupdates.Wepresentedanefcientheuristicthatbuildsanearoptimalbatchconsistentsequenceforpracticaldatasets.Forincrementalconsistentorderings,weshowedthatthereisnoprecedencegraphwhosetopologicalorderingscorrespondtoallthepermissibleincrementalconsistentorderings. 167

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CHAPTER5PC-DUOS:FASTTCAMLOOKUPANDUPDATEFORPACKETCLASSIFIERSThemaingoalofstoringpacketclassiersinTCAMsistoenablehighspeedtablelookup.Itispossibletoimplementasoftwaresolutionforpacketclassication,butitisdifculttoachievethesearchspeedrequirementingigabitroutersusingapurelysoftwaresolution[ 10 15 ].Inthischapter,weexploreadualTCAMarchitectureforpacketclassierswhichenablefasterupdatesandlookup.Thechapterisorganizedasfollows.Section 5.1 presentsbackgroundandrelatedresearchwork,whileSection 5.2 presentsthemethodologyofstoringandupdatingpacketclassiersinPC-DUOS,andSection 5.3 presentsexperimentalresults.WeconcludeinSection?? 5.1BackgroundandRelatedWorkPC-DUOS(PacketClassier-DUOS)isanextensionofDUOS[ 26 ],whichhasbeenproposedforpacketforwarding,anddescribedinChapter3.DUOS,asshowninFigure 3-2 ,hastwoTCAMs,labeledastheITCAM(InteriorTCAM)andtheLTCAM(LeafTCAM).DUOSalsoemploysabinarytrieinthecontrolplaneoftheroutertorepresenttheprexesintheforwardingtable.TheprexesfoundintheleafnodesofthetriearestoredintheLTCAM,andtheremainingprexesarestoredintheITCAM.TheprexesstoredintheLTCAMareindependentandthereforeatmostoneLTCAMprexcanmatchaspecieddestinationaddress.HencetheLTCAMdoesn'tneedapriorityencoder.PrexlookupworksinparallelonboththeTCAMs.IfamatchisfoundintheLTCAMthenthatisguaranteedtobethelongestmatchingprexandthecorrespondingnexthopisreturned.AtthesametimetheongoinglookupprocessontheITCAM(whichtakeslongerduetothepriorityresolutionstep)isaborted.Thus,ifamatchisfoundontheLTCAM,theoveralllookuptimeisshortenedbyabout50%[ 3 ].ThenalstagelogicinFigure 3-2 thatchoosesbetweenthetwonexthopscouldbemovedaheadandplacedbetweentheTCAMandSRAMstages.Inthatcase,thelogicreceivesone 168

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matchingindexinputfromtheLTCAMandanotherfromtheITCAM.IfamatchisfoundintheLTCAM,theindexfromLTCAMinputisusedtoaccesstheLSRAM,otherwise,theITCAMindexisusedtoaccesstheISRAM.Further,ifamatchisfoundintheLTCAM,theITCAMlookupisaborted.Tosupportlock-freeupdates,sotheTCAMscanbeupdatedwithoutlockingthemfromlookups,DUOSimplementsconsistentupdateoperationsthatruleoutincorrectmatchesorerroneousnexthopsduringlookup.Forconsistentupdates,itisassumedthat: 1. EachTCAMhastwoports,whichcanbeusedtosimultaneouslyaccesstheTCAMfromthecontrolplaneandthedataplane. 2. EachTCAMentry/slotistaggedwithavalidbit,thatissetto1ifthecontentfortheentryisvalid,andto0otherwise.ATCAMlookupengagesonlythoseslotswhosevalidbitis1.TheTCAMslotsengagedinalookuparedeterminedatthestartofalookuptobethoseslotswhosevalidbitsare1atthattime.Changingavalidbitfrom1to0duringadataplanelookupdoesnotdisengagethatslotfromtheongoinglookup.Similarly,changingavalidbitfrom0to1duringadataplanelookupdoesnotengagethatslotuntilthenextlookup.Additionally,theavailabilityofthefunctionwaitWriteValidateisassumedwhichwritestoaTCAMslotandsetsthevalidbitto1.IncasetheTCAMslotbeingwrittentoisthesubjectofanongoingdataplanelookup,thewriteisdelayedtillthislookupcompletes.Duringthewrite,theTCAMslotbeingwrittentoisexcludedfromdataplanelookups.Similarly,theavailabilityofthefunctioninvalidateWaitWrite,isassumed.ThisfunctionsetsthevalidbitofaTCAMslotto0andthenwritesanaddresstotheassociatedSRAMwordinsuchawaythattheoutcomeoftheongoinglookupisunaffected.AlltheseassumptionsforDUOSarealsomadebyourPC-DUOSarchitecture.TheproblemofincorporatingupdatestopacketclassiersstoredinTCAMshasbeenstudiedin[ 54 ]and[ 43 ].Theauthorsin[ 54 ]presentamethodforconsistentupdateswhentheclassierupdatesarriveinabatch.AlldeletesinanupdatebatcharerstperformedtocreateemptyslotsintheTCAM.Thentherelativepriorityoftherelevantrules(forexamplerulesoverlappingwithanewrulebeinginserted)is 169

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determinedandtheexistingrulesaremovedaccordinglytoreectanychangeinpriorityorderingastheentirebatchofupdatesisapplied.Followingtheorderingofexistingrules,newrulesareinsertedinappropriatelocations.Aproblemwiththealgorithmof[ 54 ]isthatitperformsthedeletesintheupdatebatchrst.Thiscouldleadtotemporaryinconsistenciesinlookup[ 25 ].Givenapacketclassier,anaiveapproachistostoreitinaTCAMbyenteringeachrulesequentiallyastheyappearintheclassieranddistributealltheemptyslotsbetweenrules.Asmentionedin[ 43 ],thisapproachcouldleadtohighpowerconsumptionduringlookupasthewholeTCAMhastobesearchedincludingtheemptyentries.Ontheotherhand,iftheemptyentriesarekepttogetheratthehigheraddressesoftheTCAM,thenthosemaybeexcludedfromlookups.However,iftheemptyspacesarekeptatoneendoftheTCAM,thenitwouldrequirealargenumberofrulemovestocreateanemptyslotatagivenlocation.Specically,alltherulesintheTCAM,belowtheslottobeemptiedmustbemovedbelow.WeuseasimpleTCAM(STCAM)architectureforperformancecomparison.TheSTCAMisamodicationoverthenaiveTCAMinthattherulesaregroupedbyblocknumbers,whichreducesthenumberofrequiredmoveswhenafreeslotisneeded.Therequirednumberofmovesisnowboundedbythetotalnumberofblocks.Theblocknumbersareassignedtotherulesusingthealgorithmpresentedin[ 43 ],basedonaprioritygraph.Inthismethodasubsetoftherulesisidentiedsuchthatwithinthesubset,eachruleoverlapswitheveryotherrule.Eachruleinthesubsetisassignedadifferentblocknumberbasedonitspriority.Blocknumberscanbereusedfordifferentnon-overlappingrulesubsets.Thus,ruleswiththesameblocknumberareallnon-overlappingorindependent.Tworulesareindependentiffthereisnopacketthatmatchesboththerules.Filtersaregroupedbasedontheirassignedblocknumbers.ThegroupwiththelowestblocknumberisofhighestpriorityandtheserulesarestoredinthelowestmemoryaddressesoftheTCAM. 170

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SongandTurner[ 43 ]describeafastTCAMupdateschemeonpacketclassiers.Intheirmethod,theclassierrulesareenteredarbitrarilyintheTCAMandarenotarrangedaccordingtodecreasingorderofpriority.TheyensurethattheactioncorrespondingtothehighestprioritymatchingruleisreturnedbyperformingmultiplesearchesontheTCAM.Specically,theyassignapriority(whichwecallblocknumberhere)toeachruleandencodetheblocknumberasaTCAMeldandallowthehighestpriorityTCAMmatchtobefoundusinglog2nsearches,wherenisthetotalnumberofblockvaluesassignedintheclassier.Thehighestprioritymatchcorrespondstotherulewiththeminimumblocknumber.TheruleanditsassignedblocknumberareenteredintheTCAM.EventhoughthismethoddoesnotincurTCAMwritesduetorulemovesformaintainingconsistentblocknumbersforoverlappingrulesortocreateanemptyslotattherightplaceforinsertinganewrule,thismethodinvolvesanumberofTCAMwritesastheassignedblocknumbersofruleschangeduetoinsertsordeletes.Moreover,lookupspeedissloweddownsincemultipleTCAMsearchesarerequiredandthesesearchescannotbepipelinedastheytakeplaceonthesameTCAM.OurPC-DUOSarchitectureperformslookupusingasingleTCAMsearch. 5.2PC-DUOS:MethodologyPC-DUOSusesthesametwoTCAMarchitectureasusedinDUOS(Figure 3-2 inChapter3).LookupalsoworksinthesamewayasforDUOS.Thatis,theLTCAMandITCAMaresearchedinparallelusingthepacketheaderinformation.IncaseamatchisfoundintheLTCAM,theongoingsearchintheITCAMisaborted.WhentheITCAMsearchisaborted,lookuptimeisreducedbyabout50%[ 3 ],becausetheLTCAMhasnopriorityencoder.Forthislookupstrategytoyieldcorrectresults,thefollowingrequirementsmusthold: REQ1) NopacketismatchedbymorethanoneruleintheLTCAM. REQ2) WhenapacketismatchedbyaruleintheLTCAM,thematchedrulemustbethehighestprioritymatchingrule. 171

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ThealgorithmsusedforstoringandupdatingrulesintheTCAMsarediscussedindetailinthissection. 5.2.1StoringRulesinTCAMsFigure 5-1 showstheoverallowofourmethodologyofstoringrulesintheITCAMandLTCAMofPC-DUOS.Therstphaseinvolvesstoringalltherulesinamulti-dimensionaltriemaintainedonthecontrolplaneoftheclassier.ThisisfurtherdiscussedinSection 5.2.1.1 .Thesecondphaseinourmethodologyconsistsoftraversingthemulti-dimensionaltrieandidentifyingindependentrulesforinclusionintheLTCAMasdiscussedinSection 5.2.1.2 .Inthethirdphase,rulesnotstoredintheLTCAMarestoredintheITCAMinpriorityorder.ThisisdiscussedinSection 5.2.1.3 Figure5-1. FlowdiagramforstoringpacketclassiersinTCAMs 5.2.1.1RepresentingclassierrulesTheclassierrulesarerepresentedinamulti-dimensionaltrie,whereeachdimensionrepresentsoneeldoftherule.Theeldsinalterruleappearinthefollowingorderinthetrie:.Weassumethatthedestinationandsourceeldsoftheltersarespeciedasprexes.So,thesearerepresentedinatrieinthestandardwaywiththe 172

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leftchildofanoderepresentinga0andtherightchilda1.Rangesmaybehandledinoneofmanyways.Inthischapter,weconsidertheDIRPEschemeof[ 18 ]thatrequirestheuseofamultibittrie.Ourmethodologymayalsobeappliedtootherrangeencodingschemes[ 8 11 ]. 5.2.1.2StoringrulesintheLTCAMRecallthattworulesareindependentiffnopacketismatchedbybothrules.FortheLTCAMweareinterestedinidentifyingthelargestsetofrulesthatarepairwiseindependent.Notethateveryindependentrulesetsatisestherstrequirement,REQ1,foralookuptoworkcorrectly.Tondanindependentrulesetinacceptablecomputingtime,werelaxthelargestsetrequirementandinsteadlookforalargesetofindependentrules.Itiseasytoseethattherulesinthenodesobtainedbytraversingthemultidimensionaltriefromtheroottotheleavesoftheouterleveltrieandthenfromtheseleavesintotheirattachednextleveltriesandsoonuntilwereachleavesoftheinnermostleveltriesareindependent.Wecallthissetofindependentrulestheleavesofleavesset. Figure5-2. Exampleofatwo-dimensionaltriestoringthreerules:R1,R2andR3 Figure 5-2 showsanexampleclassier,withthreerules.Theouterleveltrie(level1)isonthedestinationprexandtheinnerlevel(level2)isonthesourceprex.RulesR2andR3belongtotheleaves-of-leavesset,becausetheyarestoredatleavesoftheir 173

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sourcetrieandthesourcetrieitselfhangsoffaleafinthedestinationtrie.Ontheotherhand,R1doesnotbelongtotheleaves-of-leavesseteventhoughitisstoredinaleafofitssourcetriebecausethissourcetriehangsoffanon-leafnodeinthedestinationtrie.Itiseasytoseethattheleaves-of-leavessetofrulesareindependent.Althoughtherulesintheleavesofleavessetareuniquelydeterminedbythemulti-dimensionaltrie,bychangingthemappingbetweenltertuplecomponentsandtriedimension,wegetdifferentleavesofleavessetsofpossiblydifferentsize.Forexample,whenthedimensionorderingis,theleavesofleavessetisdifferentfromwhentheorderingisused.ThealgorithmofFigure 5-3 partitionstherulesetintotwolistsleafListandotherList,whereleafLististheleavesofleavesset,andotherListcontainstheremainingrules.Inthealgorithm,thetrieistraversedinpostorderfashion,startingwiththerootofthemulti-dimensionaltrie.Uponhittingaleafnode,wejumptoatrieforthenexteldvaluesstoredatthatleafnode.Forthistrietoo,wetraversethetrietillwehitaleaf,andthenswitchtothetriestoredatthatleaf.Wecontinuethiswaytillthelasteld.IntheexampleofFigure 5-2 ,R2andR3areaddedtotheleafListandR1isaddedtotheotherListthatistocontaintheremainingrules.OurruleplacementstrategyplacesallrulesinotherListintheITCAM.Additionally,itmaybenecessarytoplacesomeoftherulesinleafListintheITCAMaswellsoastoensurethattheruleswhichwillbeplacedintheLTCAM,satisfythesecondrequirementforlookupcorrectness.Oncetheleaves-of-leavessetofruleshasbeenidentiedandputintoleafList,thenforeachruleRinleafListitischeckedifthereexistsahigherpriorityruleinotherList(containingrulesforinsertioninITCAM)thatoverlapswithR.Ifthereis,thenthisruleisaddedtotheITCAM.InFigure 5-2 ,R3,whichisinleafList,isaddedtotheITCAMinsteadoftheLTCAM,sinceithaslowerprioritycomparedtotheotherListruleR1.Thus,inourthreeruleexampleofFigure 5-2 ,R2isaddedto 174

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Algorithm:assignRules(node)Inputs:node:atrienode,settorootofmulti-dimensionaltrie,initially.Output:leafList:alistofrulesconsistingofpotentialcandidatesforLTCAM.foreachchildiofnodeassignRules(node!child[i]);endforif(node!valid)//trueifnodecontainsaruleorarootofatrieforthenexteld.if(nodecontainsrootofatrie)if(nodeisaleaf)//trueifnodehasnochildren.assignRules(node!trie!root);else//nodebelongstotrieforthelasteldandcontainsaruleif(nodeisaleaf)appendnode(asrepresentativeofrule)toleafListendifendifendifFigure5-3. SelectingrulesforinsertionintoLTCAM theLTCAMandR1andR3areaddedtotheITCAM.SincetherulesassignedtotheLTCAMareindependent,theycanbeenteredinanyorderandthereisnoneedforapriorityencoder.OurLTCAMruleselectionprocessguaranteesthatamatchfoundintheLTCAMduringlookupwillbeofthehighestpriority.Thus,duringlookup,ifamatchisfoundintheLTCAM,thenthecorrespondingactioncanbereturned,withoutwaitingfortheITCAMlookuptonish.TheITCAMlookupmustgothroughapriorityencodertoresolvemultiplematches.ThismakeslookupsthatndamatchintheLTCAMquickerbyabout50%[ 3 ]. 5.2.1.3StoringrulesintheITCAMAprioritygraphisrstcreatedforeachruletobestoredintheITCAM.Thereisadirectededge(u,v)fromvertexutovertexviff(a)therulescorrespondingtouandvoverlap(i.e.,atleastonepacketmatchesbothrules)and(b)thepriorityofuismorethanthatofv(weassumethatoverlappingruleshavedifferentpriority).Forthedirectededge(u,v),wesaythatuistheparentofvandvisthechildofu.Theprioritygraphisusedtoassignblocknumberstorules/verticesasfollows[ 43 ].Allverticeswithin-degree0areassignedtheblocknumber1.Eachremainingvertexvisassignedablocknumber 175

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equalto1+max(u,v)2EfblocknumberofugwhereEisthesetofedgesintheprioritygraph.Thusachildofanyvertexisassignedablocknumberthatisatleastonemorethantheblocknumberofthisvertex.Therststepinbuildingtheprioritygraph,isaniterationovertherulesdesignatedfortheITCAMandidentifying,foreachITCAMrule,itsoverlappingITCAMrules.WetraversethetrietoidentifytheoverlappingrulesinsteadoffollowingasimpleO(n2)algorithmofcomparingeveryrulewitheveryotherrule.This,alongwiththefactthatabout50%oftherulesendupintheITCAM(formostcasesasshownbyourexperiments)giveussignicantperformancebenetduringtheinitialassignmentofrulestotheITCAM,comparedtothecasewhenalltherulesarestoredinaSTCAM.ThealgorithmtodeterminetherulesthatoverlapagivenruleusestriebasedtraversalandisgiveninFigure 5-4 .Forsimplicity,thealgorithmisspeciedforthecasewhenruleshaveonlytwoelds-destinationandsourceprex.Itsextensiontoruleswithalargernumberofeldsisstraightforward.Givenarule,thealgorithmrstextractsthevaluesforthedifferenteldsfortherule,andtraversesthetriealongtheseprexpathsuntilalloverlappingrulesarefound.Foreachoverlappingrulefound,adirectededgeisaddedtotheprioritygraph.Theprioritygraphisadirectedacyclicgraphandblocknumbersmaybeassignedusinganiterativeprocessthatassignsthenextblocknumbertoallverticeswhosein-degreeiszeroandthensymbolicallyeliminatestheseverticesfromtheprioritygraph. 5.2.2UpdateAlgorithmsTherststepinprocessingaclassierupdateistoperformtheupdateoperationonthemulti-dimensionaltrie.Section 5.2.2.1 describeshowthisisdone.Inthesecondstep,existingrulesaremovedeitherinthesameTCAMorbetweenTCAMstopreservetheprioritiesandpropertiesofrulesandtheactualupdateisdone.ThisisdiscussedinSection 5.2.2.2 176

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Algorithm:ndOverlappingRules(ruleInstance)Inputs:ruleInstance:atrienoderepresentingaruleandstoringitsaction.Output:list:alistofrulesoverlappingwiththeinputrulegetdestinationprexDest,sourceprexSrcfromruleInstancenodeD=rootofdestinationtrie;for(i=0;i
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Function:Trie.insert(a,b,isLeaf)=Trie.insert(rule,action);Thisfunctioninsertsaruleanditsactionintothecontrol-planemulti-dimensionaltrie.Itreturnsthetrienodeawhichstoresthenewruleandalistbofnodesthatwereleavesindifferentdimensionspriortotheinsertionoftherule,andabooleanvariableisLeafwhichistrueiftheinsertedruleisstoredinaleafofleaves.Function:Trie.delete(a,b)=Trie.delete(rule);Thisfunctiondeletesarulefromthecontrolplanetrieandreturnsthetrienodeathatusedtostoretherulejustdeletedanda'snearestancestornodebthatwillbereachedupondeletingthetrienodes.Function:Trie.changea=Trie.change(rule,action);Thisfunctionchangestheactionassociatedwithaprexandreturnsthetrienodeathatstorestherule.Figure5-5. Tableofcontrol-planetriefunctions aregeneratedtodeletethemfromtheLTCAM.TheITCAMinsertsmusthappenrstsothataTCAMsearchreturnsconsistentresults.Similarly,whenaruleisdeletedfromthetrie,someexistingrulesmaynowbecomeleaves-of-leavesrules.ThenearestancestornodebreturnedbyTrie.deletemaybetraversedtoobtainrulesthatnowbecomeleaves-of-leavesrules.Fortheserulesitisfurthercheckediftheyarethehighestpriorityrulesinthesetofoverlappingrules.Iftheyare,thenthesecondrequirementformembershipinLTCAMgetssatisedandfortheserulesanumberofLTCAMinsertandITCAMdeleterequestsaregenerated.Thus,asaresultofupdatingthetrieanumberofITCAMandLTCAMinsertanddeleterequestsaregenerated.Theserequestsstillremaininthecontrol-planeandareprocessedfurtherasdescribedbelow,beforetheyareappliedtotheTCAMs. 5.2.2.2Othercontrol-planeoperationsforupdatesAtthisstage,theTCAMrequestsgeneratedasaresultofupdatingthemulti-dimensionaltriearefurtherprocessedandrunthroughthememorymanagementalgorithmsfortheITCAMandtheLTCAM.ThememorymanagementschemesfromDUOSmaybeusedhere.FortheITCAMofPC-DUOSweimplementedtheDLFS PLOscheme,asitsthe 178

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mostefcientschemeknowntousformovingfreeslotstoadesiredlocationinaTCAM.Also,foroperationsontheITCAM,weusedynamicallysizedarraysfortop,bot,AVandprevvariablesoftheDLFS PLOscheme,sinceruleblocksarerandomlyaddedanddeletedunlikesamelengthprexblocksinpacketforwardingthatresultsinamaximumof32blocksforIPv4.IntheDLFS PLOinitialruleplacementscheme,freeslotsarekeptintheregionbetweentwoblocks.Additionally,theremaybefreeslotswithinablock.SoalistoffreeslotsismaintainedforeachblockontheTCAM,withthelistbeingemptyinitially.Asrulesaredeletedfromablock,thefreedslotsareaddedtothelistforthatblock. ITCAM.insert.:ToinsertanewruleintheITCAM,rstly,theruleisaddedtotheprioritygraphandablocknumberisassignedtoit.Itmayberequiredtoadjusttheblocknumbersofexistingrulesoverlappingwiththenewrule.Next,DLFS PLOinsertanddeleterequestsaregeneratedfortheexistingrules,whoseblocknumbersarechanged,tomovethemtothecorrespondingruleblocks.Secondly,anewDLFS PLOinsertrequestisgeneratedforthenewruletoinsertitinthedesiredruleblock.Themethodtoassignandadjustblocknumbersduringupdatesisexplainedin[ 43 ].ADLFS PLOinsertordeleterequestwouldinvokeanumberofmoveoperationstocreateafreeslotataspecicblockortomanagefreedslots.Thirdly,toensurethatthesecondrequirementformembershipinLTCAMstillholdsforalltheLTCAMrules,thepriorityofthenewruleiscomparedwiththatoftheLTCAMrules.AlloverlappingLTCAMruleswithprioritylowerthanthatofthenewrule,mustbeinsertedintheITCAMusingtherstandsecondstepsaboveandthendeletedfromtheLTCAM.OverlappingLTCAMrulesareidentiedbytraversingthetrieusingthealgorithmofFigure 5-4 .Thus,attheendofthisstepanumberofITCAMinsertandLTCAMdeleterequestsaregenerated. ITCAM.delete.: 179

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ThestepsfordeletingarulefromtheITCAMareasfollows.Firstly,theruleisdeletedfromtheprioritygraph,followingwhichaDLFS PLOdeleterequestisgeneratedtodeletetherulefromtheITCAM.Secondly,everyITCAMrulethatnowbecomesleafofleavesandhasthehighestpriorityamongotherITCAMrulesthatoverlap,aremovedtotheLTCAM. LTCAM.insertandLTCAM.delete.:ThememorymanagementschemeforLTCAMisrelativelysimpleasalltherulesintheLTCAMareindependentsoanewrulecanbeinsertedanywhereintheTCAM.However,westillneedtolocateafreeslot.TheLTCAMmemorymanagementalgorithmofDUOScreatesalinkedlistofthefreeslots.Whenafreeslotisneeded,aslotisobtainedfromtheheadofthefreeslotlist.PC-DUOSusesthememorymanagementalgorithmforDUOSforitsLTCAM(seeChapter3).ForanLTCAMinsert,theAVvariableinthecontrolplaneisusedtoaccessanavailableslotattheheadofthefreeslotlistandaninsertrequestisgeneratedforthenewruleatthatslot.Similarly,todeletearulefromtheLTCAM,adeleterequestisgeneratedtosetthevalidbitfortheslotholdingtheruleto0andtosettheAVvariableonthecorrespondingSRAMwordandthenupdateAVtotheaddressoftheslotcurrentlybeingfreed. 5.3ExperimentalResultsWeevaluatedtheperformanceofPC-DUOSinupdatingpacketclassiersusingasetofsyntheticIPv4classiersgeneratedusingClassbench[ 50 ].Ourexperimentswererunonanx86Linuxboxwith64bit,1200MHzCPU.Table 5-1 showsthedetailsofthesedatasets.Therstcolumninthisgurepresentsthenamesoftheclassiers,thesecondcolumnshowstheseedlesinClassbenchfromwhichthesetestswerederived,thethirdcolumnshowsthenumberofrulesineachoftheclassiers,andcolumnsfourtosixgivethenumberofinsertanddeleteoperationsintheupdatetracesaswellasthetotalnumberofupdateoperationsforeachdataset.Weused7seedlesbased 180

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onaccesscontrollists(acl),rewalls(fw)andIPchains(ipc)togenerate7classiers.Eachruleconsistsoftheelds:sourceaddress,destinationaddress,sourceportrange,destinationportrange,protocol.Wecreatedanupdatetracefromtheclassiersbymarkingrulesforinsertion/deletionrandomly,andlaterremovingtherulesmarkedforinsertion.Thecorrespondinginsert,anddeleteoperationsareshufedandthenwrittentotheupdatele.Toupdatetheclassierinaconsistentfashion,changeoperationsareimplementedasasuccessionofinsertanddeletecommands,thatisinsertthenew,changedrulerstandthendeletetheexistingrulebeingchanged.Hence,inourupdatesimulationwedidnotaddchangeoperations. Table5-1. Syntheticclassiersandupdatetracesusedintheexperiments DataSetseed le#Rules#Inserts#Deletes test1acl1 seed300756930029700test2fw1 seed7989288007200test3ipc1 seed153383430014700test4acl2 seed539704500045000test5fw5 seed5571459005100test6acl4 seed3425450005000test7ipc1 seed5165940504950 ThesmoothnessandscopeparametersinClassBenchusedtogeneratethepacketclassiersareasfollows-smoothness:2;addressscope:0.5,applicationscope:-0.1.Fromthedescriptionoftheseparametersin[ 50 ],thevaluesusedensurethatthegeneratedlescontainafairamountofoverlappingrules.NotethatthenumberofoverlappingrulesdirectlyimpacttheupdateperformanceastheoverlappingruleshavetoberearrangedtomaintainpriorityorderingintheITCAM.Ifwelookattheprioritygraphsforthetests,wendthatthenumberoflevelsofnodesinthesegraphsisbetween27and73.Thisindicatesacloseresemblancetoreallifepacketclassiersintermsofthemaximumlengthofachainofoverlappingupdates[ 43 ].Wehaveruntwosetsofexperimentsonourdatasets.Therstsetusesprexexpansionofranges[ 18 43 ],whereasthesecondsetusesDIRPE[ 18 ]forrepresentingsourceanddestinationportranges.DIRPEisimplementedbyintroducingmulti-bittries 181

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forsourceanddestinationportranges.ForexperimentswithDIRPE,weassumethat36bitsareavailableforencodingeachportrangeinarule.Withthisassumption,weusestrides223333forbothsourceanddestinationportrangetriesinourexperiments,whichgiveusminimumexpansionoftherules.Thestridevalue223333indicatesthatforagivenportnumber(16bits),therootoftheportrangetriewillusethersttwobitstobranchtooneofitsfourpossiblechildnodesatlevel1.Eachnodeatlevel1usesthenexttwobitstobranchtooneamongitsfourpossiblechildnodesatlevel2.Anodeatthelevel2,ontheotherhand,usesthenext3bitstobranchtooneamongitseightpossiblechildnodesatthelevel3,andsoon.Thus,allthe16bits(2+2+3+3+3+3=16)areusedtotraversethetrieandarriveatthelastnode(atthe6thlevel)representingtheportnumber.WecompareourresultswiththosefromasingleTCAMsetup(STCAM)asiscommonlyusedtodayforpacketclassication.Inthissetup,allrulesareenteredintotheTCAMinpriorityorder.Theorderingisneededonlyforrulesthatoverlap.Iftworulesdonotoverlap,theirrelativeorderingdoesnotmatter.Weuseaprioritygraphforthewholesetofrulestotracktheblocknumbersoftherulesaswellastocomputeadjustmentstoblocknumbersasnewrulesareinserted.ThememorymanagementschemeDLFS PLOisusedfortheSTCAMtoallotafreeslotforruleinsertionortomanageafreedupslotfollowingruledeletion.WedonotcomparePC-DUOS'updateperformancewiththatoftheworkin[ 43 ],sincePC-DUOS'lookupperformanceisfarsuperiortotheworstcaseof[ 43 ],whichisatleast4timesslowerintheworstcase,onourdatasets(obtainedaslogarithmofthenumberofblocks).Tables 6-3 and 5-3 showthenumberofTCAMwritesandthetotalcomputationtimeforprocessingtheupdatesstartingfromthersttothelastupdateusingSTCAMandPC-DUOSarchitectures.TheprocessingtimeincludeseverythingexcepttheactualtimetoperformtheTCAMwrites.ThewriteratioisobtainedbydividingthenumberofwritesinSTCAM,bythenumberofwrites(sumofITCAMandLTCAMwrites)inPC-DUOS. 182

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Table5-2. NumberofTCAMwritesinPC-DUOSandSTCAMusingprexrepresentationscheme Data-Sets#RulesPC-DUOSSTCAMwriteratio #ITCAMwrites#LTCAMwritesTime(s)#writesTime(s) test13007513011317311037393332952.81test2798912014672209163526133023621.36test315338477025439829112695311241.24test45397098768115130136628733327631.2test5557118137954357369351442439642.18test634254320621241247735161851.65test75165231437108681161153353168801.57 Table5-3. NumberofTCAMwritesinPC-DUOSandSTCAMusingDIRPE[ 18 ] Data-Sets#RulesPC-DUOSSTCAMwriteratio #ITCAMwrites#LTCAMwritesTime(s)#writesTime(s) test1300751301115092832767524692.82test2798978628272389281262259351.19test31533844055446812651103467801.24test453970590678966092120556817251.38test555718265630702201229762427022.63test63425412391963931430171181.95test7516520727489389144952165348081.76 WeobservefromTables 6-3 and 5-3 thatthereisanimprovementinthewriteratiowithPC-DUOS.Theimprovementisintherange[1.2,2.81]fortheprexrepresentationschemeand[1.19,2.82]fortheDIRPEbasedscheme.Asignicantimprovementinupdateprocessingtimeisseenforthetest1,whichisfasterby329timesfortheprexrepresentationschemeand308timesfasterthattheSTCAMschemewhenDIRPEisused.Thetest1isderivedfromaseedleforaccesscontrollists.Itcontainsalargepercentageofveryspecicrulesforaccesscontrol.Forexample,followingisalessspecicrule-blockaccesstoaresourceforpacketsoriginatingfromanysourceaddressandanyportnumber.SuchrulesarestoredintheITCAMofPC-DUOSandfortest1,only2%oftheruleswereassignedtoITCAM.ITCAMupdatesaremoreCPUintensiveastheyrequireupdatingtheprioritygraphandinvokingthememorymanagementschemetocreateemptyslotsattherightplace.LTCAMupdates,onthe 183

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otherhand,arefastersincerulesareindependentandcanbeaddedtoanyfreeslotandhenceasimplermemorymanagementscheme.Thus,theperformanceofPC-DUOSdependsonthenumberofrulesintheITCAMandalsoonthenumberofrulesthatoverlapwithanewrulebeinginserted.Forexample,ifanewlyinsertedruleoverlapwithalargenumberofrules,itmayrequiretheoverlappingrulestobemovedtodifferentblockstomaintainpriorityrelationship.ThesetwofactorsareprimarilyresponsibleforthedifferencesinimprovementinprocessingtimebetweenPC-DUOSandSTCAM.ThevariedtotaltimenumbersfortheteststhatweseeonthecolumnsmarkedTime,areduetothetwofactorsaboveaswellasduetodifferencesinthetotalnumberofupdatesbeingprocessedforeachofthesetests.AssumingthenumberoflookuprequestssatisedbytheLTCAMisproportionaltothenumberofrulesstoredinit,wecanestimatetheimprovementinaveragelookuptimeonourdatasets.ForasinglelookupndingamatchintheLTCAM,theimprovementis50%[ 3 ].Thebestcaseinourdatasetistest1,whichhas98%oftherulesintheLTCAM.Theimprovementinaveragelookuptimeforthistestis49%.Theworstcaseistest2withDIRPE,whichcontainsonly40%oftherulesintheLTCAM,andforthistesttheimprovementinaveragelookuptimeis20%.AnewschemePC-DUOShasbeenproposed,inthischapter,forpacketclassierlookupandupdate.TwoTCAMsareusedwhichhavebeennamedasLTCAMandITCAM.PC-DUOSstoreshighpriorityindependentrulesintheLTCAM.TheremainingrulesarestoredintheITCAM.Duringlookupforhighestpriorityrulematching,bothITCAMandLTCAMaresearchedinparallel.SincetheLTCAMstoresindependentrules,atmostonerulemaymatchduringlookupintheLTCAMandapriorityencoderisnotneeded.IfamatchisfoundintheLTCAMduringlookup,itisguaranteedtobethehighestprioritymatchandthecorrespondingactioncanbereturnedimmediatelyyieldinga50%[ 3 ]improvementinTCAMsearchtime.Theaverageimprovementinlookuptimeisestimatedtobebetween20%to48%forthetestsinourdataset.The 184

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distributionofrulestothetwoTCAMsmakesupdatesfasterbyreducingthenumberofTCAMwritesbyupto2.82timesandreducingthecontrol-planeprocessingtimebyupto329times.Themaximumreductionincontrol-planeprocessingtimeisobservedforACLlists. 185

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CHAPTER6PC-DUOS+:ANENHANCEDDUAL-TCAMARCHITECTUREFORPACKETCLASSIFIERSPC-DUOS+isanenhancedversionofPC-DUOSwithimprovedupdatealgorithms.Thechapterisorganizedasfollows.Section 6.1 describesthePC-DUOS+schemeofstoringpacketclassiersinTCAMs.AnexperimentalevaluationofPC-DUOS+isdoneinSection 6.2 andweconcludeinSection??. 6.1PC-DUOS+:MethodologyPC-DUOS+usesthesameTCAMarchitectureasdescribedforPC-DUOSandrequiresthatREQ1andREQ2outlinedinSection 5.2 ofChapter5,aresatisedforlookupstoworkcorrectly. 6.1.1StoringRulesinTCAMsFigure 6-1 showstheoverallowofstoringrulesintheITCAMandtheLTCAM.Therstphaseinvolvescreatingaprioritygraph,inadditionto,amulti-dimensionaltriefortherulesintheclassier.ThisisfurtherdiscussedinSection 6.1.1.1 .ThesecondphaseinourmethodologyconsistsofidentifyingasetofhighestpriorityindependentrulesandstoringtheseintheLTCAM,whichisdiscussedinSection 6.1.1.2 .Inthethirdphase,theremainingrulesarestoredintheITCAMinpriorityorder.ThisisdiscussedinSection 6.1.1.3 .PC-DUOS+,differsfromPC-DUOS,inthewaytheselectionofrulesfortheLTCAMismade.PC-DUOSlterstheleavesofleavessetinamulti-dimensionaltrietokeeponlythehighestpriorityrulesamongalloverlappingrules.TherulesinthelteredleavesofleavessetisthenenteredintheLTCAM.PC-DUOS+,ontheotherhand,usesaprioritygraphtoselectrulesfortheLTCAM.Moreover,PC-DUOS+useenhancedalgorithmsforITCAMruleinsertionwhichrequirefewermovestorearrangerulesforprioritybasedadjustments. 186

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Figure6-1. FlowdiagramforstoringpacketclassiersinTCAMs 6.1.1.1RepresentingclassierrulesTheclassierrulesarerepresentedinaprioritygraphaswellasinamulti-dimensionaltrie.Aprioritygraphcontainsonevertexforeachruleintheclassier.Thereisadirectededgebetweentwoverticesiffthetworulesoverlapandthedirectionoftheedgeisfromthehighertothelowerpriorityrule.Tworulesoverlapiffthereexistsatleastonepacketthatmatchesboththerules. 6.1.1.2StoringrulesintheLTCAMForPC-DUOS+,weidentifyalargesetofindependentrulesastherulesintheverticesoftheprioritygraphwithin-degree0.ThissatisesREQ1.Further,theserulesarealsothehighestpriorityrulesamongallrulesthatoverlapwiththem.Thissatisesthesecondrequirement(REQ2)foralookuptoworkcorrectly.Hence,wechoosetoentertheserulesintotheLTCAM.AllremainingrulesareenteredintheITCAM. 6.1.1.3StoringrulesintheITCAMTherulestobestoredintheITCAM,areinitiallyassignedblocknumbersinthesamewayasdescribedforPC-DUOSinSection 5.2.1.3 187

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Intheblockassignmentscheme,rulesthatareassignedthesameblocknumberareindependentandhencegroupedtogetherinasingleblock.TheseblocksareenteredintheTCAMinincreasingorderoftheassignedblocknumbers.InourimplementationforPC-DUOS+,eachvertexvintheprioritygraphhasaeldv!hpriwhichstoresapseudopriorityassociatedwiththeblocknumberofthevertex.Whilev!hpriequalstheblocknumberofvinPC-DUOS,inPC-DUOS+,priorityMap(v!hpri)istheblocknumberforrulev.Whentheprioritygraphisconstructedfortheinitialclassier,v!hpriequalstheblocknumberofvandpriorityMapisanidentitymapping.However,asweinsertanddeleterules,v!hprimaynolongerequaltheblocknumberofv(infact,v!hprimaynotbeaninteger)andpriorityMapisnolongeranidentitymapping.Tobuildtheprioritygraph,werstiterateovertheclassierrulesandforeachrule,identifyallrulesthatoverlapwithit.Atrie-basedalgorithmtodeterminetherulesthatoverlapagivenruleispresentedinFigure 5-4 ofChapter5.Eventhoughintheworstcaseallthetrienodeshavetobeexploredforndingoverlappingrules(thishappens,forexample,whenruleInstanceistherootofthemulti-dimensionaltrieandthusrepresentsaclassierrulewithwild-cardedelds)thisapproachworkswellonaverageand,infact,itmakesthecomputationinPC-DUOS+(andalsoinPC-DUOS)scalableduringtheinitialsetupaswellaswhileprocessingtheupdates.Incontrast,thesimpleapproachofiteratingoveralltherulesoftheclassiertocompareoverlapsandpriorities,quicklybecomesaperformancebottleneckasthenumberofrulesintheclassierincreases. 6.1.2UpdateAlgorithmsWhenanupdaterequestisreceived,theprioritygraphandthemulti-dimensionaltrieareupdated.Section 6.1.2.1 describeshowthisisdone.NexttheexistingITCAMrulesthatoverlapwiththeruleinvolvedintheupdatearerearrangedtoensurethatthehighestpriorityrulesarestillmatchedaftertheupdateiscomplete.Rulesmayalsobe 188

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movedfromtheITCAMtotheLTCAMorviceversaasaresultoftheupdates.ThisstepisdiscussedinSection 6.1.2.2 6.1.2.1UpdatetheprioritygraphandthetrieThisistherststepintheupdateprocess.Themulti-dimensionaltrieisupdatedwiththehelpoffunctionsasdescribedinFigure 6-2 Function:Trie.insertTrie.insert(rule,action);Thisfunctioninsertsaruleanditsactionintothecontrol-planemulti-dimensionaltrie.Function:Trie.deleteTrie.delete(rule);Thisfunctiondeletesarulefromthecontrolplanetrie.Function:Trie.changeTrie.change(rule,action);Thisfunctionchangestheactionassociatedwithaprex.Figure6-2. Tableofcontrol-planetriefunctions Theprioritygraphisupdatednext.Iftheupdateisadeleterequest,thenthevertexfortheruletobedeleted(togetherwithincidentedges)isremovedfromtheprioritygraphandrulescorrespondingtoverticeswhosein-degreebecomes0aremovedfromtheITCAMtotheLTCAM.EachrulethatistobesomovedisrstinsertedintotheLTCAMandthendeletedfromtheITCAMusinginsert/deleteproceduresdescribedinSection 6.1.2.2 .Iftheupdateisaninsert,thenanewvertexisaddedtotheprioritygraph.Allrulesoverlappingwiththenewrulearefound,andanewedgeisaddedforeachoverlappingrule.OverlappingrulesareidentiedbytraversingthetrieusingthealgorithmofFigure 5-4 .Afteraddinganewvertexvtotheprioritygraph,v!hpriiscalculated.Ifvhasnoincomingedgesv!hpriissetto1andthenewruleinvisplacedintheLTCAM.Otherwise,visplacedintheITCAM.IfvisplacedintheITCAMthenv!hpriisseteitherbymovingv'sancestorsupwardoritsdescendantsdownwardorbymovingneitherdescendantsnorancestors.ThesethreepossibilitiesareshowninFigures 6-3 (c),(d)and(e).Figure 6-3 (a)depictsaportionoftheoriginalgraph.Thenumbernexttoeachvertexshowsthehprivalueon 189

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Figure6-3. Settinghprionanewvertexinaprioritygraph thatvertex.ThenewlyaddedvertexviscoloredblackinFigure 6-3 (b).InFigure 6-3 (c),v!hpriissetbasedonv'sparenthprisothatvwillbeplacedintheITCAMblockbelowthatofitsparent.Notethatthehpriofv'schildmustbeupdatedtooandthechildismovedoneblockdownward,thusavoidingvanditschildbeingplacedinthesameITCAMblock.Suchupdatespropagatetoalldescendants.InFigure 6-3 (d),v!hpriissetbasedonthehpriofv'schildsothatvwillbeplacedintheblockabovethatofitschild.Thehpriofv'sparentisupdatedsothattheparentismovedoneblockupwardandtheseupdatespropagatetoallancestors.Figure 6-3 (e)showsacasewhereanewblockisinsertedbetweentheparentblockandthechildblock,andthehpriassociated 190

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Algorithm:insertRule(v)Input:Rulestoredinvertexvintheprioritygraph.1maxP=max(parent!hpri)ofITCAMparentsofv;minC=min(child!hpri)ofchildrenofv;2//DefaultvaluesaremaxP:)]TJ /F23 10.909 Tf 8.48 0 Td[(1andminC:innity3childMoves=parentMoves=0;4if(!(maxP50)then//Moveancestorsupwards12targetBlock=BC)]TJ /F23 10.909 Tf 10.91 0 Td[(1;13if(BC)]TJ /F23 10.909 Tf 10.91 0 Td[(1==BPandparentMoves>50)targetBlock=newblockbetweenBPandBC.14endif15//FunctionreversePriorityMapreturnspseudo-prioritycorrespondingtotargetBlock.16v!hpri=reversePriorityMap(targetBlock);assignslotintargetBlockforv;17if(!(v!hpri>maxP))begin18sorttheparentverticesinadecreasingorderofhpri;19foreachparentofvif(!(v!hpri>parent!hpri))20if(parentisinITCAM)moveParentUp(parent);21endif22else//Movedescendantsdownwards23//Initially,allhighestpriorityrulesinITCAMhavehpri=2.So,targetBlockissettothatblock.24targetBlock=priorityMap(2);25if(vhasnoparentintheITCAM)then26if(thereexistsablockBC)]TJ /F23 10.909 Tf 10.91 0 Td[(1)targetBlock=BC)]TJ /F23 10.909 Tf 10.91 0 Td[(1;27elseif(childMoves>50)targetBlock=newblockontopofBC.28else29targetBlock=BP+1;30if(BP+1==BCandchildMoves>50)targetBlock=newblockbetweenBPandBC.31endif32v!hpri=reversePriorityMap(targetBlock);33assignslotintargetBlockforv;34if(!(v!hpri
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Algorithm:moveChildDown(child)Input:Rulestoredinvertex`child'intheprioritygraph.mP=ndmax(parent!hpri)fromallparentsofchildmC=ndmin(child!hpri)fromallchildrenofchildif(mP
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casehappenswheneachvertexisconnectedtoeveryothervertex.Inthatcase,tondtheminimumandthemaximumhpri(thersttwolinesofFigures 6-4 and 6-5 )thealgorithmsmusttouchallthevertices.Calculatingthenumberofmovesisacomputeintensivetasktoo,withthesamecomplexityofO(NL)sincethesamealgorithmsareused,withoutactuallymovingtherules.So,toavoidaperformancebottleneck,weperformthesecalculationsselectively.Further,amaxLimitissetsothatassoonasthenumberofmovesexceedsmaxLimitwestopfurthercalculations.TheowchartinFigure 6-6 (a)showsanunoptimizeddecisiondiagramthatcausessignicantperformancedegradation.Inthiscase,theactualnumberofmovesiscomputedforboththecaseswhenthedescendantsandtheancestorsaremoved.Whicheverdirectionresultsinalowernumberofmoves,theprioritiesareadjustedforthatdirection.TheowchartintheFigure 6-6 (b)showsanoptimizeddecisiondiagram,thatbreaksuptheprocessintothreestagesandfocusesonrelativeinsteadofactualnumberofmoves.Intherststageofthisow,wecalculatechildMoveswhichisthenumberofmovesneededtoshiftthedescendantsdownward,withmaxLimitsetto500.IfchildMovesislessthan50,wegoaheadandmovethedescendantsdownwardswithoutcalculatingparentMoves,whichisthenumberofmovesrequiredtoshifttheancestorsupward.However,ifittakesmorethan50childMoves,thenweareatthesecondstagewheretheparentMovesarecalculatedwithmaxLimitsetto(childMoves+100),whichcouldpotentiallybeanumberupto600.IfparentMovesislessthanchildMovesatthisstage,thenwemovetheancestorsupwards.IfparentMovesismorethan500thenweareatthethirdstagewheretheexactnumberofchildMovesisrstcalculated(bysettingmaxLimittoinnity)andthenarelativenumberofparentMovesiscalculated(bysettingmaxLimitto(childMoves+100)).DescendantsaremoveddownwardsifchildMovesissmaller,otherwiseancestorsaremovedupwards.Thisowgivesanacceptableupdate 193

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AInefcientow BEfcientowFigure6-6. Decisiondiagramsforpriorityadjustmentofdescendantsvs.ancestors performanceonourdatasets,sinceveryfewupdatesinvolveover500movesineitherorboththedirections.WeuseanotheroptimizationintheITCAMruleplacementstrategy,whereanewblockisinsertedintotheTCAMbetweentwoexistingblocksasshowninFigure 6-3 (e)andonlines13and30ofFigure 6-4 .IfthemaximumblocknumberoftheparentsofvisBandtheminimumblocknumberofitschildrenisB+1,theninsteadofmovingallchildreninblockB+1toB+2orallparentsinblockBtoB)]TJ /F4 11.955 Tf 12.72 0 Td[(1,anewblockiscreatedintheITCAMbetweentheblocksBandB+1andv!hpriissettotheaverageofthehpri-softhetwoblocks(i.e.(hpri of(B)+hpri of(B+1))=2).Thenewruleforvisthenaddedtothenewblock.IfthenewruleistobeaddedontopofthetopmostITCAMblockasonline27ofFigure 6-4 ,thenv!hpriissetto(1+hpri of(B)=2).Recallthattheverticeswithin-degree0areassignedanblocknumber1.So,weadd1inthisexpressiontoensurethatnohpribecomeslessthan1.Additionofanewblockmust 194

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bedonejudiciously,sinceitrequiresanextramovewhilebringinginafreeslottoaparticularblockBwhenthenewlyinsertedblockisbetweenthefreespacepoolandB.So,weaddnewblocksonlyifthenumberofmoveswascalculatedtobeover50.Figure 6-3 (e)showsthatv!hpriforthenewvertexvissetto3.5.Anewblockisaddedbetweentheparentandthechildblocksinthiscase.Forconsistentupdates[ 25 54 ],iftheverticesaretobemoveddownwards,thenthemovesmaybeexecutedinincreasingorderofprioritystartingfromthelowestpriorityruleandafterallthedescendantsaremoved,thenewruleisadded.Iftheverticesaremovedupwards,thenthemovesmaybeexecutedindecreasingorderofpriority,startingfromthehighestpriorityrule.Afteralltheancestorsaremoved,thenewruleisadded.Lines40-43ofFigure 6-4 ensurethatnodesaremovedtotheirassignedslotsinthereverseorderofvisitingthem.Thus,thenodelastvisitedforupdatinghpriisthersttobemovedtoitsassignedslot.Thispreservesupdateconsistencyforboththecaseswhenthedescendantsaremoveddownwardsandtheparentsupwards.Thenewruleisaddedattheend(Line44). 6.1.2.2UpdatingtheTCAMsTCAMupdatesaregeneratedafterupdatingtheprioritygraph.RulesmaybemovedfromtheITCAMtotheLTCAMorviceversaortheymaybemovedwithintheITCAMforrearrangementofoverlappingrules.ToinsertormovearuleinaTCAMweneedafreeslotatanappropriatelocation.Thisslotcanbeobtainedefcientlyusingmemorymanagementalgorithms.Inparticular,thememorymanagementschemesfromDUOSmaybeusedhere.FortheITCAMofPC-DUOS+,weimplementedtheDLFS PLOscheme,justlikewedidforPC-DUOS.FortheLTCAMtoo,PC-DUOSandPC-DUOS+usethesamememorymanagementalgorithms.Sincetheblocksgrowbothways,upaswellasdown,PC-DUOS+hasamodiedinitialruleplacementpolicyasshowninFigure 6-7 where25%ofthefreeslots(representedbywhiteblocks)areplacedonthetopoftheTCAM(thatis,covering 195

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Figure6-7. InitialITCAMlayout thelowestaddresses)andanother25%arekeptatthebottomoftheTCAM(coveringthehighestaddresses).Theremaining50%ofthefreeslotsaredistributedtotheregionbetweentheblocksinproportiontothenumberofrulesinablock. ITCAM.insert.:ToinsertanewruleintheITCAM,afreeslotisrstmadeavailableatthedesiredblock.Afreeslotmaybepresentinthesameblockinwhichcasenomovesareneededtogetitfromthefreeslotlistoftheblock.Ifthereisnofreeslotintheblock,thenafreeslotmaybeobtainedfromtheinter-blockregiononthetoporthebottomoftheblock.Nomovesareneededinthiscasetoo.Ifthereisnofreeslotintheinter-blockregionadjacenttotheblock,thenafreeslotismovedfromthenearestneighboringblockwhereitsavailable.ToinsertanewblockbetweentwoblocksintheITCAM,itisrstcheckedifthereisafreeslotbetweenthetopandbottomblocks.Iftherearefreeslotsintheregionbetweenthetopandthebottomblocks,thentheruleinthenewblockisinsertedthereinsuchawaythattherearesomefreeslotsaboveandbelowthenewblock.Otherwise,freeslotsforthenewblockaremovedinfromthenearestneighboringblockthathasfreeslots. 196

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ITCAM.delete.:Afterdeletingthevertexcorrespondingtotheruleintheprioritygraph,thevalidbitonthecorrespondingTCAMslotissetto0.DLFS PLOfreesuptheblockiftheruledeletedisthelastruleintheblock.Otherwise,thefreedslotisprependedtotheheadofthelistoffreeslotsintheblock. ITCAM.change.:Supposethespeciedchangeiswithrespecttotheeldsofarule,thensuchachangeisimplementedasaninsertfollowedbyadelete.Theinsertaddsthechangedruletothesameblockastheoldrule,whilethedeleteremovestheoldrulefromthisblock.Ifthechangeisinthepriorityoftherule,then,werevisitalltheincomingandoutgoingedgesofthecorrespondingvertexvintheprioritygraphandreversetheedgesappropriatelytomaintaintheedgedirectionfromthehighertothelowerpriorityrule.Thentheblocknumberisfreshlycalculatedforv,andtheruleismovedtoablockatahigheraddress(iftheprioritywaslowered)ortoablockataloweraddress(ifthepriorityoftherulewasincreased)intheITCAM.Ifthevertexvdoesnothaveanyincomingedgefollowingtheupdate,itismovedtotheLTCAM. LTCAM.insert,LTCAM.deleteandLTCAM.change.:ToinsertanewruleintheLTCAM,afreeslotisobtainedfromtheheadoftheLTCAMfreeslotlist.IfaruleisdeletedfromtheLTCAM,thenthevalidbitoftheslotissetto0andthefreedupslotisprependedtotheheadofthefreeslotlist.Forincorporatingachangedrule,ifthechangeiswithrespecttotheeldsofarule,thenthechangedruleissimplyinsertedintheLTCAMandtheoldruledeleted.Ifthechangeisinthepriorityofaruleinsuchawaythatthecorrespondingvertexnowhasanincomingedge,thentheruleismovedtotheITCAM.Otherwise,iftherulecontinuestobethehighestpriorityruleamongalloverlappingrulesevenafterthechange,thennothingneedstobedone. 197

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6.2ExperimentalResultsTheexperimentalsetupisrstdescribedinSection 6.2.1 .WeanalyzetheresultsbasedontwoperspectivesimprovementinlookupperformanceandimprovementinupdateperformanceinSections 6.2.2 and 6.2.2.1 respectively. 6.2.1Setup 6.2.2LookupPerformance APercentageofrulesintheLTCAM BPercentageofimprovementinlookuptimeFigure6-8. PercentageofrulesstoredintheLTCAMandpercentageimprovementinlookuptimecomparedtoSTCAMarchitecture Recallthatduringalookup,ifamatchisfoundinLTCAMofPC-DUOS+thenthecorrespondingactionisreturnedfaster.HavingalargenumberofrulesintheLTCAMmakestheprobabilityofndingamatchintheLTCAM,higher.Figure 6-8 (b)shows 198

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theimprovementinaveragelookuptime.Sincethetests1(acl1)and9(acl5)had99%oftheirrulesintheLTCAM,almostallthelookupsfoundahitintheLTCAM,andconsequently,theimprovementinaveragelookuptimeonthesetestswasalmost50%.Ontheotherhand,thetestfw1hadleasthitsintheLTCAM,andshowedanimprovementofabout19%intheaveragelookuptime.Figure 6-1 presentsthedetailsonthenumberofrulesintheITCAMandLTCAMandthepercentageimprovementinlookupperformance.Therstthreecolumnsgivethedatasetindex,itsnameandthenumberofrulesrespectively.ThefourthandfthcolumnsgivethenumberofrulesenteredintheITCAMandLTCAM,respectively.Thesixthandseventhcolumnsgive,respectively,thenumberoflookupsperformedandthepercentageimprovementinaveragelookuptime.ThepercentageimprovementvaluesforlookupperformancestatisticallydependonthenumberofrulesintheLTCAM.Thustheactualimprovement,obtainedbasedonthedistributionoflookupsinatraceservedbytheITCAMandtheLTCAM,maydeviatefromtheexpectedimprovement.Forexample,fromFigures 6-8 (a)and(b),test13showsbetterimprovementinlookuptimecomparedtotest12,eventhoughboththetestscontainaboutthesamepercentageofrulesintheLTCAM. Table6-1. NumberofrulesinITCAMandLTCAMofPC-DUOS+andimprovementinlookuptimerelativetoSTCAM IndexDataset#Rules#ITCAM#LTCAM#Lookups%Improvement 1acl1300753052973112030149.62fw179894885306810385719.23ipc11533835041183410761840.64acl25397088754509510794042.65fw555712689279610543030.86acl43425458822837210310441.17ipc25165147636899813638.78acl31974567371300710285131.49acl519492260192099746049.410fw21666847391192910000840.611fw31684156881098610379433.012fw4128825004787810326620.213ipc32000080271197310016334.9 199

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Figure6-9. NumberofTCAMwriteswithrespecttoPC-DUOS+ Figure6-10. RuntimenormalizedwithrespecttoPC-DUOS+ 6.2.2.1UpdateperformanceFigure 6-9 showsthenumberofTCAMwritesneededtoprocessthetestupdatesequencebyPC-DUOS+,PC-DUOSandSTCAM,normalizedwithrespecttothatofPC-DUOS+.AnoticeableimprovementinthenumberofwritesisobservedwithrespecttoSTCAMforalmostallthetestsexceptfortests9(acl5)and13(ipc3).Test8(acl3)requiresupto3.72timesmorewritesusinganSTCAMcomparedtoPC-DUOS+, 200

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whiletest6(acl4)requiresupto1.5timesthenumberofwritesusingPC-DUOSversusPC-DUOS+.Figure 6-10 showsthetimetakentoprocesstheupdatesbyPC-DUOS+,PC-DUOSandSTCAM.ThesetimeshavebeennormalizedwithrespecttoPC-DUOS+.Tests1(acl1)and9(acl5)showthemaximumimprovementinruntimecomparedtoSTCAM,theimprovementbeing247and188timesrespectively.Thisisrelatedtothefactthatover99%oftherulesinthesetestsareenteredintheLTCAMofPC-DUOS+.TheLTCAMoffersafastandlight-weightupdatemechanismcomparedtotheITCAM.NotethattheITCAMhasasimilarupdatemechanismasSTCAM.Infact,fromFigures 6-10 and 6-8 (a),weseethattheimprovementinruntimeiscloselyrelatedtothenumberofrulesthatareintheLTCAM.Figure 6-10 showsthatcomparedtoPC-DUOS,thereisanimprovementintheruntimetoo,foralltestsexcepttest1(acl1). Figure6-11. Ratioofedgestoverticesofgraph FromFigure 6-9 weobservethattests9(acl5)and13(ipc3)needalmostsimilarnumberofwritesinallthethreesetups,namely,PC-DUOS+,PC-DUOSandSTCAM.Theprioritygraphfortest9(acl5)hasaverysmallnumberofedges.Infact,theratiooftheedgestotheverticesforthisgraphisonly0.018(Figure 6-11 ),andthelengthofthemaximumchainisjust3(Figure 6-12 ).Thus,STCAMneedsasinglewriteformostoftheinserts.Theprioritygraphfortest13(ipc3),ontheotherhand,isawell-structured 201

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Figure6-12. Maximumchainlengthingraphbeforeprocessingupdates AInitialgraph BAnewruleisaddedFigure6-13. Asmallgraphrepresentingtestipc3 Figure6-14. Percentageofupdatesthatrequire1write,3and10writes 202

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graphwiththreedistincttypesofvertices.Thersttypeisforruleswithveryspecicsourceanddestinationprex,whicharespeciedupto32bitsformostcases.Thesecondtypeisforruleswithveryspecicsourceaddressprex,butgenericdestinationprex(0or1bitlong),andthethirdtypeisforruleswithveryspecicdestinationandgenericsourceaddressprex.Asaresult,theverticesofaparticulartypearesparselyconnectedtoeachotherastheyfailtomatchonthesourceordestinationprexeldthatisspeciedupto32bits.Figure 6-13 (a)representsasmallexampleofsuchagraph.Heretherulesatthetoplevelareplacedinblocknumber1,therulesatthenextlevelareplacedinblocknumber2andtherulesonthelastlevelareplacedinblocknumber3intheTCAM.Nowsupposeaninsertrequestforanewruleisreceived.Figure 6-13 (b)showsanewvertexcorrespondingtotherule,andanupdatedprioritygraph.Ascanbeseen,thehighestblocknumberforaparentis1,andthelowestblocknumberforachildofthenewvertexis3,whichmakesthenewvertexaperfecttinblocknumber2.Thegraphforipc3isclosetothisexample,withonly6blocksand100%oftherulesareplacedintherightblockwithjustoneTCAMwrite.Thefactthat100%oftherulesneedjust1TCAMwritecanbeseenfromFigure 6-14 ,whichshowsthepercentageofrulesrequiring1TCAMwriteandthepercentageofrulesrequiringatmost3and10TCAMwrites.Thus,ipc3producessimilarresultsforPC-DUOS+,PC-DUOSaswellastheSTCAM.Itmaybenoticedthatacommonfeatureoftestsacl5andipc3isthatbothofthemhaveasmallmaximumchainlength.Table 6-2 givestheaverageandtheworstcaseTCAMwritesforPC-DUOS+andSTCAM.TheaveragewritesforPC-DUOS+arelowerthanthecorrespondingnumbersforSTCAM.TheworstcasewritesforPC-DUOS+islowerthanthoseforSTCAMforalltestsexcepttest10(fw2).ThenumberofTCAMwritesintheworstcaseforPC-DUOS+isquitehigh,eventhoughweobservedthatmorethan99%oftherulesrequireatmost10writes. 203

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Table6-2. AverageandworstcaseTCAMwritesforPC-DUOS+ IndexDataSetPC-DUOS+STCAM #Averagewrites#Worstcasewrites#Averagewrites#Worstcasewrites 1acl11.18313.31532fw12.0739713.5120143ipc11.5219002.2539454acl21.5642742.2861945fw51.651675.84260206acl41.434184.398217ipc22.0451525.27172858acl31.926517.13109469acl51.12101.1241110fw21.7191.98911fw31.5526031.871469312fw42.8319626.97699613ipc31.011.056 Table6-3. TotalTCAMwritesinPC-DUOS+,PC-DUOSandSTCAM IndexData-SetsPC-DUOS+PC-DUOSSTCAM #TCAMwritesTime(s)#TCAMwritesTime(s)#TCAMwritesTime(s) 1acl111641810116393832767524692fw1767923851058669281262259353ipc174059128887362651103467804acl213939719314872792120556817255fw582044969113358201229762427026acl41435782203031430171187ipc2201082557296663144952165348088acl31173616117984743494979acl5281040.88273661.22809016710fw251250161514027925940648811fw37751676792955105793426109812fw457822766995836213943437813ipc3300002173000028731647416 Table 6-3 showstheactualnumberofTCAMwritesforinsertingordeletingrulesinthedifferentdatasetsandthetimetakentoperformtheseupdatesinPC-DUOS+,PC-DUOSandSTCAM.PC-DUOS+,whichisanenhancementofPC-DUOS[ 28 ]andanextensionofDUOS[ 26 ],isproposedinthischapterforpacketclassierlookupandupdate.TwoTCAMsnamedLTCAMandITCAMareused.PC-DUOS+storesthehighestpriority 204

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independentrulesintheLTCAM.TheremainingrulesarestoredintheITCAM.Duringlookupforhighestpriorityrulematching,boththeITCAMandtheLTCAMaresearchedinparallel.SincetheLTCAMstoresindependentrules,atmostonerulemaymatchduringlookupintheLTCAMandapriorityencoderisnotneeded.IfamatchisfoundintheLTCAMduringlookup,itisguaranteedtobethehighestprioritymatchandthecorrespondingactioncanbereturnedimmediatelyyieldingupto50%improvementinTCAMsearchtimerelativetoSTCAM.Theaverageimprovementinlookuptimeisfoundtobebetween19%to49%forthetestsinourdataset.ThedistributionofrulestothetwoTCAMsmakesupdatesfasterbyreducingtheaveragenumberofTCAMwritesbyupto3.72times(foracl3)andreducingthecontrol-planeprocessingtimebyupto247times(foracl1).Themaximumreductionincontrol-planeprocessingtimeisobservedfortheACLtests. 205

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CHAPTER7PC-TRIO:ANINDEXEDTCAMARCHITECTUREFORPACKETCLASSIFIERSPC-TRIOisanindexed,tripleTCAMarchitecturethatsupportsfasterandlowpowerlookups,inadditionto,efcientincrementalupdates.Thechapterisorganizedasfollows.Section 7.1 presentsbackgroundandrelatedworkintheeldofpacketclassication.Section 7.1.1 describesthePC-TRIOarchitectureandassociatedalgorithmsandSection 7.4 presentsexperimentalresults.WeconcludeinSection??. 7.1BackgroundandRelatedWorkWewilldescribetheresearchonTCAMbasedpacketclassiersinSection 7.1.1 ,anddiscussthemainproblemsinhavinganindexedTCAMarchitectureforpacketclassiersinSection 7.1.2 andtheninSection 7.1.3 showhowtoovercometheseproblems. 7.1.1PacketClassiersTheworkonpacketclassiersinTCAMs,targetsthreemainproblems:portrangeexpansion,powerconsumptionandupdates.Thersttwoproblemsareinter-relatedasreducingportrangeexpansionalsoreducesthepowerconsumptioninaTCAM.Variousapproacheshavebeenproposedintheliteraturetoalleviatetherangeexpansionproblem.Theschemesin[ 8 11 18 20 22 33 ]encodetherangesandstoremodiedrulesintheTCAM.Asapacketarrives,anencodedsearchkeyiscreatedfromthepacketheadereldsusingtheencodingalgorithmandtheTCAMissearchedusingtheencodedsearchkey.Spitznageletal.[ 44 ]proposedenhancementstotheTCAMhardwaretoincluderangecomparison.WithsuchanenhancedTCAMcircuit,eachruleoccupiesasingleentryintheTCAM.CompressingpacketclassiersbyremovingredundanciesisaneffectivestrategytoreduceTCAMpowerconsumption.Theapproachesin[ 13 14 19 24 49 ]presentalgorithmsthattransformaninputclassiertoanequivalentsmallerclassier.Thesealgorithmsquitenaturallycontainportrangeexpansions.Whiletheseapproaches 206

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bringaboutsignicantreductionsinclassiersize,theyaregenerallynotsuitableforincrementalupdates,sincearuletobedeleted,forinstance,maynotbepresentinthetransformedclassier.SongandTurner[ 43 ]describeanalgorithmforfastincrementallterupdates.Anexplicitpriorityvalue(whichwecallblocknumberinthispaper)iscalculatedforeachrulebasedontherule'simplicitpriority,whichisderivedfromthepositionoftheruleintheclassier,andtheimplicitpriorityvaluesoftheoverlappingrules.TheblocknumbersocomputedisstoredalongwiththeruleintheTCAMusingunusedTCAMbits.AnewrulemaybeplacedanywhereintheTCAM.ThisrelievestheTCAMofmovingexistingrulestomaintainpriorityordering.Instead,duringlookup,multiplelookupsperpacketareperformedtoidentifythebestmatchingrule.Mishra,SahniandSeetharamaninPC-DUOS[ 28 ]andPC-DUOS+[ 29 ]usedualTCAMsforrepresentationandincrementalupdateofclassiers. 7.1.2ProblemsinStoringaClassierinanIndexedTCAMWehaveseenhowpacketforwardingtablesarestoredinindexedTCAMsassociatedwithwideSRAMsinChapter2,therebyresultinginsignicantdecreaseinlookuppower.ItisexpectedthatstoringpacketclassiersinindexedTCAMswithwideSRAMswouldyieldpowersavingsinasimilarmanner.However,therearetwoproblemsinmappingapacketclassiertoanindexedTCAMarchitecturewithwideSRAMs.RecallthatduringaTCAMlookup,thecontentsintheSRAMwordcorrespondingtotherstmatchingruleisreturned.AconstraintonthesizeofawideSRAMword(andalsothatonthesizeofaTCAMbucket),makesitimpossibletoguaranteethattherstmatchingwordwillcontainthehighestpriorityrulematchingthepacket.Forexample,considertheclassierwith4rulesinFigure 7-1 ,whereeachrulehastwoelds-adestination,andasource.TheclassierismappedtotheindexedTCAMinFigure 7-2 .ThedataTCAMhastwobucketsandtheindexTCAMusesbitsfromthedestinationprexofeachrule,toindexintothebucketsofthedataTCAM.Inthis 207

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Figure7-1. Anexampleclassier Figure7-2. ClassierrulesstoredinaindexedTCAM setup,assumingthataddressesare4bits,supposeapacketarriveswithdestinationandsourceaddressesas0000and0101respectively.ThebestmatchingrulefromFigure 7-2 isthesecondruleontherstbucketofthedataTCAMandA3isreturnedastheactiontobeappliedonthepacket.However,fromthetableinFigure 7-1 ,A2isthedesiredaction.ThusiftherearemultiplematchingrulesonaTCAM,thenallthecorrespondingSRAMwordsmustbeprocessedtoreturntheactionofthematchingrulewiththehighestpriority,andthiswilltakemorethanoneTCAMclockcycletonishasearch.Thisistherstproblem.ThesecondproblemisaboutthecoveringrulesofawideSRAMwordoradataTCAMbucket.Acoveringprex[ 21 55 ],inthecontextofpacketforwardingtables,isadefaultprexforaTCAMbucket.ThepresenceofcoveringprexesinaTCAMbucketmakeseverysearchintheTCAMbucketreturnatleastonematch.Inapacketclassier,coveringrulessimilarlyguaranteethatasearchonaTCAMbucketmatchesatleastonerule.ThefourthruleinFigure 7-1 isacoveringruleandhenceenteredinboththeTCAMbucketsinFigure 7-2 .ApacketclassiermayhaveseveralcoveringrulesforaTCAMbucket.Further,differentTCAMbucketsmayneedthesamecovering 208

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ruleswhichmakesitnecessarytostoreasinglerulemultipletimesintheTCAM,onceineveryTCAMbucketforwhichitisacoveringrule.HavingarulereplicatedassuchintheTCAM,isunacceptablespeciallyconsideringthefactthatthereplicatedrulesthemselvesmayundergorangeexpansion. 7.1.3OvercomingtheProblemsThedualTCAMarchitecturepresentedforPC-DUOSinChapter5andPC-DUOS+inChapter6,aswellasthePC-TRIOarchitecturepresentedinthischapter,makesitpossibletogetaroundboththeproblemsmentionedaboutusingwideSRAMsandindexTCAMswithaTCAMforpacketclassiers.TheLTCAM(LeafTCAM)ofPC-DUOSstoresindependentrules.Tworulesareindependentiffnopacketmatchesboththerules.StoringasetofindependentrulesinaTCAM,ensuresthatatmostoneTCAMentrymatchesduringasearchandwesimplyprocessthecorrespondingSRAMword.TheITCAM(InteriorTCAM)ofPC-DUOSstoresalltheremainingruleswhichincludesthecoveringrules.DuringalookupbothTCAMsaresearchedinparallel,andincasethereisnomatchontheLTCAM,theITCAMreturnstheactionforthematchingrulewiththehighestpriority.NotethattheLTCAMofPC-DUOSisasuitablecandidateforaugmentingwithwideSRAMwordsandanindexTCAM,sinceatmostoneTCAMentrymatchesduringasearch.TherulesintheITCAM,ontheotherhand,arenotindependentandhencemultipleTCAMentrieswillmatchduringasearch.Thus,theITCAMisnotasuitablecandidateforusingwithitawideSRAMoranindexTCAM. 7.2PC-TRIOThePC-TRIOarchitectureispresentedinSection 7.2.1 .ThealgorithmsforstoringandupdatingtheTCAMsarediscussedinSections 7.2.2 and 7.2.3 7.2.1TheArchitectureFigure 7-3 illustratesthePC-TRIOarchitecture.ItprimarilyconsistsofthreeTCAMs,theITCAM(InteriorTCAM),theLTCAM1(LeafTCAM)andtheLTCAM2.ThecorrespondingassociatedSRAMsare:ISRAM,LSRAM1andLSRAM2,respectively. 209

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Figure7-3. PC-TRIOArchitecture TheLTCAMsstoreindependentrules,henceboththeTCAMsareaugmentedwithwideSRAMsandindexTCAMs.ILTCAM1andILTCAM2aretheindexTCAMsforLTCAM1andLTCAM2,respectively.TheindexTCAMsalsohavewideassociatedSRAMs,namely,ILSRAM1andILSRAM2.SincetherulesstoredinthetwoLTCAMsandthetwoILTCAMsareindependent,atmostonerule(ineachLTCAMandILTCAM)willmatchduringasearch.SotheseTCAMsdonotneedapriorityencoder.ApriorityencoderassistsinresolvingmultipleTCAMmatchesandisusedwiththeITCAMtoaccesstheISRAMwordcorrespondingtothehighestprioritymatchingruleintheITCAM.AlookupinPC-TRIOispipelinedwith6stagesmarkedA-FinFigure 7-3 .IntherststageA,theILTCAMsaresearched.TheILSRAMsareaccessed,usingtheaddressofthematchingILTCAM1andILTCAM2entriesinstageB.ThematchingwideILSRAMwordsareprocessedinstageCtoobtainthecorrespondingbucketindexfor 210

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LTCAM1andLTCAM2.InstageD,thebucketindexessoobtainedareusedtosearchthecorrespondingbucketsintheLTCAMs.TheITCAMisalsosearchedinthisstage.InthenextstageE,theISRAM,andtheLSRAMsareaccessedusingtheaddressesofthematchingTCAMentries.InthenalstageF,thecontentsofthewideLSRAMwordsareprocessedandthebestactionischosenfromtheatmostthreeactionsreturnedbytheISRAM,LSRAM1andLSRAM2bycomparingtheprioritiesofthecorrespondingrules. 7.2.2StoringRulesinTCAMsThereareseveralstepsofprocessingapacketclassiertostoretherulesintheTCAMs.Therststepistocreateaprioritygraphandmulti-dimensionaltriesfortherulesintheclassier.ThisisfurtherdiscussedinSection 7.2.2.1 .Inthesecondandthirdsteps,theLTCAM1andLTCAM2subsystemsarepopulatedasdiscussedinSections 7.2.2.2 and 7.2.2.3 ,respectively.ThefourthstepistostoretheremainingrulesintheITCAMinpriorityorder,whichisdiscussedinSection 7.2.2.4 7.2.2.1RepresentingclassierrulesAprioritygraphiscreatedrstwhichcontainsonevertexforeachruleintheclassier.Nextwecreateamulti-dimensionaltrie,Trie1,whereeachdimensionrepresentsoneeldofarule.Initially,Trie1isthree-dimensional,withthethreeelds,source,destinationandprotocolofaclassierruleusedforthispurpose.Theeldsappearinthefollowingorderinthetrie:.Weassumethatthedestinationandsourceeldsaswellastheprotocoleldoftheltersarespeciedasprexes.So,thesearerepresentedinatrieinthestandardwaywiththeleftchildofanoderepresentinga0andtherightchilda1.Aclassierrule,alongwithitssourceanddestinationportranges,isstoredontheprotocolnodethatisarrivedataftertraversingthetriestartingfromitsroot,usingrstthedestination,thenthesourceandnallytheprotocoleldsoftherule.WeidentifyasetofindependentrulesasdescribedinSection 7.2.2.2 .Alltheremainingrulesareusedtocreateanothermulti-dimensionaltrie,Trie2,inwhichelds 211

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Algorithm:ndNode(node)Inputs:node:atrienode,initiallysettotherootofamulti-dimensionaltrie.Output:aleavesofleavessetofprotocolnodesstoringclassierrules.foreachchildiofnodendNode(node!child[i]);endforif(nodeisaleaf)//trueifnodehasnoleftorrightchild.if(nodecontainsrootofatrie)ndNode(node!trie!root);else//nodebelongstotrieforthelasteld(protocol)appendprotocolnodetoleavesofleavessetendifendifFigure7-4. Selectingprotocolnodesforleavesofleavesset Figure7-5. DataencodinginawideSRAMword inalterruleappearintheorder.NotethatthesourceanddestinationtriesareswitchedinTrie2,withrespecttoTrie1.So,whiledestinationtrieistheoutermosttrieinTrie1,inTrie2,sourceistheoutermosttrie. 7.2.2.2StoringrulesintheLTCAM1TheprocessofstoringrulesintheLTCAM1subsystemisdescribedinvesubsectionsbelow.First,wediscusshowindependentrulesareidentied,next,theformatofstoringinformationinawideLSRAMwordisdiscussed,thenwedescribethecreationofLTCAM1entriesusingtheprocessofcarving.Nextwedescribepartialportrangeexpansionthatmaybenecessary,andnally,thecreationofILTCAM1andILSRAM1entries. IdentifyingIndependentRules.TondalargesetofindependentrulesinPC-TRIO,werstcreatealeavesofleavessetofprotocolnodesinamulti-dimensionaltrieusingthealgorithminFigure 7-4 .Thenodesbelongingtotheleavesofleavesset 212

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inTrie1areobtainedbytraversingthemulti-dimensionaltriefromtheroottotheleavesofthedestinationtrieandthenfromtheseleavesintotheirattachedsourcetrieandthenfromtheleavesofthesourcetrieintotheleavesoftheirattachedinnermosttriefortheprotocoleld.Inthesecondstep,foreachprotocolnodeintheleavesofleavesset,weidentifyasetofindependentrulesstoredinthatprotocolnodebybuildingasmallprioritygraphwithrulesonlyinthatprotocolnode.Verticesintheprioritygraphwithin-degree0compriseasetofindependentrules.Acollectionofindependentrulesfromallprotocolnodesintheleavesofleavesset,givesustherulestobeenteredintheLTCAM1. WideSRAMWordFormat.OncetherulestobestoredinLTCAM1areidentied,subtriesofthemulti-dimensionaltriearecarvedandrulesintheprotocolnodesinasubtriearestoredinaLSRAM1word.Inparticular,foreachruleinaprotocolnodewestoretherule'ssourceanddestinationportranges,blocknumber,andaction.Wealsostorethesufxofaprotocolnode,whichisthepathfromtherootofthecarvedsubtrietotheprotocolnode.Figure 7-5 showsaformatforencodingthisinformationinawideSRAMword.Theeldsinthisformataredescribedbrieyasfollows: 1. Matchstartposition:Thiseldspeciesthepositionsoftherstbitinthesource,destinationandprotocoleldsofapacketheaderstartingfromwhichsufxesofprotocolnodesintheSRAMwordmustbematched. 2. Count:ThisisthenumberofprotocolnodesintheleavesofleavessetstoredintheSRAMword. 3. len(Si):ThiseldspeciesthelengthofthesufxforprotocolnodeiintheSRAMword. 4. Ci:Thisgivesthenumberofclassierrulesstoredforprotocolnodei. 5. Dataj:Data1,,DataNgivedetailsoftheNrulesinthecarvedsubtrie.Therulesforprotocolnode1ofthissubtriecomerst,followedbythoseofthesecondprotocolnodeandsoon.Datajgivestheblocknumber,action,sourceanddestinationportrangetypesforthejthclassierrule. 6. Si:Thiseldstoresthesufxforprotocolnodei. 213

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7. Portranges:StorestheportrangesfortheNrules.Therearethreetypesofrangesfoundinaclassier.Theseare:awholerange([0-65535]),arangewiththesamestartandendpoint,andarangewithdifferentstartandendpoints.TheportrangetypesubeldintheDataeldrepresentsthesethreetypesofrangesusingtwobits.TosavespaceinaSRAMword,awholerangeisneverenteredandonlyoneportnumberisenteredforarangewiththesamestartandendpoints. CreatingLTCAM1entries.AtrieiscarvedintosubtriestoassignrulestothewideSRAMwords.TheTrie1iscarvedusingthecarvingheuristicvisit postorderofDUO(seeChapter3)thathasbeenenhancedformulti-dimensionaltries.Thiscarvingheuristiccreatesindependent(disjoint)entriesfortheLTCAM1.Thepathstartingfromtherootof Figure7-6. Nodesinasourcetrieisbeingcarved. Trie1totherootofthesubtriedenesanLTCAM1entry.Figure 7-6 showsaportionofasourcetriethathangsoffadestinationtrie,wherecarvingtakesplaceatnodes00,01,and11ofthesourcetrie.Thepathfromtheroottothenodeofthedestinationtriefromwhichthesourcetriehangsoffis1101.Thus,aftercarvingthenodeat00onthesourcetrie,theLTCAM1entryis110100??????,assumingaddressesandprotocoleldsarerepresentedusing4bitseach.Similarly,thetwootherLTCAM1entriesinthisexampleare110101??????and110111??????.Figure 7-6 alsoshowsasizeassignment(inbits)onthethreenodeswherecarvingtakesplace.Thesesizesarecomputedforallthetrienodesevenbeforethecarvingalgorithmisinvoked.ThesizeassignedtoatrienoderepresentsthenumberofLSRAM1bitsneededtostorealltheclassier 214

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rules(forLTCAM1)inasubtrierootedatthatnode.Forexample,forasubtrierootedatthesourcenode01,thenumberofbitsneededtostoretheaction,blocknumber,portrangesofclassierrulesandsufxesofprotocolnodespresentinthissubtrie,is450.IftheactualwidthofaSRAMwordis,say,500bits,thentherulesinthissubtriewilltinanSRAMwordandwemaycarveatthesourcenode01.AcorrespondingLSRAM1entryisconstructedfortheclassierrulesintheformatgivenbyFigure 7-5 .Thecarvingheuristiccarvesanodenonthetriewhenanyofthefollowingtwoconditionsistrue.Here,pistheparentofninthetrie. C1) ThesizeassignedtonislessthanthewidthofaSRAMword,butthatassignedtopismorethanthethewidthofaSRAMword. C2) Adescendantofpwascarved.ThesecondconditionensuresthatthecarvingcreatesdisjointTCAMentries(seeChapter3). Partialportrangeexpansion.:ItispossiblethattheSRAMbitsneededtostoretheclassierrulesforLTCAM1onaprotocolnodeexceedsthecapacityofawideSRAMword.ThiscaseisshowninFigure 7-7 (a)wheretheblacknodeisaprotocolnodeintheleavesofleavessetandthesizeassignedtoitis600bits.SupposethewidthoftheSRAMwordis500bits.ThentoavoidoverowinganSRAMword,wemustsplittherulesintheprotocolnode,intotwoormoreSRAMwords.InsteadofreplicatingtheLTCAM1entryforeachofthesplitSRAMwords,wecreateasourceportrangetrieasshowninFigure 7-7 (b),andcarvenodesonthistrietocreateindependentLTCAM1entries.Eachnodeinthesourceporttrieinheritsthoseclassierrules(forLTCAM1)fromtheprotocolnodethathavetheirsourceportrangeoverlapwiththeportrangerepresentedbythetrienode.Thusmultiplecopiesofarulemaybecreated,oneforeachtrienodewithportrangeoverlappingthesourceportrangeoftherule.Afterthesourceporttrieiscreated,thecarvingheuristicresumesitstraversalalongthesourceporttrie,andcarvessourceportnodesiftheysatisfyeitherconditionC1,orC2.In 215

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Aapro-tocolnode BanewsourceporttrieisattachedtotheprotocolnodeFigure7-7. Prexesinforwardingtablebeforeandafterapplyingupdates theexampleofFigure 7-7 (b),twoLTCAM1entriesarecreated,oneeachforthetwocarvednodes.TheseLTCAM1entriesdifferontherstbitonthesourceporteld,withoneentryhavinga0whiletheotherhavinga1.IftheclassierrulesinaleafnodeofthesourceporttrieoverowsanSRAMword,thenadestinationporttrieiscreatedforthedestinationportrangesonrulesofthatleafnode,andthecarvingheuristicndsappropriatenodestocarveonthedestinationporttrie.ThesourceanddestinationporttriesarethuscreatedinPC-TRIOonlywhennecessary,andthen,tominimizetherangeexpansionproblemweusemulti-bittriesforstoringtheportranges.Thebitsusedtoarriveatanodeinthemulti-bittriedeneanLTCAM1entry. CreatingILSRAM1andILTCAM1entries.AftercarvingTrie1tocreatesufxesforenteringintoLSRAM1,wecarveTrie1againasecondtime,tocreatesubtriesthatcontainLTCAM1entries.AllLTCAM1entriesinasubtrieareenteredinaLTCAM1bucket.Thus,attheendofthiscarvingstep,theLTCAM1entriesarepartitionedintobuckets.Thebitsfromtherootofthemulti-dimensionaltrietoacarvednodedenesanindexthatpointstoanLTCAM1bucket.AfterpartitioningtheLTCAM1intobuckets,Trie1iscarvedathirdandnaltime.Thistime,acarvedsubtriecontainsindexestoLTCAM1buckets.Sufxesoftheseindexes,alongwiththecorrespondingLTCAM1bucketindexes,arestoredinthe 216

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ILSRAM1,andthebitsonpathfromtherootoftheTrie1toacarvednodedeneanILTCAM1entry. 7.2.2.3StoringrulesinLTCAM2ThisisdoneexactlyasforLTCAM1,byprocessingtherulesstoredinTrie2.Inparticular,Trie2undergoescarvinginasimilarmannerasdescribedforTrie1andtheLTCAM2systemispopulated.Theremainingrules,i.e.rulesthatarestoredneitherintheLTCAM1norintheLTCAM2subsystem,arestoredintheITCAM. 7.2.2.4StoringrulesintheITCAMTheITCAMdoesnothaveawideISRAM,hence,aruletobeenteredintheITCAM,musthaveitsportrangestoredintheITCAMitself.AnISRAMwordcontainstheactionandblocknumberofaclassierrulestoredinthecorrespondingITCAMentry.WeuseDIRPEtoencodetheseportrangesontheITCAM.DIRPEissuitableforincrementalupdates,unlikedatabasedependentrangeencodingschemes.However,iffastincrementalupdatesarenotneeded,thenanyrangeencodingschememaybechosenfortheITCAM. 7.2.3IncrementalUpdatesWhenanupdaterequestisreceived,theprioritygraphisupdatedasdescribedinSection 7.2.3.1 .ThenTrie1and,ifnecessary,Trie2areupdatedasdescribedinSection 7.2.3.2 .Asthetriesareupdated,itmaybenecessarytocarvethetriesatdifferenttrienodes.ThisisdiscussedinSection 7.2.3.3 .UpdatingtheTCAMsisdiscussedinSection 7.2.3.4 7.2.3.1UpdatingtheprioritygraphToinsertanewrule,therststepistostoretheruleintheprioritygraph.Anewvertexviscreatedfortherule.Theexistingrulesthatoverlapwithvareidentiedandnewedgesareformedbetweenvandtheverticesofoverlappingrules,withdirectionsoftheedgessetfromthehighertothelowerpriorityrules.Then,ablocknumberisassignedtov,whichisonemorethanthemaximumblocknumberofthenodesfrom 217

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whichvhasanincomingedge.Iftheblocknumberofachildvertexisnotmorethanthatassignedtov,thechild'sblocknumberisupdatedsothatitisatleastonemorethantheblocknumberofv.IftherulercorrespondingtothischildvertexisstoredinITCAM,then,rmustbemovedtotheITCAMblockrepresentedbyitsupdatedblocknumber,andtheISRAMentryforrisalsoupdatedwiththechangedblocknumber.Ontheotherhand,ifrisinoneoftheLTCAMs,then,wesimplychanger'sblocknumberinthecorrespondingLSRAMentry.Updatestoblocknumbersarepropagatedtoallverticesreachablefromv.Toprocessadeleterequest,thevertexcorrespondingtotherulealongwiththeincidentedgesisremovedfromtheprioritygraph. 7.2.3.2UpdatingthetriesToinsertanewrule,theruleisrstaddedtoTrie1.Iftheruleisanindependentruleinaprotocolnodeintheleavesofleavesset,thenitisinsertedintheLTCAM1.Otherwise,theruleisaddedtoTrie2.IftheruleisanindependentruleinaprotocolnodeintheleavesofleavessetforTrie2,thentheruleisinsertedintheLTCAM2.Otherwise,theruleisinsertedintheITCAM.IfanewruleisstoredintheLTCAM1ortheLTCAM2,thensomeoftheexistingrulesinthatTCAMmaynolongerbeindependent.Ifsuchanon-independentruleexistsintheLTCAM1,thenthatruleisaddedtotheTrie2andiftherulecanbeaddedtotheLTCAM2itismovedfromtheLTCAM1tothetheLTCAM2.Otherwise,theruleismovedfromtheLTCAM1totheITCAM.Similarly,anewruleaddedtotheLTCAM2maycausesomeoftheexistingLTCAM2rulestobemovedtotheITCAM.Todeletearule,theruleisdeletedfromTrie1andalsofromTrie2ifitwasstoredinTrie2.TheruleisthendeletedfromtheTCAMthatstorestherule. 7.2.3.3UpdatingthetriecarvingWenowdiscussthedynamicsofcreationandmergingofLSRAMwordswhenanewruleisaddedoranexistingruleisdeleted.BothTrie1andTrie2containnodes 218

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thatwerecarvedtocreateTCAMandSRAMentries.WedescribehowtheseentrieschangeforTrie1.TheprocessissimilarforTrie2.WhenaruleisaddedtoTrie1atnodet,ifthereisanancestoraoft,wherecarvingwasdonetocreateawideLSRAM1words,andifthereisspaceinstoplacetheaction,blocknumber,portrangesofthenewrule,then,thenewruleisplacedins.Ifthereisnospaceins,thenthecontentsofsaresplit,bycarvingdescendantsofatocreatetwoormoreLTCAM1entries.If,ontheotherhand,tdoesnothaveanancestora,thenoneofthetwothingsbelowmayhappen.Ifthereisanancestorboft,suchthatbhasatleastonecarveddescendantandthesubtrierootedatbneedsfewerSRAMbitsthanthewidthofaSRAMwordtorepresenttheclassierrules,thenbiscarved.Asaresult,thenewruleisstoredwithsomeexistingrulesinanewSRAMword.Notethattheexistingrules,haveadditionalsufxbitsinthenewlycreatedSRAMwordandoldLTCAM1entriesfortheexistingrulesaredeleted.Ifnosuchbexists,anewLTCAM1entryiscreatedbycarvingatt.ThecorrespondingLSRAM1wordcontainsonlythenewlyaddedrule.WhenaruleinanLTCAM1isdeleted,thentheruleisrstremovedfromtheLSRAM1word.IftheLSRAM1wordbecomesempty,thenthecorrespondingLTCAM1wordisdeleted.Otherwise,ifthecontentsoftheLSRAM1wordcanbemergedwithanotherLSRAM1wordthenanewLTCAM1entryiscreatedwhiletheLTCAM1entriesforthemergedwordsaredeleted.ThealgorithmstomergeandsplitbucketsontheLTCAMsaresimilarlybasedonmanipulatingthecarvinginTrie1andTrie2. 7.2.3.4UpdatingtheTCAMsToinsertormovearuleinaTCAMweneedafreeslotatanappropriatelocationintheTCAM.ThisslotcanbeobtainedefcientlyusingmemorymanagementalgorithmsdevelopedforTCAMs.Inparticular,thememorymanagementschemesfromDUO(seeChapter3)maybeused.FortheITCAMofPC-TRIO,weimplementedtheDLFS PLOscheme,asitsthemostefcientschemeknowntousformovingfreeslotstoadesired 219

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locationinaTCAM.IntheDLFS PLOinitialruleplacementscheme,freeslotsarekeptintheregionbetweentwoblocks.Additionally,theremaybefreeslotswithinablock.SoalistoffreeslotsismaintainedforeachblockontheTCAM,withthelistbeingemptyinitially.Asrulesaredeletedfromablock,thefreedslotsareaddedtothelistforthatblock.Thus,DLFS PLOrequiresnomovesformostofthetimetogetorreturnafreeslot.ThememorymanagementschemefortheLTCAMofDUOisrelativelysimpleasalltherulesintheLTCAMareindependentsoanewrulemaybeinsertedanywhereintheTCAM.However,westillneedtolocateafreeslot.TheLTCAMmemorymanagementalgorithmofDUOcreatesalinkedlistofthefreeslots.Whenafreeslotisneeded,aslotisobtainedfromtheheadofthefreeslotlist.PC-TRIOusesthememorymanagementalgorithminDUOforitsLTCAM1andLTCAM2. 7.3DifferencesamongPC-DUOS,PC-DUOS+,PC-DUOS+WandPC-TRIOPC-DUOS,PC-DUOS+andPC-TRIOdifferfromeachotherinthewaytheselectionofrulesfortheLTCAMismade.PC-DUOSlterstheleavesofleavessetinamulti-dimensionaltrietokeeponlythehighestpriorityrulesamongalloverlappingrules.TherulesinthelteredleavesofleavessetisthenenteredintheLTCAM.PC-DUOS+,ontheotherhand,usesaprioritygraphtoselectrulesfortheLTCAM.PC-TRIOselectstheleafrulesforanLTCAMusingatwo-stepprocess.Therststepistoidentifytheleavesofleavessetinathreedimensionaltrieandthesecondstepistoidentifyindependentrulesfromtherulesstoredonthenodesoftheleavesofleavesset.PC-DUOS+andPC-TRIOalsouseenhancedalgorithmsforITCAMruleinsertionwhichrequirefewermovestorearrangerulesforprioritybasedadjustments.WenotethatthemethodologyusedinthischapterforPC-TRIOmaybeusedtoaddindexTCAMsandwideSRAMstoPC-DUOS+toarriveatanewarchitecturePC-DUOS+W.AlthoughPC-DUOSmaybesimilarlyextendedtoobtainPC-DUOSW,wedonotconsiderthisextensionhereasPC-DUOS+issuperiortoPC-DUOSaswas 220

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Figure7-8. Differencesamongthearchitectures foundfromourexperiments,theresultsforwhicharepresentedinChapter6.Figure 7-8 highlightsthedifferencesamongPC-DUOS,PC-DUOS+,PC-DUOS+WandPC-TRIO.Unliketheotherarchitectures,PC-TRIOdoesnotguaranteethattherulesintheLTCAMsareofthehighestpriorityamongalloverlappingrules.Thus,PC-TRIOmustwaitforanITCAMlookuptocompleteeveniftherearematchingrulesintheLTCAMs.AlthoughtheruleassignmentalgorithmsforPC-TRIOmaybemodiedsothattheLTCAMrulesarethehighestpriorityamongalloverlappingrules(andthusavoidhavingtowaitforanITCAMlookuptocompleteincaseswhenamatchisfoundinanLTCAM),doingsoretardstheperformanceofPC-TRIOtothepointwhereitofferslittleornopowerandlookuptimebenetoverPC-DUOS+W. 7.4ExperimentalResultsInthissection,wecomparePC-TRIO,withPC-DUOS+WandPC-DUOS+[ 29 ].WerstgivethesetupusedbyusfortheexperimentsinSection 7.4.1 andthendescribeourdatasetsinSection 7.4.2 .FinallywepresentourresultsinSection 7.4.3 7.4.1SetupWeprogrammedtheruleassignment,triecarvingandupdateprocessingalgorithmsofPC-TRIOusingC++.WedesignedacircuitforprocessingwideSRAM 221

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wordsusingVerilogandsynthesizeditusingSynopsysDesignCompilertoobtainpower,areaandgatecountestimates.WeusedCACTI[ 30 ]andaTCAMpowerandtimingmodel[ 1 ]toestimatethepowerconsumptionandsearchtimefortheSRAMsandtheTCAMsrespectively.Theprocesstechnologyusedintheexperimentsis70nmandthevoltageis1.12V.ItisassumedthattheTCAMsarebeingoperatedat360MHz[ 36 ].TheTCAMandSRAMwordsizesusedareconsistentforallthearchitecturesusedinthecomparison.Thewordsizeis144bitsfortheTCAMs.ForSRAMswehavedifferentwordsizesdependingupontheTCAMstheyareusedwith.TheISRAMwordsofallthearchitectures,aswellastheLSRAMwordsofPC-DUOS+,are32bitswide.TheLSRAM1andLSRAM2wordsofPC-TRIOandtheLSRAMwordsofPC-DUOS+Ware512bits,whiletheILSRAMsare144bitswide.ThebucketsizeforLTCAMsinPC-TRIOandPC-DUOS+Wissetto65TCAMentries.PC-DUOS+usesDIRPE[ 18 ]toencodeportranges.TheclassierrulesstoredintheITCAMsofPC-TRIOandPC-DUOS+WalsouseDIRPEtoencodeportranges.SincetheTCAMwordsizeissetto144bits,weassumethat36bitsareavailableforencodingeachportrangeinarule.Withthisassumption,weusethestrides223333asthesegiveusminimumexpansionoftherules[ 18 28 ]. 7.4.2DatasetsWeusedtwosetsofbenchmarksderivedfromClassBench[ 50 ].Therstsetofbenchmarksconsistsof12datasetseachcontainingabout100,000classierrulesandisgeneratedfromseedlesinClassBench.ThisdatasetisusedtocomparethenumberofTCAMentries,power,lookupperformanceandspacerequirementsofPC-TRIO,PC-DUOS+WandPC-DUOS+[ 29 ].Thesecondsetofbenchmarkswasreusedfrom[ 29 ].Thereare13datasetsherewhichareusedtocompareincrementalupdateperformanceofPC-TRIO,withPC-DUOS+[ 29 ]andPC-DUOS+W. 222

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Table7-1. NumberofTCAMentries,ITCAMentriesandTCAMpowerandlookuptimeinPC-DUOS+,PC-DUOS+W,PC-TRIO IndexDataset#RulesPC-DUOS+PC-DUOS+WPC-TRIO Entries#ITCAMWattsTime(ns)Entries#ITCAMWattsTime(ns)Entries#ITCAMWattsTime(ns) 1acl199309117033379362624.39211463790.230.50210851820.191.00 2acl27429810185719421311122.3937491194216.3530.3636593184396.04149.43 3acl39946813124330859401640.4752632308599.4780.492682310170.402.19 4acl49933412732025189391730.4649912251897.9845.953403465472.3224.12 5acl5981171053751535322072.163293215350.530.413499322090.774.98 6fw18935614208591473432466.72984259147327.922318.822661048641.6015.01 7fw29605512924927084391543.7643146270848.3086.772219614940.533.18 8fw38088511773139199361007.04512283919911.99215.212626974792.3830.09 9fw484056211403116149643182.0313150511614935.462139.212761748941.6015.16 10fw5840131119895565034930.94655985565017.00615.492236134541.159.02 11ipc19919811215422165341288.0241920221656.8245.11238945670.261.40 12ipc21000001000003013330784.6947247301339.23113.772019500.090.75 223

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7.4.3Results 7.4.3.1NumberofTCAMentriesUsingwideSRAMwordstostoreportionsofclassierrules,reducesthenumberofTCAMentries.Table 7-1 givestheresultsofstoringourdatasetsfromthesecondbenchmark,inthethreearchitectures.Therst,secondandthirdcolumnsshowtheindex,name,andthenumberofclassierrules,respectively,ofadataset.Thefourth,fthandsixthandseventhcolumnsgiveforPC-DUOS+,thetotalnumberofTCAMentries,thenumberofITCAMentries,theTCAMpowerandlookuptime,respectively.Similarly,theeighth,ninth,tenthandeleventhcolumnsgivethecorrespondingnumbersforPC-DUOS+WandtheremainingfourcolumnsgivethoseforPC-TRIO.Figure 7-9 (a)givestheTCAMcompactionratioofthethreearchitectures,obtainedbydividingthenumberofTCAMentriesforeachdatasetbythenumberofrulesintheclassier.PC-DUOS+doesnotusewideSRAMs,hencethereisnocompaction,instead,thereisexpansiontohandleportranges.Thus,thecompactionratioforPC-DUOS+isatleast1foreverydataset.ThecompactionachievedbyPC-TRIOismorethanthatofPC-DUOS+Wforalmostallthedatasets.Thisisbecause,PC-TRIOhasfewerITCAMentriesandthereforestoresmorerulesinwideSRAMwords.Foracl5,PC-DUOS+WidentiedmoreindependentrulescomparedtoPC-TRIO.ThealgorithmtoidentifyindependentrulesisthesameforPC-DUOS+WandPC-DUOS+whichresultsinidenticalITCAMentriesforthesetwoarchitectures.NoclassierrulesintheLTCAMsofPC-DUOS+WandPC-TRIOneededpartialportrangeexpansion(Section 7.2.2.2 ).SoallLTCAMentriesinPC-DUOS+WandPC-TRIOwereatmost72bits. 7.4.3.2PowerTable 7-1 givestheTCAMpowerconsumptionduringalookup,whileFigure 7-9 (b)givesthenormalizedtotalpowerobtainedforeachdatasetbydividingthetotalTCAMandSRAMpowerinanarchitecturebythatofPC-TRIOduringalookup.Thevertical 224

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Figure7-9. Comparisonofcompactionratio,totalpower,lookuptimeandarea axisisscaledlogarithmicallyandbasedat1.PC-TRIOuseslesspowerforalldatasetsexceptacl5.TheaverageimprovementinpowerwithPC-TRIOis96%relativetoPC-DUOS+,and65%relativetoPC-DUOS+W.TheaverageimprovementinpowerwithPC-DUOS+Wis71%,relativetoPC-DUOS+.ThemaximumimprovementwithPC-TRIOisobservedforipc2(99%)andtheminimumforacl2(80%),comparedtoPC-DUOS+.ThemaximumimprovementwithPC-DUOS+Wisobservedforacl1(99%)andtheminimumforfw1(35%),comparedtoPC-DUOS+.ThemaximumimprovementwithPC-TRIOisobservedforipc2(98%)andtheminimumforacl1(2%),comparedtoPC-DUOS+W. 7.4.3.3LookupperformanceFigure 7-9 (c)givestheaveragelookuptime,normalizedwithrespecttothatofPC-TRIO.TCAMsearchtimeisproportionaltothenumberofTCAMentries.Hence,PC-DUOS+requiresthemaximumtime. 225

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PC-DUOS+WisfasterthanPC-TRIOfortheACLtestsacl1,acl2andacl5.Forthesedatasets,thenumberofITCAMentriesinPC-DUOS+WandPC-TRIO(columns9and13ofTable 7-1 )arecomparable.Thus,theITCAMsearchtimesarecomparable,asarethenumberoflookupsservedbytheITCAMs.This,coupledwiththefactthatITCAMsearchesareslower,givePC-DUOS+Wanimmediateadvantagesinceit,unlikePC-TRIO,abortsanITCAMsearchafterndingamatchintheLTCAM.However,forthesethreetests,thelookuptimesusingPC-TRIOarequitereasonable(column15ofTable 7-1 ).FortheotherdatasetsPC-TRIOhasfewerrulesintheITCAM,whichmakesPC-TRIOlookupsfastereventhoughithastowaitforITCAMsearchtonish.TheaverageimprovementinlookuptimewithPC-TRIOandPC-DUOS+W(relativetoPC-DUOS+)are98%and76%,respectively.TheaverageimprovementinlookuptimewithPC-TRIO(relativetoPC-DUOS+W)is68%.ThemaximumimprovementusingPC-TRIOratherthanPC-DUOS+isobservedforacl1(99.96%)andtheminimumforacl2(86.6%).ThemaximumimprovementusingPC-DUOS+WratherthenPC-DUOS+isobservedforacl1(99.98%)andtheminimumforfw1(5%).ThemaximumimprovementwithPC-TRIOratherthanPC-DUOS+Wisobservedfortestsfw1,fw4andipc2(99%)andtheminimumforacl4(47%). 7.4.3.4SpacerequirementsWeobtainedSRAMareafromCACTIresultsandestimatedTCAMareausingthesametechniqueasusedinPETCAM[ 27 ],whereareaofasinglecellismultipliedbythenumberofcellsandthenadjustedforwiringoverhead.Figure 7-9 (d)givesthetotalareaneededfortheTCAMsandassociatedSRAMs.Thetotalareaiscomparableforthethreearchitectures.PC-TRIOandPC-DUOS+WhavelowerTCAMarea(duetofewerTCAMentries)andhigherSRAMarea(duetowiderSRAMwords)thanPC-DUOS+. 7.4.3.5UpdateperformanceFigure 7-10 showstheaveragenumberofTCAMwritesusedperupdateonthedatasetsfromtherstbenchmark.PC-TRIOneedscomparablenumberofwrites 226

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Figure7-10. TCAMwrites asPC-DUOS+andhencesupportsefcientandconsistentincrementalupdates.PC-DUOS+WneedsmorewritesthanPC-TRIOtopreservethepropertythatallrulesstoredintheLTCAMhavethehighestprioritycomparedtooverlappingrules. 7.4.3.6CharacteristicsofthelogicthatprocesseswideSRAMwordsAcircuitdesignedtoprocessthecontentsofawideLSRAMwordwassynthesizedusinga0.18mlibrary[ 47 48 ]anditwasfoundfoundthatthedesignsuccessfullymetthetimingconstraintswitha500MHzclock.TheresultsarepresentedintheTable 7-2 Table7-2. Timingandpowerresultsforadditionalhardware ProcessTime(ns)Throughput(Msps)Voltage(V)Power(mW)GateCount 0.18m25001.861.1359724 Thethroughputisrepresentedintermsofmillionsearchespersecond(Msps).AnexampleofaTCAMwithaspeedof143MHz(effectively,143Msps)isfoundin[ 31 ],using0.13mtechnology.Itisexpectedthatthedelayoverheadandthroughputofourdesignwillimproveonusinga0.13mlibrary.Thus,ourdesigncanoperateatthesamespeedasthatofaTCAM.WepresentedinthischapteranindexedTCAMarchitecture,PC-TRIO,forpacketclassiers.ThemethodstoaddindexingandwideSRAMswereappliedonPC-DUOS+toobtainanotherindexedTCAMarchitecturePC-DUOS+W.ThesetwoarchitectureswerethencomparedwithPC-DUOS+.BothPC-TRIOandPC-DUOS+Wmaybe 227

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updatedincrementally.TheaverageimprovementinTCAMpowerandlookuptimeusingPC-TRIOwere96%and98%,respectively,whilethatusingPC-DUOS+Wwere71%and76%,respectively,relativetoPC-DUOS+.PC-DUOS+WperformedbetterontheACLdatasetscomparedtotheothertypesofclassiers.Therewas86%reductioninTCAMpower,and98%reductioninlookuptimewithPC-DUOS+WontheACLdatasetsonanaveragecomparedtoPC-DUOS+.EventhoughPC-DUOS+WlookupperformancewasbetterthanthatofPC-TRIOonthreeACLtests,PC-TRIOlookupperformancewasquitereasonableandinfact,usingPC-TRIO,therewasareductioninTCAMpowerby94%andlookuptimeby97%onanaveragefortheACLtests,comparedtoPC-DUOS+.So,werecommendPC-TRIOforpacketclassiers. 228

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CHAPTER8CONCLUSIONThefocusofthisdissertationisenablinglowpowerTCAMsforpacketforwardingandclassication,withefcientupdatingmechanism.Thecontributionsaresummarizedasfollows:PETCAM,apowerefcientTCAMarchitecturethatcanbeusedtostorepacketforwardingtables.ItwasobservedthatPETCAMsignicantlyreducebothTCAMpowerandmemoryrequirements,overexistingTCAMschemesforstoringforwardingtables.PETCAMisupdatedusingbatchupdatemechanism.DUO,adualTCAMarchitectureforforwardingtables.TheadvantagesofDUOincludelowpowerlookups,inadditionto,efcientincrementalupdatesthatcanbeappliedwithoutlockingtheTCAMsfromlookups.CONSIST,aconsistentTCAMupdatingschemeusefulwhentheupdatestobeappliedincrementally,arriveinacluster.Thelookupshappeningwhiletheupdatesarebeingappliedwillreturnappropriatenexthop(forforwardingtableslookup)oraction(forclassierlookup)whenCONSISTisused.Further,thesequenceofupdates,builtusingourstrategy,isfreefromredundanciesinupdateoperationsandproducesanearminimalincreaseintablesize.PC-DUOS,adualTCAMarchitectureforpacketclassiersthathelptoimplementfasterupdatesandlookupmechanisms.PC-DUOS+,anenhancementoverPC-DUOS,andleadstoevenfasterupdatestopacketclassiersPC-TRIO,anindexedtripleTCAMarchitectureforpacketclassiersthatleadtoultralowpowerlookupsandiseasytoupdateincrementally. 229

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BIOGRAPHICALSKETCH TaniaBanerjeeMishrareceivedherPh.D.fromComputerandInformationScienceandEngineeringDepartmentattheUniversityofFloridain2012,underthesupervisionofProf.SartajSahni.Herresearchinterestsaredatastructuresandalgorithms,networkingalgorithmsandVLSICAD.TaniareceivedIntegratedM.Sc.inMathematicsandM.TechinComputerSciencefromtheIndianInstituteofTechnology,Kharagpur,in1996and1998respectively.ShewaswithInterraSystemsbetween1998and2003andwithSequenceDesign(nowacquiredbyApacheDesignSolutions)between2003and2006workingonpowerestimationandoptimizationtechniquesforRTLdesigns. 234