<%BANNER%>

Impact of Uniaxial Stress on Silicon Diodes and Metal-Oxide-Semiconductor-Field-Effect-Transistors under Radiation

Permanent Link: http://ufdc.ufl.edu/UFE0043566/00001

Material Information

Title: Impact of Uniaxial Stress on Silicon Diodes and Metal-Oxide-Semiconductor-Field-Effect-Transistors under Radiation
Physical Description: 1 online resource (105 p.)
Language: english
Creator: Park, Hyunwoo
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2011

Subjects

Subjects / Keywords: dielectrics -- effects -- events -- high-k -- radiation -- single -- strained-si -- stress -- total-ionizing-dose -- transients -- uniaxial
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Uniaxial strained-silicon (Si) has emerged as a leading technique for enhancing transistor performance for sub-100 nm logic technology for use in commercial and consumer electronics. Traditionally, semiconductor chips for military and space applications are fabricated using expensive radiation hardened technology. There is significant interest in the radiation research community towards integrating commercial CMOS technology for use in radiation environments to reduce costs. Although radiation effects in deep-submicron MOSFETs have been studied extensively in recent years, the effects of mechanical stress on transients in advanced MOSFETs have not been understood fully. Since strained-Si technology is widely adopted to increase carrier mobility in the channel in commercial off-the-shelf (COTs) chips, it is important to understand the trade-offs between chip performance and radiation effects in strained-Si devices. This work investigates the effect of uniaixial stress on Si diodes and MOSFETs under radiation through controlled stress experiments and device simulation. X-ray-induced charge trapping and mobility degradation are investigated on uniaxially stressed HfO2-based nMOSFETs. Uniaxial tensile and compressive stress in nMOSFETs decreases the amount of net positive charge trapping and reduces the threshold voltage shift. Our experimental results suggest that changes in bond lengths and angles in HfO2 and/or SiOx as function of mechanical stress can reduce trap activation energy in gate dielectrics. Drive current (electron mobility) degradation in nMOSFETs is characterized and explained after irradiating devices under stress. Laser-induced current transients in uniaxially stressed silicon (Si) N+/P and P+/N diodes are studied. They are good representation of source and drain regions of MOSFETs. Uniaxial stress alters the shape of the current transient in diodes resulting from strain induced changes in carrier mobility. The Florida Object Oriented Device Simulator (FLOODS) is used to model and explain the mechanism of current transients in unstressed and stressed diodes. The correlation between the external mechanical stress results on large diodes and deep sub-micron MOSFETs (both n-type and p-type) with process induced stress is also investigated and explained.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Hyunwoo Park.
Thesis: Thesis (Ph.D.)--University of Florida, 2011.
Local: Adviser: Thompson, Scott.
Local: Co-adviser: Nishida, Toshikazu.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2011
System ID: UFE0043566:00001

Permanent Link: http://ufdc.ufl.edu/UFE0043566/00001

Material Information

Title: Impact of Uniaxial Stress on Silicon Diodes and Metal-Oxide-Semiconductor-Field-Effect-Transistors under Radiation
Physical Description: 1 online resource (105 p.)
Language: english
Creator: Park, Hyunwoo
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2011

Subjects

Subjects / Keywords: dielectrics -- effects -- events -- high-k -- radiation -- single -- strained-si -- stress -- total-ionizing-dose -- transients -- uniaxial
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Uniaxial strained-silicon (Si) has emerged as a leading technique for enhancing transistor performance for sub-100 nm logic technology for use in commercial and consumer electronics. Traditionally, semiconductor chips for military and space applications are fabricated using expensive radiation hardened technology. There is significant interest in the radiation research community towards integrating commercial CMOS technology for use in radiation environments to reduce costs. Although radiation effects in deep-submicron MOSFETs have been studied extensively in recent years, the effects of mechanical stress on transients in advanced MOSFETs have not been understood fully. Since strained-Si technology is widely adopted to increase carrier mobility in the channel in commercial off-the-shelf (COTs) chips, it is important to understand the trade-offs between chip performance and radiation effects in strained-Si devices. This work investigates the effect of uniaixial stress on Si diodes and MOSFETs under radiation through controlled stress experiments and device simulation. X-ray-induced charge trapping and mobility degradation are investigated on uniaxially stressed HfO2-based nMOSFETs. Uniaxial tensile and compressive stress in nMOSFETs decreases the amount of net positive charge trapping and reduces the threshold voltage shift. Our experimental results suggest that changes in bond lengths and angles in HfO2 and/or SiOx as function of mechanical stress can reduce trap activation energy in gate dielectrics. Drive current (electron mobility) degradation in nMOSFETs is characterized and explained after irradiating devices under stress. Laser-induced current transients in uniaxially stressed silicon (Si) N+/P and P+/N diodes are studied. They are good representation of source and drain regions of MOSFETs. Uniaxial stress alters the shape of the current transient in diodes resulting from strain induced changes in carrier mobility. The Florida Object Oriented Device Simulator (FLOODS) is used to model and explain the mechanism of current transients in unstressed and stressed diodes. The correlation between the external mechanical stress results on large diodes and deep sub-micron MOSFETs (both n-type and p-type) with process induced stress is also investigated and explained.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Hyunwoo Park.
Thesis: Thesis (Ph.D.)--University of Florida, 2011.
Local: Adviser: Thompson, Scott.
Local: Co-adviser: Nishida, Toshikazu.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2011
System ID: UFE0043566:00001


This item has the following downloads:


Full Text

PAGE 1

1 IMPACT OF UNIAXIAL STRESS ON SILICON DIODES AND METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS UNDER RADIATION By HYUNWOO PARK A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2011

PAGE 2

2 2011 Hyunwoo Park

PAGE 3

3 To my family

PAGE 4

4 ACKNOWLEDGMENTS First of all, I would like to thank my advisor, Dr. Scott Thompson, for his support and gu idance to help me solve research problems logically and practically. I also would like to thank my co advisor, Dr. Toshikazu Nishida, for his guidance and encouragement to continue my research consistently Also, I want to thank my committee members, Dr. J ing Guo and Dr. Brent Gila for their interest and suggestion s on my PhD research. I would like to e specially thank Dr. Daniel Cummings for his invaluable idea s and untiring effort on t he projects we worked together. My thanks to Dr. Sriram Dixit for helpin g me complete my first project in radiation effects. I want to thank Dr. Mark Law for his support with FLOODS simulation s I would like to thank Dr. Ron Schrimpf fo r his advice on my project and full support for my experiment s I am grateful to Dr. Jonatha n Pellish, Dr. Robert Reed Dr. Dale McMorrow, Dr. Daniel Fleetwood Rajan Arora, Sarah A r mstrong and Nicholas Hooten for priceless help with experiment s and advice for understanding radiation effects. I want to thank Dr. Younsung Choi for his insight ful idea s for boosting the progress of my research and his constant encouragement to keep continuing my PhD. I also want to thank Srivatsan Parthasarathy and Dr. Andrew Koehler who gave me a lot of help in editing my writing I would like to thank Dr. Uma Agho ram for her advice towards motivating me during difficult time I must also acknowledge my lab mat es who support ed my research a nd made the lab an enjoyable place to work : Amit Gupta Dr. Guangyu Sun Jingjing Lu Dr. Ji Song Lim Dr. Min Chu, Mehmet Bayka n Dr. Sagar Suthram Tony Acosta Dr. Toshi nori Numata Ukjin Roh Dr. Xiaodong Yang Dr. Yongke Sun I also want to thank Nicole Rows ey Ashish Kumar, Erin Patrick for their advice on FLOODS and FLOOPS simulation.

PAGE 5

5 I dedicate my dissertation to my family My parents Jooyoung Park and Kwangja Choi gave me their overwhelming love, endless encouragement, and steadfast support I want to acknowledge my only brother Minwoo for his support and cheer s I want to thank my parents in law Yongbin Kim and Kyunghee Y oun for their constant pray er and encouragement. Last but certainly not the least I am heartily thankful to my wife, Jaekyung Kim who has always been there for me, with the deepest love and unfailing support

PAGE 6

6 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ .. 4 LIST OF TABLES ................................ ................................ ................................ ............ 8 LIST OF FIGURES ................................ ................................ ................................ .......... 9 LIST OF ABBREVIATIONS ................................ ................................ ........................... 12 ABSTRACT ................................ ................................ ................................ ................... 13 CHAPTER 1 INTRODUCTION AND BACKGROUND ................................ ................................ 15 1.1 Motivation ................................ ................................ ................................ ...... 15 1.2 Overview of Strained S ilicon Technology ................................ ...................... 17 1.3 Overview of Radiation Effects ................................ ................................ ....... 20 1.4 Mechanical Stress Bending Setup ................................ ................................ 22 1.5 Objectives and Organization ................................ ................................ ......... 24 2 TOTAL IONIZING DOSE EFFECTS ON STRAINED HFO 2 BASED NMOSFETS .. 26 2.1 Introduction ................................ ................................ ................................ ... 26 2.2 Experimental Setup ................................ ................................ ....................... 27 2.3 Results and Discussion ................................ ................................ ................. 30 2.3.1 Radiation Induced Threshold Voltage Shifts under Uniaxial Stress ..... 30 2.3.2 Radiation Induced Mobility Degradation under Uniaxial Stress ............ 34 2.4 Conclusion ................................ ................................ ................................ .... 38 3 LASER INDUCE D CURRENT TRANSIENTS IN STRAINED SI N+/P DIODES ..... 40 3.1 Introduction ................................ ................................ ................................ ... 40 3.2 Experimental Setup ................................ ................................ ....................... 41 3.3 Experimental Results and Discussion ................................ ........................... 43 3.4 Simulation Results and Discussion ................................ ............................... 49 3.4.1 Basel ine Simulation Results under No Stress ................................ ...... 49 3.4.2 Simulation Results under Stress ................................ .......................... 52 3.5 Correlation between Transients in N+/P di ode and nMOSFET ..................... 58 3.6 Conclusion ................................ ................................ ................................ .... 61 4 LASER INDUCED CURRENT TRANSIENTS IN STRAINED SI P+/N DIODES ..... 63 4.1 Introduction ................................ ................................ ................................ ... 63 4.2 Experimental Setup ................................ ................................ ....................... 64

PAGE 7

7 4.3 Experimental Results and Discussion ................................ ........................... 65 4.4 Simulation R esults and Discussion ................................ ............................... 67 4.5 Correlation between T ransients in P+/N diode with pMOSFET ..................... 73 4.6 Conclusion ................................ ................................ ................................ .... 86 5 SUMMARY AND RECOMMENDATION FOR FUTURE WORK ............................. 88 5.1 Summary ................................ ................................ ................................ ....... 88 5.2 Recommendation for Future Work ................................ ................................ 90 LIST OF REFERENCES ................................ ................................ ............................... 91 BIOGRAPHIC AL SKETCH ................................ ................................ .......................... 105

PAGE 8

8 LIST OF TABLES Table page 2 1 TID experimental matrix ................................ ................................ ..................... 28 3 1 Values of 5 MPa 1 ) ........................ 49 3 2 5 MPa 1 ) used in 2 demensional FLOODS ................................ ................................ .................... 5 5

PAGE 9

9 LIST OF FIGURES Figure page 1 1 Uniaxial stress in Si MOSFETs beyond 90 nm logic technology ....................... 16 1 2 Strained Si MOSFETs in the radiation environment ................................ ........... 17 1 3 Uniaxial stress effect on electron and hole mobility. ................................ ........... 18 1 4 Process induced uniaxia l stress ................................ ................................ ........ 19 1 5 Total inonizing dose effects in MOSFETs. ................................ .......................... 21 1 6 Single Event Effects in MOSFETs. ................................ ................................ ..... 21 1 7 Four point mechanical bending setup A) cross section B) top view. ................... 23 1 8 Schematic of uniaxially stressed wafer via mechanical bending set up. Uniaxial tensile stress is applied to a wafer. ................................ ....................... 24 2 1 Experiment set up for TID measurements ................................ .......................... 29 2 2 Semilog and linear plot of the I D V G S characteristics as a function of the accumulated x ray dose under tensile stress of 200 MPa. ................................ 31 2 3 Threshold voltage shifts ( V T ) observed with and without tensile stress and radiation at 2V gate bias. ................................ ................................ ................... 32 2 4 Threshold voltage shifts ( V T ) observed with and without tensile stress and radiation at 2V gate bias ................................ ................................ ................... 33 2 5 Threshold voltage shifts ( V T ) vs. mechanical stress after 5Mrad (SiO 2 ) and 2.5 h under 2 V gate bias. ................................ ................................ ................. 35 2 6 Gate leakage change in Si high k MOS capacitor (7nm HfSiON dielectric) as a function of uniaxial stress. ................................ ................................ ............... 36 2 7 A band diagram of Si high k MOS capacitor showing trap activation energy reduction as a function of uniaxial stress. ................................ ........................... 36 2 8 Radiation induced charge trapping model under uniaxial stress ........................ 37 2 9 Electron mobility vs. gate over drive voltage ( V GS V T ) with and without uniaxial tensile st ress (200 MPa) and radiation (5 Mrad) ................................ .... 38 2 10 Electron mobility enhancement vs. mechanical stress before and after 5 Mrad (SiO 2 ) irradiation. ................................ ................................ ....................... 39

PAGE 10

10 3 1 Schematic of Laser induced current transient measurement system using a four point bending setup ................................ ................................ ................... 42 3 2 High speed measurement system for measuring current transients in diodes as a function of uniaxial stress. ................................ ................................ ........... 43 3 3 Cross section of N+/P diode ................................ ................................ ............... 44 3 4 Laser induced current transients and the rat io of collected charge measured as a function of <110> uniaxial mechanical stress. ................................ ............ 45 3 5 The number of laser generated electron hole pairs as a function of depth (z) and <110> uniaxial tensil e stress. ................................ ................................ ...... 46 3 6 Uniaxial tensile stress effect on electron mobility ................................ ............... 46 3 7 Schematic of laser induced current transients and 2 dimensional simulation structure of an N+/P diode. ................................ ................................ ................. 50 3 8 Simulated energy dependence of laser induced current transients .................... 51 3 9 Piezoresistance factor P(N,T) as a function of doping density ( N ) and temperature ( T ) for n type Si ................................ ................................ ............. 53 3 10 Piezoresistance factor P(N,T) as a function of doping density ( N ) and temperature ( T ) for p type Si ................................ ................................ ............. 53 3 11 Transformation of the Cartesian coordinates system for two demensional FLOODS simulation. A) original B) transformed ................................ ................. 54 3 12 Simulated laser induced current transients as a function of <110> uniaxial mechanical stress. ................................ ................................ .............................. 56 3 13 Peak current ( I max ) in N+/P diodes as a function of mechanical str ess.. ............. 57 3 14 Collected charges in N+/P diodes ( Q ). ................................ ............................... 58 3 15 Peak current ( I max ) in N+P diodes and nMOSFETs as a function of mech anical stress. ................................ ................................ .............................. 60 3 16 Collected charges ( Q ) in N+/P diodes and nMOSFETs ................................ ...... 61 4 1 Motivation for measurement of P+/N diode. ................................ ....................... 63 4 2 Laser induced current transient measurement system in P+/N diode using a four point bending setup ................................ ................................ .................... 64 4 3 Laser induced current transients in P+/N diode as a function of <110> uniaxial mechanical stress. ................................ ................................ ................. 66

PAGE 11

11 4 4 Details of two dimensional structure of 100 m junction size P+/N diode in FLOODS. ................................ ................................ ................................ ............ 68 4 5 Comparison of experiment with simulation of current transient s in P+/N diode s under no stress ................................ ................................ ...................... 70 4 6 Simulated laser induced current transients in P+/N diode as a function of <110> uniaxial mechanical stress. ................................ ................................ ...... 71 4 7 Change in p eak current ( I max ) in P+/N diode as a function of <110> uniaxial stress. ................................ ................................ ................................ ................. 72 4 8 C hange in collected charge ( Q ) in P+/N diode as a function of <110> uniaxial stress ................................ ................................ ................................ .................. 72 4 9 Details of two dimenisional structure of 0.1 m junction size pMOSFET used in FLOODS. ................................ ................................ ................................ ........ 74 4 10 Change in p eak current ( I max ) in pMOSFETs and P+/N diode as a function of <110> uniaxial stress ................................ ................................ .......................... 75 4 1 1 Change in p eak current ( I max ) in P+/N diode with <110> uniaxial stress and pMOSFETs under <110> uniaxial stress with different junction size. ................. 77 4 1 2 Change in peak current ( I max ) in 0.1 m junction coefficient component as a function of <110> uniaxial stress ............................. 81 4 1 3 Change in peak current ( I max ) in 100 m junction P+/N diode coefficient component as a fun ction of <110> uniaxial stress ............................. 81 4 1 4 Hole concentration contour at peak current in unstressed 0.1 m junction pMOSFET. ................................ ................................ ................................ .......... 82 4 1 5 Hole concentration contour at peak current in unstressed 100 m P+/N diode .. 82 4 1 6 Change in peak current ( I max ) in P+/N diode and pMOSFETs as a function of <110> uniaxial stres s. ................................ ................................ ......................... 83 4 1 7 Change in collected charge ( Q ) in P+/N diode and pMOSFETs as a function of <110> uniaxial stress ................................ ................................ ..................... 84

PAGE 12

12 LIST OF ABBREVIATION S COTs Commercial off the shelf DRAM D yn amic random access memory DSETs Digital single event transients EDS E nergy dispersive X ray spectroscopy FLOODS Florida object oriented device simulator FLOOPS Florida object oriented process simulator MOSFET Metal oxide semiconductor field effect transist or SEB S ingle event burnout SEEs Single event e ffects SEFI S ingle event functional interrupt SEGR Single event gate rupture SELU S ingle event latch up SETs Single event transients SEUs Single event upsets SRAM S tatic random access memory TEM T ransmission e lectron microscopy TID Total ionizing d ose

PAGE 13

13 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy IMPACT OF UNIAXIAL STRESS ON SILICON DIODES AND METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS UNDER RADIATION By Hyunwoo Park December 2011 Chair: Scott E. Thompson Cochair: Toshikazu Nishida Major: Electrical and Computer Engineering U niaxial strained silicon (Si) has emerged as a leading technique for enhancing transistor performance for sub 100 nm logic technology for use in commercial and consumer electronics Traditionally, s emiconductor chips for military and space applications are fabricated using expensive radia tion hardened technology There is significant interest in the radiation r esearch community towards integrating commercial CMOS technology for use in radiation environments to reduce costs Although radiation effects in deep submicron MOSFETs have been stu died extensively in recent years, the effects of mechanical stress on transients in advanced MOSFETs have not been understood fully. Since strained Si technology is widely adopted to increase carrier mobility in the channel in commercial off the shelf (COT s) chips, it is important to understand the trade offs between chip performance and radiation effects in strained Si devices. T his work investigates the effect of un i a i xial stress on Si diodes and MOSFETs under radiation through controlled stress experimen ts and device simulation X ray induced charge trapping and mobility degradation are investigated on uniaxially stressed HfO 2 based nMOSFETs. Uniaxial t ensile and compressive stress in

PAGE 14

14 nMOSFETs decreases the amount of net positive charge trapping and redu ces the threshold voltage shift. O ur experimental results suggest that changes in bond lengths and angles in HfO 2 and/or SiO x as function of mechanical stress can reduce trap activation energy in gate dielectrics D rive current (electron m obility) degradat ion in nMOSFETs is characterized and explained after irradiating devices under stress. Laser induced current transients i n uniaxially stressed silicon (Si) N+/P and P+/N diodes are studied. T hey are good representation of source and drain regions of MOSFE Ts. Uniaxial stress alters the shape of the current transient in diodes resulting from strain induced changes in carrier mobility. The Florida O bject O riented D evice S imulator (FLOODS) is used to model and explain the mechanism of current transients in uns tressed and stressed diodes. The correlation between the external mechanical stress results on large diodes and deep sub micron MOSFETs (both n type and p type) with process induced stress is also investigated and explained.

PAGE 15

15 CHAPTER 1 INTRODUCTION AND BAC KGROUND 1.1 Motivation Continued s caling of silicon (Si) MOSFETs has enabled manufacturing cost reduction and performance improvement in the semiconductor industry for the last thirty years [1, 2] In 1965 Gordon Moore predicted that t he number of transistors incorporated in a chip will approximately double every 24 months [3 6] For a number of years, simple geometrical scaling was sufficient to keep Moore s law alive However, as device dimensions reached deep sub micron levels, the p resence of severe short channel effects and high leakage current levels [7 10] meant that the conventional constant field based scaling alone was not enough to meet the goals set in the International Technology Road map for Semiconductor s (ITRS) [11] In the last decade, a number of technolog ical innovations at the device, circuit and architecture levels have been necessary to maintain Moore s law [12, 13] Amongst these innovations, u ni axial s trained Si technology has emerged as one of the most important techniques at the device level to improve performance [2, 14 18] Intentional uniaxial mechanical stress using SiN capping layer or SiGe epi taxial growth applied to the channel of MOSFETs increases their drive currents [17 19] Since the uniaxial strained Si engineering is a very cost effective technique it is widely used in logic transistors to d ay [16 18] Figure 1 1 shows t ransmission electron microscopy (TEM) micrographs of and 32 nm n and p MOSFETs that inc orporate uniaxial stress [15, 16, 20 24] Radiation hardened device technology for space and military electronics market ha s been stron gly influenced by commercial C MOS technology [25, 26] Since the cost of making radiation hardened d evices is becoming very expensive, there is an ongoing

PAGE 16

16 research effort towards the feasibility of using commercial off the shelf (COTs) chips to reduce costs However to date, there has been no systematic study on the radiation hardness of strain engineer ed advanced MOSFETs In this work, we investigate the reliability of strained devices in r adiation environment towards understanding the benefits of using strained devices for space and nuclear applications ( Figure 1 2 ) Figure 1 1. Uniaxial stress in Si MOSFETs beyond 90 nm logic technology Transistors using 90,65,45,and 32 nm technology are shown [ Reprinted, with permission, from [ S. E. Thompson et al A logic nanotechnolo gy featuring strained silicon IEEE Electron Dev. Lett., vol. 25, p. 191 F igure 1, Apr. 2004. ], [ P. Bai, et al. A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low k ILD and 0.57 m 2 SRAM cell in IEDM Tech. Dig., p. 65 8 Figure 1 and 2, Dec. 2004 ], [ K. Mistry, et al. A 45 nm logic technology with high k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb free p ackaging in IEDM Tech. Dig., p 24 8, Figure 6 Dec. 2007 ], [ C. Auth, et al., 45nm High k + metal gate strain enhanced transistors in VLS I tehnology Tech. Dig., p. 129 Figure2, Dec. 2008 ], [ P. Packan, et al. High Performance 32nm Logic Technology Featuring 2nd Generation High k + Metal Gate Transistors in IE DM Tech. Dig., p. 28.4. 2 Figure 5, Dec. 2009 ] ]

PAGE 17

17 F igure 1 2 Strained Si MOSFETs in the radiation environment [Reprinted, with permission, from S. E. Thompson et al strained IEEE Electron Dev. Lett., vol. 25, p. 191, Figure 1, Apr. 2004. ] 1.2 Overview of Str ained S ilicon Technology Mechanical stress in the transistor channel enhances the drive current in MOSFETs through an increases in carrier mobility for both electrons and holes These enhancement s are attributed to a decrease in carrier effective mass or s cattering due to stress altered Si band structure [2, 16 18, 27 29] Biaxial stress was the first technique to be investigated for enhancing carrier mobility. High amounts of biaxial stress can be introduced by growing a thin Si layer on relaxed silicon germanium (SiGe) substrate [30 32] However, due to the prese nce of a large number of defects at high stress levels [33] large threshold voltage shift [34, 35] and very small hole mobility enhancement s observed [17] biaxia l stress started losing its appeal I n addition, integration difficulties associated with introducing tensile and

PAGE 18

18 compressive stress for n and pMOSFETs simultaneously makes biaxial stress less attractive for very large scale integration [12] Figure 1 3 Uniaxial stress effect on electron and hole mobility A ) Electron and B ) hole mobility enhancement in uniaxial stress. [ Reprinted, with permission, from S. Suthram, et al. "Piezoresistance coefficients of ( 100) silicon nMOSFETs measured at low and high (similar to 1.5 GPa) channel stress," IEEE Elec. Dev. Lett., vol. 28, p 60, Figure 3 Jan. 2007 ] (b) [Reprinted, with permission, from S. Suthram, "S tudy of the Piezoresistive Properties of Si, Ge, and GaAs MO SFETs Using a Novel Flexure Based Wafer Bending Setup, PhD Gainesville: University of Florida p. 49, Figure 3 6 2008 ] Compared to biaxial stress, u niaxial compressive stress produces a large hole mobility enhancement [17, 19] and introduces minimal threshold voltage shift s [34, 35] It also decreases gate tunneling current [36, 37] E lectron mobility enhancement in nMOSFETs up to ~ 50 % (for 1.5 GPa uniaxial stress ) and h ole mobility enhancement in pMOSFETs up to ~200% (for ~2GPa uniaxial stress ) have been reported, as shown in Figure 1 3 [38] U niaxial tensile stress on n MOSFETs and uniaxial compressive stress on p MOSFETs can be concurrently applied on the same wafer without incurring much additional process complexity [17, 39 42] This was the primary reason as to why

PAGE 19

19 uniaxial stress engineering was adopted by the industry as a performance boo ster starting from the 90 nm node. Figure 1 4 Process induced uniaxial stress A ) SiGe epitaxial growth in pMOSFETs B ) SiN capping layer in n and pMOSFETs [ Reprinted, with permission, from S. E. Thompson, et al. "Uniaxial process induced strained Si: Extending the CMOS roadmap," IEEE Trans. Electron Dev ., vol. 53, p 1018, Figure 13 May 2006. ] There are two ways to apply uniaxial stress to devices. The first technique is SiGe epitaxial growth in source/drain regions to create compressive stress in pM OSFETs [15, 16, 39] as shown in Figure 1 4 (a) It was successfully implemented in 90 nm technology node by Intel in 2002 at first [15] D ual stress liner technique using compressive and tensile Silicon Nitride (SiN) can be implemented in n and pMOS FETs, respectively [39 ] as shown in Figure 1 4 (b)

PAGE 20

20 1.3 Overview of Radiation Effects Radiation effects in MOS devices are generally categorized into total ionizing dose (TID) effects and single event effects (SEEs) [43 47] TID effects in MOSFETs are due to radiation induce d trapped charges in gate oxide and shallow trench isola tion (STI) T rapped charges shift threshold voltage, decreas e carrier mobility, and degrade the dielectric [26, 43, 45 48 50] Figure 1 5 shows how radiation introduces charges in the devices which are trapped in the gate oxide. 1 100 0 keV energy range electrons or proton s create electron hole pairs in gate oxide [45, 51] In the presence of applied bias, electrons are swept out of gate oxide. However, relatively immobile holes are trapped inside the gate oxide and it results in a negative threshold voltage shift The radiation also g enerate s traps near the Si/SiO 2 interface In thick STI (~400 nm), a large number of electron s and hole s can build up and increase the off state leakage [43, 52] To maintain the same applied electric field, the thickness of gate oxide is reduced in scaled d evices as the supply voltage is lowered Due to the reduction in the insulator volume where charge trapping could occur, scaled MOSFETs have a smaller threshold voltage shift [48, 49] However, the high gate leakage current in a very thin SiO 2 increase s the off state power and impacts the reliability issues of devices H igh k dielectrics have emerged as a solution [21, 23, 53] to combat the leakage and reliability issue s within the last 5 y ears While the p erformance and r eliability of high k d ielectrics have been investigated extensively for over a decade [47, 54 60] for commercial MOSFET applications, the effect of r adiation damages in high k dielectric s has been done only recently [47, 61 64] T he effects of uniaxial stress on radiation induced charge trapping and mobility degradation in high k based MOSFETs have not been understood fully to this date

PAGE 21

21 Figure 1 5 Total inonizing dose effects in MOSFETs. [ Reprinted, with permission, from [ T. R. Oldham et al. Total ionizing dose effects in MOS oxides and devices, IEEE Trans. Nucl. Sci., vol. 50, p 484, Figure 2 Jun. 2003. ] Figure 1 6 Single Event Effects in MOSFETs SEEs in MOSFETs are voltage or current transient s in sensitive nodes ( such as the MOSFETs source and drain region s ) caused by 1 100 0 MeV high energy particles such as protons, neutrons, heavy ions, and alpha particles, as shown in Figure 1 6 [25, 44] SEEs are divided into soft (nondestructive) and hard (destructive) error s The

PAGE 22

22 common physics in both types of SEEs is the presence of a transient pulse caused by drift and diffusion of a large number of electron s or hole s due to the high energy particles [25, 44, 46] For examples, the transients can cause single event upsets (SEU) [25, 65] which manifests as inversion of the bits stored in memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM). Digital single event t ransients (DSETs) are those transients propagat ing through combinational logic circuits and are stored into memory components [44, 66] Other soft errors are single event functional interrupt (SEFI) and single even t latch up (SELU) [44, 46] While soft errors cause temporarily data loss hard errors lik e single event gate rupture (SEGR) and single event burnout (SEB) [44, 46] lead to permane nt data breakdow n 1.4 Mechanical Stress Bending Set up Controlled external mechanical stress is applied via a four point bending setup [67, 68] as shown in Figure 1 7 T he amount of applied uniaxial stress can be obtained using [69] (1 1) where is the applied stress, E is the of Si along the stress direction, is strain t is the thickness of the wafer d is vertical displacement between the upper and lower plate s of a four point bending setup a is the distance between the inn er and outer rods, and L is the distance between the two outer rods as shown in Figure 1 8 Previous work by Chu et al. [70] shows the calculated stress is in good agreement with a measurement using a strain gage with less than 5% error.

PAGE 23

23 Figure 1 7 Four point m echanical bending setup A) cross section B ) top view.

PAGE 24

24 Fi gure 1 8 S chematic of uniaxially stressed wafer via m echanical bending set up. Uniaxial tensile stress is applied to a wafer. 1.5 Objectives and Organization The main goal of this study is to understand how mechanical stress affects the reliability of semiconductor devices in the radiation environment in vie w of total ionizing effects (radiation induced trapped charges, mobility degradation) and single event effect (voltage or current transients). In C hapter 2, radiation induced threshold voltage shift and electron mobility degradation in strained metal gate high k nMOSFETs are measured quantitatively and a qualitative physics based model based is presented C hapter 3 investigates experimentally and theoretically how uniaxial stress change s the laser induced current transients in uniaxially stressed N+/P Si d iodes. The effects of mobility enhancement/degradation under mechanical stress on peak current of current transients and collected charges in the diodes are presented in detail Based on the method develop ed in C hapter 3 for analyzing transients, laser i nduced current transients in P+/N diodes as a function of uniaxial stress are studied in

PAGE 25

25 C hapter 4 experimentally and theoretically The difference between laser i nduced current transients in un iaxially stressed P+/N diode and alpha particle induced curren t transients in STI induced stressed pMOSFETs are discussed. Chapter 5 summarizes this study and suggests the future work.

PAGE 26

26 CHAPTER 2 TOTAL I ONIZING DOSE EFFECTS ON STRAINED H FO 2 BASED NMO SFETS 2.1 Introduction U niaxial strained silicon (Si) [14, 15] and high k gate dielectric [71] are key technolog ies used to enhance transistor pe rformance for sub 100 nm logic technology nodes. Uniaxial s train improves device characteristics such as mobility [17, 19] gate tunneling current [36, 37, 72, 73] with minimal threshold voltage shift s [34, 35] High k gate dielectrics are being implemented to reduce transistor gate leakage current in the 45 nm CMOS technology node [23 ] Hafnium based dielectrics, in the form of silicates and nitrided silicates with a relative dielectric constant of ~15 to 26, have emerged as the materials of choice for high k gate dielectrics. Although r adiation damage of HfO 2 based MOS devices has been studied in recent years [61, 63] t he effects of uniaxial mechanical stress on the ionizing radiation response of HfO 2 based MOS devices have not been reported Hole trapping is observed to be dominant in HfO 2 [61, 63] dielectric layers, similar to SiO 2 [26] The effects of mechanical stress on the ionizing radiation response of SiO 2 based MOS devices have been reported [74, 75] but t he mechanical stress these studies by changing the gate electrode thickness is much smaller than that used in strained Si technology (~ 2 GPa) [76, 77] In high k transistors, remote Coulomb scattering ( RCS ) is one of the main factors limiting the mobility [71, 78] In commercial devices, most of the RCS effect comes from fixed charges generated by the fabrication process [78] The effects of radiation induced [ 2008 ] IEEE. Chapter 2 is r eprinted, with permission, from [H. Park, S. K. Dixit, Y. S. Choi, R. D. Schrimpf, D. M. Fleetwood, T. Nishida, and S. E. Thompson, Total Ionizing Dose Effects on Strained HfO2 Based nMOSFETs, IEEE T rans Nucl Sci vol. 55, pp. 2981 2985, Dec 2008]

PAGE 27

27 charges on RCS would likely be similar to what is seen in comme rcial devices. Owing to the ubiquitous use of high k based strained Si technology in the future, it is important to address the radiation response of these devices as a function of stress. In this work, we investigate the effects of uniaxial stress on the radiation induced threshold voltage shift s and mobility degradation in HfO 2 based nMOSFETs using controlled external mechanical stress. 2.2 Experimental Setup Radiation induced threshold voltage shifts and mobility degradation in mechanically stressed HfO 2 based nMOSFET are extracted from drain current gate voltage ( I D V GS ) characteristics The samples used in this study are TiN/HfO 2 gate stack nMOSFETs on Si (001) wafers and <110> channel direction. The high k gate dielectric is 7.5 nm in physical thicknes s. The thickness of the SiO x interlayer is 1 nm. The effective oxide thickness (EOT) of these transistors is 2.3 nm. The size ( W/L ) of the transistors used in this investigation is 10 m/3 m. Strain in the devices is produced by applying u niaxial mechanic al stress using a four point bending setup [35] as shown in Figure 2 1 The devices are irradiated in an ARACOR 10 keV X ray irradiation system under different values of stress (100 MP a and 200 MPa tensile no stress and 200 MPa compressive), at 2 V gate bias with the source, drain, and body grounded [61] Samples are irradiated to a cumulative dose of 5 Mrad(SiO 2 ) a t a dose rate of 31.5 krad(SiO 2 )/min; the experimental matrix is shown in Table 2 1 Post irradiation I D V GS curves are measured using an Agilent 4156 semiconductor parameter analyzer Threshold voltage shifts ( V T ) are monitored as a function of radiation dose for different applied uniaxial mechanical stress es. Threshold voltages are extracted using a

PAGE 28

28 constant current (CC) method [79] Pre and post irradiation subthre shold behavior is also studied. 2 V gate bias stress experiment s without irradiation are performed Table 2 1 TID experimental ma trix Compressive 200 MPa No Stress 0MPa Tensile 100MPa Tensile 200MPa Pre rad (0Mrad) 0.5 Mrad 1 Mrad 5 Mrad [ 2008 ] IEEE. [ Reprinted, with permission, from H. Park, et al. Total Ionizing Dose Effects on Strained HfO2 Based nMOSFETs, IEEE Trans. Nucl. Sci., vol. 55, p. 298 2, Table 1 Dec. 2008] to separate the co ntributions of bias induced charge trapping/creation [80] in these gate dielectrics from the radiation induced shifts. The ext racted e lectron mobility from current voltage equation at low drain voltage ( V DS = 0.1 V ) is expressed as [1] (2 1) w here is I D is the current of nMOSFETs, V GS is the applied voltage between gate and source, L g is the channel length, W is the channel width, C ox is the gate oxide capacitance per unit area and V T is the threshold voltage. Threshold voltage instability is one of the main issues in high k devices [81 83] In this work, threshold voltage shifts are measured after being stabilized by sweeping the I D V GS curves before and after irradiation For the s amples used in this investigation the threshold voltage shift stabilizes generally after the second I D V GS curv e after ir radiation or bias stress The stabilization occurs because charges in shallow hole trap sites of SiO x or HfO 2 may detrap or holes in deep er trap sites near the interface may recombine with injected electrons during the first I D V GS sweep under a given irradiation or bias condition Previous work by Dixit et al. [61] focused on the threshold voltage shift of the

PAGE 29

29 Figure 2 1 Experiment set up for TID mea surements A ) schematic (not to scale) B ) picture for measuring total ionizing dose (TID) effects under mechanically strained nMOSFET and cross section of gate stack of high k nMOSFET (a) [ Reprinted, with permission, from H. Park, et al. Total Ionizing D ose Effects on Strained HfO2 Based nMOSFETs, IEEE Tran s. Nucl. Sci., vol. 55, pp. 298 2 Figure 1, Dec. 2008]

PAGE 30

30 first I V curve, which includes the effects of these transient shifts This work focuses instead on the changes in radiation induced charge trappin g under uniaxial mechanical stress after the threshold voltage stabilizes. 2.3 Results and Discussion Hole trapping in the gate oxide is the dominant radiation induced charge for these devices under the irradiation conditions as seen by the decrease in th e threshold voltage as shown in Figure 2 2 This agrees with previous results on HfO 2 based n MOSFETs in [61] Threshold voltage shifts ( V T ) can be caused by interface trapped charge ( Q it ) and oxide trapped charges ( Q ot ) [84] Since there i s no significant change observed in the subthreshold slope in Figure 2 2 the threshold voltage shifts are caused mainly by an increase in Q ot [61] Transistors irradiated under mechanica l stress conditions ( compressive (200 MPa), no stress and tensile (200 MPa) ) are also dominated by positive charge trapping 2.3.1 Radiation Induced Threshold Voltage Shifts under Uniaxial Stress The effect of applied mechanical stress on charge trapping is characterized by monitoring threshold voltage shifts at each given radiation dose. The tensile stress effect is shown in Figure 2 3. I ncreasing tensile stress results in less threshold voltage shift at each dose level than that measured for devices irra diated with no stress applied Smaller threshold voltage shifts are observed after applying only bias for a total time of 2.5 h, which is equivalent to the time required for 5 Mrad(SiO 2 ) irradiation Tensile stress also reduces the threshold voltage shift resulting only from the bias The data points are the average threshold voltage shifts at each radiation dose or bias time. The error bars in the data points represent the standard deviation in the data at each dose and stress

PAGE 31

31 level. Figure 2 4 shows a sim ilar trend for the threshold voltage shifts under 200 MPa of compressive stress. Figure 2 2 Semilog and linear plot of the I D V GS characteristics as a function of the accumulated x ray dose under tensile stress of 200 MPa. [ Rep rinted, with permission, from H. Park, et al. Total Ionizing Dose Effects on Strained HfO2 Based nMOSFETs, IEEE Tran s. Nucl. Sci., vol. 55, pp. 298 3 Figure 2, Dec. 2008] In contrast to the reported stress dependence of the SiO 2 nMOSFET threshold voltage shift under irradiation [74] both applied tensile and compressive uniaxial stress reduce the threshold volta ge shifts in devices with HfO2 and SiOx dielectrics in Figure 2 5 that were either irradiated under bias, or subjected only to bias stress without irradiation, for comparison

PAGE 32

32 Figure 2 3 Threshold voltage shifts ( V T ) observed with and without tensile stress and radiation at 2V gate bias [ Reprinted, with permission, from H. Park, et al. Total Ionizing Dose Effects on Strained HfO2 Based nMOSFETs, IEEE Trans. Nu cl. Sci., vol. 55, pp. 298 3, Figure 3 Dec. 2008] A possible expl anation of these results is that compressive and tensile uniaxial mechanical stress both lower the hole trap energy level in HfO 2 and /or SiO x reducing hole trapped charges. In recent work, trap assisted gate tunneling current in high k MOS capacitor s inc rease d under both compressive and tensile stress as shown in Figue 2 6 [85] suggesting that the hole trap energy distribution may be shifted to lower

PAGE 33

33 average values by uniaxial mechanical stress. Uniaxial mechan ical stress may change the trap energy levels by changing bond lengths and angles in HfO 2 and SiO x [86, 87] Figure 2 4 Threshold voltage shifts ( V T ) observed with and without tensile stress and radiation at 2V gate bias [ Reprinted, with permission, from H. Park, et al. Total Ionizing Dose Effects on Strained HfO 2 Based nMOSFETs, IEEE Trans. Nucl. Sci., vol. 55, pp. 2983, Figure 4 Dec. 2008] This is consistent with previous works on the oxygen vacancy defect that show that the trap microstructure and energy levels can be changed by stretching the Si Si bonds and/or changing the bond angles [88 91] The assumption that mechanical stress can

PAGE 34

34 chan ge the trap energy level (or trap activation energy) is also supported by a band diagram showing the relationship between trap activation energy and mechanical stress by Choi et al. [57] as shown in Figure 2 7 We can consider two possible reasons why lowering hole trap energy levels will reduce charge tr apping in HfO 2 and/or SiO x First, uniaxial m echanical s tress may enhance the detrapping of holes in shallow trap sites, or the neutralization in deep trap sites by electron injection as illustrated in Figure 2 8 (a) This reduction in hole trap energy inc reases the probability that these defects can emit a trapped hole or capture an electron to compensate a nearby trapped hole Trapped holes in deep trap sites can be neutralized by capturing electrons [89, 90] Sec ond, the effective hole mobility in the gate dielectrics along the <001> direction under uniaxial mechanical stress may be increased by reducing the average trap energy level. H ole transport in thin (~10 nm) high k oxides is expected to be consistent with a multiple trapping model [49, 92, 93] Holes move in oxides by trapping and detrapping from trap sites [49] as shown in Figure 2 8 (b). Reduced trap energ y levels can increase the effective hole mobility which is proportional to exp ( E a /kT ) [92] E a is the hole trap activation energy k is the Boltzman constant, and T is temperature. Hence, s train induced lowering of hole trap energy level s may reduce charge trapping in HfO 2 and SiO x 2.3.2 Radiation Induced Mobility Degradation under Uniaxial Stress Electron mobility is shown as a function of gate over drive voltage ( V GS V T ) in Figure 2 9 200 MPa of tensile stress enhance s the electron mobility at all gate biases Electron mobility degradation for devices irradiated to 5 Mrad(SiO 2 ) under 200 MPa of tensile stress is ~ 1% at V GS V T = 0.55 V, compared to the pre irradiation 200 MPa

PAGE 35

35 case, but the el e c tron mobility is still higher than the unstressed case. Figure 2 10 shows the electron mobility enhancement as a function of stress before and after 5 Mrad (SiO 2 ) irradiation. Th e mobility enhancement compared to unstressed devices is positive after a tot al dose of 5 Mrad(SiO 2 ) at all tensile stress levels above 70 MPa indicating the potential benefit of strained Si for producing radiation hard nMOSFET devices. Figure 2 5 Threshold voltage shifts ( V T ) vs. m echanical s tress a fter 5Mrad (SiO 2 ) and 2.5 h un der 2 V gate bias [ Reprinted, with permission, from H. Park, et al Total Ionizing Dose Effects on Strained HfO2 Based nMOSFETs, IEEE Tran s. Nucl Sci vol. 55, pp. 2984, Figure 5 December 2008]

PAGE 36

36 Figue 2 6 Gate leakage change in Si high k MOS capacitor (7nm HfSiON dielectric) as a function of uniaxial stress [ Reprinted, with permi ssion, from S. Y. Son, et al. "Strained induced changes in gate leakage current and dielectric constant nitrided Hf silicate dielectric sil icon MOS capacitors," Appl Phys Let t. vol. 93, p. 153505, Figure 3, Oct., 2008 ] Figure 2 7 A band diagram of Si high k MOS capacitor showing trap activation energy reduction as a function of uniaxial stress [ Re printed, with permission, from Y. S. C hoi, et al. "Reliability of HfSiON gate dielectric silicon MOS devices under [110] mechanical stress: Time dependent dielectric breakdown," J. Appl. Phys., vol. 105, p. 044503, Figure 7, Feb., 2009. ]

PAGE 37

37 Figure 2 8 Radiation induced charge trapping model under uniaxial stress A ) Charge detrapping/neutralization model B ) multiple trapping detrapping hole transport model [49, 92] [ Reprinted, with permission, from H. Park, et a l. Total Ionizing Dose Effects on Strained HfO2 Based nMOSFETs, IEEE Tran s. Nucl. Sci., vol. 55, pp. 298 4, Figure 6 Dec. 2008 ]

PAGE 38

38 Figure 2 9 Electron mobility vs. gate over drive voltage ( V GS V T ) with and without uniaxial tensile stress (200 MPa) and ra diation (5 Mrad) [ Reprinted, with permission, from H. Park, et al. Total Ionizing Dose Effects on Strained HfO2 Based nMOSFETs, IEEE Trans. Nucl. Sci., vol. 55, pp. 298 4, Figure 7 Dec. 2008 ] 2.4 Conclusion Positive charge trapping is the dominant radiati on induced degradation mechanism in both unstressed and mechanically str essed HfO 2 based nMOSFETs. Uniaxial t ensile and compressive stress in nMOSFETs decreases the amount of net positive charge trapping and reduces the threshold voltage shift. This is at tributed to enhanced detrapping of holes or compensating electron trapping in HfO 2 and/or SiO x

PAGE 39

39 Figure 2 10 Electron mobility enhancement vs. m echanical s tress before and after 5 Mrad (SiO 2 ) irradiation. [ Reprinted, with permission, from [H. Park, et al. Total Ionizing Dose Effects on Strained HfO2 Based nMOSFETs, IEEE Trans. Nucl. Sci., vol. 55, pp. 298 4, Figure 8, Dec. 2008 ] and/or increasing effective hole mobility in the gate dielectric Electron mobility enhancement with stress is retained in 5 M rad (SiO 2 ) irradiated devices above approximately 70 MPa of tensile stress. Uniaxial strain engineering for drive current (mobility) enhancement has the potential to increase radiation hardness in these advanced HfO 2 based MOSFETs.

PAGE 40

40 CHAPTER 3 LASER INDUCED CURRENT TRANSIENTS I N STRAINED SI N+/P DIODES 3.1 Introduction Single event transients (SETs) and single event upsets (SEUs) are related to collection of radiation generated charge at sensitive circuit nodes [25] SET s and SEU s in unstressed deep submicron MOSFETs have been studied extensively in recent years [25, 44, 66, 94 96] Although strained Si technology is widely adopted, the effects of mechanical stress on current transients generated by laser or ion strikes at the source/drain regions of uniaxially stressed devices have not been reported. I t is important to understand how mechanical stress affects these transient pulses since t he transport of the radiation generated carriers in the substrate is affected by stress. L aser induced current transients on a uniaxially stressed Si N+/P junction diode are reported in this chapter An N+/P diode is a good representation of the source/drain junctions that are responsible for charge collection in n channel MOSFETs. P channel MOSFETs are also impor tant for considering SETs and SEUs. However, stress induced electron mobility enhancement is easier to understand than that of holes [17, 18, 97, 98] so N+/P diodes are used in this chapter T he shapes of current transients and the amount of collected charges are measured as a function of stress, because both of them are crucial in predict ing SETs and SEUs in circuits [25] Controlled external mechanical stress is appl ied via a four point bending setup [35] while the samples are irradiated using a picosecond pulsed [ 2009 ] IEEE. C hapter 3 includes content with permission, from [H. Park, D. J. Cummings, R. Arora, J. A. Pellish, R. A. Reed, R. D. Schrimpf, D. McMorrow, S. E. Armstrong, U. Roh, T. Nishida, M. E. Law, and S. E. Thompson, Laser Induced Current Transients in Strained Si Diodes, IEEE Trans Nucl Sci vol. 56, pp. 3203 3209, Dec 200 9 ]

PAGE 41

41 l aser [99, 100] The characteri zation system is based on the direct measurement of the current transients [ 101, 102] The FLOODS simulation tool [103] is used to investigate the mechanisms responsible for the differences in charge collection between stressed and unstressed devices. Additionally, the simulations provide insight into the effects of high mechanical stress (~1 GPa) on laser induced current transients, above the maximum stress that could be applied using the four point bending setup (240 MPa on these samples). 3.2 Experimental Setu p The laser induced current transients in mechanically stressed Si N+/P diodes are captured using a high speed measurement system with an integrated four point ben ding setup as shown in Figure 3 1 and 3 2 The samples used in this study are N+/P diodes fabricated on (001) Si wafers using a stand ard 130 nm CMOS technology. The active area of the diodes is 50 m 100 m. Nickel silicide (NiSi), silicon oxide (SiO x ), and copper (Cu) patterns are present on top of the diodes as shown in Figure 3 3 using transmission electron microscopy (TEM) and en ergy dispersive X ray spectroscopy (EDS). The thickness of the NiSi, SiO x and Cu patterns is ~20 nm, 720 nm, and 280 nm, respectively. The doping densities of the n + p well, and p substrate are ~10 20 ~10 18 and ~10 16 cm 3 respectively [104] The shallow trench isolation (STI) in these devices is an additional source of mechanical stress. However, STI induced stress in the center of the large d iode s is negligible [105] Uniaxial mechanical stress along the <110> direction is applie d using a four point bending setup [35] A cavity d umped dye l aser with a wavelength of 590 nm, a pulse energy of 218 pJ, and a pulse width of 1 ps is used to inject electron hole pairs in the diode. The laser direction is normally incident to the diode surface with a spot size of 6.3 m full width

PAGE 42

42 half maximum diame ter The peak carrier concentration produced by the laser is ~1.6 10 19 cm 3 The pulse laser energy reaching the diode active area is smaller than the value measured at the surface of the structure due to the optical properties of the layers on top of th e diode [99, 106] The transient measurement system uses a Tektronix TDS8200 digital sampling oscilloscope with 80E03 sampling module (20 GHz bandwidth) and is connected to the device using a bias tee (10 kHz to 40 GHz) and a ground signal ground (GSG) probe tip (DC to 40 GHz). Current transients on the N+/P diode are measured under different values of stress (160 MPa and 240 MPa tensile, no stress, and 160 MPa compressive) with a 5 V reverse bias. F igure 3 1 Schematic of Laser induced current transient measurement system using a four point bending setup [ Reprinted, with permission, from H. Park, et al. Laser Induced Current Transients in Strained Si Diodes IEEE Trans action on Nucl ear Sci ence IEEE Trans. Nucl. Sci., vol. 56, pp. 3203 Figure 1, De c. 200 9 ]

PAGE 43

43 Figure 3 2 High speed measurement system for measuring current transients in diodes as a function of uniaxial stress Although the maximum applied stress (~240 MPa) in this investigation is about 16% of that produced by process induced stress ors (~ 1.5 GPa), the experiments still show the dominant mechanisms in the effects of stress on SETs; this approach is analogous to previous works describing the effects of stress on unirradiated MOS devices [17, 19, 34 37, 73, 107] 3.3 Experimental Results and Discussion The effect of the applied mechanical stress on maximum current and charge collection is characterized by monitoring laser induced current transients at each uniaxial stress value. Increasing tensile stress results in lower maximum currents ( I max ) and collected charges ( Q ) than those measured under no stress, as shown in Figure 3 4 for times up to 10 ns after the laser pulse strikes the device. Each transient curve is measured using an averaging technique (100 points) in the sampling oscilloscope. Q is obtained by integrating the measured transient as a function of time. The data points

PAGE 44

44 Figure 3 3 Cross section of N+ /P diode A) Schematic through TEM and EDS analysis (not to scale) B) TEM image. [ Reprinted, with permission, from H. Park, et al. Laser Induced Current Transients in Strained Si Diodes IEEE Trans action on Nucl ear Sci ence IEEE Trans. Nucl. Sci., vol. 56 pp. 3203 Figure2, Dec. 200 9 ]

PAGE 45

45 are the average Q at each level. The error bars in the data points represent the standard deviation in the data at that stress level. Opposite to tensile stress, compressive stress increases I max and Q. A decrease/increase i n I max and Q under tensile/compressive stress can be explained by a 1 D transient analytical solution [108] Figure 3 4 Laser induced current transients and the ratio of collected charge measured as a function of <110> uniaxial mechanical stress [ Reprinted, with permission, from H. Park, et al. Laser Induced Cu rrent Transients in Strained Si Diodes IEEE Trans action on Nucl ear Sci ence IEEE Trans. Nucl. Sci., vol. 56, p. 320 5, Figure 3 Dec. 200 9 ]

PAGE 46

46 Figure 3 5 The number of laser generated electron hole pairs as a function of depth (z) and <110> uniaxial tens ile stress .[ Reprinted, with permission, from H. Park, et al. Laser Induced Current Transients in Strained Si Diodes IEEE Trans action on Nucl ear Sci ence IEEE Trans. Nucl. Sci., vol. 56, p. 320 5 Figure 4, Dec. 200 9 ] Figure 3 6 Uniaxial tensile stre ss effect on electron mobility [97] [ Reprinted, with permission, from H. Park, et al. Laser Induced Current Transients in Strained Si Diod es, IEEE Trans action on Nucl ear Sci ence IEEE Trans. Nucl. Sci., vol. 56, pp. 320 6, Figure 5 Dec. 200 9 ]

PAGE 47

47 Current transients ( I(t) ) are proportional to N in the solution [108] where N is the number of laser gene rated electron hole pairs and is electron mobility along the <001> direction. is the dominant contribution for electron mobility, because electrons are mainly moving in the <001> direction due to applied field along the <001> direction for the large diodes used in the experiment N as a function of depth in Si is defined as [100] (3 1) where is the absorption coefficient of Si, is the photon energy (2.1 eV), z is depth in the Si, I 0 is the intensity of the laser beam, and t is the time. depends on the band gap [109] where a normalized stress dependent is defined as (3 2) E g is the Si band gap (1.12 eV). Based on ( 3. 1) and ( 3. 2), a change in N as a function of uniaxial tensile stress and the depth into Si is plotted in Figure 3 5 Since stress induced bandgap narrowing in Si is minimal (~0.01 eV at 240 MPa of both compressive and tensile stress) [34] an increase in of Si for this range of mechanical stress is negligible [109] As a result, there is no significant increase calculated in N at each depth under mechanical stress, less than 1% at 240 MPa of tensile stress, as shown in Figure 3 5 [100] Since the change in N due to stress is minimal, a ~6.5% decrease in I max at 240 MPa of tensile stress is caused mainly by a decrease in electron mobility along the <001> direction. Likewise, for compressive stress, an increase in I max results from an increase in electron mobility along the <001> direction, because strain induced band

PAGE 48

48 gap narrowing is very small (~0.01 eV at 240 MPa). This suggests that a decrease/increase in electron mobility alo ng the <001> direction under tensile/compressive stress ( ) results in a decrease/increase in I max The experimental results and qualitative analysis both can be explained by previous results on piezoresistance ( ) coefficients in Si [110, 111] (3 3) where ( ) and (0) are the mobility with and with out stress respectively, and is the change in the mobility. Changes (increase or decrease) o f the electron mobility result from changes of the average electron effective mass ( m* ), due to repopulation of electrons under mechanical stress [37, 97, 111 ] For example, Figure 3 6 shows that tensile stress splits the 2 4 Electrons repopulate from the 4 2 valley. T he Average effective mass along the <110> direction ( m ll ) decreases under tensile stress in the same direction, but the average effective mass along the <001> dir ection ( m ) increases under tensile stress in the <110> direction [97] Thus, <110> tensile stress decreases the electron mobility along the <001> direction ( ), because is inversely proportional to m* [97] The opposite dependence is expected with compressive stress. The con current transient simulations for diodes under mechanical stress in the next section. Q is also proportional to the funneling length, L = ( 1+ / ) W, where is the hole mobility along the <001> direction, a nd W is the depletion width [30, 31] A change in hole mobility along the <001> direction ( ) under uniaxial mechanical stress is negligible (~ 0.3% at 250 MPa) [110] Therefore, the change of the collected cha rge

PAGE 49

49 ( ) as a function of the applied mechanical stress is also dominated by the change in electron mobility ( ). By applying the same concepts for analyzing I(t) and L as in the N+/P diodes above, it is possible to predict how current transients in P+/N dio de s would change under mechanical stress. Since I(t) is proportional to N and (~ 1% at 1 GPa) is not significant the change in I max is not expected to be significant under stress. Q is likely to increase with tensile and decrease with compressive stress, because L is equal to ( 1+ p / n ) W [112] and affected by However, further experiment al data and simulation in P+/N diodes as a function of uniaxi al stress will be discussed in C hapter 4. Table 3 1 Values of Smith s 5 MPa 1 ) [111] Electron Hole 11 102.2 6.6 12 53.4 1.1 44 13.6 138.1 [ 2009 ] IEEE. [ Reprinted, with permission, fr om H. Park, et al. Laser Induced Current Transients in Strained Si Diodes, IEEE Trans action on Nucl ear Sci ence IEEE Trans. Nucl. Sci., vol. 56, p. 3208, Table 1 Dec. 200 9 ] 3.4 Simulation Results and Discussion 3.4.1 Baseline Simulation R esults under No Stress Based on the previous experimental analysis, FLOODS simulations are performed to understand the mechanisms of carrier transport under uniaxial stress and to predict how high stress (~1GPa) affects the current transients in diodes. The Masetti and Br ooks Herring mobility models are used to account for carrier transport in a high injection case [113] Shockley Read Hall and Auger band to band recombination models are also considered [113, 114] The number and distribution of electron hole pairs generated by the laser pulse is calculated by a s ingle photon absorption (SPA) equation [99, 100]

PAGE 50

50 Figure 3 7 Schematic of laser induced current transients and 2 dimensional simulation structure of an N+/P diode [ Reprinted, with permission, from H. Park, et al. Laser Induced Current Transients in Strained Si Diodes IEEE Trans action on Nucl ear Sci ence IEEE Trans. Nucl. Sci., vol. 56, pp. 320 6 Figure 6, Dec. 200 9 ] Before analyzing the effects of stress on curr ent transients, baseline simulations under no stress are performed. These results are matched to the measured current transient under no stress. It is very important to understand the physics that dominates current transients in an unstressed case in order to predict the results under a stressed case. A 2 dimensional simulation structure, shown in Figure 3 7 is built based on analysis of the structure and material of the N+/P diodes, as shown in Figure 3 3 The width and depth of the diodes are 100 m and 10 m, respectively. The SiO x Cu dummy patterns, and NiSi are not implemented in the simplified FLOODS simulations.

PAGE 51

51 Figure 3 8 Simulated energy dependence of laser induced current transients [ Reprinted, with permission, from H. Park, et al. Laser In duced Current Transients in Strained Si Diodes IEEE Trans action on Nucl ear Sci ence IEEE Trans. Nucl. Sci., vol. 56, pp. 320 6 Figure 7, Dec. 200 9 ] However, the omitted layers can reduce laser energy due to the reflection, absorption, and transmission p roperties of each material [99, 106] Figure 3 8 shows that a decrease in laser pulse energy results in a decrease in the peak current and charge collection. The simulated result for the case of pulse energy of 13.5 pJ agrees with the experiment result, as sho wn in Figure 3 8 However, the pulse energy (13.5 pJ) is much different from the measured pulse energy (218 pJ). The discrepancy can be explained by the absorption, reflection, and transmission properties of each layer over the active region of the diode. Since 43% of the spot area of incident laser is occupied by Cu

PAGE 52

52 dummy patterns which block the laser [100] only 57% of incident laser energy is transmitted. Next, onl y 78% of the energy is transmitted through the 720 nm SiO x due to reflection losses at the interfaces [99] Lastly, 16% of the energy is transmitted through NiSi, based on [106] Therefore, the calculated pulse laser energ y reaching the diode active area is ~15.5 pJ, ~7.1% (= 0.57 x 0.78 x 0.16) of the incident energy. If the thickness of each layer varies by ~10% and the composition of the NiSi x also varies, the calculated laser energies range from 12.5 to 22 pJ. The c olle cted charge in the simulation (12.8 pC) agrees well with the average collected charge in the experiment (12.3 pC). As a result, the amount of energy used in the simulations to produce agreement with the experiments, 13.5 pJ, is reasonable. 3.4.2 Simulatio n Results under Stress coefficients as shown in Table 3 1 is used to consider mobility enhancement as a function of mechanical stress [110, 111, 114] T he 6 x 6 piezoresistive model is defined as (3 4) where ij ij ij and ij are components of the piezoresistance coefficient, ij / ij ij ij are fractional changes i n resistivity and mobility Since the doping densities and dopant type are different in each region of N+/P diode, t he doping dependence of the coefficients derived by Kanda [115] is used ( Figure 3 9 and 3 10 ) .The piezoresistance

PAGE 53

53 coefficient s are multiplied by piezoresistance factor, P(N,T) Temperature ( T ) used in the simulation is 300K, because the experiment was done in room temperature and no wafer heat ing effect is observed. Figure 3 9 Piezoresistance factor P(N,T) as a function of doping density ( N ) and temperature ( T ) for n type Si [ Reprinted, with permission, from Y. Kanda, "A Graphical Representation of the Piezoresistance Coefficients in Sili con," IEEE Trans. Electron Dev., vol. 29, pp. 6 8 Figure 8 Jan., 1982 ] Figure 3 10 Piezoresistance factor P(N,T) as a function of doping density ( N ) and temperature ( T ) for p type Si [ Reprinted, with permission, from Y. Kanda, "A Graphical Represent ation of the Piezoresistance Coefficients in Silicon," IEEE Trans. Electron Dev., vol. 29, pp. 6 8 Figure 8 Jan., 1982 ]

PAGE 54

54 Figure 3 11 Transformation of the Cartesian coordinates system for two demensional FLOODS simulation A ) original B ) transformed [116] Since two dimensional FLOOD simulation in N+/P diode are performed to minimize simulation complexi ty and reduce simulation time, a two dimensional piezoresistive model is used to pred ict the effect of uniaxial stress on current transient in N+/P diode. The details of transferring three to two d i mensional piezoreistive matrix are discussed by Cummings in detail [116] 3 X3 piezoresistive model for two di mensional simulation is expressed as (3 5) Since uniaxial stress is applied to the diodes along the <110> direction via a wa fer bending set up, the original Cartesian coordinates system is transf ormed to the modified Cartesian coordinates system for two di mensional simulation as shown in Figure 3 11 The transformed piezoresistive matrix for the new co rdinates system using directional cosine [110, 115, 116] is defined as

PAGE 55

55 (3 6) where ij ij ij and ij are components of the piezoresistance coefficient, mechanical ij / ij ij ij are fractional changes i n resistivity and mobility. Table 3 2 Values of transformed 5 MPa 1 ) used in two di mensional FLOODS [116] Electron Hole 11 31.2 71.8 13 53.4 1.1 33 102.2 6.6 44 13.6 138.1 The 3X3 piezoresistive matrix (3.6) for new coordinates system is implemented to simulate current transients in N+/P diodes as a function of <110> uniaxial stress. For <11 0> uniaxial stress, the value of both 33 and 13 are 0 MPa. T he range of 13 from 1GPa to 1GPa is used in FLOODS simulation, as shown in Figure 3 12 From Eq. ( 3 6 ), currents are calculated as a function of mechanical stress. Current densities are ex pressed as (3 7) where J i (0) and J i are current density components with and without stress based on a new transformed coordinate system, respectively.

PAGE 56

56 Figure 3 12 Simulated laser induced current trans ients as a function of <110> uniaxial mechanical stress [ Reprinted, with permission, from H. Park, et al. Laser Induced Current Transients in Strained Si Diode s IEEE Trans action on Nucl ear Sci ence IEEE Trans. Nu cl. Sci., vol. 56, pp. 320 7 Figure 8, Dec. 200 9 ] The simulated current transients in F igure 3 13 show the same trend as the experimental data in Figure 3 4 I max and Q in the simulations also agree with the experiments, as shown in Figure 3 13 and 3 1 4 The data points in the experiments are t he average I max and Q at each stress level. The error bars in the data points represent 95% confidence interval in the data at each stress level. The simulation results predict that I max and Q under 1 GPa of tensile stress will decrease by ~23% and ~21%,

PAGE 57

57 r espectively. Analogous to tensile stress, 1 GPa of compressive stress increases I max and Q by 17% and 13%, respectively. These experiment and simulation results for strained N+/P diodes show that uniaxial stress changes the shape of current transients and collected charges. Figure 3 13 Peak current ( I max ) in N+/P diodes as a function of mechanical stress. (positive (+) : tensile, negative ( ): compressive) [ Reprinted, with permission, from H. Park, et al. Laser Induced Current Transients in Strained S i Diodes IEEE Trans action on Nucl ear Sci ence IEEE Trans. Nucl. Sci., vol. 56, pp. 3203 3209 Dec. 200 9 ]

PAGE 58

58 Figure 3 1 4 Collected charges in N+/P diodes ( Q ) (positive (+) : tensile, negative ( ): compressive) [ Reprinted, with permission, from H. Park, et al. Laser Induced Current Transients in Strained Si Diodes IEEE Trans action on Nucl ear Sci ence IEEE Trans. Nucl. Sci., vol. 56, pp. 3203 3209 Dec. 200 9 ] 3.5 Correlation between T ransients in N+/P diode and nMOSFET To apply the strain engineering concepts for mitigat ing SETs and SEUs in deep submicron MOSFETs we need to understand the difference s and similarities between these large diodes and deep submicron MOSFETs T he junction area of the large junction N+/P diodes used in the experiment is mu ch larger than the diameter of the e h pair cloud generated by pulse laser or ion strike However, the size of source/drain junctions in submicron MOSFETs is expected to be comparable or smaller than that of a radiation generated e h pair cloud [117, 118] While out of plane transport of generated

PAGE 59

59 carriers dominates the current transient s in large N+/P diodes b oth out of plane and in plane transport of radiation generated carriers under mechanical stress should be c onsidered for scaled MOSFETs Therefore, it is very important to understand how current transients in submicron MOSFETs vary as a function of mechanical stress. Based on the N+/P diodes analysis, it is concluded that the piezoresistive mobility model is u seful to simulate current transients in devices as a function of uniaxial stress. FLOODS simulation in submicron nMOSFETs can predict the trend of peak current and collected charges as a function of uniaxial stress. Alpha particle induce d current transient s in process induced strained nMOSFETs was simulated using FLOODS by Cummings [116] The size of junction in nMOSFET is 0.1 m. The simulated peak current and collected charge trend s in ST I stressed nMOSFETs are similar to those measured in externally stressed N+/P diode s using the bending setup, as shown in Figure 3 1 5 and 3 16 With both STI induced stress and externally applied stress is present in the b ulk of the nMOSFET as well as the surface [116, 119 121] Similar to the N+/P diode case, Cummings suggested that the electro n mobility change along the <001 > direction is dominant factor for altering the shape of current transients in submicron nMOSFETs [116] For logic devices in commercial off the shelf (COTs) chips, <110> uniaxial stress is applied to the channel of nMOSFETs using tensile SiN capping layers [15 17] C arrier mobility along the channel (in plane) direction i s enhanc ed due to stress induced in the channel by the c apping layers [15, 122, 123] Unlike STI induced stress, the SiN capping layer induced stress is only confined to the surface of Si [116, 119, 121] Therefore, the simulated current transient in SiN capping layer induced stressed

PAGE 60

60 nMOSFETs done by Cummings shows no significant change compared to that in unstressed nMOSFET [116] Figure 3 1 5 Peak current ( I max ) in N+P diodes and nMOSFETs [116] as a function of mechanical stress. (positive (+) : tensile, negative ( ): compressive) Other process stressors such as the stress memorization technique (SMT) [17, 77, 124] and metal gate [21, 53] are emerging to apply stress to the channel in MOSFETs. Since the applied stress using these stressors is also confined to surface of Si [125] it is ex pected that there will be no significant change in current transients in SMT or metal gate induced stressed MOSFETs. Since strained Si engineering shows the potential to control the shape of SETs or enhance the device performance without degrading the devices, f urther experiment and simulation work is required to evaluate the effects of the

PAGE 61

61 process induced stress on the reliability of submicron MOSFETs under radiation environment Figure 3 16 Collected charges ( Q ) in N+/P diodes and nMOSFETs [116] (positive (+) : tensile, negative ( ): compressive) 3.6 Conclusion Uniaxial tensile stress in Si N+/P diodes decrease s the maximum peak current and collected charge for laser induced current transi ents. Quantitative analysis and FLOODS simulation results suggest that this can be attributed to the degradation of electron mobility along the <001> direction. U niaxial compressive stress shows the opposite trend. The simulated pe ak current and collected charge trend s in STI induced

PAGE 62

62 stressed nMOSFETs [116] agree with the experimental and simulated results in N+/P diodes. Therefore, uniaxial strain engineering has the potential to control t he shape of single event transients and the amount of charges collected in deep submicron nMOSFETs Furthermore, these results suggest that strained Si technology will have a significant beneficial impact on SETs and SEUs at the circuit level

PAGE 63

63 CHAPTE R 4 LASER INDUCED CURRENT TRAN SIENTS IN STRAINED SI P+/N DIODES 4.1 Introduction We studied the physics of l aser induced current transients in uniaxially stressed N+/P diodes in C hapter 3. It was understood that un i axial stress can alter the shape of the cur rent transient and change the amount of charge co llected due to the change in electron mobility [126] However, the effects of mechanical stress on current transients on P+/N diodes have not been reported T he effect s of externally applied uniaxial stress on hole current transients in Si P+/N diode s is investigated in this chapte r. The correlation between laser induced current transients in P+/N diode and alpha particle induced current transient in pMOSFETs is explained using FLOODS simulation, because t he P+/N diode are representative of the source/drain junctions that are responsible for hole charge collection in p MO SFETs [116] as shown in Figure 4 1 Figure 4 1 Motivation for measurement of P+/N diode

PAGE 64

64 4.2 Experiment al Set up Similar to the current transient measure ment in N+/P diodes in C hapter 3 laser i nduced current transients in P+/N diodes are measured under controlled external mechanical stress, appl ied via a four point bending setup [35] The samples are irradiated using a picosecond pulse d laser [99, 100] as shown in Fig ure 4 2 A direct measurement system is built to characterize transients in P+/N diode s [101, 102] The diode is connected to a ground signal ground (GSG) probe tip (DC to 40 GHz) a b ias t ee (10 kHz to 40 GHz) and a Tektronix TDS8200 digital sampling oscilloscope with 80E03 sam pling module (20 GHz bandwidth) A cavity dumped dye laser with a wavelength of 590 nm pulse energy of 5.9 pJ and pulsewidth of 1 ps is used to generate electron hole pairs in the diode. The laser is focused to a spot size of 6.3 m full width half maxim um diameter at zero degree incidence Hole c urrent transient s on the P+/N diode are measured for stress values ranging from 70 MPa compressive to 220 MPa tensile under 5 V reverse bias. Figure 4 2 Laser induced current transient measurement system in P+/N diode using a four point bending setup

PAGE 65

65 The samples used in this study are P+/N diode s on a ( 001 ) Si wafer fabricated by a standard 130 nm CMOS technology similar to the N+/P case in C hapter 3 Large active area diodes ( 50 m 100 m ) are used for th e experiment. The d oping densities of the P+ N well, and P substrate are ~10 20 ~ 5X 10 1 7 and ~10 16 cm 3 respectively [104] The P+ and N well depths are ~ 0.1 m and ~2 m. Transmission electron microscopy ( TEM ) and energy dispersive X ray spectroscopy ( EDS ) analyses show that n ickel s ilicide (NiSi), s ilicon o xide (SiO x ), and c opper (Cu) dummy patterns are present on the top of t he diode, as shown in Figure 3 3 The thickness es of the NiS i, SiO x and Cu layers are 20 nm, 720 nm, and 280 nm respectively 4.3 Experimental R esults and Discussion The effect of stress on the peak current and charge collection is characterized by monitoring laser induced current transient s in P+/N diodes for varying mechanical uniaxial stress values as shown in Figure 4 3 Tensile stress increases both peak current ( I max ) and collected charge ( Q ) for the moderate range of stress considered in these experiments as shown in Fig ure 4 7 and 4 8 However, compress ive stress decrease s Q and I max Q is obtained by integrating the measured current transient as a function of time. The n ormalized c hange in I max as a function of uniaxial stress is observed to be larger than that in Q T he percent changes of I max and Q ar e ~2.9 % and 0.9% at 100 MPa, respectively. Similar to previous results on the N+/P diode that showed a decrease (increase) in electron carrier mobility along the <001> direction and a decrease (increase) in peak current and collected charge [126] hole mobility along the <001> direction may be dominant factor for explaining the stress dependence of I max and Q in P+/N diode.

PAGE 66

66 Figure 4 3 Laser induced current transients in P+/N diode as a function of <110> uniaxial mechanical stress. To understand the nature of the dominant mechanism for chang e I max and Q in the P+/N diode as function of uniaxial stress, it is very im portant to understand the concept of piezoresistance The stress dependence of hole current transients can be analyzed using coefficients in Si [110, 111] T coefficient represents the normalized change of mobility resulting from coef = / ( o ) where is the amount of applied stress and o is the mobility with no stress ) The extracted change of hole mobility along the <001> direct ion ( ) from I max and Q measured as a function of stress, as shown in Fig. 4 6 and 4 7 is ~ 2.9 % a nd ~ 0.9 % at 100 MPa,

PAGE 67

67 respectively. However, b ased on previous results in Si done by Smith et al. [111] due to uniaxial mechanical stress is expected to be only ~ 0. 1 % at 100 MPa [110, 111] The extracted from I max (~2 .9% at 100 MPa) is much larger than the calculated from the coefficients ( ~ 0. 1 % at 100 MPa ) [111] Since the calculated from the coefficients is much smaller than other from the coefficients coefficients in other directions could be contributing to the observed larger peak current change in the exp eri ment. The extracted from Q in the experiment (~ 0. 9 % at 100 MPa) is within experimental error of the calculated from the coefficients ( ~ 0. 1 % at 100 MPa ) [111] Since Q comes from integrating current transients as a function of time, it may represent the average change of hole mobility as a function of time. In a later section in t his chapter discussing the correlation between P+/N diode and pMOSFET s, we will clarify which coefficient component dominates the peak current and collected charge in P+/N diode and pMOSFETs, respectively. We first present detailed F LOODS simulation results on uniaxially stressed P+/N diodes i n the following section. These results are important f or understanding some aspects of the corre lation between P+/N diodes and p MOSFETs. 4.4 Simulation R esults and Discussion FLOODS is used to understand the primary contributi ng mechanism s in hole current transient s in P+/N diode s and to predict how high str ess (~ 1GPa) can affect I max and Q Similar to the pre vious N+/P diode simulation in C hapter 3, Shockley Read Hall and Auger band to band recombination model s are used [113, 114] A single photon absorption (SPA) equation [99, 100] for the photon energy (2.1e V) above Si band gap (1.1eV) is also considered to calculate the number and distribution of electron hole pair generation A unified mobility model developed by Cummings [127] considering

PAGE 68

68 Figure 4 4 Details of two dimensional structure of 100 m junction size P+/N diode in FLOODS A) simulation structure B ) grid

PAGE 69

69 majority carrier mobili ty, minority carrier mobility, carrier carrier scattering, and temperature dependence is used to simulate carrier transport in the high injection case A p iezoresistive mobility model based on Smith s coefficients [110, 111, 114] is used to simulate carrier mobili ty enhancement as a function of mechanical stress because N+/P diode results in C hapter 3 show that it is a useful model for simulating the effect of mechanical stress on current transients. The two dimensional device structure and grid used for P+/N diode simulations in FLOODS are shown in Figure 4 4 T he width and depth of the simulation structure are 120 m and 10 m, respectively. The P+ junction width is 100um. Shallow trench Isolation (STI) separate s the P+ contact from the N well contact to allow bot h contacts to be present on the top of the simulation structure. There is n o intentional STI stress in the structure. N+ doping ( 10 20 cm 3 ) is implemented to reduce the contact resistance of the N well. The applied bias of P+ and N+ are 5V and 0V, respect ively Current transient simulations in the P+/N diode under no stress are performed to understand the dominant physics. The range of transmitted energy through the Cu metal pattern, SiO x and NiSi x layers is calculated to be ~ 0.32 to 0.7 pJ, considering the optical properties such as reflection, transmission, and absorption in each layer [99, 106] T he method for calculating the amount of laser energy reaching the active a rea of diodes was explained in C hapter 3. The simulated current transient with pulse ene rgy of 0.65 pJ matches the experiment al r esult, as shown in Figure 4 5 It is reasonable to use 0.65 pJ in the simulation because the value is within the calculated range of energy from ~ 0.32 to 0.7 pJ.

PAGE 70

70 Figure 4 5. Comparison of experiment with simulat ion of current transient s in P+/N diode s under no stress The simulated current transient in Figure 4 6 agrees with the experimental results in Figure 4 3. The extracted value of I max and Q as a function of <110> uniaxial stress from the simulations (Figu re 4 6) have comparable trends to those in the experiments as shown in Figure 4 7 and 4 8. The simulation results predict a decrease in I max and Q under 1 GPa of compressive uniaxial stress of ~ 17% and ~1%, respectively. In the case of 1 GPa of tensile un iaxial stress, I max and Q are expected to increase by ~ 12.5 % and 1.4%, respectively. The interesting point here is that the normalized change in I max is 10 times larger than the normalized change in Q in the P+/N diode case. This is in stark c ontrast to the N+/P diode case where the normalized change in I max and Q were comparable to each other. As briefly discussed in the experimental results, this

PAGE 71

71 phenomenon in the P+/N diodes could arise from differences in electron and hole mobility in the <001> and <1 10> directions. C hanges of hole mobility along the <110> direction or electron mobility along the <001> or <110> direction s may affect the hole peak current due to very small change of hole mobility along the <001> direction (~1.1% at 1GPa of uniaxial stre ss). In the next section discussing the correlation between P+/N diodes and pMOSFETs, we investigate which of the three mobilities (hole mobility in <110>, electron mobility in <110> and electron mobility in <001>) could be the dominant factor for determin ing the normalized change in I max and Q in the P+/N diode. Figure 4 6 Simulated laser induced current transients in P+/N diode as a function of <110> uniaxial mechanical stress

PAGE 72

72 Figure 4 7 Change in p eak current ( I max ) in P+/N diode as a function of <110> uniaxial stress ( positi ve (+): tensile, negative ( ) : compressive) Figure 4 8 C hange in collected charge ( Q ) in P+/N diode as a function of <110> uniaxial stress ( positi ve (+): tensile, negative ( ) : compressive)

PAGE 73

73 4.5 Correlation between T ransients in P+/N diode with pMOSFET To provide p hysical insight into the impact of uniaxial strain engineering on single event transients (SETs) in deep sub micron p MOSFETs, simulation results of alpha particle induced transients in p MOSFETs with process induced strain are compared with those of laser induced transients in P+/N diodes. Previous simulation results by Cummings [116] on alpha particle induced current transient i n uniaxial co mpressive stressed pMOSFETs ( by SiN capping layer and SiGe epitaxial growth ) show that there is no significant difference of hole peak current and collected charge between the unstressed and stressed cases. S tress from the SiN capping layer and SiGe epitax ial growth is confined near the Si surface [116, 119, 121] Therefore, he suggested that there is negligible impact on the transient shape and amount of collected charge due to stress However, he also suggested that shallow trench isolation (STI) extending deep into the bulk Si [116, 119 121] similar to wafer bending (or global stress) can change the peak current a nd collected charge in MOSFETs. While simulation results of alpha particle induced transients in STI stressed nMOSFE Ts has been reported [116] the effect s of uniaxial stress on SETs in STI stressed pMOS FET have not been investigated yet. In this section, simulation results o n alpha particle induced transients in STI stressed submicron pMOSFETs are presented. T he two dimensional device stru cture and grid used for pMOSFET simulations i n FLOODS are shown in Figure 4 9 The physical gate length of p MOSFETs used in the FLOODS simulation is ~ 35 nm [116, 128] The width and depth of the simulation structure are 0.6 m and 5 m, respectively. The P+ junction width is 0.1um. Shallow trench Isolation (STI) separate s the P+ contact from the N well contact to allow both contacts on the top of the simulation structure. N+ doping ( 2X 10 20 cm 3 ) is

PAGE 74

74 Figure 4 9 Details of t wo di menisional structure of 0.1 m junction size pMOSFET used in FLOODS A ) device details B ) grid

PAGE 75

75 Figure 4 10 Change in p eak current ( I max ) in pMOSFETs and P +/N diode as a function of <110> uniaxial stress ( positi ve (+): tensile, negative ( ) : compressive) implemented to reduce the contact resistance of the N well. The d oping densities of the P+, N well, and p substrate are 2X 10 20 10 1 8 and ~10 16 cm 3 res pectively The applied drain bias in pMOSFET is 1V. Gate, source, and body in the device are grounded. Florida Object Oriented Process Simulator (FLOOPS) simulation tool [103] is used to create uniaxial stress using STI along t he < 110> channel direction. Similar to the diode experiments, a piezoresistive mobility model based on Smith s coefficients [110, 111] is used to simulate mobility enhancement under mechanical stress. To induce the current transient, a 1 MeV alpha particle strike on the drain of the p MOSFET is considered so as to represent the worst case scenario [116] T he 1/e radius of the alpha particle is 50 nm [129] The electron hole pair distribution is assumed to be Gaussian [114, 129]

PAGE 76

76 We previously observed similar trend between transients in N+/P diodes and nMOSFETs in C hapter 3 However, the simulated peak current results in STI stressed pMOSFETs are opposite to the experiment a nd simulated results in external bending stressed P +/N diode as shown in Figure 4 10 We systematical ly investigate the following factors to identify the dominant contributor to the observed difference between P+/ N and pMOSFETs: 1. Method of stress introduction ( external bending stress vs STI) 2. Differences in simulation conditions (a) bias (b) radiation so urce and (c) junction size We simulate alpha particle induced transients in external bending stressed pMOSFETs and compare the simulation results to those of STI induced stress in Figure 4 10 I t was observed that t he simulated peak current trend in extern al bending stressed pMOS FETs is opposite to those in external bending stressed P+/N diodes. However, the simulated peak current trend in external bending stressed pMOSFETs are comparable to those in STI induced stressed pMOSFET. Since STI induced stress ex tending deep into the bulk Si [116, 119, 121] is similar to that applied via w afer bending, the comparable simulated results of peak and collected charge trends in external bending and STI induced stressed pMOSFET are reasonable Next, we study the effect of differing bi as conditions ( 5V in P+/N diode and 1V in pMOSFETs), differing radiation sou r ce (laser in P+/N diode and alpha particle in pMOSFETs), and differing junction size (100 m in P+/N diode and 0.1 m in pMOSFET) Simulation results show that the p eak current trend is independent of radiation source and bias condition. However, junction size differences play an important role as shown in Figure 4 11

PAGE 77

77 Figure 4 11 Change in p eak current ( I max ) in P+/N diode with <110> uniaxial stress and pMOSFETs under <110 > uniaxial stress with different junction size ( positi ve (+): tensile, negative ( ) : compressive) As junction size in pMOSFETs decrease s from 100 m to 0.1 m, it is observed that the peak current trend in pMOSFETs as function of stress is changed, as sh own in Figure 4 11 The p eak current trend in large junction size pMOSFETs such as 100 m and 10 m is similar to those in 100 m junction P+/N diodes qualitatively. However, the peak current trend in small junction size in pMOSFETs such as 1 m and 0.1 m is opposite to those in 100 m junction P+/N diode. Since the junction size in the submicron pMOSFETs simulation structure is ~ 0.1 m, the simulated peak current trend in pMOSFETs is o pposite to those in 100 m junction P+/N diode. Based on these simulat ion results in Figure 4 11 it is concluded that there is a correlation between the peak current trend and the junction size. The differences in the junction size lead to differences in charge transport /collection mechanisms between the P+/N diodes and pM OSFET cases. Keeping in mind that the junction sizes in today's MOSFETs are about 0.1 um or smaller, it becomes quite important to understand the differences in

PAGE 78

78 transport/collection effects between large junction (100 m) P+/N diode and small junction (0.1 m) pMOSFET The physics of the differing charge transport/collection coefficients involved in these two structures. To evaluate which coefficient component dominates the normalized change of peak curr ent in 0.1 m junction pMOSFET and 100 m junction P+/N diode respectively, multiple simulations, each considering only one single coefficient are performed using a 3X3 piezoresistive matrix as described in C hapter 3 For convenience, we revisit the peiz oresistive matrix equation described earlier: (5 1) where ij ij ij and ij are components of the piezoresistance coefficient, mechanical ij ij are frac tional changes i n and mobility in the transformed coordinate system, as shown in Figure 3 11 F or example, the 2 D piezoresi s tance matrix only considering 11 of hole under uniaxial stress along the <110> direction is expressed as (5 2 ) where 11, h 11 and ij ,h are components of the piezoresistance coefficient, mechanical stress, and hole carrier mobility ij ,h ij ,h are fractional changes i n hole mobility in the transformed coordinate system respectively, as s hown in Figure 3 11

PAGE 79

79 Separate FLOOD S simulations considering 11 and 13 individually for electrons and holes are performed as shown in Figure 4 12 and 4 13 The peak current trend in external bending stressed 0.1 m junction pMOSFETs is similar to thos e considering only 11 of hole, as shown in Figure 4 12 The peak current trend in external bending stressed 100 m junction P+/N diode agrees with those considering only 11 of ele ctron, as shown in Figure 4 13 These results provide insight about the d ifferent dominant coefficients that alter the peak current trend in small 0.1 m junction pMOSFET and large 100 m junction P+/N diode cases due to the very small change in hole mobility along the <001> direction (~1.1 % at 1GPa of uniaxial stress) Hole concentration contour plots at peak current conditions ( Figure 4 1 4 and Figure 4 1 5 ) are used to visualize how 11 of hole and electron could dominate peak current in small 0.1 m junction pMOSFETs and 100 m junction P+/N diode respectively. Since the hole concentration contour spreads and becomes larger than the junction size, it is highly possible that hole s need to travel along the <110> direction in order to be collected at the P+ junction as shown in Figure 4 1 4 for 0.1 m junction pMOSFETs Therefo re, 11 of hole (the change in hole mobility along the <110> direction) dominates peak current trend in 0.1 m junction pMOSFETs as a function of mechanical stress. In contrast to the 0.1 m junction pMOSFETs holes in the 100 m junction pMOSFET are confined to large P+ junction Thus, these holes do not have to travel along the horizontal <110> direction to be collected in P+ junction. The phenomenon is expected to be similar to that of large 100 m junction P+/N diode shown in Figure 4 15 Therefore, a s sho wn in Figure 4 11 the simulated peak current trend in 100 m junction

PAGE 80

80 pMOSFET as a function of <100> uniaxial stress is observed to be similar to the peak current trend in 100 m junction P+/N diode Using the coefficient simulation results on 100 m junction P+/N diode (Figure 4 13 ), we can understand why the peak current in large junction size device such as 100 m junction pMOSFET and P+/N diode can be affected by 11 of electron (the change in electron mo bility along the <110> direction) T he interesting point in the 100 m junction P+/N diode case is that the 11 of electron dominates the change in peak current as a function of stress, even if the amount of electron collected in P+ junction is less than 0.001% of peak current. To understand why 11 of electron dominates the hole peak current in the P+/N, we should understand how current transient simulations are performed in FLOODS, using the quasi Fermi method [130 132] The method involve s self consistently solvin g for three quantities device potential (bulk and surface), quasi Fermi potential of hole, and quasi Fermi potential of electron using Poisson equation and electron/hole current continuity equations. A change in electron mobility (with stress) in the c urrent continuity equations can affect both the hole quasi Fermi potential and the device potential. As a result, the hole concentration and the gradient of the hole quasi Fermi potential are also affected, both of which control the hole peak current. Thus the electron mobility change (with stress) is self consistently fed back into the hole current through the Poisson equation. This feedback mechanism is most likely to be responsible for the change in the peak (hole) current in the P+/N diode when uniaxial stress is present in the device.

PAGE 81

81 Figure 4 1 2 Change in peak current ( I max ) in 0.1 m junction pMOSFETs with each coefficient component as a function of <110> uniaxial stress ( positi ve (+): tensile, negative ( ) : compressive) Figure 4 1 3 Chang e in peak current ( I max ) in 100 m junction P+/N diode with each coefficient component as a function of <110> uniaxial stress ( positi ve (+): tensile, negative ( ) : compressive)

PAGE 82

82 Figure 4 14 Hole concentration contour at peak current in unstressed 0. 1 m junction pMOSFET Figure 4 15 Hole concentration contour at peak current in unstressed 100 m P+/N diode

PAGE 83

83 Overall, due to very small change in hole mobility along the <001> direction (~1.1 % at 1GPa of uniaxial stress), different coefficients produce the opposite peak current trend between 100 m junction P+/N diodes and 0.1 m j unction pMOSEFETs. However, in C hapter 3, the same peak current trend in the case of 100 m junction N+/P diodes and 0.1 m junction nMOSFETs cases was observed. It is du e to large change in electron mobility along the <001> direction (~53.4 % at 1 GPa of uniaxial stress), which dominates peak current in 100 m junction N+/P diodes and 0.1 m junction nMOSFETs. Figure 4 16 Change in peak current ( I max ) in P+/N diode and pMOSFETs as a f unction of <110> uniaxial stres s. ( positi ve (+): tensile, negative ( ) : compressive)

PAGE 84

84 FLOODS simulations predict that the simulated peak current and collected charge trend in 100 um junction pMOSFETs is similar to those in 100 um P+/N diode .(Figur e 4 16 and 4 17 ). It is also seen from simulations that a decrease in peak current and collected charge in 0.1 m junction pMOSFETs would be observed with increasing STI induced tensile stress, as shown in Figure 4 16 and 4 17 It has been reported [116] that an increase in STI induced tensile stress also results in a decrease in peak current and collected charge in small 0.1 m junction nMOSFETs. Since junction size in deep submicro n MOSFETs is equivalent to or less than 0.1 m, tensile STI stress along the <110> direction is expected to be beneficial for decreasing the peak current and collected charge in both deep submicron n and pMOSFETs. Figure 4 17 Change in collected char ge ( Q ) in P+/N diode and pMOSFETs as a function of <110> uniaxial stress ( positi ve (+): tensile, negative ( ) : compressive)

PAGE 85

85 Simulation results of current transients in STI stressed n and pMOSFETs and other process stressed n and pMOSFETs (SiN capping l ayer and epitaxial growth) [116] provide insight about how strain engineering can impact drive current enhancement and single event transient (SET) response. Fortunately, in nMOSFETs, inco rporating tensile SiN capping layer and STI induced stress is expected to increase drive current (mobility) enhancement and decrease peak current and collected charge simultaneously [116, 133, 134] However, we should carefully engineer surface and bulk stress to optimize drive current enhancement and SET response (peak current and collected charge) in pMOSFETs. C ompressive stress enhances driv e current in pMOSFET [15, 17, 18, 38] but tensile stress decreases peak current and collected charge. Compressive SiN capping and SiG epitaxial layer introduce stress that is confined to surface of pMOSFET [116, 119, 121] Since the drive current enhancement is related to surface stress engineering, these two stressors improve drive current without adversely impacting SET response [116 ] Tensile STI stress decreases peak current and collected charge in pMOSFET, because it can extend deeper into bulk of the device. When tensile STI stress is present simultaneously with compressive SiN capping layer/SiGe epitaxial layers, the tensile nat ure of STI stress somewhat compensates the compressive stress in the surface of the device induced by SiN capping layer and SiGe epitaxial layer. Typically, compressive stress induced by SiN capping layers and SiGe epitaxial growth (~ 2.4 GPa) [76, 77] is larger than the tensile stress introduced by STI (~1GPa) in the surface of th e device [116] Therefore, some amount of compressive stress would be still present in the surface even after compensation. This compressive stress will

PAGE 86

86 enhance the drive current ( through hole mobility improvement). Since the bulk of the device is under tensile stress from the STI, the SET response is also improved simultaneously. Thus, by choosing a proper combinat ion of stress levels, it is possible not to degrade device performance while having all three stressors (compressive SiN capping, compressive SiGe epitaxial layer, and tensile STI) concurrently From a design perspective, a trade off between drive current enhancement and SET response from uniaxial strain engineering should be cons idered while designing transistors for radiation hardened applications. 4.6 Conclusion P eak current and collected charge trend s in small 0.1 m junction pMOSFETs as a function of uniaxial stress are found to be opposite to those in 100 m junction P+/N di ode. F o r 0.1 m junction pMOSFETs, the main contribution for the observed stress induced change in peak current and collected charge comes from the stress induced changes in hole mobility change along the <110> direction. For 100 m junction P+/N diode th e electron mobility change along the <110> direction is the main contributor. Based on our findings, we recommend tensile STI a s a good candidate to mitigate SETs and SEUs in deep submicron p MOSFETs in agreement with [116] The STI induced tensile stress extends both in the surface and bulk as is well known [116, 119 121] For nMOSFET devices, the addition of tensile STI is completely beneficial both drive curre nt and SET response is improved simultaneously For pMOSFET devices, the amount of tensile stress introduced by STI needs careful consideration T h e use of multiple surface strain stressors (SiN capping layers and SiGe epitaxial layers) and bulk strain eng ineering (using tensile STI) would likely be necessary to ensure that there is no degradation in device performance while improving SET response. Previous results

PAGE 87

87 on total ionizing dose effect s on strained MOSFETs indicat e that the benefit s of strain in th e channel region are maintained after irradiation [133, 134] Therefore, uniaxial strain ed Si technology is an attractive option for space appl ications.

PAGE 88

88 CHAPTER 5 SUMMARY AND RECOMMEN DATION FOR FUTURE WO RK 5.1 Summary T he effect of uniaxial stress on (a) threshold voltage shift and carrier mobility in n MOSFETs under radiation and (b) current transients in Si diodes under radiation are studied in this work Controlled external uniaxial stress is applied via a four point bending setup while the devices are irradiated. Device simulation using FLOODS is used to understand the effect of uniaxial stress on current transients in Si diodes. Radiation i nduced charge trapping and mobility degradation are investigated in uniaxially stressed HfO 2 based nMOSFETs. Both uniaxial t ensile and compressive stress in nMOSFETs are beneficial in reduc ing the threshold voltage shift resulting from decreasing the amoun t of positive charges in HfO 2 and/or SiO x The reduction of threshold voltage shift is attributed to the reduced trap activation energy in HfO 2 and/or SiO x for devices under stress. There is no significant electron mobility degradation in uniaxially stres sed nMOSFETs after a total dose of 5 Mrad(SiO 2 ) irradiation. These results provide the insight that uniaxial strain engineering has the potential to enhance the transistor performance without incurring significant radiation damages. Electron current trans ients in unia xially stressed N+/P diodes are studied both experimentally and theoretically U niaxial tensile stress in the diodes decrease s the maximum peak current and collected charge for laser induced current transient in N+/P diodes U niaxial compressi ve stress shows the opposite trend. Device simulations performed using FLOODS validate the experimental results. Using the peizoresistive mobility model implemented in FLOODS, it is possible to predict the effect of high (~1GPa) uniaxial stress on current transients in N+/P diode. Quantitative analysis of

PAGE 89

89 experimental results and FLOODS simulation results suggest s that the change in peak current/collected charge can be attributed to the change in the electron mobility along the <001> direction. The trends o bserved in our analysis of peak current and collected charge in externally stressed N+/P diode directly correlate to the results in STI stressed nMOSFETs as explained in [116] Similar to analysis of electron current transient in N+/P diode, hole current transients in P+/N diode and pMOSFETs are also investigated as a function of uniaxial stress. Increasing tensile (compressive) stress results in an increase (decrease) in peak current and collected charge in P+/N diode. However, the trends observed in the peak current and collected charge in externally stressed P+/N diode do not correlate to those observed in pMOSFETs, unlike N+/P diodes and nMOSFETs. Very small hole mobility change along the <001> direction as a function of uniaxial stress (~1.1% at 1GPa) [111] and different junction size (~0.1 m in pMOSFET and 100 m in P+/N diode) lead to opposite trends observed between P+/N and pMOSFETs. The dominant factor for increasing/decreasing peak current and collected charg e in P+/N diode and pMOSFETs is most likely electron mobil ity change along <110> direction and hole mobility change along the <110> direction, respectively. Based on simulation results in STI stressed nMOSFETs [116] and pMOSFETs tensile STI is a good candidate to mitigate SETs and SEUs in deep submicron p MOSFETs, because it is possible to introduce stress into the Si bulk region [116, 119 121] Previous results on TID effect s on strained MOSFETs indicat e that the benefi t s of strain in the channel region are maintained after irradiation [133, 134] Therefore,

PAGE 90

90 commercial uniaxial strain ed Si technology is an att ractive cost effective option for space applications. 5.2 Recommendation for Future Work The thickness of high k dielectrics reduces with continued MOSFET scaling. Although radiation induced charge trapping in thinner high k dielectrics has been studied re cently, the effect of uniaxial stress on radiation induced charge trapping and mobility degradation in such devices has not reported yet. Therefore, it is very important to research on TID effects on these devices. This work focused on understanding the p hysics and modeling of radiation effects as a function of stress at the device level. A study on the effects of uniaxial stress on SETs and SEUs at the circuit level (using simple circuits such as inverters, ring oscillators, and SRAMs) is strongly recomme nded to further investigate the viability of uniaxial strain engineering for radiation hardened technology. Additionally, other destructive radiation damages, SEGR and SEB, in uniaxially stressed devices are recommended for investigation.

PAGE 91

91 LIST OF REFEREN CES [1] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices : Cambridge Univ. Press, 1998. [2] S. E. Thompson and S. Parthasarathy, "Moore's law: the future of Si microelectronics," Materials Today, vol. 9, pp. 20 25, May 2006. [ 3] G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, 1965. [4] Intel, http://www.intel.com/about/companyinfo/museum/exhibits/moore.htm. [5] Intel, "Moore's law," http://download.intel.com/museum/Moores_Law/Printed_Materials/Moores_Law_2 pg.pdf [6] Intel, "Moore's law," http://download.intel.com/museum/Moores_Law/Printed_Materials/Moores_Law_P oster_Ltr.pdf [7] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. S. P. Wong "Device scaling limits of Si MOSFETs and their application dependencies," Proceedings of the Ieee, vol. 89, pp. 259 288, Mar 2001. [8] R. W. Keyes, "Fundamental limits of silicon technology," Proceedings of the Ieee, vol. 89, pp. 227 239, Mar 2001. [9] J D. Plummer and P. B. Griffin, "Material and process limits in silicon VLSI technology," Proceedings of the Ieee, vol. 89, pp. 240 258, Mar 2001. [10] Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S. H. Lo, G. A. SaiHalasz, R. G. Viswanatha n, H. J. C. Wann, S. J. Wind, and H. S. Wong, "CMOS scaling into the nanometer regime," Proceedings of the Ieee, vol. 85, pp. 486 504, Apr 1997. [11] ITRS, http://www.itrs.net/ [12] S. E. Thompson, R. S. Chau, T. Ghani, K. Mistry, S. Tyagi, and M. T. Bohr, "In search of "Forever," continued transistor scaling one new material at a time," IEEE Trans. Electron Dev., vol. 18, pp. 26 36, 2005. [13] G. Q. Zhang and A. v. Roosmalen, "The Changing Landscape of Micro/Nanoelectronics ," in More than Moore : Springer, 2009.

PAGE 92

92 [14] V. Chan, R. Rengarajan, N. Rovedo, Wei Jin, T. Hook, P. Nguyen, Jia Chen, E. Nowak, Xiang Dong Chen, D. Lea, A. Chakravarti, V. Ku, S. Yang, A. Steegen, C. Baiocco, P. Shafer, Hung Ng, Shih Fen Huang, and C. Wann "High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering," in IEDM Tech. Dig. 2003, pp. 3.8.1 3.8.4. [15] S. E. Thompson, N. Anand, M. Armstrong, C. Auth, B. Arcot, M. Alavi, P. Bai, J. Bielefeld, R Bigwood, J. Brandenburg, M. Buehler, S. Cea, V. Chikarmane, C. Choi, R. Frankovic, T. Ghani, G. Glass, W. Han, T. Hoffmann, M. Hussein, P. Jacob, A. Jain, C. Jan, S. Joshi, C. Kenyon, J. Klaus, S. Klopcic, J. Luce, Z. Ma, B. McIntyre, K. Mistry, A. Murth y, P. Nguyen, H. Pearson, T. Sandford, R. Schweinfurth, R. Shaheed, S. Sivakumar, M. Taylor, B. Tufts, C. Wallace, P. Wang, C. Weber, and M. Bohr, "A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1um 2 SRAM cell," in IEDM Tech. Dig. 2002, pp. 61 64. [16] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Y. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani K. Mistry, M. Bohr, and Y. El Mansy, "A logic nanotechnology featuring strained silicon," IEEE Electron Dev. Lett., vol. 25, pp. 191 193, Apr. 2004. [17] S. E. Thompson, G. Y. Sun, Y. S. Choi, and T. Nishida, "Uniaxial process induced strained Si: Extend ing the CMOS roadmap," IEEE Trans. Electron Dev., vol. 53, pp. 1010 1020, May 2006. [18] S. E. Thompson, S. Suthram, Y. Sun, G. Sun, S. Parthasarathy, M. Chu, and T. Nishida, "Future of Strained Si/Semiconductors in Nanoscale MOSFETs," in IEDM Tech. Dig. 2006, pp. 1 4. [19] S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson, "Piezoresistance coefficients of (100) silicon nMOSFETs measured at low and high (similar to 1.5 GPa) channel stress," IEEE Electron Dev. Lett., vol. 28, pp. 58 61, Jan. 2007. [ 20] M. Bohr, "Silicon Technology for 32 nm and Beyond System on Chip Products," in Intel Developer Forum 2009. [21] P. Packan, S. Akbar, M. Armstrong, D. Bergstrom, M. Brazier, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He*, R.Heussn er, R. James, J. Jopling, C. Kenyon, S H. Lee, M. Liu, S. Lodha, B. Mattis, A. Murthy, L. Neiberg, J. Neirynck, S. Pae, C. Parker, L. Pipes, J. Sebastian, J. Seiple, B. Sell, A. Sharma, S. Sivakumar, B. Song, A. St. Amour, K. Tone, T. Troeger, C. Weber, K. Zhang, Y. Luo, and S. Natarajan, "High Performance 32nm Logic Technology Featuring 2nd Generation High k + Metal Gate Transistors," in IEDM Tech. Dig. 2009, pp. 28.4.1 28.4.4.

PAGE 93

93 [22] P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. He ussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S. H. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, and M. Bohr, "A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low k ILD and 0.57 um2 SRAM cell," in IEDM Tech. Dig. 2004, pp. 657 660. [23] K. Mist ry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakuma r, P. Smith, C. Thomas, T. T. Roeger, P. Vandervoorn, S. Williams, and K. Zawadzki, "A 45 nm logic technology with high k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb free packaging," in IEDM Tech. Dig. 2007, pp. 247 250. [24] Chris Auth, Mark Buehler, Annalisa Cappellani, Chi hing Choi, Gary Ding, Weimin Han, Subhash Joshi, Brian McIntyre, Matt Prince, Pushkar Ranade, Justin Sandford, and Christopher Thomas, "45nm High k+Metal Gate Strain Enhanced Transistors," Intel Technology Journal, vol. 12, pp. 77 85, 2008. [25] P. E. Dodd and L. W. Massengill, "Basic mechanisms and modeling of single event upset in digital microelectronics," IEEE Trans. Nucl. Sci., vol. 50, pp. 583 602, Jun 2003. [26] T. R. Ol dham and F. B. McLean, "Total ionizing dose effects in MOS oxides and devices," IEEE Trans. Nucl. Sci., vol. 50, pp. 483 499, Jun. 2003. [27] G. Y. Sun, Y. K. Sun, T. K. Nishida, and S. E. Thompson, "Hole mobility in silicon inversion layers: Stress and su rface orientation," J. Appl. Phys., vol. 102, Oct. 2007. [28] Y. Sun, G. Sun, S. Parthasarathy, and S. E. Thompson, "Physics of process induced uniaxially strained Si," Materials Science and Engineering B Solid State Materials for Advanced Technology, vol. 135, pp. 179 183, Dec. 2006. [29] Y. Sun, S. E. Thompson, and T. Nishida, "Physics of strain effects in semiconductors and metal oxide semiconductor field effect transistors," J. Appl. Phys., vol. 101, May 2007. [30] H. M. Manasevit, I. S. Gergis, and A. B. Jones, "Electron Mobility Enhancement in Epitaxial Multilayer Si Si1 Xgex Alloy Films on (100) Si," Appl. Phys. Lett., vol. 41, pp. 464 466, 1982.

PAGE 94

94 [31] R. People, J. C. Bean, D. V. Lang, A. M. Sergent, H. L. Stormer, K. W. Wecht, R. T. Lynch, and K. Bal dwin, "Modulation Doping in Gexsi1 X/Si Strained Layer Heterostructures," Appl. Phys. Lett., vol. 45, pp. 1231 1233, 1984. [32] K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Ba bich, R. Carruthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, "Fabrication and mobility characteristics of ultra thin strained Si directly on insulator (SSDOI) MOSFETs," in IEDM Tech. Dig. 2003, pp. 3.1.1 3.1.4. [33] M. V. Fischetti, Z. R en, P. M. Solomon, M. Yang, and K. Rim, "Six calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness," J. Appl. Phys., vol. 94, pp. 1079 1095, Jul 15 2003. [34] J. S. Lim, S. E Thompson, and J. G. Fossum, "Comparison of threshold voltage shifts for uniaxial and biaxial tensile stressed n MOSFETs," IEEE Electron Dev. Lett., vol. 25, pp. 731 733, Nov. 2004. [35] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, "Key differen ces for process induced uniaxial vs. substrate induced biaxial stressed Si and Ge channel MOSFETs," in IEDM Tech. Dig. 2004, pp. 221 224. [36] Y. S. Choi, J. S. Lim, T. Numata, T. Nishida, and S. E. Thompson, "Mechanical stress altered electron gate tunne ling current and extraction of conduction band deformation potentials for germanium," J. Appl. Phys., vol. 102, pp. 104507 5, Nov. 2007. [37] J. S. Lim, X. Yang, T. Nishida, and S. E. Thompson, "Measurement of conduction band deformation potential constant s using gate direct tunneling current in n type metal oxide semiconductor field effect transistors under mechanical stress," Appl. Phys. Lett., vol. 89, pp. 073509 3, Aug. 2006. [38] S. Suthram, "Study of the piezoresistive properties of Si, Ge, and GaAs M OSFETs using a novel flexure based wafer bending setup ." Ph D Dissertation, University of Florida, 2008.

PAGE 95

95 [39] H. S. Yang, R. Malik, S. Narasimha, Y. Li, R. Divakaruni, P. Agnello, S. Allen, A. Antreasyan, J. C. Arnold, K. Bandy, M. Belyansky, A. Bonnoit, G. Bronner, V. Chan, X. Chen, Z. Chen, D. Chidambarrao, A. Chou, W. Clark, S. W. Crowder, B. Engel, H. Harifuchi, S. F. Huang, R. Jagannathan, F. F. Jamin, Y. Kohyama, H. Kuroda, C. W. Lai, H. K. Lee, W. H. Lee, E. H. Lim, W. Lai, A. Mallikarjunan, K. Mats umoto, A. McKnight, J. Nayak, H. Y. Ng, S. Panda, R. Rengarajan, M. Steigerwalt, S. Subbanna, K. Subramanian, J. Sudijono, G. Sudo, S. P. Sun, B. Tessier, Y. Toyoshima, P. Tran, R. Wise, R. Wong, I. Y. Yang, C. H. Wann, L. T. Su, M. Horstmann, T. Feudel, A Wei, K. Frohberg, G. Burbach, M. Gerhardt, M. Lenski, R. Stephan, K. Wieczorek, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, P. Huebler, S. Luning, R. van Bentum, G. Grasshoff, C. Schwan, E. Ehrichs, S. Goad, J. Buller, S. Krishnan, D. Greenlaw, M. Raab, and N. Kepler, "Dual stress liner for high performance sub 45nm gate length SOI CMOS manufacturing," in IEDM Tech. Dig. 2004, pp. 1075 1077. [40] W. H. Lee, A. Waite, H. Nii, H. M. Nayfeh, V. McGahay, H. Nakayama, D. Fried, H. Chen, L. Black, R. Bolam, J. Cheng, D. Chidambarrao, C. Christiansen, M. Cullinan Scholl, D. R. Davies, A. Domenicucci, P. Fisher, J. Fitzsimmons, J. Gill, M. Gribelyuk, D. Harmon, J. Holt, K. Ida, M. Kiene, J. Kluth, C. Labelle, A. Madan, K. Malone, P. V. McLaughlin, M. Mi nami, D. Mocuta, R. Murphy, C. Muzzy, M. Newport, S. Panda, I. Peidous, A. Sakamoto, T. Sato, G. Sudo, H. VanMeer, T. Yamashita, H. Zhu, P. Agnello, G. Bronner, G. Freeman, S. F. Huang, T. Ivers, S. Luning, K. Miyamoto, H. Nye, J. Pellerin, K. Rim, D. Sche pis, T. Spooner, X. Chen, M. Khare, M. Horstmann, A. Wei, T. Kammler, J. Hontschel, H. Bierstedt, H. J. Engelmann, A. Hellmich, K. Hempel, G. Koerner, A. Neu, R. Otterbach, C. Reichel, M. Trentsch, P. Press, K. Frohberg, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, M. Raab, D. Greenlaw, and N. Kepler, "High performance 65 nm SOI technology with enhanced transistor strain and advanced low K BEOL," in IEDM Tech. Dig. 2005, pp. 4 pp. 59. [41] E. Leobandung, H. Nayakama, D. Mocuta, K. Miyamoto, M. Ang yal, H. V. Meer, K. McStay, I. Ahsan, S. Allen, A. Azuma, M. Belyansky, R. V. Bentum, J. Cheng, D. Chidambarrao, B. Dirahoui, M. Fukasawa, M. Gerhardt, M. Gribelyuk, S. Halle, H. Harifuchi, D. Harmon, J. Heaps Nelson, H. Hichri, K. Ida, M. Inohara, I. C. I nouc, K. Jenkins, T. Kawamura, B. Kim, S. K. Ku, M. Kumar, S. Lane, L. Liebmann, R. Logan, I. Melville, K. Miyashita, A. Mocuta, P. O'Neil, M. F. Ng, T. Nogami, A. Nomura, C. Norris, E. Nowak, M. Ono, S. Panda, C. Penny, C. Radens, R. Ramachandran, A. Ray, S. H. Rhee, D. Ryan, T. Shinohara, G. Sudo, F. Sugaya, J. Strane, Y. Tan, L. Tsou, L. Wang, F. Wirbeleit, S. Wu, T. Yamashita, H. Yan, Q. Ye, D. Yoneyama, D. Zamdmer, H. Zhong, H. Zhu, W. Zhu, P. Agnello, S. Bukofsky, G. Bronner, E. Crabbe, G. Freeman, S. F. Huang, T. Ivers, H. Kuroda, D. McHerron, J. Pellerin, Y. Toyoshima, S. Subbanna, N. Kepler, and L. Su, "High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell," in VLSI technology Tech. Dig. 2005, pp. 126 127.

PAGE 96

96 [42] C. D. Sheraw, M. Yang, D. M. Fried, G. Costrini, T. Kanarsky, W. H. Lee, V. Chan, M. V. Fischetti, J. Holt, L. Black, M. Naeem, S. Panda, L. Economikos, J. Groschopf, A. Kapur, Y. Li, R. T. Mo, A. Bonnoit, D. Degraw, S. Luning, D. Chidambarrao, X. Wang, A. Bryant, D. Brown, C. Y. Sung, P. Agnello, M. Ieong, S. F. Huang, X. Chen, and M. Khare, "Dual stress liner enhancement in hybrid orientation technology," in VLSI technology Tech. Dig. 2005, pp. 12 13. [43] H. Barnaby, "Total Dose Effects in Modern Integr ated Circuit Technologies," in Short course, NSREC 2005. [44] R. Baumann, "Single Event Effects in Advanced CMOS Technology," in Short course, NSREC 2005. [45] J. Schwank, "Total Dose Effects in MOS Devices," in Short course, NSREC 2002. [46] T. Weather ford, "From Carriers to Contacts: A Review of SEE charge collection Process in Devices," in Short course, NSREC 2002. [47] H. J. Barnaby, "Total Ionizing Dose Effects in Modern CMOS Technologies," IEEE Trans. Nucl. Sci., vol. 53, pp. 3103 3121, 2006. [48] A. Holmes Siedle and L. Adams, Handbook of Radiation Effects 2 edition ed.: Oxford University Press, 2002. [49] T. P. Ma and P. V. Dressendorfer, Ionizing radiation effects in MOS devices and circuits : John Wiley & Sons, Inc, 1989. [50] D. Zupac, K. F. Galloway, R. D. Schrimpf, and P. Augier, "Radiation induced mobility degradation in p channel double diffused metal oxide semiconductor power transistors at 300 and 77 K," J. Appl. Phys., vol. 73, pp. 2910 2915, 1993. [51] G. Santin, "Space Radiation Tran sport Models," in Short course, NSREC 2006. [52] M. R. Shaneyfelt, P. E. Dodd, B. L. Draper, and R. S. Flores, "Challenges in hardening technologies using shallow trench isolation," IEEE Trans. Nucl. Sci., vol. 45, pp. 2584 2592, 1998. [53] S. Natarajan, M. Armstrong, M. Bost, R. Brain, M. Brazier, C. H. Chang, V. Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He, R. Heussner, R. James, I. Jin, C. Kenyon, S. Klopcic, S. H. Lee, M. Liu, S. Lodha, B. McFadden, A. Murt hy, L. Neiberg, J. Neirynck, P. Packan, S. Pae, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J. Seiple, B. Sell, S. Sivakumar B. Song, K. Tone, T. Troeger, C. Weber, M. Yang, A. Yeoh, and K. Zhang, "A 32nm logic technology featuring 2nd generation high k + metal gate transistors, enhanced channel strain and 0.1um2 SRAM cell size in a 291Mb array," in IEDM Tech. Dig. 2008, pp. 1 3.

PAGE 97

97 [54] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, "High k/metal gate stack and its MOSFET characteristics," IEEE Electron Dev. Lett., vol. 25, pp. 408 410, 2004. [55] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Pa rthasarathy, E. Vincent, and G. Ghibaudo, "Review on high k dielectrics reliability issues," IEEE Trans. Dev. and Mater. Reliab., vol. 5, pp. 5 19, 2005. [56] S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Kava lieros, K. Kuhn, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, and J. Wiedemer, "BTI reliability of 45 nm high K + metal gate process technology," in IEEE Int. Reliab. Phys. Symp. 2 008, pp. 352 357. [57] Y. S. Choi, H. Park, T. Nishida, and S. E. Thompson, "Reliability of HfSiON gate dielectric silicon MOS devices under [110] mechanical stress: Time dependent dielectric breakdown," J. Appl. Phys., vol. 105, p. 044503, 2009. [58] C. P rasad, M. Agostinelli, C. Auth, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Jopling, J. Kavalieros, R. Kotlyar, M. Kuhn, K. Kuhn, J. Maiz, B. McIntyre, M. Metz, K. Mistry, S. Pae, W. Rachmady, S. Ramey, A. Roskowski, J. Sandford, C Thomas, C. Wiegand, and J. Wiedemer, "Dielectric breakdown in a 45 nm high k/metal gate process technology," in IEEE Int. Reliab. Phys. Symp. 2008, pp. 667 668. [59] L. Kang, K. Onishi, Y. Jeon, L. Byoung Hun, C. Kang, Q. Wen Jie, R. Nieh, S. Gopalan, R Choi, and J. C. Lee, "MOSFET devices with polysilicon on single layer HfO2 high K dielectrics," in IEDM Tech. Dig. 2000, pp. 35 38. [60] J. C. Lee, H. J. Cho, C. S. Kang, S. Rhee, Y. H. Kim, R. Choi, C. Y. Kang, C. Choi, and M. Abkar, "High k dielectric s and MOSFET characteristics," in IEDM Tech. Dig. 2003, pp. 4.4.1 4.4.4. [61] S. K. Dixit, X. J. Zhou, R. D. Schrimpf, D. M. Fleetwood, S. T. Pantelides, R. Choi, G. Bersuker, and L. C. Feldman, "Radiation induced charge trapping in ultrathin HfO2 based n MOSFETs," IEEE Trans. Nucl. Sci., vol. 54, pp. 1883 1890, Dec. 2007. [62] J. A. Felix, D. M. Fleetwood, R. D. Schrimpf, J. G. Hong, G. Lucovsky, J. R. Schwank, and M. R. Shaneyfelt, "Total dose radiation response of hafnium silicate capacitors," IEEE Trans Nucl. Sci., vol. 49, pp. 3191 3196, Dec. 2002. [63] J. A. Felix, J. R. Schwank, D. M. Fleetwood, M. R. Shaneyfelt, and E. P. Gusev, "Effects of radiation and charge trapping on the reliability of high k gate dielectrics," Microelectron. Reliab., vol. 44, pp. 563 575, Jan. 2004.

PAGE 98

98 [64] S. R. Kulkarni, R. D. Schrimpf, K. F. Galloway, R. Arora, C. Claeys, and E. Simoen, "Total Ionizing Dose Effects on Ge pMOSFETs With High k Gate Stack: On/Off Current Ratio," IEEE Trans. Nucl. Sci., vol. 56, pp. 1926 1930, 200 9. [65] L. Massengill, "SEU Modeling and Prediction Techniques," in Short course, NSREC 1993. [66] P. E. Dodd, M. R. Shaneyfelt, J. A. Felix, and J. R. Schwank, "Production and propagation of single event transients in high speed digital logic ICs," IEEE Trans. Nucl. Sci., vol. 51, pp. 3278 3284, 2004. [67] A. Hamada, T. Furusawa, N. Saito, and E. Takeda, "A New Aspect of Mechanical Stress Effects in Scaled Mos Devices," IEEE Trans. Electron Dev., vol. 38, pp. 895 900, Apr 1991. [68] R. E. Beaty, R. C. Jae ger, J. C. Suhling, R. W. Johnson, and R. D. Butler, "Evaluation of piezoresistive coefficient variation in silicon stress sensors using a four point bending test fixture," IEEE Trans. Components, Hybrids, and Manufacturing Technology, vol. 15, pp. 904 914 1992. [69] S. Timoshenko, Strength of Materials 3rd ed.: R. E. Krieger Pub. Co., 1976. [70] M. Chu, T. Nishida, X. L. Lv, N. Mohta, and S. E. Thompson, "Comparison between high field piezoresistance coefficients of Si metal oxide semiconductor field eff ect transistors and bulk Si under uniaxial and biaxial stress," J. Appl. Phys., vol. 103, pp. Jun 1 2008. [71] J. Robertson, "High dielectric constant gate oxides for metal oxide Si transistors," Reports on Progress in Physics, vol. 69, pp. 327 396, Feb 2006. [72] Z. Wei, A. Seabaugh, V. Adams, D. Jovanovic, and B. Winstead, "Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain," IEEE Electron Dev. Lett., vol. 26, pp. 410 412, 2005. [73] X. Yang, J. Lim, G. Sun K. Wu, T. Nishida, and S. E. Thompson, "Strain induced changes in the gate tunneling currents in p channel metal oxide semiconductor field effect transistors," Appl. Phys. Lett., vol. 88, pp. Jan 30 2006. [74] K. Kasama, F. Toyokawa, M. Tsukiji, M. Sa kamoto, and K. Kobayashi, "Mechanical stress dependence of radiation effects in MOS structures," IEEE Trans. Nucl. Sci., vol. 33, pp. 1210 1215, Dec. 1986. [75] V. Zekeriya and T. P. Ma, "Effect of stress relaxation on the generation of radiation induced i nterface traps in post metal annealed Al SiO2 Si devices," Appl. Phys. Lett., vol. 45, pp. 249 251, Aug. 1984.

PAGE 99

99 [76] S. Mayuzumi, S. Yamakawa, D. Kosemura, M. Takei, K. Nagata, H. Akamatsu, K. Aamari, Y. Tateshita, H. Wakabayashi, M. Tsukamoto, T. Ohno, M. Saitoh, A. Ogura, and N. Nagashima, "Comparative study between Si (110) and (100) substrates on mobility and velocity enhancements for short channel highly strained PFETs," in VLSI technology Tech. Dig. 2009, pp. 14 15. [77] Y. Song, H. Zhou, Q. Xu, J. Lu o, H. Yin, J. Yan, and H. Zhong, "Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status," J. Elec. Mater., vol. 40, pp. 1584 1612, 2011. [78] S. Saito, D. Hisamoto, S. Kimura, and M. Hiratani, "Unified mobility model for high k g ate stacks [MISFETs]," in IEDM Tech. Dig. 2003, pp. 33.3.1 33.3.4. [79] A. Ortiz Conde, F. J. Garcia Sanchez, J. J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, "A review of recent MOSFET threshold voltage extraction methods," Microelectron. Reliab., vol. 4 2, pp. 583 596, Feb. 2002. [80] C. D. Young, D. Heh, S. V. Nadkarni, R. Choi, J. J. Peterson, J. Barnett, B. H. Lee, and G. Bersuker, "Electron trap generation in high k gate stacks by constant voltage stress," IEEE Trans. Device Mater. Rel. vol. 6, pp. 123 131, Jun. 2006. [81] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics," IEEE Electron Dev. Lett., vol. 24, pp. 87 89, Feb. 2003. [82] K. Onishi, C. Rino, K. Chang Seok, C. Hag Ju, K. Young Hee, R. E. Nieh, H. Jeong, S. A. Krishnan, M. S. Akbar, and J. C. Lee, "Bias temperature instabilities of polysilicon gate HfO2 MOSFETs," IEEE Trans. Electron Dev., vol. 50, pp. 1517 1524, Jun. 2003. [83] S. J. Rhee and J. C. Lee, "Threshold voltage instability characteristics of HfO2 dielectrics n MOSFETs," Microelectron. Reliab., vol. 45, pp. 1051 1060, Mar. 2005. [84] P. J. McWhorter and P. S. Winokur, "Simp le technique for separating the effects of interface traps and trapped oxide charge in metal oxide semiconductor transistors," Appl. Phys. Lett., vol. 48, pp. 133 135, Jan. 1986. [85] S. Y. Son, Y. S. Choi, P. Kumar, H. Park, T. Nishida, R. K. Singh, and S E. Thompson, "Strained induced changes in gate leakage current and dielectric constant nitrided Hf silicate dielectric silicon MOS capacitors," to be submitted [86] A. Hamada and E. Takeda, "Hot electron trapping activation energy in pMOSFETs under mech anical stress," IEEE Electron Dev. Lett., vol. 15, pp. 31 32, Jan. 1994. [87] E. Takeda, "A cross section of VLSI reliability hot Carriers, dielectrics and metallization," Semicond. Sci. and Tech., vol. 9, pp. 971 987, May 1994.

PAGE 100

100 [88] D. M. Fleetwood, H. D. Xiong, Z. Y. Lu, C. J. Nicklaw, J. A. Felix, R. D. Schrimpf, and S. T. Pantelides, "Unified model of hole trapping, 1/f noise, and thermally stimulated current in MOS devices," IEEE Trans. Nucl. Sci., vol. 49, pp. 2674 2683, Dec. 2002. [89] Z. Y. Lu, C. J. Nicklaw, D. M. Fleetwood, R. D. Schrimpf, and S. T. Pantelides, "Structure, properties, and dynamics of oxygen vacancies in amorphous SiO2," Phys. Rev. Lett., vol. 89, p. 285505, Dec. 2002. [90] C. J. Nicklaw, Z. Y. Lu, D. M. Fleetwood, R. D. Schrimpf, and S. T. Pantelides, "The structure, properties, and dynamics of oxygen vacancies in amorphous SiO2," IEEE Trans. Nucl. Sci., vol. 49, pp. 2667 2673, Dec. 2002. [91] X. J. Zhou, D. M. Fleetwood, I. Danciu, A. Dasgupta, S. A. Francis, and A. D. Touboul, Effects of aging on the 1/f noise of metal oxide semiconductor field effect transistors," Appl. Phys. Lett., vol. 91, pp. 173501 3, Oct. 2007. [92] O. L. Curtis and J. R. Srour, "Multiple trapping model and hole transport in SiO2," J. Appl. Phys., vol. 48, pp. 3819 3828, Sep. 1977. [93] J. R. Srour, S. Othmer, O. L. Curtis, and K. Y. Chiu, "Radiation induced charge transport and charge buildup in SiO2 films at low temperatures," IEEE Trans. Nucl. Sci., vol. 23, pp. 1513 1519, Dec. 1976. [94] V. Ferlet Cavro is, P. Paillet, D. McMorrow, A. Torres, M. Gaillardin, J. S. Melinger, A. R. Knudson, A. B. Campbell, J. R. Schwank, G. Vizkelethy, M. R. Shaneyfelt, K. Hirose, O. Faynot, C. Jahan, and L. Tosti, "Direct measurement of transient pulses induced by laser and heavy ion irradiation in deca nanometer devices," IEEE Trans. Nucl. Sci., vol. 52, pp. 2104 2113, 2005. [95] R. Lacoe, "CMOS Scaling, Design Principles, and Hardening by Design Methodologies," in Short course, NSREC 2003. [96] R. A. Reed, "Fundamental me chanisms for Single Particle Induced Soft Errors," in Short course, NSREC 2008. [97] N. Mohta and S. E. Thompson, "Mobility enhancement," IEEE Circuits Dev., vol. 21, pp. 18 23, Sep Oct 2005. [98] M. V. Fischetti and S. E. Laux, "Band structure, deformati on potentials, and carrier mobility in strained Si, Ge, and SiGe alloys," J. Appl. Phys., vol. 80, pp. 2234 2252, 1996. [99] J. S. Melinger, S. Buchner, D. McMorrow, W. J. Stapor, T. R. Weatherford, and A. B. Campbell, "Critical Evaluation of the Pulsed La ser Method for Single Event Effects Testing and Fundamental Studies," IEEE Trans. Nucl. Sci., vol. 41, pp. 2574 2584, Dec 1994.

PAGE 101

101 [100] D. McMorrow, W. T. Lotshaw, J. S. Melinger, S. Buchner, and R. L. Pease, "Subbandgap laser induced single event effects: C arrier generation via two photon absorption," IEEE Trans. Nucl. Sci., vol. 49, pp. 3002 3008, Dec 2002. [101] R. S. Wagner, J. M. Bradley, N. Bordes, C. J. Maggiore, D. N. Sinha, and R. B. Hammond, "Transient Measurements of Ultrafast Charge Collection in Semicouductor Diodes," IEEE Trans. Nucl. Sci., vol. 34, pp. 1240 1245, 1987. [102] J. S. Laird, T. Hirao, H. Mori, S. Onoda, T. Kamiya, and H. Itoh, "Development of a new data collection system and chamber for microbeam and laser investigations of single e vent phenomena," Nucl. Inst. and Meth. Phys. Res. B, vol. 181, pp. 87 94, Jul 2001. [103] M. E. Law, FLOODS/FLOOPS Manual Gainesville, FL, 2008. [104] O. A. Amusan, "Analysis of single event vunerabilities in a 130 nm CMOS technology," M.S. Dissertation, : Vanderbilt Univ., 2006. [105] R. Li, L. Yu, H. Xin, Y. Dong, K. Tao, and C. Wang, "A comprehensive study of reducing the STI mechanical stress effect on channel width dependent Idsat," Semicond. Sci. and Tech., vol. 22, pp. 1292 1297 2007. [106] M. Amiott i, A. Borghesi, G. Guizzetti, and F. Nava, "Optical Properties of Polycrystalline Nickel Silicides," Phys. Rev. B, vol. 42, pp. 8939 8946, Nov 15 1990. [107] Y. S. Choi, T. Nishida, and S. E. Thompson, "Impact of mechanical stress on direct and trap assist ed gate leakage currents in p type silicon metal oxide semiconductor capacitors," Appl. Phys. Lett., vol. 92, pp. 173507 3, May 2008. [108] G. C. Messenger, "Collection of Charge on Junction Nodes from Ion Tracks," IEEE Trans. Nucl. Sci., vol. 29, pp. 2024 2031, 1982. [109] K. Bucher, J. Bruns, and H. G. Wagemann, "Absorption Coefficient of Silicon an Assessment of Measurements and the Simulation of Temperature Variation," J. Appl. Phys., vol. 75, pp. 1127 1132, Jan 15 1994. [110] W. P. Mason and R. N. Th urston, "Use of Piezoresistive Materials in the Measurement of Displacement, Force, and Torque," J. Acoust. Society Amer., vol. 29, pp. 1096 1101, 1957. [111] C. S. Smith, "Piezoresistance Effect in Germanium and Silicon," Phys. Rev. vol. 94, pp. 42 49, 1954. [112] C. Hu, "Alpha Particle Induced Field and Enhanced Collection of Carriers," IEEE Electron Dev. Lett., vol. 3, pp. 31 34, 1982.

PAGE 102

102 [113] J. S. Laird, T. Hirao, S. Onoda, and H. Itoh, "High injection carrier dynamics generated by MeV heavy ions impac ting high speed photodetectors," J. Appl. Phys., vol. 98, pp. Jul 1 2005. [114] Synopsys, Sentaurus Device User Manual Version X 2005.10 ed., 2005. [115] Y. Kanda, "A Graphical Representation of the Piezoresistance Coefficients in Silicon," IEEE Trans. Electron Dev., vol. 29, pp. 64 70, 1982. [116] D. J. Cummings, "Enhancements in CMOS Devices Simulatio n for Single event effects Ph D Dissertation Univ ersity of Florida, 2010. [117] S. DasGupta, A. F. Witulski, B. L. Bhuva, M. L. Alles, R. A. Reed, O. A. Amusan, J. R. Ahlbin, R. D. Schrimpf, and L. W. Massengill, "Effect of Well and Substrate Potential Modulation on Single Event Pulse Shape in Deep Submicron CMOS," IEEE Trans. Nucl. Sci., vol. 54, pp. 2407 2412, 2007. [118] R. Reed, "Fundamental Mechan isms for Single Particle Indeced Soft Errors," in Short course, NSREC 2008. [119] U. Aghoram, "Impact of Strain on M emory and Lateral Power MOSFETs Ph D Dissertation Univ ersity of Florida 2010. [120] R. Arghavani, Z. Yuan, N. Ingle, K. B. Jung, M. Se amons, S. Venkataraman, V. Banthia, K. Lilja, P. Leon, G. Karunasiri, S. Yoon, and A. Mascarenhas, "Stress management in sub 90 nm transistor architecture," IEEE Trans. Electron Dev., vol. 51, pp. 1740 1744, 2004. [121] N. Shah, "Stress Mode ling of Nanosca le MOSFET." M.S. dissertation, University of Florida, 2005. [122] P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S. H. Lee, N. Lindert, M. Liu, Z. Ma T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, and M. Bohr, "A 65nm logic technology featuring 35nm gate lengths enhanced channel strain, 8 Cu interconnect layers, low k ILD and 0.57um 2 SRAM cell," in IEDM Tech. Dig. 2004, pp. 657 660.

PAGE 103

103 [123] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McLntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, "A 45nm Logic Technology with High k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb free Packaging," in IEDM Tech. Dig. 2007, pp. 247 250. [124] C. Chien Hao, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M. S. Liang, "Stress memorization technique (SMT) by selectively strained nitride capping for sub 65nm high performance strained Si device application," in VLSI technology Tech. Dig. 2004, pp. 56 57. [ 125] S. Mayuzumi, J. Wang, S. Yamakawa, Y. Tateshita, T. Hirano, M. Nakata, S. Yamaguchi, Y. Yamamoto, Y. Miyanami, I. Oshiyama, K. Tanaka, K. Tai, K. Ogawa, K. Kugimiya, Y. Nagahama, Y. Hagimoto, R. Yamamoto, S. Kanda, K. Nagano, H. Wakabayashi, Y. Tagawa M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, and N. Nagashima, "Extreme High Performance n and p MOSFETs Boosted by Dual Metal/High k Gate Damascene Process using Top Cut Dual Stress Liners on (100) Substrates," in IEDM Tech. Dig. 2007, pp. 293 296 [126] H. Park, D. J. Cummings, R. Arora, J. A. Pellish, R. A. Reed, R. D. Schrimpf, D. McMorrow, S. E. Armstrong, U. Roh, T. Nishida, M. E. Law, and S. E. Thompson, "Laser Induced Current Transients in Strained Si Diodes," IEEE Trans. Nucl. Sci., vol. 56 pp. 3203 3209, 2009. [127] D. J. Cummings, A. F. Witulski, H. Park, R. D. Schrimpf, and S. E. Thompson, "Mobility Modeling Considerations for Radiation Effects Simulations in Silicon," IEEE Trans. Nucl. Sci., 2010. [128] K. L. Cheng et al., "A highly sca led, high performance 45 nm bulk logic CMOS technology with 0.242 m2 SRAM cell," in IEDM Tech. Dig. 2007, pp. 243 246. [129] R. Reed, "Fundamental mechanisms for single particle induced soft errors," in Short course, NSREC 2008. [130] D. J. Cummings, M. E. Law, S. Cea, and T. Linton, "Comparison of Discretization Methods for Device Simulation," in Int. Conf. SISPAD 2009, pp. 1 4. [131] J. Machek and S. Selberherr, "A novel finite element approach to device modeling," IEEE Trans. Electron Dev., vol. 30, p p. 1083 1092, 1983. [132] S. Micheletti, "Stabilized finite elements for semiconductor device simulation," Computing and Visualization in Sci., vol. 3, pp. 177 183, 2001.

PAGE 104

104 [133] A. Appaswamy et al., "The Effects of Proton Irradiation on 90 nm Strained Si CM OS on SOI Devices," in IEEE Radiation Effects Data Workshop 2006, pp. 62 65. [134] H. Park, S. K. Dixit, Y. S. Choi, R. D. Schrimpf, D. M. Fleetwood, T. Nishida, and S. E. Thompson, "Total Ionizing Dose Effects on Strained HfO2 Based nMOSFETs," IEEE Trans Nucl. Sci., vol. 55, pp. 2981 2985, 2008.

PAGE 105

105 BIOGRAPHICAL SKETCH He received his B.S. degree in Materials Science and M.S. degree in Program in Micro/Nano System from Korea University, Seoul, Korea, in 2002 and 2006, respectively. He received his Ph.D. deg ree in Electrical and Computer E ngineering at the University of Florida, Gainesville FL in the fall of 2011 He was a process integration engineer in 2003 for LG Display, Korea. During that period, he was involved in developing large size LCD TV panels He interned at Intel Corporation, Santa Clara, CA from June to December 2011 working on electrical characterization of phase change memory devices. His current research is focused on electrical measurements, characterization, and modeling of strained Si d evices