Comparative Study of Substrate, Diffusion Barrier, and Deposition Method Effects on Copper Metallization

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Comparative Study of Substrate, Diffusion Barrier, and Deposition Method Effects on Copper Metallization
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english
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Chen,Chien-Tsung
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Master's ( M.S.)
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University of Florida
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Chemical Engineering
Committee Chair:
Anderson, Timothy J
Committee Members:
McElwee-White, Lisa A

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chemical -- copper -- deposition -- film -- interconnect -- metal -- metallizaton -- physical -- thin -- vapor
Chemical Engineering -- Dissertations, Academic -- UF
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Abstract:
Microelectronic devices have been moving toward smaller and smaller dimensions with increasing functionality. For example, the first generation cell phones were simply used to make phone calls in the 1980s. Thirty years later, the size of the cell phones decreased, and they are used not only as telephones but also as small computers with a wide variety of functions. It is a result of continuing miniaturization of the devices in circuits over the last few decades. For Cu interconnects, the mean-time-to-failure has been used as an estimate of how reliable the interconnects are, and it is an average time for a device to encounter failure. The mean-time-to-failure has been shown to be proportional to the average grain size and the intensity ratio between (111) and (200), which are the two most intense peaks in Cu XRD spectra. In other words, the growth of strong (111) texture, large and uniform size grains are desired. For the substrate effect study, it has been known that a smooth and strongly textured copper seed layer is needed to promote the development of highly textured, large grains in the electroplated Cu film, no significant difference in Cu(111) texture was found in the case when Si(111) was used as a substrate compared to Si(100). As for the diffusion barrier effect study, Cu seed layers grown on different diffusion barriers had different strengths of (111) texture and the grain size distributions varied drastically. However, those variations ceased when Cu was subsequently electroplated. This might be a result of the formation of an oxide in the Cu seed layer before Cu electroplating. In regard to deposition method effects, sputtered Cu seed layers were found to have much stronger (111) texture than CVD Cu seed layers. Additionally, sputtered Cu seed layers had good adhesion to the underlying layers and passed the adhesion tests, but CVD Cu seed layers showed poor adhesion performance. Those discrepancies disappeared again in the electroplated Cu films, and were attributed to the formation of Cu oxide in the Cu seed layers before electroplating of Cu.
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by Chien-Tsung Chen.
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Thesis (M.S.)--University of Florida, 2011.
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1 COMPARATIVE STUDY OF SUBSTRATE, DIFFUSION BARRIER, AND DEPOSITION METHOD EFFECTS ON COPPER METALLIZATION BY CHIENTSUNG CHEN A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE UNIVERSITY OF FLORIDA 2011

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2 2011 ChienTsung Chen

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3 To my father KuoWen Chen, and my mother BaoChu Hsieh

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4 ACKNOWLEDGMENTS I would like to thank my advisor, Dr. Timothy J. Anderson, for his support and guidance during the two years for my master degree at the University of Florida. He not only taught me experimental skills but t aught me how to organize things and plan well ; to maximize understanding and efficiency. As a master student I es peci ally appreciate the chance to learn and do everything myself, including the trainings and access to equipment I need: this is a very valuable experience in my life. M y supervisory committee member Dr. Lisa McEl wee White also gave me treasurable advices Also I want to thank my mentor, Christopher O Donohue, for his k ind teachings of everything in th e lab and the immediate help and suggestions on my researc h, and group mate Joseph C. Revelli who also gave me directions in solving problems based on his experience. Rangarajan Krishnan demonstrated the work ethic to do research and also helped me with X RD. David P. Wood and Vaibhav Chaudhari taught and assisted me with SEM imag ing skills M y research could not have been done without their help. Last but not the least, I want to thank my parents, KuoWen Chen and Bao Chu Hsieh, for their encouragement and full support during the course of my education at the University of Florida.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................. 4 LIST OF TABLES ............................................................................................................ 8 LIST OF FIGURES ........................................................................................................ 10 ABSTRACT ................................................................................................................... 12 CHAPTER 1 INTRODUCTION .................................................................................................... 14 1.1 Background ....................................................................................................... 14 1.2 Challenges to Interconnections ......................................................................... 16 1.2.1 Resistive Capacitive ( RC) Time Delay in Interconnects .......................... 16 1.2.2 Electromigration in Interconnects ............................................................ 18 1.3 Challenges to Copper ( Cu ) Metallization .......................................................... 22 1.3.1 Diffusion of C u in Silicon (Si) ................................................................... 22 1.3.2 Patterning of C u ...................................................................................... 24 1.3.3 Advantages of Refractory Carbides and Refractory Nitrides ................... 25 1.4 Problem Statement ........................................................................................... 26 2 LITERATURE REVIEW .......................................................................................... 33 2.1 Depositi on Methods for Thin Films .................................................................... 33 2.1.1 Physical Vapor Deposition (PVD) ............................................................ 33 2.1.2 Chemical Vapor Deposition (CVD) .......................................................... 34 2.2 Characterization ................................................................................................ 36 2.2.1 X Ray Diffraction (XRD) .......................................................................... 36 2.2.2 X ray Photoelectron Spectroscopy (XPS) ................................................ 37 2.2.3 Energy D ispersive X ray S pectroscopy (EDS) ........................................ 38 2.2.4 Scanning E lectron M icroscopy (SEM) ..................................................... 38 2.2.5 A tomic F orce M icroscopy (AFM) ............................................................. 39 2.2.6 Four Point Probe ..................................................................................... 40 2.2.7 Scot ch Brand Tape Test ....................................................................... 40

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6 3 EXPERIMENTAL TECHNIQUES FOR THIN FILM DEPOSITION AND CHARACTERIZATION ........................................................................................... 41 3.1 Substrates Used for Experiments and Precleaning of the Substrates .............. 41 3.2 Description of the S puttering R eactor ............................................................... 41 3.3 Description of CVD Reactor .............................................................................. 43 3.4 Precursor for C u Deposition .............................................................................. 43 3.5 Operating Procedure for CVD Reactor ............................................................. 43 3.5.1 Pretreatment for the Samples and CVD Deposition Procedure ............... 43 3.5.2 Growth Rate Cu Seed Layer Deposition by Metallo Organic Chemical Vapor Deposition ( MOCVD) .......................................................... 44 3.6 Electroplating (EP) of Cu Bulk Fill ..................................................................... 45 3.6.1 Parameters for Electrochemical Deposition ............................................. 45 3.6.2 Growth Rate EP Cu Fill ........................................................................ 45 3.7 Techniques for Thin Film Characterization ....................................................... 46 3.7.1 X Ray Diffraction (XRD) .......................................................................... 46 3. 7.2 Scanning Electron Microscopy (SEM) ..................................................... 47 3.7.3 Four Point Probe ..................................................................................... 48 3.7. 4 Scotch Brand Tape Test ....................................................................... 49 4 SUBSTRATE EFFECTS ON DIFFUSION BARRIER, COPPER SEED LAYER, AND COPPER BULK FILL ...................................................................................... 52 4.1 X Ray Diffraction Measurement ........................................................................ 52 4.1.1 Film Crystallinity ...................................................................................... 52 4.1.2 Polycrystal Grain Size ............................................................................. 56 4.2 Scanning Electron Microscopy .......................................................................... 57 4.3 Film Resistivity .................................................................................................. 59 4.4 Scotch Brand Tape Test ................................................................................. 60 5 DIFFUSION BARRIER EFFECTS ON MOCVD DEPOSITED COPPER SEED LAYER, AND ELECROPLATED COPPER ............................................................. 74 5.1 X Ray Diffraction Measurement ........................................................................ 74 5.1.1 Film Crystallinity ...................................................................................... 74 5.1.2 Polycrystal Grain Size ............................................................................. 76 5.2 Scanning Electron Microscopy .......................................................................... 77

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7 5.3 Four Point Probe Measurement ........................................................................ 79 5.4 Scotch Brand Tape Test ................................................................................. 79 6 DEPOSITION TECHNIQUE EFFECTS ON MOCVD DEPOSITED COPPER SEED LAYER, AND ELECt ROPLATED COPPER ................................................. 92 6.1 X Ray Diffraction Measurement ........................................................................ 93 6.1.1 Film Crystallinity ...................................................................................... 93 6.1.2 Polycrystal Grain Size ............................................................................. 94 6.2 Scanning Electron Microscopy .......................................................................... 95 6 .3 Film Resistivity .................................................................................................. 97 6.4 Scotch Brand Tape Test ................................................................................. 98 7 CONCLUSION ...................................................................................................... 107 LIST OF REFERENCES ............................................................................................. 110 BIOGRAPHICAL SKETCH .......................................................................................... 113

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8 LIST OF TABLES Table page 4 1 Estimated grain size of MOCVD Cu seed layer / Ta/TaN on Si(100) and Si(111) ........................................................................................................................... 67 4 2 Estimated grain size of MOCVD Cu seed layer / W2N on Si(100) and Si(111) ..... 67 4 3 Estimated grain size of EP Cu/Cu seed layer (MOCVD) / Ta/TaN on Si(100) and Si(111) ......................................................................................................... 67 4 4 Estimated grain size of EP Cu/Cu seed layer (MOCVD) / W2N on Si(100) and Si(111) ................................................................................................................ 67 4 5 Film resistivity of Ta/TaN and W2N on Si(100) and Si(111) ................................ 72 4 6 Film resistivity of Cu seed layer (MOCVD) on Ta/TaN/Si(100) and Ta/TaN/Si(111) ................................................................................................... 72 4 7 Film resistivity of Cu seed layer (MOCVD) on Ta/TaN/Si(100) and Ta/TaN/Si(111) ................................................................................................... 72 4 8 Adhesion test for Cu seed layers deposited on different types of Si substrates 73 4 9 Adhesion test for EP Cu on different types of Si substrates ............................... 73 5 1 Estimated grain size of Cu seed layer (MOCVD) deposited on diffusion barriers/Si(100) ................................................................................................... 85 5 2 Estimated grain size of EP Cu/Cu seed layer (MOCVD)/diffusion barriers/Si (100) ................................................................................................................... 85 5 3 Film resistivity of Cu seed layers (MOCVD) on diffusion barriers/Si(100) ........... 90 5 4 Adhesion test for Cu seed layer deposited on different diffusion barriers ........... 91 5 5 Adhesion test for EP Cu deposited on Cu seed layer (MOCVD)/ different diffusion barriers ................................................................................................. 91 6 1 Estimated grain size of Cu seed layer on Ta/TaN/Si(100) ................................ 102

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9 6 2 Estimated grain size of Cu seed layer on W2N/Si(100) .................................... 102 6 3 Estimated grain size of EP Cu on Ta/TaN/Si(100) ............................................ 102 6 4 Estimated grain size of EP Cu on W2N/Si(100) ................................................ 102 6 5 Film resistivity of Cu seed layer deposited on Ta/TaN and W2N ...................... 105 6 6 Adhesion test for Cu seed layer deposited by different techniques .................. 106 6 7 Adhesion test for EP Cu deposited on Cu seed layers grown by different techniques ........................................................................................................ 106

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10 LIST OF FIGURES Figure page 1 1 Process steps for the fabrication of a via and line level by the dual damascene approach. ........................................................................................................... 31 1 2 Schematic cross section of a metallization structure. ......................................... 32 1 3 Interconnect structure for RC analysis. Two metal interconnects with dimensions of W, L, H lying on SiO2. .................................................................. 32 3 1 SEM cross sectional images of Cu deposited by MOCVD for 120 minutes. ....... 50 3 2 SEM cross sectional images of EP Cu after 10 minutes. ................................... 51 4 1 XRD spectra for sputtered Ta/TaN on different Si substrates. ............................ 62 4 2 XRD spectra for sputtered W2N on different Si substrates. ................................ 63 4 3 XRD spectra for Cu seed layer ( MOCVD)/Ta/TaN on different Si substrates. .... 64 4 4 XRD spectra for Cu seed layer deposited by MOCVD on W2N/Si(100) and W2N/Si(111) ....................................................................................................... 65 4 5 XRD spectra for electroplated (EP) Cu / Cu seed layer ( MOCVD)/diffusion barriers/different Si substrates. ........................................................................... 66 4 6 SEM images of Cu seed layer ( MOCVD)/Ta/TaN on different Si substrates. ..... 68 4 7 SEM images of Cu seed layer ( MOCVD)/W2N on different Si substrates. .......... 69 4 8 SEM images of EP Cu / Cu seed layer (MOCVD) /Ta/TaN on different Si substrates. .......................................................................................................... 70 4 9 SEM images of EP Cu / Cu seed layer (MOCVD) /W2N on different Si substrates. .......................................................................................................... 71 5 1 XRD spectra of A), B) Ta on Si(100). C), D) TaN on Si( 100). ............................. 80 5 2 XRD spectra of A), B) Ta/TaN on Si(100) C), D) W2N/Si(100) ......................... 81

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11 5 3 XRD spectra of A), B) Cu seed layer (MOCVD)/Ta/Si(100). C),D) Cu seed layer (MOCVD)/TaN/Si(100). .............................................................................. 82 5 4 XRD spectra of A), B) Cu seed layer (MOCVD)/Ta/TaN/Si(100) C), D) Cu seed layer (MOCVD)/W2N/Si(100). .................................................................... 83 5 5 EP Cu on Cu seed layer (MOCVD) on diffusion barriers/Si(100) ....................... 84 5 6 SEM images of Cu seed layer (MOCVD) on TaN/Si(100) ................................. 86 5 7 SEM images of Cu seed layer (MOCVD) on Ta/Si(100) .................................... 86 5 8 SEM images of Cu seed layer (MOCVD) on Ta/TaN/Si(100) ............................ 87 5 9 SEM images of Cu seed layer (MOCVD) on W2N/Si(100) ................................. 87 5 10 SEM images of EP Cu/Cu seed layer (MOCVD) deposited on TaN/Si(100) ..... 88 5 11 SEM images of EP Cu/Cu seed layer (MOCVD) deposited on Ta/Si(100) ........ 88 5 12 SEM images of EP Cu/Cu seed layer (MOCVD) deposited on Ta/TaN/Si (100) ........................................................................................................................... 89 5 13 SEM ima ges of EP Cu/Cu seed layer (MOCVD) deposited on W2N/Si(100) ..... 89 6 1 XRD spectra of Cu seed layers on Ta/TaN/Si(100) ........................................... 99 6 2 XRD spectra of Cu seed layers on W2N/Si(100) .............................................. 100 6 3 XRD spectra of EP Cu/Cu seed layer (MOCVD or sputtering)/Ta/TaN/Si (100). ......................................................................................................................... 101 6 4 XRD spectra of EP Cu/Cu seed layer (MOCVD or sputtering)/W2N/Si(100) .... 101 6 5 SEM images of EP Cu/Cu seed layer (MOCVD or sputtering)/Ta/TaN/Si(100) ......................................................................................................................... 103 6 6 SEM images of EP Cu/Cu seed layer (MOCVD or sputtering)/W2N/Si(100) .... 104

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12 Abstract of Thesis Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degr ee of Master of Science COMPARATIVE STUDY OF SUBSTRATE, DIFFUSION BARRIER, AND DEPOSITION METHOD EFFECTS ON COPPER METALLIZATION By Chien Tsung Chen August 2011 Chair: Timothy J. Anderson Major: Chemical Engineering Microelectronic devices have been moving toward smaller and smaller dimensions with increasing functionality. For example, the first generation cell phones were simply used to make phone calls in the 1980s. Thirty years later, the size of the cell phones decreased, and they are used not only as telephones but also as small computer s with a wide variety of functions It is a result of continuing miniaturization of the devices in circuits over the last few decades. For copper ( Cu ) interconnects, the m eantime to failure has been used as an estimate of how reliable the interconnect s are, and i t is a n average time for a device to encounter failure. The m eantime to failure has been shown to be proportional to the average grain size and the intensity ratio between (111) and (200), which are the two

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13 most intens e peaks in Cu X ray diffraction ( XRD ) spectra. I n other words, the growth of strong (111) texture, large and uniform size grains are desired. F or the substrate effect study, it has been known that a smooth and strongly textured copper seed layer is needed to promote the development of highly textured, large grains in the electroplated Cu film no signif icant difference in Cu(111) texture was found in the case when silicon (Si) substrate, Si(111) was used as a substrate compared to Si(100). As f o r the diffusion barrier effect study, Cu seed layers grown on different diffusion barriers had different strength s of (111) texture and the grain size distributions varied drastically. H owever, those variations ceas ed when Cu was subsequently electroplated. T his might be a result of the formation of an oxide in the Cu seed layer before Cu electroplating (EP) In re gard to deposition method effects, sputtered Cu seed layers were found to have much stronger (111) texture than chemical vapor deposition ( CVD) Cu seed layers. Additionally sputtered Cu seed layers had good adhesion to the underlying layers and passed the adhesion tests but CVD Cu seed layers showed poor adhesion performance. T hose discrepancies disappeared again in the electroplated Cu films, and were attributed to the formation of Cu oxide in the Cu seed layers before electroplating of Cu.

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14 CHAPTER 1 I NTRODUCTION 1.1 Background The vast progress in technology over the last few decades has led to a continuous development of miniaturization in microelectronic integrated circuits (ICs) As computer a nd electronic devices such as an i P ad or cell phone, become indispensible parts of our lives, the demand for higher processing speeds for ICs and functionality o f a chip increase. This result s in a decrease in interconnect dim ensions and an increase in device integration levels. I n addition, another advantage following the advance in miniaturization is the lead to a lower cost .1 M any materials have been found applicable as a substrate for semiconductor integrated circuits (ICs), including silicon (Si) germanium (Ge) and gallium arsenide (GaAs), etc E ach of them has im portance in specific applications. F or example, GaAs is important in integrated microwave functions, and Si is used in most of today s ICs due to the fact that Si is the most abundant element on earth, and the ease of growth of silicon oxide ( SiO2) which can act as a good insulator for integrated circuits. T o see how fast the number of transistors that can be put on a chip grows, Moore s Law, an empirical law proposed by Gordon Moore, describes that the number of transistors on an integ rated circuit can be doubled approximately every two years.1 A s a

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15 matter of fact, three to four decades ago, the speed of integrated circuits w as mainly increased by scaling down the size of the transistors S caling of the devices is accompanied by a decrease in the size of the interconnects. H owever, as the s hrinking dimensions continue, the integrated circuit speed is not dominated by the speed of transistors anymore, but the interconnect delay instead. The predominance of the increase in interconnect delay surpasses the effect of scaling of the devi ce when the dimension is smaller than 150nm. The change in interconnect time delay with different tec hnology node has been reviewed and predicted.2 Additionally shrinkage of dimensions of the interconnects results in a higher current density in the transistors, which will affect the performance of the device and shorten the lifetime and the reliability of the metal interconnects Cu has been suggested as an advanced interconnect material since 1997.3 IBM first demonstrated that devices with Cu interconnections had a 4050% decrease in the resist ance of Cu wiring relative to Au (Cu) wiring. T he new Cu fill scheme, d amascene electroplating for Cu, was then developed by IBM T he superfilling feature provided by electroplating can be used to deposit Cu interconnects without voids P rocess steps involved in dual d amascene are shown in Figure 1 1

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16 1. 2 Challenges to Interconnections A ccording to the dimensions, interconnects can be local interconnects, semiglobal interconnects, and global interconnects. L ocal interconnects are very short interconnects that are used at device level. S emiglobal interconnects are interconnects that are used to connect devices within a block. G lobal interconnects are interconnects that are used to connect components between different blocks and are thus very long. F igure 12 shows the schematic diagram of the hier archy of interconnects. 1.2.1 ResistiveCapacitive ( RC) Time Delay in Interconnects The RC time delay in metal oxide semiconductor ( MOS ) can be represented in terms of circuit response. Vout(t) = Vout(max)[1 exp( )] (1 1) w here Vout(t) is the output voltage at time t, Vout(max) is the maximum output voltage, R is the resistance of the metal line, and C is the capacitance of the circuit. It can be shown that f or a simple system such as in Figure 13 the time delay L, is roughly equal to 0.89RC. The line resistance is given by: R = (1 2)

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17 w is the resistivity of the interconnect, and L, W, and H are the interconnects length, width, and height, respectively. The capacitance between the silicon substrate and the metal interconnect is given by: Cox = Kox0 (1 3) w here Xox and Kox are the thickness and the dielectric constanst of the oxide layer, respectively, and 0 is the permittivity of free space. The capacitance between different metal lines is: Cm = Kox0 (1 4) w here Ls is the distance between two metal lines. For the simple structure, the total line capacitance can be represented as: C = KI(Cox+Cm) (1 5) w here KI is a factor approximated by 2. So the time delay can be shown as: L = 0.89 KIKox0 ( + ) (1 6) Let be the smallest dimension achievable for each technology generation, which is also assumed to be equal to W, Xox, H, and l the time delay therefore becomes: L = 3.56Kox0 (1 7) wh e reas the length of the interconnect may or may not be decreased with the advance of the miniaturization

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18 depending on which level of interconnect is being discussed. For local interconnect s, L is ange in time delay H chip area increases as the device dimension shrinks, which requires longer global interconnect to connect all areas of devices. The average length of longest global interconnect s in a circuit is given by: Lmax = (1 8) w here A is the chip area. P lugging this into E quation 1 7 the global interconnect delay becomes: L = 0.89Kox0 (1 9) Since the chip area A will keep decreasi ng as the technology progresses and is getting smaller, the time delay for global interconnect is increasing. 1.2.2 Electromigration in Interconnects I n addition to RC time delay in the interconnects electromigration is another primary focus As devices keep miniaturizing, electromigration becomes a more prevalent. The reliability of ultralarge scale integrated circuits (ULSI) because of the ever increasing current density in the interconnects. Electromigtration occurs when the momentum of the high energy electrons is transferred to t he surrounding metal atoms,

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19 which results in the movement of metal atoms in the direction of electron flow The movement of the metal atoms in the interconnect leads to failure of the circuit by forming either voids or hillocks. V oids are formed where there is a net deplet ion of metal atoms, and hillocks are generated where there is a net accumulation of metal atoms.4,5 To overcome this problem the introduction of a new material with higher electrom igration resistance is needed. Many factors have been known to affect the electromigration reliability including grain si ze, grain size uniformity, crystal orientation, the lay ers surrounding the metal lines ( i.e. diffusion barrier layer and passivation layer ) and the metal interconnect material. P reviously a luminum (Al) was used as the metal for interconnect lines and electromigration has been a major reliability concern. G rain boundar ies h ave been known to be the fastest diffusion path for electromigration in Albased interconnect s.6 Therefore, improvement of Al el ectromigration resistance was realized by growing grains of larger size with respect to linewidth, and eliminating the grains which are oriented in a way such that their grain boundaries are parallel to the direction of electron flow I n addition, alloying of aluminum is another way to improve electromigration resistance. Although the addition of Cu in Al was shown to have higher electromigration resistance than solely Al as an interconnect material, it still cannot provide good

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20 resistance against electromigration as the c urrent density increases .7,8 Consequently, Cu has been selected as an alternative for IC interconnect material. Compared with Al and its alloy, Cu offers not only higher electromigration resistance, but lower electrical resistivity.9,10 These proper ties make Cu more tolerant of higher current densit ies in todays miniaturized devices and more robust against eletromigration failure. The introduction of copper as a new interconnect material has also necessitated new processing schemes and investigation of material properties. For example, it was reported that the electromigration lifetime of copper interconnect s cannot always be improved by forming larger grain size. This implies that the fastest diffusion path of metal in copper interconnect s might be different from that of aluminum ,11 where the grain boundar y is considered to be the fastest diffusion path. I nstead, the top surface of Cu is so f ar the fastest diffusion path. This can be attributed to the difference in surface/interface condition between copper and aluminum. It has been suggested that copper surfaces and interfaces between copper and its surrounding layers provide faster diffusion path for copper.12,13 Thus, the surface and interface property control becomes a more important issue regarding the interconnect reliability. In addition to higher eletromigration resistance, Cu also offers lower electr ical resistivity, which helps decrease RC delay in IC s. Although silver has the lowest bulk

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21 electrical resistivity, it doesnt show good electromigration resistance. Copper is preferred over silver since its bulk elec trical resistivity is still low, and the eletromigration resistance is expected to be higher due to higher melting point, which indicates stronger copper copper bonds. For copper interconnect s the m ean time to failure (MTTF), an estimate of the average time for the device to encounter failure, is affected by the microstructure of the copper interconnects Vaidya and Sinha proposed that the dependence of MTTF on the microstructure of the Cu met al interconnect can be expressed as the following equation:14 MTTF G = 3 ln ( ) ( ) (1 10) w here of the grain size, and I is the X ray diffraction peak intensity of specific orientation. That is to say in order to increase the electromigration resistance, material for the interconnect lines and the fabrication scheme should be chosen and the experimental condition is to be optimized in such a way that th e geometric factor is maximized by forming large grain size, smaller standard deviation, and higher (111) peak int ensity with respect to (200).

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22 1.3 C hallenges to Copper ( Cu ) M etallization A s mentioned above, t he replacement of interconnect material with copper introduced many challenges in IC fabrication; n ew processing methods are needed. d ual d amascene deposition is a new technique introduced in copper metallization.1517 T he properties of material s have to be investigated more extensively and a fundamental understanding of the diffusion mechanism is requir ed. For example, as stated previously researchers suggested that the applicability of the correlation between interconnect reliability and micros tructure of the material in Al based interconnects is to be questioned when i t comes to copper interconnects, which means a different electromigration mechanism in copper. The stability of copper with its surrounding layers should also be considered. Diffusion of copper into silicon substrate is one of the most important issues that need to be solved. 1.3.1 Diffusion of C u in Silicon (Si) Diffusion of Cu atoms into dielectric and silicon substrates causes deterioration of device performance. This phenomenon arises from the concentration gradient between two layers. The Ficks law relates the diffusive flux to the concentration as: J = D( ) (1 11)

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23 J is the atomic flux at position x, C is the atomic concentration, D is the diffusion coefficient. The diffusion coefficient is temperature dependent, which is usually expressed by Equation 112. D = Doe (1 12) w here Do is a constant, Ea is the activation energy for diffusion, R is the universal gas constant, and T is the temperature in Kelvin (K) Experimental observations suggested that the activation energy for diffusion depends on the melting point of the m aterial being diffused through Equation 113. Ea ATm (1 13) where A is a constant, Tm is the absolute melting point of material. In aluminum based interconnect systems, Ti/TiN is generally used as diffusion barrier and adhesion promoter. When copper is applied as interconnect material, diffusion becomes an even more serious problem because of the higher diffusivity of copper into Si and SiO2. The diffusion coefficient of Cu is 2x105 cm2/s a t 500 which is much higher than that of Al in silicon ranging from 3x1015 to 1.3x1013 cm2/s at 900 The fast diffusion of copper in silicon and silicon oxide results in copper precipitates and causes device failure. Furthermore, diffusion of copper into dielectric is another critical problem since it decreases the breakdown voltage of the dielectric

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24 A d iffusion barrier is therefore needed between copper and the dielectric Appropriate candidates for copper diffusion barrier s are characterized by high melting point s, good adhesion to copper and the underlying layer, and being chemically inert. Among elements existing in nature, refractory metals and their binary and ternary compounds are most desirable as diffusion barrier mat erial s. The follow ing are material s that have been studied for diffusion barrier applications are:1821 Refractory me tals like titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), and ruthenium (Ru) Refractory metal alloy s such as TixW1x Refractory metal silicon alloy s and compounds such as T i S2, WxSi1x Refractory meta l nitride and metal carbide such as W2N, TaC Silicon nitrogen and silicon carbon compound such as SiC, Si3N4 The most commonly investigated materials are titanium, tantalum, and tungstenbased compounds 1.3.2 Patterning of C u One of the challenges accompanying the transition of metal interconnect material from aluminum to copper is the difficulty in patterning copper. Wet etching cannot be used because of its isotropic nature. Reactive ion etching (RIE) uses chemically reactive plasma to generate high energy ions that are used to remove materials formed on the

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25 substrate. RIE still cannot be applied in copper patterning since Cu does not form volatile byproducts with this method. The failure of use of wet etching and RIE in copper pattering urged the development of new metallization schemes with respect to copper. A known patterning process for Cu metallization is d ual d amascene. In the d amascene process, the dielectric layer is first deposited, and photolithography and etching are employed to pattern lines and vias in the dielectric. Subsequently the diffusion barrier is deposited followed by copper fi lm deposition. Excess diffusion barrier and copper is then removed through a process called chemical mechanical planarization (CMP) P ro cess steps for d ual d amascene are shown in Figure 11 1.3.3 A dvantages of R efractory C arbides and R efractory N itrides Although it has been known that refractory transition metals are good candidates as diffusion barrier material s, refractory metal nitrides and carbides are studied more extensively for several reasons. First carbides and nitrides of transition metal s have higher melting point s than transition metal s themselves which is a desired featur e of a diffusion barrier. Sec ond the incorporation of nitrogen and carbon incr ease the mechanical stability. There are many steps in fabrication processing, and the various processing conditions require better mechanical stability of the material. For example, deposition of different layers is accompanied by accumulation of stress High stress

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26 level s can result in the fracture of the diffusion barrier, which means that a path for copper diffusion is then opened. Formation of transition metal carbides and nitrides help to significantly increase mechanical stability It is believed that the nitrogen and carbon atoms in transition metal nitrides and carbides consolidate the metal matrix and therefore improve the hardness of the material 1.4 Problem Statement Shrinkage of dimensions of microelectronics has l ed to the challenge of reducing the film thickness of diffusion barrier. International technology roadmap for semiconductor (ITRS), which is organized by a group of semiconductor industry experts, suggested that the thickness of barri er thickness wi ll have to be scaled down to 24 by 2013. This is driven by the fact that as the dimension of vias and copper lines decrease, the volume allowed for the diffusion barrier must be decreased as well or the volume for copper will be decreased. Since the diffusion barrier layer is part of the metal interconnect, the thickness of diffusion barrier is expected to be smaller so as to form a lower resistivity metal stack. As a result, the reduction in RC time delay of interconnect and current density can then be achieved. Therefore, researchers have been exploring different techniques to find out a decent process for ultrathin diffusion barrier film deposition.

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27 Since grain boundar ies of diffusion barrier film are considered as a fast path of diffusion, elimination of grain boundaries by depositing single crystalline film is desired. However, the lattice mismatch between the diffusion barrier and the substrate makes deposition of a single crystalline film difficult An a morphous microstructure is the second best choice to meet the requirement because its lack of long range order An i n crease in the impurity level result ing from the formation of an oxide or halide in the diffusion barrier should be avoided because ox ide impurities in the film lead to an increase in electrical resistivity. Nitrogen incorporation in the diffusion barrier film is believed to stuff the grain boundari es so that the diffusion path for copper through grain boundaries is blocked. Therefore, t he presence of nitrogen in a diffusion barrier film is desirable. The t ransition from aluminum to copper as the metal for interconnect s facilitates development of different diffusion barrier materials, deposition techniques, and fabrication processes for the IC industry. Titanium nitride (TaN) was used as the diffusion barrier material in the aluminum based interconnect era, but it is not an appropriate candidate for copper interconnect s due to the major concern that its oxidation takes place over 500 Ta N is an alternative for copper interconnect s. It has been shown that physical vapor deposition ( PVD) deposited TaN films have good performance as a diffusion barrier, but CVD and atomic layer deposition ( ALD) deposited TaN films are

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28 more resistive because of the preferential growth of Ta3N5 instead of TaN by CVD and ALD,22 which means TaN cannot be used in future IC generation s. As a result investigation of new materials for the diffusion barrier application is needed. Furthermore, the d ual d amascene process flow as mentioned before, is developed for copper metallization. Copper electroplating requires deposition of copper seed layer since the diffusion barrier film is not as conductive.23,24 Therefore, mor e fundamental research and studies are required to better understand the relation between the new material and deposition process. Influence of type of diffusion barrier and deposition techniques used for not only diffusion barrier film, but also copper interconnect on reliability of integrated ci rcuits is obvious as expected. Researchers have investigated the dependence of the copper electromigration phenomenon on different diffusion barrier material s, such as titanium ( Ti ) titanium nitride ( TiN ) and tantalum nitride ( TaN ) Copper seed layer deposition by different techniques have also been researched and discussed. For instance, copper seed layer deposition by elect roless plating, CVD, and PVD ha s been reported. The dependence of diffusion barrier material s and the deposition method used in fabr ication arise from the properties of the material used and the difference in microstructure and physical properties such as morphology It is also important to consider processing the sample, either before and after deposition. It has been found

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29 that heat treatment is beneficial to improving film reliability. For example, it has been found that electromigration resistance of the electroplated Cu film is enhanced by annealing, and the electromigration resistance is increased with an increase in annealing temperature within certain temperature range. In the copper metallization scheme of d ual d amascene, a copper seed layer is needed. The copper seed lay e r is expected to have a strong texture, a smooth surface, and good adhesion strength in order to promote the subsequent growth of a highly textured copper film by the following electroplating (EP), also known as electrochemical deposition (ECD). The interrelationship is com plicated by texture, grain size of the diffusion barrier film and the copper seed layer in the multistacked films. As a result, a thorough examination of the influences of the diffusion barrier layer has on the copper seed layer and the electroplated copper film is required. Barrier ty pe effects on the microstructure and reliability of copper metallization will be discussed in my present work. Depositi ng the copper seed layer can be done by PVD, which offers a fairly high deposition rate, strong texture, and good adhesion to the underl ying film, bu t it is not suitable for technology beyond the 45nm generation due to its poor step coverage.25 CVD provides better comformality so it is capable of filling features with high aspect

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30 ratio s.2629 However, the adhesion strength is reported to be weaker when deposited on certain diffusion barriers. Comparison of copper seed layers deposit ed by different techniques on vari ous potential diffusion barriers i s presented. Additionally, the effects of orientation of the substrate have not yet been revealed to the best of my knowledge, so two kinds of substrates ( Si( 100) and Si( 111) ) are used for comparison while other reaction conditions and films deposited remained the same. Copper bulk filling is done by electrochemical deposition, which has been shown to have lowest cost, highest production rate and ease of adoption. Numerous factors such as solution concentration of copper sulfate, pH value of the solution, and voltage applied are said to affect the film properties.30 Deposition of copper fill by ECD under different conditions and its effects are also examined.

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31 Figure 11 Process steps for the fabrication of a via and line level by the dual damascene approach (a) Insulator deposition. (b) via definition. (c) line definition ( d ) barrier and seed layer deposition. (e) plating and CMP.

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32 Figure 12 S chematic crosssection of a metallization structure. Figure 13 Interconnect structure for RC analysis. Two metal interconnects with dimensions of W, L, H lying on SiO2.

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33 CHAPTER 2 L ITERATURE REVIEW 2. 1 D eposition M ethods for Thin Films Several deposition techniques have been used in thin film deposition applications, including physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD) P rinciples and characteristics of those deposition techniques will be explained and elucidated in this chapter. 2.1.1 Physical Vapor Deposition (PVD) Evaporation, a physical depositio n method, was used in early semiconductor fabrication but is not suitable for future IC generations. As the lateral dimension of electronic devices shrink the ability to cover surface topography, which is also known as step coverage, becomes increasingly important T he poor step coverage of evaporation results in nonconformal and discontinuous films. Another disadvantage of evaporation is that the production of a well controlle d alloy is difficult to achieve, which limits the use of evaporation. Sputtering, which had its debut in 1852, was used as an alternative t o evaporation. Compared to evaporation, sputtering provides better step coverage and the feasibility of depositing compound material s and alloys. Other advantages of sputtering include composition consistency between the target material and deposited film can be slightly different, good film adhesion strength, and ease of deposition. In fact, step

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34 coverage remains a crit ical issue as the scaling of microelectronics continues since sputtering fail s to deposit conformal films in high aspect ratio features. 2.1.2 Chemical Vapor Deposition (CVD) C hemical vapor deposition (CVD) resolves filling high aspect ratio conformality issues and has become a widely accepted thin film deposition method in semiconductor industry CVD involves homogeneous and heterogeneous reactions There are many variants of CVD, such as plasma enhanced CV D (PECVD), low pressure CVD (LPCVD), metal organic CVD (MOCVD) and atomic layer CVD (ALCVD or ALD). CVD has been widely used as a film deposition technique for dielectrics, metals, nitrides, and other materials T he following i s a brief introduction of the most versatile one used in IC industry M etal organic chemical vapor deposition (MOCVD) also known as organometallic chemical vapor deposition (OMCVD) and vapor phase epitaxy (MOVPE), utilizes metal organic compounds as a precursor. Since III V semiconductors and their alloys have been grown by MOC VD successfully, the i mplementation of MOCVD becomes the most popular growth technique for compound semiconductors. In a CVD reactor, m etal organic precursors a re transported by a carrier gas from a bubbler to the reaction chamber through connected tubing. Depending on the particular

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35 precursor being used, careful control of temperature to avoid recondensation of the vapor in the tubing is necessary for some metal organic compounds These compounds are then delivered to a heated substrate surface. There are several advantages of MOCVD. F or instance, becaus e the precursor used in MOCVD may not necessarily contain halides as ligands, the byproducts formed may not be corrosive and would not need special handling. Consequently, t he chances that the underlying layer is etched decrease. However, there are some drawbacks of metal organic precursors. F or instance, t he carbon containing ligand can result in byproducts that incorporate into the film as impurities A lthough f ilm compositions with the proper amount of carbon is beneficial because it increases the mechanical stability of the deposited film excess carbon incorporated in the film will lead to an increase in film resistivity and is not suitable for diffusion barrier application. ALD is a variant of CVD, and its application in deposition of diffusion barrier s and copper seed layer s have been investigated.31 ,32 Different from general CVD, precursors used in ALD are transferred into the reaction chamber in a sequential manner. In practice, one reactant is first introduced into the chamber and chemi sorbs onto the surface of the substrates until the surface is saturated. E xcess reactants are then purged away After removal of nonreacted precursors of the first reactant, a second reactant is

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36 sent to the surface to react with the chemisorbed first reac tants. T he reaction chamber is then purged again. Films grow by repeating this cycle, adding a monolayer of atoms with each introduction of reactant The most impressi ve feature of this technique is that it can be used to grow very thin film with high precision due to its self limiting growth nature. Besides, ALD also offers excellent conformality and low impurity level ALD s growth rate is intrinsically slow, because only a fraction of layer can be grown per reaction cycle. The slowness is not an issue in future IC fabrication but rather a desirable feature since the thickness needed is always decreasing. 2.2 Characterization Film properties depend not only on its material propert ies but also microstructure and morphology of the deposited film. Therefore, characterization of the film is important. Some important information about the film includes composition, crystallography, surface roughness, electrical resistivity, thickness, morphology, and adhesion between two superposed layers. Summarized use and characteristics of several techniques are presented as the following. 2.2.1 X Ray Diffraction (XRD) X ray diffraction (XRD ) is a nondestructive analytical method that can be used to obtain crystallographic structure, degree of preferred orientation, physical properties

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37 such as grain size, and chemical composition of materials. XRD is based on obtaining the scattered beam intensity of an X ray beam as a function of incident and scattered angle. In powder XRD, identification of unknown material can be done by comparing the diffraction data with a database supplied by International Centre of Diffraction Data. When the film thickness is very thin (1 1000nm), the signals of the thi n film are very wea k, h owever mostly very intense peaks stemming from substrate can be observed instead. To get a stronger signal from the film itself instead of that from the substrate, grazing incidence X ray diffraction (GIXRD) can be utilized. The very small incidence angle of the primary beam results in longer path traveled by X ray and therefore the information comes more from the thin film. 2.2.2 X ray Photoelectron Spectroscopy (XPS) Chemical composition of the film can be obtained by X ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), energy dispersive X ray spectroscopy (EDS), and others XPS, also known as electron spectroscopy for chemical analysis (ESCA), is a power ful tool that can be used to measure the elemental composition of material quantitatively, and the oxidation state of each element. XPS is a surface analysis technique. Sample surface is irradiated by X ray with a probe depth of 10nm. The functionality and capability of AES is similar t o XPS. AES is surface sensitive

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38 and i t can be applied to obtain elemental composition of the film. In addition to composition determination, the use of argon sputtering equipped in both XPS and AES make it possible to perform depth profiling of deposited films Another feature that XPS and AES have in common is that they can be used to detect most of the elements in nature, except for hydrogen and helium. 2.2.3 Energy D ispersive X ray S pectroscopy (EDS) Energy dispersive X ray spectroscopy (EDS) is another analytical technique that has the ability to perform elemental analysis of material. However, this technique is considered as a way to determine composition of material only semi quantitatively since the accuracy of the spectrum is dependent on so many factors. Elements that can be detected by using this technique are those with atomic number greater than four. 2.2.4 Scanning E lectron M icroscopy (SEM) Scanning electron microscopy (SEM) is often used to measure surface morphology and topography of samples. The contrast shown on the SEM image also reveal s information about atomic number difference. During operation, a h igh energy electron beam strikes specimen surface and interacts with atoms in the sample, and then ejected electrons are captured by a detector. Those electrons can be either secondary electron or back scattered electrons. Secondary electrons result ing from inelastic scattering of the

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39 incoming electron beam near or at the specimen surface are general ly insensi tive to atomic number Therefore, secondary electrons can provide very high resolution images of the specimen surface. Back scattered electrons, on the other hand, arise from elastic scattering although they are also influenced by inelastic scattering. Bac kscattered electrons are atomic number dependent: the higher the atomic number, the more electrons escape the surface of specimen. Thus, the image of back scattered electrons can be used to obtain the distribution of elements i n the specimen. Techniques that are commonly used in determination of film thickness are crosssectional scanning electron microscopy (XSEM) and transmission electron microscopy (TEM) Both SEM and TEM can provide highly accurate information about film thickness. The p rofilometer is another piece of equipment that can be used to measure film thickness. The vertical resolution of a profilometer is in the nanometer level but accurate profiling of the film requires experienced operation. Another common use of profilometer is measurement of surface roughness 2.2.5 A tomic F orce M icroscopy (AFM) As mentioned above, a profilometer is an instrument that is used to measure surface roughness. Another apparatus that is also frequently used for the same purpose is atomic force microscopy (AFM). AFM is a destructive apparatus because the surface

PAGE 40

40 is scanned across and scratched by a probe; a cantilever. T he r esolution of AFM can be a fraction of nanometer. AFM allows measurement of root mean square (RMS) surface roughness and average grain size. The advantage of AFM over SEM is that AFM gives 3 dimensional profile of the sample, while SEM offers a 2 dimens ion al image of a sample. Furthermore, AFM does not require high vacuum environment, which lowers the cost on the equipment and maintenance. 2.2.6 Four Point Probe Measurement of resistivity of thin films is usually done by the four point probe. Sheet resis tance can be measured by passing current through two outer probes and simultaneously measuring the voltage through two inner probes. Knowing the thickness of the film, film resistivity can then be readily derived by multiplying the sheet resistance by the film thickness. 2.2.7 Scotch Brand Tape Test Scotch brand tape test is the most common method used to determine adhesion strength qual itatively. A sticky tape is attached to the film and then removed to see how good the adhesion of the film is to the underlying layer. To determine the adhesion strength quantitatively, another technique, four point bend test is one of the choices.

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41 CHAPTER 3 E XPERIMENTAL TECHNIQUES FOR THIN FILM DEPOSI TION AND CHARACTERIZATION 3.1 Substrates U sed for Ex periments and Precleaning of the Substrates Substrates used in this study are 500550 type Si( 100) doped with boron by Cemat Silicon S.A. and 505545 thick n type Si( 111) doped with arsenic by Crysteco. All the substrates are cleaned by a standard process described as the following: Substrates dipped in boiling trichloroethylene (TCE) for 3 minutes Substrates dipped in boiling acetone for 3 minutes Subs trates dipped in boiling methanol for 3 minutes Substrates dipped in boiling deionized water (DI water) for 30 s ec onds Substrates dipped in buffer oxide etch (BOE) solution for 2 minutes Substrates cleaned by swab soaked in acetone Substrates dried in con tinuous nitrogen flow 3.2 Description of the S puttering R eactor KJL CMS 18 Multi So urce wa s used to deposit the diffusion barrier films : Ta, TaN, Ta/TaN multistack, W2N, and part of the copper seed layers. It is a Combinatorial Material Science thin film sputtering system. The temperature of the process chamber wa s maintained at around 20 Since silicon oxide is formed very quickly in air atmosphere, before diffusion barrier/copper deposition, substrates wer e sputter cleaned with argon ions in the reaction chamber for 60 sec onds to remove silicon oxide formed

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42 during the time of air exposure before entering the vacuum chamber. Deposition of each material wa s done by following recipes in the computer where deposition rates we re known, although with certain level of error. By putting in the desired film thickness, the co rresponding time of deposition wa s then determined. The thickness of the singl e layer diffusion barrier, Ta, wa s 25nm S ince the deposition rate of Ta wa s 2.84 p er second, the deposition time wa s 88 sec onds The thickness of the single layer diffusion barrier of TaN wa s also 25nm, given deposition rate of 0.83 p er second, the deposition time wa s 300 sec onds For the doublelayer diffusion barrier of Ta/TaN, the thickness of each layer wa s set to be 20nm and 25nm, respectively. The deposition time of each layer wa s 71 s econds and 300 sec onds respectively. Deposition of W2N wa s fabricated by reactive sputtering in argon/nitrogen atmosphere ( Ar/N2).3336 It has been reported by researchers that W2N phase is formed when the molar ratio of N2 to Ar is greater than 1. Accordi n gly, the p re ssure set point of the chamber wa s 10 mTorr. The gas flow rate of Ar wa s 29.1sccm, and the gas flow rate of N2 wa s 42.1sccm. The thickness of the W2N film wa s 30nm, and the deposition time wa s 143 sec onds since the deposition rate wa s 2.1 per second.

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43 3.3 Description of CVD Reactor A n in house built chemical vapor deposition (CVD) reactor wa s used as another means to deposit copper seed layer s. The reactor has two chambers, one used for atomic layer deposition (ALD) for diffusion barrier films and the other is a CVD chamber designed for copper deposition. The reactor set up permits insitu transfers of samples The system wa s equipped with gas lines for delivery of nitrogen, ammonia, helium, and h ydrogen gas. T he metal organic gas lines we re wrapped with heating tapes to avoid recondensation of vapor precursor in the tubing. Gas flow rate s are controlled by an MKS mass flow controller. The precursor wa s kep t in a quartz tube bubbler and wa s transported to the reactor by nitrogen, as a car rier gas once the valves on i n let and out let we re open. T he temperature of the bubbler bath wa s maintained at 45 to 46 3.4 Precursor for C u Deposition The precur sor used for copper deposition wa s copper (I) hexafluoropentanedionate vinyltrimethylsilane (copper(hfac)(vtms)). 3.5 Operating Procedure for CVD Reactor 3.5.1 Pretreatment for the S amples and CVD D eposition P rocedure Before copper deposition t ook place, the reaction chamber wa s first pumped down to base pressure of approximately 0.26 Torr and then hydrogen gas wa s introduced into

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44 the reactor to reduce the oxide formed on the substrate surface for 10 minutes at 200 After re duction of the oxide the precursor wa s delivered into the reaction chamber for copper deposition. The susceptor wa s heated by a resistive heate r and the reaction temperature wa s kept at 185 The r eaction time lasted 70 minutes for each run resulting in a copper seed layer with thickness around 70nm. The flow rate of hydrogen wa s fixed at 196sccm, and wa s 50 sccm for t he nitrogen carrier gas. The growth rate of copper wa s around 1 nanometer per minute and wa s determined by dividing thicknes s by reaction time. Detail s concerning copper film growth rate will be clarified later. After the reaction wa s completed, the heater wa s shut off while the reactor was still kept under vacuum. Sam ples we re taken out from the reactor after about 2 hours to let them cool to near room temperature to prevent rapid oxide form ation due to high therm al energy. 3.5.2 Growth Rate Cu S eed L ayer D eposi tion by Metallo Organic Chemical Vapor Deposition ( MOCVD ) The growth rate of the MOCVD grown Cu seed layer was measured by depositing Cu film s under identical condition s less the duration to allow growth of thicker Cu film s. The thickness of th e Cu film was measured by cross se ctional SEM and t he Cu growth rate was then determined by dividing the measured thickness by the reaction time.

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45 Fig ure 31 shows the cross sectional image of Cu film deposited on silicon substrate for 120 minutes The Cu film was about 120nm thick so the growth rate of Cu film was 1nm/min. 3.6 Electroplating (EP) of Cu Bulk Fill 3.6.1 Parameters for Electrochemical Deposition Electroplating (also called electrochemical deposition (ECD )) of Cu wa s performed to grow thick er Cu film. Samples de posited with a copper seed layer we re attached to the cathode, which is a copper bar A g raphite bar wa s used as an anode. A s aturated Calomel electrode (SCE) wa s used as the reference electrode. The solution consist ed of 0.01M copper sulfate (CuSO4) sulfuric acid (H2SO4) and deionized water. The pH value of th e solution wa s adjusted to around 3 to 4, tested by hydrion papers The applied voltage wa s set to be 5 00mV. 3.6.2 Growth Rate EP Cu Fill A gain, the growth rate of electroplated Cu was determined by dividing th e thickness of Cu electroplated on the Cu seed layer by the time of the reaction. A c ross sectional view of EP Cu on Ta was examined, and the thickness of EP Cu was around 800nm as shown in Figure 32 The r eaction time for electro plating was 600 sec onds for all runs Thus, t he growth rate was 1 .33nm/sec.

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46 3.7 Techniques for Thin Film Characterization 3.7.1 X Ray Diffraction (XRD) Thin film crystallinity was examined by a Philips APD 3720. The s cattering angle, and 40 to 55 2 degree. X ray radiation was generated by applying 40 kV and 20 mA to emit Cu K radiation. The w avelength of the emitted X ray s i s 1.54 P eaks obtained from the XRD spectra were compared with reference spectra in the Joint Committee on Powder Diffraction Standards ( JCPDS) database. The extent of cry stallinity and phase of the material can therefore be determined by the relative peak intensit ies and the peak positions. Peak positions in XRD can be used to calculate the lattice parameter of a unit cell. The inter planar spacing, d, is obtained by using Braggs law. d = (3 1) wh is the wavelen gth of the X ray, which is 1.54 The lattice parameter, a, for a cubic cell can be acquired from the equation = (h2+k2+l2) (3 2) w here h, k ,and l are Miller indices. For a hexagonal crystal, the lattice parameter s, a and c, can be calculated by equation = (h2+hk+k2)+ (l2) (3 3)

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47 Grain size can also be determined by XRD. The broadening of the peak is correlated to the grain si ze of the film by the Scherrer equation. = (3 4) is Xis the line broadening at half the maximum intensity (FWHM) in radians, and is the Bragg angle. is the mean size of the ordered domai ns, which may be smaller or equal to the grain size. The shape factor K is typically 0.9, but will vary with the actual shape of the crystal. Data processing and analysis were done by using the software XPert Plus and performed Microsoft Excel. Background correction and smoothing of the curve were as to reduce the noise level and identify peaks in the spectra. 3.7.2 Scanning Electron Microscopy (SEM) Morphology of the surface and t hickness of the films wa s measured by a JOEL 6335F FEG SEM. Electrons we re generated by applying 15 kV on a single crystal tungsten tip. Secondary electrons escaping from the surface after interaction with the sample we re collected by a detector. Secondar y electrons have lower energy and are generated near the surface. They can be used to obtain feature images (morphology/topography) of the film. Thickness of the films wa s obtained by measuring the cross section of the films. For film thic kness measurement, each sample wa s first

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48 dipped into liquid nitrogen for 15 seconds and then scratched and cleaved into two smaller pieces with a diamond pen. The sample was then positioned vertically to allow examination of its cross section. Copper tape was used to attach the samples to the stub and to avoid charging effect. 3.7.3 Four Point Probe The f ilm sheet resistance and resistivity we re measured by a four point probe. The f our point probe i s a common method used for characteriz ing semiconductor s, a s it provides absolute measurement without the need of standard. Four tips are lined up in a row and c urrent is passed through the two outer tips and then the voltage across the two inner tips is measured. The distances between the tips are determined from mathematical derivation so a simple equation for sheet resistance is given by equation. R= 4 .53 (3 5) w here V is the voltage across the two inner tips and I is the current passing through two outer tips. Once the sheet resistance is obtained, the resistivity of the calculated by E quation 3 6 = R t (3 6) where t is the film thickness, which can be obtained from cross sectional SEM image.

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49 3.7. 4 Scotch Brand Tape Test Scotch tape was used to test how adhesive the deposited film i s to its underlying layer. Peeling of the films occurs when adhesion between the deposited film and the underlying layer is poor.

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50 A) B) Figure 31. SEM c ross sectional images of Cu deposited by MOCVD for 120 minutes A) X45,000 B) X100,000

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51 A) B) Figure 32. SEM cross sectional images of EP Cu after 10 min utes A) X8,000 B) X15,000.

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52 CHAPTER 4 SUBSTRATE EFFECTS ON DIFFUSION BARRIER, COPPER SEED LAYER, AND COPPER BULK FILL Two blanket silicon substrates with different crystallographic orientations ( Si( 100) and Si( 111) ) we re used for subsequent diffusion barrier layer deposition, copper seed layer deposition, and bulk copper fill The effects of the orientation of substrate have not been studied to the best of my knowledge. T wo common and promising diffusion barrier systems Ta/TaN and W2N were us ed here. To begin with, diffusion bar rier film s were deposited onto two different silicon substrates at the same time, which means that both films were grown under the exact same deposition condition including deposition time, deposition temperature, and deposition rate. The Cu seed layer was deposited by MOCVD and electrochemical deposition was performed to make thicker Cu layer s, thereafter After deposition of each layer, the film deposited was examined by XRD, SEM, four point probe, and an adhesion test. T he dependence of substrate effect on diffusion barrier materials i s discussed. 4.1 X Ray Diffraction Measurement 4.1.1 Film Crystallinity Figure 4 1 A show s the XRD spe ctr um for Ta/ TaN films deposited by sputtering. XRD spectra of Ta/TaN multilayer show that on Si( 100) and Si( 111) the Ta/TaN

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53 multilayers are amorphous as indicated by amorphous humps in the spectra (not shown in the spectra here since they are background corrected) disregarding the crystal o rientation of the substrate they were grown on. Only peaks of the silicon substrates ( = 69.23 for Si( = 28.44 for Si( 111) ) appeared in the spectr a Since Ta/TaN films deposited on both Si( 100) and Si( 111) had poor crystallinity, the films we re very likely amorphous and the grain sizes we re very small. The crystal structure of W2N is cubic. Three most intensive peaks of W2N within the scanning range are expected to appear at 37.734, 43.848, and 63.734 degrees. Again, the XRD spectra show that W2N films we re amorphous since no peaks appear ed i n the spectra for W2N sputtered on Si( 100) and Si( 111) Copper seed layers, 70 to 80nm thick, were deposited on each of the diffusion barri ers on Si( 100) and Si( 111). The XRD measurement was conducted as to compare the degr ee of crystallinity of Cu seed layer with respect to different underlying substrates. In general, copper has a crystal structure of facecentered cubic (fcc), and f o r Cu metal degrees. It should be noticed that the 43.297 peak arises from (111) oriented plane s, and 50.433 results from (200) planes. The texture of the Cu film is not always the strong (111) orientation, and the change in strength of (111) and the presence of

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54 other peaks is related to many experimental factors.37 Since the Cu( 111) orientation shows the best resistance toward electromigration and has the lowest elect rical resistivity of any textures the XRD peak intensity ratio of I(111) to I(200) becomes a measure of how good the film is in terms of electronmigration resistance and electrical resistivity. However, determination of the intensity of peaks existing in the spectra wa s difficult since the background noise level was high and the amorphous hump introduced ambiguity As a result, background correction was applied to data analysis. After the background was correct ed for smoothing of the data was performed to reduc e the noise level. Figure 4 3 shows the background corrected XRD spectrum of the Cu seed layer deposited onto the Ta/TaN stacks on two types of s ubstrates On both substrate types, the I(111)/I(200) ratio was 3.55. It can be referred from this result, that the substrate orientation has no bearing on the Cu seed layer When W2N was grown as a diffusi on barrier, the crystal orientation of the copper seed layer has to be discussed in a different way. The XRD spectra of the Cu seed layer on W2N are shown in Figure 44. The I(111)/I(200) ratio was 1.79 for the Cu seed layer deposited on W2N/ Si( 100) When Si( 111) was used as the substrate, the ratio I(111)/I(200)

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55 was 3.2. Dis similar to the result when Ta/TaN was used, Cu seed layer (MOCVD) deposited on W2N had higher I(111)/I(200) when Si( 111) was applied as a substrate. T he t exture of electroplated (EP) Cu on Cu seed layers w as also e xamined in order to investigate how a c hange in substrate effect s the electroplated Cu films In the had a very intensive Cu( 111) peak em smaller Cu( 200) peak appearing at around as shown in Figure 45 I(111)/I(200) was calculated for each sample to demonstrate the degree of preferred (111) orientation as follows. R esults of electroplated Cu on a Cu seed layer deposited by MOCVD were obtained. Firstly, when Ta was deposited as an interlayer between TaN and electroplated Cu for better adhesion strength between TaN and Cu, I(111)/I(200) was found to be 4. 09 for electroplated Cu on MOCVD Cu seed layer/Ta/TaN/ Si( 100) and 3.49 for that on MOCVD Cu seed layer/Ta/TaN/ Si( 111). Secondly Cu electroplated on MOCVD Cu seed layer/W2N/ Si( 100) gave I(111)/I(200) of 4.75, and that on MOCVD Cu seed layer/W2N/ Si( 111) gave a value of 8.71.

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56 4.1.2 Polycrystal Grain Size The grain size can be estimated using the Scherrer equation assuming that the broadening of the peaks in the XRD spectra resulted from the crystallite grain size dis tribution. The most intens e peak, the Cu( degrees, was used to determine FWHM and estimate the grain size. Estimated grain sizes of Cu seed layer (MOCVD) are listed in Table 41 and Table 4 2. W hen the Ta/TaN stack was used as diffusion barrier, the average grain size o f Cu seed layer deposited by MOCVD was 36.2nm when Si( 100) was the substrate, and was 54.4nm when Si( 111) was the substrate. W hen deposited on W2N, Cu seed layer had the average grain size of 54.4 nm on Si( 100) and 72.4nm on Si( 111). Table 43 and Table 44 show the estimated grain size of EP Cu on different diffusion barriers on different substrates. Grain sizes of electroplated Cu were also estimated by using the Scherrer equation. F or Ta/TaN the grain size was calculated to be 72.4nm for electroplated Cu on CVD deposited Cu seed layer/Ta/TaN/ Si( 100) and 61.9nm for electroplated Cu on CVD deposited Cu seed layer/Ta/TaN/ Si( 111). A s light difference in grain size was obtained for electroplated Cu on MOCVD deposited Cu when W2N was used as a diffusion barrier. T h e estimated grain size was 89.0nm and

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57 87.2nm for electroplated Cu on MOCVD deposited Cu/W2N/ Si( 100) and that on CVD deposited Cu seed layer/W2N/ Si( 111), respectively. 4.2 Scanning Electron Microscopy Scanning electron m icroscopy was utilized to examine the morphology (i .g. grain size and shape of the grains ) of Cu films deposited on top of Ta/TaN, and W2N on two different substrates Also the grain size distribution was determined For diffusion barriers deposited by sputtering, no grains can be seen even under maximum magnification, X 5 0 0 000. T his might be a result from : (1) the diffusion barrier films deposited by sputtering were so smooth that the topography did not lead to change in contrasts from secondary electrons (2) grains were too small to be resolved by SEM. (3) the deposited layer were not conductive enough and therefore charging of electrons took place. The cause can be figured out by either using TEM to get to higher magnification and see if grains can be resolved or coating the diffusion barriers to increase the electrical conductivity. As for the Cu seed layer grown by MOCVD, s urface morphology was examined by using SEM. Two magnifications ( X 30, 000, and X 70, 000 ) were used to obtain the average grain size and the grain size distribution of the Cu seed layer. Five gr ains in

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58 each of the SEM images with clear boundar ies were chosen and their average grain size s were measured. SEM images of the Cu seed layers deposited by MOCVD onto the Ta/TaN bilayer system on Si( 100) and Si( 111) are shown in Figure 46 For the Cu seed layer deposited on Ta/TaN/ Si( 100), two groups of grains with slightly different grain sizes were observed; their size ranged from around 50nm to 170nm. A s i milar result was obtained for Cu seed layer deposited on Ta/TaN/ Si( 111). A similar approach was taken for W2N based diffusion barriers As shown in Figure 4 7, t he grains of the Cu seed layer were large. In both case, the average grain size was greater than 100nm. Since sufficient ly many size grains were formed in the Cu film was observed in both cases, t he size uniformity of the Cu seed layer was poorer. However, grains in the copper film were spherical. The Cu seed layer seemed to be discontinuous on W2N as can be seen i n the SEM images. T he grain siz e s varied drastically from 20nm to more than 200nm. This phenomenon occurred in both Si( 100) and Si( 111). The only difference was that the Cu seed layer on the Si( 111) had larger grains and were more densely distributed. Therefore, the average grain size of Cu seed layer on Si( 111) was slightly larger than that on Si( 100).

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59 The s urface morp hology for elec troplated Cu was observed via SEM as well. SEM images are shown in Figure 48 and Figure 4 9 The grain s of electroplated Cu were much larger than those deposited by MOCVD as discussed above. N ormally two different sizes of grains were observed, including one group of larger grains with sizes 700 to 800nm, and the other group contained smaller grains whose diameters we re just a few tens of nanometers. 4.3 Film Resistivity Sheet resistance was measured by a four point probe and the resistivity was then readily calculated by multiplying the measured sheet resistance by the film thickness. Since the films were thin, the electrical properties of the film were not easy to measure because the measured values fluct uated drastically if not enough care was taken. In order to minimize instrumental error, the sheet resistance was measured five times and the average of those values was taken as the sheet resistance of that sample. All Cu seed layers here were deposited b y MOCVD, followed by ECD for thicker films A ll the films resistivities are listed in Table 43 to Table 44. Ta/TaN on Si( 100) had a sheet resistance of 4.88 with thickness of 90nm, and the film resistivity was therefore 43.92 cm The s ame multi stack Ta/TaN deposited on Si( 111) had a sheet resistance of 1.55 which corresponded to a film resistivity of

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60 13.95 cm Sheet resistances of W2N measured were 2N on Si( 1 00) and 2N on Si( 111), which corresponded to film resistivities o cm and cm, respectively Since the deposition time for all experiments was fixed at 70 minutes the thicknesses of Cu seed layers were al l approximately 70 nm. The s heet resistance of the Cu seed layer on the Ta/TaN stack on two types of silicon substrates was obtained. For Cu seed layer deposited on Ta/TaN on Si( 100) and Si( 111), t he sheet resistances were 65.06 and 67.68Si( 100) was cm for tha t on Si( 111). T he dependence of resistivity on orientation of silicon substrate in the Ta/TaN bilayer case was not significant. When W2N was deposited as a diffusion barrier, the difference in sheet resistance, as well as resistivity was obvious. The Cu seed layer on S i( 100) had a lower sheet resistance of 69.8 compared with 129.2 for that on Si( 111). The calculated resistivities were 0.484 cm and 0.904 cm for the Cu seed layer on Si( 100) and Si( 111), respectively. 4.4 Scotch Brand Tape Test Sco tch tape tests were conducted to determine the adhesion strength of Cu films to its underlying layers qualitatively. Cu films grown on different types of Si substrates

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61 were compared. For the Cu s eed layer deposited by MOCVD when the Ta/TaN stack was used as a diffusion barrier, a small amount of Cu debris was removed by the tape after test (denoted as pass (fair)) regardless of the substrate used. The s ame thing occurred to the Cu seed layer (MOCVD) on W2N, and even more Cu was found on the tape (denoted as pass (poor)) for the case when W2N was deposited on Si( 100). For EP Cu, removal of Cu happened for all the samples, complete removal of the Cu film was observed (denoted as fail) in the case where EP Cu was deposited on Ta/TaN/ Si( 111). T able 48 and Table 49 summarize the test results.

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62 A) B ) C) D) Figure 41. XRD spectra for sputtered Ta/TaN on different Si substrates. A) Si( 100) with scanning range from 25 to 70 2 degrees B) Si( 100) with scanning range from 40 to 55 2 degrees C) S i( 111) with scanning range from 25 to 70 2 degrees D) Si( 111) with scanning range from 40 to 55 2 degrees. 25 45 65Intentsity (a.u.)2 DegreesSi(100) 40 45 50 55Intensity (a.u.)2 Degrees 25 45 65Intensity (a.u.)2 Degrees 40 45 50 55Intensity (a.u.)2 Degrees

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63 A) B) C) D) Figure 42 XRD spectra for sputtered W2N on different Si substrates. A) Si( 100) with scanning range from 25 to 70 2 degrees B) Si( 100) with scanning range from 40 to 55 2 degrees C) Si( 111) with scanning range from 25 to 70 2 degrees D) Si( 111) with scanning range from 40 to 55 2 degrees. 25 45 65Intensity (a.u.)2 DegreesSi(100) 40 45 50 55Intensity (a.u.)2 Degrees 30 40 50 60 70Intensity (a.u.)2 Degrees 40 45 50 55Intensity (a.u.)2 Degrees

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64 A) B) C) D) Figure 43. XRD spectra for Cu seed layer ( MOCVD)/ Ta/TaN on different Si substrates. A ) S i( 100) with scanning angle from 25 to 70 2 degrees B) Si( 100) with scanning angle from 40 to 55 2 degrees C) Si (111) with scanning angle from 25 to 70 2 degrees D) Si( 111) with scanning angle from 40 to 55 2 degrees. 25 45 65Intensity (a.u.)2 DegreesSi(100) 40 45 50 55Intensity (a.u.)2 Degrees Cu(111) Cu(200) 25 45 65Intensity (a.u.) 2 Degrees Cu(111) Cu(200) Si(111) 40 45 50 55Intensity (a.u.) 2 Degrees Cu(111) Cu(200)

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65 A) B ) C) D) Figure 44. XRD spectra for Cu seed layer deposited by MOCVD on W2N/ Si( 100) and W2N/ Si( 111) A) W2N / Si( 100) with scanning angle from 25 to 70 2 degrees B) W2N / Si( 100) with scanning angle from 40 to 55 2 degrees C) W2N / Si( 111) with scanning angle from 30 to 65 2 degrees D) W2N / Si( 111) with scanning angle from 40 to 55 2 degrees. 25 45 65Intensity (a.u.)2 DegreesSi(100) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200) 30 40 50 60Intensity (a.u.)2 DegreesCu(111) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200)

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66 A) B) C) D) Figure 45. XRD spectra for electroplated (EP) Cu / Cu seed layer ( MOCVD)/diffusion barriers/different Si substrates A) T a/TaN / Si( 100) with scanni ng angle from 40 to 55 2 degrees B) Ta/TaN/ Si( 111) with scanning angle from 40 to 55 2 degrees C) W2N / Si( 100) with scanning angle from 40 to 55 2 degrees D) W2N / Si( 100) with scanning angle from 40 to 55 2 degrees. 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200)

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67 Table 41. Estimated grain size of MOCVD Cu seed layer / Ta/TaN on Si( 100) and Si( 111) Ta/TaN FWHM G rain size (nm) Cu seed layer/Ta/TaN/Si(100) 0.236 43.354 36.2 Cu seed layer/Ta/TaN /Si(111) 0.157 43.383 54.4 Table 42 Estimated grain size of MOCVD Cu seed layer / W2N on Si( 100) and Si( 111) W2N FWHM G rain size (nm) Cu seed layer/W2N/Si(100) 0.157 43.459 54.4 Cu seed layer/W2N/Si(111) 0.118 43.453 72.4 Table 43. Estimated grain size of EP Cu/Cu seed layer (MOCVD) / Ta/TaN on Si( 100) and Si( 111) Ta/TaN FWHM G rain size (nm) EP Cu/Cu seed layer/Ta/TaN/Si(100) 0.118 43.35 72.4 EP Cu/Cu seed layer/Ta/TaN/Si(111) 0.138 43.41 61.9 Table 44. Estimated grain size of EP Cu/Cu seed layer (MOCVD) / W2N on Si(100) and Si( 111) W2N FWHM G rain size (nm) EP Cu/Cu seed layer/W2N/Si(100) 0.096 43.37 89.0 EP Cu/Cu seed layer/W2N/Si(111) 0.098 43.40 87.2

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68 A) B) C) D) Figure 46. SEM images of Cu seed layer ( MOCVD)/Ta/TaN on different Si substrates. A) Si( 100) X70,000. B) Si( 100) X30,000. C) Si( 111) X70,000. D) Si(1 11) X30,000.

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69 A) B) C) D) Figure 47. SEM images of Cu seed layer ( MOCVD)/W2N on different Si substrates. A) Si( 100) X70,000. B) Si( 100) X30,000. C) Si( 111) X70,000. D) Si( 111) X30,000.

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70 A) B) C) D) Figure 4 8. SEM images of EP Cu / Cu seed layer (MOCVD) /Ta/TaN on different Si substrates. A) Si( 100) X30,000. B) S i( 100) X12,000. C) Si( 111) X30,000. D) Si( 111) X12,000.

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71 A) B) C) D) Figure 4 9 SEM images of EP Cu / Cu seed layer (MOCVD) /W2N on different Si substrates. A) Si( 100) X30,000. B) Si( 100) X10,000. C) Si(111) X30,000. D) Si( 111) X12,000.

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72 Table 45 Film resistivity of Ta/TaN and W2N on Si( 100) and Si( 111) Film resistivity cm) Ta/TaN/Si(100) 0.455 Ta/TaN/Si(111) 0.473 W2N/Si(100) 312 W2N/Si(111) 446 Table 46 Film resistivity of Cu seed layer (MOCVD) on Ta/TaN/ Si( 100) and Ta/TaN/ Si( 111) Ta/TaN 1 2 3 4 5 average cm) Cu seed layer/Ta/TaN/Si(100) ( 67.5 65.3 62.4 68.8 61.3 65.06 0.455 67.2 65.3 67.5 71.3 67.1 67.68 0.474 Table 47 Film resistivity of Cu seed layer (MOCVD) on Ta/TaN/ Si( 100) and Ta/TaN/ Si( 111) W2N 1 2 3 4 5 average resistivity cm) Cu seed layer/W2 74.9 74.3 61.6 69.6 65 69.1 0.484 Cu seed layer/W2 130 162 117 114.8 122.2 129.2 0.904

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73 Table 48 Adhesion test for Cu seed layers deposited on different types of Si substrates Ta/TaN Cu seed layer (MOCVD)/Ta/TaN/ Si( 100) fail Cu seed layer (MOCVD)/Ta/TaN/ Si( 111) fail W2N Cu seed layer (MOCVD)/W2N/ Si( 100) fail Cu seed layer (MOCVD)/W2N/ Si( 111) fail Table 49 Ad hesion test for EP Cu on different types of Si substrates Ta/TaN EP Cu/Cu seed layer (MOCVD)/Ta/TaN/ Si( 100) fail EP Cu/Cu seed layer (MOCVD)/Ta/TaN/ Si( 111) fail W2N EP Cu/Cu seed layer (MOCVD)/W2N/ Si( 100) fail EP Cu/Cu seed layer (MOCVD)/W2N/ Si( 111) fail

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74 CHAPTER 5 DIFFUSION BARRIER EF FECTS ON MOCVD DEPOSITED COPPER SEED LAYER, AND ELECROPLATED COPPER Four different refractory metal systems (i.e. Ta, TaN, Ta/TaN, and W2N) were used as diffusion barrier s. All of them were deposited by sputtering onto Si( 100) substrates following the same recipes described previously. Cu seed layers discussed here were deposited by metallorganic chemical vapor deposition (MOCVD) since CVD is an excellent technique for obtaining uniform step coverage on small feature sizes D iffusion barrier effectiveness on MOCVD deposited Cu seed layer and the subsequent electroplated Cu fill were examined with respect to their texture, grain size, surface morphology, film resistivity, and strength of adhesion after deposition. 5 .1 X Ray Diffraction Measurement 5 .1.1 Film Crystallinity XRD spectra were obtained for all four diffusion barriers deposit ed on Si( 100). XRD spectra for Ta, TaN, Ta/TaN, and W2N are shown in Fig ur e 51 and Figure 52 The spectra were obtained for angles from 3 0 to 70 or 30 to 55 2 degrees. It can be seen that except for the intense substrate peaks sitting at around 33 and 69.2 2 degrees, no other peaks were shown. Therefore, amorphous films were obtained via sputtering.

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75 Cu seed layers deposited by MOCVD were examined by XRD As shown in Figure 5 3A and Figure 53 B the XRD spectra for MOCVD deposited Cu seed layer s on Ta have peak arising at around 43.21 2 degrees which is indicative of Cu( 111) N o peak for Cu( 200) i s found. For Cu seed layer deposited by MOCVD onto TaN, both Cu( 111) and Cu( 200) peaks appear at 43.40 and 50.18 respectively as shown in Figure 53C and Figure 53D However, the Cu( 200) peak was not very distinct from the background, and the I(111)/I(200) was calculated to be 5.4 Shown in Figure 54 A and Figure 54 B are the XRD spectra for MOCVD Cu seed layers deposited on Ta/TaN. For this multistack diffusion barrier system, clearly two peaks arise at 43.45 and 50.51 degrees f rom Cu( 111) and Cu( 200) respectively. The I(111)/I(200) ratio was 3.55. When W2N was employed as a diffusion barrier, as shown in Figure 54C and Figure 54D, both peaks for Cu( 111) and Cu( 200) appeared. The Cu( 111) peak emerged at 43.46 and the Cu( and the calculated I(111)/I(200) ratio was 1.79. The Cu seed layer deposited by MOCVD therefore served as a conductive path for electrons. Cu fill was then electroplated onto Cu seed layer on various diffusion barrier systems and XRD measurement s w ere conducted. T he angles w ere sc anned from 40 to T he peak intensities for both Cu( 111) and Cu( 200) increase due to the

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76 increase in film thickness from about one hundred to several hundred nanometers XRD spectra for them are shown in Figure 55 For electroplated Cu on Cu seed layer (MOCVD) /Ta / Si( 100) peaks for Cu( 111) and Cu( degrees and I(111)/I(200) was calc ulated to be 4.04. For electroplated Cu on MOCVD deposited Cu/TaN, two distinct peaks for Cu( 111) and Cu( 200) appear at 43.36 and 50.52 are shown on the spectra, and the I(111)/I(200) obtained was 3.02. For electroplated Cu on MOCVD deposited Cu/Ta/TaN, peaks for Cu( 111) and Cu( 200) with I(111)/I(200) equaled 4.09. For electroplated Cu on MOCVD deposited on Cu/W2N, peaks for Cu( 111) and Cu( 200) are shown at 43.37 and 50.51, respectively. The I(111)/I(200) for it was 4.75. 5 .1.2 Polycrystal Grain Size E sti mates of grain sizes were determined using the Scherrer equation. Table 51 shows the estimated grain size of Cu seed layer (MOCVD) grown on different diffusion barriers. T he grain sizes estimated for Cu seed layer (MOCVD) deposited on Ta, TaN, Ta/TaN, and W2N are 27.1, 43.4, 36.2, and 54.4 nm. Since the peaks appearing in XRD spectra for electroplated Cu were much sharper than that of Cu seed layer deposited by MOCVD, the estimated grain sizes were expected to be larger. T able 5 2 shows the grain sizes of electroplated Cu on different diffusion barrier system estimated by

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77 Scherrer equation. F or Ta used as a diffusion barrier, the estimated grain size was 87.2nm W hen TaN was used, th e estimated grai n size was 72.4nm. F or Cu electroplated onto the Ta/TaN multilayer, the est imated grain size was also 72.4nm. F or the case where was W2N used as a diffusion barrier, the estimated grain siz e for electroplated Cu was 89.0nm. 5.2 Scanning Electron Microscopy N othing was seen in SEM images for all diffusion barriers deposited here by sputtering, and possible reasons have been discussed in Chapter 4. F or Cu seed layers deposited by MOCVD, SEM was used to examine the surface morphology grain size and grain size uniformity as shown in Figure 56 to Figure 59 T he grains of Cu seed layer deposited on Ta were by and large very uniform. T he average grain size obtained from averaging five diameters of gr ains in the sample was about 70nm G rains of Cu seed layer by MOCVD on TaN were not so spherelike instead their shapes were irregular. T he average grain size for these were more than 90nm. F or Ta/TaN there seemed to be two groups of different size grains of Cu seed layer formed on top of the diffusion barrier s ystem. T he larger ones had diameter about 1.5 times that of the smaller ones. The size of the smaller grains was about 70nm, and that of the other was about 110 nm. Grain size variation came to an extreme when W2N was used as a diffusion

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78 barrier. I n this case, two groups of grain sizes were found; one with a grain size of around 20nm and the other with a grain size of 200nm. I t should als o to be not ed that grains of the Cu seed layer deposited by MOCVD were loosely seated on the diffusion barrier, and the Cu film was therefore not continuous. F or bulk Cu electroplated on various kinds of diffusion barriers, grain sizes seemed to be less uniform than seed layer Cu as shown in the SEM images (Figure 510 to Figure 513) W hen Ta was employed as a diffusion barrier, small features were seen in the bulk Cu while the grain boundaries were not very clear and the grain size was hard to determine. W hen TaN was used, two definite groups of bulk Cu grain sizes were obtained. The grain size of the sm aller grain group w as about 100nm whereas the grain size of the lar ger group was more than 1ly populated on top of the smaller ones. The grain size of electroplated Cu on Ta/TaN was different since the grain size was relatively more uniform compared to that in other cases The grain size of the electroplated Cu was about 100nm. When W2N was used, still two groups of diff erent size grains were observed ; o ne with grains larger than 1 the other one with smaller grains underneath.

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79 5.3 F our Point Probe Measurement Table 5 4 shows the sheet resistance and film resistivity of Cu seed layers deposited on diffusion barriers. The deposition time f or diffusion barrier layers w as set such that the film thicknesses for TaN, Ta, Ta/TaN, and W2N 25 nm, 25n m, 20nm/25 nm, and 30nm, respectively. The thickness of the Cu seed layer deposited by MOCVD was 70nm. The s hee t resistance for Cu seed layer deposited on Ta w as 94.04, and t he correspond ing film resistivities were 0.66 cm The average sheet resistance of sputtering deposit ed Cu seed layer on TaN was 97.72 and its film resistivity was 0.68 cm The f ilm resis tivity of Cu on Ta/TaN was 0.46 cm The measured film resistivity for Cu film on W2N/ Si( 100) was 0.48 cm 5.4 Scotch Bran d Tape Test Adhesion strength of Cu seed layers deposited by MOCVD and EP Cu films to their underlying layers were compared with respect to different diffusion barriers used. The results are listed in Table 5 5 and Table 56. Generally neither Cu seed layers nor EP Cu showed strong adhesion performance, Cu was more or less removed by the tapes after tests. Peeling of EP Cu happened when EP Cu was deposited on TaN.

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80 A) B) C) D) Figure 51. XRD spectra of A), B) Ta on Si(100) C), D) TaN on Si(100) 30 40 50 60 70Intensity (a.u.)2 DegreesSi(100) 30 35 40 45 50 55Intensity (a.u.)2 Degrees 30 40 50 60 70Intensity (a.u.)2 DegreesSi(100) 30 35 40 45 50 55Intensity (a.u.)2 Degrees

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81 A) B ) C) D) Figure 52 XRD spectra of A), B) Ta/TaN on Si( 100) C), D) W2N/ Si( 100) 30 40 50 60 70Intensity (a.u.)2 DegreesSi(100) 30 40 50Intensity (a.u.)2 Degrees 30 40 50 60 70Intensity (a.u.) 2 Degrees Si(100) 30 35 40 45 50 55Intensity (a.u.)2 Degrees

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82 A) B) C) D) Figure 53 XRD spectra of A), B) Cu seed layer (MOCVD)/Ta/Si(100). C),D) Cu seed layer (MOCVD)/TaN/Si(100). 25 35 45 55 65Intensity (a.u.)2 DegreesSi(100) 35 40 45 50 55Intensity (a.u.)2 DegreesCu(111) 25 35 45 55Intensity (a.u.)2 Degrees Cu(111) 35 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200)

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83 A) B) C) D) Figure 54 XRD spectra of A), B) Cu seed layer (MOCVD)/Ta/TaN/Si(100) C), D) Cu seed layer (MOCVD)/W2N/Si(100) 25 45 65Intensity (a.u.)2 DegreesSi(100) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200) 25 45 65Intensity (a.u.)2 Degrees Si(100) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200)

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84 A) B) C) D ) Figure 55 EP Cu on Cu seed layer (MOCVD) on diffusion barriers/ Si( 100) A) TaN B) Ta. C) Ta/TaN D) W2N 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200)

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85 Table 51. Estimated grain size of Cu seed layer (MOCVD) deposited on diffusion barriers/ Si( 100) Ta FWHM G rain size (nm) Cu seed layer/Ta/Si(100) 0.315 43.21 27.1 TaN FWHM G rain size (nm) Cu seed layer/TaN/Si(100) 0.197 43.40 43.3 Ta/TaN FWHM G rain size (nm) Cu seed layer/Ta/TaN/Si(100) 0.236 43.35 36.2 W2N FWHM G rain size (nm) Cu seed layer/W2N/Si(100) 0.157 43.46 54.4 Table 52. Estimated grain size of EP Cu /Cu seed layer (MOCVD)/ diffusion barriers/Si (100) Ta FWHM G rain size (nm) E P Cu/CVD Cu seed/Ta/Si(100) 0.098 43. 40 87.2 TaN FWHM G rain size(nm) E P Cu/CVD Cu seed/TaN/Si(100) 0.118 43.36 72.4 Ta/TaN FWHM G rain size(nm) E P Cu/CVD Cu seed/Ta/TaN/Si(100) 0.118 43.35 72.4 W2N FWHM G rain size(nm) E P Cu/CVD Cu seed/W2N/Si(100) 0.096 43.37 89.0

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86 A) B) Figure 56 SEM images of Cu seed layer (MOCVD) on TaN/ Si( 100) A) X30,000. B) X70,000. A ) B ) Figure 57 SEM images of Cu seed layer (MOCVD) on Ta/ Si( 100) A) X30,000. B) X70,000.

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87 A) B) Figure 58 SEM images of Cu seed layer (MOCVD) on Ta/TaN/ Si( 100) A) X30,000. B) X70,000. A) B) F igure 59 SEM images of Cu seed layer (MOCVD) on W2N/ Si( 100) A) X30,000. B) X70,000.

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88 A) B) Figure 510. SEM images of EP Cu/Cu seed layer (MOCVD) deposited on TaN/ Si( 100) A) X10,000 B) X 85,000. A) B) Figure 511 SEM images of EP Cu/Cu seed layer (MOCVD) deposited on Ta/ Si( 100) A) X4,000. B) X13,000.

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89 A) B) Figure 512 SEM images of EP Cu/Cu seed layer (MOCVD) deposited on Ta/TaN /Si (100) A) X 12,000, B) X30 ,000. A) B) Figure 513 SEM images of EP Cu/Cu seed layer (MOCVD) deposited on W2N/Si(100) A) X4,000. B) X1 0 ,000.

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90 Table 53 Film resistivity of Cu seed layers (MOCVD) on diffusion barriers/ Si( 100) 1 2 3 4 5 cm) TaN Cu seed layer/TaN/Si(100) 105 99 100 88 94 97.72 0.684 Ta Cu seed layer /Ta/Si(100) 91 100 92 91 93 94.04 0.658 Ta/TaN Cu seed layer/Ta/TaN/Si(100) 67 65 62 68 61 65.06 0.455 W2N Cu seed layer/W2N/Si(100) 74 74 61 69 65 69.08 0.484

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91 Table 54 Adhesion test for Cu seed layer deposited on different diffusion barriers Ta Tape test Cu seed layer (MOCVD)/Ta/ Si( 100) F ail TaN Cu seed layer (MOCVD)/TaN/ Si( 100) F ail Ta/TaN Cu seed layer (MOCVD)/Ta/TaN/ Si( 100) F ail W2N Cu seed layer(MOCVD)/W2N/ Si( 100) F ail Table 55 Adhesion test for EP Cu deposited on Cu seed layer (MOCVD)/ different diffusion barriers Ta Tape test EP Cu/Cu seed layer (MOCVD)/Ta/ Si( 100) fail TaN EP Cu/Cu seed layer (MOCVD)/TaN/ Si( 100) fail Ta/TaN EP Cu/Cu seed layer (MOCVD)/Ta/TaN/ Si( 100) fail W2N EP Cu/Cu seed layer(MOCVD)/W2N/ Si( 100) fail

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92 CHAPTER 6 DEPOSITION TECHNIQUE EFFECTS ON MOCVD DEPOSITED COPPER SEED LAYER, AND ELECT ROPLATED COPPER P hysical vapor deposition (PVD) has been used successfully for thin film deposition in the IC industry. H owever, PVD is no longer an acceptable method of deposition for future miniaturized integrated circuits ( ICs ) since it is a line of sight deposition method, which results in poor step coverage of high aspect ratio features. CVD is now the predominant method used in industry for thin film deposition as it has been shown to have excellent step coverage. Fi lm properties vary when different deposition methods are employed, therefore t his part of the work was aimed a t explor ing the difference in film properties between Cu seed layers deposited by sputtering and MOCVD. The deposition method effects on the subsequent electroplated Cu film s were examined as well PVD and MOCVD were used to deposit Cu seed layers on two different substrates (e.g. Ta/TaN and W2N) on Si( 100) Electrochemical deposition was then used to deposit thicker Cu films onto those Cu seed layers. Film properties were readily examined by different techniques.

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93 6.1 X Ray Diffraction Measurement 6.1.1 F ilm Crystallinity Figure 6 1 shows the background corrected XRD in the case where Cu seed layer were deposited by MOCVD or sputtering onto Ta/TaN / Si( 100) The ratio of I(111)/I(200) was 3.55 for Cu seed layer deposited by MOCVD In the case where Cu seed layer was deposited by sputtering, the ratios of I(111)/I(200) increased to 6.93. Figure 62 shows XRD spectra for Cu seed layers deposited by MOCVD and sputtering w hen W2N was grown as a diffusion barrier T he crystal orientation of the Cu seed layer has to be discussed in a different way. The I(111)/I(200) ratio was 1. 79 for Cu seed layer grown by MOCVD In the case where Cu seed layer was deposited by sputtering, the (200) peak seemed to be immersed in the background noise, and only the (111) peak appear ed. Since the sputtered Cu seed layer had a stronger (111) peak, it is a better choice over Cu seed layer deposited by MOCVD in terms of crystal lographic orientation. T he t exture of electroplated Cu on two groups of Cu seed layers w as also examined in or der to investigate the deposition technique effects. In the scanning range Cu( 111) peak Cu( 200) peak appearing

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94 at around 50.4(111)/I(200) was calculated for each sample to demonstrate degree of preferred (111) orientation as follows. F irst, results of Cu electroplated on sputtered Cu seed layer were obtained. I(111)/I(200) was found to be 4.09 for electroplated Cu on MOCVD Cu seed layer/Ta/TaN/ Si( 100).C alculated I(111)/I(200) for electroplated Cu on sputtered Cu seed layer/Ta/TaN/ Si( 100) was 4.16. When W2N was applied as a diffusion barrier, electroplated Cu on sputtered Cu seed layer/W2N/ Si( 100) had a I(111)/I(200) of 3.64, and Cu electroplated on MOCVD Cu seed layer/W2N/ Si( 100) gave I(111)/I(200) of 4.75. 6.1.2 Polycrystal Grain Size Estimated grain size of Cu seed layers and EP Cu are listed in Table 61 to Table 6 4. The grain sizes were estimated by the Scherrer equation assuming that the broadening of the peaks in the XRD spectra resulted from the crystallite grain size distribution. Again, t he most intensive peak, Cu( 111) degrees, was used to determine FWHM and estimate the grain size. For CVD deposited copper films grown on Ta/TaN double layer diffusion barrier, the average grain size was 36.2nm when Si( 100) was used as the substrate. For Cu seed layer sputter deposited onto a Ta/TaN double layer, t he estimated grain size for

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95 was qui t e different and was 21.7nm When deposited on W2N, Cu seed layer formed by MOCVD had the average grain size of 54.4nm on W2N/ Si( 100) On the other hand, f or sputter deposited Cu seed layer on W2N/ Si( 100) t he estimated grai n size of Cu on W2N/ Si( 100) was 27.1nm Larger grains were obtained when the Cu seed layer was deposited by MOCVD no matter which diffusion barrier system was used. Grain sizes of electroplated Cu fill were also estimated using the Scherrer equation. Substrate effects were examined with respect to Cu seed layer deposited by two different techniques as well. F or Cu seed layer deposited by sputtering and Ta/TaN multilayer was employed as a diffusion barrier the estimated grain size of electroplated Cu on sputtered Cu/Ta/TaN/ Si( 100) was 87.2nm. F or Cu fill electroplated onto Cu seed layer deposited by MOCVD, grain size was calculated to be 72.4nm W hen W2N was used, estimated grain size of electroplated Cu on s puttered Cu seed layer/W2N/ Si( 100) was 71.2nm. Estimated grain size of electroplated Cu on Cu seed layer deposited by MOCVD on W2N/ Si( 100) was 89.0nm. 6.2 Scanning Electron Microscopy Just f o r Cu seed layer grown by MOCVD, s urface morphology was examined using SEM. Two magnifications, 30, 000X, and 70, 000X, were used to obtain the average grain size and the grain size distribution of the Cu seed layer However, grains of Cu seed

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96 layers deposited by sputtering would not be seen under SEM presumably became the surface of the sputtered Cu films w as to o smooth and the grains were too small. SEM images of EP Cu were observed for both types of Cu seed layers (deposited either by MOCVD or sputtering). SEM images of surface morp hology for electroplated Cu were observed and are shown in Figure 65 and Figure 6 6 Grains of electroplated Cu were much larger than t h ose deposited by MOCVD as discussed above. T wo different sizes of grains were observed. O ne group of larger grains had a size around 700 to 800n m, and the other group contained smaller grains whose diameters were just few tens of nanometers. F or Cu electroplated onto sputtered Cu/Ta/TaN/ Si( 100), grains were closely packed and their sizes were pr etty uniform and were about 700nm as shown in Figure 65. F or W2N as a diffusion bar rier two groups of grains were observed for EP Cu grown on Cu seed layer deposited by MOCVD, but not in the sputtered Cu seed layer case. EP Cu on MOCVD Cu had high population of grains that were larger than 1 m, however, there seemed to be smaller grains everywhere. Electroplated Cu on sputtered Cu/W2N/ Si( 100) was found to have uniformly and closely packed grains with size about 0.8

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97 6 .3 Film Resistivity Film resistivities were measured by four point probe. The results were obtained from averages of five measurement s for each sample. The deposition time for each dif fusion barrier w as set such that the film thicknesses for Ta/TaN, and W2N were grown to 20nm/25nm, and 30nm, respectively. Since the deposition time for all experiments was fixed to be 70 minutes the thicknesses of Cu seed layers deposited by MOCVD were all approximately 70nm. On the other hand, t he expected thick ness of the sputter ed Cu seed layer was 100nm. The sheet resistances and their corresponding resistivities of Cu seed layer for all of t he diffusion barriers used are listed i n Table 65. The s heet resistance of Cu seed layer deposited by MOCVD on Ta/TaN on Si( 100) substrate was obtained. For Cu seed layer deposited on Ta/TaN on Si( 100) the sheet resistances were 65 The film resisti vity of Cu seed layer on Si( 100) was cm Sheet resistance and film resistivity for sputtering deposited Cu seed layer on Ta/ TaN/ Si( 100) was 1 172m and 11.72 cm respectively. When W2N was deposited as diffusion barrier, difference in sheet resistance as well as resistivity was obvious. Cu seed layer deposited by MOCVD on Si( 100) had a sheet resistance of 69.8 cm for Cu seed

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98 layer on Si( 100) The sheet resistance of sputtered Cu on W2N/ Si( 100) was 1.946 t he film resistivity for sputtered Cu film on W2N/ Si( cm 6.4 Scotch Brand Tape Test Adhesion strength w as tested by using Scotch tape and the results are list ed in Table 66 and Table 67 Cu seed layers deposited by sputtering showed very strong adhesion to the underlying layer, no matter what kind of diffusion barrier was employed. Nothing was removed by the tape and no visible change on the film surface was observed. However, for Cu seed layers deposited by MOCVD, films remained on the substrates but very small amount of Cu debris was found on the tape after the test. For EP Cu, Cu films did not adhere to the underlying films very well no matter which technique was used to deposit the Cu seed layer. S i gnificant amount s of Cu were found on the tape after tests. Moreover, complete removal of EP Cu and its underlying layer occurred when EP Cu was deposited on sputtered Cu seed layer on Ta/TaN/ Si( 100). Film resistivity of Cu seed layers showed good consistency. For both diffusion barrier systems that were employed, MOCVD Cu seed layers possessed much lower film resistivities as shown in Figure 611.

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99 A) B) C) D) Figure 61. XRD spectra of Cu seed layers on Ta/TaN/ Si( 100) A) Cu seed layer ( MOCVD) with angle scanning from 25 to 70 2 degrees B) Cu seed layer ( MOCVD) with angle scanning from 40 to 55 2 degrees C) Cu seed layer ( sputtering) with angle scanning from 35 to 65 2 degrees D) Cu seed layer ( sputtering) with angle scanning from 40 to 55 2 degrees. 25 45 65Intensity (a.u.)2 DegreesSi(100) 40 45 50 55Intensity (a.u.)2 Degrees Cu(111) Cu(200) 35 45 55 65Intensity (a.u.)2 Degrees Cu(111) 35 45 55 65Intensity (a.u.)2 DegreesCu(111)

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100 A) B) C) D) Figure 62. XRD spectra of Cu seed layers on W2N/ Si( 100) A) Cu seed layer ( MOCVD) with angle scanning from 25 to 70 2 d egrees B) Cu seed layer ( MOCVD) with angle scanning from 40 to 55 2 degrees C) Cu seed layer ( sputtering) with angle scanning from 25 to 70 2 degrees D) Cu seed layer ( sputtering) with angle scanning from 40 to 55 2 degrees. 25 45 65Intensity (a.u.)2 DegreesSi(100) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200) 25 45 65Intensity (a.u.)2 DegreesSi(100) 40 45 50 55Intensity (a.u.)2 DegreesCu(111)

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101 A) B) Figure 63. XRD spectra of EP Cu/Cu seed layer (MOCVD or sputtering)/Ta/TaN/Si (100) A) EP Cu/Cu seed layer (MOCVD)/Ta/TaN/ Si( 100), B) EP Cu/sputtered Cu seed layer/Ta/TaN/ Si( 100) A ) B ) Figure 64. XRD spectra of EP Cu/Cu seed layer (MOCVD or sputtering)/W2N/Si(100) A) EP Cu/Cu seed layer (MOCVD)/W2N/ Si( 100) B) EP Cu/sputtered Cu seed layer/W2N/ Si( 100) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200) 40 45 50 55 In tensity (a.u.) 2 DegreesCu(111) Cu(200) 40 45 50 55Intensity (a.u.)2 DegreesCu(111) Cu(200)

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102 Table 6 1 Estimated grain size of Cu seed layer on Ta/TaN/ Si( 100) Ta/TaN FWHM G rain size (nm) Cu seed layer (MOCVD)/Ta/TaN/Si(100) 0.236 43.35 36.2 Cu seed layer (sputtering)/Ta/TaN/Si(100) 0.315 43.49 27.1 Table 62. Estimated grain size of Cu seed layer on W2N/ Si( 100) W2N FWHM G rain size (nm) Cu seed layer (MOCVD)/W2N/Si(100) 0.315 43.43 27.1 Cu seed layer (sputtering)/W2N/Si(100) 0.315 43.29 27.1 Table 63. Estimated grain size of EP Cu on Ta/TaN/ Si( 100) Ta/TaN FWHM G rain size (nm) EP Cu/Cu seed layer (MOCVD)/Ta/TaN/Si( 100) 0.118 43.35 72.4 EP Cu/Cu seed layer (sputtering)/TaN/ Si( 100) 0.098 43.37 87.2 Table 64. Estimated grain size of EP Cu on W2N/ Si( 100) W2N FWHM G rain size (nm) EP Cu/Cu seed layer (MOCVD)/W2N/ Si( 100) 0.096 43.37 89.0 EP Cu/Cu seed layer (sputtering)/W2N/ Si( 100) 0.12 43.38 71.2

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103 A) B) C ) D) Figure 65. SEM images of EP Cu/Cu seed layer (MOCVD or sputtering)/Ta/TaN/ Si( 100) A) EP Cu/Cu seed layer (MOCVD)/Ta/TaN/ Si( 100) X4,000. B) EP Cu/Cu seed layer (MOCVD)/Ta/TaN/ Si( 100) X12,000. C) EP Cu/Cu seed layer (sputtering)/Ta/TaN/ Si( 100) X4,000. D) EP Cu/Cu seed layer (sputtering)/Ta/TaN/ S i( 100) X10,000.

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104 A) B) C) D) Figure 66 SEM images of EP Cu/Cu seed layer (MOCVD or sputtering)/W2N/ Si( 100) A) EP Cu/Cu seed layer (MOCVD)/ W2N/ Si( 100) X4,000. B) EP Cu/Cu seed layer (MOCVD)/W2N/ Si( 100) X10,000. C) EP Cu/Cu seed layer (sputtering)/ W2N/ Si( 1 00) X4,000. D) EP Cu/Cu seed layer (sputtering)/ W2N/ Si( 100) X10,000.

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105 Table 65. Film resistivity of Cu seed layer deposited on Ta/TaN and W2N 1 2 3 4 5 average resistivity cm) Ta/TaN Cu seed layer (MOCVD)/Ta/ TaN/Si(100) 67 65 62 68 61 65.06 0.45542 Cu seed layer (sputtering)/Ta/ TaN/Si(100) 1220 1210 1190 1140 1100 1172 11.72 W2N Cu seed layer (MOCVD)/W2N/ Si(100) 74 74 61 69 65 69.08 0.48356 Cu seed layer (sputtering)/ W2N/Si(100) 2810 1790 1810 1760 1560 1946 19.46

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106 Table 66. A dhesion test for Cu seed layer deposited by different techniques Ta/TaN Tape test Cu seed layer (MOCVD)/Ta/TaN/ Si( 100) pass Cu seed layer (sputtering)/Ta/TaN/ Si( 100) pass W2N Cu seed layer (MOCVD)/W2N/ Si( 100) fail Cu seed layer (sputtering)/W2N/ Si( 100) pass Table 67. Adhesion test for EP Cu deposited on Cu seed layers grown by different techniques Ta/TaN Tape test EP Cu/Cu seed layer (MOCVD)/Ta/TaN/ Si( 100) fail EP Cu/Cu seed layer (sputtering)/Ta/TaN/ Si( 100) fail W2N EP Cu/Cu seed layer (MOCVD)/W2N/ Si( 100) pass (fair) EP Cu/Cu seed layer (sputtering)/W2N/ Si( 100) pass (poor)

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107 CHAPTER 7 CONCLUSION C rystallographic orientation of silicon substrate, i.e., Si( 100) and Si( 111) did not show an influence on (111) texture of Cu seed layer deposited by MOCVD or the subsequently grown EP Cu layer when Ta/TaN was used as diffusion barrier whereas effect of cr ystallographic orientation of silicon substrate was found to have an effect when W2N was employed. I n this case, Cu seed layer s deposited on Si( 111) had a stronger (111) texture, and the i nheritance of (111) texture promoted stronger (111) texture in the subsequent EP Cu. With regard to grain size, Cu seed layer and EP Cu deposited on Si( 111) had larger grains compared with that on Si( 100) for both Ta/TaN and W2N diffusion barriers. H owever, the grain size difference extinguished when Cu was electroplated on the seed layers. H igher electrical resistivity was found on Cu seed layer deposited on Si( 111). S puttered diffusion barriers obtained here were amorphous, and the (111) texture of Cu seed layers varied with the diffusion barrier used. H owever, inheritance of (111) texture was not shown in the following EP Cu. I ndeed, the strength of (111) texture of EP Cu did not change much no matter what diffusion barrier was used. G rain size of Cu seed layers was smallest when Cu seed layer was grown on Ta and was two times

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108 larger when deposited on W2N. Nevertheless, the size difference diminished again after Cu electrochemical deposition. F ilm resistivity for Cu seed layers deposited on various diffusion barriers did not show much difference. Cu seed layers deposited by sputtering had stronger (111) texture than those deposited by MOCVD. H owever, stronger (111) texture obtained by sputtering did not result in a significant impact on the following EP Cu N amely, I(111)/I(200) were close for EP Cu on both sputtered Cu seed layer and MOCVD seed layer. In addition to not being a line of sight process, t he m erit of Cu seed layer deposited by MOCVD was that it grew larger grains compared to sputtering. S ince large Cu grains, uniform distribution, strong (111) texture, smooth and adhesive Cu, and low electrical resistivity of Cu are desirable features to achieve higher reliability in future IC metallization, Si( 111) is a better substrate then Si( 100) given the inheritance of (111) orientation in Cu grown on Si( 1 11). Weak dependence was found regarding different diff usion barriers used, so the choice of diffusion barrier can be based on the performance of this layer to prevent Cu from diffusing through it. T echniques for Cu seed layer deposition did make differenc e in the grain size, (111) texture, and adhesion strength but not in the following EP Cu since EP Cu have been known to undergo a process called self annealing or room temperature recrystallization after

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109 growth, which significantly alter s its microstru cture .3840 T he MOCVD is better than then sputtering with respect to the ability of conformal step coverage.

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110 LIST OF REFERENCES 1 Gordon E. Moore, Electronics 38, 8 ( 1965) 2 Mark T. Bohr Electron Devices Meeting, 1995. International. 3 P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkanes, and H. Deligianni, IBM Journal of Research and Development 42, 567 ( 1998). 4 S. Vaidya, D B. Fraser, and W. S. Lindenberger J. Appl. Phys 51, 8 ( 1980) 5 J, Cho and C. V. Thompson, Appl. Phys. Lett. 54, 19 ( 1989) 6 YoungChang Joo and Carl V. Thompson, J. Appt. Phys. 76, 1 ( 1994) 7 E. Glickman and M. Nathan, J. Appl. Phys. 80, 1 ( 1996) 8 Lucile Arnaud, G. Tartavel, T. Berger, D. Mariolle, Y. Gobil, and I. Touet Microelectronics Reliability 40, 77 (2000) 9 Shoso Shingubara and Yasushi Nakasaki Appl. Phys. Lett. 58, 7 ( 1991) 10 G. Schneider, D. Hambach, B. Niemann, B. Kaulich, J. Susini, N. Hoffmann, and W. Hasse Appl. Phys. Lett. 78, 1936 (2001). 11 Hau Riege, C. S. and Thompson, Appl. Phys. Lett. 78, 3451 (2001). 12 Hu, C., Gignac, L. and Rosenberg, R. Microelectronics and Reliability 46, 213 (2006). 13 Vairagar, A., Mhaisalkar, S. and Krishnamoorthy, A. Microelectronics Reliability 44, 747 (2004). 14 Kwon, D., Park, H. and Lee, C. Thin Solid Films 475, 58 (2005).

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111 15 Carter W. Kaanta, Susan G. Bombardier, William J. Cote, William R. Hill, Gloria Kerszykowski, Howard S. Landis, Dan J. Poindexter, Curtis W. Pollard, Gilbert H. Ross, James G. Ryan, Stuart Wolff, and John E. Cronin VMIC Conference, June 1991. 16 M. Stan g l J. Acker, S. Oswald, M. Uhlemann, T. Gemming, S. Baunack, and K. Wetzig Microelectronic Engineering, 84, 54 (2007). 17 M. Stangl, J. Acand ker, S. Oswald, M. Uhlemann, T. Gemming, S. Baunack, and K. Wetzig, Microelectronic Engineering, 85, 534 (2008). 18 L. Castoldi, G. Visalli, S. Morin, P. Ferrari, S. Alberici, G. Ottaviani, F. Corni, R. Tonini, C. Nobili, and M. Bersani, Microelectronic Engineering, 76, 153 (2004) 19 M. H. Tsai and S. C. Sun, Appl. Phys. Lett. 68, 4 ( 1996) 20 R. Ecke, S.E. Schulz, M. Hecker, and T. Gessner Microelectronic Engineering, 64, 261 (2002) 21 Bystrova, S., A arnink, A. A. I., Holleman, J. Wolters, and R. A. M., Journal of The Electrochemical Society 152, G522 (2005). 22 Ajit Paranjpe, Randhir Bubber. Lino Velo, Guihua Shang, Sanjay Gopinath, Jer emie Dalton and Mehrdad Moslehi IEEE International Conference, 1999. 23 E. K. Broadbent, E. J. McInerney and L. A. Gochberg, and R. L. Jackson J. Vac. Sci. Techno l. B 17, 6 ( 1999) 24 E. C. Cooney I II, D. C. Strippe, and J. W. Korejwa, A. H. Simon and C. Uzoh. J. Vac. Sci. Technol. A 17, 4 ( 1999) 25 R. Rosenberg, D. C. Edelstein, C. K. Hu, and K. P. Rodbell, Annu. Rev. Mater. Sci., 30, 229 ( 2000) 26 R. Krger, M. Eizenberg, D. Cong, N. Yoshida, L. Y. Chen, S. Ramaswami, and D. Carl, Journal of The Electrochemical Society, 146, 3248 (1999)

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112 27 Kim, Y. S. and Shimogaki, Y. Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 19, 2642 (2001). 28 Kim, H. and Shimogaki, Y. Journal of The Electrochemical Society 154, G13 (2007). 29 Hoon Kim, Yasuhiko Kojima, Hiroshi Sato, Naoki Yoshiim Sgugetoshi Hosaka and Yukihiro Shimogaki, Japenese Journal of Applied Physics, 45, L233 (2006) 30 Darko Grujicic and Batric Pesic, Electrochimica Acta 47, 2901 (2002) 31 Ofer Sneh, Robert B.Clark Phelps, Ana R.Londer gan, Jereld Winkler, and Thomas E.Seidel Thin Solid Films 402, 248 ( 2002) 32 Raj Solanki and Balu Pathangey Electrochemical and SolidState Letters, 3 479 (2000). 33 Guruvenket, S. Materials Science and Engineering B 106, 172 (2004). 34 Y. G. Shena) and Y. W. Mai, D. R. McKenzie, Q. C. Zhang, and W. D. McFall, W. E. McBride Journal of A pplied P hysics, 88, 3 ( 2000) 35 Lee, K. S. Japanese Journal of Applied Physics 42, 3368 (2003). 36 Y.G. ShenU, Y.W. Mai., Surface and Coatings Technology 127, 246 (2000) 37 D. P. Tracy D. B. Knorr and K. P. Rodbell J. Appl. Ph ys. 76, 5 ( 1994) 38 Lee, H., Wong, S. S. and Lopatin, S. D. J. Appl. Ph ys, 93, 3796 ( 2003). 39 J. M. E. Harper, C. Cabral, Jr., P. C. Andricacos, L. Gignac, I. C. Noyan, K. P. Rodbell, and C. K. Hu J. Appl. Ph ys. 86, 5 ( 1999) 40 Kazuyoshi Ueno, Tom Ritzdorf and Scott Grace J. Appl. Ph ys. 86, 9 ( 1999)

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113 BIOGRAPHICAL SKETCH Chien Tsung Chen was born in Taipei, Taiwan in 1985. H e is the son of KuoWen Chen and BaoChu Hsieh, and has a sister, YingJhen Chen. He received his education in Taiwan before coming to Uni versity of Florida. He obtained his bachelor degree in chemistry from National Taiwan University in 2008 and then worked as a research assistant in Institute of Atomic and Molecular Sciences Academic Sinica, Taipei, Taiwan through June, 2009. In August 2009, he joined the master program in department of Chemical Engineering at University of Florida. After graduation, he will continue his path in pursuing a Ph.D. degree.