Complementary Metal Oxide Semiconductor Radio Frequency Integrated Circuit Blocks for High Power Applications

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Title:
Complementary Metal Oxide Semiconductor Radio Frequency Integrated Circuit Blocks for High Power Applications
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1 online resource (133 p.)
Language:
english
Creator:
Sun,Tie
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University of Florida
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Gainesville, Fla.
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Thesis/Dissertation Information

Degree:
Doctorate ( Ph.D.)
Degree Grantor:
University of Florida
Degree Disciplines:
Electrical and Computer Engineering
Committee Chair:
O, Kenneth K
Committee Members:
Gu, Qun Jane
Xie, Huikai
Crisalle, Oscar D

Subjects

Subjects / Keywords:
amplifier -- cmos -- diode -- frequency -- power -- radio -- receive -- switch -- transmit
Electrical and Computer Engineering -- Dissertations, Academic -- UF
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Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract:
As the devices in Complementary Metal Oxide Semiconductor (CMOS) integrated circuits are continuously scaled down, power consumption of CMOS circuits is lowered and their intrinsic speed is increased. This has made CMOS the dominant technology for modern radio frequency (RF) communication applications. However, to realize the fully integrated CMOS single-chip radio has been challenging because of the intrinsic drawbacks of the CMOS process, including high ohmic resistance of metallization, lossy substrate and especially low breakdown voltage for MOS transistors. These make it challenging to implement high power components in RF transceivers such as RF transmit/receive (T/R) switches and RF power amplifiers (PA). This dissertation focuses on the design of integrated T/R switches and power amplifiers in CMOS technology. An NMOS/Diode hybrid T/R switch with high power handling capability by using the high breakdown voltages of p-n junction diodes in TI 45 nm CMOS technology is first demonstrated. Substrate isolation is enhanced to improve the power handling capability of TX transistor. In order to decrease the insertion loss, layout of p-n junction diode is optimized. In addition, a novel on-chip switch DC biasing circuit is also proposed. Design and characterization of a 2.4 GHz CMOS Class-F power amplifier in UMC 130 nm CMOS technology are also demonstrated. The single-ended power amplifier consists of a tapered inverter driver and an output stage with a fully integrated third order harmonic peaking network incorporating impedance transformation. The PA exhibits 12.4 dBm saturated output power and 13.9 dB peak power gain with drain efficiency of 46.5% and power added efficiency (PAE) of 38% at 1.2 V supply voltage. Finally, a tunable multi-band watt-level power amplifier in TI 65 nm CMOS technology that can support 850 MHz and 1700 MHz operation is fabricated and characterized. The multi-band PA has an on-chip transformer based power combiner where eight differential PA?s are combined in order to achieve the watt-level output power at low supply voltage of 1.2 V. Measurements show that at 850 MHz, the saturated output power of 30.2 dBm with drain efficiency 24.3% is achieved. At 1700 MHz, the saturated output power is 29.5 dBm with drain efficiency 22.2%.
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In the series University of Florida Digital Collections.
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Includes vita.
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Includes bibliographical references.
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Description based on online resource; title from PDF title page.
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This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility:
by Tie Sun.
Thesis:
Thesis (Ph.D.)--University of Florida, 2011.
Local:
Adviser: O, Kenneth K.
Electronic Access:
RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2012-08-31

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UFE0043322:00001


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1 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR RADIO FREQUENCY INTEGRATED CIRCUIT BLOCKS FOR HIGH POWER APPLICATION S B y TIE SUN A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 201 1

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2 2011 Tie Sun

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3 To my parents

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4 ACKNOWLEDGMENTS I would like to begin by thanking my advi sor, Professor Kenneth K. O, whose constant encouragement and patient guidance provided a clear path for my research. I am deeply grateful to him for what I have learned from him, which will benefit me in my whole life. I would also like to thank Dr. Huikai Xie, Dr. Jenshan Lin Dr. Qun Gu and Dr. Oscar Crisalle for helpful suggestions and serving on the Ph.D committee. I would like to thank many of the former and current Silicon Microwave Integrated Circuit s and System s Research ( SiMICS ) group members for their friendship and invaluable technical assistance: Haifeng Xu, Chi kuang Yu, Eunyoung Seok, Swaminathan Sankaran, Kwangchun Jung, Chuying Mao, Hsinta Wu, Ning Zhang, Kyujin Oh, Dongha Shim, Wuttichai Lerdsitsomboon Minsoon Hwang Ruonan Han, Choongyul Cha, Chiehlin Wu and Yanghun Yun. I also like to thank my friends outside of the research group: Mingqi Chen, Hang Yu Yan Hu, Chun ming Tang, Jikai Chen, Zhiming Xiao, Zhichao Lu Zhenming Zhou, Qiuzhong Wu and Lin Xue. Finally, I am grateful to my brothers for their support. And I am most pleased to acknowledge the unconditional love, guidance, encouragement and suppor t of my parents. I dedicate this work to them.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ ............... 4 LIST OF TABLES ................................ ................................ ................................ ........................... 7 LIST OF FIGURES ................................ ................................ ................................ ......................... 8 ABSTRACT ................................ ................................ ................................ ................................ ... 13 CHAPTER 1 INTRODUCTION ................................ ................................ ................................ .................. 15 1.1 Background and Motivation ................................ ................................ ............................. 15 1.2 Dissertation Organization ................................ ................................ ................................ 19 2 NMOS/DIODE HYBRID TRANSMIT/RECEIVE SWITCH ................................ ............... 21 2.1 Overview ................................ ................................ ................................ ........................... 21 2.1.1 Complementary Metal Oxide Semiconductor (CMOS) Transmit/Receive (TR) Switches ................................ ................................ ................................ ....................... 21 2.1.2 Design Challenges of CMOS T/R Switch with High Power Handling Capability ................................ ................................ ................................ ..................... 24 2.2 NMOS/Diode Hybrid T/R Switch in CMOS ................................ ................................ .... 28 2.2.1 Design Target and Circuit Topology ................................ ................................ ...... 28 2.2.2 Circuit Design ................................ ................................ ................................ ......... 29 2.2.2.1 Design of transmit transistor with improved power handling capability ..... 29 2.2.2.2 Integrated p n diode design ................................ ................................ .......... 36 2.2.2.3 Switch biasing circuit design ................................ ................................ ........ 39 2.2.3 Measurement Results ................................ ................................ .............................. 46 2.3 Conclusions ................................ ................................ ................................ ....................... 52 3 2.4 GHZ CM OS CLASS F POWER AMPLIFIER ................................ ............................... 53 3.1 Overview ................................ ................................ ................................ ........................... 53 3.1.1 Radio Frequency (RF) Power Amplifier (PA) Specification Parameters .............. 53 3.1.1.1 Output power and power gain ................................ ................................ ...... 53 3.1.1.2 Efficiency ................................ ................................ ................................ ..... 53 3.1.1.3 Linearity ................................ ................................ ................................ ....... 55 3.1.2 Power Amplifier Classification ................................ ................................ .............. 56 3.1.2.1 Class A, AB, B and C power amplifier ................................ ........................ 56 3.1.2.2 Saturated transconductance amplifier ................................ .......................... 59 3.1.2.3 Class D power amplifier ................................ ................................ .............. 60 3.1.2.4 Class E power amplifier ................................ ................................ ............... 61 3.1.2.5 Class F power amplifier ................................ ................................ ............... 63

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6 3.2 2.4 GHz CMOS Class F Power Amplifier Design ................................ ........................... 65 3.3 Measurement Results ................................ ................................ ................................ ........ 73 3.4 Conclusions ................................ ................................ ................................ ....................... 77 4 MULTI BAND WATT LEVEL CMOS POWER AMPLIFIER ................................ ........... 78 4.1 Overview ................................ ................................ ................................ ........................... 78 4.1.1 Design Cha llenges of Watt Level Power Amplifier in Nano Scale CMOS ........... 78 4.1.2 Power Combining Techniques ................................ ................................ ............... 79 4.1.3 Multi B and Techniques in Power Amplifier ................................ .......................... 83 4.2 Watt Level Multi Band CMOS Power Amplifier ................................ ............................ 86 4.2.1 Watt Level Multi Band CMOS Power Amplifier Architecture ............................. 86 4.2.2 Watt Level Multi Band Power Amplifier Design ................................ .................. 92 4.2.2.1 PA output transistor design consideration ................................ .................... 92 4.2.2.2 Wideband PA driver design ................................ ................................ ......... 96 4.2.2.3 Transformer based power combiner design ................................ ................. 98 4.2.2.4 Multiband tuning circuits design ................................ ................................ 101 4.2.2.5 Bypassing of the multiband power amplifier ................................ ............. 105 4.2.3 Measurement Results ................................ ................................ ............................ 107 4.3 Conclusions ................................ ................................ ................................ ..................... 116 5 SUMMARY AND FUTURE WORK ................................ ................................ .................. 118 5.1 Summary ................................ ................................ ................................ ......................... 118 5.2 Future Work ................................ ................................ ................................ .................... 119 APPENDIX: PRINTED CIRCUIT BOARD DESIGN FOR MULTI BAND PA EVALUATION ................................ ................................ ................................ .................... 122 LIST OF REFERENCES ................................ ................................ ................................ ............. 125 BIOGRAPH ICAL SKETCH ................................ ................................ ................................ ....... 133

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7 LIST OF TABLES Table page 1 1 Summary of wireless technologies ................................ ................................ .................... 16 1 2 Output power required for power amplifiers for selected wireless applications ............... 17 2 1 Transmit/Receive (T/R) switch bias voltages in transmit/receive mode ........................... 44 2 2 Measured NMOS/Diode hybrid T/R switch performance summary ................................ 51 2 3 Performance comparison to the previously published CMOS T/R switches ..................... 51 3 1 Maximum efficien cy of Class F power amplifier under different harmonic termination conditions ................................ ................................ ................................ ....... 65 3 2 The transistor sizes and passive component values of the Class F power amplifier ......... 71 3 3 Performance summary of the Class F PA in this design ................................ ................... 76 3 4 Performance comparison to the previously published CMOS Class F PA ....................... 76 4 1 Summary of multi band power amplifier techniques ................................ ........................ 85 4 2 Power amplifier performance comparisons ................................ ................................ ....... 87 4 3 The circuit parameters for the PA driver ................................ ................................ ........... 96 4 4 The extracted equivalent circuit parameters for the 1:1 slab i nductor based transformer, interconnection parasitic are also included in the simulation ....................... 99 4 5 Summary of the measured multi band power amplifier performance ............................. 115 4 6 Performance comparison to the previously published tunable multi band CMOS power amplifiers ................................ ................................ ................................ .............. 115 4 7 Performance comparison to the previously published power amplifiers in nano scale CMOS ................................ ................................ ................................ ............................ 116

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8 LIST OF FIGURES Figure page 1 1 Simplified direct conversion time division duplex transceiver architecture ..................... 16 1 2 Traditional parallel path multi band multi mode approach ................................ .............. 18 1 3 Next generation multi band transceiver concept based on adaptive RF function blocks ................................ ................................ ................................ ................................ 18 2 1 Simplified time division duplex transceiver architecture ................................ ................. 21 2 2 Traditional series shunt T/R switch ................................ ................................ .................. 22 2 3 T/R switch with integrated impedance transformation network ................................ ........ 25 2 4 Floating body techniques to improve the power handling capability of transistors .......... 26 2 5 Techniques to improve TX to RX isolation of T/R switch in transmit mode, A) stacked transistors, B) resonant tank ................................ ................................ ................. 27 2 6 Simplified schematic of p n diode T/R switch ................................ ................................ 29 2 7 Schematic and equivalent model of the TX transistor ................................ ...................... 30 2 8 Power handling capability and insertion loss simulation setup for the TX transistor ...... 31 2 9 Simula ted TX transistor IP 1dB for varying width and substrate impedance at 900 MHz ................................ ................................ ................................ ................................ .. 32 2 10 Simulated TX transistor insertion loss for varying width and substrate impedance at 900 MHz ................................ ................................ ................................ ........................... 32 2 11 Metal stack for the source/drain connection ................................ ................................ ..... 34 2 12 Layout the of TX transistor ................................ ................................ ............................... 35 2 13 P n junction diodes in standard CMOS technology, A) p + n well diode, and B) n + p substrate diode . ................................ ................................ ................................ ................. 35 2 14 Cross section of n well p + n diode in 45 nm CMOS ................................ ........................ 36 2 15 Small signal equivalent circuit for a p + n well diode ................................ ....................... 37 2 16 P + n well diode cell and typical interconnection scheme ................................ ................. 39 2 17 Schematic of diode based T/R switch with DC biasing ................................ .................... 40

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9 2 18 T/R switch operation in transmit mode ................................ ................................ ............. 40 2 19 Unit cell layout of p n p transistor Q 1 ................................ ................................ ............... 41 2 20 Interconnect scheme of the p n p transistor unit cells ................................ ...................... 42 2 21 T/R switch operation in receive mode ................................ ................................ .............. 43 2 22 Gate source and gate drain voltage waveforms of transistors M 1 and M 2 when T/R switch input power is 28 dBm ................................ ................................ .......................... 44 2 23 Die photo of the NMOS/D iode hybrid T/R switch in 45 nm CMOS ............................... 45 2 24 T/R switch in receive mode including the parasitic p n p associated with D 1 . ................. 46 2 25 Measured DC characteristics of the parasitic vertical p n p transistor associated with D 1 . ................................ ................................ ................................ ................................ ...... 47 2 26 Measured DC characteristics o f the p n p transistor Q 1 ................................ .................... 48 2 27 T/R switch measurement setup ................................ ................................ ......................... 48 2 28 Measured insertion loss of the T/R switch ................................ ................................ ........ 49 2 29 Measured return loss and isolation of the T/R switch ................................ ....................... 50 2 30 Measured output power versus input power plot of the T/R switch. IP 1dB is 27.8 dBm . ................................ ................................ ................................ ................................ .. 50 3 1 Definition of PA output power, power gain and efficiency ................................ .............. 54 3 2 Definition of PA efficiency with driver stages ................................ ................................ 55 3 3 General power amplifier model ................................ ................................ ........................ 56 3 4 Drain voltage and current waveforms for Class A power amplifier ................................ 57 3 5 Drain voltage and current waveforms for Class AB power amplifier ............................... 58 3 6 Drain voltage and current waveforms for Class B power amplifier ................................ .. 58 3 7 Drain voltage and current waveforms for Class C power amplifier ................................ .. 59 3 8 Drain voltage and current waveforms for overdriven Class A power amplifier .............. 59 3 9 Drain voltage and current waveforms for overdriven Class B power amplifier .............. 60 3 10 Schematic of Class D power amplifier ................................ ................................ ............. 60

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10 3 11 Drain voltage and current waveforms of Class D power amplifier ................................ ... 61 3 12 Schematic of Class E power amplifier ................................ ................................ ............. 61 3 13 Drain voltage and current waveforms for Class E power amplifier ................................ 62 3 14 Schematic of generic Class F power amplifier ................................ ................................ .. 64 3 15 Drain voltage and current wav eforms of Class F power amplifier ................................ ... 64 3 16 Class F power amplifier with third order harmonic peaking network .............................. 66 3 17 Schematic of the fully integrated Class F PA in this design ................................ ............ 67 3 18 Equivalent circuit of the Class F PA output matching network working at A) fundamental frequency, B) second order frequency and C) third order frequency ........... 69 3 19 Layout cell of the PA output transistor ................................ ................................ ............. 70 3 20 Simulated drain voltage and current waveforms of the Class F power amplifier with third order harmonic peaking ................................ ................................ ............................ 71 3 21 Simulated drain efficiency versus Q for different induc tors ................................ ............. 73 3 22 Measurement setup for the PA power measurement ................................ ........................ 74 3 23 Measured PA saturated output power, drain efficiency and power added efficiency vs. V DD_PA ................................ ................................ ................................ ......................... 75 3 24 PA saturated output power and PAE under different input bias voltage with V DD =1.2 V for the driver and output stage . ................................ ................................ ..................... 75 3 25 Die micrograph of the Class F power amplifier ................................ ............................... 76 4 1 Evolution of the LC matching network to a lattice type LC power combing network. .... 80 4 2 Wilkinson power combiner ................................ ................................ ............................... 81 4 3 Transformer based power combiner ................................ ................................ ................. 82 4 4 Multi band Class D power amplifier in [72] ................................ ................................ .... 84 4 5 Multi band SiGe power amplifier in [7] ................................ ................................ ........... 84 4 6 Resonant LC tank is used as a variable inductor in [74] ................................ ................... 85 4 7 Schematic of single stage power amplifier ................................ ................................ ....... 87 4 8 Block diagram of the watt level multiband power amplifier ................................ ............ 88

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11 4 9 Equivalent model of transformer with capacitor tuning ................................ ................... 89 4 10 Schematic of the single ended power amplifier used in this design ................................ 90 4 11 The differential power amplifier with a transformer based matching network . ............... 91 4 12 The drain voltage and current waveforms of the differential power amplifier driven in saturatio n mode . ................................ ................................ ................................ ............ 92 4 13 Simplified layout of the power amplifier output transistor cell ................................ ........ 94 4 14 Metal stack for source/drain connections of the PA transistor ................................ ......... 94 4 15 PA transistor layout ................................ ................................ ................................ ........... 95 4 16 Inverter chain based wideband PA driver ................................ ................................ ......... 95 4 17 Input power distribution scheme for the power amplifier ................................ ................ 97 4 18 Simulated |S 11 | for the input matching of the driver ................................ ......................... 97 4 19 3 D view of the stacked transformer with patterned ground shield ................................ ... 98 4 20 Compact model for the stacked transformer ................................ ................................ ...... 99 4 21 Transformer S parameter (|S 21 |) simulation in both low frequency and high frequency bands ................................ ................................ ................................ ............................... 100 4 22 Conceptual drawing of the power combiner ................................ ................................ ... 100 4 23 The tuning capacitor connection at the primary inductor, A) differential connection across the two nodes of the primary inductor, B) separa te single ended connection from the two nodes to ground . ................................ ................................ ........................ 101 4 24 Multiband power amplifier with tunable switch capacitor banks ................................ ... 103 4 25 Multiband power amplifier with tunable switch capacitor banks ................................ ... 104 4 26 Drain efficiency of the PA versus the Q of the capacitor tuning bank C 1 and C 2 at lower frequency band (850 MHz) . ................................ ................................ .................. 104 4 27 Drain efficiency of the PA versus the Q of the capacitor tuning bank C 1 and C 2 at higher frequency band (1700 MHz). ................................ ................................ ................ 105 4 28 Differential amplifier with parasitic inductances from the routing and bond wires ....... 106 4 29 Printed circuit board bypassing for power amplifier performance evaluation ............... 107 4 30 Power amplifier power measurement setup ................................ ................................ .... 108

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12 4 31 Separate V DD on printed circuit board for PA evaluation ................................ ............... 109 4 32 Photograph of the printed circuit board for chip evaluation ................................ ............ 109 4 33 Chip on board bonding scheme and the die photo of multi band power amplifier ......... 110 4 34 Measured output power, drain efficiency and power added efficiency of the multi band PA versus frequency at the lower band. ................................ ................................ .. 111 4 35 Measured output power, drain efficiency and power added efficiency versus PA stage DC supply V DD_PA at 850 MHz ................................ ................................ ............... 112 4 36 Measured output power versus input power characteristics of the PA at 850 MHz ........ 112 4 37 Measured outp ut power, drain efficiency and power added efficiency of the multi band PA versus frequency at the higher band. ................................ ................................ 113 4 38 Measured output power, drain efficiency and power added efficiency versus PA stage DC supply V DD_PA at 1700 MHz ................................ ................................ ............. 114 4 39 Measured output p ower versus input power characteristics of the PA working at 1700 MHz ................................ ................................ ................................ ........................ 114 5 1 Schematic of NMOS/Diode hybrid T/R switch using a Sc hottky diode ......................... 120 5 2 Voltage controlled tuning at the output of power combiner ................................ ............ 121 A 1 Four layer printed circuit board thicknesses. ................................ ................................ ... 122 A 2 Top layer of the multi band PA evaluation board ................................ .......................... 123 A 3 Second layer of the multi band PA eval uation board ................................ ..................... 123 A 4 Third layer of the multi band PA evaluation board ................................ ........................ 124 A 5 Bottom layer of the multi band PA evaluation board ................................ ..................... 124

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13 ABSTRACT OF DISSERTA TION PRESENTED TO TH E GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLME NT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY COMPLEMENTARY METAL OXIDE SEMICONDUCTOR RADIO FREQUENCY INTEGRATED CIRCUIT BLOCKS FOR HIGH POWER APPLICATION S By Tie Sun Augus t 2011 Chair: Kenneth K. O Major: Electrical and Computer Engineering As the devices in Complementary Metal Oxide Semiconductor (CMOS) integrated circuits are continuously scaled down, power consumption of CMOS circuits is lowered and their intrinsic speed is increased. This has made CMOS the dominant technology for modern radio frequency (RF) communication applications. However, to realize the fully integrated CMOS single chip radio has been challenging because of the intrinsic drawbacks of the CMOS process including high ohmic resistance of metallization, lossy substrate and especially low breakdo wn voltage for MOS transistors. These make it chal lenging to implement high power components in RF transceivers such as RF transmit/receive (T/R) switches and RF power amplifiers (PA) This dissertation focus es on the design of integrated T/R switch es and power amplifier s in CMOS technology. A n NMOS/Diode hybrid T/R switch with h igh power handling capability by using the high breakdown voltages of p n junction diodes in TI 45 nm CMOS technology is first demonstrated Substrate isolation is enhanced to improve the power handling capability of TX transistor. In order to decrease the insertion loss, layout of p n junction diode is optimized. In addition, a novel on chip switch DC biasing circuit is also proposed

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14 D esign and characte rization of a 2.4 GHz CMOS Class F power amplifier in UMC 130 nm CMOS technology are also demonstrated The single ended power amplifier consists of a tapered inverter driver and an output sta ge with a fully integrated third order harmonic peaking network incorporating impedance transformation The PA exhibits 12.4 dBm saturated ou tput power and 13.9 dB pea k power gain with drain efficiency of 46.5% and power added efficiency (PAE) of 38% at 1.2 V supply voltage Finally, a tunable multi band watt level power amplifier in TI 65 nm CMOS technology that can support 850 MHz and 1700 MHz operation is fabricated and characterized The multi band PA has an on combined in order to achieve the watt level output power at low supply voltage of 1.2 V. Measurements show that at 850 MHz, the saturated output power of 30.2 dBm with drain efficiency 24.3% is achieved. At 1700 MHz, the saturated output power is 29.5 dBm with drain efficiency 22.2%.

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15 CHAPTER 1 INTRODUCTION 1.1 Background and Motivation Wireless connectivity in portable applications demands highly integrated transceivers with increase d functionality at reduced cost. This has fueled the pursuit for single chip radio transceivers realized in low cost Complementary Metal Oxide Semiconductor (CMOS) technology which has enabled cost reduction for digital integrated circuits. Furthermore, as the devices in the technology are continued to be scaled down, power consumption of CMOS circuits is lowered and their in trinsic speed is increased. These h ave made CMOS the dominant integrated circuits technology for modern radio frequency (RF) communication applications. However, there are still challenges to realize a fully integrated CMOS single chip radio because of the intrinsic drawbacks of CMOS proces s [1] including high ohmic resistance of metallization, lossy substrate and especially low breakdown voltage for MOS transistors. These make it difficult to implement the high power components in RF transceivers such as RF power amplifiers and RF transmit/receive switches in CMOS. Figure 1 1 shows a block diagram of direct conversion time division duplex (TDD) transceiver [ 2 ] [3] Both transmitter and receiver are connected to an antenna through a single pole double through (SPDT) transmit/receiv e switch. Either a transmitter or a receiver is on at a time. T/R switch can be found in any TDD based RF front end circuit, as shown in the summary of wireless technologies in Table 1 1 [ 4 ] Table 1 2 shows the typical output power of power amplifier for some wireless applications [5] In many applications an RF power amplifier is required to gene rate high output power which exceed one watt t o antenna with good efficiency. At the same time, the T/R switch should handle the high output power from the PA wi th low insertion and provide sufficient isolation to protect the receiver circuits. Of course, the high

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16 output power and power h andling capability requirements are in direct conflict with the lo w breakdown voltage transistors supported by highly scale d CMO S technology Figure 1 1 Simplified direct conversion time division duplex transceiver architecture Table 1 1 Summary of wireless technologies Technology Frequency (GHz) Data Rate (Mb/s) Peak Power Level (dBm) Duplexing Features 2G 0.9/1.8/1.9 <0.1 33 FDD 3G 1.8~2.2 <2 30 FDD/TDD 4G LTE 2.0~2.6 >50 30 FDD/TDD 4G WiMAX 2.3~3.5 <75 30 FDD/TDD Bluetooth 2.4 <54 20 TDD WLAN 2.4 or 5.8 <54 20 TDD UWB 3.1~10.6 >110 15 TDD 60 GHz 57~66 >1500 10 TDD As shown in Figure 1 1, most of the RF blocks and baseband circuits of the transceiver can be implemented using CMOS technology except the T/R switch es and power amplifiers

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17 especially for cellular application s Gallium arsenide (GaAs) technology is the dominant for commercial PA and T/R switch products with high output power and power ha ndling capability requirements compared with the CMOS counterparts [5], [6] But they cannot be integrated with the rest of the transceiver. This has motivated the investigation of th e feasibility for techniques to overcome the challenge, and the results are presented in this dissertation. Table 1 2 Output power required for power amplifiers for selected wireless applications Application Standard Frequency (MHz) Typical output power ( dBm) Modulation Cellular GSM 850 824 849 33 GMSK Cellular E GSM900 880 915 33 GMSK Cellular DCS1800 1710 1785 30 GMSK Cellular PCS1900 1850 1910 30 GMSK Cellular CDMA (IS 95) 824 849 28 O QPSK Cellular PCS (IS 98) 1750 1780 28 O QPSK Cellular WCDMA 1920 1980 27 HPSK WLAN IEEE 802.11 b 2400 2484 16 20 PSK CCK WLAN IEEE 802.11 a 5150 5350 14 20 OFDM WLAN IEEE 802.11 g 2400 2484 16 20 OFDM WiMAX IEEE 802.16d/e 2300 2700 22 25 OFDM WiMAX IEEE 802.16d/e 3300 3700 22 25 OFDM WiMAX IEEE 802.16d/e 4900 5900 22 25 OFDM

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18 Figure 1 2 Traditional parallel path multi band multi mode approach Figure 1 3 Next generation multi band transceiver concept based on adaptive RF function blocks With the evolution of wireless communication systems to the 3 rd and 4 th generations, the necessity for coexistence of different cellular and other wireless systems has increased the demand for multi band, multi mode, and multi standard terminals [7] It is pre ferred to use tunable single path rather than parallel paths concept as shown in Figure 1 2 and 1 3 to reduce

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19 the size and cost of the system [7 ]. For the circuit in receiver side, many multi band circuits have been demonstrated [8], [9], [10], [11], [12] [13], [14] While in the transmitter side, realizing a multi band tunable CMOS power amplifier with watt level output power is still challenging. Because of this, wideband T/R switches and tunable power amplifiers in CMOS tec hnology are highly desired. 1.2 Dissertation Organization This work focuses on the design and implementation of two high power components in RF CMOS transceiver front end, power amplifier s and T/R switches. Chanter 2 describes the design of T/R switch with high power handling capability that exploits the high breakdown voltages of p n junction diodes in T I 45 nm CMOS technology Substrate isolation is enhanced to improve the power handling capability of TX transistor. In order to decrease the insertion loss the layout of p n diode is optimized. In addition, a novel on chip switch DC biasing circuit is also proposed. M easurement results show that TX and RX i nsertion loss of 0.5 dB and 1.1 dB, and IP 1dB of ~28 dBm have been achieved for the proposed series NM OS and series diode hybrid configuration T/R switch. Possible methods for the switch performance improvement have also been suggested. This is the first effort to evaluate the performance can be achieved of a T/R switch operating around 900 MHz using p n d iodes in nano scale CMOS The design and characterization of a fully integrated 2.4 GHz CMOS Class F power ampl ifier are presented in chapter 3 The single ended Class F power amplifier consists of a tapered inverter driver and an output stage with a fully integrated third harmonic peaking network incorporating impedance transformat ion. It exhibits 12.4 dBm saturated output power and 13.9 dB peak power gain with drain efficiency of 46.5% and power added efficiency (PAE)

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20 of 38% at 1.2 V supply voltage The 2.4 GHz operation frequency is the lowest at which full integration of Class F PA in CMOS is demonstrated. In chapter 4 a tunable multi band CMOS power amplifier with watt level output power is designed and characterized in TI 65 nm CMOS. The multi band PA has an on chip transformer he watt level output power. A t unable network is used to cove r the frequency bands of 850 MHz and 1700 MHz. A wideband tapered square wave PA driver is designed and the transform er based power combiner is optimized for lower loss. Furthermore, a novel tuning scheme for multi band operation is propo sed. Measurement s show that at 850 MHz, 30.2 dBm saturated output power with drain efficiency and power added efficiency of 24. 3% and 20.6% is achieved. At 1700 MHz, the saturated output power is 29.5 dBm with drain efficiency and power added efficiency of 22.2% and 16.7% respectively. This is the first tunable multi band watt level power amplifier usi ng nan o scale CMOS technology that supports 850 MHz and 1700 MHz frequency bands with supply voltage lower than 2 V. Lastly, chapter 5 summarizes the research work in this dissertation. Future works to improve the performance of the T/R switch and multi band power amplifier are also suggested. A Schottky diode T/R switch and a multi band power amplifier with external var actor tuning are introduced.

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21 CHAPTER 2 NMO S/DIODE HYBRID TRANSMIT/RECEIVE SWITCH 2 .1 Overview A high performance transmit/receive (T/R) switch is the first building block of the radio frequency (RF) front end of time division duplexing (TDD) communication systems. In this chapter, t he potential use of integrated p n junction diodes in a CMOS T/R switch circuit for improvement of power handling capability is discussed. A NMOS/Diode hybrid T/R switch with novel on chip biasing circuit is proposed. And the measurement results are also shown. 2 .1.1 Complementary Metal Oxide Semiconductor (CMOS) Transm it/Receive (TR) Switche s A simplified block diagram of TDD RF transceiver architecture is shown in Figure 2 1 [15 ] Both transmitter and receiver are connected to an antenna through a single pole double through (SPDT) T/R switch. Either a transmitter or a receiver is on at a time. Figure 2 1. Simplified time division duplex transceiver architecture In receive mode, the T/R switch connects the antenna to the receiver, which usually starts with a low noise amplifier (LNA). The signal picked up by the antenna will go through the T/R n terminal Schottky terminal CoSi 2 Si Schottky Contact ILD ILD ILD ILD STI STI Polysilico n seperator l 1 l 1 l s l 2 l 2 n terminal Schottky terminal CoSi2 Si Schottky Contact R c R c R c C p C p ILD ILD ILD ILD STI STI STI STI R 3 R 3 R 2 R 2 R 1 C jo n + n + p + p + l guard l guard 1E 06 1E 07 1E 08 1E 09 1E 10 1E 11 1E 12 0 0.1 0.2 0.3 V bias (V) I (A) Slope~60m V/decade V bias (V) 1.5 1 0.5 0 0.5 1 1.5 2 2.5 3 1E 15 1E 12 1E 09 1E 06 1E 03 1E+00 1E+03 No guard STI SBD STI SBD with l guard =0.12 m STI SBD with l guard =0.16 m STI SBD with l guard =0.20 m p n diode V bias (V) 1 0 1 2 3 1E 14 1E 12 1E 10 1E 08 1E 06 1E 04 1E 02 1E+00 PGS SBD PGS SBD with l guard = 0.18m STI SBD STI SBD with l guard = 0.12 m f c d 0.5 0.5 1.5 2.5 3.5 250 255 260 265 270 Time (ps) Voltage across diode (V) N=38 N=46 N=30 1.5 1.0 0 .5 0.0 2005 2010 2015 2020 Year Frequenc y (THz) 40 3 0 2 0 1 0 0 0 V bias (V) 0.5 Schottky diode p n junction diode 1.0 1.5 I (mA) C p R s C j (V) g j (V) C nw R nw C p : Sid ewall parasitic capacitanc e R s : Seri es resistance C j (V ) : Jun ction capacitanc e g j (V ) : Jun ction conductanc e C nw : n well to p substrate diode capacitanc e R nw : n well to p substrate diode parasitic series resistance p substrate Schottky terminal Cathode n terminal C jo (fF)

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22 switch and delivered to the LNA. The loss of T/R switch increases the noise f igure of receiver by the same amount. Therefore, the T/R switch loss should be low to reduce its impact on the receiver sen sitivity. In transmit mode, the power amplifier of transmitter will be connected to the antenna through the T/R switch. The T/R switch should be able to handle high output power signal without causing excessive loss and distortion. Besides, in order to pro tect the LNA input device from the large voltage swing at the transmitter output, good isolation between the transmitter and receiver is required to limit the power leakage from PA to LNA [ 15 ] Figure 2 2 Traditional series shunt T/R switch Figure 2 2 shows a schematic of a traditional series shunt SPDT T/R switch [16 ] [17], [18] Series transistors M 1 and M 2 perform the mai n switching function, while shunt transistors M 3 and M 4 are used to improve the isolation of s witch. In TX mode, transistors M 1 and M 4 are turned on and transistors M 2 and M 3 are turned off. While in RX mode, transistors M 2 and M 3 are turned on and transistors M 1 and M 4 are turned off. The bypass capacitors C b1 and C b2 allow dc biasing of the TX an d RX nodes of the switch. By applying the same dc voltage on the top plates

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23 of bypass capacitors and at TX and RX nodes, dc power consumption is made negligible. Gate bias resistances R G1 R G2 R G3 and R G4 are imple mented using poly resistors. A typ ical va lue for the gate bias re sis tance is about 10 The purp ose of gate bias resistors i s to improve dc bias isolation and to reduce the fluctuation of transistor bias due to the RF voltage swing at the drain and source of transistors These fluctuations not only affect the MOSFET channel resistance but also may result in excessive voltage across the gate dielectric that can damage the transistor Key Figures of merit for a T/R switch are insertion loss (IL), isolation, return loss, power handling capability o r linearity, and switching time [16 ] [17 ] For convenience, ports are labeled P 1 (antenna port), P 2 (receiver port) and P 3 (transmitter port) in Figure 2 1. All three ports have the same characteristic impedance Z 0 Insertion loss ( IL ) represents the powe r loss from the switch when the switch is on. Insertion losses in receive and transmit modes in dB are (2 1) (2 2) Isolation ( IS ) characterizes how much signal power is attenuated from the switch when the switch is off. The expression for switch isolation is the same as that of insertion loss. Return loss ( RL ) measures how much power is reflected back from the spec ified switch port This parameter describes the mismatch at a port and can be expressed by Equation (2 3), in which x (1 3) is one of the three ports. (2 3) Power handling capability or linearity of a swi tch is usually represented by 1 dB compression point (P 1dB ). IP 1dB is defined as the input signal power that causes the small signal gain to drop by 1 dB and the corresponding output power is O P 1dB Switching (turn on/turn off) time is

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2 4 defined as the time from 50% control signal to when the 90%/10% signal power is delivered at the output A key limiting factor for implement ing high performance T/R switches in CMOS is the relatively high channel resis tance [ 16 ], [ 17 ], which is directly related to switch insertio n loss. Compared to GaAs transistors CMOS transistors have higher channel sheet resistance ( ch ) due to the low electron and hole mobility. The channel resistance R ch = ch L/W where W and L a re the channel width and length respecti vely, can be reduced by increasing the W/L ratio. However, W cannot be increased arbitrarily, since the parasitic capacitance to substrate w ill increase due to the increased source/drain area. This will lead to ext ra power loss to substrate [16], [17 ] [ 18 ] As a consequence, the insertion loss will be increased when the switch is on, and the isolation is also degraded when the switch transistor is off. Therefore, a minimum gate length which is determined by technology choice is usually use d to limit the transistor size. With silicon technology scaling, this situation improves. Since as the channel length scales down, the CMOS switch insertio n loss decreases resulting from lower channel resistance at given par asitic capacitance. The source/drain to substrate capacitance can be further decreased by source/drain DC biasing [ 16 ] [17] 2 .1.2 Design Challenges of CMOS T/R Switch with High Power Handling Capability Power handling capability as mentioned is another c ritical f igure of merit for T/R switches. Achieving IP 1dB higher than 30 dBm, which is needed in several communication systems, is quite challenging. Although technology scaling will improve the CMOS switch insertion loss as mentioned in the last section, it will also inevitably reduce the transistor breakdown voltage. This makes it even more challenging to achieve the necessary power handling capability One of the mechanisms which limit the CMOS T/R switch power handling capability is the forward biasing of source/drain to body diodes during large voltage swing s at the input and

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25 output of T/R switch. The forward biased junctions will distort output signal, thus limit the power handling capability. Even though source/drain to body DC biasing technique incre ases IP 1dB this is still not sufficient. Figure 2 3 T/R switch with integrated impedance transformation network The techniques to improve the transistor power handling capability include DC biasing source/drain to body nodes [ 16 ], [ 17 ], impedance transformation [19 ], and floating body [20], [21], [22], [23], [24], [25 ] [26 ], [27], [28], [29], [30], [31] and feed forward [26]. A schematic of T/R switch using an impedance transformation network is shown in Figure 2 3 [19] Im pedance transformation requires use of high Q inductor s, which is difficult to integrate at relatively low frequencies (~900 MHz). It is also only suitable for narrow band applications. The possibility of using floating body technique to improve power handling capability in CMOS was first introduced in [ 20 ] by using a minimum number of substrate contacts for transistors. Then depletion layer extende d transistors (DETs) [ 23 ], [ 24 ] were used to i ncrease the body resistance

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26 at the cost of extra fabrication masks. By making high impedance connection to the body using an LC tuned circuit [25 ] the body connection of NMOS transistor is made to float at resonant frequency In [ 26 ], [27], [29], NMOS transistors in isolated p wells of a triple well CMOS process w ere used to enhance the switch power handling capability while eliminating the need for the LC tank which consumes a significant area and makes the switch narrowband Figure 2 4 illustrates the typical floating body techniques to improve the power handling capability of transistor s Figure 2 4 Floa ting body techniques to improve the power handling capability of transistor s Another difficulty for T/R switch with high power handling capability is the TX to RX isolation in transmit mode. Series transistors can be used [26] to block the large voltage swing in antenna port as shown in Figure 2 5 ( A ). T his however requires high br eakdown voltage for

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27 transistor s which are typically not available in s caled down CMOS technology Floating body techniques should also be applied here to make the voltage swing of the antenna port more evenly distributed among the terminals of transistors M 1 to M 3 Another method is to used an LC resonate circuit [30 ] [31] as illustrated in Figure 2 5 ( B ) When V c is high, transistor M RS is turned on and L RS and C RS form the pa rallel resonant tank which presents high impedance. When V c is low, transistor M RS is turned off, therefore L RS and C C form series resonate circuit. This circuit can be co designed with low noise amplifier and limited for narrow band application s A B Figure 2 5 Techniques to improve TX to RX isolation of T/R switch in transmit mode, A) stacked transistors, B) resonant tank

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28 Although the maximum reported IP 1dB for CMOS T/R switch has reached to ~3 4 dBm (differential switch) [ 31 ] the voltage limitation for reliable operation is still the bo ttleneck for transistor. That is the reason why mo st of the T/R switches reported use t hick gate oxide I/O transistors Unfortunately, the power handling capability of I/O transistors degrades with technology scaling. The reliability issue will become more severe as technology is scaled. For example, the breakdown voltage for thin oxide transistor s is only 1.7 V in 45 nm bulk CMOS technology This makes the implementation of T/R switches with high power handling capability even more challenging. Compared to transistors, p n junction diodes in CMOS have much higher breakdown voltage, which is about 5 times of transistor breakdown voltage in 45 nm CMOS, and more robust (recoverable). U sing p n junction diodes in CMOS to implement the T/ R switches has the potential of providing a superior trade off between insertion loss and high power handling capability. 2 .2 NMOS/Diode Hybrid T/R Switch in CMOS 2 .2.1 Design Target and Circuit Topology Choice of switch topology is determined by the avail able devices and require d power handling capability. A simplified schematic of the proposed NMOS/Diode hybrid CMOS T/R switch is shown in Figure 2 6. As mentioned in the last section, the breakdown voltage of thin gate oxide transistors in 45 nm bulk CMOS is only ~1.7 V, which limits ANT to RX isolation and power handling capability in transmit mode even when a series transistors are used [26]. In this design, a series p n diode D 1 between RX port and ANT port is used to improve the power handling capabilit y because of the higher reverse breakdown voltage of p n diode s The purpose of shunt transistor M 2 in RX side is to further improve the ANT to RX isolation in transmit mode. The p ower handling capability of series transistor M 1 in TX to ANT path can be enhanced

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29 by using the floating body technique [20], [22], [26], [30] DC biasing circuits should also be carefully designed to properly bias the transistor and diode properly. Figure 2 6. Simplified s chematic of p n diode T/R switch 2 .2. 2 Circuit Design 2 .2.2.1 Design of transmit transistor with improved power handling capability To improve p ower handling capability and reduce insertion loss for the TX transistor the voltage drop across the gate oxide must be kept in the safe range and the source/drain to body parasitic diodes should be prevented from forward bias ing. An equivalent model [16 ] of the TX NMOS transistor when it is turned on is shown in Figure 2 7 Assuming the DC bias volt age of S/D is 0 V, when la rge input signal is applied to source in the positive half cycle, the vo ltage drop on the gate oxide depend s on the impedance ratio between C GS C GD and R G B y connecting a high impedance (~ k ) resistor at the gate, the gate node will be bootstrapped, which means that the gate voltage will follow the voltage of source and drain therefore high RF signal can be applied before breakdown A s imilar situation occur s in the negative half cycle I f the body

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30 resistance R sub is sufficiently high the s ource/drain to body diodes are also bo otstrapped, which prevents the diodes from forward biasing therefore, the power handling capability is enhanced. To reduce the drain body and source body capacitances, source and nodes are also biased up and in turn the reversely biased source body and dr ain body parasitic diodes will exhibit lower capacitance. Figure 2 7 Schematic and equivalent model of the TX transistor The power handling capability and insert ion loss simulation setup for TX transistor is shown in Figure 2 8. Figure 2 9 and Figure 2 10 show the simulated IP 1dB and insertion loss of the single switch transistor in 45 nm CMOS technology for varying width and substrate

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31 impedance at 900 MHz. The ga te length is fixed at minimum length of 40 nm to reduce the total parasitic capacitance for the same transistor W/L ratio. The source/drain and gate DC bias Figure 2 8. Power handling capability and insertion loss simulation setup for the TX transistor As shown in the plot, for the same transistor size, increasing substrate resistance give s better power handling capability. And for the same substrate resistance, a larger transistor show s better power handling capability becaus e it can carry more AC current and the increased source/drain capacitance reduces the voltage drop across the transistor. Bo th series on resistance and parasitic s ource/drain to body capacitance contribute to the insertion loss of the tran sistor. As shown in Figure 2 10 when the substrate resistance is relatively small (for example, R sub =0.5 k increasing transistor size rai ses insertion loss since the loss from the shunt path is dominant. On the other hand, if the substrate resistance is large (for example, R sub transistor size reduces insertion loss due to the fact that the high substrate resistance redu ces the shunt leakage and the on resistance dominate s the insertion loss.

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32 Figure 2 9 Simulated TX transistor IP 1dB for varying width and substrate impedance at 900 MHz Figure 2 10 Simulated TX transistor insertion loss for varying width and substrate impedance at 900 MHz

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33 From these simulation results, we can see that i n TX transistor design, there is tradeoff between power handling capability and insertion loss especially at modera tely high substrate resistances. The transistor size should be sufficiently increased to guarantee the switch can handle the current when large input power is applied, and to decrease the ON resistance thus lowering the insertion loss. On the other hand, a bigger transistor has more drain/source to body parasitic capacitance, which degrades the insertion loss. A factor not considered in the simulations is that increasing transistor active area also reduces the substrate impedance, degrading the power handli ng capability. The appropriate choice of transistor size is dependent on the T/R switch topology. As will be shown in a later section, over design of the T X transistor handling capability is limited by the breakdown voltage of diode. Therefore the TX transistor should be optimally sized for insertion loss, isolation and area. Another issue in the switch transistor design is the current handling capability [30 ] which should be considere d in the layout design. When a switch is working in TX mode especially approaching IP 1dB t here would be large AC current flowing through the TX transistor. For instance, at 28 dBm power and 50 the peak AC current through the transistor i s roughly 160 mA. This current will be distributed among the transistor unit cells. S everal metal layers are stacked for the source/drain connection s of the transistor as shown in Figure 2 11 to make sure the TX transistor can reliably carr y the peak current. A drawback of this met al stack is the increase of transistor source/drain capacitance C DS due to an increased fr inge capacitance. T his degrades the ANT port to TX port isolation of the switch in receive mode will be degraded. One way to reduce the fringe capacitance is to increase the distance between the source and drain fingers for each unit cell. However, this will increase the transistor acti ve are a /junction

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34 capacitance and reduce the substrate impedance which in turn limit the p owe r handling capability of switch transistor Figure 2 11. Metal stack for the source/drain connection Figure 2 12 shows the layout scheme of TX transistor. The m inimum cha nnel length of 40 nm is used and the finger width of the unit transistor is 0.6 m. The total transistor width is 600 m. The source and drain metals are stacked from metal 1 to metal 6 to make sure it can carry the AC current without any reliability issue. The t op metal (metal 7) is used for global routing of the transistor for its high current handling capability and low ohmic resistance. A s quare geometry of the transistor layout is selected to minimize t he total active area, which increase s the substrate r esistance. The dimension of transistor layout is about 38 m x 40 m. Body contacts are placed about 600 from the switch transistors. A dditionally, an implant block mask is used to block the p well implant in the regions between the switch transist or and body contacts [26], [28], [30 ] [31 ] to further increase the substrate resistance.

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35 Figure 2 12 Layout the of TX transistor A B Figure 2 13. P n junction diodes in standard CMOS technology, A) p + n well diode, and B) n + p substrate diode.

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36 2 .2.2.2 Integrated p n diode d esign There are two kinds of p n junction diodes in standard CMOS: n + p diode and p + n diode. An n + p diode is composed of a hea vily doped n type region and p type s ubstrate. This is not suitable for this T/R switch design, because in CMOS, substrate is typically grounded and bias can only be applied to the n + terminal, which means an n + p diode cannot be connected in series as shown in Figure 2 13 (B). A p + n diode c an be implemented using a heavily do ped p type region in an n well. B oth terminals could be separately biased. T herefore, p + n diode s in n well are designed and characterized. Figure 2 1 4 Cross section of n well p + n diode in 45 nm CMOS A cross section view and layout of p + n diode [32] in 45 nm CMOS is shown in Figure 2 14. The anode is formed by connecting the p + implant region with metal, while the cathode connection is realized by an ohmic contact between the heavily do ped n + region and silicide.

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37 Figure 2 1 5 shows a small signal equivalent model for the p + n diode [ 33 ] when it is forward biased The diode with the p substrate forms a parasitic vertical p n p transistor. The current gain ( ) is ~1. C j is the junction capa citance and r is the dynamic diode resistance between the cathode and anode. The parasitic components are series resi stance R s side wall capacitance C p n well to p substrate or base to collector junction capacitance, C nw and substrate resistance R sub These parasitic s degrade s the insertion loss of T/R switch Figure 2 1 5 Small signal equivalent circuit for a p + n well diode Series resistance R s includes all the resistances between the depletion region and the ohmic contact metallization. R s in Figure 2 1 5 is [32] (2 4) (2 5)

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38 where R sh nwell is the n well sheet resistance, R sh STI is the n w ell sheet resistance under the shallow trench isolation (STI), R sa n+ is the salicided n + sheet resistance, R c is the resistance associated with contacts and vias. l s is the length of a square shaped p + anode, l 1 is the STI width and l 2 is the separation between the edge of STI and n well metal contact. In order to decrease the diode and T/R switch insertion loss, the series resistance must be lower. The series resistance can be reduced by lowering the separation ( l 1 + l 2 ) between p + and n + diffusion contacts. The resistance could be further reduced by adding more contacts or shunting more uni t cells together. But these make the size of n well bigger, which increases power loss through the n well to substrate parasitic diode, especially at high frequencies. The diode on resistance in for ward bias region is (2 6) where V T is the thermal voltage of ~26mV at room temperature, I BQ is the DC anode to cathode current, and R s is the parasitic r esistance defined in Equation 2 5 The second term V T /I BQ can be reduced by incre asing the DC current, which also increase s the power consumption. To decrease R s multiple unit diode cells as illustrated in Figure 2 1 4 can be shunted together. Since the n well resistance under the shallow trench isolation R sh STI is much higher than the salicided n + sheet resistance R sa n+ the contribution associated with R sh STI is decreased by using the minimum length of l 1 allowed b y design rule. Figure 2 1 6 also shows a typical interconnection scheme of the diode cells. A n n + connection is shared between the two diodes to further decrease the n well area. The distance between anode and cathode metal connections should be carefully chosen, since too small of separation will increase the sidewall parasitic capacitance C p that de grades switch isolation. Of course, too large of separation unnecessarily increases the series resistance and n well area. The lengths for l s l 1 and l 2 in this design are 0.2, 0.16 and 0.8

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39 shown in Figure 2 1 6 there are 13 p + n well contacts. 54 such cells are connected in parallel to make a square shape to reduce the n well area. T he total n well area is 22.823.2 2 At zero bias, the measured equivalent series resistance and capacitance between anode and cathode are 77 fF respectively. C nw is ~230 fF. Figure 2 16. P + n well diode cell and typical interconnection scheme 2 .2.2 3 Switch b iasing c ircuit d esign The s chematic of test NMOS/D iode hybrid T/R switch is shown in Figure 2 1 7 A series p n diode D 1 is used in the RX branch to improve power handling capability T he p ower handling capability of transistor in TX to ANT path is enhanced by us ing a floating body technique mentioned in section 2.2.2.2. For this prototype, off chip high Q chip indu ctors L 1 and L 2 with inductance of 36 nH are used to reduce the RF loss from the shunt paths

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40 Figure 2 1 7 Schematic of diode based T/R switch with DC biasing Figure 2 18. T/R switch operation in transmit mode

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41 T he T/R switch working in transmit mode is shown in Fig ure 2 1 8 The p n diode D 1 is reverse biased at the half way point of its breakdown voltage of 9.5 V to ma ximize the power handlin g capability When V bias1 is 0 V, V bias 2 should be 4.7 V At th is bias radio frequency voltage at the ANT node can go up to 4.7 V without forward biasing the diode and down to 4.7 V without breaking down the junction of dio de Because of these, the T/R switch power handling capability is set by the diode breakdown voltage. Figure 2 19. Unit cell layout of p n p transistor Q 1 S ince the DC bias voltage of V bias2 is high in TX mode, NMOS transistors cannot be easily used in the RX biasing circuit. Instead a vertical p n p transistor Q 1 with current gain of ~ 10 is used to sustain the high DC bias voltage. The n well doping of vertical p n p has been optimized to achieve the higher current gain than that for the parasitic p n p of p + n well diode. T he breakdown voltage o f base (n well) to collector (substrate) is higher than that of p + n well diode

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42 and it can handle the node voltag e. Figure 2 1 9 sh ows the unit cell layout of vertical p n p transistor Q 1 The width (l 2 ) and length (l 3 ) of emitter is 2.5 m and 8 m respectively. T he distance between p + and n + (l 1 ) is 1 m. Totally 16 such unit cells are c onnected in parallel. Figure 2 20 shows the inter connect scheme for the p n p transistor (Q 1 ) cells. In the switch layout Q 1 can be put close to the substrate contact region since it does not need high substrate resistance as the TX transistor M 1 Figure 2 20 Interconnect scheme of the p n p transistor unit cells To improve isolation between TX and RX, M 2 is added in shunt at the RX node. It is b iased in the triode region in transmit mode to prov ide a low impedance path to ground To keep the DC power consumption in TX mode zero and also gate to source voltage less than 1.1 V, the source node is AC coupled to ground using a metal bypass capacitor C B 1

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43 T he T/R switch working in receive mode is shown in Fig ure 2 21 The TX transistor M 1 is off, and diode D 1 and vertical p n p transistor, Q 1 are forward biased Th ere is DC current flowing through the biasing path which consists of L 1 L 2 D 1 and Q 1 This establishes a low impedance path between ANT and RX ports. A m etal b y pass capacitor ( C B3 ) is also integrated to bypass the noise from Q 1 If narrow band response is acceptable L 1 and L 2 can be replaced by an on chip tu ned L C circuit s to make the diode T/R switch fully integrated. Figure 2 21 T/R switch operation in receive mode Tabl e 2 1 lists the bias voltages for the switch in transmit and receive m odes. Despite the voltages are signifi cantly higher than normal in 45 nm CMOS circuits, the voltages across gate oxide are within the safe operating region. For instance, when M 2 is off in RX mode, V G2 and gate to body voltage are 4 V. However, because of the depletion region under the gate oxide, the voltage across the gate oxide should be less than 1.2 V.

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44 Table 2 1 Transmit/Receive (T/R) switch bias voltages in transmit/receive mode Bias Nodes Bias Voltage (V) T ransmit Mode Bias Voltage (V) R eceive Mode V bias1 0 5.4 V bias2 4.7 4.5 V bias3 4.7 4.5 V bias4 0 5.4 V G1 1 5.4 V G2 6 4 V B 4.7 3.7 The simulated input 1 dB compression points of the T/R switch working at transmit mode at 900 MHz is ~28 dBm. Figure 2 22 shows the gate source and gate drain voltage waveforms of transistors M 1 and M 3 when the T/R switch is running at 1 dB input compression point in transmit mode at 900 MHz. The waveforms are extracted from harmonic balance simulations. Even though the time axis is started from 0, they are already in a steady state. As we can see all the peak voltages are smaller than 1.2 V. This means that the reliability issue for the transistors can be neglected Figure 2 22 Gate source and gate drain voltage waveforms of transistor s M 1 and M 2 when T/R switch input power is 28 dBm

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45 The NMOS/Diode hybrid T/R switch is fabricated in a 45 nm CMOS technology which supports only low leakage transistors and seven metal layers. The top copper layer thickness is ~1.5 T he test chip was mounted on a printed circuit bo ard with DC biasing. Two external chip inductors L 1 and L 2 are also soldered on the board. The photo of evaluation board and the test chip is shown in Fi gure 2 23 The total area includ ing the bond pads of the switch is ~0.82 0.76 mm 2 Fi gure 2 23 Die photo of the NMOS/D iode hybrid T/R switch in 45 nm CMOS

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46 2 .2.3 Measurement R esults As mentioned, the p n diode D 1 in Figure 2 17 forms a parasitic p n p transistor with the substrate acting as a collector when it is forward biased Figure 2 24 shows the T/R switch working in receive mode including the parasitic p n p transistor of D 1 The parasitic p n p transistor associated with D 1 and the p n p transistor Q 1 used in the biasing circuit are measured and characterized to check their impact on the switch performance. Figure 2 24. T/R switch in receive mode including the pa rasitic p n p associated with D 1 To measure the DC characteristic of parasitic vertical p n p transistor associated with D 1 the device was connected to a semiconductor DC parameter analyzer. It should be noted that the substrate resistance R sub2 between th e collector of the parasitic p n p and body contact is also included in the DC measurement. The measured DC charac teristic s are shown in Figure 2 2 5

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47 The current gain is approximately 1. When base current I B is 1 mA and V CE is bigger than 3 V, the parasiti c p n p is in the forward bias region While when I B is larger than 2 mA and V CE is smaller than 5 V, the transistor is in saturation region. In order to reduce the signal loss through this pa rasitic shunt path, V bias2 is set to 4 .5 V and V bias4 is set to 5 4 V in receive mode such that the n well to substrate capacitance is reduced. Figure 2 2 6 shows the DC characteristics of p n p transistor Q 1 which has peak current gain of approximately 8. Since Q 1 is put close to the substrate contact, the associated subst rate resistance is small. Three GS/SG probes with 150 the RF measurements. One of the three ports was terminated with a 50 load through a bias tee during two p ort S pa rameter measurements using an HP8510C network analyze r. The measurement setup is illustrated in Figure 2 26. Figure 2 2 5 Measured DC characteristic s of the parasitic vertical p n p transistor associated with D 1

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48 Figure 2 2 6 Measured DC characteristic s of the p n p transistor Q 1 Figure 2 27 T/R switch measurement setup

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49 Fig ure 2 2 8 shows the measured insertion loss. At 900 MHz, insertion loss for RX and TX are 0. 5 dB and 1. 1 dB respectively. The plot al so shows the noise figure of switch in RX mode. The noise figure is almost the same as the insertion loss indicating the noise of forward biased diode and Q 1 can be managed In RX mode, the DC bias curre nt is 5 mA. Around 2 .5 mA flows between the anode and cathode. Figure 2 28. Measured insertion loss of the T/R switch Isol ation and return loss of the T/R switch are shown in Figure 2 29. In TX mode, t he return loss is less than 1 5 dB and the isolation between TX and RX ports is better than 25 dB from 90 0 MHz to 1. 2 GHz. I n RX mode, the return loss is less than 21 dB and isolation between ANT and TX ports is better than 17 dB from 900 MHz to 1. 2 GHz. Power compression measurements were carried out using a signal generator together with an external power amplifier and a power meter. The power losses from the measurement set up and cable were de embedded. Figure 2 30 shows the output power versus input p ow er plot at 900 MHz IP 1dB is 27. 8 dBm and IIP 3 is 42.5 dBm. To examine the reliability of switch, the T/R switch was stressed at 30 dBm input power when the ANT pad was left open. The measured S

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50 parameters showed no difference before and after the stress. The performance of the proposed NMOS/Diode hybrid T/R switch is summarized in Table 2 2. And the performance comparison of this design with the previously published CMOS T/R switches is listed in Table 2 3. Figure 2 2 9 Measured return loss and isolation of the T/R switch Figure 2 30 Measured output power versus input power plot of the T/R switch IP 1dB is 27.8 dBm.

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51 Table 2 2 Measured NMOS/Diode hybrid T/R switch performance summary Specifications M easured R esults Frequency 90 0 MHz Insertion Loss (Transmit Mode) 0.5 dB Insertion Loss (Receive Mode) 1.1 dB Isolation (Transmit Mode) 2 7 .5 dB Isolation (Receive Mode) 1 5 dB IP 1dB for Transmit Mode 27.8 dBm IIP 3 for Transmit Mode 42.5 dBm Power Consumption 27 mW Chip Area 0.6 mm 2 Table 2 3 Performance comparison to the previously published CMOS T/R switches Frequency (GHz) TX IL (dB) RX IL (dB) TX Isolation (dB) RX Isolation (dB) Linearity (dBm) CMOS Technology Chip Area (mm 2 ) Ref. 2.5 1.1 32 34 I P 1dB 32 nm [31] 2.4 0.4 0.2 30 16 30 IP 1dB 90 nm 0.02 [30] 5 0.9 0.9 27 17 31 IP 1dB 90 nm 0.2 [28] 2.4 1.5 1.6 32 17 28.5 IP 1dB 0.18 m 0.56 [25] 0.9 0.5 1.0 37 29 31.3 IP 1dB 0.13 m Triple well 0.11 [26] 1.8 0.75 1.1 20 35 33 IP 0.1dB 0.1 8 m Triple well 0.4 [29] 1.9 1.5 1.9 18 32 33.5 IP 0.3 dB 0.18 m Triple well 0.4 [27] 2.4 0.7 0.7 35 35 21.3 IP 1dB 0.18 m 0.03 [22] 0.9 0.5 1.1 27.5 15 27.8 IP 1dB 45 nm 0.6 This work

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52 2 .3 Conclusions Compared to MOS transistors in nano scale CMOS, p n diodes have the advan tage of high breakdown voltage. Use of a p + n well diode in a T/R switch operating around 900 MHz has been evaluated. TX and RX i nsertion loss of 0.5 dB and 1.1 dB, and IP 1dB of ~28 dBm have been achieved in a 45 nm bulk CMOS process using a series NMOS and series diode hybrid configuration. Only thin gate oxide transistors along with p n diode are used. Presently, IP 1dB is limited by the breakdown voltage of the diode and this needs to be increased. Impedance transformation using on chip networks can also be used to increase IP 1dB for narrow band applications. To fulfill the promise for broadband operation of switch, the n well to p substrate junction capacitance should be further re duced. Generating the necessary bias voltage complicates the use of switch, although many systems have higher voltages available for display and other subsystem s. Lastly, the switch requires DC power consumption in RX mode, and approaches to lower this inc luding further reduction of current gain of parasitic p n p transistors are needed. This is the first effort to evaluate the performance can be achieved of a T/R switch operating around 900 MHz using p n diodes in nano scale CMOS

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53 CHAPTER 3 2.4 GHZ CMOS CLASS F POWER AMPLIFIER 3 .1 Overview 3 .1. 1 Radio Frequency (RF) Power Amplifier (PA) Specification Parameters RF power amplifier requirement depends on standards and applications. The key specifications of power amplifiers include output power, power gain, efficiency, and linearity [ 5 ], [ 34 ] [35 ] [36] They will be introduced in this section. 3 .1.1 .1 Output p ower and power gain Figure 3 1 shows a basic power amplifier connected to the load impedance R L The output power i s defined as the active power delivered by the power amplifier and flowing into the load impedance, which is commonly 50 (3 1) I n most cases, only the power at fundamental frequency is wanted, and all the other harmonic power will be filtered or suppressed. Assuming the amplitude of fundamental output voltage is V O the output power at fundament frequency is (3 2) Finite input power (P in ) is required to drive th e power amplifier. From Figure 3 1, the power gain is defined as (3 3) 3 .1.1.2 Efficiency Efficiency of power amplifiers defines how efficient the circuit uses the DC power to deliver output power to the load. The DC power consumption P DC,PA in Figure 3 1 will be always larger than output power P out Drain efficien cy drain of PA is defined as

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54 (3 4) To take input power into consideration, the power added efficiency (PAE) is introduced as (3 5) By using equation (3 3), PAE can be rewritten as (3 6) T he above equation shows that when the power gain of PA is large enough, drain efficie ncy is approximately the same as power added efficiency. Figure 3 1. Definition of PA output power, power gain and efficiency In most power amplifier designs, driver stages are needed between the input source and the PA output stage. Figure 3 2 shows a power amplifier with two driver stages. Those driver stages will also consume DC power. Considering the power consumption of driver stages, the overall efficiency of the power amplifier can be defined as

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55 (3 7) The more driver stages are used, the higher power gain of the entire power amplifier, but the lower of the overall efficiency The power added efficiency in this situation will be defined as (3 8) During the practical power amplifier design, the number of driver stages is decided by power gain, linearity and efficiency requirements of the PA. Figure 3 2 Definition of PA efficiency with driver stages 3 .1.1.3 Linearity Linearity of a power amplifier can be defined in phase linearity and amplitude linearity. When bandwidth of the modulated signal is small compared with the carri er frequency, phase linearity is easy to achieve. Phase nonlinearity or phase distortion is denoted as PM PM distortion. Amplitude nonlinearity or amplitude distortion is denoted as AM AM distortion. So in

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56 constant envelop systems, PA needs to have good phase linearity while amplitude linearity is not a big issue, whereas in other communication systems such as W CDMA, which has varying envelope signals, good amplitude linearity is also required. Power amplifier linearity can also be characterized by third orde r intercept point (IP 3 ) which is based on two tone signal test and gives the output power for which the third order inter modulation term becomes as large as fundamental output power. But in modern communication systems, for power amplifier, IP 3 is not usu ally specified. Instead a spectral mask, error vector magnitude and adjacent channel power are used. 3 .1.2 Power Amplifier Classification 3 .1.2.1 Class A, AB, B and C power a mplifier The general power amplifier model which could be used to study class A, A B, B and C power amplifiers in shown in Figure 3 3 A high Q LC tank is resonated at fundamental frequency and short all the other high order harmonics. The above four types of power amplifiers are distinguished by bias conditions. Figure 3 3. General power amplifier model

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57 In a Class A power amplifier, the transistor operates linearly across the full input and output range, and there is always current flowing through the output transistor The device will remains at all times in the transcondu c tance region, which means that the voltage never falls below the knee voltage. The drain voltage and current waveforms for Class A power amplifier is shown in Figure 3 3. The output swing V O is maximized as V DD if the quiescent current through the transistor is equal to V DD /R L The efficiency for Class A power amplifier is obtained as (3 9) And the maximum output powe r of Class A power amplifier related to the maximum drain source voltage V DS,max can be expressed as (3 10 ) According to equation ( 3 9 ) 50% maximum drain efficiency can be ac hieved for Class A power amplifier. If knee voltage V K of the transistor is also considered, the maximum drain efficiency of Class A power amplifier can be expressed as [36] (3 1 1 ) Figure 3 4 Drain voltage and current waveforms for Class A power amplifier

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58 In a Class AB power amplifier, the transistor conducts more than half of the cycle, i n a Class B power amplifier, the transistor conducts half of the cycle and in a Class C power amplifier, the transistor is on for less than half of the cycle. They can also be classified using which represents the total number of radians during the cycle when the device is conducting. The dra in efficiency is as follow [34 ] (3 1 2 ) Figure 3 5 to Figure 3 7 show the drain voltage and c urrent waveforms for Class AB, B and C power amplifiers. Figure 3 5. Drain voltage and current waveforms for Class AB power amplifier Figure 3 6. Drain voltage and current waveforms for Class B power amplifier

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59 Figure 3 7. Drain voltage and current waveforms for Class C power amplifier 3 .1.2. 2 Saturated t ransconductance a mplifier For a reduced co nduction angle power amplifier such as Class AB, B and C mentioned in section 3.1.2.1 the transistor will be turned off for a certain amount of time, which depends on the gate bias voltage and input RF amplitude. This reduces the current voltage overlap, resulting in a higher efficiency. On the other side, the output power of the amplifier will be reduced. Figure 3 8. Drain voltage and current wave forms for overdriven Class A power amplifier If the gate bias of the power amplifier is not changing, but the amplitude of the input voltage is increased, the output of the power amplifier will be no longer sinusoid and clipping behavior will be show up. This over driven effect will also reduce the overlap between drain

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60 voltage and current. Therefore the efficiency will be increased, along with degraded input to output linearity. Figure 3 8 and 3 9 show the drain voltage and current waveforms of overdriven or saturated Class A and Class B power amplifiers. Figure 3 9. Drain voltage and current waveforms for overdriven Class B power amplifier 3 .1.2.3 Class D power a mplifier Figure 3 10. Schematic of Class D power amplifier

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61 A schematic of Class D powe r amplifier is shown in Figure 3 10 The input signal is square wave, and the transistors are working in a switch mode. Ideally, there is no loss in the switch, and a high Q LC resonant circuit also m ake sure only the fundamental signal will be delivered to the load, and no harmonic power are dissipated on the load. S o, for an ideal Class D power amplifier, 100% drain effi ciency can be achieved. Figure 3 11 shows the drain voltage and current waveforms for ideal Class D power amplifier. Figure 3 1 1. D rain voltage and current waveforms of Class D power amplifier 3.1.2.4 Class E power a mplifier Figure 3 12. Schematic of Class E power amplifier

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62 Similar to Class D, a Class E power amplifier is also a switch mode amplifier which could achieve ideally 100% drain efficiency. The basi c circuit is shown in Figure 3 12 [21 ]. The NMOS transistor works as a switch and the high Q series LC tank forms a ha rmonic filter which is tuned at fundamental frequency. Figure 3 13 shows the drain voltage and current waveforms for Class E power amplifier [37], [38], [39] Figure 3 13 Drain voltage and current waveforms for Class E power amplifier The Class E power amplifier is entirely designed in the time domain. Assume L is a RF chock, when the switch is ON the DC current from the inductor L will flow through the switch. W hen the switch is OFF, the DC current minus the sinusoidal outp ut current will be dumped into the capacitor C 1 To ensure 100% efficiency, the power consumption of the transistor must be zero, which means that the drain current and voltage cannot be non zero at the same time. All component values are chosen to make tr ansistor drain voltage satisfy the following conditions [ 37 ] [38], [39] : 1. As the switch turns off, drain voltage remains low long enough for the current to drop to zero. 2. Drain voltage reaches to zero before the switch tunes on. 3. dV ds /dt is also near zero wh en the switch turns on.

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63 T he second condition prevents dissipation of the energy stored by the shunt capacitor at turn on, and the third condition makes the circuit less sensitive to components, frequency and switching variations. To satisfy these, values of inductor and capacitor must be (3 1 3 ) (3 1 4 ) A dra wback of C lass E power amplifier is the large peak voltage that the switch sustains in the off state, which is 3.56V DD in the ideal case This means that high transistor breakdown voltage or stacked transistor i s needed [40], [41], [42], [43] This is a cr itical issue especially when the power amplifier is implemented in advanced CMOS processes with low transistor breakdown voltage. Assume the drain voltage cannot exceed 2V DD for reliable operation of the power amplifier, the maximum output power for Class E PA is ( 3 1 5 ) R L is the nominal load impedance. 3 .1.2.5 Class F power a mplifier Power amplifier efficiency can also be improved by using harmonic tuning. Figure 3 14 shows the schematic of generic Class F power amplifier At the fundamental frequency, the impedance looking into the resonator is the optimized resistance R opt At odd order harmonic frequencies, the impedance is ideally infinity, and at even order harmonic freq uencies the resonator impedance is zero. Under the above harmonic tuning condition s the drain voltage and current would be square wave and half sine wave respectively with 180 degree phase difference as shown in Figure 3 15 100% drain efficien cy can be achieved in an ideal Class F power amplifier. If the load harmonic impedance is only considered to third order harmonics, the ideal drain efficiency is 88.4%, and 92% for fifth order harmonic termination [44], [45] Similarly as

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64 we discussed for Class E PA if the drain voltage cannot exceed 2V DD the maximum output power for Class F power amplifier with third and fifth harmonic termination network are as follows [ 35 ] [44], [45] : ( 3 1 6 ) ( 3 1 7 ) Figure 3 14. Schematic of g eneric C lass F power amplifier Figure 3 15. Drain voltage and current waveform s of Class F power amplifier

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65 3 .2 2.4 GHz CMOS Class F Power Amplifier Design Class E and C lass F are two commonly used in high efficiency non linear PA s A Class E PA is more efficient because of hard switching and zero voltage switchi ng as mentioned in the last section, and easier to build because of the relatively simple output network compared with Class F power amplifier However, for this operation, the drain voltage can be as high as 3.6V DD which can stress the MOS transistor. Th is is especially sever e in advanced CMOS technologies. On the other hand, in a Class F PA, though the output matching network is more complicated, the PA transistor experiences peak voltage of only 2V DD In order to decrease the loss from matching networks, most of the published C lass F CMOS PA s use either an off chip transmission line or bond wire inductors [46], [47], [48 ] which are not preferable for a true single chip radio integrating an on chip antenna. In this section, a fully integrated 2.4 GHz Class F CMOS PA for the true single chip radio fabricated in the UMC 130 nm digital CMOS process with eight layer copper metallization is introduced. Table 3 1 Maximum efficiency of Class F power amplifier under different harmonic termination conditio ns n=1 n=3 n=5 50% 57.74% 60.33% 63.7% m=2 70.7% 81.65% 85.32% 90.03% m=4 74.97% 86.56% 90.45% 95.45% 78.5% 90.69 94.77% 100% To implement the output network for C lass F PA ideally an infinite number of inductors and capacitors are needed. Since the quality factor of on chip inductors is not high, including multiple inductors increases loss. So, having higher order harmonic networks does not mean higher efficiency, not to men tion an increased circuit area. Table 3 1 lists the maximum output efficiency for Class F power amplifier for given set of harmo nics [44 ] [45] The efficiency

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66 improvement when terminating harmonic order than three is already limited. Practically, third order harmonic tuning network is used to build Class F power amplifier. Figure 3 16 shows a classic C lass F PA with a third order peaking network [44 ] This circuit however is not directly applicable in integrated circuits because of the parasitic drain capacitance of the transistor. Figure 3 16. Class F power amplifier with third order harmonic peaking network Figure 3 17 shows the schematic of PA with third harmonic peaking in this design, which incorporates an impedance transformation network for increased output power The input driver and output stages have a separate power connection V DD _Drv and V DD An inverter chain is used as a square wave driver. This makes the switching transition time of PA output stage shorter for increased efficiency, and removes the negative voltage s wing problem of tuned driver [47 ] C out in the output network includes the transistor output capacitance, and the parasitic capacitances of inductors L 1 L 2 and L 3

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67 Figure 3 1 7 Schematic of the fully integrated C lass F PA in this design The impedance looking in to the output network should be zero at the second order harmonic frequency and open at the third order harmonic frequency. L 2 and C 2 form a series resonant circuit which shorts out the network at second order harmonic frequency. A way to make the network open at the third harmonic frequency is to resonate L 3 and C 3 at the frequency [49], [50] ( 3 1 8 ) ( 3 1 9 ) Additionally, the impedance of peaking network in cluding L 1 L 2 C 2 and C ou t should also be open at the third or der harmonic frequency ( 3 20 ) At the fundamental frequency, the impedance of peaking network including L 1 L 2 C 2 and C out should also be infinite. ( 3 21 )

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68 In this case, the load impedance looking from the drain of the PA transistor at fundamental frequency will be only decided by the combination of L 3 C 3 C 4 and R L The L 3 and C 3 parallel circuit is inductive at the fundamental frequency This equivalent inductance L 4 along with capacitor C 4 will make the L shape impedance transformation network as shown in the inset of Figure 3 17. When the load impedance is transformed from R L to R OPT t he values of L 4 and C 4 should be ( 3 22 ) ( 3 23 ) T he values of L 3 and C 3 are adjusted to make their e quivalent inductance at the fundamental frequency equal to L 4 of the impe dance transformation network. ( 3 24 ) From equations ( 3 1 8 ), ( 3 21 ) and ( 3 23 ), L 3 and C 3 should be ( 3 2 5 ) ( 3 2 6 ) From equations ( 3 18 ), ( 3 20 ) and ( 3 21 ), the values of L 1 L 2 and C 2 are [49 ] ( 3 2 7 ) ( 3 2 8 ) ( 3 2 9 ) Once C out and R opt are known, the values of all the components are specified. Figure 3 1 8 shows the equivalent circuit of the Class F PA output matching network working at fundamental, second and third order frequencies.

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69 A B C Figure 3 1 8 Equivalent circuit of the Class F PA output matching network working at A) fundamental frequency, B) second order frequency and C) third order frequency

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70 To handle the output current, the PA output transistor size should be sufficiently wide. On the other hand, a wid er transistor has larger parasitic capacitances. From load pull simulations, the optimum width and length of PA transistor are 250 m and 0.12 m, with each finger width of 1 m. The output capacitance C out approximately equals to C db +C gd As previously me ntioned, C out should be accurately estimated to set the component values in the output network. The parasitic capacitance of metal lines for transistor connections is non negligible and should be accounted. The poly silicon gate is contacted from both side s to decrease the gate resistance. Since the transistor source is grounded, the source diffusion length is increased to 0.56 m. This increases the separation between the source and drain metal connections and that between the source and poly silicon gate connections, which in turn reduces the parasitic capacitance. Figure 3 1 9 shows the layout cell of PA output transistor. Figure 3 1 9 Layout cell of the PA output transistor

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71 Figure 3 20. Simulated drain voltage and current waveforms of the Class F power amplifier with third order harmonic peaking Table 3 2 The transistor sizes and passive component values of the Class F power amplifier Device Value Device Value M n1 21 m/0.12 m M p1 63 m/0.12 m M n2 3 m/0.12 m M p2 9 m/0.12 m M n3 9 m/0.12 m M p3 27 m/0.12 m M n4 27 m/0.12 m M p4 81 m/0.12 m M PA 250 m/0.12 m R f 140 L 1 2.2 nH L 2 1.3 nH L 3 1.3 nH C 2 820 fF C 3 360 fF C 4 870 fF

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72 Th e transformed resistance at the fundamental frequency, R opt in Figure 3 1 7 depends on the target output power and efficiency. There is tradeoff b etween the output power and efficiency. To increase the output power, R opt should be smaller. This however lowers the efficiency because the ratio between the series resistance of inductor and R opt increases and the loss of impedance transformation network increases. Since it is for short range wireless sensor applica tion, in this design, the target output power is 1 0 dBm. The maximum voltage at the drain node is set by the transistor breakdown and reliability limit. For V DD _PA =1.2V R L of 40 chosen to maximize the efficiency (with 2 dBm output power margin) and set the maximum drain voltage at 2. 4 V. The transis tor sizes and passive component values of the proposed Class F power amplifier are listed in Table 3 2. Figure 3 20 shows the simulated drain voltage and current waveforms of the proposed Class F power amplifier with third order harmonic peaking network. T he quality (Q) factor of on chip inductor is critical. In order to analyze the impact of Q of different inductors on PA efficiency, Q for each inductor is swept in simulations while the other inductors are assumed to be ideal. Th e plot is shown in Figure 3 21 Drain efficiency of 81% can be achieved when all the inductors are ideal. The drain efficiency is most sensitive to the Q of inductor L 1 T o increase Q of inductor the top two copper metal layers and Al cap aluminum layer are shunted to form the ind uctor L 1 L 2 and L 3 The metal width is chosen to be 10 m. The metal trace is ~4m above a poly silicon patterned ground shield. From ADS Momentum simulations, the quality factors of L 1 L 2 and L 3 at 2.4 GHz are 7.6, 7 and 5, respectively. Th e inductor Q is limited by the top metal thickness, and the PA efficiency can be further improved by thickening the metal layer. The simulated drain efficiency with these inductors is 51%

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73 Figure 3 2 1 Simulated drain efficiency versus Q for different inductors 3 .3 Measurement Results The PA output is connected to a power m eter through an HP8495A 50 MHz 26.5 GHz power sensor. The measurement setup is illustrated in Figure 3 2 2 The power losses from the measurement set up and cable are de embedded The measured return loss is less than 32 dB in the frequency range of 2 to 3 GHz The PA output power is saturated when input power is larger than 1. 5 dBm. The maximum saturated power gain is about 13 .9 dB. Figure 3 2 3 shows the measured satur ated PA output power, drain efficiency and power added efficiency (PAE) versus V DD _PA. V DD _Drv is kept at 1.2 V with 7 mA DC current. Output power of 12. 4 dBm is measured at V DD _PA=1.2 V with drain efficiency (E D ) of 4 6.5 % when only the PA stage is considered, and PAE of 3 8 % for the entire PA including the driver. The DC current in the power stage is 31 mA. W hen V DD _PA is increased while V DD _Drv is kept constant, the drain efficiency of PA stage decreases because the transis tor s pends more time in saturation region which

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74 increases effective loss of PA transistor On the other hand, the PAE of entire PA increases with V DD _PA because the increased output power (P out ) overcomes the decreased drain efficiency ( equation ( 3 30 ) ) F igure 3 2 4 shows the measured saturated PA output power, drain efficiency and PAE versus input frequency at 1.2 V DC supply voltage for the entire amplifier including the driver stage. The output power and efficiencies are peaked around 2.4 GHz. The die photograph of circuit is shown in Figure 3 2 5 The chip size is 0.6 mm x 0.7 mm including bond pads. Table 3 3 lists the performance summary of the PA and the comparisons with preciousl y published CMOS Class 4 Figure 3 2 2 Measurement setup for the PA power measurement ( 3 30 )

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75 Figure 3 2 3 Measured PA saturated output power, drain efficiency and power added efficiency vs. V DD_PA Figure 3 2 4 PA saturated output power and PAE under different input bias voltage with V DD =1.2 V for the driver and output stage.

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76 Figure 3 2 5 Die micrograph of the Class F power amplifier Table 3 3 Per formance summary of the Class F PA in this design Frequency (GHz) V DD (V) I Drv (mA) I PA (mA) P sat (dBm) Gain (dB) Drain efficiency (%) PAE (%) Area (mm 2 ) 2.4 1.2 7 31 12.4 13.9 46.5 38 0.42 Table 3 4 Performance comparison to the previously published CMOS Class F PA Reference [ 47 ] [ 48 ] [ 51 ] This work Frequency (GHz) 0.9 1.9 5.6 2.4 V DD (V) 1.8/3.0 3 1.9 1.2 Pout (dBm) 31.7 22.8 18.4 12.4 PAE/E D (%) 43/ 42/56 42.8/49.2 38/46.5 Technology 0.2 m 0.6 m 0.18 m 0.13 m Area (mm 2 ) 2 1.1 0.42 Fully integrated No No Yes Yes

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77 3 .4 Conclusions T he classification of power amplifiers is introduced in this chapter, and a fully integrated 2. 4 GHz Class F power amplifier fabricated in t he UMC 130 nm single poly silicon and eight metal layer digital CMOS process is demonstrated The single ended power amplifier consists of a tapered inverter driver with wideband resistive feedback input matching and an output stage with a fully integrated third harmonic peaking network incorporating impedance transformation. The drain efficiency and PAE are 4 6.5 % and 3 8 % respectively at 1.2 V supply voltage, and the saturated output power is 12.4 dBm with 13 .9 dB saturated power gain T he performance of PA from this work is compared to that of the previously published CMOS Class F P in T able 3 1. T o the best knowledge of authors, t he 2.4 GHz operation frequency is the lowest at which full integration of Class F PA in CMOS is demonstrated.

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78 CHAPTER 4 MULTI BAND WATT LEVEL CMOS POWER AMPLIFIER 4 .1 Overview 4 .1.1 Design Challenges of Watt Level Power Amplifier in Nano S cale CMOS Implementing a power amplifier with watt level output power in a CMOS technology is challenging, especially in more advanced technology nodes such as 65nm and 45nm CMOS technology with low supply voltage Unlike a GaAs HBT process, an LDMOS process and a SiGe HBT process which can provide fast and high er breakdown voltage transistors, the 65 nm CMOS technology used in this desig n supports lower breakdown voltage transistor s Because of the high output power requirement, t he reliability limit is often pushed in the design of CMOS power amplifiers It is suggested that keeping the voltage swing at each node of the transistor below twice the nominal supply voltage will cause no reliability issue [ 35 ] [ 52 ] [53], [54], [55], [56] The breakdown and stress related degradation mechanisms in MOS transistors include gate oxide breakdown, hot carrier degradation, punch through and drain bulk junction breakdown [ 35 ] [5 7 ] The gate oxide breakdown will cause permanent damage to the transistor. So, in PA design, gate to source and gate to drain voltages of MOS transistor s should be limited below the maximum allowable voltage for reli able operation. In short channel MOS transistors, if a high lateral electric field is present in the channel, the carriers may gain sufficient ener gy, and cause impact ionization [ 58 ] The highly energetic carriers are called hot carriers. The impact ioni zation also generates highly energetic electron/hole pairs. The hot carriers may tunnel through gate oxide or maybe trapped in the gate oxide. The trapped charges cause transistor parameter shift s and oxide breakdown. The hot carrier degradation occurs nea r the drain side under the condition of both high drain current and

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79 high voltage. In switch mode power amplifiers, ideally, high drain voltage and current cannot occur at the same time to increase efficiency, so hot carrier degradation should be mitigated When large voltage signal is applied on the drain side, the drain to bulk depletion region may extend to touch the source to bulk depletion region, diminishing the potentia l barrier that block s the direct current flow between the source and drain. This causes punch through [58], [59], [60], [61], [62] When punch through occurs, the gate will lose control of channel current. Punch through effect is more significant in small channel length transistors at high drain to source voltage s In PA design, drain to source voltage should be controlled to avoid the punch through effec t. The drain to bulk junction breakdown generally will not be an issue in CMOS PA design since the break down voltage is usually much higher t han the nominal supply voltage. F or example, in a 65 nm CMOS technology the breakdown voltage is roughly 10 V. 4 .1.2 Power Combining Techniques In cellular wireless communication applications, the output power required for a power amplifier is usually around 1 watt or higher. For example, for EGSM, its peak output power is even higher than two watts. As mentioned in last section, due to the low breakdown volt age of transistors in bulk CMOS, it is quite challenging to implement a single stage power amplifier with watt level output power. F or example, for 1.2 V nominal DC supply voltage the swing should be 1.2 V for reliable operation T o achieve 1 watt output power, load impedance of 0.72 is required. S uch small impedance is very difficult and unpractical to realize using an on chip impedance transformation network due to the high impedance transformation ratio as well as associated loss

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80 A B C Figure 4 1. Evolution of the LC matching network to a lattice type LC power combing network. Power combining techniques are usually used to combine outputs of multiple unit power a mplifier cells to achieve the required output power. Figure 4 1 shows how an LC matching network evolves to a lattice type LC power combining network [35 ] [54] In Figure 4 1 ( A ) a single ended PA output is connected to an LC matching network. If the output of a second power amplifier with 180 degree phase shift is connected to the capacitor of the L matching network as

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81 shown in Figure 4 1 ( B ) since the capacitor will give a negative phase shift and the inductor will give an equal positive phase shift the c urrents at the output will be combined in phase and result in higher output power. This circuit allows both impedance transformation and power combing at the same time. Since the input impedance looki ng into each branch is complex, a complex conjuga te component is placed at input of each port to make the transferred impedance real. The resulted lattice type LC power combining network is shown in Figure 4 1 ( C ) Figure 4 2 shows a Wilkinson power combiner [34 ] which is suitable for high frequency appl ication s and usually implemented off chip. Figure 4 2 Wilkinson power combiner A transformer based power combiner is suitable for fully integrated CMOS PA design. The conceptual schematic of power combining transformer [63], [64], [65], [66 ] [67], [68], [69], [70] is shown in Figure 4 3. M represents the number of primary windings, N 1 and N 2 represent the primary and secondary turns. I 1 is the input current of each primary winding and I 2 is the current flowing through t he secondary w inding. R 1 and R 2 are the parasitic resistance associated with primary and secondary winding s T he current and voltage relations are

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82 Figure 4 3. Transformer based power combiner ( 4 1) ( 4 2) C ombining equation ( 4 1) and ( 4 2), we can get ( 4 3 ) For 1:1 turn ratio for primary and secondary windings, the input impedance is ( 4 4 )

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83 A ssum ing the parasitic resistance R 1 and R 2 a re negligible, and the transformer is ideal, the input impedance for each stage is ( 4 5) T he total output power is ( 4 6) Therefore, u sing a transformer based power combiner, the PA output power can be significantly boosted without causing any reliability issues. 4.1.3 Multi B and Techniques in Power Amplifier I mplementation of a multi band system in CMOS is a critical requirement for the next generation wireless communication systems. It is preferred to use tunable single path rather than parallel paths concept to reduce the size and cost of system. For the receiver circuits many multi band circuits have been demonstrated. While in the transmitter side, realizing a multi band tunable CMOS power amplifier has been challenging and only limited examples are available in literatures. In [ 71 ], a reconfigurable qu ad band power amplifier for 1.9/2.3/2.6/3.5 GHz is implemented by selectively activating the transistor cells in the array of power transistors. Tunable series resonator is adopted in [ 72 ] to realize a multi band power amplifier from 450 MHz to 730 MHz as shown in Figure 4 4 Floating body technique is also adopted to protect the series switch from breakdown. Both of the quad band CMOS power amplifiers in [ 57 ] and [ 73 ] use two separate amplif iers for low er band (900 MHz) and high er band (1.8 and 1.9 GHz) I n [ 7 ], high Q off chip v aractor diode is used in the matching network to achieve a multi band SiGe PA which covers the 900 MHz, 1800 MHz, 1900 MHz and 2100 MHz bands, the schematic of multi band PA is shown in Figure 4 5. Bond wire inductors and a silicon on glass diode are used

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84 in this design. The multi band PA demonstrated in [ 74 ] uses resonant LC tank as a variable inductor to realize frequency tuning because the equivalent inductance of the LC tank shown in Figure 4 6 is changing with frequency The multi band techniques are summarized in Table 4 1. Until now, there is no tunable multi band CMOS power amplifier with watt level output power in the frequency bands of 850 MHz and 1700 MHz reported Figure 4 4 Multi b and C lass D power amplifier in [72 ] Figure 4 5. Multi band SiGe power amplifier in [7 ]

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85 Figure 4 6. Resonant LC tank is used as a variable inductor in [ 74 ] Table 4 1 Summary of multi band power amplifier techniques Ref. Frequency (GHz) Process V DD (V) Psat (dBm) Peak PAE (%) Multi band technique [ 71 ] 1.9/2.3/ 2.6/3.5 0.18 m CMOS 3.3 24.2/23.8/ 23.4/20.5 48.2/44.3/ 40.9/35.6 Selectively activate transistor cells. Non activated transistors are used as switching capacitors [ 74 ] 2.45/3.8 0.18 m CMOS 3.3 23.4/24.5 42/39 Resonant LC circuit is used as a variable inductor since the effective inductance of the tank is changing with frequency. [ 72 ] 0.45 0.73 0.18 m CMOS 3.3 20 70 Series switch capacitor is used to turn the resonant frequency B ody floating technique is also adopted to protect the device from break down. [ 75 ] 0.9 3.0 0.18 m CMOS 3.3 20 21 11 23 Using tunable capacitor array with output inductor to realize frequency tuning. [ 7 ] 0.9/1.8/ 1.9/2.1 SiGe 27 28 30 55 Using off chip diode based varactor for frequency tuning of matching network

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86 4 2 Watt Level Multi B and CMOS Power Amplifier 4 .2.1 Watt Level Multi B and CMOS Power Amplifier Architecture The design target is to realize a tunable multi band power amplifier with watt level output power for 85 0 MHz and 1.7 GHz bands in nano scale CMOS with low supply voltage and can be used in constant env elop modulation or envelop modulated transmit syst em s Therefo re, switch mode power amplifiers and linear ampli fiers driven in saturation mode can be considered Class E power amplifier has the high est achievable drain efficiency in CMOS technology and its matching network is relatively easy to implement on chip compared to Class F power amplifier s But the drain peak voltage is roughly 3.6V DD and the maximum output power is only ( 0.182 ) V DD 2 /R L as shown in equation 3 15 under the assumption that the drain vol tage cannot exceed twice of the nominal supply volt age Therefore, t he output power capability of Class E power amplifier is limited at given supply voltage. I t is also relatively hard to make the series components tunable in the output matching network For Class F power amplifiers, third order harmonic p ea king matching network can be integrated in CMOS as discussed in chapter 3. It has larger output po wer with the same DC supply voltage and output load impedance compared to a Class E power amplifier as shown in equation 3 16 But it is also not practical to make the third order peaking network tunable. In section 3.1.2.2, linear amplifier under over driven condition is discussed. When the gate of linear power amplifier output transistor is overdriven, the drain voltage and current clipping will occur whi ch reduce s the overlap of drain voltage and current waveforms. D rain efficiency could be improved bu t the linearity is degraded. Since the target of this design is for constant envelop modulation scheme, poor linearity is not an issue. The power amplifier performance comparison for the possible candidates is listed in Table 4 2

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87 Table 4 2 Power amplifier performance comparisons Class Class AB Class B Class E Class F(3) Peak efficiency 50~78.5% 78.5 % 100 % 88.4 % On chip m atching network complexity simple simple medium complicated Maximum output power [W] (Reliable operation, V DD =1V, R L <0.5 0.5 0.2026 0.6328 Figure 4 7. Schematic of single stage power amplifier The over dr iven linear power amplifier uses a simple output matching network. Figure 4 7 shows the schematic of a Class AB power amplifier with second order harmonic short As will discuss in later sections, this PA will be biased much closed to Class B mode. At fundamental frequency, the drain of tra nsistor M 1 will see the optimum load impedance R opt and the series connection of L 2 and C 2 will make a second harmonic short. As will be discuss ed in the subsequent sections, only shunt tuning elements are needed when a transformer is used for impedance transformation This make s it easy to use switched capacitor tuning banks to realize

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88 multi band tuning. Another benefit of using over driven linear power amplifiers is that it wi ll be convenient to make it a linear power amplifier with minor rev ision s to the driver circuit. To achieve watt level output power in nano scale CMOS technology with low supply voltage, transformer based power combining technique is used in this design. Figure 4 8 shows the block diagram of power amplifier. Eight differe ntial power amplifiers are combined with transformer based power combiner, and the primary to secondary winding ratio for each transformer is 1:1 Under the assumption of ideal power combiner, the load impeda nce seen by each differential power amplifier is Figure 4 8 Bloc k diagram of the watt level multiband power a mplifier

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89 A simplified equivalent model for the 1:1 transformer is shown i n Figure 4 9 [76 ] [77], [78], [79], [80] L p and L s are the primary and secondary winding inductances and the associated loss resistances are R s and R p respectively. K is the coupling coefficient between primary and secondary windings, and (1 k)L p and (1 k)L s are the leakage inductances. R o is the load impeda nce seen by each transformer. For this design case, R o should be one eighth of the load Shunt capacitors C p and C s are put at the primary and secondary windings to turn the transformer at certain frequency in order to decrease the loss b etween input and output ports [7 6]. The reason for single ended connection of C p is that it is easier to implement a single ended switch capacitor tuning bank than a differential one. And also, as will be discussed later, there are layout issues if C p is differentially connected between the nodes of primary inductor L p Figure 4 9 Equivalent model of transformer with capacitor tuning Figure 4 10 shows a schematic of the power amplifier in this design Instead of using an RF chock as shown in Figure 4 7 a narrow band resonant circuit is adopted. L 2 and C 2 make the second harmonic short. L 1 L 2 C 1 C 2 and the parasitic drain capacitance C out resonate at the

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90 fundamental frequency such that the load impedance seen from the drain of transistor M 1 will be R opt from the matching network. R opt is the required single ended load impedance for given output power target. I t is chosen as 3.125 this design. Figure 4 1 1 shows the schematic of PA with a transformer based matching network L p is the primary inductor of transformer. C p is the tuning capacitor shown in Figure 4 9 The inductor L 1 can be removed without changing the output impedance at fundamental frequency since it is replaced by the primary inductor L p S imilarly, C 1 and C out shown in Figure 4 11 can be absorbed into C p To over drive the PA output stage, a ta pered inverter buffer is used as a square wave driver that reduces the switching tra nsition time of PA output stage for increased efficiency. It also does not suffer from the negative voltage s w ing problem of tuned driver. The simulated drain voltage and current waveforms of t he differential power amplifier with the square wave driver is shown in Figure 4 1 2 Figure 4 10 Schematic of the single ended power amplifier used in this design

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91 Figure 4 1 1 The differential power amplifier with a transformer based matching network

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92 Figure 4 1 2 The drain voltage and current waveforms of the differential power amplifier driven in saturation mode 4 .2.2 Watt Level Multi B and Power Amplifier Design 4 .2.2.1 PA o utput t ransistor design c onsideration To proper ly choose the size of NMOS transistor s for the PA stage, many tradeoffs should be considered, including on resistance of the transistor, driver power consumption due to gate capacitance, and parasitic drain capacitance I n this design the PA transistor is over driven and acts as a switch T he gate driving signal is approximately a full swing square waveform in order to make the NMOS transistor properly switch. T he on resistance of an NMOS transistor working in linear region is [35] ( 4 7 )

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93 T he PA efficiency can be improve d by reducing the transistor on resistance, which means that large r transistor width W g and small er channel length L g are preferred T he transistor on resistance can be decrease d until the loss in the transistor is much smaller compared to the inductor loss. F or large r W g /L g transistors, there could be potentially hot carrier degradation issue, which occurs when large drain current is accompanied with large drain voltage [35] As mentioned before, h ot carrier degradation is alleviated in over driven power amplifiers, since the voltage and current are separated in time by shaping of the drain voltage and current waveforms T he gate capacitance of PA output transistor needs to be ch arged to V DD and discharged to 0 When an inverter based buffer is used, the power consumption of driver is ( 4 8 ) The gate capacitance C g includes the g ate to source capacitance and gate to drain capacitance which are proportional to gate width W g f is the operating frequency Increasing the transistor width to decrease the on resistance of PA switch transistor makes the driver stage consume more power, and this degra des the overall efficiency T here would also be increased drain parasitic capacitance when a large r PA output transistor is chosen. B ut as shown in Figure 4 1 1 this capacitance can be m erged into the output matching network The transistor size of 4.86 m m width and 65 nm channel length is chosen for th e power amplifier output stage. The layout of unit cell structure with finger width of 0.9 m is shown in Figure 4 1 3 Transistor gates are double side connecte d to reduce the gate resistance that increases the power gain P + guard ring is placed around each unit cell structure to reduce the substrate resistance. The DC current flowing through each of the single ended power amplifier stage is about 300 mA and the peak drain current is about 7 00 mA To make sure the output stage transistor can handle such high current without suffering from the electromigration problem me tal 1 to metal 5 layers are stacked up and metal 2 to metal 5 layers are connected in

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94 parallel for the source and drain connectio n out of transistor as shown in Figure 4 1 4 The top metal layer (metal 6) is used for g lobal routing of the unit cells because of its low resistivity and high current handling capability The transistor interconnection scheme is shown in Figure 4 1 5 Figure 4 1 3 Simplified layout of the power amplifier output transistor cell Figure 4 1 4 Metal stack for source/drain connections of the PA transistor

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95 Figure 4 1 5 PA transistor layout Figure 4 16 Inverter chain based wideband PA driver

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96 4 .2.2. 2 Wideband PA d river d esign T o make the PA output transistor work as a switch, square wave dr iving signal from the PA driver is needed. Because of this, an inverter chain based PA driver as shown in Figure 4 1 6 is used in this design. Resistive feedback in the first stage can provide wideband gain an d input matching for the driver No tunable elements are needed for the driver Furthermore, it is compact and fits reasonably well within the overall PA layout. However, it consumes higher power than tune d amplifier based driver s Table 4 3 T he circuit parameters for the PA driver Device Value Device Value M n1 14.4 m/0. 65 m M p1 2 8.8 m/0.65 m M n2 28.8 m/0.65 m M p2 57.6 m/0.65 m M n3 57.6 m/0.65 m M p3 115.2 m/0.65 m M n4 115.2 m/0.65 m M p4 230.4 m/0.65 m M n 5 230.4 m/0.65 m M p 5 460.8 m/0.65 m M n 6 460.8 m/0.65 m M p 6 921.6 m/0.65 m M n 7 921.6 m/0.65 m M p 7 1843.2 m/0.65 m R f 1.6 Since eight differential power amplifiers are combined in this design, matched input power distribution for all the drivers is critical to make the phase error of the power amplifiers minimum. Otherwise, the output voltage on the secondary inductor of the power combiner may potentially cancel Figure 4 1 7 shows the input r outing scheme for the power amplifier The differential lines carry the balanced input signal to the center of the chip, and symmetrically distribute to th e eight differential PA drivers. The S parameter simulation result of the input matching is shown in Figure 4 1 8 | S 11 | is below 13 dB in the frequency range of 0.4 GHz to 2.4 GHz. The parasitic from input power distribution network is also considered in the simulation.

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97 Figure 4 1 7 Input power distribution scheme for the power amplifier Figure 4 1 8 Simulated | S 11 | for the input matching of the driver

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98 4 .2.2. 3 Transformer b ased p ower c ombiner d esign Figure 4 1 9 shows the slab inductor based transformer with a patterned ground shield used for each power amplifier [63], [64] T he secondary inductor is stacked vertically above the primary inductor. The current through the primary inductor of the transformer is larger than the current in th e secondary inductor. Therefore, a thicker metal is used for the primary inductor. T he thickness es of metal 6 and Al cap layer are ~ 1.6 m and ~ 1 m respectively T he inter laye r dielectric thickness is ~ 0.85 m. P erpendicular metal 1 patterned ground shield is used to steal the electrical field from the substrate. I deally the influence on the magnetic field is small since the slots in the shield avoid the generation of induced currents. T o further preven t substrate loss, high resistivity layer (HiRES) is used to cover the substrate area underneath the transformer T he HiRES layer block s the p well doping and make s the substrat e less conductive. Figure 4 1 9 3 D view of the stacked transformer with patterned ground shield T he conductor width and length of the stacked transformer are chosen as 60 m and 9 6 0 m. A compact model in Figure 4 20 [76 ] [78], [79], [80] is used to fit the simulation results from the EM simulator. Capacitance C p and C s are shunted with the primary and secondary

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99 inductor respectively to frequency parameter simulation results of the transformer in both low frequency and high frequency bands are shown in F igure 4 21 Figure 4 20 Compact model for the stacked transformer Table 4 4 The extracted equivalent circuit parameters for the 1:1 slab inductor based transformer, interconnection parasitic are also included in the simulation Circuit parameters Extracted value Circuit parameters Extracted value L p 0.7nH L s 0.8nH R p 0.28 R s 0.59 L pf 0.08nH L sf 0.13nH R sf R pf C p1 140fF R sub1 C p2 12fF R sub2 C c 650fF k 0.85

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100 Figure 4 21 Transformer S parameter ( | S 21 |) simulation in both low frequency and high frequency bands A B Figure 4 22 Conceptual drawing of the power combiner

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101 T he conceptual drawing of power combiner with eight transformers is shown in Figure 4 22 The primary side of each transformer is connected to a differential power amplifier and the secondary sides of all the transformers are connected in series to combine the output AC voltage. DC supply voltage V DD is fed into the center of primary inductor of each transformer 4 .2.2. 4 Multiband t uning c ircuits d esign A B Figure 4 23 The tuning capacitor connection at the primary inductor, A) differential connection across the two nodes of the primary inductor, B) separate single ended connection from the two nodes to ground. As mentioned in section 4.2.1 series connection of L 2 and C 2 is used as a second order harmonic short of the power amplifier. At the fundamental frequency, the series connection is cap acitive. T his equivalent capacitance along with the parasitic drain capacitance C out is used as part of the transformer tuning capacitance C p It is not practical to connect the tuning capacitor C p across V PA+ and V PA of the primary inductor because the parasitic inductance of the capacitor

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102 rout ing become s comparable with the inductance of the primary inductor as shown in Figure 4 23 ( A ) [63], [64] [66] Tuning capacitors between drain and ground are used instead as shown in Figure 4 23 ( B ) This however increases the required capacitance. Once the dimension of transformer power combiner is decided, tuning capacitance at the primary side of each tr ansformer will be decided as C pH and C pL for higher and lower band s respectively. The capacitance value s of C 2 for higher ( C 2H ) and lower ( C 2L ) band are : (4 9) (4 10) H L are the center frequencies for higher and lower band s L 2 of 350 pH is chosen in this design. At the fundamental frequency, the equivalent capacitances of the series connection of L 2 and C 2 are (4 11) (4 12) Therefore, the shunt capacitance s of C 1 a t higher and lower band are shown as below (4 13) (4 14) Figure 4 24 shows the schematic of watt level multi band power amplifier with tunable capacitor s The tunable capacitor bank s C 1 and C 2 are realized by using a binary array of metal capacitors on top of switches, as shown in Figure 4 25 In each tuning bank, there are four voltage controls. Take the switch capacitor C M and M 1 for example, when the control voltage is C M And when the control voltage is the total capacitance value is equal to C M (C d +C M,p )/(C M +C d +C M,p ). To increase the tuning range of the capacitor bank, a minimum length transistor is used and transistor width should be

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103 small to reduce the parasitic drain capacitance However small transistor size will degrade the Q of capacitor bank since the tu rn on resistance would be increased. Q uality factors of C 1 and C 2 were swept separately to check the impact of capacitor tuning bank Q on the performance of the power amplifier Figure 4 2 4 Multiband power amplifier with tunable switch capacitor banks Figure 4 26 shows the simulated plot of power amplifier drain efficiency versus the Q of C 1 and C 2 at 900MHz band. The transistor and transformer loses are als o considered in the

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104 simulation. Q of each capacitor bank is swept separately while the other capacitor bank is assumed to be ideal. The drain efficiency versus Q of C 1 and C 2 at 17 00 MHz band is shown in Figure 4 27 Tuning bank Q of larger than 1 5 and 20 in lower band and higher band are chosen to meet the tuning range while not significantly degrading the drain efficiency. Figure 4 25 Multiband power amplifier with tunable switch capacitor banks Figure 4 26 Drain efficiency of the PA versus the Q of th e capacitor tuning bank C 1 and C 2 at lower frequency band (850 MHz).

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105 Figure 4 2 7 Drain efficiency of the PA versus the Q of the capacitor tuning bank C 1 and C 2 at higher frequency band (1700 MHz). 4.2.2.5 Bypassing of t he multiband power a mplifier Power amplifiers at low supply voltage, requires large r current from the DC voltage supply. On chip and PCB bypassing are critical to make the power amplifier properly work. For differential amplifiers, the drain current is symmet rical and the current through the supply bond wires is approximately DC. But this is the ideal case and only valid when the differential ampli fier is driven by small signal. In this design, the PA output stage is overdriven and working as a switch. Therefo re in general the drain current is not symmetric and there is AC current from the supply. Furthermore, the supply and ground bond wires between the chip and PCB introduce finite inductance L VDD_bond and L GND_bond as shown in Figure 4 28 Those indu ctors will cause ground bounce To suppress the AC current ripple through the V DD of each differential power

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106 amplifier, 300 pF on chip MOS capacitors are placed close to the DC feed point of each transformer. 3 pF capacitance cells are shunted together to form t he capacitors. Figure 4 2 8 Differential amplifier with parasitic inductances from the routing and bond wires Compa red to on chip bypassing printed circuit board (PCB) bypassing is more complicated because of the frequency limitation of the off chip capacitors. The bypass scheme on PCB is shown in Figure 4 2 9 Bulk capacitors (usually Tantalum capacitors) are used to stabilize the supply voltage on a PCB at low frequency and the purpose of high frequency capacitors (usually ceramic capacitors) is to reject the high frequency ripple on the supply. A combination of the capacitors is to properly t he frequency range of interest s In the equivalent circuit model of the capacitor as shown in Figure 4 2 9 equivalent series resistor (ESR) and series inductor (ESL ) model the DC and frequency dependent los s es of the capacitor. The parasitic inductance of package makes the off chip capacitor inductive when the frequency is higher than the self resonant frequ ency (SRF) of capacitor. We can use multiple capacitors with varies SRF to realize the low impedance bypassing at the frequency range of

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107 interests The inductance of metal trace s on a PCB should be also considered since it change s the SRF of capacitor. Figure 4 2 9 Printed circuit board bypassing for power amplifier performance evaluation 4 .2.3 Measurement Results The multiband PA is fabricated in 1.2 V TI 65 nm CMOS technology The test chip is mounted on a PCB to evaluate its performance. The power measureme nt setup is shown in Figure 4 30 Due to the high supply current for the PA output stage, three separate DC supplies are used. The DC feed points of the eight differential power amplifiers are bonded out to three separate DC pads on PC B as shown in Figure 4 31 The balanced 50 is pr ovided by connec ting each output node of the on chip power combiner to a 25 consisting two parallel 50

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108 Figure 4 30 Power amplifier power measurement setup Figure 4 32 shows a photo graph of printed circuit board for the test chip performance evaluation An off chip balun is used to generat e the differential input signal for the PA driver. External RF chocks are also connected to the supply on the printed circuit board to avoid the unexpected oscillation The chip on board bonding diagram and the PA d ie photo ar e shown in Figure 4 33 To reduce the ground bond wire inductance, two rings of bond pads are used to improve ground connection. The dimension of the chip is about 3.5 mm x 3.5 mm including the bond pads. The chip is mounted on the ground pad of printed circuit board using electronically and thermally conductive epoxy to further reduce the ground inductance and t o help heat dissipation. A heat sink is also attached to the back of the printed circuit board. The tuning of secondary inductor for the power combiner is realized by using an external trimmer. All power losses from the setup are de embedded The power los s of the bond wire is included in the PA measurement results.

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109 Figure 4 31 Separate V DD on printed circuit board for PA evaluation Figure 4 32 P hoto graph of the printed circuit board for chip evaluation

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110 Figure 4 33 Chip on board bonding scheme and the die photo of multi band power amplifier

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111 Figure 4 34 shows the measured output power, drain efficiency and power added efficiency of the multi band PA working at the lower band (850 MHz) The supply voltage V DD_Drv for the square wave driver of 1.8 V is used to overdrive the PA stage The supply voltage of PA stage V DD_PA during the frequency sweep measurement is kept at 1.2 V. The PA is tuned at 850 MHz with 30.2 dBm saturated output power with drain efficiency and power added efficiency of 24.3% and 20.6% respectively. The measured output power, drain efficiency and power added efficiency versus PA stage DC supply V DD_PA at 850 MHz are plotted in Figure 4 35 Output power versus input power characteristic of the PA at 850 MHz is shown in Figure 4 36 The PA output power is saturated when the input pow er is larger than 15.2 dBm with power gain of 15 dB. Figure 4 34 M easured output power, drain efficiency and power added efficiency of the multi band PA versus frequency at the lower band

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112 Figure 4 35 M easured output power, drain efficiency and power added efficiency versus PA stage DC supply V DD_PA at 850 MHz Figure 4 36 Measured output power versus input power characteristic s of the PA at 850 MHz

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113 Figure 4 37 shows the measured output power, drain efficiency and power ad ded efficiency of the PA in the higher band. The supply voltage V DD_Drv for the square wave driver is once again 1.8 V and the supply voltage of the PA stage V DD_PA is 1.2 V. The PA is tuned at 1700 MHz achieving 29.5 dBm saturated output power with drain efficiency an d power a dded efficiency of 22.2% and 16.7 % respectively. The measured output power, drain efficiency and power added efficiency versus PA stage DC supply V DD_PA at 1700 MHz is plotted in Figure 4 38 The o utput power versus input power characteristic s of PA at 170 0 MHz are shown in Figure 4 39 The PA output power is saturated when the input power is larger th an 17.4 dBm with saturated power gain of 12.5 dB. Figure 4 37 M easured output power, drain efficiency and power added efficiency of the multi band PA versus frequency at the higher band

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114 Figure 4 3 8 M easured output power, drain efficiency and power added efficiency versus PA stage DC sup ply V DD_PA at 1700 MHz Figure 4 3 9 Measured output power versus input power characteristic s of the PA working at 1700 MHz

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115 The performance of multi band tunable watt level power ampl ifier is summarized in Table 4 5. Table 4 6 shows the performance comparisons with the tunable power amplifier performance in the literature. The performance comparisons with the power amplifiers in nano scale CMOS te chnology are listed in Table 4 7 Table 4 5 Summary of the measured multi band power amplifier performance Frequency Band Lower band (850 MHz) Higher band (1700 MHz) Driver V DD 1.8V 1.8V PA stage V DD 1.2V 1.2V Driver DC current 0.38A 0.8A PA stage Current 3.6A 3.8A Output power 30.2 dBm 29.5 dBm Drain efficiency 24.3% 22.2% Power added efficiency 20.6% 16.7% Saturated power gain 15 dB 12.5 dB Table 4 6 Performance comparison to the previously published tunable multi band CMOS power amplifiers Reference [71] [74] [75] This Work Frequency (GHz) 1.9/2.3/2.6/3.5 2.45/3.8 0.9~3 0.85/1.7 Technology 0.18 m 0.18 m 0.18 m 65nm V DD (V) 3.3 3.3 3.3 1.2 P sat (dBm) 24.2/23.8/23.4/20.5 23.4/24.5 20~21 30.2/29.5 Peak Drain Efficiency (%) 48.2/44.3/40.9/35.6 42/39 24.3/22.2 Peak PAE (%) 11~23 20.6/16.7 Chip Area (mm 2 ) 1.61 1 0.31 12.25

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116 Table 4 7 Performance comparison to the previously published power amplifiers in nano scale CMOS Frequency (GHz) CMOS Technology V DD (V) Transistor Type P sat (dBm) Peak PAE (%) Chip Area (mm 2 ) Ref. 2.4 65 nm 1 TN 21.8 44 [82] 1.8 65 nm 3.4 TN/TK 29.4 51 [83] 2.5 0.18 m 3.3 TN/TK 31 34.8 1.98 [84] 2.75 32 nm 1.8 TN/TK 28 31.9 2 [85] 2.4 32 nm 2 TN 25.3 35 1.28 [86] 2.4 65 nm 3.3 TN/TK 31.5 25 2.7 [87] 2.4 90 nm 3.3 TN/TK 30.1 33 4.2 [88] 2.5 90 nm 3.3 TN/TK 32 48 2.25 [89] 2 0.13 m 3.3 TN/TK 29.3 69 4 [90] 1.8 0.18 m 3.3 TN/TK 31.2 41% 2.2 [65] 0.85/1.7 65 nm 1.2 TN 30.2/29.5 20.6/16.7 12.25 This work TN: Thin gate oxide transistor, TK: Thick gate oxide transistor 4 3 Conclusions A tunable multi band power amplifier designed in 1.2 V TI 65 nm CMOS process is presented in this chapter. It utilizes an on chip transformer based power combiner where eight differential PAs are combined in order to achieve watt level output power. A tapered inverter driver with resistive feedback is designed to provide wideband input matching and square wave drive for the PA stage Capacitor tuning banks are used to realize the frequency tuning between 850 MHz and 1700 MHz At 850 MHz band, the saturated output power of 30.2 dBm with drain efficiency and power added efficiency of 24.3% and 20.6% is achieved. It has saturated power

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117 gain of 15 dB. At 1700 MHz, the saturated output power is 29. 5 dBm with 12.5 dB gain. D rain efficie ncy and power added efficiency are 22.2% and 16. 7%. This is the first tunable multi band watt level power amplifier using nan o scale CMOS technology that supports 850 MHz and 1700 MHz frequency bands with supply voltage lower than 2 V.

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118 CHAPTER 5 SUMMARY AND FUTURE W ORK 5.1 Summary A T/R switch and a power amplifier are two high power RF transceiver building blocks. They are also the barriers for realizing a single CMOS radio. The research work in thi s dissertation suggests possible approaches and provides understanding of limitations for implementing T/R switch es with high power handling capability and frequency tunable power amplifier s with high output power in advanced CMOS technologies Compared to MOS transistors in nano scale CMOS, p n diodes have the advantage of high breakdown voltage. The possibility of using an on chip p n diode to implement a broadband NMOS/Diode hybrid CMOS T/R switch has been evaluated Only thin gate oxide transistors along with a p n diode are used. Transmit and receive i nsertion loss of 0.5dB and 1.1 dB, and IP 1d B of ~28 dBm have been achieved in a 45 nm bulk CMOS process using a series NMOS and series diode hybrid configuration This is the first effort to evaluate the performance in particular the power handling capability can be achieved for a T/R switch opera ting around 900 MHz using p n diodes in nano scale CMOS A fully integrated 2.4 GHz CMOS Class F power amplifier in UMC 130 nm single poly silicon and eight metal layer digital CMOS process is demonstrated The single ended power amplifier consists of a ta pered inverter driver with wideband resistive feedback input matching and an output stage with a fully integrated third harmonic peaking network incorporating impedance transformation. The drain efficiency and PAE are 4 6.5 % and 3 8 % respectively at 1.2 V supply voltage. T he saturated output power is 12.4 dBm with 13 .9 dB power gain The 2.4 GHz operation frequency is the lowest at which full integration of Class F PA in CMOS is demonstrated.

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119 A tunable multi b and power amplifier fabricated in the 1.2 V TI 65 nm CMOS pro cess is presented. It has an on chip transformer based power combiner where eight differential PAs are combined in order to achieve watt level output power. A tapered inverter driver with resistive feedback is designed to provide wideband inp ut matching. Capacitor tuning banks are used to realize the multi band tuning at 850 MHz and 1700 MHz At 85 0 MHz, the saturated output power of 30.2 dBm with drain efficiency and power added efficiency of 24.3% and 20.6% is achieved when the driver and PA stage supply voltage of 1.8 V and 1.2 V respectively. At 1700 MHz, the saturated output power is 29.5 dBm with 12.5 dB gain. Drain efficiency and power added efficiency of 22.2% and 16.7% are achieved under the driver and PA stage supply voltage of 1.8 V and 1.2 V respectively. This is the first tunable multi band watt level power amplifier using nan o scale CMOS technology that supports 850 MHz and 1700 MHz frequ ency bands with supply voltage lower than 2 V. 5.2 Future Work The following future work that extends the effort described in this dissertation is suggested. As mentioned in chapter 2. The NMOS/Diode hybrid T/R switch requires DC power consumption in RX mode, and approaches to lower this including further reduction of current gain of parasit ic p n p transistors should be considered. A S chottky diode is another type of diode s available in standard foundry CMOS process. When a S cho ttky diode is forward biased, the parasitic vertical p n p transistor action as shown in Figure 2 24 is avoided The turn on voltage of S chottky diode is also smaller compared to p n diode s This should lower the power consumption and make S chottky diode s a better choice for implementing diode T/R switch in CMOS technology The schematic of T/R switch using a S chottky diode is shown in Figure 5 1. Evaluation of this prototype is suggested in the future.

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120 Figure 5 1. Schematic of NMOS/Diode hybrid T/R switch using a S chottky diode A tunable multi band watt level power amplifier is demonstrated in chapter 4. Mechanical trimmer is used at the PA output to turn the secondary inductor of the tr ansformer based power combiner. A tuning method using voltage controlled variable capacitor is suggested in Figure 5 2. Since the voltage swing at the output of the power combiner is large, MOS capacitor based varactors cannot be used here due to their low breakdown voltage. On chip diode or external PIN diode [92] based varactors could be consider ed. For on chip diode based varactor option, high breakdown voltage diode is needed. N well to p substrate diode has the largest breakdown voltage among the diodes available in standard CMOS technology because of the lower doping density for n well. On the other hand, series resistance of such diode is relatively high and will degrade the Q of the varactor. Therefore, multiple diode cells should be shunted in parallel.

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121 Figure 5 2. Voltage controlled tuning at the output of power combiner

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122 APPENDIX PRINTED CIRCUIT BOARD DESIGN FOR MULTI BAND PA EVALUATION As mentioned in chapter 4, printed circuit board is important for low voltage and high current PA evaluation. Four layer printed circuit board is used in the multi band w att level power amplifier measurement in order to use the layer to layer capacitance wi th high self resonant frequency The layer thicknesses are shown in Figure A 1. Figure A 2 shows the layout of top layer. The DC supply for PA output stage is divided in to three separate sections to reduce the current flowing through each supply plane. The main routings on the top layer is ground plane and PA stage supply plane. To increase the printed circuit board capacitance for bypassing the second layer is chosen a s ground plane. The layout of second layer is shown in Figure A 3 For layer 3, it is mainly power plane which is divided into three power sections for power amplifier output stage, and four power plans for driver as shown in Figure A 4 T he current throug h driver stage is not high and the bypassing requirement is not demanding Having four driver power sections is only for ease of interconnection. Figure A 5 shows the layout of bottom plane, which is mainly composed of a ground plane. Four symmetric outputs are also routed on the bottom plane of the PCB. Figure A 1. F our layer printed circuit board thickness es.

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123 Figure A 2 T op layer of the multi band PA evaluat ion board Figure A 3. S econd layer of the multi band PA evaluation board

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124 Figure A 4. T hird layer of the multi band PA evaluation board Figure A 5. B ottom layer of the multi band PA evaluation board

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133 BIOGRAPHICAL SKETCH Tie Sun was born in C angzhou Hebei Province, China, in 1980. H e rece ived the Bachelor of Science degree in electrical engineering from Hefei University of Technology, Hefei, China in 2003 and Master of Science degree in electrical e ngineering from Shanghai Jiao T ong University Shanghai, China, in 2006 Since 200 7 he has been w ith Silicon Microwave Integrated Circuit s and System s Research (SiMICS) group d epartment of e lectrical and c omputer e ngineering University of Florida. From April 2006 to July 2006, he worked as an analog integ rated circuit design engineer at STMicr oelectronics Shanghai, China. H is research interests include CMOS T/R switch and power amplifier design