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Sub-Terahertz Signal Generation in CMOS

Permanent Link: http://ufdc.ufl.edu/UFE0042807/00001

Material Information

Title: Sub-Terahertz Signal Generation in CMOS
Physical Description: 1 online resource (126 p.)
Language: english
Creator: SHIM,DONGHA
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2011

Subjects

Subjects / Keywords: ANTENNA -- ANTIPARALLEL -- CMOS -- DIVISION -- DOIDE -- INDUCTOR -- LINE -- MULTIPLICATION -- ONCHIP -- OSCILLATOR -- SCHOTTKY -- SUBTERAHERTZ -- SYMMETRIC -- TRANSMISSION -- VARACTOR
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation investigates the feasibility of sub-terahertz (sub-THz) signal generation using CMOS (Complementary Metal Oxide Semiconductor) technology. The sub-THz portion of spectrum has remarkable properties especially suitable for sensing, imaging, and communication applications. The recent progress of high-frequency capability for CMOS has made it possible to consider the process as a new means to overcome the limitations of cost and integration level of conventional sub-terahertz systems. Two novel non-linear devices, complementary anti-parallel diode pair (C-APDP) and symmetric varactor (SVAR), were implemented in 130-nm digital CMOS process for sub-THz frequency multiplier applications. The C-APDP employs both n-type SBD (n-SBD) and p-type SBD (p-SBD) to eliminate the deleterious effects of substrate parasitics. The device exhibited an extrapolated cutoff frequency of ~470 GHz. The SVAR consists of a p- and n-type accumulation-mode varactor connected in parallel to achieve symmetric C-V characteristics. The device showed the maximum cutoff frequency of ~320 GHz and dynamic cutoff frequency of ~125 GHz. Harmonic power measurements showed the effective generation of odd order harmonic powers while suppressing even order ones. To investigate the feasibility of operation of a sub-THz CMOS circuit in harsh spectroscopy environments, CMOS devices are characterized under the low temperature and high magnetic field. The temperature dependences of devices including NMOS transistors, and p-n junction, and Schottky barrier diodes were measured at 300, 150, 77, and 4.2 K. The field dependence of NMOS transistors is also measured under magnetic fields up to 6 T at the liquid helium temperature. The measured results indicated that CMOS circuits should have acceptable characteristics in the cryogenic and high field spectroscopy environment. The first sub-THz CMOS frequency tripler has been demonstrated using a C-APDP. The tripler exhibited ~34-dB minimum conversion loss, -24-dBm maximum output power at 150 GHz, and 3-dB output frequency range of ~10 GHz, which is ~10X wider than that of a 140-GHz CMOS oscillator fabricated in 90-nm CMOS. To demonstrate sub-THz frequency division in CMOS, a 194-GHz divide-by-4 frequency divider has been implemented in 45-nm logic CMOS technology. Two cascaded divide-by-2 ILFD stages are employed to divide ~194-GHz input signal in to ~48.5-GHz. A sub-THz quadruple-push oscillator has been implemented using low leakage transistors in 45-nm CMOS. Quasi-optical measurements showed that the circuit generates 4th harmonic signal at 553 GHz with the power level of 220 nW, while suppressing unwanted harmonic signals. These results provide the foundation for the eventual realization of compact and affordable sub-THz systems using CMOS integrated circuits.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by DONGHA SHIM.
Thesis: Thesis (Ph.D.)--University of Florida, 2011.
Local: Adviser: O, Kenneth K.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2012-04-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2011
System ID: UFE0042807:00001

Permanent Link: http://ufdc.ufl.edu/UFE0042807/00001

Material Information

Title: Sub-Terahertz Signal Generation in CMOS
Physical Description: 1 online resource (126 p.)
Language: english
Creator: SHIM,DONGHA
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2011

Subjects

Subjects / Keywords: ANTENNA -- ANTIPARALLEL -- CMOS -- DIVISION -- DOIDE -- INDUCTOR -- LINE -- MULTIPLICATION -- ONCHIP -- OSCILLATOR -- SCHOTTKY -- SUBTERAHERTZ -- SYMMETRIC -- TRANSMISSION -- VARACTOR
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation investigates the feasibility of sub-terahertz (sub-THz) signal generation using CMOS (Complementary Metal Oxide Semiconductor) technology. The sub-THz portion of spectrum has remarkable properties especially suitable for sensing, imaging, and communication applications. The recent progress of high-frequency capability for CMOS has made it possible to consider the process as a new means to overcome the limitations of cost and integration level of conventional sub-terahertz systems. Two novel non-linear devices, complementary anti-parallel diode pair (C-APDP) and symmetric varactor (SVAR), were implemented in 130-nm digital CMOS process for sub-THz frequency multiplier applications. The C-APDP employs both n-type SBD (n-SBD) and p-type SBD (p-SBD) to eliminate the deleterious effects of substrate parasitics. The device exhibited an extrapolated cutoff frequency of ~470 GHz. The SVAR consists of a p- and n-type accumulation-mode varactor connected in parallel to achieve symmetric C-V characteristics. The device showed the maximum cutoff frequency of ~320 GHz and dynamic cutoff frequency of ~125 GHz. Harmonic power measurements showed the effective generation of odd order harmonic powers while suppressing even order ones. To investigate the feasibility of operation of a sub-THz CMOS circuit in harsh spectroscopy environments, CMOS devices are characterized under the low temperature and high magnetic field. The temperature dependences of devices including NMOS transistors, and p-n junction, and Schottky barrier diodes were measured at 300, 150, 77, and 4.2 K. The field dependence of NMOS transistors is also measured under magnetic fields up to 6 T at the liquid helium temperature. The measured results indicated that CMOS circuits should have acceptable characteristics in the cryogenic and high field spectroscopy environment. The first sub-THz CMOS frequency tripler has been demonstrated using a C-APDP. The tripler exhibited ~34-dB minimum conversion loss, -24-dBm maximum output power at 150 GHz, and 3-dB output frequency range of ~10 GHz, which is ~10X wider than that of a 140-GHz CMOS oscillator fabricated in 90-nm CMOS. To demonstrate sub-THz frequency division in CMOS, a 194-GHz divide-by-4 frequency divider has been implemented in 45-nm logic CMOS technology. Two cascaded divide-by-2 ILFD stages are employed to divide ~194-GHz input signal in to ~48.5-GHz. A sub-THz quadruple-push oscillator has been implemented using low leakage transistors in 45-nm CMOS. Quasi-optical measurements showed that the circuit generates 4th harmonic signal at 553 GHz with the power level of 220 nW, while suppressing unwanted harmonic signals. These results provide the foundation for the eventual realization of compact and affordable sub-THz systems using CMOS integrated circuits.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by DONGHA SHIM.
Thesis: Thesis (Ph.D.)--University of Florida, 2011.
Local: Adviser: O, Kenneth K.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2012-04-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2011
System ID: UFE0042807:00001


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1 SUB-TERAHERTZ SIGNAL GENERATION IN CMOS By DONGHA SHIM A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORID A IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2011

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2 2011 Dongha Shim

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3 To the memory of my father

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4 ACKNOWLEDGMENTS I would like to express my deep gratitude and appreciation to my advisor, Professor Kenneth K. O, for his pat ient guidance and cons tant encouragement throughout my doctoral research. Also much appreciation goes to Professor William R. Eisenstandt, Professor Jing Guo and Profe ssor David B. Tanner for their helpful suggestions to my research. I wo uld like to thank them for their interests in this work and serving in my Ph.D. supervisory committee. I would like to thank all the former and current colleagues in the SiMICS research group for their helpful discussions, advice and friendship. Some names ar e listed here: Chikuang Yu, Ha ifeng Xu, Jau-Jr Lin, Yu Su, Changhua Cao, Yanping Ding, Eun-Yo ung Seok, Kwangchun Jung, Swaminathan Sankaran, Hsin-ta Wu, Chuying Mao, Ning Zhang, Seon-Ho Hwang, Nallani Shashank Kiron, Myoung Hwan Hwang, Zhe Wang, Wuttichai Lerdsitsomboon, Kyujin Oh, Tie Sun, Minsoon Hwang, Ruonan Han, Gayathri Devi Sridharan, Choong-yul Cha, Yanghun Yoon, Chieh-Lin Wu, Gyungsun Sul, Te-yu Kao, Yaming Zhang, Jing Zhang. Special thanks go to Dr. Chih-Ming Hung at TI and Dr. Brian A. Floyd at IB M for their support on chip design and fabrication. I am also thank ful for those following peoples who greatly helped my measurements: Dr. Daniel J. Arenas, Dimitrios Koukis, Dr. Jung-sik Hwang, Professor Stephen Hill, Changhy un Koo, Saiti Datta, Professor Elliott R. Brown, Jonathan Suen, Zachary D. Taylor, Dr. Vess elin Vassilev, Al Ogden. I am greatly indebted to my family for their endless love, caring, and encouragement. Last but foremost, I would like to thank God who give s me wisdom and strength to complete this dissertation.

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5 TABLE OF CONTENTS page ACKNOWLEDG MENTS..................................................................................................4LIST OF TABLES............................................................................................................7LIST OF FI GURES..........................................................................................................8ABSTRACT ...................................................................................................................12CHAPTER 1 INTRODUC TION....................................................................................................141.1Overview of Sub-te rahertz Te chnology ..........................................................141.2Sub-terahertz Systems...................................................................................151.3Sub-terahertz Devices and Integrated Circuits in CMOS Technology............181.3.1Sub-Terahertz CMOS Transis tors.......................................................181.3.2Terahertz Schottky Barrier Dio de in CMOS Technology.....................201.3.3Sub-terahertz CMOS In tegrated Cir cuits.............................................211.4Organization of t he Dissertat ion.....................................................................232 CMOS SUB-TERAHERTZ DEVICES FO R FREQUENCY MULTIPLICATION.......252.1Motivati on.......................................................................................................252.2Schottky Diode in CM OS Techno logy............................................................252.3Anti-Parallel Schottky Diode Pa ir in CMOS Technology.................................272.3.1Device Stru cture..................................................................................302.3.2DC Measurem ents...............................................................................332.3.3RF Measur ements...............................................................................332.4Symmetric Varactor in CMOS Tec hnology .....................................................352.4.1Device Stru cture..................................................................................382.4.2Measurements and Results.................................................................412.5Summary ........................................................................................................493 CMOS SUB-TERAHERTZ DEVICES UNDER EXTREME ENVIRONMENTS........503.1Motivati on.......................................................................................................503.2Experiment Ov erview .....................................................................................523.3Experimental Results.....................................................................................563.3.1Low Temperature Dependence of CMOS de vices..............................563.3.2High Field Dependence of CMOS Devices at Liquid-Helium Temperat ure........................................................................................653.4Summary ........................................................................................................664 CMOS SUB-TERAHERTZ FR EQUENCY MULT IPLIER .........................................70

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6 4.1Motivati on.......................................................................................................704.2150-GHz Frequency Triple r Using CAPDP...................................................704.2.1Design Consi deratio ns........................................................................704.2.2Measurement Result s..........................................................................744.3Summary ........................................................................................................805 CMOS SUB-TERAHERTZ FREQUENCY DI VIDER...............................................815.1Motivati on.......................................................................................................815.2194-GHz Injection Lock ed Frequency Divider ................................................815.2.1Design Consi deratio ns........................................................................815.2.2Measurement Result s..........................................................................915.3Summary ........................................................................................................926 CMOS SUB-TERAHER TZ FREQUENC Y SOURCE ..............................................966.1Motivati on.......................................................................................................966.2553-GHz Quadruple-push Oscilla tor..............................................................966.2.1Design Consi deratio ns........................................................................966.2.2Measurement Re sults........................................................................1056.3Summary ......................................................................................................1127 SUMMARY AND FUT URE WORK S.....................................................................1137.1Summary ......................................................................................................1137.2Future Works................................................................................................115APPENDIX FTIR MEASUREMENT PARAMETER S......................................................................117LIST OF REFE RENCES.............................................................................................118BIOGRAPHICAL SKETCH ..........................................................................................126

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7 LIST OF TABLES Table page 2-1 Performance Comparis on...................................................................................473-1 Summary of NMOS test stru ctures.....................................................................553-2 Summary of diode test stru ctures.......................................................................553-3 Summary of Van der Pauw and Kelvin test structur es........................................553-4 Measured ideality factor of p-n ju nction diode (PND) and Schottky barrier diode (SBD )........................................................................................................654-1 Performance comparis on...................................................................................805-1 Transistor size s (L = 40 nm)...............................................................................865-2 Core inductor desi gn parameters (m)...............................................................865-3 Tuning varactor wid ths (L = 0. 11 m).................................................................875-4 Transmission line lengths (m)...........................................................................875-5 194-GHz 4 frequency divider summary...........................................................926-1 Performance summary of subTHz quadruple-push oscillator..........................111

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8 LIST OF FIGURES Figure page 1-1 Terahertz gap [11] ..............................................................................................161-2 Sub-THz wave applicat ions [12], [13].................................................................161-3 (a) Conventional optoelectronic s pectrometer [14]. (b) Conventional electronic spectrom eter [ 15]...............................................................................171-4 Conceptual diagram of the sub-THz on-chip spectromet er in CMOS.................191-5 Sub-THz signal generator...................................................................................191-6 Projected performanc e requirements of NMOS transistors from 2008 International Road Map for Semic onductors [5] and the data from the literatur e.............................................................................................................202-1 (a) Shallow trench separated Schottky barrier diode (STS SBD). (b) Polysilicon gate separated Schott ky barrier diode (PGS SBD)...........................262-2 Small signal equivalent circuit model of an n-type Schottky barrier diode..........282-3 Simulated n-well resistanc e of unit-cell STS SBD ..............................................282-4 Simulated n-well resistanc e of unit-cell PGS SBD ..............................................292-5 Scaling of STI thickness (tSTI) and gate length (Lg).............................................292-6 Simplified nonlinear I-V c haracteristic of APD P..................................................312-7 Schematic cross-section and confi guration of an n-APDP ((a) and (c)) and the proposed C-APDP ((b) and (d )), respecti vely...............................................322-8 (a) Measured I-V characteristics of a C-APDP and SBDs. (b) Measured I-V and current mismatch factor ( ) of a C-APDP around zero bias voltage............342-9 (a) Test setup for harmonic power measurements. (b) The second and third harmonic powers generated by a C-APDP and an n-SB D.................................362-10 Typical C-V characteristic of HBV diode vara ctor [39]........................................392-11 (a) Cross-section and (b) schematic of SVAR. (c) C-V characteristics of pVAR, n-VAR, and SVAR .....................................................................................402-12 Top view of unitcell MOS vara ctor.....................................................................422-13 Measured C-V characteri stics of (a) MOS varactors and (b) MOS SVAR..........43

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9 2-14 Test setup for harmoni c power measur ements...................................................432-15 RF output power versus PIN at VNW = 2.8 V........................................................462-16 Third order harmonic output powers versus VNW................................................462-17 Fifth order harmonic output power versus VNW...................................................482-18 SVAR operation conditions for di fferent n-well bias voltages (VNW)....................483-1 Basic principle of electron paramagnetic resonance (EPR) spectroscopy..........513-2 Cryostat with a superconducting magnet (Quantum Design PPMS) for millimeter-wave EPR spec troscopy [53].............................................................513-3 Van der Pauw (a) and Kelv in (b) test structur e...................................................533-4 Measurement setup............................................................................................543-5 Test chip mounted on a sample puck.................................................................543-6 Two field orientations for the field dependence measurem ents..........................573-7 (a) NMOS drain current (ID) versus drain voltage (VDS) and (b) drain current versus gate voltage at diffe rent temper atures....................................................583-8 NMOS drain current versus temp erature............................................................583-9 (a) NMOS Transconductance (gm) versus gate voltage at varying temperatures. (b) Maximum transconductance (gm_max) versus temperature.....603-10 NMOS threshold voltage (Vt) versus temperature (VDS = 50 mV).......................613-11 Effective mobility versus tem perature.................................................................613-12 (a) Sheet resistance versus temperat ure. (b) Normalized sheet resistance versus tem peratur e.............................................................................................633-13 Contact resistance ve rsus temper ature..............................................................643-14 I-V characteristics of p-n junction diode (PND) Schottky barrier diode (SBD) at varying tem peratures ......................................................................................643-15 Normalized drain current of NMOS versus m agnetic fi eld..................................673-16 Normalized maximum transconduct ance versus magnet ic fiel d.........................673-17 Normalized threshold volt age versus magnet ic fiel d...........................................68

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10 3-18 Normalized effective mobility of NMOS versus m agnetic fi eld............................683-19 Cyclotron motion of electrons in the channel of NMOS......................................694-1 Operation principle of frequency mult iplier.........................................................724-2 Frequency triple r schemat ic................................................................................724-3 Cross-section (a) and la yout (b) of C-APD P.......................................................734-4 Measured and simulated I-V char acteristic of the C-APD P................................734-5 Cross-secti on of GC PW.....................................................................................754-6 Top view of t he bandpass filt er...........................................................................754-7 Die photograph of t he frequency tr ipler..............................................................754-8 Measured and simula ted S-param eters..............................................................764-9 Measured output spectrum (PIN = 11 dBm at 50 GHz).......................................764-10 On-wafer test setup for output power m easurement s.........................................784-11 Measured conversion lo ss (CL) and output power (POUT) versus output frequency. ...........................................................................................................794-12 Measured and simulated conver sion loss (CL) and output power (POUT) at 150 GHz versus input power (PIN)......................................................................795-1 Diagram of 194-GHz frequency divider with an input sig nal generator...............825-2 Schematic of 194-GHz input signal generator ....................................................825-3 Schematic of 194-GHz 4 frequency di vider.....................................................845-4 Core inductor of DIV1 (L3/L4)..............................................................................845-5 Floating dummy fills in t he core inductor of DIV1................................................855-6 Cross-secti on of GC PW.....................................................................................855-7 Simulated input sensitivity cu rves of the fr equency divi der.................................885-8 Die photograph of t he frequency divider with t he signal gener ator.....................885-9 Test board photograph .......................................................................................895-10 On-wafer test setup for the frequency divider.....................................................90

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11 5-11 Frequency tuning ranges of DIV1 and DIV2 versus t uning volt ages...................905-12 Measured tuning range of SG, DIV1, and DIV2 ..................................................935-13 Measured locking range of the frequency divider...............................................935-14 Measured phase noise of (a) the free-r unning and (b) injection locked divider..945-15 Measured spectrum of the in jection pulled fr equency divi der.............................956-1 (a) Simulated frequency response of Gmax and |h21|. (b) Simulated fmax and ft versus Vg............................................................................................................976-2 Simplified linear model of a quadrature o scillator ...............................................996-3 Schematic of quadruple-push oscillato r schematic with an on-chip antenna......996-4 Simulated current wavefo rms in the o scillator. .................................................1006-5 Quadruple-push operation. ...............................................................................1006-6 Simulated normalized output power (POUT/POUT(m0)) and frequency (fOUT) versus m (WCPL/WC).........................................................................................1026-7 Simulated return loss of the onchip microstrip patch ant enna.........................1026-8 Simulated peak gain and efficiency of the microstrip patch antenna for varying fr equency............................................................................................. 1036-9 Simulated gain patte rn of the antenna. .............................................................1036-10 Quadruple-push oscilla tor die phot ograph........................................................ 1046-11 Layout of interconnects between the core and coupling tr ansistors.................1046-12 Test board photograph. ....................................................................................1066-13 FTIR setup for the output spectrum meas urement...........................................1076-14 FTIR spectrum of a Mercury arc la mp in the atmospher e and vacuum............1096-15 Measured spectrum of the radiated power. ......................................................1096-16 Output power meas urement setup...................................................................1106-17 Measured radiated power (PRAD) and output frequency (fOUT) versus bias current. .............................................................................................................111

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12 Abstract of Dissertation Pr esented to the Graduate School of the University of Florida in Partial Fulf illment of the Requirements for t he Degree of Doctor of Philosophy SUB-TERAHERTZ SIGNAL GENERATION IN CMOS By Dongha Shim May 2011 Chair: Kenneth K. O Major: Electrical and Computer Engineering This dissertation investigates the feas ibility of sub-teraher tz (sub-THz) signal generation using CMOS (Complementary Meta l Oxide Semiconductor) technology. The sub-THz portion of spectrum has remarkable pr operties especially suitable for sensing, imaging, and communication ap plications. The recent progress of high-frequency capability for CMOS has made it possible to consider the process as a new means to overcome the limitations of cost and integr ation level of conventional sub-terahertz systems. Two novel non-linear devices, complementar y anti-parallel diode pair (C-APDP) and symmetric varactor (SVAR), were implem ented in 130-nm digital CMOS process for sub-THz frequency multiplier applications The C-APDP employs both n-type SBD (n-SBD) and p-type SBD (p-SBD) to eliminat e the deleterious effects of substrate parasitics. The device exhibited an extr apolated cutoff frequency of ~470 GHz. The SVAR consists of a pand n-type accumulati on-mode varactor connected in parallel to achieve symmetric C-V characteristics. The device showed the maximum cutoff frequency of ~320 GHz and dynamic cutoff frequency of ~125 GHz. Harmonic power

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13 measurements showed the effective generat ion of odd order harmonic powers while suppressing even order ones. To investigate the feasibi lity of operation of a sub-THz CMOS circuit in harsh spectroscopy environments, CMOS devic es are characterized under the low temperature and high magnetic field. T he temperature dependences of devices including NMOS transistors, and p-n junc tion, and Schottky barrier diodes were measured at 300, 150, 77, and 4.2 K. The fiel d dependence of NMOS transistors is also measured under magnetic fields up to 6 T at the liquid helium temperature. The measured results indicated that CMOS circui ts should have acceptable characteristics in the cryogenic and high fiel d spectroscopy environment. The first sub-THz CMOS frequency trip ler has been demonstrated using a C-APDP. The tripler exhibited ~34-dB mi nimum conversion loss, -24-dBm maximum output power at 150 GHz, and 3-dB output fr equency range of ~10 GHz, which is ~10X wider than that of a 140-GHz CMOS osc illator fabricated in 90-nm CMOS. To demonstrate sub-THz frequency di vision in CMOS, a 194-GHz 4 frequency divider has been implemented in 45-nm logic CMOS technology. Two cascaded 2 ILFD stages are employed to divide ~194-GHz input signal in to ~48.5-GHz. A sub-THz quadruple-push oscillator has been implemented us ing low leakage transistors in 45-nm CMOS. Quasi-optical meas urements showed that the circuit generates 4th harmonic signal at 553 GHz with the pow er level of 220 nW, while suppressing unwanted harmonic signals. These results provide the foundation for the eventual realization of compact and affordable sub-THz systems using CMOS integrated circuits.

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14 CHAPTER 1 INTRODUCTION 1.1 Overview of Sub -terahertz Technology The sub-terahertz (sub-THz) region is typically defined the portion of an electromagnetic spectrum in the frequency range of ~100 GHz to ~1 THz. The waves in this frequency range have remarkable properties especially suitable for sensing, imaging, and communication applic ations [1], [2]. Until recently, however, the frequency region has remained as a part of the last unex plored territory (so-called “THz gap” in Figure 1-1) due to the lack of practical s ources and detectors. With the advances of photonic and electronic component s, this part of spectrum is becoming more accessible and newer applications for imaging, medical, industry, security, and communication are emerging. Sub-THz waves can penetrate through clothi ng, leather, papers, plastic, and many other non-metallic materials. It is a suit able candidate for the detection of hidden weapons including non-metallic ones. Unlike X -rays, sub-THz radiation is non-ionizing, and should be safer for medical imaging and therapy applications. These technologies are more accurate and economical compared to the other scanning methods such as MRI (Magnetic Resonance Imaging), and PET (Positron Emission Tomography). This emerging technology has the potential to re volutionize the way many diseases are diagnosed and cured. Sub-THz wave is also useful for non-destructive and fast inspections for industrial applications including those for pharmaceutical and semiconductor industries. Numerous organic molecules exhibit str ong absorption and dispersion of sub-THz radiation due to rotational and vibrational transitions The ability of sub-THz to probe

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15 intermolecular interactions makes subTHz a unique spectroscopic tool for the measurement of the unique spec tral fingerprints of different chemical and physical forms, permitting them to be imaged, identif ied, and analyzed. The ability has been used to spectrally identify explosives and dangerous chemicals through clothing [2]. This is enabling a new paradigm in t he fight against terrorism and detection of suspicious or controlled substances. The wide bandwidth offered by sub-THz wave links can also be used for short range and high data rate indoor communi cation applications. The sub-THz communications within rooms or buildings sh ould be quite secure and exhibit strong interference immunity. The beamlike proper ties of sub-THz wave can protect communication signals from in tercept. Battlefield communica tions among soldiers might be interesting if sub-THz communication eq uipments can be made sufficiently compact, light, and low-power consuming. Sub-THz wave applications are summarized in Figure 1-2. 1.2 Sub-terahertz Systems As mentioned, spectroscopy is an impor tant sub-THz applicat ion. Existing subTHz spectroscopy systems rely on comp lex assemblies of optical components or discrete electronic components where the elec tronic devices are coupled together using a bulky waveguide assembly as shown in Figur e 1-3. For this reason, the systems cost many tens to several hundreds of thousands of dollars. The use of CMOS technology to implement highly integrated sub-THz systems can radically lower the cost and size by eliminating the costly optical and discrete electronic components. The Integration of transmitters, detectors, and on-chip antennas [3], as well as, baseband digital signal processing (DSP) circuits, in CMOS should al low single-chip realization of compact and

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16 Optics Electronics Terahertz Gap Figure 1-1. Terahertz gap [11]. Security Medical Astronomy Spectroscopy Industry Communication Imaging Sensing Communication SubTHz Figure 1-2. Sub-THz wave applications [12], [13].

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17 (a) Circulator Down Converter Up Converter Isolator Waveguide Frequency Divider Oscillator PLL Coupler (b) Figure 1-3. (a) Conventional optoelectroni c spectrometer [14]. (b) Conventional electronic spectrometer [15].

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18 affordable THz systems. This should provid e the engine that c an drive the emergence of moderate-to-high volume and low-to -moderate cost sub-THz applications. A conceptual diagram of propos ed frequency domain sub-THz CMOS spectrometer is shown in Figure 1-4. A transmitter consists of a tunable sub-THz frequency generator and an on-chip antenna. A receiver includes an on-chip antenna, a detector or a mixer followed by a low noise amplifier/filter and an A/D converter (ADC). Figure 1-5 shows a schematic of the sub-THz frequency generat or that can be used in the spectrometer. A high s pectral purity sub-THz signa l can be generated by a phase locked loop (PLL) followed by a sub-TH z frequency multiplier. A sub-THz frequency divider, phase frequency detector (PFD), and lo w pass filter (LPF) comprise the phase locked loop (PLL). 1.3 Sub-terahertz Devices and Integrat ed Circuits in CMOS Technology 1.3.1 Sub-Terahertz CMOS Transistors Traditionally, digital CMOS technologies have not been seriously considered for sub-THz frequency applications due to it s limited maximum operation frequency. The scaling of CMOS technology ha s resulted transistors in production which have cutoff frequency (fT) and unity maximum available power gain frequency (fmax) of 360 and 450 GHz [4]. Figure 1-6 shows the projected requirements of fT’s and fmax’s for MOS, SiGe Hetero-Junction bipolar (HBT), and III-V based transistors in current technologies. The data have been extracted from the 2008 Inter national Roadmap for Semiconductors [5]. The roadmap projects that the required performances of MOS transistors in manufacturing will surpass those of production SiGe HBTs and III-V based transistors despite the poorer intrinsic electronic properties of silicon. By year 2013, the projected NMOS unity power gain frequency (fmax) requirement is ~510 GHz. Such transistors

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19 Sample On-Chip Antenna/ Resonator Output Spectrum t f0f1f2f3 f4…Output Spectrum t f0f1f2f3 f4… Schottky Diode Harmonic Mixer Input Spectrumt f0f1f2f3 f4… Input Spectrumt f0f1f2f3 f4… Low Pass Amplifier Spectrum Display ADC Sub-THz Signal Generator CMOS Technology Figure 1-4. Conceptual diagram of the s ub-THz on-chip spectrometer in CMOS. PFD LPF N REF X MSub-THz Signal Source Sub-THz Freq Multiplier Sub-THz Freq DividerfREFfOUT(N M fREF)Phase Freq Detector Reference Low Pass Filter Figure 1-5. Sub-TH z signal generator.

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20 will provide greater flexibi lity to implement and improve circuits and systems operating at sub-THz frequencies. However, there has been a concern whet her the CMOS technology scaling can continue. The reports of a bulk transis tor of a 65-nm technology [4] with fmax of 420 GHz in 2006, and an SOI transistor of a 45-nm process with fT of 450 GHz [6] in 2007 suggest that the industry is keeping up with the ITRS. 1.3.2 Terahertz Schottky Barrier Diode in CMOS Technology In the near term, at frequencies higher than ~400 GHz, it will be difficult to achieve amplification using NMOS transis tors. A way to deal with this is to use passive detectors and frequency multipliers as routinely done in the sub-millimeter and THz communities Figure 1-6. Projected perfo rmance requirements of NMOS transistors from 2008 International Road Map for Semic onductors [5] and the data from the literature.

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21 [7]. Schottky barrier diodes (SBDs) are a promising candidate due to their high operating frequencies and a low forward-voltage dr op. The carrier transport in Schottky diodes relies on the majority carrier conduction, in contrast to that in p-n junction diodes where the carrier transport involves both the minority and majority carriers. Since there are no minority carrier storage effects, SBDs are potentially capable of operation up to the frequencies approaching the reciprocal of dielectric relaxation time of the semiconductor crystal [8]. However the ex trinsic series resistance and junction capacitance typically limit the high frequency c apability before reaching the limit set by the dielectric relaxation. Schottky diodes with cutoff frequency great er than 1 THz have been demonstrated in 130-nm CMOS [9] and bipolar-CMOS (B iCMOS) technologies [ 10]. In the CMOS implementation, the high cutoff frequency ha s been achieved by exploiting the device scaling. The continued technolog y scaling provides opportuniti es to increase the diode cutoff frequency up to several THz [9]. This has led to the exploration of diode detectors [16], mixers, and frequency multipliers [17] fabricated in CMOS technology, which can operate up to 1 THz. 1.3.3 Sub-terahertz CMOS Integrated Circuits The viability of sub-THz operation of CMOS circuits has been shown by demonstration of several components includi ng oscillators, detectors, and phase-locked loops. To overcome the limitation of maximum oscillation frequency (fmax) of CMOS transistors, push-push techniques have been adopted to generate sub-THz signals. Huang et al. [19] and Cao et al. [20] have utiliz ed this technique to realize oscillators at 131 GHz and 192 GHz, respectively in 130-nm CMOS technology. Seok, et al. have reported the generation of 410 GHz signal in 45nm CMOS process [21]. The output

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22 frequency of 410 GHz is the highest frequency for signals generated using transistors in any technology, including those based on compound semiconductors. The operation frequency can be increased further above fmax by linearly superimposing quadruple phase shifted fundamental signals at one four th of the output fr equency. A 324-GHz frequency generator in 90-nm CMOS proc ess has been implemented using the technique [22]. To examine the feasibilit y of a sub-THz CMOS detector, a 182-GHz Schottky diode detector was implemented in 130-nm foundr y CMOS [16]. The detector test signal was generated on-chip by modulating the bias current of a push-push VCO. The detector consists of a ~180-GHz RF matchi ng network, a Schottky ba rrier diode, a low pass filter with ~10-GHz corner frequency, and an amplifier for driving a 50load. THz signals can also be detected by exciting plas ma waves in the inversion layer of MOS transistors [23]. An important advantage of plasma-wave THz detection is that its operating frequency can exceed the frequency at which the transistor current gain is unity. 780-GHz signals were detected by an NMOS plasma-wave detector [24]. The responsivity is greater than 200 V/W. The minimum power of a signal with 1-Hz bandwidth that can be detected is around 100 pW for a detector using NMOS transistors fabricat ed in 130-nm CMOS. Generation of free running high frequency signals by itself is not sufficient. The signal must be stabilized using a phased lock ed loop (PLL). A fully integrated PLL tunable from 45.9 to 50.5 GHz fabricated in 130-nm CMOS, which also outputs the second order harmonic at frequencie s between 91.8 and 101 GHz, has been demonstrated in a 130-nm logic CMOS process [25]. The circuit utilizes an injection-

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23 locked frequency divider ( 2) (ILFD) followed by a 512 static frequency divider to achieve high-speed frequency division up to 50.5 GHz. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies wit h the output power level around -10 dBm. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carri er is 63.5, 72, and 99 dBc/Hz, respectively. Lee et al. has r eported a 75-GHz phase-locked loop (PLL) fabricated in 90-nm CMOS technology [26 ]. The circuit incorporates three-quarter wavelength oscillators to achieve the high-frequency operation and a novel phasefrequency detector (PFD) based on SSB mixers to suppress the reference feedthrough. The PLL demonstrates an operation range of 320 MHz and reference sidebands of less than 72 dBc while consuming 88 mW from a 1.45-V supply. The operation frequency of PLL could be pushed up further by using multip le ILFDs in a frequency divider chain. A 96-GHz PLL is fabricated in a 65nm CMOS process with a low pow er consumption of 43.7 mW from a 1.2 V suppl y. The PLL locks from 95.1 to 96.5 GHz [27]. The demonstration of key components together with the continued scaling of CMOS suggests the possibility for affordable CMOS THz systems in the near future. 1.4 Organization of the Dissertation The solid blocks of the sub-THz generator in Figure 1-5 are demonstrated in the dissertation. Two novel CMOS devices, co mplementary anti-parallel diode pair (C-APDP) and symmetric varactor (SVAR), for sub-THz frequency multiplication are demonstrated in Chapter 2. Non-linear behaviors of the devices are characterized by DC, RF, and harmonic power measurements. C hapter 3 discusses the characterization of CMOS devices in a magnet cryostat to inve stigate the feasibility of the operation of sub-THz CMOS circuits in an extreme spec troscopy environment. The low temperature

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24 and high field dependences of devices are characterized down 4.2 K and magnetic fields up to 6 T. A 150-GHz frequency triple r implemented using a C-APDP in a 130-nm CMOS technology is presented in C hapter 4. In Chapter 5, 194-GHz 4 frequency divider is demonstrated in 45-nm logic CMOS using two cascaded injection locked frequency dividers. Chapter 6 presents 553-GH z quadruple-push oscill ator implemented in 45-nm CMOS technology. The oscillat or increases both the radiated power and output frequency over the 410 GHz signal generation circuit [21]. Finally, the dissertation is summarized and future works are suggested in Chapter 7.

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25 CHAPTER 2 CMOS SUB-TERAHERTZ DEVICES FOR FREQUENCY MULTIPLICATION 2.1 Motivation Two novel non-linear devices, complementar y anti-parallel diode pairs (C-APDP) and symmetric varactor (SVAR), were impl emented in a 130-nm digital CMOS process for sub-THz frequency multiplier applications The C-APDP employs both n-type SBD (n-SBD) and p-type SBD (p-SBD) to eliminate t he deleterious effects from the substrate parasitics. The device exhibited an extr apolated cutoff frequency of ~470 GHz. The SVAR consists of a pand n-type accumulati on-mode varactor connected in parallel to achieve symmetric C-V characteristics. The device showed the maximum cutoff frequency of ~320 GHz and dynamic cutoff frequency of ~125 GHz. Harmonic power measurements showed the effective generat ion of odd order harmonic powers while suppressing even order ones. 2.2 Schottky Diode in CMOS Technology Recently, two SBDs with a different c onfiguration have been reported in logic CMOS without any process modifications [ 18]. The cross-section of shallow trench separated (STS) and poly-gate separated (PGS) SBD is shown in Figures 2-1(a) and (b), respectively. The Schottky contact is fo rmed on diffusion regions where there are no source/drain implants. An ohmic contact placed on an n+ implanted n-well region form a cathode. The cathode and anode of STS and PGS SBD is separated by a shallow trench and polysilicon gate ring, respectively. A CoSi2-silicon Schottky junction has been employed in a 130-nm CMOS process fo r both SBDs [9], [18]. Figure 2-2 shows a small signal equivalent circ uit of the n-type SBDs. T he measured cutoff frequency (fc = 1/2 RsCj0) of STS and PGS SBD is ~1.5 and ~2 THz, respectively. To minimize

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26 STI STIn+ILD n+p-substrate ILD ILD ILD n+n+ n-well STI STI ILD Schottky Junction STI Separator Cathode AnodewSTI tSTI LjtNW Current Contact (a) STI STIn+ILD Cathode Anoden+p-substrate ILD ILD ILD ILD n+n+ n-well Schottky Junction Poly-Si Separator Lg Current Lj Contact (b) Figure 2-1. (a) Shallow trench separated Schottky barrier diode (STS SBD). (b) Polysilicon gate separated Schott ky barrier diode (PGS SBD).

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27 Rs at given Cj0, the diode is formed by minimum area Schottky diode cells connected in parallel. The unit-cell area of STS and PGS SBD is 0.320.32 and 0.40.4 m2, respectively. The cutoff frequencies of ~2 THz should allow fabr ication of diode detectors [16], mixers, and frequency multiplie rs [17] operating at 1 THz and higher in CMOS. Measurements show STS SBD has ~2-3X higher series resistance (RS) than PGS SBD [9]. The n-well resistance of SBDs is responsible for a large portion of RS [9]. HFSS simulations have been performed to underst and the cause of the difference in the resistance. Figure 2-3 shows the unit-cell n-well resistance (rNW) of STS SBD for varying thickness (tSTI) and width (wSTI) of the STI-ring. The simulated rNW shows strong dependence on tSTI while slightly increasing with wSTI. Figure 2-4 shows the simulated rNW of PGS SBD for a varying gate length (Lg). A smaller Lg results in shorter current path through the n-well to reduce rNW as expected. The simulated rNW is 2.7 and 0.44 k for STS and PGS SBD, respectively for re al design parameters. The smaller rNW of PGS SBD would significantly reduce RS and improve the cutoff frequency. Figure 2-5 shows scaling of gate length (Lg) and STI thickness for different technology nodes in bulk CMOS. Unlike the gate length, STI thickne ss does not scale down with technology. For this reason, the cutoff frequency of PGS SBD should scale better with technology scaling due to the elim ination of n-well r egion surrounded by the STI-ring in STS SBD. 2.3 Anti-Parallel Schottky Diode Pair in CMOS Technology Anti-parallel diode pairs (APDPs) have been a critical component in circuits for millimeter and sub-millimeter wave applicat ions including frequency multipliers and harmonic mixers [28]-[31]. A si mplified nonlinear I-V characteri stic of APDP is shown in Figure 2-6. To implement a high frequency APDP Schottky barrier diodes (SBDs) have

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28 Figure 2-2. Small signal equivalent circuit model of an n-type Schottky barrier diode. wSTI[m] tSTI[m] rNW[k ]Lj= 0.32 m tNW= 1.5 m NW= 1750 S/m Design: rNW= 2.7 k @ tSTI= 0.35 m,wSTI= 0.22 mHFSS Model Anode Cathod N-well STI Ring Figure 2-3. Simulated n-well re sistance of unit-cell STS SBD.

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29 0.3 0.4 0.5 0.6 00.20.40.60.8Lj= 0.4 m tNW= 1.5 m NW= 1750 S/mDesign: rNW= 0.44 k @ Lg= 0.12 m rNW[k ]Lg[ m] HFSS model Anode Cathod N-well Poly Ring Figure 2-4. Simulated n-well re sistance of unit-cell PGS SBD. 0.0 0.1 0.2 0.3 0.4 0.5 306090120150 0 50 100 150 t_STI LgTechnology [nm]tSTI[m] Lg[nm] tSTILg Figure 2-5. Scaling of STI thickness (tSTI) and gate length (Lg).

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30 been widely used due to their high switching s peed and lower forward voltage drop [32]. SBDs have often been fabricated with highly optimized processes on GaAs, InP, and SiC substrates [33], [34]. Two types of SBDs, nand p-type, depending on the doping type of semiconductor are possible in CMOS. N-type SBDs (n-SBD s) have been used almost exclusively for APDPs because electron mobility is higher in most of the widely studied semiconductors. However, CMOS n-SBDs are not well suited for millimet er-wave APDPs due to the associated parasitic n-well-to-substrat e junction diode and its capacitance and resistance in Figure 2-2. To mitigate this, a complementary APDP (C-APDP) using both nand p-SBD of CMOS is proposed to overco me the limitation of APDPs using only n-SBDs (n-APDPs). The C-APDPs fabricated in a foundry 0. 13-m logic CMOS process exhibit a third order harmonic generation capability that is ~25 dB higher than that of an n-SBD. 2.3.1 Device Structure Figures 2-7(a) and (c) show the cross-se ction and configuration of an n-APDP that can be fabricated in CMOS. The n-well-to-substrate capacitance CSUB and the substrate resistances RSUB can significantly degrade the harmoni c conversion characteristics of APDP especially at millimeter and sub -millimeter wave frequencies due to the attenuation of a fundamental driving signal as well as generated harmonics. This degradation due to CSUB and RSUB can be avoided by replacing the n-SBD2 responsible for the parasitics with a p-SBD. The cutoff fr equency of p-SBDs is ~80% of that for n-SBDs [9], and use of a p-SBD in C-APDP s hould not significantly degrade the highfrequency performance. The cross-section and configuration of C-APDP are shown in Figure 2-7(b) and (d), respectively. Each nand p-type SBD of C-APD P is composed of

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31 V I VIN(t)IIN(t) V I VIN(t)IIN(t) Figure 2-6. Simplified nonlinear I-V characteristic of APDP. (a) Figure 2-7. Schematic cross-section and co nfiguration of an n-APDP ((a) and (c)) and the proposed C-APDP ((b) and (d )), respectively. (Figure continues in the next page.)

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32 (b) (c) (d) Figure 2-7. Schematic cross-section and co nfiguration of an n-APDP ((a) and (c)) and the proposed C-APDP ((b) and (d)), respectively.

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33 8 parallel cells. The area of unit Schottky di ode cell is set to the minimum contacted diffusion area of 0.320.32-m2 allowed by the process. The other design and layout details of the Schottky diodes are similar to that described in [9] except for the well overlap. 2.3.2 DC Measurements Figure 2-8(a) shows measured I-V (current -voltage) characteristics of a C-APDP, and 8-cell nand p-type SBDs. For both types of the SBDs, the ideality factor is about 1.1, and the reverse leakage currents are less than 0.5 A at 2-V reverse bias. The n-SBD has a turn-on voltage of 0.35 V, which is slightly higher than the absolute value of turn-on voltage of 0.3 V fo r the p-SBD. Figure 2-8(b) s hows I-V and current mismatch around zero bias voltage. The current mismatch factor ( in Figure 2-8(b)) is defined as the difference to sum ratio of the magnitude of cu rrents at positive and negative voltage, VC-APDP and –VC-APDP. The C-APDP has a good anti-sy mmetric characteristic with modest current mismatch. An ideal APDP sh ould have zero current mismatch. The C-APDP has current mismat ch less than 10%. This mismatch can be reduced by optimizing the ratios of nand p-SBD sizes. 2.3.3 RF Measurements The one-port S-parameter s of C-APDP were measured between 15 and 20 GHz using an 8510C vector network analyzer [9]. The measured capacitances are around 7.3 fF, and the resistances increase from ~40 to ~55 over the frequency range with an average of 46 The cutoff frequency of CAPDP extrapolated from the measurements [36], [37] is greater than 470 GHz, which should be sufficient for millimeter-wave applications. This is lower t han ~1 THz expected from [9] due to the use of the logic instead of the mixed-mode tec hnology and the smaller well overlaps for

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34 10-210-410-610-810-10-2-1012 C-APDP p-SBD n-SBDVDIODE[V]Absolute Current [A] (a) 10 -5 0 5 10 -0.3-0.2-0.100.10.20.3 -20 -10 0 10 20 Current Current Mismatch ) ( ) ( ) ( ) ( ) (APDP C APDP C APDP C APDP C APDP CV I V I V I V I V VC-APDP[V]Current (I) [A] Current Mismatch ( ) [%] ) )APDP C APDP C APDP C APDP C APDP CV I( ) I(V V I( ) I(V ) (V (b) Figure 2-8. (a) Measured I-V characteristi cs of a C-APDP and SBDs. (b) Measured I-V and current mismatch factor ( ) of a C-APDP around zero bias voltage.

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35 C-APDP [9]. The n-APDP has an extrapolat ed cutoff frequency around 120 GHz with measured CSUB of 41 fF and RSUB of 33 [38]. To evaluate the harmonic generation of C-APDPs, the second and third harmonic powers generated from a C-APD P and 16-cell n-SBD are compared at zero bias. As mentioned the C-APDP utilizes 8-cell nand p-SBDs. Figure 2-9(a) shows the measurement setup. Due to the availability of com ponents and instruments, the harmonic generation was evaluated using a 900-MHz fundamental signal from an Agilent 4421B signal generat or. The generated harmonic pow er was measured using an Agilent 8563E spectrum analyzer. The input and output are isolated using a diplexer OML DPL.26 with a low (LPF) and high pass filter (HPF) Figure 2-9(b) shows the measured power levels of second and third harmonics generated by the C-APDP and n-SBD ve rsus input power levels (Pin). As expected from its I-V characteristics, t he C-APDP generates more than 25 dB higher order third harmonic power (Pout) than the n-SBD. An ideal APDP is not expected to generate even order harmonics. However, the second harmonic powers are observed due to the mismatch between nand p-SBDs discussed earlier. A C-APDP using PGS SBDs is also fabricated. The structure exhibits cu t off frequency of ~660 GHz. Details of those structures are present ed in section 4.2 on a C-APDP frequency tripler. 2.4 Symmetric Varactor in CMOS Technology Symmetric varactors (SVARs) have been a critical component for millimeterand sub-millimeter wave frequency multiplicati on [39]-[41]. The design of a frequency multiplier is simplified using an SVAR si nce only odd harmonics of the pump signal are generated, which makes even order harmonic idler circuits unnecessary [39]-[41].

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36 (a) -70 -50 -30 -10 -15-10-50510 2fo, C-APDP 3fo, C-APDP 2fo, n-SBD 3fo, n-SBD 2f0, C-APDP 3f0, C-APDP 2f0, n-SBD 3f0, n-SBDPIN[dBm] f0= 900 MHzPOUT[dBm] (b) Figure 2-9. (a) Test setup for harmonic pow er measurements. (b) The second and third harmonic powers generated by a C-APDP and an n-SBD.

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37 SVARs have often been implemented with hi ghly optimized III-V devices such as heterostructure barrier varact or (HBV) [39], [40] and anti-series Schottky diode varactor (ASV) [41]. An accumulation-mode MOS (A-MOS) varact or has been extensively employed as a tuning element especially in an LC-tank of a CMOS voltage controlled oscillator (VCO). Increasing Q-factor of this vara ctor structure has received a great deal of attention [43][45]. Recently, an A-MOS vara ctor with a cutoff frequency (fc = 1/2 RsCvar) greater than 2 THz has been reported in a foundry CMOS process [45]. SVARs in CMOS technology have been utiliz ed as a differential tuning element for common-mode noise rejection in VCOs [46] [47]. However, harmonic generation using an SVAR has not been investigated. This se ction demonstrates an SVAR formed with complementary A-MOS varactors can be used to generate third and fifth order harmonics while suppressing even order generat ion. The device was fabricated in the UMC 130-nm logic CMOS without any proce ss modification. The varistor mode operation of the C-APDP leads significant loss and could limit the efficiency of frequency triplers. The use of MOS varactor s for frequency multiplie r applications is investigated because reactive multipliers ha ve a higher theoretical maximum efficiency of 100%. This make the MOS varactor di odes potentially better suited for frequency multiplier applications. Figure 2-10 shows a typical C-V characteri stic of HBV symmetric varactor (SVAR) [48]. The symmetric varactor has symme tric capacitance-voltage (C-V) and antisymmetric current-voltage (I-V) characteri stics [39]-[41]. Frequency multiplication or harmonic generation occurs due to the nonli near voltage dependent capacitance [49].

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38 Mathematically, the C-V characteristic can be expressed as a power series given by (2.1). The bias point is normally set to zero and only even order terms remain because of the symmetry. With the current given in (2.2), only the odd order harmonic reactive currents are generated in the device when driven by a sinusoidal voltage source. Once again, the absence of even order harmonic cu rrents can substantially simplify the design of input and output f iltering/matching networks in frequency multipliers. t) cos( V V0 0 (2.1) 6 6 4 4 2 2 0 6 0 V 6 V 6 4 0 V 4 V 4 2 0 V 2 V 2 V V V C V C V C C V V C V V C V V C (0) C V) ( C (2.2) dt dV(t) (t) C dt dt dV(t) (V(t)) C dt d (V)dV C dt d at dQ(t) i(t)V t V V V (2.3) t 5 sin A t 3 sin A t sin A t sin V ) t cos V C t cos V C (C dt dV(t) ) V C V C (C i(t)0 5 0 3 0 1 0 0 0 0 4 4 0 4 0 2 2 0 2 0 4 4 2 2 0 (2.4) where ... V C 16 1 A ... V C 16 3 V C 4 1 A ... V C 8 1 V C 4 1 V C A0 5 0 4 5 0 5 0 4 0 3 0 2 3 0 5 0 4 0 3 0 2 0 0 0 1 (2.5) 2.4.1 Device Structure Figure 2-11(a) shows the cross-section of proposed SVAR in CMOS. A p-type (pVAR) and n-type A-MOS varactor (n-VAR) are connected in parallel to form the SVAR. An on-chip bypass capacitor (CBP) and bias resistor (RBIAS) are used to bias the n-well of

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39 CVVIN V 0 Cmin-VmaxVmaxQ( V) Cmax Figure 2-10. Typical C-V characteri stic of HBV diode varactor [39]. (a) Figure 2-11. (a) Cross-section and (b) schemat ic of SVAR. (c) C-V characteristics of pVAR, n-VAR, and SVAR. (Figure continues in the next page.)

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40 (b) (c) Figure 2-11. (a) Cross-section and (b) schemat ic of SVAR. (c) C-V characteristics of pVAR, n-VAR, and SVAR.

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41 n-VAR. The schematic of the SVAR is show n in Figure 2-11(b). The p-VAR and n-VAR have a monotonic transition in the C-V curves when the gate voltage (VG) is near 0 V and the n-well bias voltage (VNW), respectively (Figure 211(c)). The symmetric C-V curve is realized by combining the C-V cu rves of the pand n-VAR. The C-V curve of the SVAR is symmetric about VG = ~VNW/2, which is DC gate bias of the SVAR (VG_DC). The shape of C-V curves c an be varied by adjusting VNW to shift the C-V curve of n-VAR. 2.4.2 Measurements and Results Test structures for pand n-VAR of the SVA R composed of 12 parallel varactor cells, as well as that for SVR using the nand p-VARs are f abricated. A unit cell varactor has a gate length of 0.18 m and a finger width of 1.2 m as shown in Figure 2-12 [45]. The measured C-V curves of pand nVARs are shown in Figure 2-13(a). The one-port small-signal S-param eters of varactors were measured between 15 and 20 GHz using an 8510C vector network anal yzer [50]. The meas ured tuning range (maximum to minimum capacitance ratio) was 2.6 and 2.4 for the pand n-varactor, respectively. The capacitance mismatch ( in Figure 2-13(a)) of the varactors is less than 4%. The measured breakdo wn voltage of the pand nVAR was greater than 4.8 and 4.4 V, respectively. Figure 2-13(b) shows the measured C-V char acteristics of the SVAR at varying nwell bias voltages. For small VNW (VNW < 1.2 V), the dip in t he C-V becomes deeper with VNW until its bottom approaches the mi nimum capacitance of the SVAR (Cmin), which is the sum of the minimum capacitance of pa nd n-VARs. Further increases of the voltage (VNW > 1.6 V) makes the dip wider wi th flat bottom capacitance of Cmin. The minimum (Cmin) and maximum capacitance (Cmax) of the SVAR at VNW = 2.8 V is 31 and

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42 Diffusion Poly-Si Contact/Via Metal L W L = 0.18 m W = 1.2 m Figure 2-12. Top view of unit-cell MOS varactor. 10 20 30 40 50 -1.0-0.50.00.51.0 VG [V]CVAR [fF]-10 -5 0 5 10Mismatch n-VAR p-VAR Mismatch VG[V] Capacitance [fF] Mismatch ( ) [%] n-VAR ) V ( C ) (V C ) V ( C ) (V C V G VAR n G VAR p G VAR n G VAR p G p-VAR (a) Figure 2-13. Measured C-V c haracteristics of (a) MOS va ractors and (b) MOS SVAR. (Figure continues in the next page.)

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43 30 40 50 60 70 -10123 Vg, VCsvar, fF Vnw=0V Vnw=0.4V Vnw=0.8V Vnw=1.2V Vnw=1.6V Vnw=2.0V Vnw=2.4V Vnw=2.8V VG[V] CSVAR[fF] VNW = 0.0 V VNW= 0.8 V VNW= 1.6 V VNW= 2.4 V VNW = 0.4 V VNW= 1.2 V VNW= 2.0 V VNW= 2.8 V 30 40 50 60 70 -10123 Vg, VCsvar, fF Vnw=0V Vnw=0.4V Vnw=0.8V Vnw=1.2V Vnw=1.6V Vnw=2.0V Vnw=2.4V Vnw=2.8V VG[V] CSVAR[fF] VNW = 0.0 V VNW= 0.8 V VNW= 1.6 V VNW= 2.4 V VNW = 0.4 V VNW= 1.2 V VNW= 2.0 V VNW= 2.8 V (b) Figure 2-13. Measured C-V c haracteristics of (a) MOS va ractors and (b) MOS SVAR. Figure 2-14. Test setup for harmonic power measurements.

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44 53 fF, respectively with the complementary tuning range of 1.7. The maximum cutoff frequency (fc,max = 1/2 RsCmin) is measured to be ~320 GHz with Cmin of 31 fF and series resistance (Rs) of 16 at VG_DC = 1.4 V and VNW =2.8 V. For a varactor multiplier, the maximum conversion efficiency ( ) can be estimated from the empirical expression in (2.4) [51]. and are correlation factors extrac ted from detailed large-signal simulations for a wide range of devices and circuit conditions. The efficiency is related to the ratio of the pump frequency (fp) and the dynamic cutoff frequency (fcd) given in (2.5). To maximize the efficiency, fcd should be maximized. The measured fcd of the SVAR at VNW = 2.8 V is ~125 GHz with the average Rs of 17 The measured cutoff frequencies suggest that the SVAR can op erate up to millimet er-wave/sub-THz frequencies. % f f 1 100 td p (2.4) min c, max c, max min S cdf f C 1 C 1 R 2 1 f (2.5) Due to the limitations of instrument ation, the harmonic power generation was evaluated at 900-MHz pumping frequency using a 50RF measurement set-up in Figure 2-14 [50]. VG_DC was set to 1.4 V which is a half of applied VNW of 2.8 V. Figure 2-15 shows the measured output harmonic power (POUT) generated by the SVAR versus input power levels (PIN). A larger SVAR with 216-cell pand n-VAR is used to increase the output harmonic power levels. The mismatch loss has been de-embedded to compute PIN. As expected from its C-V characte ristics, the generat ed third harmonic powers are more than 25 dB higher than t hat of the even order harmonics. The SVAR

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45 also generates considerable fi fth order harmonic power whic h approaches that of the third order ones at input power levels above 15 dBm. An ideal SVAR is not expected to generate even order harmonics. However, the second and fourth order harmonics are observed due to the mismatches in the CV characteristic for pand n-VARs. The harmonic balance simulations were carried out using a model constructed with the measurements of SVAR with 12-cell pand n-VAR. The simulated third and fifth harmonic powers in Agilent ADS showed reas onable agreement with the measurements (Figure 2-15). The peak voltage across the gate oxide is estimated to be 1.5 V at PIN = 14 dBm in the simulation. The conversion loss can be reduced by properly impedance matching the SVAR with the 50measurement set-up. Mu lti-harmonic load-pull simulations [52] show that the minimum conversion loss (CLmin) of SVAR itself is 3.1 dB at PIN = 2.6 dBm with the optimal terminat ion impedance of 4.5+ j245 and 9.5+ j73 at 900 MHz (f0) and 2700 MHz (3f0), respectively. To better understand the applicability of A-MOS SVAR in the millimeter-wave frequency range, additional simulations [52] were performed at the pumping frequency (f0) of 50 GHz. VG_DC and VNW were set to 1.4 and 2.8 V, respectively. CLmin of 15.8 dB was achieved for the third order harmonic power at PIN = 7.4 dBm with the optimal termination impedance of 19. 6+ j69.4 and 18.2+j26.0 at 50 (f0) and 150 GHz (3f0), respectively. CLmin for fifth order harmonic generation is 23.2 dB at PIN = 9.6 dBm. The optimal termination impedance is 18. 8+j82.1, +j40.0, and 16.7+j16.1 at 50 (f0), 150 (3f0), and 250 GHz (5f0), respectively.Figure 2-16 plots the third har monic output power versus VNW at varying input power levels. Optimal VNW bias to generate the maximum ou tput harmonic power exists

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46 -80 -60 -40 -20 0 -5051015 P2 P3 P4 P5 P3_sim P5_sim PIN[dBm] POUT[dBm] 2f03f04f05f0 Measurement (f0= 900 MHz) Simulation 3f05f0 Figure 2-15. RF output power versus PIN at VNW = 2.8 V. PIN= -8 dBm PIN= +4 dBm PIN= -4 dBm PIN= +8 dBm PIN= 0 dBm PIN= +12 dBm PIN= -8 dBm PIN= +4 dBm PIN= -4 dBm PIN= +8 dBm PIN= 0 dBm PIN= +12 dBm VNW[V] POUT[dBm] @3f0 -80 -60 -40 -20 0 0123 f0= 900 MHz Figure 2-16. Third order harm onic output powers versus VNW.

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47 for each input RF power level. A maximum POUT occurs at higher VNW as PIN increases. The measured fifth order harmonic power show ed similar behaviors (Figure 2-17). This can be explained using the illustration in Figure 2-18 with a given RF input swing. For small VNW (VNW = VL), the dip in the C-V curve increases with VNW, and this increases the output harmonic powers. Wi th a further increase of VNW, the dip reaches the maximum depth, and has steep sidewalls and flat bottom (VNW = VM). The input RF voltage should be sufficient to swing acro ss the highly nonlinear C-V regions to generate the maximum output harmonic powers. When VNW is further raised to make the dip wider than the input RF voltage swing (VNW = VH), the generated harmonic output power drops due to smaller capacitance variation (flat bottom portion of C-V curve) over the RF input voltage. The optimal VNW for the maximum harmonic power generation is about the half of peak to peak voltage swing across the SVAR in simulations. The performance of AMOS SVAR is compared with that of the previously reported frequency triplers using various SVARs in Table 2-1. Table 2-1. Performance Comparison This Work [39] [40] [41] Approach A-MOS HBV HBV ASV Cmax/Cmin 1.7 N/A 2.6 3.6 fcd [GHz] 125 1000 N/A N/A CLmin [dB] 15.8* 10.5 8.2 < 15.2 fout [GHz] 150 141 113 210 Technology 130-nm CMOSGaAs InP GaAs The minimum conversion loss of this work was estimated based on simulations [52].

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48 -80 -60 -40 -20 0 0123 Vnw, VP5, dBm -4 dbm 0 dbm 4dbm 8dbm 12dbm VNW[V] POUT[dBm] @5f0 PIN= -4 dBm PIN= +8 dBm PIN= 0 dBm PIN= +12 dBm PIN= +4 dBm PIN= -4 dBm PIN= +8 dBm PIN= 0 dBm PIN= +12 dBm PIN= +4 dBm f0= 900 MHz Figure 2-17. Fifth order harm onic output power versus VNW. Figure 2-18. SVAR operation conditions for different n-well bias voltages (VNW).

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492.5 Summary Two novel CMOS devices for sub-THz fr equency multiplication were proposed and demonstrated in a foundry CMOS process. The C-APDP eliminates the deleterious effects of parasitic n-well-to-substrate junc tion of n-APDPs. A C-APDP consisting of 8 cells of 0.320.32-m2 nand p-type SBDs exhibits an ex trapolated cutoff frequency of ~470 GHz. The series resistance and capacitance of C-APDP is ~46 and 7.3 fF. The third order harmonic gener ation by the C-APDP is ~25 dB higher than that for an n-SBD. As will be described in Chapter 4, the cuto ff frequency of C-APDP is increased to ~660 GHz using poly-gate separated Schottky diodes. A symmetric varactor for harmonic pow er generation was implemented in a 130-nm CMOS process. It consists of a ccumulation-mode pand n-type MOS varactors connected in parallel. The SVAR exhibits symmetric C-V characteristics with a maximum cutoff frequency of ~320 GHz, and dynamic cutoff frequency of ~125 GHz. The generated third order harmoni c power levels are more t han 25 dB higher than that of the even order harmonics. The SVAR also generates significant fifth order harmonic power at input power levels greater than 10 dBm. These suggest that the CMOS SVAR is a good candidate device for implementation of X3 and X5 millimeter-wave frequency multipliers that can be used to increase the output frequency range and lower phase noise of millimeter wave signal sources. These suggest that CMOS C-APDP and SVAR are good candidate devices for implement ation of higher order sub-THz frequency multipliers such as triplers (X3) and quintuplers (X5).

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50 CHAPTER 3 CMOS SUB-TERAHERTZ DEVICES UNDER EXTREME ENVIRONMENTS 3.1 Motivation An important sub-THz application is spec troscopy. Spectroscopy environments are diverse, ranging from extremely low temper ature lab environments, to outer space, battlefields, etc. Building spectrometer s operating in such extreme and remote environments addresses a lot of challenges in engineering designs. Electron Paramagnetic Resonance (EPR) spectroscopy is a good example of spectroscopy in extreme environments [53]. It is one of the most popular techniques with a wide range of applicat ions in chemistry, physics, biology, and medicine. Figure 3-1 shows the basic principle of EPR spec troscopy. An unpaired electron can move between the two energy levels by either abs orbing or emitting electromagnetic radiation of energy E = h The energy gap is proportional to the applied magnetic field, and higher magnetic field is used to resolve mo re resonances by widening the energy gap. For this reason, the frequency (or energy) of microwave source should be high enough to excite EPR transitions. The high-field/ high-frequency EPR instrumentation provides the ability to study very small samples and often provides extraordinary resolution and discrimination among similar species. In EPR spectroscopy, samples are often cooled down close to 0 K to get stable spectra and study their temperature depende nce. Therefore, EPR spectroscopy employs a special cryostat with a superc onducting magnet shown in Figure 3-2 [53]. Long rigid waveguides are used to deliver m illimeter-wave power into a sample cavity inside the cryostat. Because of this, a considerable transmission loss is unavoidable due to the distance between the sample cavity in the magnetic field center and the top

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51 Magnetic Field (B0)Energy (E)Absorption h = Plank’s constant v Frequency g = g-factor Bohr magneton B0= Magnetic filed 0B g h E Figure 3-1. Basic principle of electron paramagnetic resonance (EPR) spectroscopy. Millimeter-wave Source Millimeter-wave Detector Rigid Waveguides Cavity Resonator Figure 3-2. Cryostat with a superconduc ting magnet (Quantum Design PPMS) for millimeter-wave EPR spectroscopy [53].

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52 of cryostat. The losses in waveguides accoun t for a major part of the transmission loss of the system. If the spectr ometer can be miniaturized an d deployed near a sample, the EPR sensitivity can be significantly enhanced by reducing the transmission loss inside the cryostat. This is an impor tant advantage of on-chip spec trometers. However, those extreme environments potentia lly can disturb the norma l functionality of the spectrometers. To examine the feasibilit y of sub-THz CMOS on-chip spectrometer under extreme spectroscopy environments, the behaviors of devices available in CMOS are characterized in an EPR spectroscopy environment. The temperature dependence of the devices was measured at temperatur es down to 4.2 K. To understand the field dependence of NMOS transistors, measurement s were also performed under magnetic fields up to 6 T at the liquid helium temperature. 3.2 Experiment Overview The measurements are performed at four different temperatur es: 4.2, 77, 150, and 300 K. Table 3-1 shows the summary of NMOS test structures with three different gate lengths (L). The summary of diode test structur es is listed in Table 3-2. Table 3-3 shows the summary of Van der Pauw and Kelvin te st structures to measure sheet and contact resistance, respectively. All the test structur es are fabricated in a 90-nm foundry CMOS process. Figure 3-3(a) shows the Van der Pauw te st structure used to measure the sheet resistance (R). The sheet resistance can be obtained using equation (3.1). IAB is applied current between the pad A and B. VCD is the measured voltage between the pad C and D. Figure 3-3(b) shows the Kelvin te st structure used to measure the contact resistance (RC). The size of n+/M1and M1/M2 contact (via) is 0.120.12 m2 and 0.140.14 m2, respectively. The sheet resistance can be obtained using equation (3.2).

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53 A B C D E F G H Via/Contact (a) (b) Figure 3-3. Van der Pauw (a) and Kelvin (b) test structure. Sample Puck PPMS Magnet Probe Liquid He Reservoir Computer PPMS Dewar Semiconductor Parameter Analyzer (HP4155A) PPMS Controller Magnetic Field A B D C Figure 3-4. Measurement setup. (F igure continues in the next page.)

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54 A B D Figure 3-4. Measurement setup. C Figure 3-5. Test chip mounted on a sample puck.

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55 Table 3-1. Summary of NMOS test structures Test structure L [m] W [m] NMOS-1 0.08 10.0 NMOS-2 0.5 10.0 NMOS-3 1.0 10.0 Table 3-2. Summary of diode test structures Test structure Cell Area [m2] Ncell Area [m2] p-n junction diode (p+nn+) 0.4 x 0.4 12 1.92 Schottky barrier diode (PGS SBD) 0.28 x 0.28 16 1.25 Table 3-3. Summary of Van der Pauw and Kelvin test structures Test structure Conductor/Contact Thickness [m] Non-silicide poly 0.15 Non-silicide N+ N/A Silicide N-poly 0.15 Van der Pauw M2 0.22 N+/M1 contact N/A Kelvin M1/M2 contact (via) N/A AB DCI V ln2 R (3.1) FH EG CI V R (3.2) The measurement setup is shown in Fi gure 3-4. The Quantum Design PPMS (Physical Property Measurem ent System) provides the low-temperature and highmagnetic environment for the me asurement. A test chip mounted on a sample puck is shown in Figure 3-5. I-V characteristics of devices were measured using an HP 4155A semiconductor parameter analyzer.

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56 To characterize the magnetic field dependence of CMOS devices, NMOS transistors are characterized in applied m agnetic fields up to 6 T at the liquid helium temperature (4.2 K). The measurements are performed for two different field orientations shown in Figure 3-6. The vertical magnetic field (BV) is perpendicular to the substrate while the horizontal one (BH) is parallel to the gate fingers and substrate. 3.3 Experimental Results 3.3.1 Low Temperature De pendence of CMOS devices The low temperature char acteristics of deep-submicron CMOS devices are measured. Figure 3-7 shows the measured drain current (ID) versus drain voltage (VDS) of NMOS transistors at diffe rent temperatures. Their curr ent drive capability increases for the same bias condition as the temper ature decreases, indicating considerable performance improvement at low temperature. It should be noted that obvious anomalous kink phenomena and impurity freezeout were not observed down to 4.2 K due to the high doping level used in the so urces and drains of deep submicron CMOS transistors [54]. Figure 3-8 shows the temperature depend ence of NMOS drain current at VG-Vt = 0.6 V for different gate le ngths. Effective mobility (eff) and saturation velocity (vsat) are two important parameters that determine the drain current. The velocity saturation is more dominant in a shorter channel device. Since eff increases faster than vsat with decreasing temperature, the drain current of a shorter channel NMOS shows less temperature dependence. For the longes t gate transistor (L = 1 m), ID increases up to ~200% at 4.2 K.

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57 Figure 3-6. Two field orientations fo r the field dependence measurements. 0.0 0.2 0.4 0.6 0.8 0.00.20.40.60.81.0 Drain-Source Voltage (VDS) [V] Drain Current (ID) [mA/m]L = 0.08 m T = 300, 150, 77, and 4.2 K VG= 1V T decrease T decrease L = 0.5 mL = 1.0 m (a) Figure 3-7. (a) NMOS drain current (ID) versus drain voltage (VDS) and (b) drain current versus gate voltage at different temper atures. (Figure cont inues in the next page.)

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58 0.0 0.2 0.4 0.6 0.8 0.00.20.40.60.81.0 Gate Voltage (VG) [V] Drain Current (ID) [mA/m] T decrease T decrease L = 0.08 m L = 0.5 m L = 1.0 m T = 300, 150, 77, and 4.2 K VDS= 1V (b) Figure 3-7. (a) NMOS drain current (ID) versus drain voltage (VDS) and (b) drain current versus gate voltage at different temperatures. 0.0 0.5 1.0 1.5 2.0 0100200300 0 1 2 3 Drain Current (ID) [mA/m] Normalized Drain Current (ID/ID@300K)VDS= 1 V VG-Vt= 0.6 V Temperature [K] L = 0.08 m L = 1 m L = 0.5 m Figure 3-8. NMOS drain curr ent versus temperature.

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59 Figure 3-9(a) shows the te mperature dependence of th e NMOS transconductance (gm) for different gate lengths. The transcond uctance of NMOS was obtained from the slope of the ID-VG curves. Figure 3-9(b) shows the temperature dependence of the maximum transconductance (gm_max). A longer channel device shows larger increase in gm_max with decreasing temperature. For the longest gate transistor (L = 1 m), gm_max increases up to ~200% at 4.2 K compared to t hat at 300 K, which is similar to the drain current increase. Figure 3-10 shows the tem perature dependence of NMOS threshold voltage (Vt). The extrapolation in the linear region met hod is used for the extraction of Vt at VDS = 50 mV [55]. Vt changes with temperature due to the temperature dependence of Fermi potential. Normally, the short-channel effe ct (SCE) decreases the MOSFET threshold voltage as the channel length is reduced. However, a longer channel device is measured to have a lower Vt due to halo or pocket implants that reduces SCE [56]. For the longest gate transi stor (L = 1 m), Vt increased up to 80% at 4.2 K from that at 300 K. Figure 3-11 shows the tem perature dependence of the NMOS effective mobility versus temperature in the strong inversion region. The mobility is extracted using the method described in [57]. The mobility incr eases with decreasing temperature all the way down to 4.2 K by a factor of ~3.5. Figure 3-12(a) plots the te mperature dependence of R for various conductors in CMOS. The measured sheet resistances decr ease with decreasing temperature for all layers. In general, a layer with a smaller sheet resistance show s larger temperature dependence. Figure 3-12(b) shows the temper ature dependence of normalized sheet

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60 0.0 0.5 1.0 1.5 0.00.20.40.60.81.0 Gate Voltage (VG) [V] T decrease T decrease T = 300, 150, 77, and 4.2 K VDS= 1V L = 0.08 m L = 0.5 m L = 1.0 m Transconductance (gm) [mS/m] (a) 0 1 2 3 0100200300 TK g, 0 1 2 gmnorm Temperature [K] Normalized Max. Transconductance (gm_max/gm_max@300K) Max. Transconductance (gm_max) [mS/m] VDS= 1 VL = 0.08 m L = 1 m L = 0.5 m (b) Figure 3-9. (a) NMOS Transconductance (gm) versus gate voltage at varying temperatures. (b) Maximum transconductance (gm_max) versus temperature.

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61 0.0 0.1 0.2 0.3 0.4 0.5 0100200300 1 2 3 L=0.08um_Vt L=0.5um_Vt L=1um_Vt L=0.08um_Vt_norm L=0.5um_Vt_norm L=1um_Vt_norm Temperature [K] Threshold Voltage (Vt) [V] Normalized Threshold Voltage (Vt/Vt@300K) L = 0.08 m L = 0.5 m L = 1 m VDS= 50 mV Figure 3-10. NMOS th reshold voltage (Vt) versus temperature (VDS = 50 mV). 0 200 400 600 800 1000 1200 0100200300 1 2 3 4 5 Temperature [K] Effective Mobility (eff) [cm2/Vs] Normalized Effective Mobility (eff/eff@300K) VG-Vt= 0.6 V, VDS= 50 mV Figure 3-11. Effective mob ility versus temperature.

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62 resistance. The silicided polysilicon and c opper layers exhibit a typical temperature dependence of a metal. The resistance of a metal increases linearly with temperature above about 15 K due to the increase of electron-phonon interaction. As the temperature is sufficiently reduced to freeze all the phonons, the resistance usually reaches a constant value, known as the residual resistivity due to the effect of impurities and crystal defects [58]. Figure 3-13 shows the resistances versus temperature. Both resistances decrease with decreasing temperatur e. With decreasing temperat ure the contact resistance decreased up to 30% at 4.2 K. The resist ances should be acceptable for the 4.2 K operation. These, however, indi cate that the contact and ot her series resistance will become more significant part of on resistance of a transistor at lower temperatures. Figure 3-14 shows I-V curv es of p-n junction diode (PND) and Schottky barrier diodes (SBD) at varying temper atures. Ideality factors in Ta ble 3-4 are calculated from the slope of the curves in the low-inject ion region. The PND (p+nn+) shows typical characteristic down to 77 K with an ideality factor ( ) close to one. The ideality factor of PND at 4.2 K is 40.5. This is perhaps due to the fact that the forward I-V characteristic of Si p-n junction below 30 K is dominated by the thermionic emission of carriers over a small energy barrier [60]. The SBD exhibits the higher ideality fact ors as listed in Table 3-4. Thermionic emission is not the only mechanism for el ectrons to cross the potential barrier at a Schottky junction. The quantum mechanica l tunneling through the barrier has a significant effect on I-V characteristic of a highly-doped SBD especially at low temperatures [59]. It is particular signif icance in devices designed for cryogenic

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63 0 20 40 60 80 100 120 0100200300 0.0 0.1 0.2 0.3 0.4 Non-silicide Poly Non-silicide N+ Diff Silicide Poly Metal Temperature [K] Sheet Resistance (R) [ ] Sheet Resistance (R) [ ] Non-silicided poly Non-silicided n+ diff Non-silicided poly Non-silicided n+ diff Silicided poly Copper Silicided poly Copper (a) 0 0.2 0.4 0.6 0.8 1 1.2 0100200300 Temp, KRsq/Rsq_300K Non-silicide Poly Non-silicide N+ Diff Silicide Poly Copper Temperature [K] Normalized Sheet Resistance (R/R @300K) Non-silicidedpoly Non-silicidedn+ diff Silicided poly Copper (b) Figure 3-12. (a) Sheet resistance versus temp erature. (b) Normalized sheet resistance versus temperature.

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64 0 10 20 30 0100200300 0.0 0.2 0.4 0.6 0.8 1.0 Rcont Rvia Rcont/Rcont_300K Rvia/Rvia_300K Temperature [K] Contact (Via) Resistance (RC(V)) [ ] Normalized Resistance (RC(V)/RC(V)@300K) RCONT RVIARCONT/RCONT@300KRVIA/RVIA@300K Figure 3-13. Contact resist ance versus temperature. 1.E-08 1.E-06 1.E-04 1.E-02 1.E+00 1.E+02 00.511.52 Vf, VJf, mA/um2 PND_300K PND_150K PND_77K PND_4.2K SBD_300K SBD_300K SBD_77K SBD_4.2K Voltage [V] Current Density [mA/m2] 10210010-210-410-610-8T decrease T decrease Figure 3-14. I-V characteristi cs of p-n junction diode (PND) Schottky barrier diode (SBD) at varying temperatures.

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65 operation because as temperatures are lo wered, the tunneling current component becomes the dominant. 3.3.2 High Field Dependen ce of CMOS Devices at Li quid-Helium Temperature Figure 3-15 shows the field dependence of the drain current normalized to the zero-field value (ID/ID@0T). The current decreases with incr easing vertical magnetic field. The variation is larger in a longer channe l device. However, negligible changes are observed under the horizontal magnetic field (BH). For the longest gate transistor (L = 1 m), the current decreased by ~15% at 6 T of vertical fi eld. Figure 3-16 and 3-17 show the field dependence of the maximum transconductance (gm_max/gm_max@0T) and the normalized threshold voltage (Vt/Vt@0T) with the maximum shift of ~8% and ~6%, respectively at 6 T of vertical field. The normalized field dependence of the effective mobility in a strong inversion region is show n in Figure 3-18. The mobility is reduced by ~25% at 6 T of the vertical field. These fi eld dependences can be understood in terms of the magnetoresistance associated with the cyclotron motion of electrons shown in Figure 3-19 [61], [62]. The negl igible field dependence at the horizontal field is due to the strong gate electric field preventing t he cyclotron motion. The field dependence of NMOS can be avoided by positioning the in tegrated circuits alon g the orientation of magnetic field. Table 3-4. Measured ideality fa ctor of p-n junction diod e (PND) and Schottky barrier diode (SBD) Temperature [K] Ideality factor (PND) Ideality factor (SBD) 300 1.04 1.57 150 1.04 2.70 77 1.05 4.79 4.2 40.5 106

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663.4 Summary Devices available in a 90-nm CMOS technol ogy are characterized at the cryogenic temperatures and high magnetic field leve ls of EPR spectroscopy environment. The temperature dependences of NMOS transisto rs, diodes, sheet and contact resistances were measured at 300, 150, 77, and 4.2 K. The list of measured device parameters includes the drain current, transconductance, threshold voltage, and effective mobility. The NMOS transistors showed no noticeabl e anomalous kink phenomena or impurity freeze-out. Larger temperatur e dependences are observed in a longer channel device. The p-n junction diodes showed the expected behavior down to 77 K with an ideality factor close to one. Schottky barrier diodes have a high ideality factor due to the significant tunneling current through the barrier. The temperature dependence of sheet and contact resistances were characterized us ing Van der Pauw and Kelvin structures, respectively. The magnetic field dependence of NMOS transistors is also characterized at high magnetic fields up to 6 T at 4.2 K. Larger field dependences were observed in a longer channel device. The cyclotron motion of the carriers under the magnetic field accounts for the field dependent magnetoresistance. The change of device characteristics is tolerable for implementation of CMOS circuits operating in cryogenic temperat ure and high magnetic field environment. For example, a compact on-chip EPR spectromet er in Figure 1-4 could be implemented using sub-THz CMOS circuits.

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67 0.85 0.90 0.95 1.00 1.05 0246 0.90 0.95 1.00 1.05 1.10 1um_Bv 0.08um_Bv 0.5um_Bv 0.08um_Bh 0.5um_Bh 1um_Bh Magnetic Field [T] Normalized Drain Current (ID/ID@0T) Normalized Drain Current (ID/ID@0T) L = 0.08 m BHL = 0.5 m L = 1.0 m BVL = 0.08 m BHL = 0.5 m L = 1.0 m BVVG-Vt= 0.6 V, VDS= 1 V Figure 3-15. Normalized drain current of NMOS versus magnetic field. 0.92 0.94 0.96 0.98 1.00 1.02 0246 0.96 0.98 1.00 1.02 1.04 1.06 gmmaxnorm 0.08um_Bv 0.5um_Bv 1um_Bv 0.08um_Bh 0.5um_Bh 1um_Bh Magnetic Field [T] Normalized Max. Transconductance (gm_max/gm_max@0T) Normalized Max. Transconductance (gm_max/gm_max@0T) L = 0.08 m BHL = 0.5 m L = 1.0 m BVL = 0.08 m BHL = 0.5 m L = 1.0 m BVVDS= 1 V Figure 3-16. Normalized maximum tran sconductance versus magnetic field.

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68 0.92 0.94 0.96 0.98 1.00 1.02 0246 0.96 0.98 1.00 1.02 1.04 1.06 0.08um_Bv 0.5um_Bv 1um_Bv 0.08um_Bh 0.5um_Bh 1um_Bh Magnetic Field [T] Normalized Threshold Voltage (Vt/Vt@0T) Normalized Threshold Voltage (Vt/Vt@0T) L = 0.08 m BHL = 0.5 m L = 1.0 m BVL = 0.08 m BHL = 0.5 m L = 1.0 m BVVDS= 50 mV Figure 3-17. Normalized threshold voltage versus magnetic field. 0.7 0.8 0.9 1.0 1.1 0246 B, Tueff_norm 4.2K_Bv 4.2K_Bh Magnetic Field [T] Normalized Effective Mobility (eff/eff@0T) BVBHVG-Vt= 0.6 V, VDS = 50 mV Figure 3-18. Normalized effective mobilit y of NMOS versus magnetic field.

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69 Gate SourceDrain Magnetic field downward through thegate Figure 3-19. Cyclotron motion of electrons in the channel of NMOS.

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70 CHAPTER 4 CMOS SUB-TERAHERTZ FREQUENCY MULTIPLIER 4.1 Motivation One of the common approaches for sign al generation in the sub-THz frequency range is use of a single or cascaded fre quency multiplier(s) pumped by a high-power oscillator [63] or amplifier operating at lower frequencies due to the difficulty of directly generating the signals. Frequency triplers us ing an anti-parallel diode pair (APDP) have been widely adopted for sub-THz signal generati on [31], [64] [65]. Typically, frequency triplers employ highly optimized compound semiconductor devices [31], [64], [65] often mounted in bulky waveguide structures [ 65]. As mentioned, Schottky barrier diodes (SBDs) with a cutoff frequency (fc) near 2 THz [18] and a co mplementary anti-parallel diode pair (C-APDP) with fc of ~470 GHz [50] have be en reported in foundry CMOS. This chapter describes a polysilicon ga te separated (PGS) C-APDP with cutoff frequency of ~660 GHz. The C-APDP was utilized in a fully integrated frequency tripler in 130-nm CMOS with output frequency of 150 GHz and a 10-GHz 3-dB output frequency range. The output frequency range is ~10X larger than that of CMOS oscillator circuits [20] and ~1.5X larger than that of a Schottky diode frequency doubler fabricated in CMOS operating in the sim ilar frequency range [17 ]. The 150-GHz output frequency has been chosen for ease of accu rate measurements using a calibrated power sensor. 4.2 150-GHz Frequency Tripler Using C-APDP 4.2.1 Design Considerations A frequency multiplier is composed of a n onlinear device and matching/filtering networks at input and output as shown in Fi gure 4-1.The nonlinear device is driven by

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71 an input signal source to generate harmonic powers. The input network should deliver maximum fundamental power (P1) to the nonlinear device while blocking the generated harmonic powers into the input port. Only desired harmonic power (PN) is transferred to the output load through the out put matching/filtering network. A schematic of the CAPDP frequency tripler is shown in Figure 4-2. The tripler is composed of a C-APDP and RF passive ne tworks. Both n-type SBD (n-SBD) and p-type SBD (p-SBD) are used in the C-APDP to eliminate the deleterious substrate parasitic effects in an APDP using n-SBD s [50]. The C-APDP generates odd order harmonics powers efficiently as demonstrat ed in Chapter 2. The passive networks include grounded coplanar waveguides (GCP Ws) [66] and an out put bandpass filter (BPF) to select the third order harmonic signal. Figure 4-3(a) shows a cross-section of the PGS C-APDP [1 8]. The 0.40.4-m2 unit cell Schottky contact is bounded by a 120-nm-wide polysilicon gate ring. To maximize conversion efficiency, the size of C-APDP was optimized using harmonic load-pull simulations [52]. The optimized C-APD P includes 48 n-SBD unit cells and 144 p-SBD cells connected in parallel as shown in Figure 4-3(b). The minimum conversion loss of C-APDP itself is ~27 dB with the opt imal termination impedance for the C-APDP of 6.7+j22.0 and 3.5+j7.3 at the input (f0) and output frequency (3f0), respectively. Figure 4-4 plots the measured and simulated I-V curves of C-APDP. The measurements and simulations agree well. The one-port Sparameters of C-APDP were measured between 15-20 GHz using an 8510C vector network analyzer. The measured series resistance (Rs) and zero-bias junction capacitances (Cjo) is 2.3 and 105 fF, respectively. This structure has fc of ~660 GHz compared to ~470 GHz of that using

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72 Figure 4-1. Operation princi ple of frequency multiplier. Figure 4-2. Frequency tripler schematic. (a) Figure 4-3. Cross-section (a) and layout (b) of C-APDP. (Figure continues in the next page.)

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73 (b) Figure 4-3. Cross-section (a ) and layout (b) of C-APDP. -30 -20 -10 0 10 20 30 -2-1012 1.E-06 1.E-04 1.E-02 1.E+0 0 1.E+0 2 I_fit I_meas Abs(I_meas) Abs(I_fit) VC-APDP[V] 10-6 10-4 10-2 100 102 IC-APDP[mA] ABS (IC-APDP) [mA] Rs= 2.3 Cjo= 105 fF fc=660 GHz Is, n-SBD=23 nA Is, p-SBD=35 nAn-SBD=1.40p-SBD=1.35 Measurement Simulation Measurement Simulation Figure 4-4. Measured and simulated IV characteristic of the C-APDP.

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74 shallow trench separated SBDs [50]. All transmission lines (t-lines) are impl emented using a GCPW with characteristic impedance of 48 The GCPW structure was chosen to isolate transmission lines from a lossy silicon substrate and to reduce c oupling between adjacent t-lines in the networks. The cross-sect ion of the GCPW is illustrated in Figure 4-5. The signal line is formed by shunting an Al bond pad layer and a to p copper layer (M8) together to reduce the signal line loss [66]. 3-D EM simulation s using HFSS show that the GCPW has an effective permittivity ( eff) of ~3.2 with 0.6and 1.2dB/mm loss at 50 and 150 GHz, respectively. A quarter-wave open-end stub (T L2) was used to reject the generated third harmonic signal into the input port. The tr ansmission lines, TL3, TL4 and TL5, were designed to match the optimal in put impedances of the C-APDP. The output BPF was implemented using an open-end series stub [67]. The filter exhibits 3.1-dB maximum loss between 140-160 GHz with the rejection better than 8.5 dB for signals below 50 GHz in HFSS simu lations. The geometry and dimensions are summarized in Figure 4-6. Figure 4-7 shows a die photograph of the chip fabricated in the UMC 130-nm logic CMOS technology without any process modifications. The GCPWs were folded to achieve a compac t layout. A swept bend is employed to minimize the effect of an exce ss parasitic capacitance at the bend [68]. The overall chip size is 740470 m2 including bond pads. 4.2.2 Measurement Results Figure 4-8 plots the measured and simula ted small-signal S-parameters of the frequency tripler from 40 to 110 GHz. An Agile nt E8361A network analyzer was used for the measurements. The measured input return loss (|S11|) is better than -8 dB between

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75 Figure 4-5. Cross-section of GCPW. Figure 4-6. Top view of the bandpass filter. BPF TL1 TL2 C-APDP P1 P2 TL3 TL4 TL5 BPF TL1 TL2 C-APDP P1 P2 TL3 TL4 TL5 Figure 4-7. Die photograph of the frequency tripler.

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76 -20 -15 -10 -5 0 405060708090100110 Frequency [GHz]S-parameter [dB] S11_measurement S22_measurement S21_measurement S11_simulation S22_simulation S21_simulation Measurement Simulation S11 S21 S22 -20 -15 -10 -5 0 405060708090100110 Frequency [GHz]S-parameter [dB] S11_measurement S22_measurement S21_measurement S11_simulation S22_simulation S21_simulation Measurement Simulation Measurement Simulation S11 S21 S22 Figure 4-8. Measured and simulated S-parameters. Figure 4-9. Measured output spectrum (PIN = 11 dBm at 50 GHz).

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77 49 and 54 GHz. The output spectrum wa s measured using an OML G-band harmonic mixer (M05HWD) and an Agilent E4448A sp ectrum analyzer. Figure 4-9 shows the measured output spectrum at 150 GHz when t he input power level at 50 GHz is 11 dBm. Figure 4-10 shows the on-wafer test se tup for output power measurements. The input signal from the network analyzer (Agile nt E8361A) in CW mode was amplified with a Terabeam power amplifier chain, and then fed into the tripler through a GGB probe (67A-GS-150P). The output powers were measured using GGB waveguide probes (220-GSG-150 and 120-GS-150) and ELVA-1 power meters (DPM-06 and DPM-10). Figure 4-11 shows conversion lo ss (CL) and output power (POUT) versus frequency for three different input power levels (PIN). The minimum CL of 34 dB and maximum output power of -24 dBm occur around 150 GHz. The 3-dB output frequency range is ~10 GHz between 145 and 155 GHz when the input power level is higher than ~5 dBm. Figure 4-12 shows CL and the second and third harmonic output powers versus PIN at 50-GHz input frequency. The third harmonic output power (POUT @3f0) can be further raised above -24 dBm by increasing the PIN above 11 dBm. The harmonic balance simulations of CL and output powers in Agilent ADS show a reasonable agreement with the measurements (Figure 4-12). Due to the mismatch of anti-symmetr ic I-V of the C-APDP, an unwanted second order harmonic (POUT @2f0) with a power level 10-13 dB below that of the third order was observed. A second harmonic idler in a fr equency tripler plays a critical role in conversion of the energy fr om the fundamental to the th ird order harmonic frequency [49]. The low conversion efficiency can be partially explained by the non-optimal termination of the C-APDP at the idler frequency and the absence of the embedded

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78 idler circuits [31]. Simulations show that a C-APDP with an optimal termination and idler circuits can generate up to ~9-dB higher output powers. The forward conduction loss of the C-APDP, which is inherent in a varist or mode operation [69], and the mistuned Power Amplifier Chain Signal Source Power Meter DUT G-Band Waveguide Probe V-band Coaxial Probe Network Analyzer A B C D A B C D Figure 4-10. On-wafer test setu p for output power measurements.

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79 20 25 30 35 40 45 140145150155160165 Output Frequency [GHz]CL [dB]-50 -40 -30 -20 -10 0 10POUT [dBm] CL_1 dBm CL_5 dBm CL_9 dBm Pout_1 dBm Pout_9 dBm Pout_8 dBm PIN= 2 dBm PIN= 6 dBm PIN= 10 dBm CL [dB] POUT[dBm] 20 25 30 35 40 45 140145150155160165 Output Frequency [GHz]CL [dB]-50 -40 -30 -20 -10 0 10POUT [dBm] CL_1 dBm CL_5 dBm CL_9 dBm Pout_1 dBm Pout_9 dBm Pout_8 dBm PIN= 2 dBm PIN= 6 dBm PIN= 10 dBm PIN= 2 dBm PIN= 6 dBm PIN= 10 dBm CL [dB] POUT[dBm] Figure 4-11. Measured conversion loss (CL) and output power (POUT) versus output frequency. 30 35 40 45 50 -2024681012 -50 -40 -30 -20 CL_Measurement CL_Simulation Pout_Measurement Pout_Simulation Pout@2fo_Measurement PoutSimulation CL [dB] POUT[dBm] PIN[dBm] Measurement Simulation POUT @3f0POUT @2f0 30 35 40 45 50 -2024681012 -50 -40 -30 -20 CL_Measurement CL_Simulation Pout_Measurement Pout_Simulation Pout@2fo_Measurement PoutSimulation CL [dB] POUT[dBm] PIN[dBm] Measurement Simulation POUT @3f0POUT @2f0 Figure 4-12. Measured and simulated conv ersion loss (CL) and output power (POUT) at 150 GHz versus input power (PIN).

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80 passive networks are also responsible for the high conversion lo ss. Due to the low barrier height of SBDs, the out put power starts to saturate at a lower input power level [70]. The performance comparison with the pr eviously reported frequency generators is summarized in Table 4-1. Table 4-1. Performance comparison This Work [64] [20] [17] Approach Frequency Tripler Frequency Tripler Oscillator Frequency Doubler fOUT [GHz] 145-155 a 84-103 a 139-140.2 b 120-125 a Min. CL [dB] 34 18 N/A 10 Max. POUT [dBm] -25 ( PIN = 11 ) -3 ( PIN = 16 ) -19 -1.5 ( PIN = 8.5 ) Technology 130-nm CMOS GaAs 90-nm CMOS 130-nm CMOS Area [m2]740470150010005403601100700 a 3-dB output frequency range and b Tuning range. 4.3 Summary This chapter described the first C-APDP fre quency tripler fabricated in a standard digital CMOS process without any proc ess modifications. The C-APDP was implemented with the PGS SBDs and exhibited a cutoff frequency (fc) of ~660 GHz. A maximum output power of -24 dBm was gener ated by the frequency tripler with 34-dB minimum conversion loss at 150 GHz. The 3-dB output frequency range was measured to be ~10 GHz. In the near term, Schottky diodes in CMOS can be used to generate signals at sub-THz frequencies with a wide r output frequency range well beyond that can be supported using MOS transistor oscillators.

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81 CHAPTER 5 CMOS SUB-TERAHERTZ FREQUENCY DIVIDER 5.1 Motivation A frequency divider plays a critical block in the implementation of phase locked loops (PLLs) for wireless and wireline commu nication systems. Generally, it can be classified into three groups: flip-flop-based digital, regenerative, and injection-locked frequency divider (ILFD). A conv entional digital frequency divi der is not suitable for subTHz frequency operation due to their mo derate maximum operating frequency even under high power consumption. A maximu m speed of ~60 GHz has been reported in 65-nm CMOS [71]. A regenerat ive divider has not been popular in CMOS technology due to complexities in implementation [7 2]. A 40-GHz Miller regenerative divider has been demonstrated in 0.18-m CMOS technolo gy using resonance techniques but with high power consumption [73]. An LC-based ILFD features high-frequency capability at low power consumption [74]. Recently, direct ILFDs in CMOS boasted their high operation capability at millimeter-wave frequencies [52], [7 5], [76]. A drawback of ILFDs is narrow locking range due to the reliance on circuit oscillation. To demonstrate subTHz frequency division in CMOS technology a 194-GHz 4 frequency divider using two cascaded ILFDs has been implemented. 5.2 194-GHz Injection Lo cked Frequency Divider 5.2.1 Design Considerations The diagram of the 194-GHz fr equency divider is shown in Figure 5-1. It is composed of two cascaded 2 ILFD stages to divide ~194-GHz signal in to ~48.5-GHz one. Due to the limitations of instrumentation, a 194-GHz signal generator (SG) is

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82 Figure 5-1. Diagram of 194-GHz frequency di vider with an input signal generator. Figure 5-2. Schematic of 194GHz input signal generator.

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83 integrated together to provide the input si gnal for the divider. A frequency doubled (~388 GHz) signal is also generated and radiat ed through an on-chip antenna. The radiated signal could be detected using qu asi-optical measurement [21]. Figure 5-2 shows the schematic of the signal generator implemented using a cross-coupled differential LC-o scillator. One of t he differential outputs is connected to the input of divider for injection of a ~1 94-GHz signal. Two-stage buffers are used to isolate the oscillator from external loads. The transistor sizes are listed in Table 5-1. Matching and bias networks in the circuit ar e implemented using transmission lines (tlines). The shunt bypass capacitors connected to t-lines, CBP1, CBP2, and CBP3, are implemented with the woven metal-oxide-meta l structure [77]. Second order harmonic currents in the oscillator are constructively added at the center tap of the inductor. The push-push node (n0) is connected to an on-chip microstrip patch antenna for a quasioptical measurements [21]. Figure 5-3 shows the schematic of the 194-GHz 4 frequency divider. The first (DIV1) and second ILFD (DIV2) are cascaded via an inter-stage buffer (ISF). The freerunning oscillation frequency of the first (DIV1) and second ILFD (DIV2) is ~97 and ~48.5 GHz, respectively. A differential indu ctor and cross-coupled transistor pair are employed for LC-based oscillation. The size of all transistors in Figure 5-3 is listed in Table 5-1. A single-turn circular inductor us ing the ~2.5-m-thick Metal 7 layer (M7) is employed for each ILFD. Figure 5-4 shows the la yout of the differentia l inductor for DIV1. In modern CMOS technologies metal dummy fills are used to achieve a uniform metal density for the CMP (Chemical Mechanical Polis hing) process. Dummy fills adjacent to an inductor line have a strong impact on Qfactor and SRF (Self Resonant Frequency)

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84 Figure 5-3. Schematic of 194-GHz 4 frequency divider. P3DummyDummy DummyDummy P1P2Dummy Dummy dL wL Figure 5-4. Core inductor of DIV1 (L3/L4).

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85 M1-M6 Dummy Poly-Si Dummy M7 Dummy Figure 5-5. Floating dummy fills in the core inductor of DIV1. Figure 5-6. Cross-section of GCPW.

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86 [78]. A custom dummy filling technique is em ployed to block out dummy fills near the inductor line. The inductor ha s a higher-density region arou nd the center to meet the metal density rules. Poly-silicon dummy fills are uniformly spread under the inductor. Each dummy fill has a minimum area allowed by design rules. The size and density of the dummy fills in M1-M6 layers is 0.40.4 m2 and ~30%, respectively. Figure 5-5 shows the dummy fill patterns around the induc tor line. HFSS simulations are performed to model the inductor. A differential inductance (Ldiff) and Q-factor (Qdiff) of the inductor are obtained from the simula ted S-parameters using (5.1)-(5 .4) [79]. The parameters of the differential inductors, L3/L4 and L5/L6, are listed in Table 5-2. 2 S S S S S21 12 22 11 diff (5.1) diff diff 0 dffS 1 S 1 Z 2 Z (5.2) (Z Im Ldiff diff) (5.3) ) )diff diff diff(Z Re (Z Im Q (5.4) Table 5-1. Transistor sizes (L = 40 nm) M1/M2 M3 M4 M7/M8 M9 M11 M12/M13 M14 W [m] 9.5 3.0 9.1 13.7 6.8 3.0 21.3 12.9 Table 5-2. Core inductor design parameters (m) dL [m] wL [um]Ldiff [pH] Qdiff SRF [GHz] L3/L4 46 4 ~85 @100GHz ~15 @100GHz ~350 L5/L6 84 6 ~180 @50GHz ~20 @50GHz ~200

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87 The injection transistors, M9 and M14, are biased through 4.5-k silicide-block poly resistors, RB1 and RB2. The coupling capacitors, CC1 and CC2, are implemented using 60-fF parallel plate capacitors. Two parallel binary-scaled varactor pairs for each ILFD are tuned to enhance their locking range [25]. An accumulation-mode MOS structure is employed with a non-minimum gate length (L = 0.11 m) with a higher tuning ratio [43]. The varactor widths are listed in Table 53. The inter-stage buffer (ISB) between DIV1 and DIV2 is matched using t-line networks. All t-lines are implemented using GCPW (Grounded Coplaner Waveguide) structure with characteristic impedance of 45 [66]. The signal line is formed by an Al bond pad la yer [66]. 3-D EM simulations using HFSS show that the GCPW has an effective permittivity ( eff) of ~3.4 with 1.3-dB/mm loss at 100 GHz. The cross-section of the GCPW is illustrated in Figure 5-6. The t-line lengths in the design are listed in Table 5-4. Tw o-stage output buffers are used to drive 50measurement equipments. Figure 5-7 shows simu lated input sensitivity curves of DIV1 for different bias voltages of the injection signal (VINJ_DC1). The divider has 4.4 GHz (2.0%) at the injection power level of 0 dBm and VINJ_DC1 = 1.0 V. Figure 5-8 shows a die photograph of the divider with the signal generator fabricated in a 45-nm digital CMOS technology. The overa ll chip size is 1.11.3 mm2 including bond pads. The frequency divider alone occupies 340310 m2. Table 5-3. Tuning varactor widths (L = 0.11 m) CV11/12 CV21/22 CV31/32 CV41/42 W [m] 2.7 5.4 8.0 16.1 Table 5-4. Transmission line lengths (m) TL1/TL2 TL3 TL4 TL5 TL6 TL7 TL8 TL9 TL10 95 110 100 70 70 80 70 120 110

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88 -20 -10 0 10 210215220225 Vg=1.0V Vg=0.8V Vg=0.9VFrequency [GHz]Injection Power [dBm] VINJ_DC1= 1.0 V VINJ_DC1= 0.9 V VINJ_DC1= 0.8 V VDD_DIV1= 1.0 V IB_DIV1= 3.8 mA Figure 5-7. Simulated input sensitiv ity curves of the frequency divider. Signal Gen. On-Chip Antenna DIV1 DC Bond PadsfIN fDIV1 fDIV2 DIV2 340 m310 m Figure 5-8. Die photograph of the frequency divider wi th the signal generator.

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89 Chip Bypass Capacitor Figure 5-9. Test board photograph. B E F Spectrum Analyzer Spectrum Analyzer Spectrum Analyzer Spectrum Analyzer DC Bias Board DC Power Supply C D A DUT HM1 HM3 HM2PRB1PRB2PRB3GGB 120-GS-150 W-Band Waveguide Probe PRB2 GGB 220-GSG-150 G-Band Waveguide Probe PRB1 Agilent 11970U U-Band Harmonic Mixer HM3 GGB 67A-GS-150P V-Band Coaxial Probe PRB3 Agilent 11970W W-Band Harmonic Mixer HM2 OML M05HWD G-Band Harmonic Mixer HM1 GGB 120-GS-150 W-Band Waveguide Probe PRB2 GGB 220-GSG-150 G-Band Waveguide Probe PRB1 Agilent 11970U U-Band Harmonic Mixer HM3 GGB 67A-GS-150P V-Band Coaxial Probe PRB3 Agilent 11970W W-Band Harmonic Mixer HM2 OML M05HWD G-Band Harmonic Mixer HM1fINfDIV1fDIV2 Figure 5-10. On-wafer test se tup for the frequency divider. (F igure continues in the next page.)

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90 E F B A D C Figure 5-10. On-wafer test setup for the frequency divider. 46 48 50 52 54 0.00.20.40.60.81.0 92 94 96 98 100 VCTRL31=0V VCTRL31=1V VCTRL21=0V VCTRL21=1VfDIV2[GHz] fDIV1[GHz] fDIV2@VT3= 0V fDIV2@VT3= 1V fDIV1@VT1= 0V fDIV1@VT1= 1VVT2 andVT4 [V] Figure 5-11. Frequency tuning ranges of DI V1 and DIV2 versus tuning voltages.

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915.2.2 Measurement Results The chip is mounted and wirebonded to a test board as shown in Figure 5-9. Figure 5-10 shows the detail on-wafer meas urement setup. The output frequency of SG, DIV1, and DIV2 (fIN, fDIV1, and fDIV2, respectively) was measured using millimeter-wave probes and harmonic mixers followed by spectrum analyzers. Figure 5-11 shows the measured free-running frequen cy of DIV1 and DIV2 for varying tuning voltages (VT’s). The tuning range of SG, DIV1 and DIV2 is summarized in Figure 5-12. The figure demonstrates that the tuning r anges of two dividers are well -aligned to cover the output frequency range of the signal generation. Each divider block, DIV1, ISB, and DIV2, draws 3.1, 0.7, 2.2 mA of current, respectively from a 1.0-V supply. The bias voltages of injection signals, VINJ_DC1 and VINJ_DC2, are set to 1.0 V. The divider consumes 6 mW excluding the output buffers. The locking range of the frequency divider is measured by changing the output frequency of the signal generator. The inject ion signal frequency could be tuned from 192.4 to 196.6 GHz. The free-runni ng frequency of DIV1 and DIV2 (fDIV1_FR and fDIV2_FR) is set to 97.0 and 48.5 GHz, respectively The frequency divider loses lock as the injection signal frequency is tuned above195.5 GHz. The fr equency divider exhibited the locking range of 3.1 GHz from 192.4 to 195.5 GHz as shown in Figure 5-13. The phase noise of the frequency divider is dominated by that of the injection signal for a small offset frequency from a ca rrier [80]. Figure 5-14 shows the measured output phase noise of DIV2 with and without the injection signal. Both SG and DIV1 were turned-off to measure the phase noise of the free-running DIV2 in Figure 5-14(a). The injection locked divider (Figure 5-14(b )) exhibits ~5-dB lo wer phase noise at 10 MHz offset.

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92 Injection pulling occurs in LC-based ILFD if the injection signal frequency is close to the limit of the locking range [81]. Figure 5-15 shows t he measured spectrum of the injection pulled frequency divider with the in jection signal frequency slightly above the locking range. The spectrum exhibits the ty pical fast beat behavior in an injection pulled oscillator [81]. The performance of the divider is summarized in Table 5-5. Table 5-5. 194-GHz 4 frequency divider summary Supply voltage 1.0 V Power consumption* 6.0 mW (6.0 mA/Total = 3.1 mA/DIV1 + 0.7 mA/ISB + 2.2 mA/DIV2 Locking range 192.4–195.5 GHz (1.6%) Technology 45-nm Logic CMOS (7 Metal layers) Area340310 m2 Excluding output buffers. 5.3 Summary A 194-GHz frequency divider was implement ed in 45-nm logic CMOS. Two ILFDs are cascaded to perform 4 frequency division for the sub-THz input signal provided by a built-in signal generator. T he frequency divider exhibits a locking range of 3.1 GHz at ~194 GHz. The injection locking is also verified by observing the phase noise change and injection pulling. These results suggest t he feasibility of sub-THz phase locking at low power consumption in CMOS.

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93 185190195200205210 Frequency [GHz]00011011 011011fIN2fDIV14fDIV2 Frequency [GHz]00VT1(VT2) VT2(VT4) 1 V 1 V 11 0 V 1 V 10 1 V 0 V 01 0 V 0 V 00 VT1(VT2) VT2(VT4) 1 V 1 V 11 0 V 1 V 10 1 V 0 V 01 0 V 0 V 00 VT4VT3 = VT2VT1 = Figure 5-12. Measured tuning range of SG, DIV1, and DIV2. 192 194 196 198 36912 48.0 48.5 49.0 49.5 fIN fDIV2Bias Current (IB_SG) [mA]fIN[GHz] fDIV2[GHz] fINfDIV2VDD_SG= 1.4 V fDIV1_FR= 97.0 GHz fDIV2_FR= 48.5 GHz Figure 5-13. Measured locking range of the frequency divider.

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94 Carrier Freq = 48.47 GHz PN= -103.8 dBc/Hz @10MHz (a) Carrier Freq = 48.52 GHz PN= -108.7 dBc/Hz @10MHz (b) Figure 5-14. Measured phase noise of (a ) the free-running and (b) injection locked divider.

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95 fIN/4 = 48.84 GHz Figure 5-15. Measured s pectrum of the injecti on pulled frequency divider.

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96 CHAPTER 6 CMOS SUB-TERAHERTZ FREQUENCY SOURCE 6.1 Motivation N-push techniques have been employed to generate signals above the unity maximum available gain frequency (fmax) of devices [21], [22], [82], [83]. Recently, a 1.3-THz signal has been generated in CMOS using the 6th harmonic of a 4-push oscillator [83]. The signal is one of the unex pected harmonics. None of the power levels of the circuit were available. In addition, the fourth order output power level was lower than those of the fi rst three harmonics. This chapter reports a quadruple-push o scillator fabricated using low leakage transistors of a 45-nm CMOS technology with improved 4th harmonic current generation and suppression of unwanted harmonics. It radi ates 220 nW of power at 553 GHz. The output power is ~4X that radiated at 410 GHz in [21] which has been the highest radiated from a CMOS circui t at frequencies above 400 GHz. 6.2 553-GHz Quadrupl e-push Oscillator 6.2.1 Design Considerations A maximum operation frequency of an oscilla tor is limited by the unity maximum available power gain frequency (fmax) of a transistor [84]. Figure 6-1(a) shows the simulated frequency response of the maximum available power gain (Gmax) and unity current gain (|h21|) of a 45-nm CMOS tr ansistor. The peak fmax and ft of the device is estimated to be 362 and 243 GHz, respectively. A simulated fmax and ft for various gate bias voltages is plotted in Figure 6-1(b) A quadruple-push (4-push) technique is devised to push output frequency substantially above the fmax of this device.

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97 0 10 20 30 40 50 1101001000 Gmax h21Frequency [GHz]Gain [dB] Gmax@ VG = 0.85 V |h21| @ VG = 1.1 Vfmax= 362 GHz ft= 243 GHzftNMOS W = 0.6 20 m L = 40 nm VDS= 1.1 V fmax (a) 0 100 200 300 400 0.40.60.81.01.2 fmax ftNMOS W = 0.6 20 m L = 40 nm VDS= 1.1 VFrequency [GHz]VG[V] fmax ft (b) Figure 6-1. (a) Simulated frequency response of Gmax and |h21|. (b) Simulated fmax and ft versus Vg.

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98 The 4-push signal generator is based on a quadrature oscillator [85]. Figure 6-2 shows a linear model of t he quadrature oscillator. Gm and Gmc represents the transconductance of cross-c oupled core transistors (MC) and coupling transistors (MCPL), respectively. Due to the combination of direct and inverted connection between two oscillators, the output si gnals should have a quadrature phase offset to satisfy Barkhausen criteria. Figure 6-3 shows the sc hematic of proposed 4-push oscillator with an on-chip antenna. The harmonic currents ICPL in MCPL are added by a passive combining network implemented with trans mission lines. Instead of using a separate linear phase combiner [22], this circuit utiliz es the quadrature coupling transistors in the oscillator core as the combiner. This reduc es the capacitive loading of the LC tanks by the gates of phase combiner circuit, which in tu rn allows the size of transistors in the quadrature oscillator core to be increased for higher output power. All transmission lines (t-lines) ar e once again implemented using grounded coplanar waveguide (GCPW) with characteristic impedance of ~45 [66]. The signal line is formed using the Al bond pad layer wi th thickness of ~1.2 m, and Metal 1 to Metal 3 layers are shunted together for t he bottom ground plane. 3-D EM simulations using HFSS show that the GCPW has an effective permittivity ( eff) of 3.2 with 3-dB/mm loss at 600 GHz. A single-turn circular inducto r using ~2.5-m thick Metal 7 layer (M7) is employed for the LC tanks. The i nductor has the outer diameter (dL) of 31.0 m and width (wL) of 2.8 m. The custom floating du mmy fills discussed in Chapter 5 are employed for the inductor. HFSS simulati ons show the differential inductance (Ldiff) of 56 pH and Q-factor (Qdiff) of 14 at 150 GHz. The sources of MCPL (n1 node) are terminated with a t-line matching network to ma ximize the power output at the 4th harmonic

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99 Figure 6-2. Simplified linear m odel of a quadrature oscillator. Figure 6-3. Schematic of quadruple-push oscillator schemat ic with an on-chip antenna.

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100 frequency. The nodes n2 and n3 are potentially another nodes at which the 4th order harmonic could be extracted. Simulations showed that the 4-pus h harmonic combining at the node n2 and n3 results ~30 and ~50% lower outpu t power, respectively than that generated at the node n1. The node n3 would need long interconn ects to the combining network in a typical symmetric layout of a quadrature oscillator to keep core and coupling transistors close together. The interconnects introduce additional losses and increase the layout complexity of the circuit. -5 0 5 10 15 14001405141014151420 -0.8 -0.4 0.0 0.4 0.8ICPL[mA] ICPL_I+ ICPL_IICPL_Q+ ICPL_Q-IOUT IOUT[mA]Time [ps]VDD= 1.4 VIBIAS= 44mA Figure 6-4. Simulated current waveforms in the oscillator. II+ I+ QQ+ QI+IQ+Q-IQ+ I+ QQ+ IFundamental (f0) 2ndharmonic (2f0) 3rdharmonic (3f0) 4thharmonic (4f0) Figure 6-5. Quadruple-push operation.

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101 Figure 6-4 shows simulated indivi dual current waveform through MCPL and the output node. They contain higher order har monics due to the nonl inearities in the oscillator. In the 4-push oscillator, only 4nth (n = 1, 2, 3, …) order harmonics are constructively combined while other harmonics cancel out as illustra ted in Figure 6-5. Increasing the coupling transistor width ra ises the output power and lowers output frequency because of increased LC tank c apacitance. Figure 6-6 shows the tradeoff between POUT (power delivered to the on-chip antenna) and fOUT as function of WCPL to WC ratio, m. The output power (POUT) saturates as m approaches one. The width of MC and MCPL is set to be ~12 and ~7.5 m, respecti vely with the minimum gate length of 40 nm. Device mismatches, parasitic inductive coupling, and layout asymmetries lead to departure from the ideal quadr ature generation in a quadrat ure oscillator [86]. The phase error degrades image suppression capabili ty of a wireless receiver with an image-reject architecture. In the case of 4push oscillator, the pha se error reduces the output power. To analyze the effect of phase error to the output power, additional simulations are performed for the oscillator with 2% mismatch in the tank resonant frequency of the Iand Q-oscillators. T he output power degrades less than 2% for m higher than 0.5 as shown in Figure 6-6. The level of frequency mismatch in real quadrature oscillators is expected to be < 0. 1%. The 4-push oscillator should have an outstanding immunity to the phase error. The on-chip antenna was implemented using a microstrip patch antenna [21]. The aluminum pad layer is used to form the patch. The ground plane is formed by shunting Metal 1 to Metal 6 layer. The thickness of each metal layer is ~0.2 m. The separation between the patch and ground plane is ~4 m. HFSS simulations were performed to

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102 0.0 0.5 1.0 1.5 0.00.51.01.5 580 590 600 610 620 630m (WCPL/WC) w/o mismatch w/ mismatch POUT/POUT(m0)Design fOUT[GHz] m = m0 Figure 6-6. Simulated nor malized output power (POUT/POUT(m0)) and frequency (fOUT) versus m (WCPL/WC). -25 -20 -15 -10 -5 0 540560580600620640660Frequency [GHz]Return Loss [dB]HFSS Model 120 m 160 m Figure 6-7. Simulated return loss of the on-chip microstrip patch antenna.

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103 -4 -2 0 2 540560580600620640660Frequency [GHz]Peak Gain [dBi]0 10 20 30Efficiency [%] Peak Gain Efficiency Figure 6-8. Simulated peak gain and efficien cy of the microstrip patch antenna around the resonant frequency. E-plane H-plane [dBi] Figure 6-9. Simulated gai n pattern of the antenna.

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104 Patch Antenna VDD4-Push Oscillator GNDGND VB 540 m 530 m Figure 6-10. Quadruple-push oscillator die photograph. MC1/MC2 MC3/MC4 MCPL2 MCPL1 MCPL4 MCPL3 Interconnects Figure 6-11. Layout of in terconnects between the core and coupling transistors.

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105 analyze antenna performance. The antenna exhibits a good input match around 600 GHz as shown in Figure 6-7. Figure 6-8 shows a simulated peak gain and efficiency around the resonant frequency. The peak gain and efficiency of the antenna is -0.2 dB and 28%, respectively around 600 GHz. Simula ted Eand H-plane gain pattern of the antenna are plotted in Figure 6-9. An inse t-feed structure is used for input impedance matching. The patch size is 160120 m2. Figure 6-10 shows a die photograph of the fabricated oscillator. The lay out was optimized for symmetry to minimize mismatches. Figure 6-11 shows the layout of interconnec ts between the core and coupling transistors with an identical length. The overall chip size is 540530 m2 including bond pads. The chip is mounted and wirebonded to a test board as shown in Figure 6-12. 6.2.2 Measurement Results It is challenging to detect sub-microwa tt signals above 500 GHz using electronic instrumentation due to excessive loss [ 22]. Furthermore, no electronic probe is presently available. In this work, a quasioptical setup using t he on-chip antenna and a Fourier transform infrared (FTIR) spectrom eter (Bruker ISF 113v) in Figure 6-13 is employed [21]. A 23-m-thick Mylar beam sp litter was used in the FTIR. Detailed measurement parameters are list ed in Appendix. The oscillator spectrum is measured in the atmosphere at room temper ature. Due to the intense mo lecular rotational transitions of water molecules, THz signals exhibit a strong atmospheric attenuation depending on frequencies [90], [91]. The a ttenuation is corrected using the Mercury arc lamp spectrum data measured in the atmos phere and vacuum (Figure 6-14). A strong attenuation is observed at the typical water vapor absorption lines including ~558, ~753, and ~989 GHz [92]. The atmosphere attenuation is measured to be ~50% at the output frequency of the oscillator (553 GHz).

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106 Chip Bypass Capacitor Figure 6-12. Test board photograph. Fixed Mirror Bolometer Movable Mirror Beam Splitter FFT ffOSCfOSC Intensity OSCf c On-chip Patch AntennaMichelson Interferoemeter 4-Push Oscillator A B C /2 Figure 6-13. FTIR setup for t he output spectrum measurement. (Figure continues in the next page.)

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107 C B A B A Figure 6-13. FTIR setup for the output spectrum measurement.

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108 Figure 6-15 plots the measured output spectrum and radiated power (PRAD). The oscillator generated an output signal at 553 GHz with the power level of 220 nW. Harmonics up to 6th order (829.2 GHz) were observed. The power levels of all unwanted harmonics are suppressed below 50 nW. The ta rget operating frequency of the on-chip antenna is ~47-GHz higher than the measured output frequency of the oscillator. The frequency mismatch degrades input return lo ss and radiation efficiency of the antenna. The radiated power is estimated to be 1. 29 W with an on-chip antenna tuned at the measured oscillation frequency. The oscillator draws 46 mA of cu rrent from a 1.4-V supply. The radiated power is measured us ing a liquid helium-c ooled Si bolometer (Infrared Laboratories HD-3) wi th responsivity of 4.0104 V/W. A detail measurement setup is shown in Figure 6-16. The oscillat or was powered by 10-Hz square wave from a waveform generator to modulate the r adiated power. The output signal from the bolometer was measured using a lock-in am plifier (Ithaco 393). Figure 6-17 plots the measured radiated power and frequency versus bias current. The circuit starts to oscillate at 12 mA and the radi ated power monotonically increas es with the bias current. The output frequency varied ~0.5 GHz over the bias range. The performances of the 4-push oscillator are summarized in Table 6-1.

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109 0 1 2 3 4 5 20040060080010001200 Frequency [GHz]Intensity [a.u.] Vacuum Atmosphere 558.2 752.6 988.5 988.5 GHz 752.6 GHz 558.2 GHz Figure 6-14. FTIR spectrum of a Mercury arc lamp in the atmosphere and vacuum. 0 50 100 150 200 250 1003005007009005f0552.8 GHz2f03f0f0 Frequency [GHz] PRAD[nW]6f0VDD= 1.4 V IBIAS= 46 mA4f0138.2 GHz 276.4 GHz 414.6 GHz 691.0 GHz 829.2 GHz Figure 6-15. Measured spectr um of the radiated power.

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110 Signal Generator Bolometer 10 Hz Oscilloscope 4-Push Oscillator VDD0V A B C D E Lock-in AmplifierVINVOUT A B C D E VINVOUT Figure 6-16. Output power measurement setup.

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111 0 50 100 150 200 250 1020304050 552.0 552.5 553.0 Prad FreqBias Current [mA] fOUT[GHz] PRAD[nW]VDD= 1.4 V Figure 6-17. Measured radiated power (PRAD) and output frequency (fOUT) versus bias current. Table 6-1. Performance summary of sub-THz quadruple-push oscillator Output frequency 553 GHz Supply voltage 1.4 V Radiated power (PRAD) 220 nW Antenna peak efficiency 28% (simulation) Antenna peak gain -0.2 dBi (simulation) Estimated radiated power (PRAD) w/ a tuned on-chip antenna 1.29 W Power consumption 64 mW Technology 45nm Logic CMOS (7 Metal layers) Chip area 540530 m2

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1126.3 Summary A half-THz continuous wave signal was generated by a CMOS 4-push oscillator. Since the forth harmonic curr ent in a quadrature oscillator is directly added up by an embedded combining network, the oscillator does not need a s eparate active harmonic power combiner. The output signal is coupled to an optical instrument by an on-chip antenna to detect 220-nW radiated power at 553 GHz. The well-suppressed unwanted harmonic powers suggest that sufficient quadrature accuracy has been achieved in the oscillator.

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113 CHAPTER 7 SUMMARY AND FUTURE WORKS 7.1 Summary This dissertation investigated the implem entation of devices and building blocks for sub-THz signal generation using digi tal CMOS (Complementary Metal Oxide Semiconductor) technology. [42], [89]. Two novel non-linear devices C-APDP [50] and SVAR [87], were implemented in 130-nm CMOS process for sub-THz frequency multiplier applications. Both devices predominantly produce odd harmonics of an appli ed signal due to the anti-symmetric I-V characteristics. To eliminate the deleterious effects from s ubstrate parasitics both n-type SBD (n-SBD) and p-type SBD (p-SBD) are us ed in the C-APDP. The C-APDP exhibited the maximum extrapolated cutoff frequency of ~470 and ~660 GHz using STS and PGS SBDs. The SVAR consists of pand n-type accumulation-mode varactors connected in parallel and shows symmetric C-V characte ristics. The maximum and minimum cutoff frequency is measured to be ~295 and ~175 GHz, respectively with a dynamic cutoff frequency of ~120 GHz. Measurements of generated harmonic power showed the absence of even order harmonics and presenc e of high levels of third and fifth harmonics. This suggests that frequency tr iplers and quintuplers can be implemented using the structure. To investigate the feasibi lity of operation of CMOS ci rcuit in EPR spectroscopy applications, CMOS devices are characte rized under the low temperature and high magnetic field. The temper ature dependences of NMOS tr ansistors, diodes, sheet and contact resistances are measured at 300, 1 50, 77, and 4.2 K. Th e NMOS transistors exhibited no anomalous kink phenomena or im purity freeze-out. Larger temperature

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114 dependences were observed in a longer channel device. A p-n junction diode exhibited a expected behavior down to 77 K with the i deality factor close to one. Higher ideality factors were measured in the Schottky barri er diodes due to the significant tunneling current component through the barrier typica l in a Schottky junction formed on a highly doped semiconductor. Van der Pauw and Kelvin structures were used to measure the temperature dependence of sheet and contact resistances, respectively. The magnetic field dependence of NMOS transistors is al so measured under high magnetic fields up to 6 T at the liquid helium temperature. Larger field dependences were observed in a longer channel device for the magnetic fiel d perpendicular to the channel direction. However, these indicate that CMOS circui ts should have acceptable characteristics in the cryogenic and high field environment for EPR spectroscopy. The first complementary anti-parallel Schottky diode frequency tripler in CMOS has been demonstrated in Chapter 4 [88]. The tripler exhibited ~34-dB minimum conversion loss and -24-dBm maximum output power at 150 GHz. The measured 3-dB output frequency range is ~10X wider t han that of a 140-GHz CMOS oscillator fabricated in 90-nm CMOS [20]. A 194-GHz 4 frequency divider using two cascaded injection-locked frequency dividers (ILFDs) has been demonstrated in 45-nm CMOS. The locking range is measured to be 3.1 GHz from 192.4 to 195.5 GHz. This circuit is the fastest CMOS frequency divider with a division modulus gr eater than two. The frequency divider along with the built-in signal generat or suggests the feasibility of a sub-THz phase-locked loop at low power consumption in CMOS.

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115 A half-THz quadruple-push oscillator has been demonstrated using 45-nm logic CMOS technology [93]. Quasi-optical meas urements showed that the circuit generates 4th harmonic signal at 553 GHz with the power level of 220 nW, while suppressing unwanted harmonic signals. The o scillator generates ~4X higher power at ~1.5X higher frequency than the 410 GHz signal generator pr eviously demonstrated in the same process [21]. This circuit is the highest fr equency oscillator with an identified power level in CMOS. 7.2 Future Works A varactor-mode sub-THz frequency multipli er would be implemented using the symmetric varactor demonstrated in Chapter 2. The symmetric C-V characteristic of the device makes even order harmonic idler circ uits unnecessary in frequency tripler or quintupler designs. Due to the mismatch in the anti-symmetric I-V of C-APDP, the device generates considerable second harm onic powers. The conversion loss of C-APDP frequency tripler in Chapter 4 would be improved by proper termination of C-APDP at the second har monic idler frequency. The output power level from the sub-THz osc illator is still low for most real-world applications. The output power could be increas ed by further optimization in design and layout to minimize losses and parasitics in transistors, inductors, and t-lines. The oscillator generated an output si gnal at 553 GHz while the on-chip microstrip patch antenna was tuned to ~585 GHz. Since the antenna has a narrow bandwidth, the operation at the non-resonant frequency result s in a significant drop in radiation efficiency. More output power should be radi ated if the oscillator frequency is matched to the resonant frequency of antenna. It would be interesting to develop a wideband sub-THz antenna in CMOS to resolve the mistuning issue.

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116 Many sub-THz systems need a signal source with a wide tuning range. The subTHz oscillator could incorporate a frequen cy tuning capability by adding accumulationmode MOS (A-MOS) varactors. A-MOS varact or has the highest Q-factor among CMOS variable capacitors. However, loss of the device increase s with operation frequency. An A-MOS varactor potentially causes severe degradation in Q-factor and tunability of LCtank operating in the sub-THz frequency. It is essential to develop a CMOS tunable device with a high-Q and high tuning range in the sub-THz region to realize a more useful frequency source.

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117 APPENDIX FTIR MEASUREMENT PARAMETERS Optic Aperture Setting 3; 10 mm Beam splitter Mylar 23 um Detector Setting 1; DTGS/KBr (MIR) or BOLO High Pass Filter Open Low Pass Filter 7; 137 Hz Optical Filter Setting Black Polyethylene Scanner velocity 7; 12.5 KHz Signal Gain 1 Acquisition Acquisition Mode Single sided Delay Before Measurement 0 Stabilization Delay 4 Wanted High Freq Limit 700 Wanted Low Freq Limit 0 Sample Scans 64 Result Spectrum Transmittance Resolution 0.1 FT Apodization Function Norton-Beer, Medium Phase Resolution 10 Phase Correction Mode Mertz Zero Filling Factor 4 Instrument High Folding Limit 987.375 Low Folding Limit 0 Laser Wavenumber 15798 Absolute Peak Pos in Laser 5294 Sample Spacing Gain 1 Scan time (sec) 930.56 Peak Amplitude 919 Peak Location 153 Instrument Type IFS113 Running Sample Number 19568

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126 BIOGRAPHICAL SKETCH Dongha Shim received his B.S. and M.S. degrees from Seoul National University, Seoul, Korea, in 1996 and 1998, respecti vely. In 1998, he joined Samsung Advanced Institute of Technology ( SAIT), where he mainly worked on RF MEMS (RadioFrequency Micro-Electro-Mechanical-System s) applications. Since 2005, he has been pursuing the Ph.D. degree in electrical and com puter engineering at the University of Florida, Gainesville. His research interest s are in the design and analysis of millimeterwave and sub-terahertz integrated circuits in CMOS (Complementary Metal Oxide Semiconductor). He is a member of Et a Kappa Nu (HKN) and Tau Beta Pi (TBP).