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Techniques for crystalless operation of wireless inter-chip data communication systems

Permanent Link: http://ufdc.ufl.edu/UFE0041973/00001

Material Information

Title: Techniques for crystalless operation of wireless inter-chip data communication systems
Physical Description: 1 online resource (142 p.)
Language: english
Creator: Oh, Kyujin
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2010

Subjects

Subjects / Keywords: antenna, ber, cdr, crstalless, duplexing, receiver, transceiver, transmitter, vco, wireless
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Use of wireless inter-chip data communication to isolate return paths of high voltage motor drive sections and a low voltage digital control section in an engine controller board of a Hybrid Electric Vehicle (HEV) is presented. The return voltage levels can differ by several hundreds of volts. Presently, the board utilizes numerous photo-couplers that can support ~1 Mbps data rate. Use of conventional radio architecture for this application requires a frequency reference for each high voltage section. This increases cost and board area that makes the approach impractical. Cost effectively providing frequency reference and clock is a fundamental challenge in two way wireless inter-chip communication systems for this type of isolation applications. A fully integrated merged 400-Mbps clock data recovery (CDR) local oscillator (LO) generation circuit which provides both 24-GHz LO signal for a TX and 400-MHz clock for a RX has been demonstrated in a 130-nm foundry CMOS process. A voltage controlled oscillator (VCO) operation at higher than the input data rate at 400Mbps by using a divider (divide-by-60) in the feedback loop enables generation of 24-GHz LO signal for TX and integration of an LC-VCO that uses an inductor with practical size and Q. Including the divider in the feedback loop provides additional degree of freedom for reducing the size of loop filter capacitors for integration. The jitter performance of recovered clock at 400MHz is the lowest among fully integrated CDR?s with the similar data rate (~400Mbps) in the literature. The phase noise of LO signal generated in a CDR with a PRBS 231-1 input is ~10dB worse than that with a clock input. A fully integrated FDMA TX chain at motor side incorporating a CDR, an up conversion mixer, a power amplifier, an IF-generator and an attenuator is demonstrated in the UMC 130-nm CMOS technology. The TX output powers range from the minimum of -4.6dBm to the maximum of 2.3dBm. The target output power is 0dBm. The increased phase noise of LO generated by a CDR does not degrade the performance of ASK systems using a square law detector in the receiver. It should also be possible to use the LO for wide bandwidth systems with other low order modulation schemes. The feasibility of establishing a wireless link within the controller board is also demonstrated using the TX. This indicates that a TX integrated with an RX incorporating a CDR can bypass the need for an external frequency reference. The wireless link demonstration on the board suggests communication range of 15cm should be possible. TX consumes ~192mW of power. An entire RX chain including a new differential baseband amplifier is demonstrated. The RX chain has IP1dB of -45dBm and sensitivity of ~-45dBm for BER of 10^-12 and 400-Mbps data rate. Furthermore, full-duplex operations of TRX at motor side with an on-chip antenna are investigated by comparing BER performance of RX chain and RMS jitter of recovered clock with TX on and off. The BER degradation due to the TX turned on is small when the input power is sufficiently large to achieve BER of less than 10^-12. RMS jitters of recovered clock increase by no more than ~1ps from ~2.5ps when TX is turned on. These suggest the feasibility of full-duplex operation for CMOS radios with an on-chip antenna. The receiver is also used to detect multi-level AM signals.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Kyujin Oh.
Thesis: Thesis (Ph.D.)--University of Florida, 2010.
Local: Adviser: O, Kenneth K.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2011-08-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2010
System ID: UFE0041973:00001

Permanent Link: http://ufdc.ufl.edu/UFE0041973/00001

Material Information

Title: Techniques for crystalless operation of wireless inter-chip data communication systems
Physical Description: 1 online resource (142 p.)
Language: english
Creator: Oh, Kyujin
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2010

Subjects

Subjects / Keywords: antenna, ber, cdr, crstalless, duplexing, receiver, transceiver, transmitter, vco, wireless
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Use of wireless inter-chip data communication to isolate return paths of high voltage motor drive sections and a low voltage digital control section in an engine controller board of a Hybrid Electric Vehicle (HEV) is presented. The return voltage levels can differ by several hundreds of volts. Presently, the board utilizes numerous photo-couplers that can support ~1 Mbps data rate. Use of conventional radio architecture for this application requires a frequency reference for each high voltage section. This increases cost and board area that makes the approach impractical. Cost effectively providing frequency reference and clock is a fundamental challenge in two way wireless inter-chip communication systems for this type of isolation applications. A fully integrated merged 400-Mbps clock data recovery (CDR) local oscillator (LO) generation circuit which provides both 24-GHz LO signal for a TX and 400-MHz clock for a RX has been demonstrated in a 130-nm foundry CMOS process. A voltage controlled oscillator (VCO) operation at higher than the input data rate at 400Mbps by using a divider (divide-by-60) in the feedback loop enables generation of 24-GHz LO signal for TX and integration of an LC-VCO that uses an inductor with practical size and Q. Including the divider in the feedback loop provides additional degree of freedom for reducing the size of loop filter capacitors for integration. The jitter performance of recovered clock at 400MHz is the lowest among fully integrated CDR?s with the similar data rate (~400Mbps) in the literature. The phase noise of LO signal generated in a CDR with a PRBS 231-1 input is ~10dB worse than that with a clock input. A fully integrated FDMA TX chain at motor side incorporating a CDR, an up conversion mixer, a power amplifier, an IF-generator and an attenuator is demonstrated in the UMC 130-nm CMOS technology. The TX output powers range from the minimum of -4.6dBm to the maximum of 2.3dBm. The target output power is 0dBm. The increased phase noise of LO generated by a CDR does not degrade the performance of ASK systems using a square law detector in the receiver. It should also be possible to use the LO for wide bandwidth systems with other low order modulation schemes. The feasibility of establishing a wireless link within the controller board is also demonstrated using the TX. This indicates that a TX integrated with an RX incorporating a CDR can bypass the need for an external frequency reference. The wireless link demonstration on the board suggests communication range of 15cm should be possible. TX consumes ~192mW of power. An entire RX chain including a new differential baseband amplifier is demonstrated. The RX chain has IP1dB of -45dBm and sensitivity of ~-45dBm for BER of 10^-12 and 400-Mbps data rate. Furthermore, full-duplex operations of TRX at motor side with an on-chip antenna are investigated by comparing BER performance of RX chain and RMS jitter of recovered clock with TX on and off. The BER degradation due to the TX turned on is small when the input power is sufficiently large to achieve BER of less than 10^-12. RMS jitters of recovered clock increase by no more than ~1ps from ~2.5ps when TX is turned on. These suggest the feasibility of full-duplex operation for CMOS radios with an on-chip antenna. The receiver is also used to detect multi-level AM signals.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Kyujin Oh.
Thesis: Thesis (Ph.D.)--University of Florida, 2010.
Local: Adviser: O, Kenneth K.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2011-08-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2010
System ID: UFE0041973:00001


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TECHNIQUES FOR CRYSTALLESS OPERATION OF WIRELESS INTER-CHIP DATA
COMMUNICATION SYSTEMS





















By

KYUJIN OH


A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

2010


































2010 Kyujin Oh

































To my family









ACKNOWLEDGMENTS

I would like to begin by thanking my advisor, Professor Kenneth K. O, whose constant

encouragement and patient guidance provided a clear path for my research. I would also like to

thank Dr. Gijs Bosman, Dr. William Eisenstadt and Dr. Nam Ho Kim for helpful suggestions and

serving on the Ph.D. committee.

I would like to thank the former SiMICS members Yanping Ding, Eunyoung Seok,

Kwangchun Jung, Chikuang Yu, Haifeng Xu, Jau-Jr Lin, Changhua Cao, Yu Su and Shashank

Nallani Kiron. I have been quite fortunate to have worked with my colleagues Swaminathan

Sankaran, Hsinta Wu, Dongha Shim, Tie Sun, Ruonan Han, Wuttichai Lerdsitomboon, Chuying

Mao, Dr. Choongyul cha, Kyungsun Seol and Ning Zhang. The discussions with them and their

advice were immensely helpful for completing this work.

Much appreciation goes to TOYOTA Motor Corporation for funding this work. My special

thanks go to Eric Schwartz at Agilent Technologies for help in BER measurements and Al

Ogden for bonding and dicing chips. I would also like to acknowledge Dr. Hyeopgoo Yeo and

Dr. Jonksick Ahn for helpful technical discussions.

I am deeply grateful to my family for their unconditional love, guidance, encouragement,

and support which are the source of my strength. I dedicate this work to my family.









TABLE OF CONTENTS

page

A CK N O W LED G M EN T S ........... ... ............... ............................ ............... .....................4

L IST O F T A B L E S .......... .... ......................................................................................... 7

L IST O F FIG U R E S ............................................................................... 8

A B ST R A C T ........ .. ................ ... ................................................................................... 14

CHAPTER

1 WIRELESS INTERCONNECTS IN ENGINE CONTROLLER BOARDS .........................16

1 .1 In tro d u ctio n ............... ... ......... ............................................................................................ 16
1.2 System Overview........... .... .......................................17
1.3 O organization of D issertation.................................................. ............................... 22

2 OVERVIEW OF CLOCK AND DATA RECOVERY CIRCUIT.....................24

2 .1 In tro d u ctio n ............. ......... ...... ...... ......... ................... ................ 2 4
2.2 Non Return to Zero (NRZ) Test Pattern ................................................ ...............25
2.3 Clock and D ata Recovery (CDR) Overview ........................................ .....................27
2.3.1 Linear Phase Detector for Random Data................... .................................. 27
2.3.2 L near M odel of C D R ......... ........................... ...... .................... ............... 31
2.3.3 Choosing a B andw idth of CD R ........... ................ ........................ ............... 35
2 .4 S u m m a ry ............... ..... ..................................................................................................... 3 7

3 CLOCK AND DATA RECOVERY CIRCUIT AS AN LO GENERATOR ......................38

3 .1 In tro d u ctio n .............................. .............. .. ................... ................ 3 8
3.2 New CDR Structure ................. .............................. ............... ........... 38
3.2.1 Loop Filter .................................................... ...............40
3.2.2 V oltage Controlled O scillator (V CO ) ........................................ .....................41
3.2.3 D ivider Chain (D ivide-by-60) ........................................... ......................... 42
3.2.4 Phase D detector .................................................... .......... .............. .. 43
3.2.5 Charge Pump (CP)............... ...... ........................... .....45
3.3 Simulation Results ....................................................... ........... .. ............46
3.4 M easurem ent Results .................. ................................................................. ........ 49
3.5 The Influence of Phase Noise of CDR on ASK Modulation................ ............... ....56
3 .6 C on clu sion ...................................... ................................... ................ 59

4 FDMA TRANSMITTER AT MOTOR SIDE....................................................................61

4.1 Introduction ................... ..................................................................... .. 61
4.2 Evolution of Transmitter at M otor Side............................ .. ............................... 61









4.3 Circuit Topology of Transmitter at M otor Side.................................... ............... 63
4.3.1 IF Generator........................................... 64
4.3.2 8-to-1 Multiplexer and Attenuator................................. ...............68
4.3.3 Three Stage L O B uffer ..................................... ............................................. 69
4.3.4 U p-conversion M ixer.................. ... ...... ....................................... ............... 70
4.3.5 Pow er A m plifier ......... .. .. .......... .................... .. ...... .. ............ 72
4.4 Measurement Results of IF Generator................................................... ...............74
4.5 M easurem ent R results of TX Chain................................................. ............... .... 78
4.5.1 Spectrum of TX Output and Harmonic Control ................................................. 78
4.5.2 ASK Modulation (Carrier at 26GHz Amplitude-modulated by 25MHz
M odulating Square Signal) ........................................ .... ........ ................................84
4.5.3 ASK Modulation (Carrier at 26GHz Amplitude-modulated by 50Mbps PRBS
231 M odulating Signal) ............................ .. .... ............................ .............. 87
4.5.4 Wireless Link Test at the Motor TX ............... ..... .......... ............... 89
4.6 C conclusion ......... ... ...... ......... ................................... ..........................9 1

5 DUPLEX OPERATION AND LINK DEMONSTRATION ...........................................92

5.1 Introdu action ................................................................................................................. 92
5.2 A Differential Baseband Amplifier ............................................................................ 94
5.2 .1 C circuit D description .............................. ......................... ... ...... .... ..... ...... 94
5.2.2 M easurem ent R esults............................... ... ........................................ 97
5.3 Measurement Results of Full RX Chain for Motor Section .................................100
5.4 Duplex Operation of TRX at Motor Side ............................................................ 106
5.4.1 Characterization of RX with TX On and Off .................................................. 107
5.4.2 Characterization of RX with TX On and Off using the Chip without Laser Cut. 112
5.4.3 Wireless Demonstration of Duplex Operation at Motor Side ............................1114
5.5 Detection of M multiple Level ASK Signal ............................................ ......... ...... 115
5 .6 C o n clu sio n s....................................................... ................ 12 2

6 SUM M ARY AND FUTURE W ORK ...................................................................... ...... 124

6 .1 S u m m a ry ................................................................................................................... 12 4
6.2 F utu re W ork ......................................................125

APPENDIX

A C D R TE ST STR U C TU R E ....................................................................... ......................126

B SPECTRUM OF TX OUTPUT WITH AN EXTERNAL IF SIGNAL SOURCE ...............133

L IST O F R E F E R E N C E S .................................................................................. ..................... 136

BIOGRAPHICAL SKETCH ............................................................. ........... 142









LIST OF TABLES


Table page

1-1 Frequency plans for transmitter and receiver at the motor side......................................19

1-2 Frequency plan for transmitter and receiver at deadtime controller..............................20

1-3 Link m argin analysis for FD M A ............................ .................. .............................. 22

1-4 L ink m argin analysis for C D M A ............................................................ ...... ...............22

2-1 Sum m ary ofjitter specification ............................................................... .....................36

3-1 Summary of measured CDR performance................................... ...............54

3-2 Com prison of jitter perform ance........................................................... ............... 55

4 -1 IF sig n al g en eration ........ ............................................................................ ...... ............... 6 5

4-2 Simulated power consumption in TX at motor node.............. .... .................73

4-3 Simulated and measured duty cycle of IF signals..................................77

4-4 Summary of TX output power level at motor side .................................... ...............79

4-5 Power consumption of transmitter at motor side..... .................................91

5-1 Summary of measurement results of baseband amplifier.................. ...... ............. 100

5-2 Summary of RX chain measurement results.............................................................106

5-3 Summary of measured jitter performance..................................................................... 110

5-4 Summary of measured BER performance of RX chain at motor side.............................111

5-5 Summary of measured RMS jitter and BER performance ............................................ 113

A-1 Summary of measured CDR performance....................................................................132

B-1 Summary of TX output power level at motor side with an external IF signal source .....133









LIST OF FIGURES


Figure page

1-1 Engine controller board for a HEV. Dl and D2 communicate with M1-M6 and
M7-M12, respectively (Courtesy of TOYOTA). ................................... .....................18

1-2 Signaling scheme for the up (FDMA) and down (CDMA) links. ....................................19

1-3 Frequency bands and data rate in deadtime controller and motors............................... 19

1-4 Frequency plans for the transceiver at the motor side. ................... ................... .......... 20

1-5 Frequency plan for transceiver at deadtime controller side....................... ...............20

2-1 PRBS signal (a) waveform in time domain, (b) autocorrelation, and (c) power
spectral density in frequency domain [20] ............... ........ .............................. ....... ..26

2-2 B lock diagram of C D R .......................................................................... .....................27

2-3 A linear phase detector (a) block diagram, and (b) waveform under the locked
condition ........................................................ .................................28

2-4 Waveform of phase detector for (a) early clock and (b) late clock ................................28

2-5 Input-output characteristic of linear phase detector ........... .... ............... ................... 30

2-6 Input-output characteristic of tri-state phase and frequency detector (PFD) .....................30

2-7 Linear model of PLL based CDR circuit.... .................... ... ........ ................. 31

2-8 The 2nd order passive lead-lag filter (a) schematic and (b) transfer function ..................32

2-9 Bode plot of the open loop gain for a CDR circuit. ................... ................................ 34

2-10 Linear model of second order CDR and its jitter plot........... ............. ..............36

3-1 Block diagram of conventional CDR .................................... .................. ... ............ 39

3-2 Block diagram of new CDR ....................... ........................................ ............... 39

3-3 Schematic of the 24GHz LC VCO................................................... ...................... 42

3-4 Block diagram of divider chain (divide-by-60). ..................................... ............... 43

3-5 Block diagram of divide-by-2 and implementation of latch circuit..............................43

3-6 Block diagram of (a) phase detector and (b) implementation of each DFF using
D CV SL logic circuits ............................................ ........... ... ... ............ 44









3-7 Schem atic of charge pum p ......................................... .... ............................ ..................45

3-8 Plot of current mismatch between up and down current in the charge pump....................46

3-9 Simulated VCO tuning range plot with 3-bit digital control for coarse tuning. ................47

3-10 Simulated CDR settling behavior at the VCO control voltage.......................................48

3-11 Input data signal versus recovered clock under the locked condition. ...........................48

3-12 Die photograph of 24GHz CDR. ....... ..........................................................49

3-13 Measured tuning range plot with 3 bits digital control for coarse tuning........................50

3-14 VCO tuning range and gain at digital bits 111. ..................................... ............... 50

3-15 Jitter histogram of the recovered clock at 400MHz for a PRBS 231-1 input.....................51

3-16 Spectrum of the recovered clock at 24GHz for a PRBS 231-1 input ..............................52

3-17 Spectrum of 400Mbps PRBS 2n-1 signal (top), PNRZ signal after edge detection in
the phase detector (middle), and recovered clock at 24GHz (bottom). ..........................52

3-18 Phase noise plot of the recovered clock at 24GHz for a PRBS 27-1 input ...................53

3-19 Phase noise plot of the recovered clock at 24GHz for a PRBS 231-1 input ..................53

3-20 Plots of (a) amplitude and (b) phase spectra for x(t) and corresponding waveform (c)
in tim e dom ain. ..................................................................58

4-1 Block diagram of original transceiver at a motor section ............................................62

4-2 Block diagram of transmitter at motor side. ............... ............................................ 62

4-3 Block diagram of the interface between a CDR and a mixer. ............... ...............63

4-4 B lock diagram of IF generator .......................................... ..................... .... .......... ... 64

4-5 Block diagram and waveform of(a) divide-by-2.5 and (b) divide-by-1.5 .......................66

4-6 Block diagram of (a) DETFF and schematic of (b) MUX, (c) LATCH, and (d) AND
p lu s L A T C H .......................................................................... 6 7

4-7 Block diagram of 8-to-1 MUX and attenuator ............... .......................................68

4-8 Schem atic of capacitor bank. ...................................................................... ..................68

4-9 Schem atic of three stage LO buffer. ................................................................................70









4-10 Schem atic of up-conversion m ixer. ..................................................................................71

4-11 Generation of undesired interferers by mixing harmonics of IF signal with LO signal....72

4-12 Schem atic of pow er am plifier ........................................ .............................................73

4-13 Die photograph and testing PC board of IF generator. ............................................. 74

4-14 Spectrum and waveform of IF signals at (a) 400MHz, (b) 800MHz, (c) 1.2GHz, (d)
1.5GHz, (e) 2.0GHz, (f) 2.4GHz, and (g) 3.0GHz. ................................... ..................... 75

4-15 Generation of undesired interferers due to the mixing of 2nd, 3rd, and 5th order
harm onics of IF signals w ith LO signal ........................................ ......................... 77

4-16 Die photograph of crystalless transceiver at motor section. ............................................78

4-17 Block diagram of transmitter at motor side. ..... ...............................................79

4-18 Spectrum of TX m otor 1 with attenuator ........................................ ....................... 80

4-19 Spectrum of TX motor 1 without attenuator............................ ..... ................. 80

4-20 Zoom ed-in spectrum of TX m otor 1............................................................................ 81

4-21 Spectrum of TX m otor 2 with attenuator ........................................ ....................... 82

4-22 Spectrum of TX motor 2 without an attenuator. ...................................... ............... 82

4-23 Spectrum of TX m otor 3 with attenuator ........................................ ....................... 83

4-24 Spectrum of TX motor 3 without attenuator ..................................... ........ ............... 84

4-25 The impact of interferer signals on desired channels with attenuator on. .........................84

4-26 Waveform and spectrum of (a) un-modulated carrier and (b) ASK modulated carrier.....85

4-27 Waveform and spectrum of square wave with 50% duty cycle.................. ...............85

4-28 Spectrum of TX output at motor 5 (26GHz) before and after ASK modulation with
25-MHz square signal. .................................................................. 86

4-29 Waveform of TX output at motor 5 after ASK modulation with 25-MHz square
sig n a l. ........ ........ ............................................................................ 8 7

4-30 Spectrum of TX output at motor 5 before and after the ASK modulation with
50M bps PR B S 231-ldata signal. ............................................................. .....................88

4-31 Eye diagram output at motor 5 after ASK modulation with a 50Mbps PRBS 231-1
d ata sig n al. ............................................................. ................ 8 8









4-32 Setup of wireless link demonstration at TX motor side................... ..........................89

4-33 Spectrum of TX output (a) before modulation (b) after ASK modulation with 25-
MHz square clock signal. (c) Waveform of TX output after ASK modulation with
25MHz square clock signal. (d) Spectrum of received 26-GHz carrier signal
amplitude modulated by 25-MHz square signal (with metallic cover)............................90

5-1 Block diagram of receiver chain at motor section. ..... .................... ........... ............ 92

5-2 Positive feed back path due to parasitic inductors in multistage single-ended
amplifiers. ................................................. 93

5-3 Schem atic of baseband am plifier. ........................................ .........................................95

5-4 Schematic of the wide-swing cascode current mirror....................................................96

5-5 Die photograph and baseband amplifier PC board for testing ........................................97

5-6 Waveform of a single-ended square wave input at 200MHz. Differential outputs
when input voltage level is (a) 6.8mVpp, (b) 20mVpp and (c) 30mVpp. .............................99

5-7 Measured 3-dB bandwidth of baseband amplifier in frequency domain .........................100

5-8 Block diagram of RX chain at motor section and measurement setup...........................101

5-9 RX output power as function of input single sideband power and input carrier power
(A M m odulation index of 100% )......................................................................... ..... 102

5-10 M measured BER versus input power...... ............................................................ 103

5-11 Plots of (a) Amplitude modulated 16.8-GHz carrier with 200-MHz square wave at
LNA input. (b) Spectrum of demodulated 200MHz signal at BB output. (c)
Waveforms of demodulated 200MHz signal at BB output and 400MHz recovered
clock at CDR output. (d) Jitter histogram of recovered clock at 400MHz........ .........104

5-12 Plots of (a) Amplitude modulated 16.8-GHz carrier with 400-Mbps PRBS 231- at
LNA input. (b) Spectrum of demodulated 400Mbps signal at BB output. (c)
Waveforms of demodulated 400Mbps signal at BB output and 400MHz recovered
clock at CDR output. (d) Jitter histogram of recovered clock at 400MHz........ .........105

5-13 Block diagram of TRX at motor section and measurement setup ................................. 107

5-14 Spectrum of demodulated baseband signal in RX when (a) TX is off, (b) TX is on
and a modulating signal for TX is a 50-MHz clock, and (c) TX is on and a
modulating signal for TX is a 50-Mbps PRBS 27-1 signal. The plots on the right side
are the zoom ed-in plots............... ........................ ... .... ..... .. .. ............ 108









5-15 RMS jitter plots of recovered clock with and without turning on TX for (a) 200-MHz
square clock, (b) 400-Mbps PRBS 27-1, (c) 400-Mbps PRBS 223-1, and (d) 400Mbps
PRB S 231-1 m odulating signal for RF input. ............................ ..... ......... ................110

5-16 BER plots (a) 400-Mbps PRBS 27-1 modulation signal for RF input with TX on and
off, (b) 400-Mbps PRBS 231-1 with TX on and off, (c) TX on with 400-Mbps PRBS
27-1 and 231-1 modulation signal, and (d) TX off with 400-Mbps PRBS 27-1 and
2311 ........................................................................... 111

5-17 RMS jitter plots at RF input power of -47dBm with TX on and off for (a) 200MHz
square clock, (b) 400Mbps PRBS 27-1, (c) 400Mbps PRBS 223-1, and (d) 400Mbps
PRBS 231-1. The connection between the LNA and duplexer is not laser cut...............113

5-18 BER plots at RF input power of -47dBm for (a) 400Mbps PRBS 27-1 with TX on
and off, and (b) 400Mbps PRBS 231-1 with TX on and off. The connection between
LN A and duplexer is not laser cut. ........................................................................ .... 114

5-19 Measurement setup for the duplex operation of TRX at motor side.............................1.14

5-20 Spectrum of both RX and TX band at motor side ....................... ................115

5-21 Measurement set up for link demonstration and block diagrams of TX and RX ............116

5-22 Waveform of (a) amplitude modulated signal by a 400Mbps pattern 060606 at TX
output, (b) demodulated signal at BB out, and recovered clock at CDR output with
total 39dB attenuation between the PA output and LNA input ..................................... 117

5-23 Waveform of (a) amplitude modulated signal by a 400Mbps pattern 01506250 at TX
output, (b) demodulated signal at BB out, and recovered clock at CDR output with
total 39dB attenuation between the PA output and LNA input ..................................... 118

5-24 Waveform of (a) amplitude modulated signal by a 400-Mbps 060606 pattern at TX
output, (b) demodulated signal at BB out, and recovered clock at CDR output with
total 20dB attenuation between the PA output and LNA input ..................................... 118

5-25 Waveform of (a) amplitude modulated signal by a 400-Mbps 01506250 pattern at
TX output, (b) demodulated signal at BB out, and recovered clock at CDR output
with total 20dB attenuation between the PA output and LNA input.............................119

5-26 Waveform of demodulated signal (varying amplitude levels 01506250) at BB output
when the data rate of modulating signal is (a) 200Mbps and (b) 100Mbps with total
20dB attenuation between the PA output and LNA input. ..............................................119

5-27 Waveform of (a) amplitude modulated signal by a 400-Mbps 0241353246 pattern at
TX output, (b) demodulated signal at BB output, and recovered clock at CDR output
with total 20dB attenuation between the PA output and LNA input ............................121









5-28 Waveform of demodulated signal (varying amplitude levels 0241353246) at BB
output when the data rate of modulating signal is (a) 200Mbps and (b) 100Mbps with
total 20dB attenuation between the PA output and LNA input ............ ................122

5-29 Jitter histogram of (a) demodulated signal at BB out and (b) recovered clock at CDR
output for a modulating signal at 400Mbps with total 20dB attenuation between the
PA output and LN A input ............................................................................... ....... 122

A-i Block diagram of CDR test structure ..................................................... ............. 126

A-2 Schematic of the 5.84GHz LC VCO.............. ..... ........................ 127

A-3 Die photograph of 5.84GHz CDR. .................................... 129

A-4 Photograph of CDR testing printed circuit board. .................................................... 129

A-5 Plot of VCO tuning range and gain at digital bits 0000000 ........................................... 130

A-6 Plot of recovered clock at 365MHz and jitter histogram for a PRBS 231-1....... ........ 131

A-7 Spectrum of recovered clock at 5.84GHz for a PRBS 231-1 input signal.....................131

A-8 Plot of phase noise of recovered clock at 5.84GHz for a PRBS 231-1 input signal ........132

B-1 Measurement setup for the transmitter at motor side using an external IF source. ........133

B-2 Spectrum of TX motor 1 driven with an external IF signal source ............................. 134

B-3 Zoomed-in spectrum of TX motor 1 driven with an external IF signal source. ............134

B-4 Spectrum of TX motor 7 driven with an external IF signal source ............................. 135

B-5 Zoomed-in spectrum of TX motor 7 driven with an external IF signal source. ............135









Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy

TECHNIQUES FOR CRYSTALLESS OPERATION OF WIRELESS INTER-CHIP DATA
COMMUNICATION SYSTEMS

By

Kyujin Oh

August 2010

Chair: Kenneth K. O
Major: Electrical and Computer Engineering

Use of wireless inter-chip data communication to isolate return paths of high voltage motor

drive sections and a low voltage digital control section in an engine controller board of a Hybrid

Electric Vehicle (HEV) is presented. The return voltage levels can differ by several hundreds of

volts. Presently, the board utilizes numerous photo-couplers that can support -1 Mbps data rate.

Use of conventional radio architecture for this application requires a frequency reference for

each high voltage section. This increases cost and board area that makes the approach

impractical. Cost effectively providing frequency reference and clock is a fundamental challenge

in two way wireless inter-chip communication systems for this type of isolation applications.

A fully integrated merged 400-Mbps clock data recovery (CDR) local oscillator (LO)

generation circuit which provides both 24-GHz LO signal for a TX and 400-MHz clock for a RX

has been demonstrated in a 130-nm foundry CMOS process. A voltage controlled oscillator

(VCO) operation at higher than the input data rate at 400Mbps by using a divider (divide-by-60)

in the feedback loop enables generation of 24-GHz LO signal for TX and integration of an LC-

VCO that uses an inductor with practical size and Q. Including the divider in the feedback loop

provides additional degree of freedom for reducing the size of loop filter capacitors for

integration. The jitter performance of recovered clock at 400MHz is the lowest among fully









integrated CDR's with the similar data rate (-400Mbps) in the literature. The phase noise of LO

signal generated in a CDR with a PRBS 231-1 input is -10dB worse than that with a clock input.

A fully integrated FDMA TX chain at motor side incorporating a CDR, an up conversion

mixer, a power amplifier, an IF-generator and an attenuator is demonstrated in the UMC 130-nm

CMOS technology. The TX output powers range from the minimum of-4.6dBm to the

maximum of 2.3dBm. The target output power is OdBm. The increased phase noise of LO

generated by a CDR does not degrade the performance of ASK systems using a square law

detector in the receiver. It should also be possible to use the LO for wide bandwidth systems with

other low order modulation schemes. The feasibility of establishing a wireless link within the

controller board is also demonstrated using the TX. This indicates that a TX integrated with an

RX incorporating a CDR can bypass the need for an external frequency reference. The wireless

link demonstration on the board suggests communication range of 15cm should be possible. TX

consumes ~192mW of power.

An entire RX chain including a new differential baseband amplifier is demonstrated. The

RX chain has IP1dB of -45dBm and sensitivity of -45dBm for BER of 10-12 and 400-Mbps data

rate. Furthermore, full-duplex operations of TRX at motor side with an on-chip antenna are

investigated by comparing BER performance of RX chain and RMS jitter of recovered clock

with TX on and off. The BER degradation due to the TX turned on is small when the input

power is sufficiently large to achieve BER of less than 10-12. RMS jitters of recovered clock

increase by no more than l-ps from ~2.5ps when TX is turned on. These suggest the feasibility

of full-duplex operation for CMOS radios with an on-chip antenna. The receiver is also used to

detect multi-level AM signals.









CHAPTER 1
WIRELESS INTERCONNECTS IN ENGINE CONTROLLER BOARDS

1.1 Introduction

Design of an interface in engine controller board of a Hybrid Electric Vehicle (HEV) [1]-

[4] where high voltage motor drive sections and a low voltage digital control section coexist is

challenging. The return voltage levels for the sections can differ by greater than 300 volt (V).

Presently, the two sections have been electrically isolated using photo-couplers to protect the low

voltage section from overvoltage damages. However, the use of more than 10 photo couplers

increases cost not to mention the low data transmission rate of less than IMpbs. In order to

replace photo-couplers used in the hybrid engine controller board, silicon based solutions have

been utilized to suggest the feasibility to lower cost and increase data rate.

As an alternative to photo-coupler, an electronic isolator that isolates the ground level of

high and low voltage sections by coupling signals has been investigated. Several isolators using

capacitive coupling method in silicon on insulator (SOI) technology are reported in [5]-[7]. The

isolator can achieve 2.3kV ac isolation and 100-MHz signal transmission in an area of 1.5mm2

[7]. This approach, however, requires a large external coupling capacitor. The electronic isolator

can also be realized using inductive coupling [8]. Such an isolator implemented in 130-nm

CMOS technology achieves only 70-V DC isolation due to the low breakdown voltage which is

not suitable for the hybrid engine controller board.

Wireless interconnects using single chip radios including an on-chip antenna can be

another lower cost, and high data rate (faster than 100's of Mbps) alternative to the photo-

couplers. Unlike the others, it can be fully realized in foundry CMOS. An on-chip antenna is a

key block to implement this. On-chip antennas have been extensively studied [9], [10] in both

indoor and outdoor environment and integrated in a 20-GHz down converter [11] and a 24-GHz









transmitter [12] for wireless communication. The feasibility of on-chip antennas used for

wireless communication in the hybrid engine controller board has been verified [8].

Two separate integrated wireless transceiver circuits can operate with two different ground

potentials to handle the large voltage difference. Use of wireless interconnects can also reduce

the PC board area by removing metal traces for making connections from and to the photo-

couplers. The frequency bands and channels can be allocated without satisfying the emission

rules of the Federal Communications Commission (FCC) because the board is contained inside a

metallic cover. Incidentally, wireless interconnects using ZigBee could be another wireless

solution. However, ZigBee supports very low data rate and requires external crystal references

for implementation.

1.2 System Overview

Figure 1-1 shows a hybrid engine controller board with two low voltage control nodes (D1,

D2) and 12 high voltage motor nodes (M1-M12). Control nodes Dl and D2 called deadtime

controllers located at the low voltage section transmit phase information to six motor drivers

M1-M6 or M7-M8 in the high voltage sections. The fault status of each driver is transmitted

back to the deadtime controller. There are also two links that transmit the motor temperature to

the deadtime controller. Among multiple access schemes, Code Division Multiple Access

(CDMA) [13] is chosen for downlink from a deadtime controller to each of 6 motors. For a data

rate of 50Mbps per channel, spreading spectrum is achieved by multiplying 8-bit Walsh codes

with each data bits, which results in a chip rate of 400Mcps per channel. Total 6 encoded

waveforms for motor 1-6 are added together in time domain and formed multi-level signal with

a chip rate of 400Mcps for transmission [8]. The deadtime controller needs only one transmitter

to support the six channels, thereby dramatically reducing RF circuit complexity. For an uplink

from the motor to the deadtime controller, Frequency Division Multiple Access (FDMA) is









chosen. Each of two deadtime controllers has a CDMA transmitter and a FDMA receiver

supporting 7 channels. Each of six motors has a CDMA receiver and a FDMA transmitter.


















Figure 1-1. Engine controller board for a EV. D and D2 communicate with M M6 and
M10 M11 M12







25cm

Figure 1-1. Engine controller board for a HEV. DI and D2 communicate with M1~M6 and
M7-M12, respectively (Courtesy of TOYOTA).

Figures 1-2 and 1-3 show signaling scheme for the up and down links and frequency bands

in the transmitter and receiver, respectively. The transmission and reception bands are separated

by 6GHz to improve isolation between the two bands. The system requires duplex operation with

a data transmission rate of 400Mcps from the low voltage digital control section to the high

voltage motor drive section and a data transmission rate of 50Mbps from the high voltage motor

to the deadtime controller in the low voltage section. The transmission from the low voltage

section utilizes a 15.6-18GHz band and the transmission from the high voltage section utilizes a









24.2-27.2GHz. More detailed system .- : :. .::: :: can be found in [14]. The f- :::- :: 1.:: of

transmitter and the receiver at the motor side are summarized in Table 1-1 and depicted in Figure

1-4. In addition, the frequency plans of transmitter and receiver at the deadtime controller side

are summarized in Table 1-2 and shown in Figure 1-5.

FDMA- Ch7
-A 1 Motor
Deadtime Temp.
S Controller Tep.


Figure 1-2. ":


.. .:. scheme for the up i ii :'.: i ) and down (: i ': i ) links.


Deadtime
Controller

Low voltage
section
- -_-_-_ -


24.2GHz~
27.2GHz

(50Mbps)

15.6GHz
~18GHz

(400Mcps)


Motor
Drivers

High voltage
section


Figure 1-3. F,: ::.:: bands and data rate in deadtime controller and motors.

Table 1-1. r: :: ... for transmitter and receiver at the motor side
TX channel Freq. Band RX Freq. Band
(GHZ) channel (GHz)
1 24.2-24.6 1 15.6-18.0, C1
2 24.6-25.0 2 15.6-18.0, C2
3 25.0-25.35 3 15.6-18.0, C3
Motor 4 25.35-25.7 4 15.6-18.0, C4
5 25.8-26.2 5 15.6-18.0, C5
6 26.2-26.6 6 15.6-18.0, C6
7 26.8-27.2


Chip
1
2
3
4
5
6
7










FDMA TX bands (24.2 GHz 27.2 GHz) at motor section


I I I I I I
S 24.4 24.8 25.2 25.5 26.0 26.4


CDMA RX bands (15.6 GHz 18 GHz) '**.. -6GHz isolation between RX & TX bands
at motor section


CDMA RX bands


Figure 1-4. Frequency plans for the transceiver at the motor side.


Table 1-2. Frequency plan for transmitter and receiver at deadtime controller
TX c l Freq. Band RX Freq. Band C
(GHZ) channel (GHz)


Deadtime
controller


15.6-18.0, C1
15.6-18.0, C2
15.6-18.0, C3
15.6-18.0, C4
15.6-18.0, C5
15.6-18.0, C6


24.2-24.6
24.6-25.0
25.0-25.35
25.35-25.7
25.8-26.2
26.2-26.6
26.8-27.2


FDMA RX bands (24.2 GHz 27.2 GHz) at deadtime
controller section
f* "^


24.4 24.8 25.2 25.5 26.0 26.4 27.0


CDMA TX bands (15.6 GHz 18 GHz) '"*.. ~6GHz isolation between TX & RX bands
at deadtime controller section


CDMA TX bands


Figure 1-5. Frequency plan for transceiver at deadtime controller side.


_ I I _


I









It should be noted that the frequency plans for motor 4 and motor 7 have been slightly

changed from the original one where the center frequency of motor 4 and motor 7 are located at

25.6GHz and 26.8GHz respectively. The frequency of motor 4 is shifted down by 100MHz and

motor 7 is shifted up by 200MHz in the updated frequency plan. This is because the 25.5GHz

and 27GHz are generated by mixing 24GHz with 1.5GHz and 3GHz intermediate frequencies

(IF) respectively. This is much simpler than mixing 24GHz with 1.6GHz and 2.8GHz. The IF-

frequency generation will be discussed in Chapter 4. Because of this change, the overall required

TX bandwidth at motor side or, equivalently, RX bandwidth at deadtime controller was changed

from 2.8GHz to 3GHz.

To evaluate the ability of system to detect the transmitted signal, with an acceptable error

probability, in the presence of noise, link budget analyses are necessary first step. For a

separation of 15cm, the link budget analysis for an individual channel of the FDMA links is

summarized in Table. 1-3. The output TX power is OdBm and propagation loss at 27GHz is

45dB. An on-chip dipole antenna on a 100-[m thick substrate has gain of-8 dB [15]. The

required Eb/No for BER of 10-13 of a system using non coherent ASK modulation is 14.5dB [16].

The bandwidth of RX is 50MHz and noise figure of RX is assumed 8dB. With all these

information taken into account, the required receiver sensitivity is -74.3dBm and link margin is

greater than 15dB for the FDMA link. The link budget analysis for CDMA is also shown in

Table 1-4, where sensitivity is -74.3dBm and link margin is 21.3dB.

Lastly, if these wireless links were implemented using conventional radio architecture, the

system would require 12 crystal references on motor nodes to provide TX LO signals. This

would make implementing a wireless interconnect system impractical due to increased cost. To









overcome this challenge, this dissertation research explored system and circuit techniques for

crystalless operation of wireless inter-chip data communication.

Table 1-3. Link margin analysis for FDMA
FDMA (From TX motor to RX deadtime controller)
Range (R) 15 cm
TX power 0 dBm
Propagation Loss @ 27 GHz (X/4nR) 2 45 dB
Antenna Gain (0.25k = 3.2 mm) -7 dB
Received power -59 dBm
Thermal Noise [kT (K)] -173.8 dBm/Hz
Bandwidth (50 MHz) 77 dB
Eb/No for BER of x10-13 for ASK 14.5 dB
RX noise figure 8 dB
Sensitivity -74.3 dBm
Link margin 15.3 dB

Table 1-4. Link margin analysis for CDMA
CDMA (From TX deadtime controller to RX motor)
Range (R) 15 cm
TX power (Total power -10dBm) 2 dBm
Propagation Loss @ 18 GHz (X/47nR)2 41 dB
Antenna Gain (0.25k = 3.2 mm) -7 dB
Received power -53 dBm
Thermal Noise [kT (K)] -173.8 dBm/Hz
Bandwidth (50 MHz) 77 dB
Eb/No for BER of x10-13 for ASK 14.5 dB
RX noise figure 8 dB
Sensitivity -74.3 dBm
Link margin 21.3 dB

1.3 Organization of Dissertation

The emphases of research are the design of clock and data recovery circuit, crystalless

transmitter in motor sections, investigation of the impact of full-duplex operation of TRX with

an on-chip antenna, and demonstration of a wireless link between TX at deadtime controller and

RX at motor side.

In Chapter 1, the system overview of wireless inter-chip data communication on an engine

controller board of hybrid electric vehicles (HEV) for signal return path isolation is presented.









Chapter 2 discusses the general properties of such data format as pseudo random binary sequence

(PRBS) that a CDR is typically used to characterize. Properties of a phase detector (PD) in

comparison to a phase frequency detector (PFD) are described. A linear model of CDR is

presented to evaluate the stability of the CDR loop. Finally, the choice of CDR loop bandwidth is

discussed.

Chapter 3 is dedicated to the proposed CDR design and measurement results. The circuit

design of each block making up the CDR and simulation results are described. A fully integrated

CDR based 24-GHz LO generation circuit is demonstrated in the UMC 130-nm CMOS

technology. Qualitative analysis for the impact of phase noise from the recovered clock to ASK

systems using a square-law detector is presented.

In Chapter 4, the circuit designs of all TX building blocks at motor side, which include an

up-conversion mixer, 3-stage LO buffers, IF generator, attenuator, 8-to-1 multiplexer, and power

amplifier are discussed. Compared to the original TX architecture, the new TX architecture

adopts a modified CDR structure described in Chapter 3, which enables the system to be simpler

and more power efficient. The stand-alone test structure of IF generator followed by an entire TX

chain supporting 7 different channels are characterized. Finally, the feasibility of establishing a

wireless link using the TX is demonstrated in the UMC 130-nm CMOS technology.

In Chapter 5, full RX chains with an improved baseband amplifier for the motor side are

fully characterized. The full-duplex operation of TRX at motor side with an on-chip antenna is

investigated by comparing BER performance of RX and RMS jitters of recovered clocks.

Finally, multiple level AM detection is demonstrated using the RX. The measurements indicated

that further work will be needed to make the RX fully support the multiple level signals. Finally,

the dissertation is summarized and future works are suggested in Chapter 6.









CHAPTER 2
OVERVIEW OF CLOCK AND DATA RECOVERY CIRCUIT

2.1 Introduction

Use of wireless interconnection to isolate the return paths of multiple high voltage motor

drive sections and low voltage digital control section in an engine controller board of a Hybrid

Electric Vehicle (HEV) is described in Chapterl. The system requires duplex operation with a

data transmission rate of 400Mbps from the low voltage digital control section to the high

voltage motor drive section and a data transmission rate of 50Mbps from a high voltage section.

Transmission from the low voltage section utilizes a 15.6-18GHz band and transmission from the

high voltage section utilizes a 24.2-27.2GHz band. The return level for these sections can differ

by several hundreds of volts. Use of conventional radio architecture for this application requires

a frequency reference for each high voltage section which increases cost and board area. To

mitigate this, the system has been architected so that the receiver and transmitter for the high

voltage motor sections require no external frequency reference.

The conventional LO generation scheme such as a phase lock loop (PLL) cannot be

adopted. Instead, clock and data recovery circuit (CDR) is used as a perfect candidate for internal

clock generation from incoming data, which is one of unique features of CDR. In the crystalless

transceiver architecture, the choice of non-coherent ASK detection as well as CDR obviates the

need for the use of external frequency references. Diode detection in RX removes a frequency

synthesizer and mixer drivers which simplify the RX and reduce the power consumption.

Furthermore, CDR internally recovers clocks, which can be viewed as the frequency reference

for the system if the jitter or phase noise of recovered clock can be kept to the minimum.

Chapter 2 describes the basics of clock and data recovery circuit (CDR). Among many

CDR structures, a phase locked loop (PLL) based CDR with a linear phase detector such as









Hogge detector [17] is emphasized. The serial data stream whose format is called "non-retum-to-

zero" is transmitted without an accompanying additional timing reference in many digital

systems. A receiver is then required to process this data stream and generate synchronous clock.

It is the CDR in the receiver that recovers the clock. Generally, a CDR first produces clock from

an internal VCO and then phase-aligns the clock to the transitions of incoming data stream with

the help of feed back loop in a PLL. The challenge of clock and data recovery is that data could

be a long sequence of ONEs or ZEROs without a transition. During a no-transition period, the

voltage controlled oscillator in the PLL may drift or vary in the clock frequency due to the

absence of additional correction signal provided by the feed back loop. To ensure frequent

transitions, coding schemes are often used.

In Chapter 2, the non return to zero data (NRZ) format is first described. A phase detector

suited to handle the data format is then introduced. A CDR loop analysis using a linear model for

determination of loop stability information by calculating phase margin is presented. Finally,

Chapter 2 describes how to choose the CDR bandwidth which is critical for improving the jitter

performance of CDR.

2.2 Non Return to Zero (NRZ) Test Pattern

NRZ test patterns [18] have been created for system test and verification in digital

communication systems. In NRZ signaling, the signal is either high (one) or low (zero) during

the entire bit period with equal probability regardless of the state of preceding bits. There is a

change in level whenever data change from a high to low or from a low to high. It is therefore

possible to have a binary sequence with a long string of consecutive ones or zeros. This situation

is referred as having "low transition density" [18]. Since low transition density data contain low

frequency contents, it is difficult to implement ac coupling function and to recover low jitter

clock.









It is difficult to generate a completely random binary sequence. Commonly used are

pseudo random binary sequences (PRBS) [19]. The PRBS is in fact deterministic and repeats. A

PRBS is typically expressed as a PRBS 2X-1, which creates a pattern 2x-1 bit long (called length,

L), that repeats every 2x-1 bits. The maximum run length defined by the number of maximum

consecutive ones or zeros is equivalent to X.


7bit pattern (L=7Tb) n 7 bits
S O loo I t = 1101 00111 0100111 0
(a) _o 11 n
Tb 2Tb 3Tb 4Tb 5Tb 6Tb 7Tb t -2L -L 0 L 2L t

Autocorrelation Autocorrelation Autocorrelation

y(z nL)
STb
(b) Tb
-2T, -Tb 0 Tb 2Tb -2L -L 0 L 2L -Tb Tb L 2L r

Fourier Transform Fourier Transform Fourier Transform
............. ....... .. .. I ..ran...o.r....... ............rer "r n r ... ..... ... .... .............
T2sinc2 (Tf) Tb2 rij b

(c) X I = I I

-2/T -1/Tb 0 1/Tb 2/Tb -2/L -I/L 0 1/L 2/L -2/T b -1/Tb 0 1/Tb 2/Tb


Figure 2-1. PRBS signal (a) waveform in time domain, (b) autocorrelation, and (c) power
spectral density in frequency domain [20].

Figure 2-1(a) shows the waveform in time domain for a PRBS 23-1 signal. A pattern

repeats itself every 7bits and the maximum run length is equal to 3. Figure 2-1(b) shows the

autocorrelation functions for each component of test patterns shown in Figure 2-1(a). The

autocorrelation of 7-bit test pattern approximates a triangle and the accuracy improves with

increasing pattern length. Figure 2-1(c) shows the Fourier transform of autocorrelation functions

to calculate the power spectral density. There are straightforward relationships between the time









domain characteristics of PRBS test patterns and their frequency domain characteristics.

Important observations are as follows [20].

1. The nulls in the sinc2(f) envelop occur at integer multiples of the data rate.

2. Spectral lines are evenly spaced at an interval inversely proportional to pattern length.

3. The sinc2(f) envelop flattens out as the data rate and/or pattern length increases.

In the limit, as the pattern length approaches infinity, the spacing between the spectral lines

becomes infinitesimally small and the spectrum shape approaches a continuous sinc2(f) function.

2.3 Clock and Data Recovery (CDR) Overview

A CDR employing a phase locked loop (PLL) to tune the frequency and phase of a VCO to

match that of the input data is of focus. Figure 2-2 shows a block diagram of the PLL-based

CDR circuit which consists of a phase detector, a charge pump, a loop filter, and a VCO. The

phase detector (PD) compares the phase and frequency of the input data with that of a voltage

controlled oscillator (VCO) and generates UP/DOWN pulsed signals for phase and frequency

correction to the charge pump which is followed by a loop filter. A control voltage from the loop

filter adjusts the phase and frequency of an oscillator to match that of the input data. The

following subsections overview the fundamentals of CDR blocks.

Input Recovered
data Phase Charge Loop Recovere
detector pump filter clock

Retimed VCO
Data


Figure 2-2. Block diagram of CDR.

2.3.1 Linear Phase Detector for Random Data

A topology of a linear phase detector [17], [21] and its output waveform under locked

condition are shown in Figure 2-3. Under this condition in which the rising edge of clock








samples exactly the center of incoming data, UP signal and DN signal produce the same pulse

widths. Retimed data can be either signal A or signal B. Signal A is a half clock delayed and

signal B is a clock delayed compared to the input data, DIN.


DIN I


CLK


I i


DIN D Q D Q B | I
DFF1 DFF2
FCLK rCLK UP n1-
CLK DN nj nJ nnJ

(a) (b)

Figure 2-3. A linear phase detector (a) block diagram, and (b) waveform under the locked
condition.


DIN

CLK

A


- -

DN f(

(a)


DIN

CLK


flY1flT1flfl I


A

B

up I

DN JQJ JT JTI

(b)


Figure 2-4. Waveform of phase detector for (a) early clock and (b) late clock.

Figure 2-4 shows the waveform of (a) early and (b) late clock in the linear phase detector.

When the rising edge of clock samples the data before the center point ("early clock"), the area


I H H I I
I I I I III I .......n









under the UP signal is smaller than the DN signal such that the VCO delays the phase of clock,

thereby CDR eventually gets driven to the locked condition. On the other hand, when the rising

edge of clock samples the data after the center point ("late clock") the area under the UP signal is

bigger than the DN signal so that VCO pulls the phase of clock forward thereby once again

driving the CDR to the locked condition.

Unlike a tri-state PFD operation [22] in a PLL, where UP and DN signals turn on

simultaneously under the locked condition, DN signal is produced a half clock cycle after the UP

signal. This offset in time of the UP and DN signals under locked condition perturbs VCO

control line every time data transition occurs, which degrades VCO phase noise.

Figure 2-5 shows the characteristic of linear phase detector assuming the maximum

transition density of 100%. As ODIN- OCLK becomes zero, the output of phase detector which is

an average value of UP-DN equals zero consistent with Figure 2-3(b). Here, ODIN- OCLK being

zero means the locked case where the rising clock samples the center of data bit period. When

ODIN- DCLK becomes negative (-7T
in Figure 2-4(a). Conversely, when ODIN- OCLK becomes positive (0
corresponds to the late clock case shown in Figure 2-4(b). A linear phase detector as its name

implies has limited frequency tracking capability which can be explained using Figure 2-5.

Considering the case where large initial frequency difference between DIN and CLK exits, the

resulting large phase/frequency error causes the output of phase detector to be quickly swept

across different regions (i.e. from point A to point B in Figure 2-5). This is so called "cycle

slipping" [23], [24]. This phase detector output alternating between regions can be averaged to

zero by a loop filter. When this occurs, slipping, recovered clock frequency oscillates without

getting proper correction information from the feed back loop.







On the other hand, a typical tri-state PFD in a PLL possesses input-output characteristic
such that certain polarity, positive or negative rather than zero is provided when being swept
across different regions as shown in Fig 2-6. That is why a PFD in a PLL can track frequency not
to mention phase

Average (UP-DN)


A


-1


ODIN-CLK


4.I__ _


-2-r


/B


/"2


Figure 2-5. Input-output characteristic of linear phase detector.

Average (UP-DN)


REF -DIV


Figure 2-6. Input-output characteristic of tri-state phase and frequency detector (PFD).


'U U I P -









2.3.2 Linear Model of CDR


Linear
Phase Charge Loop
Detector Pump Filter VCO


I(f1 1 cI Z(s) 2nKvco


Divider



N


Figure 2-7. Linear model of PLL based CDR circuit.

Figure 2-7 shows a linear model of CDR circuit. A conventional CDR circuit does not

have a divider in the feed back loop. Since frequency division decreases phase by the division

ratios, N, a phase divider block is added in the loop. A linear phase detector can be modeled as

(1/2)-(1/7), where (1/2) represents the average transition density for a PRBS (Pseudo Random Bit

Sequence) pattern which is the typical input data format for CDR circuit [25] and (1/h)

represents the gain of linear phase detector or the slope of curve in Figure 2-5. Including (1/2) in

the phase detector model reveals that the gain of phase detector depends on the data transition

density.

A charge pump can be simply modeled as a charge pump current Icp. In general, a VCO

produces a frequency output which is the input voltage, vin(t) multiplied by VCO gain, Kvco.

fout(t) = Kvco V (t)

The unit of Kvco is Hz/V. Integration of output frequency fout(t) leads to phase output as a

function of input voltage and VCO gain.









out (t) = l 2 7. f.ot (T) dT

= rt 2 7 Kvco v, (t) d

Therefore, the corresponding Laplace model of VCO is simply expressed as 2Kvco The
s

representation of frequency divider in time domain is represented as

fout(t) = .f, (t)

where N is the division factor. If this is expressed in terms of phase, then out (t) is


out(t)= f271.fout(Tc)dT = f 271. f, (T)dr= 4 (t).
J. J.- N N

This means the phase transfer function of a frequency divider is as mentioned simply modeled as

1/N.

For a loop filter model, the simplest form is chosen, which is a 2nd order passive lead-lag

filter whose schematic and transfer function are shown in Figure 2-8.


I V z(s) V=ou(s)
OIN VOUT IN(s)
-1 I I 1+ -
|| R +T
Rz Cp sC, SCz


SsCzC sRz + CzC,
I 1 sR C
".................................................

Figure 2-8. The 2nd order passive lead-lag filter (a) schematic and (b) transfer function.

In order to characterize the stability of feedback loop with phase margin (PM), the open

loop gain of CDR needs to be computed. Using the linear model of each block described above,

the open loop transfer function is









1 1 2 tK 1
HOL(S) = 1.cp Z(s). -
2 7 s N

1+sRzCz Kvco 1
SICP + sRC KVC
scsCz, sR C+ P s N


1+ s
1+ 1

SI RzCz2 Kvco 1
s N

s(C,+C,). 1+ s (2.1)
CZ + C,


The open loop transfer function (2.1) is for a type-two, third-order system. Among the three

poles, two poles are at the origin and the third pole cop and one zero coz are located at

Cz +Cp 1
op = P and co = (2.2)
RzCzCp RzCz

A Bode plot of the open loop gain is depicted in Figure 2-9. The intersection of magnitude

plot and OdB occurs at cot, which is referred to as the gain bandwidth of CDR circuit. As

indicated in Figure 2-9, phase margin (PM) is defined as the difference between the phase angle

at cot and -180. From (2.1), PM can be written as

PM= phase@ct -(- 180)

tan 'oKt 90 90 tan-' t -(-180) (2.3)


=tan-" tan -r
zro rPJ










20log IHoL(W)I

t


nrdR


Angle HO

Angle HOLw)


-40dB/dec


-20dB/dec
I"


W -40dB/dec


log w


Inn iI


.................. PM


Figure 2-9. Bode plot of the open loop gain for a CDR circuit.


8P
To maximize the phase margin, cot should be chosen when -
0a

8PM 1 1 1 1
=C
00+) t I++) t)
KwtY z iKw YP
l) lZpt CO


Solving (2.4) for cot, the maximum phase margin occurs when

0tPM ZW


M
-is equal to 0.
)t


(2.4)






(2.5)


f iop is the geometric mean and is located in the center point between the zero oz and the

third pole cop on a log scale. Typically, phase margin of 600 or higher is preferred for stability. If


-900

-1350
-1800


)


,,,


I


!>


w









coz is defined as a factor a below ot,PM and cop a factor P above 0ot,PM, the unity gain frequency, cot

can be derived from (2.1) by replacing s = jco and setting the open loop gain HOL(S) as 1. The cot

is then expressed as,


ICP Kco Rz Cz 1+a2
ot N Cz + C a +p2
N C P (2.6)

ICP Kvco Rz
N

In addition, the size of passive elements in the loop filter can be calculated.

N
RZ = N 0t (2.7)
ICPKvco

Cz = ICPKvco 1 (2.8)
C=- = 2.a (2.8)
RZCOt N COt


ICP N o +2 (2.9)
N 0)2 a12

To achieve sufficient phase margin, both a and 0 should be equal and higher than /10 [18].

2.3.3 Choosing a Bandwidth of CDR

For conventional CDRs for wire line applications, many standards such as SONET/SDH

(synchronous optical network /synchronous Digital Hierarchy) are already well established and

they include detailed jitter specifications. Two important jitter specifications related to choosing

the bandwidth of CDR in this proposal is jitter transfer and jitter tolerance. The jitter transfer is

defined as the ratio of the output to input jitter of the CDR. This measures how much jitter from

the input data signal is present on the output clock signal. A low-pass response is required to

suppress jitter. The jitter tolerance is defined as the maxim amount of jitter allowed on the data

input signal while still achieving the necessary bit error rates (BER) in detecting the data. It is

desired to have a large jitter tolerance bandwidth to track jitter on the data input. Figure 2-10









shows a jitter plot for a simple second order CDR circuit where a loop filter consists of a resistor

in series with a capacitor.

Linear
Phase Charge Loop
Detector Pump Filter VCO
Detector
X(s) E()
I Icp K(s) 2,Kco Y- )




Jitter tolerance
Jitter transfer
............. ......, E(s)
Y(s) X(s)
X(s)



fc f (log scale)

Figure 2-10. Linear model of second order CDR and its jitter plot.

Table 2-1. Summary of jitter specification
Rate Corner frequency (fc)
Jitter tolerance Jitter transfer
OC-1 20kHz 40kHz
OC-3 65kHz 130kHz
OC-12 250kHz 500kHz
OC-48 1MHIz 2MHz

Table 2-1 shows the corer frequency of the SONET/SDH (synchronous optical network

/synchronous Digital Hierarchy) jitter specification [27], [28]. The SONET/SDH bit rates are

multiples of 51.84Mbps. For instance OC-3 signal would have a data rate of 3 x51.84Mbps which

is 155.2Mbps. The OC-12 rate is therefore 12x51.84Mbps or 622.08Mbps.

The conflicting requirement between the jitter transfer requiring a narrow band CDR and

the jitter tolerance requiring a wide band CDR suggests that the bandwidth must be chosen in the

half way between the corner frequencies of two jitter specifications [29]. For example, the

bandwidth of CDR should be chosen between 250 kHz and 500 kHz for OC-12 data rate.









2.4 Summary

Chapter 2 described the basics of clock and data recovery circuits. Since a CDR circuit

recovers clock from a digital data stream whose format is NRZ type, the characteristics of NRZ

data format are first discussed. The circuit description and operation of linear phase detector are

then followed by loop analysis on linear model of CDR. Finally, the discussion for the choice of

CDR bandwidth is presented.









CHAPTER 3
CLOCK AND DATA RECOVERY CIRCUIT AS AN LO GENERATOR

3.1 Introduction

The CDR circuit in the transceiver for the motor side takes in 400-Mbps data to generate

400-MHz and 24-GHz LO signal. Moderate data rate (100-1000 Mbps) CDR's use a voltage

controlled oscillator (VCO) based on a relaxation oscillator (R.O.) [30]-[34], and typically jitter

performance is not good compared to the LC-VCO because of low Q and many noisy transistors

used in the circuits. In addition, these CDR's require a large external capacitor for the loop filter

except in [32] which requires an external crystal frequency reference.

Use of an LC-VCO with better phase noise and jitter performance at moderate data rates is

challenging due to a low quality factor (Q) and large size of required inductors. A new CDR

structure allows use of an LC-VCO and fully integrated loop filter capacitor despite moderate

input data rate (400Mbps). Since the incoming data for CDR is 400Mbps, a conventional CDR

structure will generate recovered clock at only 400MHz. However, the new CDR structure

generates recovered clocks at both 400MHz and 24GHz. This 24-GHz clock can be used as an

LO signal to drive an up-conversion mixer at TX side. RMS phase error of LO signal would be

an important performance parameter in digital communication systems, especially those using

phase modulation. However, since the transmitter utilizes amplitude shift keying (ASK), the

phase noise issue is bypassed. Qualitative analysis on the impact of phase noise on ASK

modulated signal at TX output is presented.

3.2 New CDR Structure

Figure 3-1 and 3-2 show a block diagram of a conventional CDR structure and the new LO

generation circuit merged into a CDR circuit, respectively. The new CDR structure allows use of

an on-chip LC-VCO at input data rate of 400 Mbps. Different from the conventional CDR









structure which consist of a phase detector, a charge pump, a loop filter, and a VCO, the new

CDR circuit includes a frequency divider in the feedback path, which is similar to continuous-

rate CDR's [29], [30], [33].

400Mbps
PRBS Phase Charge
Data Detector pump

L ..... ...... ........ 400MHz
400Mbs Cz Ring
Retimed oscillator
Data ........................... based
Off-Chip VCO



S400MHz
Recovered
Clock

Figure 3-1. Block diagram of conventional CDR.


Digital tuning


400Mbps
PRBS
Data


24GHz
Recovered
Clock


Figure 3-2. Block diagram of new CDR.

Even if structural similarity between proposed CDR and continuous-rate CDR's exists,

none of the continuous-rate CDR's have been used as an LO generator. By choosing a division









ratio of 60, the VCO is made to operate at 24 GHz. At this frequency, the VCO needs a 352-pH

center tapped inductor. The Q of such an on-chip inductor is -18. These easily make the

architecture suitable for integration.

A conventional CDR often incorporates a large off-chip capacitor to realize a small loop

bandwidth, thereby low-pass filtering the high frequency noise/jitter of incoming data. The

capacitor Cz in the loop filter in Figure 3-2 is typically sized as [35]:


C KVCO xCP (3.1)
Nx (WBW)2

where Kvco, ICP, N, WBW are VCO gain, charge pump current, division ratio, and loop

bandwidth, respectively. The CDR structure that contains a divider after a VCO gives the second

benefit of providing an additional control factor to size and reduce the capacitor. In general, as

VCO frequency increases, N should increase proportionally assuming the input data rate is fixed.

Kvco also increase accordingly. However, since the amount of Kvco increase compared to that of

N increase can be made smaller, the size of capacitor Cz can be reduced.

Considering the fact that smaller Kvco leads to better phase noise performance, Kvco is

already minimized to begin with. For this reason, Kvco itself is not a free knob of reducing Cz.

Incidentally, Icp in the numerator of Equation (3-1) can not be arbitrarily lowered to reduce the

size of capacitor Cz, either. When Icp is lowered, the resistor Rz of loop filter increases, which

typically degrade the phase noise and jitter performance of the recovered clock [35].

3.2.1 Loop Filter

A loop filter in Figure 3-2 is a 2nd order passive filter formed with one silicide blocked p

polysilicon resistor and two polysilicon/n-well MOS capacitors [36]. The resulting CDR is then a

type-two, third order system [37]. The loop bandwidth of 500-kHz, charge pump current of

60tA, divide ratio of 60 and VCO gain of 1GHz/V are chosen. Equations (2.7) (2.9) are used









to compute Cz, Cp, and Rz whose values are 288pF, 32pF and 3.5kQ, respectively. The biggest

capacitor Cz occupies 180mtmx213tm. The simulated phase margin of CDR loop is 55.

3.2.2 Voltage Controlled Oscillator (VCO)

Figure 3-3 shows a circuit schematic of a 24GHz VCO, which consists of an LC-tank, an

NMOS cross coupled pair, noise filter inductor and capacitor, a pair of accumulation mode

varactors [38], [39] for continuous fine tuning, a digitally tuned capacitor bank for discrete

coarse tuning, a PMOS tail current source, and a pair of inductively loaded buffers. The capacitor

bank supports 3-bit digital tuning to keep the VCO gain low for reduced phase noise and loop

filter capacitor values, while maintaining an adequate tuning range. To increase inductor Q, LO is

drawn as a single center tapped spiral inductor [40] using top two copper layers shunted together.

The total metal thickness is -1.5am. The metal spacing, width, and number of turns are 3am,

4am, and 3, respectively. The inductance for L1 is 352pH, and the inductor including a

polysilicon pattern ground shield [41], [42] occupies 72 amx72 am. The simulated Q [43] of

inductor is about 18 at 24GHz.

The Q of MOS varactor at 24GHz is 13 in the accumulation region and 32 in the depletion

region [44]. Since the Q of varactor at 24GHz is almost comparable to the inductor Q, assuming

VCO oscillates at 24GHz at the control voltage of 0.6V, the overall tank Q is -9. The capacitor

bank consists of three parallel binary-scaled MOS varactors whose control voltages are

connected to either VDD for Cmin or ground for Cmax. The measured Cmax/Cmin is around 3.5. A

large capacitor Cl in parallel with the current source M3 shunts noise frequencies around the 2nd

harmonic to ground. A bottom inductor L4 also provides high impedance at the tail in order to

block the 2nd harmonic current from flowing through the switching pair (Ml and M2) to ground,

which de-Qs the original LC tank [45].




































Figure 3-3. Schematic of the 24GHz LC VCO.

3.2.3 Divider Chain (Divide-by-60)

Figure 3-4 shows the divide-by-60 circuit which starts with a divide-by-2 stage in front

followed by a two stage tapered inductor loaded buffers to reduce the load seen by the first

divide-by-2 stage. A divide-by-2 stage is used to restore 50% duty cycle for the output of divide-

by-5 stage. For the final stage, rather than using a divide-by-3 stage, a divide-by-1.5 followed by

a divid-by-2 stage is used to generate recovered clock with a 50% duty cycle. Since the phase

detector uses both rising/falling edges of clock to determine the phase difference, keeping a 50%

duty cycle is important. All the divider blocks are designed using current mode logic (CML)

static frequency dividers with the bottom current source omitted [46] for low voltage operation

and a PMOS load with grounded gate [47] except for the divde-by-5 stage where poly silicon









resistor loads are used to increase the maximum operating frequency. Careful transistor sizing for

the 1st divide-by-2 circuit handling 24GHz is required [48].

2 Stage Buffer

24GHz +2 +5 2 +15 2 400MHz



Figure 3-4. Block diagram of divider chain (divide-by-60).

The divide-by-5 stage consists of three differential D-flip-flops and one AND gates. The

first and second flip flops form a divide-by-4, while the third flip-flop adds an extra delay of a

clock period to divide-by-5 [49]. Divide-by-1.5 is realized using a conventional divide-by-3 in

which a single-edge triggered D-flip-flop is simply replaced by a double-edge triggered D-flip-

flop. The circuit schematic of divide-by-2 and each latch circuit is shown in Figure 3-5 [50]. The

divide-by-5 and divide-by-1.5 circuits will be discussed in details in Chapter 4.




D Q D Q T
LATCH1 LATCH2
D Q D Q DH ]
__ OUT
CLK CLK CLK CLK

IN IT TI CLK^ CLK


Figure 3-5. Block diagram of divide-by-2 and implementation of latch circuit.

3.2.4 Phase Detector

Among popular phase detectors, the linear (Hogge) phase detector has some advantages

over non-linear (Alexander) phase detector [51]. One advantage is that a CDR loop adopting a









linear phase detector and a charge pump can be understood using the linear loop theory in a

straightforward manner. The other advantage is that a CDR shows less jittery behavior on the

VCO control line under the locked condition. Most CDR circuits for multi-Gb/s applications use

a non-linear phase detector because a linear phase detector usually poses serious speed

bottleneck for high frequency operation in the interface between a linear phase detector and a

charge pump. The CDR only needs to support 400-Mbps data rate which is sufficiently low to

use a linear phase detector.


Din





CLK


I- ............. ..............LK


Figure 3-6. Block diagram of (a) phase detector and (b) implementation of each DFF using
DCVSL logic circuits.








Figure 3-6 shows (a) the block diagram of the Hogge phase detector and (b) the circuit

schematic of the D flip-flop (DFF), respectively. The Hogge phase detector consists of two flip-

flops, one XOR and one XNOR. In real implementation of DFF 1 and DFF2, differential

signaling is utilized although only positive signal is drawn for simplicity in the block diagram.

Since DFFs operate with differential signals, differential-cascode-voltage-switch-logic gates

(DCVSL) [52] are employed.

3.2.5 Charge Pump (CP)

The schematic of charge pump is shown in Figure 3-7 [53], [54]. The UP in the Ml 1

and M12 are directly connected to the output of XNOR gate in the phase detector, and "DN" in

the M15 and M16 are connected to the output of XOR gate in the phase detector. The output

node of charge pump is followed by a loop filter.



M1 I M4 1M7 0-Iu M1
UP
UP
cL..H M12
M2 M5 M8 M13
CP current l CP
control CP
output

M3 --- M6 M9 MuI I14 M15
C2 DN

M10 0- M16
DN


Figure 3-7. Schematic of charge pump.

The charge pump current is chosen to be 60tA. Since 60tA is relatively small, it could be

sensitive to process and temperature variations. In order to mitigate this, the length and width of










MOS transistors are intentionally chosen to be large, which also helps to alleviate the mismatch

and channel-length modulation problem of mirror transistors. M2 is added to facilitate external

current control. Cl and C2 are both 10-pF capacitors to bypass current spikes when M11 and

M16 switch between on and off. M12 and M15 are charge removal transistors, which help to cut

out long current tail when switch M11 and M16 turn off. As CP output voltage deviates from

VDD/2, the current mismatch between up and down path becomes pronounced due to the finite

output resistance at the CP output node.

3.3 Simulation Results

Figure 3-8 shows a current mismatch between up and down current as the output voltage of

charge pump sweeps from OV to VDD. With the VDD of 1.2V, the mismatch between UP and DN

current gets bigger as the output voltage deviates from 0.6V. Therefore, under the locked

condition, VCO must be designed to oscillate at 24GHz at the control voltage of -0.6V so that

the charge pump optimally operates around 0.6V at which the UP and DN current mismatch is

the least.


70u

50u

30u
lup-ldown
(A) 1O0

-10U

-30u

-50u

-70u


0.0 .20 40 .60 80 10


,2


CP output voltage (V)


Figure 3-8. Plot of current mismatch between up and down current in the charge pump.









Figure 3-9 shows the plot of VCO tuning range with 3-bits digital control for coarse

tuning. The gain decreases as the control voltage deviates from center because of the saturation

of varactor capacitance. As seen in Figure 3-9, a set of digital bits 000 corresponds to the target

tuning curve, which generates 24GHz at VCO control voltage of 0.6V. The lowest digital bits

(000) for the target frequency of 24GHz are used in simulations is because based on the previous

UMC 130-nm tape-out, the a measured frequency would shift down by -2GHz compared to the

simulation frequency.

27 .0 G ...........................................


26.0G

Frequency
(Hz)
25.0G


111
110
101
100
011
010
001
000


.0 .20 .40 .60 .80 1.0 1.

VCO control voltage (V)


Figure 3-9. Simulated VCO tuning range plot with 3-bit digital control for coarse tuning.

The plot in Figure 3-10 is the transient response of VCO control voltage. Around 3.5as, the

CDR enters the locking region, where recovered clock samples the center of incoming data.

Figure 3-11 shows the input data versus recovered clock that is locked. The simulation indicates

that the recovered clock almost keeps a 50% duty cycle and the rising edge of clock samples the

center of bit period as expected.









640m


610m


Time (s)


Figure 3-10. Simulated CDR settling behavior at the VCO control voltage.


1.4 1 0 1


Input
Data
(V) 50m
200m-
lI 0 m ..
1.3


Recovered
700m
Clock
(V) 400m


Time (s)


Figure 3-11. Input data signal versus recovered clock under the locked condition.


Control
Voltage
(V)


Locking
Region









3.4 Measurement Results

The CDR has been fabricated in the UMC 130-nm logic CMOS technology with eight

copper layers. Shown in Figure 3-12 is a die photograph. The chip area without the bond pads

occupies 0.79mmxO.58mm. The CDR has been measured on a PC board with the chip directly

mounted on the board (chip-on-board). The measured CDR locking range is from 395 to

405Mpbs.























Figure 3-12. Die photograph of 24GHz CDR.

Figure 3-13 shows the measured 3-bit VCO tuning characteristics. The VCO can be tuned

from 21.5GHz to 24.5GHz. In order to generate the 24-GHz LO signal, digital tuning bit setting,

111 was selected which covers from 23.5GHz to 24.5GHz. Compared to the simulation result in

Figure 3-9, the measured tuning curves shifted down by ~2GHz such that digital tuning bit 111

covers the target frequency around 24GHz. Figure 3-14 shows a VCO tuning range and the

corresponding VCO gain for digital tuning bit setting, 111. The measured VCO gain is

~1.3GHz/V around the control voltage of 0.6V in comparison to the designed VCO gain of











1GHz/V. The supply voltage is 1.2V. The VCO draws 6.6mA. The total power consumption of

CDR excluding that of the buffers for driving an external 500 load is 18.3mW.


24.5

24

S23.5

o 23
23

[ 22.5
L-
0
0 22

21.5

21


0.2 0.4 0.6 0.8 1 1.2
VCO voltage (V)


Figure 3-13. Measured tuning range plot with 3 bits digital control for coarse tuning.


24.6

24.4

24.2

24

23.8

23.6

23.4

23.2


0.2 0.4 0.6 0.8

VCO Control Voltage (V)


Figure 3-14. VCO tuning range and gain at digital bits 111.









"*. :" i_ ; ,-, n:II Ilhl _-rn j. r J, hl.. r .: li U -t I|. _n, r. .iiii .. .j '







,. .. .

_.. ..*





IJcr 24 z wih a 4- s P 11 inpt wen te CR is The specm















peak near the center frequency is broadened besides the higher in-band phase noise. This
Figure 3-15. Jitter histogram of the recovered clock at 400lMHz for a PRBS 231-1 input.

Figure 3-15 shows the jitter histogram of recovered clock at 400PMHz with a PRBS 231-1

input. The measured RMS and peak to peak (p-p) jitters are 2.6ps (rms) and 22.2ps (p-p), which

are 0.1% and 0.89% of bit period, respectively. Figure 3-16 shows the spectrum of recovered

clock at 24GHz with a 400-Mbps PRBS 231-1 input when the CDR is locked. The spectrum of

peak near the center frequency is broadened besides the higher in-band phase noise. This

broadening originates from the 400-MHz peak extracted during the edge detection process [55]

in the linear phase detector. The PRBS NRZ signal with a null at the data rate frequency is

converted in the phase detector into pseudo non return to zero (PNRZ) signal with a peak at the

data rate frequency [55]. The broadened spectrum near the center frequency results from the

densely spaced spectral lines in the PNRZ spectrum. The spacing of spectral lines is scaled by

2n-1. For n of 31, the spacing between spectral lines is -0.2 Hz. Figure 3-17 illustrates how the

peaks of spectrum for the source PRBS signal manifest in the CDR output spectrum through the

CDR loop.










Ftten 10 dB


Mkrl 23.999 967 GHz
-16.06 dBm


Center
24.00000000 GHz


W1 S2
S3 FCi


Center 24.000 000 GHz
*Res BW 30 kHz


#VBW 3 kHz


Span 5 MHz
*Sweep 138 ms (601 pts)


Figure 3-16. Spectrum of the recovered clock at 24GHz for a PRBS 231-1 input.


400 MVHz


2^

0 400MHz 800MHz






'I l .i T .


40(


f


0MHz 800MHz


Figure 3-17. Spectrum of 400Mbps PRBS 2n-1 signal (top), PNRZ signal after edge detection in
the phase detector (middle), and recovered clock at 24GHz (bottom).


Ref 0 dBm
Norm
Log
10
dB/











Carrier Power -14.61 dBm Atten 0.00 dB
Ref -36.00dBc/Hz
10.00


Mkr 4 10.0000 MHz
-114.83 dBc/Hz


50 KHz

Marker Trace
1 2
2 2
3 2
4 2


Frequency Offset
Type
Spot Freq
Spot Freq
Spot Freq
Spot Freq


X Axis
60 KHz
100 KHz
1 MHz
10 MHz


20 MHz

Value
-62.27 dBc/Hz
-62.98 dBc/Hz
-92.06 dBc/Hz
-114.83 dBc/Hz


Figure 3-18. Phase noise plot of the recovered clock at 24GHz for a PRBS 27-1 input.


Carrier Power -14.48 dBm Atten 0.00 dB
Ref -36.00dBc/Hz
10.00
dB/


Mkr 2 100.0000 KHz
-62.66 dBc/Hz


50 KHz

Marker Trace
1 2
2 2
3 2
4 2


Frequency Offset
Type
Spot Freq
Spot Freq
Spot Freq
Spot Freq


X Axis
60 KHz
100 KHz
1 MHz
10 MHz


20 MHz

Value
-61.33 dBc/Hz
-62.66 dBc/Hz
-88.73 dBc/Hz
-110.94 dBc/Hz


Figure 3-19. Phase noise plot of the recovered clock at 24GHz for a PRBS 231-1 input.









Wider span phase noise plots for a PRBS 27-1 and 231-1 are shown in Figure 3-18 and 3-

19, respectively. In Figure 3-18, spurs at integer multiples of -3.15MHz from 24-GHz output

signal result from the spectral lines -3.15-MHz spacing (400 MHz / (27-1)) in the 400-MHz

PNRZ spectrum. Although, the spurs are out of the loop bandwidth of CDR of -500 kHz, they

are too big for the CDR low-pass loop filter to completely suppress them. In the case of

400Mbps PRBS 231-1, the phase noise plot does not show any discrete spurs. This is because the

spacing between spectral lines is so close (-less than 0.2Hz) that the resolution bandwidth of 10

kHz for the measurements spreads and averages them.

Table 3-1. Summary of measured CDR performance
Technology UMC 130-nm
Input data rate 400-Mbps
CDR lock range 395-Mbps 405-Mbps
VCO tuning range 21.5-GHz 24.5-GHz
24-GHz clock
phase noise PRBS 27-1 PRBS 223-1 PRBS 231-1 oc input VCO
(dBc/Hz)
@ 60-KHz offset -62.3 -61.0 -61.1 -70.9 -53.4
@ 1-MHz offset -92.1 -90.0 -88.7 -92.6 -96.2
@ 10-MHz offset -112.2 -111.0 -115.2 -115.8
400-MHz Input data jitter
RMS rising Peak to peak .
clock jitter (ps) S r g Pk t p (RMS rising)
with PRBS 27-1 2.19 16.22 1.67
with PRBS 223-1 2.36 21.11 1.89
with PRBS 231-1 2.58 22.22 1.93
BER Less than 10-13 with 95% confidence for PRBS 231-1
Chip size (w/o pad) 789 x 584 [tm2
Power Phase Charge Divider Total
consumption detector pump (w/o buffer)
(VDD:1.2V) 501.6(tW) 248.4(aW) 7.92(mW) 9.64(mW) 18.31(mW)

The phase noise performance is measured with PRBS 27-1, 223-1 and 231-1 data streams,

and clock input at 200MHz. The phase noise performance is also measured without locking the

24-GHz VCO. These results as well as other measured characteristics of CDR are summarized in

Table 3-1. For a PRBS 231-1 input, in-band phase noise at 60-kHz offset is -61dBc/Hz. The









phase noise at 1-MHz offset is -89dBc/Hz and the out-of-band phase noise at 10-MHz offset is -

11 ldBc/Hz. The in-band phase noise at 60 kHz increases by -9 dB when PRBS data are used

instead of a 200-MHz clock. The phase noise at 10-MHz offset increases by 3.0, and 4.2 dB for

PRBS 223-1 and 231-1 input, respectively compared to the clock case. The BER performance has

been measured using an Agilent N4906A BERT. At 400 Mbps, a total number of 3.456x 1013 bits

was monitored over a 24-hour period. The measured BER with 95% confidence is less than 10-13.

The actual data pattern for the wireless communication system in a hybrid engine

controller board is random. The system uses code division multiple access with 8-bit long Walsh

codes [14]. The receiver limits (Figure 4-2) the CDMA waveforms to generate an NRZ data fed

to the CDR. Because of this, the long sequences of ones or zeros in the PRBS 231-1 are not

present in the real NRZ data, and the jitter performance and phase noise performance of the

actual system should be better than that for the PRBS 231-1 input case.

Table 3-2. Comparison of jitter performance
Ref VCO type
NRef V type Off-Chip PRBS Output RMS clock jitter
No. / Tech
R.O /
30] .18m CAP 2311 23.4ps (1.46% UI) @622MHz
m C 80.4ps (1.25% UI) @155MHz
CMOS
R.O /
R[31] 5m CAP 231 10.9ps (0.68% UI) @622MHz
[31] 0.35[tm CAP 2 -1
CMO 18.8ps (0.38% UI) @200MHz
CMOS
R.O /
R / Ext. 4.5ps (0.23% UI) @500MHz
[32] 0.25[tm CLK 8.3ps (0.21% UI) @250MHz
CMOS
33 R.O / 7_ 5.2ps (0.32% UI) @622MHz
Bipolar 14.4ps (0.22% UI) @155MHz
[34] CAP 2-1 62.7ps (0.97% UI) @155MHz
Bipolar
R.O/ Ext. 23
[56] R / E 223-1 17.2ps (0.27% UI) @155MHz
Bipolar VCO
S LC /
This 0.13 m On-Chip 231-1 2.6ps (0.1% UI) @400MHz
work CMO
CMOS









Table 3-2 summarizes the jitter performance of CDR's in the literature with moderate data

rates between 100 and 600 Mbps. The jitter of only fully integrated CDR reported here is the

lowest by almost factor of two. The measurement results of another CDR test structure that

recovers clock at 400MHz and at 5.84GHz for TX LO signal are also presented in Appendix A.

3.5 The Influence of Phase Noise of CDR on ASK Modulation

A TX employing an unconventional LO from CDR must deal with the effects of LO phase

noise since the LO phase noise from a CDR using jittery incoming data as essentially a

frequency reference is worse than that from a PLL using a crystal oscillator as a frequency

reference. The effects of phase noise on ASK modulation can be analyzed qualitatively.

Referring to TX in Figure 4-2, the LO signal from the CDR can be expressed as

s(t) = Acos[cot + Pn(t)]

= A cos(o)t) cos(p (t)) A sin(o)t) sin(p, (t))

A cos(o, t) Ap (t) sin(o, t) (3.2)

= A + (p (t))2 cos[oot+ (t)]

where A denotes amplitude of LO signal, co, is LO frequency, pn(t) is phase noise,

(pn(t)<
noise, (pn(t) on the amplitude change is negligible. As discussed, IF signals are generated by

frequency dividers. For instance, if 2-GHz IF signal is chosen, the original 24-GHz CDR output

is frequency divided by 12. After the division, the overall phase noise improves by

201og(24GHz/2GHz) 21.6dB [57].

The LO signal from the CDR output and the IF signal from the divider output are mixed

together. The former signal consists of desired input signal, SCDR and undesired input noise, NCDR

likewise the latter signal consists of desired input signal, SDIV and undesired input noise, NDIV.









The, the mixer output is comprised of SOUT, desired output signal, and NOUT, undesired output

noise:

SOU T N SCDRSDIV SCDRNDIV + DIVNCDR N CDRNDIV, (3.3)

where the mixer is assumed noiseless, NCDRNDIV can be neglected, and the first term is the

desired signal and the second and the third terms constitute undesired noise at the mixer output.

The overall SNR at mixer output then can be approximated as [58]

SCDR SDIV
SNR OT SCDR x S V NCDR NDIV SNRDR x SNRD (3.4)
ScDRNDIV + SDIVNCDR CDR SDIV SNRCDR+ SNRDIV
NCDR NDIV

The SNR at mixer output is dominated by the lower SNR among two input signals. Therefore,

Equation (3.2) is the expression for the mixer output with phase variations mainly due to the

CDR phase noise. Finally, the signal is amplitude modulated by the on-off switch in the power

amplifier. If a square clock is assumed to be the modulating signal, then the modulating signal

and modulated signal can be expressed as [59], [60]:

1 2 1 1 1
g(t)= -+- cost -cos3oot+ cos5c ot--cos7cot+--
2 7r 3 5 7
(3.5)
k=+ 2 sin- k
<> G(w)= 2 8( kwoo)
k=- k

x(t) = g(t) x s(t) =g(t) x Acos[ot + 0(t)]

A (3.6)
<- X()= [G((-m)eje()+G (w+ )e et)]


where G(co) and X(co) are the Fourier transforms ofg(t) and x(t), respectively, coo is the

modulation angle frequency, co is the carrier angle frequency.









The amplitude and phase spectra for x(t) and corresponding waveform in time domain are

shown in Figs. 3-20(a), (b), and (c) in order. In Equation (3.6), 0(t) due to the phase noise from

CDR manifests itself as phase variations of each spectral component of modulated signal in the

phase spectrum in Figure 3-20(b),These are translated into the phase variations of carrier in the

modulated signal in time domain as depicted in Figure 3-20(c). The modulating signal which

carries the information is not affected by the phase variation 0(t).


, t .-4


K* ** a. .
I i: I \?T* -


(b)
..::T:::::.......... -
............ ..... .... -.-.. ... _.
:^ ::-:!:::: :: :;:- -:L :: ::U::
.::: :* : T


IX(


1 tI I wo


._ .................. 9(t) phase
1- variation
S.. ..... ...... Vacation
......................................
** **********


....W.. .W.
1 fo 1/fc + Timing Jitter
due to 9(t)


Figure 3-20. Plots of (a) amplitude and (b) phase spectra for x(t) and corresponding waveform
(c) in time domain.


__









When this amplitude modulated signal is demodulated by squaring and low pass filtering

in the receiver, the effects of phase variations or LO phase noise is removed. The received

amplitude modulated signal with phase variations is

r(t) = A(t). cos[oct + 0(t) + 6(t)], (3.7)

where 6(t) represents the additional phase variations due to the transmission path between a

transmitter and a receiver. If the ASK waveform of (3.7) is applied to the input of the square-law

detector, the output signal ri(t) is

r, (t) = a r(t)2 = a (A(t) cos[ot + 0(t) + 6(t)])2

= A(t)2 I1+ cos[2ott + 20(t) + 26(t)] (3.8)
2 ) I

where a is a constant. After low pass filtering, the output r2(t) is

A(t)2 A(t)
r2 (t) = -a -K.- (3.9)
2 2

where P and K = p a are constant, and A(t)2=A(t) when A(t)=0 or 1. As shown in Equation (3.9),

LO phase noise has no effect in ASK systems using a square-law detector.

3.6 Conclusion

A merged 400-Mbps fully integrated CDR and 24-GHz LO generation circuit, a key

component for a transceiver that can operate without a crystal frequency reference for wireless

data communication in a hybrid engine controller board is proposed. The circuit fabricated in

130-nm logic CMOS achieves phase noise of -88.7dBc/Hz at 1MHz offset for the 24-GHz LO

signal, RMS jitter of 2.6ps for the 400-MHz recovered clock and BER of less than 10-13 with a

PRBS 231-1 input. The jitter and phase noise performance with the actual data pattern for the

system should be better.









To accomplish this at the moderate data rate, the CDR architecture has been modified to

include a frequency divider and an LC-VCO with reduced phase noise. The VCO operation at

the frequency (24 GHz) 60 times higher than the 400-Mbps input data rate enables generation of

LO signal for transmitter with an integrated LC-VCO that uses an inductor with practical size

and Q. Including the divider provides additional degree of freedom for reducing the size of loop

filter capacitors for integration. The LO signal at 24GHz from the CDR should be suitable for

wireless communication systems using simple ASK modulation. It should also be possible to use

it as an LO for wide bandwidth systems with other low order modulation schemes. The jitter of

this fully integrated CDR reported here is the lowest by almost factor of two compared to the

other CDR's for similar data rate. Lastly, it is also reported the phase noise performance of LO

signal generated in a CDR and the effects of PRBS input data on phase noise performance.

Finally, qualitative analysis of the impact of phase noise on ASK modulated signal at TX

output and at RX baseband is presented. The increased phase noise of the LO generated by a

CDR does not degrade the performance of ASK systems using a square law detector receiver.









CHAPTER 4
FDMA TRANSMITTER AT MOTOR SIDE

4.1 Introduction

The feasibility of implementing the receiver for the motor section in CMOS that supports

400Mbps is already demonstrated [61]. The receiver successfully non-coherently detected an

amplitude modulated 400Mbps data stream using Schottky barrier diodes (SBD) [61]. Chapter 4

describes a FDMA transmitter that radiates ASK signal without using an external crystal

reference.

Before delving into the main discussion of transmitter blocks, first, evolution of transmitter

at a motor section for a simplicity and higher power-efficiency eliminating functionally

redundant blocks is discussed. The circuit implementation of TX blocks, IF generator, 8 to 1

multiplexer, 3-stage LO buffers, up-conversion mixer, and power amplifier are then presented in

order. In the sections 4.5 and 4.6, measurement results of IF generator and entire TX chain

fabricated in UMC130-nm CMOS technology are presented. Finally, the feasibility of wireless

link from a TX motor to the low voltage section within the controller board is demonstrated.

4.2 Evolution of Transmitter at Motor Side

A block diagram of the original transceiver at a motor section is shown in Figure 4-1. A

CDR recovers the clock at 400MHz from an incoming 400-Mbps data. The recovered clock

signal at 400MHz is followed by a divider that generates the low frequency reference signal for a

PLL. The clock at 24GHz is then synthesized by the PLL and used as the LO signal in an up-

conversion mixer. The recovered clock is also used to synchronize ADC and decoder operation.

This original transceiver has been simplified without compromising the performance of

original transceiver. The main distinctive modification is that the phase locked loop (PLL) of

transmitter no longer exists in the architecture shown in Figure 4-2. This becomes possible









because a new CDR structure that merges the PLL function into the VCO of CDR can directly

provide the 24-GHz LO signal. Omitting the PLL greatly reduces the circuit complexity, area,

and power consumption. Details of the new CDR architecture are already presented in Chapter 3.

The CDR provides the frequency references for both 24-GHz LO signal in TX and 400-MHz

clock for ADC and decoder in RX, which makes the transceiver a reference-less radio. With the

choice of an appropriate modulation scheme such as non-coherent amplitude modulation,

detrimental impact of phase noise degradation can be completely eliminated.


SBD Multi-level
Rectifier CDMA signal


Figure 4-1. Block diagram of original transceiver at a motor section.


SBD Multi-level
Rectifier CDMA signal


Figure 4-2. Block diagram of transmitter at motor side.









4.3 Circuit Topology of Transmitter at Motor Side

A block diagram of the updated transceiver at a motor section is shown in Figure 4-2. The

transmitter is comprised of a CDR, an up-conversion mixer, 3 stage LO buffers which are not

shown, an IF frequency generator, an attenuator and an 8-to-1 multiplexer, a power amplifier, a

duplexer, and a 4-mm on-chip dipole antenna.



2 stage 4 IF MIXER
buffer generator

CDR\
.........CDR.......... 2 |8tol MUX| PA


AC PADAttenuator

24GHz
............................


3 stage LO buffer


Figure 4-3. Block diagram of the interface between a CDR and a mixer.

The interface between a CDR and an up-conversion mixer is shown in Figure 4-3. A TX

chain starts from the CDR which generates a 24-GHz LO signal. One branch from the CDR

drives the IF frequency generator which produces 7 channels ranging from 400MHz to 3GHz.

The IF generator is followed by an attenuator for harmonic control, and an 8-to-1 multiplexer for

selecting one out of 7 possible channels. The 7th port is for direct connection to an external

signal generator. The other branch from a CDR directly drives a mixer LO port through 3-stage

inductor loaded cascode buffers. Because of the large layout separation (0.75mm) from the CDR

output to the mixer LO port, these buffers must be inserted in order to maintain sufficient drive.

An up-conversion mixer is followed by a class-E type power amplifier [62] that is amplitude










modulated using simple on-off switches. Finally, a duplexer following the power amplifier is

connected to a 4mm on-chip dipole antenna.

4.3.1 IF Generator

Figure 4-4 shows a block diagram of an IF frequency generator. The grey divider blocks

use VDD of 1.5V for improved driver operation. All the rest of blocks use VDD of 1.2V.

Considering the fact that seven 350-gtm long metal 8 lines from the output of IF generator are

closely spaced (width: 1-tm and space: 0.5-tm), crosstalk [63] among signals is a concern. To

alleviate this problem, only one selected branch carries signal, thereby eliminating the effects of

crosstalk.
...............................................................................................

21.5 GHz

S3.0GHz
+2 3 GHz



duty(2: 1)

S2.4GHz 2.4 GHz
1 ----5d uty(3:2)

2 m 1.2 GHz


+1.5 +2 0.8 GHz

1 : switch
.2 0.4 GHz



Figure 4-4. Block diagram of IF generator.

A switch shown as a black box at the end of each branch is a simple shunt NMOS

transistor which controls the signal flow. When the switch is "on" in a branch, signal is bypassed

through the switch to the ground, and the branch is deactivated. On the other hand, when the









switch is "off", the branch is able to pass signal onto the next block. Therefore, the switch for the

selected is "off" to let the signal pass onto the next block while the switches for the other IF

branches are on. The switch control can easily be achieved with the help of a 3-bit decoder

implemented inside the 8 to 1 multiplexer. Since the outputs of a 3-bit binary decoder are "one-

hot encoded" [64], adding an inverter after a decoder can provide the necessary control signals

for the switches.

Table 4-1. IF signal generation
Signal Frequency Generation
LO 24GHz 24GHz VCO at CDR
IF1 0.4GHz LO/2/2/2.5/1.5/2/2
IF2 0.8GHz LO/2/2/2/2.5/1.5/2
IF3 1.2GHz LO/2/2/2.5/2
IF4 1.5GHz LO/2/2/2/
IF5 2.0GHz LO/2/2/3
IF6 2.4GHz LO/2/2/2/.5
IF7 3.0GHz LO/2/2

Table 4-1 summarizes the seven IF signal generation schemes from th 24-GHz LO of

CDR. If IF signal does not keep 50% duty cycle, the output of up-conversion mixer will contain

the undesired harmonic frequency contents that are generated by mixing of LO with harmonics

of IF signal. In particular, the 2nd order harmonics of IF signal mixed with LO cause undesired

frequency contents that fall in the neighboring motor channels.

Assuming the duty cycle of input clock is equal to 50%, the duty cycle of divide-by-1.5

and divide-by-2.5 output are 2:1 and 3:2, respectively. Therefore, divide-by-1.5 and divide-by-

2.5 stages need to be followed by a divide-by-2 stage to restore the duty cycle to 50%. Among

the seven IF generation circuits, IF5 (2GHz) and IF6 (2.4GHz) do not have 50% duty cycle. The

2nd order harmonics of these mixed with the 24-GHz LO signal produce signals at 20GHz and










28GHz for IF5, and at 19.2GHz and at 28.8GHz for IF6. Since these frequencies are, however,

all out of 24.2-27.2GHz TX band, the deviation from 50% duty cycle for IF5 and IF6 is allowed.

Since the first divide-by-2 block must operate at the highest frequency of 24GHz, careful

design attention is required especially when it is realized by a CML type static divider [48]. All

divider blocks in the IF generator are the CML type static dividers. Figure 4-5 shows the

schematic and waveform of divide-by-2.5 and divide-by-1.5 circuits. The divide-by-2.5 and

divide-by-1.5 circuits are implemented using divide-by-5 and divide-by-3 circuits in which the

conventional single-edge-triggered flip flops are simply replaced by double-edge-triggered flip

flops (DETFF) [65].





A D QOTD Q D Q IN
A 1 DETFF1 DETFF2 DETFF3
B D Q D Q Q OUT
L OUT
B CLK CLK CLK CLK CLK CLK
FN OUT

IN
IN
(a)




A O INA
D Q A D Q
DETFF1 I DETFF2
OUT B ou
D Q Q OUT
CLK CLK OUT CLK CLK
IN- OUT
IN
(b)


Figure 4-5. Block diagram and waveform of (a) divide-by-2.5 and (b) divide-by-1.5.

A block diagram of DETFF and its circuit schematics are shown in Figure 4-6. In Figure 4-

6(a), when CLK is high, the value stored in LATCH1 is multiplexed to the output while









LATCH2 is transparent. When CLK is low, the value stored in LATCH2 is multiplexed to the

output while LATCH1 is transparent. Hence, DETFF samples the input data at both the rising

and falling edges of clock signal. On the other hand, SETFF (single edged triggered flip flop) is

triggered at only either the rising or the falling edge of clock signal. As shown in Figure4-6(d), a

DETFF can incorporate AND function by merging the AND function [66] and the DETFF. This

increases the switching speed and reduces the power consumption.
D ------------------I

Q i Mux
I IQ
CLK-- -D CLK-
LATCH1 D Q D D0
DH -
D DO D1
L Qs -S
-CLK
pls LATCH2


(a) (b)




Q Q Q














plus LATCH.
plus LATCH.










4.3.2 8-to-1 Multiplexer and Attenuator

Figure 4-7 shows an 8-to-1 multiplexer (MUX) and an attenuator. The seven frequency

channels from 400MHz to 3GHz of IF generator are assigned to seven ports in the MUX and the

last one port is allocated for an external signal source. The purpose of an attenuator block is both

to reduce signal amplitude, and filter out high order harmonics from the incoming square wave

so that the gm stage of up-conversion mixer can properly deal with the incoming IF signal.

The attenuator consists of three stage programmable RC low pass filters. Since the

frequency of incoming signal can be one of seven different frequencies ranging from 400MHz to

3GHz, the corner frequency of a low pass filter should vary depending on the frequency of

incoming signal. Each RC low pass filter is comprised of a 1-kQ silicide blocked p+ poly silicon

resistor and a capacitor bank, where four digital bits synthesize the required corner frequency.


0 4GHz Switch1 I switch
0 8GHz -
12GHz-- 1kQ 1kQ 1kQ ToPA
1 6GHz 8tol VkA- I I
2 0GHz- IF
--- 24GHz MUX LO(24GHz)
From IF 3 OGHz -
Generator External bl bl -
b2 cap b2 cap b2 cap
3bits b3 bank b3 -bank b3 bank
b4 b4 b4


Figure 4-7. Block diagram of 8-to-1 MUX and attenuator.





50fF 100fF 150fF 200fF


b1l- b2- b3- b4--



Figure 4-8. Schematic of capacitor bank.









A schematic of capacitor bank is shown in Figure 4-8. There are 4 different sized

capacitors with each branch connected to ground through a switching transistor. When the

transistor is turned on by connecting the gate of transistor to VDD, the capacitor connected to the

transistor is activated. Thus, depending on the particular IF frequency selected by the 8-to-1

MUX, the control bits bl, b2, b3, and b4 can be connected to either VDD or GND to synthesize

appropriate corner frequency for the RC low pass filter.

For N identical stages, overall 3-dB bandwidth is given by [19]

c0)d ,,,, 2 1 (4-1)

where os3dB is the 3-dB bandwidth of each stage. For three identical stages, overall 3-dB

bandwidth is then -0.5 os3dB. For example, in the case of 400MHz IF signal, the 3-dB bandwidth

of each stage (osdBO) should be 800MHz rather than 400MHz. With a resistor 1KQ, the total

capacitance required to achieve the bandwidth of 800MHz for each stage is then -200fF. This

capacitance can then be synthesized by assigning b b2 b3 b4 of either 0 0 0 1 or 11 1 0.

A metal to metal capacitor using metal 5-8 layers is used for the capacitors in the bank.

The width and length of all transistors shown in Figure 4-8 are 5tm and 120nm, respectively.

Illustrated in Fig 4-7, there are two extra switches switchl and switch) that enable incoming

signal to bypass the RC stages for measurement purpose. When both switch and switch are

turned on, signal would undergo smaller attenuation. Due to the large area of capacitor banks, the

area occupied by the 8 to 1 MUX and attenuator is 320[tm by 264[tm.

4.3.3 Three Stage LO Buffer

The three stage LO buffer that interconnects the 24GHz output of CDR and the LO port of

up-conversion mixer separated by -600am is shown in Figure 4-9. Since the operating frequency

is as high as 24GHz, the inductance of metal lines between LO buffer stages should be properly









accounted. The width of line inductors ML1, ML2, and ML3 are 2am, 1.2am and 3am,

respectively. The lengths ofML1, ML2 and ML3 are 220am, 200am, and 160am, respectively.

ML1, ML2, and ML3 are all made of metal 8. The simulated corresponding inductance values from

ML1, ML2, and ML3 are around 220pH, 200pH, and 160pH, respectively. The Q-factor of L1, L2,

and L3 are chosen to be around 5 to accommodate the process variation. The size of all

transistors Mnl~Mn6 is 14m/120nm. The supply voltage for the buffer is 1.5V.

VDD VDD VDD


L1: 350pH L2: 500pH L3: 350pH


Mn4 ML1 Mn5 ML2 Mn6 ML3


220um 200um 160um
OUT
IN- Mn1 Mn2 Mn3






Figure 4-9. Schematic of three stage LO buffer.

4.3.4 Up-conversion Mixer

Figure 4-10 shows the schematic of an up-conversion mixer which is configured as a

double balanced mixer to reduce the LO feedthrough. Because of the voltage head room

limitation, the bottom current source is taken out. The LO port is driven by the 24-GHz CDR

output through the 3-stage LO buffers. The IF port of mixer is connected through the 8:1 MUX

and attenuator to the IF frequency generator. IF signals should be sufficiently small such that

transistors Mni and Mn2 can function as the gm stage of mixer without being distorted. In

addition, harmonic control of IF signal is required in order to prevent unwanted harmonics of

selected signal from falling into the neighboring channel as interfering signals.









The size of transistor Mni and Mn2 in the gm stage is 200pm/120nm. The size of transistors

Mn3~Mn6 in the switching stage is all 30[pm/120nm. The simulated conversion gain is around

OdB. The supply voltage of up-conversion mixer is 1.5V. The simulated power consumption is

17.6 mW.
"" ......... ... ......... "
RF Frequency
Motorl- 24.4GHz VD
Motor2~ 24.8GHz
Motor3- 25.2GHz p 235pH 235pH
Motor4~ 25.5GHz
RF+ RF-
Motor5~ 26.0GHz RF
Motor6~ 26.4GHz
SMotor7 .27.0.GH..

LO Frequency LO+ Mn3 Mn Mn, LO+
24GHz

IF Frequency ... M Mn6: 30um/120nm
Motorl- 0.4GHz C1 C2
Motor2~ 0.8GHz
Motor3~ 1.2GHz I7 Mn1 Mn1, Mn2:200um/120nm Mn2
Motor3- 1.2GHz
Motor4- 1.5GHz IF+ i
S1 R2 i -
MotorS~ 2.0GHz
Motor6~ 2.4GHz
**..Mtor .OG Vblas Vbias
Mo,.......tor7.. 3.....0GH. z.. .

Figure 4-10. Schematic of up-conversion mixer.

Figure 4-11 shows how a mixing process generates undesired interferers from the

harmonics of IF signal and how the undesired interferes affect signals in the neighboring

channels. For instance, the 3rd harmonic of IF signal mixed with LO signal produces an

interferer at 25.2GHz, which happens to be the same desired RF frequency of motor 3 at

25.2GHz. The 5th harmonic of IF signal mixed with LO signal also generates an interferer at

26.0GHz, which is the same frequency as the desired RF frequency of motor 5 at 26.0GHz. The

interferer at 26.0GHz due to the 5th harmonic of IF1 signal should be negligible because of small

signal power. However, an interferer at 26GHz is amplified by the higher gain in the following









stage. Because the power amplifier following the mixer has a tuned gain response with a peak

gain occurring at around 25.6GHz, the interferer at different frequencies are amplified with

varying gains. Finally, the 3rd harmonic of IF2 mixed with LO produces an interferer at

26.4GHz, which is the same frequency as the desired RF frequency of motor 6 at 26.4GHz.

Other harmonics of IF signal mixed with LO are all out of band of interest. In summary, it is

important to have IF generator to be followed by an tunable filter that also attenuates the IF

signal.


Freq 3rd 5th
(GHz) (GHz) (GHz)
1 0.4 1.2 2.0


RF Freq Interferer
(Motor) (GHz) (GHz)
1 24.4 1.%25.i..) 266'.0


2 0.8 2.4 2 24.8 ..::26'.
3 1.2 3 25.2' '
4 1.5 4 25.5
5 2.0 ~ 5 26.0 <-..... --- ...
6 2.4 6 26.4
7 3.0 7 27.0


LO:24GHz

Figure 4-11. Generation of undesired interferers by mixing harmonics of IF signal with LO
signal.

4.3.5 Power Amplifier

A single ended schematic consisting of three pre-amplifying stages and a class-E type

power amplifier [67], [68] is shown in Figure 4-12. The pre-amplifying stages help to increase

the signal swing thereby resulting in complete switching in the PA at the last stage. In the

schematic, there are two NMOS switches. With the help of these two NMOS switches at the 2nd

and 3rd stages, the LO signal can be amplified and quenched based on Datain signal. The 50-

Mbps amplitude modulating signal applied in the "Datain" terminal generates ASK modulated









signal at the PA output. For L3-L6, circular shaped inductors with top two metal layers (metal 7

and metal 8) shunted together are used to increase inductor Q.
......................... --------------------------------------
Inductor V0D12 VDD4
L1~453pH
L2~254pH L L2
L3~326pH
L4~388pH L3 L4 4 P
L5~189pH PA output
L5~189pH2 M
L6~320pH 2 4 75fF
d 75fF
46fF 75fF
From mixer L, 1
M5


IVb3 ]--I pVb4
Datain -
................. ...........I........................... I
'-




attenuator
Pre-Amplifier Output Stage
--------------------------------------------
M1, M2: 14pm / 120nm M5: 40pm / 120nm
M3, M4: 28pm / 120nm M6: 100pm / 120nm

Figure 4-12. Schematic of power amplifier.

The PA is designed to generate 7dBm output power at all frequencies from 24.4 to 27 GHz

with VDD of 1.5V. The PA efficiency at the last stage is 33%. The overall PA efficiency is 27%.

OP-1dB is designed to be around 7.4dBm. The PA consumes 50mW and the PA chip size is

634[m by 700pom. The designs and measurement results of a duplexer and a 4mm on-chip dipole

antenna are described in [8], [15]. Finally, the simulated power consumption of each block in

TX is summarized in Table 4-2. The PA dissipates -38% of the total power in TX.

Table 4-2. Simulated power consumption in TX at motor node
IF MUX & Div2 &
Block CDR MIX PA LO buffer & D Total
generator Div2 buffer
Power
power 20 7.6 50 20.4 22.7 12.2 132.9
(mW)
Percentage 3
Percentage 15 5.7 37.6 15.3 17.1 9.2 100
(%)









4.4 Measurement Results of IF Generator

The standalone test structure of an IF generator together with an 8 to 1 MUX has been

fabricated in the UMC 130-nm CMOS technology. Shown in Figure 4-13 are a die photograph

and a testing PC board. IF generator has been measured on a PCB with the chip directly mounted

on the board (chip-on-board). Sinusoidal signal at 12GHz from a signal generator is applied to

the input of the IF generator by probe-landing directly on the chip. Output signal selected by the

8 to 1 MUX is then measured in the frequency and time domain through a SMA connector.



llt sg Ui

IF gen











Figure 4-13. Die photograph and testing PC board of IF generator.

Figure 4-14 shows the spectrum and waveform of all seven IF signals. The violation of

50% duty cycle in the waveform manifests itself as a growth in the second order harmonic in the

spectrum. In the simulation, only IF signals at 2GHz and 2.4GHz violate 50% duty cycle, which

is acceptable because harmonics fall out of TX bands. However, the measured results reveal that

IF signals at 800MHz and 1.2GHz also do not have 50% duty cycle in addition to the IF signals

at 2GHz and 2.4GHz.













Ref 0
Norm
Log
10
dB/


dBmn


dBm


Mkr2 1.200 GH
-13.31 dBm


Rtten 10 dB


I I 2 I


S 1U ,1 1H .I I I
1 (1) Freq 488 MHz -1.63 dB0
2 (1) Freq 1.288 GHz -13.31 dBm
3 (1) Freq 2.658 GHz -19.33 dBm


Attend 10 d~..


Ref 0
Norm
Log
10
dB/


IM, I
: ..


Freq 858 MHz
Freq 1.640 GHz
Freq 2.4A4 6Hz


IMKr 2.4V bMZ
-22.62 dBm


(a)* i40M. LHz ...S* 1Hz ... .u *
(a) 400MHz


. .









(b) 800MHz


S
i-


(c) 1.2GHz


a-n-


iC


(d) 1.5GHz


Figure 4-14. Spectrum and waveform of IF signals at (a) 400MHz, (b) 800MHz, (c) 1.2GHz, (d)

1.5GHz, (e) 2.0GHz, (f) 2.4GHz, and (g) 3.0GHz.


Mkrl 1.200 H:
Ref 0 dBm Atten 10 dB 4.05 dBm
Norm
10
dB/









F1I Freqi. F -- ; -2 ,, q
1 <1) Froq 1.244 6Hz 4.5 dBHo
2 (1) Freq 2.444 SHz 15.71 dBF
3 (1) Fr4e 3.699 GHz 22.77 dBo


Mkr3 4.500 GH
dBm A tten 10 dB 15.00 dBm





____--------------jA-I--W-I----W | ----W


Ref 0
Norm
Log
10
dB/


II:1 1 I:: 1 1
1 (1) Freq 1.5588 Hz
2 (1) Freq 3.588 GHz
3 (1) Freq 4.588 GHz


2I 11 )
1 (1)
5 (1)


-4.75 dBm
15.17 dBn
22.62 dBE


-8.18 dBm
32.33 dBm
15.88 d6m


r'r ..... ',... I-iq r T'- r' I ( I.... r l ''F r T


I













Mkrl 2.000 GHz
Mef 0 dBm Rtten 10 dB 4.23 dBm
*orm


iB/


cSm

*f3l


1111' 1 'I J 1 1 I'
( .-. -..i G^ : l& j ;'j, !. L .


(e) 2.0GHz


Mkr3 7.2 GIHz
Ref d dBm Atten 1 d3.93 dBm













ReS LI 1 I ll. 1 1
Tark race Type Aplitude
Fr-q 4.0e (H 2.4GHz
3 1) Freq 7.2eO S1l 3.93 3 dDn.
3 ____ yj ___ Frea _____ 7.288 SHa ______ -33.93 d~m________|


Rtten 10 dE


Mkr3 9.000 GHr
-28.02 dBm


dBm


9-


3.70 dBm
-42.05 dBm
20.02 dBm


1~~~~ ~ ''~-111 ''..


(1) Freq
(1) Freq
(1) Freq


3.000 GH:
9.000 EH]


S


'. 4
a


(g) 3.0GHz


Figure 4-14. Continued


Figure 4-15 shows interferer generation including the effects of unexpected 2nd order


harmonics of IF signals at 800MHz and a 1.2GHz. In particular, the 2nd order harmonic of


800MHz signal at 1.6GHz mixed with 24GHz generates an interferer at 25.6GHz that is only


100MHz away from the RF frequency of motor 4 at 25.5GHz. In addition, the 2nd order


harmonic of 1.2GHz at 2.4GHz mixed with 24GHz generates an interferer at 26.4GHz which is


Wef 0
lorm
.09o
.0
JB/


HAv

11 SP


.J

, ,,, ,









the RF frequency of motor 6. Table 4-3 summarizes the simulated and measured duty cycles of

IF signals. The problems of non 50% duty cycle of IF signals at 800MHz and 1.2GHz result

from the fact that output waveforms of divide-by-1.5 and a divide-by-2.5 that have originally

40% and 33% duty cycle respectively are not often fully restored to the 50% duty cycle by a

subsequent single divide-by-2 circuit. Since the amount of duty cycle violations in the output

waveforms are small, adding a simple duty correction circuit after a divide-by-2 is suggested to

fix these problems.


Freq 2nd 3rd 5th
IF
(GHz) (GHz) (GHz) (GHz)
1 0.4 1.2 2.0


I- i


RF Freq Interferer
(Motor) (GHz) (GHz)
1 24.4 25.2) (26


2 24.8 -


3 1.2 2.4 3 25.2 26.4 ,-
4 1.5 4 25.5
5 2.0 1. 5 26.0 ..............
6 2.4 6 26.4 4
7 3.0 7 27.0


LO:24GHz

Figure 4-15. Generation of undesired interferers due to the mixing of 2nd, 3rd, and 5th order
harmonics of IF signals with LO signal.

Table 4-3. Simulated and measured duty cycle of IF signals


IF number 1 2 3 4 5 6 7


IF Frequency
(GHz)
Simulated
Duty Cycle (%)
Measured
Duty Cycle (%)


0.4

50

53.2


0.8

50

59.4


1.2

50

60.8


1.5

50

50.2


2.0

33.3

27.1


2.4

40

45.3


3.0

50

49.4


25.6.) 26:J| '









4.5 Measurement Results of TX Chain

The TRX at motor side has been fabricated in the UMC 130-nm logic CMOS. Shown in

Figure 4-16 is a die photograph of a transceiver. All the circuits and components are fully

integrated. The chip area without the bond pads and 4mm on-chip dipole antenna occupies

1.54mmx2.22mm. The transmitter has been measured on a PCB with the chip directly mounted

on the board (chip-on-board). To characterize the clock recovery and LO generation at the

proposed CDR circuit followed by mixing, modulation, and amplification at the TX chain, the

output spectrum and waveform of ASK modulated signal at the duplexer output are measured

while applying 400Mbps PRBS 231-1 signal to the limiter input in the back end of RX. For this

measurement, the antenna was cut off



4mn dipole anlenna I nlixenr

II




RX I



IN I





Figure 4-16. Die photograph of crystalless transceiver at motor section.

4.5.1 Spectrum of TX Output and Harmonic Control

The block diagram of TX at motor side and measurement setup are shown in Figure 4-17.

An antenna was cut off to eliminate the additional measurement loss and mismatch. The power is









monitored at the duplexer output. This is because only the antenna side has no bond wire the

probe landing is possible only in this direction. Measured power at the duplexer output is around

7dB lower than that of power amplifier output due to the high duplexer loss [8] in the frequency

band from 24.2GHz to 27.2GHz. Table 4-4 summarizes TX power level at the duplexer output

for the 7 motor channels. In the table, power1 specifies TX output power after de-embeding the

cable and balun losses. Measured TX power ranges from the minimum of-4.6dBm to maximum

of 2.3dBm, which are close to the target power of OdBm. Spectrum of TX output with an

external IF source are presented in Appendix B.


Laser
cutting Monitoring point of the differential TX output power




I MIX CDR
| iDuplexer PA II

400Mbps
ATTEND& MUX & IF GEN PRBS 231-1


Figure 4-17. Block diagram of transmitter at motor side.

Table 4-4. Summary of TX output power level at motor side
Motor 1 2 3 4 5 6 7
Channel (GHz) 24.4 24.8 25.2 25.5 26.0 26.4 27.0
Power (dBm) -10.6 -8.6 -4.6 -8.4 -4.0 -6.8 -4.84
Cable & balun loss
6.0 6.4 5.9 6.4 6.3 6.8 7.1
(dB)
Power' (dBm) -4.6 -2.2 1.3 -2.0 2.3 0 2.3
*Power : output power after de-embedding the cable and the balun loss.












Fet e dBm
Norm
Log

dB/



Marker
124.4000000000 G
L A- 1-10.59 dBm

W1 '2
Ce-rnter :' 4 (H:
Res BH 3 MHz
Marker Trace Type
1 (1) Freq
2 (1) Fraq
('1) Fran


Atten 10 dB


~0~*.


*r .


Mkrl 24.40 GH;
-10.59 dBm


rI' 'I 11 III II '' l' llll"nl llll' Ilmll~'l Ill'
'I lh If'1 I"Hz
VBW 3 MHz Sweep 25 ms (601 pts)
X Axis APplituda
24.48 6Hz -18.59 dBr
25.20 6Hz -34.3S dBm
2R.R88 GH -4q_~R dRm


Figure 4-18. Spectrum of TX motor 1 with attenuator.


Ref 0 d
Norm
Log
10
dB/


Bm


---* .R.t-10-dB
t. IE 1 1..





M ark e r __ ____ .ln \ _J k _i mr I.
I ,, n I I 1 ., I ...


n ettR 10 dB


24.400000000 GH;
S-9.59 dBm n


Mkrl 24.40 GHz
-9.59 dBm


LgRAv


W1 S2
Center 24.40 (
Res BW 3 MHz


Span 10 GHz
Sween 25 ms (601 nts)


Marker Trace Type X Afxi Amplitude
1 (1) Freq 24.40 GHz -9.59 dBm
2 (1) Freq 25.20 GHz -14.35 dBm
3 (1) Freq 26.00 GHz -18.18 dBm
4 (1) Freq 2G.80 GHz -22.14 dBm


Figure 4-19. Spectrum of TX motor 1 without attenuator.

Figure 4-18 shows the output spectrum of TX for motor 1 at the duplexer output with

harmonic control using an attenuator. The peak power level at 24.4GHz is -4.6dBm (-10.6dBm

before de-embedding the balun and cable losses). Since the 3rd and the 5th order harmonics of IF


-










signal at 400MHz fall into the motor 3 (25.2GHz) and 5 (26GHz), the harmonic control is

imperative to limit this problem.

The 3rd and 5th harmonics of 400MHz mixing with 24GHz turn out to be -28.5dBm at

25.2GHz and -42.7dBm at 26GHz, respectively. The power difference between the undesired

interferer at 25.2GHz and the desired signal of motor 3 at 25.2GHz is 30dB (=1.3dBm-(-

28.5dBm)), which should be sufficiently large enough to ignore the contribution of the interferer.

For comparison, the spectrum of TX motor 1 at the duplexer output without attenuator is shown

in Figure 4-19. In this case, the power difference between the undesired interferer at 25.2GHz

and the desired signal at 25.2GHz is only 9.8dB (=1.3dBm-(-8.5dBm)), which is not negligible.

For the 5th order harmonic of 400MHz, the power difference between the undesired interferer at

26.0GHz and the desired signal at 26.0GHz is 45dB (=2.3dBm-(-42.7dBm)), which should be

sufficiently large. The power difference without an attenuator is 14.2dB (=2.3dBm-(-11.9dBm)).

Figure 4-20 shows a zoomed-in spectrum at the TX motor with span of 100MHz.

I| Mkrl 24.400 0 GH2
Fef 0 IBr., Atten 10 dB -11.53 iBr.
Nor'ini
Log ; i .
10 .
dB/

;.....................
Marker
24.400000000 GHz :
Lgn -11.53 dBm

S3 FC





Cen:ei 2.40.') Ci1-1z Span 100 MHz
#Res BW 10 kHz VBW 10 kHz *Sweep 4 s .6ul pts)

Figure 4-20. Zoomed-in spectrum of TX motor 1.











Ref 0 dl
Norm
Log
10
dB/


Bm


Atten 10 dB


Marker_ I
24.800000000 GHz-
-10.89 dBm --,r -


iiI. I I y i


11111111111


Mkrl 24.80 GH2
-10.89 dBm


Figure 4-21.


LgAv
Center 24.80 GHz
Res BW 3 MHz


VBW 3 MHz


Span 10 GHz
Sweep 25 ms (601 pts)


Marker Trace Type X Axis Amplitude
1 (1) Freq 24.80 GHz -18.89 dBm
2 (1) Freq 25.60 GHz -23.95 dBm
3 (1) Freq 26.40 GHz -33.26 dBm
4 (1) Freq 27.20 GHz -43.82 dBm

Spectrum of TX motor 2 with attenuator.

Mkrl 24.80 GHz
ef 0 dBm Ftten 10 dB -7.02 dBm
orm '''\ .. .
Log \ = : 2 4 %


S Marker -
24.800000000 GHz




gAv

enter 24.80 GHz Span 10 GHz
Res BW 3 MHz VBW 3 MHz Sweep 25 ms (601 pts)
Marker Trace Type X Axis Amplitude
1 (1) Freq 24.80 GHz -7.02 dBm
2 (1) Freq 25.60 GHz -17.70 dBm
3 (1) Freq 26.40 GHz -14.98 dBm
4 (1) Freq 27.20 GHz -28.73 dBm


Figure 4-22. Spectrum of TX motor 2 without an attenuator.

Figure 4-21 and 4-22 show the output spectrum of TX for motor 2 at the duplexer output

with an attenuator and without an attenuator, respectively. The unexpected 2nd harmonic of the IF

signal at 800MHz falls into the 25.6GHz which is only 100MHz away from the RF frequency for

motor 4. The power difference between the undesired interferer at 25.6GHz and the desired


.~.- .
'.wY ~s'?


-1--1










signal at 25.5GHz is 15.6dB (=-2dBm-(-17.6dBm)) for the case with an attenuator, and 9.3dB

(=-2dBm-(-11.3dBm)) for the case without an attenuator. The power differences in both cases

are not large, which may cause desired signal at motor 4 to experience distortion. The 3rd order

harmonic of IF signal at 800MHz falls into the motor 6 (26.4GHz). The power difference

between the undesired interferer at 26.4GHz and the desired sinal at 26.4GHz is 26.5dB

(=0dBm-(-26.5dBm)) for the case with an attenuator. Without an attenuator, the power

difference is only 8.2dB (=-OdBm-(-8.2dBm)), which should not be acceptable.

The output spectrums of TX for motor 3 at the duplexer output with an attenuator and

without an attenuator are shown in Figures 4-23 and 4-24, respectively. Similar to the motor 2

case, the unexpected 2nd order harmonic of the IF signal at 1.2GHz mixed with the LO at

24GHz falls into the 26.4GHz which is the RF frequency of motor 6. The power difference

between the undesired interferer at 26.4GHz and the desired signal in the channel for motor 6 is

19.4dB (=OdBm-(-19.4dBm)) for the case with an attenuator. The power difference is only 9.4dB

(=OdBm-(-9.4dBm)) for the case without an attenuator, which may not be large enough. Figure

4-25 summarizes the impact of interferer signals on desired channels for the case with attenuator.

Re dBm Rtten 1 Mkrl 25.20 dGHz
Ref 0 dBm Fltten 10 dB -10.80 dBm


Norm
Log
10
dB/


S.... ..-.



lr^ ke r ., I .. ,,.,,,..,,,. ..,,,ir B ili^ iihiliit f i^ .. L ... ,z-j^ -t
,., ,.,.


LgAv -11.8 dBm

Center 25.20 GHz Span 10 GHz
Res BW 3 MHz VBW 3 MHz Sweep 25 ms (601 pts)
Marker Trace Type X AxIS Amplitude
1 (1) Freq 25.20 GHz -10.80 dBm
2 (1) Freq 26.40 GHz -26.17 dBm
3 (1) Freq 27.60 GHz -38.22 dBm
4 (1) Freq 28.80 GHz -44.86 dBm

Figure 4-23. Spectrum of TX motor 3 with attenuator.









Ref 0 d
Norm
Log
18
dB/


Bm


Atten 10 dB


SMarkerI I. .11. i
,arker, l ,,,,ia i^ J i L~ l ,,,~ii l,,iL ^ -j


Mkrl 25.20 GH2
-6.56 dBm


Center 25.20 GHz Span 10 GHz
Res BW 3 MHz VUBW 3 MHz Sweep 25 ms (601 pts)
Marker Trace Type X Axis Amplitude
1 (1) Freq 25.20 GHz -6.56 dBm
2 (1) Freq 26.40 GHz -16.20 dBm
3 (1) Freq 27.60 6Hz -19.94 dBm
4 (1) Freq 28.80 6Hz -25.85 dBm


Figure 4-24. Spectrum of TX motor 3 without attenuator.

30dB 15.6dB 45dB 19.4dB
A ----A----- A



All^A l


24.4 24.8 25.2
24.4 24.8 25.2


25.6 26.0 26.4
25.6 26.0 26.4


I 2
26.8 27.2 GHz


Desired power -4.6 -2.2 1.3 -2.0 2.3 0 2.3
(dBm)
Interferer power -28. -17.6 -42.7 -19.4 -
(dBm)

Figure 4-25. The impact of interferer signals on desired channels with attenuator on.

4.5.2 ASK Modulation (Carrier at 26GHz Amplitude-modulated by 25MHz Modulating
Square Signal)

A transmitter that radiates an un-modulated carrier power will send out half of the power

when it is ASK modulated by a data with 100% transition. For instance, a 26-GHz transmitter

that radiates ImW of un-modulated carrier power will radiate only 0.5mW of power when it is

ASK modulated by the 01010101 data pattern. Furthermore, of 0.5mW, 0.25mW will be in the

carrier lobe and the other 0.25mW will be divided among the side lobes. Therefore, the carrier of


A








ASK modulated signal has 6dB lower power than un-modulated carrier power as shown in

Figure 4-26.


OdBm 632mVPP

(a)


-6dBm
(b) -10dBm

*t + t 4 t **


Figure 4-26. Waveform and spectrum of (a) un-modulated carrier and (b) ASK modulated
carrier.

As shown in Figure 4-27, when a square signal with 50% duty cycle is used as an

amplitude modulating signal, the power difference between the carrier lobe and the 1st side lobe

of ASK modulated signal is 4dB. Thus, the 1st side lobe of ASK modulated signal has 10dB

lower power than un-modulated carrier power.

1


2T


0 1 1
2T T


2 )2
* 3 l2 (Jl_'
* *.4 2
V I 51


32 5
2T T 2T


Figure 4-27. Waveform and spectrum of square wave with 50% duty cycle.
To characterize the ASK modulation of the TX output, one of the seven TX channels,

especially motor 5 (26.0GHz), is selected due to its highest output power. Since a 25MHz


^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^k.


^^^^ ^^^ ^^^^ ^^^ ^^^ ^^^^ ^^^ ^^^ ^^^^ ^^^ ^ 'I


4dB
4!^-... v'











square signal with a 50% duty cycle corresponds to a 50Mbps data with 100% transition density,


a 25MHz square clock is applied for amplitude modulation.


Figure 4-28 shows the spectrum of TX output for motor 5 before and after the ASK


modulation with a 25MHz square wave. Once ASK modulated by on-off keying the signal path


in the Power amplifier, the overall TX power level decreases by -6dB from -7dBm to -


12.65dBm, This is consistent with the illustration in Figure 4-26. In addition, after modulation,


the power difference between the carrier lobe at 26GHz and the 1st side lobe at 25.975GHz or


26.025GHz is 4dB, which means the modulation index is 100%. This can be easily verified by


looking at the waveform in Figure 4-29. The modulation index appears to be indeed 100%.

Mkrl 26.80 GHz Mkrl 26.00 GHz
Ref 8 dBm Rtten 18 dB ..-7.00 dBm Ref dBrm Atten 10 dB .... 12.65 dBm
Horm h* orm / **
109 10

(span 10GHz) q. (span 10GHz)
Marker Marker
26.000000000 GH: 26.000000000 GH:
LR -7.00 dBm 12.5 dB






Center 26.60 GHz .S Span8 i r 26.0 GHz 1 Span 10 GHz
R. BA 3 MHN----BS.3 MHH SMe 25 m- (Al Nt) I MW' i I --7 -") M (01 n.',t
Mkrl 26.888 0 GH Mkrl 26.000 0 GH
ef 0 dBm Atten 10 dB -5.64 dBm Ref 8 dBr Rtten 18 dB -13.48 dBm
0L ,25MHz 25MHz



oi 'e1 ir,11,
1| I I


26.00000000 GHZ Z 2b 00000000 GH;
gAv -5.64 dBm LgR -13.48 dBn
Ss2 Zoom in (span 100MHz) W 2 Zoom in (span 100MHz)
Center 26.0006 GHz Span ."u: 1;,r 2.08 0 H z $pan 188 MHz
Res BH 91s kHz VBH 916 kHz Sweep 1 ms (( ,,, t 910 kHz VBN 910 kHrz Swep 1 r3 (601 pts)
M.Irkr T.. Typ, 1 .rt.e Ty Per Xl ,...pDi Ar 4.
1arker T1) e Tr aH2 -.B 1 (1) Frq I 26.888 0 H2 13,8 B7 R 4dB
S () Freq 25.975 H -S.62 1dB) Frq 2S.975 n GH -17.28 dBm
3 1) Freq 26.2 8 6Xz .5'83 dBm 3 (1) Fr.q 26.02S 0 EHz t &-?.?8 i difference :
M odulation
Before Modulation After Modulation index 100%


Figure 4-28. Spectrum of TX output at motor 5 (26GHz) before and after ASK modulation with
25-MHz square signal.









E[ Cirmol SePip I z fre C'IIra p tLlllke III 0 rFebt= 07 14

"m o 20ns











0fl ,j '-----------1 mw


Modulation index 100% ......................-
~38.46ps (26GHz)

Figure 4-29. Waveform of TX output at motor 5 after ASK modulation with 25-MHz square
signal.

4.5.3 ASK Modulation (Carrier at 26GHz Amplitude-modulated by 50Mbps PRBS 231-1
Modulating Signal)

Figure 4-30 shows the spectrum of TX output at motor 5 before and after the ASK

modulation with 50Mbps PRBS 231-1 data signal. Since the modulating signal is a PRBS data

rather than a clock signal, a spectrum after the modulation shows nulls at the integer multiples of

50MHz from the carrier frequency at 26GHz, which is the typical property for a PRBS signal. A

common way of visualizing long sequences of random data waveform is an eye diagram, which

displays an accumulation of edges and levels of data by folding all of the bits into a short

interval, e.g., typically two or three bits wide. Figure 4-31 shows a waveform of TX output at

motor 5 after ASK modulation with 50Mbps PRBS 231-1 data signal. Accumulation of all of the

bits into a short interval creates this waveform in which each data bits are filled with the carrier

signal 26GHz. Vertical bit boundaries are colored in darker tone.











Mkrl 26.88 GHU MKrir eo..w bU
Ref 0 dBm Rtten 18 dB -5.53 dBm Ref dBm Rtten 1 d .. -1.31 dBm
Normn Norm




26.0o00o000o 0 GHz l .0oooo 00000000


As B. 3 dHH r2 VB 3 U H L S10ee 25 ms (61 Ls) 10e 3 HW 3 Seen 5 m (6 nt
(span 10GHz) (span 10GHz)

enkri 28.00 0 GH Hkri 26.090 0 GH
Ref dBm Rten dB -5.81 dBm Ref dBm Atten 1 dB -1.01 dB
Norm Log 50MHz i 50MHz

dD/ dB/WW f10
A N L i ,I

26.000000000 GH:z 26.000000000 GH
LHv -5.81 dBm LgAv -10.01 dBm
N s3 Zoom in (span 100MHz) NC s2 Zoom in (span 200MHz)
Center 26.880 0 GHz Spen 100 MHz Center 26.088 0 GHz Span 280 MHz
Res BH 910 kHz VBH 910 kHz Sweep 1 ms (681 pts) Res BH 1.8 MHz VB 1.8 MHz Sweep 1 ms (681 pts)
Marker Irce. ryp 4 xis Apll tude Mark.r Trce. Typ. X A.l; AplitudE
1 (1) FR.q 26.88B 2 -6.81 dBk 1 (1 *req 26.8R8 6 -18.81 dBR
2 < Fr-e 25.175 1 6HZ -46.83 dBm 2 (1) roq 2.958 g GH -41.5S dem
i F R -- QR 3 (1) fr.q 26.858 8 6H -36.S3 dBm


Before Modulation


After Modulation


Figure 4-30. Spectrum of TX output at motor 5 before and after the ASK modulation with
50Mbps PRBS 231-ldata signal.


Modulation index 100%


-38.46ps (26GHz)


Figure 4-31. Eye diagram output at motor 5 after ASK modulation with a 50Mbps PRBS 231-1
data signal.


114 ~*~*CII









4.5.4 Wireless Link Test at the Motor TX

The feasibility of establishing a wireless link at the TX motor within the controller board is

demonstrated. A metallic cover is placed -3.5cm above the controller board to emulate the

operation environment, which increases the received signal power [61]. As shown in Figure 4-

32, a 4mm on-chip dipole antenna separated by 5cm from the TX picks up the 26-GHz carrier

signal amplitude modulated by 25-MHz square signal. The CDR was driven with 400-Mbps

PRBS 231-1 signal.


4mm on-chip dipole antenna for
receiving the transmitted signal


Figure 4-32. Setup of wireless link demonstration at TX motor side.

Figure 4-33(a) shows an output spectrum of un-modulated 26GHz carrier signal (CDR

output at 24GHz mixed with IF at 2GHz (24GHz/2/3/2)) at the duplexer output without

modulation. Figure 4-33(b) shows the spectrum of TX carrier signal at 26GHz modulated by 25-

MHz square signal. The -4-dB amplitude difference between the carrier and the first harmonics









at 26GHz +/- 25MHz in Figure 4-33(b) indicates the AM modulation index of 100%. This is also

consistent with the time domain waveform in Figure 4-33(c) where the peak to peak voltage

level is -320mV and off level is -10mV. Since the noise level should be less than the off level,

SNR should be greater than 30dB. Incidentally, the signal power of -11.4dBm (-17.7dBm +

cable/balun loss of 6.3dB at 26GHz) for the 1st side lobe at 26.025GHz in Figure 4-33(b) is

~10dB lower than the un-modulated carrier signal power of -2.15dBm in Figure 4-33(a).


(a) (c)
-320mV
Output power: -2.15dBm
(After de-embedding cable &
balun loss of 6.3dB at 26GHz)
Marker Res BW 10 KHz
26.000000000 GHz VBW 10 KHz
-8.45 dBm Sweep 4 s (601 pts) .
Span 100 MHz

Vll i.hl IIJJI ~-38.46ps
(b) -13.dBm (d)
--13.5dBm
-17.2dBm2 25MHz 1 25MHz -17.7dBm
-62.32dBm -58.3ldBm -62.68dBm

26000000000 'Hz '26'iGHIII
-13.48 dBm 26GHz
Res BW 910KHz, VBW 910KHz, Sweep 1ms, Span 100MHz Res BW 100KHz VBW 100KHz Sweep 12.08ms Span 100MHz

Figure 4-33. Spectrum of TX output (a) before modulation (b) after ASK modulation with 25-
MHz square clock signal. (c) Waveform of TX output after ASK modulation with
25MHz square clock signal. (d) Spectrum of received 26-GHz carrier signal
amplitude modulated by 25-MHz square signal (with metallic cover).

With the measured TX signal power at the duplexer output of-11.4dBm (-17.7dBm +

cable/balun loss of 6.3dB at 26GHz) at 26.025GHz, the measured signal power at 5 cm

separation shown in Figure 4-33 (d) is -56.4dBm (-62.68dBm + cable/balun loss of 6.3dB at

26GHz) or -53.4dBm (2 ASK sidebands). For the case of 15cm separation, received power is

expected to be~-64.7dBm. This is -10 dB higher than the sensitivity target for BER of 10-13. This

margin can be utilized to accommodate the variations of propagation loss and implementation









loss of receiver. Table 4-5 summarizes the TX power consumption. The measurement results

suggest that a transmitter integrated with a receiver incorporating a CDR can bypass the problem

of providing external frequency reference, which is a fundamental technique needed for a two-

way wireless inter-chip data communication for return path isolation applications.

Table 4-5. Power consumption of transmitter at motor side
IF LO MUX & DIV2 &
TX blocks CDR MIX PA L M & Total
generator buffer DIV2 buffer
Power
power 18.3 17.6 91.2 25.8 22.7 16.3 191.9
(mW)

4.6 Conclusion

The integrated circuit implementation of the FDMA transmitter at the motor section is

presented in Chapter 4. The original transmitter architecture has been simplified by the new CDR

architecture that merges the PLL function into the VCO of CDR, thereby reducing the circuit

complexity, chip area and power consumption. Individual TX blocks such as an IF generator, an

8-to-1 multiplexer, 3-stage LO buffers, an up-conversion mixer, and a power amplifier are

described in both circuit and system levels.

The measured duty cycles of IF signals at 800MHz and 1.2GHz are off from 50%. This

generates unexpected interfering signals at the other channels. Un-modulated TX carrier powers

at the duplexer output are measured for all 7 motor channels. The output Power ranges from the

minimum of -4.6dBm to maximum of 2.3dBm. The output powers for motor 3, 5, 6, and 7 satisfy

the target power of OdBm. Finally, the feasibility of establishing a wireless link using the

transmitter is demonstrated. A 4mm on-chip dipole antenna separated by 5cm from the TX

successfully picks up the 26GHz carrier signal amplitude modulated by a 25MHz square signal.

The total TX power consumption is -192mW where PA dissipates 48% of the total TX power

consumption.









CHAPTER 5
DUPLEX OPERATION AND LINK DEMONSTRATION

5.1 Introduction

A link between the TX at a deadtime controller and RX at a motor side is demonstrated in

Chapter 5. To fulfill the link demonstration, ensuring the satisfactory performance in both TX

and RX is the first priority. Furthermore, at a motor side, the feasibility of a full-duplex

capability of TRX with an on-chip antenna should be verified to make sure the TX operations do

not significantly degrade or, in worst case, disrupt RX performance.

A block-level schematic of RX chain at motor side is illustrated in Figure 5-1. The

differential LNA output is changed to a single-ended signal using an active current-mirror balun,

which is followed by multiple filter stages and amplification stages along the RF signal path. The

schottky barrier diode (SBD) is connected in shunt as a half-wave rectifier for signal detection

[14]. The down-converted signal is then filtered using a 2nd order 1.2-GHz wide Chebychev

low-pass filter. The filter is followed by a 3-stage differential baseband amplifier and a buffer for

driving 500.

RF Section Baseband
LNA with 2nd order amplifier
2nd order 3rd order LPF section
BPF BPF RF buffer,------_ -" 4
-- ------------------ -- Multi-level
S', ,I I ~,CDMA signal

S.....- Lim iter ,
Duplexer ___--------_________ ______-- --- ----
Active RF amplifier SBD! ,
balun with 3rd order based C
BPF rectifier Recovered
Clock

Figure 5-1. Block diagram of receiver chain at motor section.









In the 1 st version of chip, only the RX was integrated. A PC board for the RX

measurement was designed and fabricated to characterize the RX chain. Later, however, when

both RX and TX at motor side are integrated in the same chip, the increased number of bond

pads resulted in longer bond wire between chip and PCB pads. In addition, increased PCB size

resulted in longer FR4 traces on the PCB, that increased the parasitic inductance. These can

cause stability problems.

A main cause of oscillation in the presence of parasitic inductance comes from a single-

ended multistage baseband amplifier within the original RX chain. Two examples of instability

due to parasitic inductance are illustrated in Figure 5-2.


/ Lpar VDD VDD






,,, Lpar
I I

M3 M M2






(a) (b)

Figure 5-2. Positive feed back path due to parasitic inductors in multistage single-ended
amplifiers.

In Figure 5-2(a), transient current thorough a parasitic inductor Lpar due to bond wires and

FR4 traces develops voltage at node P. This voltage feeds back to node Q through R1, possibly

driving the following common-source stages into oscillation. A positive feedback path is shown

using a dotted line. In Figure 5-2(b), a positive-feedback path drawn using a dotted line is created

due to the ground bond wire, Lpar. By contrast, for differential amplifier, voltage developed at

node Q and P in Figure 5-2 (a) appears as a common-mode disturbance. The ground inductance









in Figure 5-2(b) does not affect the primary positive feedback path in the differential structure

[19].

In Chapter 5, a newly designed baseband amplifier is first introduced and the measurement

results of the amplifier by itself are presented. The performance of entire RX chain at motor side

including the new baseband amplifier is characterized. Furthermore, a full-duplex operation of

TRX at motor side is verified. Finally, a wire-line link between the TX at deadtime controller

and the RX at motor side is demonstrated.

5.2 A Differential Baseband Amplifier

5.2.1 Circuit Description

The original baseband amplifier suffered from the oscillation problem under the nominal

VDD and bias condition. Because of this, the original RX was characterized at non-optimum VDD

and bias conditions, which degraded gain, and compromised all RX measurement. Therefore, the

baseband amplifier has been modified from a single-ended to a differential structure which is less

vulnerable to the oscillation problem. However, the differential amplifier also poses the

following design challenges.

An ideal single to differential conversion at the first stage is supposed to generate balanced

differential outputs, showing identical gain and 1800 phase difference between the two

differential outputs. In practical circuits, however, this cannot be achieved. For instance, a bias

current source with finite output impedance and the parasitic capacitor at common-source node

results in imbalance. In addition, the AC gate to drain voltage of the input ports are different

because one is grounded.

Increasing the output impedance of a current source using cascoded transistors reduces the

imbalance. Additional cascaded fully differential stages following the single to differential

conversion at the first stage suppress the magnitude and phase error further. Simulations indicate









both errors become less than 1% by the time single-ended input signal reaches the differential

outputs of final stage.

Another concern of the baseband design is DC offset problem due to the mismatch of

differential pair and load resistors. Inserting AC coupling capacitors between stages could

prevent the DC offset problem. However, choosing a huge capacitor to avoid "DC wander" in

high pass configuration for AC coupling always accompanies the parasitic capacitor, which

reduces the bandwidth of a baseband amplifier below the requirement. Since a baseband

amplifier needs to process 400-Mbps data stream (same as 200MHz for 100% transition),

accounting for the 3rd order harmonic of 200MHz, the overall bandwidth of amplifier should be

at least 600MHz. Thus the bandwidth of each stage must be at least -1.4GHz according to

Equation (4-1).

VDD BUFFER VDD


1.6K 1.6K 1.6K 1.6K 1.6K 1.6K 75 75
ohm ohm
Vout

L- 40u/120n ,-] 30u1120n 20u/120n "- 48u1120n


,-r 20u1120n I 20u20n 20u/120n
Vbiasup Vbiasup asupibiasupl .Lasu

bias 40u/240n -bias40u/240n --i 40u/240n Vbias- 48u/240n
Vbias_dn I Vbias_dn Vbiasdni I .

I=500uA I=500uA I=500uA I=20mA

Figure 5-3. Schematic of baseband amplifier.

Figure 5-3 shows the schematic of a single to differential baseband amplifier. The

transistor sizes of a differential pair in each stages are chosen to be as big as possible in order to

limit the mismatch induced DC offset while satisfying bandwidth requirement. An earlier stage is










sensitive to the DC offset problem than later stages because signal amplitude increases as signal

propagates through the stages Thus, progressive sizing is employed such that the transistor width

of differential pair is 40pm, 30pm, and 20pm for the 1st, the 2nd, and the 3rd stage, respectively.

To reduce mismatch, a common centroid layout is adopted for the differential pair and silicide

blocked P+ poly resistors in each stage. The last stage is a buffer stage that drives the 50-Q input

impedance of equipment, limiter and ADC.


46u/600n 46u/600n 46u/600n VDD





3ullu *
4u/2.16u 4ull20n
2-( ^ MP5 M,
Vcont Vbias_up


3ullu I=100uA ...** .......
SIM3 i M8 8u/240n
Vbias_dn


I=100uA I=100uA


Figure 5-4. Schematic of the wide-swing cascode current mirror.

As shown in Figure 5-4, a wide-swing cascode current mirror provides gate bias voltages

for current sources in the baseband amplifier. The idea of this circuit is to bias the drain to source

voltages of transistor M8 on the edge of the triode region by setting the gate voltage of M7 at

2VDSAT+VTH such that the cascoded transistors M7 and M8 drop only 2VDSAT, while operating in

the saturation region. In practical short-channel designs, since the output resistance of a

MOSTFET heavily depends on the drain to source voltage, it is imperative to bias M8 deeper

into the saturation region by using a larger gate voltage in M7 in order to increase the output









resistance of cascoded current sources. To raise the gate voltage of M7, and thus increase the

drain voltage of M8, the length of M5 is chosen to be 18 times larger than that of M7 instead of

4-5 times in long-channel designs. The bias circuit generates 100A of current flow through the

mirror transistor M5. The first three stages of baseband amplifier mirrors 5 times of this current

when VDD is 1.5V. The buffer stage draws 20mA at VDD of 1.5-1.8V. Additionally, Vcont is

included for adjusting the current, thus the overall voltage gain of baseband amplifier.

5.2.2 Measurement Results

The standalone test structure of baseband amplifier has been fabricated in the UMC 130-

nm CMOS technology. A die photograph and a testing PC board are shown in Figure 5-5. The

baseband amplifier has been measured on a PCB with the chip directly mounted on the board

(chip-on-board). Input and output are terminated with SMA connectors, and 500. Thus, the

voltage gain and power gain are the same.









Amplifier &
bias circuit
I








Figure 5-5. Die photograph and baseband amplifier PC board for testing.

Figure 5-6 shows the waveforms of square inputs at 200MHz with different amplitudes and

corresponding differential outputs. Under the nominal VDD and bias condition, the output









waveforms confirm that the circuit does not suffer from the oscillation problem and generates

balanced differential outputs, also indicating the gain and phase difference between the

differential outputs are negligible. When the input voltage level is above -10mVpp, the measured

duty cycle difference between differential outputs exhibits less than 1% error from 50%, which

implies nearly 180-phase difference between the differential outputs is achieved. As the input

level increases, the balance improves.

The voltage gain of baseband amplifier is 34dB when the input voltages of 6.8-mVpp in

Figure 5-6 (a) and 20-mVpp in Figure 5-6(b) are applied. For larger input voltage of 30-mVpp in

Figure 5-6(c), measured gain is reduced to 32dB. Thus, IP1dB of baseband amplifier occurs at the

input power level somewhere between 20mVpp (-30dBm) and 30mVpp (-26.5dBm). By changing

Vont, the voltage gain can be varied by at least +/- 3dB from 34dB.

The measured worst case rise/fall time (10% to 90%) shown in Figure 5-6(b) is 573ps,

which is 11.5% of a data period of 5ns. The rise time of 573ps can be used to estimate the signal

bandwidth [69].

0.35
freq-3dB (5-1)
rise time

From Equation (5-1), the estimated signal bandwidth is equal to 611MHz, which is close to

bandwidth design target of 600MHz. The measured frequency response in Figure 5-7 shows that

the 3-dB bandwidth is 670MHz. The VDD of bias circuit and first stages of baseband amplifier

are 1.5V. The circuit draws 2.2mA. The buffer stage has a separate VDD of 1.8V and consumes

22mA. The total power consumption is 43mW. Table 5-1 summarizes the measurement results.









S '1.1 1 I Ii I i 1~-


Zij
T- J
4--:


(a)


6.8mVpp


. j CZ


Ij








IS


z w"-1' 'l.:: 1 .-" "l* ." j I 1 .. IJ'" A."l ..'c :'w --.Z I" ; -w' w


-F
4- '


- I I .1 I .ii


(b)


I -- I I,11- 1


.- 1.1 -_ --, I- :1 1- "Il- 1 1 ... ... Ij


. i .. .. H


Psi

Ii .


J I'I" 1 :' I I::


I I iu m I. .1- I I II ip
.:.- -. 1 .






4 llI FM

30mVpp ..
580mVpp



Figure 5-6. Waveform of a single-ended square wave input at 200MHz. Differential outputs
when input voltage level is (a) 6.8mVpp, (b) 20mVpp and (c) 30mVpp.


20mVpp


I550mV

550mVpp

* I 1 '":: I ,.) I .. .. -' I "o'. ... I ;,. -' I


170mV

170mVn _


YrYLr ~


i- I I iji- : I 1 I" Il- 11


..... ** i













30- ----------- Freq-3dB: 670MHz


S25


20- I


15 "**
100 1000 10000
Frequency (MHz)

Figure 5-7. Measured 3-dB bandwidth of baseband amplifier in frequency domain.

Table 5-1. Summary of measurement results of baseband amplifier
Single-ended input
Single-ended input -33.3 -30 -26.5 -24.9
power (dBm)
Single-ended input 6.8 20 30 36
voltage (mVpp)
Single-ended output 170 550 580 610
voltage (mVpp)
1. Rise/fall time (ps) 581/560 566/552 552/543 491/479
2. Rise/fall time (ps) 602/427 573/463 553/493 484/445
1. Duty cycle (%) 52.2 50.2 50.3 50.4
2. Duty cycle (%) 49.3 49.2 49.4 49.7
Single to differential
34 34 32 30.6
Voltage Gain (dB)
3-dB bandwidth (MHz) 670
IP1dB (dBm) Somewhere between -30 -26.5
Bias circuit &
Sc Last buffer stage Total
first 3 stages
Power dissipation fi 3 stages
3.3mW 39.6mW
43mW
(1.5V / 2.2mA) (1.8V / 22mA)
*1 and 2 indicate each waveform of differential output signals.

5.3 Measurement Results of Full RX Chain for Motor Section

The entire RX chain including an updated baseband amplifier at motor side is

characterized with a 2-level amplitude modulated signal. Without the oscillation problem under









the nominal VDD and bias condition, RX successfully demodulated the baseband data at

400Mbps from an incoming ASK signal in which the carrier frequency at 16.8GHz is amplitude

modulated by PRBS 231-1 signal. Furthermore, the CDR locked to the incoming 2 level data at

400Mbps, and generated the clock and LO signals at 400MHz and 24GHz.

In Figure 5-8, a block diagram of RX chain at motor side and measurement setup are

illustrated. An antenna and a duplexer are laser-cut. The amplitude modulated RF signal is

externally generated using a commercial double side band (DSB) passive mixer. Mixing an LO

signal at 16.8GHz and an IF signal at 200MHz square signal or 400Mbps PRBS signal produces

a double-sideband large-carrier (DSB-LC) AM signal. Since the designed RX architecture

utilizes square-law detection (non-coherent rectifier), to avoid signal distortion, the amplitude

modulated signal should contain carrier signal with DSB, ensuring the modulation index is

always less than 100%. The RF signal from the mixer output is connected to a balun through the

cable, followed by a GSSG probe landing on the bond pads at the input of LNA.

Balun &
Ban & Active SBD rectifier
GSSG probe LNA balun Amp BB Amp

B8
South

Limiter
cable External DSB
passive mixer
CDR
r--------..^ -<. 16.8GHz
;AM modulated' RF LO -C
Sinal Recovered Clock
Sial. IF @400MHz

r--------------
I 200MHz clock /
:400Mbps PRBS signal I


Figure 5-8. Block diagram of RX chain at motor section and measurement setup.









The output power, Pout versus the input power, Pin of RX chain is plotted in Figure 5-9 by

applying ASK signals with varying power level to the LNA input while maintaining 100%

modulation index. The carrier frequency is 16.8-GHz and amplitude modulating signal is 200-

MHz single tone sine wave. In this plot, the power gain of the amplifier is given by the ratio of

the output power to the input power. The carrier power does not directly contribute to the output

power after demodulation because it does not contain any modulation information. Thus, the

practical power gain should be computed by subtracting the input side band power from the

output power rather than the input carrier power in a dB scale. The 1 dB compression point,

IP1dB, occurs at input sideband power of --45dBm. The slope of plots indicates a 2-decade output

power increase for an 1-decade input power increase because of the square-law detection.

0

-10 Sideband r

-20

E -30-

S-40 Carrier
0
-50

-60 0

-70
-75 -70 -65 -60 -55 -50 -45 -40 -35 -30
Pin (dBm)


Figure 5-9. RX output power as function of input single sideband power and input carrier power
(AM modulation index of 100%).

The BER of RX chain is measured to figure out the sensitivity of RX chain. The BER

measurement setup is described in section 5.4.1 (Figure 5-13). As shown in Figure 5-10, the









measured sensitivity of RX chain for BER of 10-12 and 400-Mbps data rate is --45dBm. The high

sensitivity of RX chain is due to the low gain of RF section in the RX chain. Compared to the

design target of RF section gain of 40dB for sensitivity of less than ~-60dBm, measured gain of

RF section is ~15dB [14], which results in the significant degradation of RX sensitivity. In order

to achieve BER of 10-12 at even lower sensitivity, RF section should be updated to meet the

design target of -40dB gain.



1.00E-02

1.00E-04

1.00E-06

m 1.00E-08

1.00E-10

1.00E-12 --- ---------------- ------

1.00E-14 -
-52 -50 -48 -46 -44 -42
Input Power (dBm)


Figure 5-10. Measured BER versus input power

The performance of an entire RX chain was characterized by applying ASK signal to the

LNA input and monitoring the spectrum and waveform at the end of receiver chain. The carrier

frequency is 16.8-GHz and amplitude modulating signal is 200-MHz square wave signal. The

RMS jitters of recovered clock are also characterized. In the case of the 1st input sideband power

of-45dBm in Figure 5-11(a), demodulated signal output power at BB out is -6.5dBm at 200MHz

in Figure 5-11(b). Waveforms of demodulated data and recovered clock are shown in Figure 5-

1 (c). The peak-peak voltage of data is 400mV. A rising edge of a recovered clock at 400MHz in









CDR samples close to center of demodulated data bits. The jitter histogram of recovered clock at

400MHz shows RMS jitter of 1.78ps in Figure 5-11(d).

0

(a) (b) -10 "-6.5dBm @ 200MHz
-20
-39dBm -30
-45dBm -
-40
-50
-60
16.6 16.8 17 (GHz) -70 ....
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
(c) (d) freq GHz
"' .1.".I -.. .. i lC 3 ... .. ..... .. .. .... ..
SRecovered clock
_Dala .
al D RMS Jitter- 1.78ps




san p a 4q A ls W I5 -





Figure 5-11. Plots of (a) Amplitude modulated 16.8-GHz carrier with 200-MHz square wave at
LNA input. (b) Spectrum of demodulated 200MHz signal at BB output. (c)
Waveforms of demodulated 200MHz signal at BB output and 400MHz recovered
clock at CDR output. (d) Jitter histogram of recovered clock at 400MHz.

For the following RX chain measurement results, 400-Mbps PRBS 231-1 is used to

amplitude modulate 16.8-GHz carrier. Total input power level is kept same as the previous case.

This ASK modulated signal is applied at the LNA input, and output spectrum and waveform are

monitored. Furthermore, a CDR locks to the 400-Mbps data stream from the BB out, and

recovers clock and LO signal at 400MHz and 24GHz. Figure 5-12 shows (a) the spectrum of

ASK modulated signal at LNA input, (b) the spectrum of output demodulated signal at BB out,










(c) the waveform of demodulated data and recovered clock at CDR output, and (d) jitter

histogram of recovered clock.

The jitter performance of recovered clock at 400MHz is measured in the cases of 400Mbps

PRBS 231-1, 223-1, and 2 -1. The RMS jitters are 2.5ps, 2.5ps, and 2.2ps, respectively. For the

first version of RX chip with the oscillation issues, the measured RMS jitters of recovered clock

for 400Mbps PRBS 231-1, 223-1, and 27-1 were 29ps, 28.5ps, and 10.3ps, respectively. Thus, a

significant jitter reduction is achieved in the updated RX chain to provide TX with more stable

and purer LO signal. Table 5-2 summarizes the RX measurement results. The total RX power

consumption is 53mW.

-15

(a) 400MHz 400MHz (b -25



-S5-----------i---- ----------------- ---------------- -------------- -------I -35---------------------------


16.8GHz 400MHz
-85
16 162 164 166 re GHz 170.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
(c) (d) freq, GHz
.... .. .. -. .... .. 3 .... .. _, : .. .. 1
Dala -



,^g1 I| .. l i. ., l,
RMS Jitter-) 2.51ps





n rjj ----Recovered clock '!., .,,..
,I ..,."...I IJ : j ", I ". l A


Figure 5-12. Plots of (a) Amplitude modulated 16.8-GHz carrier with 400-Mbps PRBS 231-1 at
LNA input. (b) Spectrum of demodulated 400Mbps signal at BB output. (c)
Waveforms of demodulated 400Mbps signal at BB output and 400MHz recovered
clock at CDR output. (d) Jitter histogram of recovered clock at 400MHz.









Table 5-2. Summary of RX chain i
Input Power (dBm)
*modulation index
less than 100%
Output power (dBm)
@200MHz
Output Voltage (mVpp)
RX Power Gain in terms of
1st sideband input power (dB)
IP1dB
Sensitivity
for BER of 1012


Power dissipation


measurement results
Carrier: -48 Carrier: -44
1st sideband: -54 1st sideband: -50

-22.7 -14.7

-60 -120

31 35.3

-45dBm

-45dBm

RF section SBD
(,
49.5mW -0.lmW
(1.5V/33mA) (0.6V/0.13mA) (1.


Carrier: -39
1st sideband: -45

-6.5

-240

38.5


BB amp
v/o buffer)
3.3mW
5V/2.2mA)


Total

53mW


RMS with PRBS 231-1 4.70 3.13 2.51
Jitter of with PRBS 223-1 4.59 3.06 2.48
clock at with RRBS 27-1 4.46 2.65 2.20
400MHz with clock input 2.90
(ps) @ 200MHz 9878

5.4 Duplex Operation of TRX at Motor Side

On-chip antennas in low-cost silicon IC technologies have been verified for use in

communication within a chip as well as a beacon (antenna and an oscillator) [10], [70]-[72]. A

20GHz down-converter with an on-chip antenna [11] and a 24GHz transmitter with an on-chip

antenna [12] have been reported. However, there have been no reports of duplex communication

using CMOS transceivers with on-chip antennas. For a two-way wireless inter-chip data

communication for return path isolation application, a full-duplex capability allows for a

communication in both directions simultaneously using RX bands from 15.6-18GHz and TX

bands from 24.2-27.2GHz. This sub-section 5.4 mainly verifies the impacts of concurrent TX

operation on the performance of RX by investigating the degradation of RX BER and RMS

jitters of recovered clock.










5.4.1 Characterization of RX with TX On and Off

A successful duplex operation of TRX requires sufficient reduction of the leakage signal or

noise from TX to RX. The impact of signal/noise coupled from TX on the RX through the

substrate, VDD, GND and bond-wires is investigated by comparing the BER performance of RX

and RMS jitter of recovered clock from the CDR when TX is "on" and "off'.

50Mbps IF Generator Recovered Clock
f modulating @400MHz
PA data

CDR
Pre Amp U-p-Mixer
BLaser Cut Active Amp Limit
hi LNA Balunp

-vIN out
"11 BBAmp
S o i SBD rectifier
Balun &
On-Chip GSSG probe
mesrm ntena ie 5p A External DSB BERT .d
Ac ea D cabl R passive mixer M 00
1I

[AM modulated; I I~200MHz clock/
SSignal i -- 400Mbps PRBS signal
---------' i 16.8GHz i


Figure 5-13. Block diagram of TRX at motor section and measurement setup.

Shown in Figure 5-13 is a measurement setup where a duplexer is laser cut off from the

LNA input to inject input signal while avoiding the 500 mismatch loss. Similar to the

measurement setup in Figure 5-8, the input ASK signal is externally generated and up converted

using a commercial DSB passive mixer. Mixing LO signal at 16.8GHz and 200-MHz square

wave or 400-Mbps PRBS IF signal produces DSB LC AM signal. For BER measurements, a

pattern generator function of BERT is used to transmit the PRBS modulating signals to the

external mixer which generates the ASK signal. On the RX side, an analyzer of BERT compares

the demodulated baseband signals from the output of receiver chain with the transmitted signals










from the generator. The recovered clock from CDR is used as clock signals in the analyzer where

clock signals are synched to the received signals.

In the transmitter, a carrier signal is selected from 24.4GHz to 27GHz based on the choice

of IF signal. The carrier is on-off keyed by a simple switch circuit in the PA. Since a PRBS

pattern resembles the actual modulating signal format used in the system, a 50-Mbps PRBS

signal rather than a clock signal should be applied to the switch input as amplitude modulating

signal.

0 0
(a)
S-20- -20-

g -40- -40



-80 -80
0 200 400 600 800 0 50 100 150 200
Frequency (MHz) Frequency (MHz)
0 0

-20- () -20

-40 -40-

-60- -60-
-80 -80
0 200 400 600 800 0 50 100 150 200
Frequency (MHz) Frequency (MHz)
20 0







-8-80
0 200 400 600 800 0 50 100 150 200
Frequency (MHz) Frequency (MHz)


Figure 5-14. Spectrum of demodulated baseband signal in RX when (a) TX is off, (b) TX is on
and a modulating signal for TX is a 50-MHz clock, and (c) TX is on and a modulating
signal for TX is a 50-Mbps PRBS 27-1 signal. The plots on the right side are the
zoomed-in plots.









It is observed that demodulated baseband signals depend on the type of TX modulating

signal, i.e., clock or PRBS signal. Figure 5-14 shows the spectrum when ASK signal (carrier

frequency at 16.8GHz is amplitude modulated by a 200-MHz square clock with the 1st sideband

RF input signal of --45dBm) is applied to LNA input.

Compared to the case when TX is off in Figure 5-14(a), the spectrum of baseband signal

with TX on reveals a bunch of undesired spurs coupled from the TX side. If the harmonic power

levels are comparable to or exceed the desired baseband signal at 200MHz, CDR fails to lock.

On the other hand, when TX modulating signal is 50-Mbps PRBS signal, the spectrum of

baseband signal is affected much less by the harmonic contents associated with TX as shown in

Figure 5-14(c). This is because the spectrum of PRBS signal is flattened due to spreading.

So far, the demodulated baseband signal at RX is assumed to be a 200-MHz square wave.

However, since the real baseband signal is 400-Mbps data stream similar to the PRBS signal, the

50-Mbps PRBS signal from TX must affect the 400-Mbps demodulated RX PRBS signal

differently because spectra of their signals overlap even though the coupled TX PRBS signal is

relatively smaller than the RX PRBS signal.

In order to quantify these, the RX chain was first characterized by applying ASK signal to

the LNA input and monitoring the RMS jitter of recovered clock in CDR with TX turned on. In

order to characterize the jitter performance in terms of different RF input power, the 1st side

band power of the ASK signal (an LO at 16.8GHz modulated by an IF at 200MHz square signal)

is varied from -45dBm (IP1dB point) to -58dBm (CDR locking sensitivity), below which the CDR

fails to lock. The measured RMS jitter versus the RF input sideband power is summarized in

Table 5-3. The 200-MHz square clock and 400-Mbps PRBS signals are used as the modulating

signal of RF input. The results show that as RF input power decreases, RMS jitters increase.










However, it is noted that the RMS jitter of recovered clock at each RF input power increases by

no more than -lps when TX is turned on. Figure 5-15 shows the plots of RMS jitters

summarized in Table 5-3.

Table 5-3. Summary of measured jitter performance
RF input 1st -58
side band CDR locking -54 -50 -45
power (dBm) Sensitivity

Modulating RMS Jitter (ps) RMS Jitter (ps) RMS Jitter (ps) RMS Jitter (ps)
Signal TX off TX on TX off TX on TX off TX on TX off TX on

200MHz
8.43 9.38 2.90 3.60 1.98 2.20 1.78 2.08
clock
400Mbps
PR0S 271 9.36 10.43 4.46 5.54 2.65 2.76 2.20 2.55
PRBS 2 -1
400Mbps
PRB 231 9.58 10.53 4.59 5.64 3.06 3.10 2.48 2.81
PRBS 2 -1
400Mbps
PRS 2311 9.76 10.64 4.70 5.96 3.13 3.20 2.51 2.86
PRBS 2 -1

10 1 12
5,TX on
S8 (a) 200MHz TX on 10 (b) 400Mbps TX off
square clock TX off 8 PRBS 27-1
6 -
6-
4 -
4-
S2 2
0 0
-60 -55 -50 -45 -60 -55 -50 -45
Input Power (dBm) Input Power (dBm)

12- 12
STX on 10 TX on
10 (c) 400Mbps 10 (d) 400Mbps TX off
10 (c)400Mbps TX off
8 PRBS 223-1 8 PRBS 231
6 E 6
'04 c 4
W 2 W 2-
0 0
-60 -55 -50 -45 -60 -55 -50 -45
Input Power (dBm) Input Power (dBm)

Figure 5-15. RMS jitter plots of recovered clock with and without turning on TX for (a) 200-
MHz square clock, (b) 400-Mbps PRBS 27-1, (c) 400-Mbps PRBS 223-1, and (d)
400Mbps PRBS 231-1 modulating signal for RF input.











Secondly, the BER performance of RX chain versus RF input powers are compared to


further investigate the impact of simultaneous operation of TX and RX.


Table 5-4. Summary of measured BER performance of RX chain at motor side

RF Input 1st PRBS 27-1 PRBS 231_
side band
power (dBm) TX off TX on TX off TX on

Less than Less than 2. -12 58x12
-44 i.ox10-12 L.O 10-12 2.3 x 101 5.8 10-

-45 2.2x10-12 5.3x10-12 6.3x10-11 5.4x10-10

-46 3.3x10-7 7.1x10-6 1.3x10-6 8.4x10-6

-48 6.7x10-5 4.7x10-4 1.1x10-4 4.1x10-4

-50 1.1 x 102 1.9x10-2 2.5 x10-2 4.3 x10-2


* TX on
* TX off


(a) 400Mbps
PRBS 27-1


-50 -48 -46 -44
Input Power (dBm)

I K U PRBS 231-
PRBS 27-1


(c) TX on


-62 -60 -48 -46
Input Power (dBm)


1.00E-02

1.00E-04
1.00E-06

m 1.00E-08
1.00E-10

1.00E-12
S 1.00E-14
-42



1 1.00E-02
1.00E-04

1.00E-06

m 1.00E-08
1.00E-10

1.00E-12

1.00E-14


-44 -42


* TX on
* TX off


(b) 400Mbps
PRBS 231-1


-62 -60 -48 -46 -44 -4
Input Power (dBm)

SPRBS 231-1
t" PRBS 27-1


(d) TX off


-62 -60 -48 -46
Input Power (dBm)


-44 -42


Figure 5-16. BER plots (a) 400-Mbps PRBS 27-1 modulation signal for RF input with TX on
and off, (b) 400-Mbps PRBS 231-1 with TX on and off, (c) TX on with 400-Mbps
PRBS 27-1 and 231-1 modulation signal, and (d) TX off with 400-Mbps PRBS 27-1
and 231-1.


1.00E-02

1.00E-04

1.00E-06

m 1.00E-08

1.00E-10
1.00E-12

1.00E-14
-52



1.00E-02

1.00E-04

1.00E-06

m 1.00E-08
1.00E-10
1.00E-12

1.00E-14









As shown in Table 5-4, the measurements indicate that BER is lower when smaller PRBS

length is used such as PRBS 2 -1. BER is less than 10-12 if the RF input power is larger than -

44dBm regardless of the PRBS length. When RF input power is less than -45dBm, BER

degrades rapidly. At each RF input power level, running TX along with RX indeed degrades

BER performance. However, the extent of degradation due to the TX is less than a factor of 10.

Especially, when input power is greater than -45dBm, the difference is small. In addition, the

degradation of BER is more strongly dependent on the RX input powers than having the TX on

or off. This suggests that the degradation is related to the low gain problem of receiver. If the

gain is increased, the impact of having TX on should be reduced at even low RX input levels.

Figure 5-16 shows BER plots based on the measured data in Table 5-4.

5.4.2 Characterization of RX with TX On and Off using the Chip without Laser Cut

So far, the impact of TX operation to RX performance has been investigated using chips

with the connection between duplexer and LNA input laser cut. However, a concern of this setup

is that the impact of coupling or leakage of TX signal/noise via the duplexer and the on-chip

antenna to the LNA side is not fully captured because of the laser cut. To investigate the effects

of this, circuits without the laser cut are characterized. The new measurement setup is exactly

same as Figure 5-13 except the laser cut. When a probe lands on the chip pads at the LNA input

to apply the RF signal, higher power should be applied to compensate for the mismatch loss

resulting from the probe load. By observing the output signal power at the baseband output, the

RF input power can be estimated using the Pin versus Pout plot in Figure 5-9.

The RMS jitter of recovered clock and the BER performance of RX chain are measured

using RF input 1st side band power of -47dBm. RMS jitter and BER with TX on are measured

and compared to the cases with TX off, and summarized in Table 5-5. In addition, the new

measured data are overlaid in the RMS jitter plots and BER plots in Figure 5-17 and 5-18,










respectively. The measurements indicate the impact of coupling or leakage of TX signal/noise

via the duplexer and the on-chip antenna to the LNA side is negligible. These indicate that full

duplex operation using on-chip antennas are possible.

Table 5-5. Summary of measured RMS jitter and BER performance
RMS jitter of recovered clock with TX on and off
(Effective RF input of -47dBm)
200MHz 400Mbps 400Mbps 400Mbps
Modulating Signal- 7 23 31
square clock PRBS 2 -1 PRBS 2 -1 PRBS 2 -1

RS ier TX off 1.86ps 2.37ps 2.44ps 2.46ps
TX on 2.45ps 2.78ps 2.80ps 2.96ps


RF input 1st side
band power of
-47dBm


BER performance with TX on and off
PRBS 2 -1
TX off TX on 1
2.5x10-7 6.8x10-6 3.


X o1
2x1(


31
PRBS231-
ff TX on
)06 9.5x10-6


(b) 400Mbps U + TX on
PRBS 27-1 X TX off


55 -50
In put Power (dBm)


(c) 400Mbps 0 + TX on
PRBS 223-1 X TX off


Input Power (dBm)


12
10
S8
S6
c0 4
u. 2


Input Power (dBm)


(d) 400Mbps U + TX on
< PRBS 231-1 X TX off


Input Power (dBm)


Figure 5-17. RMS jitter plots at RF input power of -47dBm with TX on and off for (a) 200MHz
square clock, (b) 400Mbps PRBS 27-1, (c) 400Mbps PRBS 223-1, and (d) 400Mbps
PRBS 231-1. The connection between the LNA and duplexer is not laser cut.


(a) 200MHz
square
clock


* + TX on
* X TX off


12
10
C,
8
6 8
0 4
S2
0










1.00E-02 + TX on 1.00E-02 U + TX on
1.E-4 X TX off 1.E4 X TX off
1.00E-04 1.00E-04
1.00E-06 X 1.00E-06
w w
m 1.00E-08 m 1.00E-08
(a) 400Mbps (b) 400Mbps
1.00E-10 PRBS 27-1 00E-10 PRBS 231-1
1.00E-12 -------------------------- ----- 1.00E-12 ------------------------- -----
1.00E-14 1.00E-14- I
-52 -50 -48 -46 -44 -42 -52 -50 -48 46 44 42
Input Power (dBm) Input Power (dBm)

Figure 5-18. BER plots at RF input power of -47dBm for (a) 400Mbps PRBS 27-1 with TX on
and off, and (b) 400Mbps PRBS 231-1 with TX on and off The connection between
LNA and duplexer is not laser cut.

5.4.3 Wireless Demonstration of Duplex Operation at Motor Side

A full-duplex operation of TRX at motor side is observed by picking up signals from both

TX and RX bands at the same time as shown in Figure 5-19


Horn Antenna
Freq: 18~28GHz Spectrum
Gain: 20dBi analyzer


RX band TX band
15.6~18GHz 24.2~27.2GHz





RX band CHIP
S 15.6.18GHz

5cm l

4mm on-chip dipole antenna
for transmitting the RF signal


Figure 5-19. Measurement setup for the duplex operation of TRX at motor side

A 4-mm on-chip dipole antenna separated by 5-cm from the TRX radiates the 16.8-GHz

carrier signal amplitude modulated by 400-Mbps PRBS signal. The radiated ASK modulated









signals are picked up by the RX on the other side via a 4-mm on-chip dipole antenna and by an

external horn antenna placed -7cm above the surface. The received ASK signal in RX is

rectified and fed to CDR. Internally generated TX LO signal at 24GHz from CDR mixed with IF

signal at 1.5GHz generates a carrier signal at 25.5GHz that is amplified and amplitude modulated

by a modulating signal, i.e. 50Mbps PRBS signal, in PA. Finally, the ASK modulated TX signal

is fed to a duplexer and radiated via the on-chip dipole antenna. Figure 5-20 shows the captured

spectrum in both RX band (15.6-18GHz) and one of TX channels (25.35~25.7GHz).

-30

RX band TX band
-40-
^ I 15.6- (motor4)
S-50 18GHz 25.35-
S-60 25.7GHz
0

(* -70-

-80-

-90
15.5 16.5 17.5 18.5 19.5 20.5 21.5 22.5 23.5 24.5 25.5 26.5
Frequency (GHz)


Figure 5-20. Spectrum of both RX and TX band at motor side

5.5 Detection of Multiple Level ASK Signal

For the wireless communication in the hybrid engine controller board, the RX must detect

multi-level ASK signals. To evaluate this, multi-level AM signal is generated using a stand alone

coder and PA [62] combination for the TX of the deadtime controller side. A carrier signal at

16.8-GHz is amplitude modulated by 400-Mbps multi-level signal from the output of coder

generates AM signals with seven different levels. Block diagrams of RX and the PA at TX along

with the measurement setup is shown in Figure 5-21. A single-ended PA output at TX is









connected to differential LNA input in RX through a GS probe landed on the PA output, an RF

cable followed by a variable attenuator emulating propagation loss, a balun converting single to

differential signal and a GSSG probe landed on differential LNA inputs. The antenna and

duplexer are laser-cut off to avoid the mismatch loss. Unlike wireless channels that are random

and difficult to analyze, the wired interconnection in this setup provides stationary and

predictable channel behaviors.

Balun & Active SBD rectifier
GSSG probe LNA balun Amp Amp
^ I BB
out
out

Signal attenuator RX Limiter


Monitoring CDR
point
cable Recovered Clock
PA Attenuator Pre-amp @400MHz
16.8GHz ICarrier
signal
GS probe Multi-level
Control signal Digital
coder

Figure 5-21. Measurement set up for link demonstration and block diagrams of TX and RX

Demodulated multi-level data signal at the baseband output is followed by a limiter in

which each level of incoming data is compared with a threshold voltage set to the middle

between level 6 and level 0. If the incoming level is bigger than the threshold voltage, signal is

railed up to VDD otherwise signal is railed down to GND. Thus, a CDR following the limiter

recovers clocks by processing 2-level input signal. This allows use of conventional CDR

architecture. It is important to mention that 2-level signals converted from multi-level signals









should not change the minimum data bit period of 2.5ns. For example, if a varying amplitude

level such as 012456 repeats itself at a data rate of 400-Mbps, then it becomes 000666 after the

limiter and the repetition of this pattern changes original data rate at 400Mbps to one third of

400Mbps, which results in a failure of CDR locking to 400Mbps input signal.

An initial measurement setup uses 39dB attenuation (GS probe/cable loss of 3dB, 35dB

attenuator, balun/GSSG probe loss of IdB) between the TX and RX. In case of wireless link,

given a pair of antenna loss of 16dB and a duplexer loss of 3dB for TX and RX side, the

remaining 17-dB corresponds to a channel loss in free space. This 17dB is equivalent to -1-cm

separation at 16.8GHz. Shown in Figures 5-22 and 5-23 are a carrier signal at 16.8GHz

amplitude modulated by an alternating pattern between level 0 and level 6 similar to the 2-level

modulating pattern and a 01506250 input pattern, respectively. Each data bit period is 2.5ns.

Measured waveforms of demodulated signals at BB out are also shown. For the 39dB attenuation

setup, the amplitude of the baseband signal is -220mV which should fit the ADC input

requirement of 300mV. However, it is difficult to clearly distinguish each level.

.I '- -. I -.I. '- -,- -_I.. :- -_ -. I. I -: 4 J [ :_ 3 11 .- ,II,- 2- 1 .. -I. : 1 I I


6 0 6 0 6 0 6








(a| ....- .
bb ~ h iW A IF



J ",:* I ])1 | ;...... J 1," ** I .. .... .;, L I 1.,I '" ', I :! **"*


~220mVpp

(b)


Figure 5-22. Waveform of (a) amplitude modulated signal by a 400Mbps pattern 060606 at TX
output, (b) demodulated signal at BB out, and recovered clock at CDR output with
total 39dB attenuation between the PA output and LNA input.









II. I I. I ji: lit 11 iI hi- 1 .



kli
I 0 1 5 0 6r 2 5 0


l Ie._ : .- .
(a) '.i .. ",


l.f:. .t ., i- ^ -,, i^


..... (a)

J ,; I '::: : "... 9 :;: '' | .. .. l ||


S 1- 11 11 i i r .... 1


5 0 6 2


5 0


~220mVp,


JZt.Z tIA 's~W~


Figure 5-23. Waveform of (a) amplitude modulated signal by a 400Mbps pattern 01506250 at
TX output, (b) demodulated signal at BB out, and recovered clock at CDR output
with total 39dB attenuation between the PA output and LNA input.

The 2nd measurement setup uses 20dB attenuation between the TX and RX. As shown in

Figure 5-24, a carrier signal at 16.8GHz amplitude modulated by an alternating pattern between

level 0 and level 6 is captured in time domain. Each data bit period is equal to 2.5ns. The

measured waveform of demodulated signal at BB out and 400MHz recovered clock at CDR

output are also shown. A rising edge of recovered clock samples the data near the center.


,if. =.. '' "
C-






hf :. :

g 4~~a)-^----


Figure 5-24. Waveform of (a) amplitude modulated signal by a 400-Mbps 060606 pattern at TX
output, (b) demodulated signal at BB out, and recovered clock at CDR output with
total 20dB attenuation between the PA output and LNA input.


I '. 1 I IIr l I- *I '*



(b) -500mVpp

, ..la : :: 1':, I '. -l I : I









I i 11 III- .

_0 1 5 0 r 2 5 0


04-
d ... ..2 ,






.(a) '4
J I I I JL-1 111


- "''''iii F-.I~ *.j~"i.


~zti zi 1


Figure 5-25. Waveform of (a) amplitude modulated signal by a 400-Mbps 01506250 pattern at
TX output, (b) demodulated signal at BB out, and recovered clock at CDR output
with total 20dB attenuation between the PA output and LNA input


I l I I"II __ I Ill 11- I l'l" :-1 _" ." I I .. j 1

0 1 5 0 6 2 5 0







(a) ~500m pp
(a) 5ns
I II I ~ hiij
T3 TE .... o ...


\ I. .
-,; I).:..- ^ I ; ".: I .: I, j


Figure 5-26. Waveform of demodulated signal (varying amplitude levels 01506250) at BB
output when the data rate of modulating signal is (a) 200Mbps and (b) 100Mbps with
total 20dB attenuation between the PA output and LNA input.

In Figure 5-25(a), waveform of signal is generated using 400Mbps 01506250 pattern. The

carrier frequency is 16.8GHz. The waveform of demodulated signal at BB output and 400-MHz

recovered clock at CDR output are shown in Figure 5-25(b). The output waveform of

demodulated signal follows the negative envelope of amplitude modulated signal, which is

consistent with the detector design.


0 6 2 5 0


~550mVpp


10ns


I .


0 1 5









In comparison to the waveform of baseband signals from the 1st measurement setup using

39dB attenuation, bigger baseband signal (~500mVpp) results in more recognizable levels.

However, the signal amplitude already exceeds the acceptable ADC input range. Thus, in order

to accommodate large baseband signals, the ADC should be modified.

When the data rate of modulating signal is lower than 400Mbps, demodulated waveform

shows clearer distinction between levels. Figure 5-26 shows the waveforms of demodulated

signal at 200Mbps and 100Mbps. The results suggest that increasing the bandwidth of baseband

amplifier in RX to include up to 5th order harmonics of 200MHz signal improves the signal

quality.

An amplitude modulated signal that includes the combination of all 7 levels is chosen and

the corresponding baseband output is measured. The varying amplitude levels such as

0241353246 cause the malfunction of the comparator of limiter when level-3 is compared. The

level-3 located at the center between level 0 and 6 is exactly identical to the threshold voltage

that is set at the middle between level 0 and 6. Therefore, level 3 cannot be resolved. This failure

results in a long drift of rising edge and disturbing the decision of comparator in the subsequent

bit. This eventually increases the jitter of recovered clock and in the worst case CDR fails to lock

or generate clock at wrong frequency. As a temporary solution, the threshold voltage could be

externally adjusted to create difference between the threshold and level-3. However, this solution

is no longer useful when detected baseband signal level is small. If the overall signal level is

smaller, the amplitude difference between levels become smaller so that the comparator easily

falls into the meta-stable state because setting the threshold voltage slightly above or below the

center makes the threshold to be close to another level. In other words, the limiter cannot operate









without generating unacceptably high jitters of recovered clock or CDR locking to wrong data

rate when incoming signal consists of a series of middle levels.

"_ -- ._V. ", .. ., '-1 ..- I ... I ', .. ..- -' ... j








I 1 I I I' WU ..U






Figure 5-27. Waveform of (a) amplitude modulated signal by a 400-Mbps 0241353246 pattern
at TX output, (b) demodulated signal at BB output, and recovered clock at CDR
output with total 20dB attenuation between the PA output and LNA input.

Figure 5-27 shows the modulated signal with a 400-Mbps 0241353246 pattern, and

demodulated signal at BB output and corresponding recovered clock at 400MHz. Figure 5-28

shows the waveform of demodulated signal at 200Mbps and 100Mbps. When the data rate of

modulating signal is at 100Mbps, demodulated waveform shows clear distinction of levels and

sharper rising/falling time during level transitions. In Figure 5-29, measured RMS jitter of

recovered clock is as high as 47.6ps, which is due to the frequent occurrence of middle levels

such as level 3 and 4 in the input pattern. In this case, even though multi-level signals are

detected at 400Mbps in the baseband output, CDR generates a recovered clock at 399.4MHz

instead of 400MHz because of the malfunction of limiter stage.

In order to avoid the meta-stability problem in the limiter and hence the failure of clock

recovery in the CDR, the middle levels of multi-level signals at TX should be readjusted before

signal transmission. In the PA at deadtime controller, level 3 and 4 should be set as far away as










possible from the middle point between level 6 and level 0 such that, in the RX at motor side, the

comparator of limiter has greater margin between the threshold voltage and level 3 or 4.


IL hh
1 ,, ,ih i h.I > ,ji _Il 1-- ii- II i ." *-,. .,, J 11


S0 2 4 1 3 5 3 2 4 6 0






(a)

S (a) 5ns ~510mp


_- .I -'- ij : _iI [I- 11-


024


1 3


- 1." 'i i


5 3


10ns


2 4 6 0








-550mV,


zwu *w w I 1


Figure 5-28. Waveform of demodulated signal (varying amplitude levels 0241353246) at BB
output when the data rate of modulating signal is (a) 200Mbps and (b) 100Mbps with
total 20dB attenuation between the PA output and LNA input


S i ,I l -hi i i -l _- I

.j RMS jitter-> 43.9ps




*nI


*1 1- hh -II- -1 i 7


RMS jittery 47.6ps









F ... jVi
~~JtZ E III~ ~J


Figure 5-29. Jitter histogram of (a) demodulated signal at BB out and (b) recovered clock at
CDR output for a modulating signal at 400Mbps with total 20dB attenuation between
the PA output and LNA input.

5.6 Conclusions

The single-ended baseband amplifier from the previous implementation is updated to a

differential structure to eliminate the oscillation problem of RX chain. The measurements of









stand alone test structure indicate that under the normal VDD and bias condition, the oscillation

problem has been eliminated. The gain of amplifier is 34dB. The 3dB bandwidth is 670MHz that

satisfies the design target of 600MHz. The amplifier including the bias circuit consumes 3.3mW

of power.

The entire RX chain including an updated baseband amplifier at motor side is

characterized with 2-level amplitude modulated signals. RX chain has IP1dB of-45dBm and

sensitivity of -45dBm for BER of 10-12 and 400Mbps data rate. Full-duplex operations of TRX

with an on-chip antenna are verified by comparing the BER performance of RX chain and RMS

jitters of recovered clock for the cases with TX on and off. The BER degradation due to the TX

on is less than a factor of 10. Especially, when the output signal is near the design target, the

difference is almost negligible. The jitters of recovered clock increase by no more than -Ips

when TX is on. In addition, the full-duplex operation of TRX at motor side is observed by

picking up signals from both TX and RX bands at the same time using an external horn antenna.

This work has demonstrated that full-duplex operation of CMOS transceivers with an on-chip

antenna is possible.

Finally, the feasibility of the detecting multi-level CDMA signal is demonstrated using 7-

level AM signals. Due to the major malfunction in the limiter with middle data levels, i.e. level 3

and 4, the jitter of recovered clock increases to -48ps from ~2ps. In addition, the CDR recovers

the clock at wrong frequency, and in the worst case, loses lock. Some possible solutions to this

problem are suggested.









CHAPTER 6
SUMMARY AND FUTURE WORK

6.1 Summary

A fully integrated CDR based LO generation circuit which provides both 24-GHz LO

signal for a TX and 400-MHz clock for a RX has been demonstrated in UMC 130-nm CMOS

process. A VCO operation 60 times higher than the input data rate at 400Mbps by using a divider

in the feedback loop enables generation of 24-GHz LO signal for TX and integration of an LC-

VCO that utilizes an inductor with reasonable size and Q. Including the divider in the feedback

loop provides additional degree of freedom for reducing the size of loop filter capacitors for

integration. The jitter performance of recovered clock at 400MHz is the lowest among fully

integrated CDR's with the similar data rate (-400Mbps) published in the literature.

A fully integrated FDMA TX chain for motor side in the hybrid engine controller board is

demonstrated using the UMC-130nm CMOS technology. The increased phase noise of LO

generated by a CDR does not degrade the performance of ASK systems using a square laws

detector in the receiver. It should also be possible to use a recovered clock from a CDR as an LO

for a wide band width systems with other low order modulation schemes. The feasibility of

establishing a wireless link using the transmitter within the controller board is also demonstrated.

This indicates that a TX integrated with a RX incorporating a CDR can bypass the problem of

having an external frequency reference. A wireless link demonstration on the board suggests the

target communication range of 15cm should be possible.

An entire RX chain including an updated single to differential baseband amplifier is

characterized. More importantly, full-duplex operations of TRX for motor side with an on-chip

antenna are demonstrated for the first time. Finally, the feasibility of detecting multiple level AM

signal is also demonstrated.









6.2 Future Work

The following efforts that extend the work predicted in this dissertation should be

considered for future efforts.

(a) For successful link demonstration between TX at deadtime controller and RX at motor

side, the RF gain of RX front end at motor side should be increased to improve its sensitivity.

The RX chain should be demonstrated with a 3-bit 800-Msample/s ADC. The middle levels such

as level 3 and 4 of multi-level signals at TX should be readjusted before transmission so as to

avoid the meta-stability problem in the limiter that can cause the failure of clock recovery, and

increase jitter. In the PA at the deadtime controller side, level 3 and 4 should be positioned to be

away from the middle point between level 6 and level 0 so that, in the RX for the motor side, the

comparator of limiter can have large amplitude margins between the threshold voltage and level

3 or 4. A wireless link that supports multiple amplitude modulation should be demonstrated.

(c) Once the RX chain at deadtime controller is verified, a wireless link between TX at

motor side and RX at deadtime controller side should be demonstrated.

(b) In the IF generator, waveforms of IF signals at 800MHz and 1.2GHz violate 50% duty

cycle. For this reason, the increased 2nd harmonics of these IF signals mixed with LO signal

create interfering signals that fall into the desired neighboring channels. Approaches to reduce

the deviation should be incorporated.









APPENDIX A
CDR TEST STRUCTURE

A block diagram of a CDR test structure which consists of a phase detector, a charge

pump, a loop filter, a 5.84-GHz LC VCO, and a divide-by-16 block is shown in Figure A-1. This

CDR test structure outputs both 365-MHz clock and 5.84-GHz LO signal. A loop filter can be

fully integrated with a reasonable capacitance value. Since this CDR test structure was a

prototype design, more than the necessary digital control bits (up to 7bits) are incorporated in the

VCO to increase the likelihood of satisfying the frequency target.

Digital tuning

4- 7
365Mbps
PRBS Phase Charge
Data Detector pump

L < 5.84GHz
P365Mbs Cz LC VCO
Retimed X
Data


SDivider (+ 16)

365MHz L 5.84GHz
Recovered / Recovered
Clock Clock

Figure A-1. Block diagram of CDR test structure.

A.1 Circuit Description of CDR Test Structure

Much of the circuit topology is the same as the CDR circuit mentioned in section 3.2. The

loop bandwidth of 500kHz, charge pump current of 70uA, divide ratio of 16 and VCO gain of

300MHz/V are chosen. For the loop filter, two capacitors Cz, Cp, and one resistor Rz are 324pF,

31pF and 3.lkQ respectively. The biggest capacitor Cz occupies 200mmx210m. The simulated

phase margin of CDR loop is 55.










Buffer VCO VDD Buffer
VDD VDD
M1- ,J M2

L2
L3

BO

OUTP OUTN






M4 M5










Bias



Figure A-2. Schematic of the 5.84GHz LC VCO.

Figure A-2 shows a circuit schematic of the 5.84GHz LC VCO, which consists of an LC-

tank, a PMOS cross coupled pair, a pair of accumulation mode varactors for continuous fine

tuning, a digitally tuned capacitor bank for discrete coarse tuning, an NMOS tail current source,

and a pair of inductively loaded buffers. The capacitor bank supports 7-bit digital tuning to keep

the VCO gain low for reduced phase noise while maintaining an adequate tuning range. To

increase the inductor Q, L1 is drawn as a center tapped spiral inductor [40] using the top two

copper layers shunted together. The total metal thickness is -1.6am. The estimated series









resistance of inductor is 2.3 Q. The metal spacing, width, and number of turns are 2.9am, 4.8am,

and 3, respectively. The inductance for L1 is 0.9nH, and the inductor including a polysilicon

pattern ground shield [41], [42] occupies 100lmx 100am. The simulated Q [43] of inductor is

-15 at 5.84GHz. The capacitor bank consists of seven parallel binary-scaled MOS varactors

whose control voltages are connected to either VDD for Cmin or GND for Cmax. The Cmax/Cmin is

around 3. To implement a divide-by-16, four divide-by-2 circuits are cascaded in series.

A.2 Measurement Results of CDR Test Structure

The CDR has been fabricated in the UMC 130-nm logic CMOS technology with eight

copper layers. Shown in Figure A-3 is a die photograph. The chip area without the bond pads is

0.88mmx0.67mm. This includes the area for a pair of inductor loaded buffers

(0.1 lmmx0. 11mm) for the VCO measurements. The CDR has been measured on a PC board

with the chip directly mounted on the board (chip-on-board) illustrated in Figure A-4. The size of

PCB is 4.8cm by 4.8cm. Direct probe landing is performed to measure the LO at 5.84GHz. The

recovered clock at 385MHz and the retimed data are both measured via SMA connectors. The

measured CDR locking range is from 360.4 to 369Mpbs. Figure A-5 shows the VCO tuning

range and corresponding VCO gain change for digital tuning bit 0000000. The measured VCO

gain is -300MHz/V which is the same as the design target of 300MHz/V around the control

voltage of 0.4V. However, the gain decreases as the control voltage deviates from this point due

to the saturation of varactor capacitance. The supply voltage is 1.2V. The VCO draws 12mA.

The power consumption of CDR excluding that of buffers for driving an external load is

~16mW.






















Figure A-3. Die photograph of 5.84GHz CDR.


Probe
Landing
Direction


4.8cm
Figure A-4. Photograph of CDR testing printed circuit board.


4.8cm


4tHfv jI










5.95 350

5.9 300

250 N
> 5.85 I
r 200
o 5.8 c
150 M


S5.7 50

5.65 0 "
0 0.2 0.4 0.6 0.8 1 1.2
VCO Control Voltage (V)

Figure A-5. Plot of VCO tuning range and gain at digital bits 0000000.

Figure A-6 shows the measured waveform of recovered clock at 365MHz and jitter

histogram in response to a PRBS 231-1 input, respectively. The measured RMS and peak to peak

jitters are 8.9ps (rms) and 76.9ps (p-p), respectively, which are 0.32% and 2.8% of a clock

period. The BER performance has been measured using an Agilent N4903 J-BERT. Since a BER

measurement must be statistically valid, a CDR should be tested long enough to have a certain

confidence level in its BER results [73]. BER testing time must be at least 23 hour 37 min if the

desired BER is 10-13, and desired confidence level is 95% when input data rate is 356-Mbps.

During BER measurements, 3.154x 1013 bits were checked for 24 hours. The measured BER is

less than 10-13.

Figure A-7 shows the spectrum of the recovered clock at 5.84GHz with 365-Mbps PRBS

231-1 input signal when the CDR is locked. Since the CDR loop bandwidth is designed to be 500-

kHz, the noise shaping within the loop bandwidth can be observed in the spectrum. The phase

noise performance at the offset frequency of 60kHz, 1MHz, and 10MHz are measured with RBS









2 -1, 223-1, 231-1 and clock input at 182.5-MHz. Figure A-8 shows the phase noise plot for PRBS

231-1. The in-band phase noise at 60-kHz offset is -74.5dBc/Hz. The phase noise at 1-MHz offset

is -94. ldBc/Hz and the out-of-band phase noise at 10-MHz offset is -113.0dBc/Hz. The

measured CDR characteristics are summarized in Table A-1. This work has demonstrated the LO

generation circuit can be incorporated with a clock and data recovery circuit.




.. .. .. .. .. .. ...... .. .. ... .

-eS

1. ..-







Figure A-6. Plot of recovered clock at 365MHz and jitter histogram for a PRBS 2311.

Mkrl 5.840 000 GHz
Ref 0 dBm Atten 10 dB -11.985 dBm


Samp
Log
10
dB/


Marker-
5.840000000 GHz.
LgAv -11.985 dBm
100 _________
W1 S2
S3 FC
AR
(f):
f>5@k
Swp

Center 5.840 000 GHz Span 5 MHz
#Res BW 30 kHz #UBW 3 kHz Sweep 138 ms (601 pts)

Figure A-7. Spectrum of recovered clock at 5.84GHz for a PRBS 231-1 input signal.


- .-. I.










Carrier Power -10.86 dBm Atten 0.00 dB
Ref -36.00dBc/Hz___
dB/ i -


50 kHz
Marker Trace
1 2
2 2
3 2


Mkr3


Frequency Offset


Type
Spot Freq
Spot Fre9
Spot Freq


X Axis
68 kHz
1 MHz
10 MHz


10.0000 MHz
13.01 dBc/Hz


50 MHz
Value
-74.49 dBc/Hz
-94.06 dBo/Hz
-113.01 dBo/Hz


Figure A-8. Plot of phase noise of recovered clock at 5.84GHz for a PRBS 231-1 input signal.

Table A-1. Summary of measured CDR performance


Technology
Input data rate
CDR lock range
VCO tuning range
5.84-GHz clock
Phase noise
(dBc/Hz)
@ 60-KHz offset
@ 1-MHz offset
@ 10-MHz offset


UMC 130-nm
365-Mbps
360.4-Mbps 369-Mpbs
5.7-GHz ~ 7.12-GHz


PRBS
27-1

-74.6
-100.6
-118.3


PRBS
23_
2 -1

-73.0
-93.3
-113.1


PRBS
311
2 -1

-74.5
-94.1
-113.0


Clock input
@182.5MHz


-84
-102
-121


VCO


-63.4
-104.7
-126.3


365-MHz clock
z ck RMS rising Peak to Peak
jitter (ps)
with PRBS 27-1 6.1 45.8
with PRBS 223-1 8.8 66.7
with PRBS 231-1 8.9 76.9
with clock input 4.3 41.1
@182.5MHzl
BER with
95% confidence Less than 10-13
for PRBS 231-1
Chip size 2
/Chip se 0.88x0.67 mm
(w/o pad)


Power (mW)


CP
0.25


VCO
14.4


......F
I~. I,,.11,


DIV(simulation)
1.2


I I I I 1 1111 1 I I I I I









APPENDIX B
SPECTRUM OF TX OUTPUT WITH AN EXTERNAL IF SIGNAL SOURCE

Figure B-l shows the measurement setup with an external IF frequency source. The

antenna was cut off to eliminate the additional measurement loss and mismatch. The TX power

is measured at the duplexer output. Since the sinusoidal IF signals produced by an external signal

generator is squared with 50% duty cycle after a few inverter stages, when the IF signal is mixed

with LO signal, the contribution of even order harmonics within the TX band is negligible and

hence only odd harmonics are taken into consideration.

Laser
cutting Monitoring point of the differential TX output power



I MIX CDR 400Mbps
C PRBS 231-1
I Duplexer PA PRBS 23-1


ATTEN&MUX IFGEN Ext. Frequency source
ATTEN& MUX & IF GEN
(0.4GHz ~ 3GHz)

Figure B-1. Measurement setup for the transmitter at motor side using an external IF source.

Table B-1. Summary of TX output power level at motor side with an external IF signal source
Motor 1 2 3 4 5 6 7
Channel (GHz) 24.4 24.8 25.2 25.5 26.0 26.4 27.0
Power (dBm) -8.5 -8.9 -5.4 -6.6 -5.1 -4.7 -5.6
Cable & balun loss
6.0 6.4 5.9 6.4 6.3 6.8 7.1
(dB)
Power1 (dBm) -2.5 -2.5 0.5 -0.2 1.2 2.1 1.5
*Powerl: output power after de-embedding measurement cable and balun loss.

With an external IF signal source, the generation of undesired interferers from motor and

their influence on the neighboring channels well agree with the diagram in Figure 4-11. Table B-

1 summarizes the TX output power levels for seven motor channels. In this table, power1

specifies TX output power after de-embedding the cable and balun losses.









A spectrum of TX motor 1 at the duplexer output with antenna cut off is shown Figure B-

2. The peak power level at 24.4GHz is -2.5dBm (-8.53dBm before de-embedding the balun and

cable losses). Since the 3rd and 5th order harmonics of 400MHz signals fall into motor 3

(25.2GHz) and motor 5 (26GHz) channels, harmonic control is once again important for

reducing the interference. The 3rd and 5th harmonics from 400MHz are --20dBm at 25.2GHz

and --32dBm at 26GHz, respectively. Proper attenuator settings can further minimize the

harmonic contribution, though this will reduce the desired output power level. Figure B-3 shows

a zoomed in spectrum of the TX motor 1.


Figure B-2. Spectrum of TX motor 1 driven with an external IF signal source.


Figure B-3. Zoomed-in spectrum of TX motor 1 driven with an external IF signal source.












Figure B-4 shows a spectrum of motor 7 at the duplexer output. The peak power level at


27GHz is 1.5dBm (-5.6dBm before de-embedding the balun and cable losses). The 2nd order


harmonic from 3GHz mixed with 24GHz is -3 IdBm at 30GHz, which is outside of the TX


bands. Figure B-5 shows a zoomed in spectrum of the TX motor 7.

Mkrl 27.00 GHz
Ref 0 dBm Atten 10 dB ..-. -5.60 dBm
Norm ; (30GHz) 2nd
S / harmonic of
dB/ 3.0 GHz

.............. '.,


LA -5 .6 d*m









Res BW 3 MHz VUB 3 MH Sweep 25 ms (M81 pts)


Figure B-4. Spectrum of TX motor 7 driven with an external IF signal source.

Mkrl 27.908 0 G6H
Ref 0 dBm Atten 10 dB -7.56 dBm
Norm ,

dB/

.....................
Marker
27.000000000 GHz
LH: -7.56 dBm
.......................
$3O






Center 27.8800 GHz Span 10 MHz
,Res BW 10 kHz VBI 10 kHz -Sweep 4 s (601 ts)


Figure B-5. Zoomed-in spectrum of TX motor 7 driven with an external IF signal source.









LIST OF REFERENCES


[1] D. Hermance, and S. Sasaki, "Hybrid Electric Vehicles Take to The Streets," IEEE
Spectrum, Vol. 35, Issue 11, pp. 48-52, Nov. 1998.

[2] Floyd A Wyczalek, "Market Mature 1998 Hybrid Electric Vehicles," IEEE Aerospace
and Electronic Systems Magazine, Vol. 14, Issue 3, pp. 41-44, March 1999.

[3] A kira Kawahashi, "A New-Generation Hybrid Electric Vehicle and Its Supporting
Power Semiconductor Devices," IEEE Power Semiconductor Devices and ICs Symp.
Dig. Tech. Papers, pp. 23-29, 24-27 May 2004.

[4] T. P. Bohn, R.D. Lorenz, and E. R. Olson, "Measurement of In-Situ Currents in a Hybrid
Electric Vehicle Integrated Power Module Using Giant Magnetoresistive Sensors," IEEE
Power Electronics in Transportation, pp. 55-59, 2004.

[5] N. Kanekawa, Y. Kojima, S. Yukutake, M. Nemoto, T. Iwasaki, K. Takami, Y.
Tekeuchi, A. Yano, and Y. Shima, "An analog front-end LSI with on-chip isolator for
V.90 56 kbps modems," IEEE CICC Dig. Tech. Papers, pp. 327-330, May 2000.

[6] Y. Kojima, M. Nemoto, S. Yukutake, T. Iwasaki, M. Amishiro, N. Kanekawa, A.
Watanabe, Y. Takeuchi, and N. Akiyama, "2.3 kVac 100 MHz multi-channel monolithic
isolator IC," The 12th Int. Symp. Power Semiconductor Devices andlCs, 2000. Proc., pp.
309-312, May 2000.

[7] N. Akiyama, Y. Kojima, M. Nemoto, S. Yukutake, T. Iwasaki, M. Amishiro, N.
Kanekawa, A. Watanabe, and Y. Takeuchi, "A hi-voltage monolithic isolator for a
communication network interface," IEEE Trans. Electron Devices, Volume 49, Issue 5,
pp. 895-901, May 2002.

[8] Hsinta Wu, Ph.D. Dissertation "Transmitter for wireless inter-chip data communications"
University of Florida, Gainesville, FL, 2009.

[9] K. Kim, H. Yoon, and K. K. O, "On-chip wireless interconnection with integrated
antennas," Tech. Digest oflEDM, pp. 485-488, San Francisco, 2000.

[10] K. K. O, K. Kim, B. Floyd, J. Mehta, H. Yoon, C.-M. Hung, D. Bravo, T. Dickson, X.
Guo, R. Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, D.-J. Yang, J. Bohorquez, L.
Gao, A. Sugavanam, J.-J. Lin, J. Chen, F. Martin, and J. Brewer, "Wireless
communication using integrated antennas," in Proc. Int. Interconnect Technol. Conf., San
Francisco, CA, Jun. 2003, pp. 111-113.

[11] Y. Su, J.-J. Lin, and K. K. O, "A 20-GHz CMOS RF down-converter with an on-chip
antenna," in 2005 IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp.
270-271.









[12] C. Cao, Y. Ding, X. Yang, J.-J. Lin, A. K. Verma, J. Lin, F. Martin, and K. K. O, "A 24-
GHz transmitter with an on-chip antenna in 130-nm CMOS," in Symp. VLSI Circuits Dig.
Tech. Papers, Jun. 2006, pp. 184-185.

[13] T. Rappaport, "Wireless Communications, Principles and Practice," Second edition,
Prentice Hall, 2002.

[14] Swaminathan Sankaran, Ph.D Dissertation "Recievers Using Schottky Barrier Diodes in
CMOS," University of Florida, Gainesville, FL, 2008.

[15] Jau-Jr Lin, Ph.D Dissertation "On-Chip Antennas for Short-Range Wireless
Communications," University of Florida, Gainesville, FL, 2007.

[16] U. L. Rohde, J. Whitaker and T. T. N. Bucher, Communication Receivers: Principles and
Design, NY: McGraw Hill, 1996.

[17] C. Hogge, "A self-correcting clock recovery circuit," J. Lightwave Technol., vol. LT-3,
pp. 1312-1314, Dec. 1985.

[18] B. Sklar, "Digital Communications, Fundamentals and Applications," Prentice Hall,
1987.

[19] B Razavi, Design of Integrated Circuits for Optical Communications, McGRAW-HILL,
2003.

[20] J. Redd, C.Lyon, "Spectral Content of NRZ test patterns", Maxim Integrated Circuits,
Sep. 2004.

[21] B. Razavi, "Challenges in the Design of High-Speed Clock and Data Recovery Circuits,"
IEEE Communication Magazine, volume 40, pp. 94-101, August 2002.

[22] D. Mijuskovic, M. Bayer, T. Chomicz, N. Garg, F. James, P. McEntarfer, J. Porter, "Cell-
based fully integrated CMOS frequency synthesizer," IEEE Journal of Solid-Stage
Circuits, volume 29, Issue 3, pp. 271-279, March 1994.

[23] F. M. Gardner, "Phaselock Techniques," third edition, Wiley, Jul. 2005.

[24] M. H. Perrott, "High Speed Communication Circuits and Systems -Lecture 15, Integer-N
Frequency Synthesizers," MIT course, Spring 2002.

[25] Michael H. Perrott, "PLL design using the PLL design assistant program", pp.31-32, Jul.
2008, website: www. cppsim.com

[26] C. M. Hung, Ph. D Dissertation "Investigation of a multi-GHz single-chip CMOS PLL
frequency synthesizer for wireless applications" University of Florida, Gainesville, FL,
2000.









[27] J. J. Young, "Jitter Considerations in High Bit Rate Digital Video Signals," IEEE
Transactions on Broadcasting, vol. 40, no. 2, Jun. 1994.

[28] L. M. DeVito, "Unusual Clcok Recovery Architecture Ameliorates SONET Jitter
Tradeoff," presented at Univ of Cal., Berkeley, Feb. 2003.

[29] D. Dalton, K. Chai, M. Ferriss, D. Hitchox, P. Murray, S. Selvanayagam, P. Shepherd, L.
Devito, "A 12.5 Mb/s to 2.7 Gb/s continuous-rate CDR with automatic frequency
acquisition and data-rate readback," IEEEJ. Solid-State Circuits, vol. 40, pp. 2713, Dec.
2005.

[30] R-J Yang, K-H Chao, S-C Hwu, C-K Liang, S-I Liu, "A 155.52 Mbps-3.125 Gbps
Continuous-Rate Clock and Data Recovery Circuit," IEEE J. Solid-Stage Circuits, vol.
41, no. 6, pp. 1380-1390, June 2006.

[31] R-J Yang, K-H Chao, S-I Liu, "A 200-Mbps-2-Gbps Continuous-Rate Clock-and-Data-
Recovery Circuit," IEEE Trans. Circuits and systems I, vol. 53, Issue. 4, pp. 842-847,
Apr. 2006.

[32] P. Larsson, "A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability,",
IEEEJ. Solid-State Circuits, vol. 34, pp. 1951-1960, Dec. 1999.

[33] J. Scheytt, G. Hanke and U. Langmann "A 0.155, 0.622 and 2.488 Gb/s automatic bit-
rate selecting clock and data recovery IC for bit-rate transparent SDH systems," IEEE J
Solid-State Circuits, vol. 34, pp. 1935-1943, Dec. 1999.

[34] L. DeVito, et al., "A 52 MHz and 155 MHz clock recovery PLL," in IEEE Int. Solid-
State Circuits Conf. (ISSCC) Dig. Tech. Papers San Francisco, CA, Feb. 1991, pp. 142-
143.

[35] Craninckx and M. Steyaert, "A fully integrated CMOS DCS-1800 frequency
synthesizer," IEEEJ. Solid-State Circuits, vol. 33, pp. 2054-2065, Dec. 1998.

[36] C. M. Hung, Y. C. Ho, I. C. Wu, and K. K. O, "High-Q capacitors implemented in a
CMOS process for low-power wireless applications," IEEE Trans. Microw. Theory
Tech., vol. 46, no. 5, pp. 505-511, May 1998.

[37] Floyd M. Gardner, "Charge pump phase locked loops," IEEE Transactions on
Communications Electronics, pp. 1849-1858, Nov. 1980.

[38] J. Kim, J. K. Kim, B. J. Lee, N. Kim, D. K. Jeong, W. Kim, "A 20-GHz Phase-Locked
Loop for 40-Gb/s Serializing Transmitter in 0.13-[tm CMOS," IEEE Journal of Solid-
State Circuits, volume 41, pp899-908, April 2006.

[39] T. Soorapanth, C. P. Yue, D. K. Shaeffer, T. I. Lee, T.I, and S. S. Wong, "Analysis and
optimization of accumulation-mode varactor for RF ICs," Symp. VLSI Circuits Dig. Tech.
Papers, pp 32 33, June 1998.









[40] J.-O. Plouchart, H. Ainspan, M. Soyuer, and A. Ruehli, "A fully monolithic SiGe
differential VCO for 5GHz wireless applications," in Proc. IEEE RFIC Symp., Boston,
MA, June 2000, pp. 57-60.

[41] C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-
based RFIC's," IEEEJ. Solid-State Circuits, vol. 33, no. 6, pp. 743-752, Jun. 1998.

[42] S.-M. Yim and K. K. O, "The effects of a ground shield on the characteristics and
performance of spiral inductors," IEEEJ. Solid-State Circuits, vol. 37, no.2, pp. 237-244,
Feb. 2002.

[43] K. K. O, "Estimation methods for quality factors of inductors fabricated in silicon
integrated circuit process technologies," IEEEJ. Solid-Stage Circuits, vol. 37, no. 8, pp.
1249-1252, Aug. 1998.

[44] Changhua Cao, Ph.D. Dissertation "A 24-GHz Fully-Integrated CMOS Transmitter with
On-chip Antenna" University of Florida, Gainesville, FL, 2006.

[45] E. Hegazi, H. Sjoland, A. Abidi, "A filtering technique to lower oscillator phase noise,"
IEEE ISSCC Digest of Technical Papers, pp. 364-365, Feb. 2001.

[46] B. A. Floyd and K. K. O, "SOI and bulk CMOS frequency divider operating above
15GHz", IEE Electronics Letter, vol. 37, n. 10, pp. 617-618, May 2001.

[47] D.-J. Yang, and K. K. O, "A 14-GHz 256/257 Dual-Modulus Prescaler With Secndary
Feedback and Its Application to a Monolithic CMOS 10.4-GHz Phase-Locked Loop,"
IEEE Trans. Microwave Theory Tech., pp. 461-468, Feb. 2004.

[48] C. Cao and K. K. O, "A power efficient 26GHz 32:1 static frequency divider in 130-nm
bulk CMOS," IEEEMicrow. Wireless Compon. Lett., vol. 15, pp. 721, Nov. 2005.

[49] Y. Yamauchi, O. Nakajima, K. Nagata and M. Hirayama, "A 15-GHz Monolithic Two-
Modulus Prescaler," IEEEJ. Solid-Stage Circuits, vol. 26, no. 8, pp. 1632-1636, Nov.
1991.

[50] K. Ware, H.-S. Lee, C. G. Sodini, "A 200-MHz CMOS phase-locked loop with dual
phase detectors," IEEE Journal of Solid-State Circuits, vol. 24, no. 6, pp. 1560-1568,
Dec. 1989.

[51] J. D. H. Alexander, "Clock Recovery from Random Binary Data," Elect. Lett., vol. 11,
pp. 541-42, Oct. 1975.

[52] J M. Rabaey, A Chandrakasan, and B. Nikolic, "Digital Integrated Circuits -A design
perspective", second edition, Printice Hall, 2003.

[53] C. Lam, B. Razavi, "A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-atm CMOS
technology," IEEE Journal of Solid-State Circuits, Volume 35, Issue 5, pp. 788-794
May 2000.









[54] C. M. Hung, K. K. 0, "A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop,"
IEEE Journal of Solid-State Circuits, Vol. 37, no. 4, pp. 521-525. Apr. 2002.

[55] H. K. Lee, J. T. Ahn, M.-Y. Jeon, K. H. Kim, D. S. Lim, and C.-H. Lee, "All-optical
clock recovery from NRZ data of 10 Gb/s," IEEE Photon. Technol. Lett., vol. 11, pp.
730-732, June 1999.

[56] T. Lee and J. Bulzacchelli, "A 155-MHz clock recovery delay- and phase-locked loop,"
IEEEJ. Solid-State Circuits, vol. 27, no. 12, pp. 1736-1746, Dec. 1992.

[57] Y. Ding and K. K. O, "A 21-GHz 8-modulus prescaler and a 20-GHz phase-locked loop
fabricated in 130-nm CMOS," IEEEJ. Solid-State Circuits, vol. 42, no. 6, pp. 1240-1249,
Jun. 2007.

[58] D. Banerjee, PLL Performance, Simulation and Design, 4th edition. 2006.

[59] B. P. Lathi, "Modern Digital and Analog Communication Systems," third edition,
Oxford, 1998.

[60] A. V. Oppenheim, A. S. Willsky, S. H. Nawab, "Signal & Systems," second edition,
Prentice Hall, Aug. 1996.

[61] S. Sankaran, K. Oh, H. Wu, and K. K. O, "Wireless Interconnection within a Hybrid
Engine Controller Board" Proc. CICC, pp.149-152, Sep. 2008.

[62] Hsin-Ta Wu, Ruonan Han, Lerdsitsomboon W, Changhua Cao, and Kenneth K. O,
"Multi-Level Amplitude Modulation of a 16.8-GHz Class-E Power Amplifier with
Negative Resistance Enhanced Power Gain for 400-Mbps Data Transmission," IEEE J.
Solid-State Circuits, vol. 45, no. 5, pp. 1072-1079, May. 2010.

[63] N. H. E. Weste, D. Harris, "CMOS VLSI Design, A Circuit and Systems Perspective,"
third edition, Addison Wesley, May 2004.

[64] S. Brown and Z. Vranesic, "Fundamentals of Digital Logic with VHDL Design," second
edition, McGrawHill, Jul. 2004.

[65] S. H. Unger, "Double-edge-triggered flip-flops," IEEE Trans. Computers, vol. C-30, no.
6, pp. 447-451, June 1981.

[66] H.-D. Wohlmuth, and D. Kehrer, "A 15 GHz 256/257 dual-modulus prescaler in 120 nm
CMOS," European Solid-State Circuits Conference, pp. 77 80, Sep. 2003.

[67] N. 0. Sokal, and A. D. Sokal, "Class E-A New Class of High Efficiency Tuned Single-
Ended Switching Power Amplifier," IEEEJ. Solid-State Circuits, vol. 10, no. 3, pp. 168-
176, Jun. 1975.









[68] C. Cao, H. Xu, Y. Su, and K. K. O, "An 18-GHz, 10.9-dBm Fully-Integrated Power
Amplifier with 23.5% PAE in 130-nm CMOS," Eur. Solid-State Circuit Conf. Dig. Tech.
Papers, pp. 137-140, Sep. 2005.

[69] H. Johnson, M. Graham, "High-Speed Digital Design: A Handbook of Black Magic,"
Prentice Hall, 1993.

[70] B. A. Floyd, K. Kim, and K. K. O, "Wireless interconnection in a CMOS IC with
integrated antennas," in 2000 IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb.
2000, pp. 328-329.

[71] B. A. Floyd, C.-M. Hung, and K. K. O, "15-GHz Wireless interconnect implemented in a
0.18-[tm CMOS technology using integrated transmitters, receivers, and antennas," IEEE
J. Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002.

[72] F. Touati and M. Pons, "On-chip integration of dipole antenna and VCO using standard
BiCMOS technology for 10 GHz applications," in Proc. 29th Eur. Solid-State Circuits
Conf. (ESSCIRC 2004), Estoril, Portugal, Oct. 2003, pp. 493-496.

[73] Agilent Technologies, "Agilent J-Bert N4903 High-Performance Serial Bert User
Guide", Jun. 2007.









BIOGRAPHICAL SKETCH

Kyujin Oh was born in Busan, South Korea, in 1974. He received the B.S. degree in

electrical engineering from Yonsei University, Seoul, South Korea in 2001 and M.S. degree in

electrical engineering from University of Southern California, Los Angeles in 2004. Currently,

he is a Ph.D. candidate in the Department of Electrical and Computer Engineering at the

University of Florida, Gainesville and has been with the Silicon Microwave Integrated Circuits

and Systems (SIMICS) research group since 2006.

During the summer of 2007, he interned at Samsung Electronics where he was involved in

VCO and divider design of a phase locked loop (PLL) for 4G wireless communication (LTE).

His current research interests are in analysis and design of RF circuits, wireless transceiver, and

high-speed analog circuits in CMOS.





PAGE 1

TECHNIQUES FOR CRYSTALLESS OPERATION OF WIRELESS INTER-CHIP DATA COMMUNICATION SYSTEMS By KYUJIN OH A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2010 1

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2010 Kyujin Oh 2

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To my family 3

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ACKNOWLEDGMENTS I would like to begin by thanking my advisor, Professor Kenneth K. O, whose constant encouragement and patient guidance provided a clear path for my research. I would also like to thank Dr. Gijs Bosman, Dr. William Eisenstadt and Dr. Nam Ho Kim for helpful suggestions and serving on the Ph.D. committee. I would like to thank the former SiMICS members Yanping Ding, Eunyoung Seok, Kwangchun Jung, Chikuang Yu, Haifeng Xu, Jau-Jr Lin, Changhua Cao, Yu Su and Shashank Nallani Kiron. I have been quite fortunate to have worked with my colleagues Swaminathan Sankaran, Hsinta Wu, Dongha Shim, Tie Sun, Ruonan Han, Wuttichai Lerdsitomboon, Chuying Mao, Dr. Choongyul cha, Kyungsun Seol and Ning Zhang. The discussions with them and their advice were immensely helpful for completing this work. Much appreciation goes to TOYOTA Motor Corporation for funding this work. My special thanks go to Eric Schwartz at Agilent Technologies for help in BER measurements and Al Ogden for bonding and dicing chips. I would also like to acknowledge Dr. Hyeopgoo Yeo and Dr. Jonksick Ahn for helpful technical discussions. I am deeply grateful to my family for their unconditional love, guidance, encouragement, and support which are the source of my strength. I dedicate this work to my family. 4

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TABLE OF CONTENTS page ACKNOWLEDGMENTS ...............................................................................................................4 LIST OF TABLES ...........................................................................................................................7 LIST OF FIGURES .........................................................................................................................8 ABSTRACT ...................................................................................................................................14 CHAPTER 1 WIRELESS INTERCONNECTS IN ENGINE CONTROLLER BOARDS.........................16 1.1 Introduction.......................................................................................................................16 1.2 System Overview..............................................................................................................17 1.3 Organization of Dissertation.............................................................................................22 2 OVERVIEW OF CLOCK AND DATA RECOVERY CIRCUIT.........................................24 2.1 Introduction.......................................................................................................................24 2.2 Non Return to Zero (NRZ) Test Pattern...........................................................................25 2.3 Clock and Data Recovery (CDR) Overview....................................................................27 2.3.1 Linear Phase Detector for Random Data................................................................27 2.3.2 Linear Model of CDR.............................................................................................31 2.3.3 Choosing a Bandwidth of CDR..............................................................................35 2.4 Summary...........................................................................................................................37 3 CLOCK AND DATA RECOVERY CIRCUIT AS AN LO GENERATOR.........................38 3.1 Introduction.......................................................................................................................38 3.2 New CDR Structure..........................................................................................................38 3.2.1 Loop Filter..............................................................................................................40 3.2.2 Voltage Controlled Oscillator (VCO)....................................................................41 3.2.3 Divider Chain (Divide-by-60)................................................................................42 3.2.4 Phase Detector........................................................................................................43 3.2.5 Charge Pump (CP)..................................................................................................45 3.3 Simulation Results............................................................................................................46 3.4 Measurement Results........................................................................................................49 3.5 The Influence of Phase Noise of CDR on ASK Modulation............................................56 3.6 Conclusion........................................................................................................................59 4 FDMA TRANSMITTER AT MOTOR SIDE........................................................................61 4.1 Introduction.......................................................................................................................61 4.2 Evolution of Transmitter at Motor Side............................................................................61 5

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4.3 Circuit Topology of Transmitter at Motor Side................................................................63 4.3.1 IF Generator............................................................................................................64 4.3.2 8-to-1 Multiplexer and Attenuator..........................................................................68 4.3.3 Three Stage LO Buffer...........................................................................................69 4.3.4 Up-conversion Mixer..............................................................................................70 4.3.5 Power Amplifier.....................................................................................................72 4.4 Measurement Results of IF Generator..............................................................................74 4.5 Measurement Results of TX Chain...................................................................................78 4.5.1 Spectrum of TX Output and Harmonic Control.....................................................78 4.5.2 ASK Modulation (Carrier at 26GHz Amplitude-modulated by 25MHz Modulating Square Signal)..........................................................................................84 4.5.3 ASK Modulation (Carrier at 26GHz Amplitude-modulated by 50Mbps PRBS 2 31 -1 Modulating Signal).............................................................................................87 4.5.4 Wireless Link Test at the Motor TX.......................................................................89 4.6 Conclusion........................................................................................................................91 5 DUPLEX OPERATION AND LINK DEMONSTRATION.................................................92 5.1 Introduction.......................................................................................................................92 5.2 A Differential Baseband Amplifier..................................................................................94 5.2.1 Circuit Description.................................................................................................94 5.2.2 Measurement Results..............................................................................................97 5.3 Measurement Results of Full RX Chain for Motor Section...........................................100 5.4 Duplex Operation of TRX at Motor Side.......................................................................106 5.4.1 Characterization of RX with TX On and Off.......................................................107 5.4.2 Characterization of RX with TX On and Off using the Chip without Laser Cut.112 5.4.3 Wireless Demonstration of Duplex Operation at Motor Side..............................114 5.5 Detection of Multiple Level ASK Signal.......................................................................115 5.6 Conclusions.....................................................................................................................122 6 SUMMARY AND FUTURE WORK..................................................................................124 6.1 Summary.........................................................................................................................124 6.2 Future Work....................................................................................................................125 APPENDIX A CDR TEST STRUCTURE...................................................................................................126 B SPECTRUM OF TX OUTPUT WITH AN EXTERNAL IF SIGNAL SOURCE...............133 LIST OF REFERENCES.............................................................................................................136 BIOGRAPHICAL SKETCH.......................................................................................................142 6

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LIST OF TABLES Table page 1-1 Frequency plans for transmitter and receiver at the motor side.........................................19 1-2 Frequency plan for transmitter and receiver at deadtime controller..................................20 1-3 Link margin analysis for FDMA........................................................................................22 1-4 Link margin analysis for CDMA.......................................................................................22 2-1 Summary of jitter specification..........................................................................................36 3-1 Summary of measured CDR performance.........................................................................54 3-2 Comparison of jitter performance......................................................................................55 4-1 IF signal generation............................................................................................................65 4-2 Simulated power consumption in TX at motor node.........................................................73 4-3 Simulated and measured duty cycle of IF signals..............................................................77 4-4 Summary of TX output power level at motor side............................................................79 4-5 Power consumption of transmitter at motor side...............................................................91 5-1 Summary of measurement results of baseband amplifier................................................100 5-2 Summary of RX chain measurement results....................................................................106 5-3 Summary of measured jitter performance........................................................................110 5-4 Summary of measured BER performance of RX chain at motor side.............................111 5-5 Summary of measured RMS jitter and BER performance...............................................113 A-1 Summary of measured CDR performance.......................................................................132 B-1 Summary of TX output power level at motor side with an external IF signal source.....133 7

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LIST OF FIGURES Figure page 1-1 Engine controller board for a HEV. D1 and D2 communicate with M1~M6 and M7~M12, respectively (Courtesy of TOYOTA)...............................................................18 1-2 Signaling scheme for the up (FDMA) and down (CDMA) links......................................19 1-3 Frequency bands and data rate in deadtime controller and motors....................................19 1-4 Frequency plans for the transceiver at the motor side.......................................................20 1-5 Frequency plan for transceiver at deadtime controller side...............................................20 2-1 PRBS signal (a) waveform in time domain, (b) autocorrelation, and (c) power spectral density in frequency domain [20].........................................................................26 2-2 Block diagram of CDR......................................................................................................27 2-3 A linear phase detector (a) block diagram, and (b) waveform under the locked condition............................................................................................................................28 2-4 Waveform of phase detector for (a) early clock and (b) late clock...................................28 2-5 Input-output characteristic of linear phase detector...........................................................30 2-6 Input-output characteristic of tri-state phase and frequency detector (PFD).....................30 2-7 Linear model of PLL based CDR circuit...........................................................................31 2-8 The 2 nd order passive lead-lag filter (a) schematic and (b) transfer function....................32 2-9 Bode plot of the open loop gain for a CDR circuit............................................................34 2-10 Linear model of second order CDR and its jitter plot........................................................36 3-1 Block diagram of conventional CDR.................................................................................39 3-2 Block diagram of new CDR...............................................................................................39 3-3 Schematic of the 24GHz LC VCO.....................................................................................42 3-4 Block diagram of divider chain (divide-by-60).................................................................43 3-5 Block diagram of divide-by-2 and implementation of latch circuit...................................43 3-6 Block diagram of (a) phase detector and (b) implementation of each DFF using DCVSL logic circuits.........................................................................................................44 8

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3-7 Schematic of charge pump.................................................................................................45 3-8 Plot of current mismatch between up and down current in the charge pump....................46 3-9 Simulated VCO tuning range plot with 3-bit digital control for coarse tuning.................47 3-10 Simulated CDR settling behavior at the VCO control voltage..........................................48 3-11 Input data signal versus recovered clock under the locked condition...............................48 3-12 Die photograph of 24GHz CDR........................................................................................49 3-13 Measured tuning range plot with 3 bits digital control for coarse tuning..........................50 3-14 VCO tuning range and gain at digital bits 111..................................................................50 3-15 Jitter histogram of the recovered clock at 400MHz for a PRBS 2 31 -1 input.....................51 3-16 Spectrum of the recovered clock at 24GHz for a PRBS 2 31 -1 input..................................52 3-17 Spectrum of 400Mbps PRBS 2 n -1 signal (top), PNRZ signal after edge detection in the phase detector (middle), and recovered clock at 24GHz (bottom)..............................52 3-18 Phase noise plot of the recovered clock at 24GHz for a PRBS 2 7 -1 input........................53 3-19 Phase noise plot of the recovered clock at 24GHz for a PRBS 2 31 -1 input.......................53 3-20 Plots of (a) amplitude and (b) phase spectra for x(t) and corresponding waveform (c) in time domain...................................................................................................................58 4-1 Block diagram of original transceiver at a motor section..................................................62 4-2 Block diagram of transmitter at motor side.......................................................................62 4-3 Block diagram of the interface between a CDR and a mixer............................................63 4-4 Block diagram of IF generator...........................................................................................64 4-5 Block diagram and waveform of (a) divide-by-2.5 and (b) divide-by-1.5........................66 4-6 Block diagram of (a) DETFF and schematic of (b) MUX, (c) LATCH, and (d) AND plus LATCH.......................................................................................................................67 4-7 Block diagram of 8-to-1 MUX and attenuator...................................................................68 4-8 Schematic of capacitor bank..............................................................................................68 4-9 Schematic of three stage LO buffer...................................................................................70 9

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4-10 Schematic of up-conversion mixer....................................................................................71 4-11 Generation of undesired interferers by mixing harmonics of IF signal with LO signal....72 4-12 Schematic of power amplifier............................................................................................73 4-13 Die photograph and testing PC board of IF generator.......................................................74 4-14 Spectrum and waveform of IF signals at (a) 400MHz, (b) 800MHz, (c) 1.2GHz, (d) 1.5GHz, (e) 2.0GHz, (f) 2.4GHz, and (g) 3.0GHz............................................................75 4-15 Generation of undesired interferers due to the mixing of 2nd, 3rd, and 5th order harmonics of IF signals with LO signal.............................................................................77 4-16 Die photograph of crystalless transceiver at motor section...............................................78 4-17 Block diagram of transmitter at motor side.......................................................................79 4-18 Spectrum of TX motor 1 with attenuator...........................................................................80 4-19 Spectrum of TX motor 1 without attenuator......................................................................80 4-20 Zoomed-in spectrum of TX motor 1..................................................................................81 4-21 Spectrum of TX motor 2 with attenuator...........................................................................82 4-22 Spectrum of TX motor 2 without an attenuator.................................................................82 4-23 Spectrum of TX motor 3 with attenuator...........................................................................83 4-24 Spectrum of TX motor 3 without attenuator......................................................................84 4-25 The impact of interferer signals on desired channels with attenuator on..........................84 4-26 Waveform and spectrum of (a) un-modulated carrier and (b) ASK modulated carrier.....85 4-27 Waveform and spectrum of square wave with 50% duty cycle.........................................85 4-28 Spectrum of TX output at motor 5 (26GHz) before and after ASK modulation with 25-MHz square signal........................................................................................................86 4-29 Waveform of TX output at motor 5 after ASK modulation with 25-MHz square signal..................................................................................................................................87 4-30 Spectrum of TX output at motor 5 before and after the ASK modulation with 50Mbps PRBS 2 31 -1data signal.........................................................................................88 4-31 Eye diagram output at motor 5 after ASK modulation with a 50Mbps PRBS 2 31 -1 data signal..........................................................................................................................88 10

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4-32 Setup of wireless link demonstration at TX motor side.....................................................89 4-33 Spectrum of TX output (a) before modulation (b) after ASK modulation with 25-MHz square clock signal. (c) Waveform of TX output after ASK modulation with 25MHz square clock signal. (d) Spectrum of received 26-GHz carrier signal amplitude modulated by 25-MHz square signal (with metallic cover)..............................90 5-1 Block diagram of receiver chain at motor section.............................................................92 5-2 Positive feed back path due to parasitic inductors in multistage single-ended amplifiers...........................................................................................................................93 5-3 Schematic of baseband amplifier.......................................................................................95 5-4 Schematic of the wide-swing cascode current mirror........................................................96 5-5 Die photograph and baseband amplifier PC board for testing...........................................97 5-6 Waveform of a single-ended square wave input at 200MHz. Differential outputs when input voltage level is (a) 6.8mV pp (b) 20mV pp and (c) 30mV pp ..............................99 5-7 Measured 3-dB bandwidth of baseband amplifier in frequency domain.........................100 5-8 Block diagram of RX chain at motor section and measurement setup............................101 5-9 RX output power as function of input single sideband power and input carrier power (AM modulation index of 100%).....................................................................................102 5-10 Measured BER versus input power..................................................................................103 5-11 Plots of (a) Amplitude modulated 16.8-GHz carrier with 200-MHz square wave at LNA input. (b) Spectrum of demodulated 200MHz signal at BB output. (c) Waveforms of demodulated 200MHz signal at BB output and 400MHz recovered clock at CDR output. (d) Jitter histogram of recovered clock at 400MHz......................104 5-12 Plots of (a) Amplitude modulated 16.8-GHz carrier with 400-Mbps PRBS 2 31 -1 at LNA input. (b) Spectrum of demodulated 400Mbps signal at BB output. (c) Waveforms of demodulated 400Mbps signal at BB output and 400MHz recovered clock at CDR output. (d) Jitter histogram of recovered clock at 400MHz......................105 5-13 Block diagram of TRX at motor section and measurement setup...................................107 5-14 Spectrum of demodulated baseband signal in RX when (a) TX is off, (b) TX is on and a modulating signal for TX is a 50-MHz clock, and (c) TX is on and a modulating signal for TX is a 50-Mbps PRBS 2 7 -1 signal. The plots on the right side are the zoomed-in plots....................................................................................................108 11

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5-15 RMS jitter plots of recovered clock with and without turning on TX for (a) 200-MHz square clock, (b) 400-Mbps PRBS 2 7 -1, (c) 400-Mbps PRBS 2 23 -1, and (d) 400Mbps PRBS 2 31 -1 modulating signal for RF input....................................................................110 5-16 BER plots (a) 400-Mbps PRBS 2 7 -1 modulation signal for RF input with TX on and off, (b) 400-Mbps PRBS 2 31 -1 with TX on and off, (c) TX on with 400-Mbps PRBS 2 7 -1 and 2 31 -1 modulation signal, and (d) TX off with 400-Mbps PRBS 2 7 -1 and 2 31 -1..................................................................................................................................111 5-17 RMS jitter plots at RF input power of -47dBm with TX on and off for (a) 200MHz square clock, (b) 400Mbps PRBS 2 7 -1, (c) 400Mbps PRBS 2 23 -1, and (d) 400Mbps PRBS 2 31 -1. The connection between the LNA and duplexer is not laser cut.................113 5-18 BER plots at RF input power of -47dBm for (a) 400Mbps PRBS 2 7 -1 with TX on and off, and (b) 400Mbps PRBS 2 31 -1 with TX on and off. The connection between LNA and duplexer is not laser cut...................................................................................114 5-19 Measurement setup for the duplex operation of TRX at motor side................................114 5-20 Spectrum of both RX and TX band at motor side...........................................................115 5-21 Measurement set up for link demonstration and block diagrams of TX and RX............116 5-22 Waveform of (a) amplitude modulated signal by a 400Mbps pattern 060606 at TX output, (b) demodulated signal at BB out, and recovered clock at CDR output with total 39dB attenuation between the PA output and LNA input.......................................117 5-23 Waveform of (a) amplitude modulated signal by a 400Mbps pattern 01506250 at TX output, (b) demodulated signal at BB out, and recovered clock at CDR output with total 39dB attenuation between the PA output and LNA input.......................................118 5-24 Waveform of (a) amplitude modulated signal by a 400-Mbps 060606 pattern at TX output, (b) demodulated signal at BB out, and recovered clock at CDR output with total 20dB attenuation between the PA output and LNA input.......................................118 5-25 Waveform of (a) amplitude modulated signal by a 400-Mbps 01506250 pattern at TX output, (b) demodulated signal at BB out, and recovered clock at CDR output with total 20dB attenuation between the PA output and LNA input...............................119 5-26 Waveform of demodulated signal (varying amplitude levels 01506250) at BB output when the data rate of modulating signal is (a) 200Mbps and (b) 100Mbps with total 20dB attenuation between the PA output and LNA input...............................................119 5-27 Waveform of (a) amplitude modulated signal by a 400-Mbps 0241353246 pattern at TX output, (b) demodulated signal at BB output, and recovered clock at CDR output with total 20dB attenuation between the PA output and LNA input...............................121 12

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5-28 Waveform of demodulated signal (varying amplitude levels 0241353246) at BB output when the data rate of modulating signal is (a) 200Mbps and (b) 100Mbps with total 20dB attenuation between the PA output and LNA input.......................................122 5-29 Jitter histogram of (a) demodulated signal at BB out and (b) recovered clock at CDR output for a modulating signal at 400Mbps with total 20dB attenuation between the PA output and LNA input................................................................................................122 A-1 Block diagram of CDR test structure...............................................................................126 A-2 Schematic of the 5.84GHz LC VCO................................................................................127 A-3 Die photograph of 5.84GHz CDR...................................................................................129 A-4 Photograph of CDR testing printed circuit board............................................................129 A-5 Plot of VCO tuning range and gain at digital bits 0000000.............................................130 A-6 Plot of recovered clock at 365MHz and jitter histogram for a PRBS 2 31 -1.....................131 A-7 Spectrum of recovered clock at 5.84GHz for a PRBS 2 31 -1 input signal........................131 A-8 Plot of phase noise of recovered clock at 5.84GHz for a PRBS 2 31 -1 input signal.........132 B-1 Measurement setup for the transmitter at motor side using an external IF source..........133 B-2 Spectrum of TX motor 1 driven with an external IF signal source.................................134 B-3 Zoomed-in spectrum of TX motor 1 driven with an external IF signal source...............134 B-4 Spectrum of TX motor 7 driven with an external IF signal source.................................135 B-5 Zoomed-in spectrum of TX motor 7 driven with an external IF signal source...............135 13

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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy TECHNIQUES FOR CRYSTALLESS OPERATION OF WIRELESS INTER-CHIP DATA COMMUNICATION SYSTEMS By Kyujin Oh August 2010 Chair: Kenneth K. O Major: Electrical and Computer Engineering Use of wireless inter-chip data communication to isolate return paths of high voltage motor drive sections and a low voltage digital control section in an engine controller board of a Hybrid Electric Vehicle (HEV) is presented. The return voltage levels can differ by several hundreds of volts. Presently, the board utilizes numerous photo-couplers that can support ~1 Mbps data rate. Use of conventional radio architecture for this application requires a frequency reference for each high voltage section. This increases cost and board area that makes the approach impractical. Cost effectively providing frequency reference and clock is a fundamental challenge in two way wireless inter-chip communication systems for this type of isolation applications. A fully integrated merged 400-Mbps clock data recovery (CDR) local oscillator (LO) generation circuit which provides both 24-GHz LO signal for a TX and 400-MHz clock for a RX has been demonstrated in a 130-nm foundry CMOS process. A voltage controlled oscillator (VCO) operation at higher than the input data rate at 400Mbps by using a divider (divide-by-60) in the feedback loop enables generation of 24-GHz LO signal for TX and integration of an LC-VCO that uses an inductor with practical size and Q. Including the divider in the feedback loop provides additional degree of freedom for reducing the size of loop filter capacitors for integration. The jitter performance of recovered clock at 400MHz is the lowest among fully 14

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integrated CDRs with the similar data rate (~400Mbps) in the literature. The phase noise of LO signal generated in a CDR with a PRBS 2 31 -1 input is ~10dB worse than that with a clock input. A fully integrated FDMA TX chain at motor side incorporating a CDR, an up conversion mixer, a power amplifier, an IF-generator and an attenuator is demonstrated in the UMC 130-nm CMOS technology. The TX output powers range from the minimum of -4.6dBm to the maximum of 2.3dBm. The target output power is 0dBm. The increased phase noise of LO generated by a CDR does not degrade the performance of ASK systems using a square law detector in the receiver. It should also be possible to use the LO for wide bandwidth systems with other low order modulation schemes. The feasibility of establishing a wireless link within the controller board is also demonstrated using the TX. This indicates that a TX integrated with an RX incorporating a CDR can bypass the need for an external frequency reference. The wireless link demonstration on the board suggests communication range of 15cm should be possible. TX consumes ~192mW of power. An entire RX chain including a new differential baseband amplifier is demonstrated. The RX chain has IP 1dB of -45dBm and sensitivity of ~-45dBm for BER of 10 -12 and 400-Mbps data rate. Furthermore, full-duplex operations of TRX at motor side with an on-chip antenna are investigated by comparing BER performance of RX chain and RMS jitter of recovered clock with TX on and off. The BER degradation due to the TX turned on is small when the input power is sufficiently large to achieve BER of less than 10 -12 RMS jitters of recovered clock increase by no more than ~1ps from ~2.5ps when TX is turned on. These suggest the feasibility of full-duplex operation for CMOS radios with an on-chip antenna. The receiver is also used to detect multi-level AM signals. 15

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CHAPTER 1 WIRELESS INTERCONNECTS IN ENGINE CONTROLLER BOARDS 1.1 Introduction Design of an interface in engine controller board of a Hybrid Electric Vehicle (HEV) [1]-[4] where high voltage motor drive sections and a low voltage digital control section coexist is challenging. The return voltage levels for the sections can differ by greater than 300 volt (V). Presently, the two sections have been electrically isolated using photo-couplers to protect the low voltage section from overvoltage damages. However, the use of more than 10 photo couplers increases cost not to mention the low data transmission rate of less than 1Mpbs. In order to replace photo-couplers used in the hybrid engine controller board, silicon based solutions have been utilized to suggest the feasibility to lower cost and increase data rate. As an alternative to photo-coupler, an electronic isolator that isolates the ground level of high and low voltage sections by coupling signals has been investigated. Several isolators using capacitive coupling method in silicon on insulator (SOI) technology are reported in [5]-[7]. The isolator can achieve 2.3kV ac isolation and 100-MHz signal transmission in an area of 1.5mm 2 [7]. This approach, however, requires a large external coupling capacitor. The electronic isolator can also be realized using inductive coupling [8]. Such an isolator implemented in 130-nm CMOS technology achieves only 70-V DC isolation due to the low breakdown voltage which is not suitable for the hybrid engine controller board. Wireless interconnects using single chip radios including an on-chip antenna can be another lower cost, and high data rate (faster than 100s of Mbps) alternative to the photo-couplers. Unlike the others, it can be fully realized in foundry CMOS. An on-chip antenna is a key block to implement this. On-chip antennas have been extensively studied [9], [10] in both indoor and outdoor environment and integrated in a 20-GHz down converter [11] and a 24-GHz 16

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transmitter [12] for wireless communication. The feasibility of on-chip antennas used for wireless communication in the hybrid engine controller board has been verified [8]. Two separate integrated wireless transceiver circuits can operate with two different ground potentials to handle the large voltage difference. Use of wireless interconnects can also reduce the PC board area by removing metal traces for making connections from and to the photo-couplers. The frequency bands and channels can be allocated without satisfying the emission rules of the Federal Communications Commission (FCC) because the board is contained inside a metallic cover. Incidentally, wireless interconnects using ZigBee could be another wireless solution. However, ZigBee supports very low data rate and requires external crystal references for implementation. 1.2 System Overview Figure 1-1 shows a hybrid engine controller board with two low voltage control nodes (D1, D2) and 12 high voltage motor nodes (M1~M12). Control nodes D1 and D2 called deadtime controllers located at the low voltage section transmit phase information to six motor drivers M1~M6 or M7~M8 in the high voltage sections. The fault status of each driver is transmitted back to the deadtime controller. There are also two links that transmit the motor temperature to the deadtime controller. Among multiple access schemes, Code Division Multiple Access (CDMA) [13] is chosen for downlink from a deadtime controller to each of 6 motors. For a data rate of 50Mbps per channel, spreading spectrum is achieved by multiplying 8-bit Walsh codes with each data bits, which results in a chip rate of 400Mcps per channel. Total 6 encoded waveforms for motor 1~6 are added together in time domain and formed multi-level signal with a chip rate of 400Mcps for transmission [8]. The deadtime controller needs only one transmitter to support the six channels, thereby dramatically reducing RF circuit complexity. For an uplink from the motor to the deadtime controller, Frequency Division Multiple Access (FDMA) is 17

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chosen. Each of two deadtime controllers has a CDMA transmitter and a FDMA receiver supporting 7 channels. Each of six motors has a CDMA receiver and a FDMA transmitter. M5 Figure 1-1. Engine controller board for a HEV. D1 and D2 communicate with M1~M6 and M7~M12, respectively (Courtesy of TOYOTA). Figures 1-2 and 1-3 show signaling scheme for the up and down links and frequency bands in the transmitter and receiver, respectively. The transmission and reception bands are separated by 6GHz to improve isolation between the two bands. The system requires duplex operation with a data transmission rate of 400Mcps from the low voltage digital control section to the high voltage motor drive section and a data transmission rate of 50Mbps from the high voltage motor to the deadtime controller in the low voltage section. The transmission from the low voltage section utilizes a 15.6-18GHz band and the transmission from the high voltage section utilizes a D1 D2 M1 M2 M3 M4 M6 15cm M7 M9 M8 M12 M10 M11 25cm 18

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24.2-27.2GHz. More detailed system specifications can be found in [14]. The frequency plans of transmitter and the receiver at the motor side are summarized in Table 1-1 and depicted in Figure 1-4. In addition, the frequency plans of transmitter and receiver at the deadtime controller side are summarized in Table 1-2 and shown in Figure 1-5. Dead ti me Controller Motor -1 Motor -2 Motor -3 Motor -4 Motor -5 Motor -6 Motor Temp. C D M A C h 1 F DM A C h 1 C D M A C h 2 F D M A C h 2 FD M A C h7 C D M A C h 6 F DM A C h 6 Dead ti me Controller Motor -1 Motor -2 Motor -3 Motor -4 Motor -5 Motor -6 Motor Temp. C D M A C h 1 F DM A C h 1 C D M A C h 2 F D M A C h 2 FD M A C h7 C D M A C h 6 F DM A C h 6 Figure 1-2. Signaling schem e for th e up (FDMA) and down (CDMA) links. 24.2GHz~ 27.2GHz Motor Drivers Deadtime Controller ( 50Mbps ) Figure 1-3. Frequency bands and data ra te in deadtim e controller and m o tors. Table 1-1. Frequency p l ans for tran sm itter and receive r at th e m o tor side TX channel Freq. Band (GHZ) RX channel Freq. Band (GHz) Chip 1 2 4 2 ~ 2 4 6 1 1 5 6 ~ 1 8 0 C 1 1 2 2 4 6 ~ 2 5 0 2 1 5 6 ~ 1 8 0 C 2 2 3 2 5 0 ~ 2 5 3 5 3 1 5 6 ~ 1 8 0 C 3 3 4 2 5 3 5 ~ 2 5 7 4 1 5 6 ~ 1 8 0 C 4 4 5 2 5 8 ~ 2 6 2 5 1 5 6 ~ 1 8 0 C 5 5 6 2 6 2 ~ 2 6 6 6 1 5 6 ~ 1 8 0 C 6 6 Motor 7 2 6 8 ~ 2 7 2 7 Low voltage se ctio n High voltage se ction 15.6GHz ~18GHz ( 400Mcp s ) 19

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24.4 24.8 25.225.5 26.0 26.4 27.0 Motor 1Motor 2 Motor 3 Motor 4 Motor 5 Motor 6 Motor 7 (GHz) 15.618.0 CDMA RX bands FDMA TX bands (24.2 GHz ~ 27.2 GHz) at motor sectionCDMA RX bands (15.6 GHz ~ 18 GHz) at motor section~6GHz isolation between RX & TX bands 24.4 24.8 25.225.5 26.0 26.4 27.0 Motor 1Motor 2 Motor 3 Motor 4 Motor 5 Motor 6 Motor 7 (GHz) 15.618.0 CDMA RX bands FDMA TX bands (24.2 GHz ~ 27.2 GHz) at motor sectionCDMA RX bands (15.6 GHz ~ 18 GHz) at motor section~6GHz isolation between RX & TX bands Figure 1-4. Frequency plans for the transceiver at the motor side. ller channel and Chip Table 1-2. Frequency plan for transmitter and receiver at deadtime contro TX channel Freq. Band RX Freq. B (GHZ) (GHz) 1 15.1 2 6~18.0, C 1 4.2~24.6 1 2 15.6~18.0, C2 2 24.6~25.0 1 3 15.6~18.0, C3 3 25.0~25.35 1 4 15.6~18.0, C4 4 25.35~25.7 1 5 15.6~18.0, C5 5 25.8~26.2 1 6 15.6~18.0, C6 6 26.2~26.6 1 Deadtime controller 7 26.8~27.2 1 Figure 1-5. Frequency plan for transceiver at deadtime controller side. FDMA RX bands (24.2 GHz ~ 27.2 GHz) at deadtime FDMA RX bands (24.2 GHz ~ 27.2 GHz) at deadtime 24.4 24.8 25.225.5 26.0 26.4 27.0 Motor 1Motor 2 Motor 3 Motor 4 Motor 5 Motor 6 Motor 7 (GHz) 15.618.0 CDMA TX bands controller sectionCDMA TX bands (15.6 GHz ~ 18 GHz) at deadtimecontroller section~6GHz isolation between TX & RX bands 24.4 24.8 25.225.5 26.0 26.4 27.0 Motor 1Motor 2 Motor 3 Motor 4 Motor 5 Motor 6 Motor 7 (GHz) 15.618.0 CDMA TX bands controller sectionCDMA TX bands (15.6 GHz ~ 18 GHz) at deadtimecontroller section~6GHz isolation between TX & RX bands 20

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It should be noted that the frequency plans for motor 4 and motor 7 have been slightly chang at d lity of system to detect the transmitted signal, with an acceptable error probas is [16]. rgin is nal radio architecture, the system To ed from the original one where the center frequency of motor 4 and motor 7 are located25.6GHz and 26.8GHz respectively. The frequency of motor 4 is shifted down by 100MHz and motor 7 is shifted up by 200MHz in the updated frequency plan. This is because the 25.5GHz and 27GHz are generated by mixing 24GHz with 1.5GHz and 3GHz intermediate frequencies (IF) respectively. This is much simpler than mixing 24GHz with 1.6GHz and 2.8GHz. The IF-frequency generation will be discussed in Chapter 4. Because of this change, the overall requireTX bandwidth at motor side or, equivalently, RX bandwidth at deadtime controller was changed from 2.8GHz to 3GHz. To evaluate the abi bility, in the presence of noise, link budget analyses are necessary first step. For a separation of 15cm, the link budget analysis for an individual channel of the FDMA linksummarized in Table. 1-3. The output TX power is 0dBm and propagation loss at 27GHz is 45dB. An on-chip dipole antenna on a 100-m thick substrate has gain of -8 dB [15]. The required E b /N o for BER of 10 -13 of a system using non coherent ASK modulation is 14.5dBThe bandwidth of RX is 50MHz and noise figure of RX is assumed 8dB. With all these information taken into account, the required receiver sensitivity is -74.3dBm and link magreater than 15dB for the FDMA link. The link budget analysis for CDMA is also shown in Table 1-4, where sensitivity is -74.3dBm and link margin is 21.3dB. Lastly, if these wireless links were implemented using conventio would require 12 crystal references on motor nodes to provide TX LO signals. This would make implementing a wireless interconnect system impractical due to increased cost. 21

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overcome this challenge, this dissertation research explored system and circuit techniques for crystalless operation of wireless inter-chip data communication. Table 1-3. Link margin analysis for FDMA FDMA (From TX motor to RX deadtime controller) Range (R) 15 cm TX power 0 dBm Propagation Loss @ 27 GHz (/4R) 2 45 dB Antenna Gain (0.25 = 3.2 mm) -7 dB Received power -59 dBm Thermal Noise [kT ( o K)] -173.8 dBm/Hz Bandwidth (50 MHz) 77 dB E b /N o for BER of 1x10 -13 for ASK 14.5 dB RX noise figure 8 dB Sensitivity -74.3 dBm Link margin 15.3 dB Table 1-4. Link margin analysis for CDMA CDMA (From TX deadtime controller to RX motor) Range (R) 15 cm TX power (Total power ~10dBm) 2 dBm Propagation Loss @ 18 GHz (/4R) 2 41 dB Antenna Gain (0.25 = 3.2 mm) -7 dB Received power -53 dBm Thermal Noise [kT ( o K)] -173.8 dBm/Hz Bandwidth (50 MHz) 77 dB E b /N o for BER of 1x10 -13 for ASK 14.5 dB RX noise figure 8 dB Sensitivity -74.3 dBm Link margin 21.3 dB 1.3 Organization of Dissertation The emphases of research are the design of clock and data recovery circuit, crystalless transmitter in motor sections, investigation of the impact of full-duplex operation of TRX with an on-chip antenna, and demonstration of a wireless link between TX at deadtime controller and RX at motor side. In Chapter 1, the system overview of wireless inter-chip data communication on an engine controller board of hybrid electric vehicles (HEV) for signal return path isolation is presented. 22

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Chapter 2 discusses the general properties of such data format as pseudo random binary sequence (PRBS) that a CDR is typically used to characterize. Properties of a phase detector (PD) in comparison to a phase frequency detector (PFD) are described. A linear model of CDR is presented to evaluate the stability of the CDR loop. Finally, the choice of CDR loop bandwidth is discussed. Chapter 3 is dedicated to the proposed CDR design and measurement results. The circuit design of each block making up the CDR and simulation results are described. A fully integrated CDR based 24-GHz LO generation circuit is demonstrated in the UMC 130-nm CMOS technology. Qualitative analysis for the impact of phase noise from the recovered clock to ASK systems using a square-law detector is presented. In Chapter 4, the circuit designs of all TX building blocks at motor side, which include an up-conversion mixer, 3-stage LO buffers, IF generator, attenuator, 8-to-1 multiplexer, and power amplifier are discussed. Compared to the original TX architecture, the new TX architecture adopts a modified CDR structure described in Chapter 3, which enables the system to be simpler and more power efficient. The stand-alone test structure of IF generator followed by an entire TX chain supporting 7 different channels are characterized. Finally, the feasibility of establishing a wireless link using the TX is demonstrated in the UMC 130-nm CMOS technology. In Chapter 5, full RX chains with an improved baseband amplifier for the motor side are fully characterized. The full-duplex operation of TRX at motor side with an on-chip antenna is investigated by comparing BER performance of RX and RMS jitters of recovered clocks. Finally, multiple level AM detection is demonstrated using the RX. The measurements indicated that further work will be needed to make the RX fully support the multiple level signals. Finally, the dissertation is summarized and future works are suggested in Chapter 6. 23

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CHAPTER 2 OVERVIEW OF CLOCK AND DATA RECOVERY CIRCUIT 2.1 Introduction Use of wireless interconnection to isolate the return paths of multiple high voltage motor drive sections and low voltage digital control section in an engine controller board of a Hybrid Electric Vehicle (HEV) is described in Chapter1. The system requires duplex operation with a data transmission rate of 400Mbps from the low voltage digital control section to the high voltage motor drive section and a data transmission rate of 50Mbps from a high voltage section. Transmission from the low voltage section utilizes a 15.6-18GHz band and transmission from the high voltage section utilizes a 24.2-27.2GHz band. The return level for these sections can differ by several hundreds of volts. Use of conventional radio architecture for this application requires a frequency reference for each high voltage section which increases cost and board area. To mitigate this, the system has been architected so that the receiver and transmitter for the high voltage motor sections require no external frequency reference. The conventional LO generation scheme such as a phase lock loop (PLL) cannot be adopted. Instead, clock and data recovery circuit (CDR) is used as a perfect candidate for internal clock generation from incoming data, which is one of unique features of CDR. In the crystalless transceiver architecture, the choice of non-coherent ASK detection as well as CDR obviates the need for the use of external frequency references. Diode detection in RX removes a frequency synthesizer and mixer drivers which simplify the RX and reduce the power consumption. Furthermore, CDR internally recovers clocks, which can be viewed as the frequency reference for the system if the jitter or phase noise of recovered clock can be kept to the minimum. Chapter 2 describes the basics of clock and data recovery circuit (CDR). Among many CDR structures, a phase locked loop (PLL) based CDR with a linear phase detector such as 24

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Hogge detector [17] is emphasized. The serial data stream whose format is called non-return-to-zero is transmitted without an accompanying additional timing reference in many digital systems. A receiver is then required to process this data stream and generate synchronous clock. It is the CDR in the receiver that recovers the clock. Generally, a CDR first produces clock from an internal VCO and then phase-aligns the clock to the transitions of incoming data stream with the help of feed back loop in a PLL. The challenge of clock and data recovery is that data could be a long sequence of ONEs or ZEROs without a transition. During a no-transition period, the voltage controlled oscillator in the PLL may drift or vary in the clock frequency due to the absence of additional correction signal provided by the feed back loop. To ensure frequent transitions, coding schemes are often used. In Chapter 2, the non return to zero data (NRZ) format is first described. A phase detector suited to handle the data format is then introduced. A CDR loop analysis using a linear model for determination of loop stability information by calculating phase margin is presented. Finally, Chapter 2 describes how to choose the CDR bandwidth which is critical for improving the jitter performance of CDR. 2.2 Non Return to Zero (NRZ) Test Pattern NRZ test patterns [18] have been created for system test and verification in digital communication systems. In NRZ signaling, the signal is either high (one) or low (zero) during the entire bit period with equal probability regardless of the state of preceding bits. There is a change in level whenever data change from a high to low or from a low to high. It is therefore possible to have a binary sequence with a long string of consecutive ones or zeros. This situation is referred as having low transition density [18]. Since low transition density data contain low frequency contents, it is difficult to implement ac coupling function and to recover low jitter clock. 25

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It is difficult to generate a completely random binary sequence. Commonly used are pseudo random binary sequences (PRBS) [19]. The PRBS is in fact deterministic and repeats. A PRBS is typically expressed as a PRBS 2 X -1, which creates a pattern 2 X -1 bit long (called length, L), that repeats every 2 X -1 bits. The maximum run length defined by the number of maximum consecutive ones or zeros is equivalent to X. 0 1 0 0 1 1 1 Tb 2Tb 3Tb 4Tb 5Tb 6Tb 7Tb 1L L 0 L 2L1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 1 0 T b Tb 0Tb 2Tb 1L L 0 L 2L Tb TbTbL 2LTb /T b /Tb 01/Tb 2/Tb 1/L /L 0 1/L 2/LTb2 /T b /Tb 01/Tb 2/Tb AutocorrelationFourier Transform AutocorrelationAutocorrelationFourier TransformFourier Transform**===Xttt ff(a)(b)(c) f nL nLt LnfL1fTTbb22sinc7bit pattern (L=7Tb) 7 bits 7 bits L1 LTb2 0 1 0 0 1 1 1 Tb 2Tb 3Tb 4Tb 5Tb 6Tb 7Tb 1L L 0 L 2L1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 1 0 T b Tb 0Tb 2Tb 1L L 0 L 2L Tb TbTbL 2LTb /T b /Tb 01/Tb 2/Tb 1/L /L 0 1/L 2/LTb2 /T b /Tb 01/Tb 2/Tb AutocorrelationFourier Transform AutocorrelationAutocorrelationFourier TransformFourier Transform**===Xttt ff(a)(b)(c) nL nLt LnfL1fTTbb22sinc7bit pattern (L=7Tb) 7 bits 7 bits L1 LTb2 f Figure 2-1. PRBS signal (a) waveform in time domain, (b) autocorrelation, and (c) power spectral density in frequency domain [20]. Figure 2-1(a) shows the waveform in time domain for a PRBS 2 3 -1 signal. A pattern repeats itself every 7bits and the maximum run length is equal to 3. Figure 2-1(b) shows the autocorrelation functions for each component of test patterns shown in Figure 2-1(a). The autocorrelation of 7-bit test pattern approximates a triangle and the accuracy improves with increasing pattern length. Figure 2-1(c) shows the Fourier transform of autocorrelation functions to calculate the power spectral density. There are straightforward relationships between the time 26

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domain characteristics of PRBS test patterns and their frequency domain characteristics. Important observations are as follows [20]. 1. The nulls in the sinc 2 (f) envelop occur at integer multiples of the data rate. 2. Spectral lines are evenly spaced at an interval inversely proportional to pattern length. 3. The sinc 2 (f) envelop flattens out as the data rate and/or pattern length increases. In the limit, as the pattern length approaches infinity, the spacing between the spectral lines becomes infinitesimally small and the spectrum shape approaches a continuous sinc2(f) function. 2.3 Clock and Data Recovery (CDR) Overview A CDR employing a phase locked loop (PLL) to tune the frequency and phase of a VCO to match that of the input data is of focus. Figure 2-2 shows a block diagram of the PLL-based CDR circuit which consists of a phase detector, a charge pump, a loop filter, and a VCO. The phase detector (PD) compares the phase and frequency of the input data with that of a voltage controlled oscillator (VCO) and generates UP/DOWN pulsed signals for phase and frequency correction to the charge pump which is followed by a loop filter. A control voltage from the loop filter adjusts the phase and frequency of an oscillator to match that of the input data. The following subsections overview the fundamentals of CDR blocks. VCOPhase detector Charge pumpInput data RetimedData Loop filterRecovered clock VCOPhase detector Charge pumpInput data RetimedData Loop filterRecovered clock Figure 2-2. Block diagram of CDR. 2.3.1 Linear Phase Detector for Random Data A topology of a linear phase detector [17], [21] and its output waveform under locked condition are shown in Figure 2-3. Under this condition in which the rising edge of clock 27

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samples exactly the center of incoming data, UP signal and DN signal produce the same pulse widths. Retimed data can be either signal A or signal B. Signal A is a half clock delayed and signal B is a clock delayed compared to the input data, DIN. DIN CLK AB UPDN DIN CLK AB UPDN DQCLKDFF1 DQCLKDFF2 CLK DIN UPDNXORXOR AB DQCLKDFF1 DQCLKDFF2 CLK DIN UPDNXORXOR AB (a) (b) Figure 2-3. A linear phase detector (a) block diagram, and (b) waveform under the locked condition. DIN CLK ABUPDN DIN CLK ABUPDN DIN CLK ABUPDN DIN CLK ABUPDN (a) (b) Figure 2-4. Waveform of phase detector for (a) early clock and (b) late clock. Figure 2-4 shows the waveform of (a) early and (b) late clock in the linear phase detector. When the rising edge of clock samples the data before the center point (early clock), the area 28

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under the UP signal is smaller than the DN signal such that the VCO delays the phase of clock, thereby CDR eventually gets driven to the locked condition. On the other hand, when the rising edge of clock samples the data after the center point (late clock) the area under the UP signal is bigger than the DN signal so that VCO pulls the phase of clock forward thereby once again driving the CDR to the locked condition. Unlike a tri-state PFD operation [22] in a PLL, where UP and DN signals turn on simultaneously under the locked condition, DN signal is produced a half clock cycle after the UP signal. This offset in time of the UP and DN signals under locked condition perturbs VCO control line every time data transition occurs, which degrades VCO phase noise. Figure 2-5 shows the characteristic of linear phase detector assuming the maximum transition density of 100%. As DIN CLK becomes zero, the output of phase detector which is an average value of UP-DN equals zero consistent with Figure 2-3(b). Here, DIN CLK being zero means the locked case where the rising clock samples the center of data bit period. When DIN CLK becomes negative (-< DIN CLK <0), it corresponds to the early clock case shown in Figure 2-4(a). Conversely, when DIN CLK becomes positive (0< DIN CLK < ), it corresponds to the late clock case shown in Figure 2-4(b). A linear phase detector as its name implies has limited frequency tracking capability which can be explained using Figure 2-5. Considering the case where large initial frequency difference between DIN and CLK exits, the resulting large phase/frequency error causes the output of phase detector to be quickly swept across different regions (i.e. from point A to point B in Figure 2-5). This is so called cycle slipping [23], [24]. This phase detector output alternating between regions can be averaged to zero by a loop filter. When this occurs, slipping, recovered clock frequency oscillates without getting proper correction information from the feed back loop. 29

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On the other hand, a typical tri-state PFD in a PLL possesses input-output characteristic such that certain polarity, positive or negative rather than zero is provided when being swept across different regions as shown in Fig 2-6. That is why a PFD in a PLL can track frequency not to mention phase Average (UP-DN)DIN-CLK 1-12-2 Average (UP-DN)DIN-CLK 1-12-2 A B Figure 2-5. Input-output characteristic of linear phase detector. Average (UP-DN)REF-DIV 1-12-2 4-4 Average (UP-DN)REF-DIV 1-12-2 4-4 Figure 2-6. Input-output characteristic of tri-state phase and frequency detector (PFD). 30

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2.3.2 Linear Model of CDR 121IcpZ(s) sKvco 2 N1+_Linear Phase DetectorVCODividerDIN OUT Charge PumpLoop Filter 121IcpZ(s) sKvco 2 N1+_Linear Phase DetectorVCODividerDIN OUT Charge PumpLoop Filter Figure 2-7. Linear model of PLL based CDR circuit. Figure 2-7 shows a linear model of CDR circuit. A conventional CDR circuit does not have a divider in the feed back loop. Since frequency division decreases phase by the division ratios, N, a phase divider block is added in the loop. A linear phase detector can be modeled as (1/2)(1/), where (1/2) represents the average transition density for a PRBS (Pseudo Random Bit Sequence) pattern which is the typical input data format for CDR circuit [25] and (1/) represents the gain of linear phase detector or the slope of curve in Figure 2-5. Including (1/2) in the phase detector model reveals that the gain of phase detector depends on the data transition density. A charge pump can be simply modeled as a charge pump current I cp In general, a VCO produces a frequency output which is the input voltage, v in (t) multiplied by VCO gain, K VCO )t(vK)t(finVCOout The unit of K VCO is Hz/V. Integration of output frequency f out (t) leads to phase output as a function of input voltage and VCO gain. 31

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d (t)vK2d )(f2)t(tinVCOtoutout Therefore, the corresponding Laplace model of VCO is simply expressed as sKvco2 The representation of frequency divider in time domain is represented as )t(fN1)t(finout where N is the division factor. If this is expressed in terms of phase, then )t(out is )t(N1d )(fN12d )(f2)t(intintoutout This means the phase transfer function of a frequency divider is as mentioned simply modeled as 1/N. For a loop filter model, the simplest form is chosen, which is a 2nd order passive lead-lag filter whose schematic and transfer function are shown in Figure 2-8. RZCZCP IINVOUT RZCZCP IINVOUT PZPZZPZZZZPINOUTCCCCsRCsCCsRsCsCsIsVsZ11R || 1)()()(Z Figure 2-8. The 2 nd order passive lead-lag filter (a) schematic and (b) transfer function. In order to characterize the stability of feedback loop with phase margin (PM), the open loop gain of CDR needs to be computed. Using the linear model of each block described above, the open loop transfer function is 32

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N1sKCCRCCs1CCsCR1s1IN1sKCCCCsRCsCCsR1IN1sK2)s(ZI121)s(HVCOPZZPZPZZZCPVCOPZPZZPZZZCPVCOCPOL (2.1) The open loop transfer function (2.1) is for a type-two, third-order system. Among the three poles, two poles are at the origin and the third pole P and one zero Z are located at PZZPZPCCRCC and ZZZCR1 (2.2) A Bode plot of the open loop gain is depicted in Figure 2-9. The intersection of magnitude plot and 0dB occurs at t which is referred to as the gain bandwidth of CDR circuit. As indicated in Figure 2-9, phase margin (PM) is defined as the difference between the phase angle at t and -180. From (2.1), PM can be written as Pt1zt1Pt1zt1ttantan180tan9090tan180@phasePM (2.3) 33

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zPt-40dB/dec-20dB/dec-40dB/dec20log |HOL()|log log AngleHOL()-90-180 -1350dB PM zPt-40dB/dec-20dB/dec-40dB/dec20log |HOL()|log log AngleHOL()-90-180 -1350dB PM Figure 2-9. Bode plot of the open loop gain for a CDR circuit. To maximize the phase margin, t should be chosen when tPM is equal to 0. 0111111PMP2PtZ2Ztt (2.4) Solving (2.4) for t the maximum phase margin occurs when PZPM ,t (2.5) PZ is the geometric mean and is located in the center point between the zero Z and the third pole P on a log scale. Typically, phase margin of 60 or higher is preferred for stability. If 34

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Z is defined as a factor below t,PM and P a factor above t,PM the unity gain frequency, t can be derived from (2.1) by replacing tjs and setting the open loop gain H OL (S) as 1. The t is then expressed as, NRKI11CCCNRKIZVCOCP22PZZZVCOCPt (2.6) In addition, the size of passive elements in the loop filter can be calculated. tVCOCPZKINR (2.7) 2tVCOCPtZZ1NKIRC (2.8) 222tVCOCPP1111NKIC (2.9) To achieve sufficient phase margin, both and should be equal and higher than 10 [18]. 2.3.3 Choosing a Bandwidth of CDR For conventional CDRs for wire line applications, many standards such as SONET/SDH (synchronous optical network /synchronous Digital Hierarchy) are already well established and they include detailed jitter specifications. Two important jitter specifications related to choosing the bandwidth of CDR in this proposal is jitter transfer and jitter tolerance. The jitter transfer is defined as the ratio of the output to input jitter of the CDR. This measures how much jitter from the input data signal is present on the output clock signal. A low-pass response is required to suppress jitter. The jitter tolerance is defined as the maxim amount of jitter allowed on the data input signal while still achieving the necessary bit error rates (BER) in detecting the data. It is desired to have a large jitter tolerance bandwidth to track jitter on the data input. Figure 2-10 35

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shows a jitter plot for a simple second order CDR circuit where a loop filter consists of a resistor in series with a capacitor. 121IcpK(s) sKvco 2+_Linear Phase DetectorVCO)(s)(sCharge PumpLoop Filter)(s fCJitter toleranceJitter transferf (log scale) )()(ss )()(ss 121IcpK(s) sKvco 2+_Linear Phase DetectorVCO)(s)(sCharge PumpLoop Filter)(s fCJitter toleranceJitter transferf (log scale) )()(ss )()(ss Figure 2-10. Linear model of second order CDR and its jitter plot. Table 2-1. Summary of jitter specification Corner frequency (f C ) Rate Jitter tolerance Jitter transfer OC-1 20kHz 40kHz OC-3 65kHz 130kHz OC-12 250kHz 500kHz OC-48 1MHz 2MHz Table 2-1 shows the corner frequency of the SONET/SDH (synchronous optical network /synchronous Digital Hierarchy) jitter specification [27], [28]. The SONET/SDH bit rates are multiples of 51.84Mbps. For instance OC-3 signal would have a data rate of 3.84Mbps which is 155.2Mbps. The OC-12 rate is therefore 12.84Mbps or 622.08Mbps. The conflicting requirement between the jitter transfer requiring a narrow band CDR and the jitter tolerance requiring a wide band CDR suggests that the bandwidth must be chosen in the half way between the corner frequencies of two jitter specifications [29]. For example, the bandwidth of CDR should be chosen between 250 kHz and 500 kHz for OC-12 data rate. 36

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2.4 Summary Chapter 2 described the basics of clock and data recovery circuits. Since a CDR circuit recovers clock from a digital data stream whose format is NRZ type, the characteristics of NRZ data format are first discussed. The circuit description and operation of linear phase detector are then followed by loop analysis on linear model of CDR. Finally, the discussion for the choice of CDR bandwidth is presented. 37

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CHAPTER 3 CLOCK AND DATA RECOVERY CIRCUIT AS AN LO GENERATOR 3.1 Introduction The CDR circuit in the transceiver for the motor side takes in 400-Mbps data to generate 400-MHz and 24-GHz LO signal. Moderate data rate (100~1000 Mbps) CDRs use a voltage controlled oscillator (VCO) based on a relaxation oscillator (R.O.) [30]-[34], and typically jitter performance is not good compared to the LC-VCO because of low Q and many noisy transistors used in the circuits. In addition, these CDRs require a large external capacitor for the loop filter except in [32] which requires an external crystal frequency reference. Use of an LC-VCO with better phase noise and jitter performance at moderate data rates is challenging due to a low quality factor (Q) and large size of required inductors. A new CDR structure allows use of an LC-VCO and fully integrated loop filter capacitor despite moderate input data rate (400Mbps). Since the incoming data for CDR is 400Mbps, a conventional CDR structure will generate recovered clock at only 400MHz. However, the new CDR structure generates recovered clocks at both 400MHz and 24GHz. This 24-GHz clock can be used as an LO signal to drive an up-conversion mixer at TX side. RMS phase error of LO signal would be an important performance parameter in digital communication systems, especially those using phase modulation. However, since the transmitter utilizes amplitude shift keying (ASK), the phase noise issue is bypassed. Qualitative analysis on the impact of phase noise on ASK modulated signal at TX output is presented. 3.2 New CDR Structure Figure 3-1 and 3-2 show a block diagram of a conventional CDR structure and the new LO generation circuit merged into a CDR circuit, respectively. The new CDR structure allows use of an on-chip LC-VCO at input data rate of 400 Mbps. Different from the conventional CDR 38

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structure which consist of a phase detector, a charge pump, a loop filter, and a VCO, the new CDR circuit includes a frequency divider in the feedback path, which is similar to continuous-rate CDRs [29], [30], [33]. Figure 3-1. Block diagram of conventional CDR. Figure 3-2. Block diagram of new CDR. Even if structural similarity between proposed CDR and continuous-rate CDRs exists, none of the continuous-rate CDRs have been used as an LO generator. By choosing a division 400MHz Ring oscillator based VCO Phase Detector R Z C Z C P 400Mbps PRBS Charge pump Data 400Mbs Retimed Data Off-Chip 400MHz Recovered Clock Digital tuning 3 24GHz LC VCO Phase Detector R Z C Z C P Divider ( 60) 400Mbps PRBS Charge pump Data 400Mbs Retimed Data 400MHz 24GHz Recovered Clock Recovered Clock 39

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ratio of 60, the VCO is made to operate at 24 GHz. At this frequency, the VCO needs a 352-pH center tapped inductor. The Q of such an on-chip inductor is ~18. These easily make the architecture suitable for integration. A conventional CDR often incorporates a large off-chip capacitor to realize a small loop bandwidth, thereby low-pass filtering the high frequency noise/jitter of incoming data. The capacitor C Z in the loop filter in Figure 3-2 is typically sized as [35]: 2BWCPVCOZWNIKC (3.1) where K VCO I CP N, W BW are VCO gain, charge pump current, division ratio, and loop bandwidth, respectively. The CDR structure that contains a divider after a VCO gives the second benefit of providing an additional control factor to size and reduce the capacitor. In general, as VCO frequency increases, N should increase proportionally assuming the input data rate is fixed. K VCO also increase accordingly. However, since the amount of K VCO increase compared to that of N increase can be made smaller, the size of capacitor C Z can be reduced. Considering the fact that smaller K VCO leads to better phase noise performance, K VCO is already minimized to begin with. For this reason, K VCO itself is not a free knob of reducing C Z Incidentally, I CP in the numerator of Equation (3-1) can not be arbitrarily lowered to reduce the size of capacitor C Z, either. When I CP is lowered, the resistor R Z of loop filter increases, which typically degrade the phase noise and jitter performance of the recovered clock [35]. 3.2.1 Loop Filter A loop filter in Figure 3-2 is a 2nd order passive filter formed with one silicide blocked p + polysilicon resistor and two polysilicon/n-well MOS capacitors [36]. The resulting CDR is then a type-two, third order system [37]. The loop bandwidth of 500-kHz, charge pump current of 60A, divide ratio of 60 and VCO gain of 1GHz/V are chosen. Equations (2.7) ~ (2.9) are used 40

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to compute C Z C P and R Z whose values are 288pF, 32pF and 3.5k, respectively. The biggest capacitor C Z occupies 180m213m. The simulated phase margin of CDR loop is 55. 3.2.2 Voltage Controlled Oscillator (VCO) Figure 3-3 shows a circuit schematic of a 24GHz VCO, which consists of an LC-tank, an NMOS cross coupled pair, noise filter inductor and capacitor, a pair of accumulation mode varactors [38], [39] for continuous fine tuning, a digitally tuned capacitor bank for discrete coarse tuning, a PMOS tail current source, and a pair of inductively loaded buffers. The capacitor bank supports 3-bit digital tuning to keep the VCO gain low for reduced phase noise and loop filter capacitor values, while maintaining an adequate tuning range. To increase inductor Q, L0 is drawn as a single center tapped spiral inductor [40] using top two copper layers shunted together. The total metal thickness is ~1.5m. The metal spacing, width, and number of turns are 3m, 4m, and 3, respectively. The inductance for L1 is 352pH, and the inductor including a polysilicon pattern ground shield [41], [42] occupies 72mm. The simulated Q [43] of inductor is about 18 at 24GHz. The Q of MOS varactor at 24GHz is 13 in the accumulation region and 32 in the depletion region [44]. Since the Q of varactor at 24GHz is almost comparable to the inductor Q, assuming VCO oscillates at 24GHz at the control voltage of 0.6V, the overall tank Q is ~9. The capacitor bank consists of three parallel binary-scaled MOS varactors whose control voltages are connected to either V DD for C min or ground for C max The measured C max /C min is around 3.5. A large capacitor C1 in parallel with the current source M3 shunts noise frequencies around the 2 nd harmonic to ground. A bottom inductor L4 also provides high impedance at the tail in order to block the 2 nd harmonic current from flowing through the switching pair (M1 and M2) to ground, which de-Qs the original LC tank [45]. 41

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Figure 3-3. Schematic of the 24GHz LC VCO. 3.2.3 Divider Chain (Divide-by-60) Figure 3-4 shows the divide-by-60 circuit which starts with a divide-by-2 stage in front followed by a two stage tapered inductor loaded buffers to reduce the load seen by the first divide-by-2 stage. A divide-by-2 stage is used to restore 50% duty cycle for the output of divide-by-5 stage. For the final stage, rather than using a divide-by-3 stage, a divide-by-1.5 followed by a divid-by-2 stage is used to generate recovered clock with a 50% duty cycle. Since the phase detector uses both rising/falling edges of clock to determine the phase difference, keeping a 50% duty cycle is important. All the divider blocks are designed using current mode logic (CML) static frequency dividers with the bottom current source omitted [46] for low voltage operation and a PMOS load with grounded gate [47] except for the divde-by-5 stage where poly silicon V CONT B0 B1 B2 VCO VDD VCO Bias M3 M1 M2 M4 M5 L1 L2 L3 C1 Buffer VDD Buffer VDD OUTP OUTN L4 42

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resistor loads are used to increase the maximum operating frequency. Careful transistor sizing for the 1st divide-by-2 circuit handling 24GHz is required [48]. 2 Stage Buffer Figure 3-4. Block diagram of divider chain (divide-by-60). The divide-by-5 stage consists of three differential D-flip-flops and one AND gates. The first and second flip flops form a divide-by-4, while the third flip-flop adds an extra delay of a clock period to divide-by-5 [49]. Divide-by-1.5 is realized using a conventional divide-by-3 in which a single-edge triggered D-flip-flop is simply replaced by a double-edge triggered D-flip-flop. The circuit schematic of divide-by-2 and each latch circuit is shown in Figure 3-5 [50]. The divide-by-5 and divide-by-1.5 circuits will be discussed in details in Chapter 4. Figure 3-5. Block diagram of divide-by-2 and implementation of latch circuit. 3.2.4 Phase Detector Among popular phase detectors, the linear (Hogge) phase detector has some advantages over non-linear (Alexander) phase detector [51]. One advantage is that a CDR loop adopting a QQLATCH1 DCLK D CLK QQLATCH2 DCLK D CLK ININ OUTOUT DD CLKCLK QQ QQLATCH1 DCLK D CLK QQLATCH2 DCLK D CLK ININ OUTOUT QQLATCH1 DCLK D CLK QQLATCH1 DCLK D CLK QQLATCH2 DCLK D CLK QQLATCH2 DCLK D CLK ININ OUTOUT DD CLKCLK QQ .5 400MHz 24GHz 43

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linear phase detector and a charge pump can be understood using the linear loop theory in a straightforward manner. The other advantage is that a CDR shows less jittery behavior on the VCO control line under the locked condition. Most CDR circuits for multi-Gb/s applications use a non-linear phase detector because a linear phase detector usually poses serious speed bottleneck for high frequency operation in the interface between a linear phase detector and a charge pump. The CDR only needs to support 400-Mbps data rate which is sufficiently low to use a linear phase detector. DQCLKDFF1 DQCLKDFF2 CLK Din DoutUP DNXNORXOR DQCLKDFF1 DQCLKDFF2 CLK Din DoutUP DNXNORXOR DD QQ CLKCLK CLK DD QQ CLKCLK CLK (a) (b) Figure 3-6. Block diagram of (a) phase detector and (b) implementation of each DFF using DCVSL logic circuits. 44

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Figure 3-6 shows (a) the block diagram of the Hogge phase detector and (b) the circuit schematic of the D flip-flop (DFF), respectively. The Hogge phase detector consists of two flip-flops, one XOR and one XNOR. In real implementation of DFF1 and DFF2, differential signaling is utilized although only positive signal is drawn for simplicity in the block diagram. Since DFFs operate with differential signals, differential-cascode-voltage-switch-logic gates (DCVSL) [52] are employed. 3.2.5 Charge Pump (CP) The schematic of charge pump is shown in Figure 3-7 [53], [54]. The UP in the M11 and M12 are directly connected to the output of XNOR gate in the phase detector, and DN in the M15 and M16 are connected to the output of XOR gate in the phase detector. The output node of charge pump is followed by a loop filter. CP current controlUP DNCP outputDNUP M1M2M3M4M5M6M7M8M9M10M11M12M13M14M16M15C1C2 CP current controlUP DNCP outputDNUP M1M2M3M4M5M6M7M8M9M10M11M12M13M14M16M15C1C2 Figure 3-7. Schematic of charge pump. The charge pump current is chosen to be 60A. Since 60A is relatively small, it could be sensitive to process and temperature variations. In order to mitigate this, the length and width of 45

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MOS transistors are intentionally chosen to be large, which also helps to alleviate the mismatch and channel-length modulation problem of mirror transistors. M2 is added to facilitate external current control. C1 and C2 are both 10-pF capacitors to bypass current spikes when M11 and M16 switch between on and off. M12 and M15 are charge removal transistors, which help to cut out long current tail when switch M11 and M16 turn off. As CP output voltage deviates from V DD /2, the current mismatch between up and down path becomes pronounced due to the finite output resistance at the CP output node. 3.3 Simulation Results Figure 3-8 shows a current mismatch between up and down current as the output voltage of charge pump sweeps from 0V to V DD With the V DD of 1.2V, the mismatch between UP and DN current gets bigger as the output voltage deviates from 0.6V. Therefore, under the locked condition, VCO must be designed to oscillate at 24GHz at the control voltage of ~0.6V so that the charge pump optimally operates around 0.6V at which the UP and DN current mismatch is the least. I up -I down (A) CP output voltage (V) Figure 3-8. Plot of current mismatch between up and down current in the charge pump. 46

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Figure 3-9 shows the plot of VCO tuning range with 3-bits digital control for coarse tuning. The gain decreases as the control voltage deviates from center because of the saturation of varactor capacitance. As seen in Figure 3-9, a set of digital bits 000 corresponds to the target tuning curve, which generates 24GHz at VCO control voltage of 0.6V. The lowest digital bits (000) for the target frequency of 24GHz are used in simulations is because based on the previous UMC 130-nm tape-out, the a measured frequency would shift down by ~2GHz compared to the simulation frequency. 111 110 101 100 Frequency 011 (Hz) 010 001 000 ` VCO control voltage (V) Figure 3-9. Simulated VCO tuning range plot with 3-bit digital control for coarse tuning. The plot in Figure 3-10 is the transient response of VCO control voltage. Around 3.5s, the CDR enters the locking region, where recovered clock samples the center of incoming data. Figure 3-11 shows the input data versus recovered clock that is locked. The simulation indicates that the recovered clock almost keeps a 50% duty cycle and the rising edge of clock samples the center of bit period as expected. 47

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Locking Region Control Voltage (V) Time (s) Figure 3-10. Simulated CDR settling behavior at the VCO control voltage. 1 0 1 1 Input Data (V) Recovered Clock (V) Time (s) Figure 3-11. Input data signal versus recovered clock under the locked condition. 48

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3.4 Measurement Results The CDR has been fabricated in the UMC 130-nm logic CMOS technology with eight copper layers. Shown in Figure 3-12 is a die photograph. The chip area without the bond pads occupies 0.79mm.58mm. The CDR has been measured on a PC board with the chip directly mounted on the board (chip-on-board). The measured CDR locking range is from 395 to 405Mpbs. DC Pads 24GHz ClockOutP Figure 3-12. Die photograph of 24GHz CDR. Figure 3-13 shows the measured 3-bit VCO tuning characteristics. The VCO can be tuned from 21.5GHz to 24.5GHz. In order to generate the 24-GHz LO signal, digital tuning bit setting, 111 was selected which covers from 23.5GHz to 24.5GHz. Compared to the simulation result in Figure 3-9, the measured tuning curves shifted down by ~2GHz such that digital tuning bit 111 covers the target frequency around 24GHz. Figure 3-14 shows a VCO tuning range and the corresponding VCO gain for digital tuning bit setting, 111. The measured VCO gain is ~1.3GHz/V around the control voltage of 0.6V in comparison to the designed VCO gain of 400MHz ClockOutP 400MHz ClockOutN 400Mbps DataOutP 400Mbps DataOutN 24GHz ClockOutN 400MHz DataInP 400MHz DataInN VCO and Buffer Divider Loop Filter PD & Charge Pump 49

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1GHz/V. The supply voltage is 1.2V. The VCO draws 6.6mA. The total power consumption of CDR excluding that of the buffers for driving an external 50 load is 18.3mW. 2121.52222.52323.52424.500.20.40.60.811.2VCO voltage (V)VCO Frequency (GHz) 111 110 101 100 011 010 001 000 Figure 3-13. Measured tuning range plot with 3 bits digital control for coarse tuning. 23.223.423.623.82424.224.424.600.20.40.60.811.2VCO Control Voltage (V)VCO Freuqency (GHz)00.20.40.60.811.21.4VCO Gain (GHz/V) Figure 3-14. VCO tuning range a nd gain at digital bits 111. 50

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Figure 3-15. Jitter histogram of the recovered clock at 400MHz for a PRBS 2 31 -1 input. Figure 3-15 shows the jitter histogram of recovered clock at 400MHz with a PRBS 2 31 -1 input. The measured RMS and peak to peak (p-p) jitters are 2.6ps (rms) and 22.2ps (p-p), which are 0.1% and 0.89% of bit period, respectively. Figure 3-16 shows the spectrum of recovered clock at 24GHz with a 400-Mbps PRBS 2 31 -1 input when the CDR is locked. The spectrum of peak near the center frequency is broadened besides the higher in-band phase noise. This broadening originates from the 400-MHz peak extracted during the edge detection process [55] in the linear phase detector. The PRBS NRZ signal with a null at the data rate frequency is converted in the phase detector into pseudo non return to zero (PNRZ) signal with a peak at the data rate frequency [55]. The broadened spectrum near the center frequency results from the densely spaced spectral lines in the PNRZ spectrum. The spacing of spectral lines is scaled by 2 n -1. For n of 31, the spacing between spectral lines is ~0.2 Hz. Figure 3-17 illustrates how the peaks of spectrum for the source PRBS signal manifest in the CDR output spectrum through the CDR loop. 51

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Figure 3-16. Spectrum of the recovered clock at 24GHz for a PRBS 2 31 -1 input. 0400MHz800MHz0400MHz800MHz24GHz CDR BW 12MHz 400n fff0 0400MHz800MHz0400MHz800MHz24GHz CDR BW 12MHz 400n fff0 Figure 3-17. Spectrum of 400Mbps PRBS 2 n -1 signal (top), PNRZ signal after edge detection in the phase detector (middle), and recovered clock at 24GHz (bottom). 52

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Carrier Power -14.61 dBmAtten0.00 dBRef -36.00dBc/Hz10.00 dB /50 KHz20 MHzFrequency Offset-114.83 dBc/Hz10 MHzSpot Freq24-92.06 dBc/Hz1 MHzSpot Freq23-62.98 dBc/Hz100 KHzSpot Freq22-62.27 dBc/Hz60 KHzSpot Freq21ValueX AxisTypeTraceMarker-114.83 dBc/Hz10 MHzSpot Freq24-92.06 dBc/Hz1 MHzSpot Freq23-62.98 dBc/Hz100 KHzSpot Freq22-62.27 dBc/Hz60 KHzSpot Freq21ValueX AxisTypeTraceMarkerMkr4 10.0000 MHz-114.83 dBc/Hz Figure 3-18. Phase noise plot of the recovered clock at 24GHz for a PRBS 2 7 -1 input. Carrier Power -14.48 dBmAtten0.00 dBRef -36.00dBc/Hz10.00 dB /50 KHz20 MHzFrequency Offset-110.94 dBc/Hz10 MHzSpot Freq24-88.73 dBc/Hz1 MHzSpot Freq23-62.66 dBc/Hz100 KHzSpot Freq22-61.33 dBc/Hz60 KHzSpot Freq21ValueX AxisTypeTraceMarker-110.94 dBc/Hz10 MHzSpot Freq24-88.73 dBc/Hz1 MHzSpot Freq23-62.66 dBc/Hz100 KHzSpot Freq22-61.33 dBc/Hz60 KHzSpot Freq21ValueX AxisTypeTraceMarkerMkr2 100.0000 KHz-62.66 dBc/Hz Figure 3-19. Phase noise plot of the recovered clock at 24GHz for a PRBS 2 31 -1 input. 53

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Wider span phase noise plots for a PRBS 2 7 -1 and 2 31 -1 are shown in Figure 3-18 and 3-19, respectively. In Figure 3-18, spurs at integer multiples of ~3.15MHz from 24-GHz output signal result from the spectral lines ~3.15-MHz spacing (400 MHz / (2 7 -1)) in the 400-MHz PNRZ spectrum. Although, the spurs are out of the loop bandwidth of CDR of ~500 kHz, they are too big for the CDR low-pass loop filter to completely suppress them. In the case of 400Mbps PRBS 2 31 -1, the phase noise plot does not show any discrete spurs. This is because the spacing between spectral lines is so close (~less than 0.2Hz) that the resolution bandwidth of 10 kHz for the measurements spreads and averages them. Table 3-1. Summary of measured CDR performance Technology UMC 130-nm Input data rate 400-Mbps CDR lock range 395-Mbps ~ 405-Mbps VCO tuning range 21.5-GHz ~ 24.5-GHz 24-GHz clock phase noise (dBc/Hz) PRBS 2 7 -1 PRBS 2 23 -1 PRBS 2 31 -1 clock input @200MHz VCO @ 60-KHz offset -62.3 -61.0 -61.1 -70.9 -53.4 @ 1-MHz offset -92.1 -90.0 -88.7 -92.6 -96.2 @ 10-MHz offset -112.2 -111.0 -115.2 -115.8 400-MHz clock jitter (ps) RMS rising Peak to peak Input data jitter (RMS rising) with PRBS 2 7 -1 2.19 16.22 1.67 with PRBS 2 23 -1 2.36 21.11 1.89 with PRBS 2 31 -1 2.58 22.22 1.93 BER Less than 10 -13 with 95% confidence for PRBS 2 31 -1 Chip size (w/o pad) 789 584 m 2 Phase detector Charge pump VCO Divider Total (w/o buffer) Power consumption (V DD :1.2V) 501.6(W) 248.4(W) 7.92(mW) 9.64(mW) 18.31(mW) The phase noise performance is measured with PRBS 2 7 -1, 2 23 -1 and 2 31 -1 data streams, and clock input at 200MHz. The phase noise performance is also measured without locking the 24-GHz VCO. These results as well as other measured characteristics of CDR are summarized in Table 3-1. For a PRBS 2 31 -1 input, in-band phase noise at 60-kHz offset is -61dBc/Hz. The 54

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phase noise at 1-MHz offset is -89dBc/Hz and the out-of-band phase noise at 10-MHz offset is -111dBc/Hz. The in-band phase noise at 60 kHz increases by ~9 dB when PRBS data are used instead of a 200-MHz clock. The phase noise at 10-MHz offset increases by 3.0, and 4.2 dB for PRBS 2 23 -1 and 2 31 -1 input, respectively compared to the clock case. The BER performance has been measured using an Agilent N4906A BERT. At 400 Mbps, a total number of 3.456 13 bits was monitored over a 24-hour period. The measured BER with 95% confidence is less than 10 -13 The actual data pattern for the wireless communication system in a hybrid engine controller board is random. The system uses code division multiple access with 8-bit long Walsh codes [14]. The receiver limits (Figure 4-2) the CDMA waveforms to generate an NRZ data fed to the CDR. Because of this, the long sequences of ones or zeros in the PRBS 2 31 -1 are not present in the real NRZ data, and the jitter performance and phase noise performance of the actual system should be better than that for the PRBS 2 31 -1 input case. Table 3-2. Comparison of jitter performance Ref No. VCO type / Tech Off-Chip PRBS Output RMS clock jitter [30] R.O / 0.18m CMOS CAP 2 31 -1 23.4ps (1.46% UI) @622MHz 80.4ps (1.25% UI) @155MHz [31] R.O / 0.35m CMOS CAP 2 31 -1 10.9ps (0.68% UI) @622MHz 18.8ps (0.38% UI) @200MHz [32] R.O / 0.25m CMOS Ext. CLK 4.5ps (0.23% UI) @500MHz 8.3ps (0.21% UI) @250MHz [33] R.O / Bipolar CAP 2 7 -1 5.2ps (0.32% UI) @622MHz 14.4ps (0.22% UI) @155MHz [34] R.O / Bipolar CAP 2 7 -1 62.7ps (0.97% UI) @155MHz [56] R.O / Bipolar Ext. VCO 2 23 -1 17.2ps (0.27% UI) @155MHz This work LC / 0.13m CMOS On-Chip 2 31 -1 2.6ps (0.1% UI) @400MHz 55

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Table 3-2 summarizes the jitter performance of CDRs in the literature with moderate data rates between 100 and 600 Mbps. The jitter of only fully integrated CDR reported here is the lowest by almost factor of two. The measurement results of another CDR test structure that recovers clock at 400MHz and at 5.84GHz for TX LO signal are also presented in Appendix A. 3.5 The Influence of Phase Noise of CDR on ASK Modulation A TX employing an unconventional LO from CDR must deal with the effects of LO phase noise since the LO phase noise from a CDR using jittery incoming data as essentially a frequency reference is worse than that from a PLL using a crystal oscillator as a frequency reference. The effects of phase noise on ASK modulation can be analyzed qualitatively. Referring to TX in Figure 4-2, the LO signal from the CDR can be expressed as )]t(tcos[))t((1A)tsin()t(A)tcos(A))t(sin()tsin(A))t(cos()tcos(A)]t(tcos[A)t(sc2ncncncncnc (3.2) where A denotes amplitude of LO signal, c is LO frequency, n (t) is phase noise, n (t)<<1, cos n (t)1, sin n (t) n (t), and (t) tan -1 n (t) are assumed. The impact of phase noise, n (t) on the amplitude change is negligible. As discussed, IF signals are generated by frequency dividers. For instance, if 2-GHz IF signal is chosen, the original 24-GHz CDR output is frequency divided by 12. After the division, the overall phase noise improves by 20log(24GHz/2GHz)21.6dB [57]. The LO signal from the CDR output and the IF signal from the divider output are mixed together. The former signal consists of desired input signal, S CDR and undesired input noise, N CDR likewise the latter signal consists of desired input signal, S DIV and undesired input noise, N DIV 56

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The, the mixer output is comprised of S OUT desired output signal, and N OUT undesired output noise: DIVCDRCDRDIVDIVCDRDIVCDROUTOUTNNNSNSSSNS (3.3) where the mixer is assumed noiseless, NCDRNDIV can be neglected, and the first term is the desired signal and the second and the third terms constitute undesired noise at the mixer output. The overall SNR at mixer output then can be approximated as [58] DIVCDRDIVCDRDIVDIVCDRCDRDIVDIVCDRCDRCDRDIVDIVCDRDIVCDROUTSNRSNRSNRSNRNSNSNSNSNSNSSSSNR (3.4) The SNR at mixer output is dominated by the lower SNR among two input signals. Therefore, Equation (3.2) is the expression for the mixer output with phase variations mainly due to the CDR phase noise. Finally, the signal is amplitude modulated by the on-off switch in the power amplifier. If a square clock is assumed to be the modulating signal, then the modulating signal and modulated signal can be expressed as [59], [60]: kk00000)k(kk2sin2 wG t7cos71t5cos51t3cos31tcos 221)t(g (3.5) )t(jc)t(jcce Ge G 2A)X( )]t(tcos[A)t(g)t(s)t(g)t(x (3.6) where G() and X() are the Fourier transforms of g(t) and x(t), respectively, 0 is the modulation angle frequency, c is the carrier angle frequency. 57

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The amplitude and phase spectra for x(t) and corresponding waveform in time domain are shown in Figs. 3-20(a), (b), and (c) in order. In Equation (3.6), (t) due to the phase noise from CDR manifests itself as phase variations of each spectral component of modulated signal in the phase spectrum in Figure 3-20(b),These are translated into the phase variations of carrier in the modulated signal in time domain as depicted in Figure 3-20(c). The modulating signal which carries the information is not affected by the phase variation (t). |X(w)| W 0 Figure 3-20. Plots of (a) amplitude and (b) phase spectra for x(t) and corresponding waveform (c) in time domain. 0 (t) phase variation
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When this amplitude modulated signal is demodulated by squaring and low pass filtering in the receiver, the effects of phase variations or LO phase noise is removed. The received amplitude modulated signal with phase variations is )]t()t(tcos[)t(A)t(rc (3.7) where (t) represents the additional phase variations due to the transmission path between a transmitter and a receiver. If the ASK waveform of (3.7) is applied to the input of the square-law detector, the output signal r 1 (t) is 2)]t(2)t(2t2cos[1)t(A)]t()t(tcos[)t(A)t(r)t(rc22c21 (3.8) where is a constant. After low pass filtering, the output r 2 (t) is 2)t(A2)t(A)t(r22 (3.9) where and are constant, and A(t) 2 =A(t) when A(t)=0 or 1. As shown in Equation (3.9), LO phase noise has no effect in ASK systems using a square-law detector. 3.6 Conclusion A merged 400-Mbps fully integrated CDR and 24-GHz LO generation circuit, a key component for a transceiver that can operate without a crystal frequency reference for wireless data communication in a hybrid engine controller board is proposed. The circuit fabricated in 130-nm logic CMOS achieves phase noise of -88.7dBc/Hz at 1MHz offset for the 24-GHz LO signal, RMS jitter of 2.6ps for the 400-MHz recovered clock and BER of less than 10 -13 with a PRBS 2 31 -1 input. The jitter and phase noise performance with the actual data pattern for the system should be better. 59

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To accomplish this at the moderate data rate, the CDR architecture has been modified to include a frequency divider and an LC-VCO with reduced phase noise. The VCO operation at the frequency (24 GHz) 60 times higher than the 400-Mbps input data rate enables generation of LO signal for transmitter with an integrated LC-VCO that uses an inductor with practical size and Q. Including the divider provides additional degree of freedom for reducing the size of loop filter capacitors for integration. The LO signal at 24GHz from the CDR should be suitable for wireless communication systems using simple ASK modulation. It should also be possible to use it as an LO for wide bandwidth systems with other low order modulation schemes. The jitter of this fully integrated CDR reported here is the lowest by almost factor of two compared to the other CDRs for similar data rate. Lastly, it is also reported the phase noise performance of LO signal generated in a CDR and the effects of PRBS input data on phase noise performance. Finally, qualitative analysis of the impact of phase noise on ASK modulated signal at TX output and at RX baseband is presented. The increased phase noise of the LO generated by a CDR does not degrade the performance of ASK systems using a square law detector receiver. 60

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CHAPTER 4 FDMA TRANSMITTER AT MOTOR SIDE 4.1 Introduction The feasibility of implementing the receiver for the motor section in CMOS that supports 400Mbps is already demonstrated [61]. The receiver successfully non-coherently detected an amplitude modulated 400Mbps data stream using Schottky barrier diodes (SBD) [61]. Chapter 4 describes a FDMA transmitter that radiates ASK signal without using an external crystal reference. Before delving into the main discussion of transmitter blocks, first, evolution of transmitter at a motor section for a simplicity and higher power-efficiency eliminating functionally redundant blocks is discussed. The circuit implementation of TX blocks, IF generator, 8 to 1 multiplexer, 3-stage LO buffers, up-conversion mixer, and power amplifier are then presented in order. In the sections 4.5 and 4.6, measurement results of IF generator and entire TX chain fabricated in UMC130-nm CMOS technology are presented. Finally, the feasibility of wireless link from a TX motor to the low voltage section within the controller board is demonstrated. 4.2 Evolution of Transmitter at Motor Side A block diagram of the original transceiver at a motor section is shown in Figure 4-1. A CDR recovers the clock at 400MHz from an incoming 400-Mbps data. The recovered clock signal at 400MHz is followed by a divider that generates the low frequency reference signal for a PLL. The clock at 24GHz is then synthesized by the PLL and used as the LO signal in an up-conversion mixer. The recovered clock is also used to synchronize ADC and decoder operation. This original transceiver has been simplified without compromising the performance of original transceiver. The main distinctive modification is that the phase locked loop (PLL) of transmitter no longer exists in the architecture shown in Figure 4-2. This becomes possible 61

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because a new CDR structure that merges the PLL function into the VCO of CDR can directly provide the 24-GHz LO signa1. Omitting the PLL greatly reduces the circuit complexity, area, and power consumption. Details of the new CDR architecture are already presented in Chapter 3. The CDR provides the frequency references for both 24-GHz LO signal in TX and 400-MHz clock for ADC and decoder in RX, which makes the transceiver a reference-less radio. With the choice of an appropriate modulation scheme such as non-coherent amplitude modulation, detrimental impact of phase noise degradation can be completely eliminated. LNA Limit CDRSBD RectifierampDuplexerMulti-level CDMA signal ADC amp 3Decoder Data Out 400Mbps Data FreqDividerMUX 7 PA TX LO 24GHz 50 Mbps modulating data RX band15.6GHz ~ 18GHzTX band24.4GHz ~27GHz PLL Div 400MHz Clock LNA Limit CDRSBD RectifierampDuplexerMulti-level CDMA signal ADC amp 3Decoder Data Out 400Mbps Data FreqDividerMUX 7 PA TX LO 24GHz 50 Mbps modulating data RX band15.6GHz ~ 18GHzTX band24.4GHz ~27GHz PLL Div 400MHz Clock Figure 4-1. Block diagram of original transceiver at a motor section. Figure 4-2. Block diagram of transmitter at motor side. LNA Limit CDR SBD Rectifier amp Duplexer Multi-level CDMA signal ADC amp 3 Decoder Data Out 400MHz Clock Freq Divide r MUX 7 PA 24GHz Clock RX band 15.6GHz ~ 18GHz TX band 50 Mbps modulating data 24.4GHz ~27GHz 62

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4.3 Circuit Topology of Transmitter at Motor Side A block diagram of the updated transceiver at a motor section is shown in Figure 4-2. The transmitter is comprised of a CDR, an up-conversion mixer, 3 stage LO buffers which are not shown, an IF frequency generator, an attenuator and an 8-to-1 multiplexer, a power amplifier, a duplexer, and a 4-mm on-chip dipole antenna. IF generator 8 to1 MUX Attenuator CDR AC PADMIXERIFLO 2 stage buffer3 stage LO buffer PA24GHz IF generator 8 to1 MUX Attenuator CDR AC PADMIXERIFLO 2 stage buffer3 stage LO buffer PA24GHz Figure 4-3. Block diagram of the interface between a CDR and a mixer. The interface between a CDR and an up-conversion mixer is shown in Figure 4-3. A TX chain starts from the CDR which generates a 24-GHz LO signal. One branch from the CDR drives the IF frequency generator which produces 7 channels ranging from 400MHz to 3GHz. The IF generator is followed by an attenuator for harmonic control, and an 8-to-1 multiplexer for selecting one out of 7 possible channels. The 7th port is for direct connection to an external signal generator. The other branch from a CDR directly drives a mixer LO port through 3-stage inductor loaded cascode buffers. Because of the large layout separation (0.75mm) from the CDR output to the mixer LO port, these buffers must be inserted in order to maintain sufficient drive. An up-conversion mixer is followed by a class-E type power amplifier [62] that is amplitude 63

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modulated using simple on-off switches. Finally, a duplexer following the power amplifier is connected to a 4mm on-chip dipole antenna. 4.3.1 IF Generator Figure 4-4 shows a block diagram of an IF frequency generator. The grey divider blocks use V DD of 1.5V for improved driver operation. All the rest of blocks use V DD of 1.2V. Considering the fact that seven 350-m long metal 8 lines from the output of IF generator are closely spaced (width: 1-m and space: 0.5-m), crosstalk [63] among signals is a concern. To alleviate this problem, only one selected branch carries signal, thereby eliminating the effects of crosstalk. 2 GHz duty(2:1)3 GHz .5 .52.4 GHz duty(3:2) 1.2 GHz 0.4 GHz 0.8 GHz 24GHz12GHz6GHz 1.5 GHz 2.4GHz2.0GHz3.0GHz 2 GHz duty(2:1)3 GHz .5 .52.4 GHz duty(3:2) 1.2 GHz 0.4 GHz 0.8 GHz 24GHz12GHz6GHz 1.5 GHz 2.4GHz2.0GHz3.0GHz : switch Figure 4-4. Block diagram of IF generator. A switch shown as a black box at the end of each branch is a simple shunt NMOS transistor which controls the signal flow. When the switch is on in a branch, signal is bypassed through the switch to the ground, and the branch is deactivated. On the other hand, when the 64

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switch is off, the branch is able to pass signal onto the next block. Therefore, the switch for the selected is off to let the signal pass onto the next block while the switches for the other IF branches are on. The switch control can easily be achieved with the help of a 3-bit decoder implemented inside the 8 to 1 multiplexer. Since the outputs of a 3-bit binary decoder are one-hot encoded [64], adding an inverter after a decoder can provide the necessary control signals for the switches. Table 4-1. IF signal generation Signal Frequency Generation LO 24GHz 24GHz VCO at CDR IF1 0.4GHz LO/2/2/2.5/1.5/2/2 IF2 0.8GHz LO/2/2/2.5/1.5/2 IF3 1.2GHz LO/2/2/2.5/2 IF4 1.5GHz LO/2/2/2 IF5 2.0GHz LO/2/2/3 IF6 2.4GHz LO/2/2/2.5 IF7 3.0GHz LO/2/2 Table 4-1 summarizes the seven IF signal generation schemes from th 24-GHz LO of CDR. If IF signal does not keep 50% duty cycle, the output of up-conversion mixer will contain the undesired harmonic frequency contents that are generated by mixing of LO with harmonics of IF signal. In particular, the 2nd order harmonics of IF signal mixed with LO cause undesired frequency contents that fall in the neighboring motor channels. Assuming the duty cycle of input clock is equal to 50%, the duty cycle of divide-by-1.5 and divide-by-2.5 output are 2:1 and 3:2, respectively. Therefore, divide-by-1.5 and divide-by-2.5 stages need to be followed by a divide-by-2 stage to restore the duty cycle to 50%. Among the seven IF generation circuits, IF5 (2GHz) and IF6 (2.4GHz) do not have 50% duty cycle. The 2nd order harmonics of these mixed with the 24-GHz LO signal produce signals at 20GHz and 65

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28GHz for IF5, and at 19.2GHz and at 28.8GHz for IF6. Since these frequencies are, however, all out of 24.2-27.2GHz TX band, the deviation from 50% duty cycle for IF5 and IF6 is allowed. Since the first divide-by-2 block must operate at the highest frequency of 24GHz, careful design attention is required especially when it is realized by a CML type static divider [48]. All divider blocks in the IF generator are the CML type static dividers. Figure 4-5 shows the schematic and waveform of divide-by-2.5 and divide-by-1.5 circuits. The divide-by-2.5 and divide-by-1.5 circuits are implemented using divide-by-5 and divide-by-3 circuits in which the conventional single-edge-triggered flip flops are simply replaced by double-edge-triggered flip flops (DETFF) [65]. QQDETFF1 DCLK D CLK QQDETFF3 DCLK D CLK AABB ININ QQDETFF2 DCLK D CLK OUTOUT QQDETFF1 DCLK D CLK QQDETFF3 DCLK D CLK AABB AABB ININ QQDETFF2 DCLK D CLK OUTOUT INOUTOUT INOUTOUT QQDETFF1 DCLK D CLK QQDETFF2 DCLK D CLK AABB OUTOUT ININ QQDETFF1 DCLK D CLK QQDETFF2 DCLK D CLK QQDETFF2 DCLK D CLK AABB AABB OUTOUT ININ INOUTOUT INOUTOUT (a) (b) Figure 4-5. Block diagram and waveform of (a) divide-by-2.5 and (b) divide-by-1.5. A block diagram of DETFF and its circuit schematics are shown in Figure 4-6. In Figure 4-6(a), when CLK is high, the value stored in LATCH1 is multiplexed to the output while 66

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LATCH2 is transparent. When CLK is low, the value stored in LATCH2 is multiplexed to the output while LATCH1 is transparent. Hence, DETFF samples the input data at both the rising and falling edges of clock signal. On the other hand, SETFF (single edged triggered flip flop) is triggered at only either the rising or the falling edge of clock signal. As shown in Figure4-6(d), a DETFF can incorporate AND function by merging the AND function [66] and the DETFF. This increases the switching speed and reduces the power consumption. DCLKQ DCLKQ QD1D0 DCLK SLATCH1LATCH2 MUX DCLKQ DCLKQ QD1D0 DCLK SLATCH1LATCH2 MUX D1D1 SS QQ D0D0 D1D1 SS QQ D0D0 DDCLKCLKQQ DDCLKCLKQQ BB CLKCLK QQ AA BB CLKCLK QQ AA (b) (a) (d) (c) Figure 4-6. Block diagram of (a) DETFF and schematic of (b) MUX, (c) LATCH, and (d) AND plus LATCH. 67

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4.3.2 8-to-1 Multiplexer and Attenuator Figure 4-7 shows an 8-to-1 multiplexer (MUX) and an attenuator. The seven frequency channels from 400MHz to 3GHz of IF generator are assigned to seven ports in the MUX and the last one port is allocated for an external signal source. The purpose of an attenuator block is both to reduce signal amplitude, and filter out high order harmonics from the incoming square wave so that the g m stage of up-conversion mixer can properly deal with the incoming IF signal. The attenuator consists of three stage programmable RC low pass filters. Since the frequency of incoming signal can be one of seven different frequencies ranging from 400MHz to 3GHz, the corner frequency of a low pass filter should vary depending on the frequency of incoming signal. Each RC low pass filter is comprised of a 1-k silicide blocked p + poly silicon resistor and a capacitor bank, where four digital bits synthesize the required corner frequency. 0.4GHz0.8GHz1.2GHz1.6GHz2.0GHz2.4GHz3.0GHzExternal8to1MUX 3bits Figure 4-7. Block diagram of 8-to-1 MUX and attenuator. Figure 4-8. Schematic of capacitor bank. b1b2b3b450fF100fF150fF200fF b1b2b3b450fF100fF150fF200fF To PA From IF Generator capbank capbank capbank b1b2b3b4 b1b2b3b4b1b2b3b41k1k1k 0.4GHz0.8GHz1.2GHz1.6GHz2.0GHz2.4GHz3.0GHzExternal8to1MUX 3bits LO(24GHz)IF switch1 switch2 To PA From CDR From IF Generator capbank capbank capbank b1b2b3b4 b1b2b3b4 b1b2b3 b1b2b3b4b1b2b3b4b1b2b3b41k1k1k LO(24GHz)IF switch1 switch2 From CDR 68

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A schematic of capacitor bank is shown in Figure 4-8. There are 4 different sized capacitors with each branch connected to ground through a switching transistor. When the transistor is turned on by connecting the gate of transistor to V DD the capacitor connected to the transistor is activated. Thus, depending on the particular IF frequency selected by the 8-to-1 MUX, the control bits b1, b2, b3, and b4 can be connected to either V DD or GND to synthesize appropriate corner frequency for the RC low pass filter. For N identical stages, overall 3-dB bandwidth is given by [19] 12N0dB3dB3 (4-1) where 3dB0 is the 3-dB bandwidth of each stage. For three identical stages, overall 3-dB bandwidth is then ~0.5 3dB0 For example, in the case of 400MHz IF signal, the 3-dB bandwidth of each stage ( 3dB0 ) should be 800MHz rather than 400MHz. With a resistor 1K, the total capacitance required to achieve the bandwidth of 800MHz for each stage is then ~200fF. This capacitance can then be synthesized by assigning b1 b2 b3 b4 of either 0 0 0 1 or 1 1 1 0. A metal to metal capacitor using metal 5-8 layers is used for the capacitors in the bank. The width and length of all transistors shown in Figure 4-8 are 5m and 120nm, respectively. Illustrated in Fig 4-7, there are two extra switches (switch1 and switch2) that enable incoming signal to bypass the RC stages for measurement purpose. When both switch1 and switch2 are turned on, signal would undergo smaller attenuation. Due to the large area of capacitor banks, the area occupied by the 8 to 1 MUX and attenuator is 320m by 264m. 4.3.3 Three Stage LO Buffer The three stage LO buffer that interconnects the 24GHz output of CDR and the LO port of up-conversion mixer separated by ~600m is shown in Figure 4-9. Since the operating frequency is as high as 24GHz, the inductance of metal lines between LO buffer stages should be properly 69

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accounted. The width of line inductors M L1 M L2 and M L3 are 2m, 1.2m and 3m, respectively. The lengths of M L1 M L2 and M L3 are 220m, 200m, and 160m, respectively. M L1 M L2 and M L3 are all made of metal 8. The simulated corresponding inductance values from M L1 M L2 and M L3 are around 220pH, 200pH, and 160pH, respectively. The Q-factor of L1, L2, and L3 are chosen to be around 5 to accommodate the process variation. The size of all transistors M n1 ~M n6 is 14m/120nm. The supply voltage for the buffer is 1.5V. Figure 4-9. Schematic of three stage LO buffer. 4.3.4 Up-conversion Mixer Figure 4-10 shows the schematic of an up-conversion mixer which is configured as a double balanced mixer to reduce the LO feedthrough. Because of the voltage head room limitation, the bottom current source is taken out. The LO port is driven by the 24-GHz CDR output through the 3-stage LO buffers. The IF port of mixer is connected through the 8:1 MUX and attenuator to the IF frequency generator. IF signals should be sufficiently small such that transistors M n1 and M n2 can function as the g m stage of mixer without being distorted. In addition, harmonic control of IF signal is required in order to prevent unwanted harmonics of selected signal from falling into the neighboring channel as interfering signals. VDD Mn1 L1: 350pH VDD Mn2 L2: 500pH VDD L3: 350pH Mn3 Mn4 Mn5 Mn6 M L1 M L2 M L3 220um 200um 160um OUT IN 70

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The size of transistor M n1 and M n2 in the g m stage is 200m/120nm. The size of transistors M n3 ~M n6 in the switching stage is all 30m/120nm. The simulated conversion gain is around 0dB. The supply voltage of up-conversion mixer is 1.5V. The simulated power consumption is 17.6 mW. Figure 4-10. Schematic of up-conversion mixer. Figure 4-11 shows how a mixing process generates undesired interferers from the harmonics of IF signal and how the undesired interferes affect signals in the neighboring channels. For instance, the 3rd harmonic of IF1 signal mixed with LO signal produces an interferer at 25.2GHz, which happens to be the same desired RF frequency of motor 3 at 25.2GHz. The 5th harmonic of IF1 signal mixed with LO signal also generates an interferer at 26.0GHz, which is the same frequency as the desired RF frequency of motor 5 at 26.0GHz. The interferer at 26.0GHz due to the 5th harmonic of IF1 signal should be negligible because of small signal power. However, an interferer at 26GHz is amplified by the higher gain in the following Mn1Mn2Mn4Mn3Vbias VbiasIF+R1R2 RF+RFC1 Mn6Mn5 C2 235pH235pHIF-LO+LO+LOIF FrequencyMotor1~ 0.4GHzMotor2~ 0.8GHzMotor3~ 1.2GHzMotor4~ 1.5GHzMotor5~ 2.0GHzMotor6~ 2.4GHzMotor7~ 3.0GHz LO Frequency24GHz RF Frequency Mn3~Mn6: 30um /120nmMn1, Mn2: 200um /120nm Motor1~ 24.4GHzMotor2~ 24.8GHzMotor3~ 25.2GHzMotor4~ 25.5GHzMotor5~ 26.0GHzMotor6~ 26.4GHzMotor7~ 27.0GHz VDD Mn1Mn2Mn4Mn3Vbias VbiasIF+R1R2C1 RF+RFMn6Mn5 C2 235pH235pHIF-LO+LO+LOMn3~Mn6: 30um /120nmMn1, Mn2: 200um /120nm IF FrequencyMotor1~ 0.4GHzMotor2~ 0.8GHzMotor3~ 1.2GHzMotor4~ 1.5GHzMotor5~ 2.0GHzMotor6~ 2.4GHzMotor7~ 3.0GHz LO Frequency24GHz RF Frequency Motor1~ 24.4GHzMotor2~ 24.8GHzMotor3~ 25.2GHzMotor4~ 25.5GHzMotor5~ 26.0GHzMotor6~ 26.4GHzMotor7~ 27.0GHz VDD 71

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stage. Because the power amplifier following the mixer has a tuned gain response with a peak gain occurring at around 25.6GHz, the interferer at different frequencies are amplified with varying gains. Finally, the 3rd harmonic of IF2 mixed with LO produces an interferer at 26.4GHz, which is the same frequency as the desired RF frequency of motor 6 at 26.4GHz. Other harmonics of IF signal mixed with LO are all out of band of interest. In summary, it is important to have IF generator to be followed by an tunable filter that also attenuates the IF signal. 3.072.462.051.541.232.40.822.01.20.415th(GHz)3rd (GHz) Freq(GHz) IF 3.072.462.051.541.232.40.822.01.20.415th(GHz)3rd (GHz) Freq(GHz) IF 27.0726.4626.0525.5425.2326.424.8226.025.224.41Interferer(GHz) Freq(GHz) RF(Motor) 27.0726.4626.0525.5425.2326.424.8226.025.224.41Interferer(GHz) Freq(GHz) RF(Motor) LO:24GHz Figure 4-11. Generation of undesired interferers by mixing harmonics of IF signal with LO signal. 4.3.5 Power Amplifier A single ended schematic consisting of three pre-amplifying stages and a class-E type power amplifier [67], [68] is shown in Figure 4-12. The pre-amplifying stages help to increase the signal swing thereby resulting in complete switching in the PA at the last stage. In the schematic, there are two NMOS switches. With the help of these two NMOS switches at the 2nd and 3rd stages, the LO signal can be amplified and quenched based on Data_in signal. The 50-Mbps amplitude modulating signal applied in the Data_in terminal generates ASK modulated 72

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signal at the PA output. For L3~L6, circular shaped inductors with top two metal layers (metal 7 and metal 8) shunted together are used to increase inductor Q. VDD12 VDD4Vb1Vb2Vb310pF VDD3 Vb4M5M1M3M2M6Output StagePre-Amplifier From mixerPA output M4 attenuatorattenuator Figure 4-12. Schematic of power amplifier. The PA is designed to generate 7dBm output power at all frequencies from 24.4 to 27 GHz with VDD of 1.5V. The PA efficiency at the last stage is 33%. The overall PA efficiency is 27%. OP-1dB is designed to be around 7.4dBm. The PA consumes 50mW and the PA chip size is 634m by 700m. The designs and measurement results of a duplexer and a 4mm on-chip dipole antenna are described in [8], [15]. Finally, the simulated power consumption of each block in TX is summarized in Table 4-2. The PA dissipates ~38% of the total power in TX. Table 4-2. Simulated power consumption in TX at motor node generator r MUX & Div2 & Total Data_in InductorL1~453pHL2~254pH L3~326pHL4~388pHL5~189pHL6~320pHL1L2L3L4L5L6 M1, M2: 14m / 120nm M3, M4: 28m / 120nmM5: 40m / 120nm M6: 100m / 120nm VDD12 VDD4Vb1Vb2Vb310pF VDD3 Vb4M5M1M3M2M6 From mixer M4 attenuatorattenuator Data_inL1~453pHL2~254pH L3~326pHL4~388pHL1L2L3LL5L6 100fF75fF75fF46fF VDD12 VDD4Vb1Vb2Vb310pF VDD3 Vb4M5M1M3M2M6Output StagePre-Amplifier From mixerPA output M4 attenuatorattenuator Data_in InductorL1~453pHL2~254pH L3~326pHL4~388pHL5~189pHL6~320pHL1L2L3L4L5L6 M1, M2: 14m / 120nm M3, M4: 28m / 120nmM5: 40m / 120nm M6: 100m / 120nm VDD12 VDD4Vb1Vb2Vb310pF VDD3 Vb4M5M1M3M2M6 From mixer M4 attenuatorattenuator Data_inL1~453pHL2~254pH L3~326pHL4~388pHL1L2L3LL5L6 100fF75fF75fF46fF Block CDR MIX PA IF LO buffe Div2 buffer Power (mW) 20 7.6 50 22.7 132.9 20.4 12.2 Percentage 15 5.7 37.6 15.3 17.1 9.2 100 (%) 73

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4.4 Measurement Results of IF Generator The standalone test structure of an IF geneUX has been fabrich d Figure 4-14 shows the spectrum and waveform of all seven IF signals. The violation of 50% he rator together with an 8 to 1 M ated in the UMC 130-nm CMOS technology. Shown in Figure 4-13 are a die photograpand a testing PC board. IF generator has been measured on a PCB with the chip directly mounteon the board (chip-on-board). Sinusoidal signal at 12GHz from a signal generator is applied to the input of the IF generator by probe-landing directly on the chip. Output signal selected by the 8 to 1 MUX is then measured in the frequency and time domain through a SMA connector. Figure 4-13. Die photograph and testing PC board of IF generator. Input signals DC pads DC pads DC pads DC pad IF gen Bypass cap Chip location Output signals s duty cycle in the waveform manifests itself as a growth in the second order harmonic in tspectrum. In the simulation, only IF signals at 2GHz and 2.4GHz violate 50% duty cycle, which is acceptable because harmonics fall out of TX bands. However, the measured results reveal that IF signals at 800MHz and 1.2GHz also do not have 50% duty cycle in addition to the IF signals at 2GHz and 2.4GHz. 74

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(a) 400MHz (b) 800MHz (c) 1.2GHz (d) 1.5GHz Figure 4-14. Spectrum and waveform of IF signals at (a) 400MHz, (b) 800MHz, (c) 1.2GHz, (d) 1.5GHz, (e) 2.0GHz, (f) 2.4GHz, and (g) 3.0GHz. 75

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(e) 2.0GHz (f) 2.4GHz (g) 3.0GHz Figure 4-14. Continued Figure 4-15 shows interferer generation including the effects of unexpected 2nd order harmonics of IF signals at 800MHz and a 1.2GHz. In particular, the 2nd order harmonic of 800MHz signal at 1.6GHz mixed with 24GHz generates an interferer at 25.6GHz that is only 100MHz away from the RF frequency of motor 4 at 25.5GHz. In addition, the 2nd order harmonic of 1.2GHz at 2.4GHz mixed with 24GHz generates an interferer at 26.4GHz which is 76

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the RF frequency of motor 6. Table 4-3 summarizes the simulated and measured duty cycles of IF signals. The problems of non 50% duty cycle of IF signals at 800MHz and 1.2GHz result from the fact that output waveforms of divide-by-1.5 and a divide-by-2.5 that have originally 40% and 33% duty cycle respectively are not often fully restored to the 50% duty cycle by a subsequent single divide-by-2 circuit. Since the amount of duty cycle violations in the output waveforms are small, adding a simple duty correction circuit after a divide-by-2 is suggested to fix these problems. 2.41.62nd(GHz)3.072.462.051.541.232.40.822.01.20.415th(GHz)3rd (GHz) Freq(GHz) IF 2.41.62nd(GHz)3.072.462.051.541.232.40.822.01.20.415th(GHz)3rd (GHz) Freq(GHz) IF LO:24GHz 26.425.6Interferer(GHz)27.0726.4626.0525.5425.2326.424.8226.025.224.41 Freq(GHz) RF(Motor) 26.425.6Interferer(GHz)27.0726.4626.0525.5425.2326.424.8226.025.224.41 Freq(GHz) RF(Motor) Figure 4-15. Generation of undesired interferers due to the mixing of 2nd, 3rd, and 5th order harmonics of IF signals with LO signal. Table 4-3. Simulated and measured duty cycle of IF signals IF number 1 2 3 4 5 6 7 IF Frequency (GHz) 0.4 0.8 1.2 1.5 2.0 2.4 3.0 Simulated Duty Cycle (%) 50 50 50 50 33.3 40 50 Measured Duty Cycle (%) 53.2 59.4 60.8 50.2 27.1 45.3 49.4 77

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4.5 Measurement Results of TX Chain The TRX at motor side has been fabricated in the UMC 130-nm logic CMOS. Shown in Figure 4-16 is a die photograph of a transceiver. All the circuits and components are fully integrated. The chip area without the bond pads and 4mm on-chip dipole antenna occupies 1.54mm.22mm. The transmitter has been measured on a PCB with the chip directly mounted on the board (chip-on-board). To characterize the clock recovery and LO generation at the proposed CDR circuit followed by mixing, modulation, and amplification at the TX chain, the output spectrum and waveform of ASK modulated signal at the duplexer output are measured while applying 400Mbps PRBS 2 31 -1 signal to the limiter input in the back end of RX. For this measurement, the antenna was cut off. PA Mixer 4mm dipole antenna Duplexer RX CDR & IF gen Figure 4-16. Die photograph of crystalless transceiver at motor section. 4.5.1 Spectrum of TX Output and Harmonic Control The block diagram of TX at motor side and measurement setup are shown in Figure 4-17. An antenna was cut off to eliminate the additional measurement loss and mismatch. The power is 78

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monitored at the duplexer output. This is because only the antenna side has no bond wire the probe landing is possible only in this direction. Measured power at the duplexer output is around 7dB lower than that of power amplifier output due to the high duplexer loss [8] in the frequency band from 24.2GHz to 27.2GHz. Table 4-4 summarizes TX power level at the duplexer output for the 7 motor channels. In the table, power 1 specifies TX output power after de-embeding the cable and balun losses. Measured TX power ranges from the minimum of -4.6dBm to maximum of 2.3dBm, which are close to the target power of 0dBm. Spectrum of TX output with an external IF source are presented in Appendix B. DuplexerPA Laser cutting Monitoring point of the differential TX output power CDRATTEN& MUX & IF GEN MIX 400Mbps PRBS 231-1 DuplexerPA Laser cutting Monitoring point of the differential TX output power CDRATTEN& MUX & IF GEN MIX 400Mbps PRBS 231-1 Figure 4-17. Block diagram of transmitter at motor side. Table 4-4. Summary of TX output power level at motor side Motor 1 2 3 4 5 6 7 Channel (GHz) 24.4 24.8 25.2 25.5 26.0 26.4 27.0 Power (dBm) -10.6 -8.6 -4.6 -8.4 -4.0 -6.8 -4.84 Cable & balun loss (dB) 6.0 6.4 5.9 6.4 6.3 6.8 7.1 Power 1 (dBm) -4.6 -2.2 1.3 -2.0 2.3 0 2.3 *Power 1 : output power after de-embedding the cable and the balun loss. 79

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Figure 4-18. Spectrum of TX motor 1 with attenuator. Figure 4-19. Spectrum of TX motor 1 without attenuator. Figure 4-18 shows the output spectrum of TX for motor 1 at the duplexer output with harmonic control using an attenuator. The peak power level at 24.4GHz is -4.6dBm (-10.6dBm before de-embedding the balun and cable losses). Since the 3rd and the 5th order harmonics of IF 80

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signal at 400MHz fall into the motor 3 (25.2GHz) and 5 (26GHz), the harmonic control is imperative to limit this problem. The 3rd and 5th harmonics of 400MHz mixing with 24GHz turn out to be -28.5dBm at 25.2GHz and -42.7dBm at 26GHz, respectively. The power difference between the undesired interferer at 25.2GHz and the desired signal of motor 3 at 25.2GHz is 30dB (=1.3dBm-(-28.5dBm)), which should be sufficiently large enough to ignore the contribution of the interferer. For comparison, the spectrum of TX motor 1 at the duplexer output without attenuator is shown in Figure 4-19. In this case, the power difference between the undesired interferer at 25.2GHz and the desired signal at 25.2GHz is only 9.8dB (=1.3dBm-(-8.5dBm)), which is not negligible. For the 5th order harmonic of 400MHz, the power difference between the undesired interferer at 26.0GHz and the desired signal at 26.0GHz is 45dB (=2.3dBm-(-42.7dBm)), which should be sufficiently large. The power difference without an attenuator is 14.2dB (=2.3dBm-(-11.9dBm)). Figure 4-20 shows a zoomed-in spectrum at the TX motor1 with span of 100MHz. Figure 4-20. Zoomed-in spectrum of TX motor 1. 81

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Figure 4-21. Spectrum of TX motor 2 with attenuator. Figure 4-22. Spectrum of TX motor 2 without an attenuator. Figure 4-21 and 4-22 show the output spectrum of TX for motor 2 at the duplexer output with an attenuator and without an attenuator, respectively. The unexpected 2 nd harmonic of the IF signal at 800MHz falls into the 25.6GHz which is only 100MHz away from the RF frequency for motor 4. The power difference between the undesired interferer at 25.6GHz and the desired 82

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signal at 25.5GHz is 15.6dB (=-2dBm-(-17.6dBm)) for the case with an attenuator, and 9.3dB (=-2dBm-(-11.3dBm)) for the case without an attenuator. The power differences in both cases are not large, which may cause desired signal at motor 4 to experience distortion. The 3rd order harmonic of IF signal at 800MHz falls into the motor 6 (26.4GHz). The power difference between the undesired interferer at 26.4GHz and the desired sinal at 26.4GHz is 26.5dB (=0dBm-(-26.5dBm)) for the case with an attenuator. Without an attenuator, the power difference is only 8.2dB (=-0dBm-(-8.2dBm)), which should not be acceptable. The output spectrums of TX for motor 3 at the duplexer output with an attenuator and without an attenuator are shown in Figures 4-23 and 4-24, respectively. Similar to the motor 2 case, the unexpected 2nd order harmonic of the IF signal at 1.2GHz mixed with the LO at 24GHz falls into the 26.4GHz which is the RF frequency of motor 6. The power difference between the undesired interferer at 26.4GHz and the desired signal in the channel for motor 6 is 19.4dB (=0dBm-(-19.4dBm)) for the case with an attenuator. The power difference is only 9.4dB (=0dBm-(-9.4dBm)) for the case without an attenuator, which may not be large enough. Figure 4-25 summarizes the impact of interferer signals on desired channels for the case with attenuator. Figure 4-23. Spectrum of TX motor 3 with attenuator. 83

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Figure 4-24. Spectrum of TX motor 3 without attenuator. 24.424.825.225.626.026.426.8 27.2 GHz 30dB 45dB 15.6dB 19.4dB -4.6-2.21.3-2.02.302.3Desired power---28.5-17.6-42.7-19.4-Interferer power (dBm)(dBm) 24.424.825.225.626.026.426.8 27.2 GHz 30dB 45dB 15.6dB 19.4dB -4.6-2.21.3-2.02.302.3Desired power---28.5-17.6-42.7-19.4-Interferer power (dBm)(dBm) Figure 4-25. The impact of interferer signals on desired channels with attenuator on. 4.5.2 ASK Modulation (Carrier at 26GHz Amplitude-modulated by 25MHz Modulating Square Signal) A transmitter that radiates an un-modulated carrier power will send out half of the power when it is ASK modulated by a data with 100% transition. For instance, a 26-GHz transmitter that radiates 1mW of un-modulated carrier power will radiate only 0.5mW of power when it is ASK modulated by the 01010101 data pattern. Furthermore, of 0.5mW, 0.25mW will be in the carrier lobe and the other 0.25mW will be divided among the side lobes. Therefore, the carrier of 84

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ASK modulated signal has 6dB lower power than un-modulated carrier power as shown in Figure 4-26. (a)(b)0dBm-6dBm-10dBm 632mVpp (a)(b)0dBm-6dBm-10dBm 632mVpp Figure 4-26. Waveform and spectrum of (a) un-modulated carrier and (b) ASK modulated carrier. As shown in Figure 4-27, when a square signal with 50% duty cycle is used as an amplitude modulating signal, the power difference between the carrier lobe and the 1st side lobe of ASK modulated signal is 4dB. Thus, the 1 st side lobe of ASK modulated signal has 10dB lower power than un-modulated carrier power. T2T 1 22 232 2520 2T1 T1 2T3 T2 2T5 4dB T2T 1 22 232 2520 2T1 T1 2T3 T2 2T5 4dB Figure 4-27. Waveform and spectrum of square wave with 50% duty cycle. To characterize the ASK modulation of the TX output, one of the seven TX channels, especially motor 5 (26.0GHz), is selected due to its highest output power. Since a 25MHz 85

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square signal with a 50% duty cycle corresponds to a 50Mbps data with 100% transition density, a 25MHz square clock is applied for amplitude modulation. Figure 4-28 shows the spectrum of TX output for motor 5 before and after the ASK modulation with a 25MHz square wave. Once ASK modulated by on-off keying the signal path in the Power amplifier, the overall TX power level decreases by ~6dB from -7dBm to -12.65dBm, This is consistent with the illustration in Figure 4-26. In addition, after modulation, the power difference between the carrier lobe at 26GHz and the 1st side lobe at 25.975GHz or 26.025GHz is 4dB, which means the modulation index is 100%. This can be easily verified by looking at the waveform in Figure 4-29. The modulation index appears to be indeed 100%. Zoom in (span 100MHz)Zoom in (span 100MHz) After Modulation 25MHz 25MHz Figure 4-28. Spectrum of TX output at motor 5 (26GHz) before and after ASK modulation with 25-MHz square signal. Before Modulation 4dB difference : Modulation index 100%(span 10GHz)(span 10GHz) Zoom in (span 100MHz)Zoom in (span 100MHz) After Modulation 25MHz 25MHz Before Modulation 4dB difference : Modulation index 100%(span 10GHz)(span 10GHz) 86

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20ns ~38.46ps (26GHz) Modulation index 100% 20ns ~38.46ps (26GHz) Modulation index 100% Figure 4-29. Waveform of TX output at motor 5 after ASK modulation with 25-MHz square signal. 4.5.3 ASK Modulation (Carrier at 26GHz Amplitude-modulated by 50Mbps PRBS 2 31 -1 Modulating Signal) Figure 4-30 shows the spectrum of TX output at motor 5 before and after the ASK modulation with 50Mbps PRBS 2 31 -1 data signal. Since the modulating signal is a PRBS data rather than a clock signal, a spectrum after the modulation shows nulls at the integer multiples of 50MHz from the carrier frequency at 26GHz, which is the typical property for a PRBS signal. A common way of visualizing long sequences of random data waveform is an eye diagram, which displays an accumulation of edges and levels of data by folding all of the bits into a short interval, e.g., typically two or three bits wide. Figure 4-31 shows a waveform of TX output at motor 5 after ASK modulation with 50Mbps PRBS 2 31 -1 data signal. Accumulation of all of the bits into a short interval creates this waveform in which each data bits are filled with the carrier signal 26GHz. Vertical bit boundaries are colored in darker tone. 87

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Figure 4-30. Spectrum of TX output at motor 5 before and after the ASK modulation with 50Mbps PRBS 2 31 -1data signal. Figure 4-31. Eye diagram output at motor 5 after ASK modulation with a 50Mbps PRBS 2 31 -1 data signal. 20ns ~38.46ps (26GHz) Modulation index 100% 20ns ~38.46ps (26GHz) Modulation index 100% Zoom in (span 100MHz)Zoom in (span 200MHz) Before Modulation After Modulation 50MHz 50MHz (span 10GHz)(span 10GHz) Zoom in (span 100MHz)Zoom in (span 200MHz) Before Modulation After Modulation 50MHz 50MHz (span 10GHz)(span 10GHz) 88

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4.5.4 Wireless Link Test at the Motor TX The feasibility of establishing a wireless link at the TX motor within the controller board is demonstrated. A metallic cover is placed ~3.5cm above the controller board to emulate the operation environment, which increases the received signal power [61]. As shown in Figure 4-32, a 4mm on-chip dipole antenna separated by 5cm from the TX picks up the 26-GHz carrier signal amplitude modulated by 25-MHz square signal. The CDR was driven with 400-Mbps PRBS 2 31 -1 signal. Spectrum Analyzer RX off Lim &CDRon TX on PRBS Generator400Mbps PRBS 231-1 Dup Spectrum Analyzer Balun 5cmcablecable Balun Spectrum Analyzer RX off Lim &CDRon TX on PRBS Generator400Mbps PRBS 231-1 Dup Spectrum Analyzer Balun 5cmcablecable Balun 5cm TRX PCB TRX CHIP 4mm on-chip dipole antenna for receiving the transmitted signal 5cm TRX PCB TRX CHIP 4mm on-chip dipole antenna for receiving the transmitted signal Figure 4-32. Setup of wireless link demonstration at TX motor side. Figure 4-33(a) shows an output spectrum of un-modulated 26GHz carrier signal (CDR output at 24GHz mixed with IF at 2GHz (24GHz/2/3/2)) at the duplexer output without modulation. Figure 4-33(b) shows the spectrum of TX carrier signal at 26GHz modulated by 25-MHz square signal. The ~4-dB amplitude difference between the carrier and the first harmonics 89

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at 26GHz +/25MHz in Figure 4-33(b) indicates the AM modulation index of 100%. This is also consistent with the time domain waveform in Figure 4-33(c) where the peak to peak voltage level is ~320mV and off level is ~10mV. Since the noise level should be less than the off level, SNR should be greater than 30dB. Incidentally, the signal power of -11.4dBm (-17.7dBm + cable/balun loss of 6.3dB at 26GHz) for the 1st side lobe at 26.025GHz in Figure 4-33(b) is ~10dB lower than the un-modulated carrier signal power of -2.15dBm in Figure 4-33(a). Figure 4-33. Spectrum of TX output (a) before modulation (b) after ASK modulation with 25-MHz square clock signal. (c) Waveform of TX output after ASK modulation with 25MHz square clock signal. (d) Spectrum of received 26-GHz carrier signal amplitude modulated by 25-MHz square signal (with metallic cover). With the measured TX signal power at the duplexer output of -11.4dBm (-17.7dBm + cable/balun loss of 6.3dB at 26GHz) at 26.025GHz, the measured signal power at 5 cm separation shown in Figure 4-33 (d) is -56.4dBm (-62.68dBm + cable/balun loss of 6.3dB at 26GHz) or -53.4dBm (2 ASK sidebands). For the case of 15cm separation, received power is expected to be~-64.7dBm. This is ~10 dB higher than the sensitivity target for BER of 10 -13 This margin can be utilized to accommodate the variations of propagation loss and implementation 25MHz 25MHz Res BW 910KHz, VBW 910KHz, Sweep 1ms, Span 100MHz -17.7dBm -17.2dBm -13.5dBm 26GHz -58.31dBm -62.68dBm -62.32dBm 25MHz 25MHz 26GHz Res BW 100KHz VBW 100KHz Sweep 12.08ms Span 100MHz (b) (d) (a) (c) Output power: -2.15dBm (After de-embedding cable & balun loss of 6.3dB at 26GHz) Res BW 10KHz VBW 10 KHz Sweep 4 s (601 pts) Span 100 MHz 20ns ~320mV ~38.46ps 90

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loss of receiver. Table 4-5 summarizes the TX power consumption. The measurement results suggest that a transmitter integrated with a receiver incorporating a CDR can bypass the problem of providing external frequency reference, which is a fundamental technique needed for a two-way wireless inter-chip data communication for return path isolation applications. Table 4-5. Power consumption of transmitter at motor side TX blocks CDR MIX PA IF generator LO buffer MUX & DIV2 & DIV2 buffer Total Power (mW) 18.3 17.6 91.2 25.8 22.7 16.3 191.9 4.6 Conclusion The integrated circuit implementation of the FDMA transmitter at the motor section is presented in Chapter 4. The original transmitter architecture has been simplified by the new CDR architecture that merges the PLL function into the VCO of CDR, thereby reducing the circuit complexity, chip area and power consumption. Individual TX blocks such as an IF generator, an 8-to-1 multiplexer, 3-stage LO buffers, an up-conversion mixer, and a power amplifier are described in both circuit and system levels. The measured duty cycles of IF signals at 800MHz and 1.2GHz are off from 50%. This generates unexpected interfering signals at the other channels. Un-modulated TX carrier powers at the duplexer output are measured for all 7 motor channels. The output Power ranges from the minimum of -4.6dBm to maximum of 2.3dBm. The output powers for motor 3, 5, 6, and 7 satisfy the target power of 0dBm. Finally, the feasibility of establishing a wireless link using the transmitter is demonstrated. A 4mm on-chip dipole antenna separated by 5cm from the TX successfully picks up the 26GHz carrier signal amplitude modulated by a 25MHz square signal. The total TX power consumption is ~192mW where PA dissipates 48% of the total TX power consumption. 91

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CHAPTER 5 DUPLEX OPERATION AND LINK DEMONSTRATION 5.1 Introduction A link between the TX at a deadtime controller and RX at a motor side is demonstrated in Chapter 5. To fulfill the link demonstration, ensuring the satisfactory performance in both TX and RX is the first priority. Furthermore, at a motor side, the feasibility of a full-duplex capability of TRX with an on-chip antenna should be verified to make sure the TX operations do not significantly degrade or, in worst case, disrupt RX performance. A block-level schematic of RX chain at motor side is illustrated in Figure 5-1. The differential LNA output is changed to a single-ended signal using an active current-mirror balun, which is followed by multiple filter stages and amplification stages along the RF signal path. The schottky barrier diode (SBD) is connected in shunt as a half-wave rectifier for signal detection [14]. The down-converted signal is then filtered using a 2nd order 1.2-GHz wide Chebychev low-pass filter. The filter is followed by a 3-stage differential baseband amplifier and a buffer for driving 50. Active balun LNA with 2ndorder BPFRF buffer2ndorder LPF SBD based rectifierMulti-level CDMA signalRecovered Clock Duplexer 3rdorder BPFRF amplifier with 3rdorder BPF RF SectionBaseband amplifier section Limiter CDR Active balun LNA with 2ndorder BPFRF buffer2ndorder LPF SBD based rectifierMulti-level CDMA signalRecovered Clock Duplexer 3rdorder BPFRF amplifier with 3rdorder BPF RF SectionBaseband amplifier section Limiter CDR Figure 5-1. Block diagram of receiver chain at motor section. 92

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In the 1st version of chip, only the RX was integrated. A PC board for the RX measurement was designed and fabricated to characterize the RX chain. Later, however, when both RX and TX at motor side are integrated in the same chip, the increased number of bond pads resulted in longer bond wire between chip and PCB pads. In addition, increased PCB size resulted in longer FR4 traces on the PCB, that increased the parasitic inductance. These can cause stability problems. A main cause of oscillation in the presence of parasitic inductance comes from a single-ended multistage baseband amplifier within the original RX chain. Two examples of instability due to parasitic inductance are illustrated in Figure 5-2. M1 M2 M3 VDDLpar PQ M1 M2 R1Lpar VDD(a)(b) M1 M2 M3 VDDLpar PQ M1 M2 R1Lpar VDD(a)(b) Figure 5-2. Positive feed back path due to parasitic inductors in multistage single-ended amplifiers. In Figure 5-2(a), transient current thorough a parasitic inductor L par due to bond wires and FR4 traces develops voltage at node P. This voltage feeds back to node Q through R1, possibly driving the following common-source stages into oscillation. A positive feedback path is shown using a dotted line. In Figure 5-2(b), a positive-feedback path drawn using a dotted line is created due to the ground bond wire, L par By contrast, for differential amplifier, voltage developed at node Q and P in Figure 5-2 (a) appears as a common-mode disturbance. The ground inductance 93

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in Figure 5-2(b) does not affect the primary positive feedback path in the differential structure [19]. In Chapter 5, a newly designed baseband amplifier is first introduced and the measurement results of the amplifier by itself are presented. The performance of entire RX chain at motor side including the new baseband amplifier is characterized. Furthermore, a full-duplex operation of TRX at motor side is verified. Finally, a wire-line link between the TX at deadtime controller and the RX at motor side is demonstrated. 5.2 A Differential Baseband Amplifier 5.2.1 Circuit Description The original baseband amplifier suffered from the oscillation problem under the nominal V DD and bias condition. Because of this, the original RX was characterized at non-optimum V DD and bias conditions, which degraded gain, and compromised all RX measurement. Therefore, the baseband amplifier has been modified from a single-ended to a differential structure which is less vulnerable to the oscillation problem. However, the differential amplifier also poses the following design challenges. An ideal single to differential conversion at the first stage is supposed to generate balanced differential outputs, showing identical gain and 180 phase difference between the two differential outputs. In practical circuits, however, this cannot be achieved. For instance, a bias current source with finite output impedance and the parasitic capacitor at common-source node results in imbalance. In addition, the AC gate to drain voltage of the input ports are different because one is grounded. Increasing the output impedance of a current source using cascoded transistors reduces the imbalance. Additional cascaded fully differential stages following the single to differential conversion at the first stage suppress the magnitude and phase error further. Simulations indicate 94

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both errors become less than 1% by the time single-ended input signal reaches the differential outputs of final stage. Another concern of the baseband design is DC offset problem due to the mismatch of differential pair and load resistors. Inserting AC coupling capacitors between stages could prevent the DC offset problem. However, choosing a huge capacitor to avoid DC wander in high pass configuration for AC coupling always accompanies the parasitic capacitor, which reduces the bandwidth of a baseband amplifier below the requirement. Since a baseband amplifier needs to process 400-Mbps data stream (same as 200MHz for 100% transition), accounting for the 3rd order harmonic of 200MHz, the overall bandwidth of amplifier should be at least 600MHz. Thus the bandwidth of each stage must be at least ~1.4GHz according to Equation (4-1). 20u/120n 1.6K Vin 1.6K1.6K1.6K1.6K1.6K75 ohm75 ohm30u/120n20u/120n48u/120n40u/240n20u/120n40u/240n20u/120n40u/240n48u/240n I=500uAI=500uAI=500uAI=20mA40u/120n VDDBUFFER VDDVbias_upVbias_dnVbiasVbias_dnVbias_dnVbias_upVbias_upVout 20u/120n 1.6K Vin 1.6K1.6K1.6K1.6K1.6K75 ohm75 ohm30u/120n20u/120n48u/120n40u/240n20u/120n40u/240n20u/120n40u/240n48u/240n I=500uAI=500uAI=500uAI=20mA40u/120n VDDBUFFER VDDVbias_upVbias_dnVbiasVbias_dnVbias_dnVbias_upVbias_upVout Figure 5-3. Schematic of baseband amplifier. Figure 5-3 shows the schematic of a single to differential baseband amplifier. The transistor sizes of a differential pair in each stages are chosen to be as big as possible in order to limit the mismatch induced DC offset while satisfying bandwidth requirement. An earlier stage is 95

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sensitive to the DC offset problem than later stages because signal amplitude increases as signal propagates through the stages Thus, progressive sizing is employed such that the transistor width of differential pair is 40m, 30m, and 20m for the 1st, the 2nd, and the 3rd stage, respectively. To reduce mismatch, a common centroid layout is adopted for the differential pair and silicide blocked P + poly resistors in each stage. The last stage is a buffer stage that drives the 50input impedance of equipment, limiter and ADC. I=100uAVcont I=100uA Vbias_dnVbias_upI=100uA45u/500n45u/500n45u/500nVDD4u/2.16u4u/120n8u/240n M1M2M3M4M5M6M7M8 3u/1u3u/1u I=100uAVcont I=100uA Vbias_dnVbias_upI=100uA45u/500n45u/500n45u/500nVDD4u/2.16u4u/120n8u/240n M1M2M3M4M5M6M7M8 3u/1u3u/1u Figure 5-4. Schematic of the wide-swing cascode current mirror. As shown in Figure 5-4, a wide-swing cascode current mirror provides gate bias voltages for current sources in the baseband amplifier. The idea of this circuit is to bias the drain to source voltages of transistor M8 on the edge of the triode region by setting the gate voltage of M7 at 2V DSAT +V TH such that the cascoded transistors M7 and M8 drop only 2V DSAT while operating in the saturation region. In practical short-channel designs, since the output resistance of a MOSTFET heavily depends on the drain to source voltage, it is imperative to bias M8 deeper into the saturation region by using a larger gate voltage in M7 in order to increase the output 96

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resistance of cascoded current sources. To raise the gate voltage of M7, and thus increase the drain voltage of M8, the length of M5 is chosen to be 18 times larger than that of M7 instead of 4~5 times in long-channel designs. The bias circuit generates 100A of current flow through the mirror transistor M5. The first three stages of baseband amplifier mirrors 5 times of this current when V DD is 1.5V. The buffer stage draws 20mA at V DD of 1.5~1.8V. Additionally, V cont is included for adjusting the current, thus the overall voltage gain of baseband amplifier. 5.2.2 Measurement Results The standalone test structure of baseband amplifier has been fabricated in the UMC 130-nm CMOS technology. A die photograph and a testing PC board are shown in Figure 5-5. The baseband amplifier has been measured on a PCB with the chip directly mounted on the board (chip-on-board). Input and output are terminated with SMA connectors, and 50. Thus, the voltage gain and power gain are the same. Input signal Figure 5-5. Die photograph and baseband amplifier PC board for testing. Figure 5-6 shows the waveforms of square inputs at 200MHz with different amplitudes and corresponding differential outputs. Under the nominal V DD and bias condition, the output Output signal DC pads DC pads Chip location Bypass Cap Amplifier & bias circuit 97

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waveforms confirm that the circuit does not suffer from the oscillation problem and generates balanced differential outputs, also indicating the gain and phase difference between the differential outputs are negligible. When the input voltage level is above ~10mV pp the measured duty cycle difference between differential outputs exhibits less than 1% error from 50%, which implies nearly 180-phase difference between the differential outputs is achieved. As the input level increases, the balance improves. The voltage gain of baseband amplifier is 34dB when the input voltages of 6.8-mV pp in Figure 5-6 (a) and 20-mV pp in Figure 5-6(b) are applied. For larger input voltage of 30-mV pp in Figure 5-6(c), measured gain is reduced to 32dB. Thus, IP 1dB of baseband amplifier occurs at the input power level somewhere between 20mV pp (-30dBm) and 30mV pp (-26.5dBm). By changing V cont the voltage gain can be varied by at least +/3dB from 34dB. The measured worst case rise/fall time (10% to 90%) shown in Figure 5-6(b) is 573ps, which is 11.5% of a data period of 5ns. The rise time of 573ps can be used to estimate the signal bandwidth [69]. time rise35.0freqdB3 (5-1) From Equation (5-1), the estimated signal bandwidth is equal to 611MHz, which is close to bandwidth design target of 600MHz. The measured frequency response in Figure 5-7 shows that the 3-dB bandwidth is 670MHz. The V DD of bias circuit and first 3stages of baseband amplifier are 1.5V. The circuit draws 2.2mA. The buffer stage has a separate V DD of 1.8V and consumes 22mA. The total power consumption is 43mW. Table 5-1 summarizes the measurement results. 98

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(a) 6.8mV pp 170mV pp (b) 20mV pp 550mV pp (c) 30mV pp 580mV pp Figure 5-6. Waveform of a single-ended square wave input at 200MHz. Differential outputs when input voltage level is (a) 6.8mV pp (b) 20mV pp and (c) 30mV pp 99

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Freq -3dB : 670MHz Figure 5-7. Measured 3-dB bandwidth of baseband amplifier in frequency domain. Table 5-1. Summary of measurement results of baseband amplifier Single-ended input power (dBm) -33.3 -30 -26.5 -24.9 Single-ended input voltage (mV pp ) 6.8 20 30 36 Single-ended output voltage (mV pp ) 170 550 580 610 1. Rise/fall time (ps) 581/560 566/552 552/543 491/479 2. Rise/fall time (ps) 602/427 573/463 553/493 484/445 1. Duty cycle (%) 52.2 50.2 50.3 50.4 2. Duty cycle (%) 49.3 49.2 49.4 49.7 Single to differential Voltage Gain (dB) 34 34 32 30.6 3-dB bandwidth (MHz) 670 IP 1dB (dBm) Somewhere between -30 ~ -26.5 Bias circuit & first 3 stages Last buffer stage Total Power dissipation 3.3mW (1.5V / 2.2mA) 39.6mW (1.8V / 22mA) 43mW *1 and 2 indicate each waveform of differential output signals. 5.3 Measurement Results of Full RX Chain for Motor Section The entire RX chain including an updated baseband amplifier at motor side is characterized with a 2-level amplitude modulated signal. Without the oscillation problem under 100

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the nominal V DD and bias condition, RX successfully demodulated the baseband data at 400Mbps from an incoming ASK signal in which the carrier frequency at 16.8GHz is amplitude modulated by PRBS 2 31 -1 signal. Furthermore, the CDR locked to the incoming 2 level data at 400Mbps, and generated the clock and LO signals at 400MHz and 24GHz. In Figure 5-8, a block diagram of RX chain at motor side and measurement setup are illustrated. An antenna and a duplexer are laser-cut. The amplitude modulated RF signal is externally generated using a commercial double side band (DSB) passive mixer. Mixing an LO signal at 16.8GHz and an IF signal at 200MHz square signal or 400Mbps PRBS signal produces a double-sideband large-carrier (DSB-LC) AM signal. Since the designed RX architecture utilizes square-law detection (non-coherent rectifier), to avoid signal distortion, the amplitude modulated signal should contain carrier signal with DSB, ensuring the modulation index is always less than 100%. The RF signal from the mixer output is connected to a balun through the cable, followed by a GSSG probe landing on the bond pads at the input of LNA. Active balun LNA SBD rectifierRecovered Clock @400MHz Limiter CDR Amp BB Amp 16.8GHz 200MHz clock / 400Mbps PRBS signalExternal DSB passive mixerLOIFRF AM modulated Signal Balun& GSSG probe cable BB out Active balun LNA SBD rectifierRecovered Clock @400MHz Limiter CDR Amp BB Amp 16.8GHz 200MHz clock / 400Mbps PRBS signalExternal DSB passive mixerLOIFRF AM modulated Signal Balun& GSSG probe cable BB out Figure 5-8. Block diagram of RX chain at motor section and measurement setup. 101

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The output power, P out versus the input power, P in of RX chain is plotted in Figure 5-9 by applying ASK signals with varying power level to the LNA input while maintaining 100% modulation index. The carrier frequency is 16.8-GHz and amplitude modulating signal is 200-MHz single tone sine wave. In this plot, the power gain of the amplifier is given by the ratio of the output power to the input power. The carrier power does not directly contribute to the output power after demodulation because it does not contain any modulation information. Thus, the practical power gain should be computed by subtracting the input side band power from the output power rather than the input carrier power in a dB scale. The 1 dB compression point, IP 1dB occurs at input sideband power of ~-45dBm. The slope of plots indicates a 2-decade output power increase for an 1-decade input power increase because of the square-law detection. -70-60-50-40-30-20-100-75-70-65-60-55-50-45-40-35-30Pin (dBm)Pout (dBm) Sideband Carrier -70-60-50-40-30-20-100-75-70-65-60-55-50-45-40-35-30Pin (dBm)Pout (dBm) Sideband Carrier Figure 5-9. RX output power as function of input single sideband power and input carrier power (AM modulation index of 100%). The BER of RX chain is measured to figure out the sensitivity of RX chain. The BER measurement setup is described in section 5.4.1 (Figure 5-13). As shown in Figure 5-10, the 102

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measured sensitivity of RX chain for BER of 10 -12 and 400-Mbps data rate is ~-45dBm. The high sensitivity of RX chain is due to the low gain of RF section in the RX chain. Compared to the design target of RF section gain of ~40dB for sensitivity of less than ~-60dBm, measured gain of RF section is ~15dB [14], which results in the significant degradation of RX sensitivity. In order to achieve BER of 10 -12 at even lower sensitivity, RF section should be updated to meet the design target of ~40dB gain. 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BER 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BER Figure 5-10. Measured BER versus input power The performance of an entire RX chain was characterized by applying ASK signal to the LNA input and monitoring the spectrum and waveform at the end of receiver chain. The carrier frequency is 16.8-GHz and amplitude modulating signal is 200-MHz square wave signal. The RMS jitters of recovered clock are also characterized. In the case of the 1st input sideband power of -45dBm in Figure 5-11(a), demodulated signal output power at BB out is -6.5dBm at 200MHz in Figure 5-11(b). Waveforms of demodulated data and recovered clock are shown in Figure 5-11(c). The peak-peak voltage of data is 400mV. A rising edge of a recovered clock at 400MHz in 103

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CDR samples close to center of demodulated data bits. The jitter histogram of recovered clock at 400MHz shows RMS jitter of 1.78ps in Figure 5-11(d). 16.81716.6-39dBm-45dBm(GHz) 16.81716.6-39dBm-45dBm(GHz) 0.20.30.40.50.60.70.80.91.00.11.1 -60-50-40-30 -2-1 00-700 freq, GHz-6.5dBm @ 200MHz (b) (a) (c) (d) Recovered clock Data RMS Jitter 1.78ps Figure 5-11. Plots of (a) Amplitude modulated 16.8-GHz carrier with 200-MHz square wave at LNA input. (b) Spectrum of demodulated 200MHz signal at BB output. (c) Waveforms of demodulated 200MHz signal at BB output and 400MHz recovered clock at CDR output. (d) Jitter histogram of recovered clock at 400MHz. For the following RX chain measurement results, 400-Mbps PRBS 2 31 -1 is used to amplitude modulate 16.8-GHz carrier. Total input power level is kept same as the previous case. This ASK modulated signal is applied at the LNA input, and output spectrum and waveform are monitored. Furthermore, a CDR locks to the 400-Mbps data stream from the BB out, and recovers clock and LO signal at 400MHz and 24GHz. Figure 5-12 shows (a) the spectrum of ASK modulated signal at LNA input, (b) the spectrum of output demodulated signal at BB out, 104

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(c) the waveform of demodulated data and recovered clock at CDR output, and (d) jitter histogram of recovered clock. The jitter performance of recovered clock at 400MHz is measured in the cases of 400Mbps PRBS 2 31 -1, 2 23 -1, and 2 7 -1. The RMS jitters are 2.5ps, 2.5ps, and 2.2ps, respectively. For the first version of RX chip with the oscillation issues, the measured RMS jitters of recovered clock for 400Mbps PRBS 2 31 -1, 2 23 -1, and 2 7 -1 were 29ps, 28.5ps, and 10.3ps, respectively. Thus, a significant jitter reduction is achieved in the updated RX chain to provide TX with more stable and purer LO signal. Table 5-2 summarizes the RX measurement results. The total RX power consumption is 53mW. 0.10.20.30.40.50.60.70.80.91.00.01.1 -75-65-55-45-35-25-85-15 freq, GHz (b) (a) 400MHz 400MHz 16.8GHz 400MHz (c) (d) Data RMS Jitter 2.51ps Recovered clock Figure 5-12. Plots of (a) Amplitude modulated 16.8-GHz carrier with 400-Mbps PRBS 2 31 -1 at LNA input. (b) Spectrum of demodulated 400Mbps signal at BB output. (c) Waveforms of demodulated 400Mbps signal at BB output and 400MHz recovered clock at CDR output. (d) Jitter histogram of recovered clock at 400MHz. 105

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Table 5-2. Summary of RX chain measurement results Carrier: -48 Carrier: -44 Carrier: -39 Input Power (dBm) *modulation index less than 100% 1 st sideband: -54 1 st sideband: -50 1 st sideband: -45 Output power (dBm) @200MHz -22.7 -14.7 -6.5 Output Voltage (mV pp ) ~60 ~120 ~240 RX Power Gain in terms of 1 st sideband input power (dB) 31 35.3 38.5 IP 1dB -45dBm Sensitivity for BER of 10 -12 -45dBm RF section SBD BB amp (w/o buffer) Total Power dissipation 49.5mW (1.5V/33mA) ~0.1mW (0.6V/0.13mA) 3.3mW (1.5V/2.2mA) 53mW with PRBS 2 31 -1 4.70 3.13 2.51 with PRBS 2 23 -1 4.59 3.06 2.48 with RRBS 2 7 -1 4.46 2.65 2.20 RMS Jitter of clock at 400MHz (ps) with clock input @ 200MHz 2.90 1.98 1.78 5.4 Duplex Operation of TRX at Motor Side On-chip antennas in low-cost silicon IC technologies have been verified for use in communication within a chip as well as a beacon (antenna and an oscillator) [10], [70]-[72]. A 20GHz down-converter with an on-chip antenna [11] and a 24GHz transmitter with an on-chip antenna [12] have been reported. However, there have been no reports of duplex communication using CMOS transceivers with on-chip antennas. For a two-way wireless inter-chip data communication for return path isolation application, a full-duplex capability allows for a communication in both directions simultaneously using RX bands from 15.6~18GHz and TX bands from 24.2~27.2GHz. This sub-section 5.4 mainly verifies the impacts of concurrent TX operation on the performance of RX by investigating the degradation of RX BER and RMS jitters of recovered clock. 106

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5.4.1 Characterization of RX with TX On and Off A successful duplex operation of TRX requires sufficient reduction of the leakage signal or noise from TX to RX. The impact of signal/noise coupled from TX on the RX through the substrate, V DD GND and bond-wires is investigated by comparing the BER performance of RX and RMS jitter of recovered clock from the CDR when TX is on and off. Active Balun LNA SBD rectifierRecovered Clock @400MHz CDR Amp BB Amp 16.8GHz 200MHz clock / 400Mbps PRBS signalExternal DSB passive mixerIFLORF Balun& GSSG probe cable BB out Limiter 50Mbps modulating dataPA Up-Mixer IF GeneratorPre Amp Duplexer Laser Cut AM modulated Signal On-ChipAntenna BERT Active Balun LNA SBD rectifierRecovered Clock @400MHz CDR Amp BB Amp 16.8GHz 200MHz clock / 400Mbps PRBS signalExternal DSB passive mixerIFLORF Balun& GSSG probe cable BB out Limiter 50Mbps modulating dataPA Up-Mixer IF GeneratorPre Amp Duplexer Laser Cut AM modulated Signal On-ChipAntenna BERT Figure 5-13. Block diagram of TRX at motor section and measurement setup. Shown in Figure 5-13 is a measurement setup where a duplexer is laser cut off from the LNA input to inject input signal while avoiding the 50 mismatch loss. Similar to the measurement setup in Figure 5-8, the input ASK signal is externally generated and up converted using a commercial DSB passive mixer. Mixing LO signal at 16.8GHz and 200-MHz square wave or 400-Mbps PRBS IF signal produces DSB LC AM signal. For BER measurements, a pattern generator function of BERT is used to transmit the PRBS modulating signals to the external mixer which generates the ASK signal. On the RX side, an analyzer of BERT compares the demodulated baseband signals from the output of receiver chain with the transmitted signals 107

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from the generator. The recovered clock from CDR is used as clock signals in the analyzer where clock signals are synched to the received signals. In the transmitter, a carrier signal is selected from 24.4GHz to 27GHz based on the choice of IF signal. The carrier is on-off keyed by a simple switch circuit in the PA. Since a PRBS pattern resembles the actual modulating signal format used in the system, a 50-Mbps PRBS signal rather than a clock signal should be applied to the switch input as amplitude modulating signal. 2004006000800 -60-40-20-800 2004006000800 -60-40-20-800 2004006000800 -60-40-20-800 5010015002 00 -60-40-20-800 501001500200 -60-40-20-800 501001500200 -60-40-20-800 Frequency (MHz)Frequency (MHz)Frequency (MHz)Frequency (MHz)Frequency (MHz)Frequency (MHz)Power (dBm)Power (dBm)Power (dBm)(a)(b)(c) 2004006000800 -60-40-20-800 2004006000800 -60-40-20-800 2004006000800 -60-40-20-800 5010015002 00 -60-40-20-800 501001500200 -60-40-20-800 501001500200 -60-40-20-800 Frequency (MHz)Frequency (MHz)Frequency (MHz)Frequency (MHz)Frequency (MHz)Frequency (MHz)Power (dBm)Power (dBm)Power (dBm)(a)(b)(c) Figure 5-14. Spectrum of demodulated baseband signal in RX when (a) TX is off, (b) TX is on and a modulating signal for TX is a 50-MHz clock, and (c) TX is on and a modulating signal for TX is a 50-Mbps PRBS 2 7 -1 signal. The plots on the right side are the zoomed-in plots. 108

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It is observed that demodulated baseband signals depend on the type of TX modulating signal, i.e., clock or PRBS signal. Figure 5-14 shows the spectrum when ASK signal (carrier frequency at 16.8GHz is amplitude modulated by a 200-MHz square clock with the 1st sideband RF input signal of ~-45dBm) is applied to LNA input. Compared to the case when TX is off in Figure 5-14(a), the spectrum of baseband signal with TX on reveals a bunch of undesired spurs coupled from the TX side. If the harmonic power levels are comparable to or exceed the desired baseband signal at 200MHz, CDR fails to lock. On the other hand, when TX modulating signal is 50-Mbps PRBS signal, the spectrum of baseband signal is affected much less by the harmonic contents associated with TX as shown in Figure 5-14(c). This is because the spectrum of PRBS signal is flattened due to spreading. So far, the demodulated baseband signal at RX is assumed to be a 200-MHz square wave. However, since the real baseband signal is 400-Mbps data stream similar to the PRBS signal, the 50-Mbps PRBS signal from TX must affect the 400-Mbps demodulated RX PRBS signal differently because spectra of their signals overlap even though the coupled TX PRBS signal is relatively smaller than the RX PRBS signal. In order to quantify these, the RX chain was first characterized by applying ASK signal to the LNA input and monitoring the RMS jitter of recovered clock in CDR with TX turned on. In order to characterize the jitter performance in terms of different RF input power, the 1st side band power of the ASK signal (an LO at 16.8GHz modulated by an IF at 200MHz square signal) is varied from -45dBm (IP 1dB point) to -58dBm (CDR locking sensitivity), below which the CDR fails to lock. The measured RMS jitter versus the RF input sideband power is summarized in Table 5-3. The 200-MHz square clock and 400-Mbps PRBS signals are used as the modulating signal of RF input. The results show that as RF input power decreases, RMS jitters increase. 109

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However, it is noted that the RMS jitter of recovered clock at each RF input power increases by no more than ~1ps when TX is turned on. Figure 5-15 shows the plots of RMS jitters summarized in Table 5-3. Table 5-3. Summary of measured jitter performance RF input 1 st side band power (dBm) -58 CDR locking Sensitivity -54 -50 -45 RMS Jitter (ps) RMS Jitter (ps) RMS Jitter (ps) RMS Jitter (ps) Modulating Signal TX off TX on TX off TX on TX off TX on TX off TX on 200MHz clock 8.43 9.38 2.90 3.60 1.98 2.20 1.78 2.08 400Mbps PRBS 2 7 -1 9.36 10.43 4.46 5.54 2.65 2.76 2.20 2.55 400Mbps PRBS 2 23 -1 9.58 10.53 4.59 5.64 3.06 3.10 2.48 2.81 400Mbps PRBS 2 31 -1 9.76 10.64 4.70 5.96 3.13 3.20 2.51 2.86 0246810-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 0246810-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off (a) 200MHz(c) 400MbpsPRBS 223-1(d) 400MbpsPRBS 231-1(b) 400MbpsPRBS 27-1square clock 0246810-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 0246810-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off (a) 200MHz(c) 400MbpsPRBS 223-1(d) 400MbpsPRBS 231-1(b) 400MbpsPRBS 27-1square clock Figure 5-15. RMS jitter plots of recovered clock with and without turning on TX for (a) 200-MHz square clock, (b) 400-Mbps PRBS 2 7 -1, (c) 400-Mbps PRBS 2 23 -1, and (d) 400Mbps PRBS 2 31 -1 modulating signal for RF input. 110

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Secondly, the BER performance of RX chain versus RF input powers are compared to further investigate the impact of simultaneous operation of TX and RX. Table 5-4. Summary of measured BER performance of RX chain at motor side PRBS 2 7 -1 PRBS 2 31 -1 RF Input 1 st side band power (dBm) TX off TX on TX off TX on -44 Less than 1.0 -12 Less than 1.0 -12 2.3 -12 5.8 -12 -45 2.210 -12 5.3 -12 6.3 -11 5.4 -10 -46 3.310 -7 7.1 -6 1.3 -6 8.4 -6 -48 6.710 -5 4.7 -4 1.1 -4 4.1 -4 -50 1.110 -2 1.9 -2 2.5 -2 4.3 -2 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off TX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERPRBS 231-1PRBS 27-1 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERPRBS 231-1PRBS 27-1 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERPRBS 231-1PRBS 27-1 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERPRBS 231-1PRBS 27-1 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off TX onTX off (a) 400MbpsPRBS 27-1(b) 400MbpsPRBS 231-1(c) TX on(d) TX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off TX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERPRBS 231-1PRBS 27-1 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERPRBS 231-1PRBS 27-1 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERPRBS 231-1PRBS 27-1 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERPRBS 231-1PRBS 27-1 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off TX onTX off (a) 400MbpsPRBS 27-1(b) 400MbpsPRBS 231-1(c) TX on(d) TX off Figure 5-16. BER plots (a) 400-Mbps PRBS 2 7 -1 modulation signal for RF input with TX on and off, (b) 400-Mbps PRBS 2 31 -1 with TX on and off, (c) TX on with 400-Mbps PRBS 2 7 -1 and 2 31 -1 modulation signal, and (d) TX off with 400-Mbps PRBS 2 7 -1 and 2 31 -1. 111

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As shown in Table 5-4, the measurements indicate that BER is lower when smaller PRBS length is used such as PRBS 2 7 -1. BER is less than 10 -12 if the RF input power is larger than -44dBm regardless of the PRBS length. When RF input power is less than -45dBm, BER degrades rapidly. At each RF input power level, running TX along with RX indeed degrades BER performance. However, the extent of degradation due to the TX is less than a factor of 10. Especially, when input power is greater than -45dBm, the difference is small. In addition, the degradation of BER is more strongly dependent on the RX input powers than having the TX on or off. This suggests that the degradation is related to the low gain problem of receiver. If the gain is increased, the impact of having TX on should be reduced at even low RX input levels. Figure 5-16 shows BER plots based on the measured data in Table 5-4. 5.4.2 Characterization of RX with TX On and Off using the Chip without Laser Cut So far, the impact of TX operation to RX performance has been investigated using chips with the connection between duplexer and LNA input laser cut. However, a concern of this setup is that the impact of coupling or leakage of TX signal/noise via the duplexer and the on-chip antenna to the LNA side is not fully captured because of the laser cut. To investigate the effects of this, circuits without the laser cut are characterized. The new measurement setup is exactly same as Figure 5-13 except the laser cut. When a probe lands on the chip pads at the LNA input to apply the RF signal, higher power should be applied to compensate for the mismatch loss resulting from the probe load. By observing the output signal power at the baseband output, the RF input power can be estimated using the P in versus P out plot in Figure 5-9. The RMS jitter of recovered clock and the BER performance of RX chain are measured using RF input 1st side band power of -47dBm. RMS jitter and BER with TX on are measured and compared to the cases with TX off, and summarized in Table 5-5. In addition, the new measured data are overlaid in the RMS jitter plots and BER plots in Figure 5-17 and 5-18, 112

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respectively. The measurements indicate the impact of coupling or leakage of TX signal/noise via the duplexer and the on-chip antenna to the LNA side is negligible. These indicate that full duplex operation using on-chip antennas are possible. Table 5-5. Summary of measured RMS jitter and BER performance RMS jitter of recovered clock with TX on and off (Effective RF input of -47dBm) Modulating Signal 200MHz square clock 400Mbps PRBS 2 7 -1 400Mbps PRBS 2 23 -1 400Mbps PRBS 2 31 -1 TX off 1.86ps 2.37ps 2.44ps 2.46ps RMS Jitter TX on 2.45ps 2.78ps 2.80ps 2.96ps BER performance with TX on and off PRBS 2 7 -1 PRBS 2 31 -1 RF input 1 st side band power of TX off TX on TX off TX on -47dBm 2.510 -7 6.8 -6 3.2 -6 9.5 -6 0246810-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 0246810-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off (a) 200MHz(c) 400MbpsPRBS 223-1(d) 400MbpsPRBS 231-1(b) 400MbpsPRBS 27-1square clock 0246810-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 0246810-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off 024681012-60-55-50-45Input Power (dBm)RMS Jitter (ps)TX onTX off TX onTX off (a) 200MHz(c) 400MbpsPRBS 223-1(d) 400MbpsPRBS 231-1(b) 400MbpsPRBS 27-1square clock Figure 5-17. RMS jitter plots at RF input power of -47dBm with TX on and off for (a) 200MHz square clock, (b) 400Mbps PRBS 2 7 -1, (c) 400Mbps PRBS 2 23 -1, and (d) 400Mbps PRBS 2 31 -1. The connection between the LNA and duplexer is not laser cut. 113

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1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off TX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off TX onTX off (a) 400MbpsPRBS 27-1(b) 400MbpsPRBS 231-1 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off TX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off 1.00E-141.00E-121.00E-101.00E-081.00E-061.00E-041.00E-02-52-50-48-46-44-42Input Power (dBm)BERTX onTX off TX onTX off (a) 400MbpsPRBS 27-1(b) 400MbpsPRBS 231-1 Figure 5-18. BER plots at RF input power of -47dBm for (a) 400Mbps PRBS 2 7 -1 with TX on and off, and (b) 400Mbps PRBS 2 31 -1 with TX on and off. The connection between LNA and duplexer is not laser cut. 5.4.3 Wireless Demonstration of Duplex Operation at Motor Side A full-duplex operation of TRX at motor side is observed by picking up signals from both TX and RX bands at the same time as shown in Figure 5-19 4mm on-chip dipole antenna for transmitting the RF signal TRX CHIP Horn AntennaFreq: 18~28GHz Gain: 20dBi 5cm TX band 24.2~27.2GHz RX band 15.6~18GHz RX band 15.6~18GHz Spectrum analyzer 4mm on-chip dipole antenna for transmitting the RF signal TRX CHIP Horn AntennaFreq: 18~28GHz Gain: 20dBi 5cm TX band 24.2~27.2GHz RX band 15.6~18GHz RX band 15.6~18GHz Spectrum analyzer Figure 5-19. Measurement setup for the duplex operation of TRX at motor side A 4-mm on-chip dipole antenna separated by 5-cm from the TRX radiates the 16.8-GHz carrier signal amplitude modulated by 400-Mbps PRBS signal. The radiated ASK modulated 114

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signals are picked up by the RX on the other side via a 4-mm on-chip dipole antenna and by an external horn antenna placed ~7cm above the surface. The received ASK signal in RX is rectified and fed to CDR. Internally generated TX LO signal at 24GHz from CDR mixed with IF signal at 1.5GHz generates a carrier signal at 25.5GHz that is amplified and amplitude modulated by a modulating signal, i.e. 50Mbps PRBS signal, in PA. Finally, the ASK modulated TX signal is fed to a duplexer and radiated via the on-chip dipole antenna. Figure 5-20 shows the captured spectrum in both RX band (15.6~18GHz) and one of TX channels (25.35~25.7GHz). 16.517.518.519.520.521.522.523.524.525.515.526.5 -80-70-60-50-40-90-30 RX band 15.6~ 18GHz TX band (motor4) 25.35~ 25.7GHzFrequency (GHz)Power (dBm) 16.517.518.519.520.521.522.523.524.525.515.526.5 -80-70-60-50-40-90-30 RX band 15.6~ 18GHz TX band (motor4) 25.35~ 25.7GHzFrequency (GHz)Power (dBm) Figure 5-20. Spectrum of both RX and TX band at motor side 5.5 Detection of Multiple Level ASK Signal For the wireless communication in the hybrid engine controller board, the RX must detect multi-level ASK signals. To evaluate this, multi-level AM signal is generated using a stand alone coder and PA [62] combination for the TX of the deadtime controller side. A carrier signal at 16.8-GHz is amplitude modulated by 400-Mbps multi-level signal from the output of coder generates AM signals with seven different levels. Block diagrams of RX and the PA at TX along with the measurement setup is shown in Figure 5-21. A single-ended PA output at TX is 115

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connected to differential LNA input in RX through a GS probe landed on the PA output, an RF cable followed by a variable attenuator emulating propagation loss, a balun converting single to differential signal and a GSSG probe landed on differential LNA inputs. The antenna and duplexer are laser-cut off to avoid the mismatch loss. Unlike wireless channels that are random and difficult to analyze, the wired interconnection in this setup provides stationary and predictable channel behaviors. Active balun LNA SBD rectifierRecovered Clock @400MHz Limiter CDR Amp Amp 16.8GHz Digital coderAttenuatorCarrier signalMulti-level control signal [2][3] PA Pre-amp Balun& GSSG probe GS probe Signal attenuator Monitoring point [1] cable TXRX Active balun LNA SBD rectifierRecovered Clock @400MHz Limiter CDR Amp Amp 16.8GHz Digital coderAttenuatorCarrier signalMulti-level control signal [2][3] PA Pre-amp Balun& GSSG probe GS probe Signal attenuator Monitoring point [1] cable TXRX BB out Figure 5-21. Measurement set up for link demonstration and block diagrams of TX and RX Demodulated multi-level data signal at the baseband output is followed by a limiter in which each level of incoming data is compared with a threshold voltage set to the middle between level 6 and level 0. If the incoming level is bigger than the threshold voltage, signal is railed up to V DD otherwise signal is railed down to GND. Thus, a CDR following the limiter recovers clocks by processing 2-level input signal. This allows use of conventional CDR architecture. It is important to mention that 2-level signals converted from multi-level signals 116

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should not change the minimum data bit period of 2.5ns. For example, if a varying amplitude level such as 012456 repeats itself at a data rate of 400-Mbps, then it becomes 000666 after the limiter and the repetition of this pattern changes original data rate at 400Mbps to one third of 400Mbps, which results in a failure of CDR locking to 400Mbps input signal. An initial measurement setup uses 39dB attenuation (GS probe/cable loss of 3dB, 35dB attenuator, balun/GSSG probe loss of 1dB) between the TX and RX. In case of wireless link, given a pair of antenna loss of 16dB and a duplexer loss of 3dB for TX and RX side, the remaining 17-dB corresponds to a channel loss in free space. This 17dB is equivalent to ~1-cm separation at 16.8GHz. Shown in Figures 5-22 and 5-23 are a carrier signal at 16.8GHz amplitude modulated by an alternating pattern between level 0 and level 6 similar to the 2-level modulating pattern and a 01506250 input pattern, respectively. Each data bit period is 2.5ns. Measured waveforms of demodulated signals at BB out are also shown. For the 39dB attenuation setup, the amplitude of the baseband signal is ~220mV which should fit the ADC input requirement of 300mV. However, it is difficult to clearly distinguish each level. 6 0 6 0 6 0 6 ~220mV pp (b) (a) Figure 5-22. Waveform of (a) amplitude modulated signal by a 400Mbps pattern 060606 at TX output, (b) demodulated signal at BB out, and recovered clock at CDR output with total 39dB attenuation between the PA output and LNA input. 117

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0 1 5 0 6 2 5 0 1 5 0 6 2 5 0 ~220mV pp (b) (a) Figure 5-23. Waveform of (a) amplitude modulated signal by a 400Mbps pattern 01506250 at TX output, (b) demodulated signal at BB out, and recovered clock at CDR output with total 39dB attenuation between the PA output and LNA input. The 2nd measurement setup uses 20dB attenuation between the TX and RX. As shown in Figure 5-24, a carrier signal at 16.8GHz amplitude modulated by an alternating pattern between level 0 and level 6 is captured in time domain. Each data bit period is equal to 2.5ns. The measured waveform of demodulated signal at BB out and 400MHz recovered clock at CDR output are also shown. A rising edge of recovered clock samples the data near the center. 6 0 6 0 6 0 6 ~500mV pp (b) (a) Figure 5-24. Waveform of (a) amplitude modulated signal by a 400-Mbps 060606 pattern at TX output, (b) demodulated signal at BB out, and recovered clock at CDR output with total 20dB attenuation between the PA output and LNA input. 118

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0 1 5 0 6 2 5 0 (b) ~500mV pp (a) Figure 5-25. Waveform of (a) amplitude modulated signal by a 400-Mbps 01506250 pattern at TX output, (b) demodulated signal at BB out, and recovered clock at CDR output with total 20dB attenuation between the PA output and LNA input 0 1 5 0 6 2 5 0 0 1 5 0 6 2 5 0 ~500mV pp ~550mV pp 5ns (b) 10ns (a) Figure 5-26. Waveform of demodulated signal (varying amplitude levels 01506250) at BB output when the data rate of modulating signal is (a) 200Mbps and (b) 100Mbps with total 20dB attenuation between the PA output and LNA input. In Figure 5-25(a), waveform of signal is generated using 400Mbps 01506250 pattern. The carrier frequency is 16.8GHz. The waveform of demodulated signal at BB output and 400-MHz recovered clock at CDR output are shown in Figure 5-25(b). The output waveform of demodulated signal follows the negative envelope of amplitude modulated signal, which is consistent with the detector design. 119

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In comparison to the waveform of baseband signals from the 1st measurement setup using 39dB attenuation, bigger baseband signal (~500mV pp ) results in more recognizable levels. However, the signal amplitude already exceeds the acceptable ADC input range. Thus, in order to accommodate large baseband signals, the ADC should be modified. When the data rate of modulating signal is lower than 400Mbps, demodulated waveform shows clearer distinction between levels. Figure 5-26 shows the waveforms of demodulated signal at 200Mbps and 100Mbps. The results suggest that increasing the bandwidth of baseband amplifier in RX to include up to 5th order harmonics of 200MHz signal improves the signal quality. An amplitude modulated signal that includes the combination of all 7 levels is chosen and the corresponding baseband output is measured. The varying amplitude levels such as 0241353246 cause the malfunction of the comparator of limiter when level-3 is compared. The level-3 located at the center between level 0 and 6 is exactly identical to the threshold voltage that is set at the middle between level 0 and 6. Therefore, level 3 cannot be resolved. This failure results in a long drift of rising edge and disturbing the decision of comparator in the subsequent bit. This eventually increases the jitter of recovered clock and in the worst case CDR fails to lock or generate clock at wrong frequency. As a temporary solution, the threshold voltage could be externally adjusted to create difference between the threshold and level-3. However, this solution is no longer useful when detected baseband signal level is small. If the overall signal level is smaller, the amplitude difference between levels become smaller so that the comparator easily falls into the meta-stable state because setting the threshold voltage slightly above or below the center makes the threshold to be close to another level. In other words, the limiter cannot operate 120

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without generating unacceptably high jitters of recovered clock or CDR locking to wrong data rate when incoming signal consists of a series of middle levels. 0 2 4 1 3 5 3 2 4 6 0 ~420mV pp (b) (a) Figure 5-27. Waveform of (a) amplitude modulated signal by a 400-Mbps 0241353246 pattern at TX output, (b) demodulated signal at BB output, and recovered clock at CDR output with total 20dB attenuation between the PA output and LNA input. Figure 5-27 shows the modulated signal with a 400-Mbps 0241353246 pattern, and demodulated signal at BB output and corresponding recovered clock at 400MHz. Figure 5-28 shows the waveform of demodulated signal at 200Mbps and 100Mbps. When the data rate of modulating signal is at 100Mbps, demodulated waveform shows clear distinction of levels and sharper rising/falling time during level transitions. In Figure 5-29, measured RMS jitter of recovered clock is as high as 47.6ps, which is due to the frequent occurrence of middle levels such as level 3 and 4 in the input pattern. In this case, even though multi-level signals are detected at 400Mbps in the baseband output, CDR generates a recovered clock at 399.4MHz instead of 400MHz because of the malfunction of limiter stage. In order to avoid the meta-stability problem in the limiter and hence the failure of clock recovery in the CDR, the middle levels of multi-level signals at TX should be readjusted before signal transmission. In the PA at deadtime controller, level 3 and 4 should be set as far away as 121

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possible from the middle point between level 6 and level 0 such that, in the RX at motor side, the comparator of limiter has greater margin between the threshold voltage and level 3 or 4. 0 2 4 1 3 5 3 2 4 6 0 0 2 4 1 3 5 3 2 4 6 0 ~550mV pp 10ns 5ns (b) (a) ~510mV pp Figure 5-28. Waveform of demodulated signal (varying amplitude levels 0241353246) at BB output when the data rate of modulating signal is (a) 200Mbps and (b) 100Mbps with total 20dB attenuation between the PA output and LNA input RMS jitter 43.9ps RMS jitter 47.6ps (b) (a) Figure 5-29. Jitter histogram of (a) demodulated signal at BB out and (b) recovered clock at CDR output for a modulating signal at 400Mbps with total 20dB attenuation between the PA output and LNA input. 5.6 Conclusions The single-ended baseband amplifier from the previous implementation is updated to a differential structure to eliminate the oscillation problem of RX chain. The measurements of 122

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stand alone test structure indicate that under the normal V DD and bias condition, the oscillation problem has been eliminated. The gain of amplifier is 34dB. The 3dB bandwidth is 670MHz that satisfies the design target of 600MHz. The amplifier including the bias circuit consumes 3.3mW of power. The entire RX chain including an updated baseband amplifier at motor side is characterized with 2-level amplitude modulated signals. RX chain has IP 1dB of -45dBm and sensitivity of -45dBm for BER of 10 -12 and 400Mbps data rate. Full-duplex operations of TRX with an on-chip antenna are verified by comparing the BER performance of RX chain and RMS jitters of recovered clock for the cases with TX on and off. The BER degradation due to the TX on is less than a factor of 10. Especially, when the output signal is near the design target, the difference is almost negligible. The jitters of recovered clock increase by no more than ~1ps when TX is on. In addition, the full-duplex operation of TRX at motor side is observed by picking up signals from both TX and RX bands at the same time using an external horn antenna. This work has demonstrated that full-duplex operation of CMOS transceivers with an on-chip antenna is possible. Finally, the feasibility of the detecting multi-level CDMA signal is demonstrated using 7-level AM signals. Due to the major malfunction in the limiter with middle data levels, i.e. level 3 and 4, the jitter of recovered clock increases to ~48ps from ~2ps. In addition, the CDR recovers the clock at wrong frequency, and in the worst case, loses lock. Some possible solutions to this problem are suggested. 123

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CHAPTER 6 SUMMARY AND FUTURE WORK 6.1 Summary A fully integrated CDR based LO generation circuit which provides both 24-GHz LO signal for a TX and 400-MHz clock for a RX has been demonstrated in UMC 130-nm CMOS process. A VCO operation 60 times higher than the input data rate at 400Mbps by using a divider in the feedback loop enables generation of 24-GHz LO signal for TX and integration of an LC-VCO that utilizes an inductor with reasonable size and Q. Including the divider in the feedback loop provides additional degree of freedom for reducing the size of loop filter capacitors for integration. The jitter performance of recovered clock at 400MHz is the lowest among fully integrated CDRs with the similar data rate (~400Mbps) published in the literature. A fully integrated FDMA TX chain for motor side in the hybrid engine controller board is demonstrated using the UMC-130nm CMOS technology. The increased phase noise of LO generated by a CDR does not degrade the performance of ASK systems using a square laws detector in the receiver. It should also be possible to use a recovered clock from a CDR as an LO for a wide band width systems with other low order modulation schemes. The feasibility of establishing a wireless link using the transmitter within the controller board is also demonstrated. This indicates that a TX integrated with a RX incorporating a CDR can bypass the problem of having an external frequency reference. A wireless link demonstration on the board suggests the target communication range of 15cm should be possible. An entire RX chain including an updated single to differential baseband amplifier is characterized. More importantly, full-duplex operations of TRX for motor side with an on-chip antenna are demonstrated for the first time. Finally, the feasibility of detecting multiple level AM signal is also demonstrated. 124

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6.2 Future Work The following efforts that extend the work predicted in this dissertation should be considered for future efforts. (a) For successful link demonstration between TX at deadtime controller and RX at motor side, the RF gain of RX front end at motor side should be increased to improve its sensitivity. The RX chain should be demonstrated with a 3-bit 800-Msample/s ADC. The middle levels such as level 3 and 4 of multi-level signals at TX should be readjusted before transmission so as to avoid the meta-stability problem in the limiter that can cause the failure of clock recovery, and increase jitter. In the PA at the deadtime controller side, level 3 and 4 should be positioned to be away from the middle point between level 6 and level 0 so that, in the RX for the motor side, the comparator of limiter can have large amplitude margins between the threshold voltage and level 3 or 4. A wireless link that supports multiple amplitude modulation should be demonstrated. (c) Once the RX chain at deadtime controller is verified, a wireless link between TX at motor side and RX at deadtime controller side should be demonstrated. (b) In the IF generator, waveforms of IF signals at 800MHz and 1.2GHz violate 50% duty cycle. For this reason, the increased 2 nd harmonics of these IF signals mixed with LO signal create interfering signals that fall into the desired neighboring channels. Approaches to reduce the deviation should be incorporated. 125

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APPENDIX A CDR TEST STRUCTURE A block diagram of a CDR test structure which consists of a phase detector, a charge pump, a loop filter, a 5.84-GHz LC VCO, and a divide-by-16 block is shown in Figure A-1. This CDR test structure outputs both 365-MHz clock and 5.84-GHz LO signal. A loop filter can be fully integrated with a reasonable capacitance value. Since this CDR test structure was a prototype design, more than the necessary digital control bits (up to 7bits) are incorporated in the VCO to increase the likelihood of satisfying the frequency target. Digital tuning 7 Figure A-1. Block diagram of CDR test structure. A.1 Circuit Description of CDR Test Structure Much of the circuit topology is the same as the CDR circuit mentioned in section 3.2. The loop bandwidth of 500kHz, charge pump current of 70A, divide ratio of 16 and VCO gain of 300MHz/V are chosen. For the loop filter, two capacitors C Z C P and one resistor R Z are 324pF, 31pF and 3.1k respectively. The biggest capacitor C Z occupies 200m210m. The simulated phase margin of CDR loop is 55. 5.84GHz LC VCO Phase Detector R Z C Z C P Divider ( 16) 365Mbps PRBS Charge pump Data 365Mbs Retimed Data 365MHz 5.84GHz Recovered Clock Recovered Clock 126

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M1M2VCONT B0B1 B7 M3VCO Bias M5L3 Buffer VDDOUTN M4L2Buffer VDD OUTPVCO VDD L1 M1M2VCONT B0B1 B7 M3VCO Bias M5L3 Buffer VDDOUTN M5L3 Buffer VDDOUTN M4L2Buffer VDD OUTP M4L2Buffer VDD OUTPVCO VDD L1 Figure A-2. Schematic of the 5.84GHz LC VCO. Figure A-2 shows a circuit schematic of the 5.84GHz LC VCO, which consists of an LC-tank, a PMOS cross coupled pair, a pair of accumulation mode varactors for continuous fine tuning, a digitally tuned capacitor bank for discrete coarse tuning, an NMOS tail current source, and a pair of inductively loaded buffers. The capacitor bank supports 7-bit digital tuning to keep the VCO gain low for reduced phase noise while maintaining an adequate tuning range. To increase the inductor Q, L1 is drawn as a center tapped spiral inductor [40] using the top two copper layers shunted together. The total metal thickness is ~1.6m. The estimated series 127

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resistance of inductor is 2.3 The metal spacing, width, and number of turns are 2.9m, 4.8m, and 3, respectively. The inductance for L1 is 0.9nH, and the inductor including a polysilicon pattern ground shield [41], [42] occupies 100m100m. The simulated Q [43] of inductor is ~15 at 5.84GHz. The capacitor bank consists of seven parallel binary-scaled MOS varactors whose control voltages are connected to either V DD for C min or GND for C max The C max /C min is around 3. To implement a divide-by-16, four divide-by-2 circuits are cascaded in series. A.2 Measurement Results of CDR Test Structure The CDR has been fabricated in the UMC 130-nm logic CMOS technology with eight copper layers. Shown in Figure A-3 is a die photograph. The chip area without the bond pads is 0.88mm.67mm. This includes the area for a pair of inductor loaded buffers (0.11mm0.11mm) for the VCO measurements. The CDR has been measured on a PC board with the chip directly mounted on the board (chip-on-board) illustrated in Figure A-4. The size of PCB is 4.8cm by 4.8cm. Direct probe landing is performed to measure the LO at 5.84GHz. The recovered clock at 385MHz and the retimed data are both measured via SMA connectors. The measured CDR locking range is from 360.4 to 369Mpbs. Figure A-5 shows the VCO tuning range and corresponding VCO gain change for digital tuning bit 0000000. The measured VCO gain is ~300MHz/V which is the same as the design target of 300MHz/V around the control voltage of 0.4V. However, the gain decreases as the control voltage deviates from this point due to the saturation of varactor capacitance. The supply voltage is 1.2V. The VCO draws 12mA. The power consumption of CDR excluding that of buffers for driving an external load is ~16mW. 128

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Figure A-3. Die photograph of 5.84GHz CDR. Figure A-4. Photograph of CDR testing printed circuit board. 4.8cm 4.8cm CDR chip GSSG Probe Probe Landing Direction 129

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5.655.75.755.85.855.95.9500.20.40.60.811.2VCO Control Voltage (V)VCO Freuqency (GHz)050100150200250300350VCO Gain (MHz/V ) Figure A-5. Plot of VCO tuning range and gain at digital bits 0000000. Figure A-6 shows the measured waveform of recovered clock at 365MHz and jitter histogram in response to a PRBS 2 31 -1 input, respectively. The measured RMS and peak to peak jitters are 8.9ps (rms) and 76.9ps (p-p), respectively, which are 0.32% and 2.8% of a clock period. The BER performance has been measured using an Agilent N4903 J-BERT. Since a BER measurement must be statistically valid, a CDR should be tested long enough to have a certain confidence level in its BER results [73]. BER testing time must be at least 23 hour 37 min if the desired BER is 10 -13 and desired confidence level is 95% when input data rate is 356-Mbps. During BER measurements, 3.154 13 bits were checked for 24 hours. The measured BER is less than 10 -13 Figure A-7 shows the spectrum of the recovered clock at 5.84GHz with 365-Mbps PRBS 2 31 -1 input signal when the CDR is locked. Since the CDR loop bandwidth is designed to be 500-kHz, the noise shaping within the loop bandwidth can be observed in the spectrum. The phase noise performance at the offset frequency of 60kHz, 1MHz, and 10MHz are measured with RBS 130

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2 7 -1, 2 23 -1, 2 31 -1 and clock input at 182.5-MHz. Figure A-8 shows the phase noise plot for PRBS 2 31 -1. The in-band phase noise at 60-kHz offset is -74.5dBc/Hz. The phase noise at 1-MHz offset is -94.1dBc/Hz and the out-of-band phase noise at 10-MHz offset is -113.0dBc/Hz. The measured CDR characteristics are summarized in Table A-1. This work has demonstrated the LO generation circuit can be incorporated with a clock and data recovery circuit. Figure A-6. Plot of recovered clock at 365MHz and jitter histogram for a PRBS 2 31 -1. Figure A-7. Spectrum of recovered clock at 5.84GHz for a PRBS 2 31 -1 input signal. 131

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Figure A-8. Plot of phase noise of recovered clock at 5.84GHz for a PRBS 2 31 -1 input signal. Table A-1. Summary of measured CDR performance Technology UMC 130-nm Input data rate 365-Mbps CDR lock range 360.4-Mbps ~ 369-Mpbs VCO tuning range 5.7-GHz ~ 7.12-GHz 5.84-GHz clock Phase noise (dBc/Hz) PRBS 2 7 -1 PRBS 2 23 -1 PRBS 2 31 -1 Clock input @182.5MHz VCO @ 60-KHz offset -74.6 -73.0 -74.5 -84 -63.4 @ 1-MHz offset -100.6 -93.3 -94.1 -102 -104.7 @ 10-MHz offset -118.3 -113.1 -113.0 -121 -126.3 365-MHz clock jitter (ps) RMS rising Peak to Peak with PRBS 2 7 -1 6.1 45.8 with PRBS 2 23 -1 8.8 66.7 with PRBS 2 31 -1 8.9 76.9 with clock input @182.5MHz 4.3 41.1 BER with 95% confidence for PRBS 2 31 -1 Less than 10 -13 Chip size (w/o pad) 0.88.67 mm 2 PD CP VCO DIV(simulation) Power (mW) 0.5 0.25 14.4 1.2 132

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APPENDIX B SPECTRUM OF TX OUTPUT WITH AN EXTERNAL IF SIGNAL SOURCE Figure B-1 shows the measurement setup with an external IF frequency source. The antenna was cut off to eliminate the additional measurement loss and mismatch. The TX power is measured at the duplexer output. Since the sinusoidal IF signals produced by an external signal generator is squared with 50% duty cycle after a few inverter stages, when the IF signal is mixed with LO signal, the contribution of even order harmonics within the TX band is negligible and hence only odd harmonics are taken into consideration. DuplexerPA Laser cutting Figure B-1. Measurement setup for the transmitter at motor side using an external IF source. Table B-1. Summary of TX output power level at motor side with an external IF signal source Motor 1 2 3 4 5 6 7 Channel (GHz) 24.4 24.8 25.2 25.5 26.0 26.4 27.0 Power (dBm) -8.5 -8.9 -5.4 -6.6 -5.1 -4.7 -5.6 Cable & balun loss (dB) 6.0 6.4 5.9 6.4 6.3 6.8 7.1 Power 1 (dBm) -2.5 -2.5 0.5 -0.2 1.2 2.1 1.5 *Power 1 : output power after de-embedding measurement cable and balun loss. With an external IF signal source, the generation of undesired interferers from motor and their influence on the neighboring channels well agree with the diagram in Figure 4-11. Table B-1 summarizes the TX output power levels for seven motor channels. In this table, power 1 specifies TX output power after de-embedding the cable and balun losses. Monitoring point of the differential TX output power CDR ATTEN& MUX & IF GEN MIX 400Mbps PRBS 231-1 DuplexerPA Laser cutting Ext. Frequency source (0. 4 GH z ~ 3GH z ) Monitoring point of the differential TX output power CDR ATTEN& MUX & IF GEN MIX 400Mbps PRBS 231-1 Ext. Frequency source (0. 4 GH z ~ 3GH z ) 133

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A spectrum of TX motor 1 at the duplexer output with antenna cut off is shown Figure B-2. The peak power level at 24.4GHz is -2.5dBm (-8.53dBm before de-embedding the balun and cable losses). Since the 3rd and 5th order harmonics of 400MHz signals fall into motor 3 (25.2GHz) and motor 5 (26GHz) channels, harmonic control is once again important for reducing the interference. The 3rd and 5th harmonics from 400MHz are ~-20dBm at 25.2GHz and ~-32dBm at 26GHz, respectively. Proper attenuator settings can further minimize the harmonic contribution, though this will reduce the desired output power level. Figure B-3 shows a zoomed in spectrum of the TX motor 1. (25.2GHz) 3rdharmonic of 400MHz(26GHz) 5thharmonic of 400MHz1stharmonic of 400MHz (25.2GHz) 3rdharmonic of 400MHz(26GHz) 5thharmonic of 400MHz1stharmonic of 400MHz Figure B-2. Spectrum of TX motor 1 driven with an external IF signal source. Figure B-3. Zoomed-in spectrum of TX motor 1 driven with an external IF signal source. 134

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Figure B-4 shows a spectrum of motor 7 at the duplexer output. The peak power level at 27GHz is 1.5dBm (-5.6dBm before de-embedding the balun and cable losses). The 2nd order harmonic from 3GHz mixed with 24GHz is -31dBm at 30GHz, which is outside of the TX bands. Figure B-5 shows a zoomed in spectrum of the TX motor 7. (30GHz) 2ndharmonic of 3.0 GHz (30GHz) 2ndharmonic of 3.0 GHz Figure B-4. Spectrum of TX motor 7 driven with an external IF signal source. Figure B-5. Zoomed-in spectrum of TX motor 7 driven with an external IF signal source. 135

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LIST OF REFERENCES [1] D. Hermance, and S. Sasaki, Hybrid Electric Vehicles Take to The Streets, IEEE Spectrum, Vol. 35, Issue 11, pp. 48-52, Nov. 1998. [2] Floyd A Wyczalek, Market Mature 1998 Hybrid Electric Vehicles, IEEE Aerospace and Electronic Systems Magazine, Vol. 14, Issue 3, pp. 41-44, March 1999. [3] A kira Kawahashi, A New-Generation Hybrid Electric Vehicle and Its Supporting Power Semiconductor Devices, IEEE Power Semiconductor Devices and ICs Symp. Dig. Tech. Papers, pp. 23-29, 24-27 May 2004. [4] T. P. Bohn, R.D. Lorenz, and E. R. Olson, Measurement of In-Situ Currents in a Hybrid Electric Vehicle Integrated Power Module Using Giant Magnetoresistive Sensors, IEEE Power Electronics in Transportation, pp. 55-59, 2004. [5] N. Kanekawa, Y. Kojima, S. Yukutake, M. Nemoto, T. Iwasaki, K. Takami, Y. Tekeuchi, A. Yano, and Y. Shima, An analog front-end LSI with on-chip isolator for V.90 56 kbps modems, IEEE CICC Dig. Tech. Papers, pp. 327-330, May 2000. [6] Y. Kojima, M. Nemoto, S. Yukutake, T. Iwasaki, M. Amishiro, N. Kanekawa, A. Watanabe, Y. Takeuchi, and N. Akiyama, .3 kVac 100 MHz multi-channel monolithic isolator IC, The 12 th Int. Symp. Power Semiconductor Devices and ICs, 2000. Proc., pp. 309-312, May 2000. [7] N. Akiyama, Y. Kojima, M. Nemoto, S. Yukutake, T. Iwasaki, M. Amishiro, N. Kanekawa, A. Watanabe, and Y. Takeuchi, A hi-voltage monolithic isolator for a communication network interface, IEEE Trans. Electron Devices, Volume 49, Issue 5, pp. 895-901, May 2002. [8] Hsinta Wu, Ph.D. Dissertation Transmitter for wireless inter-chip data communications University of Florida, Gainesville, FL, 2009. [9] K. Kim, H. Yoon, and K. K. O, On-chip wireless interconnection with integrated antennas, Tech. Digest of IEDM, pp. 485-488, San Francisco, 2000. [10] K. K. O, K. Kim, B. Floyd, J. Mehta, H. Yoon, C.-M. Hung, D. Bravo, T. Dickson, X. Guo, R. Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, D.J. Yang, J. Bohorquez, L. Gao, A. Sugavanam, J.-J. Lin, J. Chen, F. Martin, and J. Brewer, Wireless communication using integrated antennas, in Proc. Int. Interconnect Technol. Conf., San Francisco, CA, Jun. 2003, pp. 111-113. [11] Y. Su, J.-J. Lin, and K. K. O, A 20-GHz CMOS RF down-converter with an on-chip antenna, in 2005 IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 270-271. 136

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[12] C. Cao, Y. Ding, X. Yang, J.-J. Lin, A. K. Verma, J. Lin, F. Martin, and K. K. O, A 24-GHz transmitter with an on-chip antenna in 130-nm CMOS, in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2006, pp. 184-185. [13] T. Rappaport, Wireless Communications, Principles and Practice, Second edition, Prentice Hall, 2002. [14] Swaminathan Sankaran, Ph.D Dissertation Recievers Using Schottky Barrier Diodes in CMOS, University of Florida, Gainesville, FL, 2008. [15] Jau-Jr Lin, Ph.D Dissertation On-Chip Antennas for Short-Range Wireless Communications, University of Florida, Gainesville, FL, 2007. [16] U. L. Rohde, J. Whitaker and T. T. N. Bucher, Communication Receivers: Principles and Design, NY: McGraw Hill, 1996. [17] C. Hogge, A self-correcting clock recovery circuit, J. Lightwave Technol., vol. LT-3, pp. 1312-1314, Dec. 1985. [18] B. Sklar, Digital Communications, Fundamentals and Applications, Prentice Hall, 1987. [19] B Razavi, Design of Integrated Circuits for Optical Communications, McGRAW-HILL, 2003. [20] J. Redd, C.Lyon, Spectral Content of NRZ test patterns, Maxim Integrated Circuits, Sep. 2004. [21] B. Razavi, "Challenges in the Design of High-Speed Clock and Data Recovery Circuits," IEEE Communication Magazine, volume 40, pp. 94-101, August 2002. [22] D. Mijuskovic, M. Bayer, T. Chomicz, N. Garg, F. James, P. McEntarfer, J. Porter, Cell-based fully integrated CMOS frequency synthesizer, IEEE Journal of Solid-Stage Circuits, volume 29, Issue 3, pp. 271-279, March 1994. [23] F. M. Gardner, Phaselock Techniques, third edition, Wiley, Jul. 2005. [24] M. H. Perrott, High Speed Communication Circuits and Systems Lecture 15, Integer-N Frequency Synthesizers, MIT course, Spring 2002. [25] Michael H. Perrott, PLL design using the PLL design assistant program, pp.31-32, Jul. 2008, website: www. cppsim.com [26] C. M. Hung, Ph. D Dissertation Investigation of a multi-GHz single-chip CMOS PLL frequency synthesizer for wireless applications University of Florida, Gainesville, FL, 2000. 137

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[27] J. J. Young, Jitter Considerations in High Bit Rate Digital Video Signals, IEEE Transactions on Broadcasting, vol. 40, no. 2, Jun. 1994. [28] L. M. DeVito, Unusual Clcok Recovery Architecture Ameliorates SONET Jitter Tradeoff, presented at Univ of Cal., Berkeley, Feb. 2003. [29] D. Dalton, K. Chai, M. Ferriss, D. Hitchox, P. Murray, S. Selvanayagam, P. Shepherd, L. Devito, A 12.5 Mb/s to 2.7 Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback, IEEE J. Solid-State Circuits, vol. 40, pp. 2713, Dec. 2005. [30] R-J Yang, K-H Chao, S-C Hwu, C-K Liang, S-I Liu, A 155.52 Mbps-3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit, IEEE J. Solid-Stage Circuits, vol. 41, no. 6, pp. 1380-1390, June 2006. [31] R-J Yang, K-H Chao, S-I Liu, A 200-Mbps~2-Gbps Continuous-Rate Clock-and-Data-Recovery Circuit, IEEE Trans. Circuits and systems I, vol. 53, Issue. 4, pp. 842-847, Apr. 2006. [32] P. Larsson, A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability,, IEEE J. Solid-State Circuits, vol. 34, pp. 1951-1960, Dec. 1999. [33] J. Scheytt G. Hanke and U. Langmann A 0.155, 0.622 and 2.488 Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems, IEEE J. Solid-State Circuits, vol. 34, pp. 1935-1943, Dec. 1999. [34] L. DeVito, et al., A 52 MHz and 155 MHz clock recovery PLL, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers San Francisco, CA, Feb. 1991, pp. 142-143. [35] Craninckx and M. Steyaert, A fully integrated CMOS DCS-1800 frequency synthesizer, IEEE J. Solid-State Circuits, vol. 33, pp. 2054-2065, Dec. 1998. [36] C. M. Hung, Y. C. Ho, I. C. Wu, and K. K. O, High-Q capacitors implemented in a CMOS process for low-power wireless applications, IEEE Trans. Microw. Theory Tech., vol. 46, no. 5, pp. 505-511, May 1998. [37] Floyd M. Gardner, Charge pump phase locked loops, IEEE Transactions on Communications Electronics, pp. 1849-1858, Nov. 1980. [38] J. Kim, J. K. Kim, B. J. Lee, N. Kim, D. K. Jeong, W. Kim, A 20-GHz Phase-Locked Loop for 40-Gb/s Serializing Transmitter in 0.13-m CMOS, IEEE Journal of Solid-State Circuits, volume 41, pp899-908, April 2006. [39] T. Soorapanth, C. P. Yue, D. K. Shaeffer, T. I. Lee, T.I, and S. S. Wong, Analysis and optimization of accumulation-mode varactor for RF ICs, Symp. VLSI Circuits Dig. Tech. Papers, pp 32 33, June 1998. 138

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[40] J.-O. Plouchart, H. Ainspan, M. Soyuer, and A. Ruehli, A fully monolithic SiGe differential VCO for 5GHz wireless applications, in Proc. IEEE RFIC Symp., Boston, MA, June 2000, pp. 57-60. [41] C. P. Yue and S. S. Wong, On-chip spiral inductors with patterned ground shields for Si-based RFICs, IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 743-752, Jun. 1998. [42] S.-M. Yim and K. K. O, The effects of a ground shield on the characteristics and performance of spiral inductors, IEEE J. Solid-State Circuits, vol. 37, no.2, pp. 237-244, Feb. 2002. [43] K. K. O, Estimation methods for quality factors of inductors fabricated in silicon integrated circuit process technologies, IEEE J. Solid-Stage Circuits, vol. 37, no. 8, pp. 1249-1252, Aug. 1998. [44] Changhua Cao, Ph.D. Dissertation A 24-GHz Fully-Integrated CMOS Transmitter with On-chip Antenna University of Florida, Gainesville, FL, 2006. [45] E. Hegazi, H. Sjoland, A. Abidi, A filtering technique to lower oscillator phase noise, IEEE ISSCC Digest of Technical Papers, pp. 364-365, Feb. 2001. [46] B. A. Floyd and K. K. O, SOI and bulk CMOS frequency divider operating above 15GHz, IEE Electronics Letter, vol. 37, n. 10, pp. 617-618, May 2001. [47] D.-J. Yang, and K. K. O, A 14-GHz 256/257 Dual-Modulus Prescaler With Secndary Feedback and Its Application to a Monolithic CMOS 10.4-GHz Phase-Locked Loop, IEEE Trans. Microwave Theory Tech., pp. 461-468, Feb. 2004. [48] C. Cao and K. K. O, A power efficient 26GHz 32:1 static frequency divider in 130-nm bulk CMOS, IEEE Microw. Wireless Compon. Lett., vol. 15, pp. 721, Nov. 2005. [49] Y. Yamauchi, O. Nakajima, K. Nagata and M. Hirayama, A 15-GHz Monolithic Two-Modulus Prescaler, IEEE J. Solid-Stage Circuits, vol. 26, no. 8, pp. 1632-1636, Nov. 1991. [50] K. Ware, H.-S. Lee, C. G. Sodini, A 200-MHz CMOS phase-locked loop with dual phase detectors, IEEE Journal of Solid-State Circuits, vol. 24, no. 6, pp. 1560-1568, Dec. 1989. [51] J. D. H. Alexander, Clock Recovery from Random Binary Data, Elect. Lett., vol. 11, pp. 541-42, Oct. 1975. [52] J M. Rabaey, A Chandrakasan, and B. Nikolic, Digital Integrated Circuits A design perspective, second edition, Printice Hall, 2003. [53] C. Lam, B. Razavi, A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-m CMOS technology, IEEE Journal of Solid-State Circuits, Volume 35, Issue 5, pp. 788-794 May 2000. 139

PAGE 140

[54] C. M. Hung, K. K. O, A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop, IEEE Journal of Solid-State Circuits, Vol. 37, no. 4, pp. 521-525. Apr. 2002. [55] H. K. Lee, J. T. Ahn, M.-Y. Jeon, K. H. Kim, D. S. Lim, and C.-H. Lee, All-optical clock recovery from NRZ data of 10 Gb/s, IEEE Photon. Technol. Lett., vol. 11, pp. 730-732, June 1999. [56] T. Lee and J. Bulzacchelli, A 155-MHz clock recovery delayand phase-locked loop, IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1736-1746, Dec. 1992. [57] Y. Ding and K. K. O, A 21-GHz 8-modulus prescaler and a 20-GHz phase-locked loop fabricated in 130-nm CMOS, IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1240-1249, Jun. 2007. [58] D. Banerjee, PLL Performance, Simulation and Design, 4 th edition. 2006. [59] B. P. Lathi, Modern Digital and Analog Communication Systems, third edition, Oxford, 1998. [60] A. V. Oppenheim, A. S. Willsky, S. H. Nawab, Signal & Systems, second edition, Prentice Hall, Aug. 1996. [61] S. Sankaran, K. Oh, H. Wu, and K. K. O, Wireless Interconnection within a Hybrid Engine Controller Board Proc. CICC, pp.149-152, Sep. 2008. [62] Hsin-Ta Wu, Ruonan Han, Lerdsitsomboon W, Changhua Cao, and Kenneth K. O, Multi-Level Amplitude Modulation of a 16.8-GHz Class-E Power Amplifier with Negative Resistance Enhanced Power Gain for 400-Mbps Data Transmission, IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1072-1079, May. 2010. [63] N. H. E. Weste, D. Harris, CMOS VLSI Design, A Circuit and Systems Perspective, third edition, Addison Wesley, May 2004. [64] S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, second edition, McGrawHill, Jul. 2004. [65] S. H. Unger, Double-edge-triggered flip-flops, IEEE Trans. Computers, vol. C-30, no. 6, pp. 447-451, June 1981. [66] H.-D. Wohlmuth, and D. Kehrer, A 15 GHz 256/257 dual-modulus prescaler in 120 nm CMOS, European Solid-State Circuits Conference, pp. 77 80, Sep. 2003. [67] N. O. Sokal, and A. D. Sokal, Class E-A New Class of High Efficiency Tuned Single-Ended Switching Power Amplifier, IEEE J. Solid-State Circuits, vol. 10, no. 3, pp. 168-176, Jun. 1975. 140

PAGE 141

[68] C. Cao, H. Xu, Y. Su, and K. K. O, An 18-GHz, 10.9-dBm Fully-Integrated Power Amplifier with 23.5% PAE in 130-nm CMOS, Eur. Solid-State Circuit Conf. Dig. Tech. Papers, pp. 137-140, Sep. 2005. [69] H. Johnson, M. Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall, 1993. [70] B. A. Floyd, K. Kim, and K. K. O, Wireless interconnection in a CMOS IC with integrated antennas, in 2000 IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2000, pp. 328-329. [71] B. A. Floyd, C.-M. Hung, and K. K. O, 15-GHz Wireless interconnect implemented in a 0.18-m CMOS technology using integrated transmitters, receivers, and antennas, IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002. [72] F. Touati and M. Pons, On-chip integration of dipole antenna and VCO using standard BiCMOS technology for 10 GHz applications, in Proc. 29 th Eur. Solid-State Circuits Conf. (ESSCIRC 2004), Estoril, Portugal, Oct. 2003, pp. 493-496. [73] Agilent Technologies, Agilent J-Bert N4903 High-Performance Serial Bert User Guide, Jun. 2007. 141

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BIOGRAPHICAL SKETCH Kyujin Oh was born in Busan, South Korea, in 1974. He received the B.S. degree in electrical engineering from Yonsei University, Seoul, South Korea in 2001 and M.S. degree in electrical engineering from University of Southern California, Los Angeles in 2004. Currently, he is a Ph.D. candidate in the Department of Electrical and Computer Engineering at the University of Florida, Gainesville and has been with the Silicon Microwave Integrated Circuits and Systems (SIMICS) research group since 2006. During the summer of 2007, he interned at Samsung Electronics where he was involved in VCO and divider design of a phase locked loop (PLL) for 4G wireless communication (LTE). His current research interests are in analysis and design of RF circuits, wireless transceiver, and high-speed analog circuits in CMOS. 142