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Rf/microwave/millimeter Wave Embedded Detectors

Permanent Link: http://ufdc.ufl.edu/UFE0041488/00001

Material Information

Title: Rf/microwave/millimeter Wave Embedded Detectors
Physical Description: 1 online resource (145 p.)
Language: english
Creator: Rami, Said
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2010

Subjects

Subjects / Keywords: amplitude, bist, dft, envelope, peak, rf, rms, s
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Testing millimeter wave circuits can be a challenging undertaking. Expenditures required for vendors test solutions at those frequencies are costly. Moreover, as vertical integration is gaining momentum, the ability to determine functionality of every layer is crucial. Circuits operating at millimeter wave frequencies are especially susceptible to process variations. Yield is significantly affected if any of the layers is not functional to specifications. To mitigate these effects, a slew of strategies need to be implemented. Process variation monitoring circuits should be included. Non-invasive Built-In-Self-Test (BIST) circuitry is necessary to enable self-repair, self-healing of mmWave circuitry. All these factors call for innovation of simple circuits capable of performing alternate RF tests. This dissertation discusses simple topologies of amplitude detectors suitable for millimeter wave BIST. The detectors can be implemented in different technologies; they occupy a small area, have low power consumption, a wide operating frequency range, negligible loading effects, and a suitable dynamic range. Detectors act as virtual probes that convert RF amplitude information into DC or low frequencies. The detectors response is discussed over multiple operating conditions with special attention to issues relevant to BIST applications. A differential detector that measures the pure differential component of a mixed mode signal is also presented. This detector is further enhanced to measure both components of mixed mode signals including common mode. System applications are presented to illustrate the advantages of each detector topology reported in this dissertation. Finally, this dissertation concludes with a summary and proposed future work section.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Said Rami.
Thesis: Thesis (Ph.D.)--University of Florida, 2010.
Local: Adviser: Eisenstadt, William R.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2011-04-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2010
System ID: UFE0041488:00001

Permanent Link: http://ufdc.ufl.edu/UFE0041488/00001

Material Information

Title: Rf/microwave/millimeter Wave Embedded Detectors
Physical Description: 1 online resource (145 p.)
Language: english
Creator: Rami, Said
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2010

Subjects

Subjects / Keywords: amplitude, bist, dft, envelope, peak, rf, rms, s
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Testing millimeter wave circuits can be a challenging undertaking. Expenditures required for vendors test solutions at those frequencies are costly. Moreover, as vertical integration is gaining momentum, the ability to determine functionality of every layer is crucial. Circuits operating at millimeter wave frequencies are especially susceptible to process variations. Yield is significantly affected if any of the layers is not functional to specifications. To mitigate these effects, a slew of strategies need to be implemented. Process variation monitoring circuits should be included. Non-invasive Built-In-Self-Test (BIST) circuitry is necessary to enable self-repair, self-healing of mmWave circuitry. All these factors call for innovation of simple circuits capable of performing alternate RF tests. This dissertation discusses simple topologies of amplitude detectors suitable for millimeter wave BIST. The detectors can be implemented in different technologies; they occupy a small area, have low power consumption, a wide operating frequency range, negligible loading effects, and a suitable dynamic range. Detectors act as virtual probes that convert RF amplitude information into DC or low frequencies. The detectors response is discussed over multiple operating conditions with special attention to issues relevant to BIST applications. A differential detector that measures the pure differential component of a mixed mode signal is also presented. This detector is further enhanced to measure both components of mixed mode signals including common mode. System applications are presented to illustrate the advantages of each detector topology reported in this dissertation. Finally, this dissertation concludes with a summary and proposed future work section.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Said Rami.
Thesis: Thesis (Ph.D.)--University of Florida, 2010.
Local: Adviser: Eisenstadt, William R.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2011-04-30

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2010
System ID: UFE0041488:00001


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1 RF/MICROWAVE/MILLIMETER WAVE EMBEDDED DETECTORS By SAID RAMI A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2010

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2 2010 Said Rami

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3 ACKNOWLEDGMENTS I am highly indebted to the many people that directly or indirectly taught, guided, counseled, helped, and mentored me in my journey toward the completion of this dissertation. I am highly appreciative of my advisor, Prof. William Eisenstadt, who provided me with the opportunity to pursue my Ph.D. education with constant support and guidance He was behind most of the defining moments in my time at University of Florida since my involvement with his group as an undergraduate student. I simply acknowledge him as the person who had the strongest impact on me in my training as an electrical engineer I t was through him that I had the opportunity to meet many people such as Bob Ste ngel from Motorola and Andrea Paganini from IBM who inspired me and introduced me the industrial world. I am also thankful to the members of my committee. Prof. Robert Fox was a t a key junction in my educational path as I took my first senior level underg raduate course with him. His teaching methodologies and pertinent questions influenced me and directed my research interest. I am thankful to Prof. Jenshan Lin who inculcated in me a steadfast approach to problem solving while always exuding a support ive a ttitude since I was his teaching assistant as well as his assistance in providing access to the test equipments. I am also grateful to Prof. Gloria Wiens for setting aside her valuable time and her keen interest during her involvement in my research work. I thank all my colleagues and acquaintances in the fifth floor of the new engineering building First and foremost, I am highly indebted to the previous generation of students who had the patience to disseminate all their knowledge without restrictions I would like to thank my peers who made this journey enjoyable because the

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4 immensurable daily feedback and technical interactions we shared. It goes without saying that the future generation also play ed a significant role because of their inquisitive and s timulating discussions. I cannot put into words my gratitude to my parents, sisters, and lovely wife f or their unconditional support, sacrifice and patience as was absent as a son, brother, and husband more than I should have.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................. 3 LIST OF TABLES ............................................................................................................ 7 LIST OF FIGURES .......................................................................................................... 8 ABSTRACT ................................................................................................................... 12 CHAPTER 1 INTRODUCTION .................................................................................................... 14 Challenges in High Frequency Test ........................................................................ 14 Proposed Solution .................................................................................................. 17 Organization of the Dissertation .............................................................................. 22 2 MOSFET AMPLITUDE DETECTOR ....................................................................... 25 Introduction ............................................................................................................. 25 Saturation Region ................................................................................................... 29 Subthreshold Region .............................................................................................. 31 Body Effect Summary ............................................................................................. 33 Triode Regio n ......................................................................................................... 35 Summary ................................................................................................................ 35 3 DETECTORS RESPONSE .................................................................................... 37 RMS Detector ......................................................................................................... 37 Subthreshold Region ........................................................................................ 3 7 Saturation Region ............................................................................................. 39 Envelope Detector .................................................................................................. 42 Settling Time ........................................................................................................... 46 Frequency Response .............................................................................................. 49 Detectors Accuracy ................................................................................................ 52 Temperature Variations .................................................................................... 53 First order calibration ................................................................................. 53 Ad hoc solutions ......................................................................................... 59 Temperature sens or ................................................................................... 60 Process Variations ........................................................................................... 61 Calibration ........................................................................................................ 65 DC offset .................................................................................................... 65 Reference detector .................................................................................... 66 Statistical methods ..................................................................................... 67 Yield impact ............................................................................................... 68

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6 Dynamic Range ...................................................................................................... 69 Summary ................................................................................................................ 70 4 ALTERNATE DETECTOR TOPOLOGIES .............................................................. 71 MOSFET Detector Subthreshold Crossover Region ............................................... 71 Introduction ....................................................................................................... 71 Type II Detector ................................................................................................ 71 Type III Detector ............................................................................................... 73 Comparison Between the Three Types of Detectors ........................................ 75 Type III Detector in the Saturation Region .............................................................. 77 Multiple Regions Detector ....................................................................................... 83 5 MIXED MODE DETECTION ................................................................................... 90 Introduction ............................................................................................................. 90 Key Details for Desi gn of Differential Detectors ...................................................... 95 Mixed Mode Detectors ............................................................................................ 99 Calibration ............................................................................................................. 107 6 SYSTEM APPLICATIONS .................................................................................... 111 Introduction ........................................................................................................... 111 LNA Example ........................................................................................................ 111 Multi port Reflectometers ...................................................................................... 119 Introduction ..................................................................................................... 119 Compact Multi Port Reflectometers ................................................................ 122 7 SUMMARY AND SUGGESTIONS FOR FUTURE WORK .................................... 129 Summary .............................................................................................................. 129 Suggestions for Future Work ................................................................................ 130 APPENDIX ONE PORT CALIBRATION .................................................................................. 132 LIST OF REFERENCES ............................................................................................. 138 BIOGRAPHICAL SKETCH .......................................................................................... 145

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7 LIST OF TABLES Table page 2 1 Summary of RF to DC conversion equations ..................................................... 34 3 1 Monte Carlo simulations of different normalized transistor sizes ........................ 63 3 2 Comparing saturation and s ubthreshold d etection ............................................. 70 4 1 Value of V S1S2 /nV T for the three types of detectors ........................................ 75 4 2 Trade off of each operating region ..................................................................... 89 6 1 Maximum gain estimated by the detectors within .5dB accuracy ...................... 116 6 2 Maximum gain estimated by the typeIII detectors within .5dB accuracy ........... 117 6 3 Comparing ideal and estimated reflection coefficients ...................................... 124

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8 LIST OF FIGURES Figure page 1 1 ITRS prediction of multi site testing required for RF products ............................ 15 1 2 Complicated devices under test .......................................................................... 15 1 3 Automatic Test Equipment (ATE). Courtesy of LTX ........................................... 16 1 4 Architecture of signal generation for onchip onboard tester for mult i sites ....... 19 1 5 Alternate test architecture Tester on chip on board and embedded BIST ....... 20 1 6 Alternate test architecture Tester on chip on probe for characterization test ... 21 2 1 Stages in amplitude detection ............................................................................. 25 2 2 Meyers detector MOSFET equivalent ................................................................ 26 2 3 Measurement of MOSFET detector .................................................................... 28 2 4 Detector's response in saturation and subthreshold ........................................... 31 2 5 Measurement results in different operating regions ............................................ 36 3 1 Relative error of the detectors output to various waveform shapes ................... 38 3 2 Relative error of the detectors output to various waveform shapes ................... 40 3 3 AM modulated signal to the left. Output of the detector to the right .................... 44 3 4 Measurement of the detectors output when input is modulated ......................... 45 3 5 Oscilloscope capture of detector's response to a triangular AM input ................ 45 3 6 Discharge and charge paths ............................................................................... 47 3 7 Charging rate as V ov is swept ............................................................................ 49 3 8 Loading effects of the detector on the DUT ........................................................ 51 3 9 Detectors output over frequency ........................................................................ 52 3 10 Loss to a DUT caused by the detectors loading effects ..................................... 52 3 11 Detector using resistor ........................................................................................ 54 3 12 Detector using feedback to compensate for temperature variations ................... 55

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9 3 13 Subthreshold response vs. temperature ............................................................. 57 3 14 Saturation response vs. temperature .................................................................. 57 3 15 Detectors response vs. temperature .................................................................. 58 3 16 Temperature coefficient of the detectors response as function of the overdrive voltage ................................................................................................ 59 3 17 Variations of detectors response in the subthreshold region .............................. 64 3 18 Variations of detectors response in the saturation region ................................... 65 3 19 Monte Carlo in the saturation region considering only intradie variations .......... 66 4 1 Type II MOS detector ......................................................................................... 72 4 2 Type III MOS detector ........................................................................................ 73 4 3 Error of approximated detector's output relative to the theoretical value ............ 76 4 4 (a) Diode used for RMS detection, (b) Diode stack with increased RMS dynamic range .................................................................................................... 78 4 5 Detector using resistor ........................................................................................ 78 4 6 Normalized detection slope vs. input level .......................................................... 80 4 7 Monte Carlo simulation for different types of detectors in the saturation regi on. ................................................................................................................ 82 4 8 Subthreshold response vs. triode response ....................................................... 84 4 9 New detector multiple regions detector ........................................................... 85 4 10 Power sweep of the RF input level for the Meyer and new detector in triode ..... 85 4 11 Simulation results of the multipleregions detectors response ........................... 87 4 12 Measurement of the detector in logarithmic scale .............................................. 88 5 1 Conventional measurement method for differential signals ................................ 90 5 2 Detector using a differential pair ......................................................................... 91 5 3 Differential diode detector ................................................................................... 92 5 4 Bipolar differential detector ................................................................................. 93

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10 5 5 Balanced differential detector ............................................................................. 94 5 6 Differential detectors response to pure differential and pure common mode stimulus respectively .......................................................................................... 96 5 7 Measurement r esults of the B JT b alanced differential detector. ......................... 98 5 8 Detectors dependence on the inputs amplitude ................................................ 99 5 9 Mixed mode detector ........................................................................................ 100 5 10 Simplified diagram of mixedmode detector ..................................................... 100 5 11 Differential response to mixedmode stimulus .................................................. 102 5 12 Commonmode response to mixedmode stimulus .......................................... 102 5 13 Picture of mixedmode detector ........................................................................ 105 5 14 Measurement of differential DC response. ....................................................... 106 5 15 Measurement of commonmode DC response ................................................. 106 6 1 Detectors for measuring gain and compression of an LNA .............................. 112 6 2 Actual gain compared to different methods used to estimate the gain ............. 114 6 3 Error between ideal gain and gain estimated from detectors that are biased at different overdrive voltages ........................................................................... 116 6 4 Error between ideal gain and estimated gain from type III detectors ................ 117 6 5 Error between ideal gain and estimated gain from the multipleregions detectors ........................................................................................................... 118 6 6 Vector network analyzer port ............................................................................ 119 6 7 Six port reflectometer port ................................................................................ 120 6 8 Phase shifter ..................................................................................................... 121 6 9 Wheatstone bridge ........................................................................................... 121 6 10 Wheatstone bridge for measurement of S parameters magnitude .................. 123 6 11 Smith chart showing ideal and estimated reflections coefficients ..................... 124 6 12 Circuit that measures S parameters' magnitude and absolute value of phase 125

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11 6 13 Compact six port reflectometer ......................................................................... 125 6 14 Graphical method to measure the reflection coefficient .................................... 127 6 15 Smith chart showing reflection coefficients measured by the compact SPR .... 128 A 1 Uncalibrated measurement and simulation results ........................................... 132 A 2 Forward and reverse waves at different points in the measurement setup ....... 133 A 3 Hypothetical error adapter network ................................................................... 134

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12 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy RF/MICROWAVE/MILLIMETER WAVE EMBEDDED DETECTORS By Said Rami May 2010 Chair: Wil liam R. Eisenstadt Major: Electrical and Computer Engineering Testing millimeter wave circuits can be a challenging undertaking. Expenditures required for vendors test solutions at those frequencies are costly. Moreover, as vertical integration is gaining momentum, the ability to determine functionality of every layer is crucial. Circuits operating at millimeter wave frequencies are especially susceptible to process variations. Yield is significantly affected if any of the layers is not functional to spec ifications. To mitigate these effects, a slew of strategies need to be implemented. Process variation monitoring c ircuits should be included. Noninvasive Built In Self Test (BIST) circuitry is necessary to enable self repair, self healing of mmWave circui try. All these factors call for innovation of simple circuits capable of performing alternate RF tests. This dissertation discusses simple topolog ies of amplitude detector s suitable for millimeter wave BIST. The detector s can be implemented in different te chnologies; they occupy a small area, have low power consumption, a wide operating frequency range, negligible loading effects, and a suitable dynamic range. Detectors act as virtual probes that convert RF amplitude information into DC or low frequencies. The detector s response is discussed over multiple operating conditions with special attention to issues relevant to BIST applications. A differential detector that measures the pure differential

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13 component of a mixed mode signal is also presented. This det ector is further enhanced to measure both components of mixed mode signals including common mode. S ystem applications are presented to illustrate the advantages of each detector topology reported in this dissertation. Finally, this dissertation concludes w ith a summary a nd proposed future work section.

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14 CHAPTER 1 INTRODUCTION Challenges in High Frequency Test The RF test engineer constantly tackles new sets of issues to keep up with technological advances. The engineer is required to develop test solutions for highly complex circuits without affecting profit margins [ 1 ]. Devices under test (DUT) become more complex as they pack more functionality into an ever shrinking form factor. For example, MultipleInput Multiple Output (MIMO) technology is used in most recent standards (802.11n, WiMax, LTE). MIMO has stringent synchronization requirements throughout the entire transceiver chain. To minimize measurement related errors when testing MIMO systems, it is important to maintain accurate time and phase alignments [ 2 ]. Additionally, many system architectures are emerging by taking advantage of an abundant electronic processing power. Advanced radars emulate the mechanical rotation associated with standard radars by electronically scanning a multitude of stationary circuits. However, data extracted from the stationary circuits ne eds to have an accurate phase match; t hen, data can be post processed to accurately resolve an image [ 3 ]. Pulse to pulse phase is an important specification in advanced radar systems [ 4 ]. There fore, most modern electronic applications have strict tester specifications. Additionally, to boost the overall testing efficiency in mass production applications the ITRS keeps increasing the goal for RF multi site testing [ 5 ]. Multi site testing enables parallel measurements which decreases the overall test time; however it complicates the test setup.

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15 Figure 1 1 ITRS prediction of multi site testing required for RF products Figure 1 2 Complicated devices under test 0 100 200 300 '07 '08 '09 '10 '11 '12 '13 '14 '15 '16 '17 '18 '19 '20 '21 '22Number of multi sitesYear Wafer Packaged RF Logic IO RF Memory Analog/ Mixed-Signal Analog/ Mixed-signal Logic Memory IO 3D Wafer Stacks MIMO

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16 As described above, the test engineer has to test multiple DUTs in parallel. These DUTs are further complicated because of their MIMO architecture. Also, innovative architectures demand tight specifications to enable new functionalities. These are only some of the complications associated with the DUT itself. The test engineer has to also deal with another set of problems related to the test equipments. Figure 1 3 Automatic Test Equipment (ATE). Courtesy of LTX The ITRS Test Roadmap identifies testers inaccuracies as o ne of the difficult challenges facing the test industry [ 5 ] Extensive calibration is needed to take into account errors associated with the measurement setup. Also, commercial test solutions need synchronization units to synchronize all their instruments in addition to phasematching or phasetracking coax ial cables to connect the DUT to the instruments. However, the longer the cables the more difficult matching becom es [ 3 ]. Also, the higher

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17 the frequency of operation, the longer the electrical length becomes. Consequently, the cables performance becomes more sensitive to dielectric variations, bends, and temperature. Therefore, the l ong cables required for the conventional test solutions are more sensitive to temperature variations because of their greater thermal mass [ 3 ]. Proposed Solution All these issues demand innovation of novel alternate test solutions. To lower testing costs, [ 1 ] moved RF test on the probe interface board. This s olution uses customizable modular test circuits which effectively eliminate some of the tradeoffs of generic solutions. For example, the publication [ 1 ] reports a design of a synthesizer that is customized for a GPS test applications Whereas a generic vendor solution needs to cover a wide range of operating frequenc ies this customized solution can afford to operate at a bandwidth that is only satisfactory for its targeted test application. The customized solution has better phase noise attributes because of the smaller bandwidth. Also, since this solution is easily customizable, the frequency band is easily modified by replacing its Voltage Controlled Oscillator (V CO) to cover other test applications. Up to this point, discrete components were used to achieve this. However, different approaches should be considered for mmWave frequencies. Specifications of regular printed circuit boards are no longer suitable at hig her frequencies. Once circuits size becomes comparable to few wavelengths, PCB design can become challenging [ 6 ]. Low loss, high density, good match, and low coupling are difficult to achieve with CPW or microstrip lines at mmWave frequencies [ 7 ]. The PCB designer has to balance a number of tradeoffs. For example, t he designer needs to physically separate and shield the interconnect lines to minimize coupling. Conversely, the interconnect lines need to be matched to minimize amplitude and phase mismatch which in turn necessitates

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18 close spacing In [ 7 ], micromachining is used to leverage coaxial lines which are better suited to operate at higher frequencies. They implement microcoaxial lines on a PCB that support pure TEM (transverse electromag netic) propagation up to .5THz range. Therefore, miniaturization is one way to deal with issues at mmWave frequencies. Our goal is take advantage of miniaturization by designing modules for a tester on chip. Thus test circuits could be embedded on the DUT when possible; and for test applications that do not warrant any performance penalty, a hybrid solution that integrates a tester onchip into a tester onboard is proposed. However, by moving the testers on chip, post fabrication customization is not easy ; therefore, the proposed solution may lose a degree of freedom compared to the discrete component solution This means that testers onchip may need to adopt some of the same approaches of the generic vendor solutions. [ 8 ] describes how Software Defined Radio (SDR) strategies may be adopted in designing the next generation of RF instrumentations. For example, a frequency multiplier/differential quadraturegenerator for SDR applications reported in [ 9 ], has attributes required for onchip signal generation; i t is tunable and occupies a small area. The circuit can be cascaded w ith the synthesizer described in [ 1 ] as seen in Figure 1 4 which illustrates t his architecture. The synthesizer can generate a low phase noise signal with a fine frequency tuning resolution. The critical signals paths are shortened by moving them as close to the DUT as possible. Generation of higher frequencies and differential quadrature is done onchip to minimize errors associated with the test setup. On the measurement side, the test development engineer needs to borrow concepts from SDR topologies as well. By having a general purpose receiver front end, a number of alternative test approaches become possible such as design of a

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19 true synthetic instrument. Synthetic instruments implement many measurements using one test setup. For instance, an Error Vector Magnitude (EVM) measurement can characterize an entire transceiver; while a traditional transceiver test setup measures S parameter s, noise figure, compression point and a number of other specifications; with each of these requiring a different measurement setup. Low Phase Noise Synthesizer With Fine Freq Resolution Frequency Multiplier/ Quadrature Generator 0 Frequency Multiplier/ Quadrature Generator Frequency Multiplier/ Quadrature Generator Frequency Multiplier/ Quadrature Generator 90 180 270 0 90 180 270 0 90 180 270 0 90 180 270On-BoardLow frequencyOn-ChipHigh frequency Figure 1 4 Architecture of signal generation for onchip onboard tester for multi sites On another note, embedding test circuits on the DUT is also necessary nowadays. In the ever increasing world of integration in electronics, test access points are scarce. Multi chip packaging offers increased capability at the expense of an increased complexity [ 10]. C urrently, levels of integration reached anot her height with wafer stacking. 3D wafer stacking present s a new set of challenges for the test engineer. Even, expensive troubleshooting techniques such as noncontact probing (laser or thermal infrared) become virtually impossible [ 11]. These techniques become exponentially difficult as the number of layers in a chip increases. Therefore, n on -

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20 invasive BIST circuits can be useful to increase the number of test access points. BIST circuits can be described as virtual probes. Their role is not only limited to enabling more test capability, they also allow many alternative strategies. In applications that are prone to yield issues, BIST can facilitate self repair and self healing of DUTs. Probe Interface Board Tester-On-Board DUT1 DUT2 DUT3 DUT4 Tester-On-Chip Signal Measurement Tester-On-Chip Signal Generation Signal Processing DDS DDS Example DUT BIST BIST BIST BIST BIST A D... System Clock Supply Regulation Figure 1 5 Alternate test architecture Tester onchip onboard and embedded BIST Figure 15 shows the overall test architecture described above. It includes the proposed hybrid solution of onchip onboard testers for production test This drawing is

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21 a high level drawing that does not reflect the true scale. The o n chip tester should occupy a considerably smaller area. The figure also shows how BIST circuits allow access to internal nodes on the DUT. Figure 1 6 shows how a tester onchip can be integrated within a probe. This is a low cost solution suitable for characterization test. Figure 1 6 Alternate test architecture Tester onchip onprobe for characterization test As previously mentioned, current market conditions put pressure on the semiconductor industry to seek new business models. Because its difficult to assess future market conditions, short timeto market is essential. Lean, agile organizations trim their processes which easily facilitates their adaptation to changing market conditions. In the semic onductor industry, the development cycle isnt flexible because of the finality of the hardware product; thus, suitable lean thinking principles are limited.

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22 However, the strategies proposed in this dissertation can be implemented to reduce capital investm ents and to shorten the design cycle for example. By using alternate test strategies, the overall test cost can also be lowered by decreasing test time and reusing economical resources. Additionally, unnecessary wafer respins can be eliminated if failure s locations are detected efficiently. BIST allows insight to previously inaccessible nodes easily locating faulty circuit subcomponents. This is not the only way BIST fulfill the lean thinking methodology; BIST can be useful beyond reducing the design cycl e time. Given the way semiconductor devices are shrinking (geometries), it is inevitable to adopt new approaches to deal with process variations. BIST can enable self healing of the DUT. Easy adaptability is one of the basic premises of the lean thinking principle. It can also affect the DUT once it is deployed. So, for example, as the DUT ages or its operating conditions changes, it should be adaptable and self repair itself. BIST circuits can monitor important metrics, therefore, allowing the DUT to adapt to its operating conditions. Widespread adoption of BIST circuits, especially RF BIST, is usually received with some resistance. However, because of the severity of issues the semiconductor industry is set to face according to ITRS projections, many players in the industry realize that cooperative test approaches are necessary [ 12]. Finally, BIST is a necessity since integrated circuits are penetrating new markets that demand constant verification of functionality such as medical applications, and imaging for automotive collision avoidance and homeland security. Organization of the Dissertation This section provides an overview of this dissertation. The first chapter m entions the issues the test industry is facing to keep up with technological advances. It also discusses alternative test solutions and how the herein proposed work fit among those

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23 solutions This dissertation proposes modules for a low cost integrated tes t approach. This methodology combines embedding noninvasive circuits on the DUT and embedding other test circuit s on a test board. Chapter 2 is a comprehensive analysis of a MOS amplitude detector for millimeter wave BIST The detectors response is inves tigated in different operating regions. A simplified RF to DC conversion gain equation for detection in the saturation region is derived. Two conversion modes are uncovered in the subthreshold operation region. The first mode has a linear RF to DC proporti onality which applies only to relatively large signal levels. A new equation for small signal detection is introduced. The body effect was investigated in the saturation region and subthresholds two modes. Detection in the triode region is also discussed. In C hapter 3, the amplitude detectors response is characterized in detail For instance, the circuits RMS detection dynamic range is presented in different operating regions. The next section discusses envelope measurements when t he detector is stimula ted with amplitude modulated input s instead of single tone inputs This is f ol lowed by a discussion of the detectors settling time. It is important to describe the important metrics that affect the settling time as it directly impacts the overall test tim e. A novel bandwidth equation that takes into account the detectors loading effects on the circuit under test is introduced for BIST applications Finally, the detectors accuracy when it is subjected to environmental and process variations is discussed under different operating conditions. Alternate simple MOS FET topologies are proposed in C hapter 4. T wo topologies that minimize the crossover region in subthreshold are described. Subthreshol d

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24 detectors ha ve a large crossover region where neither the linear nor the square law modes are accurate. In the crossover region, when the input has a varying crest fact or the detector cannot estimate the inputs amplitude accurately. A topology with ex tended RMS detection dy namic range is introduced in this section as well. Finally, a new detector that operates in three operating regions (saturation, subthreshold, and triode) is introduced. This new detector topology is advantageous because of its flexi bility ; the same topology can be customized for different applications by changing its biasing region. Chapter 5 touch es on mixed mode signals. It presents a detector that measures the pure differential component of a port under test Another topology that improves upon the differential detector is unveiled. The common mode component of a mixed mode signal can be measured with a minor modification to the previous topology. In C hapter 6, system applications for the single ended and differential detectors ar e discussed. An LNA example is used to showcase the tradeoffs associated with each of the single ended topologies proposed in this dissertation. Additionally, compact Six port reflectometers topologies that measures S parameters which require differential detectors are reported. Chapter 7 is a summary of all the accomplishments and proposes future work.

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25 CHAPTER 2 MO S FET AMPLITUDE DETECT OR Introduction Amplitude detectors that realize RF to DC conversion are commonly used in RF BIST. T he RF input s amplitude is converted to DC through the nonlinear properties of a rectifying circuit. Many amplitude detectors operate by implementing a V/I (voltage to current) conversion, then RF to DC conversion, and finally an I/V (current to voltage) conversion. V/ I conversion circuits in previous publications limit the bandwidth to few GHz [ 13] [ 14 ] For those circuits, amplification is necessary for efficient rectification. Then, RF to DC conversion is usually done using a half wave rectifier [ 13] or using the translinear loop principle [ 14 ] The RF to DC conversion is usually realized in the current domain; thus, an I /V converter is needed to convert the resulting DC current to a DC voltage. V/I Conversion Rectification I/V Conversion RF input DC output Figure 2 1 Stages in amplitude detection There exists another class of detectors that do not require amp lification before rectification, where d etection is based on the nonlinear properties of a single device For instance, the popular classic diode detector belongs to this category For BIST applications, it is important for the amplitude detector to b e compatible with standard MOS processes to cover most products This section focuses on simple detectors

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26 based on MOS technology. The first MOS detector to the author s knowledge was designed by Vittoz in 1977 [ 15 ] This MOS detector operates in the subthreshold region. In 1990, a patent was filed for a MOS detector based on the squarelaw model of the transistor [ 16] In 1998, a paper from ENST Paris published two MOSFET structures [ 17] The two designs used th e non linear properties of the transistor channel to obtain a DC value that is proportional to the RF input. In recent years, [ 18 ], [ 19 ], [ 20], and [ 21] reused these topologies or other variants for BIST purposes. T1 T2 IDCIDCVrfVbiasVbiasVDDVS1S2C1C2 Figure 2 2 Meyers detector MOSFET equivalent In this chapter an analysis of a configuration popularized by Meyer [ 22] is presented. [ 22 ] reports a BJT version of the detector; while Figure 2 2 shows a MOSFET equivalent version. In th is topology, the fi rst step of rectification V/I conversion occurs through the drain current equation = ( ) ; t he drain current is a function of the RF input voltage. RF to DC conversion takes place throug h the nonlinear properties of the transistor T 1 where t he drain current is t he main source of non-

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27 linearity; a s a result the RF current generates an equivalent DC current. The last step of rectification, I/V conversion, is created through the gatesource junction. From Fi gure 2 2 the total DC current through transistor T1 consists of the quiescent current IDCquiescent in addition to the DC current created from the RF input signal IDCrf = + (2 1) At steady state, since the bias current source IDC is constant, then the current IDCrf is proportional to the current IDCquiescent. Also the gatesource voltage of the rectifying transistor changes proportionally to the DC quiescent current IDCquiescent; h ence, I/V conversion is obtained as the source voltage of the rectifying transistor T1 changes proportionally to the DC current IDCrf. T hus as explained above, all the steps necessary fo r amplitude detection can happen using a simple transistor configuration. V/I conversion, RF to DC conversion, I/V conversion are all functions that are carried out using one transistor. The distinctive idea is that the RF to DC conversion occurs before am plification. As long as the rectifying transistor is biased properly, the Meyer topology can gener ate a noticeable voltage change; t hen amplification at DC can ensue if necessary. This detection strategy extends the bandwidth of the detector well above the millimeter wave range, as opposed to being limited by the bandwidth of conventional V/I converters. Figure 23 shows m easurements results of a MOS detector at two different frequencies. The two plots do not overlap because pad and probes effects were not fully deembedded from the measurement results. Full details regarding the calibration associated with the measurement setup are presented i n APPENDIX A. Since testing the detector requires an absolute measurement, as opposed to ratioed, this calibration procedure is necessary.

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28 Figure 2 3 Measurement of MOSFET detector Alternate test methods which use amplitude detectors usually belong to two categories. The first method treats detectors as implicit feature extractors and relies on statistical analysis to estimate DUT specifications from detector measurements [ 23 ]. The second school of thought identifies detector structures whose outputs can be directly mapped to the DUT specifications; for example, [ 24 ] directly extracts gain and IIP3 of a DUT using rms detectors without resorting to learning steps. Both m ethods need the detectors response to have strong correlation to the DUT specifications. This sometimes requires significant pre or post processing for the first method; the second methods drawback is usually the long list of assumptions required to achi eve the direct correlation. In the next section s, the focus is to present simple design guidelines to dispel the disadvantages associated with the second method. T he detectors response is characterized across multiple operating conditions to increase the readers insight into this detector topology which, hopefully, will enable a wider use of this and similar RF BIST topologies.

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29 Saturation Region T he following analysis assumes that the dominant source of nonlinearity in MOS transistors emerges from the drain current. To simplify the derivations below, the long channel model is used. An analysis of short channel effects is done in [ 20 ], which uses a slight ly different topology ; nevertheless, it operates in saturation as well. The publication [ 20] determines that the detector still functions even when short channel effects are taken into account. When a MOSFET is biased in the saturation region, the long channel drain current is = 2 ( ) 2 (2 2) When the detector is stimulated with an RF input, the equation above becomes = 2 ( ) + 2 (2 3) where is = ( ) To calculate the output voltage V s1s2 in Figure 2 2 the drain current through transistor T1 is equal to the bias current I DC at steady state. Given that equal bias currents are applied to transistors T 1 and T 2 which are identically sized, the following equation results ( 1 1 ) + 2= ( 2 2 )2 ( 1 1 )2+ 2 ( )2+ 2 ( 1 1 ) cos ( ) = ( 2 2 )2. Also, since cos ( )2=1 + cos ( 2 ) 2 the equation above can be simplified further into ( 1 1 )2+ 22 + 22 ( 2 ) + 2 ( 1 1 ) cos ( ) = ( 2 2 )2 The low pass filter (Capacitor C 1 ) at the output cancels the terms cos ( ) and cos ( 2 ) And only the DC terms will remain. Therefore, ( 1 1 )2+ 22 = ( 2 2 )2

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30 1 = 1 ( 2 2 )2 22 Since the transistor is biased in the saturation region, V gs1 >V t1 Then, 1 = 1 + ( 2 2 )2 22 1 + 2 = 2 + 1 + ( 2 2 )2 22 1 2 = ( 2 1 ) ( 2 2 ) 2 2 2 (2 4) By definition, the threshold voltage is dependent on the source to body voltage Then, it is possible for the two threshold voltage to be different 1 2 since t he voltage 1 changes proportionally with When t he body of transistor T 1 is tied to ground, then the voltage 1 is n ot constant when changes. As a result, the threshold voltage 1 will change as well. On the other hand, if the body and the source of the transistor are tied together, such as the case of triple well transistors, then the two threshold voltages are equal 1= 2. The two threshold voltages are also equal for very small input signals since 1 does not vary substantially compared to 2. Using Taylors series expansion, equation (2 4) becomes 1 2 = 1 4 ( 2 2 ) 2 + 1 32 ( 2 2 ) 3 4 + (2 5) This will be discussed in the following section. Figure 2 4 shows simulation results of the detectors RF to DC response when it operates in the saturation region. It also shows the response when the detector is biased in the subthreshold region. Furt her details regarding this operating region will be discussed in the following section. Figure 2 4 also shows dashed lines that represent the best fit line of the det ectors response. For the saturation region, the plotted best line is a secondorder equation. As predicted

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31 from the Taylor s expansion equation (2 5) for smaller signal levels, there is good conformance between the detectors response and the second order best fit plot. For those input levels, the detector implements a sum of squares function which is needed for RMS detection. As the input signal levels increases, the detectors response starts deviating from square law rectification. Figure 2 4 Detector's response in saturation and subthreshold Subthreshold Region Depending on the application, it is possible to operate this detector in the subthreshold (weak inversion) region In that operating region, MOS transistor s have similar characteristics to BJT device s [ 25] In subthreshold the drain current I d becomes = 0 (2 6) Also, the collector current for a bipolar transistor is [ 26 ] = (2 7) 1.E 05 1.E 04 1.E 03 1.E 02 1.E 01 1.E+00 0.005 0.05 0.5 DC Output (V) RF Input Amplitude (Vpk) Square Law Subthreshold Crossover Subthreshold Linear Subthreshold Saturation

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32 As seen in the previous two equations, both the subthreshold and bipolar currents have an exponential format. Then, to obtain the MOS detector s output, only a slight modification to the BJT Meyer detector s output equation is necessary. The equation for the Meyer Detector [ 22] is 1 2 = 2 ln 2 (2 8) The manipulated equation for MOS detector in subthreshold is 1 2 = 2 ln 2 (2 9) The preceding equation (2 9) does not take into account the body effect. [ 21 ] does an analysis that assum es the body is tied to ground. In that case, t he output equation is slightly different 1 2 = 2 ln 2 (2 10) An extension taken from a publication [ 27 ] which uses the Meyers BJT topology can be applied to the MOS version when biased in subthreshold. [ 27 ] indicates that equation (2 8) derived for bipolar detector s is only accurate for inputs that are larger than 100mV. That paper also reports an equation for input amplitudes lower than 30m V 1 2 2 4 (2 11) By the same token, this can be extended to MOS detectors such as 1 2 2 4 (2 12) However, this equation is only valid for triple well MOS transistors. When the body effect is considered, t he drain current for transistors in subthreshold is (assum ing that > > ) = 0

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33 After further manipulations, the new equation for the subthreshold detector with body ef fect for small signal levels is 1 2 = 2 4 2 1 2 (2 13) Further simplification to this equation can be done; since it was derived for small signal levels, the difference between the two threshold voltages 1 and 2 is negligible The equation can be rewritten such as: 1 2 2 4 2 (2 14) Comparing equations (2 12) and (2 14) the body effect contributes an additional 1/n factor. Irrespective of the body effect, we have determined in this section that the detectors response in the subthreshold region vary according to the input signal level. For large signal levels, the detectors response is mostly linear according to equation (2 9) which means that the detector measures peak values Figure 2 4 shows that in the linear subthreshold mode, simulation results closely match a best fit line derived using linear regression analysis. For the square law subthreshold mode (small signal levels), second order regression analysis was necessary to obtain the best fit line as predicted by equation (2 12) In that mode the detector imple ment s RMS measurements. In this section, short channel effects were ignored since they are insignificant in the subthreshold region [ 18 ] F or low bias current levels the channel field strength is low; the effects of velocity saturation are minimal as long as V gs V t < .1 *c L [ 26 ]. Body Effect Summary The following table shows a sum mary of all the equations presented before for the DC output of the MOS FET detector.

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34 Table 2 1 S ummary of RF to DC conversion e quations S aturation S ubthreshold All inputs Small input Large input T riple well ( 2 2 ) ( 2 2 ) 2 2 2 2 4 2 ln 2 B ody effect ( 2 1 ) ( 2 2 ) 2 2 2 2 4 2 2 2 As seen in the table above, the body effect impacts the RF to DC conversion of MOS detector s. In the saturation region, the body effect appears through the threshold voltage 1 The threshold voltage is [ 26] = 0+ ( 2 + 2 ) When the detectors body is tied to ground, increases with higher input signal levels ; which in turn increases the threshold voltage 1. In equati on (2 4) a larger threshold voltage 1 translates into a smaller detectors DC output ; however, its overall impact is small due the square root in equation (2 4) Moreover, for very small input levels, the inputs amplitude effect on the threshold voltage is minimal since the DC voltage in the sour ce terminal of transistor T 1 varies weakly when the input is small Therefore, the body effect in detectors biased in the saturation region is not significant For detectors operating in the subthreshold the body effect appears as a 1/n factor. T he effect of th is factor is also minimal since n is usual ly a number between 1
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35 Triode Region All the previous analyses were done assuming that V ds of the rectifying transistor is high. Lets investigate operation in the triode region. Similar to the previous sections, the drain current is assumed to be the do minant source of nonlinearity In the triode region, = 2 ( ) 22 T his equation shows that the RF input at the gate terminal will not generate any nonlinearity. This is the case because the drain current equation given above does not have any nonlinear term in the term Vg. For the Meyer topology, the RF to DC conversion is generated because the current has higher order proportionality to the voltage Vg. For example, in the saturation region, the RF to DC conversion happens because the drain current follows the square law equation. Specifically, the voltage Vg which consists of the bias Voltage plus the RF input gets squared. But in this case, for the triode region, the voltage Vg is linearly proportional to the drain current Id. However, measurement results show a weak RF to DC conversion that occurs in the triode region. This may happen because of the mobilitys dependence on the voltage Vgs, non linearities in MOS parasitic capacitances, and leakage of the RF signal through the substrate or parasitics to a nonlinear junction Summary In this chapter, we introduced a class of detectors that is suitable for mmWave BIST. Carrying out all the stages necessary for detection using a single transistor enables operation at very high frequencies. A compilation of the detectors responses across multiple operating regions and different signal levels was presented. This was

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36 done for detectors with and without the body effect. There was compelling motivation to gather all the equations into a single document as they we re scattered across multiple publications. Also, the preceding literature did not clearly describe the conditions of operation associated with each equation. Moreover, the detectors responses were simplified ; i t is important to determine the type of proportionality each response has. A Taylors series expansion was used for the first time to simplify the saturation response. Also, t he detector has a linear and squarelaw proportionality depending on its operating region and the input signal level. When the detector has a linear proportionality, it is a peak detector. And when it has squarelaw proportionality, it is an RMS detector. Finally, it was determined that detection in the triode region is not possible with this topology. The measurement results presented in Figure 2 5 were part of joint collaboration effort using a colleagues MOS detector circuit [ 28]. Figure 2 5 shows the detectors response across multiple operating regions. So, in this ch a p t er, the detectors building blocks were introduced. Next chapter presents a more profound characterization of the detectors response. Figure 2 5 Measurement results in different operating regions 0 50 100 150 200 250 300 350 400 450 0 0.1 0.2 0.3 0.4 0.5DC output (mV) RF input (Vrms) Saturation Subthreshold Triode

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37 CHAPTER 3 D ETECTORS RESPONSE RMS Detector Subthreshold Region The previous analyses assume a single tone continuous wave (CW) signal was used to stimulate the input of the DUT. T his is adequate from many BIST applications; f or example, when measuring gain, it is suf ficient to stimulate the DUT with a time invariant input and measure the detectors output at steady state. However, to do multi tone tests [ 29 ] or measurements involving different waveforms shapes RMS detectors are important. C alorimetric sensor s that rely on thermal dissipation are very accurate RMS detectors This technique cannot be applied in BIST because of thermal coupling from adjacent circuits and slow response time. Another implementation uses diodes with a square law behavior. Diodes suffer from high noise levels, high temperature coefficients, and high performance Schottky barrier diodes (SBD) are not available in standard CMOS processes. [ 14 ] designed an RMS detector based on the translinear principle using a BiCMOS technology. However, the bandwidth is restricted to 1GHz due to the performance of the V/I converter circuit. [ 30] states that the BJT Meyer detector is an RMS detector for low input signal levels (<30mV). For larger signals, the detector acts more like a peak detect or. As a result, RMS detection is not possible for larger signal values unless attenuators are used. To extend the dynamic range of this detector, [ 30] used a number of attenuators to decrease high signal levels so that the detector operates in the RMS mode. This technique can be used for the MOSFET Meyer detector as well when it operates in the subthreshold region; so that the detector

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38 operates in the square lawsubthreshold mode. RMS measurements require adding the squares of each input harmonic to obtain the total power. Figure 3 1 Relative error of the detectors output to various waveform shapes Figure 3 1 shows simulation results of the detector when it oper ates in the subthreshold region when v arious w aveform shapes with equivalent RMS amplitu de are used as stimulus to the detector. The error relative to the detectors response when stimulated with a single tone is plotted for each waveform respectively. As predicted, the error in the squarelaw mode (low signal levels) is small. On the other hand, as the signal enters the linear mode, the detectors response to different waveform shapes varies. For example, each harmonic in a two tones signal has an amplitude of / 2 And the single tones RMS equivalent amplitude is In the squarelaw subt hreshold mode, the DC term proportional to each tone in the two tones signal is squared. This realizes the following function ( / 2 )2+ ( / 2 )2= 2, which is equivalent to an RMS operation. However, in the linear subthreshold mode, the detector performs a li near conversion. In that case, the detector will overestimate the RMS power because the two 20 15 10 5 0 5 10 15 20 25 0.005 0.05 0.5Error (%) RF input (Vrms) Sine Two tones Square Triangular

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39 tone signal peak amplitude is / 2 + / 2 > From Figure 3 1 the rms detection error is lower than 6% when V rms <70mV for the two tones input. Saturation Region The RF to DC conversion equation in both BJT and MOS Meyer detectors consists of a series with an infinite number of terms. Approximating square law behavior is only possible in a specific range when higher order terms can be neglected. This means that when the MOS detector operates in the saturation region, RMS detection can be achieved in a certain range. Once the sum of squares is achieved through detection, any post processing such as the sq uare root function or linear to decibel conversion which might be required to complete RMS measurements can be done off chip since the output of the detector is DC. When the detector is stimulated with a periodi c signal of any shape = cos ( = 1 + ) In the saturation region the drain current becomes = 2 2+ 2 + 2 where the overdrive voltage V ov is equal to the gate to so urce voltage minus the thres hold voltage V gs V t For the Meyer topology, the term 2 V ov V rf is eliminated by the low pass filter. Using Volterra algebra, t he only DC components that remain from V rf2 are 1 2 2. None of the other cross modulation terms that results from V rf2 a re translated to DC. The square law behavior of the drain current in the saturation region makes RMS detection possible. The MOS detectors output when it operates in the saturation region given any periodic RF stimulus is

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40 1 2 = 2 1 2 2 (3 1) Applying the Taylor series expansion to the equation above 1 2 = 1 4 2 + 1 32 3 2 2 + (3 2) Equation (3 2) can be simplified further into 1 2 = 1 4 2 (3 3) However, this equation is accurate only in a certain range. Solving the following inequality will determine this range 1 2 1 2 1 2 < This inequality describes when the simplified equation deviates from the actual equation within a certain threshold. Its solution is given with the following inequality 2 < ( 8 | | 8 2 ) 2 (3 4) Lets use an example to c larify this further. Lets set = 6 %, then the range where the detector conforms to square law within a 6% error is 2< 45 2. Figure 3 2 Relative error of the detectors output to various waveform shapes 20 15 10 5 0 5 10 15 20 25 0.005 0.05 0.5Error (%)RF input (Vrms) Sine Two tones Square Triangular

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41 Figure 3 2 shows that t he detector outputs RMS values with good accuracy for low signal levels; a s the signal s amplitude starts increasing, the response deviates from RMS detection. Similar to the analysis done for the subthreshold region, lets use a two tones example to uncover the cause. For low signal levels, since the detector fol lows the squarelaw, RMS detection is accurate because ( / 2 )2+ ( / 2 )2= 2. For higher input signal levels, higher order terms become significant. RF to DC conversion occurs through even order terms in the drain current ( cos ( )2, cos ( )4, ) As explained above, if the drain current displayed ideal square law behavior, the detectors response will be the same irrespective of the signals shape. However, for example, if the drain current has a fourth order component, RMS detection of a twotone signal is no longer accurate relative to single tone. For the two tones input, by using Volterra algebra, the DC term created from a fourth order drain current term ( / 2 cos ( 1 ) + / 2 cos ( 2 ) )4 is 3 /8 ( ( / 2 )4+ ( / 2 )4) = 3 /16 4. But for the equivalent single tone stimulus, the DC value generated from the fourth order term is 3 /8 4 This time, the detector underestimates the two tones RMS value relative the single tone RMS value. From Figure 3 2 RMS detection is accurate within 6% up to V rms <190mV for the two tones input. The theoretical value derived from inequality (3 4) gives V rms <208mV. Lets keep in mind that this theoretical inequality (3 4) was derived assuming an ideal square law current that is the dominant source of nonlinearity It does not take into account cross modulation between the harmonics, and second order effects such as the short channel, body effects, or higher order terms in the drain current. The inequality only accounts for the effects of ignoring higher order term in equation (3 2) This is not the same as the results shown in Figure 3 2 which plot the difference of the response to

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42 different input shapes relative to the response with a single tone input. It should be kno wn that even the single tone detectors response deviates from the square law behavior at higher signal levels. To sum up, any deviation from RMS detection results from higher order terms which becom e significant at higher input signal levels. In any case, the purpose of this section was to demonstrate that, when compared to subthreshold detectors or bipolar detectors, saturation detection has a wider dynamic range with accurate RMS detection characteristics. This range can be increased by increasing However, there is a limit to this method; a s is increased, short channel effects such as mobility degradation become dominant which limits RMS detection accuracy. This section discusse d RMS detection and its dynamic range for both subthreshold an d saturation MOS detectors It was shown theoretically and through simulations that RMS detection in the saturation region can be tuned by changing V ov Sources of errors which cause the detector to deviate from implementing a sum of squares function were discussed through examples as well Envelope Detector The previous section only considers the detectors DC output. Recent developments in RFIC test extract more specifications from the envelope of an RF modulated signal using alternate test methodologies [ 31] Another publication [ 32] uses a nonlinear regression method to map the envelopes amplitude into third order intercept (TOI) specification of a DUT. The detector discussed in this dissertation can effectively be used to measure the envelope of an RF signal. The detector can track the envelope of a mplitude m odulated (AM) signals or digital modulations based on

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43 a mplitude shift k eying (ASK). The bandwidth of the low pass filter at the output of the detector should be high enough for baseband frequencies associated with the envelope. Also, the filters bandwidth should be lower than the carrier frequency. This bandwidth is sometimes referred to as video bandwidth. Lets look at the RF to DC conversion in different operating regions when the detector is stimulated with a modulated signal = 1 + ( ) ( ) (3 5) is the amplitude of the carrier, ( ) is the baseband data signal, and represents the carrier frequency. In the previous sections, we determined that the RF to DC conversion follows a square law behavior in the saturation region and in the squarelaw subthreshold mode Thus the detectors output in both regions is 1 2 1 + ( ) 2 (3 6) is a constant which depends on the operating conditions of the detector In the linear subthreshold, the equation becomes 1 2 1 + ( ) (3 7) In the linear subthreshold, the carrier amplitude can be extracted from the DC output. The envelopes amplitude can then be extracted from the frequency content of the baseband (BB) signal. In the saturation and squarelaw subthreshold regions, the DC output is no longer proportional to the carriers amplitude only. Because of the sq uaring, some envelope information will show up at DC as well. In case the envelope is a sinusoidal wave with frequency equation (3 6) becomes 1 2 2 1 + 2 2 + 2 ( ) + 2 2 ( 2 ) (3 8) If the envelopes amplitude is small, the term associated with 2 can be neglected. It should be noted that there are many sources of errors that make the

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44 detector deviate from these ideal envelope detection equations For example, in the saturation region short channel effects may become important which will make the detector a nonideal square law device. In the linear subthreshold, the logarithmic error term may be sig nificant. One should also consider that if the signal levels are high, especially if the modulation index (depth) is high, it is possible that the conversion equation changes from linear proportionality to squarelaw proportionality. This happens because t he detectors operation in the two subthreshold modes depends on the signal level. Distortion to the envelope can also occur because of inappropriate output filter bandwidth or small bias current levels. With careful design and a suitable calibration method, it is possible to use this detector as an envelope detector. As seen in the Figure 3 3 the amplitude detector can act as an envelope detector as well. The detect or is stimulated with an AM modulated signal with a 70GHz carrier frequency, 100MHz modulation rate, and 50% AM depth. Figure 3 3 AM modulated signal to the left. Output of the detector to the right Figure 3 4 shows measurement results of the detector with an AM modulated signal at three different carrier frequencies 5GHz, 9GHz, 13GHz. For those thr ee carrier

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45 frequency, the AM depth was set to 50%, and AM Rate was 1 KHz. It should be noted that the AM rate is low because the detector was not initially designed for envelope measurements. The amplitude of the detectors output is plotted as the input s ignal level is swept. The amplitude of the baseband (BB) signal at detectors output which was measured using an Oscilloscope is effectively proportional to the RF signal strength. Figure 3 4 Measurement of the detectors output when input is modulated Figure 3 5 Oscilloscope capture of d etector's r esponse to a triangular AM input Further Oscilloscope captures are shown in Figure 3 5 from a circuit presented in [ 28] and designed jointly with a colleague. The following figure shows the detectors 10 100 1000 25 20 15 10 5 0 5Detector's Output (mV)Carrier Amplitude (dBm) 5GHz 9GHz 13GHz

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46 response when it is stimulated with 10GHz triangular AM modulated signal. The Modulation Rate is 100KHz. The detector was biased at two different operating points and two different modulation depths were used to expose the different responses. As previously mentioned, simple calibration methods can be used to extract the exact envelope as long as the detectors output filter is suitable. The next section discusses factors that are relevant to the output filter design. Settling Time All the prev ious equations were derived at steady state; discussion the settling time of the amplitude detector is necessary Settling time is important because it directly impacts the overall test time. Also, if the detector is to be used as an envelope detector, we need to take into account the effects of the time variant stimulus over the detectors response. [ 33] discusses the importance of the detectors response speed in applications with high crest fact (ratio of peak and rms value). Therefore, we need to incorporate another dimension, time, into this analysis. In this section, important metrics related to detectors time domain response are discussed T he settling time of the detectors response needs to be fast; however, it should be limited to reject ripples at the output of the detector [ 13 ] [ 34 ] discusses in detail the output ripples of the low pass filter in RMS detectors. In the frequency domain, this means that the video bandwidth should not extend all the way to the carrier freq uency Therefore, there is a limitation on the minimum settling time of the detector As for the maximum settling time, it needs to be fast enough to correctly track the inputs envelope or meet test time specifications Moreover, charge and discharge times are distinctly different since they are not always equal (cf. Figure 3 5 subthreshold). Previous publications [ 22], [ 27 ] and [ 35 ] define the discharge rate (droop rate) as

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47 = (3 9) w here the capacitance C refers to the capacitor used in the low pass filter, and the current is the DC bias current. Therefore, current and low pass filter capacitance determines how fast and how slow the output voltage changes. It should be noted that equation (3 9) is only an approximation of the discharge rate. Among other assumptions used to derive the equation, the amount of current discharging the capacitor C is only equal to when the rectifying transistor is completely turned off. This assumption is not always true especially in the case of modulated input signals. The total current flowing out of the discharging capacitor is equal to 1, where the current 1 is the DC current in transistor T 1 in Figure 3 6 The DC current 1 can be decomposed into the transistors quiescent current and the DC current converted from the RF input. For the charging rate, the total current flowing into the capac itor C is 1 IT1IT1IDC-IT1IDCIT1-IDCIDC(a) Discharge (b) ChargeT1T1C C Figure 3 6 Discharge and charge paths The detectors speed is almost always limited by the discharge time. The discharge time is mostly limited by ; while, the charging current is set by 1 which

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48 can be large compared to The instant an RF input is applied to a transistor, a large current can be generated from RF to DC conversion. In the linear subthreshold, the total DC current through tr ansistor T 1 is 1 = 0 1 2 (3 10) As seen in this equation, if A is really large, the charging time of the detector in subthreshold can be really fast due to the multiplicative effect. The settling time of detectors depends on many factors such as the operating region, the capacitor C in the LPF, the input signal level, and the aspect ratio of the rectifying transistor. It was important to show that the settling time of the detector does n o t only depend on the bias cu rrent One can deduce from the simplified equation (3 9) that increasing the current always makes the detector faster. This is not always true; f or example, in the saturation region the current that charges the capacitor is 1 = 2 1 2 + 2 2 2 2 2 (3 11) As can be seen in the equation above, if the bias current is increased by changing V ov which is equal to the gateto source voltage minus the threshold voltage, the effect is minimal on the charging current. The charging rate is not faster in this case, because the change in bias current ( ) is cancelled by the change in the quiescent current ( 1) Also, the DC current generated from the rectified RF input is not dependent on V ov in this case. Therefore, the rectified current is constant regardless of the change in V ov

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49 Figure 3 7 Charging rate as V ov is swept The settling time in detectors is no t as straight forward as it seems to be. However, an important deduction can be made. Decreasing the low pass filter capacitor value will always make the settling time faster. This is also the case when the aspect ratio of the rectifying transistor is increased. Increasing the bias current generally helps, especially with increasing the discharge rate. And finally, the charging rate in subthreshold detectors is no t always as slow as might be perceived. This is the case, because rectification in subthreshold can produce a current that is several factors of the quiescent current. Frequency Response Up to this point, all the equations presented for the detectors RF to DC conversion are not frequency dependent. The RF to DC conversion gain is equal to DC output of the detector over the RF input. Then, this detector could be described as passive frequency translation device. Therefore, the detector bandwidth is not limited by the gainbandwidth product since the device does not amplify signals At this point, according to the previous statement, it should be clear that the common perception that subthreshold detectors can only work at low frequencies is not true. The bandwidth in detectors should be different from the conventional methods used to define bandwidth. 0 5 10 15 20 100 0 100 200 300Charging rate (mV/ns) Vgs Vt (mV)

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50 A common equation used to define detectors bandwidth in the literature [ 20 ] [ 21] [ 22] and [ 27 ] is 3 = 1 2 (3 12) where, Rg: is the series resistance looking into the input of the rectifying transistor Cg: the gate capacitance. It should be clear that this equation is calculating the effects of the gate series Since the detector is employed for BIST, bandwidth should also consider the loading effec t the detector has on the circuit under test (CUT). In modern processes, the detectors load is mainly equal to the rectifying transistors gate capacitance. This is usually only few femto Farads. Therefore, the detector will have minimal effect on the CUT. That capacitance can easily be absorbed into the matching networks. In case the CUT cannot be modified, an alternate equation that reasonably represents the bandwidth of the embedded detector is defined. Lets first identify all the variables needed to derive this equation. Loss : the maximum loss that the CUT can tolerate from the detectors loading effects. ZL: the impedance looking into the node to be tested. The following example is derived in the context of a detector at the output of the CUT. When the detector is used at the input of a CUT, the equation will hold true as well.

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51 Figure 3 8 Loading effects of the detector on the DUT The gain of a CUT without the detector is where stands for the transconductance of the CUT. The gain of the CUT with the embedded detector is | | +1 2 Therefore, the loss caused by the detectors loading is = | | + 1 2 (3 13) After further manipulations, solving the equation above for the tolerable loss frequency, the new formula which accounts for detectors loading effects on the DUT is obtained = 1 2 1 2 2 + 2 2 (3 14) To give this equation some meaning, lets give an example using commonplace values in modern processes. Lets set RgCg= 4fF, ZL to Loss = .1dB which is a conservative value. The corresponding frequency where the CUT will experience a relative gain loss of .1dB is = 110 The 3dB frequency defined by equation (3 12) is 796 GHz ; the l oss to the CUT at that frequency is 18dB and is not 3dB as one might assume. In any regards, one should look at both of these frequencies when using detectors for BIST In addition, these equations are only accurate to a first degree since transistor paras itics do vary with biasing frequency, and signal levels Also, one should consider that if passive elements (such as ac coupling

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52 capacitors) are used at the input of the detector, the bandwidth is considerably affected by the attributes of these passive elements. Both Figure 3 9 and Figure 3 10 show the impact of using a coupling capacitor at the input of the detector. Figure 3 9 Detectors output over frequency Figure 3 10. Loss to a DUT caused by the detectors loading effects Detectors Accuracy Any integrated circuit is set to experience environmental variations such temperature changes. These types of variations have to be accounted for early in the design stage for inclusion of mitigation strategies. 0.07 0.072 0.074 0.076 0.078 0.08 1 10 100Detector's Output (V)Frequency (Ghz) Ideal Cap Cap w/ parastics 0.4 0.3 0.2 0.1 0 1 10 100Loss (dB) Frequency (Ghz) Ideal Cap Cap w/ parastics

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53 Temperature Variations Temperature effects on the amplitude detector are investigated in the following section. The detectors response is not immune to temperature variat ions and several calibration methods were proposed in the literature to compensate for these effects. First order calibration Feedback loop using amplifier Temperature compensation strategies have been widely investigated for all types of detector topologies. [ 36] reports a method to minimize temperature effects on diode detectors. Its compensation strategy is based on a feedback loop which uses an amplifier that adjusts the biasing conditions of the rectifying element as the temperature changes across a circuit used as a standard. The standard is a replica of the rectifyi ng circuit without any input applied to it. This method eliminates the detectors dependence on current variations through the rectifying devices by assuming that temperature variation affects the rectifying device in the same manner as the standard. [ 37 ] and [ 38 ] share a similar temperature compensation scheme implemented for detectors that use transistors. [ 37] is a bipolar amplitude detector slightly different than the Meyer topology. [ 38] is a MOS detector; however, instead of measuring RF signals, it measures radiations. These detectors are included in this discussion because of their interesting temperature compensation strategies and since they are bas ed on similar principles as MOS amplitude detectors by exploiting the nonlinear properties of a transistor. Figure 3 11 shows the topology on which these two detectors are based; its major difference compared to the Meyer topology is the use of a resistor instead of current source.

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54 VDDOut1 T1 T2In VbiasVbias R R C C Figure 3 11. Detector using resistor This topology was also reported in the literature [ 39] without any consideration to temperature effects. This detectors accuracy is greatly decreased since it s output is highly dependent on temperature. For example, for small signal levels when the rectifying transistor is biased in subthreshold, the output of the detector is derived such as 1 = 1 1 1 1 + 2 2 2 2 (3 15) 2 = 2 2 2 (3 16) w here the voltage V d1 stands for voltage at the drain of transistor T 1 A is the amplitude of the high frequency input signal stimulating the detector Vt is the threshold voltage, and VT is the thermal voltage kT/q The output of this detector is the difference between V d2 and V d1 Since the overdrive voltage (V gs V t ) across the two transistors T 1 and T 2 are the same, equation (3 15) can be subtracted from (3 16) to obtain: 1 = 1 1 1 2 2 2 2 (3 17)

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55 This equation is highly dependent on temperature, especial ly through the exponential term Several attempts have been made to minimize the temperature effects of the topology shown in Figure 3 11. [ 16 ] for example, proposes a closed loop system that changes the biasing of the amplitude detector dynamically as the temperature changes. It uses a temperature compensator circuit in conjunction with a diode used as reference. The patent, however, does not disclose any information regarding the temperature compensation circuit. VDD T1 T2In Vbias Out2 R R C C Figure 3 12. Detector using feedback to compensate for temperature variations Another feedback method employed in [ 37 ], [ 38] which minimizes temperature effects is shown in Figure 3 12 After the feedback loop settles when the detector is stimulated with a n RF input, the currents trough transistor T 1 and T 2 should be equal. 1 1 1 1 + 22 2 2 = 2 2 2 T his equation is simplified such as

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56 1 + 22 2 2 = 2 1 Since the output of this topology is taken across the gates of the two transistors T 1 and T 2 and with some manipulations to the equation above, the detectors output is 2 = 22 Unlike the output in equation (3 17) this detector is no longer exponentially dependent on temperature. Note that this equation is exactly the same as the Meyer topology equation. As can be seen, these compensation methods are not completely immune to temperature variations; nevertheless, they provide a first order compensation method. Meyer topology In the Meyer topology, a current source is used compared to the resistor used in [ 37], [ 38 ]. It was shown that the output of the topology in Figure 3 12 when feedback was used is similar to the Meyer topology output; thus, the Meyer topology does not require any additional compensation. Good accuracy can be achieved as first order temperature compensation is inherent within the Meyer configuration. [ 37 ] emphasizes the importance of bias currents in detectors; it leveraged the amplitude detector shown in [ 13 ] by using a fixed transconductance bias circuit. This allowed .5dB accuracy across process corners in the temperature range of 0C to 70C. Furthermore, the im pact of using the current source can be verified by examining the theoretical equations derived for the MOSFET Meyer detectors output. Simulations below show the outputs dependence on temperature across many regions of operation to comply with the spirit of this dissertation which attempts to present Meyers detector response in the simplest way possible across different operating conditions.

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57 Figure 3 13. Subthreshold response vs. temperature Figure 3 14. Saturation response vs. temperature These plots show the response of the detector for small input signal levels ( 35dBm to 33dBm) and large signal levels (1dBm to 3dBm) over t he commercial temperature range [0C, 70C]. In subthreshold, as expected from the detectors output theoretical equations (2 9) and (2 12) temperature is more dominant for smaller input levels compared to larger input signal levels. For instance, when the input level is 2dBm, the output varies between [262mV, 276mV]; for 1dBm, the corresponding output varies between [228mV, 241mV]. Since there is no overlap between the two ranges, the 0.0E+00 5.0E 02 1.0E 01 1.5E 01 2.0E 01 2.5E 01 3.0E 01 3.5E 01 1.5E 04 2.5E 04 3.5E 04 4.5E 04 5.5E 04 6.5E 04 7.5E 04 8.5E 04 0 20 40 60 80Output (V) Output (V) Temperature ( C) Subthreshold 35dBm 34dBm 33dBm 1dBm 2dBm 3dBm 0.0E+00 3.0E 02 6.0E 02 9.0E 02 1.2E 01 1.5E 01 1.8E 01 2.1E 01 2.5E 05 5.0E 05 7.5E 05 1.0E 04 1.3E 04 1.5E 04 1.8E 04 2.0E 04 0 20 40 60 80Output (V) Output (V) Temperature ( C) Saturation 35dBm 34dBm 33dBm 1dBm 2dBm 3dBm

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58 detector can predict signal level with an accuracy that is better than 1dB. Another way to represent the previous data is shown below. (a) (b) Figure 3 15. Detectors response vs. temperature As seen in the plots above, the detector accuracy over temperature is set by variations in smaller input signal levels. In subthreshold, the accuracy of the detector is .5dB; in the saturation region, the error is larger amounting to .65dB. Additionally, the accuracy of the detector is highly dependent on the operating point of t he rectifying transistor. Figure 3 16 summarizes the temperature effects depending on the operating region of the rectifying transistor. The graph shows values for how many parts per million per degree Celsius the detectors output changes. This is calculated by dividing 0.2 0.25 0.3 0.35 1.0E 04 2.0E 04 3.0E 04 4.0E 04 35dBm 34dBm 33dBm 1dBm 2dBm 3dBm Output (V) Output (V)Subthreshold 0 C 17.5 C 35 C 52.5 C 70 C 0.1 0.15 0.2 0.25 2.0E 05 4.0E 05 6.0E 05 8.0E 05 35dBm 34dBm 33dBm 1dBm 2dBm 3dBm Output (V) Output (V)Saturation 0 C 17.5 C 35 C 52.5 C 70 C

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59 the difference of the detectors output at the two extreme temperatures (0C and 70C) by the detectors output at the center of that range. This value is then multiplied by 10^6 to convert it to ppm and then divided by the temperature range. The equation below summarizes how the detectors response temperature coefficient w as calculated = ( 0 ) ( 70 ) ( 35 ) 10670 Figure 3 16. Temperature coefficient of the detectors response as function of the overdrive voltage Figure 3 16 shows that the accuracy of the detector is set by lower amplitude inputs. It also confirms that the error in saturation is higher than the error in subthreshold as seen in Figure 3 13 compared to Figure 3 14. Inte r estingly when operating around zero overdrive voltag e whether in saturation (moderate inversion) or subthreshold, the detectors dependence on temperature decreases. Ad hoc solutions Finding the optimum operating point which minimizes tem perature effects is one solution A set of publications introduce ad h oc solutions to further improve the accuracy of the amplitude detector. [ 22 ] and [ 41] adopt minor modifications to the original Meyer 0 500 1000 1500 2000 2500 3000 3500 4000 4500ppm/ CVgs Vt Small inputs ( 35dBm) Large inputs (3dBm) Subthreshold Saturation

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60 topology ; nevertheless, the detectors accuracy is improved only for specific conditions. In Meyers Peak detector [ 22] the output dependence on temperature can be eliminated by modifying the replica such as I 2 =2*I 1 and R 2 =R 1 /2 when the input is a square wave. [ 41] shows that mismatching the current sources between the rectifying and the replica of the detector such as I 1 /I 2 will improve the temperature performance of the reported detector topology is the por tion of the input fed to the replica circuit set by the resistive divider circuit in that detector. Unfortunately, this improvement is only effective in the linear region (higher input signal levels) of the detector. A possible workaround consists of desig ning a current mirror whose temperature coefficient cancels the temperature coefficient associated with the rectification process. Nevertheless, as seen in Figure 3 16, the detectors temperature coefficient changes with the input signal level. Consequently, this solution remains limited and can be applied in specific conditions only. Temperature sensor [ 38] suggests that in addition to employing the feedback method, more accuracy is possible by using an additional temperature sensor. If the temperature of the circuit is know n post processing of the detectors output can be done to estimate the RF input with more accuracy. This is the same strategy that is employed in commercial solutions such as standalone power sensors, where calibration data is stored in nonvolatile memory and is used in combination with a temperature sensor to achieve a dynamic range in excess of 90dB [ 42 ]. Interestingly, the amplitude detector has implicit temperature sensing capability. [ 43] uses a nonlinear mapping from a multitude of detectors to predict specifications

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61 such as P1dB, IIP3, and noise figure within a 1dB error. This BIST methodology can account for temperature variations by using one of the detectors as a temperature sensor. So, in summary, [ 43] reports that non linear mapping of several detectors response can predict specifications of a DUT in the presence of process and environmental variations as the nonlinear mapping provides an autocalibration. In order for this method to be successful, the alternate test circuits (detectors) have to produce a measurement that can be strongly correlated to the specifications under test while accounting for environmental and process variations. The highest levels of accuracy in amplitude detectors can be achieved by including a temperature sensor. [ 38 ], [ 42 ], and [ 43 ] all include a temperature sensing capability and apply correction factors t o the amplitude detector using post processing methods. Process Variations The previous section dealt with temperat ure effects on the detector and offered some solutions to minimize those effects. Semiconductor devices also suffer from physical variations in addition to the aforementioned environmental variations. Physical variations are caused by changes in the semiconductor process since its impossible to replicate the level of control over the process from one wafer lot to the next or wafer corners as well The Meyer topology was preferred over other topologies since it provides superior performance compared to other detector structure s of the same family type. Similar to temperature effects, process variations in the Meyer topology are also expected to be lower than the structure shown in Figure 3 11 The previous section discussed how severe temperature variations can affect that topology because its output depended directly on the current through the rectifying transistor when biased in

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62 subthreshold. In addition to being highly dependent on temperature, the DC current in that structure is also heavily susceptible to process variations which also affect the accuracy of the detector. [ 44] whic h uses the same structure as the one shown in Figure 3 11, derives the output of the detector when its biased in the saturation region. = 4 2 (3 18) Even in the saturation regions, variations in the topology which uses a resistor are higher than variations in Meyer topology. Equation (3 18) shows that the Figure 3 11 topology is susceptible to variations in the term C ox W/L as well as variations in the resistor R, while the Meyer topology is affected only by variations in the C ox W/L term. Therefore, first order compensation to process variations is also intrinsic within the Meyer detector topology in the saturation region. Nevertheless, process variations are more severe with deeply scaled pro cess technologies. As predicted by Pelgroms models [ 45 ], the level of mismatch between two elements is inversely proportional to the size of the elements. 2( ) = 2 + 2 2 Where 2 is the variance of the difference of parameter P AP and SP are constants, W and L are the dimensions of the elements, and DX is the distance between the elements. Moreover, this model only applies to intra die variation When inter die variations which include dies from different wafers or lots the variance of the circuit is much larger and size is no longer critical. For the detector, as long as the size of the rectifying transistor is few times larger than the minimum size transistor in the process the standard deviation of the detectors response reaches a minimum and size of the

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63 rectifying transistor becomes irrelevant. These statements are summarized in Table 3 1 which shows Monte Carlo simulations resul ts when the detector is stimulated with a 0dBm input. These Monte Carlo simulations were implemented using a Skew file provided by the foundry IBM which defines the statistical variation of the process parameters in the technology. The size of the dete ctor was varied and the values shown in Table 3 1 are normalized to the minimum size transistor in the process. For all sizes, the detector was biased in the saturation region while maintaining the same overdrive voltage across the rectifying transistor. Table 3 1 Monte Carlo simulations of different normalized transistor sizes Size Std Deviation mismatch only Std Deviation mismatch + process 1x 0.8% 5.5% 4.25x 0.4% 3.2% 42.5x 0.1% 3.2% The table shows that when only intradie (mismatch only) variations are considered, only minor spreads of the detectors response are produced and the detector is expected to be accurate. It i s also obvious that the variations are proportional to the detectors size as predicted by Pelgroms equation. However, when inter die (mismatch + process) variations are included in addition to the intradie variations, the distribution of the detectors response has a much higher standard deviation. The standard deviation of the variations is highest for the minimum size transistor, but it seizes to decrease as the size of the rectifying transistor reaches a certain threshold as seen in the table above. Process variations are also dependent on the operating region [ 46 ]. In this light, variations are presented across the different operating regions. From the theoretical equations derived for the detectors output in different operating conditions, it was

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64 pr edicted that subthreshold detection is less sensitive to process variations than saturation detection. Mor eover, it i s expected that detector s experience more variations for low input power levels compared to higher input power levels. The following figures show Monte Carlo simulations of the detector including process and mismatch variations (worst case condition). Figure 3 17. Variations of detectors response in the subthreshold region in the plot above refers to the mean value, and refers to the standard deviation. It i s seen that in the subthreshold region, the detector has an accuracy that is better than .5dB. The plot shows the response of the detector when stimulated respectively w ith the input power levels 33dBm, 34dBm, and 35dBm. For each input power level, the detectors response varies in a limited range which does not overlap with the other ranges that are associated with the adjacent power levels. 0 10 20 30 40 50 60 Percent (%)Detector's Output (V) 33dBm 34dBm 35dBm 180uV 2.8% 226uV 2.3% 284uV 2%

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65 Figure 3 18. Variations of detectors response in the saturation region In the saturation region, the accuracy of the detector is worse compared to the subthreshold region. The Monte Carlo plot above shows that the spacing required for adjacent power levels to achieve no ambiguity when predicting in the input power level is .8dB. Bear in mind that this value is dependent on the rectifying transistors overdrive voltage. Calibration DC offset The most significant variation in the MOS FET amplitude detector is a DC offset which arises between the rectifying part of the detector and the replica. [ 21 ], [ 44 ] states that this offset is constant and remains independent of the high frequency input. Hence, this dictates a one shot DC calibration for each detector to cancel the DC offset. Threshold voltage variations are expected to be the main cause of this offset which can be minimized by using triple well transistors [ 21 ]. 0 5 10 15 20 25 30 35 40 Percent (%)Detector's Output (V) 31.8dBm 33.4dBm 35dBm 35.3uV 5.8% 51.1uV 5.8% 73.8uV 5.8%

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66 Reference detector As discussed previously, first order calibration of process variation is built in the topology. When this first order compensation is not enough because higher levels of accurac y are required, more elaborate calibration methods are necessary. The simplest option is to include an extra detector in the wafer whose input can be probed so that it can be used to calibrate the remaining detectors since intradie variations are small. T he standard deviation of the detectors response is.7% when only intradie variations are considered as seen in Figure 3 19 compared to 5.8% seen in Figure 3 18 when inter die variation are taken into account as well. When a detector is calibrated and used as a standard, the accuracy of other detector s within the same die will beco me .1dB instead of .8dB when only mismatch is considered. Furthermore, the number of additional detectors used for calibration can be increased and placed in various wafer corners if intradie variations are large. Figure 3 19. Monte Carlo in the saturation region considering only intradie variations 0 5 10 15 20 25 30 35 Percent (%)Detector's Output (V) 34.6dBm 34.8dBm 35dBm 35.5uV .7% 37.1uV .7% 38.9uV .7%

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67 Statistical methods In deeply scaled process technologies, process variations become accentuated and the previous calibration methods might not be sufficient. [ 47 ] reports a promising method that calibrate s detectors to higher accuracy levels. In addition to one detector which can be calibrated dir ectly with an RF signal, the method relies on DC signals only for calibrating the remaining detectors. It uses statistical analysis to map the DC to DC response into the RF to DC response. In [ 47 ], the detector reaches accuracy levels better than 1% for signal levels higher than 2 00 m V. [ 32] also uses statistical analysis to account for process variations; however, it calibrates the DUT and the detectors simultaneously. The method measures a number of samples using both conventional and the alternate test methods; then, it hinges on a statistical training which correlates the alternate test method to the actual specifications as it uses detectors whose output s are directly correlated to the specification space. On the other hand, [ 43 ] is not concerned whether the detectors response is directly linked to the specification space; it just identifies the detector as an implicit feature extractor and uses statistical mapping to extract further information from the alternate test measurement space. To guarantee strong correlation between the alternate test measurements and the DUT specifications, it uses a multitude of detector types. Bipolar detectors are used because of their currents exponential relationship in addition to Mosfet detectors for thei r square law relationship; however, this limits the methods feasibility to BiCMOS process only as it was originally proposed in [ 43]. Actually, the method can be adapted to standard bulk CMOS process knowing that MOSFET detectors can be biased in different regions to obtain exponential relationship in subthreshold and square law in saturation.

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68 [ 29] optimizes the test pattern generation instead of using a multitude of detectors to find signals which can stimulate the alternate test method to achieve the strong correlation between the al ternate test space and the specification space. This methods algorithms render it immune to process and environmental variations. All these statistical methods rely on a fault dictionary that is built either from simulations or conventional measurements w hen possible ; then a mapping engine can estimate the specifications of the DUT from the alternate measurement space after training The alternate test methods are immune to process and environmental variations as long as there are strong correlations between the alternate test measurement space and the DUTs specification space. Yield impact Calibration benefits are not only limited to achieving higher levels of accuracy; another benefit is to detect catastrophic faults in the alternate test method that can be caused by random defects. Catastrophic faults in the detectors are critical since they directly impact the yield as they give a false reading; although this yield impact is expected to be low since the area occupied by the BIST circuitry is smaller com pared to the DUT. Calibration methods have an inherent capability of detecting most failures. For example, measuring the DC voltage at the output without any RF stimulus can be used to locate catastrophic failures such as shorts and opens. Applying a low f requency input to the detectors output through a bias tee will have high fault coverage except failures between the DUT and the detectors input such as open. All the other calibration methods can also be used as well to detect catastrophic failures. At t he very least, if failures are still a concern and yield loss is expected to be high, the BIST method can be used for binning the DUT to minimize test escapes faster in an initial wafer test

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69 DUTs can be sorted into pass, fail, and a third category which r equires further test because of inconclusive BIST results. Dynamic Range In general, for CW signal, dynamic range in amplitude detectors is limited in the higher end by transistor breakdown. Unlike other active devices where compression point such as P 1dB puts a limit to the dynamic range, amplitude detectors are not affected by compression since they work through the exploitation of nonlinearities of the rectifying devices. However, if the input is not a CW signal, detection accuracy depends on the input signal levels as discussed in the previous section. The lower end in the dynamic range of detector (sensitivity) can be limited by two mechanisms. The first factor which is inherent to the det ector itself is noise sources such as shot noise, and flicker n oise. The second limitation that affects the sensitivity measurements is the precision of the digital multimeter (DMM). When the DMM limits the measurement capability, subthreshold detection is advantageous compared to detection in the saturation region. From the equations in Table 2 1 subthreshold detector s ha ve a higher RF to DC proportionality coefficient than saturation detector s. For small signal levels, the saturation detector will have a DC output higher than the squarelaw subthreshold detector only if < when equations (2 5) and (2 12) are compared. This condition is not possible since the inequality means that the saturation detector is biased in m oderate inversion. For higher signal level s, by comparing (2 5) and (2 9) and making some assumptions such neglecting the log arithmic term in equation (2 9) the saturation detector can have a higher DC output only when > 4 This condition occurs only when the input signal is very large (breakdown),

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70 or when the rectifying transistor is biased near subthreshold. Thus, from the discussion above, subthreshold detectors have a higher DC output for a given RF input level co mpared to saturation detectors. This makes them more sensitive compared to saturation detectors when measurements are limited by the precision of the DM M. Summary In this section, the tradeoffs of detection in each operating region are recapitulated The first section of this chapter showed that subthreshold detectors operate in two modes which limit their RMS detection dynamic range. The RMS detection r ange in the saturation region was larger as well as tunable as shown by inequality (3 4) On the other hand, subthreshold operation can be useful when power consumption needs to be minimized. However, the settling time of the detectors output is slow due to the low bias currents. Therefore, this detector cannot be used for high symbol rate applications. The frequency response of the detector was also discussed to show that the detector is suitable for mmWave BIST. Moreover, by comparing the equations in Table 2 1 as well as the simulation results in the previous sections, subthreshold detector s are more immune to environment al and process variations Calibration methods to account for these types of variation were also reviewed. Finally, factors that limit the dynamic range were also reported. The benefits associated with each operating region of the detector are summarized in the table below. Table 3 2 Comparing saturation and s ubthreshold d etection RMS dynamic ran ge Power consumption Video Bandwidth Immunity to variations Sensitivity Saturation + + Subthreshold + + +

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71 CHAPTER 4 ALTERNATE DETECTOR T OPOLOGIES MOSFET Detector Subthreshold Crossover Region Introduction As stated previously, the amplitude detector is not ideal; Linear or squarelaw behavior is only an approximation of the detectors actual response. Nonetheless, there exist some techniques to increase the detectors precision. Feedback loops can be used to increase the accuracy of peak detectors (Linear detection) [ 48 ], [ 49 ] However, feedback loops which operate a t the input signals frequency severely restricts the bandwidth of the detector [ 33 ] uses an open loop circuit with two mismatched detectors and some post processing at DC to minimize the detectors error. Nonetheless this technique works for large signal levels only For applications with large dynamic range, it is desirable to maintain one type of detection (RMS or Peak) over a wide range of signal levels This section deals particularly with the subthreshold crossover region. Two topologies that minimize this region are introduced in this section. Type II Detector The s ubthreshold MOS amplitude detector like the bipolar detector, has two separate detection modes; a linear detection mode for higher amplitudes and a squarelaw mode for lower amplitude input levels Additionally there exists a large crossover reg ion where neither squarelaw or linear fit is accurate. [ 27] developed a technique that reduces the range of this crossover region in bipolar transistors by minimizing the effect of an error term in the linear mode. This same technique can be used for MOS transistors i n the subthreshold region. Equation (2 9) shows that the detector s DC output is not exactly linearly proportional to the RF input s amplitude. It shows a

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72 logarithmic term that is dep endent on the inputs amplitude which causes deviations from linear proportionality. Nevertheless this error value is compressed as it is logarithmic According to [ 27 ] which reported this method in bipolar detectors this error is within 10% for inputs larger than 100mV. As seen in Figure 4 1 this technique works such that the DC output is referenced to a replica circuit whose input is a fraction of the RF input. This is different from the traditional Meyer detector where the replica has no RF input T1 T2 IDCIDCVrfVbiasVbiasVDDVS1S2 Figure 4 1 Type II MOS detector The output of th is MOS detector named here type II, in subthreshold is given in the following equation 1 2 = ( 1 ) + 2 ( ) (4 1) The term is the fraction of the input stimulating the reference replica circuit. As can be seen in the equation above, the logarithmic term is no longer dependent on the input

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73 signals amplitude ; this effectively makes the detector linear Furthermore, for smaller RF input amplitudes. The output equation becomes 1 2 ( 1 2 ) 2 4 (4 2) In the saturation region if this technique is used, the type II detector output becomes 1 2 = 1 4 ( 2 2 ) ( 1 2 ) 2 + (4 3) Type III Detector Another circuit that minimizes the subthreshold crossover region is presented in this dissertation. Unlike the type II detector that linearizes the subthresholdlinear mode, this circuit extends the subthresholdsquarelaw range. The circuit shown in Figure 4 2 averages the DC drain currents in the transistor pair T11 and T12. T11 T21 T12 T22 VrfVbiasVbiasVDDVS1S2VbiasVbias(1+M)IDC1x Mx (1+M)IDC1x Mx Figure 4 2 Type III MOS detector

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74 As seen in Figure 4 2 only transistor T11 is stimulated with an RF input. I n the subthreshold region, the following equations result 11 + 12 = 21 + 22 (4 4) 0 1 0( ) + 0 1 = ( 1 + ) 0 2 0 1 0( ) + 1 + = 0 2 1 2 = 0 ( ) + 1 + (4 5) where M is the factor which relates the size of transistor T 12 to transistor T 11 b = A/nV T and 0( ) is the 0th order modified Bessel function 0( ) = 24 ( )2 = 0 0( ) can be approximated for small signal levels (squarelaw) such as 0( ) = 1 + 24 And the approximation used for 0( ) for large signal levels ( linear subthreshold) is 0( ) = 2 For type III detectors, when 0( ) is approximated, the quantity 1 2 in equation (4 5) deviates from the ideal value by = 0( ) + 1 + 0( ) + 1 + 0( ) + 1 + = 0 ( ) 0 ( ) 0 ( ) + (4 6) Whereas, the error for type I (Non modified Meyer Topology) detectors, the quantity 1 2 from equation (4 5) deviates from the ideal value when approximation is us ed by = 0 ( ) 0 ( ) 0 ( ) (4 7)

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75 Therefore, by comparing equation (4 6) and (4 7) the error in type III detectors is always smaller than type I detectors. Comparison B etween the Three Types o f Detectors A numerical analysis was done using Matlab to compare the three types of detectors. The following table shows t he theoretical and approximated output values 1 2 for each detector For type II detectors, the value of is set as = 5 ; and for type III detectors, the value of M was set to M =1 Table 4 1 V alue of V S1S2 /nV T for the three types of detectors Type I Type II Type III Theoretical 0 ( ) 0 ( ) 0 2 0 ( ) + 1 2 Square law approx. 2 4 3 2 16 2 8 Linear approx. 2 2 2 8 The Linear approximation for type I and type III in this table is not exactly linear; a best fit linear regression is used to linearize the approximations further Deviations of these approximations from the theoretical values are computed and plotted in Figure 4 3 as a function of the input level b The errors are highest in the crossover region which is defined as the range when the detectors output deviates by 8% from the linear or squarelaw approximations [ 27] This section showed how the crossover region varies for each ty pe of detector. Besides having a small crossover region, parasitics at the input of type III detectors are lower compared to type II detectors.

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76 Figure 4 3 Error of approximated detector's output relative to the theoretical value Additionally, the type III detector has a faster discharge rate when compared to the other two types. This is useful w hen lowering the low pass filter capacitance C, increasing the aspect ratio of the rectifying transistor, or increasing the bias current are not possible options due to the tradeoffs linked to each solution. The type III detector increases the speed of the detector using a somewhat hybrid approach of increasing the as pect ratio and increasing the bias current without the tradeoffs associated with

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77 each approach. The type III detector increases the transistor count without increasing the loading effect s on the DUT; i t also increases the bias current without changing the operating point of the rectifying transistor. Therefore, this makes the discharge rate faster, which is important for applications with high symbol rates. This is especially beneficial in subthreshold since the video bandwidth is low in that region. The benefits of the Type III detector are not limited to what was discussed above. The next section will introduce advantages of using the type III detector in the saturation region. Type III Detector in the Saturation Region As discussed previously, square law response is desirable in many applications where the input is not a simple CW signal. There has been a wide interest in the industry to design detectors with extended RMS dynamic range. Many circuit techniques were developed to replace calorimetric detectors which are inherently squarelaw devices capable of working properly even for higher signal levels. The calorimetric detectors are not suitable for BIST from which aris e the need to develop alternative solutions. [ 50 ] describes how the square law dynamic range of a diode can be extended by replacing it with a diode stack which consi sts of several diodes connected in series. The patent [ 50] explains that the response of the detector changes with the input signal levels because of an effect called the diodes junction capacitance modulation. When employing several diodes in series, this junction capacitance is decreased, thus, minimizing the amount of modulation. [ 51] presents a more sophisticated detector which combines diodes stacks with resistive attenuation network to achieve an even larger square law dynamic range. The use of diode stacks in addition to resistive attenuators is justified since high attenuat ion values cannot be

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78 obtained in integrated circuits; parasitic coupling such as substrate leakage sets the limit of the maximum possible attenuation to 30dB or 40dB Vrf Vout (DC) Vrf Vout (DC) ...(a) (b) Figure 4 4 (a) Diode used for RMS detection, (b) Diode stack with increased RMS dynamic range Using diode stacks effectively increases the square law dynamic range. Nevertheless, a method that is compatible with CMOS processes where high performance diodes are not readily available is required to extend the RMS dynamic range. Actually, square law d etection is possible in MOS transistors when biased in the saturation region. Hence, a square law detector can be obtained by implementing the topology shown in Figure 4 5 VDDOut1 T1 T2In VbiasVbias R R C C Figure 4 5 Detector using resistor

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79 The output of this topology in the saturation region is = 4 2 However, this topologys accuracy is heavily reliant on the attributes of the resistor R More advanced detector topologies were developed to circumvent this issue. The MOSFET Meyer detector is more robust because it uses a current source instead. On the other hand, once a current source is used the Meyer detector implement s square law only up to a limited range of power levels as discussed in the previous chapters In the saturation region, an inequality was derived to estimate the range of amplitudes for which the detector continues to exhibit square law response 2< 8 ( | | 2) 2 A i is amplitude of each frequency tone in the input signal, and Err is the maximum acceptable error for deviations from the square law. More information regarding the derivation of this equation can be found in Chapter 3. This inequality shows that the square law range can be extended if the overdrive voltage across the rectifying transistor is increased. Increasing the overdrive v oltage is effective only up to certain level s since it is associated with performance tradeoffs. When the overdrive voltage is increased, short channel effects become important and process variations are more significant However, more fundamentally, short channel effects cause the detector t o considerably deviate from the square law proportionality. Alleviating problems attributed to short channel effects given a certain bias point is made possible only by increasing the size of the transistor. Nevertheless this is not desirable since it dir ectly impacts the detectors loading effects on the DUT. Therefore, there is a need to develop methods to extend the detectors square law response dynamic range.

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80 The type III detector discussed in the previous section can extend the dynamic range without increasing the loading effects. Lets derive the detectors output in the saturation region to show how this works. The total DC drain current through transistors T 11 and T 12 when a high frequency input is stimulating the detector is = 2 1 2+ 22 + 1 2 The current through the replica circuit is = 2 ( + 1 ) 2 2 Solving for V s1s2 and applying the Taylor series expansion, the detectors output is 1 2= 1 4 2 ( + 1 ) 2+ 1 32 2 3 ( + 1 )2 4+ The (M+1) factor in the denominator of the equation above achieves the same result as increasing the overdrive voltage without the associated tradeoff of increased short channel effects. The (M+1) factor makes the higher order terms more negligible which in effect increases the RMS detection range. Figure 4 6 evaluates square law response through the calculation of the normalized linearity of the type I detector incre ased overdrive type I detector, and type III topology w ith M=1 and M=10 Figure 4 6 Normalized detection slope vs. input level 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 35 25 15 5 5Normalized Linearity Input (dBm) type I type I High Vov type III M=1 type III M=10

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81 The following shows how the normalized linearity plot is obtained. The detector is a square law device when its output is = 2/ w here Out is the DC output of the detector, A is the amplitude of high frequency input, and k is a constant which depends on the operating conditions of the detector In the decibel scale, the equation becomes 20 log ( ) = 20 log ( 2/ ) Since = 10 log 22 0 10 3 Z 0 is the system impedance. Then, = 2 Therefore, when plotting the detectors response in a decibel scale, the slope of the detectors response should be equal to 2 when its following the square law. The normalized linearity plot above is obtained by dividing the slope of the detectors response in decibel scale over the ideal slope of 2. Figure 4 6 shows that the type I detector s response deviates from square law linearity by 2 % starting around inputs higher than 12.5dBm. When the detectors overdrive is increased, deviation from square law occur s earlie r because of short channel effects as the 2% error threshold is reached for signal s that are larger than 15dBm The type III detector with M=1 conforms to square law linearity until 6.5dBm as seen in the figure above. And the type III detector with M= 10 increases the dynamic range further up to 2.5dBm. Additionally the benefits of this detector are not limited to an increase in the square law dynamic range. Better accuracy compared to increasing the overdrive voltage is possible as seen in Figure 4 7 which show s Monte Carlo simulations. Monte Carlo simulations of type III with M=10 were omitted since they are

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82 large ( =16%) relative to the other examples discussed above. The M=10 example was only introduced to corroborate the theory discussed above which stated that the square law dynamic range can be increased with increasing M Beyond these numbers which indicate the benefits of this topology, the most important as set of the type III detector is the introduction of another designdimension which enlarges the performance tradeoff space. Thus, this topology provides the designer with more freedom to customize and balance the detectors tradeoffs depending on the targeted application (a) (b) Figure 4 7 Monte Carlo simulation for detectors in the saturation region when stimulated with 35dBm input for (a) type I, (b) type I with increased overdrive, and (c) type III detector with M=1 0 5 10 15 Percentage (%)Output (V)Type I Mean 35.3uV Standard Deviation 5.8% 0 5 10 15 Percentage (%)Output (V)Type I High Vov Mean 16.1uV Standard Deviation 9.1%

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83 (c) Figure 47 continued Monte Carlo simulations implemented using the foundrys Skew file in Figure 4 7 show that the type III detector s response has a slightly higher standard deviation compared to the type I detector when biased at the same overdrive voltage. On the other hand, increasing the overdrive voltage leads to a higher sensitivity to process variations compared to using the type III detector as seen in Figure 4 7 (b). Furthermore, temperature sim ulations of this type III detector showed that the detector have the same accuracy as the type I detector of .65dB in the saturation region when both type I and type III are biased at the same overdrive voltage. Multiple Regions Detector As mentioned in the triode section in Chapter 2, the Meyer topology has a very weak response when biased in the triode region. Figure 4 8 shows measurement s of the RF to DC response i n the subthreshold and triode regions for the Meyer topology The figure shows that the triode response is approximately two decades smaller than the subthreshold measurements. 0 5 10 15 Percentage (%)Output (V)Type III M=1 Mean 17.7uV Standard Deviation 6.4%

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84 Figure 4 8 Subthreshold response vs. triode response Looking at the triode drain current equation, the current is quadratically proportional to the voltage V ds = 2 22 Therefore, some non linearity can be generated if the RF in put signal is applied at the drain or at the source. If the RF input is applied to the drain, efficient rectification in subthreshold and saturation is not possible. As a reminder, in the saturation and subthreshold regions, nonlinearities in the drain current were created from the currents higher order proportionality to the voltage V gs Thus, applying the RF input at the source will maintain strong nonlinearity for the detector in all regions of operations. The topology of this new detector is shown in Figure 4 9 Figure 4 10 compares measurements of this new det ector and measurements of the Meyer detector when they operate in the triode region. This new detector has much better performance in the triode region. The performance of this new detector is 0.1 1 10 100 1000 25 20 15 10 5 0 5DC output (mV)RF input (dBm) Subthreshold Triode

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85 expected to be similar compared to the Meyer topology in the saturation and subthreshold regions. T1 T2 IDCIDCVrfVbiasVbiasVDDVS1S2 Figure 4 9 New detector multiple regions detector Figure 4 10. P ower sweep of the RF input level for the Meyer and n ew d etector in triode When an RF input is stimulating this detector, the drain current for the saturation region and the subthreshold detector s is respectively 0.1 1 10 100 1000 25 20 15 10 5 0 5DC output (mV)RF input (dBm) Meyer Topology Multiple Regions Detector

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86 = 2 ( ) 2 = 0 ( ) These equations are almost the same as the Meyer detector equations with one minor difference; The RF input amplitude is negative since it i s applied at the source instead of the gate of the rectifying transistor. These two equations can be rewritten such as = 2 + ( + ) 2 = 0 + ( + ) Now, knowing that the detector is an amplitude detector which cannot discriminate phase differences, these equations will yield the same results as the Meyer topology. Thus, all the equations that were derived for the Meyer topology in the saturation and subthreshold regions can be applied to this new detector. In the triode region, the detectors response needs to be derived as t here is no symmetry between the gate and source in that region. When the high frequency content is filtered at the detectors output, t he DC drain current through the rectifying transistor T 1 becomes = 2 22 + 24 Solving for V s1s2 while ignoring the body effect, yields the following equation 1 2= ( 2 ) ( 2 )2 22 This equation is the same as the saturation equation (2 4) for the Meyer topology. The Taylor series expansion applied in Chapter 2 for the Meyer topology can be applied for this multiple regions detector when its operating in triode as well. 1 2 = 1 4 2 2 + 1 32 2 3 4 + (4 8)

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87 This expansion showed that the detector can be approximated as a square law detector if the higher order term s in equation (4 8) are ignored. Hence, this multipleregions detector can exploit some of the benefits attributed to the Meyer detector in the saturation region, namely the extended square law range, without the associated increase in power consumption. Figure 4 11. Simulation results of the multipleregions detectors response In the subthreshold region, the square law mode is recognizable for small signal levels; for large signal levels, the detectors response becomes l inear. The plot also shows dashed lines which represent ideal square law response to illustrate the range where the detectors response is also square law. When the detector is biased in triode region, the square law response dynamic range is larger as seen in Figure 4 11. The response of the detectors follows the ideal square law response for most input power levels. This is also confirmed in the measurement results below where the slope of the triode response in logarithmic scale is 2. 100 80 60 40 20 0 20 40 30 20 10 0 10 20Output (dBV)Input (dBm) Triode Subthreshold

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88 Figure 4 12. Measurement of the detector in logarithmic scale Additionally, the inequality which was derived for the saturation region Meyer detector showed that the square law dynamic range is directly proportional to the overdrive voltage of the rectifying transistor. 2< 8 ( | | 2) 2 This inequality can be applied to the triode multiple regions detector since it has the same RF to DC conversion as the saturation Meyer detector. Moreover, this square law dynamic range in the triode can be extended to larger values compared to the Meyer detectors since short channel effects become relevant in the saturation region for higher overdrive voltages which distorts the detectors response from square response. In the triode region, the drainto source voltage is low which minimizes velocity saturation effects [ 26 ]. Another advantage of this detector when operating in the triode is to have extended squarelaw performance without the required additional current consumption associated with the saturation region. However, the tradeoff is increased sensitivity to process variations (Monte Carlo) when operating in triode. Bear in mind that this y = 1.76x 19.64 y = 1.99x 18.29 65 55 45 35 25 25 20 15 10 5DC output (dBV) RF input (dBm) Subthreshold Triode

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89 problem is alleviated somewhat since the detector is useful because of its extended dynamic range, specifically for large signal levels where process variations are not as problematic in detection as for small signal levels. Monte Carlo simulations for the multiple regions detector in triode show ~7% standard deviation when the input power is 0dBm, and ~14% for 35dBm input; while the variations due to temperature have similar levels compared to the Meyer detector topology. Also because of the increased number of passives at the input of the detector, the bandwidth of the detector will be highly dependent on the attributes of these passive elements. Table 4 2 summarizes the tradeoffs of each operating region. The key advantage of this multipleregions detector is its flexib ility; the structure can be customized depending on its targeted application by only changing its operating point. Table 4 2 Trade off of each operating region Power consumption Accuracy Square law dynamic range Video bandwidth Saturation + ++ ++ +++ Subthreshold +++ +++ + + Triode +++ + +++ +

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90 CHAPTER 5 MIXED MODE DETECTION Introduction Measurements of mixedmode S parameters are essential for characterizing differential circuits and historically have been performed using 4port network analyzers [ 52] For BIST applications, replicating this architecture onchip is not possible as it would require a large chip area. Another way to measure differential circuits is to use a balun coupled to a singleended detector. However, this approach typically exhibits narrow band behavior, or involves a larger and more costly silicon footprint [ 53]. Such solution can also introduce more uncertainty in the measurement, making it less desirable in BIST applications. Figure 5 1 Conventional m easurement m ethod for d ifferential signals A number of publications used a detector based on a differential pair topology which does not account for commonmode signals or assumes commonmode signals are negligible [ 21], [ 24], [ 35 ], and [ 54 ] [ 58] The circuit in Figure 5 2 simply acts as two single ended amplitude detectors whose outputs are averaged together into one output. If this circuit is stimulated with the following inputs + = ( + 1) = ( + 2) The output of the detector is = ( ) + ( ) 2

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91 where f det () is the function the detector implements when it relates the RF input s amplitude to the DC output This output does not have any dependence on the phases 1 or 2 since the detector measures amplitude only. Differential pairs work well in their traditional implementation which is when the output is the same frequency as the input; the output will retain phase information in this case However, for amplitude detector s, the output is DC and has no phase information. Therefore, these pseudodifferential pair detectors cannot discriminate phase information making th em unsuitable for measurement of a signals differential component. T1 T2 IDCIDCIn+ VbiasVbiasVDD InOut Figure 5 2 Detector using a diff erential pair A design that is suitable for BIST applications which overcomes this limitation is presented in [ 59 ] and [ 60]. As seen in Figure 5 3 the classical diode detector is slightly modified by including an additional capacitor at the diodes cathode. Since the input to this detector is applied directly across t he diode junction, a subtraction function between the inputs two branches is performed. As a result, the circuit will reject any common-

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92 mode signal, and the rectified output is proportional to the difference between the two input branches which is equival ent to the differential component A diff = 2+ 2 2 ( 1 2) For a pure differential input where A=B and 1-2=180 the differential component simplifies to A diff =2 A For a pure commonmode input where A=B and 1-2=0 the differential component simplifies to A diff = 0 VrfVbias Vdiff (DC) + Figure 5 3 Differential d iode d etector Its worth mentioning that this circuit was intended in its original publication [ 60] for ports that are not referenced to a common ground in a six port junction circuit, more explicitly, ports where ground is not available. There was no clear indi cation that the circuit can be used for amplitude detection of differential circuits. [ 41] is the first one to identify the circuit as such, it leveraged this circuit and replaced the diode with a BJT transistor to make the detector compatible with a larger set of commercial semiconductor processes. Additionally, the idea of applying the input across a junction

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93 was adapted to the singleended Meyer detector topology [ 22] as shown in Figure 5 4 This structure is more robust to process and envi ronmental variations since it uses a current source instead of a resistor. The topology shown in Figure 5 4 was also introduced by a different author in [ 61 ]; however the patent reports only narrowband performance and describes the circuit as a peak detector. Detectors are known to be wideband devices; their bandwidth is limited by the parasitics in the path leading to the nonlinear junction capacitance [ 22 ]. These parasitics are small and become significant only around f t of the rectifying device. The circuit exploits the nonlinear properties of transistors, making rectification possible without prior am plification which extends the bandwidth of the detector into the mm Wave range. Additionally, the detector in [ 61] should be identified instead as an amplitude detector since it exhibits peak detection only for a limited range of input levels as will be shown in the following sections. IDCVrfVbiasVDD Vdiff (DC) + Figure 5 4 Bipolar d ifferential d etector Furthermore, for BIST applications, the detector should have minimal loading effects on the DUT. The impedance looking into the emitter is high if the bias current

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94 I DC is low. However, this circuit might present a slight impedance imbalance between the two branches of the port under test [ 41] [ 61] further enhanced t his differential detec tor by developing a balanced version. As seen in Figure 5 5 the circuit in Figure 5 4 is duplicated and the two branches of the input are switched. The input across the baseemitter junction of Q1 is V r f The baseemitter junction of the second transistor Q2 sees V r f The refore, each branch of the port under test sees one base and one emitter; hence the name balanced detector. IDCVrfVbias Vdiff (DC) + IDCVrfVbiasVDD + Q1Q2CLPF Figure 5 5 Balanced differential d etector The advantage of the balanced detector is a balanced load to the CUT. However, the disadvantage is a bigger circuit area, especially the four input coupling capacitors. This section introduced amplitude detectors capable of measuring the differential component; where differential detection is obtained as the input branches are appli ed across the base emitter junction to replicate the subtraction function. If the input is applied across transistor branches which do not perform the subtraction function, true

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95 differential detection is not possible as was the case in the topology shown [ 62]. Hence, investigation of the conditions for which differential detection is possible is necessary; especially since transistors can be biased in more operating regions compared to diodes The next section provides a detailed analysis of the differential detector which was lacking in the previous literature [ 41 ] [ 61 ] as well as measurement results. Key Details for Design of Differential Detectors Alternate test methods which use amplitude detectors usually belong to two categories. The f irst method treats detectors as implicit feature extractors and relies on statistical analysis to estimate DUT specifications from detector measurements [ 23 ]. The sec ond school of thought identifies detector structures whose measurements can be directly mapped to the DUT specifications; for example, [ 24] directly extracts gain and IIP3 of a DUT using rms detectors without resorting to learning steps. Both methods need the detectors response to have strong correlation to the DUT specifications. This sometimes requires significant pre or post processing for the first method; the sec ond methods drawback is usually the long list of assumptions required to achieve the direct correlation. In this section, the focus is to present simple design guidelines to dispel the disadvantages associated with the second method as well as sources of error to the detectors response, and finally characteristics of the detectors response. The dominant source of rectification, when a BJT transistor is used, stems from the nonlinearities generated in the collector current. The Ebers Moll equations express the currents of a BJT transistor in all its operating regions [ 26]. The collector current is = 1 1 In the forward active region, the equation simplifies to

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96 = When a detector is stimulated with a high frequency input, this equation becomes = + ( + 1 ) ( + 2 ) (5 1) Equation (5 1) shows how the subtraction operation occurs when one of the input signal branches is applied to the base and the other input branch is applied to the emitter of the BJT transistor. When a series expansion of the exponential term is implemented, nonlinear terms are generated including a DC value that is proportional to the input difference. Conversely, in the other operating regi ons, the second term in the Ebers Moll equation is significant rendering differential detection impossible. The following equation depicts the collector current when stimulated with a high frequency input. It shows a second term that is not proportional to the differential component of the input signal. = + ( + 1 ) ( + 2 ) 1 +( + 1) 1 (5 2) Figure 5 6 Differential detectors response to pure differential and pure common mode stimulus respectively 0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.2 0.4 0.6 0.8 1 1.2Detector's output (V)Vce Common mode input Differential input Saturation Forward Active

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97 When biased in the forward active region, the detector responds to the differential stimulus and is indifferent to the common mode stimulus a s expected. As Vce across the rectifying transistor is decr eased, the detector no longer exhibits properties that are associated with true differential detect ion as predicted by equation (5 2) Also, its worth noting that eve n in the forward active region, any deviations from the subtraction function between the inputs two branches will create cross mode terms in the detectors. Cross mode terms for this detector are defined as a differential response to a common mode stimulus; ideally, the response to commonmode stimulus should be zero for a true differential detector. In reality, signal distortions can be produced because of imbalances between the base and emitter paths into the rectifying transistors; these can be minimized by adopting careful design practices. Additionally, sources of nonlinearity are not only limited to the baseemitter junction; instead, any second order effect or junction in the transistor might cause an undesirable rectification. When the high frequency inputs two branches are not referenced to each others across all the sources of nonlinearity, imbalances are created which generate the cross mode terms. For example when the Early effect is taken into account, equation (5 1) becomes = + ( + 1) ( + 2) 1 + ( + 2) If V A is small, an imbalance is introduced since this equation deviates from ideal subtraction necessary for differential detection. Alternatively, its possible to reduce this imbalance, for example, by shorting the base and collector of the rectifying transis tor and slightly modifying the design. The simplified equation (5 1) ignores these second order effects as they are negligible when the rectifying transistor is biased in the forward

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98 active region. This assumption is confirmed by the s imulation shown in Figure 5 6 and measurement results in Figure 5 7 ; both Figures show a negligible commonmode response compared to the differential response. Figure 5 7 Measurement r esults of the BJT b alanced differential d etector. Furthermore, rectification depends on another parameter besides the operating region of the detector; the inputs amplitude affect s the type of response the detector exhibits. Since it was est ablished that this detector is only an extension of the single ended Meyer detector, the output equations derived for the single ended Meyer topology in [ 27] can be a pplied to the differential detector as well. The outputs are derived for designs that include a replica circuit which is usually used as a reference to cancel the quiescent DC offset voltage at the output of the detector. For small signal levels (lower than 20dBm), the differential detector output is ( ) = 24 For large signal levels (larger than 10dBm), ( ) = 2 2 (5 3) 0 100 200 300 400 500 40 30 20 10 0 10 20DC output (mV)RF input (dBm) Common mode Input Differential Input

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99 These equations confirm that detector is an RMS detector for small signal levels and a peak detector for large signal levels as the logarithmic term in equation (5 3) can be ignored when the inputs amplitude is large. These equations as well as the plot in Figure 5 8 confirm that the detectors response change with the operating conditions as it performs an RMS or peak measurement depending on the input signal level. Figure 5 8 Detectors dependence on the inputs amplitude As seen in the Figure 5 8 when the detectors response is plotted in a logarithmic scale, the slope of the response is twice as high for smaller inputs compared to the slope at higher input levels. A slope of 2 in the logarithmic scale indicates that the detectors output is proportional to the square of the input which is equivalent to RMS detection. A slope of 1 means that the detector is a peak detector since its output is linearly proportional to the amplitude of the input. Mixed Mode Detectors The true differential detection potential of the topology was introduced in the previous section. In this section, an additional improvement is introduced by also enabling measurements of the commonmode component of a port under test. This 70 60 50 40 30 20 10 0 40 30 20 10 0 10Output (dBV) Input (dBm) Square Law Linear

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100 added capability will allow more insight into the circuit such as measurements of puremode gains and cross mode gains. For example, if the measured differential gain of a circuit was lower than expected, its not possible to troubleshoot using differential measurements only. Conversely, if the commonmode signals amplitude is known, then diagnosis of certain faults such as coupling from adjacent circuit blocks or ins ufficient differential gain in the DUT itself becomes possible. T1 T2 IDCIDCVrfVbiasVbiasVDDVcm (DC) T3 IDCVbias VDD Vdiff (DC) + Vrf + Vx Figure 5 9 Mixed mode detector Figure 5 10. Simplified diagram of mixedmode detector

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101 With a careful look at the circuit in Figure 5 5 the V dif f (DC) node is a virtual ground for differential signals only. For commonmode signals, the capacitor C LPF shorts that node in Figure 5 5 With a small design change, the signal in that node can be routed to another detector to measure the amplitude of the commonmode component. The modified circuit in Fig ure 5 9 shows how the commonmode signals amplitude A cm can be detected. = 2+ 2+ 2 ( 1 2) 2 Node V x in Figure 5 9 also represents the differential DC output and should be accessible for measurement purposes as seen in the Figure. Another modification was implemented in this design cycle. To make this det ector compatible with standard bulk MOS processes, the BJT transistor s were replaced by MOS transistor s. As seen in Figure 5 9 the circuit has two DC outputs. In addition to the DC differential output, there is a DC commonmode output. The added capability of measuring commonmode signals was implemented without increasing the loading effects on the DUT. The circuit also maintains its symmetrical structure to present a balanced load to the DUT. The 3D plot in Figure 5 11 shows that the differential DC output responds to pure differential RF stimulus only. Even when the commonmode RF stimulus level is swept, the differential DC output is constant. Now, for the commonmode response of the mixed mode detector, the circuit responds to commonmode RF stimulus only as shown in Figure 5 12.

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102 Figure 5 11. Differential response to mixedmode stimulus Figure 5 12. Commonmode response to mixedmode stimulus Similar to the BJT version of the differential detector, the MOS version cannot perform differential detection in all the operating regions. When the detector is stimulated with a high frequency input, the drain current when the rectifying transistor s are biased in the saturation (5 4) subthreshold (5 5) and triode (5 6) respectively is

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103 = + ( + 1 ) ( + 2 ) 2 (5 4) = 0 + ( + 1 ) ( + 2 ) (5 5) = + cos ( t + 1 ) cos ( t + 2 ) cos ( t + 2 ) cos ( t + 2 ) 2 (5 6) with L W C Kox2 As seen in the saturation and subthreshold equations (5 4) and (5 5) differential detection is possible since the drain current is a function of the difference between the inputs two branches. In the triode region, the drain current in (5 6) has some error terms that are proportional to only one of the inputs branches. Thereby, differential detection is not possible in the triode region. Also, long channel models are used in order to simplify the analysis. Differential detection is still possible since equation (5 7) which accounts for short channel effects (velocity saturation) is still balance d between the gate and source [ 26 ]. A lso, mobility degradation due to lateral fields has balanced effects on differential detection. L V V V V K Ic t gs t gs d1 '2 (5 7) where c is the critical electrical field. Furthermore, in subthreshold and triode operating regions, short channel effects are negligible. For common mode detection, the input branches are summed before they are measured using a single ended detector. [ 28 ] shows that single ended detection is only possible in saturation and subthreshold when the input is applied to the gate of the rectifying transistor. In addition, the cross mode terms which occur in this mixed mode detector are not limited to the differential response to common mode stimulus as was the case for the

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104 topology in Figure 5 5 ; there is another cross mode term which consists of the commonmode response to differential stimulus. T his term depends mostly on imbalances in the common mode signal path. It i s not affected by second order non linear effects like the differential detec tor as commonmode detection exploits a single ended structure Furthermore, The MOSFET differential detector portion exhibits more significant cross mode detection compared to the BJT detector in the previous section Second order nonlinear effects such as the Early effect were shown in the previous section to cause these cross mode terms in the differential detector topology. The MOSFET design was implemented in a non epi (low doping) substrate making channel length modulation effects substantial T he Early effect is inversely proportional to the doping levels in the channel [ 26 ]. While the Bipolar design was designed using SiGe HBT devices in a BiCMOS process wh ich typically has a higher base doping concentration [ 63 ]. As mentioned in the previous section, it is possible to minimize these effects by modifying the topology and connecting the gate of the rectifying transistors to their drain. Below are the equations showing the detectors response in different operating regions. The body effect was ignored when these equations were derived. In the saturation region, the output is ... 32 4 ) (3 4 2 ov i ov i iV A V A DC V (5 8) where subscript i can be replaced by subscript diff or cm and V ov is the overdrive voltage across the rectifying transistor ( V gs V t ) When the higher order terms are ignored in equation (5 8) the detector performs rms measurements. In the subthreshold region, for small input levels, the output is

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105 T i inV A DC V 4 ) (2 For large signal levels, the output is T i T i inV A nV A DC V2 ln 2 ) ( Figure 5 13. Picture of mixedmode detector This circuit was fabricated in an IBM8HP process. It occupies an area of 0.59mm2 including pads, 0.045 mm2 without pads. The detector cons umes 0 .5mW of static power including power consumed by a current reference circuit; otherwise, power consumption was a mere 8 W when accounting for the detection circuit only The detectors output settling time is approximately 100ns. The detectors measured dynamic range is at least 30dB. This mixed mode detector was measured at different frequencies. The detector was simulated to work at millimeter wave frequencies up to 70GHz, which is the range where the detectors mixedmode reflection coefficients (Sdd11 and Scc11) remain below 10dB when refere detector can be embedded into a DUT without any customization; on the other hand, the detector s load should be integrated into the matching network design at higher frequencies. The degradation in the frequency response was mostly due to the quality of the passive circuits that were used. Figure 5 14 shows measurements of the

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106 differential DC response when the detector is stimulated with a pure differential and pure commonmode signal. The detector only responds to pure differential stimulus. Figure 5 15 fo r measurements of the common mo de DC output shows the opposite behavior of differential DC output. The response stays near zero when the input is a pure differential signal. Figure 5 14. Measurement of differential DC response. Figure 5 15. Measurement of common mode DC response 0 100 200 300 400 500 600 30 25 20 15 10 5 0DC output (mV) RF input (dBm) 6GHz Differential In 6GHz Common Mode In 0 50 100 150 200 35 30 25 20 15 10 5 0DC output (mV) RF input (dBm) 20GHz Differential In 20GHz Common Mode In

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107 In Figure 5 14 and Figure 5 15 small cross mode detection is evident at higher input levels and increases as the signals frequency is increased. Besides errors which are inherent to the detector, a portion of this error is due to the measurement setup where it was difficult to supply pure mode stimulus all the way to the probe tips. There are commercial solutions to solve this issue such as Agilents N5242 four por t network analyzer which offers automated calibration of the measurement setup [ 64 ]. [ 65] is another solution that presents a manual method to generate pure mode stimulus. All the meas urements in this chapter are presented for the purpose of verifying the functionality of this circuit and should not be taken for absolute values since calibration of the test setup to verify the detector was not possible at the time of measurement. Furthermore, d ue to instrumentation constraints, mixedmode measurements were limited to 20GHz, whereas singleended measurements were implemented up to 40GHz to verify the circuit further Finally unlike previous designs that ignore the common mode signals th is new design outputs a DC voltage that is proportional to the true differential component and another DC output that is proportional to the true commonmode component Calibration Since these detectors are an enhanced version of the Meyer single ended detector, all the merits associated with the single ended topology can be extended to the detector topologies presented in this chapter The output equations derived for the detector show that first order immunity to process variations and temperature variat ions is inherent within the detectors topology. First, similar to the single ended detector, a DC offset which arises between the rectifying part of the detector and the replica needs to be taken into account. This offset

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108 can severely limit the dynamic range of the detector if its not removed. [ 21 ], [ 44 ] states that this offset is constant and remains independent of the high frequency input in the single ended detector topology. This observation can be upheld for mixedmode detectors as well since the DC offset is not dependent on the high frequency input. This offset is removed by performing one time DC measurement at the beginning of testing. Monte Carlo simulations were implemented using the foundrys Skew file and variations at the differential DC output V diff (DC) had a standard deviation of 4.5% when the detector was stimulated with a differential input of 35dBm; this standard deviation value means the detector will have 1dB accuracy in 99% of cases. The detector experiences the highest variations when the input power is low; hence, the use of 35dBm to measure the maximum amount of variations. For the commonmode output, the standard deviation is 6.4% when the input was pure commonmode and 1dB accuracy is possible for only 93% of cases. The standard deviation is higher for the common mode detector compared to the differential detector because of the number of additional passives in the commonmode signal path. Nevertheless, more fundamentally, the detectors accuracy is only as good as the current source used in the design. A MOSFET peaking current source was used because of its potential to generate low current values. The MOS peaking current source was biased at an operating point which minimizes the detectors temperature dependence; [ 66 ] showed that for MOS transistors there is an operating point where the mobility temperature dependence cancels the effect of temperature on the threshold voltage. The detectors overall acc uracy was better than 1dB in the commercial temperature range of 0C to 70C. Regrettably, at the time of circuit tapeout, process variations for the current

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109 source were not fully considered and the final design was not robust to process variations as the simulated standard deviation of the current generated by the source was 28%. Even with this high value, the standard deviation of the detectors response was much lower than the standard deviation of the current source which attests to detectors immunity to variations. When the detector is simulated with an ideal current source, the variations are much lower below 2%. When only mismatch (intradie var i ations) is considered in Monte Carlo simulations, the standard deviation is below 1%. Since intradie variations are smaller, an increased accuracy can be achieved when an extra detector whose input can be probed is included to be used as a reference for calibration purposes. Calibration of this detector is also possible by using a single ended input which s implifies the calibration process. Using single ended stimulus is equivalent to applying a differential and a commonmode signal simultaneously such as A single ended =A diff /2+A cm /2 This results in calibrating the differential detection portion in addition to the common mode detection portion at the same time. Furthermore, the detector can be calibrated by applying a low frequency single ended input at the V diff (DC) output using a bias T in an unconventional way. The choke port of the bias T can be used to m easure the DC output of the detector and the low frequency signal can be coupled through the capacitor port. When detectors are embedded in a DUT, high frequency external access to the detector s inputs for calibration purposes is not possible. More elabor ate calibration methods are also possible as process variations become important in deeply scaled process technologies. Several methods were developed to calibrate single ended amplitude detectors; they can be extended to the

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110 mixed mode detector since most variations are associated with the active elements in the topology. [ 47] relies on DC signals only for calibrating the detector by using statistical analysis to map a DCto DC response into the RF to DC response. [ 29 ], [ 32], and [ 43 ] use statistical analysis to account for process variations by calibrating the DUT and the detectors simultaneously. The methods rely on a defined dictionary that can be built either from simulations or actual measurements assuming the DUT can be measured using conventional methods; then a mapping engine can estimate the specifications of the DU T from the alternate measurement space. The alternate test methods are immune to process and environmental variations as long as there are strong correlations between the alternate test measurement space and the DUTs specification space.

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111 CHAPTER 6 S YSTEM A PPLICATIONS Introduction The purpose of this chapter is to introduce concrete examples to clearly demonstrate the effectiveness of the amplitude detectors reported in the previous chapters. First, a setup that uses single ended detectors to measure specifications of an LNA is disc ussed in the next section. Another section, discusses multi port reflectometers that employ differential and singleended detectors. This chapter sheds more light on the numerous tradeoffs discussed previously and indicates examples of suitable applicatio ns for each type of detector LNA Example As seen in Figure 6 1 two detectors can be used to measure gain and compression point P 1dB of a Low Noise A mplifier (LNA). Similar topologies were previously published in [ 13], [ 24 ], [ 31 ], [ 41], [ 43 ], [ 54], and [ 67] [ 69 ] In addition to gain and compression point, other parameters can be estimated through further analysis of the amplitude detectors output. For example, [ 69] estimated the Noise Figure and reflection coefficient relying on simplified equations that are accurate for specific conditions discussed in more details in [ 70 ]. [ 31] extracts Noise figure, and P 1dB by applying wavelet analysis on the detectors output when the LN A is stimulated with a two tone stimulus. Statistical regression analysis was also employed in [ 43 ] to estimate IIP3 in addition to the previous specifications. The s timulus in that methodology was simplified by using a singletone input; however, this entailed use of two types of detectors at the output of LNA. [ 54 ] uses two tones stimulus and non linear mapping to extract TOI as well; moreover, [ 24] improved upon the method reported in [ 54 ] by

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112 deriving an equation which directly relates the detectors output to TOI without resorting to any statistical methods. Thus, there is abundant literature that discusses the capabilities of amplitude detectors. In this section, the focus is to delve into the details of various sources of errors that might corrupt estimation of the specifications from the setup shown in Figure 6 1 Among other errors, the discussion is mai nly limited to errors that stem from the inherent workings of the amplitude detector. As previously discussed, the detectors response varies with the operating region, different signal levels, and signal shapes. Therefore, what has lead to this detectors flexibility can easily lead to its downfall if not carefully considered. Whether these alternate test methods use implicit or explicit detectors, th e strong correlation needed between the detectors measurements and the DUT specifications might not be maintained when the detectors type of response changes. The detectors response need to have a large dynamic range to cover a wide range of applications without necessitating complex customizations. Accordingly, the advantages of each of the detector topologies discussed in the previous chapters are introduced in this context. Figure 6 1 Detectors for m easuring gain and compression of an LNA

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113 Its worth mentioning that the discussion in this section is limited to gain measurements for the sake of simplicity. Gain is one of the simplest DUT specifications; if it is not accurately estimated, none of the other specifications can be predicted. [ 68] measures the gain by including an amplifier after det1 and variable gain amplifier (VGA) after det2. For a given input power, this method estimates the gain of the LNA by sweeping the gain of the VGA. To measure the compression point, this method might be inefficient since sweeping the gain of the VGA is necessary for every input signal level. Additionally, [ 68] does not explicitly state the dynamic range of the reported alternate test setup. The P 1dB compression point estimated using the method published in [ 67 ] is accurate within 1dB of the actual compression point. However, this accuracy is achieved within a limited dynamic range making the method prone to errors [ 67] sweeps the input power level to extract gain and compression point by comparing the respective input powers where det2 and det1 output the same DC value. For example, given that det2 outputs a DC val ue x at input power P a and det1 had that same DC value x when the input power was P b then the gain of the DUT is P b P a This method has a limited dynamic range because, as shown in the previous sections, the detectors type of response varies with the input signals amplitude. If the input signal level is in one range (i.e. square law subthreshold mode) and the output sig nal level is another range (i.e. linear subthreshold mode), then the gain extracted using this method is not accurate. This can be seen in Figure 6 2 which shows that gain estimated using the method described above (blue curve) starts deviating from the actual gain (red curve) as the input signal is increased.

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114 Figure 6 2 Actual gain compared to different methods used t o estimate the gain Alternately, higher order fitting of the detectors response yields accurate estimations of the DUT specifications. As seen in Figure 6 1 the first detector can be characterized as it is connected to the signal source. By sweeping the input signals power level, the RF to DC conversion equation of the detector can be obtained. Assuming that det2 is well matched to det1, the two detec tors will have the same RF to DC conversion equation. The next step is to derive the inverse function of the RF to DC conversion equation. Finally, by measuring the DC value of det2, the gain of the DUT can be calculated. Figure 6 2 shows that when the detectors response is fitted with a 5th order regression equation, accurate estimation of the LNAs gain is obtained by following the steps discussed above. On a side note, higher order regression analysis might mean longer characterization time unless there are good matching conditions across the wafer, temperature stability, and good biasing strategy. Aside from the process variations issue, all the other conditions are required to maintain good accuracy for conventional commercial test setups as well. Provided that these conditions are met, the time 0 2 4 6 8 10 12 40 30 20 10 0Gain (dB) Input Power (dBm) Actual Gain Assume Same Response type 2nd Order Regression 5th Order Regression

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115 required to compute or retrieve from a memory module the RF amplitude given a DC output from det2s should be considered as it can be substantial. Higher order regression is possible only when the processing unit experiences some idle time margin. Overall testing time consists of the time required to setup the measurement in addition to the time needed for the actual measur ement. For example, the index time of high performance membrane probes is in the tens of milliseconds; a settling time associated with any change to the test stimulus also exists [ 1 ] Therefore, the time margin required for the test setup dictates the accuracy that can be achieved with this alternate test method when higher order regression is needed. Achieving a larger detection dynamic range without sacrificing test time is possible by using some the strategies or structures reported in the previous chapters. Figure 6 2 also shows that 2nd order regression accurately predicts the LNAs gain at low power levels. This is consistent with the theory discussed in Chapter 2 which stated that the detectors response follows the square law for small signal levels and deviates from that type of response as the input signal level is increased. Chapter 3 uncovered that the squarelaw response dynamic range can be increased by increasing the overdrive voltage across the rectifying transistor. This is beneficial since the LNAs gain can be extracted over a large dynamic range without resorting to higher order regression analysis. Figure 6 2 showed that gain is accurately estimated for the four curves as long as the input power is small; however, accurate estimation of P 1dB depends on the method that is used. On the other hand, if the LNAs gain is larger than the amplitude detectors dynamic range, even estimation of the gain is no longer possible. Figure 6 3 shows that the dynamic range of the alternate test method can be increased by raising

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116 the overdrive voltage across the rectifying transistor in the detector. Although, as discussed in Chapter 3 there is limit to this method since short channel effects become dominant when the overdrive voltage is too high as seen in both Figure 6 3 and Table 6 1 Figure 6 3 Error between ideal gain and gain estimated from detectors that are biased at different overdrive voltages Table 6 1 Maximum gain estimated by the detectors within .5dB accuracy V ov 1 00mV 0 V 100mV 200mV 30 0mV Gain 27dB 31 dB 38dB 34 dB 32.5dB In Chapter 4, novel detector topologies were introduced to minimize the ranges where the detectors exhibited nonideal response. Among the many benefits of the novel type III detector, it is capable of increasing the square law dynamic range even further by circumvent ing short channel effects. Figure 6 4 and Table 6 2 show the maximum gain that can be measured by the detectors within .5dB accuracy by inc reasing M a factor introduced in Figure 4 2 4 2 0 2 4 6 8 10 0 10 20 30 40 50 60Error (dB)Amplifier Gain (dB) Vov= 100mV Vov=0mV Vov=100mV Vov=200mV Vov=300mV

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117 Figure 6 4 Error between ideal gain and estimated gain from type II I detectors Table 6 2 Maximum gain estimated by the typeIII detectors within .5dB accuracy M 0 1 2 4 6 Gain 31dB 3 5dB 38.5dB 46.5dB 49.5dB Additionally, Chapter 4 also introduced a novel topology advantageous because of its flexibility; the multiple regions detector can operate in subthreshold, saturation, and triode where each of these operating regions is associated with certain tradeoffs which were summarized in Table 4 2 For example, operation in triode has the largest square law dynamic range as seen in Figure 6 5 since short channel effects are minimal in that region compared to operation in the saturation region. Also, static power consumption is lowest in the triode region which is indicated by the numbers adjacent to the plots in Figure 6 5 However, triode detectors have a long settling time which increases the overall test time or lowers the video bandwidth and they possibly suffer from a higher sensitivity to process variations compared to operation in the saturation and subthreshold regions. 2 0 2 4 6 8 0 10 20 30 40 50 60Error (dB)Amplifier Gain (dB) M=4 M=6 M=1 M=2 M=0

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118 Figure 6 5 Error between ideal gain and estimated gain from the multipleregions detectors Finally, both the type III and multipleregions detectors extend the square law dynamic range which enables lower test time and accurate measurements of the DUT specifications for a larger set of applications. The difference between the two detectors is that type I II is advantageous in high frequency circuits since it has less parasitics at its input path compared the multipleregions detector; it also offers extended dynamic range without decreasing the video bandwidth. Therefore, it is appropriate for production t esting that requires complicated measurements such as P 1dB and IIP3. On the other hand, the multipleregions detector offers flexibility since the same structure can be used in different situations. For example, in characterization test where time is not of the essence, operation in triode is advantageous since extended dynamic range is achieved in that operating region. When the product is qualified for production, the multiple region can be operated in the saturation region because of its fast settling t ime. Provided that there is a high correlation between gain and IIP3, the larger dynamic range in triode might not be necessary in production test. Now that the tradeoffs of each operating regions were dissected, there is a limitless number of applications where 2 0 2 4 6 8 10 0 10 20 30 40 50 60Error (dB)Gain (dB) Triode Saturation Subthreshold 1x ( nW range) 4000x 12x

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119 the flexibility offered by these detectors is beneficial. Furthermore, all these concepts can be projected onto the mixedmode detector from Chapter 5 when the DUT is a differential with the exception of operating in triode as it was determined in Chapter 5 that differential detection is not possible in that region. The type III topology can be adapted to the differential detector; however, it requires the use of inductors. Multi port Reflectometers I ntroduction Measurement of S parameters which characterize the DUTs matching, gain, and reverse isolation is essential in RF circuits. S parameters are represented by complex vectors with amplitude and phase information; t hey are commonly measured using vector network analyzers. Figure 6 6 shows a simplified architecture of a network analyzer. This high level diagram shows the main building blocks of a network analyzers port which consists of coup lers and detector structures. Receiver /Amplitude & Phase Detectors Source Test Port Figure 6 6 Vector network analyzer port An alternative to this architecture is the multiport reflectometer which does no t employ phase detectors. The topology uses a multitude of amplitude detectors to calculate magnitude and phase of S parameters This allows the structure to achieve a wider bandwidth compared to the heterodyne architecture implemented in network analyzers; however, the simplicity of the multi port hardware is compromised by

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120 complicated calibrations which are required to account for imperfection of the multi port topology. Additionally, [ 71] st ates that there is a tradeoff between the power dissipated in the multi port topologies and their bandwidth. For alternate test applications such as the tester on chip onboard or the tester onchip onprobe discussed in Chapter 1, multiport reflectomete rs are advantageous compared to the tradeoffs associated with heterodyne architectures. Multi port techniques were subject to great deal of research since the publication of classic papers from NIST in the 1970s [ 72 ] Moreover, multi port reflectometer circuits are attractive in many applications beyond the one discussed here because of their low cost, wide bandwidth capability [ 73]. In this chapter, the discussion is limited to the introduction of this family of circuits especially since the focus of this chapter is to demonstrate applications for the detectors that were reported in the previous chapters. To sum up, the intent is to use these multi port reflectometers as a vehicle to demonstrate the effectiveness of the amplitude detectors. Figure 6 7 shows a six port reflectometer (SPR) structure suitable for on chip integration that was published in [ 74 ]. The phase shifter is implemented using two inductors and a capacitor as seen in Figure 6 8 [ 74] Amp Det Source Test Port Phase Shifter Amp Det Amp Det Amp Det Figure 6 7 Six port reflectometer port

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121 L L C Figure 6 8 Phase shifter The coupler is implemented using a resistive structure as seen in Figure 6 9 Where, = 0 2 (6 1) Port1 Port3 Ra Rc Port2 Port4 Figure 6 9 Wheatstone bridge In Figure 6 7 port 1 of the Wheatstone bridge is connected to the signal source; and port2 is connected to the phase shifter. [ 59 ] reports an S parameter matrix for this bridge. [ ] = 0 1 1 + 0 1 1 + 0 0 1 1 + 0 0 0 1 1 + 0 1 1 + 0 0 0 1 1 + 0 0 1 1 + 0 1 1 + 0 0 (6 2)

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122 Compact Multi Port Reflectometers Besides the motivations introduced in the previous section, this opportunity is exploited to propose novel multi port topologies which might be beneficial for the proposed alternate test methodologies; though, it is difficult to envision employing these si xport networks for BIST purposes because of their large size and loss introduced in the signal path. Even a novel SPR topology introduced later in this chapter which is more compact and less lossy than the circuit in Figure 6 7 occupied .5mm2 for a targeted operation around 5GHz using a 130nm technology. Therefore, it is hardly justifiable to use Multi port circuits in BIST knowing that many specificat ions can be measured by amplitude detectors only. Yet, SPR circuits are suitable for tester onchip onboard or onprobe solutions as mentioned previously. Given these applications, design in CMOS is no longer a restriction since these alternate test circu it s are not targeted for embedded test As mentioned in Chapter 5, SiGe HBT differential detectors are superior over their bulk MOS counterparts because they are less sensitive to early voltage effects. Hence, SiGe HBT detectors were employed in all the ci rcuits that are introduced in this section. By inspecting the S parameter matrix (6 2) port3 is isolated from port2; while a portion of the signal from port1 is transmitted to port3. Also, port4 is isolated from port1 despite the fact that it measures a portion of the signal incident from port2. Then, a detector in port3 can measure the magnitude of the forward wave a1 incident from port1 and a detector in port4 can measure the magnitude of the wave a2 reflected from port2 as seen in Figure 6 10. Thus, two differential detectors are sufficient to measure the magnitude of the reflection coefficient; on the other hand, two single ended detectors embedded at any nodes of the Wheat stone bridge network cannot measure the

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123 reflection coefficient since there are three unknowns a1, b2, and a 2 ( b 1 =0 since S11=0 from matrix (6 2) ). Source ZTest Port Ra Rc Port4 Port1 Port2 Det Z0 Port3 Det Z0 a1 b1 a2 b2 Figure 6 10. Wheatstone bridge for measurement of S parameters magnitude The circuit in Figure 6 10 is equivalent to a single port in a scalar network analyzer which measures the magnitude of S parameters. The following equations which characterize the circuit in Figure 6 10 can be solved to express the magnitude of the reflection coefficient 2 = 21 1 | 2 | = | 42| | 1 | = | 31| where Sxx are the S parameters from matrix (6 2) and Arev is the amplitude measured by the detector across port4 in Figure 6 10, while Afrwd is measured by detector across port3. The equations simplify to | | = 2 2 = 21 (6 3)

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124 Equation (6 3) shows that this network can only measure the magnitude of the reflection coefficient. This circuit was simulated with different loads and the results are summarized in Table 6 3 and Figure 6 11 showing that a worst case deviation from the ideal values of 1.6%. Table 6 3 Comparing ideal and estimated reflection coefficients Actual .5 .5 .5 58 .5 58 .5 122 .5 122 Estimated .4995 .4494 .492 .507 .492 .507 Figure 6 11. Smith chart showing ideal and estimated reflections coefficients To measure the magnitude and phase of the reflection coefficient, multi port reflectometer theory dictates the use of at least three amplitude detectors; ad ditionally, a fourth detector is used to overdetermine the system so that it is robust to imperfections. The placement of the additional detectors onto the Wheatstone bridge as shown in Figure 6 12 allows measurements of the reflection coefficient over only two quadrants in the complex plane. This circuit can only resolve phase information from 0 to 180 since differential detectors have some phase ambi guity as they output the same value for signals with opposite phases.

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125 Source ZTest Port Ra Rc Port1 Port2 Det4 Z0 Det3 Z0 Det6 Det5 Figure 6 12. Circ uit that measures S parameters magnitude and absolute value of phase Multi port reflectometers also require elements that can shift the phase of the waves across the multitude of amplitude detectors to measure the complex reflection coefficient. The SPR structure shown in Figure 6 7 dealt with this issue by using a phase shifter. In this dissertation a new circuit which combines the phase shi fter into the Wheatstone bridge is shown in Figure 6 13 Source ZTest Port L C Port1 Port2 Z0 Z0 Det4 Det3 Det6 Det5 Figure 6 13. Compact six port reflectometer

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126 Figure 6 13 shows that inductor L and capacitor C replaced resistors Ra and Rc from Figure 6 12 respectively. To maintain the properties of the Wheatstone bridge, the following equation need to be satisfied = 0 2 = 0 2 (6 4) This new SPR can fully measure phase and magnitude of and contains a lower number of passives compared to the other structure. The topology shown in Figure 6 7 has four resistors, two inductors and one c apacitor for the bridge and phase shifter. This proposed structure has just two resistors, one inductor and one capacitor. Moreover, multi port reflectometers, such as the circuit in Figure 6 7 somewhat deviate from the traditional definition of a reflectometer since they synthesize forward and reflected waves instead of directly measuring them. The circuit in Figure 6 13 reverts back as it embodies the traditional definition of a reflectometer; the circuit also relies on multi port theory since it uses amplitude detectors only. [ 75 ] specifically argued against multi port circuits that are based on the traditional reflectometer topology stating that the circuits dynamic range is entirely dependent on the dynamic range o f the detectors that are used. For alternate test applications that do not require 100dB dynamic range such as the applications targeted in [ 75], use of the structur e in Figure 6 13 is advantageous because of its compact structure. Additionally, the structure still maintains one of the key conditions for robust multiport design such as correction for inputs power fluctuations; multi port theory is significantly simplified when one of the ports is proportional to the incident power [ 75 ]. In the most general case of SPR circuits a 6x6 matrix constituted from the interactions between each of the ports incident and reflected waves needs to be solved

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127 to synthesize the waves at the port under test [ 73]. However, if the design of the SPR is constrained to certain conditions such as the ones discussed above, a graphical method can be used to solve for the reflection coefficient of the port under test. Figure 6 14. Graphical method to measure the reflection coefficient Each SPR can be characterized by its q points which are inherent to the circuit and are independent of the characteristics of the port under test [ 75 ]. The q points cannot be collinear as was the case of the circuit in Figure 6 12 because two possible values of are obtained. As seen Figure 6 14, the q points of the circuit in Figure 6 13 are not collinear, thus, allowing measurements of the reflection coefficient since the three circles intersect at single point. Only readings from the amplitude detectors, which set the radii of the circles show n in Figure 6 14, are needed to estimate the reflection coefficient of the port under test. This method was applied to the circuit in Figure 6 1 3 and the results are summarized in Figure 6 15. The circuit estimates the reflection coefficient of a port under test within a certain error which can be minimized by implementing calibration methods. As previously mentioned, SPR are attractive

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128 because of their hardware simplicity; however, their disadvantage is the painstaking complicated calibration needed to increase their accuracy which was extensively covered in the previous literature [ 73 ]. The simulation results in Figure 6 15 show raw measurement data which does not include any calibration method. The deviations arise from the fact that only second order was used to estimate the power levels at the input of each d etector. Additionally, although the SPR was simulated with imperfections including nonideal passive elements which constituted the network and parasitics from the detectors, ideal values in conjunction with the detectors readings were used to calculate t he estimated reflection coefficients. Nevertheless, Figure 6 15 shows that the compact SPR topology in Figure 6 13 is functional demonstrating that differential and single ended detectors are valuable. Figure 6 15. Smith chart showing reflection coefficients measured by the compact SPR

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129 CHAPTER 7 S UMMARY AND SUGGESTIO NS FOR FUTURE WORK Summary This dissertation discussed amplitude detectors which are appropriate for high frequency low cost alternate test strategies. For RF BIST, only simple test circuits with a strong correlation to the DUTs specifications can enable mainstream deployment. Alon g these lines, a simple, wideband, compact and noninvasive amplitude detector was indentified. The detector was used as a basis to report novel contributions with the hope of presenting simple design methodologies and improvements to standardize RF BIST. The most significant contribution of this work was to identify key parameters which affect the detectors response. The dissertation also proposed simple techniques and minor modifications to the topology to increase the design space and offer flexibility which widens the range of practical applications. Additionally, these methods were projected onto a mixedmode detector that is suitable for testing differential DUTs. The dissertation started by deriving simple equations which describe the detectors response in key operating conditions which are the detectors operating region and input signal power level. Further analysis of the detector topology compared major detector specifications such as the detectors video bandwidth, static power consumption, accuracy in environmental and process variations, and dynamic range in each of the key operating conditions. A tradeoff summary of each of these specifications is reported to offer simple parameteri zed design choices. Furthermore, the most significant contributors which cause deviation of the detectors response were identified. Novel design methodologies and simple modifications were proposed to minimize these deviations as they affect the detectors

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130 the dynamic range. The benefits of an increased dynami c range are twofolds; a larger set of applications can be targeted without requiring complex customization, increased accuracy can be achieved without resorting to c omplicated calibration methods. Additionally, a compact, wideband true differential detect or structure is identified which is also based on the simple detector topology discussed above. Besides analyzing the detectors response according to its operating conditions, sources of error in differential detection are also discussed for the first tim e. Additionally, the structure is improved to include commonmode detection capability without increas ing the loading effects on DUT. Finally, a chapter showing applications for these detectors is presented at the end. Suggestions for Future Work The succe ss of RF BIST hinges on the simplicity of the alternate test structures. Complicated methods cannot be used unless RF design becomes synthesizable like digital circuits. Until that happens, RF circuit designers will resist adopting any complicated test met hods especially if they entail increase of the design cycle time. The motivation of this dissertation was to identify key parameters which affect the detectors the most; then attempt to simplify all the effects and offer solutions so that parameterized det ector topologies can be offered or easily designed. Efforts along this path should be continued to expand the library of simple useful circuits, and hopefully, foundries can start offering alternate test IP part of their design kits. Once universal test c ircuits that are strongly correlated to the DUT specifications become available, there is bound to be some post processing of the alternate test response. Alternate test responses are very difficult to formalize to directly extract complicated specificatio ns [ 76]; although, recent successes were reported in [ 24]. The

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131 ATE industry, that is perennially agonizing to seek profitable business models, can hopefully adopt alternate RF test by at least working on post processing the output of the BIST circuits. I believe that the ATE industry can play a large role in adopting or developing efficient algorithms to lower test costs. Up to now, laudable efforts have surfaced such as the collaborative test advocated by [ 12]; nonetheless, this work was not targeting RF test. In parallel, a new research area which seek s novel methods for self healing of RF circuits is attracting a lot of interest [ 77 ] [ 78 ] Developing these solutions is especially critical as vertical integration is gaining momentum and proc ess variations effects increase in deeply scaled technologi es This new research area is monumental as there is a tremendous amount of topics to be explored as self healing need to work on the system level, subcomponent level, and even the transistor level.

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132 APPENDIX O NE PORT CALIBRATION When testing detectors, the raw measured data is not consistent with simulations as shown in the graph below The plot in Figure A 1 compares uncalibrated measurement results to simulation results of a detector. The RF input frequency is swept from 300MHz to 3GHz while keeping the RF input power level in the signal generator constant at 0dBm. Ideally, the curves are supposed to be flat since the input power is constant. The simulation results show that the output DC voltage is constant from 1.2GHz to 3GHz. The roll off for f requencies lower than 1.2GHz is due to the use of small on chip coupling capacitors. But the curve of interest here is that of the uncalibrated results. For that curve, the DC output decreases as the frequency increases. This loss pattern is consistent wit h cable insertion loss. Therefore, we need to account for the measurement setup losses. Some measurements like S parameter s are ratioed measurement s and do not need an exact power level The only requirement for the power in that case is to maintain a smal l signal level that is above the noise level Detector measurement s require knowing the exact power level at the input of the DUT. Figure A 1 Uncalibrated m easurement and s imulation r esults 180 190 200 210 220 230 240 0 1000 2000 3000 4000DC Ouput (mV)Frequency (MHz) Meas Sim

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133 Modern VNAs have a capability t hat account s for insertion loss in the measurement setup that is called source power calibration. It calibrates the VNA so that the power is constant at a reference plane across the swept parameter range. This setup requires a power meter, and it is fairly easy to do. In case this equipment is not available, calibration has to be done manually. There is a detailed analysis of this approach in this reference [ 79]. This analysis is called oneport calibration and will allow us to know the exact power level at the input of the DUT. It moves the reference plane all the way to the probe tips by taking into account n on idealities in the measurement setup. This technique is explained in Figure A 2 Figure A 2 Forward and reverse waves at different points in the measurement setup The power at the output of the signal generator is = 1 2 ( | 0 | 2 | 0 | 2 ) (A 1) w here a0 and b0 are the incident and reflected peak waves. The actual power displayed in the signal generator is the available power = | 0 | 2 2 (A 2) The available power is equal to the measured power when the system is perfectly matched as there is no reflection which makes b0=0. However the actual power

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134 delivered to the load might be different From Figure A 2 the load power can be defined such as = 1 2 ( | 1 | 2 | 1 | 2 ) = | 1 | 2 2 ( 1 | | 2 ) (A 3) In [ 79 ], an error adapter network is defined to model the errors in the measurement setup. This hypothetical error adapter is shown in Figure A 3 This network has three types of errors: Directivity error e00: represents the signals that are reflected at the discontinuity between the signal source reference plane and the cable. Frequency response errors e10 and e01: represent the transfer function from the port of the signal source to the load under test. Port match error e11: represents the reflection caused by the mismatch between the load and the impedance looking backward int o the error network. This network allows us to link the actual waves a1, b1 to the measured waves a0 and b0. 1 = 0 10 + 1 11 (A 4) Figure A 3 Hypothetical error adapter network This becomes 1 = 0 10 1 11 (A 5)

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135 T o calculate Pload, we have to calculate the errors represented by the hypothetical error adapter network. By doing a Short Open Load (SOL) calibration to the error network, [ 79] derives the following equations. 00 = (A 6) 11 = 1 2 (A 7) 01 10 = 2 ( ) (A 8) where is measured by a short as a load, and is measured by using an open load. Please, note that at very high frequencies open, short, and load using the calibration substrate have parasitics. These should be accounted for by entering the values into the VNAs calkit. [ 79 ] states that in practice, the terms e01, e10 cannot be distinguished from each others. Furthermore, in our measurement setup, the cables and the probes are passive. Therefore, we can assume that 10= 0110 Now, the last remaining piece of the puzzle to calculate Pl oad is to derive the actual reflection coefficient This is given in [ 79] as: = 00 11 ( 00 ) + 01 10 (A 9) w here refers to the reflection coefficient measured by the VNA when the probe is landed on the DUT. By substituting equations (A 5) into (A 3) the power at the load becomes = 1 2 0 10 1 11 2 ( 1 | | 2 ) (A 10) Using equation (A 2) = 10 1 11 2 ( 1 | | 2 ) (A 11)

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136 The first term 101 11 2 in the equation represents the loss associated with the measurement setup. The second term ( 1 | |2) represents the power loss due to the mismatch between the source impedance and DUT input impedance. Therefore, we can now derive an equation for an ideal source power. Lets call this source power which is a calibrated version of the raw measurement power The intent in this derivation is to compare measurement results to simulations. = ( 1 | | 2 ) (A 12) Substituting (A 11) in (A 12) the calibrated (simulation) power is = 10 1 11 2 (A 13) where is the raw measurement available power. It is the power displayed by the signal generator. Furthermore, power detectors may require knowing the actual power at the input of the detector. However, amplitude detectors may require knowing the actual voltage. Therefore, it is necessary to derive an equation for the actual voltage as well. = | | 2 2 | | 2 ( ) (A 14) The impedance ZL can be derived from the previously calculated as shown below = 1 + 1 (A 15) Rs represent the source impedance. Also, Pavail is defined such as = | | 2 8 (A 16) By substituting equation (A 12) (A 13) and (A 16) into equation (A 14) the voltage across the input of the DUT is: | | = 10 1 11 2 ( 1 | | 2 ) | | 2 4 { } (A 17)

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137 This equation is used for an input source with matched, the reflection coefficient becomes = 0 Then equation (A 17) becomes = | 10 | 2 (A 18) But when the detector is high impedance, = 1 and equation (A 17) becomes = 10 1 11 (A 19) because lim ( 1 | | 2 ) | | 2 4 { } = 1 (A 20)

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145 BIOGRAPHICAL SKETCH Said Rami was born in Seattle, WA. He received his B.Sc. and M.Sc. in e lectrical e ngineering from University of Florida Gainesville in 2005 and 2006, respectively, where he is currently pursuing his Ph. D degree in e lectri cal e ngineering. He worked as an intern during two summer internships, 2005 and 2006, at Motorola in Plantation, FL. He also worked during Spring and Summer of 200 8 as an intern at IBM in Essex J unction, VT. His research interests are analog/mixedsignals/RF design, as well as alternate test development at the integrated circuit and component levels.