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Impact of Strain on Memory and Lateral Power MOSFETS

Permanent Link: http://ufdc.ufl.edu/UFE0041422/00001

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Title: Impact of Strain on Memory and Lateral Power MOSFETS
Physical Description: 1 online resource (86 p.)
Language: english
Creator: Aghoram, Umamaheswari
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2010

Subjects

Subjects / Keywords: breakdown, demosfet, floops, ldmosfet, memory, mosfet, retention, shallow, silicon, strain
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: To circumvent the limitations of conventional scaling, the semiconductor industry incorporated strained silicon technology to boost the performance of digital logic devices. Since strain alters several semiconductor properties, its effect on all device parameters needs to be investigated. This work focuses on the effect of mechanical stress on memory and power devices. Growth of digital electronics is largely attributed to the success of CMOS memory such as DRAM and Flash. The most significant device characteristic for memory is the duration of time for which the memory cell is capable of storing the data with integrity or retention time. Using four-point wafer bending apparatus to apply mechanical stress the dependence of memory retention time on strain is studied. From measurements it was observed that while DRAM retention degenerates with mechanical stress, NVM improved with tensile stress. Power MOSFETs are used as high current and voltage drivers in automotive, telecommunication and power industries. The two main figures of merit of power devices are their on-resistance and breakdown voltage. The design of these devices is complicated by the tradeoff between the requirements for minimum on-resistance and maximum breakdown voltage. This work focuses on the application of mechanical stress to improve the performance of Lateral Diffusion MOSFET. The device behavior was analyzed by measuring and extracting piezoresistance coefficients of these devices and by monitoring avalanche breakdown with mechanical stress. It was found that the on-resistance reduced with stress, while breakdown voltage remained a constant thus making strain a viable performance booster in these devices. With the understanding of device behavior with strain, the application of stress via process was simulated with FLOOPS and Sentaurus process. The amount/ type of stress present in device gives insight into strained device structure and performance.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Umamaheswari Aghoram.
Thesis: Thesis (Ph.D.)--University of Florida, 2010.
Local: Adviser: Thompson, Scott.
Local: Co-adviser: Nishida, Toshikazu.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2010-10-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2010
System ID: UFE0041422:00001

Permanent Link: http://ufdc.ufl.edu/UFE0041422/00001

Material Information

Title: Impact of Strain on Memory and Lateral Power MOSFETS
Physical Description: 1 online resource (86 p.)
Language: english
Creator: Aghoram, Umamaheswari
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2010

Subjects

Subjects / Keywords: breakdown, demosfet, floops, ldmosfet, memory, mosfet, retention, shallow, silicon, strain
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: To circumvent the limitations of conventional scaling, the semiconductor industry incorporated strained silicon technology to boost the performance of digital logic devices. Since strain alters several semiconductor properties, its effect on all device parameters needs to be investigated. This work focuses on the effect of mechanical stress on memory and power devices. Growth of digital electronics is largely attributed to the success of CMOS memory such as DRAM and Flash. The most significant device characteristic for memory is the duration of time for which the memory cell is capable of storing the data with integrity or retention time. Using four-point wafer bending apparatus to apply mechanical stress the dependence of memory retention time on strain is studied. From measurements it was observed that while DRAM retention degenerates with mechanical stress, NVM improved with tensile stress. Power MOSFETs are used as high current and voltage drivers in automotive, telecommunication and power industries. The two main figures of merit of power devices are their on-resistance and breakdown voltage. The design of these devices is complicated by the tradeoff between the requirements for minimum on-resistance and maximum breakdown voltage. This work focuses on the application of mechanical stress to improve the performance of Lateral Diffusion MOSFET. The device behavior was analyzed by measuring and extracting piezoresistance coefficients of these devices and by monitoring avalanche breakdown with mechanical stress. It was found that the on-resistance reduced with stress, while breakdown voltage remained a constant thus making strain a viable performance booster in these devices. With the understanding of device behavior with strain, the application of stress via process was simulated with FLOOPS and Sentaurus process. The amount/ type of stress present in device gives insight into strained device structure and performance.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Umamaheswari Aghoram.
Thesis: Thesis (Ph.D.)--University of Florida, 2010.
Local: Adviser: Thompson, Scott.
Local: Co-adviser: Nishida, Toshikazu.
Electronic Access: RESTRICTED TO UF STUDENTS, STAFF, FACULTY, AND ON-CAMPUS USE UNTIL 2010-10-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2010
System ID: UFE0041422:00001


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1 IMPACT OF STRAIN ON MEMORY AND LATERAL POWER MOSFETS By UMAMAHESWARI AGHORAM A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF P HILOSOPHY UNIVERSITY OF FLORIDA 2010

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2 Umamaheswari Aghoram

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3 To my family

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4 ACKNOWLEDGMENTS I would like to express my sincere gratitude to my advisor Dr. Scott E. Thompson for his guidance and support over the years. I thank my co chair Dr. Toshikazu Nishida for his encouragement and helpful discussions. I would also like to thank Dr. Ant Ural and Dr. Franky So for serving on my committee. Special thanks go to the industry liaisons from Texas Instruments, Dr Sridhar Seetharaman, Dr Marie De nison Dr Rick Wise, and Dr Sameer Pendharkar for their help and guidance on the SRC project. I am grateful to SRC and TI for the opportunity to work on their project. My heart felt thanks to all the current and past members of our research group: Andy, Am it, Guangyu, Hyunwoo, Jingjing, Ji S ong, Kehuey, Lu, Mehmet, Min, Nidhi, Sagar, Sri, Tony, Ukjin, Xiaodong, Yongke, Younsung for their assistance, support and friendship. I would like to thank Saurabh, Daniel and David for helping me with TCAD simulations My sincere gratitude goes to Dr. Toshinori Numata for his invaluable help and mentorship. Last but not the least; I would like to thank my colleagues at TI, friends, faculty and staff and everyone who helped me during my graduate studies here at UF. A sp ecial thanks to my good friends Min, Krishna, Manasa, and Saranya for their encouragement and support. I dedicate my dissertation to my family for their unwavering love, encouragement, and support.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................ ................................ ................................ .. 4 LIST OF TABLES ................................ ................................ ................................ ............ 7 LIST OF FIGURES ................................ ................................ ................................ .......... 8 CHAPTER 1. INTRODUCTION ................................ ................................ ................................ .... 13 Strained Silicon Technology ................................ ................................ ................... 13 Memory Overview ................................ ................................ ................................ ... 17 Lateral Power MOSFET ................................ ................................ .......................... 19 Organization ................................ ................................ ................................ ........... 21 2. EFFECT OF MECHANICAL STRESS ON MEMORY DEV ICES ............................ 22 In troduction ................................ ................................ ................................ ............. 22 DRAM Retention ................................ ................................ ................................ ..... 22 Experiment ................................ ................................ ................................ ....... 25 Results and Discussion ................................ ................................ .................... 26 Conclusion ................................ ................................ ................................ ........ 30 Flash Memory Retention ................................ ................................ ......................... 31 Experiment ................................ ................................ ................................ ....... 31 Results and Discussions ................................ ................................ .................. 32 Summary ................................ ................................ ................................ ................ 34 3. EFFECT OF STRAIN ON LATERAL POWER MOSFETS ................................ ...... 35 Introduction ................................ ................................ ................................ ............. 35 LOCOS vs. STI technology ................................ ................................ ..................... 36 Introduction ................................ ................................ ................................ ....... 36 Experimental Approach ................................ ................................ .................... 37 Results and Discussion ................................ ................................ .................... 38 On resistance ................................ ................................ ............................. 38 Breakdown voltage ................................ ................................ .................... 42 Orientation D ependence ................................ ................................ ......................... 43 Experiment ................................ ................................ ................................ ....... 45 Results and Discussions ................................ ................................ .................. 46 High Stress ................................ ................................ ................................ ............. 54 Device Voltage Rating ................................ ................................ ............................ 54 Summary ................................ ................................ ................................ ................ 56 4. STRESS SIMULATION OF STRAIN ED MEMORY AND LDMOSF ET .................... 57

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6 Introduction ................................ ................................ ................................ ............. 57 Overview of Simulation tool ................................ ................................ .................... 58 Simulation Setup ................................ ................................ ................................ ..... 59 Strain in DRAM Transistor ................................ ................................ ................ 60 Strained Flash Memory Device ................................ ................................ ........ 61 Strained LDMOSFET ................................ ................................ ....................... 62 Nitride capping ................................ ................................ ........................... 63 STI induced stress ................................ ................................ ..................... 66 Results and Discussion ................................ ................................ ........................... 68 Strain in DRAM Transistor ................................ ................................ ................ 68 Strained Flash Memory ................................ ................................ .................... 69 Strained LDMOS ................................ ................................ .............................. 70 Nitride capping with dummy gates ................................ ............................. 70 STI induced stress ................................ ................................ ..................... 72 Summary ................................ ................................ ................................ ................ 76 5. S UMMARY AND RECOMMEND ATIONS FOR FUTURE WO RK ........................... 78 Summary ................................ ................................ ................................ ................ 78 Recommendations for F uture W ork ................................ ................................ ........ 78 LIST OF REFERENCES ................................ ................................ ............................... 80 BIOGRAPHICAL SKETCH ................................ ................................ ............................ 86

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7 LIST OF TABLES Table page 1 1. Comparison between DRAM and Flash memory ................................ ................... 19 3 1. Expected and measured longitudinal coefficients of <110> NLDMOS and DEPMOS ................................ ................................ ................................ ............ 40 3 2. Comparison of carrier mobility and coefficient in logic MOSFET and bulk along different orientations. [8, 9, 46] ................................ ................................ 45 3 3. Expected and measured coefficients for <100> and <110> N LDMOS and DEPMOS with the measurement uncertainty in brackets ................................ .. 49 4 1. Material Constants used in simulation ................................ ................................ .... 60 4 2. Beneficial stress for N LDMOSFET ................................ ................................ ........ 63

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8 LIST OF FIGURES Figure page 1 1. Strained silicon technology nodes of Intel nano transistors [5] ............................... 14 1 2. Process induced uniaxial a nd biaxial stress [6] ................................ ...................... 14 1 3. Layout of mixed signal integrated chip ................................ ................................ ... 15 1 4. Four point wafer bending jig ................................ ................................ ................... 16 1 5. Schematic for applying uniaxial and biaxial stress [8] ................................ ............ 16 1 6. Classification of semiconductor memory ................................ ................................ 17 1 7. World wide memory market in year 2000 [10] ................................ ........................ 18 1 8. Evolution of LDMOS from NMOS ................................ ................................ ........... 20 1 9. System rating of power device s [15] ................................ ................................ ...... 21 2 1. DRAM leakage components ................................ ................................ .................. 24 2 2. Band diagram ................................ ................................ ................................ ......... 25 2 3. Typical currents gate voltage (Vg) characteristics of NMOSFET. .......................... 26 2 4. Setup to measure leakage in MOSFET ................................ ................................ .. 26 2 5. S hift in substrate current of n MOSFET with SiO 2 dielectric under the tensile stress. ................................ ................................ ................................ ................. 29 2 6. GIDL shift under mechanical stress for n MOSFET with SiO 2 and high dielectric at high (filled marks) and low (open marks) electric fields. .................. 30 2 7. Band diagram of NVM under retention ................................ ................................ ... 31 2 8. Experiment setup for data retention bake under stress of NVM cell ....................... 32 2 9 NVM cell retenti on after baking at 190C for 24h ................................ ..................... 34 3 1 Cross section of lateral power MOSFET with LOCOS and STI .............................. 37 3 2. Drain current enhancement under low and high gate bias ................................ ..... 39 3 3. Pola r pi plot of n Bulk under longitudinal tensile stress along <110> direction ....... 41 3 4. Shift in breakdown voltage of N LDMOS under tensile stress ................................ 43

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9 3 5. Mobility enhancement factors for (001) surface n MOSFETs under 100 longitudinal, 110 longitudinal, and biaxial tensile stress [5] ............................ 44 3 6. Channel orientation on (100) wafer ................................ ................................ ........ 45 3 7. Linear Drain current enhancement versus stress for NLDMOS ............................. 47 3 8. Linear Drain current enhancement versus stress for DEPMOSFET ...................... 49 3 9. N bulk piezoresistance vs. angle of spread in drift region under stress ................. 51 3 10 P Bulk piezoresistance vs. angle of spread i n drift region ................................ .... 52 3 11. On Resistance distribution of N LDMOS at rated gate bias ................................ 53 3 12. Linear drain current enhancement under high stress ................................ ........... 54 3 13. Linear drain current enhancement versus stress with increasing drift region length ................................ ................................ ................................ .................. 55 4 1. Applied Materials scheme fo r strained NAND Flash. (Courtesy AMAT) ................. 61 4 2. Multi gate simulation structure with HARP STI and PMD ................................ ....... 62 4 3. N LDMOSFET with dummy gat es and nitride capping ................................ ........... 64 4 4. Longitudinal channel stress vs. gate length in logic MOSFET with tensile capping layer [59] ................................ ................................ ............................... 65 4 5. 2D capping layer on N LDMOSFET simulation structure ................................ ....... 65 4 6. DIELER structure ................................ ................................ ................................ ... 66 4 7. Principle of Dielectric RESURF [60] ................................ ................................ ....... 67 4 8. STI induced stress simulation structure for 2 D and 3 D ................................ ........ 67 4 9. A process simulation of built in stress in the middle and the gate edge of the channel in a strained Si MOSFET with stressed silicon nitride CESL ................. 68 4 10. Stress in NAND flash memory due to STI and PMD ................................ ............ 69 4 11. S tress in nested gate structure. A) Expected simulation result of LDMOS with tensile capping layer B) Actual simulation cross section from [60] ..................... 71 4 12. Stress in device center as a function of ga te to gate separation. ......................... 72 4 13. STI induced stress in active region [59] ................................ ............................... 73

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10 4 14. 2D stress contours of STI induced stress in active d rain extension fingers .......... 74 4 15. Transverse compression along the fin ................................ ................................ 75 4 16. Out of plane tension along the fin ................................ ................................ ........ 75 4 17. Longitudinal tension along fin ................................ ................................ ............... 76

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11 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfi llment of the Requirements for the Degree of Doctor of Philosophy IMPACT OF STRAIN ON MEMORY AND LATERAL POWER MOSFETS By Umamaheswari Aghoram May 2010 Chair: Scott Thompson Cochair: Toshikazu Nishida Major: Electrical and Computer Engineering To circu mvent the limitations of conventional scaling, the semiconductor industry incorporated strained silicon technology to boost the performance of digital logic devices. Since strain alters several semiconductor properties, its effect on all device parameters needs to be investigated. This work focuses on the effect of mechanical stress on memory and power devices. Growth of digital electronics is largely attributed to the success of CMOS memory such as DRAM and Flash. The most significant device characterist ic for memory is the duration of time for which the memory cell is capable of storing the data with integrity or point wafer bending apparatus to apply mechanical stress the dependence of memory retention time on strain is stud ied. From measurements it was observed that while DRAM retention degenerates with mechanical stress, NVM improved with tensile stress. Power MOSFETs are used as high current and voltage drivers in automotive, telecommunication and power industries. The tw o main figures of merit of power devices are their on resistance and breakdown voltage. The design of these devices is complicated by the tradeoff between the requirements for minimum on resistance and

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12 maximum breakdown voltage. This work focuses on the ap plication of mechanical stress to improve the performance of Lateral Diffusion MOSFET. The device behavior was analyzed by measuring and extracting piezoresistance coefficients of these devices and by monitoring avalanche breakdown with mechanical stress. It was found that the on resistance reduced with stress, while breakdown voltage remained a constant thus making strain a viable performance booster in these devices. With the understanding of device behavior with strain, the application of stress via proc ess was simulated with FLOOPS and Sentaurus process. The amount/ type of stress present in device gives insight into strained device structure and performance

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13 CHAPTER 1 INTRODUCTION Strained Silicon Technology The revolutionary growth of the semicondu ctor industry can be attributed to scaling [1] However improving the performance of transistors by s caling is progressively becoming difficult and this has spurred the industry to look for other mechanisms to Ge was investigated as a means to improve logic performance [2] In 2003, Intel introduced strained silicon technology in its 90nm node [3] Since then fourth generati on strained silicon has been incorporated into the 32nm technology [4] I nternational T echnology R oadmap for Semiconductors (ITRS ) named strained silicon as one of the potential solutions to improve the performance of devices in 22nm node (Figure 1 1). Not only is strain intentional ly introduced to improve performance (Figure 1 2), but strain is inherently present due to device fabrication process such as isolation, oxidation, silicidation, implant and packaging. Since strain is known to alter several semiconductor properties such as : Band structure, carrier mass, scattering and t rap properties it is important to study its effect on device properties, so that we can engineer strain to improve the device.

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14 Figure 1 1. Strained silicon technology nodes of Intel nano transistors [5] Figure 1 2. Process induced uniaxial and biaxial stress [6] The layout of a standard mixed signal integrated chip is shown in Figure 1 3. It consists of a digital core with semico nductor memory and the interface to the real world is provided by the surrounding analog shell [7] The analog shell protects the core from external electric stresses, provides power management and acts as the communication link be tween the control logic circuitry and th e load. This technology is gaining more importance with the increasing interest in System On Chip for consumer electronics, telecommunications, automobile and power management for portable equipments. With

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15 the scaling of the digital core to increase functi onality there is an increased pressure on the analog shell to scale as well. Traditionally, scaling in semiconductor industry has been predominantly digital centric, i.e. focused on logic M etal O xide S emiconductor F ield E ffect T ransistor s (MOSFET) Scaling of the analog shell lags several years behind digital logic due to cost considerations and stress from increased power density. Since the main performance metric for memory and power devices are not similar to that of logic MOSFETs, the effect of strain on these devices needs to be studied. Also, it is of interest to see if strain can improve the performance in these devices. Figure 1 3. Layout of mixed signal integrated chip Experiment Setup: The four point wafer bending apparatus is used to apply mech anical stress to device wafer. This apparatus, shown in Figure 1 4, has been calibrated using wafer curvature and strain gage measurements. Both uniaixal and biaxial stresses can be applied by using the setup shown in Figure 1 5. The distance of separatio n between the rods determines the amount of stress per graduation and can be calculated using the simple formula (Equation 1 1) The jig is easy and reliable to

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16 use and is especially valuable in taking repeated device measurements under low stress levels. = 2 2 2 3 (1 1) Where E Modulus, y vertical displacement, t wafer thickness, L distance between outer two rods, a Distance between outer rod and inner rod. Figure 1 4. Four point wafer bending jig Figure 1 5. Sche matic for applying uniaxial and biaxial stress [8] The device electrical characteristics are monitored using Keithley 4200 semiconductor characterization system. Historically the strain induced change in device

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17 drive current is quantized by extracting the piezoresistan ce coefficient ( coefficient). coefficient is defined as the normalized change in resistance per unit applied stress. (1 2) Where semiconductor piezoresistance applied mechanical stress, semiconductor resistivity, m carrier mobility, and I D Drain current First reported by Smith [9] in 1954, the piezoresistance of silicon has been the basis by which industry predicts strained device behavior. Memory Overview The growth of digital electronics can be largely attributed to the success of semiconductor memory. It is found in most consumer electronics such as cell phones computers, digital cameras, global positioning systems, etc. CMOS memory can be divided into two main categories: Volatile memory ( Random access memory or RAM) and non volatile memory (NVM) or read only memory (ROM) [10] Volatile memory loses the stored information once the power supply is turned off. NVM on the other hand retains the data. Figure 1 6 shows the various types of semiconductor memory devices. Figure 1 6. Classification of semiconductor memory

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18 Figure 1 7. World wi de memory market in year 2000 [10] Dynamic Random Access Memory (DRAM) and Flash memory are billion d ollar industry and are the most popular CMOS memory types (Figure 1 7). Commercially introduced by Intel in 1971, DRAM consists of one transistor and one capacitor (1T 1C) [11] It is a volatile memory that requires the stored information to be refreshed after every read cycle. It has fast read/write times. With the advent of trench capacitors the density of DRAM has increased dramatically. Floating gate flash memory [12] was produced by Toshiba in 1984. It consists of only one tra nsistor with a polysilicon floating gate acting as the storage element. Channel hot electron (CHE) injection is used to store electrons in the floating gate, thus altering the threshold voltage of the device (programmed state). Data is erased by removing t he electrons from the floating gate by Fowler Nordheim tunneling (F N tunneling). In 2001, AMD introduced the first commercial Mirror bit flash [13] which was capable of storing two independent bits of information. The electrons are locally trapped in two separate locations on the silicon nitride trapping layer. A comparison between DRAM and Flash memory is shown in Table 1 1.

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19 Table 1 1. Comparison between DRAM and Flash memory Lateral Power MOSFET Power MOSFETs are solid state switches with high power handling capability that evolved fro m CMOS technology. T he process of increasing the blocking voltage capability of lateral MOSFET structure led to the development of Diffusion MOSFET (DMOS) [14] In NLDMOS structure the source and drain n+ regions are self aligned base region is then driven in deeper than the source [15] al diffusion determines Thus, these devices have very small channel lengths and hence low on resistance. These devices have an n type drift region which increases the breakdown voltage. Also the presence of field plate an d RESURF [16] reduces the electric field at the surface. Figure 1 8 shows the evolution of LDMOS from NMOSFE T.

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20 Figure 1 8. Evolution of LDMOS from NMOS Figure 1 9 shows the system rating of power devices. The lateral power MOSFET has high input impedance, operation frequency, current and voltage handling capability and ease of integration. They find wide appl ication in automotive, telecommunication and power industries.

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21 Figure 1 9. System rating of power devices [15] Organization The effect of mechanical stress on memory retention and power MOSFET device characteristics is presented in this work. Chapter 2 d iscusses the change in GIDL leakage current with mechanical stress and its effect on DRAM retention. Chapter 3 reports the piezoresistance coefficient of n LDMOS and DEPMOS devices. The experimental result of strain induced change in breakdown voltage is a lso shown. Chapter 4 deals with simulation of strained memory and power MOSFET structures. Summary and recommendations for future work are provided in chapter 5.

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22 CHAPTER 2 EFFECT OF MECHANICAL STRESS ON MEMORY DEV ICES Introduction Mechanical stress alters several properties of semiconductors such as band structure, carrier mass, scattering and trap properties. Thus several characteristics of memory devices may be altered by strain. The most important properties in memory devices are [17] : Endurance: Read/Write cycles the device can endure before failure Data Retention: The v alue of time for which a memory cell retains data Memory Disturb: Loss or gain of charge in a memory cell Program/Erase time: Time required for programming/erasing memory cell Among all these properties, retention time is the most important parameter. The industry generally requires N on V olatile M emory (NVM) to have 10 years retention time. In order to predict the memory retention time, accelerated testing methods such as Data Retention Bake (DRB) is used. In DRB programmed memory devices are baked at high temperatures such as 250C for 24 48 hours. The difference in device characteristics before and after bake, determines the retention. DRAM Retention Scaling of memory devices is ultimately determined by the data retention capability of the designed memory cell. In DRAM, leakage occurs from the capacitor through the MOSFET during retention period. The main leakage mechanisms in DRAM (Figure 2 1) are Subthreshold leakage (I SUBVt ) : This leakage refers to the flow of charge carriers from source to drain even w hen the device is in the off condition.

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23 This leakage current is especially large in short channel MOSFETs due to the Drain induced barrier lowering (DIBL). Gate induced drain leakage, GIDL (I GIDL ) : This leakage refers to band to band leakage between the r eversed biased gated diode of drain substrate region. For instance in an NMOSFET, high positive bias on the drain results in the drain substrate junction being reverse biased. However when there is a negative bias on gate resulting in an accumulation regi on in the channel the depletion region width of the reverse bias diode reduces at the surface below the gate. This causes an increased electric field and a subsequent increase in band to band tunneling current (Figure 2 2A). Junction leakage (I JXN ) : This merely refers to the reverse biased junction leakage of the drain substrate diode. With the scaling of the transistor in DRAM, the increase in subthreshold leakage is c ountered by applying a negative gate bias during retention. This has resulted in the inc rease of GIDL leakage. Thus GIDL current has become the most dominant leakage mechanism in DRAM.

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24 Figure 2 1. DRAM leakage components GIDL current is dominated by band to band tunneling ( BTBT ) leakage current at high normal electric fields and by interfa ce trap assisted tunneling ( TAT ) leakage current at low electric fields [18 20] Mechanical stress in DRAM may be present due to the technology node or as a result of processing and packaging. Several studies have been conducted on the effect of S hallow T rench I solati on (STI) and process induced strain on GIDL [21 23] in MOSFETs with oxide and high dielectrics. They report an increase in GIDL current under compressive stress due to band gap narrowing and increase in intrinsic carrier density. The reduction in silicon band gap due to strain induced band splitting is reported in reference [24] Since band to band t unneling is exponentially dependent on bandgap (E G ), mechanical stress can be very detrimental to DRAM retention. (2 1) Where J b b Band to band tunneling leakage current, E g Band gap and A Constant

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25 A B Figure 2 2. Band diagram A) GIDL B) Strain induced Si band gap narrowing E xperiment The devices used in this study were Si licon (Si) n channel MOSFETs with oxide (Si O 2 ) and h igh gate dielectrics on (001) wafer. The SiO 2 gate dielectric MOSFETs had n + poly Si gate and 1.4 nm SiO 2 gate dielectrics. The high gate devices were formed with 10 nm Ti tanium N itride (TiN) gate and 2 nm Hafnium silicate ( HfSiO ) gate dielectric. The oxid e interfacial layers were created by the gate stack formation. The MOSFETs with compressive built in stress were also formed by the process modulated silicon nitride contact etch stop layers (CESL). The typical current s and gate voltage ( V g ) characteristi c of a long channel n MOSFET is shown in Figure 2 3. In thin gate dielectric devices, the minimum drain current is dominated by the gate leakage. Thus to monitor GIDL, the substrate current (I sub ) was measured. Figure 2 4 shows the measurement setup used t o distinguish between the various I sub components. I sub is composed of the GIDL current at negative V g and the impact ionization current at positive V g both of which were higher than the corresponding p n junction leakage between drain and substrate.

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26 Ten sile and compressive mechanical stresses were applied longitudinally along the <110> channel by using the four point bending jig. Figure 2 3. Typical current s gate voltage ( Vg ) characteristics of NMOSFET. Figure 2 4. Setup to measure leakage in MOSFET Results and Discussion Fig ure 2 5 shows the I sub V g and the shift in I sub for tensile stress of 150MPa o n long channel MOSFET with the SiO 2 gate dielectric with zero built in stress On the

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27 application of tensile stress, the I sub shift shows a constant enhancement at high negative gate voltages On the other hand at low V g I sub decreases. It is thus found that the GIDL current increases in the high electric field and decreases in the low electric field for the tensile stress. I n the impact ionization r egion (high positive V g ), I sub shows a constant enhancement. Figure 2 6 shows the GIDL current shift with stress at high and low electric fields. It is seen that a t high electric field, GIDL current increase for both tensile and compressive stresses. I n t his electric field region, GIDL current is generally dominated by BTBT, which is sensitive to the variation in band gap. The Si band gap decreases for both tensile and compressive stress, although the sub bands shifts for 2 and 4 valleys and heavy and light holes are opposite for the tensile and compressive stress e s [6] On the other hand, the GIDL current in low electric field is due to trap assisted generation of electron hole pairs, which can be described by using Shockley Read Hall model [20] It is reported that the intrinsic carrier density is the main stress dependant parameter in the bu lk generation recombination current in p n junction [25] A theoretical calculation shows that f or the wafer orientation and stress range considered in this paper, the intrinsic carrier density decreases with tensile and increases with compressive stress [26, 27] This is similar to the strain altered GIDL shifts observed at low electric field However, for a more accurate analysis several other stress altered parameters such as the surface current, trap energy and new generation recombination centers need to be considered Figure 2 6 shows the relative change in GIDL current of high gate devices under applied stress. This trend w as ob served in the entire range of electric field up to the break down gate voltage. In zero built in stress device, the GIDL current increases with

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28 an increase in the compressive stress and gently decreases with tensile stress. These trends are similar but larger than those obtained at low electric fields in the SiO 2 gate dielectric devices In high gate dielectric devices, an additional GIDL component is introduced by trap assisted tunneling from the re mote traps located at the interfac e of the high dielectric and oxide in the gate stack [28] The larger change in GIDL current measured in th ese devices seems to suggest tha t the change in trap energy with strain further enhances the shift in generation recombination current. Figure 2 6 also shows the tensile str ain altered GIDL current shift of devices with compressive built in s tress. The slope of curve changes beyond a cer tain stress value (flex point). T he rate of the GIDL current shift be yond the flex point is identical to that of the device with zero built in stress The flex points of the process stressed devices change s with gate length. This type of trend strongly su ggests that the channel region, where GIDL current is generated, has a non zero built in stress modulated by externally applied mechanical stress. Therefore the stress value corresponding to the flex points give an estimate of the original built in stress in the channel near the gate edge where the GIDL current is generated. These flex points also shows that the built in stress still remains in the long channel devices with stressed CESL.

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29 Figure 2 5. S hift in substrate current of n MOSFET with SiO 2 diele ctric under the tensile stress.

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30 Figure 2 6. GIDL shift under mechanical stress for n MOSFET with SiO 2 and high gate dielectric at high (filled marks) and low (open marks) electric fields Conclusion The GIDL current dominated by BTBT leakage in high electric field increases for both tensile and compressive stress and t he stressed enhancement of Si MOSFETs is abo ut 2 3 % per 100MPa in this measurement. Even for strained long channel devices, the stress in the gate drain overlap region is not negligible. This has a serious impact on DRAM retention and off state leakage of devices using narrow band gap materials [24, 29] In n MOSFETs with high dielectric, compressive stress reduces GIDL. Thus strain on DRAM memory with high MOSFETs shows potential in increasing retention time.

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31 Flash Memory Retention Mirror bit Flash or SONOS (silicon oxide nitride oxide silicon) memory consists of a trapping nitride layer, instead of the floating gate as the charge storage layer In retention mode electrons trapped in the nitride layer leaks back into the silicon substrate throu gh several mechanisms illustrated in Figure 2 7 [30] Retention in these devices is monitored by data retention bake followed by measuring the shift in threshold voltage. At high temperature and in the absence of external electric field, thermal emission followed by drift of electrons due to the internal field is the main leakage mechanism [31] Figure 2 7. Band diagram of NVM under retention Experiment A long strip of device wafer is cleaved and all the isolated devices are progr ammed by applying high gate and drain bias for a few microseconds at room

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32 temperature. Under thes e bias conditions, channel hot electrons are captured into the nitride layer. This results in a shift in threshold voltage (V T ) of the Flash cell Next, mechanical stress is applied on devices on one die of the sample by using four point bending jig. The s ample along with the jig is then baked at 190 C for 24 h ours The advantage of this experiment setup is that both stress ed and uns tressed samples are baked at simultaneously. The V T before and after baking is monitored since the delta in V T is directly pro portional to the loss of electrons from the trapping layer. Figure 2 8. Experiment setup for data retention bake under stress of NVM cell Results and Discussions Shift in threshold voltage before and after the bak ing for stressed and unstressed devices i s shown in Figure 2 9 As can be seen from Figure 2 9 a, even for small values of stress as those applied in this experiment, all devices under tensile stress show improved retention (smaller V T shift) than unstressed devices. On the other hand compressiv e stress is observed to de teriorate retention (Figure 2 9 b). The leakage current density due to thermal emission is given by equation sim ilar to Arrhenius relationship. The shift in threshold voltage is proportional to the integral of

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33 current density ov er time. Thus the threshold voltage shift is exponentially proportional to the inverse of trap activation energy. (2 2 ) From the threshold voltage shift data of device with W/L=0.16/1 at two different temperatures at zero stress, w e extracted the trap activation energy to be 1.54eV. This value lies within the range reported in literature for electron traps in nitride layer [30] This gives us confidence that thermal emission is in fact the dominant leakage mechanism. (2 3 ) Strain is known to alter trap activation energy (E TA ) [32] From the relationship between V T shift and activation energy of traps, an increase in E TA under tensile stress and a decrease in E TA of nitride traps under compressive stress may explain the observed trend.

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34 A B Figure 2 9 NVM cell retention after baking at 190C for 24h A) Under Tensile stress and B) Under Compressive stress [33] Summary Effect of mechanical stress on retention time of DRAM and flash memory was investigated. Stre ss deteriorated DRAM retention while tensile stress improved charge trapping memory. Careful consideration needs to be given to process induced stress while manufacturing memory devices to maintain device reliability.

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35 CHAPTER 3 EFFECT OF STRAIN ON LATERAL POWER MOSFETS Introduction I medium power applications. Their high input impedance, operati ng frequency and excellent safe operating area make them ideal candidates for power, automotive and telecommunications industry. These devices form the analogue shell that surrounds the digital core and provides the link between the IC and real world. The main requirement in these devices is high drive current and ability to withstand large voltages Since the total current and power dissipation in these devices is limited by the on resistance and the maximum voltage r ating by the breakdown voltage, minimizing on resistance and maximiz ing breakdown voltage is the key to designing a high performance p ower MOSFET However the conflicting requirements needed to satisfy both these conditions complicates the design of these devices. Hence scaling of these devices lags behind the current CMOS technology. Despite having lower power rating than vertical power MOSFETs, lateral power MOSFETs are widely used because of their ease of integration. Following the conventional way of reducing on resistance by reducing dimensions has resulted in the need for innovative techniques such as REduced SURface Field (RESURF) [16, 34] field plating [15] and Superjunctions [35] to improve device breakdown. Strained silicon technology is a novel technique that can enhance power MOSFET performance by reducing the on resistance ( R ON ) without affectin g the breakdown voltage. Kondo et al [36] investigated biaxially stress ed lateral double diffused MOSFETs (LDMOSFETs) formed on strained silicon grown over relaxed Si 0.85 Ge 0.15

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36 layer. 16 21% lower on resistance of was reported. Recently, Moens et al [37] reported a strained trench po wer MOSFET. Tensile stress of the order of 200MPa was produced in the drift region by trench oxide on either side. MicroRamanSpectroscopy was used to verify the stress magnitude and direction. Strain induced mobility enhancement reduced the on resistance in the device by 10%. However no report on the effect of industry preferred uniaxial stress on power MOSFET performance has been made till date. This chapter deals with the effect of strain on n and p type LDMOSFETs, investigating the dependence on type of device isolation, voltage rating, channel orientation, and high mechanical stress. A simple analytical model using channel and bulk pi coefficients is used to explain the 4 point probe bending data. Based on the experimental result conclusions regarding t he best option for strain enhanced LDMOSFET is reached. LOCOS vs. STI technology Introduction The presence of i solation oxide in drift region reduces electric field and thus plays a critical role in improving the breakdown voltage in power MOSFET devices. In older analog technologies, LOCal Oxidation of Silicon (LOCOS) was used. Current technologies use the Shallow Trench Isolation process for isolation. The cross sections of the devices using LOCOS and STI isolations are illustrated in Figure 3 1. The ef fect of strain on the isolation technology is studied by monitoring its effect on On resistance and breakdown voltage of the device.

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37 Experimental Approach <110> oriented N LDMOS and DEPMOS on (100) substrate (Figure 3 1) with shallow trench isolation and LOCal Oxidation of Silicon isolation were used in this study. External mechanical stress was applied using four point wafer bending apparatus and the I V characterization was done using the Keithley 4200 SCS. Linear device characteristics were measured b y applying a constant DC bias of 0.1V at the drain and sweeping the gate bias from 0 to rated gate bias while keeping source and substrate grounded. Breakdown characteristics were obtained by sweeping the drain bias till avalanche breakdown occurred and the drain current was 10nA, while maintaining the gate, source and substrate at 0V In case of STI isolated devices, measuring the breakdown voltage is complicated by the excessive charging of the STI oxide. A B Figure 3 1. Cross section of lateral power MOSFET with LOCOS and STI A) N LDMOS and B) DEPMOS

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38 Results and Discussion On r esistance The percentage gain in linear drain current (I DLIN ) with longitudinal tensile stress on N LDMOSFET with STI and LOCOS isolation at low and high gate bias (V G ) is show n in Figure 3 2a and F ig ure 3 2b shows a similar plot for DEPMOSFET. At low V G the p iezoresistance coefficient ( coefficient ) of LDMOS with STI and LOCOS is similar to logic MOSFET ( NLDMOS = 25 and NMOS = 31; DEPMOS =55 and PMOS =71). As V G increases, the gain in I DLIN of N LDMOS decreases. Also at high V G the gain in I DLIN was higher in LOCOS device (1.2% for 100 MPa) than STI device (0.9% per 100 MPa). No V G or device isolation dependence was observed in the DEPMOS devices. A Figure 3 2. D rain current enhancement under low and high gate bias A) NLDMOS B) DEPMOS

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39 B Figure 3 2 Continued The above results can be understood by examining the effect of strain on the ind iv idual components of R ON of the power MOSFET. The coefficient of a laterally diffused power MOSFET is estimate d b ased o n its device model which consists of an enhancement mode MOSFET in series with a resistor [38 40] At low V G (weak inversion), the channel resistance ( R CH ) dominates the on resistance ( R ON ) and is given by (3 1) Where, L eff effective channel length, W channel width, C ox gate capacitance/unit D electron inversion layer mobility, V G applied gate bias, and V T Threshold voltage of enhancement mode M OSFET. Thus the coefficient of the power device is predicted to be similar to the logic MOSFET. At high V G R ON is dominated by the drift resistance ( R D ).

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40 (3 2) Where, L D n B ulk bulk electron mobility, W channel width, and Q d drift region charge. Hence, the coefficient is expected to be identical to bulk silicon (Si coefficient. Based on this concept, the expected values for the coefficient of power MOSFET are listed in Table 3 1. The values for the logic MOSFET were taken from [8] and bulk [9] From table 3 1 it can be observed that a t low V G the strained lateral p ower device follows expectation. However at high V G the values of the N LDMOS differs significantly from bulk Si. On the other hand no such degradation of enhancement is observed in DEPMOSFETs. This discrepancy can be understood by considering the strain induced change in mobility of carriers that spread vert ically into the drift region. Table 3 1. Expected and measured longitudinal coefficients of <110> NLDMOS and DEPMOS Longitudinal (x10 11 Pa 1 ) LOCOS STI Low V G High V G Low V G High V G NLDMOS 24 12 25 9 Expectation 31 31 31 31 DEPMOS 55 50 52 42 Expectation 71 71 71 71 For the LDMOSFET, R ON is the sum of channel resistance ( R CH ), accumulation resistance ( R ACC ), spread resistance ( R S ), and drift resistance ( R D ) [41] The coefficient of R CH is the same as logic MOSFET and the value of R D and R S is that of

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41 of N Bulk along that direction. The coefficient of R S ( S ) is a function of the angle of spread of carriers int o the bulk of the drift region. For materials with cubic symmetry such as Si, the coefficient along any direction can be determined from the piezoresistance tensor and direction cosines [42, 43] The de pendence of S on spread angle for <110> n channel device under longitudinal tensile stress shown in Figure 3 3 is derived as (3 3) Where 11 12 and are the three basic coefficients, and represents the spread an gle. Figure 3 3. Pol ar pi plot of n Bulk under longitudinal tensile stress along <110> direction

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42 From the polar plot for N Bulk (Figure 3 3), it is easy to see that as electron s spread more vertically into the substrate, the spread resistance increases with the applied mech anical stress. At high V G where R D and R S dominate R ON the increase in R S with stress results in the observed degradation of the coefficient of N LDMOS. In the case of low breakdown DEPMOS devices, there is no isolation present in the drift region. H owever, even in the presence of isolation, the insignificant coefficient of the spreading resistance results in DEPMOS I DLIN enhancement to be independent of V G Breakdown v oltage From F ig ure 3 4 it is seen that the shift in breakdown voltage for l ateral power MOSFETs is only ~ 80 mV for 6 0 MPa, comparable to the amount of shift caused by ch arging of the oxide from repeated measurements. A ssuming a linear trend with st ress, this translates to ~1 V for 1 GPa stress. This shift is rather insignificant when dealing with breakdown voltages of magnitude ~35 V

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43 Figure 3 4. Shift in breakdown voltage of N LDMOS under tensile stress From the measurement of piezoresistance coefficients of <110> lateral power devices, it i s observed that the coefficients of power devices are not similar to logic MOSFETs. This is due to the vertical spread of carriers in the drift region. The enhancement for N LDMOS device i s not as high as expected. For 20% reduction in R ON the required amount of stress exc eeds 1.5 GPa. This large value of stress makes application of strained silicon technology not a very attractive option for <110> NLDMOS devices Orientation dependence Work from Kanda [36] reports that strain induced enhancement in a semiconductor is de pendent on the direction of current flow. For n type logic devices, determination of the best strained orientation was conducted by Uchida. From his plot on mobility enhancement with stress, it is easy to see that <1 0 0> is the best orientation for NMOSFET at low values of stress and <110> is the best orientation at high stresses

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44 However from the previous discussion, it is easy to see that <110> is not the best orientation for strained N LDMOSFET. Figure 3 5. Mobility enhancement factors for (001) surfac e n MOSFETs under 100 longitudinal, 110 longitudinal, and biaxial tensile stress [5] Use of a lt ernate or ientations and hybrid wafer substrate s in the manufacture of power MOSFETs has been widely investigated especially for p type power devices [44, 45] From the comparison of hole mobility for different substrate and channel orientations (Table 3 2), <110> direction on (110) substrate is the ideal orientation for p type power MOSFETs. The piezoresistance of strained po wer LDMOSFET is a function of both MOSFET and bulk value. A comparison of carrier mobility and coefficient of MOSFET and bulk silicon along different orientations (Table 3 2) is useful in determining the best orientation for strained lateral power MOSF ET.

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45 Table 3 2. Comparison of carrier mobility and coefficient in logic MOSFET and bulk along different orientations. [8, 9, 46] Wafer/Channel Orientation Channel Mobility Channel coefficient Bulk coefficient n p n p n P (100) [110] n p 32 71 31 71.8 (100) [100] ~ n p 47 15 102 6.6 (110) [110] 0.4 n 2.6 p 17 27 31 71.8 (110) [110] 0.6 n 1.7 p 24 31.3 102 6.6 From this table it is easy to see that <100> cha nnel and <110> channel on (100) wafer is the best orientation for strained N LDMOSFET and DEPMOSFET respectively. By simply rotating the wafer notch by 45 degrees, the same processing for the devices with standard orientation will yield devices with channe l along the <100> direction (Figure 3 6). This enables the simultaneous production of both n and p type strained power MOSFETs on the same wafer. Figure 3 6. Channel orientation on (100) wafer Experiment The current voltage characteristics of <100> orie nted N LDMOSFET and DEPMOSFET with STI on (100) wafer under mechanical stress was measured and

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46 compared with the control <110> oriented device. coefficients were extracted at low and high gate bias. coefficients of on chip resistances we re also measure d to accurately determine bulk values. From the measurement, an analytical model for the piezoresistance of lateral power MOSFET was developed and the lowest value of stress required for 20% reduction in on resistance was calculated. Results and Discussi ons The linear drain current enhancement with applied mechanical stress for <100> and <110> oriented n type lateral power MOSFETs is shown in Figure 3 7 and the extracted coefficients is listed in Table 3 3. B oth <1 10> and <100> channel device show ed lo wer enhancement s of I DLIN at high V G ( <110> = 9 x10 11 Pa 1 and <100> = 20 x10 11 Pa 1 ) than at low V G ( <110> = 25 x10 11 Pa 1 and <100> = 36 x10 11 Pa 1 ). At high V G longitudinal tensile stress on <100> channel N LDMOS shows the largest im provement of ~ 2% per 100 MPa. Also, transverse stress on N LDMOS is not as beneficial as longitudinal tensile stress.

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47 A B Figure 3 7 Linear Drain current enhancement versus stress for NLDMOS A) <100> oriented device B) <110> oriented device

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48 In case of strai ned DEPMOSFET on a (100) wafer at high V G the st andard orientation namely <110> is the preferred channel direction. Nearly a 5% enhancement is observed from Figure 3 8 for every 100 MPa of longitudinal compressive stress. For the <100> channel DEPMOS, tr ansverse compression is more beneficial than longitudinal stress. A Figure 3 8 Linear Drain current enhancement versus stress f or DEPMOSFET A) <100> oriented device B) <110> oriented device

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49 B Figure 3 8 Continued Table 3 3. Expected and measured coefficients fo r <100> and <110> N LDMOS and DEPMOS with the measurement uncertainty in brackets. N LDMOS coefficient (x10 11 Pa 1 ) Longitudinal Transverse Low E OX High E OX Low E OX High E OX (100) <110> expected 32 13 32 15 13 15 (100) <110> measured 25 (2) 9 (5) 19 (8) 6 (6) (100) <100> expected 47 13 82 22 13 35 (100) <100> measured 36 (7) 20 (10) 15(8) 9 (11) DEPMOS coefficient (x10 11 Pa 1 ) Longitudinal Transverse Low E OX High E OX Low E OX High E OX (100) <110> expected 71 13 71.8 16 32 13 66.3 16 (1 00) <110> measured 52 (22) 51(24) 32 (7) 32 (6) (100) <100> expected 1 14 6.6 16 23.8 14 1.1 16 (100) <100> measured 7 (2) 11 (4) 26 (8) 19 (8) Modeling : The coefficient of a laterally diffused power MOSFET is estimate d b ased o n the device model whic h consists of an enhancement mode MOSFET in series

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50 with a resistor [38 40] At low V G (weak inversion), the channel resistance ( R CH ) dominates the on resistance ( R ON ). Thus the coefficient of the power device is predicted to be similar to the logic MOS FET. At high V G R ON is dominated by the drift resistance ( R D ). Hence, the coefficient is expected to be ident ical to bulk silicon (Si) coefficient Based on this c oncept, the expected values for the coefficient of power MOSFET are listed in Table 3 3 The values for the logic MOSFET were taken from [8] Since the bulk coefficient is dependent on the doping concentration [43] measured values of n well resistor on the wafer were used and these values were values for n bulk [47] values were used for p bulk [9] As mentioned earlier, in order t o accurately estimate the coefficient of the power MOSFET along different orientations, it is important to understand the effect of strain on all components of R ON For the LDMOSFET, R ON is the su m of channel resistance ( R CH ), accumulation resistance ( R ACC ), spread resistance ( R S ), and drift resistance ( R D ) [41] The coefficient of R S ( S ) is a function of the angle of spread of carriers into the bulk of the drift region. For materials with cubic symmetry such as Si, the coefficient along any direction can be determined from the piezoresistance tensor and direction cosines [42, 43] The de pendence of S on spread angle for <110> n channel device under longitudinal tensile stress shown in Figure 3 9 is derived as shown in Equation 3 3. Similar expressions can be derived for all stress type and directions and the result in the form of polar plots are sh own in F ig ure 3 9 1 0

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51 A B Figure 3 9. N bulk piezoresistance vs. angle of spread in drift region under stress A) Longitudinal B) Transverse

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52 A B Figure 3 10 P Bulk p iezoresistance vs. angle of spread in drift region A) Longitudinal stres s B) Transverse stress At low V G R ON is almost completely dominated by R CH At high V G the percentage contribution of each component to R ON for N LDMOS is shown in Figure 3 1 1 Since carriers are confined to the surface both in inversion ( R CH ) and accumul ation ( R ACC ), the coefficient of these resistances is similar to that of the logic MOSFET ( MOSFET ). On the other hand the drift resistance is similar to a bulk Si resistor ( Bulk ). Utilizing the

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53 coefficient of bulk Si and logic MOSFETs from Table 3 3 and associating a weight to each of the contributing resistance from the resistance distribution, it is possible to calculate the coefficient of lateral power MOSFET for a given V G and channel orientation. In case of N LDMOSFET, for rated V G (3 4 ) Wh ere x is a fitting parameter represent ing the percentage contribution of the R S For the <110> channel N LDMOS, LDMOS MOSFET = 32 and Bulk = 32. Since the geometry of the STI causes the electrons to spread at an angle of ~ 80 o S from F ig ure 3 10 at this spreading angle is 34. Substituting these values into E q uatio n 3 4 the value of x is determined to be 0.21. With this value of x in Equation 3 4 the calculated transverse coefficient for <110> channel is 2 as opposed to the measured value of 6 Simi larly using the polar plots in Figure 3 10 to determine S and using x=0.21, the calculated longitudinal and transverse coefficients for <100> channel N LDMOS are 26 and 10 respectively. T hese calculated values are very cl ose to the measured values. Figure 3 11. On Resistance distribution of N LDMOS at rated gate bias Un like the LDMOSFETs, DEMOSFETs have long channel lengths. Thus, in these devices R CH remains the dominant contributor of R ON even at high V G This result s in the

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54 high V G coefficient of DEPMOS to be similar to that at low V G as observed from Table 3 3. High Stress Experimentally measured linear drain current enhancement with stress on <100> = oriented NLDMOS and <110> oriented DEPMOS is shown in Figure 3 1 2 N o saturation e ffects or non linearity was observed in lateral power MOSFETs even at stresses as large as 500MPa. Thus performance predictions can be made using a linear relationship between the coefficient and applied stresses up to half a GPa. Figure 3 12. Linear drain current enhancement under high stress Device Voltage Rating In order to increase the amount of voltage the device can withstand the length of the drain extension or drift region is increased. This causes the drift resistance of the device to become t he dominating component of R ON as device rating increases. An increased R D RIFT means that the coefficient of the power MOSFET becomes closer to the bulk value.

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55 Figure 3 1 3 shows the measured strain enhanced drain current of <100> NLDMOSFET and <110> DEPMOSFET with increasing drift length. As observed I DLIN of <100> channel N LDMOS is seen to i ncrease as the drift region length ( L Drift ) of the device increases. With increase in L Drift the contribution of the R S to the total R ON r educes resulting in the coefficient of the N LDMOS to approach that of n bulk For DEPMOSFETs, the low voltage rated device has no STI in the drain extension region. Thus, the lack of R S results in of low breakdown device being similar to the bulk value. As L Drift increases to increase breakdown voltage, a thick STI oxide is introduced in the drift region to red uce surface field. Despite the increase in spread resistance due to the STI geometry, no dependence with L Drift is seen from Figure 3 13 for the <110> channel DEPMOS This is because longitudinal compressive stress d oes not alter the spread resistance sign ifi cantly as shown in Figure 3 11. Figure 3 13. Linear drain current enhancement versus stress with increasing drift region length

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56 Summary Under 1GPa mechanical stress the maximum expected I DLIN enhancement is ~20% for n type and ~5 0% for p type powe r MOSFET with the breakdow n voltage shifting < 1 V The s train induced on resistance improvement was largest for the <100> N LDMOS channel making it the preferred orientation for the strained n type power device. For DEPMOS dev ices on (100) wafer the large coefficient along the <110> direction makes it the preferred channel orientation. Modeling showed the contribution of the spread resistance is significant and needs to be factored when predicting the behavior of the strained lateral power device. With ap plication of strain technology and careful device design to minimize spreading it is po ssible to significantly reduce on resistance for a given breakdown voltage.

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57 CHAPTER 4 SIMULATION OF STRAIN ED MEMORY AND LDMOSFET Introduction From the previous chapter s, it is clear that strain improves data retention in Flash memory and reduces on resistance in N LDMOSFETs It is also sh own to deteriorate retention in Dynamic Random Access Memory (DRAM). T his chapter investigate s the incorporat ion of stress via pro cess in the Flash and power MOSFET devices and identifies the amount of process induced stress in DRAM structures Current CMOS processing techniques include several methods to incorporate strain into device structure. Uniaxial str ess is introduced via cappin g layers and embedded S ource /D rain regions Channel stress as high as 1GPa has been reported [48, 49] Biaxial stress on the other hand is produced by growing a silicon layer over relaxed Si Ge. The lattice mismatch introduces biaxial stress in the Si layer. T he industry has adopted uniaxial str ess over biaxial str ess because of the larger performance improvement [50] Although there ha s been significant discussion on the effect o f STI induced compressive stress on device behavior [51 54] logic technology rarely uses STI induced mechanical stress for performance enhancement. This is due to the irregular patterni ng of STI. The structure and dimensions of Flash and power devices are very different from logic devices. In general, flash has thick gate stack layer to store data and power devices have large drift regions in order to withstand high voltages. Thus applyi ng processing techniques of logic devices to strain these devices may not be efficient. Simulation is a n effective and cost saving method to investigate the various structures to incorporate stress in these devices.

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58 Overview of Simulation tool S Process (S entaurus process) and ISE FLOOPS (Florida Object Oriented Process Simulator) are the two primary tools used to investigate the stress in device structures. The main goal of the simulation is to determine the best method to effectively strain the device st ructure s that benefit from str ess For this reason simple structures without the complication of actual process ing conditions are used. FLOOPS is a front end process modeling tool that is extremely useful in determining process induced stress in strained s ilicon devices. It is based on C++ and uses ALAGATOR as the scripting language. Stress in the device is determined by the stress solve command. Elastic model is used, i.e. all the stress induced displacements are within elastic limit. The boundary conditio ns are reflecting since the device stress is assumed to be un affected by the boundary. Stress and strain in a complex device structure is obtained by solving basic D the simulated node to obtain the displacement with the stiffness matrix given as equation 4 1. From the d isplacement strain and stress at each node is obtained as below. (4 1) (4 2) (4 3) S Process is a multi dimensional process simulation tool based on FLOOPS developed by Synopsys. Th e scripting language is Alagator. Three dimensional

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59 structures were simulat ed using this tool. Stress is determined by solving force equilibrium equations at all nodes of the mesh consisting of tetrahedrons. Various mechanics models are available for solvi ng stress in materials such as: Viscous, Viscoelastic, Elastic, etc. Elastic model is used in our simulations along with the default Dirichlet boundary conditions which initializes the velocity normal to the plane as zero. This boundary condition is applie d to left, right, front and back surfaces. The strain tensor in S Process like FLOOPS consists of two parts: Deviatoric which describes the material behavior under arbitrary deformation without change in volume and Dilatational which describes the behav ior when there is a pure volume change. Built in stress in materials can easily be defined as well as stress caused by thermal and lattice mismatch. Simulation Setup 2D simulation using FLOOPS and 3D simulations using S Process were executed. Mesh was cho sen such that the area of interest in the device had closely spaced nodes (5 100nm) resulting in a tight mesh. Mechanical constants were initialized to the values shown in Table 4 1 The stress in str ain ing layer (oxide/capping layer) was incorporated as a n intrinsic isotropic stress. Stress in the device structures were analyzed using Stress solve / Mechdata command and stress contour plots were generated at various device cross sections. Since the magnitude of stress changes with the material constants, am ount of intrinsic stress, layer thickness es and presence of structures such as spacer, the numerical results from these simulations may not be an exact reflection of that present in the actual device. However, the trends obtained, gives insight into strain ed devices.

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60 Table 4 1 Material Constants used in simulation Material Modulus (G P a) ratio Bulk Shear <100> Silicon 79 54 132 0.22 <110> Silicon 98 79 168 0.22 Ni tride 185 122 300 0.23 Oxide 34 31 72 0.15 Strain in DRAM Transistor One of the conclusions in Chapter 2 was that GIDL current in transistors increased nearly 2 3% in for 100MPa of mechanical stress. This is a real concern in DRAM. Historically the industry was focused on reducing the mechanical stress inherent to fabrica tion to improve DRAM retention [55, 56] However with the current technology nodes incorporating strained silicon to boost device performance, the amount of stress in the lowly doped drain (LDD) where GIDL takes place, becomes even more significant. The 2 D simulation structure involves a MOSFET with tensile CESL with isotropic stress of 1.2GPa. Channel lengths ranging from 45nm 10um were studied. The mesh was chosen so as to be fine near in the channel region and coarser deeper into the substrate. Th e stress values were taken 50A below the surface of silicon at the channel center.

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61 Strained Flash Memory Device Both floating gate and mirror bit f lash memory retention shows im provement under the application of tensile stress [ 33 ] Currently the structure shown in Figure 4 1 is commercially available from A p plied M aterials. Unlike logic, Flash memory has repeating patterns of STI. This makes STI stress an excellent option to st rain these devices. Normally STI induced stress is compressive in nature. However by using High Aspect Ratio Process (HARP) [57] it is possible to generate tensile stress using STI. This method along with pre metal dielect ric stress is used in Figure 4 1 Figur e 4 1. Applied Materials scheme for strained NAND Flash. (Courtesy AMAT) In this work, the effectiveness of HARP STI along with PMD on a multi gate structure shown in Figure 4 2 was simulated using 2D Floops. Tensile stress of 1GPa magnitude was the intri nsic stress present in PMD and oxide layers. The stress in the memory was monitored in the c enter of the array at 100A below the silicon/oxide interface

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62 Figure 4 2. Multi gate simulation structure with HARP STI and PMD Strained LDMOSFET From the measure d coefficient it is clear that the application of certain types of mechanical stress reduces power MOSFET on resistance without affecting its breakdown voltage. In case of <100> N LDMOSFET, longitudinal tension or transverse compression can reduce device o n resistance. However, an important consideration in moving to a newer technology is that the industry expects at least a 20% improvement in device performance to justify the increase in manufacturing cost. It is evident from table 4 2 that nearly 1 GPa st ress is needed for the required 20% reduction in on resistance.

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63 Table 4 2. Beneficial stress for N LDMOSFET Stress Type Strained Region Determination Reduction in R ON / GPa stress Longitudinal Tension Entire Device <100> N LDMOS 20% Transverse Compression Drift region <100> N Bulk resistor 17% Measured bulk coefficients indicate that for <100> N LDMOSFET, transverse compression on the bulk drift region can also significantly reduce R ON (~1.7% for 100MPa). This is because nearly 50% of R ON in LDMOSFET is contributed by drift region. Further in <100> oriented device, even the carriers spreading into the bulk of the drift region will experience transverse compression if the stress is along <110>. Thus all carriers are benefit ted by the applied transverse compression resulting in a reduction in spreading resistance. Nitride capping Nitride capping layers can apply either compressive or tensile stress on the entire device. However capping layers are most effective for short chan nel devices. Thus in order to use this method to strain power devices which have large drift lengths, dummy gates with short gate lengths are utilized throughout the drift region This structure was proposed in reference [58] and is shown in Figure 4 3.

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64 Figure 4 3. N LDMOSFET with dummy gates and nitride capping Th e simulation nested gate structure (Figure 4 4 ) is similar to Figure 4 3 and the dimensions are based on results from reference [ 59] Channel stress dependence on gate length illustrated in Figure 4 5 shows that above 50nm of gate length the stress in the channel is virtually negligible. Also the channel stress increases with decreasing gate length. Thus the dimension of the dummy gates is chosen to be 45nm. Since nearly a Giga Pascal of longitudinal tensile stress is required for 20% device performance improvement, a n in built isotropic stress of 1GPa is present in the nitride capping layer. The simulation is used to determine the stress contours along the drift region.

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65 Figure 4 4 2D capping layer on N LDMOSFET simulation structure Figure 4 5 Longitudinal channel stress vs. gate length in logic MOSFET with tensile capping layer [59] Y Z

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66 STI induced stress DIELEC RESURF [60] is a structure that is currently being investigated, since it has the potential to increase the breakdown voltage of the lateral power MOSFET s This structure shown in Figure 4 6 also has regular patterns of STI inte rleaving the drift region. Presence of the STI increases the depletion width across the reverse biased p n junction thus decreasing the electric field (Figure 4 7). The regular patterns of STI in this structure can be utilized to strain the drift region of the power MOSFET. Since drift region resistance ( R D ) accounts for more than half of the on resistance ( R ON ) of the device, stressing the drift region so as to reduce its resistance is also an effective method to reduce R ON Figure 4 6. DIELER structure

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67 Figure 4 7 Principle of Dielectric RESURF [ 60] 2D structure was simulated using FLOOPS and the three dimensional structure shown in Figure 4 8 was simulated using Sprocess. Dependence on active area (moat width) and STI dimensions was investigated alon g with the uniformity of stress along the STI depth. Figure 4 8 STI induced stress simulation structure for 2 D and 3 D

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68 A 17% reduction in on resistance is estimated by 1GPa transverse compression on the <100> oriented drift region. Even carriers that spread vertically into the substrate experience the transverse compressive stress, thus there is no detrimental effect due to the spreading of carriers. Results and Discussion Strain in DRAM Transistor The magnitude of stress at the center and gate edge in devices of different channel length is shown in Figure 4 9 As is seen from figure even long channel device s suffer from nearly 100MPa of stress at gate edge even though the channel stress is negligible This means that the GIDL is 2 3% larger than a dev ice without any capping layer. Thus effect of stress needs to be considered when considering strained transistors for DRAM. Figure 4 9 A process simulation of built in stress in the middle and the gate edge of the channel in a strained Si MOSFET with st ressed silicon nitride CESL

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69 Strained Flash Memory The simulation results (Figure 4 10 ) prove that as the distance between the STI increases (number of bits increases) the stress starts to decrease. Also the stress from the STI is maximum at its edges and progressively reduces as we move away from the STI. This means that as the number of gates in the multigated flash memory increases, the uniformity in the magnitude of the stress induced by the STI reduces. However this is overcome by the tensile PMD. The simulation result shows that STI or PMD alone is not as effective in straining the NAND flash as is the combination of the two. From the measurement on Flash devices, it was seen that even a small amount of tensile stress was able to make a measurable diff erence in retention. So strain ing the flash memory using PMD and STI can successfully enhanc e performance in these devices Figure 4 10 Stress in NAND flas h memory due to STI and PMD

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70 Strained LDMOS Nitride capping with dummy gates As seen from Figure 4 5 even at 45nm gate length the channel stress is ~400MPa. So the stress in device through this method is small. The dummy gate structure results in tensile stress beneath the gate but along the distance between the two gates, the stress becomes compressi ve (Figure 4 1 1 ) Thus stress uniformity is a concern in this structure especially since longitudinal compressive stress is detrimental to device performance. A Figure 4 1 1 Stress in nested gate structure A ) Expected simulation result of LDM OS with t ensile capping layer B) Actual simulation cross section from [60]

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71 B Figure 4 1 1 C ontinued Ga te to gate distance can be reduced to decrease the non uniformity of stress type along th e device However this comes with the price of reducing the magnitude of stress. Beyond pinch off (Figure 4 1 2 ), we can expect the stress to increase, however this method is strictly limited by processing considerations. Increasing the thickness of nitride layer might improve the stress magnitude as shown in inset. However as shown in Figure 4 1 1 the stress magnitude over the entire device is insufficient to produce any considerable gain in device performance.

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72 Figure 4 1 2 Stress in device center as a function of gate to gate separation. The inset [59] shows the change in stress in device center as a function of capping layer thickness Another issue in this method is that the magnitude of stress reduces drastically as we go deeper into the subs trate. This method is effective for producing stress on the surface; however electrons spread vertically into the substrate in LDMOSFET s So the success of this method to effectively improve power MOSFET device performance is questionable. STI induced stre s From results reported in reference [59] (Figure 4 13 ) STI is an excellent method to incorporate stress in devices The type and magnitude of stress will depen d on processing conditions of the STI oxide and dimensions of active and STI regions respectively. Stress produced via the STI interleaves is analogous to the channel stress

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73 induced by the Si Ge source drain in logic PMOSFETs. Thus significantly large valu e of transverse compressive stress is expected. Figure 4 1 3 STI induced stress in active region [59] From literature the stress is expected to b e uniform along the depth of the STI region [61, 62] and thus in LDMOSFETs even the carriers that spread into the b ulk of the drift region can be strained by choosing the depth of STI t aking the current flow pattern into consideration. 2D flo o ps simulation confirms the uniformity of STI induced compressive stress along the depth direction. Also magnitudes of stress are ~650MPa. Deeper trenches are more useful in straining LDMOSFETs sinc e the current spreads up to a micron depth in these devices.

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74 Figure 4 1 4 2D stress contours of STI induced stress in active drain extension fingers S process simulation of 3 D structure showed some interesting results. Not only was there large magnitu des of transverse compression, but there was also equally large out of plane tensile stresses present. Figures 4 15 through 17 show the stress contours in the silicon fin across device cross section taken in the center of the silicon fin of the 3 D simulat ion structure.

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75 Figure 4 1 5 Transverse compression along the fin Figure 4 1 6 Out of plane tension along the fin

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76 Figure 4 1 7 Longitudinal tension along fin Since drain extension or drift region contributes to nearly 50% on R ON 500MPa transverse c ompression predicted would result in R ON reducing by 17.5%. This calculation is a r esult of using piezoelectric coefficients measured previously. The 40MPa of longitudinal tension along the <100> oriented fin will result in a 3.2% reduction in R ON However also present was 600MPa of out of plane tension. This is equivalent to applying biaxial compression on the fin. This stress will degrade mobility and cause a n increase in R ON by 21%. Thus the result is that there is no net change in on resistance under stress. Summary Using simulation tools the best method to incorporate stress into Flash and LDMOSFET structu re was investigated. The combination of PMD and STI stress proved to be a successful method of straining NAND flash devices. Capping layer stress on LDMOS with dummy gates, however, was not effective. Preliminary simulation results

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77 on STI stress on drain e xtension fingers show the presence of a large out of plane tensile stress apart from the compressive stress perpendicular to direction of current. This stress counter acts the enhancement in carrier mobility produced by the compressive stress. Further inv estigation to overcome this stress will result in success of STI strained power MOSFETs.

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78 CHAPTER 5 SUMMARY AND RECOMMEN DATIONS FOR FUTURE W ORK Summary The effect of stress on memory retention and power MOSFET performance was measured and analyzed. Mechani cal stress was applied using four point wafer bending jig and I V characterization was done using Keithl e y 4200 SCS. Memory retention as a function of stress was analyzed by monitoring leakage and threshold voltage shift under data retention bake for memor y. Extracted piezoresistance and breakdown characteristics were determined for power LDMOSFETs. For memory, DRAM retention deteriorated with stress while Flash retention improved with tensile stress. Power MOSFET on resistance reduced with stress and no si gnificant shift in its breakdown voltage was observed. Under 1GPa mechanical stress the maximum expected I DLIN enhancement is ~20% for n type and ~5 0% for p type power MOSFET with the breakdow n voltage shifting < 1 V The s train induced on resistance impr ovement was largest for the <100> N LDMOS channel making it the preferred orientation for the strained n type power device. Thus with careful consideration memory and power device performance can be enhanced with mechanical stress. Recommendations for futu re work This work showed that stress was detrimental to DRAM retention. Future work in this area needs to concentrate on the reduction of stress in these devices. Strained retention can be studied in newly emerging Flash technologies such as TANOS and Fi nFET SONOS. Also effect of strain can be examined on exotic memory devices such as Magnetic RAM, FeRAM and phase change memory.

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79 In order to successfully incorporate stress in power MOSFETs, effect of strain on novel structures and devices on hybrid wafers need to be studied. STI shows a lot of promise to incorporate stress in DIELER structures. With proper choice of lining layers, this structure can be successfully manufactured. Process and device simulations on these structures will help understand the impact of strain and establish baseline numerical values as to the expectation of device improvements.

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80 LIST OF REFERENCES [1] G. Moore, "Progress in digital integrated electronics," IEEE International Electron Device meeting pp. 11 13 1975. [2] J. Welser, J. L. Hoyt, and J. F. Gibbons, "NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon germanium structures," presented at Electron Devices Meeting, 1992. Technical Digest., International, 1992. [3] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Y. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El Mansy, "A logic nanotechnology featuring strained silicon," IEEE Electron Device Letters vol. 25, pp. 191 193, 2004. [4] S. Natarajan, M. Armstrong, M. Bost, R. Brain, M. Brazier, C. H. Chang, V. Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He, R. Heussner, R. James, I. J in, C. Kenyon, S. Klopcic, S. H. Lee, M. Liu, S. Lodha, B. McFadden, A. Murthy, L. Neiberg, J. Neirynck, P. Packan, S. Pae, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J. Seiple, B. Sell, S. Sivakumar, B. Song, K. Tone, T. Troeger, C. Weber, M. Yang, A. Y eoh, and K. Zhang, "A 32nm logic technology featuring 2 nd generation high k + metal gate transistors, enhanced channel strain and 0.171 m 2 SRAM cell size in a 291Mb array," presented at Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 2008. [ 5] M. Chu, Y. Sun, U. Aghoram, and S. Thompson, "Strain: A solution for higher carrier mobility in nanoscale MOSFETs," Annual review of materials research vol. 39, 2009. [6] J. Lim, "Strain effects on silicon CMOS transistors: threshold voltage, gate tun neling current, and 1 /f noise characteristics," in Electrical Engineering PhD. Gainesville: University of Florida, 2007. [7] P. Hower, S. Pendharkar, and J. Smith, "Integrating power devices into silicon roadmaps," Iee Proceedings Circuits Devices and Sys tems vol. 153, pp. 73 78, 2006. [8] M. Chu, T. Nishida, X. L. Lv, N. Mohta, and S. E. Thompson, "Comparison between high field piezoresistance coefficients of Si metal oxide semiconductor field effect transistors and bulk Si under uniaxial and biaxial str ess," Journal of Applied Physics vol. 103, pp. 2008. [9] C. S. Smith, "Piezoresistance Effect in Germanium and Silicon," Physical Review vol. 94, pp. 42 49, 1954. [10] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, "Flash memory cells An overview," Proc eedings of the IEEE vol. 85, pp. 1248 1271, 1997.

PAGE 81

81 [11] R. Dennard, "FET memory," vol. 3387286. US, 1968. [12] D. Kahng and S. Sze, "A floating gate and its application to memory devices," The Bell System Technical Journal vol. 46, pp. 1288 1293, 1967. [1 3] AMD, "AMD Mirror Bit Flash," 2003. [14] B. J. Baliga, "Evolution of Mos Bipolar Power Semiconductor Technology," Proceedings of the IEEE vol. 76, pp. 409 418, 1988. [15] B. J. Baliga, Power Semiconductor Devices : PWS Publishing Company, 1995. [16] A. W Ludikhuize, "A review of RESURF technology," presented at Power Semiconductor Devices and ICs, 2000. Proceedings. The 12th International Symposium on, 2000. [17] J. Makwana and D. Schroder, "A non volatile memory overview." [18] I. C. Chen, C. W. Teng, D J. Coleman, and A. Nishimura, "Interface Trap Enhanced Gate Induced Leakage Current in Mosfet," IEEE Electron Device Letters vol. 10, pp. 216 218, 1989. [19] F. Gilibert, D. Rideau, A. Dray, F. Agut, M. Minondo, A. Juge, P. Masson, and R. Bouchakour, "C haracterization and modeling of gate induced drain leakage," I EICE Transactions on Electronics vol. E88C, pp. 829 837, 2005. [20] M. Rosar, B. Leroy, and G. Schweeger, "A new model for the description of gate voltage and temperature dependence of gate ind uced drain leakage (GIDL) in the low electric field region," IEEE Transactions on Electron Devices vol. 47, pp. 154 159, 2000. [21] C. Y. Cheng, Y. K. Fang, J. C. Liao, T. J. Wang, Y. T. Hou, P. F. Hsu, K. C. Lin, K. T. Huang, T. L. Lee, and M. S. Liang, "The effects of STI induced mechanical strain on GIDL current in Hf based and SiON MOSFETs," Solid State Electronics vol. 53, pp. 892 896, 2009. [22] R. Li, L. J. Yu, Y. M. Dong, and C. D. Wang, "Effect of STI induced mechanical stress on leakage current in deep submicron CMOS devices," Chinese Physics vol. 16, pp. 3104 3107, 2007. [23] W. Yang, X. Qin, X. Yu, and L. Tian, "Analysis of GIDL dependence on STI induced mechanical stress," Proceedings of the IEEE Electron Devices and Solid state ciruits pp. 769 772, 2005. [24] T. Krishnamohan, C. Jungemann, K. Donghyun, E. Ungersboeck, S. Selberherr, P. Wong, Y. Nishi, and K. Saraswat, "Theoretical Investigation Of Performance In Uniaxially and Biaxially Strained Si, SiGe and Ge Double Gate p MOSFETs," prese nted at Electron Devices Meeting, 2006. IEDM '06. International, 2006.

PAGE 82

82 [25] J. J. Wortman and J. R. Hauser, "Effect of Mechanical Stress on P N Junction Device Characteristics .2. Generation Recombination Current," Journal of Applied Physics vol. 37, pp. 3527 &, 1966. [26] J. F. Creemer and P. J. French, "The orientation dependence of the piezojunction effect in bipolar transistors," Proceedings of the European Solid state dvice research conference pp. 416 419, 2000. [27] J. F. Creemer and P. J. French, The saturation current of silicon bipolar transistors at moderate stress levels and its relation to the energy band structure," Journal of Applied Physics vol. 96, pp. 4530 4538, 2004. [28] M. Gurfinkel, J. S. Suehle, J. B. Bernstein, and Y. Shapira, "Enh anced Gate Induced Drain Leakage Current in HfO2 MOSFETs due to Remote Interface Trap Assisted Tunneling," presented at Electron Devices Meeting, 2006. IEDM '06. International, 2006. [29] D. Kim, T. Krishnamohan, Y. Nishi, and K. Saraswat, "Band to band tu nneling limited off state current in ultra thin body double gate FETs with high mobility materials: III V, Ge and strained Si/Ge," Proceedings of International Conference of Simulation of Semiconductor processes and Devices pp. 389 392, 2006. [30] Y. L. Yang and M. H. White, "Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures," Solid State Electronics vol. 44, pp. 949 958, 2000. [31] L. Lundkvist, C. Svensson, and B. Hansson, "Discharge of MNOS structures at elevated tem peratures," Solid State Electronics vol. 19, pp. 221 227, 1976. [32] A. Hamada and E. Takeda, "Hot Electron Trapping Activation Energy in Pmosfets under Mechanical Stress," IEEE Electron Device Letters vol. 15, pp. 31 32, 1994. [33] R. Arghavani, N. Derh acobian, V. Banthia, M. Balseanu, N. Ingle, H. M'Saad, S. Venkataraman, E. Yieh, Z. Yuan, L. Q. Xia, Z. Krivokapic, U. Aghoram, K. MacWilliams, and S. E. Thompson, "Strain engineering to improve data retention time in nonvolatile memory," IEEE Transactions on Electron Devices vol. 54, pp. 362 365, 2007. [34] J. A. Appels, M. G. Collet, P. A. H. Hart, H. M. J. Vaes, and J. F. C. M. Verhoeven, "Thin Layer High Voltage Devices (Resurf Devices)," Philips Journal of Research vol. 35, pp. 1 13, 1980. [35] T. Fujihira, "Theory of semiconductor superjunction devices," Japanese Journal of Applied Physics Part 1 Regular Papers Short Notes & Review Papers vol. 36, pp. 6254 6262, 1997.

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83 [36] M. Kondo, N. Sugii, Y. Hoshino, W. A. H. W. Hirasawa, Y. A. K. Y. Kimura, M A. M. M. Miyamoto, T. A. F. T. Fujioka, S. A. K. S. Kamohara, Y. A. K. Y. Kondo, S. A. K. S. Kimura, and I. A. Y. I. Yoshida, "High performance RF power LDMOSFETs for cellular handsets formed in thick strained Si/relaxed SiGe structure," presented at Ele ctron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005. [37] P. Moens, F. Bauwens, J. Baele, K. Vershinin, E. DeBacker, E. M. S. Narayanan, and M. Tack, "XtreMOS : The First Integrated Power Transistor Breaking the Silicon Limit," p resented at Electron Devices Meeting, 2006. IEDM '06. International, 2006. [38] S. Colak, "Effects of Drift Region Parameters on the Static Properties of Power Ldmost," IEEE Transactions on Electron Devices vol. 28, pp. 1455 1466, 1981. [39] M. D. Pocha a nd R. W. Dutton, "Computer Aided Design Model for High Voltage Double Diffused Mos (Dmos) Transistors," IEEE Journal of Solid State Circuits vol. 11, pp. 718 726, 1976. [40] S. C. Sun and J. D. Plummer, "Modeling of the on Resistance of Ldmos, Vdmos, and Vmos Power Transistors," IEEE Transactions on Electron Devices vol. 27, pp. 356 367, 1980. [41] M. Jian, G. Shan, C. Jun Ning, and K. Dao Ming, "The analysis and modeling of on resistance in high voltage LDMOS," presented at Solid State and Integrated Cir cuit Technology, 2006. ICSICT '06. 8th International Conference on, 2006. [42] D. W. Burns, "Micromechanics of integrated sensors and the planar processed pressure transducer," PhD: University of Wisconsin Madison, 1988. [43] Y. Kanda, "A Graphical Represe ntation of the Piezoresistance Coefficients in Silicon," IEEE Transactions on Electron Devices vol. 29, pp. 64 70, 1982. [44] D. Pattanayak, T. Chau, and K. Chen, "High mobility power metal oxide semiconductor field effect transistor." US: Vishay Siliconi x, 2008. [45] K. Throngnumchai, "Ultralow on Resistance P Channel Lateral Dmos Fabricated on (110) Oriented Si Substrate," IEEE Transactions on Electron Devices vol. 40, pp. 2132 2133, 1993. [46] M. Yang, E. P. Gusev, M. K. Ieong, O. Gluschenkov, D. C. Bo yd, K. K. Chan, P. M. Kozlowski, C. P. D'Emic, R. M. Sicina, P. C. Jamison, and A. I. Chou, "Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics," IEEE Electron Device Letters vol. 24, pp. 339 341, 2003. [47] K. Matsuda, K. Suzuki, K. Yamamura, and Y. Kanda, "Nonlinear Piezoresistance Effects in Silicon," Journal of Applied Physics vol. 73, pp. 1838 1847, 1993.

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84 [48] C. H. Jan, P. Bai, J. Choi, G. Curello, S. Jacobs, J. Jeong, K. Johnson, D. Jo nes, S. Klopcic, J. Lin, N. Lindert, A. Lio, S. Natarajan, J. Neirynck, P. Packan, J. Park, I. Post, M. Patel, S. Ramey, P. Reese, L. Rockford, A. Roskowski, G. Sacks, B. Turkot, Y. Wang, L. Wei, J. Yip, I. Young, K. Zhang, Y. Zhang, M. Bohr, and B. Holt, "A 65nm ultra low power logic platform technology using uni axial strained silicon transistors," presented at Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005. [49] A. Steegen, R. Mo, R. Mann, M. C. Sun, M. Eller, G. Leake, D Vietzke, A. Tilke, F. Guarin, A. Fischer, T. Pompl, G. Massey, A. Vayshenker, W. L. Tan, A. Ebert, W. Lin, W. Gao, J. Lian, J. P. Kim, P. Wrschka, J. H. Yang, A. Ajmera, R. Knoefler, Y. W. Teh, F. Jamin, J. E. Park, K. Hooper, C. Griffin, P. Nguyen, V. K lee, V. Ku, C. Baiocco, G. Johnson, L. Tai, J. Benedict, S. Scheer, H. Zhuang, V. Ramanchandran, G. Matusiewicz, Y. H. Lin, Y. K. Siew, F. Zhang, L. S. Leong, S. L. Liew, K. C. Park, K. W. Lee, D. H. Hong, S. M. Choi, E. Kaltalioglu, S. O. Kim, M. Naujok, M. Sherony, A. Cowley, A. Thomas, J. Sudijohno, T. Schiml, J. H. Ku, and I. Yang, "65nm cmos technology for low power applications," presented at Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005. [50] G. Y. Sun, Y. K. Sun, T. K. Nishida, and S. E. Thompson, "Hole mobility in silicon inversion layers: Stress and surface orientation," Journal of Applied Physics vol. 102, pp. 2007. [51] P. Fantini, G. Giuga, S. Schippers, A. Marmiroli, and G. Ferrari, "Modeling of STI induced stress phenomena in CMOS 90nm Flash technology," presented at Solid State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European, 2004. [52] A. Kahng, P. Sharma, and R. Topaloglu, "Exploiting STI stress for performance," in Procee dings of the 2007 IEEE /ACM international conference on Computer aided design San Jose, California: IEEE Press, 2007. [53] A. T. Tilke, C. Stapelmann, M. Eller, K. H. Bach, R. Hampp, R. Lindsay, R. Conti, W. Wille, R. Jaiswal, M. Galiano, and A. Jain, "Sha llow Trench Isolation for the 45 nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance," Semiconductor Manufacturing, IEEE Transactions on vol. 20, pp. 59 67, 2007. [54] L. Yuhao and D. K. Nayak, "Enhancement of CMOS performance by process induced stress," Semiconductor Manufacturing, IEEE Transactions on vol. 18, pp. 63 68, 2005. [55] J. W. Sleight, L. Chnan, and G. J. Grula, "Stress induced defects and transistor leakage for shallow trench isolated SOI," Electron Device Letters, IEEE vol. 20, pp. 248 250, 1999.

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85 [56] K. Tai Kyung, K. Do Hyung, P. Jae Kwan, P. Tai Su, P. Young Kwan, L. Hoong Joo, L. Kang Yoon, K. Jeong Taek, and P. Jong Woo, "Modeling of cumulative thermo mechanical stress (CTMS) produced by the shallow trench isol ation process for 1 Gb DRAM and beyond," presented at Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International, 1998. [57] A. Al Bayati, L. Washington, L. Xia, M. Balseanu, Z. Yuan, M. Kawaguchi, F. Nouri, and R. Arghavani, "Production pro cesses for inducing strain in CMOS channels," in Semiconductor Fabtech vol. 26, 2005. [58] S. Chu, Y. Li, G. Zhang, and P. Verma, "LDMOS using a combination of enhanced dielectric stress layer and dummy gates," Chatered Semiconductor Manufacturing LTD, 20 08. [59] N. Shah, "Stress modeling of nanoscale MOSFET," in Electrical and Computer Engineering vol. Masters. Gainesville: Florida, 2005, pp. 77. [60] A. Heringa and J. Sonsky, "Novel power transistor design for a process independent high voltage option i n standard CMOS," presented at Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on, 2006. [61] R. Liu and M. Canonico, "Applications of UV Raman spectroscopy and high resolution X ray diffraction to microelectronic mater ials and devices," Microelectronic Engineering vol. 75, pp. 243 251, 2004. [62] C. Stuer, J. Van Landuyt, H. Bender, R. Rooyackers, and G. Badenes, "The use of convergent beam electron diffraction for stress measurements in shallow trench isolation struct ures," Materials Science in Semiconductor Processing vol. 4, pp. 117 119, 2001.

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86 BIOGRAPHICAL SKETCH Umamahe swari Aghoram (Uma) was born in Chennai Indi a. In 2003, s he graduated with distinction from the University of Madras receiving a Bachelors deg ree in electrical engineering. She degree and doctorate in electrical and computer engineering from the University of Florida in 200 5 and 2010 respectively. She is currently employed as a process integration engineer in Texas Instrume nts Incorporated. Her areas of interest include semiconductor device design and circuits.