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Integrated Power Inductors in Silicon for Compact DC-DC Converters in Portable Electronics

Permanent Link: http://ufdc.ufl.edu/UFE0041226/00001

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Title: Integrated Power Inductors in Silicon for Compact DC-DC Converters in Portable Electronics
Physical Description: 1 online resource (136 p.)
Language: english
Creator: Wang, Mingliang
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2010

Subjects

Subjects / Keywords: converter, inductor, integrated, mems, molding, packaging, power, silicon, substrate
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

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Abstract: Integrated Power Inductor in Silicon for DC-DC Converters in Portable Electronics Candidate's name: MINGLIANG WANG Phone number: 352-392-1049 Department: Electrical and Computer Engineering Supervisory chair: Huikai Xie Degree: Doctorate Month and year of graduation: May. 2010 In this dissertation, a new class of integrated power inductor, called Power Inductor in Silicon (PIiS), is proposed and fabrication techniques have been developed to demonstrate the proposed idea experimentally. By embedding copper windings into silicon substrate, the PIiSs increase the Q of the micro-fabricated inductors at high frequency dramatically. The PIiSs can be used as packaging substrates to make integrated power systems even more compact. Therefore, the design and the techniques developed in this dissertation make it more feasible for micro-fabricated power inductors to be adopted in the real-world applications.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Mingliang Wang.
Thesis: Thesis (Ph.D.)--University of Florida, 2010.
Local: Adviser: Xie, Huikai.

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Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2010
System ID: UFE0041226:00001

Permanent Link: http://ufdc.ufl.edu/UFE0041226/00001

Material Information

Title: Integrated Power Inductors in Silicon for Compact DC-DC Converters in Portable Electronics
Physical Description: 1 online resource (136 p.)
Language: english
Creator: Wang, Mingliang
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2010

Subjects

Subjects / Keywords: converter, inductor, integrated, mems, molding, packaging, power, silicon, substrate
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Integrated Power Inductor in Silicon for DC-DC Converters in Portable Electronics Candidate's name: MINGLIANG WANG Phone number: 352-392-1049 Department: Electrical and Computer Engineering Supervisory chair: Huikai Xie Degree: Doctorate Month and year of graduation: May. 2010 In this dissertation, a new class of integrated power inductor, called Power Inductor in Silicon (PIiS), is proposed and fabrication techniques have been developed to demonstrate the proposed idea experimentally. By embedding copper windings into silicon substrate, the PIiSs increase the Q of the micro-fabricated inductors at high frequency dramatically. The PIiSs can be used as packaging substrates to make integrated power systems even more compact. Therefore, the design and the techniques developed in this dissertation make it more feasible for micro-fabricated power inductors to be adopted in the real-world applications.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Mingliang Wang.
Thesis: Thesis (Ph.D.)--University of Florida, 2010.
Local: Adviser: Xie, Huikai.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2010
System ID: UFE0041226:00001


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1 INTEGRATED POWER INDUCTOR S IN SILICON FOR COMPACT DC DC CONVERTERS IN PORTAB LE ELECTRONICS By MINGLIANG WANG A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIR EMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2010

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2 2010 Mingliang Wang

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3 To my parents and my wife

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4 ACKNOWLEDGMENTS First of all, I would like to thank my advisor Dr. Huikai Xie, for his continuous encouragement, patience, expert advice, guidance and support throughout my research. His profound knowledge and expertise in MEMS and other engineering fields are sources I can always rely on. I learned lots of from his methodology on research and his way on organizing stuff. I also would like to thank my co ad visor, Dr. Khai D. T. Ngo, for his kindness, help and guidance throughout my doctorate study and research. His broadband knowledge on power electronics provides a solid stage for my research. His kindness always encourage s me when I was struggling with my research. I would like to extend my appreciation to my Ph.D. committee members, Dr. David Arnold Dr. Fan Ren and Dr. Peng Jiang for their advice and comments. I am glad to have Dr. Arnold s attention and encouragement since the initial stage of my research I benefited a lot from his expertise in magnetic s His group had been helping me on magnetic material exploration and characterization throughout my research I am thankful to Dr. Ren for granting me the access to the equipments in his lab. I appreciate the help from my fellow group members at t he Biophotonics and Microsystem Lab. My special thanks go to Jiping for his tremendous help on process development and device characterization. Also I really enjoy my 4 years studying and working with Kemiao, Lei and Hongzhi. Their discussion and advice and help on my device fabrica tion are valuable. I am happy to share lots of pleasant memory outside of school When I sta rted my research at UF, I received lots of help from Hongwei, Ankur, Deyou and Jian that would never fade My friendship with Sagni k, Xuesong, Jingjing and Lin will always be cherished. My thanks also go to the members at the Interdisciplinary Microsystems Group at the University of Florida. I benefited from the research environment in IMG. Specially, I want to

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5 thank Naigang and his wife for their help on magnetic material p reparation and characterization; polishing; electroplating and thick photoresist pr ocessing. The fabrication of the devices was mostly carried out at the University of Florida Nano Fabrication facilities (UFNF). Thanks go to Al Ogdan, Bill Lewis and Dr. Ivan Kravchenko at UFNF for their training and continuous support. I also thank Shan non Chillingworth, the department graduate coordinator, for her considerate help in my graduate study. I am grateful to my family and friends for their constant support and encouragements. I am deeply ind ebted to my parents for their unconditional support L ast but not the least, the endless love from my wife gives me the courage to complete my Ph.D. studies

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6 TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................................... 4 LIST OF TABLES ................................................................................................................................ 9 LIST OF FIGURES ............................................................................................................................ 10 LIST OF ABBREVIATIONS ............................................................................................................ 15 ABSTRACT ........................................................................................................................................ 16 CHAP T ER 1 INTRODUCTION ....................................................................................................................... 18 1.1 DC DC Converters ................................................................................................................ 18 1.2 Introduction to Inductor Basics ............................................................................................ 19 1.2.1 Basic Laws .................................................................................................................. 19 1.2.2 Design Formula .......................................................................................................... 21 1 .2.3 Properties of Magnetic Materials .............................................................................. 22 1.2.4 Loss Mechanisms ....................................................................................................... 24 1.3 Power Inductor Integration and Its Challenges ................................................................... 28 1.4 Proposed Solution ................................................................................................................. 30 1.5 Research Objectives .............................................................................................................. 31 1.6 Outline of this D issertation ................................................................................................... 31 2 STATE OF -ART TECHNOLOGIES FOR INTEGRATING POWER INDUCTORS IN DC DC CONVERTERs ............................................................................................................. 33 2.1 Integrated Power Inductors by Packaging Techniques ....................................................... 33 2.1.1 Co-Packaging .............................................................................................................. 33 2.1.2 Hybrid Inductors ......................................................................................................... 34 2.1.3 Inductors on Printed Circuit Board (PCB) ................................................................ 35 2.1.4 Inductors on Low Temperature Co-fired Ceramic (LTCC) .................................... 36 2.1. 5 Inductors on Magnetic Substrates ............................................................................. 37 2.1.6 Inductors on Magnetic Coated Bond -Wires ............................................................. 39 2.2 Integrated Power Inductors On Silicon ............................................................................... 40 2.2.1 Inductors with Air Core Coils ................................................................................... 40 2.2.2 Inductors with Sputtered Magnetic Materials .......................................................... 42 2.2.3 Inductors with Electroplated Magnetic Materials .................................................... 45 2.2.4 Inductors with Laminated Magnetic Cores ............................................................... 47 2.2.5 Inductors with Composite of Magnetic Powder and Polymer Bonder ................... 50 2.3 Power Inductors In Package vs Power Inductors On Silicon ............................................. 52 2.4 Tradeoffs and Challenges for Inductors On Silicon ........................................................... 54

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7 3 CONCEPT OF POWER INDUCTOR IN SILICON AND ITS ENABLING TECHNOLOGIES ...................................................................................................................... 56 3.1 Power Inductor in Silicon (PIiS) .......................................................................................... 56 3.1.1 Concept ....................................................................................................................... 56 3.1.2 Topologies of Inductors In Silicon ............................................................................ 57 3.1.2.1 Inductors In Silicon with Isolation Layers ..................................................... 58 3.1.2.2 Inductors In Silicon without Isolation Layers ................................................ 59 3.1.3 Merits of PIiS .............................................................................................................. 62 3.2 Silicon Molding Technique .................................................................................................. 63 3.2.1 Direct Silicon Molding Te chnique ............................................................................ 65 3.2.2 Polymer Enhanced Silicon Molding Technique ...................................................... 65 3.3 Development of Silicon Molding Techniques .................................................................... 67 3.3.1 DRIE ........................................................................................................................... 67 3.3.2 Creation of Direct Silicon Molds .............................................................................. 68 3.3.3 Creation of Polyme r Enhanced Silicon Molds ......................................................... 69 3.3.4 ThroughWafer Bottom -Up Electroplating .............................................................. 72 3.3.5 Polishing ..................................................................................................................... 76 3.4 Summary................................................................................................................................ 80 4 DESIGN AND FABRICATION OF PIiS WITH PERMALLOY CORE ............................... 81 4.1 Preparation and Charac terization of Electroplated Permalloy ........................................... 81 4.2 Topology and Dimensions of PIiS with NiFe core ............................................................. 82 4.3 Fabrication of PIiS with NiFe Magnetic Core .................................................................... 84 4.4 Characterization .................................................................................................................... 89 4.5 Summary................................................................................................................................ 92 5 DESIG N AND FABRICATION OF PIiS WITH MAGNETIC POWDER CORE ............... 94 5.1 Preparation and Characterization of Magnetic Material ..................................................... 94 5.2 Topology and Dimensions of PIiS with Magnetic Powder Core ....................................... 96 5.2.1 Topology of PIiS with Magnetic Powder Core ........................................................ 96 5.2.2 Specifications of PIiS with Magnetic Powder Core ................................................. 99 5.2.3 Dimensions of PIiS with Magnetic Powder Core .................................................. 100 5.3 Fabrication of PIiS with Magnetic Powder Core .............................................................. 102 5.4 Characterizations ................................................................................................................. 107 5.5 Summary.............................................................................................................................. 108 6 DEMO NSTRATION OF A COMPACT DC -DC CONVERTER WITH PIiS .................... 110 6.1 Approaches for Integrating DC DC Converters with PIiS ............................................... 110 6.1.1 One Chi p Integration ............................................................................................... 110 6.1.2 Integration by Wafer -to -Wafer Bonding ................................................................ 111 6.1.3 Integration by Die -to -Die Bonding ......................................................................... 114 6.2 Merits of DC DC Converters with Inductors In Silicon (PIiSs) ...................................... 115

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8 6.3 Demonstration of A Compact DC DC Converter ............................................................. 115 6.4 Characterizations ................................................................................................................. 118 6.5 Summary.............................................................................................................................. 122 7 SUMMARY AND FUTURE WORK ..................................................................................... 124 7.1 Summary.............................................................................................................................. 124 7.2 Future work ......................................................................................................................... 125 LIST OF REFERENCES ................................................................................................................. 128 BIOGRAPHICAL SKETCH ........................................................................................................... 136

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9 LIST OF TABLES Table page 1 1 Commercialized DC DC converters with integrated induc tors .......................................... 29 2 1 Inductors in package VS inductors on silicon ...................................................................... 53 3 1 Process parameters in silicon ICP DRIE system .................................................................. 67 3 2 Anisotropic SiO2 etch recipe on the Plasma Therm SLR770 ECR RIE system at UF ...... 69 3 3 Instruments for the electroplating system ............................................................................. 73 3 4 Copper electroplating b ath .................................................................................................... 73 4 1 Ni80Fe20 electroplating bath ................................................................................................... 81 4 2 Properties of e lectroplated Ni80Fe20 ...................................................................................... 81 5 1 Specs of the PIiS with magnetic powder core .................................................................... 100 5 2 Parameters of PIiS with magneti c powder core ................................................................. 102 6 1 Commercial step down DC DC converters in MHz without integrated inductors .......... 113 6 2 Specification of the int egrated buck converter with PIiS .................................................. 116 7 1 Comparison of the PIiS based converter and the commercialized converters with integrated inductors .............................................................................................................. 125

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10 LIST OF FIGUR ES Figure page 1 1 Schematic for a switching inductive DC DC converter ...................................................... 19 1 2 Demonstration Figures for (a) Ampere la w (b) Faladays law .......................................... 20 1 3 Hysteresis loop of magnetic materials .................................................................................. 23 1 4 Cross -section view of copper wires ..................................................................................... 25 1 5 B -H loop for induc tor using in DC DC converter ................................................................ 26 1 6 Schematic of induced eddy current loss ............................................................................... 27 1 7 Schematic 3D model of a PIiS ............................................................................................... 31 2 1 Integrated of commercial inductor with power IC in the same package ............................ 33 2 2 Hybrid inductors of planar coil ass embled with two ferrite E -cores .................................. 34 2 3 Hybrid toroidal inductor ........................................................................................................ 35 2 4 Perspective revi ew of PCB with integrated inductors and capacitors ................................ 35 2 5 Thin 60 W offline converter with PCB integrated transformer and capacitors ................. 3 6 2 6 Process of LTCC inductors .................................................................................................... 36 2 7 Demonstration of fully integrated DC DC converter with LTCC inductor ....................... 37 2 8 Spiral integrated inductor on Ni Zn ferrite substrate ........................................................... 38 2 9 Inductors fabricated on .......................................................................................................... 38 2 10 Packaging of power IC chip and magnetic substrate with integrated inductor .................. 39 2 11 Coating of magnetic material on the bond wires .................................................................. 39 2 12 Microphotograph of on-chip 2 nH inductor for 170 MHz DC DC converters .................. 41 2 13 Photograph of DC -DC converters with IC chip and pas sive chip being flip -chip bonded ..................................................................................................................................... 41 2 14 Out of plane air core inductor by Plastic Deformation and Magnetic Assembly .............. 42 2 15 Perspective review of thin film inductor which was monolithic integrated on top power IC and its t op view ...................................................................................................... 43

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11 2 16 Cross -section view of inductor integrated on 130nm CMOS process with 6 metal layers ....................................................................................................................................... 44 2 17 Photograph of the cr oss-section of a V -groove inductor with sputtered magnetic core .... 44 2 18 Common Topologies of micro inductor with electroplated magnetic core ........................ 46 2 19 A micro fabricated toroidal inductor with electroplated NiFe ............................................ 47 2 20 Cross -section view of laminated NiFe core by all aqueous -based electro -chemical process ..................................................................................................................................... 49 2 21 Prospective views of laminated NiFe core by using copper as sacrificial layer ................ 50 2 22 Schematic of laminated NiFe core by electroplati ng on the side walls of throughwafer silicon trenches ............................................................................................................. 50 2 23 Photograph of integrated inductor based on composite of ferrite powder and polymer bonder and its process sequence. ........................................................................................... 52 2 24 The trade -offs in the designs of integrated inductors. .......................................................... 54 3 1 Typical cross -section view of inductors on silicon .............................................................. 57 3 2 Cross -section view of the proposed inductors in silicon ..................................................... 57 3 3 Pot core PIiS with single layer of spiral winding and composite of magnetic powder and polymer ............................................................................................................................ 58 3 4 Pot -core PIiS with single layer of spiral winding and electroplated magnetic. ................. 59 3 5 Pot core PPIiS with double layers of spiral windings and composite of magnetic powder and polymer ............................................................................................................... 60 3 6 Toroidal type PIiS with magnetic power filled polymer ..................................................... 61 3 7 Cross -section view of through-wafer silicon molds for embedding metals/alloys /polymer or mixture into the silicon substrate. ..................................................................... 64 3 8 Direct silicon molding technique for emb edding metal/ magnetic into silicon substrate ... 65 3 9 Polymer -enhanced silicon molding technique for embedding metal/magnet ic alloy into silicon substrate. ............................................................................................................ 66 3 10 SEM picture of a 500 m deep and 100 m wide through wafer silicon trench with and negative slope sidewall ................................................................................................... 68 3 11 SEM of the cross section of direct silicon molds with 10 m thick Cu at the bottom.. .... 69

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12 3 12 SEM of remained thin layer of oxide wall after copper being electroplated and the silicon substrate being etched away to release the electrop lated copper. ........................... 70 3 13 SU 8 trenches transferred from through wafer silicon trenches .......................................... 71 3 14 Photograph (a) and SEM (b) of the composite of magnetic powder and polymer ............ 72 3 15 SEMs of the composite being filled into trenches with different widths.. ......................... 72 3 16 Schematic (a) and the photograph (b) of the electroplated setup ........................................ 73 3 17 Electroplated permalloy in direct silicon molds ................................................................... 74 3 18 Current density waveform of pulse reverse electroplating .................................................. 74 3 19 10 hours pulse -reverse electroplated 170 m thick copper in 200 m deep direct silicon molds ........................................................................................................................... 75 3 20 Improved simple but effective electroplating setup for high aspect ratio through wafer trenches bottom up electroplating. ............................................................................. 76 3 21 Photograph of CMP machin e ................................................................................................ 77 3 22 SEM of sample (a) over -electroplated, before polishing, (b) after polishing ..................... 78 3 23 Photograph of sample mounted 6 inc h sample holder for polishing................................... 79 3 24 SEM of polished sample by the polishing setup at UF ........................................................ 79 4 1 BH curve of electroplated Ni80Fe20...................................................................................... 82 4 2 Schematic model of PIiS with NiFe core ............................................................................. 83 4 3 Cross -section views of the SU 8 enhanced process flow for integrated p ower MEMS inductors .................................................................................................................................. 85 4 4 SEM of the device after 2.5 turns Cu winding and NiFe vias are electroplated and the surface is polished. ................................................................................................................. 88 4 5 Optical microscope picture of the fabricated pot core inductor. ......................................... 88 4 6 SEM of the cross -section view along the a a line in Figure 4 4. ....................................... 89 4 7 Schematic of DC resistance measurement by a 4 -probe testing setup. ............................... 90 4 8 Schematic of inductance and equivalent AC resistance measurement by a 4 -probe. ........ 91 4 9 Measured inductance versus frequency ................................................................................ 91

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13 4 10 Equivalent resistance versus frequency ................................................................................ 92 4 11 Q versus frequency ................................................................................................................. 92 5 1 BH curve of the composite of ferrite powder 89wt% and PDMS 11wt% ........................ 95 5 2 Photos of (a) donut shape plastic molds made by a fast prototyping machine; and (b) a hand wounded toroidal inductor with magnetic composite .............................................. 95 5 3 3D models of hand wound inductors .................................................................................... 96 5 4 Schematic and 3D models of PIiS based converter ............................................................. 97 5 5 Inside view of PIiS ................................................................................................................. 97 5 6 Flux distribution in PIiS with and without magnetic in between the spacing .................... 98 5 8 the efficiency versus DC resistance of inductor ................................................................. 100 5 9 Parameters of optimized PIiS .............................................................................................. 101 5 10 The magnetic flux distribution of the design PIiS with magnetic powder ....................... 101 5 11 Cross -section view of the process flow .............................................................................. 103 5 12 Photos of the solder balls manipulation system ................................................................. 104 5 13 Schematic of th e solder ball being stamped on silver epoxy layer ................................... 104 5 14 Photo picture of the device after the winding, ring and vias being embedded into silicon substrate and the silicon between winding be ing etched away. ............................ 105 5 15 Photo picture of the device after the magnetic composite is filled and polished; and solder balls are bonded on the top. ...................................................................................... 105 5 16 Photo picture of the device after the magnetic composite being compressed on the top and being polished until solder balls are exposed. ....................................................... 105 5 17 Photos of a fabrica ted PIiS. (a) Frontside of a single PIiS die; (b) Backside of a PIiS; (c) Cross -section view of a PIiS; and (d) PIiS compares to a US dime ............................ 106 5 18 Test fixture for open calibration and short calibration ..................................................... 108 5 19 Measured inductance versus frequency .............................................................................. 108 6 1 Schematic of single-chip integration of PIiS and power ICs. ........................................... 111 6 2 Schematics of an PIiS wafer and an IC wafer before wafer to wafer bonding. ............... 112

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14 6 3 Illustration of wafer bonding of power ICs and PIiSs with magnetic composite. ........... 112 6 4 Cross -section view of bonded PIiSs and ICs ...................................................................... 112 6 5 Cross -section view of wafer le vel bonded PIiSs and ICs after the bulk silicon substrates of ICs are polished away to reduce the totally thickness of the converter. ..... 113 6 6 An integrated converter by die -to -die bonding PIiS power IC chip and capacitors. ...... 114 6 7 Photo of the converter after the PIiS being mounted on the top of testing PCB .............. 116 6 8 Ph oto of the converter after the IC chip being mounted on the top of the PIiS ............... 117 6 9 Photo of the converter after the capacitors being mounted on the top of the PIiS ........... 117 6 10 Photo of a DC DC converter with PIiS on a testing PCB board ....................................... 117 6 11 Photo of the TIs evaluation board of TPS 62601.............................................................. 118 6 12 Schematic for measuring the inductor current .................................................................... 118 6 13 Probed inductor current of the DC DC converter with a PIiS ........................................... 119 6 14 Schematic of the power stage of buck converter ................................................................ 120 6 15 Schematic for measuring the efficiency of the demonstrated converter ........................... 121 6 16 DC DC converters efficiency versus output current ........................................................ 122 6 17 DC DC converters efficiency versus temperature ............................................................ 122

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15 L IST OF ABBREVIATIONS DRIE Deep reactive ion etching IOS Inductors on silicon MEMS Micro Electro -Mechanical Systems PIiS Power Inductors in silicon PMIC Power management integrated circuit PSiP Power system in packaging PSoC Power system on c hip SEM Scannin g electron microscopic

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16 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy INTEGRATED POWER INDUCTOR S IN SILICON FOR COM PACT DC DC CONVERTERS IN PORTAB LE ELECTRONICS By Mingliang Wang May 2010 Chair: Huikai Xie Major: Electrical and Computer Engineering DC DC converters provide various DC voltage supplies required by electronic devices. Among all converters, the switching -mode DC DC converter is most popular due to its high power density with high efficiency. It typically consists of switching MOSFETs, control circuits, power capacitors and power inductors. Modern portable electronics devices are becoming more and more co mpact while having more features integrated which demand more power. In order for semiconductor industry to meet the market need, it is imperative to reduce the size and increase the power density of DC DC converters. Switching MOSFETs and control circuits are integrated, but power passives, especially inductors, are still bulky and off -chip components, which become the obstacle to further reduce the size of DC DC converters Powe r Systems in Packaging (PSiP) and Power System s on Chip (PSoC) are the two mos t commonly used approaches to integrate power inductors with power ICs. PSiP uses off -shelf inductors, so they can handle large power but the ir size reduction is limited. PSoC integrates power inductors directly on IC chips This approach can minimize the size by taking advantages of the microfabrication but it still needs to overcome the small inductance and/or low quality ( Q ) of thin -film inductors to be practically useful.

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17 In this dissertation, a new type of microfabricated power inductor, called Power Inductor in Silicon (PIiS), is proposed and experimentally demonstrated. Instead of fabricating the power inductor on the top of silicon substrate, the PIiS is fabricated into the silicon substrate to fully use the space of the inside and both sides of th e substrate. T hick copper windings are embedded into the silicon substrate and have the same thickness as the substrate ranging from 200~500 m, which results in very low DC resistance Two magnetic plates are fabricated on both sides of the substrate and are connected by magnetic vias, which form the magnetic core to boost the inductance. Therefore, PIiS has large inductance and high Q PIiS can be batch fabricated at wafer level and can be integrated with power ICs by die to -die, die to -wafer or wafer -to -wafer bonding. Additionally, t hrough -silicon vias (TSV) are fabricated simultaneously with the copper windings in PIiS, so t he PIiS is surface mount ready and can be used as a packaging substrate eliminating the need of bonding wires or lead frames In t his dissertation, a silicon molding technique for embedding thick copper winding into the silicon substrate is developed. A PIiS with a permalloy core and a PIiS with a magnetic powder core are designed, fabricated and characterized. A compact DC DC conver ter based on a PIiS is also demonstrated and tested to verify t he feasibility of the technique. Such a compact DC DC converter has great potential application in the portable electrics that demand small and high performance DC DC converter.

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18 CHAPTER 1 IN TRODUCTION This work is focused on developing inductors which have small size but large inductance and low loss. A compact DC DC converter based on the developed inductor has also been demonstrated. This chapter gives a brief introduction of DC DC converte rs, the current technological challenges for inductor integration and the proposed solution. 1.1 DC-DC Converters Modern portable electronics devices, such as cell phones, GPS and PDAs, are getting smaller but at the same time having more and more features embedded which need more power. Thus, smaller, smarter and more efficient DC DC converters are needed. Three kinds of DC DC converters widely used in portable electronics are linear converters, switching capacitive converters and switching inductive conve rters. At early times, linear converters were the primary converters that were fully integrated on the chip due to the easy integration. A linear converter only requires a MOSFET and a feedback loop. No inductive components are needed. Therefore, it is sma ll and low cost. However, its power converting efficiency and power density are low, especially when the voltage conversion ratio is high. Thus, its application is limited to low power and it is usually used where cost and size are more important than effi ciency. Switching capacitive converters do not have inductive components. They transfer the power from the supply to the load by charging and discharging capacitors, which results in better efficiency than linear regulators. The capacitors are in the pF ra nge and can be easily integrated on IC chips with acceptable chip areas. However, there is a trade-off between the accuracy of the output voltage and the power conversion efficiency. At the optimized operating points, the typical efficiency is lower than 80% for reasonable capacitance [1, 2]

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19 In contrast, s witching inductive converter s uses inductor s to transfer power fro m the battery to the l oad, which can lead to 100% efficiency in an ideal case. Moreover, it exhibits excellent transient performance, such as line/load regulations without sacrificing efficienc y [3]. Therefore, switching inductive converter s are the dominant DC DC converters when the require d power density is high and the efficiency is critical. In modern portable electronics, such as cell phone s the power -hungry subsystems are always regulated by switching inductive converters. [4] As s hown in Figure 1 1, a switching inductive DC DC converter consists of an off-chip power inductor, two off -chip power capacitors and power integrated circuits ( IC). Typically, t he integrated circuits for the DC DC converters in th e portable electronics are integrated in a single chip. Cout L Vin Vout Cin Error Amplifier Vref Gate Driver LoadIntegrated Circuits Figure 1 1 Schematic for a switching inductive DC DC converter 1.2 Introduction to Inductor Basics T his section briefly introduces some basic magnetic laws and the power loss mechanisms in inductors. 1.2.1 Basic Laws (a) Amperes Law

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20 As shown in Figure 1 2 (a), when a current flows in a one turn wingding, the relation between the induced magnetic field and the input current follows the Amperes law: path closedt I dl t H ) ( ) ( 1 .1 where H(t) is the magnetic field strength dl is the vector length of the flux path and I(t) is the total currents passing through the interior of the path. For a uniform magnetic field and n turns wi ndings, ()()()mHtlItnit 1 .2 where lm is the magnetic path length. (a) (b) Figure 1 2 Demonstration Figures for (a) Ampere law (b) Faladays law (b) Faradays Law As shown in Figure 1 2 (b), when a magnetic flux pass es through a wire loop, the relation between the induced voltage and the flux source follows Faladays law: ()() ()cdtdBt vtA dtdt 1.3 where ) ( t is the f lux passing through the loop, v(t) is induced voltage induced by the flux source, B(t) is flux density and Ac is the enclosed cross -section area of the loop. The induced voltage is proportional to the change rate of flux density. For n turns windings,

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21 ()() ()cdtdBt vtnnA dtdt 1.4 (c) Material characteristics and inductance The generated magnetic flux and the magnetic field strength are related by: ()() BtHt 1 .5 where, is the permeability of the magnetic material. It relates the flux density with magnetic field. Substitute equation ( 1 .5 ) into ( 1 4), () ()cdHt vtnA dt 1 .6 t hen, substitute equation ( 1 2) into ( 1 6), 2() ()c mnA dit vt ldt 1.7 which is of the form () () dit vtL dt 1.8 with 2 2 2n A l n l A n Lc m m c 1 .9 c mA l where is the reluctance of the core material, which is analogous to the resistance R in the electrical circuit. 1.2.2 Design Formula (a ) Inductance

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22 T he formula to calculate the inductance of an inductor with magnetic core and air gap is: c g c r m gap air magA l A l N N L 0 0 2 2 1.10 where, (b ) Flux Saturation Current The formula for the generated flux in the magnetic core is: cA N I L B 1.11 where I is the inductor current. The generated flux density in the core must be smaller than Bsat to avoid saturation. If the inductor enters the saturation region, it will lose the magnetic amplifica tion and work as an inductor with an air core. 1.2.3 Properties of Magnetic Materials (a) Permeability Permeability is one of the important properties of magnetic core materials. Analogous to conductivity to current, it describes the ease with which a magn etic flux is established in a core. The higher the permeability of a material is, the easier for the material to be magnetized. 0 r 1.12 N :number of turns : permeability c A :cross section area of magnetic path :length of magnetic path r :length of air gap gl ml

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23 where 0 is the permeability of free space, which is equal to 7410 H/m and r is the relative permeability. (b) Hysteresis Loop Figure 1 3 Hy s teresis loop of magnetic materials Figure 1 3 illustrates the hys teresis loop of a typical soft magnetic material. The hysteresis loop is a closed double -valued magnetization curve. This double valued phenomenon is caused by the energy loss in the core due to magnetization every cycle. There are three properties of this curve. First, the saturation flux density Bsat and the corresponding saturation current Isat are defined on the current flowing in the winding exc eeds a certain point Isat, the induced flux density will not increase significantly any more and the induced voltage v(t) is almost zero. Then the inductor will behave like a resistor, who resistance is the DC resistance of the winding. Second, the slope represents the permeability of the magnetic material. Third, the area of the hysteresis loop shows the energy that a magnetic core consumes per unit volume in each cycle. This area is generally characterized by Coercive ( Hc), as shown in Figure 1 -3. For magnetic materials in power inductor the smaller the Hc is, the less the loss will be (c) Skin Effect B sat B H H c

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24 The skin effect is the tendency of an alternating electric current to distribute itself within a conductor so that the current density near the surface of the conductor is greater than that at its center That is, the electric current tends to flow at the "skin" of the conductor. The following current density is an exponential function of the distance from the surface into the conductor. The characteristic length is the skin depth or penetration depth, which is given by: f 1.13 where is the conductivity of the conductor, is the permeability of the conductor, and f is the frequency of AC current. (d) Resistivity Increasing the resistivity wil l reduce the eddy current loss since the eddy current originates from the induced voltage in the core. For magnetic core for power applications, high resistivity core materials are always preferred. Unfortunately, high resistivity materials always come wit h low permeability. In the magnetic c ore design, there is always a trade off between these two properties. 1.2.4 L oss Mechanism s There are several energy loss mechanisms i n inductors: DC conducting loss; AC conducting loss; hysteresis loss and eddy current loss. Conducting losses are related to the conducting winding, while hysteresis and eddy current losses are related to the magnetic core. (a) DC conducting loss The majority energy loss of an inductor comes from its DC resistance ( RDC). The power loss due to DC resistance is given by: 2 _)( *rms LDC DC lossI R P 1.14

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25 where, DC lossP_ is the power loss due to DC resistance, and rms LI_ is the rms current of the inductor. For high performance inductors, DC conducting loss dominates and other losses need to be suppressed. (b) AC conducting loss There are two physical phenomena that generate AC conducting loss: skin effect and proximity effect. [3] Skin effect is the phenomenon that the AC current tends to accumulate on the surface skin of conductor, as shown in Fi gure 1 4 (a). Therefore, increasing the thickness of a conductor beyond the skin depth does not reduce the AC resistance. As shown in Figure 1 4 (b) and (c), the skin depth of copper at 1 MHz and 10 MHz are 67 m and 21 m, respectively. (a) (b) (c) Figure 1 4 Cro ss-section view of copper wires: (a) the current density at the surface is larger than the current density in the center; (b) skin depth of copper at 1 MHz is 67 m; (c) skin depth of copper at 6 MHz is 29 m. The proximity effect is a phenomenon that a conductor that carries a high frequency AC current will increase the AC resistance of an adjacent conductor. This proximity effect is pronounced in high current conductors, particu larly in high frequency AC converters. However, for inductors in portable electronics, whose currents are typically below 2 A, the AC loss due to proximity effect can be neglected. Skin depth

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26 (c) Hysteresis Loss Energy is required to generate a change in the magnetiz ation of a core material. Not all of the energy is recoverable in electrical form; so a fraction of the energy is lost as heat. This power loss can be observed electrically as the hysteresis of the B H loop, as shown in Figure 1 5 Figure 1 5 B -H loop for inductor using in DC DC converter [3] Consider an nturn inductor excited by a periodic waveform. The net energy that flows into the inductor over one cycle is cycle one m cHdB l A W ) ( 1.15 where the term ) (m cl A is the volume of the core and the integral is the area of the B -H loop T hen the hysteresis power loss is the energy loss per cycle multiplied by the frequency f i.e.; HPWf 1.16 So the hysteresis loss is proportional to the area of the hysteres is loop of the inductor and the switching frequency f (d) Eddy Current Loss Minor B H loop B sat B c H c0 H Large B H loop

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27 As shown in Figure 1 6 the AC current in the copper winding will induce AC flux in the magnetic core. A ccording to Lenzs law, AC magnetic flux will indu ce AC voltage within the core The voltage will i nduce current, which is called eddy current The eddy current loss is the loss generated by the eddy current. Figure 1 6 Schematic of induced eddy current loss [5] The power of the eddy current loss is given by: 2 2() ()e eevt PitR R 1.17 According to Faradays Law: dt t dB A dt t d t vc e) ( ) ( ) ( 1.1 8 The induced voltage ve(t ) is proportional to the derivative of the flux density () t In consequence, the magnitude of the induced voltage is directly proportional to the excitation frequency f Therefore, the eddy current loss is proportional to 2f Also the magnitude of the magnetic cores electrical impedance decreases with increasing frequency. So the eddy current loss typically increases faster than 2f which woul d become a serious problem in high frequency. The way to suppress eddy current loss is to reduce the thickness of the magnetic core close to or

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28 smaller than its skin depth. When the thickness of the magnetic core is in the same scale with the skin depth, t here will be not enough space for large eddy currents to be generated due to the skin effect. 1.3 Power Inductor Integration and Its Challenges Following the Moore s Law, the size of the power IC has rapidly decreas ed in recent years, while the bulky induc tor has become the bottleneck to further miniaturize a switching inductive DC DC converter The required inductance and the physical size of inductors are normally decreased with the increase of switching frequency. For example, over 100 MHz DC DC converte r s with only 1~10 nH inductors have been demonstrated. These inductors can be an air core inductor bonded on the package [6, 7] or by a spiral air -core inductor integrated on chip [8]. In current industry, high switching frequency over 100 MHz is in the phase of R&D, and is limited to low power applications Current technologies can not solve the problem of the ex tremely high switching loss generated from charging and discharging the gate capacitors of the power MOSFETs at such high switching frequency. Nowadays, the switching frequency of sta t e of the art DC -DC converters in portable electronics in the market ranges from1~10 MHz and the required inductance range s from 0.3~2H [9 11] With advanced technologies, it is possible to integrate small -size inductors with power ICs and realize fully int egrated DC DC converters. Such integrated DC DC converter s will be more compact and have lower cost and better transient performance. Many techniques have been developed to integrate inductors with power ICs and there are still numerous under -going research and development projects. Currently, Power System i n Packaging (PSiP ) [12] and Power System on Chip (PSoC) [13] are the two most widely adapted approaches for power inductor integration

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29 In PSiP, a power inductor and power ICs are either mounted side by side or stacked on a tiny substrate (PCB or lead frame), and th en they are packed inside one package. Generally, the power inductor is an off -shelf component, such as an SMT inductor [9, 14] an LTCC inductor [15, 16] an inductor in PCB [6], or an i nductor in magnetic substrate [17] It is capable to handle up to tens of amperes output current but its size reduction is limited by the packaging techniques DC -DC conv erters with integrated power inductors have been commercialized. Table 1 1 lists some products available in the market Table 1 1 Commercialized DC DC converters with integrated inductor s f sw (MHz) L (uH) V in (V) V out (V) I out (A) Footprint (mm3) LTM460 8 [18] 1.5 2.375 5.5 0.6~5 8 1592.8 EN5396 QI [10] 5 0.09 2.375~5.5 0. 75~5 9 10121.8 EN5368 QI [9] 4 0.5 2.4~5.5 0.6~ 5 0.6 3 1.1 MIC3385 [19] 8 0.47 2.7~5.5 0.6~5 0.5 33.50.9 LM3218 [14] 2 2.6 2.6~5.5 0.8~3.6 0.65 3 2.5 2 FB6831J [20] 2.5 2.7~5.5 0.8~ 5 0.5 2.92.41 More interestingly and promisingly, the emerging m icro e lectro m echanical s ystems (MEMS) technology provides a n unprecedented capab ility of producing high power -density inductors at the micron scale and monolithicall y integrating these tiny inductors on power ICs, and realizing Power System on Chip (PSoC), which can lead to further size reduction of power converters. Moreover, the waf er -level fabrication advantages of MEMS technologies will further reduce inductor s cost and ease the packaging. This approach miniaturizes a DC DC converter b y taking advantages of microfabrication and further reduce s the cost because of batch fabrication Several types of PSoC power inductors have been reported, e.g., spiral air core inductors [7, 21] sputtered magnetic inductors [22, 23] electroplated magnetic inductors [13, 24 28] and ferrite magnetic inductors [29, 30] These inductors are typically thin -film inductors fabricated

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30 on the top of CMOS substrates. The thickness es of t heir copper winding and magnetic core are in tens of microns, which result s in small inductance and/or low Q One of the challenges in fabricating integrated high -power density inductors is the difficulty in fabricating thick conductor layers with magnetic core s to a chieve low winding resistance and high inductance A single layer of copper coil up to 90m thick without a magnetic core was reported based on thick phot oresist electroplating molds [31] H owever, the inductances of this kind of air core ind uctors was not sufficient for converters wi th 1~10M Hz switching frequency and 1~10W output power. For power inductors with magnetic cores, three stacking layers (i.e., two layers for winding and one layer for core, or one for winding and two for core) are generally needed. The reported micro -fabri cated inductors suffered from high winding resistance and/or low inductance T he relatively large winding resistance is due to the difficulty to fabricate stacked thick highaspect -ratio electroplating molds and also due to the fact that all the inductor l ayers are stacked on a single side of the substrate. 1.4 Proposed Solution A solution i s proposed in this dissertation to address the challenges stated above. Instead of being stacked on a single side of a silicon substrate, three thick layers are distributed inside and both sides of a silicon substrate. For example, copper windings are embedded into silicon substrate and magnetic cores are stacked from both sides of the wafer. The copper windings are embedded into silicon substrate by electroplating copper into through -wafer silicon electroplating molds, which are created by De ep Reactive Ion Etch (DRIE). DRIE is a widely used silicon etching technique to create high aspect ratio silicon trenches. After the windings are embedded into the silicon substrate, thick magnetic cores will be fabricated on both sides of the silicon substrate by thick polymer photolithography techniques or by screen printing based on the magnetic materials. Figure 1 7 shows the schematic 3D model of a PIiS

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31 In this approach, the copp er can be as thick as the silicon wafer (200~500 m) and the thickness of the cores on both sides of the wafer can be tens or even hundreds of microns. Therefore, it has a great potential to demonstrate a power inductor with low DC resistance while maintai ning sufficiently high inductance. This kind of power inductor with the winding being embedded into silicon substrate is called Power Inductor in Silicon (PIiS) in this dissertation. Figure 1 7 Schematic 3D model of a PIiS 1.5 Research Object ives T he main goal of this research is to develop new inductor design and fabrication processes that can lead to monolithic integration of DC DC converters with high power and small size. The detailed research objectives are list below: (1 ) Design and develop the fabrication process based on the silicon molding technique. (2 ) Design and fabricate a PIiS based on the developed process. (3 ) Demonstrate a fully integrated DC DC converter with a PIiS. 1. 6 Outline of this Dissertation Chapter 1 briefly introduces basic s of DC -D C converters and power inductors. The integration of power inductors and the challenge s for inductor integration are discussed The proposed solution to address the challenge s is given. The research objectives are defined. Magnetic Cu winding Si substrate

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32 Chapter 2 gives the literature re view of state -of -the art technologies for integrated power inductors in DC DC converters. There are two main approaches to integrate inductors. One approach integrates power inductors by packaging technologies, while the other one integrates power inductor s on silicon. The reported techniques are reviewed and compared. The trade -offs in inductor design are analyzed and the c hallenges for integrating inductors on silicon are compared and discussed as well. Chapter 3 introduces the concept of PIiS and its mer its. Silicon molding techniques for embedding copper into the silicon have been described in detail. The critical processes for the silicon molding techniques have been developed. Chapter 4 presents a PIiS with a NiFe core. With an electroplated NiFe magn etic core, a PIiS has been designed, fabrica ted and characterized. Chapter 5 presents another PIiS with a magnetic powder core that has been designed, fabricated and characterized. Chapter 6 describes a compact DC DC converter based on a PIiS with a magnet ic powder core. The design, packaging and testing results are reported Chapter 7 summarize s this work and describes future work.

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33 CHAPTER 2 STATE OF -ART TECHNOLOGIES FOR INTEGRATING POWER INDUCTORS IN DC DC CONVERTER S In this chapter, the start of art te chnologies for integrated power inductors in DC DC converters are reviewed in detail. There are mainly two types of integrated power inductors. One type is integrated power inductors based on packaging, and the other type is integrated power inductors on s ilicon. A literature review of both types of integrated inductors is given in detail in this chapter. At the end of the chapter, the challenges and problems for integrating inductors on silicon are discussed. 2 .1 Integrated Power Inductors by Packaging Tec hniques 2 .1.1 Co -Packaging (a) Side by side (b) Stacking together (c) View of product from Enpirion Figure 2 1 Integrated of commercial inductor with power IC in the s ame package The most straightforward approach to integrate inductors and power ICs is to mount off shelf inductors and power ICs on the same lead frame or packaging substrate, as shown in Figure 2 1. SMT inductors are often used. In Figure 2 1 (a), the inductor and the IC chip are mounted I nductor Power IC I nductor Power IC

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34 side by side. This can be used for large output current applications, such as LTM4608 from Linear Technology (Iout = 8A) [18] and EN5396Q from Enpirion Inc (Iout = 9A) [10] When the output current is below 2 A, the inductor can be stacked on the IC chip to reduce the footprint, as shown in Figure 2 1 (b), e.g., LM3218 from National Semiconductor (Iout =0.65 A) [14] and EN5322QI from Enpirion Inc [9]. This approach requires small change on the DC DC converters with external inductors and is the easiest way to be adopted by industry. 2.1.2 Hybrid I nductor s In integrated hybrid i nductors, the coils are fabricated by microfabrication technologies, while the magnetic cores are fabricated separately. They are assembled to form hybrid inductors. Figure 2 2 shows an E -core type hybrid inductor, in which the coils were fabricated on a p olyimide fil 3 shows a toroidal type hybrid inductor. Figure 2 2 Hybrid inductors of planar coil assembled with two ferrite E -cores. [32]

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35 Figure 2 3 Hybrid toroidal inductor : size 2 mm5 mm250 mm (W, L, T). Ni80Fe20 core of O shape is assembled between windings by fli p -chip bonding [33] 2.1.3 Inductors on Printed Circuit Board (PCB) In the integrated inductors on PCB, both coils and magnetic cores are fabricated in PCB, as shown in Figure 2 4. The coils are fabricated by patterning the copper layers on the PCB. Magnetic materials are added to boost the inductor, which can be ferrite polymer compounds (FPC) [34, 35] or electroplated CoNiFe [36] NiFe [37] Then the PCB is used as packaged substrate for other components as shown in Figure 2 5. This approach takes full advantage of the PCB for i nductor fabrication, however its size and performance are limited [38] Figure 2 4 Perspective review of PCB with integrated inductors and capacitors [34]

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36 Figure 2 5 Thin 60-W offline converter with PCB integrated transformer and capacitors [34] 2 .1.4 Inductor s on Low Temperature Co -fired Ceram ic (LTCC) Figure 2 6 Process of LTCC inductors [16] Low temperature co -fired ceramic (LTCC) is a well -established multi layer technology which has been in use for many years in the microelectronics packaging industry. Each of the layers is processed in parallel and only brought together in an accurately aligned stack

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37 immediately prior to firing. [39] The fabrication process of LT CC inductors is shown in Figure 2 6 which is quite similar to the PCB approach except that it starts with LTCC tapes and is fired in 700~ 900 C after being stacked. PCB inductors can not be fired due to the PCB board material, which limits the permeability of the magnetic core. Although t he permeability of ferrite powder composites increases after firing, the achievable thickness of LTCC inductors is smaller than that of PCB inductors [15] For inductors made using LTCC tapes, the magnetic material may be NiCuZn [16, 29, 40] or NiZn [15] Figure 2 7 shows a fully integrated DC DC converter with an LTCC inductor [40] Figure 2 7 Demonstration of fully integrated DC DC converter with LTCC inductor [16] 2 .1.5 Inductors on Magnetic Substrates Instead of adding magnetic material s on the substrate magnetic substrates have been used for inductor integration [17, 30, 41] Similar to the PCB and LTCC approaches, t his approach also take s the full advantage of the space available on the packaging substrate. Furthermore, it removes the space of additional magnetic material. There are t wo topologies for inductors on magnetic substrates. The first topology is a spiral type. As shown in Figure 2 8, spiral coils are deposited on an Ni Zn ferrite substrate, and then are covered by a composite composed of MnZn powders and a polymer binder. T he second

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38 topology is toroidal, as shown in Figure 2 9. Through-substrate holes are punched on a magnetic substrate and then copper is electroplated through the holes. After the inductor is fabricated on the substrate, the inductor is stacked with a power IC chip and packaged, as shown in Figure 2 10. Figure 2 8 Spiral integrated inductor on Ni -Zn ferrite substrate [30] Figure 2 9 Inductors fabricated on [17]

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39 Figure 2 10. Packaging of power IC chip and magnetic substrate with integrated inductor [17] 2 .1.6 Inductors on Magnetic Coated Bond W ir es Figure 2 11. Coat ing of magnetic material on the bond wires [42, 43] It is well known that a bonding wire for packaging has certain inductance (1nH/mm). Generally, t he inductance is too small to be used in power converters and is treated as parasitic.

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40 However, magnetic materials have been coated on the surface of bond wires to increase the inductance, as shown in Figure 2 11. The coated magnetic materials may be a com posite of NiZn powder or MnZn powder mixed with a polymer binder. The inductance can be increased up to tens of times. This is a low cost technology, but it is difficult to control the inductance. 2 .2 Integrated Power Inductor s O n Silicon The other directi on for fully integrated DC DC converters is to integrate inductors on silicon by microfabrication technologies. The advanced microfabrication technologies for i ntegrated inductors on silicon enable one -chip solution or multi -chips stacking solution to real ize power system s on silicon [13] A variety of materials and fabrication technologies are available for integrated power inductors in package, but the available materials f or integrated power inductors on silicon are limited by the compatibility with silicon and IC technologies. In the following section, the reviewed technologies are categorized based on magnetic material fabrication methods. 2 .2.1 Inductors with Air Core Co ils Air -core inductors are popular for realizing i ntegrated inductors due to the rela tively simple structure and easy integration They are widely used in RF circuits. But they are difficult to be used in power converters due to the limitation of the achie vable maximum inductance. Recent advanced IC technologies allow power MOSFETs to switch at extremely high frequency (over 100M Hz) in acceptable switching loss [7, 8, 21, 44] In such high frequency, inductors in nH scale can meet the requirements of DC -DC converters in portable electronics and can be realized on IC chips with acceptable Q in decent chip area s The first kind of air core inductor on chip is the spiral inductors on metal layers in IC. Figure 2 12 is the microphotograph of a DC DC converter chip with a 2 nH inductor. Th e chip was implemented in a 130 nm CMOS technology with 8 metal layers and the inductor was built

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41 chip area was 600 m by 600 m. Figure 2 12. Microphotograph of on-chip 2 nH inductor for 170 MHz DC DC converters [8] (a)20 nH planar air core inductor (b) CMOS die flip -chipped on wafer with passives Figure 2 13. Photograph of DC -DC converters with IC chip and passive chip being flip -chip bonded [6] Spiral inductors by CMOS technology suffer from high resistance due to the thickness limitation of the interconnection metal layers. In [6] inductors and capacitors were fabricated on separate silicon wafers by micro fabrication techniques. The inductor was a 3 turn, 8 m -thick 13

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42 shows the fabricated inductor and the DC -DC converter with a CMOS die flip -chip bonded. The con verter switches at 80 MHz and outputs 1.1 V and 100 mA with a 65% efficiency. It is well known that in -plane spiral air inductors generate loss on silicon substrate. Out of plane spiral inductors were realized as shown in Figure 2 14, by post CMOS technolo gies to The inductor was fabricated in plane first and then was pulled out of plane by external magnetic force. The inductor stayed out of plane after the release of the external magnetic force due to plastic deformation. With the out of -plane inductor, a DC DC converter was implemented to output 75 mW output with an efficiency of 60% at 10 MHz. Figure 2 14. Out of plane air core inductor by Plastic Deformation a nd Magnetic Assembly (PDMA) [45] 2 .2.2 Inductors with Sputtered Magnet ic Materials Sputtering is a process whereby atoms are emitted from a solid target mate rial due to bombardment of accelerated energetic ions and deposit on the sample substrate Intensive studies have been done on sputtering magnetic material, especially i n the magnetic reading head industry. The magnetic materials by sputtering generally have excellent performance in high

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43 frequency, such as NiFe [46, 47] CoZrNb [48] CoZrRe [49] CoZ rTa [50] CoZrO [23] CoHfTaPd [22] FeCoBn [51] and FeBN [52] Figure 2 15 shows a report ed monolith ic DC DC converter by fabricating the inductor on the top of a power MOSFET in 2000 by Fuji Electronics The inductor consisted of two 9 m sputtered magnetic plates with a 35 m thick spiral copper winding sandwiched in the between. The magneti c material was CoHfTaPd, which was deposited by sputtering. With a 16 turn winding the inductor was 0.96 H, and the 0.35 A, 3V power at 3 MHz with a 83% peak efficiency. Figure 2 16 is a picture demonstrated by Intel to show an integrated inductor on its 130 nm CMOS process in 2007. The difference from Figure 215 was that this Intel inductor had magnetic vias to connect the top and bottom magnetic material. The magnetic plates were 2 m thick CoTaZr, which was also deposited by sputtering. The inductances were boosted 9 times compared to the corresponding air core inductor s. Up to tens of nH inductance can be achieved. These inductors are intended for over 100 MHz switching frequency applications. Figure 2 15. Perspective review o f thin film inductor which was monolithic integrated on top power IC and its top view [22]

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44 Figure 2 16. Cross -section view of inductor integrated on 130nm CMOS process with 6 metal layers [53] Figure 2 17. Photo graph of the cross -section of a V -groove inductor with sputtered magnetic core [54] Although isolation layers are generally needed betw een the conducting winding and magnetic core, the isolation layer is not needed when it comes to one turn topology. Figure 217 shows the cross-section of a V -groove inductor, which is a straight line copper covered by a sputtered magnetic material without isolation. This inductor had very small DC resistance due to large cross -section area, but it took a 11 mm length to obtain 8 nH. The converter output 8 A, 1.1 V power at 5 MHz with a 89% peak efficiency.

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45 There are limitations for power inductors with spu ttered magnetic materials. First, they suffer from small thickness (<10m) due to the thin film stress. Second, the sputtering deposition rate is very low, generally ~0.1nm per second, which causes long deposition time. Third, the resistivities of most of sputtered alloy are not high enough and lamination is required to suppress the eddy current loss. For example, 7 layers of 2 m CoZrTa were laminated by silicon oxide to form a 14 m thick magnetic core [50] 2 .2.3 Inductor s with Electroplated Magnetic Materials Electroplating is the most popular technology used for fabricating micro scale magnetic components. It has t he ability to build magnetic with thickness from a few microns up to several hundreds microns with deposition rate up to a hundreds microns per hour Also i t is a cheap and well studied technology and is a low temperature process compatible with most of other processes. Among the electroplated magne tic materials, NiFe and CoFe based alloys are the most attractive materials due to their favorable soft magnetic properties. The common alloys used in micro magnetic component s are permalloy (Ni80Fe20), orthonol (Ni50Fe50), amorphous cobalt iron -copper (Co FeCu) and supermalloy (NiFeMo). Different from sputtering, metals are only deposited in the molds by electroplating, enabling precise dimension and structure control. As described in previous section, spiral type is the major topology for inductors by sput tering. For inductors by electroplating, there are three common topologies: spiral type [28, 55, 56] toroidal type [25, 57 60] and meander type [61] as shown in Figure 2 18. All these kinds of inductors have three layers, one conducting layer and two magnetic layers, or one magnetic layer and two cond uctive layers. In toroidal type inductors, magnetic vias are added to close the magnetic path; while in meander type inductors, conducting vias are needed to connect the conducting path In some cases, magnetic vias are also added to boost the inductance in spiral type inductors.

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46 (a) Spiral type (b) Toroidal type (c) Meander type Figure 2 18. Common Topologies of micro inductor with electroplated magnetic core Magnetic Conducting Winding Magnetic Conducting Winding Magnetic Conducting Winding

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47 Their fabrication processes are quite similar. First, the bottom metal is electroplated. Then the isolation lay er is coated, followed by electroplating the middle metal layer. Next is the electroplating of vias. The final step is forming the top metal layer. Figure 219 shows a reported micro fabricated toroidal inductor with electroplated NiFe. Figure 2 19. A m icro fabricated toroidal inductor with electroplated NiFe [25] Most MEMS inductors with electroplated magnetic use NiFe alloy as the magnetic. However, NiFe alloy is not preferred in high frequency because it has large loss and low permeability in high frequency. An improved material, CoNiFe, has been reported to have better saturation flux density and higher resistiv ity [62, 63] and it has been used for integrated high frequency inductors [36] 2 .2.4 Inductors w ith Laminated Magnetic Cores Most magnetic materials by sputtering and electroplating have low resistivity. Thus the eddy current loss problem becomes serious in high frequency. It is well known that the eddy current loss can be suppressed when the thickne ss of the magnetic layer is smaller than the skin depth. So one way to reduce the core loss at high frequency, while maintaining sufficient core thickness, is using laminated multi layers cores. In bulk magnetic devices, low loss lamination

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48 cores are typic ally achieved by staking alternating layers of a core material and an insulating material. For micro magnetic devices, lamination is a big challenge for conventional micro fabrication technologies. Several approaches have been proposed and different lamina ted cores have been demonstrated. In 1999, a laminated core was fabricated by repetitively depositing polymer insulator, seed layer, and electroplating magnetic metal layers [64] The laminated core had 12m permalloy or 5m supermalloy layers isolated by 5m photoresist. This approach is straightforward like the stacking layers in bulk cores, but it is a cumbersome process which needs many transfers between an electroplating bath and a deposition chamber Also it needs many steps of photolithography alignment and each seed layer must be removed after the corresponding electrolating. In 2006, an all aqueous -based electro -chemical process was reported for laminating magnetic cores, as shown in Figure 2 20. An electrodepositable photoresist Eagle 2100 ED was employed to deposit the dielectric photoresist in an aqueous bath. The seed layers were deposited by electroless plating after photoresist surface activation. In this process, it was all aqueous -based and only one mask is needed at the first step. The following layers were selectively deposited. No seed layer removal was required. But the seed layer electroless -plating needed additional surface treatment. Again, this was a cumbersome process which series s urface treatments were needed for each layer. The process discussed above used dielectric layers between core layers. Another approach is that laminated core layers were suspended by each other, under the support of poles. By alternatively depositing NiFe and Cu layers and following by Cu removal, Park et al. fabricated another laminated cores [65 67] as shown in Figure 2 21. In this process, only one mask was used, and no surface treatment was required. But sacrificial Cu layers must be removed to obtai n

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49 lamination. Based on the same idea, Leith et al. fabricated laminated cores by alternatively electroplating nickel rich and iron -rich NiFe alloy layers and then removing the ironrich layers by potential -enhanced acid etching [68] So, all the electroplating processes of the core were carried out in the same bath. The sacrificial layers were electroplated by varying the electroplating conditions. Figure 2 20. Cross -section view of laminated NiFe core by all aqueous -based electro -chemical process [69] In addition to later al lamination mentioned above, vertical laminated cores were also demonstrated in two ways: partially filled trenches and fully -filled trenches [70, 71] Through wafer silicon trenches were created by DRIE and used as electroplating mold. In partially -filled trenches, magnetic core layers were electroplate d on the sidewall of the silicon trenches, and the core layers were separated by silicon and air gap alternatively, as shown in Figure 2 22. In the fully -filled trench method, the wafer with through -wafer trenches was attached to another wafer with a metal seed layer. Then the vertical core layers were filled into the vertical through -wafer silicon trenches. The big advantage of this approach is that all the laminated vertical core layers were fabricated in one electroplating step at the same time and no sa crificial layer removal is needed.

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50 Figure 2 21. Prospective views of laminated NiFe core by using copper as sacrificial layer [67] Figure 2 22. Schematic of laminated NiFe core by electroplating on the side walls of through wafer silicon trenches [70] 2 .2.5 Inductors with Composite of Magnetic P owder and Polymer Bonder Currently, most of sputtered and electroplated magnetic materials need laminations to have sufficient inductance while maintaining low loss. However, the complicated fabrication steps of lamination process es prevent them from being adopted es pecially in the industry. On the other hand, ferrite based and ceramic based magnetic materials are the dominate materials for bulk

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51 inductor s and integrated inductor s by packaging technologies. They have moderate permeability (10~1500) and have very high resistivity ( c m ) [72] But these materials need high temperature (> 700 C) sintering, [73] which is not compatible with silicon IC fabrication In order to combine the favorable properties of the magnetic materials with the simple processing sequences, small particles of magnetic materials are suspended in a nonmagnetic matrix or binder [74 77] 1.2 m NiZ n and 0.8 m MnZn ferrites particles had been mixed with polyimide. The mixtures were coated and patterned by screen printing and were cured at 160 300. The resistivities of the fa bricated magnetic components were for NiZn based composite and 1M for MnZn based composite The saturation flux densities are 0. 43 T and 0.28 T respectively. However, without high temperature sintering, t he permeabilities are relative ly low, which are 25 for NiZn based composite and 32 for MnZn based composite resp ectively. Figure 2 23 shows an integrated inductor with the composite of ferrite powder and polymer bonder. Compared to electroplating and sputtering, the fabrication process is much simpler. First, the composite is screen printed on the substrate. Then e lectroplating molds are created, followed by electroplating copper windings. Next, the molds and seed layers are removed and the composite is screen printed on the top again to finish the fabrication. The reported inductances were 300~500 nH with 12 turns copper winding in 2.5 mm by 2.5 mm substrate. The inductance remained constant up to 10 MHz. The fabrication process for inductors based on the composite of magnetic powder with polymer bonder is simple and has flexibility in selecting the magnetic materia l. The resistivity of the fabricated micro magnetic core is increased dramatically at the expense of relatively low saturation flux density and low permeability.

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52 Figure 2 23. Photograph of integrated inductor based on composite of ferrite powder and pol ymer bonder and its process sequence: (a) Polymer filled ferrite screen printed on substrate, (b) Plating mold wa s formed for conductor lines and plated with copper, (c) After removing the mold, composite wa s screen printed again. [75] 2.3 Power Inductors In Package vs Power Inductors On Silicon Power inductors in packages and power inductors on silicon are two mainstream approaches for integrated power inductors. There have been a lot of discussions i n the industry and in the academia. It is an ongoing debate on which approach is better. But people do agree that it depends on the applications and the developed technologies. Table 2 -1 tries to make simple comparisons between inductors in packages and inductors on silicon. In this table, the High, Low, Large and Small are not intended to define the range of the values, but just for making comparisons between these two approaches. As described in previous two sections, the magnetic materials for in ductors in package have much more choices, while the magnetic materials for inductors on silicon are limited by the compatibilities with silicon IC. This is the main advantage of inductors in package over inductors on silicon. Also, inductors in package ha ve high inductance with low DC resistance and high saturation current. This is due to the fact that in packaging technologies, thick copper windings

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53 are much easier to make than on silicon. Therefore, inductors in package have larger power handling capabil ity. Table 2 1 Inductors in package VS inductors on s ilicon Inductor s in package Inductor s on silicon Inductance High Low DC resistance Low High Saturation c urrent High Low Magnetic material More options Limited Output power High Low Size Large Sm all Cost High Low On the other side, the size of inductors on silicon is smaller than that of inductors in package, which is the benefit of the sub-micron scale fabrication technologies. Moreover, due to wafer level batch fabrication feature, inductors on silicon are more cost effective. However, their DC resistance is high and current handling capability is low. Currently, the thicknesses of copper windings in the integrated power inductors with magnetic cores are below 100 m, resulting in high DC resi stance. Using wider copper windings to reduce DC resistance is not desirable, since it will increase the footprint. For example, in [30] a 2 mm wide, 45 m -thick copper winding Most of commercial converters with integrated inductors, as listed in Table 1 1, are based on inductors in package. There are several reasons: (a ) Integrated power inductors on silicon can not provide sufficient performance to meet the tight requirements of the market, due to the limitations of materials and technologies. (b ) Researchers and manufacturer s on power converters are much more f amiliar with packaging technologies, while few researchers in MEMS focuses on integrated power inductors.

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54 (c ) Integrated i nductors in packages can be more easily adopted. In general, inductors in package have better fit in converters with output current over 10 A. But in the near future, it is believed that inductors on silicon have a better potential to fit into low current converters with small form factor and low cost, especially for portable electronics whose output currents are below 2 A. 2.4 Tradeoffs an d Challenges for Inductors On Silicon Inductors with small size, low resistance, high saturation current and high inductance are always favorable. However, accord ing to equations 1.9 and 1 .10, inductance and saturation current compete with each other. Obvi ously, the DC resistance and the physical size are heavily depended on the number of turns, therefore related to inductance an d saturation current. Figure 2 24 shows the tradeoffs in the inductor design: In creasing the inductance will de crease the saturati on current for the same physical size. To have large saturation current, large core is needed for the same inductance. To have large inductance, it needs more turns or it needs large core. But increasing the turns will reduce the saturation current and in crease the RDC. To increase the core size will increase the physical size of the inductor. inductance Saturation current Physical size DC resistance inductance Saturation current Physical size DC resistance Figure 2 24. The trade -offs in the designs of integrated inductors.

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55 With the great demanding need for small form factor and low cost inductors, more and more effo rts have been pouring into developing new materials and exploring the new fabrication technologies for inductors on silicon. A high performance inductor in power converter should have sufficient inductance and high current handling capability, and should have low loss and small size. These specifications compete with each other. To increase the inductance, we may either increase the turns of the windings, or increase the thickness of the core, or use magnetic materials with larger permeability. While incre asing the winding turns will increase the winding resistance, thus increase the DC winding loss. Increasing the permeability will reduce the current handling capability since the magnetic material will saturate at lower current. Increasing the core thickne ss will increase the core loss at high frequency especially when the loss comes from eddy current. a ) The first challenge is the lack of fabrication technologies that have the ability to fabricate integrated inductor with magnetic, whose copper winding thicknesses are over 100 m. So down to subb ) The second challenge is the lack of fabrication technologies that have the ability to fabricate thick m agnetic core together with thick copper winding to obtain sufficient inductance in a limited area, wh ile maintaining low resistance. c ) The third challenge is to find new materials that have decent permeability and high frequency performance. The new material s should have high resistivity and low hysteresis loss and maintain decent permeability. The technologies need to be inexpensive and compatible with IC technologies and can be easily adopted. The main focus of this dissertation is to address the above cha llenges. The proposed new inductor fabrication technique will be introduced in Chapter 3 and the demonstrated inductors will be presented in Chapter 4 and 5.

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56 CHAPTER 3 CONCEPT OF POWER INDUCTOR IN SILICON AND ITS ENABL ING TECHNOLOGIES In previous chapter state -of the art technologies for integrated inductors are reviewed. Inductors on silicon show great potential in realizing small former factor and low cost DC DC converters for applications in portable electronics. However there are still challenges bot h from fabrication technologies and materials. In this chapter, a new concept of power inductors in silicon (PIiS) is proposed and demonstrated, which is realized by the proposed new silicon molding techniques. 3 .1 Power In ductor i n Silicon (PIiS ) 3.1.1 Concept From the reviews of inductors on silicon in the previous chapter, a common feature of their topologies can be found: all the metals layers are stacked on the top of silicon substrate layer by layer, as shown in Figure 3 1. This approach has difficult y to stake multi thick metals layers, resulting in high DC resistance and low current handling capability. As shown in Figure 3 1, the space of silicon substrate is not fully utilized. To take full utility of silicon substrate, a new topology shown in Fig ure 3 2 is proposed. Copper windings are embedded into the silicon substrate, two magnetic plates are fabricated on both sides of the substrate, and magnetic vias are also formed through silicon substrate to connect the magnetic plates on both sides. For c onvenience, in this dissertation, the inductors, fabricated on the top of silicon substrate by the conventional approaches, are called inductors on silicon, or IOS, while the proposed inductors, whose metals are embedded into the silicon substrate and on t he both sides of the substrate, are called power inductors in silicon, or PIiS.

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57 Silicon substrate Silicon substrate Figure 3 1 Typical cross -section view of inductors on silicon Figure 3 2 Cross -section view of the proposed inductors in silicon Figure 3 3 shows the con cept of a PIiS with a pot -core inductor (a), in which the copper winding and magnetic vias are embedded into the silicon substrate (c) with both sides capped by magnetic powders (b). The copper winding is embedded into the silicon substrate by electroplati ng copper into the through -substrate silicon molds. Silicon molds with aspect ratios over ten can be created by Deep Reactive Ion Etching (DRIE) [16] Such high aspect ratios will help laminate the copper winding to its skin depth and reduce both AC and DC winding losses at high frequency. The high aspect ratio of the copper spacing will help reduce the inductors area. 3.1.2 Topologies of Inductors In Silicon There are generally two kinds of magnetic materials. One is conductive magnetic materials, which r equire isolation layers between winding and magnetic. The other one is nonMagnetic Cu Dielectrics Magnetic Cu Dielectrics

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58 conductive magnetic materials, which does not need isolation layers. In this section, spiral type and toroidal type PIiS with different magnetic materials are proposed. (a) Top view (b) Schematic view (c) Cross -section view Figure 3 3 Pot core PIiS with single layer of spiral winding and composite of magnetic powder and polymer 3.1.2.1 Inducto rs In Silicon with Isolation Layers Figure 3 4 illustrates a PIiS with a single spiral winding layer and two electroplated magnetic core layers. From the cross -section view in Figure 3 4 (c), the copper windings and Magnetic Cu winding Si

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59 magnetic vias are embedded into the silic on substrate. From the schematic view in Figure 3 4 (b), the spiral windings are capped by two magnetic plates. This is called a pot -core inductor. (a) Top view (b) Schematic view (c) Cross -section view Figure 3 4 Pot -core P IiS with single layer of spiral winding and electroplated magnetic. The isolations inside the silicon substrate, such as isolation between windings, isolation between winding and magnetic, and i solation between metals and silicon, are provided either by silicon walls with silicon oxide or by dielectric polymer, such as SU 8 and PDMS. The isolations on the both sides of the substrate are provided by dielectric polymer. This topology can be realize d by the direct silicon molding techniq ue shown in Figure 3 8 or by the polymer enhanced silicon moldin g technique shown in Figure 3 9 The detail of the process flows will be discussed in the next session. 3.1.2.2 Inductors In Silicon without Isolation La yers Figure 3 3 shows a pot -core inductor with magnetic powder filled polymer which is non conductive magnetic material It shares the same topology with Figure 3 4 except that the Magnetic Cu winding Si

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60 windings are completely surrounded by the composite and there is no silicon in the center of the device. This inductor design can be realized by the polymer -enhanced silicon molding technique as shown in Figure 3 9 The details will be discussed in the next session. Since there is no isolation layer, the process is simpler than the process for PIiS with conductive magnetic material s (a) Top view (b) Schematic view (c) Cross -section view Figure 3 5 Pot core PPIiS with double layers of spiral windings and composite of magnetic powder and polymer N on conductive m agnetic Cu winding Si Si

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61 One of the disadvantages of the topologies with a single layer of spiral windings in Figure 3 3 and Figure 3 4 is that the footprint will go up when the number of turns increases Figure 3 5 shows a PIiS with double layers of spiral windings. Same with Figure 33, it is a pot core inductor with the windings capped in the center by the magnetic core. These two layers of windings are fabricated on separated wafers and then are bonde d on the wafer level with the composite in between. This topology can achieve higher inductance density at the expense of more complicated process and thicker devices. (a) Top view (b) View of the middle plate (c) S chematic view of copper winding Figure 3 6 Toroidal type PIiS with magnetic power filled polymer Non conductive magnetic Cu winding Si

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62 Figure 3 6 shows a toroidal PIiS with a magnetic powder filled polymer. Like conventional toroidal inductors, the ma gnetic core is surrounded by the windings. In Figure 3 6, the copper windings must cover the magnetic core as much as possible to reduce the leakage loss [78, 79] The fabrication of the middle plate in Figure 3 7 (b) is the same as the process for the middle plates in Figure 3 4 and 3 5. After the middle plate, coppers are deposited on both sides of the wafer to complete the copper winding. The footprint of this topology is smaller than that of a pot core design since the footprint does not increase with the number of turns. However, compared to the pot -core design, the toroidal design n eeds more turns to obtain the same inductance, resulting in higher resistance. 3.1.3 Merits of PIiS The proposed PIiS have the following merits: 1 Batch fabrication/Low cost. Just as all other silicon -based technologies, the wafer level fabrication will brin g down the cost dramatically. 2 Compact size. Most of the silicon substrate is removed and the space is utilized for windings, magnetic core, vias, interconnections, and thermal plugs for heat sink. 3 Low DC loss. Substrate -molded conductors are as thick as th e substrate (200~500m) and have much larger cross -section areas than the state of -the art counterparts, resulting in low DC winding resistance. 4 Completely IC compatible. All the processes involved are low temperature. Power systems on chip can be realized 5 Easy fabrication. Only five simple process steps are needed. 6 Multiple thick metal layers. The two magnetic plates on both sides can be easily fabricated up to several hundreds microns. 7 Low profile. Compared to the methods with inductors built on the top of substrate, this silicon molding method makes better utilization of the space of the silicon substrate for stacking multiple thick metal layers. Therefore the resulted profile is much smaller than its counterparts.

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63 3 .2 Silicon Molding Technique Silicon trenches have been widely studied for microfabrication applications. They can be created by wet etching or dry etching. The trenches can be etched isotropically or anisotropically for creating different 3D microstructures. One of the main applications of s ilicon trenches is used for metal electroplating. For instance, V -groove shape silicon trenches have been anisotropically wet etched for Cu electroplating, which was used for a 1 turn inductor [54] On the other hand, deep reactive ion etch (DRIE) has become a standard micromachining tool that can create high aspect ratio silicon structures. R esearchers have fabricated through -wafer silic on trenches for interconnects in thre e -dimensional packaging [80, 81] and for micro metal components [82, 83] High aspect ratio spiral micro -coils without magnetic for RF applications have been fabricated in high aspect ratio silicon trenches [84] Vertical magnetic lamination was demonstrated on the sidewalls of through-wafer silicon trenches [70] In this dissertation a silicon molding technique is proposed to create through -wafer electroplating molds for embed ding windings and magnetic inside the silicon substrate Figure 3 7 show the cross-section view of through -wafer silicon molds for embedding metals/alloys /polymer or mixture s into the silicon substrate. Figure 3 7 (a) shows a direct silicon mold. It is constructed with through -wafer silicon trenches with silicon dioxide on the sidewalls and thick copper seed layers exposed at the bo ttom of the trenches. Figure 3 7 (b) shows a polymer -enhanced silicon mold. It is constructed with through -wafer trenches with polymer or composite of polymer with magnetic powder as sidewall and thick copper seed layers exposed at the bottom of the trenches. The s ilicon molds shown in Figure 3 7 (a) can be used as electroplating molds d irectly for co pper windings or electroplated magnetics such as NiFe or CoNiFe which is called direct silicon molding technique Also t hey ca n be used as molds to

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64 create electrop lating molds shown in Figure 3 7 (b), which is called polymer enhanced silicon molding techniques. (a) (b) Figure 3 7 Cross -section view of through-wafer silicon molds for embedding metals/alloys /polymer or mixture into the silicon subst rate. (a) Direct silicon molds: through -wafer silicon molds with silicon dioxide on the sidewalls and thick copper seed layer exposed at the bottom of the trenches. (b) Polymer -enhanced silicon molds: through wafer molds with polymer or composite of polyme r with powder as sidewall. Figure 3 8 shows the cross -sectional view of the fabrication process flow to embed metals and magnetic into silicon substrate by directly using the through -wafer silicon trenches passivated with SiO2 on the sidewalls as electropl ating molds. The process starts with sputtering a 100 Ti and a 1000 the silicon substrate followed by a 10 m Cu electroplating. Ti serves as a diffusion barrier and adhesion promotion layer between Cu and silicon oxide. T he 10 m Cu l ayer is used for increasing mechanical strength. Then photoresis t is coated and patterned on the front side. Through-wafer silicon trenches are created by deep reactive ion etching (DRIE). A 0.6 m -thick silicon dioxide layer is deposited conformally on the silicon trenches using plasma enhanced chemical vapor depositi on (PECVD). The oxide on the trench bottom is removed by anisotropic oxide etching to expose the seed layer underneath, leaving an oxide layer on the trench sidewall s This oxide layer serves as a dielectric layer between the electroplated metal or magneti c and silicon substrate. Next, Cu or NiFe is Silicon Oxide Silicon Substrate Polymer or Composite of Polymer and Magnetic powder Seed layer

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65 electroplated in silicon trenches and the over -plated part is removed by c hemical m echanical polishing (CMP). Finally, the seed layers are etched away. 3 .2.1 Direct Silicon Molding Technique Fig ure 3 8 Direct silicon molding technique for embedding metal/magnetic into silicon substrate: (a) S eed layer deposition on the backside and 10 m Cu electroplating (b) through wafer Si trench etching by DRIE SiO2 conformal coating and anisotropic etching, (c) m etal /magnetic electroplating and surface polishing, and (d) remov al of the 10 m Cu on the backside 3.2.2 Polymer -Enhanced Silicon Molding Technique Instead of electroplating metals or magnetic into the through-wafer silicon molds, a polymer or a mixture of a polymer and a magnetic powder can be filled in the trenches to create micro magnetic components or molds, as shown in Figure 3 7 (b). Figure 3 -9 (a) ~ (c) shows the cross -sectional view of the fabrication process flow. Similar to the process shown in Figure 3 8, the process starts with sputtering a 100 substrate, followed by a 10 m Cu electroplating. Then photoresist is coated and patterned on the front side. Through -wafer silicon trenches are create d by DRIE. Next, a polymer or a mixture of Si SiO 2 (a) (b) (c) (d) Cu/NiFe

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66 a polymer and a magnetic powder is filled in silicon trenches and the over -filled part is removed by CMP. It is noted that the polymer itself is a good dielectric material. Therefore no silicon oxide is needed in Figure 3 9 (b). In step (d), the silicon between the polymers is removed by DRIE again to create polymer enhanced through -wafer silicon molds. These molds are used as electroplating molds for metal/magnetic electroplating, as in step (e). Fig ure 3 9 Polymer -enhanced silicon molding technique for embedding metal/magnetic alloy into silicon substrate: (a) seed layer deposition on the backside and 10 m Cu electroplating (b) through -wafer s i licon trench etching by DRIE, (c) polymer or composite of polymer and magnetic powder filling and surface polishing, (d) silicon etching by DRIE, and (e ) Cu/NiFe electroplating, surface polishing and seed layer removal. Cu/NiFe Si Polymer (a) (b) (c) (d) (e)

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67 3.3 Development of Silicon Molding Technique s In the process flows described in previous sec tion, there are several key techniques that will be needed: (a) deep reactive ion etching (DRIE); (b) creation of direct silicon molds; (c) creation of polymer enhanced silicon molds; (d) through wafer bottom up electroplating; (e) surface polishing. In th is section, the process development is discussed. 3.3 .1 DRIE Silicon DRIE is a common process for both bulk and surface micromachining due to its high anisotropy and high selectivity to photoresist and SiO2. The key feature of the ICP DRIE system is the t wo separate RF powers, one for the generation of etching radicals and the other for biasing for directional etching. The directional etching is further enhaced by using the alternation of etch and passivation. Table 3 1 Process parameters in silicon ICP DRIE system (for STS DRIE at UF) Parameters Etching Passivation Coil Power 600 W 600 W Platen 12 W 0 W Pressure 40 mTorr 20~25 mTorr SF 6 flow 130 sccm 0 sccm O 2 flow 30 sccm 0 sccm C 4 F 8 flow 0 sccm 85 sccm Process time 13 sec/cycle 7 sec/cycle In this project, a STS ICP DRIE etching system at UF campus was used to etch silicon. The process parameters are shown in Table 3 1. An etching rate of 4.8m/min wa s obtained with the listed para meters In the DRIE silicon etching, photoresist AZ 9260 was us ed as masks Figure 3 10 shows an SEM picture of the cross -section view of a silicon trench e tched with the recipe in Table 3 1 The depth of the trench is 500m and width is 100m. With other parameters fix ed, the etching rate and the slope of sidewall ca n be tuned by tuning the etching and passivation duration and their ratio. Higher ratios will result in more negative trench angles, which means narrower opening of the trench.

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68 Figure 3 1 0 SEM picture of a 500 m deep and 100 m wide through wafer sili con trench with and negative slope sidewall 3.3 .2 Creation of Direct Silicon Molds The process to create direct silicon molds is described in section 3 .2.1. There are two key process steps: (a) DRIE etching and (b) anisotropic etching of SiO2. The SiO2 on the bottom of the trenches must be etched away to expose the seed layer for metal electroplating, but at the same time, the SiO2 on the sidewalls must be kept for isolation That is an anisotropic etching process, which can be done by SiO2 RIE. The challen ge is that SiO2 on the sidewall is thinner than that on the bottom of the trench. In this process, oxide etch was performed using CHF3/O2 in a PlasmaTherm RIE SLR790. Table 3 2 lists the operating parameters used, and the etch rate wa s 0.2 m/min The coil power generate d plasma and the platen power accelerate d the ionized particles toward the target. Due the acceleration of platen power, the ionized particles bombard the etched sample directly. For a trench in Figure 3 10 which has narrower opening on the top, the highly directional ions have much less chance to reach the sidewall due to the negative slope. In this way, sidewall passivation can be achieved. Figure 3 1 1 is an SEM of a fabricated direct silicon mold. To verify the effectiveness of the sidewal l passivation, the silicon substrate was

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69 etched away, exposing the electroplated copper. A thin layer of oxide wall ca n be seen clearly in Figure 3 12. Table 3 2 Anisotropic SiO2 etch recipe on the Plasma Therm SLR770 ECR RIE system at UF Parameters Value CHF3 30 sccm O2 3 sccm Platen power 45 W Coil power 850 W Chamber pressure 5 mTorr Helium Flow 10 sccm Fig ure 3 1 1 SEM of the cross section of direct silicon molds with 10 m thick Cu at the bottom. The negative slope is used to help protect the oxide on the sidewall during the anisotropic oxide etching for removing the oxide on the trench bottom. 3.3.3 Creation of Polymer Enhanced Silicon Molds Besides DRIE etching, polymer filling is another key process in creating polymer enhanced silicon molds. There are two kinds of polymer enhance silicon molds used in this project. One is pure polymer, such as SU 8 or PDMS. The other one is composite of polymer and magnetic powder. Si Cu

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70 Figure 3 1 2 SEM of remained t hin layer of oxide wall after copper being electroplated and the silicon substrate being etched away to release the electroplated copper (a) SU -8 enhanced silicon molds SU 8 is a negative photo sensitive material known for its high aspect ratio lithography. Generally it is used to create hig h aspect ratio microstructures on the top of substrate. In this process, SU 8 enhanced silicon molds are created inside the substrate by filling SU 8 into the silicon trenches, polishing away the over -fill part and etching away the silicon between SU 8. Be fore it is filled into silicon trenches, SU 8 is diluted by Thinner P to reduce its viscosity. The wafer sample is heated to 60 C for 30 minutes after the SU 8 filling to remove the trapped bubbles in the trenches. Then it is pre -baked at 90 C for 60 minut es with a 4 C/min ramp and cools down on a hotplate slowly. After the pre -bake, the wafer is exposed without masks for the expose dose of 540 mJ/cm2 and post -baked at 90 C for 45 minutes with a 4 C/min ramp and slow cooling down again. In Figure 3 9 (d ), a fter the wafer is etched through, there may be silicon residuals on the SU 8 sidewalls. Those residual s can be removed by adding a short isotropic silicon dry etching. Unlike the silicon molds, SU 8 is an excellent dielectric material for electroplating. T here is no need for sidewall passivation. However, without proper surface treatment, SU 8 is a SiO 2 wall Cu

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71 hydrophobic material. To ensure the electroplating electrolyte getting into SU 8 molds, the SU 8 surfaces are treated by 10~15 seconds oxygen plasma, which resul t s in hydrophilic SU 8 surfaces [85] After oxygen plasma and before electroplating, the sample is put into an ultrasonic water bath for 5 minutes to help the electroly te get into the trenches. Figure 3 1 3 shows SU8 trenches tran sferred from through wafer silicon trenches (b) C omposite of magnetic powder and polymer The process to create magnetic components or m agnetic complimentary molds is similar to the process for SU enhanced silicon molds, except replacing SU 8 with composit e of magnetic powder and polymer. First, NiZn ferrite powder [86] is mixed with SU 8 completely, a s shown in Figure 3 14. Then it is pressed into direct silicon modes without silico n oxide and the wafer is put into a vacuum chamber to pump out the trapped air bulbs. Next, the surface is polished and the silicon between the composite is removed. Figure 3 1 5 shows the results of the composite being filled into different -width trenches. It can be seen that the process works well in the wide trenches. Figure 3 1 3 SU 8 trenches transferred from through wafer silicon trenches SU 8 wa lls Trenches

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72 (a) (b) Figure 3 1 4 Photograph (a) and SEM (b) of the composite of magnetic powder and polymer Figur e 3 1 5 SEMs of the composite being filled into trenches with different widths The surrounded silicon was removed to show the composite trenches. 3.3 .4 Through Wafer Bottom -Up Electroplating (a) E lectroplating setup and electrolytes at UF Figure 3 1 6 show s the electroplating setup at UF. It consists of a current source, two multimeters, a hotplate with a magnetic stirrer, an anode, a cathode and an electrolyte bath. The instruments used in t his setup are listed in Table 3 3. The electroplating bath of copper is lis ted in Table 3 4. (b) Electroplating u niformity In most cases, electroplated metals are required to have high uniformity, including micro uniformity and macro uniformity. Micro uniformity is the local uniformity in a small area; macro

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73 uniformity is the uniformity of the whole wafer. In both cases, the uniformity is determined by the migration of ions, which is depended on the electrical field distribution and the flowing of electrolyte. Current Source Heater&Agitator Anode Wafer Multimeter (a) (b) Figure 3 1 6 Schematic (a) and the photo graph (b) of the electroplated setup Table 3 3 Instruments for the electroplating system Instruments Model Current source KEITHLEY 225 Current Source Multimeters HP 3468B Hotplate Thermolyne Anode Phosphorized copper for Cu electroplating Nickel for nickel electroplating Electrolyte Technic CU 3300 for Cu electroplating Technic NI for nickel electroplating Table 3 4 Copper electroplating b ath [87] Chemi cals Value Copper Sulfate Pentahydrate(CuSO 4 5H 2 0) 40 g/l Sulfuric Acid 12% v/v Chloride Ion 80 mg/l TECHNIC CU 3300 Brightener 0.5% v/v TECHNIC CU 3300 Carrier 0.75% v/v TECHNIC CU Polarizer 5.00% v/v For good microuniformity, low current dens ity DC electroplating (5~20mA/cm2) is But for thick -copper (hundreds of microns)

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74 electroplating, especially in high aspect -ratio molds, the uniformity of the deposited metal bec omes poor, as shown in Figure 3 17. Figure 3 1 7 Electrop lated permalloy in direct silicon molds Figure 3 1 8 Current density waveform of pulse reverse electroplating To improve the uniformity, pulse -reverse electroplating, as shown in Figure 3 18, is employed. Tf and Jf are the period and the current de nsity for forward electroplating and Tr and Jr are the period and the current density for forward electroplating. Typically, Tf and Jf are 20 ms and 20~40mA/cm2. Tr and Jr are 1 ms and 60~120mA/cm2. The short reverse electroplating dissolves part of the el ectroplated metal and compensates the consumed ions in the forward electroplating. Therefore it creates a uniform distribution of the ion concentration in the local area [88] In Figure 3 19, 170m copper was electroplated with uniform thickness in silicon mold by pulse reverse electroplating J (mA/cm 2 ) t (ms) J f Jr T f Tr

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75 Figure 3 19. 10 hours pulse reverse electroplated 170 m thick copper in 200 m deep direct silicon molds For macro uniformity, pulse reverse electroplating does not help much on wafer level. At wafer level, the uniformity depends more on the electrical potential distribution and flowing of the electrolyt e. The electrical potential is determined by the current distribution on the sample and the distance of the anode and cathode. So normally the surface of the sample is parallel to the anode and the current is loaded evenly to the sample. Of course, a good conducting seed layer should be used to reduce the potential drop when the current travels over the surface. Besides the potential distribution, a stirring system is generally used to improve the flow uniformity of the electrolyte over the wafer. To impro ve the macro and micro uniformity, a simple but effective electroplating setup has been designe d, which is shown in Figure 3 20. As shown in the picture, the sample and the anode are placed horizontally with a dummy anode sitting in between. The dummy anode takes a similar size of the cathode and sits under the cathode with a 10~15 mm distance without any electrical connection. The first function of this dummy anode is to redistribute the electrical field evenly in the region close to the cathode, which wil l improve the micro uniformity. Also there are many punched-through holes in the dummy anode. The holes help to generate a uniform agitation when there is magnetic stirring at the bottom. Due to these holes, much faster stirring

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76 can be used without worrying about the nonuniform agitation in the region close to the cathode. Therefore, it will also help on the macro uniformity. Figure 3 20. Improved simple but effective electroplating setup for high aspect ratio through wafer trenches bottom up electroplating. 3.3 .5 Polishing Chemical -mechanical planarization or Chemical -mechanical polishing, commonly abbreviated CMP, is a technique used in semiconductor fabrication for planarizing the top surface of an in -process semiconductor wafer or other sub strate. It is introduced in this project to planarize the surface of electroplated metals and remove the over -fill SU8. Figure 3 21 is a photo of a simple CMP machine at University of Central Florida that had been used for this project. The sample holder with a mounted sample is placed upside -down and the surface of the sample is in contact with the pad. During polishing, the pad rotates at a preset speed, normally from 30rpm to 100rmp, and the rocking arm rocks back and forward. Under the forces of the ro tating pad and rocking arm, the sample holder will self rotate and rock between Anode (Cu) Magnetic bar Cathode (sample) Dummy Anode

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77 the center and edge of the pad, generating a uniform polishing pattern. An abrasive or corrosive slurry is added to the pad periodically through the slurry tub. The slurry will react with the sample and abrasively remove contact points on the surface of the sample. Usually, the slurry is consisted of a chemical solution and abrasive fine powders such as alumina powders (sizes from should used different pads to avoid cross contamination. Figure 3 2 1 Photograph of CMP machine The removal rate depends on the slurry, the rotation speed of the pad, the pressure between the holder and the pad, and the size of the sample. Larger particle size of the abrasive powder, faster pad rotation speed, larger pressure and smaller sample size will result in faster sample polishing. After that, t polishing. In this machine, the pressure is controlled by the weight of sample holder. To increase mina powders, 50rpm pad rotating speed, single holder without additional chunks, and 10mm by Sample holder P ad Conditioner ring Rocking arm Slurry tub

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78 Figure 3 23 (a) is an SEM picture of the over -electroplated sample before polishing, and (b) is an SEM picture of the sample after polishing. (a) (b) Figure 3 2 2 SEM of sample (a) over -electroplated, before polishing, (b) after polishing For convenience, a very simple hand polishing has also been used. In this method, the sample is mounted on a 6 inch sample holder. To guarantee good leveling during the polishing, dummy chips that have the same thickness as the sample substrate are mounted around the sample and at the edge of the sample holder, as shown in Figure 323. For good polishing, sample mounting is very important. Firstly, the wax should be completely melted and just a small amount of wax is applied on the holder to avoid any significant thickness increase. Secondly, the backside of the sample and the dummy chips should be particle free. Thirdly, the

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79 wax reflow during the coolingdown, which will change the surface level of the sample, should be paid close attention. A hard flat surface can be used to cover on the top of the holder to avoid the reflow. Figure 3 2 3 Photograph of sample mounted 6 inch sample holder for polishing Figure 3 2 4 SEM of polished sample by the polishing setup at UF A 12 inch by 12 inch window glass and a 1500 grit sand paper are used for coarse and fast polishing. Another 12 inch powder) are used for fine polishing. Generally, it takes 5~10 minutes coarse polishing and another 5~10 minutes on fine polishing. Figure 3 25 shows an SEM of a sample polished by the Dummy chips Sample Cu SU 8 NiFe Si

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80 poli shing setup at UF. Although compared to Figure 3 10 (b), the surface is rougher, it is 3.4 Summary In this chapter, t he concept of Powe r Inductor in Silicon (PIiS) is introduced and t he PIiS topologies and their merits are discussed. In a PIiS, the copper winding is embedded into the through -wafer silicon trenches to have the same thickness with the silicon substrate and the magnetic cores are fabricated on the both sides of silicon substrate. With such a topology a PIiS has low DC resistance, high inductance and high saturation current. The two kinds of enabling technologies, direct silicon molding techniques and polymer enhanced silicon molding technique ar e proposed. Direct silicon molding techniques uses oxide on the sidewalls as isolation and the metals are electroplated directly into silicon molds. Due to thermal expansion coefficient difference between metals and silicon, this structure will suffer from thermal stress during the process. P olymer enhanced si licon molding technique uses polymer for better and more reliable isolation. Polymer is also used as a buffer to have better device thermal stability. The key process steps for the proposed silicon molding techniques have been successfully developed. The f abrication of the inductors reported in Chapter 4 and 5 is based on these key processes.

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81 CHAPTER 4 DESIGN AND FABRICATION OF PIIS WITH PERMALLOY CORE In previous chapter the silicon molding techniques for PIiS was discussed. In this chapter, a PIiS with a conductive magnetic core (permalloy) was designed. Then it was fabricated by the polymer enhanced silicon molding technique. T he fabricated PIiS was characterized. 4 .1 Preparation and Characterization of Electroplated Permalloy Ni80Fe20 i s selected to demonstrate a PIiS with a conductive magnetic material. Ni80Fe20 is also called permalloy. It is a widely used magnetic material for micro soft magnetic component s because it is well studied and can be easily fabricated by electroplating. Table 4 1 Ni80F e20 e lectroplating b ath Nickel Sulfate (NiSO 4 6H 2 O) 200 g/l Ferrous Sulfate (FeSO 4 7H 2 O) 8 g/l Nickel chloride (NiCl 2 6H 2 O) 5 g/l Boric Acid (H 3 BO 3 ) 25 g/l Saccharin 3 g/l PH 2.5~3.0 Temperature 25~30 C Electroplating Current Density 20~30mA/cm 2 Table 4 2 Properties of Electroplated Ni80Fe20 Properties Ni 80 Fe 20 Permeability 400~450 Resistivity ( ) 40~50 Saturation Flux density ( T ) 0.9 Skin depth at 10 MHz ( m ) 5.9 The electroplating setu p described in section 3.3.4 for copper electroplating was also employed for Ni80Fe20 electroplating. The principles for copper electroplating were also applied to Ni80Fe20 electroplating. The electroplating bath was listed in Table 4 1. The fabricated Ni80Fe20 was tested by a vibrating sample magnetometer (VSM) and its B H curve was shown in Figure 4 1. The characterized magnetic properties were listed in Table 4 2.

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82 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 -6000 -4000 -2000 0 2000 4000 6000 H(Oe) B(T) Figure 4 1 B H curve of electroplated Ni80Fe20 4 .2 Topology and Dimensions of PIiS with NiFe core For the PIiS, the magnetic path is closed a nd there is no air gap, so E quation 1.8 can be reduced to: m c rl N A L2 0 4.1 From this equation, the inductance increases with permeability, the cross -section area of the magnetic core and the number of turns, and it decreases when the magnetic path increases. From Equation (1.9), the flux saturation current can be calculated as: L A NB Ic sat sat 4.2 In this PIiS with permalloy core, a pot -core type topology with a single spiral copper winding, as shown in Figure 3 4, is employed. The copper winding is embedded into the silicon substrate by using polymer as dielectric layers. Two magnetic plates and through -wafer magnetic vias are electroplated on both sides and inside the silicon substrate. Instead of taking a square shape as shown in Figure 3 4, a round shape is used for this design, as shown in Figure 4 2.

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83 Figure 4 2 Schematic model of PIiS with NiFe core After the magnetic material is characterized and the topol ogy is defined, the dimensions of the PIiS with permalloy needs to be determined next. The thickness of the copper winding Cut is set to 200 m, which is the thickness of the wafer to be used. The width of the copper winding w is set to 200 m to have large cross -section area and thus low DC resistance. The spacing of the copper winding s is set to 100 m based on the fabrication. The thicknesses of the top and bottom magnetic plate s coret are set to the same 15 m. Based on the geometry of the pot -core inductor shown in Figure 4 2 the average of the cross -section area of the core cA is simpl y expressed as: core in ct s w n r A )] ( 2 [ 4 3 where inr is the inner radius of the center of the spiral inductors, coret is the thickness of the core w is the width of the copper winding, s is the spacing between the windings and n is the number of turns of copper windings ml is the effective magnetic path length, and, from the geometry, ml is simply expressed as: Magnetic Copper

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84 cu mt s w n l 2 ) ( 2 4 .4 where Cut is the thickness of the copper winding which is 200 m. Substituting Equation (4.3), (4.4) and the characterized magnetic properties into Equation (4.1) and (4.2), the inducta nce and saturation current are calculated to be 160 nH and 1.3 A respectively. The DC resistance of the copper winding is calculated based on the total length of the copper winding, which are expressed as a function of the inner diameter ind and the number of turns n The equation for DC resistance is: )] ( 2 1 2 [ 2 s w n r w t n Rin cu cu dc 4 5 where, dcR is the DC resistance of the winding, and Cu is the resistivity of copper The calculated dcR 4 .3 Fabrication of PIiS with NiFe Magnetic Core The cross -sectional view of the fabrication process based on silicon substrate molding technique with SU 8 is shown in Figure 4 3. Double sides polished, 200 m thick, 4-inch p type (100) silicon wafers with 0.5m SiO2 on the backside are used. (a) Seed layers of 50 Ti and 2000 Cu are deposited by sputtering on the backside. A 10m thick copper layer is electropla ted with a 20mA/cm2 DC current for 20 minutes. Copper electroplating electrolyte (Technic CU 3300) from Technic Inc is used. This 10 m copper is used as the seed layer and as a mechanical support as well. As in Figure 4 3 (b), part of the silicon substrat e in the middle will be separated by the substrate and stand on the seed layer.

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85 Figure 4 3 Cross -section view s of the SU 8 enhanced process flow for integrated power MEMS inductors : (a) Sputter 50 Ti and 2000 Cu and electroplate 10 m Cu; (b) Spin coat and pattern photoresist (AZ 9260) and etch through -wafer silicon trenches by DRIE; (c) Remove AZ 9260 by acetone, fill SU 8 into the trench, cure the SU 8 by soft -bake, expose and post bake, and polish the surface; (d) Spin coat and pattern AZ 9260, etch the silicon by DRIE and etch the SiO2 by wet etching (BOE); (e) Through wafer bottom up Cu electroplating, remove AZ 9260 and polish the surface; (f) Repeat (d); (g) Through wafer bottom up NiFe electroplati ng, remove AZ 9260 and polish the surface; (h) Spin coat and pattern 50~100 m SU 8; (i) Sputter a seed layer of 50 Ti/2000 Cu/50 and spin coat and pattern 10 m AZ 9260; (j) Electroplate 40~50 m NiFe; (k) Remove AZ9260 and remove the seed layers on both sides; and (l) Repeat (h)~(k) on the backside (b) AZ 9260 is spin coated at 4000rpm for 60 second, and then it is prebake d at 90C for 20 min utes in an oven, followed by a 880mJ/cm2 exposion under a 365nm UV light. It is developed by being immersed i n a developer (AZ 300) for 4 min utes. The final film thickness is 10 m. (a) (b) (c) (d) (e) (f) SU 8 Cu NiFe AZ9260 Si SiO 2 ( g ) ( h ) ( i ) ( j ) ( k ) ( l )

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86 The exposed silicon windows are etched through vertically in an STS ICP DRIE system with 130sccm SF4, 13sccm O2, 80sccm C4F8, and 14 W platen power. Each cycle consists of 13 seconds etching and 7 seconds passivation. Under these conditions, it takes ~160 cycles to etch through 200 m silicon substrate. The etching stops at the SiO2 at the bottom of the trenches. There may be silicon residuals left on the sidewalls, which can be remove d by a short isotropic silicon etching. (c) AZ 9260 is removed by acetone. SU 8 is filled in the trenches. The wafer is heated to 65 C for 30 minutes to remove the trapped bubbles in the trenches. SU 8s viscosity will be reduced at an increased temperatu re. To further reduce its viscosity and ease the filling, Thinner P may be used to dilute SU 8. After the filling, the wafer is pre -baked on a hotplate, whose temperature ramps from 65 C to 95 C with 4 C/min and stays at 95 C for 60 minutes Then the hotpl ate is turned off and the wafer cools down on the hotplate slowly. After the pre -bake, the wafer i s exposed without masks for an expose dose of 540 mJ/cm2 under a 365 nm UV light. The sample stays at room temperature over night to release the stress. Then it is post baked on a hotplate, whose temperature ramps from room temperature to 95 C with 4 C/min and stays at 95 C for 45 minutes Then the hotplate is turned off and the wafer cools down on the hotplate slowly again Finally, the wafer is polished by 1 m alumina powder until the SU 8 on the top of the substrate is completely removed. (d) Step (b) is repeated. The SiO2 on the bottom is etched by immersing in a 6:1 buffered oxide etchant (BOE) for 8 minutes. Without surface treatment, SU 8 is a hydrophobi c material. To help the BOE to reach the bottom of the trenches, the wafer is treated by an O2 plasma for 10~15 seconds to convert the SU 8 surface from hydrophobic to hydrophilic [85] (e) Copper is electroplated bottom up until it is over -plated. To have a uniform thickness and avoid voids inside the copper, pulse revers e electroplating is employed The short reverse

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87 electroplating dissolves part of the electroplated metal and compensates the consumed ions du ring the forward ele ctroplating, which will balance the ion concentration on the electroplating area [88] It takes ~ 15 hours to electroplate 200 m thick copper. After the copper electroplating, the over -plated copper is polished away. (f) Repeat (d). It is known that C4F8 and O2 plasma attacks SU 8. However, in this step, the top surface of SU 8 i s covered by photoresi st ( AZ9260) during the DRIE etching and d ue to the directional etching nature of DRIE, the e tching on the sidewall of SU 8 i s not significant. (g) Permalloy ( Ni20Fe80) vias is electroplated with the parameters listed in Table 4 1 After the permalloy is ov er -electroplated AZ 9260 is removed by acetone and the over plated permalloy is polished. Figure 4 4 shows an SEM picture of the device as of this step. (h) SU 8 is spin coated at 1000 rpm for 30 seconds with a 300 rpm/sec ramp. Then it is pre baked on th e hotplate The hotplate ramps from room temperature to 95 C at 4 C/ min and stays at 95 C for 1 hour, the wafer cools down on the hotplate slowly. Then it is exposed for 525 mJ/cm2. The wafer stays at room temperature over night to release the stress. Then it is post baked at 95 C for 45 minutes with a 4 C/min ramp and slow ly cool s down again The pattern is developed by immersing the wafer in the SU 8 developer for 5 minutes. (i) S eed layer s of 50 Ti/2000 Cu/50 are sputtered. Before the sputtering, S U 8 is treated by O2 plasma to increase the adhesion. Spin coating of AZ 9260 described in (b) is repeated except doubling the exposure dose and the development time, since the photoresist over the permalloy vias is thicker than the photoresist on the top surface. The feature sizes are hundreds of microns and the effect from the over exposure and the over development can be ignored. (j) Permalloy electroplating in step (g) is repeated for 2 hours, which results in a 40~50 m thick permalloy layer.

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88 (k) AZ 9260 is removed by acetone. The seed layers on both sides are removed by Copper Etchant BTP from Transene. (l) Repeat (h)~(k) on the backside Figure 4 4 SEM of the device after 2.5 turns Cu winding and NiFe vias are electroplat ed and the surface is polished. Figure 4 5 Optical microscope picture of the fabricated pot -core inductor. Figure 4 5 shows an optical microscope picture of a fabricated inductor. Figure 4 6 shows the cross -section view of the finished device along the a a line in Figure 4 -4 It can be seen that the cross -section of the copper winding is about 200 m by 200 m. Si NiFe via s 2.5 turns Cu Windings a a SU 8 NiFe 3mm Cu

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89 Figure 4 6 SEM of the cross -section view along the a a line in Figure 4 4 4 .4 Characterization The fabrica ted inductor was tested on a probe station The inductance and resista nce of a fabricated inductor ar resistance of the connection wires and conta ct resistance of the probes are comparable to or even larger than those of the inductor under test [89] Thus a 4 -probe testing approach was used to mitigate these effects. As shown in Figure 6 18, a current was injected into the inductor through two pads, and the injected current was measured by a current meter. The induced voltage was measured through the other two pads by a voltage meter. The measured DC resistance was 9.1 A similar approach was adapted for inductance and equivalent AC resistance measurement. [90] The equivalent AC resistance represents the total loss of the in ductor, including DC conducting loss, AC winding loss and AC core loss. As shown in Figure 4 7 a sinusoidal signal from a function generator was amplified by a power amplifier and then injected into the inductor. The magnitude and phase of the injected current were picked up by a current Cu NiFe SU 8

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90 probe and monitored by a multi -channel oscilloscope. The inductance and the equivalent AC resistance can be calculated based on the following equations: f I V L 2 1 sin 4.6 cos I V Req 4.7 where L is the inductance, Req is the equivalent resistance, V is the amplitude of the induced voltage, I is the amplitude of the injected current, is the phase difference of V and I, and f is the frequency. For an ideal inductor, was 90 and Re q was zero. HP 3478A Digital multimeter Device under test 0 1320 A DC source L 0 0013 V HP 3478A Digital multimeter Figure 4 7 Schematic of DC resistance measurement by a 4 probe testing setup. Figure 4 9 shows the measured inductances versus frequenc y (from 200 kHz to 10 MHz). The measured inductance was 134 nH at 200 kHz and was 50~60 nH at 1 MHz to 6 MHz The inductance decreased at high frequency because both the permeability of permalloy and the effective thickness of the core decrease at high frequency. There was a resonant peak at 10MHz, which was caused by the self oscillation of the testing setup It should be noted that the induced voltages were too small to be picked by the oscilloscope at frequencies below 200 kHz for a 1 A injection current since the inductance was in the hundreds of nH range. So no experiments data were provided below 200 kHz in this four probe testing approach.

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91 AFG 3102 Function Genereator ENI 2100 RF Power Amplifier TDS5104B Tektronix Oscilloscope Device under test TCPA300 Tektronix current Probe L Figure 4 8 Schematic of inductance and equivalent AC resistance measurement by a 4 probe. 10 100 1000 1.00E+05 1.00E+06 1.00E+07 Frequency (Hz) Inductance (nH) Figure 4 9 Measured inductance versus frequency Figure 4 10 shows the frequency dependence of the equivalent resistance Req, which was 10.2 equivalent resistance increased quickly with frequency because permalloy is not a good high frequency magnetic material. T he core loss increases with frequency and the eddy current loss dominates the loss at high frequency. Figure 4 11 shows the frequency dependence of the Q which keeps decreasing when the frequency increases due to the serious eddy current loss.

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92 0 0.05 0.1 0.15 0.2 0.25 0.3 1.00E+05 1.00E+06 1.00E+07 Frequency (Hz) Req (ohm) Figure 4 10. Equivalent resistance versus frequency 0 2 4 6 8 10 12 14 16 18 1.00E+05 1.00E+06 1.00E+07 Frequency (Hz) Q Figure 4 11. Q versus frequency 4 .5 Summary T his cha pter reports a fabricated PIiS with permalloy core which validates the idea of PIiS with conductive magnetic materials and its enabling polymer enhanced silic on molding technique.

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93 The demonstrated low DC resistance verifies that the silicon substrate molding technique is one of the potential ways to fabricating ultra low DC resistance power inductors. The successful fabrication of the power in ductor shows the feasibility to integrate magnetic materials on the winding with a large cross -section area by the proposed polymer enhanced silicon substrate molding technique to boost the inductance. T he core loss of the fabricated inductor increases dra matically at fr equencies over 1 MHz. This high core loss in high frequency is due to the fact that the thickness of the permalloy core is much larger than the skin depth of permalloy material in high frequency, which induces serious eddy current loss. The core loss can be reduced by laminating the permalloy core or using magnetic materials with better high frequency performance to replace the permalloy

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94 CHAPTER 5 DESIGN AND FABRICATION OF PIIS WITH MA GNETIC POWDER CORE Chapter 4 reports a PIiS with a conducting magnetic core material (NiFe) fabricated by a polymer -enhanced silicon molding technique. In this chapter, a non conducting magnetic material, which is a composite of a magnetic powder and a polymer, is explored and used as the core material for PIi S. The newly designed PIiS is fabricated by a simple direct silicon molding technique. 5 .1 Preparation and Characterization of Magnetic Material Magnetic powders can be mixed with a polymer to form a non-conducting magnetic composite. In this project, a fully -sintered NiZn ferrite powder (FP350 from Powder Processing Technology, LLC) is mashed in a ball milling machine for 6 hours to reduce their sizes from ~10m to 1~2m. Then the mashed magnetic powders are mixed with a polymer, Sylgard 184 (from Dow Corn ing), at the weight ratio of 89wt% over with 1 1wt%. The mixed composite has been shown in Figure 3 4 The mixed magnetic composite has been tested b y a vibr ating sample magnetometer (VSM). Its B H curve is shown in Figure 5 1 The initial p ermeability ( r), coercive ( Hc), and saturation flux density ( Bsat) can be extracted from the curve, which are 8, 15 Oe and 0.2 T respectively. The permeability measured from the VSM is the initial permeability. Typically, t he permeability will decrease with frequency. T o measure t he permeability at 1~10 MHz donut shape plastic molds with different diameters and different trench width, as shown in Figure 5 2 were made by a fast -prototyping machine. The magnetic composite was pressed into the trenches manually. Then coppe r wired was wound on the donuts to form a hand -wound indu ctor, as shown in the Figure 5 2 (b). The hand wound inductor was tested using a Precision Impedance

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95 Analyzer (HP2494A) The permeabilit y was calculated by E quation (4.1 ) roughly. Then a more accurat e number was found by matching the simulation inductances with the tested results. Figure 5 3 shows the 3D model for simulating the hand wound inductors in Maxwell. The measured permeability was ~6 at 1~10 MHz. -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 -1000.0 -500.0 0.0 500.0 1000.0 Figure 5 1 B H curve of the composite of ferrite powder 89wt% and PDMS 11wt% (a) (b) Figure 5 2 P hoto s of (a) donut shape plastic molds made by a fast -prototyping machine; and (b) a hand wounded toroidal inductor with magnetic composit e 10mm B (T) H (Oe)

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96 Figure 5 3 3D models of hand wound inductors 5 .2 Topology and Dimensions of PIiS with Magnetic Powder Core 5 .2 .1 Topology of PIiS with Magnetic Powder Core Similar to the structure of the PIiS with a permalloy core shown in Figure 3 -4 a pot -core type topology is adopted in the PIiS with a magnetic composite core. Since the composite of magnetic powder and polymer is a non-conductive, no isolation is needed; and the top and the bottom magnetic layers are directly on the top o f the copper winding, which makes the topology much simpler and the fabrication process easier. As discussed in section 3.1.3, a copper routing layer can be added on the top of the device and conducting vias can be embedded inside the device. Such a PIiS c an be used as a packaging substrate for capacitors and IC chips, as shown in Figure 5 4. It can be seen that no additional wire bonding and packaging lead frame are needed. Therefore the structure is compact and the space is efficiently used. Figure 5 5 sh ows the inside view of a PIiS with magnetic powder. Most of the silicon inside the device is removed and replaced with copper windings, conducting vias and magnetic composite. To have a mechanical robust device, a copper ring is added. This copper ring is also

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97 intended to serve as an electrical ground for the DC DC converter and to help dissipate the heat from the top to the PCB board. (a) top view (b) bottom view (c) cross section view Figure 5 4 Schematic and 3D models of PIiS based conv erter Figure 5 5 Inside view of PIiS Cout C in IC chip Vias Cu routing Cu ring Vias Cu winding Silicon substrate Magnetic

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98 From the above structure design, there is no doubt that the magnetic is needed on the top and bottom of the winding. Also it is known that the magnetic is needed at the center and the edge of the winding to finish the magnetic loop of the core to boost the inductance. For comparis on, both magnetic material and non-magnetic material in the spacings between the windings are considered. In a PIiS, the magnetic composite and silicon are the magnetic and nonmagn etic materials for filling the winding spacing, as shown in Figure 5 6. Based on the simulation results using Maxwell, the inductance of a PIiS with magnetic spacing is 12% larger than that of a PIiS with silicon spacing. From the flux distributions, it is seen that, with magnetic spacing, the flux leakage through spacing 3 6 can be ignored, while the flux through spacing 1 2 increases the effective core area. Therefore, the magnetic composite is used in the spacing. (a) with silicon in between the spacing (b) with magnetic in between the spacing Figure 5 6 Flux distribution in PIiS with and without magnetic in between the spacing From Figure 5 6, t he flux is crowded at the center of PIiS with magnetic powder between spacing. The flux density may be reduced by increasing the area of magnetic core at the center. Two simulations, as shown in Figure 5 7, have been performed to exam the effect of the area of the magnetic core at the center. To have a fair co mparison, all the parameters are kept the same (even the inner diameter), except reducing the width of the center copper vias to make room for 1 2 3 4 5 6 Silicon Magnetic powder

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99 magnetic core. The simulation results show that when the inner width of magnetic core increases from 200m to 500m, the inductance only increase s by 1.9%. Figure 5 7 Flux distribution comparison of different center magnetic width 5 .2.2 Spec ification s of PIiS with Magnetic Powder Core Before determining the dimensions, the specifications such as inductance, DC resistance and saturation current, need to be defined. This PIiS will be used to demonstrate a DC DC converter with a commercial IC chip. Currently, most of high frequency converters switch at 5~10M Hz and require 0.3~1 H inductor s. In this design, the inductance is set to be ~0.4 H to meet the minimum inductance with a 25% margin. The DC resistance should be defined by balancing between the physical size and the converters efficiency. It is known that the losses from the MOSFET and the inductor are the two major losses of a converter. So when the MOSFET loss becomes dominant, it is not wise to keep reducing the DC resistance. Therefore, an optimum value of the DC resistance must be specified for the targeted applications. Figure 5 8 is the curve of a converters efficiency versus the inductors DC resistance. This curve is plotted based on the switching loss information of the commercial power IC (TPS 62601) that switch at 6 M Hz. From the curves, the efficiency does not decrease much when the inductors DC resistance i s smaller than 100 d in Magnetic flux in the center part are in the same pattern and the same scale d in

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100 Figure 5 8 the efficiency versus DC resistance of inductor The output current of a converter for portable electrics is typically smaller than 2A. So the target saturation curren t is designed to cover 2A. The specs of the PIiS with a magnetic powder core are listed in Table 5 1. Table 5 1 Spec s of the P Ii S with magnetic powder core Specifications Values Inductance ~400 nH DC resistance ~10 0 Saturation Current > 2 A 5 .2.3 Dimensions of PIiS with Magnetic Powder Core The cross -sectional view of the pot -core PIiS inductor design is shown in Figure 5 9 where tc is the thickness of the magnetic core; tw is the height of the winding; w is the width of the winding; s is the dist ance of the spacing of the winding; and din is the inner diameter of the winding. Inductors DC resistanc Io=2A Io=1A Io=0.5A 0.1 0.01 1 DC DC Converters Efficiency 0.9 0.7 0.5

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101 Figure 5 9 Parameters of optimized PIiS The thickness of the copper winding is set to be 200 m, which is the thickness of the silicon wafer to be used. The width of the copper winding is set to be 60 m sinc e the skin depth of copper at 6 MHz is around 30 m. The aspect ratio of the spacing is set to be 5 based on the process cap ability which results in 40 m wide spacings Equation s 4.1, 4.2 and 4 .3 are used to estimate the rest parameters Then optimization simulations have been performed in Mawell by using the estimated parameters as initial values. Figure 5 10 shows the magnetic flux distributions of the optimized PIiS with magnetic powder with 1 A excitation current. It is clear that the maximum flux density is 0.043 T, which is far below the characterized saturation flux density. Table 5 2 lists the optimized parameters of the PIiS with a magnetic powder core Figure 5 10. The magnetic flux distribution of the design PIiS with magnetic powder t w t c w s d in

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102 Table 5 2 Parameters of PIiS with magnetic p owder c ore Parameters Values Number of turns 10 Height of winding 200 m Width of winding 60 m Spacing of winding 40 m Thickness of core 200 m Inner diameter 300 m Indu c tance 392 nH Saturation Current > 7 A DC resistance 5 .3 Fabrication of PIiS with Magnetic Powder Core The fabrication process flow is shown in Fig. 5 11. First, a 10 m -thick copper layer is deposited on the backside of the substrate, which serves as the seed layer for the following electroplating and as a mechanical support for the silicon walls. The silicon substrate is etched through by deep react ive ion etching (DRIE) (Figure 5 11(1)), and copper is electroplated with the over -plated copper being polished away (Figure 5 11(2)). Then the substrate is etched through by DRIE again. A microscopic picture of the device at this step is shown in Figure 5 14. After the silicon molds ar e formed, the magnetic composite described in Section 5 .1 i s filled in the silicon trenches with the overfilled part being polish ed away (Figure 5 11(3)). To prepare t he magnetic composite, the size of the NiZn ferrite powder is first reduced from ~10 m down to about 1 2 m in a ball milling machine. The powder is then mixed with Sylgard 184 PDMS completely. Next, t he completely -mixed composite is poured into the silicon trenches and pressed via a thin plastic sheet. The pla stic sheet is later peeled off carefully To have good adhesion, the entire silicon substrate including the trenches is surface activated by oxygen plasmas before the composite filling [85] After filling, the s ubstrate is put int o a vacuum chamber (<10 4 Torr) for 30 minutes to pump out the trapped air bubbles Then the sample is

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103 heated at 100 C for 20 minutes to solidify the composite. The overfilled composite is then polished away by techniques described in section 3.3.5 (Figur e 5 11(3)). Next, solder balls are dispensed on the top of the substrate with silver epoxy as the bonder (Figure 5 11(4)) which is shown in the microscopic picture in Figure 5 15. T he process for the magnetic composite is repeated the wafer is polished unt il the solder balls are exposed (Fig ure 5 11(5)) (see the picture in Figure 5 16), followed by electroplating a 20 m copper routing layer on top of the magnetic composite (F igure 5 11(6)). Finally, the 10 m -thick copper seed layer on the backside is etch ed away and the process steps for the solder balls and magnetic composite are repeated on the backside as shown in Figure 5 11(7)). Figure 5 11. Cross -section view of process flow: (1) Deposit 10 m Cu on backside, etch throug h 200 m Si substrate; (2) Electroplate and polish Cu; (3) Etch thr ough substrate, as in Figure 5 10, fill in magnetic composite and polish; (4) Bond 300 m solder balls wit h silver epoxy, as in Figure 5 11; (5) Press magnetic composite and polish until so lder ball is exposed, as in Figure 5 12; (6) Electroplate 20 m Cu routing on the top of magnetic composite, etch away the Cu layer on the backside with Cu routing on the frontside protected by photoresist; (7) repeat (4) and (5) on the backside. In this process, all process steps have been developed and introduced in Chapter 3 except the solder balls handling. Figure 5 12 shows the solder ball manipulation system, which is built (1) (2) (3) (5) (4) (6) (7) Cu Si Magnetic composite Solder ball

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104 to bond the solder balls to the sample with an accurate and repeatable manner. The solder ball is held by a vacuum pen and then is stamped into a 100m -thick silver epoxy layer, as shown in Figure 5 13. The 100m -thick silver epoxy layer is made by first sticking two 100 m -thick tapes on a flat glass to create a 100 m thick spacer Then fill in with silver epoxy and scratch the over filled silver epoxy. A layer of silver epoxy is coated on the solder ball after the stamping. Then the solder ball is aligned to and placed on the sample. The position of the solder ball is controlled by three micrometer controllers in X, Y and Z directions, as shown in Figure 5 12. Figure 5 12. Photos of the solder balls manipulation system Figure 5 13. Schematic of the solder ball being stamp ed on silver epoxy layer Y X Z Vacuum pen Microscope Incident light Side view Top view Flat glass slice Solder ball Vacuum pen Silver epoxy 100m thick tape

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105 Figure 5 14. Photo picture of the device after the winding, ring and vias being embedded into silicon substrat e and the silicon betwe en winding being etched away. Figure 5 15. Photo picture of the device after the magnetic composite is filled and polis h ed; and solder balls are bonded on the top Figure 5 16. Photo picture of the device after the magnetic composite being compresse d on the top and being polished until solder balls are exposed. Through wafer trenches Copper winding Solder ball Copper ring Magnetic powder Magnetic powder Exposed Solder ball

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106 (a) (b) Figure 5 17. Photos of a fabrica ted PIiS. (a) Frontside of a single PIiS die; (b) Backside of a PIiS ; (c ) Cross -sectio n view of a PIiS ; and (d) PIiS compares to a US dime 3mm Cu routing Cu winding via Solder balls Magnetic composite 0.6mm (d) (c)

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107 Figure 5 17 shows the pictures of a fabricated PIiS with a magnetic powder core. Figure 5 17 (a) and (b) are respectively the photo pictures of the devices frontside and backside view. Figure 5 17 (c) shows a photo of the cross -section view of the PIiS. The PIiS size is 330.6 mm3. Figure 5 17 (d) shows the comparison of a PIiS with a dime. 5 .4 Characterizations The fabricated inductor is tested on a probe station The technique shown in Figure 4 7 is also employed to measure the DC resistance of the fabricated PIiS with a magnetic powder core Th e measured DC resistance is 140 It is copper winding thickness reduction resulting from the multi polis hing steps and the over etching when removing the backside copper seed layer and (2) the resistivity of the electroplated copper is higher than the ideal copper. The frequency dependence of the inductance (L), Q and AC resistance (RAC) were measured using an HP Precision Impedance Analyzer. To reduce the interferences of the parasitic inductance and resistance of the wire s the probe station and contact s open calibration and short calibration are performed before the testing. To minimize parasitics, a test fixture as shown in Figure 5 18 is designed, which is built on a PCB. There were two short calibration landing pads and two open calibration landing pads. The distance of each pair of the pads was the same as that of the pads of the designed PIiS. The refo re, during the short and open calibration, the probes can easily be aligned with the pads. With such a test fixture, the contact resistance, the self inductance/capacitance and the mutua l inductance stay the same for short and open calibration and actual measurement. The measured inductance, resistance and quality factor are plotted in Figure 5 1 9 At 6 MHz, the measured L was 390 nH, the Q was 10, and the RAC L is close to simulated results which is 392nH

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108 Figure 5 18. Test fixture for open calibration and short calibration Figure 5 19. Measured inductance versus frequency 5 .5 Summary A PIiS with magnetic powder core was designed and fabricated successfully, which validates the idea of a PIiS with non -conductive magnetic materials and its enabling technique, direct silicon molding technique. Compared to the process based on polymer enhanced silicon molding for PIiS with a conductive magnetic core, the process based on direct silicon mol ding is much simpler since no isolation layers are needed. L Q R AC Frequency (Hz) 10 4 10 5 10 6 10 7 L (nH) 200 300 400 500 R AC 0 4 8 12 Probe landing pads for short calibration Probe landing pads for open calibration Copper layer Isolation trenches

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109 The measured inductance was over 390 nH up to 6 MHz, which showed that the magnetic powder was a better high frequency magnetic material than permalloy. However, the AC resistance was increased fr hysteresis loss. A Q of 10 has been achieved at 6 MHz due to the better magnetic material and the optimized design. Also, copper routing and conducting vias can be easily added in this process, s o that the PIiS can be served as the packaging substrate for a DC DC converter, which is the focus in the next chapter.

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110 CHAPTER 6 DEMONSTRATION OF A COMPACT DC -DC CONVERTER WITH PIIS The goal of this research is to develop a DC DC converter with small f orm factor and high efficiency. The previous chapter has reported the successfully -fabricated PIiS that has high Q and is surface mounting ready. This chapter will describe the potential ways to integrate the PIiS with capacitors and power ICs. The merits of PIiS -based integrated converters are discussed. A compact PIiS based DC -DC converter is demonstrated to verify the fe asibility of the proposed idea. 6 .1 Approaches for Integrating DC-DC Converters with PIiS Compared to the integrated inductors by packag ing technologies, PIiS can be much more easily integrated with ICs because it is a silicon -based technique, which is preferred by the IC manufacture foundry. In this section, the potential approaches for integrating PIiS with power ICs are investigated. Th eir features are discussed. 6 .1.1 One -Chip Integration The most straight forward integration is to fabricate the PIiSs directly on a power IC wafer, as shown in Figure 6 1 since the silicon molding techniques for P IiS fabrication are compatible wit h IC t echnologies. In the one -chip approach, the PIiS and power ICs are placed side by side since the PIiS is fabricated in through -wafer silicon molds, in which the silicon within the PIiS are completely removed. The resulted profile (<0.5 mm) is thinner than c ommercial DC DC converters (~1 mm). However, the total footprint will be almost doubled, which is undesirable for small form factor integration. Since cost of ICs is base on the chip area such big areas will be costly especially when the advanced CMOS te chnologies (130nm, 60nm) are used for power IC fabrication.

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111 Figure 6 1 Schematic of single -chip integration of PIiS and power ICs. 6 .1.2 Integration by Wafer -to Wafer Bonding The second approach is that the PIiSs and ICs are fabricated on the different wafers, as shown in Figure 6 2 and then are bonded at the wafer level, as shown in Figure 6 3 and in Figure 6 4 In this approach, the PIiSs and power ICs are stacked together to cut almost half of the footprint of the single -chip integration. Moreover, much cheaper fabrication technologies can be used for PIiS s since the minimum feature sizes are well over one micron. So the cost per area of PIiSs will be reduced dramatically. Compared to the side -by-side integration approach, the vertical stacking cuts down the footprint by half, but the profile is almost doubled (~0.8mm). However the bulk silicon substrate of ICs can be thinned since the PIiS substrate can also serve as the supporting substrate for ICs after wafer bonding, as shown in Figure 6 5 Theref ore the total thickness should be close to that of the single -chip integration approach.

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112 Figure 6 2 Schematics of an PIiS wafer and an IC wafer before wafer to wafer bonding. Figure 6 3 Illustration of wafer bonding of power ICs and PIiSs with magnetic composite. Figure 6 4 Cross -section view of bonded PIiSs and ICs + =

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113 Figure 6 5 Cross -section view of wafer level bonded PIiSs and ICs after the bulk silicon substrates of ICs are polished away to reduce the totally thickness of the converter. In this approach, to avoid wasting the expensive silicon area of ICs, the footprint of the inductor should be sma ller or close to that of the IC chip since the cost/area of ICs is much higher than that of PIiSs. Currently, the areas of the most power IC with switches, drivers and control circuits for MHz switching frequency are between 22mm2 and 33mm2. Table 6 1 lists the specifications of the commercial step -down DC DC converters with all of the ICs except the input and output capacitors and output inductor. Tab le 6 1 Commercial step down DC DC converters in MHz without integrated inductors f sw (MHz) L ( H) V in (V) V out (V) I out (A) Footprint (mm 3 ) TPS62300 [91] 3 2.2 2.7~6 0.6~5.4 0.5 330 .8 LTC3412 [92] 0.4~4 1 2.6~5.5 0.8~5 2.5 440.8 LM2832 [14] 3 3.3* 3.0~5.5 0.6~4.5 2 330.86 MIC2285A [93] 8 0.47 2 .7~5.5 1~4.5 0.6 220.55 NCP1522B [94] 3 2.2 2.7~5.5 0.9~3.3 0.6 220.65 FAN5350 [95] 3 1 2.7~5.5 1.82 0.6 330.8 ST L6928 [96] 1.4 4.7 2~5.5 0.6~ vdd 0.7 0.8 330.9 ADP2102 [97] 3 1 2.7~5.5 0.8~3.3 0.6 330.9 TC1303 [98] 2 4.7 2.7~5.5 0.8~4.5 0.5 330.85 MAX8805 [99] 4 1~2.2 2.7~5.5 0.8~3.4 0.6 220.7 ISL6273 [100] 1.5 1.8 2.7~5.5 0.8~Vin 1.2 330.85 Based on the proposed silicon molding technique, even in such small areas, it is possible to fabricate PIiSs to be used in MHz converters for portable electronics.

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114 6 .1.3 Integration by Die -to -Die Bonding The footprints of the inductor and IC chip need to be closely matched to use wafer to wafer bonding. When they are largely different die to die bonding is a better option. Figure 6 6 shows an integrated converter, in which the PIiS, the power IC chip and the capacitors are fabricated separately before they are bonded. (a) Top view (b) Bottom view (c) Cross -section view Figure 6 6 An i ntegrated converter by die to die bonding PIiS, power IC chip and capacitors. This approach is similar to the approach based on the packaging technologies. It uses the PIiS as the packaging substrate. The inductor and the capacitors are standing on the top of the

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115 PIiS. Therefore no additional packaging substrate or lead frame is needed. Furthermore, with the copper routing and conducting vias already formed on the PIiS, no bond ing wires are needed. 6 .2 Merits of DC -DC Converters with Inductors In Silicon (PIiSs) The wafer level integration and flip -chip bonding approaches are preferable for integrating PIiSs with ICs and capacitor s in terms of compactness, cost and robust ness B esides the merits of P IiSs as discussed in section 3.1.3 the converters based on these integration approaches have the following merits: 1 No packaging substrates or lead frames are needed. PIiS inductors can serve as the packaging substrates. 2 No wire bond ing is needed. PIiS inductors are surface mounting ready. The through-wafer metals can connect the bonding pads of the PIiS chips to the pins of the packages. 3 Good heat dissipation through thermal plugs. The through -wafer metals, especially copper, can s erve as a very good thermal path to dissipate heat. 4 High space utilization efficiency. Most of the substrate space is utilized for windings, magnetic cores, connections, and heat sink. 5 In house fabrication. Both inductors and ICs can be manufactured by the same semiconductor foundry, which will further bring down the manufacturing cost. 6 .3 Demonstration of A Compact DC-DC Converter The IC chip TPS62601 (from TI, 1.30.90.6 mm3) and two SMT capacitors (4.7 F, 0402 and 2.2 F, 0402) are selected to be mounted on the top of a PIiS to demonstrate a compact DC DC converter. TPS 62601 outputs 500mA, 1.8V at 6 MHz. Table 6 2 lists the specs of the DC DC converter based on a PIiS with magnetic powder core. The compact DC DC converter was built by using a flip-chip bonding system. First, the fabricated PIiS was mounted on the testing PCB with solder balls and silver epoxy, as shown in Figure 6 7. Then the IC chip was mounted on the top of the PIiS, as shown in Figure 6 8. Finally the capacitors were mounted on the top of the PIiS as shown in Figure 6 9.

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116 Table 6 2 Specification of the integrated buck converter with PIiS Specifications Values Inductor (PIiS) 0.3 0.5 H 330.6 mm3 TPS62601 (TI) 1.30.90.6 mm3 Cout (0402) 4.7 F Cin (0402) 2.2 F Input voltage 2.3 5.5V Output voltage 1.8V Output current 500 mA Switching frequency 5 6 MHz Figure 6 7 Photo of the converter after the PIiS being mounted on the top of testing PCB

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117 Figure 6 8 Photo of the converter after the IC chip be ing mounted on the top of the PIiS Figure 6 9 Photo of the converter after the capacitors being mounted on the top of the PIiS Figure 6 10. Photo of a DC DC converter with PIiS on a testing PCB board Cap IC chip Power Inductor in Silicon 4.43.350.9mm 3 331.2mm 3

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118 Figure 6 11. Photo of the TIs evaluation board of TPS 62601 Figure 6 10 shows the photo of the integrated compact DC DC converter (331.2mm3) based on a PIiS and its testing board. Figure 6 11 shows the photo of the Texas Instruments (TI) evalua tion board of TPS 62601, which results in a 4.4 .35 0.9 mm3. 6 .4 Characterizations Measuring the current of an inductor can extract the inductance and resistance of the inductor. As shown in Figure 6 12, the inductor current is picked up by a current prob e (Tecktronix TPCA300) and is sent to an oscilloscope. Figure 6 1 3 shows an acquired waveform of the inductor current. Vb a t t e r yCi nLCo u tRl o a dIC chip (TPS 62601) Current probe Vout(voltage meter)Slope=I/t current Probe Tektronix TPCA300 Oscilloscope Tektronix TDS5104B Figure 6 1 2 Schematic for measuring the inductor current The inductance and the resistance can be calculat ed based on the measured inductor current. For inductor s we know t I L dt di L VL 6.1 where L is the inductance, VL is the voltage cross the inductor, and t I is the slope of the inductor current.

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119 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Time (us) Inductor current (A) Figure 6 1 3 Probe d indu ctor current of the DC -DC converter with a PIiS Figure 6 1 4 shows the schematic of the power stage of a stepdown DC -DC converter. During the rising edging of the inductor current, M1 is turned on and M2 is turned off, it can be derived that: out L p dson out in LI R R V V V ) (_ 6 .2 During the falling edging of inductor current, M1 is turned off and M2 is turned on, it can be derived that: out L n dson out LI R R V V ) (_ 6 .3 where p dsonR_ and n dsonR_ are the on resistance of M1 and M2 whi ch are known and can be found on the datasheet of TPS 62601. M1 M2 R dson_p R dson_n V in V out + C out ESR_C R L L

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120 Figure 6 1 4 Schematic of the power stage of buck converter Substituting 6 .2 and 6 .3 into 6 .1, we can derive the equations of the slopes of the inductor s current. The slope of the inductors current on the rising edge (Sr): L I R R V V Sout L p dson out in r ) (_ The slope of the inductors current on the falling edge ( Sf): L I R R V Sout L n dson out f ) (_ In these two equations, all the parameters except L and RL were known. By solving these two equations, L and RL were calculated to be which match ed well with 390nH and 1.17 which were measured from Impedance Analyzer. From the hysteresis loop of the magnetic material, the permeability will reduce with the i ncrease of the inductor current and become 1 when the inductor gradually enters the saturation region. From the experiments, it was found that the inductance stayed the same even when the output current was increased up to 500 mA, which means that the inductors saturation current was well above 500 mA. Due to the current limitation of the IC chip, the device was not tested at currents larger than 500 mA. The efficiency of the built DC DC converter is another important parameter that is needed to be tested to evaluate the performance of the PIiS. Figure 6 15 shows the schematic for measuring the efficiency. The efficiency can be calculated as in in out outV I V I efficiency where the input current ( Iin), the input voltage ( Vin), the output current ( Iout) and the out put voltage ( Vout) can be measured by multi -meters.

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121 Vb a t t e r yIout(Current meter)Ci nLCo u tVout(voltage meter)Rl o a dIC chip (TPS 62601) Iin(Current meter)Vin(voltage meter) Figure 6 15. Schematic for measuring the efficiency of the demonstrated converter The efficiency curve of the demonstr ated converter is shown in Figure 6 16. Its peak efficiency is 79.6% when the output current is around 200mA at a 1.8 V output voltage. The refore, the total loss is 92 mW. From the datasheet of TPS 62601, the loss from the IC chip is ~60mW. The inductor loss is ~ 32 mW, which consists of a ~5 mW DC winding l oss and ~27mW AC loss. Since th e width of the copp er winding is 60 m, which is two times of the skin depth of copper at 6 MHz, the AC winding loss is negligible. Also the composite of magnetic powder is a non -conductive magnetic material, so the eddy current loss in the magnetic core i s greatly suppressed. The losses due to the output capacitances parasitic resistance and the PCB trace resistance are negligible. Therefore the calculated 27mW AC loss is primarily the hy s teresis loss of the magnetic core. To test the thermal stability o f the device, the built converter has been tested from room temperature to 1 30 C. As s hown in Figure 6 17, t he efficiency only drops ~ 2 % over a 100 C temperature inc rease.

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122 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 600 Output Current (mA) Efficiency (% Figure 6 16. DC -DC converter s efficiency versus output current Figure 6 17. DC -DC converters efficiency versus temperature 6 .5 Summary In this chapter, the potential methods to integrate PIiS with power ICs to realize a fully integrated compact DC DC converter have been proposed and compared. It is believed that the Efficiency ( % ) Temperature ( ) Iout=202mA Iout=101mA 20 40 60 80 100 1 20 50 60 70 80 140 Converters with PIiS Converters on TIs evaluation boar d

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123 wafer to -wafer bonding and the die to -die bonding are two po ssible ways to bring down the cost and reduce the size. The merits of a converter based a PIiS have been discussed. A compact DC DC converter has been demonstrated successfully by using the fabricated PIiS with magnetic powder core as the packaging substr ate for power IC and capacitors to verify the idea of the die to -die bonding. The demonstrated converter has a very promising performance with a compact structure. The inductance and resistance of the PIiS have extracted by testing the inductor current in the DC DC converter. The extracted results were matched well the measured results reported in Chapter 5.

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124 CHAPTER 7 SUMMARY AND FUTURE W ORK 7 .1 Summary The goal of this dissertation is to develop integrated DC DC converters with small form factor and high efficiency. In order to achieve this goal, the concept of power inductors in silicon (PIiS) has been proposed, fabricated and experimentally verified. Unlike other thin -film power inductors, which are fabricated on the top of silicon, PIiSs are fabricated into the silicon substrate and they have low DC resistance and high Q PIiSs can be batch fabricated at wafer level and the fabrication process is completely IC compatible. PIiSs are very compact since most of the space initially occupied by the silicon su bstrate has been utilized as part of PIiSs. Two silicon molding techniques have been developed for PIiS fabrication: direct silicon molding technique and polymer enhanced silicon molding technique. The key process steps, such as deep silicon molding, side wall dielectric passivation, deep SU 8 molding, deep SU 8 passivation, sidewall slope -tunable process, through -wafer bottom up electroplating, throughsilicon vias, and polishing have been developed. In addition, a process to prepare magnetic composites by mixing magnetic powers and polymers has been successfully developed. Two PIiSs have been designed, fabricated and characterized as examples to verify the proposed PIiS idea and to study the feasibility of the silicon molding techniques. One is a PIiS with NiFe as the magnetic core material, which is fabricated by the polymer enhanced silicon molding technique and the other is a PIiS with a composite of magnetic powder and polymer, which is fabricated by the direct silicon molding technique. The process for the PIiS with NiFe is much more complicated due to the necessity of dielectric layers between the winding and magnetic. The PIiS with NiFe has smaller DC resistance but higher AC loss due to large eddy current of low resistivity NiFe at high frequency.

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125 A DC DC converter based on the PIiS with magnetic composite has been demonstrated. The fabricated PIiS is used as the packaging substrate, and a power IC and several SMT capacitors are directly surfaced mounted on top of the PIiS chip. Built in through -sili con vias (TSVs) have been added to serve as signal paths and thermal plugs. The demonstrated DC DC converter delivers 1.8V and 500mA output power at 6 MHz with the peak efficiency of 80%. Table 7 1 compares the PIiS based converter and the commercialized c onverters with integrated inductors. It should be noted the indicated size of the PIiS based converter includes the IC chip, the PIiS and the input and output capacitors, while the listed sizes of the commercialized converters do not include the capacitors Table 7 1 Comparison of the PIiS based converter and the commercialized converters with integrated inductors f sw (MHz) L (uH) V in (V) V out (V) I out (A) C in / C out (uF) Footprint (mm3) Unit price LTM4608 [101] 1.5 2.3 5.5 0.6~5 8 10/100 1592.8 $12.43 EN5365QI [10] 5 0.09 2.3~5.5 0.75~3.3 6 47/47 10121.8 $4.40 EN5322QI [9] 4 0.5 2.4~5.5 0.6~ V in 2 10/47 461.1 $2.27 MIC3385 [11] 8 0.47 2.7~5.5 1~ V in 0.5 1/10 33.50.9 $1.75 FB6831J [20] 2.5 2.7~5.5 0.8~ V dd 0.5 4.7 /4.7 2.92.41 $1.5 PIiS 6 0.39 2.7 5.5 1.8 0.5 2.2/4.7 331.2 NA In summary, in this thesis work, ultra -compact PIiSs and a PIiS based DC DC converter have been demonstrated. This thesis work shows that the PIiS is a very promising approach for power converter integration and size reduction for portable electronics. 7 .2 Future work (a) Higher Power Application The DC -DC converter demonstrated in this work was designed to handle a 500 mA output current, which was limited by the employed power IC chip. H owever, the pro posed PIiS has a great potential to handle larger current up to 10 A. It has been calculated that a PIiS with 200 nH

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126 5mm by embedding copper winding into a 500m thick silicon wafer Excellent heat dissipation is one of the merits of PIiS. For a 500 mA and 1.8 V output power, the advantage of PIiS on the heat dissipation may not be so significant since the total heat generated from the power loss is not so serious. PIiS will show a big advantag e over other thin -film micro inductors when the output power is high. (b) Explore New Magnetic Materials It is clear that the two magnetic materials used in this study both have their strengths and draw backs. The permalloy has large p ermeability but low re sistivity. So the PIiS with permalloy has high low frequency inductance, while its inductance reduces in high frequency and it suffers serious eddy current loss in high frequency. The composite of magnetic powder and polymer has very high resistivity, but its permeability is low and its coercive is higher Therefore, a PIiS with magnetic powder core suffer larger size and larger DC resistance. Although the hyteresis loss of magnetic powder is much less serious than the eddy current loss of permalloy, it sti ll become the dominant loss of an inductor in high frequency. T o explore a new method to increase the permeability of magnetic composites or to find a new magnetic material that has better magnetic properties a nd can be fabricated in silicon becomes criti cal to further reduce the size and the loss of a PIiS. (c) Verify wafer -to wafer packaging A compact DC DC converter was demonstrated in this dissertation by die to -die packaging due to equipments availability and the size differences of the PIiS and the I C chips. After the inductor size being reduced to close to the size of a power IC, wafer to -wafer packaging should be verified, since wafer to -wafer packaging is believed to reduce the packaging cost dramatically.

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127 If high -density capacitors can also be rea lized on/in silicon, it is possible to do multiple wafers packaging with the through -wafer conducting paths in the PIiS as multiple wafer interconnections. (d) Reliability Only a simple thermal testing was performed in this dissertation. There are lots of more work should be done in the reliability testing before it can be used in the really application, such as: (1) thermal stability over temperature cycles; (2) mechanical vibration/shock testing and (3) packaging/humility/aging testing.

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128 LIST OF REFERENC ES [1] K. D. T. Ngo and R. Webster, "Steady-state analysis and design of a switched -capacitor DC DC converter," Aerospace and Electronic Systems, IEEE Transactions on, vol. 30, pp. 92101, 1994. [2] M. S. Makowski and D. Maksimovic, Performance limits of switched -capacitor DC DC converters," in Power Electronics Specialists Conference, 1995. PESC '95 Record., 26th Annual IEEE, 1995, pp. 12151221 vol.2. [3] R. W. Erickson and D. Maksimovic, Fundamentals of power electronics Norwell, Massachusetts: Kluwer Academic, 2000. [4] S. Chunlei, B. C. Walker, E. Zeisel, B. Hu, and G. H. McAllister, "A Highly Integrated Power Management IC for Advanced Mobile Applications," Solid -State Circuits, IEEE Journal of, vol. 42, pp. 17231731, 2007. [5] C. Systems, http://www.coilgun.eclipse.co.uk/coilgun_basics_3.html, 2004. [6] H. J. Bergveld, R. Karadi, and K. Nowak, "An inductive down converter system in package for integr ated power management in battery -powered applications," in Power Electronics Specialists Conference, 2008. PESC 2008. IEEE 2008, pp. 33353341. [7] P. Hazucha, G. Schrom, H. Jaehong, B. A. Bloechel, P. Hack, G. E. Dermer, S. Narendra, D. Gardner, T. Karn ik, V. De, and S. Borkar, "A 233-MHz 80%87% efficient four -phase DC DC converter utilizing air -core inductors on package," Solid -State Circuits, IEEE Journal of, vol. 40, pp. 838845, 2005. [8] J. Wibben and R. Harjani, "A High-Efficiency DC DC Converter Using 2 nH Integrated Inductors," Solid -State Circuits, IEEE Journal of, vol. 43, pp. 844854, 2008. [9] Enpiron, "EN5322Q datasheet," 2007. [10] Enpiron, "EN5396Q datasheet," 2007. [11] Micrel, "MIC3385 datasheet," 2007. [12] F. C. Lee, J. D. van Wyk D. Boroyevich, L. GuoQuan, L. Zhenxian, and P. Barbosa, "Technology trends toward a system -in a module in power electronics," Circuits and Systems Magazine, IEEE, vol. 2, pp. 4 22, 2002. [13] S. C. O. Mathuna, T. O'Donnell, W. Ningning, and K. Rinne, Magnetics on silicon: an enabling technology for power supply on chip," Power Electronics, IEEE Transactions on, vol. 20, pp. 585592, 2005. [14] "LM2832 datasheet," National Semiconductor.

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BIOGRAPHICAL SKETCH Mingliang Wang received his B.S. and M .S. degree in Mechanic al and Electrical Engineering from Xiamen University, Xiamen, China in 2001 and 2004, respectively. He also holds a M.S. and a Ph.D. in Electrical and Computer Engineering from the University of Florida in 2008 and 2010. His research interests include the design and fabrication of monolithic integrated high power density converter, micro-fabrication technologies and power packaging.