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Strain Effects on the Performance of Silicon MOSFETs

Permanent Link: http://ufdc.ufl.edu/UFE0041195/00001

Material Information

Title: Strain Effects on the Performance of Silicon MOSFETs
Physical Description: 1 online resource (103 p.)
Language: english
Creator: Yang, Xiaodong
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: leakage, mobility, mosfet, strain, workfunction
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Since the first integrated circuits were invented in the 1960s, semiconductor technology has been so successful to exponentially improve the microprocessor performance during the past half century. This amazing growth becomes more difficult as physical limits of materials are being challenged. Strain technology is a key element in current 32nm node and is widely believed to be used in the future 28 and 22nm technology, since the technique is compatible with other new device structures such as high-k/metal gate, SOI, and FinFETs to deliver large drive current. In this dissertation, strain induced gate leakage current change, mobility enhancement at low temperature, effective work function change are comprehensively studied which could provide a better understanding of the strain technology and its potential application for the most advanced semiconductor devices. A simple physical picture for stress altered gate direct tunneling current in n and p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) is presented. It is shown that the gate electron tunneling current decreases (increases) for uniaxial tensile (compressive) stress. The stress altered gate hole tunneling current is opposite to the electron current. These results can be understood from the strain-altered out-of-plane effective mass, energy splitting, and carrier population. It is indicated that longitudinal tensile stress increases the carrier population in the delta 2 valley having a large out-of-plane mass which results in a decreased electron tunneling current. Whereas, uniaxial tension enlarges the hole gate direct tunneling current by decreasing the density of holes from top band with a larger out-of-plane mass. However, due to weak confinement in accumulation, the normalized leakage current change is higher in accumulation than in inversion. A self-consistent solution to the Poisson and Schro umlautdinger's equation considering the strain Hamiltonian combined with the transfer matrix method are used for modeling the tunneling process. Hole and electron mobility is studied for strained p and n-channel MOSFETs at low temperature. Longitudinal compressive stress increased hole mobility enhancement is observed as temperature is lowed from 300K to 87K. With a six band k.p model and finite difference formalism, comparison with calculation suggests hole mobility is phonon-limited at room temperatures, while it is limited by both surface roughness and phonon scattering around 87K. Strain induced mobility enhancement at low temperature arises from the reduction of the average hole conductive effective mass due to band warping. However, surface roughness reduction is the dominant physical mechanism for n-channel MOSFETs. Several physical models are discussed and a reasonable modification of present model is presented. Metal gate induced effective work function change provide a good candidate for work function tuning which is one of the most challenge parts for the present high-k/metal gate devices. Both external mechanical stress and process induced large stress indicated that the effective work function always decrease with the applied stresses regardless the type of stresses. Although the stress induced by the TiN gate strongly depends on the thermal treatment, thermal annealing process generates tension inside the gate. Bowing technique and charge pumping method are used for stress and interface state measurement, respectively. It is indicated that the EWF decrease with the reduction of metal gate thickness and the interface state induced donor-like charge generation is the dominant physical mechanism.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Xiaodong Yang.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Thompson, Scott.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0041195:00001

Permanent Link: http://ufdc.ufl.edu/UFE0041195/00001

Material Information

Title: Strain Effects on the Performance of Silicon MOSFETs
Physical Description: 1 online resource (103 p.)
Language: english
Creator: Yang, Xiaodong
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: leakage, mobility, mosfet, strain, workfunction
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Since the first integrated circuits were invented in the 1960s, semiconductor technology has been so successful to exponentially improve the microprocessor performance during the past half century. This amazing growth becomes more difficult as physical limits of materials are being challenged. Strain technology is a key element in current 32nm node and is widely believed to be used in the future 28 and 22nm technology, since the technique is compatible with other new device structures such as high-k/metal gate, SOI, and FinFETs to deliver large drive current. In this dissertation, strain induced gate leakage current change, mobility enhancement at low temperature, effective work function change are comprehensively studied which could provide a better understanding of the strain technology and its potential application for the most advanced semiconductor devices. A simple physical picture for stress altered gate direct tunneling current in n and p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) is presented. It is shown that the gate electron tunneling current decreases (increases) for uniaxial tensile (compressive) stress. The stress altered gate hole tunneling current is opposite to the electron current. These results can be understood from the strain-altered out-of-plane effective mass, energy splitting, and carrier population. It is indicated that longitudinal tensile stress increases the carrier population in the delta 2 valley having a large out-of-plane mass which results in a decreased electron tunneling current. Whereas, uniaxial tension enlarges the hole gate direct tunneling current by decreasing the density of holes from top band with a larger out-of-plane mass. However, due to weak confinement in accumulation, the normalized leakage current change is higher in accumulation than in inversion. A self-consistent solution to the Poisson and Schro umlautdinger's equation considering the strain Hamiltonian combined with the transfer matrix method are used for modeling the tunneling process. Hole and electron mobility is studied for strained p and n-channel MOSFETs at low temperature. Longitudinal compressive stress increased hole mobility enhancement is observed as temperature is lowed from 300K to 87K. With a six band k.p model and finite difference formalism, comparison with calculation suggests hole mobility is phonon-limited at room temperatures, while it is limited by both surface roughness and phonon scattering around 87K. Strain induced mobility enhancement at low temperature arises from the reduction of the average hole conductive effective mass due to band warping. However, surface roughness reduction is the dominant physical mechanism for n-channel MOSFETs. Several physical models are discussed and a reasonable modification of present model is presented. Metal gate induced effective work function change provide a good candidate for work function tuning which is one of the most challenge parts for the present high-k/metal gate devices. Both external mechanical stress and process induced large stress indicated that the effective work function always decrease with the applied stresses regardless the type of stresses. Although the stress induced by the TiN gate strongly depends on the thermal treatment, thermal annealing process generates tension inside the gate. Bowing technique and charge pumping method are used for stress and interface state measurement, respectively. It is indicated that the EWF decrease with the reduction of metal gate thickness and the interface state induced donor-like charge generation is the dominant physical mechanism.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Xiaodong Yang.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Thompson, Scott.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0041195:00001


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1 STRAIN EFFECTS ON THE PERFORMANCE OF SILICON MOSFET S By XIAODONG YANG A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOS OPHY UNIVERSITY OF FLORIDA 2009

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2 2009 Xiaodong Yang

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3 To my dear m other

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4 ACKNOWLEDGMENTS First of all, I would like to thank my advisor, Dr. Scott E. Thompson, for his continuous encouragement and patient guidance I have learned from Dr. T hompson not only how to do experiment al and theoretical research, but also how to explore this world as an electrical engineer I would also like to thank Dr. Toshikazu Nishida for his numerous critical advices in experimental measurements and academic wri tings. I would like to thank Dr. Christopher J. Stanton and Dr. Jing Guo for serving as my committee members in their busy schedules and providing important comments about this dissertation. I would like to thank Dr. Thomas Hoffman for offering me an excel lent internship opportunity at IMEC where I met lots of talented experts in semiconductor field and learned the differences between industry and academia. I would like to thank m y colleagues at SWAMP They have contributed a lot to my research activities. Dr Yongke Sun and Dr. Guangyu Sun provide a lot of help in the simulation process. Dr. Jisong Lim, Dr. Younsong Choi, Srivatsan Parthasarathy and Andrew Koehler gave me tremendous suggestions in experimental measurements. I would also like to thank othe r pervious and present group members, Dr. Sagar Suthram, Dr. Kehui Wu, Min Chu Hyunwoo Park, Uma Aghoram, Tony Acosta Ukjin Roh and Mehmet Baykan for their helps This dissertation is dedicated to my family I would like to especially thank my mother fo r her constant support and understanding. I also would like to thank my beautiful girlfriend Yajing Wang for motivating and helping me realize my dream.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................................... 4 LIST OF TABLES ................................................................................................................................ 7 LIST OF FIGURES .............................................................................................................................. 8 ABSTRACT ........................................................................................................................................ 12 CHAPTER 1 INTRODUCTION ....................................................................................................................... 15 Traditional CMOS limits ............................................................................................................ 15 Strained Silicon ........................................................................................................................... 16 Biaxial Strained Silicon Devices ........................................................................................ 17 Uniaxial Strained Silicon Devices ...................................................................................... 18 Motivation .................................................................................................................................... 19 Outline of the Dissertation .......................................................................................................... 20 2 STRAIN EFFECTS ON BULK SI LICON BAND STRUCTURE .......................................... 22 Stress and Strain .......................................................................................................................... 22 Strain Effect on Conduction Band ............................................................................................. 25 Strain Effect on Valence Band ................................................................................................... 26 3 STRAIN INDUCED LEAKAGE CURENT CHANGE .......................................................... 29 Leakage Current Change in Inversion Regime ......................................................................... 30 Quantum Mechanical Model for n -Channel MOSFETs ................................................... 33 A. Self -consistent solution of Schrdinger and Poisson equations ........................... 35 B. Tunneling current .................................................................................................... 36 Quantum Mechanical Model for p -Channel MOSFETs ................................................... 39 Qualitative Analysis of Tunneling Current Change .......................................................... 43 Leakage Current Change in Accumulation Regime for n Channel MOSFETs ...................... 46 Summary ...................................................................................................................................... 55 4 LOW TEMPERATURE EFFECT ON MOBILITY IN STRAINED MOSFETS .................. 57 Scattering Mechanism ................................................................................................................. 58 Phonon Scattering ................................................................................................................ 59 Surface Roughness Scattering............................................................................................. 60 Low Temperature Effect on Mobility in Strained p -channel MOSFETs ................................ 61 Low Temperature Effect on Mobility in Strained n -channel MOSFETs ................................ 68 Summary ...................................................................................................................................... 72

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6 5 EFFECTIVE WORK FUNCTION CHANGE WITH THE APPLIED STRESS ................... 73 Effective Work Function Change with the External Mechanical Stress ................................. 74 Experimental Setup .............................................................................................................. 75 Experimental Results ........................................................................................................... 78 Effective Work Function Change wi th the Process Introduced Stress .................................... 81 Bowing Technique for Stress Measurement ...................................................................... 81 Charge Pumping for Interface States Measurement .......................................................... 82 Summary ...................................................................................................................................... 86 6 SUMMARY AND SUGGESTIONS ABOUT FUTURE WORKS ........................................ 87 Summary ...................................................................................................................................... 87 Suggestions about Future Works ................................................................................................ 88 LIST OF REFERENCES ................................................................................................................... 90 BIOGRAPHICAL SKETCH ........................................................................................................... 103

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7 LIST OF TABLES Table page 1 1 Performance enhancement challenges, difficulties, and possible solutions. ...................... 16 2 1 Independent component of the elastic t ensor in GPa and elastic compliance constants in 1012m2/N. ........................................................................................................................... 25 3 1 Luttinger -Kohn parameters, deformation potentials and split off energy for Si and Ge. ................................................................................................................................................. 41 5 1 EWF and its change with different metal gate thickness as 10, 5, and 2 nm, respectively. ............................................................................................................................ 78

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8 LIST OF FIGURES Figure page 1 1 Biaxial tensile stressed Silicon on relaxed SiGe layer ......................................................... 18 1 2 TEM micrographs of p and n -channel MOSFETs with 45 nm gate length. ..................... 18 2 1 Nine stress components acting on a small cube. .................................................................. 23 2 2 (a) Conduction band structure of silicon in the unstrained case. Ellipsoids of constant electron energy in reciprocal k sp ace, each corresponding to one of the degenerate conduction band valleys. (b) A lo ngitudinal uniaxial tensile stress in the (001) silicon place removes the degeneracy between the four in out of ...................................................................................................... 26 2 3 Valence band and const ant energy surfaces (E=25meV) in k space for the top band and bottom band in the case of (a) unstressed silicon, (b) longitudinal compressive stress, and (c) biaxial tensile stress. ...................................................................................... 27 3 1 The four point bending jig used to apply uniaxial stress to the substrate. In this picture, (a) uniaxial tensile and (b) compressive stresses are generated on the p type silicon and n -type silicon substrates respectively. ............................................................... 30 3 2 Schematic diagrams illustrate the carrier separation measurement for n -channel MOSFETs. Is/d measured the electron current tunneling from p -type silicon substrate. The set up for p -channel MOSFETs is similar with this. .................................................... 31 3 3 Carrier separation measurement results indicate that electron conduction process is dominant in n -channel MOSFETs (a) and hole is dominant in p -channel MOSFETs (b). ........................................................................................................................................... 32 3 4 The normalized the electron and hole tunneling current change versus the applied tensile and compressive stress on (100) wafer for n-channel MOSFETs (a) and p channel MOSFETs (b), respectively. .................................................................................... 34 3 5 Unstressed, biaxial stressed, and uniaxial stressed Silicon constant surface at 25meV below valence band. ............................................................................................................... 43 3 6 Charge density versus applied stress for the top, bottom, and split off bands for three applied stresses. (a) uniaxial compression, (b) biaxial compression, and (c) biaxial tension. The inset shows the simplified hole valence band structure for out -of -plane direction with the c orresponding effective mass. ................................................................. 44 3 7 The relative change of the tunneling currents versus applied uniaxial compression, biaxial compression, and biaxial tension, respectively. Dots are experime ntal data and lines are physical model. ................................................................................................. 45

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9 3 8 Schematic band diagram and subband splitting diagrams for direct carrier tunneling process in (a) n channel MOSFETs and (b) p -channel MOSFETs, re spectively. Black (white) dots represent electrons (holes). Number of the dots represents the population density of carriers. ............................................................................................... 47 3 9 Schematic band diagram for direct electron tunneling in an n -channel MOSFET for accumulation layer (a) and inversion layer (b), respectively. ............................................. 50 3 10 The normalized the electron tunneling current change versus the applied uniaxial longitudinal tensile stress on (100) wafer for accumulation layer (a) and inversion layer (b), respectively. ............................................................................................................ 52 3 11 (a) The lowest subband energy level in stress for both inversion and accumulation layer, where the zero of energy is taken to be the bottom of the conduction band; (b) The normalized lowest subband energy level change with the applied uniaxial stress in accumulation layer. ................................................................................................................ 53 3 12 Spatial distributions of the electron density in the n -channel MOSFETs for accumulatio n layer (a) and inversion layer (b), respectively. The inset shows the surface charge density change for the tensile stress from compressive 3 GPa to tensile 3 GPa i.e. 3000~3000MPa .................. 55 4 1 Schematic diagram of effective field dependence of total mobility in inversion layer. Total scattering mechanism including the phonon, surface roughness and coulomb scattering. Coulomb scattering is neglected for h igh effective field [77]. .......................... 59 4 2 Measured (dots) and calculated (lines) hole mobility and normalized mobility enhancement (Inset) for (100) Si along the <110> channel direction as a function of temperature for unstressed, 20MPa, 45MPa, and 60MPa longitudinal compressive stressed p channel MOSFETs. .............................................................................................. 62 4 3 (a) Energy contours at 25meV (red line) and 150meV (blue line) to the top band edge on the (100) surface with zero (solid line), 0.06GPa (dotted line), and 1GPa (dashed line) uniaxial compressive stress along the <110> direction. (b) Normalized conductivity effective mass reduction as a function of temperature for 20MPa, 45MPa, and 60MPa longitudinal compressive stressed p-channel MOSFETs. ................. 64 4 4 Calculated phononlimited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed (triangle dots) and 60MPa longitudinal uniaxial compressive stressed (square dots) p channel MOSFETs. ................................... 66 4 5 Relative contribution by phonon-limited mobility and surface roughness limited mobi lity for a (100)/<110> Si p-channel MOSFET with 60MPa longitudinal uniaxial compressive stress. ................................................................................................................. 66

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10 4 6 Calculated surface roughness limited mobility for (100) Si along the <110> channel direct ion as a function of temperature for unstressed (triangle dots) and 60MPa longitudinal uniaxial compressive stressed (square dots) p -channel MOSFETs. .............. 67 4 7 Calculated optical phonon, acoustic phonon, and surface roughness scattering rate for p -channel MOSFETs along the <110> channel direction as a function of longitudinal compressive stress at (a) 300K and (b) 87K, respectively. ............................ 68 4 8 Measured (dots) and calculated (lines) electron mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal compressive stressed n -channel MOSFETs. ......................................................................... 69 4 9 Calculated phononlimited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal tensile stressed n -channel MOSFETs. ............................................................................................................ 71 4 10 Calculated surface roughness limited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal tensile stressed n channel MOSFETs. .............................................................................................. 71 5 1 Terraced oxide wafer with different silicon oxide thickness from 1 to 4 nm. Highk and metal gate are deposited with the same thickness. ........................................................ 74 5 2 (a) Measured capacitance voltage curve results for a single terraced wafer with different silicon oxide thickness. (b) The flat band voltage as a function of EOT. A good linear relation is show for these devices. ..................................................................... 76 5 3 Experimental setup of four point bending jig for uniaxal stresses (a) schematic diagram (b) actually jig from side view. ............................................................................... 77 5 4 Extracted EWF for TiN gate stack with un iaxial stress (a), and biaxial stress (b). WF_D21, WF_D22, WF_D23 represent the TiN gate thickness as 10, 5, and 2nm, respectively. ............................................................................................................................ 79 5 5 Normalized EWF change for TiN gate stack with uniaxia l stress (a), and biaxial stress (b). WF_D21, WF_D22, WF_D23 represent the TiN gate thickness as 10, 5, and 2nm, respectively. ........................................................................................................... 80 5 6 Schematic diagram of high k/metal gate MOSFETs with differ ent metal gate thickness. Higher stress in expected for MOSFETs with thinner metal gate. IL is the interfacial layer between the Silicon and HfSiO. ................................................................. 81 5 7 Diagram for Bowing measurement, where R is the calculated radius of curvature, ts is the substrate thickness, tf is the film thickness, and rsc is the scan distance. ...................... 82 5 8 Measured average stress on the wafer for MOSFETs without thermal treatment, 600C annealing, and 1035C annealing, respectively. It is clearly shown that the stress always increase for MOSFETs with thinner metal gate thickness. ..................................... 83

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11 5 9 Schematics of c harge pumping measurement setup for an n channel MOSFET [143]. .... 84 5 10 Schematics illustration of the two level charge pumping method for an n-channel MOSFET. In this situation, base level of the gate pulse is increased and the substrate switches from strong accumulation to strong inversion. The upper curve shows the charge pumping current change with the base gate voltage level. ...................................... 84 5 11 Measured Charge pumping current on an n-channel MOSFET with 2, 5, and 10 nm TiN gate electrode. ................................................................................................................. 85 5 12 Schematic diagram for stress induced generation of donor like interface traps bet ween the interfacial layer and the Silicon substrate. ....................................................... 85

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12 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of D octor of Philosophy STRAIN EFFECTS ON THE PERFORMANCE OF SILICON MOSFETS By Xiaodong Yang December 2009 Chair: Scott E. Thompson Major: Electrical and Computer Engineering Since the first integrated circuits were invented in the 1960s, semiconductor t echnology has been so successful to exponentially improve the microprocessor performance during the past half century. This amazing growth becomes more difficult as physical limits of materials are being challenged. Strain technology is a key element in cu rrent 32nm node and is widely believed to be used in the future 28 and 22nm technology, since the technique is compatible with other new device structures such as high k/metal gate, SOI, and FinFETs to deliver large drive current. In this dissertation, str ain indu ced gate leakage current change, mobility enhancement at low temperature, effective work function change are comprehensively studied which could provide a better understanding of the strain technology and its potential application for the most adva nced semiconductor devices A simple physical picture for stress altered gate direct tunneling current in n and p -channel metal -oxide -semiconductor field effect transistors (MOSFET s ) is presented It is shown that the gate electron tunneling current decrea ses (increases) for uniaxial tensile (compressive) stress. The stress altered gate hole tunneling current is opposite to the electron current. These results can be understood from the strainaltered out -of -plane effective mass, energy splitting, and carri er population. It is indicated that l ongitudinal uniaxial tensile stress increase s the carrier population

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13 2 valley having a large out of plane mass which results in a decreased electron tunneling current. Whereas, uniaxial tension enlarges the hol e gate direct tunneling current by decreasing the density of holes from top band with a larg er out -of -plane mass. However, due to weak confinement in accumulation, the normalized leakage current change is higher in accumulation than in inversion. A self -co nsistent solution to the Pois s on and Schrdingers equation considering the strain Hamiltonian combined with the transfer matrix method are used for modeling the tunneling process. Hole and electron mobility is studied for strained p -channel and n channel MOSFETs at low temperature. Longitudinal compressive stress increased hole mobility enhancement is observed as temperature is lowe d from 300K to 87K. With a six band k p model and finite difference formalism, comparison with calculation suggest s hole mobil ity is phonon limited at room temperatures, while it is limited by both surface roughness and phonon scattering around 87K Strain induced m obility enhancement at low temperature arises from the r eduction of the average hole conductive effective mass due t o band warping. However, surface roughness reduction is the dominant physical mechanism for n -channel MOSFETs. Several physical models are discussed and a reasonable modification of present model is presented. Metal gate induced effective work function ch ange provide a good candidate for work function tuning which is one of the most challenge parts for the present highk/metal gate devices Both external mechanical stress and process induced large stress indicated that the effective work function always de crease with the applied stresses regardless the type of stresses. Although the stress induced by the TiN gate strongly depends on the thermal trea tment, thermal annealing process constantly generates tension inside the gate. Bowing technique and charge pu mping method are used for stress and interface state measurement, respectively. It is indicated

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14 that the EWF decrease with the reduction of metal gate thickness and the interface states increase induced donor like charge generation is the dominant physical mechanism.

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15 CHAPTER 1 INTRODUCTION Traditional CMOS limits The first metal -oxide -semiconductor field -effect transistor (MOSFET) and integrated circuits (IC) were invented in the beginning of 1960s. From that time traditional semiconductor technologies ha ve been so successful to exponentially improve performance during the past fift y years. This amazing growth was predicted in 1965 by Gordon Moore [1] who is the co -founder of the largest semiconductor company in the world, Intel Corporation. However, furth er scaling down of the feature size to the nanometer region becomes more difficult as physical limits of existing structure s and materials are reach ed. Key reasons that prevent the continuous scaling down of current semiconductor devices are 1) static powe r consumption due to direct gate tunneling and band to band tunneling [2]; 2) large source -drain series resistance in the source and drain region [3,4]; 3) The lithography limitations; 4) the limited subthreshold slope. With the above restrictions, possi ble solutions fall into two categories: 1) changes of the present transistor structures, and 2) substitutes of new materials or modifications of current material. Non -traditional device structures such as FinFETs, double gate MOSFETs and ultra thin body MO SFETs (SOI) are promising candidates Similarly, on the new materials, high k materials such as Hafnium component dielectrics with metal gate materials have shown high performance results beyond 45nm technology node [5], and are considered favorable for co ntinuous scaling down to 28 and 22nm Table 1 1 [6] summarizes these challenges difficulties, and corresponding possible technology options. The performance of MOSFETs is increased with better charge control, electron/hole transportation, and less parasi tic resistance/capacitance. Especially, the mobility enhancement could improve the performance greatly for advanced MOSFETs beyond 90nm. A

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16 proper structure or material is required here to provide continuous mobility enhancement in order to continue the fam ous Moores Law. Table 1 1. Performance enhancement challenges difficulties, and possible solutions Source of enhancement Parameters been changed Possible m ethod Charge density 1.S (subthreshold slope) 2. Qinv (inversion charge) 1. Multi gate MOSFET s 2. Low working temperature. Electron/hole transport 1.Mobility 2. V elocity 3. Ballistic transport 1. Strained silicon. 2. High mobility materials (e.g., Ge, III -V) 3 Low working temperature. Parasitic resistance 1.R S/D 1. Extended s ource and drain. 2. Low er Schottky contact. Parasitic capacitance 1.C j 2.CGD, CGS, CGB 1. SOI. 2. Multi gate MOSFETs Strained Silicon As shown in Table 1 1, Carrier transport could be improved by high mobility materials, e.g., Germanium, whi ch was the first materia l which is utilized in the modern semiconductor devices, but silicon substituted it very quickly during the beginning of 1960s, because Silicon has several advantages compared with Germanium. At first, Silicon can be easily oxidized as SiO2 with high quality as a insulator layer for MOSFETs. Secondly, there is tremendous Silicon element available on the earth and it is very easy to obtain, which made Silicon an excellent material used for high volume industry production Wide band ga p of Silicon compared with Germanium made it easily to operate at critical conditions like high temperatures. Meanwhile,

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17 well established processing advantages were the dominant reasons for the use of Silicon over other semiconductor materials like III -V m aterials [7]. Without sacrificing too much production cost and still maintain ing performance improvements as stated in Moore's law s train technology is a key element in current MOSFET technol ogies and is widely believed also in the future 22 nm technology node since it can enhance the drain current without decreas ing the transistor gate length. Furthermore, the technique is compatible with other new device structures such as multi gate, SOI and high k/metal gate devices, with deliver ing larg e drive current s [8 9]. For example, the advantages of an ultra thin body MOSFET, such as the better inversion charge control of the channel by the gate, can be combined with enhanced electron or hole mobility provided by strained Silicon Therefore, better understandin g of strain technology is critical to improve the performance of Silicon MOSFETs There are normally two kind of strain were applied for the silicon devices. Biaxial strain is evenly distributed over the whole surface, whereas the uniaxial strain is applie d along a particular direction within the transport surface which is commonly along the channel direction or longitudinal direction. Biaxial Strained Silicon Devices Because the lattice constants of Si licon and Germanium are differ ent by 4.2%, the epitaxia l layers of Silicon will be naturally biaxial tensioned as shown in Fig. 1 1. Stress, strain, band gap and piezoresistance on SiGe technology have been widely studied since 1950s [ 10]. I n 1975, first Si1xGex layers with x<0.15 were grown on Silicon surfac e using ultra high vacuum epitaxial technology [11 ]. At the beginning because strain destroys the original crystal structure and cannot be avoided, it was considered as a disadvantage and people were always trying to eliminate strain from the process However, in 1982, it was found that strain provided an additional choice for band structure engineering [ 12]. A fter that MOSFET s with biaxial strain

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18 were fabricated [ 13]. To date, biaxial tensile strain has been widely investigated both experimentally and theoretically in CMOS technology [9]. Normally, i t improves the electron mobility, but decreases the hole mobility at small stress range. Figure 1 1. Biaxial tensile stressed Silicon on relaxed SiGe layer Uniaxial Strained Silicon Devices In 2002, uniaxial stress has been applied to 90nm tec hnology node by Intel to improve the mobility without substantially increased manufacturing complexity [14]. In order to achieve mobility enhancement l ongitudinal compressive stress for p -channel MOSFETs and longitudinal tensile stress for n channel MOSFE Ts are the most effective ones Usually uniaxial strain is Figure 1 2 TEM micrographs of pand n -channel MOSFET s with 45 nm gate length

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19 in troduced from the source and train using SiGe for p channel MOSFETs and a nitride capping layer with a large ten sile stress for n -channel MOSFETs Transmission electron micrographs (TEMs) of p channel and n -channel MOSFETs are shown in Fig. 1 2. Based on the performance from both biaxial and uniaxial strained MOSFETs, industry prefer the uniaxial strain because: 1) uniaxial stress enhances hole mobility at both low stress and high electric field due to the large band warping of the valence band induced conductivity effective mass reduction [15]; 2) uniaxial stress could be used to enhance the mobility of nanosca le short channel devices whereas biaxial stress is becoming more and more difficult to apply beyond 90nm technology node ; 3) process induced uniaxial stress causes much smaller threshold voltage change which is critical for high k/metal gate devices [8]. Based on the above advantages for uniaxial s tress the industry is now looking at other uniaxial st ressors except the two metho d mentioned above. For instance, Yang et al. Reported a high performance CMOS devices, in which nitride contact layers were used a s dual stress layers to induce tensile and compressive stress simultaneously. This dual stress layers technology results in about 10% and 30% effective mobility enhancement for both electrons and holes, respectively [16]. Motivation Based on the above disc ussion, we noticed that strain technology has been widely used in the semiconductor industry and is very promising in the future technology node. For better utilizing of strain technology, physical mechanism understanding is inevitable for the advance MOS FET device s Although the strain altered MOSFET s in -plane conductivity mass and its e ffect on mobility has been studied[17~20], much less understood is how strain alters the out of -plane conductivity effective mass and the band offset between Si and SiO2, both of which will affect the direct tunneling gate current which dominates in ultra thin oxides. For these reasons, it is

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20 important to understand how strain alters the MOSFET gate current from inversion layers Meanwhile, the direct tunneling process of electrically programmable read only memories (EPROMs) [21], and the gate tunneling current occurring in memory cells [22,23] make the understanding of the tunneling process in the accumulation layer increasingly important. L arge mobility enhancement has been experimentally achieved for holes by longitudinal compression at normal operation condition. Further study of hole mobility at lo w temperature can provide more physical insight on strain-enhanced performance of Silicon MOSFETs. To date, much less unde rstood is how strain alters the phonon scattering, surface roughness scattering, and conductivity effective mass for p -channel MOSFETs at low temperature. While enormous studies has been placed on the temperature effect on n-channel strained MOSFETs [24, 25]. However, a big discrepancy still exists between experimental and theoretical expectations [26~29] for n-channel MOSFETs due to less understanding about surface roughness change with the applied stress. Strain induced work function change provide s anoth er effective candidates for threshold voltage tuning Meanwhile, considering the mobility degradation for highk/metal gate devices, the compatibility between the strain technology and promising insulator substitutes with hi gh dielectric constant is critic al, especially beyond 45nm Both process and external mechanical bending induced stresses could provide a deep understanding for strain effects on high k/metal gate Silicon devices. Outline of the Dissertation This research focuses on the physics underlyi ng the st rain effects on leakage current, mobility and metal gate work function for Silicon MOSFETs. Chapter 2 provides a description of the strain effect on silicon band structure. Chapter 3 presents a detailed analysis for strain induced leakage current change for n and p -channel MOSFETs in inversion layers and

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21 accumulation layers. In Chapter 4, strain induced mobility change for p -channel and n -channel MOSFETs at low temperatures were discussed. Strain induced effective work function change for high k/m etal gate Silicon device are covered in Chapter 5. Finally, Chapter 6 provides some possible future study for strain and low temperature effects on novel devices, e.g., FinFETs, SOI.

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22 CHAPTER 2 STRAIN EFFECTS ON BU LK SILICON BAND STRU CTURE The band stru cture provides the information about the states of energy and the electronic dispersion relation under a specific condition Lots of studies have shown that if the band structure of the material is modifi ed, mechanical and electrical properties of the material will be also changed, such as effective mass and corresponding mobility [30]. Band structure analysis could prov ide more details about strain effect s on electron/hole transport property For instance, strain induced lattice constant change will induce band warping in both conduction band and valence band. However, the effective mass change is much more important for holes in valence band due to strong correlation between six subbands. Stress and Strain Because of the elasticity of the materials, the de formation of structure under the application of an external force could be recovered back to their original shape after the force is removed. The external applied force is known as stress, while the amount of deformation is named the strain The stress at one particular position may be considered as forces F put on a very small area A By making the area infinitesimally small er the stress vector [31] 0limAF A (2.1) From Figure 2 1, we could understand that the force acting on a small area can be decomposed into a force within the small area, a shear component and a force which is perpendicular to the small area, a normal component. The shear stress can be further divided into two orthogonal force components Totally, there are three total stress components on each small area.

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23 Figure 2 1. Nin e stress components acting on a small cube. Thus, the stress on a small element can be expressed b y nine stress components i.e., three normal and six shear components. These components compose the stress tensor as xxxyxz yxyyyz zxzyzz (2.2) where the shear stress components across the diagonal are identical due to static equilibrium of materials ,,xyyxyzzyxzzx (2.3) Similarly as stress, strain could also be expressed with a symmetric tensor xxxyxz yxyyyz zxzyzz (2.4)

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24 The relation between stress and strain was first expressed by Hooks law, which concluded that deformation of a material shape is linearly related to the outside force applied. The Hooks law in matrix form for crystals with cubic symmetry is 111212 121112 121211 44 44 44000 000 000 2 00000 2 00000 2 00000xx xx yy yy zz zz yz yz xz xz xy xyCCC CCC CCC C C C (2.5) where Cij is the independent element of the elastic tensor matrix Normally people interested in the strain value with a certain stress applied The strain components could be expressed by invert ed Hook's law and using the compliance coefficients Sij as 111212 121112 121211 44 44 44000 000 000 2 00000 2 00000 2 00000xx xx yy yy zz zz yz yz xz xz xy xySSS SSS SSS S S S (2.6) The three independent compliance coefficients can be expressed as 1112 11 22 11111212 12 12 22 11111212 44 44, 2 2 1 CC S CCCC C S CCCC S C (2.7) The compliance coefficients and Cij for Si and Ge are listed in Table 2 1.

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25 Table 2 1. Independent component of the elastic tensor in GPa and elastic compliance constants in 1012m2/N. C 11 C 12 C 44 S 11 S 12 S 44 Si 166.0 64.0 79.6 2.13 7.67 12.6 Ge 126.0 44.0 67.0 2.50 9.69 14.8 For <110> longitudinal stress, the strain tensor could be expressed as 1112 44 44 1112 12()/2/40 /4()/20 00 SSS SSS S (2.8) F or biaxial stress, the strain tensor could be expressed as 1112 1112 1200 00 002 SS SS S (2.9) Strain Effect on Conduction Band For n -channel MOSFETs, the band structure close to the conduction band edge can be approximately expressed by parabolic energy dispersion. For the momentum at the bottom of the conduction band min 02/(0,0,0.85) ka the energy dispersion is 222 22 min() () () 22xy z ltkk kk Ek mm (2.10) where ml=0.92 m0 is the longitudinal mass and mt=0.19m0 is the transverse mass of Silicon. Due to the point symmetry of the fcc lattice structure of Silicon, the six ellipsoidal energy surfaces are equivalent and g enerated Consequently, t he conduction band is consists of six equal 6) with the same energy as shown in Fig. 2 2 (a). Stress longitudinal to the <110> channel or

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26 vertical electrical field from the applied gate to source voltage removes the degeneracy between the four in -of as shown in Fig. 2 2 (b). KzKxKy KzKyKx224444(a) (b) 666666Unstrained Bulk Strained Bulk 246 Figure 2 2 (a) Conduction band structure of silicon in the unstrained case. Ellipsoids of constant electron energ y in reciprocal k space, each corresponding to one of the degenerate conduction band valleys. (b) A longitudinal uniaxial tensile stress in the (001) silicon place removes the degeneracy between the four in of -plane valle Strain Effect on Valence Band For holes, the valence -band structure of silicon is much more complicated than the conduction band. For unstrained silicon at room temperature, holes occupy the top two subbands The unstrained constant energy surfac es (E=25meV) for the top and bottom bands are shown in Fig. 2 3 (a). With the application of strain, the light and heavy hole bands which is normally

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27 used, lose their meaning with energy levels and become mixtures of two bands due to band warping and band shifting. Correspondingly, we name the bands the top and the bottom band. The warped bands diagram and the corresponding 3D constant energy surfaces are shown in Fig. 2 3 (b) and (c) for the applied longitudinal compressive stress and biaxial tensile stre ss, respectively [26, 32], in which strain remove the degeneracy and reduce the coupling between the top band and the bottom band. It is observed that the out of -plane effective mass of the top Top BandBottom Band EK(a) Top BandBottom Band K E(b) Top BandBottom Band KE(c) Unstrained Uniaxial Strained Biaxial Strained<001> <110> KxKyKz <001> <110> Figure 2 3. Valence band and constant energy surfaces (E=25meV) in k space for the top band and bottom band in the case of (a) unstressed silicon, (b) longitudinal compressive stress, and (c) biaxial tensile stress. band is larger than that of the bottom band for the longitudinal compressive stress while the opposite results for biaxial tensile stress as see in Fig. 2 3 (b) and (c). However, the much smaller conductivity effective mass along the <110> direction of the top band is shown in Fig. 2 -

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28 3 (b) compared with the effective mass indicated in the unstrained si tuation. Both out of -plane and in -plane effective mass change are very important to understand the physical mechanism of strain induced performance change for Silicon MOSFETs.

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29 CHAPTER 3 STRAIN INDUCED LEAKA GE CURENT CHANGE The rapid scaling down of MOSFE Ts drives increasing device performance and fast growth of the information technology innovation The feature size of the technology node has been reduced to the nanometer scale during the past fifty years and fast gate oxide thickness scaling has resulted in a ~1 nm physical oxide [ 33] which already reaches the gate direct tunneling limit for SiO2. Strained silicon is being introduced to improve net transistors performance for MOSFETs beyond 90nm technology [14]. This chapter explains the physical mechanism for strain altered gate leakage current in both n -channel and p -channel MOSFETs under inversion or accumulation operation regime. There are several process techniques to introduce uniaxial stress into the silicon underlayer : a tensile or compressive cappi ng layer over a MOSFET [34, 35], high stress shallow trench isolation (STI) fill [ 36], or heteroepitaxy in the source and drain of nanoscale transistors [37]. For this work, a 4 point bending jig is used to apply uniaxial mechanical stress which is longitudinal or transverse to the <110> channel on a (100) wafer silicon as shown in Fig. 3 1 [ 15, 38, 39]. The external mechanical bending method is a very good candidate to investigate the strain effects on the performance of MOSFETs. The external bending jig excludes other process induced effects besides stress, like interface traps, nitrogen diffusion, annealing temperature effects, etc. These undesirable effects also contribute a lot to the performance change of MOSFETs and they are very hard to decouple fro m the strain effect for the process induced stress case The device samples used are from Intel 90nm technologies and consist of heavily doped poly -silicon gates, 1.3nm physical thickness SiO2 gate dielectrics, and ~ 51017cm3 substrate

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30 doping. The gate tu nneling current is measured with the drain, source, and body all tied to ground using a Keithley 4200 DC semiconductor characterization system. (a) (b)TensionCompression Figure 3 1. The four point bending jig used to apply uniaxial stress to the substrate. In this picture, (a) u niaxial tensile and (b) compressive stresses are generated on the p type silicon and n -type silicon substrates respectively. Leakage Current Change in Inversion Regime F or direct tunneling in MOSFETs t here are three major mechanisms: (a) electron tunneli ng from conduction band (ECB); (b) electron tunneling from valence band (EVB); and (c) holes tunneling from valence band (HVB). In order to determine the dominant tunneling mechanism, sample wafers were measured by carrier separation method [40]. Fig. 3 2 shows the experimental set up for n -channel MOSFETs, in which the n+ polysilicon gate is positively biased, while the p type silicon substrate and n type source/drain are grounded. Electrons tunneling from the inverted silicon substrate to the polysilicon gate is measured by the source/drain current (Is/d). Holes are collected by the substrate current (Isub). The gate tunneling

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31 current (Ig) is measured at 1.0 V gate bias For p -channel MOSFETs it is the exact same setup with 1.0V negative gate bias A N+ N+ PSubstrate N+ Poly A A Isub (holes) Is/d (electrons) Ig (electrons) Vg>0 electrons Figu re 3 2. Schematic diagrams illustrate the carrier separation measurement for n -channel M OSFETs. Is/d measured the electron current tunneling from p -type silicon substrate. The set up for p -channel MOSFETs is similar with this. Fig. 3-3 shows the measured results, in which the Ig is dominated by Is/d for both n and pchannel MOSFETs. The results show that ECB tunneling dominates in the in version regime in n channel MOSFETs [ 41]. In contrast, HVB dominates the gate leakage of the inverted pchannel MOSFETs in the bias range Vg<1 .0 V [1 2]. In all ECB cases, electrons can tunnel through the relatively small er 3.15eV b arrier rather easily than holes with 4.50V barrier. The experimental results for normalized the gate tunneling current change s versus the applied uniaxial compression (negative stress) and tension (positive stress) is shown for n channel MOSFETs in Fig. 34 (a) and p -channel MOSFETs in Fig. 3 4 (b). The gate current

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32 0.0 0.2 0.4 0.6 0.8 1.0 10-1210-1010-810-610-4 Ig (electrons) Isub (holes) Current (A)Vg (V) Is/d (electrons) N-MOSFET (a) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 10-1310-1110-910-710-5 Ig (holes)P-MOSFET Current (A)Vg (V) Is/d (holes) Isub (electrons) (b) Figure 3 3. Carrier separation measurement results indicate that elect ron conduction process is dominant in n -channel MOSFETs (a) and hole is dominant in p -channel MOSFETs (b).

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33 decreases/increases with tensile/compressive stress for electrons. However, the feature of the hole current s are opposite to the electron current s which are consistent with Zhaos recent results [ 42]. Because the most work on strained silicon during the past twenty years were focused on biaxial stress [43], we also show gate tunneling currents results for p-channel MOSFETs with applied biaxial stress compared with uniaxial stress in Fig. 3 4 (b) Strain induced gate tunneling leakage current change can be understood from the strainaltered out of -plane effective mass, subbands splitting, and carrier re population. T he direct tunneling current density u sually is expressed as a sum of the tunneling current contributions of the total subbands n G n nNJq (3. 1) where Nn is the inversi on charge population for the nth subband q is the electronic charge, and n is the corresponding lifetime of t he nth subband which depends on the out -of -plane effective mass and relative tunneling barrier height Quantum Mechanical Model for n -Channel MOSFETs The main effect of strain on electron band structure in silicon comes from the conduction band splitting. Longitudinal t ensile strain cause s the six -fold degenerate d valleys in unstrained silicon to split into two different valleys The group with low er energy is the two -fold degenerated 2 valley, whose longitudinal effective conductivity mass, ml, is perpendicular to the electron channel surface and the transverse effective conductivity mass mt, is parallel with the sur face. The other group, the four -fold degenerated 4 valley with higher energy, has a mt normal to the surface [26]. A full subband structure solution of the silicon inversion layer involves a self -consistent numerical sol ution of the Poisson s an d Schrdingers equations [44].

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34 -300 -200 -100 0 100 200 300 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 longitudinal stress, Zhao 2005N-MOSFET JG/JG (%)Stress (MPa) longitudinal stress, this work (a) -300 -200 -100 0 100 200 300 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 transverse stress, this work longitudinal stress, this work biaxial stress, this work longituidnal stress Zhao 2005P-MOSFET JG/JG (%)Stress (MPa) (b) Fig ure 3 4. The normalized the electron and hole tunneling current change versus the applied tensile and compress ive stress on (100) wafer for n -channel MOSFETs (a) and p channel MOSFETs (b), respectively

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35 A. Self -consistent solution of Schrdinger an d Poisson equations In the framework of the effective mass approximation, the electron nth eigenfunctions n and the nth subband energy levels En are derived from the time independent Schrdinger equation for a par ticular electrostatic potential V(x) 22 *2()()(), 2strain n nn nd HqVzzEz mdz (3.2 ) where nm is the out -of -plane effective mass associated with the electron motion perpendicular to the sur fac e, is the reduced Planck constant, strainH is the strain Hamiltonian, and q is the electron charge. For a (100) crystal of silicon, the out -of -plane effective mass for the 2 valley and 4 valley are 200.92 mm and 400.19 mm respectively where 0m is the mass for a free electron. In the oxide, an isotropic effective mass 00.5OXmm is us ed here [45]. To obtain the stra in Hamiltonian, the strain tensor is employed according to the deformation potential theory as in Eq. 2. 8 [46, 47]. In general the strain induced shift of the conduction band edge has a hydrostatic and a shear component. These shifts are conventionally ex pressed in terms of the deformation potentials d and u, respectively, ,2 332212 ()()() 33strain duijuH Tr (3.3) ,4 332211 ()()() 33strain duijuH Tr (3.4) where Hstrain and Hstrain are the strain Hamiltonians for the 2 and 4 valleys, respectively. For the shear deformation potential, u, used to calculate energy level splitting is well known with good accuracy from piezoresistance measurements and extracted to be 9. 16eV [48]. However, the hydrostatic deformation potential, d, is difficult to directly measure using the

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36 co nventional optical techniques. As a result, a very wide range of values even with opposite signs have been reported (1.13 to 10. 7 eV ) [49]. Accor ding to our previous measurement results based on the gate leakage current change for n -channel MOSFETs d is extracted to be 1.0 0.1 eV [39] which used in here for numerical simulation Once the strain Hamiltonian has been identified, t he simulation of th e electron density is obtain ed by add ing the population of each subband in each valley. The electron concentration in the quantum well is given by, 2 2() ln[1exp(/)](),dB FnBn nmkT nz EEkTz (3.5 ) where T is the absolute tem perature, kB is the Boltzmann constant, and EF is the Fermi energy level The DOS dm for the 2 and 4 valley s are ,2 00.19dmm and ,4 00.417dmm respectively T he elec trostatic potential () Vz in Eq. ( 3.2 ) is self -consistently determined using the total charge density from Poisson s equation [20], 2 2()[()()()()],da Sidq VzpznzNzNz dx (3.6 ) where Si is the permittivity of silicon, () pz is the hole density, () nz is the electron density, ()dNz is the dopant concentration, ()aNz is the accepter concentration For strong inversi on case in n channel MOSFETs, () nz and ()aNz are dominant. Based on the method of finite differences carrier population and the subband energy in the inversion layer were obtained by the self -consistent solution. B. Tu nneling current To compute the transmission probability, a simple analytical method based on the WKB approximation is normally used [50~52 ] and is pretty accurate for traditional MOSFETs with

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37 thick oxide layer. T he WKB approximation is only valid when the change of wave vector is much greater than the particle wave length. In other words, WKB approximation accuracy diminishes for ultra thin and low barriers [5 3 ]. Although modified WKB has been used for devices with ultra thin oxide layers [54 55 ], e mpirica l parameters are required for this approximation e g group velocity of electrons leaving the oxide layer which ideally should be obtained from the transmission probability solution Another method for solving the tunneling process is the transfer matrix method [56 ~ 58]. Any barrier shape is suitable for transfer matrix method and there is no need for other empiric al parameters Transfer matrix method is an ideal candidate for advanced MOSFETs with ultra thin oxide layer around 1nm. To apply this approach the tunneling barrier is separated into many small rectangular batters and assume s the finite quantum well is restricted in the region [ 0, L ]. The potential is zero at z <0 or z >L If we divide the region into N (N>>1) segments, the modulation potential m ay be considered as a constant in each part. Thus, the plane wave functions can be expressed as ()() ()(),0, () ,, (1,2,,),0,jjikzikz ikzLikzL ikzjdkzjd jjcecez zcecezL cecejNzL (3.7 ) where 22yk E k k 22()()j jyjkEVzkAz ( jzjd ). According to the continuity of the wave function and the corresponding derivatives at z =0 and z =L 1 1 11cos()sin() sin()cos() cos()sin() () sin()cos()NN NN NN N jkdikd cc ik k kdkd cc kk kdikd cc Mj ikk kdkd cc kk 3.8

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38 w here ) cos( ) sin( )sin( ) cos( ) (1 1d k k k d k k ik d k i d k jMj j j j j j j j Eq. 3.8 reduce s to a simpler form: c c c c m m m m c c c c22 21 12 11 3.9 Noting that there are only transmission waves in the absence of reflect ed waves when zL that is c =0, we obtain 22 11 12 21 22 21 12 11m m m m m m m m c c 3.10 Thus, the transmission coefficient is given by [59] 22 11122122 12211122()111 cmmmm TER cmmmm 3.1 1 We assumed here that the transmission probability depends only on the momentum which is vertical to the interface. Furthermore, the lifetime of an nth subband state is derived by [60], 01() 2/[()]nnn z n nnCTE mEEzdz (3.12) w here Ec( z ) is the edge of the conduction band and zn is the classical turning point for the nth sub state. Combining Eq. 3.5 to Eq. 3.12 and the tunneling current can be given by a sum of the tunneling current c ontributions from n subbands ,2,4 ,2,4()nn G n nnNN Jq (3.13) wher e ,2 nN and ,4 nN are the n th subband inve rsion charge density for 2 and 4 valley,

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39 respectively, and ,2 n and ,4 n are the corresponding lifetime of t he nth subband. Quantum Mechanical Model for p -Channel MOSFETs In this work, the strain induced Silicon subband energy level change valence band warpin g and band to band repopulation among the top three valence subbands is calculated by the k p method because: 1) this numerical solution is around the gamma point where only a very small set of wave vectors are require d ; 2) it is based on Luttinger Hamiltonian which deal s with band structures precisely. T he tight banding method and pseudopotential method have to treat the strained silicon band structure as a much more sophist icated system. Based on the theory of Luttinger [20], the valence band structure of strained Silicon is express ed by a 6 6 Hamiltonian in the envelope -function space. In the inversion layer for n type Silicon holes are restricted in a quantum well which i s formed by the oxide and Silicon interface and substrate surface potential and it is very similar as electron for n -channel MOSFETs, in which a two dimensional treatment is required. The charge density and subband energy levels are calculated also by a se lf -consistent solution of the coupled Schrdinger s and Poissons equations. Based on the effective mass approximation, the nth subband energy level En and the corresponding eigenfunctions n are given by the time independent Schrdinger equation for a given electrostatic potential VH(x) Luttinger()()(),HnnnHqVxxEx (3.14) where LuttingerH is the Luttinger Ham iltonian which determines the band shift and repopulation between subbands. For a MOSFET in the z -direction, ) ( z VH is calculated from the total charge density 2 2()[()()],Hd Sidq VzpzNz dx (3.15)

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40 whe re () nz and ()aNz neglected due to strong inversion which is opposite with the case in Eq. 3.6 for nchannel MOSFETs Because the split -off energy (0.044eV) is much small er than the band gap for Silicon (1.12eV) all valenc e bands can be described by six subbands without considering the influences from conduction bands [61]. Using the basis of the angular momentums, six subbands considering the spin effect can be expressed as |3/2,3/2 > |3/2,1/2>, |3/2, 1/2>, |3/2, 3/2>, |1/2,1/2>, and |1/2, 1/2>, where the total angular momentum and the angular momentum for a specific axis are represented by the first and the second number, respectively T he corresponding Hamiltonian for the top six bands with spin effect i.e., heavy -hole bands (HH), light hole bands (LH), and split -off bands (SO) is expressed as [62] 1 02 2 3 02 2 3 02 2 1 02 2 13 220 2 2 31 220 2 2 PQSR SR SPQRRS RPQSSQ RSPQRS SQSRP RSQSP (3.16) w here 2 222 1 0,, ,, (), 2kk kk k xyzPPPQQQ RRRSSS Pkkk m

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41 2 222 2 0 2 22 23 0 2 3 0(2), 2 3()2,(3.17) 2 23(), 2 ( ), (2), 2 3 (), 2 (),k xyz k xy xy k xyz vxxyyzz xxyyzz xxyy xy zxyzQkkk m R kkikk m S kikk m Pa b Q Rbid Sdi where the wave vector k is interpreted as a differential operator i ; ij is the symmetric strain tensor; 1 2 and 3 are the Luttinger parameters; av, b and d are deformation potentials; the split -off energy which is 44meV T he Luttinger constant s and deformation potentials of Si licon and Ge minium are listed in Table 3 1. Tabl e 3 1. Luttinger -Kohn parameters, deformation potentials and split -off energy for Si and Ge. 1 2 3 av (eV) b (eV) d (eV) (eV) Si 4.22 0.39 1.44 2.46 2.58 1 4. 3 0.044 Ge 13 .4 4.24 5.69 1.24 2.9 5.3 0.296 Fig. 3 5 shows the 3D equal energy surface of Silicon top two valence bands with no stress, 1GPa biaxial tensi le stress and 1 GPa longitudinal com pressive stress obtained by the 66 Luttinger Hamiltonian [8]. The top ba nd is the most important subband in which most holes occupied due to the lowest energy level close to the oxide/substrate interface. It is shown in Fig.

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42 3 5, both biaxial and uniaixal stress decreases the effective mass along the channel direction. However the out of -plane effective mass change is much smaller compared with the in plane conductivity effective mass change for all different kind of stresses. Further study for band to -band repopulation is necessary to fully understand the average out of -plan e effective mass modification impact on the gate direct tunneling leakage current change. Fig. 3 6 plots the cha rge density in the top three bands versus stress on (100) wafer at 1V gate bias. Also listed in Fig. 3 6 is the out -of -plane effective mass at t he gamma point for the three top sub band s : 0.29 0m (0.27 0m ), 0.20 0m (0.22 0m ), and 0.24 0m (0.2 3 0m ) respectively for b iaxial ( u niaxial) stress on (100) wafers The out -of -plane masses in the top three subband s are point for about 500MPa of stress. However, the average out of -plane effective mass increases with the applied compression due to the charge density increase in the top band as shown in Fig. 3 6. This out -of -plan e effective mass change will increase the tunneling barrier height for holes and decrease the corresponding gate direct tunneling leakage current. With the electron charge density obtained from the k p method, t he lifetime of an nth subband state in the i nversion layer is given by ,() 1 2/[]nn n nVnTE mEEdz (3 .18 ) where Ev is the top of the valence band The tunneling current can be readily obtained as a sum of the tunneli ng current contributions of the n subbands which is similar as Eq. 3.13. The simulated change of gate current is compared with the experimental data in Fig. 3 7 which showing a good agreement. Deformation potential av describes the shi ft in the energy levels while b and d indicating the splitting between the subbands. Values of av, b and d used are 2.46

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43 Figure 3 5. Unstressed, biaxial stressed, and uniaxial stressed Silicon constant surface at 25meV below valence band. [63], 2.58 [64], and 14.3, respectively The values chosen for av and b are commonly used [ 65] and similar values provide good fits to the strain-induced MOSFET threshold voltage shif t [66]. The modeled results primarily depend on b and d and are only we a kly affect ed by av. The value of d used in this work is larger than reported elsewhere [65] and is needed to fit the magnitude of the tunneling current decrease for compressive uniaxial stress ( d has no e ffect on the modeled biaxial stress). Q ualitative A nalysis of Tunneling Current Change A qualitative schematic of the direct electron or hole tunneling process and subband splitting for n -channel and p -channel MOSFET are shown in Fig. 3 8, where EC, EV, and EF are the silicon conduction band edge, valence band edge, and Fermi energy level, respectively. E

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44 0 100 200 300 0.0 3.0x10126.0x10129.0x1012 Split Off Band Bottom Band Charge Density (cm-2)Stress (MPa)E 0.24m00.20m0 0.29m0 KTop Band Biaxial Tension(c)0 100 200 300 0.0 3.0x10126.0x10129.0x1012 Split Off Band Bottom BandCharge Density (cm-2)E 0.24m00.20m0 0.29m0 K(b) Top Band Biaxial Compression 0 100 200 300 0.0 4.0x10128.0x10121.2x1013 Split Off Band Bottom Band Top Band Charge Density (cm-2)E 0.23m00.22m0 0.27m0 K Uniaxial Compression(a) Figure 3 6. Charge density versus applied stress for the top, bottom, and split off bands for three applied stress es (a) uniaxial compression, (b) biaxial compression, and (c) biaxial tension. T h e inset shows the simplified hole valence band structure for out -of -plane direction with the corresponding effective mass.

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45 0 50 100 150 200 250 300 -0.06 -0.04 -0.02 0.00 0.02 0.04 Biaxial Tension Biaxial Compression Uniaxial Compression Model J/J0Stress (MPa) Figure 3 7. The relative change of the tunneling currents versus applied uniaxial compression, biaxial compression, and biaxial tension, respectively. Dots a re experimental data and lines are physical model. and E2 4 valley, and and are the corresponding tunneling barriers at the oxide/substrate interface for n -channel MOSFETs ETop and EBottom are the energy levels of the top and bottom band in the quantized invers ion layer for p -channel MOSFETs B,Top and B,Bottom is the tunneling barrier for the holes from the top band and bo ttom band, respectively. Black (white) dots represent electrons (holes) in which n umber of the dots represents the population density of c arriers. Since the subband splitting is large for strong inversion situation nearly all the electrons and holes occupy the ground state for the different valley, i.e., E and E (ETop and EBottom) for n (p) -channel MOSFETs as shown in Fig. 3 8. Strain a lters the subband energy levels and hence the gate tunneling process. For example, tensile stresses increase the electron population in the 2 valley and increase barrier height with tensile stress, as shown in Fig. 3 8 (a), both of which increase n. Simi larly, in Fig. 3 8 (b),

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46 compressive stresses increase the hole tunneling barrier height and corresponding life time. According to Eq. 3.1 due to the increase of n, the gate leakage current is observed to decrease for the types of stresses adopted by the industry, i.e. tensile and compressive stress for n and pchannel MOSFETs, respectively. From the band structures for bulk silicon, we can further understand the strain altered gate leakage. The conduction band is comprised of six degenerate valleys ( 6) with the equal energy as shown in Fig. 2 2 (a). Stress es longitudinal to the <110> channel or effective vertical electrical field removes the degeneracy between the four in-plane valleys ( 4) and the two out of -plane valleys ( 2) due to the energy splitting, as shown in Fig. 2 2 (b). The lower energy of 2 valleys and larger effective mass (0.98m0) in Fig 3 8 (a) both decrease the gate leakage current for n channel MOSFETs. For holes, the valence -band structure of silicon is much more complex than the c onduction-band. For unstrained silicon at room temperature, most holes occupy the top two bands. The unstrained constant energy surfaces (E=25meV) for the top two bands are shown in Fig. 2 2 (a). It is observed that the out -of -plane effective mass of the t op band is smaller than that of the bottom band for the biaxial tensile stress while the opposite results for uniaxial compressive stress as see in Fig. 2 2 (b) and (c). This results in stress altered gate leakage current for p -channel MOSFETs to increase for biaxial tensile stress but to decrease for uniaxial compressive stress. Leakage Current Change in Accumulation Regime for n -Channel MOSFETs Strain induced changes in the gate tunneling current can reduce the leakage current for performance enhancing uniaxial strain on polysilicon gate n -channel MOSFETs [38,39,67] Since the tunneling probability depend on the effective mass, the strain dependence of the gate tunneling current can also provide an estimate for the change in the out of -plane effective mass, which is of technological importance since it determines whether the mobility enhancement is

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47 E 2EFECEV Poly -gate Oxide Si -channel 4 B 2 B E 4 Unstrained Tensile Strained 2E 4E (a) 0.98m0 0.19m0 increaseRepopulation 42 2 B EBottom ETopEFECEV BTop Poly -gate Oxide Si -channel BBottom Unstrained Compressive Strained Top Bottom (b) TopE BottomE 0.27m00.22m0 increase Repopulation BTop Figure 3 8 Schematic band diagram and s ubband splitting diagrams for direct carrier tunneling process in (a) n channel MOSFETs and (b) p -channel MOSFETs, res pectively. Black (white) dots represent electrons (holes). Number of the dots represents the population density of carriers.

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48 maintained or lost at high vertical field. The strain effect and 2D inversion layer confinement sub -band splitting are additive for uniaxial stress, in which mobility enhancement maintained at high vertical fields, but subtractive for biaxial stress, in which mobility enhancement lost in the inversion layer [8,19] Recently, strain -induced changes in the gate tunneling current for pch annel MOSFETs in inversion has been measured [38]. However, the tunneling current for n channel MOSFETs in a ccumulation is not well characterized. The leakage current from gates for the erase mode of electrically erasable programmable read only memories (E PROMs) [21] a nd the gate leakage current occurring in memory cells [22,23] make the understanding and model ing of the tunneling process in the accumulation layer increasingly important. In this chapter, we also experimentally and theoretically investigate the strain -induced leakage current change for n channel MOSFETs in both accumulation and inversion for externally applied uniaxial tensile stress for polysilicon gate, using a four point bending apparatus and self -consistent solution to Schrdinger and Po isson equation and Transfer Matrix method mentioned in the above section A qualitative schematic of the direct electron tunneling process for a n -channel MOSFET is shown i n Fig. 3 9 for electron tunneling from the gate, Fig. 3 9 (a), and electron tunnelin g from the substrate, Fig.1 (b), where CE VE and FE are the silicon conduction band edge, valence band edge, and Fermi energy level, respectively. 2E and 4 E are the energy level s for the 2 and 4 valley, and 2 B and 4 B are the tunneling barriers for the 2 and 4 valleys As qualitatively illustrated in Fig. 3 9 (b), quantization results in a redistribution of the carrie r density close to the interface, and only the discrete bound states are considered for 2DEG However, the situation is much complicat ed in the accumulation situation [45]. Electrons are not only quantized but also wave functions spread as traveling waves forming a quasi -bound state close to the interface [60]. In accumulation electrons are divided into the discrete subbands and

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49 a continuous energy region It is shown a s a shaded region in Fig. 3 9 (a). However, the direct tunneling current from the extended region is approximately only related to the highest quantized energy level, EnMAX, which is still restricted in the substrate surface potential well and the F ermi e nergy level in the silicon [52, 53, 60]. The value of EnMAX depends on how many quantiz ed subbands are included in the model [68]. Since EF is essentially independent of the applied uniaxial stress [38, 39], only the strain-effect on the bounded states ne ed to be considered for the leakage current change with stress since electrons in the extended region contribute nothing to the leakage current change in accumulation. It should be noticed that the bounded states in polysilicon are different from that in s ingle crystal silicon due to the crystal grain boundaries. Each polysilicon grain can be treated as a perfect single crys tal structure, surrounded by a grain boundary. Thus, each grain can be assumed as a three dimension well which is conductive as an ohm ic contact. The size of grains is approximately around 100 nm which is much bigger than the typical dimension of the tunneling structure we investigated [69]. Here, a perfect crystal structured and heavily doped polysi licon gate with (100) surface is assum ed for simplicity [70]. As mentioned before, t here are three major mechanisms for direct tunneling in MOSFETs ECB tunneling process dominates in the accumulation regime for p -channel MOSFETs and in both bias polarities for n -channel MOSFETs as shown in Fi g. 3 9 [71]. In all these ECB cases, small 3.15eV barrier for electrons can be directly tunneled easily. In contrast the gate leakage of the inverted p-channel MOSFET s devices is dominated by HVB in the low bias range [54]. In order to distinguish the tunneling current in experiments for different carriers and major mechanisms, carrier separation measurement for n -channel MOSFET is used as shown before in Fig. 3 2 T he experimental data (dots) and physical model (lines) for a normalized change in the

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50 (a) (b) F igure 3 9. Schematic band diagram for direct electron tunneling in a n n channel MOSFET for accumulation layer (a) and inversion layer (b), respectively.

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51 gate tunneling currents versus the applied uniaxial tensile stress is shown for accumulation layer in Fig. 3 10 (a) and for inversion layer in Fig. 3 10 (b). For these n channel MOSFETs, it is o bserved that the gate tunneling current linearly decreases with longitudinal tensile stress for both inversion layer and accumulation layer. Furthermore, the normalized change is smaller with increase of the gate voltage. Similar trends have been reported for n -channel MOSFETs in inversion [39, 67]. Without stress, t he silicon conduction bands are six -fold degenerate d along the axes. Due to the breaking of symmetry induced by uniaxial stress, the degeneracy of -valleys separated as 2 and 4 valleys. The uniaxial longitudinal tensile stress decreases the 2 valley and increases the 4 valley. Decreases in the gate tunneling current for l ongitudinal tensile stresses primarily result from electron repopulation into subbands with larger out -of -plane effectiv e mass [39]. However, the magnitude of the normalized leakage current change in the accumulation layer is about twice higher than that in the inversion layer. To understand this result, Fig. 3 11 (a) shows the lowest subband energy level in the 2 and 4 v alley versus the applied uniaxial stress for both inversion and accumulation layer, where the zero of energy is taken to be the bottom of the conduction band close to the oxide/substrate interface Due to the strong confinement in inversion layer as shown is Fig. 3 9(b), E 2 and E 4 in the inversion layer are higher than that in the accumulation layer. Meanwhile, the normalized lowest subband energy level change with the applied uniaxial stress in 2 and 4 valley for inversion and accumulation layer are plotted in Fig. 3 1 1 (b). It is obvious ly shown that valleys with a weak confinement in the accumulation layer will shift more in energy relative to valleys with a strong confinement in the inversion layer. Since the tunneling probability from bound states depend exponential ly on the electrons

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52 (a) (b) F igure 3 10. The normalized the electron tunneling current change versus the applied uniaxial longitudinal tensile stress on (1 0 0) wafer for accumulation layer (a) and inversion layer (b), respectively.

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53 (a) (b) F igure 3 11. (a) The lowest subband energy level in uniaxial stress for both inversion and accumulation layer, where the zero of energy is taken to be the bottom of the conduction band; (b) The normalized lowest subband energy level change with the applied uniaxial stress in and accumulation layer.

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54 energy perpendicular to the barrier, this different energy shift for the accumulation layer and inversion layer will result in the different leakage cur rent change as is shown in Fig. 3 10. To see the different confinement more clearly, the concentration of electrons is calculated as a functi on of the distance from the Si/S iO2 interface for the particular case of an n channel MOSFET in accumulation layer, Fig. 3 12 (a), and in inversion layer, Fig. 3 12 (b), respectively. It is seen that electrons are confined in a much wider region in the accumulation layer. Although the band bending is much smaller in the accumulation layer, the peak of the 2 valley electron distribution is not much lower than that in the inversion layer due to the Fermi energy approaching the conduction band edge in the accumulation layer, which is shown in Fig. 3 9(a). Longitudinal tensile stress increases the electron pop ulation in the high out of plane mass. T h e inset of Fig. 3 12 shows the surface charge density change for the 2 and 4 valleys with the applied longitudinal tensile stress. The value of the stress in the (a)

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55 (b) Figure 3 12. Sp atial distributions of the electron density in the n -channel MOSFETs for accumulation layer (a) and inversion layer (b), respectively. T h e inset shows the surface c harge density change for the 2 and with the applied uniaxial tensile stress from compressive 3 GPa to tensile 3 GPa i.e. 3000~3000MPa simulation is varied from compressive 3 GPa to tensile 3 GPa In contrast, the electron concentration in the 2 valleys decreases with applied longitudinal compressive stress which increases the electro n tunneling current for n -channel MOSFETs [39]. All results are consistent with the 2 valleys have a larger out of plane conductivity mass (0.98m0). Summary In summary, a simple picture is provided for physic al underlying of the strain effect on change of gate tunneling current for n and p-channel MOSFETs in inversion regime. It is shown that a model based on strain altered out of -plane effective mass, energy splitting, and subband repopulation reveals the key mechanism of gate tunneling process in inversi on regime for both n channel and p -channel MOSFETs. F or stresses that produce favorable hole mobility versus

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56 electric field ( biaxial and uniaxial compression ), it is observed that the gate tunneling current is reduced by stress which results in the top sub band having a larger out -of -plane effective mass. The same is true for strain induced e lectron mobility enhancement. For instance, n channel MOSFET s benefited from stresses such as longitudinal tensile stress which decrease s the direct electron tunneling c urrent and increases the electron mobility Meanwhile due to the weak confinement, the normalized leakage current change in accumulation layer is highe r than that in inversion layer.

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57 CHAPTER 4 LOW TEMPERATURE EFFECT ON MOBI LITY IN STRAINED MOSFETS Although large mobility enhancement has been experimentally achieved for electrons and holes, further studies of mobility at low temperature can provide useful physical insight on the surface roughness scattering mechanism, which are responsible for the strain enhanced mobility at high vertical electrical fiel d [20, 61, 72~74]. So far, lots of works have been done for the temperature effect on n-channel strained MO SFETs for electron mob ility [24, 25], and large surface roughness scattering reduction is expected even for small tensile stresses (500MPa) [26~29, 75]. Cammarata predict that the compre ssive stress has much less effect on the surface roughness compared with tensile stress for thin films [76]. However, it is not clear how compressive stress could change the interface roughness in the heterostructure of MOSFETs. Low temperature hole mobility measurement is a good candidate to investigate the compressive stress induced surface roughness change in MOSF ETs and also physical mechanism for strain induced hole mobility enhancement. Meanwhile, low temperature electron mobility measurement with the tensile stress could furt her confirm the previous conclusion about the reduced surface roughness scattering for n-channel MOSFETs. In this chapter, controlled external uniaxial mechanical stress is applied to MOSFETs to measure the strain altered hole and electron mobility versus temperature. A kp method and a modified surface roughness scattering model are used to simulate the low temperature mobility as low as 77K. Boltzmann equation is used for the calculation of the mobility in inversion layers. The xx component of the mobility tensor, ij can be written as [20] 2 20 00 22 0 ,, ,,1(4.1) 4E xx x Bsx KE KEKE qE ddEKEfEfE E kTnK K

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58 w here svvNn and nv is the car rier population of the subband v ()(,)v xK is the relaxation time and 1 0{1exp[()/()]}FBfEEkT Based on the results from Chapter 3, momentum relaxation rate is still needed for mobility calculation. For simplicity, the hole mobility also could be expressed by the carrier scattering rate and conductivity effective mass, ,// pe m ( 4.2 ) where ,// pm is the conductivity effective mass in the channel direction, and is the average carrier momentum relaxation time, which is evaluated by considering phonon scattering and surface roughness scattering for high effective f ield here. Scattering Mechanism For ideal periodic lattice, electron or holes may be transport freely without considering the boundary condition. However, due to the fluctuation of temperature or any other outside deviations, like impurities and crystal de fects, scattering s are generated Usually, phonon scattering, impurity scattering and surface roughness scattering are considered for MO S FETs mobility simulation as shown in Fig. 4 1 [ 77]. It is indicated that the total mobility increase with lower tempera tures. Meanwhile, phonon scattering and surface roughness scattering are dominant at high electrical field regime for room temperature. With the decrease of the temperature, surface roughness sc attering becomes the dominant scattering mechanism and it is c learly shown in low temperature case, especially below 77K [77] Charged and neutral impurity scattering or coulomb scattering is neglected here since only high transverse electric field (0.6MV/cm) is considered Due to strong field from inversion charge layer, screening effect eliminated the electrical potential generated from ionized dopants.

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59 Figure 4 1. Schematic diagram of effective field dependence of t otal mobility in inversion layer. Total s cattering mechanism including the phonon, surface roughn ess and coulomb scattering. Coulomb scattering is neglected for high effective field [77]. Phonon Scattering It is know that there are two types of phonon scattering, i.e. intravalley phonon scattering and intervalley phonon scattering. According to the selection rules for the phonon scattering in Silicon, intravalley phonon scattering usually only allowed for acoustic phonons with lower energy but forbidden for optical phonons. The momentum relaxation time for deformation potential scattering by intrava lley acoustic phonons is given by 2 22 1 ()Beff vv v ac lkT FEK u (4.3 ) where eff equal s 7.18eV and 9eV as the effective acoustic deformation potential of the v al ence band and conduction band, respectively. v is the two dimensional DOS of subband v which is defined as

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60 2 (0) 2 0 (,)1(,) ()[] (2)vv v v KEKE EEEd E K (4.4 ) The form factor F is given by 2 ()() 00 0()()W v vFdzzz (4.5 ) The momentum relaxation time for intervalley phonon scattering is given by 2 0 0() 1[()] 1 11 () 1[()]22op op vv op op v op opDK fEK FEK n fEK (4. 6 ) where the average deformation potential (DK)op equal s 13.24eV and 19.2eV for valence band and conduction band, respectively. Surface Roughness Scattering Surface roughness scattering is associated with roughness at the interface between the oxide an d the Silicon substrate where is not microscopically smooth for free transport These random variations in the interface cause a n electrical potential change that scatter s the electrons or holes. The effect of the surface roughness is usually included in the potential and is expressed by a Taylor series expansion of the scattering element Using the Andos model [ 7 8 ] for surface roughness scattering, the momentum relaxation time is given as 2 2 3 01 () 2d ij SRm Mqd K (4. 7 ) where the s cattering matrix element Mij is given by 22 2 2 2 22()()()() 1 2n ij i jL MqezEzzdz qL (4. 8 ) where is a average surface roughness potential height and L is a cor relation length. [20].

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61 Low Temperature Effect on Mobility in Strained p -channel MOSFETs E xperiments are performed on industrial (100)/<110> oriented Si long channel ( W/L = 10 /10 ) MOSFET s with boron doped p + poly -Si licon gate electrodes, 5 1017cm3 n ty pe well doping, and 1.2 nm nitrided SiO2 gate insulators. Mechanical longitudinal compressive stress along the <110> direction is introduced into the MOSFET using a 4 -point bending setup [38] that was custom built to be used in a Desert Cryogenics variable temperature probe station The electrical data is measured with a Keithley 4200 DC semiconductor characterization system at temperatures ranging from 300K to 87K. T he experimentally measured and theoretically calculated hole mobility versus temperature fo r unstrained, 20MPa, 45MPa, and 60MPa compressive stressed p -channel MOSFETs are shown in Fig. 4 2 Mobility is extracted from the drain current at low drain voltage ( VD S=50mV ) in linear region [79], It is observed in the inset of Fig. 4 2 that strain enha ncement increases at lower temperatures. This result contrasts with present n channel MOSFET experimental results in which mobility enhancement decreases [24~26] or remains constant at lower temperatures [75]. Although decreased interface surface roughness scattering rate [27, 28] for n -channel MOSFETs may explain the electron case for tensile stress, increase of hole mobility enhancement at lower temperatures reveals different mechanisms for compressive stressed p channel MOSFETs At room temperature, the dominant mechanism responsible for hole mobility enhancement is expected to be reduced conductivity effective mass for small compressive stress. The modeling shows that, for stresses below 500MPa, the stress enhanced mobility results mainly from band warping. The band warping creates strong in -plane energy anisotropy in the top band with a light hole like mass occurring along the <110> channel direction near the band edge.

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62 50 100 150 200 250 300 350 0 100 200 300 400 500 50 100 150 200 250 300 0.05 0.10 0.15 0.20 0.25 0.30 20MPa 45MPa 60MPa ( -(0MPa))/ (0MPa)Temperature (K) 0MPa 20MPa 45MPa 60MPa ( c m2/(V S)Temperature (K) Figure 4 2. Measured (dots) and calculated (lines) hole mobility and normalized mobility enhancement (Inset) for (100) Si along the <110> channel direction as a function of temperature for unstressed, 20MPa, 45MPa, and 60MPa longitudinal compressive stressed p channel MOSFETs. L ower temperatures decrease the Fermi energy level from 272meV at 300K to 304meV at 87K, in which the zero energy level is the valence band edge at the interface. The top subband edge also decreases from 273meV to 283meV. Both Fermi energy level decrease and Fermi distribution step s harpen at lower temperatures concentrat e more hoes at states with lower subband energy levels, which has a light hole conductivity mass along the channel direction for longitudinal compressive stress. Confined 2D 25meV and 150meV energy contour s are plott ed in Fig. 4 3 (a) near the top band edge on (100) plane for unstressed, 60MPa, and 1GPa uniaxial stressed Si licon The energy contour is composed of four wings of which two longitudinal wings contribute larger conductivity effective mass and two transvers e wings contribute smaller mass.

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63 The total conductivity effective mass is the average contribution by the four wings. T he conductivity mass along the <110> direction for 25meV is smaller than that for 150meV for uniaxial compressive stressed Si licon; this trend is more clear for the 1GPa uniaxial compressive stressed Silicon compared with the 60MPa case. The normalized conductivity effective mas s reduction is shown in Fig. 4 3 (b), it is clearly shown that the effective mass decrease more at lower temperatu res with the same stresses. Meanwhile, the effective mass reduction is almost the same as the mobility enhancement a s shown in the inset of Fig. 42 Scattering rate change is very important for low temperature electron mobility, but, it is shown that most enhancement for low temperature hole mobility are from band warping effects. O ptical phonon scattering dominates at room temperature and both the heavy hole (HH) like band and the light hole (LH) -like band contribute to the carrier transport for unstrai ned Silicon. Strain induced band warping mixes these bands and redistribute the hole population. Based on the Boltzmann equation [ 78], we calculat ed the phononlimited mobility as a function of temperature for unstressed (triangle dots) and 60MPa longitudi nal compressive stressed (square dots) p -channel MOSFETs as shown in Fig. 4 4 As expected, Phonon limited mobility increases exponentially with lowering temperatures. Moreover, phonon limited mobility is enhanced by the stress, and this enhancement is inc reasing with lowing temperature which is similar with the total mobility. Meanwhile, surface roughness scattering starts to dominate at low temperature because more holes will be confined in the lower subband which exhibits lower surface roughness limited mobility. As shown in Fig. 4 5, the relative contribution by surface roughness limited mobility for p -channel MOSFETs with 60MPa longitudinal compressive stress increases with lowering temperatures. At 87K, surface roughness start dominates for strained p -channel MOSFETs.

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64 (a) 50100150200250300 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 20MPa 45MPa 60MPa (m*-m*(0MPa))/m*(0MPa)Temperature (K) (b) Figure 4-3. (a) Energy contours at 25meV (red line) and 150meV (blue line) to the top band edge on the (100) surface with zero (solid line), 0.06GPa (dotted line), and 1GPa (dashed line) uniaxial compressive stress along the <110> direction. (b) Normalized conductivity effective mass re duction as a function of temperature for 20MPa, 45MPa, and 60MPa longitudinal compressive stressed p-channel MOSFETs.

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65 Using Andos model [78], the surface roughness s ca ttering matrix element is given by Eq. 4.8, where =0.4nm is the average surface roughness potential height, L =2.6nm is the correlation length, and n usually is between 3/2 and 3, [20, 28] we choose n=5/2 here. The scattering matrix element is inversely pr oportional to the effective width of the inversion layer as given by 21 ()()ijW zzdz (4.9 ). The momentum relaxation time of holes is determined by t he density -of -states effective mass and the effective width of the inversion layer. However, the strain induced decrease of the effective width of the inversion layer in the top band is compensated by the strain induced reduction of the densityof -states e ffective mass. Consequently, for a strained p -channel MOSFET, repopulation almost does not change the surface roughness scattering rate [74]. Th erefore, the applied stress effectively enhances surface roughness limited mobility mainly by decreasing the effective mass for the HH band as shown in Fig. 4 6. Both strain enhanced phonon and surface roughness limited mobility result in increased total mobility enhancement at low temperature as shown in Fig. 4 2. This result is consistent with biaxial stress offe ring little hole mobility enhancement at small stress and requiring ~2GPa to alter the scattering rates and enhance mobility [9]. However, the physics for uniaxial stress is much different than biaxial stressed Silicon which has much less band warping indu ced effective mass change and little gain observed in the hole mobility at low temperatures. To further verify the above conclusion, we calculate d the phonon and surface roughness scattering rates as a function of stress in p -channel MOSFET inversion layer at 300K and 87K as shown in Fig. 4 7 (a) and (b), respectively As expected, the phonon scattering rate decreases

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66 50 100 150 200 250 300 0 200 400 600 800 1000 Unstrainedph ( cm-2/V Sec )Temperature (K)Uniaxial Compression 60MPa F igure 4 4 Calculated phononlimited mobility for (100) Si along the <110> channel direction as a function of t emperature for unstressed (triangle dots) and 60MPa longitudinal uniaxial compressive stressed (square dots) p channel MOSFETs. 50 100 150 200 250 300 0.0 0.2 0.4 0.6 0.8 1.0 Phonon ScatteringMobility Contribution Temperature (K)Uniaxial Compression 60MPa Surface Roughness Scattering Figure 4 5 Relative contribution by phononlimited mobility and surface roughness limited mobility for a (100)/<110> Si p-channel MOSFET with 60MPa longitudinal uniaxial compressive stress.

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67 50 100 150 200 250 300 0 2000 4000 UnstrainedSR ( cm-2/V Sec )Temperature (K)Uniaxial Compression 60MPa F igure 4 6 Calculated surface roughness limited mobility for (100) Si along the <110> channel direction as a function of temperature f or unstressed (triangle dots) and 60MPa longitudinal uniaxial compressive stressed (square dots) p -channel MOSFETs. 0 1 2 3 0.0 5.0x10121.0x10131.5x10132.0x10132.5x1013 Optical Phonon Acoustic Phonon Surface roughnessScattering Rate ( Sec -1 )Uniaxial Compressive Stress (GPa)T=300K (a)

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68 0 1 2 3 0.0 8.0x10111.6x10122.4x10123.2x10124.0x1012 Scattering Rate ( Sec -1 )Uniaxial Compressive Stress (GPa) Optical Phonon Acoustic Phonon Surface roughnessT=87K (b) Figure 4 7 Calculated optical phonon, acoustic phonon, and surface roughness scattering rate for p -channel MOSFETs along the <110> channel direction as a function of longitudinal compressive stress at (a) 300K and (b) 87K, respectively. dramatically when lowering temperatures. D ue to the decrease of kinetic energy of holes in t he inversion layer, the surface roughness scattering rate increases at lower temperatures [20]. In modeling the experimental data, we do not observe any significant strainaltered phonon or surface roughness scattering rates at the small stresses (500MPa) in this work. Optical phonon scattering is dominant at 300K and Surface roughness scattering is crucial at 87K. Acoustic phonon scattering is not sensitive as optical phonon scattering and surface roughness scattering. Low Temperature Effect on Mobility in Strained n -channel MOSFETs Based on p revious empirical model [ 80], dotted line in Fig 4 8 shows the mobility change with temperature for unstrained and 60MPa stressed MOSFETs. The model matches experimental data well for unstrained devices, but the s imulated mobility enhancement for stressed device is much lower than experimental data, especially at low temperature. The only available assumption for the present experimental data is reduced surface roughness scattering in

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69 strained Si [27]. For p -channe l MOSFETs, the mobility enhancement could be explained by the band warping. However, there is not much effective mass change either by band warping or repopulation between subbands for n -channel MOSFETs and the mechanism of mobility change could only be ex pl ained by scattering rate change [27]. 50 100 150 200 250 300 300 400 500 600 700 800 900 SB/OP=5/1 0MPa 60MPa Mobility ( cm2/s.V )Temperature (K)The model based on Hadjisavvsa's work [28] (SB/OP=1/3) the model without scattering rate change Figure 4 8 Measured (dots) and calculated (lines) electron mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal com pressive stressed n -channel MOSFETs. There are mainly two different theoretical models about scattering rate decreasing with the applied stresses. Bonnos model claimed that roughness amplitude decreases with the applied biaxial tensile stress [ 81]. The su rface roughness s cattering matrix element is given by Eq. 4. 8 For high electrical field and high inversion charge density, scattering matrix element could be simplified as 2 2()ijMq L (4. 10)

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70 According to Bonnos model, scattering rate decreases with the reduction of roughness amplitude, correspondingly, the mobility should be enhanced with the applied biaxial tensile stress for n -chan nel MOSFETs. Meanwhile according to Eq. 4. 10, correlation length should be another important factor for surface roughness scattering rate change with the applied stresses. However, L is considered as a constant value in Bonnos model. In real situation L could be either increase or decrease with tensile stresses. Based on th e experimental results, L has a liner relationship with for most material s [82 ], in which, decrease of roughness amplitude means shorter correlation length. For Silicon, the relation between L and stresses is still unknown. Correspondingly, Bonnos model could not explain the relation between surface roughness scattering rate and the applied stresses precisely. The validation of the model still needs further experimental verification. Recently, another quantum mechanical electron moti lity model without any empirical parameters show ed that reduced surface scattering is the dominant mechanism for strain enhancement electron mobility [28, 83]. According to this model, surface roughness sc attering matrix element is ()ijMqikVjk (4. 11) where V is the potential change due to defects and it could represent by defrefVVV (4.1 2 ) Vdef is a potential with scattering centers and Vref is a re ference potential. Although the concept of this model is different from Bonnos mode l, the feature size of roughness amplitude is similar which is around 0.3nm. Potential change with the applied stresses depends on the type of scattering centers or defects. OP (oxide protrusion) represents an extra O atom in Silicon substrate which provide an attractive potential due to the presence of extra

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71 50 100 150 200 250 300 0 1x1032x1033x1034x1035x1036x1037x103 Unstrainedph (cm-2/V Sec)Temperature (K)Uniaxial Compression 60MPa F igure 4 9. Calculated phononlimited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal tensile str essed n channel MOSFETs. 50 100 150 200 250 300 0.0 5.0x1021.0x1031.5x103 UnstrainedSR (cm-2/V Sec)Uniaxial Compression 60MPa Temperature (K) F igure 4 10. Calculated surface roughness limited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal tensile stressed n channel MOSFETs.

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72 oxygen ion. On the other hand, SB (suboxide bond) represents an Si -Si bond in the oxide layer, and repulsive potential is created by oxygen missing here [28, 83]. As shown in Fig. 4 8, atomic scale roughness was incorporated in empirical m odel in the dashed line. However, there is still discrepancy between simulation and experiments. It is reasonable to change the defects ratio assumptions. Here, we assume that SB/OP=5/1 and the solid line in Fig. 48 indicated that the surface roughness sc attering change with stress is critical to reproduce strain induced mobility enhancement for n -channel MOSFETs. Fig. 4 9 and 410 show the phononlimited and surface roughness -limited mobility change with temperature in unstrained and strained MOSFETs, res pectively. Similar trend as p -channel MOSFETs is shown here for electrons due to the surface roughness instead of band warping. Summary With applied compressive uniaxial stress, lower temperatures cause more holes to populate states at the band edge whic h have a lighter hole conductivity mass in the channel direction and hence results in the larger stress induced mobility gain The experimental data and modeling suggests that small stresses do not significantly alter the hole scattering rates. It is sho wn that the surface roughness scattering becomes dominant at low temperature, and compressive stress induced surface roughness limited hole mobility enhancement mainly due to the smaller effective mass along the channel direction for p -cha nnel MOSFETs. How ever, increase of electron surface roughness limited mobility by tensile stress is contributed mos tly from scattering rate change for n -channel MOSFETs

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73 CHAPTER 5 EFFECTIVE WORK FUNCT ION CHANGE WITH THE APPLIED STR ESS One of the biggest issues in modern CMOS technology is the gate dielectric. As the gate oxide became scaling down to the ultra thin oxide region the direct tunneling current increases [5]. Furthermore, quantum mechanical effects and the polysilicon depletion effect start dominate as the SiO2 thickness decreasing. Due to these limitations of SiO2, alternative gate dielectrics with higher dielectric constant are necessary to decrease the effective oxide thickness, and increase the physical thickness of the insulator [84~87] During past decade s, numerous candidates has been used as the high k dielectric layer [88], e.g., rare earth [89], Zirconium oxide [90~92], and Hafnium oxide [93,94]. Due to the capability with the present processing technology, Hafnium based highk dielectric materials became more and more dominant. Besides HfO2, HfSiON [95], HfAlON [96], and HfTaON [97] has also been widely used recently. Polysilicon depletion effect is a nother limitation for current CMOS technology. This effect becomes more critical as the effective diel ectric thickness is decreased. Threshold voltage is strongly affected by the Fermi level pinning effect due to polysilicon gate induced interface states [98]. Replacing polysilicon gate with metal gates could be able to eliminate this issue [99~101], and l ots of metal gate materials has been studied [102], such as FUSI [103], Al [104], Au [105], ScN [106], and TiSiN [107]. In 2007, MOSFETs with TiN gate have been productively achieved in the industry in the 45nm technology node [108]. Although several studies have been reported about the strain induced contact resistance reduction [109], strain effect on the properties of highk dielectrics [110~113], and strain effect on radiation [114] for high k/metal gate devices, there is much less understanding about electrical parameter compatibility of high k/metal gate devices and strained Silicon technology

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74 In this chapter, strain induced effec tive work function (EWF) change for high k/metal gate devices will be discussed. Effective Work Function Change with the External Mechanical Stress The metal work function choice is a very important consideration because the threshold voltage and the performance of MOSFETs are determined by metal work function [115, 116] Work function represents the minimum energy for electr ons to escape from the solid surface, and it is normally measured by Kelvin probe force microscopy (KFM) [117]. However, t he measurement of EWF is a challenging task because the overall work functions for gate stacks are different from traditional metal wo rk function for metal only [118~122], and EWF also depends on process conditions EWF is modified by Lanthanum or Aluminum Doping [123~127] thermal treatment [128~131], and capping layers [132]. In this section, we investigated WEF tuning with the applied stress. Figure 5 1 Terraced oxide wafer with different silicon oxide thickness from 1 to 4 nm. Highk and metal gate are deposited with the same thickness.

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75 Experimental Setup A capacitance based method [133] with a single wedding structured wafer was used to extract the EWF as shown in Fig. 51. The thermally grown SiO2 are etched into rings with various thicknesses of 1, 2, 3, 4 nm. Highk dielectrics, HfSiO, and metal gate, TiN, are deposited with the same thickness on the terraced SiO2 [134]. C a pacitance voltage (CV ) curves were measured with an HP 4284 semiconductor characterization system at 100 kHz, and the flat band voltage, Vfb, and effective oxide thickness, EOT, values were simulated from the North Carolina State University (NCSU) CVC pro gram [135]. The EWF for gate stack is extracted from the work function difference between gate and substrate ms by equation int 011 ()()h tox f fbms ox h o h ox h oQQ V Txxdxxxdx (5.1) where Qf is the fixed charge at the silicon oxide and substrate interface, Qint is the interface charges which is depends on the effective electrical field and electrically communicable with the substrate, Tox is the EOT, ox is the permittivity of silicon oxide, h is the permittivity of high k dielectrics, h is the charge density inside the highk dielectrics, o is the permittivity of silicon oxide, o is the charge density inside th e silicon oxide. Fig. 5 2 (a) shows C -V measurement results for a single terraced wafer with different silicon oxide thickness. Fig. 5 2 (b) shows the flat band voltage as a linear function of EOT which indicated that the charges inside the HfSiO and SiO2 are much less than interface charges. Otherwise, there is a parabolic relation between flat band voltage and EOT. As shown in Fig. 5 2 (b), a linear function is simplified from Eq. 5.1, which is used for the EFW extraction in this work.

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76 (a) (b) Figure 5 2. (a) Measured c apacitance voltage curve results for a single terraced wafer with different silicon oxide thickness (b) T he flat band voltage as a function of EOT A good linear relation is show for these devices.

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77 (a) (b) Figure 5 3 Experimental setup of four point bending jig for uniaxal stresses (a) schematic diagram (b) actually jig from side view. External stresses are applied by a four point bending jig for uniaxial stresses as shown in Fig. 5 3. Applied external stresses are calculated by 3 2 2 2 a L a y t Ea x (5.2)

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78 where is the stress, E is Youngs modulus t is the sample thickness y is the vertical displacement a and L are rod spacing Biaxial stresses are applied by two rings with different sizes. Experimental Results Fig. 5 4 shows the extracted EWF for TiN gate stack with uniaxial stress (a), and biax ial stress (b). WF_D21, WF_D22, WF_D23 represent the TiN gate thickness as 10, 5, and 2nm, respectively. It is observed that the EWF linearly deceases with the applied stresses regardless the stress type and the thickness of TiN metal gate. This trend is m ore clearly shown in Fig. 5 5 as the normalized EWF change with uniaxial stress (a) and biaxial stress (b). Strain induces more interface defects and they are contributing to the capacitance measurement with response to the applied gate voltage [136,137]. It is shown in Fig. 5 4 that the WEF is smaller for the capacitors with thinner metal gate. The WEF shift could reach as large as 0.21eV which is shown in Tab. 5 1. This EWF tuning results are consistent with previous published results [138,139]. With the metal gate thickness decrease, more tensile stress are induced in the metal gate and substrate where more defects are generate d in the interface due to the dangling bond activation energy decrease Stresses either increase or decrease the dangling bond angel and this bond angel change induces more interface defects correspondingly To further verify this assumption, interface state measurement under different stresses is required. Table 5 1. EWF and its change with different metal gate thickness as 10, 5, and 2 nm, respectively. TiN 10 nm 5 nm 2 nm EWF (eV) 4.5983 4.4200 4.3862 0.0000 0.1783 0.2121

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79 (a) (b) Figure 5 4 Extracted EWF for TiN gate stack with uniaxial stress (a), and biaxial stress (b). WF _D21, WF_D22, WF_D23 represent the TiN gate thickness as 10, 5, and 2nm, respectively.

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80 (a) (b) Figure 5 5 Normalized EWF change for TiN gate stack with uniaxial stress (a), and biaxial stress (b). WF_D21, WF_D22, WF_D23 represent the TiN gate thickness as 10, 5, and 2nm, respectively.

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81 Effective Work Function Change with the Process Introduced Stress E xternal mechanical stresses are too small to induce enough interface state change for measurement Process induced stre ss for different metal gate thickness is a good option for this measurement. The highk metal gate device for the interface state measurement is shown in Fig.5 6. Different metal gate thickness was deposited on the Silicon substrate and the inevitable inte rfacial layer thickness is 1nm. Polysilicon gate is added after TiN gate formed. Larger process induced stress is expected for MOSFETs with thinner metal gate thickness. Figure 5 6. Schematic diagram of high k/metal gate MOSFETs with different metal gat e thickness. Higher stress in expected for MOSFETs with thinner metal gate. IL is the interfacial layer between the Silicon and HfSiO. Bowing Technique for Stress Measurement Bowing technique provide s a useful tool to characterize the surface stress on the wafer [140,141]. Fig. 5 7 show the bowing measurement set up where R is the calculated radius of curvature, ts is the substrate thickness, tf is the film thickness, and rsc is the scan distance. The average surface stress is given by Stoneys equation 211 61s ft E tR (5. 3 ) where is the average film stress, E /1 -v is biaxial elastic modulus of substrate, ts is the subst rate thickness tf is the film thickness. There are several assumptions for Eq. 5.2: 1) tf << ts << wafer; 2) substrate is elastically isotropic and flat; 3) uniform film and substrate thickness and

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82 Figure 5-7. Diagram for Bowing measurement, where R is the calculated radius of curvature, ts is the substrate thickness, tf is the film thickness, and rsc is the scan distance. temperature; 4) maximum wafer de flection is less then half of ts. Stress measurement results are shown in Fig. 5-8. It is indicated that the stress va lue is always increases with the decrease of the metal gate thickness. However, the stress magn itude, even the stress type strongly depends on the thermal treatment. For the film as deposited, the stress is compression and it is larger for MOSFETs with thinner TiN. Whereas, tension is introduced for film af ter annealing and the stress is larger for low temperature proce ss. Although, stress type and value are process dependent, higher stress always corresponding to MOFETs with thinner TiN. These provide a clear picture about how stress will change the inte rface states for different metal gate thickness. Charge Pumping for Interface States Measurement Charge pumping method using a MOSFET precise ly measure the selective recombination of carriers trapped in the interface states [142]. Measurement setup is shown in Fig. 5-9 for an nchannel MOSFET. Gate pulse is applied to the gate and source and drain are tied together with a

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83 small reverse bias applied. The silicon surface switches from stron g accumulation to strong inversion with a large gate pulse. A schematic illustration of the two level charge pumping method for an n-channel MOSFET is shown in Fig. 5 10. In this case, base level of the gate pulse is increased and height of the gate pulse is constant. The upper curve shows the charge pumping current change with the base gate voltage level. In strong accumulation region, all gate voltage is lower than the flat band voltage, and there is no holes came out for recombination. In weak accumulati on region, the holes captured in the interface traps start recombine electrons from channel and the charge pumping current is increased. In depletion region, the recombination process saturated and the charge pumping current reaches the maximum value. In w eak inversion region, the interface traps can not be fully filled with holes and the recombination process is not completed as it does Figure 5 8. Measured average stress on the wafer for MOSFETs without thermal treatment, 600C annealing, and 1035C ann ealing, respectively. It is clearly shown that the stress always increase for MOSFETs wi th thinner metal gate thickness.

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84 Figure 5-9. Schematics of charge pumping measurement setup for an n-channel MOSFET [143]. Figure 5-10. Schematics illustration of the two level charge pumping method for an n-channel MOSFET. In this situation, base level of th e gate pulse is increas ed and the substrate switches from strong accumulation to str ong inversion. The upper curve shows the charge pumping current change with the base gate voltage level.

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85 in depletion region. In strong inversion region, there is no holes captured in the interface traps and the charge pumping current is zero. Figure 5 11. Measured Charge pumping current on an n -channel MOSFET with 2, 5, and 10 nm TiN gate electrode. Figure 5 12. Schematic diagram for stress induced generation of donor -like interface traps between the interfacial layer and the Silicon substrate. Fig. 5 11 shows the measured charge pumping current on an n-channel MOSFET wi th 2, 5 and 10 nm TiN gate electrode. It is indicated that the interface traps increase for MOSFETs with thinner metal gate electrode which corresponding to larger stress on the wafer surface as shown

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86 in Fig. 5 8. This result confirmed the measurement of t he EWF of capacitors in Fig. 5 4 and 5 5. Meanwhile, the negative shift of the peak of charge pumping current implies the capture of more positive charges, and the stress generates more donor like interface states [144] as shown in Fig. 5 12. Summary Effe ctive work function change is studied for both external mechanical applied stress and process induced high stress Stress within the TiN surface strongly depends on the thermal treatment for process induced stress. Bowing technique and charge pumping method are used for stress and interface state measurement, respectively. It is indicated that the EWF always decrease with the applied stress and the interface s tates increase induced donor -like charge generation is the dominant physical mechanism.

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87 CHAPTER 6 SUMMARY AND SUGGESTIONS ABOU T FUTURE WORKS Summary Low power device will be benefited from gate direct tunneling leakage current reduction. Drain current increase depends on the mobility enhancement. Effective work function tuning will greatly improve the performance of high k/metal gate MOSFETs. In this work several physical models are provided for the strain effect on the performance of Silicon MOSFETs, and different electrical characterizations is used to investigate leakage current, mobility, and work function. S train effect on the chang e of gate tunneling current for n and p-channel MOSFETs in both inversion and accumulation regime s are characterized A physical model based on out -of -plane effective mass, energy splitting, and repopulation indicate s t he insight of gate tunneling process for both n -channel and p -channel MOSFETs. Biaxial and uniaxial compression not only improve the hole mobility, but also reduce the gate tunneling leakage current for p -channel MOSFETs. The same benefit is applicable to n channel MOSFETs due to the repopulation induced out -of plane effective mass change. The relative l eakage curr ent change in accumulation regime is lag e r than that in inversion layer due to the weak confinement and less energy splitting Temperature depen dent mobility measurement provides a clear picture of conductivity effective mass and scattering mechanism. Banding warping induced effective mass is much more important of p -channel MOSFETs. Whereas, the repopulation between subbands induced effective mas s reduction is critical for n -channel MOSFETs. With applied compressive stress, lower temperatures concentrate more holes to the states near the band edge where the band warping effect is most dominant Phonon scattering is dominant at 300K and the surfac e roughness scattering starts to be critical beyond 87K, and will be the dominant scattering

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88 mechanism close to 33K. Both experimental data and modeling suggests that much larger mobility enhancement will be observed for large stress under low temperature Work function selection has been the most difficult challenge for high k/metal gate devices for the most recent 32nm technology node. Gate last formulation introduces large stress in the metal gate. Not only mobility is enhanced tremendously, but also a novel effective work function tuning candidate is provided. Both tension and compression effectively reduced the work function for n-channel MOSFETs which is confirmed by external mechanical stress and process induced large biaxial stress. Suggestions abou t Future Works Silicon -oninsulator (SOI) transistor architecture has been considered a promising candidate to greatly improve the performance of the traditional MOSFETs. The basic idea of SOI is to fabricate traditional transistor structure on a very thin Silicon layer which is separated from the bulk substrate by a thick insulator layer, in which, parasitic capacitance is dramatically decreased and the maximum working frequency will be increased correspondingly. Meanwhile, to more effectively control the inversion charge for short channel devices FinFETs have been widely investigated theoretically and experimentally recently SOI and FinFET devices have been shown to enhance the device performance and decrease the power c onsumption. Combination of these two novel device structures are very promising to be used in the future 22nm CMOS technology node Besides strain effects on traditional Silicon MOSFETs strained SOI may add the strain induced contact resistance reduction with their control advantages. Me anwhile how multi interfaces with insulator should affect surface roughness scattering more than the traditional Silicon MOSFETs, which made surface roughness change with the applied stress more important At low temperature, we could obtain more detailed information Comparing with SOI, mobility

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89 change of FinFETs should provide a clear picture of surface roughness scattering mechanism due to its multi gate controlled transport channels and two simultaneously applied electrical field which will also provid e more information at low temperature.

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90 LIST OF REFERENCES [1 ] G. Moore, Progress in Digital Integrated Electronics, IEDM Tech. Digest pp. 11 13, 1975. [2 ] E.J. Nowak, Maintaining the Benefits of CMOS Scaling when Scaling Bogs Down IBM J.Res.Develop. vol. 46, no. 2 3, pp. 169 186, 2002. [3 ] S. Thompson, P. Packan, and M. Bohr, MOS Scaling: Transistor Challenges for the 21st Century, Intel Technology Journal vol. 3, pp. 3 5, 1998. [4 ] T. Skotnicki, J. A. Hutchby, TsuJae King, H. S. P. Wong, and F. Boeuf The e nd of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance, IEEE Circuits & Devices vol. 21, pp. 16-26, 2005. [5 ] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, High -k Metal Gate St ack and Its MOSFET Characteristics IEEE Electron Device Lett. vol. 25, no. 6, pp. 408410, 2004. [6 ] H. -S. P. Wong, Beyond the conventional transistor, IBM journal of Research and Development vol. 46, pp. 133168, 2002. [7 ] R. C. Jaeger, Introduction to micr oelectronic fabrication 2nd ed. Prentice Hall, pp. 1 2, 2002. [8 ] S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, Uniaxial -process -induced strainedSi: Extending the CMOS Roadmap IEEE Trans. Electron Devices vol. 53, no. 5, pp. 10101020, 2006. [9 ] K. Ri m, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carmthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, Fabrication and mobility characteristics of ultra thin strained Si directly on insulator (SSDOI) MOSFETs IEDM Tech. Dig. pp. 311314, 2003. [10] M. Glicksman, "Magnetoresistance of Germanium -Silicon Alloys," Physical Review vol. 100, pp. 1146 1147, 1955. [11] E. Kasper, H. J. Herzog, and H. Kibbel, "A One Dimensi onal SiGe Superlattice Grown by UHV Epitaxy," Appl.Phys. vol. 8, pp. 199 201, 1975. [12] G. C. Osbourn, "StrainedLayer Superlattices from Lattice Mismatched Materials," J. Appl. Phys. vol. 53, pp. 1586 1589, 1982 [13] H. Daembkes, H. J. Herzog, H. Jorke, H. Kibbel, and E. Kasper, "The n Channel SiGe/Si ModulationDoped Field Effect Transistor," IEEE Trans.Electron Devices vol. 33, pp. 633 638, 1986.

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91 [14] Scott E. Thompson, Member, IEEE, Mark Armstrong, Chis Auth, Steve Cea, Robert Chau, Glenn Glass, Thomas Hoff man, Jason Klaus, Zhiyong Ma, Brian Mcintyre, Anand Murthy, Borna Obradovic, Lucian Shifren, Sam Sivakumar, Sunit Tyagi, Tahir Ghani, Kaizad Mistry, Member, IEEE, Mark Bohr, Fellow, IEEE, and Youssef El -Mansy, Fellow, IEEE, "A Logic Nanotechnology Featuring Strained-Silicon," IEEE Electron Device Letters vol. 25, No. 4, pp. 191193, 2004. [15] S.E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, Key differences for process induc ed uniaxial vs. substrate -induced biaxial stressed Si and Ge channel MOSFETs, IEDM Tech. Dig. pp. 221224, 2004. [16] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus K. Kuhn, Z. Y. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shiften, B. Tufts, S. Tyagi, M. Bohr, and Y. El -Mansy, "A 90-nm logic technology featuring strained -silicon," IEEE Transactions on E lectron Devices vol. 51, pp. 17901797, 2004. [17] V. Chan, R. Rengarajan, N. Rovedo, W. Jin, T. Hook, P. Nguyen, J. Chen, E. Nowak, X. Chen, D. Lea, A. Chakravarti, V. Ku, S. Yang, A. Steegen, C. Baiocco, P. Shafer, H. Ng, S. Huang, and C. Wann High spee d 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering, IEDM Tech. Dig. pp. 77 80, 2003. [18] P. R. Chidambaram, B.A. Smith, L.H Hall, H. Bu, S. Chakravarthi, Y. Kim, A.V. Samoilov, A.T. Kim, P.J. Jones, R.B. Ir win, M.J Kim, A.L.P Rotondaro, C.F Machala, and D.T. Grider 35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS, Proc. Symp. VLSI Technology pp. 48 49 2004. [19] S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Cha u, G. Glass, T. Hoffman, J. Klaus, Ma Zhiyong, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, Y. El -Mansy, A 90 -nm Logic Technology Featuring Strained -Silicon, IEEE Electron Device Lett. vol. 25, pp. 191199, 2004. [20] M. V. Fischetti, Z. Ren, P. M. Solomon, M. Yang a nd K. Rim, Six -band k.p calculation of the hole mobility in silicon inversion layers:dependence on surface orientation, strain, and silicon thickness, J. Appl. Phys. vol. 94, pp. 10791095, 2003. [21] R. B. Sethi, U. S. Kim, I. Johnson, P. Cacharelis, and M. Manley, Electron barrier height change and its influence on EEPROM cell IEEE Electron Device Lett. vol. 13, pp. 244246, 1992. [22] S. Banerjee, D. Coleman, Jr., W. Richardson, and A. Sha h, Leakage Mechanisms in the Trench Transistor DRAM Cell, IEEE Trans. Electron Devices vol. 35, pp. 108116, 1988.

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92 [23] M. Herrmann and A. Schenk, Field and hightemperature dependence of the long term charge loss in erasable programmable read only memories : Measurements and Modeling J. Appl. Phys. vol. 77, pp. 45224540, 1995. [24] F. Lime, F. Andrieu, J. Derix, G. Ghibaudo, F. Buf, and T. Skotnicki Low temperature characterization of effective mobility in uniaxially and biaxially strained nMOSFET Solid -State Electronics vol. 50 pp. 644649 2006. [25] M. N. Tsai, T. C. Chang, P. T. Liu, O. Cheng, and C. T. Huang, Temperature Effects of n MOSFET Devices with Uniaxial Mechanical Strains, Electrochemical and Soild-State Lett. vol. 9 pp. 2 76 278, 2006. [26] S. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, Comparative study of phononlimited mobility of two -dimensional electrons in strained and unstrained Si metal oxide semiconductor field -effect transistors J. Appl. Phys. vol. 80, pp. 15671577, 199 6. [27] M. V. Fischetti, F. Gamiz, and W. Hansch, On the enhanced electron mobility in strained -silicon inversion layers J. Appl. Phys. vol. 92, pp.73207324, 2002. [28] G. Hadjisavvas, L. Tsetseris, and S. T. Pantelides The Origin of Electron Mobility Enhancement in Strained MOSFETs, IEEE Electron Device Lett. vol. 28, pp. 1 0181020, 2007. [29] K. Uchida, T. Krishnamohan, K. C. Saraswat, and Y. Nishi Physical Mechanisms of Electron Mobility Enhancement in Uniaxial Stressed MOSFETs and Impact of Uniaxial Stress En gineering in Ballistic Regime, IEDM Tech. Dig. pp. 135138, 2005. [30] P.R. Chidambaram et al., Fundamental of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing, IEEE Trans Electron Devices vol. 53, pp. 944 964, 2006. [31] P. Y. Yu, and M. Cardona, Fundamentals of semiconductors Springer, New York, NY, 2001. [32] D.K. Nayak, and S.K. Chun, Low -field hole mobility of strained Si on (100) Si1 xGex substrate, Appl. Phys. Lett., vol. 64, pp. 2514 2516, 1994. [33] S. E. Thompson et al. A 90nm Logic Technology Futuring 50nm Strained Silicon Channel Transistors, 7 layers of Cu Intercinnects, Low k ILD, and 1 mm2 SRAM Cell, IEDM Tech. Dig. pp. 61 64, 2002. [34] A. Shimizu et al. Local Mechanical -Stress Control (LMC): A New Technique for CMOS -Performance Enhancement, IEDM Tech. Dig. pp. 19.4.1 4, 2001. [35] S. Ito and et al. Mechanical Stress Effect of Etch Stop Nitride and its Impact on Deep Submicron Transistor Design, IEDM Tech. Dig. pp. 247250, 2000.

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93 [36] H. Cheng Liang H. Soleimani, G. Grula, N. D. Arora, and D. Antoniadis, Isolation process dependence of channel mobility in thin-film SOI devices, IEEE Electron Device Letters vol. 17, no. 6, pp. 291293, 1996. [37] C. K. Maiti, L. K. Bera, S. S. Dey, D. K. Nayak, and N. B. Chakrabarti, Hole Mobility Enhancement in Strained -Si p -MOSFETs Under High Vertical Field, Solid -State Electron. vol. 41, no. 12, pp. 18631869, 1997. [38] X. Yang, J. Lim, G. Sun, K. Wu, T. Nishida, and S. E. Thompson, Strain induced changes in the gate tunneling currents in p-channel metal oxide semiconductor field effect transistors, Appl. Phys. Let., vol. 88, pp. 052108, 2006. [39] J. Lim, X. Yang, T. Nishida, and S. E. Thompson, Measurement of conduction band deformation potential constants using gate direct tunneling current in n type metal oxide semiconductor field effect transistors under mechanical stress, Appl. Phys. Lett. vol. 89, pp. 073509, 2006. [40] Ying Shi, T. P. Ma, S. Prasad, and S. Dhanda, Polarity dependent gate tunneling currents in dual -g ate CMOSFETs, IEEE Trans. Electron Devices vol. 45, no. 11, pp. 23552360, 1998. [41] Wen Chin Lee, and Chenming Hu, Modeling CMOS tunneling currents through ultrathin gate oxide dueto conduction and valence band electron and hole tunneling, IEEE Trans. Electron Devices vol. 48, no. 7, pp. 13661373, 2001. [42] Wei Zhao, Alan Seabaugh, Vance Adams, Dejan Jovanovic, and BrianWinstead, Opposing Dependence of the Electron and Hole Gate Currents in SOI MOSFETs Under Uniaxial Strain, IEEE Electron Device Letters, vol. 26, no. 6, pp. 410412, 2005. [43] C. W. Leitz, M. T. Currie, M. L. Lee, and Z. -Y. Cheng, D. A. Antoniadis, and E. A. Fitzgerald, Hole mobility enhancements and alloy scattering limited mobility in tensile strained Si/SiGe surface channel metal oxide semiconductor field -effect transistors, J. Appl. Phys. vol. 92, no. 7, pp. 3745 3751, 2002. [44] F. Stern, Self Consistent Results for n Type Si Inversion layers, Phys. Rev. B vol. 15, pp. 48914899, 1972. [45] J. Sune, P. Olivo, and B. Ricco, Self -consisten t solution of the Poisson and Schrdinger equations in accumulated semiconductor -insulator interfaces J. Appl. Phys. vol. 70, pp. 337345, 1991. [46] I. Balslev, Influence of Uniaxial Stress on the Indirect Absorption Edge in Silicon and Germanium, Phys. R ev. vol. 143, pp. 636647, 1966. [47] M. M. Rieger, and P. Vogl, Electronic -band parameters in strained Si1xGex alloys on Si1yGey substrates, Phys. Rev. B vol. 48, pp. 1427614287, 1993.

PAGE 94

94 [48] H. Miyata, T. Yamada, and D. K. Ferry, Electron transport propertie s of a strained Si layer on a relaxed Si1 xGex substrate by Monte Carlo Simulation Appl. Phys. Lett. vol. 62, pp. 26612663, 1993. [49] K. Rim, J. Welser, J. Hoyt, and J. Gibbons, Enhanced hole mobilities in surface -channel strained Si p -MOSFETs, IEDM Tech Dig., pp. 517 520, 1995. [50] Z. A. Weinberg, Tunneling of electrons from Si into thermally grown SiO2, Solid -State Electron vol. 20, pp. 11, 1977. [51] O. Simonetti, T. Maurel, and M. Jourdain, Theoretical prediction of the dielectric spectrum of an antiferro electric liquid crystal J. Appl. Phys. vol. 92, pp. 449455, 2002. [52] L. F. Register, E. Rosenbaum and K. Yang, A nalytic model for direct tunneling current in polycrystalline silicon gate metal oxide semiconductor devices Appl. Phys. Lett. vol. 74, pp. 457459, 1999. [53] W. Z. Shangguan, X. Zhou, S. B. Chiah, G. H. See, and K. Chandreasekaran, Compact gate current model based on transfer -matrix method J. Appl. Phys. vol. 97, pp. 123709, 2005. [54] N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, Mode ling study of ultra thin gate oxides using direct tunneling current and capacitance voltage measurements in MOS devices, IEEE Trans. Electron Divices vol. 46, pp. 14641471, 1999. [55] Y. T. Hou, M. F. Li, Y. Jin, and W. H. Lai, Direct tunneling hole current s through ultrathin gate oxides in metal oxide semiconductor devices J. Appl. Phys. vol. 91, pp. 258264, 2002. [56] A. Matulis, F. M. Peeters, and P. Vasilopoulos, Wave -vector dependent tunneling through magnetic barriers Phys. Rev. Lett. vol. 72, pp. 15181521, 1994. [57] M. Buttiker, C apacitance, admittance, and rectification properties of small conductors J. Phys: Condens. Matter vol. 5, pp. 93619378,1993. [58] R. Clerc, A. Spinelli. G. Ghibaudo, and G. Pananakakis, Theory of direct tunneling current in m etal oxide semiconductor structures J. Appl. Phys. vol. 91, pp. 1400, 2002. [59] X. D. Yang, R. Z. Wang, Y. Guo, W. Yang, D. B. Yun, B. Wang, H. Yan, G iant magnetoresistance effect of two -dimensional electron gas systems in a periodically modulated magnetic field Phys. Rev. B vol. 70, pp. 115303115307, 2004. [60] F Rana, S Tiwari, and D. A. Buchanan Self -consistent modeling of accumulation layers and tunneling currents through very thin oxides Appl. Phys. Lett. vol. 69, pp. 11041106, 1996.

PAGE 95

95 [61] Y. Sun, S. E. Thompson, and T. Nishida, Physics of strain effects in semiconductors and metal -oxde -semiconductor -field -effect transistors, J. Appl. Phys. vol. 101, pp. 104503, 2007. [62] Y. P. Chao, and S. L. Chuang, Spin -orbit -coupling effects on the valence band structure of strained semiconductor quantum wells, Phys. Rev. B vol. 46, pp. 4110, 1992. [63] C. G. Van de Walle, B and lineups and deformation potentials in the model -solid theory Phys. Rev. B vol. 39, pp. 18711883, 1989. [64] M. Cardona and E. H. Pollak, E nergyBand Structure of Germanium and Silicon: The kp ,method Phys. Rev. vol. 142, pp. 530-, 1966. [65] M. V. Fischetti and S. E. Laux, Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys, J. Appl. Phys. vol. 8 0, pp. 2234, 1996. [66] J. Lim, S.E. Thompson, and J. G. Fossum C omparison of threshold -voltage shifts for uniaxial and biaxial tensile -stressed n MOSFETs IEEE Electron Device Lett. vol. 25, pp. 731733, 2004. [67] W. Zhao, A. Seabaugh, V. Adams, D. Jovanovic, and B. Winstead, Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain, IEEE Electron Device Lett. vol. 26, pp. 410412, 2005. [68] J. A. Lopez -Villanueva, I. Melchor, F. Gamiz, J. Banqueri, and J. A. Jimenez Tejada, A model for the quantized accumulation layer in metal insulator -semiconductor structures Soild -State Electronics vol. 38, pp. 203210, 1995. [69] A. S. Spinelli, A. Pacelli, and A. L. Lacaita, Polysilicon quantization effects on the electrical properties of MOS transistors, Trans. Electron Devices vol. 47, pp. 23662371, 2000. [70] H. Iwata, T. Matsuda and T. Ohzone, Quantum -Mechanical Simulation of Gate Tunneling Current in Accumulated n-Channel Metal Oxide -Semiconductor Devices with n+ Polysilicon,Gates J pn. J. Appl. Phys. vol. 41, pp. 50945097, 2002. [71] Wen Chin Lee and Chenming Hu, M odeling CMOS tunneling currents through ultrathin gate oxide dueto conduction and valence -band electron and hole tunneling Trans. On Electron Devices vol. 48, pp. 1366, 2001. [72] C. Beer, T. Whall, E. Parker, D. Leadley, B. D. Jaeger, G. Nicholas, P. Zimmerman, M. Meuris, S. Szostak, G. Gluszko, and L. Lukasiak, Low temperature mobility in hafnium oxide gated germanium p -channel metal -oxide -semiconductor field effect transist ors, Appl. Phys. Lett, vol. 91 pp. 263512, 2007. [73] D. R. Leadley, M. J. Kearney, A. I. Horrell, H. Fischer, L. Risch, E. H. C. Parker, and T. E. Whall Analysis of hole mobility and strain in a Si/Si0.5Ge0.5/Si metal oxide semiconductor field effect tran sistor, Semicond. Sci. Technol. vol. 17 pp. 708, 200 2.

PAGE 96

96 [74] G. Sun, Y. Sun, T. Nishida, and S. E. Thompson, Hole mobility in silicon inversion layers: Stress and surface orientation, J. Appl. Phys. vol. 102, pp. 084501, 2007. [75] N. Sugii, and K. Washio, Low Temperature Electrical Characteristics of Strained -Si MOSFETs, Jpn. J. Appl. Phys ., vol. 42, pp. 1924, 2003. [76] C. Cammarata, and K. Sieradzki, Effects of surface stress on the elastic moduli of thin films and superlattices, Phys. Rev. Lett. vol. 62, pp. 2005, 1989. [77] Takagi, S.; Toriumi, A.; Iwase, M.; Tango, H. On the universality of inversion layer mobility in Si MOSFET's: Part I -effects of substrate impurity concentration, Trans. On Electron Devices vol. 41, pp. 23572362, 1994. [78] T. Ando, A. B. Fowler and F. Stern, Electronic properties of two-dimensional systems, Rev. Mod. Phys. vol. 54 pp. 437672, 1982. [79] J. R. Hauser Extraction of experimental mobility data for MOS devices, IEEE Trans. On Electron Device, vol. 4 3 pp. 1981, 199 6 [80] J. B. Roldan F. Gamiz, P. Cartujo -Cassinello, P. Cartujo, J. E. Carceller, and A. Roldan, Strained Si on Si/sub 1 -x/Ge/sub x/ MOSFET mobility model, Trans. On Electron Devices vol. 50, pp. 14081411, 2003. [81] O. Bonno, S. Barraud, D. Mariolle, and F. Andrieu. Effect of strain on the electron effective mobility in biaxially strained silicon inversion layers: An experimental and theoretical analysis via atomic force microscopy measurements and Kubo Greenwood mobility calculations, J. Appl. Phys. vol. 103, pp. 063715, 2008. [82] G. Rasigni, F. Varnier, M. Rasigni, and J. P. Palmari, Autocovariance functions, root mean -square roughness height, and autocovariance length for rough deposits of copper, silver, and gold, Phys. Rev. B vol. 25, pp. 23152323, 1982. [83] M. H. Evans, X. G. Zhang, J. D. Joannopoulos, and S. T. Pantelides, First -Principles Mobility Calculations and Atomic -Scale Interface Roughness in Nanoscale Structures, Phys. Rev. Lett. vol. 95, pp. 106802, 2005. [84] J. Robertson, High dielectric constant gate oxides f or metal oxide Si transistors, Rep. Prog. Phys. vol. 69, pp. 327 396, 2006. [85] B. Cheng, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. C. Stork, Z. Yu, P. M. Zeitzoff, and J. C. S. Woo, The impact of highelectrodes on sub100 nm MOSFETs, IEEE Trans. Electron Devices vol. 46, no. 7, pp. 15371544, 1999. [86] A. A. Demkov, O. Sharia, J. K. Lee, Theoretical analysis of high k dielectric gate stacks, Microelectronic Engineering, vol. 84, pp. 2032 2034, 2007.

PAGE 97

97 [87] E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn -Schmidt, C. D'Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L. A. Ragnarsson, P. Ronsheim, K. Rim, R. J. Fle ming, A. Mocuta, A. Ajmera, Ultrathin high -K gate stacks for advanced CMOS devices, IEDM Tech. Dig. pp. 20.1.1 20.1.4, 2001. [88] H. J. Cho, C. S. Kang, S. Rhee, Y. H. Kim, R. Choi, C. Y. Kang, C. Choi, M. Abkar, High k dielectrics and MOSFET characteristics, IEDM Tech. Dig. pp. 4.4.1 4.4.4, 2003. [89] A. E. Lim, R. T. Lee, G. S. Samudra, D. Kwong, and Y. C. Yeo, Novel Rare Earth Dielectric Interlayers for Wide NMOS Work Function Tunability in Ni -FUSI Gates, IEEE Trans. Electron Devices vol. 55, no. 9, pp. 23702377, 2008. [90] G. Lucovsky, B. Rayner, Y. Zhang, J. Whitten, Experimental determination of band offset energies between Zr silicate alloy dielectrics and crystalline Si substrates by XAS, XPS and AES and ab initio theory: a new approach to the compositional dependence of direct tunneling currents, IEDM Tech. Dig. pp. 617620, 2002. [91] C. C. Fulton, G. Lucovsky, and R. J. Nemanich, Electronic properties of the Zr ZrO2 SiO2 Si(100) gate stack structure, J. Appl. Phys. vol. 99, pp. 063708, 2006. [92] G. Giorgi, A. Korkin, K. Yamashita, Zirconium and hafnium oxide interfa ce with silicon: Computational study of stress and strain effects, Computational Materials Science vol. 43, pp. 930937, 2008. [93] R. Choi, K. Onishi, C. S. Kang, S. Gopalan, R. Nieh, Y. H. Kim, J. H. Han, S. Krishnan, H. J. Cho, A. Shahriar, J. C. Lee, Fab rication of high quality ultra thin HfO2 gate dielectric MOSFETs using deuterium anneal, IEDM Tech. Dig. pp. 613616, 2002. [94] F. Rochette, M. Cass, M. Mouis, A. Haziot, T. Pioger, G. Ghibaudo, F. Boulanger, Piezoresistance effect of strained and unstrain ed fully -depleted silicon -oninsulator MOSFETs integrating a HfO2/TiN gate stack, Solid -State Electronics vol.53, pp. 392 396, 2009. [95] S. Inumiya, K. Sekine, S. Niwa, A. Kaneko, M. Sato, T. Watanabe, H. Fukui, Y. Kamata, M. Koyama, A. Nishiyama, M. Takayan agi, K. Eguchi, Y. Tsunashima, Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65 nm mode low power CMOS applications, Proc. Symp. VLSI Technology pp. 17 18, 2003. [96] R Y. Y. Chen, W. Y. Fu, C. F. Yeh, Electrical Characteristics of the HfAlON Gate Dielectric With Interfacial UV Ozone Oxide, IEEE Electron Device Lett. vol. 29, pp. 6062, 2008. [97] X. P. Wang, A. Eu Jin Lim, H. Y. Yu, M. F. Li, C. Ren, W. Y. Loh, C. X. Zhu, A. Chin, A. D. Trigg, Y. C. Yeo, S. Biesemans G. Q. Lo, and D. L. Kwong, A Comparative Study of HfTaON/SiO2 and HfON/SiO2 Gate Stacks With TaN Metal Gate for

PAGE 98

98 Advanced CMOS Applications, IEEE Trans. Electron Devices vol. 54, no. 2, pp. 284290, 2007. [98] C. Hobbs, L. Fonseca, V. Dhandapani, S Samave dam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcla, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White and P. Tobin, Fermi Level Pinning at the PolySi/Metal Oxide Interface, Proc. Symp. VLSI Technology pp. 9 10, 2003. [99] Y C. Yeo, Metal gate technology for nanoscale transistors material selection and process integration issues, thin solid film vol. 34 41, pp. 462463, 2004. [100] Y. C. Yeo, T. J. King, and C. M. Hu, Metal -dielectric band alignment and its implications for me tal gate complementary metal -oxide -semiconductor technology, J. Appl. Phys. vol. 92, no. 12, pp. 7266, 2002. [101] K. Shiraishi, Y. Akasaka, S. Miyazaki, T. Nakayama, T. Nakaoka, G. Nakamura, K. Torii, H. Furutou, A. Ohta, P. Ahmet, K. Ohmori, H. Watanabe, T. Chikyow, M. L. Green, Y. Nara, and K. Yamada, Universal theory of workfunctions at metal/Hf -based high k dielectrics interfaces Guiding principles for gate metal selection, IEIC Technical Report (Institute of Electronics, Information and Communication Engineers) pp. 2932, 2006. [102] W. Mnch, On the electric -dipole contribution to the valence -band offsets in semiconductor -oxide heterostructures Appl. Phys. Lett vol. 91, pp. 042117, 2007. [103] C. S. Park and B. J. Cho, Dopant Free FUSI PtxSi Metal Gate for High Work Function and Reduced Fermi Level Pinning, IEEE Electron Device Lett. vol. 26, no. 11, pp. 796798, 2005. [104] C. S. Park, B. J. Cho, and D. L. Kwong, MOS Characteristics of Substituted Al Gate on High k Dielectric IEEE Electron Device Lett. vol. 25, no. 11, pp. 725727, 2004. [105] W. Mnch, On the explanation of the barrier heights of InP Schottky contacts by metal induced gap states Appl. Phys. Lett., vol. 93, pp. 172118, 2008. [106] Chalker, Youngs modulus, Poissons ratio, and residual stress and strain in (111) -oriented scandium nitride thin films on silicon J. Appl. Phys., vol. 100, pp. 023514, 2006. [107] H. Luan, H. N. Alshareef, H. R. Harris, H. C. Wen, K. Choi, Y. Senzaki, P. Ma jhi, and B. H. Leed, Evaluation of titanium silicon nitride as gate electrodes for complementary metal -oxide semiconductor Appl. Phys. Lett, vol. 88, pp. 142113, 2006. [108] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Bueh ler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Heussner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T.

PAGE 99

99 Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, K. Zawadzki, A 45nm Logic Technology with High k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging, IEDM Tech. Dig. pp. 247250, 2007. [109] A. Yagishita, T. King, and J. Bokor, Schottky Barrier Height R eduction and Drive Current Improvement in Metal Source/Drain MOSFET with Strained Si Channel, Jpn. J. Appl. Phys. vol. 43, no. 4B, pp. 1713 1716, 2004. [110] L. Kima, J. Kim, D. Jung, J. Lee, Strain effect on dielectric property of SrTiO3 lattice: first princ iples study, Thin Solid Films vol. 475, pp 97 101, 2005. [111] S.K. Raya, R. Mahapatr, S. Maikap, A. Dhar, D. Bhattacharya, Je Hun Lee, Ultrathin HfO2 gate dielectrics on partially strain compensated SiGeC/Si heterostructure, Materials Science in Semiconduct or Processing, vol. 7, pp. 203 208, 2004. [112] S. Y. Son, Y. S. Choi, P. Kumar, H. W. Park, T. Nishida, R. K. Singh, and S. E. Thompson, Strain induced changes in gate leakage current and dielectric constant of nitrided Hf -silicate metal oxide semiconductor ca pacitors Appl. Phys. Lett vol. 93, pp. 153505, 2008. [113] C. Claeys, E. Simoen, S. Put, G. Giusi, F. Crupi, Impact strain engineering on gate stack quality and reliability Solid -State Electronics vol. 52, pp. 1115 1126, 2008. [114] H. Park, S. K. Dixit, Y. S. Choi, R. D. Schrimpf, D. M. Fleetwood, T. Nishida, and S. E. Thompson, Total Ionizing Dose Effects on Strained HfO2 -Based nMOSFETs IEEE Trans on Nuclear Science, Vol. 55, no. 6, pp. 29812985, 2008. [115] Y. C. Yeo, P. Ranade, T. J. King, and C. Hu Effe cts of High k Gate Dielectric Materials on Metal and Silicon Gate Work function IEEE Electron Device Lett. vol. 23, no. 6, pp. 342344, 2004. [116] H. Y. Yu, C. Ren, Y. Yeo, J. F. Kang, X. P. Wang, H. H. Ma, Ming Fu Li, D. S. H. Chan, and D. L. Kwong Fermi Pinning Induced Thermal Instability of Metal -Gate Work Functions IEEE Electron Device Lett. vol. 25, no. 5, pp. 337339, 2004. [117] T. Mizutani, T. Usunami, S. Kishimoto, and K. Maezawa, Measurement of Contact Potential of GaAs/AlGaAs Heterostructure Usin g Kelvin Probe Force Microscopy, J. Appl. Phys. vol. 38, pp. 767769, 1999. [118] W. Li, D. Y. Li, In situ measurements of simultaneous electronic behavior of Cu and Al induced by mechanical deformation, J. Appl. Phys. vol. 99, pp. 073502, 2006. [119] W. Li, Y. W ang, and D. Y. Li, Response of the electron work function to deformation and yielding behavior of copper under different stress states, phys. stat. sol. vol. 201, no. 9, pp. 2005 2012, 2004.

PAGE 100

100 [120] W. Li, D. Y. Li, Variations of work function and corrosion be haviors of deformed copper surfaces, Applied Surface Science, vol. 240, pp. 388 395, 2005. [121] S.V. Loskutov, Work function for the deformed metal surface, Surface Science, vol. 585, pp. 166 170, 2005. [122] A. Kiejna, V. V. Pogosov, Simple theory of elastically deformed metals: Surface energy, stress, and work function, Phys. Rev. B vol. 62, no. 15, pp. 10445, 2000. [123] X. P. Wang, A. Lim, H. Y. Yu, M. F. Li, C. Ren, W. Loh, C. X. Zhu, A. Chin, A. D. Trigg, Y. Yeo, S. Biesemans, G. Lo, and D. L. Kwong, Work Funct ion Tunability of Refractory Metal Nitrides by Lanthanum or Aluminum Doping for Advanced CMOS Devices, IEEE Trans. Electron Devices vol. 54, no. 11, pp. 28712877, 2007. [124] R. Singanamalla, H. Y. Yu, B. Van Daele, S. Kubicek, and K. De Meyer Effective Wor k -Function Modulation by Aluminum Ion Implantation for Metal Gate Technology (Poly -Si/TiN/SiO2) IEEE Electron Device Lett. vol. 28, no. 12, pp. 10891091, 2007. [125] K. Xiong, J. Robertson, G. Pourtois, J. Ptry, and M. Mller, Impact of incorporated Al on the TiN/HfO2 interface effective work function, J. Appl. Phys. vol. 104, pp. 074501, 2008. [126] A. E. Lim, R. T. Lee, G. S. Samudra, D. Kwong, and Y. C. Yeo, Modification of Molybdenum Gate Electrode Work Function via (La Al Induced) Dipole Effect at High k/SiO2 Interface IEEE Electron Device Lett. vol. 29, no. 8, pp. 848850, 2008. [127] X. P. Wang, Ming -Fu Li, C. Ren, X. F. Yu, C. Shen, H. H. Ma, Albert Chin, C. X. Zhu, Jiang Ning, M. B. Yu, and D. Kwong, Tuning Effective Metal Gate Work Function by a Nove l Gate Dielectric HfLaO for nMOSFETs IEEE Electron Device Lett. vol. 27, no. 1, pp. 31 33, 2006. [128] X G. Sjblom, J. Westlinder, and J. Olsson, Investigation of the Thermal Stability of Reactively Sputter Deposited TiN MOS Gate Electrodes, IEEE Trans. Electron Devices vol. 52, no. 10, pp. 23492352, 2005. [129] C. Ren, D. S. H. Chan, W. Y. Loh, S. Balakumar, A. Y. Du, C. H. Tung, G. Q. Lo, R. Kumar, N. Balasubramanian, and D. L. Kwong Work -Function Tuning of TaN by High Temperature Metal Intermixing Techniqu e for Gate -First CMOS Process IEEE Electron Device Lett. vol. 27, no. 6, pp. 811813, 2006. [130] K. Choi, T, P. Lysaght, H. Alshareef, C. Huffman, H. C. Wen, R. Harris, H. Luan, P. Y. Hung, C. Sparks, M. Cruz, K. Matthews, P. Majhi, B.H. Lee, Growth mechan ism of TiN film on dielectric films and the effects on the work function, thin solid film vol. 468, pp. 141144, 2005. [131] Y. Sugimoto, M. Kajiwara, K. Yamamoto, Y. Suehiro, D. Wang, and H. Nakashimaa, Effective work function modulation of TaN metal gate on HfO2 after postmetallization annealing, Appl. Phys. Lett, vol. 91, pp. 112105, 2007.

PAGE 101

101 [132] K. Choi, H. N. Alshareef, H. C. Wen, H. Harris, H. Luan, Y. Senzaki, P. Lysaght, P. Majhi, and B. H. Leef, Effective work function modification of atomic layer -deposit ed TaN film by capping layer, Appl. Phys. Lett, vol. 89 pp. 032113, 2006. [133] R. Jha, J. Gurganos, Y. H. Kim, R. Choi, J. Lee, nd V. Misra A Capacitance Based Methodology for Work Function Extraction of Metals on Highk IEEE Electron Device Lett. vol. 25, no. 6, pp. 420422, 2004. [134] H. C. Wen, R. N. Choi, G. A. Brown, T. Boscke, K. Matthews, H. R. Harris, K. Choi, H. N. Alshareef, H. F. Luan, G. Bersuker, P. Majhi, D. L. Kwong, and B. H. Lee, "Comparison of effective work function extraction methods using capacitance and current measurement techniques," IEEE Electron Device Letters vol. 27, pp. 598601, 2006. [135] J. R. Hauser, and K. Ahmed, Characterization of ultra thin oxides using electrical C and I Proc. AIP Conf. Proc. pp. 235, 1998. [136] K. T. Lee, C. Y. Kang, O. S. Yoo, C. D. Young, G. Bersuker, H. K. Park, J. M. Lee, H. S. Hwang, B. H. Lee, H. Lee, and Y, Jeong, A Comparative Study of Reliability and Performance of Strain Engineering using CESL Stressor and Mechanical Strain, IEEE 46t h Annual International Reliability Physics Symposium pp. 306309, 2008. [137] L. R. C. Fonseca, A. A. Knizhnik, First -principles calculation of the TiN effective work function on SiO2 and on HfO2, Phys. Rev. B vol. 74, pp. 195304, 2006. [138] C. Y. Kang, R. Choi, M. M. Hussain, J. Wang, Y. J. Suh, H. C. Floresca, M. J. Kim, J. Kim, B. H. Lee, and R. Jammy, Effects of metal gate induced strain on the performance of metal -oxide semiconductor field effect transistors with titanium nitride gate electrode and hafnium oxide dielectric, Appl. Phys. Lett vol. 91, pp. 033511, 2007. [139] OR. Singanamalla, H. Y. Yu, G. Pourtois, I. Ferain, K. G. Anil, S. Kubicek, T. Y. Hoffmann, M. Jurczak, S. Biesemans, and K. De Meyer O n the Impact of TiN Film Thickness Variations on the Ef fective Work Function of Poly-Si/TiN/SiO2 and Poly Si/TiN/HfSiON Gate Stacks IEEE Electron Device Lett. vol. 27, no. 5, pp. 332334, 2006. [140] K. Unala, and H. K. Wickramasinghe, Nanoscale quantitative stress mapping with atomic force microscopy, Appl. P hys. Lett vol. 90, pp. 113111, 2007. [141] Ch. Hsieh, and M. Chen, Electrical Measurement of Local Stress and Lateral Diffusion Near Source/Drain Extension Corner of Uniaxially Stressed n -MOSFETs, IEEE Trans. Electron Devices vol. 55, no. 3, pp. 844849, 2008. [142] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. Keersmaecker, A Reliable Approach to Charge -Pumping Measurements in MOS Transistors, IEEE Trans. Electron Devices vol. 31, no. 1, pp. 4253, 1984.

PAGE 102

102 [143] N. Kim, S. Kim, K. Park, E. Choi, M. Lee, H. Kim, K. Noh, J. Om, H. Lee, and G. Bae, Analysis of Si SiO2 Interface Using Charge Pumping with Various Capping Materials between Gate Stacks and Inter Layer Dielectric in NAND Flash Memory Jpn. J. Appl. Phys. vol. 45, no. 9A, pp. 68416844, 2006. [144] C. Y. Cheng, Y. K. Fang, J. C. Hsieh, H. Hsia, Y. M. Sheu, W. T. Lu, W. M. Chen, and S. S. Lin Investigation and Localization of the SiGe Source/Drain (S/D) Strain Induced Defects in PMOSFET With 45 -nm CMOS Technology IEEE Electron Device Lett. vol. 28, no. 5, pp 408410, 2007.

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103 BIOGRAPHICAL SKETCH Xiaodong Yang obtained the B.S. degree in p hysics from Inner Mongolia Normal University in 2001 M.S. degree in m aterials from Beijing University of Tech nology in 2004, M.S. degree in management from Warrington Colle ge of Business Administration at University of Florida in 2008, respectively. He has been work with Dr. Thompson group since 2005 and graduated with a PhD degree in electrical and computer e ngineering at the University of Florida in the fall of 2009. He w as with the CMOS Development and Research Department IMEC at Belgium as a device research engineer intern at 2008. During that period, he was involved in the highk/metal gate device development for the 32nm technology node. His current research interests are strain effects on the performance of MOSFETs.