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Synchronization and Control of High Frequency DC-DC Converters

Permanent Link: http://ufdc.ufl.edu/UFE0041162/00001

Material Information

Title: Synchronization and Control of High Frequency DC-DC Converters
Physical Description: 1 online resource (141 p.)
Language: english
Creator: Li, Pengfei
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: boost, buck, cmos, dc, delay, hysteretic, multiphase, pwm
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Modern high performance microprocessor systems in advanced CMOS technologies demand high peak current, large current transients, stringent voltage tolerance and high power dissipation. In order to cope with these requirements, near-load power delivery solutions are proposed to integrate the voltage regulator module near or within the processor die for localized power delivery. This solution is based on high frequency dc-dc converter designs, leading to fast load response, reduction in the component sizes and reduction in the external peak current. The objective of this work is to explore several high frequency dc-dc converter designs and synchronization techniques for near-load power delivery systems. This work begins with an overview of high frequency power converter design techniques. The multiphase hysteretic controlled converter is investigated in detail as it provides current staggered operation for ripple reduction and fast load response. We present a novel delay locked loop based hysteretic control scheme for high-frequency multiphase buck converters topologies to enable synchronous and stable operation. The converter employs the switching signal from the main voltage-regulation control loop and generates multiphase control signals with accurate duty cycle adjustment. Its key advantages include large output voltage range determined by the attainable duty cycle of the DLL. A digital phase locked loop frequency locking technique for high frequency hysteretic controlled dc-dc buck converters is also presented. The proposed technique achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or output voltage conversion range. The DPLL is programmable over a wide range of parameters and can be locked to a reference clock to ensure the converter switching frequency falls outside power supply resonance bands. Finally, this thesis reports a digital delay locked loop to synchronize a high frequency multiphase boost converter. The boost converter employs current mode pulse-width-modulation, and the D-DLL provides multiphase synchronization signals with accurate duty cycle control. The proposed digital control scheme can easily accommodate high frequency dc-dc converters with different structures and control loops, enabling fast and flexible design strategies for power management systems.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Pengfei Li.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Bashirullah, Rizwan.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0041162:00001

Permanent Link: http://ufdc.ufl.edu/UFE0041162/00001

Material Information

Title: Synchronization and Control of High Frequency DC-DC Converters
Physical Description: 1 online resource (141 p.)
Language: english
Creator: Li, Pengfei
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: boost, buck, cmos, dc, delay, hysteretic, multiphase, pwm
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: Modern high performance microprocessor systems in advanced CMOS technologies demand high peak current, large current transients, stringent voltage tolerance and high power dissipation. In order to cope with these requirements, near-load power delivery solutions are proposed to integrate the voltage regulator module near or within the processor die for localized power delivery. This solution is based on high frequency dc-dc converter designs, leading to fast load response, reduction in the component sizes and reduction in the external peak current. The objective of this work is to explore several high frequency dc-dc converter designs and synchronization techniques for near-load power delivery systems. This work begins with an overview of high frequency power converter design techniques. The multiphase hysteretic controlled converter is investigated in detail as it provides current staggered operation for ripple reduction and fast load response. We present a novel delay locked loop based hysteretic control scheme for high-frequency multiphase buck converters topologies to enable synchronous and stable operation. The converter employs the switching signal from the main voltage-regulation control loop and generates multiphase control signals with accurate duty cycle adjustment. Its key advantages include large output voltage range determined by the attainable duty cycle of the DLL. A digital phase locked loop frequency locking technique for high frequency hysteretic controlled dc-dc buck converters is also presented. The proposed technique achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or output voltage conversion range. The DPLL is programmable over a wide range of parameters and can be locked to a reference clock to ensure the converter switching frequency falls outside power supply resonance bands. Finally, this thesis reports a digital delay locked loop to synchronize a high frequency multiphase boost converter. The boost converter employs current mode pulse-width-modulation, and the D-DLL provides multiphase synchronization signals with accurate duty cycle control. The proposed digital control scheme can easily accommodate high frequency dc-dc converters with different structures and control loops, enabling fast and flexible design strategies for power management systems.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Pengfei Li.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Bashirullah, Rizwan.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0041162:00001


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1 SYNCHRONI Z ATION AND CONTROL OF HIGH FREQUENCY DC DC CONVERTERS By PENGFEI LI A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2009

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2 2009 Pengfei Li

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3 To my Mom and Dad

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4 ACKNOWLEDGMENTS First of all I would like to thank my academic advisors, Dr. Rizwan Bashirullah for his valuable guidanc e over the course of the last five years. I would also like to thank Dr Robert Fox, Dr Kenneth O Dr. Loc Vu Quoc and Dr. Prabhat Mishra for their advice and their willingness to be on my thesis committee. A special thanks to Deepak Bhatia, Lin Xue, Jika i Chen, Yan Hu, Hang Yu, and C hunming Tang for having usef ul design related discussions. I would also like to thank Zhiming Xiao, Pawan Sabharwal for always being open to answer any question at any time, let it be day or night. Speaking about the classes a t UFL, I would like to thanks Dr. Bashirullah for his excellent Advanced VLSI class, Dr Fox for his Bipolar and MOS design class, especially the simple design related approach and second order analysis, Dr O for his excellent Microwave IC design class D r. Ngo for his introduction to power electronics Finally, I would like to thank my mom, dad for all their love and support till date.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................................... 4 LIST OF TABLES ................................................................................................................................ 8 LIST OF FIGURES .............................................................................................................................. 9 LIST OF ABBREVIATIONS ............................................................................................................ 13 ABSTRACT ........................................................................................................................................ 14 CHAPTER 1 INTRODUCTION ....................................................................................................................... 16 1.1 Background ........................................................................................................................... 16 1.2 Recent Progress towards Integration of High Frequency DC DC Converter s ................. 19 1.3 Thesis Organization .............................................................................................................. 23 2 SWITCH ED INDUCTOR DC DC CONVERTERS ................................................................ 24 2. 1 Introduction ........................................................................................................................... 24 2. 2 Buck / Boost DC DC Converters Basic s ............................................................................. 24 2. 2 .1 Buck Converter Topology ......................................................................................... 24 2. 2 .2 Boost Converter Topology......................................................................................... 26 2. 2 .3 Indu ctor Current Ripple and Output Voltage Ripple ............................................... 28 2. 2 .4 Continuous C onduction Mode (CCM) and Discontinuous C onduction Mode (DCM) ............................................................................................................................... 29 2. 2 .5 Overall efficiency analysis for synchronous buck converter ................................... 31 2. 3 Control Scheme of DC -DC Converters ............................................................................... 34 2. 3 .1 Voltage M ode Pulse Width Modulation ( PWM ) Controller ................................... 34 2. 3 .2 Variable Frequency Controller .................................................................................. 35 2. 3 .2.1 Current mode h ysteretic c ontroller ................................................................. 35 2. 3 .2.2 Voltage m ode h ysteretic and c onstant o n -time c ontroller ............................. 38 2. 4 Multiphase Technique .......................................................................................................... 40 3 MULTIPHASE SYNCHRONIZATION WITH DELAY LOCKED LOOP .......................... 43 3.1 Introduction ........................................................................................................................... 43 3.2 DLL Based Multiphase Hysteretic Controller .................................................................... 44 3.2.1 System Architecture ................................................................................................... 44 3.2.2 Delay Locked Loop (DLL) Design ........................................................................... 45 3.2.3 Circuits Implementation............................................................................................. 48

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6 3.2.3.1 Delay c ell .......................................................................................................... 48 3.2.3.2 Phase f requency d etector and s tartup c ircuit .................................................. 48 3.2.3.3 Charge p ump and l oop f ilter ........................................................................... 50 3.3 Analysis for DLL based Multiphase Buck Converter ........................................................ 51 3.3.1 Voltage Conversion Range ........................................................................................ 51 3.3.2 Voltage Ripple ............................................................................................................ 53 3.3.3 Effects of Ph ase and Duty Cycle Mismatch ............................................................. 53 3.3. 4 Effect of Inductor Mismatch ...................................................................................... 58 3.3. 5 Effect of DLL on Transient Response ...................................................................... 58 3.4 Simulation Results ................................................................................................................ 61 3.4.1 Loop Dynamics .......................................................................................................... 61 3.4.2 Duty Cycle Error and Cur rent Mismatch .................................................................. 64 3.5 Measurement Results ............................................................................................................ 65 3.5.1 Four Phase Operation ................................................................................................. 66 3.5.2 Frequency Dependence .............................................................................................. 67 3.5.3 Efficiency .................................................................................................................... 68 3.5.4 Transient Response .................................................................................................... 69 3.5.5 Performance Summary ............................................................................................... 72 3.6 Summary................................................................................................................................ 74 4 FREQUENCY SYNCHRONIZATION WITH DIGITAL PHASE LOCKED LOOP (DPLL) ......................................................................................................................................... 76 4.1 Introduction ........................................................................................................................... 76 4.2 DPLL Synchronized DC DC Converter .............................................................................. 78 4.2.1 System Architecture ................................................................................................... 78 4.2.2 Modeling Hysteretic Buck Converter as a Voltage Controlled Oscillator ............. 80 4. 2 3 Modeling the DPLL Synchronized Converter as a Charge Pump PLL .................. 81 4.2. 4 Frequency Response ................................................................................................... 83 4.3 C ircuit Implementation of DPLL Synchron ized Hysteretic Converter ............................. 86 4. 3 1 Digital Phase Locked Loop (DPLL) Design ............................................................ 87 4. 3 2 Digitally Controlled Delay Line (DCDL) ................................................................. 89 4. 3 3 Hysteretic Comparator ............................................................................................... 90 4. 3 4 Non -Overlapping Clock Generation ......................................................................... 91 4. 3 5 On Chip Load ............................................................................................................. 92 4. 3 6 Layout of the Power Switches ................................................................................... 93 4.4 Mixed Signal Simulation of DPLL Synchronized Hysteretic C onverter .......................... 94 4.4.1 DPLL Operation with Variable Proportional Path Gain .......................................... 94 4.4.2 Transient Response to a Frequency and Load Step .................................................. 95 4.5 Measurement Results ............................................................................................................ 96 4.5.1 Frequency Locking Performance .............................................................................. 96 4.5.2 Efficiency .................................................................................................................... 98 4.5.3 Load Transient Response ........................................................................................... 99 4.5. 4 Digital Frequency Control ....................................................................................... 101 4.5. 5 Performance Summary ............................................................................................. 102 4.6 Summary.............................................................................................................................. 104

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7 5 HIGH FREQUENCY BOOST CONVERTER WITH DIGITAL DELAY L OCKED LOOP (D DLL) ......................................................................................................................... 105 5 .1 Introduction ......................................................................................................................... 105 5 .2 Multiphase Boost Converter with High Voltage Devices ................................................ 106 5 2 1 System Architecture ................................................................................................. 106 5 2 2 Schottky Diode Based Rectifier .............................................................................. 107 5 2 3 Synchronou s Switch ................................................................................................. 109 5 3 Proposed Digital Delay Locked Loop ............................................................................... 112 5 3 1 D DLL Architecture ................................................................................................. 112 5 3 2 Digital Controlled Delay Line ................................................................................. 114 5 4 Circuit Implementation ....................................................................................................... 116 5 4 1 Current Mode PWM Control ................................................................................... 116 5 4 2 Current Sensing Circuit ............................................................................................ 120 5 4 3 Oscillator (OSC) ....................................................................................................... 122 5 4 4 Layout for Power Switches ...................................................................................... 123 5 5 Measurement Results .......................................................................................................... 124 5 5 .1 Four Phase Operation ............................................................................................... 124 5 5 2 Efficiency .................................................................................................................. 126 5 5 3 Transient Response .................................................................................................. 127 5 5 4 Performance Summary ............................................................................................. 128 5 6 Summary .............................................................................................................................. 129 6 CONCLUSIONS AND FUTURE WORKS ........................................................................... 131 6 1 Summary and Contributions ............................................................................................... 131 6 2 Future Works ....................................................................................................................... 132 LIST OF REFERENCES ................................................................................................................. 134 BIOGRAPHICAL SKETCH ........................................................................................................... 141

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8 LIST OF TABLES Table page 2 1 Summary of CCM DCM characteristics for the buck and boost converters ...................... 31 3 1 Duty cycle and current -sharing analysis of the DLL controller .......................................... 65 3 2 Performance summary ........................................................................................................... 73 3 3 Perfor mance comparison ....................................................................................................... 73 3 4 Performance comparison ....................................................................................................... 74 4 1 Performance summary ......................................................................................................... 103 4 2 Performance comparison ..................................................................................................... 103 5 1 D DLL p erformance summary ............................................................................................ 126 5 2 Performance summary ......................................................................................................... 129 5 3 Performance comparison ..................................................................................................... 129

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9 LIST OF FIGURES Figure page 1 1 Processor's voltage and current of ITRS R oadmap, 2006 ................................................... 18 1 2 Intel's roadmap for processors slew rate .............................................................................. 18 1 3 Simplified power delivery network for Intel Pentium4 proces sor ...................................... 18 1 4 Near load converter insertion for processor power supply.................................................. 20 1 5 A multiphase CPU power delivery system for an AMD Soc ket 939 processor ................. 21 2 1 A standard step -down buck converter topology ................................................................... 25 2 2 Buck converter equivalent circuits. ....................................................................................... 25 2 3 Synchronous buck converter topology.................................................................................. 26 2 4 An ideal step up boost converter topology ........................................................................... 27 2 5 Boost converter equivalent circuits. ...................................................................................... 27 2 6 Capacitor current waveform for (a) buck converter, and (b) boost converter .................... 28 2 7 Buck converter operating in DCM ........................................................................................ 30 2 8 Voltage mode PWM buck converters (a) schematic and (b) waveforms .......................... 35 2 9 Single phase current mode hysteretic buck converter .......................................................... 36 2 1 0 Voltage waveforms at nodes VFB and VX. ............................................................................ 36 2 11 Single phase voltag e mode hysteretic buck converter ......................................................... 39 2 1 2 Single phase constant on -time buck converter ..................................................................... 39 2 1 3 a Basic 2 phase synchronous buck converter topology and (b) current waveforms ............. 40 2 1 4 Inductor current cancellation effect affected by the number of phases and duty cycle. .... 41 3 1 Block diagram of DLL based four phase interleaved dc dc converter .............................. 45 3 2 Block diagram of DLL based synchronization controller ................................................... 46 3 3 Representative timing waveforms of core and duty cycle loops ......................................... 47 3 4 Block diagram and schematic of delay cells ........................................................................ 49

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10 3 5 Circuit schematic of the phase frequency detector .............................................................. 49 3 6 Circuit schematics of charge pump/loop filter (CP/LF) ...................................................... 50 3 7 Derivation of DLL locking range for minimum and maximum duty cycles ...................... 52 3 8 Derivation of ripple voltage due to (a) phase and (b) duty cycle errors ............................. 54 3 9 a DC current imbalance in a 2 phase converter and (b) DC current sharing model ............. 56 3 1 0 Derivation of DLL based controller load response for a four phase buck converter. ....... 60 3 1 1 Simulated loop response during (a) startup and (b) line step. ............................................. 63 3 12 Four phase inductor currents and ripple cancellation. ......................................................... 64 3 1 3 Die photo. ............................................................................................................................... 66 3 1 4 Measured bridge output waveforms with 220nF/phase. ...................................................... 67 3 1 5 Measured jitter while dc -dc converter is operational ........................................................... 67 3 1 6 Measured switching frequency and duty cycle vs. output voltage as VREF is swept ......... 68 3 1 7 Measured efficiency for VIN=4.8V, VOUT=3.3V, 220nH/phase and 26MHz 30MHz ....... 69 3 18 Measured load response for 0.3A current step. .................................................................... 70 3 19 Output voltage droop for a 0.3A current step. ...................................................................... 70 3 20 Measured output voltage at 4.9V/3.3V conversion .............................................................. 71 4 1 P roposed DPLL synchroniz ation scheme for hysteretic control loop ................................ 79 4 2 A s -domain model of the charge pump PLL with dc dc converter as a VCO .................... 81 4 3 Bode plot of the (a) open loop and (b) closed loop transfer function. ................................ 83 4 4 Transient response to a frequency step for diffe rent damping factor ................................. 85 4 5 Transient response to a frequency step versus converter duty cycle ................................. 85 4 6 Proposed DPLL synchronized hysteretic controlled buck converter .................................. 86 4 7 DPLL block diagram .............................................................................................................. 88 4 8 Digital Controlled Delay Line ............................................................................................... 90 4 9 Hysteretic comparator Schematic .......................................................................................... 91

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11 4 10 Circuit schematic for non overlapping clock generation ..................................................... 92 4 11 On -chip emulated transient load with programmable rise time and amplitude ................. 92 4 12 Layout of power switches ...................................................................................................... 93 4 13 Control word versus time in the startup simulation for different values of KP .................. 94 4 14 Simulated control word versus time in a transient response. .............................................. 95 4 1 5 Die photograph ....................................................................................................................... 96 4 1 6 Converter switching frequency versus output voltage ......................................................... 97 4 1 7 Jitter histog ram of (a) divided clock and (b) buck converter bridge output. ...................... 98 4 1 8 Measured efficiency ............................................................................................................... 99 4 1 9 Measured load response at 1.2 V/0.8V conversion using 25nF output capacitor ............. 100 4 20 Measured load response at 1.2V/0.8V conversion. ............................................................ 102 5 1 Four -phase boost converter with D DLL based controller ................................................ 107 5 2 Cross section and J -V curves for schottky diodes with or without guard ring ................. 108 5 3 Cross section of the DENMOS and measured breakdown characteristics. ...................... 111 5 4 8 Phase Delay Locked Loop................................................................................................ 113 5 5 Digitally -Contro lled Delay Line ......................................................................................... 115 5 6 Current mode PWM controller ............................................................................................ 117 5 7 Schematic of the error amplifier and the comparator in the voltage f eedback loop ........ 117 5 8 Demonstration of loop instability in a current mode converter. ........................................ 119 5 9 Schematic of the current sensing cir cuit ............................................................................. 121 5 10 Schematic of the oscillator (OSC) with current ramp generator ....................................... 122 5 11 Layout for the output stages of the single phase boost converter ..................................... 123 5 12 Die photo ............................................................................................................................... 124 5 1 3 Measured waveforms of 4 -phase boost converter .............................................................. 125 5 1 4 Measured jitter while boost converter is operational. ........................................................ 126

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12 5 1 5 Measured efficiency ............................................................................................................. 127 5 1 6 Measured load response for 50% current step ................................................................... 128

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13 LIST OF ABBREVIATION S VRM Voltage regulator module D Duty cycle of the converter PWM Pulse w idth m odulator DPWM Digital Pu lse w idth m odulator PFM P ulse -frequency -modulation CCM Continuous conduction mode DCM Dis continuous conduction mode TS Switching time period DLL Delay locked loop DDLL Digital d elay locked loop VCDL Voltage controlled delay line DCDL Digital controlled delay line VCO Voltage controlled oscillator PLL Phase locked loop DPLL Digital phase locked loop L Peak -peak inductor current ripple ESR Equivalent series resistance rms Root mean square PFD P hase frequency detector CP Charge Pump

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14 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy SYNCHRONIZATION AND CONTROL OF HIGH FREQUENCY DC DC CONVERTERS By Pengfei Li December 2009 Chair: Rizwan Bashirullah Major: Electrical and Computer Engineering Modern high performance microprocessor systems in advanced CMOS technologies demand high peak current, large current transient s, stringent voltage tolerance and high power dissipation In order to cope with the se requirements, near load power delivery solutions are proposed to i ntegrat e the voltage regulator module near or within the processor die for localized power delivery This solution is based on high frequency dc -dc converter design s leading to fast load response reduction in the component sizes and reduction in the external peak current The objective of this work is to explore several high frequency dc dc co nverter designs and synchronization techniques for near load power delivery systems. This work begins with an overview of high frequency power converter design techniques The multiphase hysteretic controlled converter is investigated in detail as it provides current staggered operation for ripple reduction and fast load response. We present a novel delay locked loop based hysteretic control scheme for high -frequency multiphase buck converters topologies to enable synchronous and stable operation The conve rter employs the switching signal from the main voltage regulation control loop and generates multiphase control signal s with accurate duty cycle adjustment. Its key advantages include large output voltage range determined by the attainable duty cycle of t he DLL

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15 A digital phase locked loop frequency locking technique fo r high frequency hysteretic con trolled dc -dc buck converters is also presented The proposed technique achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or output voltage conversi on range. The DPLL is programma ble over a wide range of parame ters and can be locked to a ref erence clock to ensure the converter switching frequency falls outside power supply res onance bands. Finally, this thesis reports a digital delay locked loop to synchronize a high frequency multiphase boost converter. The boost converter employs current mode pulse -width -modulation and t he D DLL provides multiphase synchronization signals w ith accurate duty cycle control T he propose d digital control scheme can easily accommodate high frequency dc dc converters with different structure s and control loops enabling fast and flexible design strategies for power management systems.

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16 CHAPTER 1 INTRODUCTION 1.1 Background The c ontinu ed scaling of CMOS technologies used in high performance microprocessor systems enable s increase d functionality with higher transistor count and of ten times faster clock speed s, resulting in higher current demands i ncreased power dissipation and heat generation Fig. 1 1 shows the ITRS roadmap for the processors required current and voltage [1]. Though the supply voltage decreases to levels as low as 0.7 V, the total power skyrockets due to the tremendously increased supply current (>150A). Additionally, higher curre nts and lower voltages decrease the processors load impedance, requiring power supply impedance s of less than 1m ohm for accurate and efficient power delivery [2] The continuous increase of speed and the transistor count for the microprocessor raises another serious challenge for voltage regulation module (VRM) design. T he high clock frequency causes very high current slew rates (di/dt) when the mi croprocessor operation changes from full power to sleep modes and vice versa [2] [4]. The rate of change between these modes is more than one thousand times per second F ig. 1 2 sho ws this developin g trend: the slew rate of the processors current can reach ~100A/ns. This high dynamic characteristic makes accurate voltage regulation extremely difficult, requiring a VRM with very fast transient response. Also, this VRM must be placed in close proximit y to the microprocessor to reduce the impedance of the power delivery path [5], [6]. Therefore, power converter design for the processors of the next decade is very important and challenging. The di rect problem is maintaining the output voltage within the 5% 10% tolerance range, thus allowing for a re gulation window of only about 35mV 70mV for 0.7V DC supply voltage. Furthermore, the voltage must maintain accuracy during large current excursions

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17 and fast di/dt changes In order to meet the voltage accuracy requirements, traditional power delivery methods employ fast on -board voltage regulators modules (VRM) and make extensive use of external and ondie decoupling capacitances. For instance, the extern al decoupling layer ceramic capacitor (MLCC) size 1206 1206 Al electrolytic capacitors [7], increasing the cost of onpackage and motherboard decoupling capacitors as shown in Fig. 1 3 Furth ermore, at higher frequencies above which the external dc dc power supplies can respond, the use of on-chip decoupling ca pacitors as a sole means to supply the temporary current demands is becoming more difficult as the decrease in oxide thickness in advanced nodes leads to possible electrostatic discharge (ESD) induced oxide breakdown and an increase in static power via gat e tunneling leakage. One strategy t o reduce the size of the external motherboard decoupling capacitor is to operate t he VRM at significantly higher switching frequencies. For instance, when the VRM is operated that is required when the VRM is operated at 500 kHz [8]. Another benefit of operating at a higher frequency is the smaller inductor size which also occupies significant sp ace in VRM design. However, high frequency converters raise efficiency and thermal issues due to s evere switching and conduction loss es, especially when d elivering large currents (~ 100200A ) to the output As a result, high efficiency, high power density, fast transient VRMs are critical for meeting the power requirements of the next generation of processors.

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18 0 0.2 0.4 0.6 0.8 1 2005 2007 2009 2011 2013 0 50 100 150 200 250 0 0.2 0.4 0.6 0.8 1 Supply Voltage (V) 0 5 0 100 1 5 0 200 2 5 0Current (A) 2005 2007 2009 2011 2013Year Figure 1 1 Processor's voltage and current of ITRS Roadmap, 2006 Figure 1 2. Intel's roadmap for processors slew rate Figure 1 3 Simplified power delivery network for Intel Pentium4 processor

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19 1.2 Recent Progress towards Integration of High Frequency DC DC Converter s Based on the power management issues mentioned in the previous section, it is clear that high efficiency, high power density, fas t transient dc -dc converter s are critical for meeting the power requirements of future microprocessors. Several innovative control loop s have been introduced in the literature including enhanced V2 control [9], active -droop control [10] [11] valley current mode control [12] multiphase voltage -mode hysteretic control [13] [14] multiphase current -mode hysteretic control [15] dynamic pulse modulator method [16] and hybrid control [17] The digital ly control led power converter has also been developed improving design flexibilit y and noise immunity [18] -[25] However, some control schemes have potential problems when applied to integrated high frequency (10s 100sMHz) dc -dc converters including control accuracy control delay, multi phase synchronization and power dissipation. Despite the development in converter control schemes, n ear -load converter insertion solution s utilizing high -frequency low -voltage dc -dc converters are currently being pursued to reduce the component sizes and the parasitic impedances of the power s upply connections [15] [26] As sho wn in Fig. 1 4 a i ntegrating the dc dc converter near or within the processing die has several advantages. First, the load respons e of a high frequency near load converter can be improved by several orders of magnitude to cope with fast localized transients due to the smaller impedance between the dc dc converters and the load circuits. Second, a high voltage conversion ratio near th e load trades voltage for current efficiency to reduce the external peak current (IEXT) t hat must be supported by the power distribution network, therefore reducing the conduction loss on the board interconnect and relaxing the stringent impedance requirem ents of packages and board level traces. Third, ultra -high frequency converters can lead to a reduction in capacitor and inductor sizes by several orders of magnitude. Thus, the cost of increased ondie area from integrating the dc -dc converter can be trad ed for smaller and fewer external components at the

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20 board level, which decreases the cost and footprint of the external power delivery system. Finally, localized and efficient power delivery systems naturally lend themselves to multiple voltage domains for multi -core processing architectures as shown in Fig. 1 4b MB VRM Analog or I/O C ESL ESR VDD ESL ESR GND IEXT Logic SRAM DC/ DC DC/ DC VDD1 VDD2 Microprocessor (a) (b) Figure 1 4 Near -load converter insertion for processor power supply (a) on a 3D -stacked dies and (b) simplifi ed power network Near load dc -dc converter insertion based on multiphase topologies can be used to reduce external current requirements and to decrease on -die capacitance and the size of output filter s, enabling multiple supply domains in future microproce ssor platforms Multiphase technique s ha ve been widely used in computer power supplies to convert the 12V power supply to a lower voltage For instance, Fi g 1 5 shows a p icture of a three phase power supply for an AMD Socket 939 processor. The three phases of this supply can be recognized by the three black toroidal inductors in the foreground. Digital pulse width modulators (DPWM) are often used for multip hase dc -dc converter synchronization [19] [27] In order to synthesize the switching signal with high resolution duty cycle, [27] uses a much faster system clock (50 MH z) to generate a 16 phase 150 kHz switching signal while [19] employs a 128 stage differential ring oscillator generating a 100kHz to 5MHz four phase signal in 0.25 m CMOS process. Thus, it is difficult to employ these digital techniques in future integrated dc -dc converter designs with ultra high

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21 frequency (>100MHz). In the analog controller regime, a recently reported four phase dc -dc converter in 90nm CMOS process in [28] can operate at 480MHz by using externally generated signals to synchronize a hysteretic controller via injection locking at the switching instants. However, it does not ensure accurate synchronization with high resolut ion duty cycle. An improved voltage -mode control loop is proposed in [14] but the conversion factor is limited to 1/N, where N is the number of converter phases, and therefore requires larger minimum input voltage when the num ber of phases increases. Figure 1 5. A multiphase CPU power delivery system for an AMD Socket 939 processor Although there are numerous control schemes for step -down voltage regulators, multiphase hysteretic controlled buck converters are a potential can didate for near load VRMs as this topology exhibits a near instantaneous load response and ripple cancellation effect. U nlike the traditional PWM controller, the hysteretic controller is inherently stable without complex compensation. Thus it exhibits a fa ster load response and further reduces the decoupling capacitor size, given the same load transient requirement. However, combining hysteretic controlled techniques with multiphase dc dc converters can be challenging due to a lack of accurate converter syn chronization. For the controller to operate correctly, all bridge drive signals must be synchronized and staggered in time, and their duty cycles must be proportional to

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22 the desired output voltage conversion ratio. Lack of synchronization leads to increase d ripple voltage, slower response, and larger inductor sizes. In chapter 3, w e propose a d elay lock ed loop (DLL) based scheme to solve th e multiphase synchronization problem for the hysteretic controller. Another problem with hysteretic control is that the free running switching frequency changes with conversion voltage. If left unchecked, the free running oscillations may fall in undesired power supply resonance bands created by parasitic package inductance interconnects and on-die decoupling capacitances. Operation at these frequencies can potentially generate large voltage excursions in the supply network due to high impedance peaks formed by the multi resonant networks, compromising overall system operation and device reliability [29] Therefore, it is desirable to synchronize the converter to an on-chip clock generated from within the processor to mitigate noise injection in undesirable frequency bands. A d igital p hase lock loop (DPLL) based synchronization scheme is presente d to solve this problem in Chapter 4. A lthough the synchronization techniques in Chapter 3 and Chapter 4 are proposed for the current -mode hysteretic buck converter, these techniques are easily compatible with other converter topologies and voltage control loops. In Chapter 5, we demonstrate a digital delay locked loop (D DLL) synchronization scheme for boost converters High frequency b oost converters integrated with advanced CMOS technology can find use in battery powered portable systems, to deliver high voltage for display device s audio amplifier s and flash memory. In this work, a curr ent -mode pulse -width -modulation (PWM) 4 -phase boost converter is operated with 100MHz switching frequency and synchroniz e d with the proposed D DLL based controller achie ving automatic multiphase signal generation, accurate duty cycle control and current sharing.

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23 1.3 Thesis Organization The focus of this thesis is to investigate the synchronization scheme and control loop designs for high frequency dc -dc converters Our ob jective is to implement high frequency digitally assisted dc dc converters in CMOS process to enable integrated power supply systems on -chip or on -package Th is thesis is organized into six chapters and t his chapter introduces the background and motivation for integrated high frequency dc dc converter s A literature review of switch ed inductor dc -dc converter topologie s is presented in chapter 2. Chapter 3 demonstrates a synchronization scheme for high -frequency multiphase hysteretic controlled buck convert ers using a delay locked loop (DLL) based controller It can achieve automatic phase synchronization with accurate duty cycle, and large voltage conversion range. A 25M 70MHz multiphase hysteretic buck controller has been des igned with this scheme in a 0.5 m CMOS process. Chapter 4 describes a digital phase locked loop ( DPLL) frequency locking technique for ultra -high frequency hysteretic buck converters to mitigate noise injection in undesirable frequency bands. The modeling of the hysteretic converter as a voltage controlled oscillator (VCO) and the analysis of the entire system as a charge pump PLL (CPPLL) is proposed. A 90M 240MHz single phase hysteretic buck controller has been designed with this scheme in 0.13 m CMOS process Chapter 5 reports a multip hase boost converter design utilizing digital delay locked loop (D DLL) with current -mode PWM control. B y using integrated schottky diodes and stacked NMOS device in CMOS process, a 1.2V input 100MHz 4 -phase boost converter a chieve d 3 5 V output Fin ally, conclusions and continuing work are presented in chapter 6

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24 CHAPTER 2 SWITCH ED INDUCTOR DC DC CONVERTERS 2. 1 Introduction The key principle in the switch ed inductor converter is the tendency of an inductor to resist changes in current. When the ind uctor is being charged it acts as a load and absorbs energy; when being discharged it acts as a n energy source. During the discharging phase, the resulted voltage drop across the inductor is related to the slope of the inductor current, thus allowing diff erent output voltages generated from the absorbed energy. In this chapter, the basic topologies for switch ed inductor converters are introduced in section 2. 2 The fundamental concepts of conduction mode, output ripple and efficiency will be discussed. C ontrol loops includ ing pulse width modulation (PWM) and hysteretic control are presented in section 2. 3 followed by a brief review of the multiphase technique in section 2. 4 2. 2 Buck / Boost DC -DC Converters Basic s 2. 2 .1 Buck Converter Topology A buck co nverter is a dc -dc converter which generate s step down voltages (i.e. input voltage VIN is larger than output voltage VO). S how n in Fig. 2 1, between the input voltage VIN and the load RL, is the standard buck converter topology consisting of an inductor L an output capacitor C, an active switch Q1 and a n ideal diode D1. The duty cycle, D is defined as the r atio between the on -time of switch Q1 and the period of the switching signal TS. The expression (1 D ) represents the time ratio that Q1 is off and i s referred to as D` for convenience. Fig. 2 2 shows the buck converters equivalent circuits as the switch Q1 turns on/off and the voltage/current waveforms of the inductor vL(t), iL(t). During the time interval DTS, Q1 turns on and connects VX to VIN, whi ch reverse biases diode D1, turning it off. vL(t) is then equal to the difference VIN-VO and iL(t) increases, as shown in Fig. 2 2a and 2 2c. During the time interval

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25 D`TS, Q1 turns off and, in order to continue the inductor current, D1 turns on, connecting VX to ground. Then vL(t) jumps to -VO and forces iL(t) to decrease, as shown in Fig. 2 2b and 2 2c. VIN RLC L VXD1 Q1 iL(t ) vL(t ) VO Figure 2 1. A standard step -down buck converter topology VIN RLC L iL(t ) vL(t ) VIN RLC L VX=0 iL(t ) vL(t ) VX=VINVOVOWhen Q1 is on When Q1 is off ( a) ( b ) ( c) t iL(t) t vL(t) VIN-VODTSD`TS IO-VO Figure 2 2. Buck converter equivalent circuits when (a) Q1 is on, (b) when Q1 is off. (c) shows the voltage and current waveforms of the inductor L. In terms of power transfer, the inductor L is functioning as a regulated current source supporting the required output current IO during the whole cycle TS It is recharged by the input power only during DTS. In terms of signal processing, the inductor and capacitor work as a secondorder low pass filter attenuating the switching components and harmonics while also

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26 generating a DC output from the switching signal VX. Ideally without considering the resistive loss on the current path, the output voltage VO is simply equal to the average value of VX. IN X ODV V V (2 1) When integrated buck converters are fabricated in CMOS technology, diode D1 is typically replaced by a controlled NMOS switch, shown as Q2 in Fig. 2 3 S maller turn on voltage drop and improved efficiency are the primary reasons for the substitution of the switch This topo logy, called a synchronous buck converter is the modified version of the standa rd buck converter (or asynchronous buck converter) i n Fig. 2 1. Typically it requires a controller to generate non -overlapp ing control signals to prevent Q1 and Q2 from conducting at the same time [30] RLC L VXQ2 Q1 iL(t ) vL(t ) Control Figure 2 3. Synchronous buck converter topology 2. 2 .2 Boost Converter Topology The boost converter shown in Fi gure 2 4, is a dc -dc converter topology that generates step up output voltages (i.e. VO>VIN). The ste ady state waveforms and equivalent circuits for t he boost converter are provided in F igure 2 5. When the active switch Q1 is switched on by the gating signal, VX is grounded. Thus, inductor L has a charging path through ground and its current level increase s During this period of DTS, D1 is reversed b iased and the output load is powered by capacitor C. As shown in Fig. 2 5b, when Q1 turns of f ( during D`TS), t he inductors

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27 continuous charging current forces VX to increase to VO (neglecting the diode turnon voltage) Inductor L then transfers its stored energy to the load. VIN RLC L VXD1 Q1 iL(t ) vL(t ) VO Figure 2 4. An ideal stepup boost converter topology When Q1 is on ( a) ( b ) ( c) t iL(t) t vL(t) VINDTSD`TS IINVIN-VO VIN RLC L VX=0 iL(t ) vL(t ) VO VIN RLC L VX=VO iL(t ) vL(t ) VO When Q1 is off Figure 2 5. Boost converter equivalent circuit s when (a) Q1 is on, (b) Q1 is off. (c) shows the voltage and current waveform s for inductor L. As shown in Fig 2 5c, during stea dy state, the net change in inductor current over a cycle is zero. Therefore, VIN-VO must be negative, or equivalently, VO must be larger than VIN. In terms of power transfer, inductor L in the boost converter connects the input voltage source, VIN, and re gulates the input current, IIN, during the whole cycle, TS, and charges the output load only during D`TS. Therefore, the boost converters output voltage can be given by the following,

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28 O X INV D V V ` (2 2 a ) D V D V VIN IN O 1 ` (2 2b ) 2. 2 .3 Inductor Current Ripple and Output Voltage Ripple As shown in Fig. 2 2c, for the buck converter, the in ductor current ripple can be expressed as L DT V V IS O IN L) ( (2 3 ) Fig. 2 6 shows the typical timing waveform s for the capacitor current iC(t) in the buck and the boost converter, respectively, assuming the capacitor charging current is positive. For the buck converter, iC(t)=iL(t) -IO and thus IC=IL, as shown in Fig. 2 6a. In the steady state, the capacitors current has 0 dc value and the total charge dumped and removed from the output IL/4 fS. Therefo re, the output voltage ripple (half of the peakto peak value) can be written as LC f D V V C f I V VS O IN S L C O 28 ) ( 8 (2 4 ) t iC(t) IODTSD`TS t iC(t) DTSD`TS IL/2 IL/2 (a) (b) Figure 2 6. Capacitor current waveform for (a) buck converter, and (b) boost converter As shown in Fig. 2 5c, the inductor current ripple in the boost converter can be expressed as L T D V V IS O IN L) 1 )( ( (2 5 )

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29 Also iC(t)= -IO during DTS and iC(t)= iL(t) during D`TS, as shown in Fi g. 2 6b. Since the change in output voltage VO is quite small compared to VO, it can be assumed that the load current IO remains constant at VO/R When the capacitor current is constant, its voltage changes linearly with time and the voltage ripple is given by RC f DV C DT R V VS O S O O (2 6 ) 2. 2 .4 Continuous C onduction Mode (CCM) and Discontinuous C onduction Mode (DCM) So far t he converters analyzed were assumed to operat e in the continuous conduction mode (CCM). In this mode, the inductor s current is continuous and its average value (dc value) is larger than half of the current ripple (IL/2). However, when the required output power level becomes small enough, converters can enter the dis continuous conduction mode (DCM). Consider the buck converter as an example, as shown in Fig. 2 7; for very light load s the inductor current ramp iL(t) falls to zero during part of the period. In this case, the inductor is completely discharged because diode D1 in Fig. 2 1 cannot support the negative current of the inductor (i.e. negative iL indicates the reverse leakage current from the load). Then VX i s charged to VO and D1 is off. Note that the synchronous buck converter in Fig. 2 3 cannot enter DCM in light loads This is b ecause an NMOS switch, un like a diode based rectifier allows negative inductor current iL, indicating a reverse leakage current from the load to ground. This current leakage costs an additional power loss and undermine s the light load efficiency. To solve this problem the control circuit needs an auxiliary loop to sense the zero-cross ing current indicating when to turn off the N M OS switch properly [31]

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30 VIN RLC L VX=VO iL(t ) vL(t ) VOWhen Q1 and D1 are off (a) (b) t iL(t) t vL(t) VIN-VODTS-VO TS 0 Figure 2 7. Buck converter operating in DCM (a) equivalent circuit when Q1 and D1 are both off and (b) inductor voltage and current waveform The inductor va lue determines the slope a nd the amplitude of iL, and thus determine s when the converter enter s DCM. For a buck converter with a load resistance of RL= Rlim, the load current at the boundary between CCM and DCM equal s to half of the inductor current ripple (IL/2). Based on Eq. 2 4 and Eq. 2 1, this relationship can be written as S IN L OLf D D V I R V 2 1 2lim (2 7 ) Therefore, t he minimum inductor value Lmin, which guarantees CCM operation for the specified load range ( R Rlim) is S S O INf R D f V R D D V L 2 1 2 1lim lim min (2 8 ) In other words, when L
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31 Table 2 1. Summary of CCM -DCM characteristics for the buck and boost converters Converter L min V O in CCM V O in DCM Buck Sf R D 2 1lim D VIN 28 1 1 2 RD Lf VS IN Boost Sf R D D 2 1lim 2 D VIN 1 2 2 1 12 S INLf RD V 2. 2 .5 Overall efficiency analysis for synchronous buck converter T he conduction efficiency calculation in dc -dc converters only includes the conduction losses caused by the parasit ic resistive impedances (the on resistance of the power MOSFET and diode, the inductors ESR). In contrast the overall efficiency include s the conduction losses and the switching losses due to the parasitic capacitive impedances of the circuit components Here we only d emonstrate the overall efficiency analysis for the synchronous buck converter topology as an example (see Fig. 2 3) The main power loss comes from (1) the power MOSFET and the related g ate drivers, and (2) inductor L ; the power dissipation of the controller circuits and the output capacitors are typically small as compared to the loss of (1) and (2); the short circuit power loss is neglected assuming non-overlapp ing control signals are applied for the power MOSFET Therefore, the conduction loss and the switching loss for the power MOSFET and the related gate drivers are given by the following [33] BRDG L O R MOSR I I P 32 2 (2 9a ) 2 _1IN S BRDG C MOSV f C P (2 9b)

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32 D W R D W R RNMOS NMOS PMOS PMOS BRDG 1 (2 9c ) MOS NMOS PMOS db gd gs ox NMOS PMOS BRDGC W W C C C C W W C 2 (2 9d ) where PMOS_R is the conduction loss which is inverse proportional to the width of the NMOS ( WNMOS) and PMOS ( WPMOS) in Eq. 2 9c ; PMOS_C is the swit ching loss proportional to the width of the MOSFETs ( WPMOS+ WNMOS). RBRDG and CBRDG are respectively, the equivalent series resistance and equivalent capacitance of the buck bridge The bridge consists of both high -side PMOS and low -side NMOS transistors The tapering factor of the gate drivers, is used in Eq. 2 9 b to include the additional loss from the gate driver. RPMOS and RNMOS are, respectively, the on resistance of a 1 m -wide PMOS and NMOS. Cox, Cgs, Cgd, and Cdb are the gate oxide, gate to source overlap, gate to -drain overlap, and dra in to body junction capacitances, respectively, of a 1 m -wide MOSFET For simplicity, we assum e that these parameter s are the same for both PMOS and NMOS devices. The sum of these capacitances is represented by CMOS in Eq. 2 9 d As given by above equati ons, increasing the MOSFET width decreases the conduction loss while increasing the switching loss Thus, for a target load current IO and the converter frequency fS, the optimum width s for PMOS ( WPMOS_OPT) and NMOS ( WN MOS_OPT) that optimize s the overall e fficiency is given by 2 2 2 _1 3IN s MOS L O PMOS OPT PMOSV f C I I D R W (2 1 0 a )

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33 2 2 2 _1 3 1IN s MOS L O NMOS OPT NMOSV f C I I D R W (2 1 0 b ) The cond uction loss related to the inductor is 2 2 23IN S ind ind L O indV f C R I I P (2 1 1 ) where Rind and Cind are the parasitic series resistance and the parasitic stray capacitance of the inductor respectively Considering all the primary loss mechanism s described above, the overall efficiency of the synchronous buck converter can be expressed as 2 2 2 2 2 2 2 2 _3 1 3IN S ind ind L O IN S BRDG BRDG L O L O L O ind C MOS R MOS O OV f C R I I V f C R I I R I R I P P P P P (2 1 2 ) where PO is the output power and RL is the load resistance. If the power MOSFET widths and the input/output vol tages are fixed, the peak efficiency based on the Eq. 2 1 0 only occurs at the target load IO. At lighter loads than IO, efficiency degrades because the switching loss dominates the total input power. At heavier loads, the efficiency decreases due to higher conduction losses associated with the inductor and bridge resistances. Additionally, high input voltage VIN leads to smaller duty cycle for a fixed VO, and mak es high efficiency converter design more difficult due to the VIN related component s shown in Eq 2 1 2

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34 2. 3 Control Scheme of DC -DC Converters 2. 3 .1 Voltage Mode Pulse Width Modulation ( PWM ) Controller PWM is t he most common control scheme for dc -dc converters As shown in Fig 2 8 t h e control loop senses the output voltage VO and subtracts this from a reference voltage VREF to establish an error signal ( VERROR). This error signal is compared to a fixed frequency carrier waveform ( VCAR), usually triangular or saw tooth in shape a s shown in Fig. 2 8b. T he comparison between VERROR and VCAR resul ts in a square wave signal VX and generate s a dc output VO. When VO changes due to the varying input/output conditions VERROR changes accordingly to modulate the output pulse width. This pulse width modulation then moves the output voltage towards VREF du e to the negative feedback loop. Let the carrier waveform VCAR vary from VCAR_min to VCAR_max, then the duty cycle D ca n be estimated to be as min max min _-CAR CAR CAR ERRORV V V V D (2 1 3 ) VINPWM generatorL VXrL IOCOUTVO Bridge drivers ++Compensation VREFVERRORVCARError amplifierVINPWM generatorL VXrL IOCOUTVO Bridge drivers ++Compensation VREFVERRORVCARError amplifier (a)

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35 t t VX(t) VINDTS VERRORVCAR(t) 0 t t VX(t) VINDTS VERRORVCAR(t) 0 (b) Figure 2 8 V oltage mode PWM buck converter s (a) schematic and (b) waveforms This control scheme is optimized for output voltage regulation, but is not preferred in terms of loop dynamics [34] [35] As shown in Fig. 2 8a an RC compensation circuit is required to ensure the stability of the PWM control loop. The design of the compensation circuit can be complicated, especially when the load current has l arge dynamic range or when the load capacitor is not fixed in the design. Also, increased stability by the compensation circuit design (i.e. increased phase margin) degrades the loop response to a load or line transient. 2. 3 .2 Variable Frequency Controll er 2. 3 .2.1 Current m ode h ysteretic c ontroller PWM control is a fixed frequency control loop, in which the duty cycle is variable. In contrast, a v ariable frequency control ler has variable duty cycle and switching frequency determined by the load conditions Current mode hysteretic cont rol is one type of variable frequency controller and is favored due to its simple topology and fast transient response. Fig 2 9 shows a current mode hysteretic controlled buck converter comprised of a hysteretic comparator, a cascade of buffers to drive the high -side PMOS and low -side NMOS bridge, a switched inductor L and the feedback network RF, CF. The feedback network RF and CF is an RC integrator used to estimate the inductor current.

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36 VINHystereticComparatorL CFRF RD VX VFBVREFrL IOCOUTVO +Bridge drivers Figure 2 9 Single phase current mode hysteretic buck converter VREF+VHVREF VFB VXVIN0 DTS VFB time VXDTSVREF+VHVREFVIN0 timeONOFF (a) (b) Figure 2 1 0 Voltage waveforms at nodes VFB and VX (a) without converter propagation delay and (b) with finite propagation delay. Fig. 2 10a s hows the idealized voltage waveforms VFB at the feedback node and VX at the bridge output. The switching frequency of the buck converter can be derived from the slope of VFB at the feedback node and the hysteretic window VH. If we consider the finite propagation delays of the comparator, buffers and bridge, as shown in Fig. 2 10b, the switching frequency can be expressed as [36] 11 1 / D D D D V V fOFF ON IN H RC S (2 14a) where RC equals RFCF, ON and OFF correspond to the finite propagation delays of switching the inductor to VIN and ground, respectively, and D is the duty cycle. If the propagation delays are assumed to be equal ( ON= OFF= D), the switching frequency reduces to

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37 D IN H RC SV V D D f / 1 (2 14b) This suggests that the maximum switching frequency occurs when D=0.5 or fMAXRC(VH/VIND). Since D sets the output conversion ratio VO/VIN, the switching frequency exhibits a parabolic dependence on the conversion ratio. If the conversion range of the converter is D=0.2 to D=0.8 the switching frequency will vary from 0.64fMAX to fMAX. Unlike a PWM control the hysteretic control loop does not require a n error amplifier with frequency compensation resulting in a wide r bandwidth and simpler design. Therefore, i t react s faster to load and line transients than a PWM does If resistor RD is introduced between the comparator output and VFB as shown in Fig 2 9 the converter output impedance will exhibit a resistive response for improved load response [37] When the converter is loaded with current, the output will exhibit a dc error proportional to the output resistance, forcing the output voltage to position itself along a load line with the slope of the output resistance a concept known as voltage positioning [15] [37] At the output of the hystereti c comparator the average voltage is DVIN, which is reduced by the bridge series resistance RBRDG and the inductor effective series resistance rL at the bridge output. It fo llows that the average voltage < VO> at the output of the buck converter is O L BRDG IN X OI r R DV V V (2 15) A nd the average voltage < VFB> can be expressed as [15] O BRDG F D D IN FBI R R R R DV V (2 16) where VIN and < VX> are the input voltage and the a verage bridge output voltage, respectively, and < IO> is the average output current. Since the negative feedback loop of the controller forces the voltage variation of VFB to match the hysteretic window, VH, set by the

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38 comparator, the average voltage VFB is given by VREF + VH/2 where VREF is the input reference voltage. Then the average output voltage can be expressed as O L BRDG F D F H REF OI r R R R R V V V 2 (2 17) Thus, the output impedance can be adjusted by selecting RD to yield an improved load respons e at the expense of a dc error in the output voltage. 2. 3 .2.2 Voltage m ode h ysteretic and c onstant o n -time c ontroller Unlike current mode hysteretic control, voltage mode hysteretic modulation sense s the output voltage VO as the feedback ramp, as shown in Figure 2 11. When the feedback voltage exceeds the reference voltage VREF, the comparator output goes low, turning off the upper switch The switch remains off until the feedback voltage falls below the reference hysteresis. Then, the comparator turn s on t he switch allowing the output voltage to rise again. As mentioned previously, this techniqu e is fast, simple, and low -cost while i ts disadvantage is the varying switching frequency [38] [39] In steady state the hysteretic window VH limits the output voltage ripple, and thus we can deriv e t he switching frequency a s H C IN SLV D D r V f 1 (2 1 8 ) w here rC is th e ESR of the output capacitor. A second disadvantage is that this control sch eme requires a triangle like voltage ripple for stable operation. Thus, the ESR of the output capacitor can not be too small [40] Otherwise t he output voltage will not cross the hysteretic comparator thresholds in phase, and the contr ol scheme will not operate in a smooth and stable manner Typically, an electrolytic capacitor is used for COUT to meet this voltage ripple requirement.

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39 VINHysteretic ComparatorL VX VREFrL IOCOUTVO +Bridge drivers rCVINHysteretic ComparatorL VX VREFrL IOCOUTVO ++Bridge drivers rC Figure 2 11. Single phase voltage mode hysteretic buck converter VINHysteretic ComparatorL VX VFBVREFrL IOCOUTVO +Bridge drivers ON time one shotVINHysteretic ComparatorL VX VFBVREFrL IOCOUTVO ++Bridge drivers ON time one shot Figure 2 1 2 Single phase constant ontime buck converter T he constant ontime (COT) control is a modifi ed version of a conventional voltage mode hysteretic control. In a COT control ler the on time of the upper switch is fixed and the off -time is varied according to a reference voltage [41] The implementation of the control scheme is shown in Figure 2 12. A comparator samples the output voltage VO at a fixed sample frequency and compares it to the reference VREF. When VO
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40 T hus the switching loss is greatly reduced with slower frequency in light load s This control scheme provides the advantage of high efficiency in ultra light loads and is ideal for the converter in standby mode. However, a COT con troller used with a va rying input supply results in variable input to -output energy transferred per switching cycle producing widely var ying ripple and average output voltages [43] 2. 4 Multiphase Technique Mul tiphase dc dc converters are often used in computer power supplies to convert the 12V supply to roughly 1 V. This technique is suitable for modern microproc essors which require ~100A current and have very tight ripple requirements ( ~ 10mV). Typical motherboard power supplies use 3 or 4 phases, although control IC manufacturers allow as many as 6 phases [44] This t echnique is often used with the synchronous buck topology where the basic buck converter s are placed in parallel between the input and load. IL1IL2 IL_tot IL_tot RLC CLK1 IL1 L1 Controller CLK2 IL2 L2 Controller IL1IL2 IL_tot IL_tot RLC CLK1 IL1 L1 Controller CLK2 IL2 L2 Controller IL_tot RLC CLK1 IL1 L1 Controller CLK2 IL2 L2 Controller (a) (b) Figure 2 1 3 (a) Basic 2 phase synchr onous buck converter topology and (b) current waveforms Fig 2 13 shows a basic 2 phase buck converter with a dashed line to represent the feedback network There is 180 degree phase shift between CLK1 and CLK2, so the inductor current IL1 and IL2 also has 180 degree phase shift. After adding these inductor current s together, the ac

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41 components are cancelled which results in a smaller current ripple per total inductor current output IL_tot. Therefore, we can achieve smaller voltage ripple with the same LC filter or we can use a smaller sized LC filter to obtain the same ripple performance. Another important advantage provided by the multiphase converter is that the load current split s among the n phases of the multiphase converter allowing the heat genera tion on each of the switches to be spread across a larger area. N=2 N=3 N=4 1.0 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1.0Duty Cycle 0.1 0.3 0.5 0.7 0.9IL_tot/IL N=2 N=3 N=4 1.0 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1.0Duty Cycle 0.1 0.3 0.5 0.7 0.9IL_tot/IL Figure 2 1 4 Inductor current cancellation effect affected by the number of phases (N=2,3,4) and duty cycle. In the multiphase buck converter, the staggered operation of each phase produces a current ripple cancellation effect at the output node where the total current IL_tot is integrated onto the output capacitor. For an ideal N phase buck converter, the ratio of the magnitudes of the output current ripple L_tot to the current ripple L by the following expression [45] : D D D N m N mD N I IL tot L 1 1_ (2 18)

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42 where m=floor(N is the maximum integer that does not exceed N N is the number of phases and D is the duty cycle. Fi g. 2 14 s hows how the current ripple cancellation is affected by the number of phases (N=2, 3, 4) and duty cycle. Only at duty cycles of 1/N, 2/N, ,(N -1)/N, can the N -phase converter achieve ideal current cancellation with zero ripple output. On average converters with more phases have better ripple cancellation effect across most of the duty cycle range. A multiphase topology provides an additional benefit: the l oad response can be improved significantly because t he load is monitored by an N times higher s ampling frequency Additionally l arge increases /decreases in load current can be addressed by turning on/off multiple phases to improve the overall system efficiency [46]

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43 CHAPTER 3 MULTIP HASE SYNCHRONIZATION WITH DELAY LOCKED LOOP 3.1 Introduction Although there are numerous embodiments of step-down voltage regulators for near load power delivery systems, the switchedinductor multiphase and hysteretic controlled dc dc converter topology i s a suitable candidate as it exhibits a near instantaneous load response and ripple cancellation effect via current sharing [47] Unlike the pulse -width modulation (PWM) controller, the hysteretic controller exh ibits a faster load response and is inherently stable but is difficult to synchronize to multiple phases. For the controller to operate correctly, all bridge drive signals must be synchronized and staggered in time, and their duty cycles must be proportion al to the desired output voltage conversion ratio. Lack of synchronization leads to increased ripple voltage, slower response and larger inductor sizes. External synchronization of the multiphase hysteretic controller is feasible by direct injection of syn chronization signals into the reference voltage nodes of the hysteretic comparators [15] However, this approach requires that the amplitude, shape and frequency be carefully controlled to achieve proper frequency lock. Multiph ase topologies based on PWM controllers reported in [19] were synchronized using high frequency clocks in relation to the switching frequency and are therefore not suitable for very high frequency multiphase converters, whereas multiphase voltage -mode hysteretic controllers based on [14] exhibit an output conversion range limited to 1/N of the input voltage, where N is the number of converter phases, and therefore requires larger minimum input voltage when the number of phases increases. In this chapter, we demonstrate a synchronization scheme for high -frequency multiphase hysteretic controlled dc -dc converters using a delay locked loop (DLL) controller that achieves automatic phase synchronization wi th accurate duty cycle and large voltage conversion range. A

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44 four phase hysteretic buck converter was implemented in 0.5m CMOS process and is operational from 25MHz to 70MHz with an output voltage conversion range of 17.5 % 8 0 %. In section 3.2, we present a DLL based multiphase hysteretic buck converter design. Detailed analysis of the proposed converters performance is discussed in section 3.3. Simulation results, measurement results and concluding remarks are presented in section 3.4, 3.5 and 3.6, respec tively. 3.2 DLL Based Multiphase Hysteretic Controller 3.2.1 System Architecture The proposed DLL based multiphase hysteretic controller for a four -phase buck converter is shown in Fig. 3 1 The co nverter consists of four single phase modules, one of whi ch operates independently to set the desired output voltage from VREF and generate the reference clock (CKS0) for the DLL. The switching frequency and duty cycle is thus determined by the first hysteretic control loop, which can be digitally programmed by changing the value of the feedback resistor RF. When the DLL is locked, the synchronization signals (CKS90, CKS180 and CKS270) for the remaining converters are appropriately offset by 90, 180 and 270 to stagger the inductor currents for ripple cancellation. Using this method, the hysteretic controlled bridge and the remaining DLL controlled bridges are combined seamlessly without external driving clocks to synchronize the phases. In addition, the output voltage range is now determined by the attainable d uty cycle of the DLL, which is larger than previous designs [14] [15] To achieve proper synchronization between N output phases, the DLL must be able to 1) track the switching frequency of the mas ter hysteric controller, 2) maintain a 360o/N offset between each phase and 3) avoid duty cycle distortion in the bridge drive signals.

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45 L L Phase 180Phase 270 VPH180 VSENSE HystereticComparatorDLL L CFRF RD VIN VXA1 +VFB VREFR1R2 VPH0 VSENSEPhase 0 L CFRF RD VIN VX VPH90Phase 90 VPH270 VSENSE VSENSE IOCOUTVO Control bits CKS0 CKS0 CKS90 CKS270CKS180 Figure 3 1 Block diagram of DLL based four -phase interleaved dc -dc converter 3.2.2 Delay Locked Loop (DLL) Design Fig 3 2 sh ows the block diagram of the DLL controller. The DLL consists of three loops: a core loop for fine phase synchronization and two auxiliary loops for duty cycle adjustment and coarse phase tuning. The voltage control del ay line (VCDL) is composed of eight identical delay cells that are controlled primarily by the coarse loop via the main bias generator block. The coarse loop consists of two replica delay cells which are identical to the VCDL cells, an XOR phase detector a nd a charge pump (CP). At the input of the coarse loop, a divide by2 circuit

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46 divides down the reference clock (CKS0) from the output of the hysteretic comparator to produce a 50% duty signal. The XOR gate compares the divided down clock with the same sign al delayed by the two replica delay cells. Under locked conditions, the coarse loop voltage (VCOARSE) at the output of the charge pump forces the delay of the two replica delay cells to be approximately one fourth of the reference clock period. Since the s ame delay cells are used in the VCDL, the delay of the VCDL will be approximately equal to the reference clock period. It can be shown that by intentionally setting the coarse loop charge pump pull up current to three times the pull -down current, the DLL l ock range can be increased to 7:1 [48] PFDStartupCP LF CP LF /2 D D D D D D D D D D VDD/2 CP LF VPcoarseVNcoarseVCOARSEVFINEUP1 UP2 DN2 DN1 VPcoreVNcore VCDL Core Loop Coarse Loop Duty Cycle Loop VDUTY CKS90CKS180CKS270 CKS0 from hysteretic comparator To bridge drivers CKS360 CKS0 Bias Gen Bias Gen Figure 3 2 Block diagram of DLL based synchronization controller

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47 CKS0UP1 DN1(UP2) (DN2)CKS360 CKS0CKS360 Figure 3 3 Representative timing waveforms of core and duty cycle loops Fig. 3 3 shows timing waveforms of the core and duty cycle loops. The core loop compares the outputs of the hysteretic comparator (CKS0) and the VCDL (CKS360) using a phase frequency detector (PFD) to fine tune the VCDL. Up (UP1) or down (DN1) pulses proportional to the phase difference of the input clock signals are generated by the PFD and fed to the chargepump (CP) to produce a proportional current filtered by a first order loop filter (LF), thereby reducing or increasing VFINE until the cl ock edges are aligned by the negative feedback loop of the DLL. As shown in Fig. 3 3 the duty cycle of the reference clock generated by the hysteretic comparator can deviate from 50%. A dedicated duty cycle loop is used to correct for mismatch arising fr om unbalanced rise and fall times in the VCDL. Since the duty cycle of the reference clock signal CKS0 at the output of the hysteretic comparator determines the buck converter voltage conversion ratio, the VCDL must maintain accurate duty cycle across all its phases to ensure proper current sharing operation of the multi phase converter. The duty cycle correction loop comprised of a charge pump and loop filter operates on inverted CKS0 and CKS360 signals (or UP2 and DN2) to generate a voltage VDUTY proporti onal to the error in pulse widths. The voltage VDUTY is used to change the current ratio in the delay cells and adjust the duty cycle of the VCDL.

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48 3.2.3 Circuits Implementation 3.2.3.1 Delay c ell Fig. 3 4 show s the basic VCDL delay cell configuration It is composed of two current starved inverter delay cells (DC), one duty cycle delay (DCD) cell and two inverters, one to buffer the following delay stage and the other to buffer the input of the drivers to the dc -dc bridges. The current starved delay cells (DC) are controlled using VPcore and VNcore from the bias generator circuit. These control signals are determined by VFINE and VCOARSE from the core and coarse loops and used primarily to adjust the delay and align the rising edges of reference clock and V CDL output. VDUTY is used to adjust the current ratio of the DCD cell to ensure proper duty cycle matching. Since the duty cycle is applied to all the delay cells, the duty cycle is preserved for all output phases. Although VDUTY is adjusted simultaneously with VPcore and VNcore, a sufficiently smaller loop gain in the duty cycle correction loop ensures overall DLL loop stability. The relative gain of VFINE and VCOARSE over the VCDL can be adjusted using a V I current summing circuit in the bias generator t o produce voltages VNcore and VPcore that directly control the delay cells. The bias generator circuit employs two weighted current sources (P1 and P2) to control the coarse and fine delay tuning range, respectively, and a current sink IMIN to set the mini mum bias current and thus the maximum delay of the delay cells. In the coarse loop VDD/2 is applied to the bias generator instead of VFINE and the control voltages VPcoarse and VNcoarse control the replica delay cell (see Fig. 3 2 ). 3.2.3.2 Phase frequency d etector and s tartup c ircuit Schematic of the phase frequency detector (PFD) is provided i n Fig. 3 -5 The PFD is comprised of a conventional sequential PFD and a startup circuit. The startup circuit is used to disable the charge -pump for eight reference c ycles and reset the core loop control voltage (VFINE) to mid voltage (i.e. VDD/2) in the event of lock failure when VFINE drops below 0.1V. Lock

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49 failure problem for the core loop might occur at the startup condition before the coarse loop is locked, and the core loops control voltage VFINE is stuck at ground potential. In this case, the startup circuit generates a zero pulse from the latched comparators output as the reset signal. After eight reference cycles, the reset signal becomes 1 to restart the c ore loop. VPcore VNcore in out VPcore VNcore in out Bias Gen DC DCD Delay cell duty cycle control VDUTY Current starved delay cell DC DCD DC in out VDUTY VFINEVCOARSE to bridge drivers VFINEVCOARSE VPcore VNcore P1P2 IMIN Bias Generator Figure 3 4 Block diagram and schematic of delay cells UP DN CKS0 CKS360 D QQPhase Frequency DetectorresetCKS0 8 Startup Circuit 0.1V 0.5VDD VFINEFrom CP/LF Figure 3 5 Circuit schematic of the phase frequency detector

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50 3.2.3.3 Charge p ump and l oop filter The static phase offset in the DLL mainly stems from the timing mismatch in phase detecto r and the current mismatch in the charge pump. By matching the up and down signal propagation paths in phase detector, the phase detector mismatch can be neglected given the moderate operating frequencies. Therefore, the dominant source of static phase err or is caused by charge pump current mismatch which can be approximated as: CP CP S ONI I T T (3 1 ) where TS and TON are the reference period and the charge pump on time, respectively; CP is the charge pump current mismatch and ICP is the charge pump current. Notice that the charge pump mismatch is more relevant in the auxiliary duty cycle loop as the on time is equal to the duty cycle of the converter ( D ). Startup DN UP UP VOP1 P2 P3 N1 N2 N3 VRP4 P5 N5 N4Current Steering NetworkVN 2DN UP Loop Filter VODN ICH Charge Pump Figure 3 6 Circuit schematics of charge pum p/loop filter (CP/LF) The charge pump circuit in Fig. 3 6 provides accurate current matching to reduce static phase error [49] Static phase error or offset in the DLL stems mainly from timing mismatch in phase frequency detect or and current mismatch in the charge pump. Timing mismatch in the PFD is mitigated by matching the up and down signal propagation delays. The charge -pump

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51 consists of matched PMOS current sources P1 -P3 and the NMOS current sinks N1 N3, with minimum sized M OS switches in between to reduce the effect of charge feedthrough. An error amplifier inserted between the current mirrors improves current matching by forcing VR equal to VO, such that when UP is enabled the source currents are equal ( IP2=IP1=IN1), and wh en DN enabled the sink currents are equal ( IN2=IN1=IP1). In addition, a current steering network comprised of N5 and P5 legs is used to minimize current spikes across the output capacitor filter. When switch N4 is disabled, the complementary N5 switch turn s on to maintain the N2 drain voltage (VN2) stable. Without the current steering legs the drain node of N2 can be discharged to ground leading to current spikes at the switching instants of the UP and DN signals. The schematics for the CPs and LF s in all t hree loops (see Fig. 3 2 ) are the same, except in the coarse loop where the P2:P1 current ratio is set to 3:1 instead of 1:1 as the pull up current is three times the pull -down current for improved DLL locking range [48] In ad dition, the current to loop-filter capacitance ratio are 3x190A/18pF, 130A/12pF and 45A/18pF for the coarse, fine and dutycycle loops, respectively. 3.3 Analysis for DLL based Multiphase Buck Converter 3.3.1 Voltage Conversion Range The voltage conver sion range is largely determined by the duty cycle range that is attainable by the DLL based controller. As shown in Fig. 3 7 since the output voltage is proportional to the duty cycle, the maximum output voltage VOmax is DmaxVIN and the minimum output vo ltage VOmin is DminVIN, where Dmax and Dmin are the maximum and minimum duty cycles of the DLL, respectively. The duty cycle range in turn is related to the locking range of the DLL. As indicated in Fig. 3 7, for the DLL to lock properly without stuck or harmonic lock problems under worst -case conditions, the minimum VCDL delay ( TVCDLmin) should be located between

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52 DmaxTS < TVCDLmin < TS, and the maximum VCDL delay ( TVCDLmax) between TS < TVCDLmax < (1+Dmin)TS, where TS is the clock reference (CKS0) period f rom the output of the hysteretic comparator. DLL locking range PVT variations ( Dmax)TS VOmax= DmaxVIN (1 Dmin)TS VOmin= DminVIN ( Dmax)TS (1+Dmin)TS TS (1 Dmax)TS ( Dmin)TS Figure 3 7 Derivation of DLL locking range for minimum and maximum duty cycles As described in the previous section, the frequency range of the DLL improves as the control voltage VCOARSE of the replica dela y line forces the VCDL delay to be approximately TS. However, stuck -free conditions in the core loop should still be satisfied for minimum and maximum duty cycles to avoid harmonic lock issues. As show n in Fig. 3 7 the margin for stuck free operation decr eases when the duty cycle is too large or too small, as the initial VCDL delay may deviate from TS causing the DLL to fall into harmonic lock. Since the coarse loop provides only coarse delay tuning for a wider frequency range, an initial delay error exist s. For instance, the delay cells in the replica delay line and VCDL, although identical, can have delays which are not exactly the same as this would require the control voltages in the delay cells of the two delay lines to be identical (i.e. VNcore=VNcoar se, VPcore=VPcoarse and VDUTY equal to one -half the supply voltage as shown in Fig. 3 2 ). Therefore, while VCOARSE of coarse loop sets the maximum tuning

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53 range of the VCDL, it limits the attainable duty cycle range of the DLL. If the coarse loops maximum phase error is about 5%~10% of the period based on the duty cycle and PVT variations, the maximum tuning range of the core loop should be set larger than 10% for fine tuning. Consequently, the attainable duty cycle range of this DLL is approximately 20% to 80%. 3.3.2 Voltage Ripple As shown in section 2. 3 in multiphase buck converter s the staggered operation of each phase produces a current ripple cancellation effect at the output node where the total current IL_tot is integrated onto the output capacitor (COUT). For an ideal N -phase buck converter, the ratio of L_tot L flowing in each phase Eq. 2 1 8 Since the total charge dumped and removed from the IL_tot/(4 NfS) according to Eq. 2 4 in Section 2.1.3, the voltage ripple for an ideal N phase buck converter can be expressed as 2 2 _8 1 1 1 8S OUT IN OUT S tot L ripplef LC V D D N m D N m C Nf I V (3 2 ) and the peak to -peak ripple is 2 ripple. From this equation the ripple volta ge decreases inversely to the square of the switching frequency. Hence, for a constant ripple voltage, a 10X increase in switching frequency decreases the required LC value by 100X to yield faster transient response. The ripple voltage is further decreased by increasing the number of phases N, although it should be noted that for D<1/N and D>(N -1)/N the effectiveness of multiphase ripple cancellation diminishes as indicated by Eq. 3 2 3.3.3 Effects of Phase and Duty Cycle Mismatch The above derivation does not take into account the effect of duty cycle and phase mismatch among the individual phases. In the proposed DLL based controller, deviations in output phase are caused by the static phase error of the charge pump whereas duty cycle errors

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54 are caused by inaccuracies from the duty cycle loop. As shown in Fig. 3 8 a, a small phase error -shift proportional to TS between the input and output of the VCDL (i.e. between CLKS0 and CLKS360), where The phase error i for i -th phase in the VCDL, or equivalently ii can be expressed in terms of the total phase error as N i for N i i 2 1 (3 3 ) ILi DTS ILiILi iTS Vi ILiILDi ILDi VDiDTSDiTS (a) (b) Figure 3 8 Derivation of ripple voltage due to (a) phase and (b) duty cycle errors If we assume only the inductor current of the i -th phase IL i experiences an error of i TS, a leading version of the current I i is generated while the other phase currents remain the same (see Fig. 3 8a). This timing mismatch produces an extra current ripple i which can be modeled as a square pulse for small i with a peak to -peak value of D D I T D T I DT T I Ii L S S i L S S i L i L 1 1 (3 4 a) This integral of the extra current ripple results in a triangle -wave voltage ripple V i on the output capacitor with a peak to peak value of i OUT S L OUT S S S i L iC f I C DT DT T I V (3 4 b)

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55 The effect of duty cycle errors on ripple voltage at each phase of the VCDL can be estimated using a similar procedure. As shown in Fig. 3 8b, D from input to output of the VCDL (i.e. between CLKS0 and CLKS360) causes a timing mismatch of D TS. The duty cycle error for the i th phase can be expressed in terms of the VCDL duty cycle error as N i for N iD i D 21 (3 5 ) As shown in Fig. 3 8 b, if the duty cycle error of one phase is considered, the ripple current generated as a result is D D I Ii D L i LD 1 (3 6 a) The corresponding voltage ripple VD i has a peak to -peak of i D OUT S L OUT S S S i D L i DC f I C DT DT T I V 2 2 (3 6 b) From Fig. 3 8 t he peaks and valleys of the voltage ripples V i and VD i occur at ap proximately the same relative timing corresponding to the ideal inductor current ripples. The peak ripple voltage due to phase and duty cycle errors occur at the output of the N -th phase when i=N= (N -1/N) and D i=N= (N -1/N) D. Thus, the worst -case ripple due to phase and duty cycle error contributions for the DLL based controller can be approximated as D OUT S L DC f I V V 5 0 (3 7 ) As shown in Fig. 3 9 a, d uty cycle mismatch also produces a DC current imbalance among the converter phases and as a result, an increased conduction loss in the power train resistances [27] [50] This dc conduction loss is minimized when the dc voltage drops across the power train resistances for all phases are equal, or equivalently when the average voltages at the bridge

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56 outputs are equal, with the constraint that the sum of the individual phase currents must equal the total load current [47] Sin ce t he cumulative effect of duty cycle errors generated by the VCDL in the DLL based controller will produce corresponding differences in bridge output voltages, it is worthwhile to investigate the impact on overall dc conduction efficiency. To estimate the dc conduction loss we employ the DC current sharing model of an N -phase converter shown in Fig. 3 9 b, where resistors R1, R2, RN model the dc resistances of each phase and V1, V2, VN model the average open -circuit voltage for each phase. The power train resistances Ri can be estimated from the weighted average of the series resistances of the high side ( RHS i) and low -side ( RLS i) switches and the inductor DC resistance ( rL i) of the i th phase given by i L i LS i i HS i ir R D R D R 1 (3 8 ) IL2 IL1 IL I12 IO IL2 IL1 IL I12 IO (a) VOR1IL1R2IL2RN ILNV1=VIND1V2=VIND2VN=VINDN IO Converter phase N Converter phase 2 Converter phase 1 (b) Figure 3 9 (a) DC current imbalance in a 2 phase converter and (b) DC current sharing model of a N -phase converter

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57 For any converter phase i the duty cycle error in the VCDL phases can be described by Eq. 3 5 which produces unequal voltages V1, V2, VN as a result of duty cycle mismatch among the phases. To evaluate the impact of duty cycle error we assume equal power train resistances R1= R2== RN=R. Then the average current mismatch IL i:i 1 between adjacent phases is given by N i N R V D D R V I I ID IN i i IN Li Li i i L 3 21 1 1 : (3 9 ) where the average inductor current IL i is N i I i N N I Ii i L O Li 3 2 1 2 2 11 : (3 1 0 ) It follows that the total dc conduction power loss PRD due to the power train resistances is R I PN i Li RD1 2 (3 1 1 a) which, after simple algebraic manipulations, can be expressed as 12 1 12 1 : 2 N N N R I R N I Pi i L O RD (3 1 1 b) Ideally when all phases have the same duty cycle, IL i:i 1 equal s zero and the dc conduction loss is RIO 2/N Since the input power PIN equals VINDIO, the corresponding conduction efficiency is D NV R I P PIN O IN O cond 1 (3 1 2 ) Substituting the expression for average current mismatch IL i:i 1 and efficiency cond into PRD yields 2 2 2 2 2 2 2 21 12 1 1 1 12 1 1 D R N I D N N R N I PD cond O D cond O RD (3 1 3 )

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58 where IO 2R/N is the ideal the dc conduction loss of the power train when the duty cycles applied to the different phases are identical, and cond=PO/PIN is the conduction effic iency and < D > is the average duty cycle. For example, if a 4 phase buck converter with an ideal duty cycle of D=0.2 has a conduction efficiency of 90%, then a duty cycle error of D=5% will increase the dc conduction loss by 48.8%, dropping the overall con duction efficiency to about 85.8%. 3.3. 4 Effect of Inductor Mismatch Mismatch in passive components can also lead to unbalanced c urrent distribution between converter phases and reduce the effectiveness of ripple cancellation in interleaved converters. For instance, the maximum number of converter phases N for a given inductor tolerance and conversion ratio is given by [51] : (%) 100 ) 1 ( 1 2 1 L D D NMAX (3 1 4 ) and voltage conversion of 20%80% NMAX is then less than 5 representing that the number of phases should be limited to 5 for effective ripple cancellation. (Additional ph ases lead to diminishing effect because the cause of ripple current and voltage is dominant by the mismatched inductor current). The mismatch due to on -chip passives (RD, RF and CF in Fig. 3 1 ) can be minimized to within 1 2% with proper layout techniques. Moreover, the mismatch effect of power transistor s is small given their large areas. 3.3. 5 Effect of DLL on Transient Response The hysteretic controlled dc -dc converter exhibits a fast load response as the voltage droop at VO directly couples to VFB of th e hysteretic comparator via the high -pass RF and CF feedback network (see Fig. 2 9 RC (or RFCF) time constant couples a larger voltage from the output to VFB of the hysteretic comparator and imp roves the transient response [36] But

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59 as indicated in Eq. 2 14b, this also decreases the switching frequency. Since the switching frequency also affects the ripple voltage, there exists a tradeoff between droop response and ripple voltage. From Eq. 1b, both the hys teretic window VH and the converter delay D provide an additional degree of freedom to adjust the switching frequency. In order to determine the effect of the DLL based multiphase controller on response time, we assume the hysteretic control loop has negligible delay. Therefore, an abrupt chang e in load IO will couple all N inductors immediately to either ground or VIN. That is, at steady state the multiphase converter staggers the phases for ripple cancellation, and during a load transient it operates temporarily as a single phase converter with an effective switched inductance of L/N for a faster load response. Neglecting the effect of finite converter propagation delay, the inductors in the N phase converter needs time TIND to accommodate a current change of O [15] 0 0O O IN O O O O INDI V V I N L I V I N L T (3 15) Note that TIND assumes the converter accommodates the current demand within one cycle. As shown in Fig. 3 10, when a low to O) is applied to an N phase converter with D= 1/N (i.e. when a single phase is on at any given time), the slope of the output current under small ripple approximation increases from (VINVO)/L in steady state operation to N(VINVO)/L during the a transient event. The net change in the slope of the out put current of the N -phase converter compared to a single phase converter is therefore (N -1)(VINVO)/L as illus trated by dotted lines in Fig. 3 10.

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60 VPH0VPH90VPH180VPH270 IO IOinductor current changeIL time A B C D E0.25 TS0.5 TS0.75 TSTS0 0.5 TS k=IL/t 3k 2k k slope= 3k Figure 3 1 0 Derivation of DLL based controller load response for a four -phase (N=4) buck converter. In contrast, a DLL based controller has only a single hysteretic comparator that accommodates load changes, and the corresponding control signal from the comparator (i.e. CLKS0 in Fig. 3 1 ) is p ropagated through the VCDL to update the remaining converter phas es. Therefore, the converter phases turn on sequentially until all phases are coupled to VIN when a low to -high current step is applied, effectively delaying the response of the overall converter, as shown by the solid li ne in Fig. 3 10. Thus t he DLL effec tively delays the response of the overall converter. By simple inspectio n of Fig. 3 10, the DLL delays the response by 0.5TS. For the general case of an N -phase DLL based converter, the additional delay can be defined as the time difference TBTC, or TBC. From Fig. 3 10 it c an be shown that the triangle formed by nodes A, B and C, or triangle ABC, is proportional to triangle ADE. It follows that IAB/IAD equals TBC/TDE and thus

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61 AD BD DE BCI IT T 1 (3 16a) The ratio IBD/IAD can be expressed as 1 2 2 1 1 2 2 1 N N N N N I IAD BD (3 16b) and TDE as S DET N N T 1 (3 16c) Therefore, the response of DLL based controller is delayed by an additional 2 1 2 2 1 1S S BCT N N TN N T (3 16d) The transient response of the DLL based converter can be expressed as 2 S IND DLL INDT T T (3 17) where TS is the converter switching period. Thus, the DLL based controller exhibits a worst -case load response that is on average half a cycle sl ower than the typical multiphase hysteretic controller. This also applies when the duty cycle is smaller than 1/N, whereas for larger duty cycles the response is better than predicted b y Eq. 3 17. 3.4 Simulation Results 3.4.1 Loop Dynamics Fig. 3 1 1 a sho ws the startup loop dynamics of a DLL based converter configured to operate at 50MHz with an output voltage of ~3.5V. As noted in Section 3 2.2 control voltages VCOARSE and VFINE are used by the coarse and core loops to adjust the cell delays, respectivel y, and VDUTY is used to correct the duty cycle across the multiphase signals. During startup, the

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62 output voltage increases rapidly and the hysteretic controller, which operates independent from the remaining converter phases, sets the reference clock frequ ency (CKS0) and duty cycle for the DLL. In Fig. 3 11a, the converter output reaches 3.15V (or 90% of 3.5V) within 100ns or 5 reference cycles. To ensure loop stability, the DLL bandwidth is set smaller than the hysteretic controller bandwidth. Thus, VCOARS E exhibits a slower response and settles within 2s or approximately 100 cycles at 50MHz. The ripple in VCOARSE stems from the intentional 3:1 charge -pump current mismatch (pull up current is 3x the pull down current) to improve the DLL locking range. Once the coarse loop settles the VCDL phases are approximately staggered by 90 degrees and the core loop tracks the input reference to fine tune the VCDL. The duty cycle loop also tracks at a much slower response time to correct for duty cycle errors across al l phases. The DLL locks in approximately 8s, and the phase and the duty cycle errors between CKS0 and CKS360 are 0.3% and 0.6%, respectively, resulting in a maximum current imbalance of 5mA between phases. Fig. 3 1 1 b shows the loop response to a 10% line step from 5V to 4.5V. In order to understand how an input step affects the loop dynamics, we consider the relation between input step and switching frequency for the hysteretic controller. A highto low input step causes an increase in duty cycle D, and si nce D>0.5 as VOUT>0.5VIN, the step causes a decrease in frequency according to Eq. 2 1 4b (Section 2 3 .2.1 ). Thus a highto low input step is seen as a decreasing frequency step by the DLL. As a result the coarse and core loops react by increasing VCOARSE a nd VFINE to increase the replica and VCDL delays, respectively (i.e. an increase in control voltage slows the delay cells). Since the coarse loop and the replica delay cells do not depend on the VCDL feedback reference, VCOARSE settles once the replica del ay is approximately of the reference clock (CKS0) period. At this point, VFINE and VDUTY track the input reference

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63 to adjust the VCDL delay and duty cycle, respectively, with a slower response in the duty cycle loop. A similar but opposite behavior is ob served for the low to -high input voltage step. 0 2 4 6 8 10 12 14 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Voltage (V)Time ( s)VOUTVDUTYVCOARSEVFINE (a) 4 6 8 10 12 14 16 18 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Time ( s)Voltage (V)VOUTVDUTYVCOARSEVFINEVIN (b) Fig ure 3 1 1 Simulated loop response during (a) startup and (b) line step.

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64 3.4.2 Duty Cycle Error and Current Mismatch Fig. 3 12 shows the inductor currents and the ripple cancellation as a result of duty cycle variation when the DLL is synchronized (or locked) and un -synchronized (or un locked). Prior to locking the duty cycle loop, a duty cycle deviation of 1.4% causes severe current imbalance (Fig. 3 12a). Once the duty cycle loop of the DLL is locked, the static duty cycle error is approximately 13ps and nearly equal current distribution is achieved. The results are summarized i n Table 3 1 (a) (b) Figure 3 12. Four phase inductor current s and ripple cancellation (a) b efore the duty cycle loop is locked (b) a fter the duty cycle loop is locked

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65 Table 3 1. Duty cycle and current -sharing analysis of the DLL controller for locked and unlocked st ates Fig. 3 1 2 a Fig. 3 1 2 b Max. duty cycle 68.4% 67.5% Min. duty cycle 65.6% 67.4% Duty cycle deviation (Max. duty-Min. duty)/2 1.4% 0.05% Phase 1 current (mA) 203.8 157.4 Phase 2 current (mA) 176.7 156.7 Phase 3 current (mA) 153.4 155.4 Phase 4 current (mA) 102.5 153.4 Inductor ripple current (mA) 200 196 Output ripple current after cancellation (mA) 62 46 Output voltage V O (V) 3.130 3.153 3.5 Measurement Results A four -phase integrated buck converter was fabricated in standard 0.5m 5V CM OS process to verify the proposed DLL -based hysteretic controller. The die photo is shown in F ig. 3 13. The converter is operational from 25MHz to 70MHz and occupies approximately 2.8mm by 2.8mm, which includes a 3.3nF on-die capacitor. The DLL controller measures roughly 0.6mm by 0.4mm. The converter performance was evaluated using four SMT size 805 220nH air core inductors with quality factor of 25 at 30MHz and various external chip capacitors ranging from 4.7nF to 47.7nF.

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66 2.8mm2.8mm Capacitor DLLHysteretic comparator RC filter4 -phase buck converter bridge Load Figure 3 1 3 Die photo. 3.5.1 Four Phase Operation Staggered operation of the four bridge outputs are shown i n Fig. 1 4 a and 1 4 b for switching duty cycles of 17.5% to 80%, respectively. For a ~4.9V input voltage, this is equivalent to an output voltage range of 0.86V to 3.93V. This wide range is made possible by the DLL controller, which accurately tracks the wide range of input frequency and duty cycle and maintains the 90o offset among the phases to cancel out the ripple, indicating proper phase synchronization and duty cycle accurate operation of the controller. The jitter histogram of the controller output phase in Fig. 3 1 5 ind icates a ~6.3ps rms and 47ps peak to peak jitter. At 30MHz, the peak to peak jitter corresponds to only 0.14% of switching period and has a negligible effect on ripple cancellation of the multiphase converter.

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67 20ns/div1V/divVPH0 VPH90VPH180VPH270 10ns/div1V/div VPH0VPH90VPH180VPH270 (a) (b) Figure 3 1 4 Measured bridge output waveforms with 220nF/phase (a) VOUT=0.86V, D=17.5 %, 32MHz and (b) VOUT=3.93V, D=80%, 42MHz. RMS jitter 6.332ps Fig ure 3 1 5 Measured jitter while dc -dc conver ter is operational 3.5.2 Frequency Dependence Fig. 3 1 6 sho ws the measured bridge switching frequency and duty cycle for load current of 0.5A as the input VREF is swept. The DLL controller automatically adjusts the duty cycle to set the desired converter o utput voltage. The measurements show the expected linear dependence of output voltage with input duty cycle. Also as predicted in S ection 2.3.2.1 the measured

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68 converter switching frequency exhibits the characteristic parabolic dependence on input duty cyc le, with a maximum occurring at 50% duty cycle. The measured peak to peak ripple voltage is 2 10% of the output voltage depending on the conversion ratio. The measured ripple performance is slightly worse than expected due to noise coupling from the on chi p ground to the output node, which can be improved with better isolation between the grounds of the switching converter and the output load. 0 10 20 30 40 50Frequency (MHz)0 20 40 60 80 100Duty Cycle (%)Output Voltage VOUT(V) 0 0.5 1 1.5 2 2.5 3 3.5 4 Fig ure 3 1 6 Measured switching frequency and duty cycle vs. output voltage as VREF is swept for ILOAD=0.5A 3.5.3 Efficiency The measured power efficiency versus load current for 4.8V/3.3V conversion is shown in Fig. 3 1 7 The pe ak efficiency of 83% is achieved for a load current of 0.6A at 3.3V, or an output power of about 2 Watts. Increasing the load current decrea ses the efficiency due to higher conduction losses associated with the inductor and bridge resistances, whereas at lighter loads the bridge switching losses dominate. For the 220nH SMT air core inductors, the efficiency is optimum at a switching frequency of 26MHz 30MHz.

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69 Load Current ILOAD (A)Efficiency (%) 50 55 60 65 70 75 80 85 90 0 0.2 0.4 0.6 0.8 1.0 Figure 3 1 7 Measured efficiency for VIN=4.8V, VOUT=3.3V, 220nH/phase and 26MHz 30MHz 3.5.4 Transient Response Fig. 3 18 shows the transient response to a 0.3A load step generated using an external device with measured rise and fall ramp times of 30ns and 10ns, respectively The converter response was measured for several conversion ratios at an input voltage of 4.9V. For each case, the operating frequency was adjusted by changing the delay of the hysteretic controller and the feedback re sistor RF using control bit settings (see Fig.3 1 ). The measured frequency over the range of output voltages was 32MHz 35MHz. For all cases shown in Fig. 3 18, external SMT inductors of 110nH/phase were used with a total output capacitance of 51nF. The wor st -case droop for both low to -high and high to low steps was approximately 250mV, which corresponds to a droop of less than 10% for our target conversion of 4.9V/3.3V. The output has a steady-state error of about 100 mV which was intentionally introduced b y voltage positioning, as discussed in Section 2.3.2.1.

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70 (a) (b) (c) (d) Fig ure 3 18. Measured load response for 0.3A current step, L=110nH/phase and C=51nF ov er several output voltages VOUT (a) 1.8V, (b) 2.5V, (c) 3.3V and (d) 3.7V. The step voltage shown is applied to an external device to generate the current step. 0 5 10 15 20 25 30 100 300 Output capacitance ( nF)Voltage droop (%) 10% 0 100 200 300 400 500 0 2 4 6 8 1.8V 2.5V 3.3V 3.7VL/C of output filter ( nH/nF )Voltage droop (mV) 1.8V 1.8V 2.5V 2.5V 3.3V 3.3V 3.7V 3.7V 220nH/phase 110nH/phase (a) (b ) Fig ure 3 19. Output voltage droop for a 0.3A current step and output voltage range of 1.8V 3.7V with 110nH and 220nH inductance per phase (a) percentage of voltage droop as a function of output filter capacitance and (b) voltage droop vs. L/C output filt er ratio.

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71 2.8 2.9 3.0 3.1 3.2 3.3 3.4Voltage (V)0 0.2 0.4 0.6 0.8 1.0 1.2 Time ( s)220nH, 33nF 220nH, 51nF 110nH 51nF 110nH 33nF 220nH, 187nF 110nH, 187nF 3.1 3.2 3.3 3.4 3.5 3.6 3.7Voltage (V)0 0.2 0.4 0.6 0.8 1.0 1.2 Time ( s)220nH, 33nF 220nH, 51nF 110nH, 33nF 220nH, 187nF 110nH, 51nF 110nH, 187nF (a) (b) Fig ure 3 20. Measured output voltage at 4.9V/3.3V conversion using various inductors and output capacitors for 0.3A (a) low -to high and (b) highto low curre nt steps Fig. 3 19a shows the measured percentage of voltage droop over a range of output voltages as a function of output capacitance for two sets of inductors per phase. It is apparent from Fig. 3 19a that the ratio of peak output voltage deviation and n ominal output voltage increases for smaller output voltages. For fixed converter parameters this relative increase is due to the smaller output voltage and can be corrected by adding output capacitance and/or decreasing the inductance/phase. As shown in Fi g. 3 19b, the actual voltage droop decreases with smaller L/C ratio of the output filter. In addition, the droop is also affected by the controller characteristics. For the hysteretic contro RC improves the transient response but also decreases the operating frequency and degrades the ripple. As discussed in Section 3.3.5 this can be compensated by adjusting the hysteretic window VH D. In the present RC is limited by the range of the on -chip programmable resistor RF RC cannot be further increased to improve the converters voltage droop. Thus, further improvement in droop requires additional output capacitance. Fig. 3 20 shows close -in measurements of the output voltage transient response at 4.9V/3.3V conversion. The transient behavior of the hysteretic converter is largely determined

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72 by the slew rate of the inductor currents and thus improves with smaller inductance/phase. Increasing the output capacitor decreases the voltage droop at the expense of response time. For 110nH/phase and 33nF output capacitance, the voltage droop is within 10% of the output voltage. As mentioned previously, the 10 0mV steady state voltage drop at the output is due to the resistive response int roduced by voltage positioning [37] The ripple voltage is approximately 20mV and the measured response time is less than 3 cycles at 32MHz. This r esponse time is larger than TIND_DLL in Eq. 3 17 as the derivation assumes the converter accommodates the current step within one cycle. In addition TIND as reported in [15] does not include the propagation delay of the feedbac k loop. The DLL based controller introduces additional delay as only one hysteretic controlled phase responds to an applied load step and all remaining phases follow on average after one half of the switching period. However, the response time is still fas ter than the widely used pulse -width modulation (PWM) controller, which is about five to ten cycles 3.5.5 Performance Summary Table 3 2 summarizes the measured dc dc converter performance. Th e dc -dc converter can deliver 3.3W at 80% efficiency and approximately 2W with a peak efficiency of 83% [52] Table 3 3 shows a comparison with previously reported on-chip buck converters implemented using similar process techn ology [54] [56] Our design has an output power rating that is at least 2x larger than the reported implementations. Although the efficiency is slightly lower, the high operating frequency coupled w ith the multiphase technique reduces the required inductor and decoupling capacitor values. Table 3 4 shows a performance comparison with previously reported integrated hysteretic and multiphase converters [15] [57] [59] Among the reported converters, only [15] and this work utilize both the multiphase and hysteretic control techniques and thus combine their advantages in one topology for cu rrent staggering, LC filter size

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73 reduction and fast transient response. However, the synchronization scheme in [15] requires that the amplitude, shape and frequency be carefully controlled to achieve proper frequency injection locking, while this work achieves automatic phase synchronization and duty cycle tracking for a wide input reference voltage range. Table 3 2. Performance summary Technology 0.5m CMOS 3M2P Chip area 7.84mm 2 DC DC converter area 3.3mm 2 Bridge area, A BR DG 0.6mm 2 Decoupling Capacitance 8 187nF Number of phases, N 4 Inductance / phase, L 110nH 220nH Input voltage, V IN 4V~5V Output voltage, V OUT 0.86V 3.93V Switching frequency, f 25M~70M Maximum current, I MAX 1A Current density, I MAX / A BRDG 1.67A/ mm 2 V IN =4.8V, V OUT =3.3V Efficiency (peak) 83% Efficiency @ I MAX 80% Table 3 3. Performance comparison [54] [55] [56] This Work [52] Year 2004 2007 2007 2007 0.6 0.5 0.5 0.5 # phases 1 1 1 4 V IN [V] 3.6 3.6 2.7 4.8 V OUT [V] 2 1.8 1.5 3.3 f[MHz] 0.5 3 0.78 ~30 Eff.[%] 89.5 89.1 85.6 83 L TOT [H] 4.7 3.3 3.9 0.22/phase C[F] 10 4.7 47 0.008 0.19 I MAX [A] 0.45 0.4 0.8 1 Area[mm 2 ] 2.87 5.3 4.5 3.3

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74 Table 3 4. Performance comparison [57] [58] [59] [15] This work [52] Year 2007 2006 2006 2005 2007 Tech[m] 0.13 CMOS 0.18 SiGe 0.09 CMOS 0.09 CMOS 0.5 CMOS Control Scheme PWM PWM PWM Hysteretic Hysteretic # phases 2 1 2 8 4 4 V IN [V] 1.2 2.8 2.4 1.2 4.8 V OUT [V] 0.9 1.8 1.2 0.9 3.3 f[MHz] 170 45 100 233 ~30 E ff.[%] 77.9 65 79 83.2 83 L[nH]/phase 2 11 0.8 6.8 110 220 C[F] 0.0052 0.006 8.8 0.0025 0.0080.19 I MAX [A] 0.35 0.2 20 0. 3 1 Area[mm 2 ] 1.5 27 10 0.14 3.3 1Stacked interleaved phases. 3.6 Summary A delay locked loop (DLL) based hysteretic control sch eme for high -frequency multi phase dc dc converters is presented. The controller generates multiphase synchronization signals with accurate duty cycle control directly from the output of a hysteretic comparator. The hysteretic control loop parameters and i nput reference voltage sets the switching frequency and additional external synchronization signals are not required. The proposed implementation requires only one hysteretic comparator since the additional phases are generated by the DLL. The dc -dc conver ter was implemented wide voltage conversion range of 17.5% to 80% and peak efficiency of 83% at ~2Watts for load current of 0.6A. The peak output power is 3.3W at an efficiency of 80%. The converter is operational from 25MHz to 70MHz. This technique can be easily scaled to advanced process nodes to achieve higher operating frequency and reduction in inductor size for ultra high-

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75 frequency converters. The proposed technique can be used to synchronize high-frequency multi phase h ysteretic dc -dc converters by adjusting only the input reference voltage, enabling fast power supply modulation or fast entry/exit power management strategies.

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76 CHAPTER 4 FREQUENCY SYNCHRONIZ ATION WITH DIGITAL P HASE LOCKED LOOP (DPLL) 4.1 Introduction Hyst eretic controlled multiphase switch -mode converters operated at ultra high frequencies upwards of 100MHz and with peak load efficiencies greater than 80% have been shown to provide extremely fast load response times of 1 5ns [15 ]. This enables several orders of magnitude reduction in capacitor (and inductor) size, potentially leading to highly integrated near -load power delivery solutions for high performance microprocessors requiring fast entry and exit strategies from multiple supply domains [60] Unlike the widely used pulse width modulation (PWM) controller, hysteretic control techniques based on a simple feedback loop achieves a near immediate load response without stability issues. However, if t he controller is not properly synchronized, the free running switching frequency will change with conversion voltage (see S ection 2. 3 .2.1 and Fig. 3 16). If kept unchecked, the free running oscillations may fall in undesired power supply resonance bands cr eated by parasitic package inductance interconnects and on-die decoupling capacitances. This can potentially generate large voltage excursions in the supply network due to high impedance peaks formed by the multi resonant networks, compromising overall sys tem operation and device reliability [29] Therefore, ideally it is desirable to synchronize the converter to an on-chip clock generated from within the processor to mitigate noise injection in undesirable frequency bands. Previous implementations of synchronization schemes for hysteretic control techniques have employed injection of synchronization signals in the reference voltage of the hysteretic comparator [15] However, this approach requires that the amplitude, shape and frequency be carefully controlled to achieve proper frequency lock. In a multiphase voltage -mode hysteretic controller reported in [14] the synchronization scheme limits the output conversion range t o 1/N of the input voltage,

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77 where N is the number of converter phases, and therefore requires larger minimum input voltage when the number of phases increases. The DLL based hysteretic controller design proposed in [53] has sho wn a flexible mult iphase synchronization scheme with a large output voltage range. However, this design, like other hysteretic loops in [14] and [15] still has the frequency dependence problem: it does not maintain a constant switching frequency when the conversion ratio changes. For instance, a s indicated by measured results for a 4 phase hysteretic controlled buck converter shown in Fig. 3 16, the switching frequency exhibits a parabolic dependenc e on the conversion range and closely follows Eq. 2 14b. To solve this problem, some frequency compensation techniques have been published recently for voltage mode (V -mode) hysteretic controller [62] [63] and quasi -V2 hysteretic controller [64] In [62] an adaptive ontime circuit adjusts the converter on -time according to the input voltage, achieving a nearly constant frequency operation However, this approach cannot compensate the frequency change caused by the output voltage change. In addition, it does not provide frequency synchronization capability. In contrast, an adaptive delay compensation technique proposed in [63] and [64] can lock the converter frequency by comparing the variable frequency to a constant reference. In [63] this reference is a constant analog voltage represent ing a constant fre quency, with bias accuracy and noise performance being major design issue s Instead [64] provide d a digital approach. However, it utilize d a much faster sampling clock (150MHz) than converter clock (3MHz) for time to -digital conversion, which is difficult to employed in future integrated dc -dc converter design with ultra -high frequency (>100MHz). In this chapter we present a digital phase lock ed loop (DPLL) synchronization scheme for hysteretic converters that achieves accurate frequency synchr onization and ultra -high frequency operation over a wide output conversion range. W ith this synchronization scheme, a hysteretic

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78 converter works like a PWM converter within the DPLL s bandwidth, which is set much lower than the switching f requency due to the stability requirement for phase locked look (PLL). And compared to a real PWM converter it still has the advantage of simpler feedback design and faster responses because the high frequency response of the hysteretic control loop is no t affected by PLL. In the proposed controller, the use of DPLL has better noise immunity and scalability than analog PLL or the analog frequency control loop in [63] Owing to the digital nature of the PLL all parameters incl uding frequency, are digitally programmable allowing further digital power supply control at the system level. To validate the proposed technique a single phase current -mode hysteretic buck converter is designed in 130nm digital CMOS process that achieves 90 240MHz locked fre quency operation. In section 4.2 we present an overview of the hysteretic buck converter and the proposed DPLL synchronization scheme. L oop analysis with a PLL behavior model [61] is also pr ovided to validate the proposed DPLL system. Section 4.3 presented the detailed c ircuit implementation for the proposed system and Section 4.4 shows the mixed signal simulation results Measurement results and concluding remarks are presented in section 4.5 and 4.6 respectively. 4.2 DPLL Synchronized DC -DC Converter 4.2.1 System Architecture Fig. 4 1 shows the proposed DPLL synchronized hysteretic controlled buck converter. The hysteretic controlled dc dc converter can be viewed as a free running oscilla tor, whose switching frequency fs is defined by Eq. 2 14b and nominally depends on the duty cycle ( D ), the time constant ( RC) and the overall loop delay. Since D RC affects both the load response via the high-pass feedback network RFCF and the ripple voltage via the hysteretic window VH, it is desirable to synchronize the oscillating frequency fs by changing the control loop delay. In order to digitally adjust the control loop delay and hence the oscillating

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79 frequency, a dig itally controlled delay line (DCDL) is inserted in the controller feedback path, as shown in Fig. 4 1. The refore, the delay of DCDL ( ) will also affect the switching frequency fs, which can be given by D IN H RC SVV D D f 1 (4 1) In this case, the hysteretic converter can be viewed as a voltage controlled oscillator (VCO) and its frequency can be adjusted via a DPLL in F ig. 4 1 to maintain a fixed loop frequency even when the duty cycle varies due to the changing input/output voltage or load current. Hysteretic Comparator L CFRF VX VFBVREFrL IOCOUTVO + RBRIDGE REF 1/N PFD 1/N Digital Loop Filter DPLLCKS0 Digital Controlled Delay Line Figure 4 1. Proposed DPLL synchroniz ation scheme for hysteretic control loop To achieve fixed frequency operation in hys teretic converters, the proposed DPLL approach and the adaptive delay compensation (ADC) approach proposed in [64] both inserted a digital controlled variable delay in converter control loops. The main difference between these two approaches is how the frequency is detect ed and compar ed : our DPLL utilizes a PFD which compares the divided down system clock to a reference clock whereas the ADC approach utilizes a time to -digital conver ter to compare the converted number with a re ference number.

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80 Thus, compared to the ADC approach, the DPLL based controller does not require a faster reference clock and therefore suitable for ultra -high frequency (>100MHz) converter designs 4.2.2 Modeling Hysteretic Buck Converter as a Voltage Contr olled Oscillator The hysteretic buck converter with a digital controlled delay line (DCDL) can be modeled as a voltage controlled oscillator (VCO). As indicated in Eq. 4 1, DCDL introduces an extra delay term ( ) which mo dulates the switching frequency. A ssuming the converter is in steady state operation, the duty cycle remains approximately constant and so do the filter and fixed loop delay values RC and D. For simplicity, we use F= RC(VH/VIN)+ D to represent the fixed time constant term in Eq. 4 1 Si nce the amount of delay that is added by the delay line is small compared to F, (i.e. / F<1 ), a Taylor series expansion yields 2 1) 1 ( 2 ) 1 ( 2 1 ) 1 (2F F F F SD D D D D D (4 2 ) Next we denote the first term 2 D(1 -D)/ F as FR and letDLVcont, where KDL and Vcont is the gain of the delay line and control voltage (i.e. digital value controlling the DCDL delay in Fig. 4 1 ) respectively. Then Eq. 4 2 can be written as: cont DL F FR sV K D D2) 1 ( 2 (4 3 ) In Eq. 4 3 FR remains constant. Thus t he excess phase at the output of the hysteretic converter out, can be obtained by integrat ing Eq. 4 3 in terms of Vcont. Then the transfer function (out(s)/Vcont(s) ) of the hysteretic buck converter, or equivalently the VCO is Kvco/s and the gain of the VCO (Kvc o) can be expressed as [61] 2) 1 ( 2F DL vcoK D D K (4 4)

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81 4. 2 3 Modeling the DPLL Synchronized Converter as a Charge Pump PLL In the above section, the buck conver ter was modeled as a VCO. Now the overall DPLL synchronized system can be modeled as a charge pump PLL. A charge pump PLL model is chosen for analysis as a digital PI loop filter can be easily transformed to a RC filter using the bilinear transform [65] A design procedure exists for deriving parameters for a DPLL based on an equivalent analog charge pump PLL model shown in Fig. 4 2 [65] In this model, the bilinear tr ansform s giv en by the following equations are used to transform the analog filters to their digital counterparts, and preserves the frequency response and stability of the system during s domain to z -domain transformation. C T R Ks P2 (4 5 ) C T Ks I (4 6 ) where KP is the proportional gain and KI is the integral gain of the digital filter in Fig. 4 1 ; R and C represent the resistance and capacitance of the analog filter model in Fig. 4 2 Though KP and KI ind ividually affect the stability, its the ratio KP/KI= ( RC/TS) ( 1/2 ) that actually determines when the system is stable. Higher the value of KP/KI, higher the value of RC in the analog filter model, the more stable the system is. [66] Digital Filter PFD sC R 1 2/ IPsKVCO/N / 1 fREFDC DCe VCO(DC-DC) Frequency Divider Figure 4 2 A s -domain model of the charge pump PLL with dc -dc converter as a VCO As shown in Fig. 4 2 an s domain model of the DPLL with a dc dc converter represented as the VCO has an open loop transfer function given by [67]

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82 N s K Cs R I s svco p open in out1 1 2 ) ( ) ( (4 7 ) where in is the phase at the input of PFD, Ip is the charge pump current, R,C is the resistance and capacitance value of the low -pass filter, and N is the division factor of the VCO output. Thus the closed loop transfer function for the block diagram is [67] 2 2 2 22 2 2 2 1 2 ) (n n n n vco p vco p vco ps s s N K C I Rs N K I s RCs CN K I s H (4 8 ) where t he zero, damping factor and natural frequency of oscillation can be expressed as RC sz1 (4 9 ) N CK I Rvco p 2 2 (4 10) CN KIvco p n 2 (4 11) where KVCO is related to the converter parameters by Eq. 4 4. From Eq. 4 9, t he zero (sZ) is only determined by the filter parameters ( see KP and KI in Eq. 4 5 and Eq 4 6) From Eq. 4 10, i t is evident that the d amping factor of the system can be altered by changing the filter parameters, charge pump current ( Ip) or VCO gain ( KVCO). To understand how the filter parameters affect the system stability, Fig. 4 3 shows the bode plots for the open and closed loop trans fer function of the system with different filter parameters. In the presented numerical simulation, duty cycle D is 0.5, the integration gain KI is 6 and the division factor N equals 8. Then the damping factor can be changed by adjusting the proportional gain KP (i.e. adjusting the resistance R of the loop filter). Increasing the damping factor (or increasing KP) moves the position of the zero towards

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83 the origin, which increases the phase margin of the system. In Fig. 4 3 a, when KP/KI is swept from 1 to 7, The magnitude response of the closed loop transfer function in Fig. 4 3 b shows peaking at low KP/KI and low damping factor values. As the damping factor increases, the overshoot decreases, phase response smoothens, and the closed loop bandwidth increases. 108 109 KP/KI=1 =0.20 KP/KI=3 =0.48 KP/KI=5 =0.76 KP/KI=7 =1.03Closed Loop Bode Plot -40 -20 0 20 40 60 Magnitude (dB) 105 106 107 108 109 -180 -135 -90 Phase (deg) Frequency (Hz) Open Loop Bode Plot KP/KI=1 =0.20 KP/KI=3 =0.48 KP/KI=5 =0.76 KP/KI=7 =1.03 D=0.5 D=0.5 (a) (b) Fig ure 4 3 Bode plot of the (a) open loop transfer func tion and (b) closed loop transfer function for different KP/KI value when the duty cycle of the converter is 0.5. 4.2. 4 Frequency Response When a frequency step ( ) is applied to the system, the phase change is obtained by integrating the frequency step at the reference input. Thus, a frequency step at the reference input is equivalently a ramp in terms of the phase, and the error transfer function for the frequency step is given by [68] 2 2 2 2 _2) (n n freq es s s s s H (4 1 2 )

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84 The inverse transform function of Eq. 4 1 2 gives the phase error. Fig. 4 4 shows the normalized phase error e based on the frequency step At t=0 when the frequency st ep is applied, the phase error is zero. As the phase error increases due to the integration of the frequency error, the loop responds and eventually reduces the error to zero. It is also observed that as the damping factor increases, the system settles dow n faster because of a larger phase margin (see Fig. 4 3 ). Fig. 4 4 demonstrated transient responses affected by the damping factor associated with the loop filter parameter KP and KI. In the following analysis, we will discuss how the VCO ( or dc -dc con verter) parameters affect the stability of the system. In the VCO model for the buck converter, the gain of the VCO ( Kvco) depends on the duty cycle ( D ), and time constants RC and D associated with the constant propagation delay of the buck converter. R C and D is fixed when the converter design is fixed, however, D changes when input/output voltages changes. An analysis of how different D values affect the frequency transient responses is presented in Fig. 4 5 Fig. 4 5 a shows the under -damped responses for low value of damping factor, whereas Fig. 4 5 b shows the over -damped responses for high value of damping factor. The low and high values are set by adjusting KP/KI value of the loop filter. As observed in Fig. 4 5 a, the loop settles down the fastest f or D=0.5 due to the corresponding peak value of the VCO gain Kvco determined by Eq. 4 4 Any value other than D=0.5 will decrease Kvco, decrease the damping factor in slower settling time. For the over -damped case in Fig. 4 5 b, the trend is identical to the under damped damped case but the loop settles much faster. Based on Eq. 10 and Eq. 4 4 the damping D (1 -D) thus D=0.2 case and D=0.8 case shows the same transient curves. From the above analysis we can conclude that for a hysteretic converter acting as a VCO, the converter parameters do not affect the settling time as much as the position

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85 of the zero as set by the loop filter parameters. That is, the overall stability of the system can be digitally controlled by the loop filter parameters (KP, KI). 0 0.2 0.4 0.6 0.8 1 -0.4 -0.2 0 0.2 0.4 0.6 0.8 TimeNormalized Phase Error KP/KI=1 =0.20 KP/KI=3 =0.48 KP/KI=5 =0.76 KP/KI=7 =1.03 D=0.5 Time ( s) Normalized Phase Error Fig ure 4 4 Transient response to a frequency step for different digital filter design and corresponding damping factor 0 0.1 0.2 0.3 0.4 0.5 0.6 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 TimeNormalized Phase Error D=0.2 =0.39 D=0.3 =0.44 D=0.5 =0.48 D=0.7 =0.44 D=0.8 =0.39 KP/KI = 3 Time ( s) Time ( s)D=0.2 =0.83 D=0.3 =0.95 D=0.5 =1.03 D=0.7 =0.95 D=0.8 =0.83 KP/KI = 7 Fig ure 4 5 Transient response to a frequency step versus converter duty cycle with (a) small damping factor ( KP/KI=3) and (b) large damping factor ( KP/KI=7).

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86 4.3 C ircuit Implementation of DPLL Synchronized Hysteretic Converter + VFB VREF RD CFRF L VIN VX ILOADCDIEVOUT 8 REF 1/N early /late SERIAL INTERFACE DATA R1R2 1/M PD DIGITAL LOOP FILTER + VFB VREF RD FRF VIN VX 1/N early /late CLK R R 1/M PFD Digital Loop Filter 1 DPLL CKS0A1 Digital Controlled Delay Line Non overlapping Fig ure 4 6 Proposed DPLL synchronized hysteretic controlled buck converter The complete system schematic for the DPLL synchronized hysteretic converter is shown in Fig. 4 6 The hysteretic comparator is constructed with a comparator A1 and a R1R2 resistive divider, and thus the hysteretic window is VH=VINR1/(R1+R2) A resistor RD is added in the control loop to adjust the output impedance for improved load response, [15], [37] In the DPLL, t he output cloc k of the hysteretic comparator ( CKS0) is divided down by NxM times and compared against an external reference clock using a bang -bang type phase frequency detector (PFD). The resulting early/late information is filtered by a proportional -integral (PI) digi tal loop filter. The output bits of the loop filter are fed to a sigma delta modulator and a decoder to adjust the DCDL accordingly. The first order sigma -delta is clocked and used to enhance the delay resolution of the DCDL. To ensure the stable operation the bandwidth of the DPLL should be much slower than that of the hysteretic converter loop. The DCDL s output is sent to a non overlapping circuit to generate non -overlapping clocks to drive high-side and low -side power

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87 MOSFETs. To experimentally verify the proposed design, a serial interface is added to program DPLL parameters such as the proportional and integral gains, and the divide ratio. Some parameters in the hysteretic converter are also programmable including the hysteretic window height VH, the feedback resistor RF and an on-chip load c ircuit 4. 3 1 Digital Phase Locked Loop (DPLL) Design The DPLL design is presented in detail in [61] and briefly described herein for completeness. Fig. 4 7 shows the block diagram of the DPLL. The bang-bang PFD compares the arrival times of the reference clock and the divided down signal from the output of the hysteretic controller. The PFD generates the early/late signals for the digital loop filter with controllable gains on the int egral and proportional paths. The integral gain ( KI) and the proportional gain ( KP) are set to stabilize the loop. Out of the 11-bit digital filter s output 3 bits are used by the sigma -delta to generate a bit -stream which controls one of the fine delay c ells in the DCDL. The 8 remaining bits at the output of the selector along with the sigma -delta output form a 9 bit control word (A[0:8]), where A[0] represents the bit -stream of the first order sigma -delta. In the DCDL, t wo 3 to 8 decoders control the coa rse delay line and the three LSBs of the control word directly control the fine delay cells. Programmable dividers generate the necessary clocks for the PFD, sigma delta and digital loop filter The sigma delta is clocked at a programmable divide by-M rat io, whereas the loop filter and PFD operate at a divide -by NxM ratio locked to the reference clock frequency. With the exception of the PFD and DCDL, automatic synthesis and place and route tools were employed to implement the DPLL. As shown in Fig 4 7 a t the rising edge of the reference clock or the divided down feedback (REF / FBK), U or D signal become s 1. When both U and D are 1 the NAND would reset both U and D to W hen the FBK becomes 1 D rises and th en samples the U signal to determine t he e/l signal. If REF signal is lagging / leading t he rising edge of D will sample

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88 U=0 / 1 making e/l =0 / 1 accordingly Therefore, initially during acquisition the e/l signal remains at 1 or 0 for most of the time and at lock condition it ke eps switching between 1 and 0 The minimum pulse width of D signal determined by the total propagation delay of NAND and flip -flop, should be large enough to drive the flip flop at the output From Hysteretic Comparator 19 8REF PFDSELDCDL 11 3 KPZ1KP_SEL BIT_SEL DIV_SEL KI_SEL Digital Loop Filter 1/NTo Non overlapping circuit KI 1/M A<8:0 > DECODER 3 COUT D Q D Q R D Q R D Q U DFBKe/l Fig ure 4 7 DPLL block diagram The digital filter in this design is a p roportional i ntegral (PI) f ilter. As shown in Fig. 4 7 t he integral path of the filter is an accumulator with integral gain KI, and the proportional path is a feed -forward path with proportional gain KP. A 19 -bit accumulator is used in the design. The integral gain control and the proportional gain are adjustable to control the stability of the loop. T he p roportional part in the PI filter adds a zero in the system which stabilizes the system. Varying gain control allows us to control the pos ition the zero and hence provides greater control over the loop stability. The output of the loop filter is given to a bit selector (SEL) which selects 11bits out of the 19 coming from the loop filter (i.e [10:0], [11:1],). The 3 LSBs of the selected 11 bits are given to the sigma delta modulator and the remaining 8 bits are given to the delay line to control the coarse and fine cells.

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89 A first order s igma d elta modulator is used in the design to increase the resolution of the DPLL. The s igma d elta is clocked by a frequency divider whose division factor is N times lower than that of the dividers used to clock the loop filter. The modulator takes in 3 bits from the filter output and oversamples it by a factor of N. Th erefore, a dithering signal for the D CO is generated N times faster than the normal control word, effectively increasing its resolution and pushing the phase noise to higher frequencies. The DPLL closed loop response resembles a l ow p ass filter, so the high frequency noise gets rejected. The sigma delta as shown in Fig. 4 7 is a 3 bit accumulator with the carry out of the final adder producing the bit -stream. The sigma delta can be operated at 1/4, 1/8, 1/16 or 1/32 of the output frequency depending upon the 2 -bit control signal (DIV_SEL). 4. 3 2 Digitally Controlled Delay Line (DCDL) The digital -controlled delay line as shown in Fig. 4 8 is employed to supply variable delay to the control loop. The delay line consist s of two tuning stages: a coarse tuning stage and a fine tuning stage. The coar se tuning delay chain is made up of 63 delay buffers each of which has fixed delay of about 40ps. A s shown in Fig. 6, 64 delay buffers are divided into 8 delay groups (D) and notice that the last buffer is a dummy. Therefore, 0~63 delay buffers can be incl uded into the delay line depending upon the 6 MSBs (A[ 8 : 3 ]) of the control word Thus the tunable delay range of the coarse tuning stage is 0~2.52ns. Two stage tri -state inverters are used and t wo 3 to 8 decoders act together to generate the required dela y from the coarse delay line. A[ 8 : 6 ] selects the number of group (from 1 to 8) and then A[ 5 : 3 ] selects the number of delay cell (from 0 to 7) in each group. For example, if A[ 8 : 3 ]=[001111], the second group and 7 delay cell s in each group are selected by t urning on the corresponding tri -state gates, s o 15 (or 8+ 7 ) delay cell s contribute to the coarse delay stage. Thus the coarse tuning stage adds a 600ps delay to the

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90 control loop as (see Eq. 4 1 ), changing the converter frequency. The fine tuning stage is an inverter with 3 tri -states (1X, 1X, 2X) in parallel adding a 0~40ps tunable delay to the DCDL The bit -stream from the sigma -delta (A[0]) and 2 LSBs (A[1], A[2]) control the three tri -state gates. Out To next stage From previous stage IN A<5:3> OUT A<8:6> A<2:0>EN I/P O/P D2 D3 D4 D5 D6 D7 D1 D0 MUX 1X 1 1X 1X 2XCoarse Delay Fine Delay MUX Fig ure 4 8 Digital Controlled Delay Line 4. 3 3 Hysteretic Comparator A s shown in Fig. 4 9 the comparator A1 comparing VFB to VREF is composed of three stage differential stages followed by a single -ended output stage. A common mo de feedback (CMFB) ensures the output level to equal about half of the power supply. The CMFB directly adjusts the tail current of the input stage by changing the gate bias of the two parallel NMOS In the simulation, the comparators dc gain is 44dB, and the propagation de lay is less than 300ps with 10mV amplitude input Resistors with large values in advanced CMOS technology usually have large parasitic capacitance that limits the bandwidth. Therefore, the R1-R2 divider connecting

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91 VREF and VOUT in Fig. 4 6 is implemented with a resistive network including RH0, RH1, RH2 and a R2R ladder which do not require large resistors Digital control bits B[1:4] from the serial interface can change the divider ratio of the R 2R ladder, varying the hysteretic window from 1/80 to 1/10 of VIN. V+ VVBIAS VBIAS VBIAS VBIAS VOUT Common Mode Feedback R -2R Ladder 2R 2R 2R R 2R R 2R R 2R R 2R R 2R R RH1 RH0 RH2 VREF Buffer (VFB) B1 B2 B3 B4 VBIAS Fig ure 4 9 Hysteretic comparator Schematic 4. 3 4 Non -Overlapping Clock Generation When switching on and off the power MOSFETs of the buck converter a fixed dead time is applied to turn off both NMOS and PMOS, avoiding the sh ort circuit losses. The dead time is set by a nonoverlapping clock genera tion circuit as shown in Fig. 410. CLK is generated from the output of DCDL, while CLK_P and CLK_N are sent to the input of the high-side and low -side drivers, respectively (see Fig 4 6 ). The circuit between CLK and CLK_N works like a glitch register, setting 0 or 1 when the negative or positive edge of CLK comes. With appropriate sizing of the devices, the negative edge propagation delay from CLK to CLK_N is ~70ps slower than t he four inverter propagation delay from CLK to CLK_P. In addition, considering the clock skewing between the high-side and low -side drivers, the total dead time after switching off the

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92 high -side PMOS is ~60ps. A similar but opposite behavior occurs for the positive edge of CLK, resulting in a ~40ps dead time after switching off the low -side NMOS. CLK_N CLK CLK_P P0P1N1N0 Fig ure 4 10. Circuit schematic for non-overlapping clock generation 4. 3 5 On -Chip Load To test the load response of the converter with ultra -high switching frequ ency, an on -chip load circuit is used to generate load transient with programmable ramp time and current step. As shown in Fig. 4 11, the load circuit consisting of eight programmable current sources, can be trigger ed by either an internal ring oscillator or by an external clock (fEXT) selected with a multiplexer. The fast rising or falling edge is generated by turning on or off the current sources staggered by 50ps delay. The ramp time can change from 50ps to 400ps by se tting the control bits S[1:8], where as the current step is controlled by C[1:3]. S1 S2 S7 S8 ILOAD fEXT 50ps ~500nsDelay 1 1X C1 1X C2 2X C3 4X Programmable current source Fig ure 4 1 1 On -chip emulated transient load with programmable rise time and amplitude

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93 4. 3 6 Layout of the Power Switches The size of the power transistors are selected to achieve high efficiency at load curre nts of ~0.2A and operational frequency around 100MHz. The test chip is impleme nted in a 130nm CMOS process. Fig. 4 12 shows t he layout of the power switches measured 350 m by 270 m, which is divided into multiple NMOS and PMOS switch cells. Each cell measu res 20 m wide and contains distributed power grid for VIN and GND, input decoupling capacitor, low -side / high -side driver and NMOS/PMOS device connected to the output node VX. With decoupling capacitor inse rted among the switch cells, the width of power t races is increased and the current density is reduced. The area of the bridge (i.e. NMOS and PMOS device) is 0.021mm2, approximately 22% of the total area Since the maximum output current for the converter i s roughly 24 0mA the bridge current density of 11.4A/mm2 is achieved. PMOS Stage NMOS Stage VX 20 m20 mm 20 m 270 m 350 mVXVX VX NSwitch Cell Power Switch Array P Switch Cell GND VIN VX GND VIN Fig ure 4 12. Layout of power switches

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94 4.4 Mixed Signal Simulation of DPLL Synchronized Hysteretic Converter Mixed signal simulations are performed on the DPLL synchronized hysteretic buck converter. In the DPLL, except the delay li ne, all the components are replaced by the Verilog code [61] Other analog blocks are simulated at the transistor level. M ixed signal s imulations are carried out in SpectreVerilog to analyze the system behavior when the proport ional path gain KP is changed and when frequency and load steps are applied to the DPLL based converter 4.4.1 DPLL Operation with Variable Proportional Path Gain In the DPLL, the stability of the loop is determined by the damping factor, which in turn de pends on the proportional path gain. A simulation with different KP values is carried out to analyze this behavior of the DPLL Fig. 4 1 3 sh ows after the system startup how the control word settles with different proportional path gains. In the simulation setup, the reference frequency is 12.5 MHz with a total division factor of 16 (i.e. M=2 times N=8). Two simulations with different proportional path gains are carried out. As the proportional path gain affects the position of the zero in the system, it als o affects the stability and the settling behavior of the DPLL. Fig 4 1 3 shows that for higher values of KP, the damping factor becomes larger and the system settles faster, but the ripple in the control word is higher. M=2,N=8 K1=0.5,K2=3 M=2,N=8 K1=0.5,K2=7 0 50 100 150 200 250 300 350 400 30 40 50 60 Reference periodsControl Word 0 50 100 150 200 250 300 350 400 30 40 50 60 Control Word M=2,N=8 KI=0.5,KP=3 M=2,N=8 KI=0.5,KP=7 M=2,N=8 K1=0.5,K2=3 M=2,N=8 K1=0.5,K2=7 0 50 100 150 200 250 300 350 400 30 40 50 60 Reference periodsControl Word 0 50 100 150 200 250 300 350 400 30 40 50 60 Control Word M=2,N=8 KI=0.5,KP=3 M=2,N=8 KI=0.5,KP=7 Figure 4 1 3 Control word versus t ime in the startup simulation for different values of KP

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95 4.4.2 Transient Response to a Frequency and Load Step Fig. 4 1 4 shows the response of the DPLL to a frequency step at the reference and a load step at the converter output In the simulation setup, an initial referen ce frequency of 40MHz was set and then decreased to 33.33MHz. The division factor N is set to 4. The integral path gain i s set to 0.5 a nd the proportional path gain i s set to 3. As seen in Fig. 4 14a, the loop first locks to 40MHz, settin g the switching fr equency to 160MHz. Later the loop locks to 33.33MHz, settin g the switching frequency to 133MHz. When a frequency step is applied, the control word changes and finally settles to a new value. For Fig. 4 1 4b, a similar s etup is used except that the referen ce frequency is maintained at 45 MHz A load step of 80mA is applied at the converter output resulting in a change of duty cycle determined by Eq. 2 14b. And according to Eq. 4 1 the change in duty cycle will change the switching frequency of the converter To compensate for the se change s the DPLL adjust the digital control word for the delay line, as seen in Fig. 4 1 4 b, and force the loop frequency to lock to the reference again Therefore, we can conclude that a load step at the converte r output is similar to a frequency step at the DPLL. This circuit simulation result corroborate s the behavior model demonstrated in this section for the DPLL controlled hysteretic converter. Frequency step Lock LockControl WordReference Period 0 100 200 400 300 500 60 40 50 30 0 100 200 300 400 500 40 45 50 55 60 Reference periodsDigital control word Load step Lock Lock Control Word60 50 55 45 40 Reference Period 0 100 200 400 300 500 (a) (b) Fig ure 4 1 4 Simulated c ontrol word versus time in a transient response to (a) a frequency step and (b) a load step.

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96 4.5 Measurement Results An integrated buck dc -dc converter with hysteretic control loop and DPLL based synchronization was fabr icated in standard 130nm digital CMOS process. Fig. 4 1 5 shows the die photo The buck converter is operational from 90MHz to 240MHz and occupies approximately 0.34mm2, which includes the DCDL inside the controller and a 0.7nF input decoupling capacitor. T he DPLL without the DCDL measures 320m by 200m. The converter was evaluated at different frequency, using various external SMT size 805 air core inductors ranging from 8.2nH to 24nH and capacitor of 25nF for output decoupling. Buck converter and input decoupling 1.9 mm 1.5 mmControl DPLL Serial Interface On chip load and output decoupling Buck converter and input decoupling 1.9 mm 1.5 mmControl DPLL Serial Interface On chip load and output decoupling Figure 4 1 5 Die photogra ph 4.5.1 Frequency Locking Performance In order to evaluate the performance of the DPLL synchronization scheme, the converter output voltage was varied and the output frequency was measured at a fixed input voltage ( VIN) 1.2V as shown in Fig. 4 1 6 The in ductor and output capacitor are 8.2nH and 2 5 nF, respectively. Firstly the DPLL is disabled and the DCDL is set for the minimum delay, the maximum free -

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97 running frequency exhibits the parabolic dependence on output voltage To test the DPLL, we set the divid e ratio to 128 and var ied the reference frequency from approximately 703kHz to 1.875MHz in 30MHz/128 increments. The corresponding measurements show that the output switching frequency is locked to the input reference over a wide range of 90MHz to 240MHz. The output voltage range over which the DPLL locks is bounded by the maximum free running frequency of the converter. Thus the output voltage range decreases as the frequency is increased. The jitter histogram of the divided down clock ( VDIV) and the multi plied clock or bridge output signal ( VX) are shown in Fig. 4 1 7 The divided down clock ( VDIV) shows RMS and peak to -peak jitter of 10.4ps and 83ps, respectively. T he bridge output ( VX) is outside the phase locked loop and include the delay of the noisy po wer stages (see Fig. 4 6 ), resulting in worse RMS and peak to -peak jitter of 42.5ps and 244ps, respectively. 0 50 100 150 200 250 300 350 0.2 0.4 0.6 0.8 1 1.2 Output Voltage (V)F r e q u e n c y (MH z) Without PLL 1.875MHz 1.64MHz 1.40MHz 1.17MHz 938kHz 703kHz Figure 4 1 6 Converter switching frequency versus output voltage

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98 VXVXVDIVVDIV (a) (b) Figure 4 1 7 Jitter histogram of (a) divided clock and (b) buck converter bridge output. 4.5.2 Efficiency The measured power efficiency for 1.2V/0.8V conversion is shown in Fig. 4 1 8 For the set ups with 90MHz and 120MHz running frequency, the peak efficiency of ~81% is achieved for a load current of around 150mA. For 180MHz case, an 8.2nH inductor with quality factor of 25 is used and the peak efficiency of ~80% is achieved for a load current of 200mA. Increasing the load current decreases the efficiency due to higher resistive loss associated with the ripple current in the inductors, whereas at lighter loads the switching frequency loss associated with the bridge is dominant. Because a larger ind uctor comes with a lager series resistance and larger conduction loss, the efficiency of a converter setup with lower frequency, larger inductor and higher peak efficiency degrades faster and eventually becomes worse than the efficiency of a converter setu p with higher frequency and smaller inductor.

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99 55 60 65 70 75 80 85 0 50 100 150 200 250 Load (mA)Effi c e n c y (% ) 90M, 24nH, 25nF 120M, 15nH, 25nF 180M, 8.2nH, 25nF Figure 4 1 8 Measured efficiency 4.5.3 Load Transient Response Fig. 4 19 shows the converter transient response to a 120mA load step for different converter frequencies with various indu ctor values. The output capacitor is set to 25nF for fair comparison. The current step was generated using a programmable on chip load with a ramp time of 100ps [69] The resulting output voltage is about 0.8V for a low current load of 80mA and 0.75V for a high load of 200mA. The voltage droops for both low -to high and highto -low current steps range between 95mV at 180MHz case and 130mV at 90MHz case. This results shows that voltage droop decreases with smaller L and larger C ( or smaller L/C ). To further improve the transient response, a larger value of RC (or RFCF) time constant should be used to couple larger voltage from the output to the hysteretic comparator [36] But as indicated in Eq. 4 1 this also limits the maximum switching frequency that the DPLL based converter can achieve. In our design, RC is selected to ensure ~300MHz maximum frequency without DCDL and the

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100 delay of DCDL is designed to lock the frequency to a lower frequency reference from 90MHz to 240MHz, as shown in Fig. 4 16. Therefore, this frequency co mpensation approach, using loop delay insertion, trades off the maximum switching frequency and the loop transient response for the frequency control capability. This can be further improved by controlling RFCF or VH in Eq. 4 1 instead of by reusing the DPLL core implementation scheme demonstrated in this work. In Fig. 4 19, the slew rate of the voltage drop / overshoot is the same at the beginning due to the same load current ramp (di/dt) across the same effective series inductance (ESL) of th e output capacitor. The 50mV steady state voltage drop at the output is due to the resistive response introduced by voltage positioning [37] The ripple voltage shown in Fig. 4 19 is approximately 10mV and the m easured response time is approximately 40ns. With a larger time scale (see Fig. 4 2 0 ), the converter shows a ripple of around 25mV due to the noise coupling from the DPLL and digital IO running at the divided clock, which can be improved with better isolation between the grounds of the digital circuits and the output load. 0 100 200 300 400 0.66 0.68 0.7 0.72 0.74 0.76 0.78 0.8 0.82 Time (ns) Voltage (V) 90M, 24nH 120M, 15nH 180M, 8.2nH 400 90M, 24nH 120M, 15nH 180M, 8.2nH (a) (b) Figure 4 1 9 Measured load response at 1.2V/0.8V conversion using 25nF output capacitor and various indu ctors and for 0.12A (a) low -to high and (b) highto low current steps

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101 4.5. 4 Digital Frequency Control For a converter with fixed filter sizes, although running at higher frequency (i.e. 180MHz) yields smaller ripple, the tradeoff is a degradation in light load efficiency due to higher switching loss (see Fig. 4 1 8 ). Since the DPLL parameters are fully digitally programmable, this technique can be used to implement auto -selectable -frequency PFM control scheme to improve light load efficiency [70] This recently proposed control schem e select s pre -defined s witching frequency based on load currents and the se pre -defined frequencies are all binary -weighted multiples of a fundamental frequency (i.e. fs, 2fs, 2Nfs) a nd thus the spectrum of PFM controller is as predictable as one with PWM controller. Fig. 4 20 shows the converter operating in this auto selectable -frequen cy mode by setting the digital control words in serial interface. In this test, 8.2nH inductor and 2 5nF c apacitor is used for 1.2V/0.8V voltage conversion. With the divide ratio of 128, we vary the reference frequency from approximately 703kHz to 1. 406MHz when a load step is generated by the on -chip load. Then the switching frequency jumps from 180MHz at heavy load of 2 4 0mA to 90MHz at light load of 60 mA At light load running at 90MHz reduces the switching loss and improves the efficiency. The measured total efficiency is 77% when t he time ratio for the heavy and l ight loads is set to 1:1 as seen in Fig. 4 2 0. If the same load step configuration is applied to the converter with 180MHz switching frequency, the efficient is 74.4% Therefore, a 2.6% efficiency improvement is achieved. Decreasing the time ratio of heavy to light load s can lead to higher i mprovement in overall efficiency For infinite light load time it improves by 13% equaling to the light load efficiency difference between 90MHz and 180MHz shown in Fig. 41 8. T he settling time of this D PLL for this load and frequency step is around 1. 3 m s or ~910 cycles for 730kHz input reference. That is because a small loop gain is selected to reduce the jitter, which also decreases the loop response to a frequency step.

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102 58 60 62 64 66 68 70 72 0.5 0.6 0.7 0.8 0.9 Time (ms) Voltage (V) 90MHz, 60mA 180MHz, 240mA Time (ms) Voltage (V) Figure 4 20. Measured load response at 1.2V/0.8V conversion using 8.2nH induct or, with frequency jump ing from 180MHz at 240mA to 90MHz at 60mA. 4.5. 5 Performance Summary Table I summarizes the measured hysteretic buck converter performance. The converter is operational from 90MHz to 240MHz by using DPLL synchronization. For 1.2V/0.8 V input/output conversion at 180MHz setup, it can achieve a peak efficiency of 8 0 % with 200mA load. Table II shows a comparison with previously reported integrated buck converters with different types of hysteretic control loop. Among reported converters, [15] [52] and this work [71] use current mode (C -mode) hysteretic control and operate in tens ~ hundreds MHz frequency. Compared to and [15] and [52] our design can compensate the frequency change by updating the delay configuration in the hysteretic control loop. In this case, a hysteretic converter, a variable frequency converter, works like a fixed frequency P WM converter within the bandwidth of DPLL. Other frequency compensation techniques for voltage mode (V -mode) hysteretic controller [62] [63] and quasi -V2 hysteretic controller [64] are published recently. As introduced in section I, [62] dose not provides frequency synchronization capability and cannot compensate the frequency change caused by output voltage change. [63] and [64] uses closed

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103 loop frequency control but the frequency is compared or say synchronized to a reference voltage or a digital words. Instead this work uses DPLL to provide accurate frequency synchronization. In addi tion, this work can operate i n much higher frequency than [62] [64], resulting in much smaller passive values and faster transient response s. Table 4 1 Performance summary Technology 130nm CM OS Chip area 2.85mm 2 DC DC converter area 0.42mm 2 Bridge area, A BRDG 0.03mm 2 Decoupling Capacitance 2 5 nF Inductance, L 8.2nH Input voltage, V IN 1.2V Output voltage, V OUT 0.4V~0.96V Switching frequency, f 90M~240M Maximum current, I MAX 2 40m A Curr ent density, I MAX / A BRDG 8 A/mm 2 V IN = 1 2 V, V OUT = 0 8 V f = 180MHz Voltage Droop @ 0.12A step 100mV Efficiency (peak) 80% Efficiency @ I MAX 77.5% Table 4 2 Performance comparison [62] [63] [64] [52] [15] This Work [71] Year 200 7 200 7 200 9 2007 2005 2008 Control Loop V mode hysteretic V mode hysteretic Quasi V 2 hysteretic C mode hysteretic C mode hysteretic C mode hysteretic Fixed Freq. Yes Yes Yes No No Yes Freq. Ref. No Voltage Digit No No Clock Tech m] 0. 5 0. 3 5 0.5 0.5 0.09 0.13 # phases 1 1 1 4 4 1 V IN [V] 1 4 4.2 3. 0 2.7 4.8 1.2 1.2 V OUT [V] 0.5 1.5 1.5 3.3 0. 9 0.8 f[MHz] ~ 0. 14 ~0.85 0.78 30 233 180 Peak Eff.[%] 8 3 94.5 85.6 83 83.2 80 L TOT [H] 1 4 7 3.9 0.22 X4 0.00 68 X4 0.008 C[F] 2 0 10 47 0.008 0.05 0.0025 0.0 2 5 I MAX [ m A] 2 5 0 500 8 00 1 000 300 240 Area[mm 2 ] N/A 1.67 4.5 3.3 0.14 0.42

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104 4.6 Summary We d emonstrate a DPLL frequency locking technique for ultra -high frequency hysteretic con trolled dc -dc buck converters. The DPLL locks the converter operating frequency to a clock reference to eliminate the dependence of switching frequency on output conversio n voltage. Moreover, since the DPLL parameters are programmable, this technique allows implementing hysteretic converters with digital frequency control schemes, such as digital PWM control or auto -selectable -frequen cy PFM control [70] The DPLL converter operates over a wide frequency range of 90 240MHz and achieves a conversion range of 33% to 80%, or 0.4V to 0.96V. Using a single inductor (8.2n~24nH) and 25nF capacitor, the converter achieves a load response of 40ns to a 120m A step. The dc dc converter was implemented in 130nm 1.2V digital CMOS process and achieves a peak efficiency of 80% at 180MHz for load current of 200mA.

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105 CHAPTER 5 HIGH FREQUENCY BOOST CONVERTER WITH DIGIT AL DELAY LOCKED LOOP (D DLL) 5 .1 Introduction In s ome battery powered portable systems, one of the key components is the integrated boost converter delivering high voltage for display device s audio amplifier s and flash memory. In order to reduce the size of the passives for a smaller overall footprint a nd/or system in -package (SIP) applications, the dc -dc converter can be operated at higher switching frequenc ies (tens ~ hundreds MHz [72] -[74] ) and in discontinues conduction mode (DCM) [75] To enable DCM operation, boost converter topologie s require a rectifier connecting the switched inductor to the high voltage output. Conve ntional boost converters use a PN -junction diode [72] or diode con nected NMOS [73] as the rectifier stage, enabling DCM without additional control circuitry. However, these types of rectifier s suffer from large turn -on voltage s resulting in low conduction efficiencies especially in low volta ge applications To reduce this conduction loss, the rectifier can be fabricated using a MOSFET with additional control circuit ry, [74] [75] However, both methods ha ve difficulties when the target output is higher than the breakdown voltage of the MOSFET. Therefor e, we propose the use of integrated schottky diodes which can sustain ~10V reverse bias voltage in 0.13 m CMOS process. The use of integrated schottky rectifiers does not requi re additiona l circuitry for high -side switch control, and eliminates the high -side power hungry drivers In this work, we report a 100MHz multiphase converter utilizing schottky diodes in a 0.13 m CMOS process for SIP or system -on -chip (SOC) applications In addition, a digital delay locked loop (D DLL) is proposed t o synchronize the current mode PWM controlled converter. In this chapter, we demonstrate a synchronization scheme for high -frequency multiphase boost converters using a D DLL based controller that achieves automatic phase synchronization

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106 with accurate duty cycle and large voltage conversion range. A 100MHz four phase boost converter was implemented in 1.2V 0. 13m CMOS process and achieve s 3V 5V of output voltage range In S ection 5 .2, we present the proposed system architecture of the 4 phase boost converter along with the high voltage devices. The D DLL design proposed by [61] is demonstrated in Section 5.3, followed by the circuit implementation and the simulated results in S ect ion 5 4. M easurement results and concluding remarks are presented in S ection 5 5 and 5 6 respectively. 5 .2 Multiphase Boost Converter with High Voltage Devices 5 2 1 System Architecture Fig. 5 1 shows the architecture of the digitally aided four -phase DCM boost converter. Since the inductor current is interleaved among all four phases, the input current ripple decreases resulting in smaller input and output filter size and reduced peak current requirement from the battery. The converter consists of four s ingle -phase asynchronous boost converter stages, one of which operates independently to set the desired output voltage from VREF and the reference clock (CKS0) for a D DLL. When the D DLL is locked, the synchronization signals (CK90, CK180 and CK270) are a ppropriately offset by 90, 180 and 270 degrees to drive the remaining converters. E ach single -phase converter stage consist s of a switched inductor, a schottky diode as a rectifier and a s tacked NMOS switch comprised of a 1.2V device N0 and a 3.3V thick ga te device N1 to absorb the blocking voltage across the switching nodes VX. The detailed design and characteristic for the schottky diode and the s tacked NMOS will be discussed in Section 5.2.2 and 5.2.3, respectively With this architecture, the current mode PWM controlled converter and the remaining D DLL controlled converter s are combined seamlessly using a single current -mode PW M controller for all phase s To achieve proper synchronization between N output phases, the D -

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107 DLL must be able to : 1) track t he switching frequency of the master PWM controller, 2) maintain a 360o/N offset between each phase and 3) avoid duty cycle distortion in the multiphase clocks The detailed circuit implementation for D DLL will be presente d in the section 5.3. CKS0 VREF Phase 180 Phase 270VX180 Digital DLL VIN VX0Phase 0 VX270 CKS180 Schottky Diode 2.5V N0 VIN VX90Phase 90 2.5V CKS90 IOCOVO VC CKS270VoN1 CKS0 Current Mode PWM Figure 5 1. Four -phase boost converter with D DLL based controller 5 2 2 Schottky Diode Based Rectifier As discussed in Section 5.1 using the schottky diode as the rectifier stage in a boost converter eliminates the voltage drive for the stacked MOSFET switch a long with level

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108 conversion circuits and drivers, enabling power savings. By selectively blocking the n+ implants in desired diffusion areas or directly contacting the n -well with metallization, the SBD can be integrated in standard CMOS process [76] The fabrication of the SBD does not require any process enhancements and can be designed entirely with available process layers. It exhibit higher cutoff frequencies and lower forward voltage drop in comparison to PN -junction based diodes. In addition, it can sustain larger reverse voltage compared to MOSFET based rectifiers, and do es not require drivers and control circuits, which can be complicated and power hungry at high operating frequency (hundreds MHz). ILD N well p+ p+ n+ n+ ILD ILD ILD STI STIGuard Ring ILD N well p+ p+ n+ n+ ILD ILD ILD STI STIGuard Ring Figure 5 2. Cross s ection and J -V curves for schottky diodes with or without guard ring Fig. 5 2 shows the measured current density and breakdown voltage of the SBD. Self aligned p+ guard rings around the metal semiconductor junction are used to reduce the reverse leakage cu rrent due to sharp electrode edge effects and extend the reverse breakdown voltage to ~1 1 V.

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109 SBD measurements indicate a barrier height of ~0. 7 eV, ideality factor of ~1.0 7 and forward voltage of ~28 0mV at 1A/cm2. 5 2 3 Synchronous Switch The maximum output voltage of the integrated boost converter is typically limited by the breakdown voltage of the output power devices including the high-side rectifier and the low -side synchronous switch. The blocking voltage across the rectifier equals the output voltage VO, while the blocking voltage for the synchronous switch is the sum of VO and the maximum forward voltage across the rectifier. For instance, for a 5V output boost converter using a rectifier with ~0.8V maximum forward voltage, the blocking voltage is ~5. 8V. Thus the breakdown voltage of the synchronous switch should exceed ~7V given a ~20% design safety margin. In the standard 130nm CMOS process, the minimum drain breakdown voltage for the thin-gate transistor and the thick gate transistor are ~2V and ~5V respectively Devices with higher breakdown voltage than 5V in 130nm CMOS process are often implemented with stacked transistors [77] In this design, the synchronous MOS switch is made of a thick ox (~70) transistor stacked on a native thin -ox device. In Fig. 5 3 t he stacked structure shows a measured breakdown of ~10V for a thick ox gate bias of 2.5V and the correspon ding on -mm. The thick gate device is rated 3.3V in 130nm CMOS process, but the peak gate to -drain voltage can reach ~ 4.5V, as discussed above. Therefore, the reliability issue due to the increased oxide stress needs to be considered. Time d ependent d ielectric b reakdown (TDDB) is a result of the wear out of the insulating pro perties of the gate oxide and will reduce the life time of the transistor. F or thick oxides under a high field stress ( EOX), TDDB lifetime can be given by [78] : OX BDE G t t1 1exp (5 1)

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110 where t1 and G1 are t he slope and intercept of the In (tBD) versus 1/EOX plot, respectively Both t1 and G1 are based upon data fitting from experimental data and their temperature dependence are taken into account by: 300 1 1 exp0 1T k E t tB B (5 2) 300 1 1 1 exp0 1T k G GB (5 3) Both of the above equations contain constants that are extracted from data and will vary depending upon specific oxide properties and defect con tent From the above equations, the maximum EOX for a required life time can be calculated based on the specific process parameter and temperature In literature [79] the acceptable value for EOX is reported as 7MV/cm to achie ve a 10 -year lifetime at 125oC. Then in our design, f or the thick -ox transistor with 70 oxide thickness the maximum gate to -drain voltage for this field dress limitation is about 4.9V. A d rain -extended NMOS ( DE N MOS ) structure was also implemented in our design as another option for the synchronous switch. A s shown in Fig. 5 3 a DE N MOS is fabricated by using the light ly doped n -well instead of the n+ layer to form a NMOS s drain. In this case, when the transistor is off, the majority of the drain voltage is dropped across the n-well. Therefore, the electric field under the gate at the drain side is reduced, allowing higher drain to source voltage s before breakdown In addition, the n -well drain and the p -substrate form a sufficient depletion region at the drain end to increase the junction breakdown voltage D esign ing a DENMOS typically require s choosing three dimensions including the gate length the drain well overlap under the gate and the distance between the n+ drain contact and the drain edge of the gate [80] To achieve the required voltage level t hese dimensions must be optimized based on the doping levels in the CMOS process

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111 n+ N well n+ ILD P sub ILD POLYDrain Gate SourceILD ILD STI 3.3 thick ox 1.2 thin ox n+ N well n+ ILD P sub ILD POLYDrain Gate SourceILD ILD STI 3.3 thick ox 1.2 thin ox 3.3 thick ox 1.2 thin ox Figure 5 3. Cross section of the DENMOS and measured breakdown characteristics for stacked NMOS and DENMOS. In Fig. 5 3 the measured I -V characteristics including breakdown, for the DENMOS are shown to be close to our expectations but are less ideal th an stacked NMOS. With a design target for other applications, a DENMOS can achieve higher br eakdown voltage up to 20V in advanced CMOS process [80] [81] which is higher than that a stacked NMOS structure can achieve. Moreover, DENMOS does not require addit ional bias voltage (i.e. 2.5V for stack NMOS), thus it can be a suitable candidate for the synchronous switch if its onresistance is acceptable. However, the measured on -resistance per gate width is 10x worse than our expectation and 30x worse th an the st acked NMOS, resulting in worse efficiency and limited output voltage level. This undesirable result for the DENMOS design is possibly caused by the layout rule violation in the fabrication process. In our layout, the active region under the gate does not e xtend into the drain

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112 extended n -well If the thick -ox extends into the channel the n the channel underneath may not enter strong inversion degrading the effective channel conductance for the rated 1.2V gat e voltage 5 3 Proposed Digital Delay Locked Loop 5 3 1 D -DLL Architecture Fig. 5 4 shows the D DLL used to synchronize each of the independent SI stage of the m ultiphase boost converter over a wide frequency and duty cycle range for high frequency DCM switching The detailed D DLL design is presented in [61] and briefly described herein for completeness. It consists of t hree p hase detectors (PD1 -PD3) Successive Approximation Register (SAR) [82] Counter, Delay Line, False Lock Detecto r, Delay Ini tialization Circuitry (INIT), a 1st order Sigma Delta with a digital clock multiplier (MULT), divider circuitry and Duty Cycle Correction circuitry. The SAR register, INIT and the C ounter are 11 bits each. With the exception of the phase detectors and dela y line automatic synthesis and place and route tools were employed to implem ent the D D LL. The main phase synchronization loop operates together with the initialization, successive approximation register (SAR) and counter modules. During startup, a fals e lock detector together with the initialization (INIT) module sets an initial delay to avoid false locking. Then the D D LL enter s the SAR mode for fast locking based on the output from the first phase detector (PD1). Once the SAR mode is complete, the sys tem enters the counter mode where the loop tracks changes in input reference using a second phase detector (PD2), continuously updating an 11 bit control word until the D DLL is locked. The digitally controlled delay line is made of eight identical delay c ells each of which contains a coarse fine tuning and dithering delay unit s. To improve the delay resolution, a first order sigma delta modulator and a 4X reference clock multiplier are used to dither the fine delay cells. In addition, a duty cycle correc tion loop is

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113 adopted to achieve precise step up ratios across all phases by adjusting the P/N ratio of the delay cells, thereby compensating for duty cycle distortion in the delay line. INIT Delay Line SAR Counter 11 8 3False Lock Detector REFPD1 PD2 Duty Cycle Correction 3 SAR DONE Fast/SlowSAR_ON INIT PD3 MULT 4X CLK 11 8 6 5 4 3 2 1 7 Figure 5 4. 8 -Phase Delay Locked Loop In the i nitialization m ode the control word is initialized to 10000000000. So the delay of the delay line is initialized to half of its maximum value. The f alse l ock d etect or analyses all the phases coming from the delay line to check whether the delayed 8) is within 0.5 TREF and1.5 TREF. The false lock detection circuit produces two signals U and D which determine whether the signal is within the above specified range. Depending upon these signals the INIT module sets the initial values of the re gister. During this process the INIT signal is active to bypass the SAR registers and the counter. Once the initial delay is set the INIT signal becomes in active and SAR registers operation begins. The SAR registers use the binary search algorithm. The number of clock cycles the SAR register takes to give a final control word is equal to the size of the SAR register. The SAR registers determines whether to increase the delay or decrease the delay based on the control signal received from the first phase detector (PD1). After the operation of the register is

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114 complete, the D DLL is locked with some finite offset. In SAR mode the counter acts as a bypass to the control bits until the SAR_DONE signal becomes active. After the SAR register has completed its operation the system moves to counter mode The 11 -bit counter increases or decreases the control word on the basis of the control signal received from PD2. After lock if there is a sudden jump in the frequency of the reference which makes the delay refe 8) go out of 0.5 TREF to1.5 TREF range, the INIT module would get the counter word to the correct range and the counter would then get the system back to lock. This process is slower than SAR operation and would take more time to lock. To improve t he resolution of the DDLL a 1st order sigma delta is used. As the sigma delta needs a higher frequency clock a digital clock multiplier circuit is designed to generate a 4X reference clock. In addition, a Duty Cycle Correction Loop is used to tackle change s in the duty cycle of the phases due to distortion in the delay line. The divider circuit in the design provides clock to SAR, counter and the initialization circuit. The divider is programmable which provides an option to operate different blocks at diff erent frequencies. The counter generally works at a highest frequency and the INIT module works the slowest. This method of providing divided clock helps in lowering the power and gives enough time for the loop to settle before new changes are made on the control word. Finally the serial interface in the design provides control signals to set up the D DLL before operation begins. 5 3 2 Digital-Controlled Delay Line The delay line for an 8 -phase delay locked loop is divided in 8 phases as shown in Fig 5 5 Each phase has a coarse delay stage, a fine delay stage and a cell which is controlled by the sigma delta bit. The coarse delay stage is a 32 stage l attice delay line 26. The fine delay stage is made up of 8 delay cells which have duty cycle control assoc iated with them. The sigma delta

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115 cell is a simple inverter with tri-state in parallel. The output from the sigma delta cell is driven by a higher strength inverter which makes the overall output from the delay line noninverting. D<7>IN OUT FINE D<0>... ... ... Coarse delay Fine delay delay IN OUT 5 3 bit 3 IN OUT C<1> CB<1> C<31> CB<31>THERMOMETRIC DECODER C<0> CB<0> 5 ... SIG_DEL IN OUT D<7>IN OUT FINE D<0>... ... ... Coarse delay Fine delay delay IN OUT 5 3 bit 3 IN OUT C<1> CB<1> C<31> CB<31>THERMOMETRIC DECODER C<0> CB<0> 5 ... SIG_DEL IN OUT Figure 5 5. Digitally Co ntrolled Delay Line Each coarse delay step accounts for 80 ps delay in the system. The LDL is controlled by a Binary to Thermometric decoder. A 5 -bit control word from the counter is the input to the decoder and it generates a 32 -bit output in its true and complement form. These decoded outputs determine the number of Lattice Delay Units to be included in the delay line. The 5 bit control of the coarse delay line is the same for all the 8 -phases in the system. So when the control word increases by one bit, one extr a delay unit is added to each phase of the delay line so that all the phases are properly aligned at 45 degree offset to each other. As shown in Fig 5 5, t he fine delay cell has an always active tri-state gate with 2 addition tri -state gates in parallel to it. By turning on/off the tri -state gates the driving capability of the cell increases /decrease and thus the delay decreases /increases The delay associated with each fine cell is ~ 40ps. To enable the duty cycle control with the fine delay c ell, a n additional eight NMOS and PMOS are arranged in parallel to the always active tri -state. These NMOS and PMOS makes the tri -state negative skewed or positive skewed depending upon the duty cycle control bits given by the duty cycle decoder.

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116 In itially four PMOS and four NMOS are ON. Based on the output from PD3, the duty cycle control bits will vary the strength of the PMOS and NMOS and force the duty cycle of the output clock equal to that of the reference clock. The sigma -delta delay is an inverter parallel with a tri -state which is controlled by the sigma delta modulator. Turning on/off the tri -state cause s ~20ps delay difference in the delay line. 5 4 Circuit Implementation 5 4 1 Current Mode PWM Control The boost converter in this work employ s c u rrent -mode PWM contro l to provide a regulated output voltage. As shown in Fig. 5 6 the controller includes a resistive divider R1R2, an error amplifier, a voltage comparator, a n oscillator (O SC ), an inductor -current sensing circuit and an R -S flip -flop to generate the driving clock (CKS) with duty cycle (D). The OSC sends short pulses (signal S ) with a constant period TS to the RS latch, synchronizing the rising edge of the switching signal CKS, as shown in the presented waveforms. Then the duty cycle of CKS is modulated by the comparator s output ( signal R ), which is determined by the error voltage (VERR) and the sensed current waveform (VSEN). VSEN is provided via a current sensing circuit, emulating the rising ramp of the inductor current (IL) by sensing the NMOS s drain voltage (VC). The current mode PWM has two feedback paths: one is the voltage feedback to regulate the output voltage VO, which is similar to the voltage -mode PWM (see Section 2.3.1); another one is the inner current feedback to re gulate the inductor current IL. Therefore, in this current mode PWM, the inductor current can modulate the control signal CKS directly through the comparator, resulting in faster transient response s compared to the conventional voltage -mode PW M [83] However, the current mode PWM has sub -harmonic oscillation problem, requiring slope compensation generated from OSC [84]

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117 VC VREFVERR Slope Compensation S R Q VO Current Sensing+ +R1R2 OSC + CKs VERRVSENVSENILS R CKs +Current Mode PWMError Amp -Comparator Voltage Feedback Current Feedback Figure 5 6 Current m ode PWM controller P2P1 N2 N1P0N0 V+ V Vbp2Vbn2Vbn1VOUTVbp1 Vbp3 Rz=60kohm Cz=800fF Cp=165fF VREF ++VOR1=7R2R2 VERRR3R4=4R3 +VSEN To R S Latch Comparator Error Amplifier Voltage Feedback Path Figure 5 7 Schematic of the error amplifier and the comparator in the voltage feedback loop To stabilize the voltage feedback loop in this current mode PWM controller the classical type -II compensation network (i.e. CP, CZ, RZ) is utilized for the voltage error amplifier [35]

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118 [85] While the compensation network is fully integrated, it is external to the amplifier itself. The transfer function for the compensated error ampli fier assuming ideal amplifier analysis, is written as below [85] : pc p z zc z p z p z z zs s R R C C s R C C s R R C C s R sC s A 1 || 1 || 1 || 1 ) (2 1 2 1 (5 4 ) where the zero and non-origin pole are ZC=1/RZCZ and PC=1/ ( RZ(CZ//CP) ), respectively Eq. 5 1 indicates the compensat ed amplifier introduces a pole at the origin and a single pole zero pair. The primary reason for using this compensation method is to obtain very high gain at dc, due to this p ole at the origin, to reduc e the dc error T he pole -zero pair provides a constant gain and a reduced phas e lag between the zero frequency ZC and the pole frequency PC. By combining Eq. 5 4 with the small -signal model of the boost converter in DCM, the l oop gain of the voltage feedback loop can be expressed as [85] : 1 _1 1 12 ) 1 2 ( 2 ) ( ) (p s o RAMP PP os M M L T RM V V s A s T (5 5 ) w here =R2/(R1+R2) is the divider ratio, VPP_RAMP is the amplitude of the voltage ramp, M=VO/VIN is the voltage conversi on ratio, and RO is the load res istance P1 is the pole introduced by the boost converter topology operated in DCM which can be derived as [85] o o pC R M M 1 2 1 11 (5 6 ) w here CO is the load capacitance. F or t he minimum load or largest RO, the boost converter s pole, P1, is about 2.85Mrad/s. Then, to ensure stability, we allocate the pole -zero pair of the

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119 compensation to PC =125Mrad/s and ZC =20.8Mrad/s by choosing the resistor and capacitor values a s shown in Fig.5 7 As shown in Fig. 5 7, t he same two stage folded-casc o de amplifier design is used in both the error amplifier and the comparator. To achieve rail to rail input common -mode range, the first stage combines two folded-cascode amplifiers with NMOS a nd PMOS differential pair s in parallel [67] The R3R4 voltage divider is inserted at the output of the error amplifier to limit the maximum value of VERR to 0.8VDD. With this condition, VSEN will cross VERR when the boost converter turns on, ensuring correct system start up. D0D1 m1m2 D VERR VERR D0D1 Dm1m2 (a) (b) VERRD Dm1m2 D D Subharmonic Oscillation 2TIL D VERRCompensation Slopem1m2 D0 D1 (c) (d) Figure 5 8 Demonstration of loop instability in a current mode converter when (a) D>0.5, (b) D<0.5, (c) subharmonic oscillation occurs, and (d) D>0.5 with slope compensation. For a current mode PWM converter, without compensation, the inner current loop is unconditional ly u nstable when the duty cycle is above 50%, or D>0.5 [84] As shown in Fig. 8 a and 8 b, the error voltage VERR sets the peak value of IL (by limiting VSEN defined in Fig 5 6) and

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120 modulates the duty cycle of the converter When an initial perturbation in the duty cycle D0 occurs it will decrease with time for D<0.5 (see Fig. 8 a), and increase for D>0.5 (see Fig. 8 b). The dotted line represents the resulting current waveform after the perturbation in duty cycle. The s e duty cycle instabilities in the current loop can cau se subharmonic oscillation of the converter, shown in Fig. 8 c. In this case, the inductor current error affects the output voltage and then the error voltage via the voltage feedback. As a result, the error voltage VERR oscillate s at one -half the switching frequency, showing a duty cycle variation D in consecutive pulses. To avoid this subharmonic oscillation we can introduce a ramp in the error voltage to force the duty cycle error to decrease with time, as shown in Fig. 8 d. Notice that in this case D1 is smaller than D0. This technique called slope compensation effectively adds damping to the subharmonic oscillation. T he slope may either be added to the current waveform or subtracted from the error voltage [84] In our design, this slope is generat ed by OSC, which will be discussed in S ection 5.4.3 5 4 2 Current Sensing Circuit To implement a current mode PWM controller, a current sensing circuit is design ed to sense the drain current of power switch N0 (see Fig. 5 1), emulating the rising slope o f the inductor current As shown in Fig. 5 9 N0 is the 1.2V thin -gate power switch while N2 is a sensing transistor whose size is KN times smaller than that of N0. When the control signal CKS turns on switch es N0, N2 and N3 simultaneously due to the bal anced signal path design the switches N4 and N5 are turned off. Since the current IMIN is very small, the drain -to -source voltage of N3 can be neglected (a small effective I -R drop), meaning Vis approximately equal to the drain voltage of N0 (VC). The d rain voltage of the sensing transistor N2 (V+) also equals Vdue to the negative feedback loop containing A0 and P0. Therefore, w ith the same drain voltages and gate -source voltages N2 s drain -current is proportional to N0 s drain current. Specifically, the drain current

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121 of N2 is KN times smaller than N0 s drain current IN0 and is equal to IL/ KN. T h is emulated inductor current is then reproduced by the P0-P1 current mirror with a factor KP, generating a sensing voltage VSEN=RSENISEN=RSENILKP/KN. During t he OFF period of CKS, N2 and N3 are turned off to disconnect the current sensing circuit from the power switch Switches N4 and N5 are turned on supplying P0 s drain current with IMIN, thereby setting the sensing voltage to a much smaller value: VSEN=RSENIMINKP. + + CKSCKS VSENIMIN VX0 VC2.5V N0N1N2N3P0P1N4N5ISEN RSENA0V+VCurrent ramp generator from OSC IRAMP IN0=IL+IMIN~IL When CKS= 1 VIN VO Current sensing Circuit DADBDC IN2=IL/KN Figure 5 9. Schematic of the c urrent sensing circuit T he described current sensing circuit is easily stabilized because both input nodes of A0 have low impedance due to the low on -resistances of switches N2N5. As a r esult, there is only one high -impedance node at the output of A0. Stability is then easily achieved by using large sizes for P0 and P1, provid ing dominant pole compensation through their combined gate capacitances

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122 5 4 3 Oscillator (OSC) A n RC oscillator g enerating the trigger frequency (fTRIG) and the compensation slope (IRAMP) is shown in Fig. 5 10. An externally programmable current source biased with IBIAS generates VRAMP on the capacitor CF. When VRAMP reaches a threshold set by the RHRL divider, A1 o utputs a short pulse to reset VRAMP to ground with switch N1. An inverter chain acting as a delay line, is inserted before N1 to set the pulse width to ~500ps. Meanwhile, turning on switch N2 modifies the divider ratio by putting RN in parallel with RL, a dding a hysteresis to comparator A1 for stable operation. The frequency of short pulses fTRIG (i.e. the frequency of the switching converter) ranges from 40MHz to 200MHz, and is controlled by switches F1-F5 to vary the rising slope of VRAMP. A current ramp generator translates VRAMP in OSC to IRAMP, which provides slope compensation to VSEN, the output from the current sensing circuit. A voltage follower comprised of A2, P2 and RA recreates the ramp voltage on RA, thus P2s current is VRAMP/RSEN by setting RA=RSEN. T his current is then copied via a programmable current mirror to IRAMP, which is added to ISEN for slope compensation. The copy ratio is controlled with switches S1-S4, va rying the compensating slope. + + + A1 IBIAS F1 F5 1X 16X 8X 2X F2 + + + A2 S1 S21Y 2Y S48Y RSEN Current ramp generator From current sensing circuit 1Y 16Y CFN1N2fTRIGN3P1P2 VRAMPIRAMP VSEN ISEN RHRL To RS latch RA=RSENVADD IP2=VRAMP/RSEN RN Figure 5 10. Schematic of the oscillator (OS C) with current ramp generator

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123 5 4 4 Layout for Power Switches The size of the high voltage devices are selected to optimize the efficiency at load currents of ~0.1A and operational frequency around 100MHz. Fig. 5 11 shows t he layout of the output stages o f the single phase boost converter 130nm CMOS process It is di stributed into multiple layout cells, each cell measures 20 m wide and contains a distributed power grid for VIN and GND, an input decoupling capacitor, stacked NMOS switch with driver, and an SBD between VX and VOUT. With decoupling capacitor inserted among the switch cells, the width of power traces is increased and the current density is reduced. The total layout measures 380 m by 150 m with the high voltage devices (i.e. NMOS and SBD) occupying 0.025mm2, approximately 43% of the total area 20 mVX Single Phase Boost Converter VX GND VINVOUTVOUT Thick Gate Driver Stacked NMOS VX 150 m 380 m VOUTCapacitor 20 mSBD Figure 5 11. Layout for the output stages of the single phase boost c onverter

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124 5 5 Measurement Results A 4 -pha se D DLL controlled boost converter was fabricated in standard 0. 13m 1.2 V CMOS process to verify the proposed D DLL -based control scheme and high voltage devices The die photo is shown in F ig. 5 12. The co nverter occupies approximately 0 55 mm2, which includes a 0 13mm2 D DLL based controller and ~1 nF on -die input decoupling capacitor. The converter performance was evaluated using four SMT size 805 22nH air core inductors with quality factor of 33 at 100MHz and a 2 5 nF external chip capacitor. Figure 5 12. Die photo 5 5 .1 Four Phase Operation The converter is tested with 1.2V input and 3V 5V output range. A 2.5V gate voltage for thick gate device is provided externally, which should come from the output in a complete system design. At a load voltage/current of 4V /40mA staggered operation of the four phases at the switching output is demonstrated in Fig. 5 1 3 The converter control signal CKS0 (i.e. the input reference of the D -DLL) shows 50% duty cycle. Each phas e of the boost converter operates in DCM and the schottky diodes have an on -time of ~10% of the period. The switching signal s

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125 of the 4 phase converter maintain 90o offset appropriat ely among the phases (VX0-VX270) increasing the effective charging frequen cy by a factor of 4 seen from the output and leading to output capacitor size reduction. In addition, the stager operation cancel out the total input current ripple, indicating proper phase synchronization and duty cycle accurate operation of the controlle r. Figure 5 1 3 Measured waveform s of 4 -phase boost converter D DLLs performance is summarized in Table 5 1. The attainable duty cycle range is 10% 90% for 50 100MHz frequency, ensuring the 30%80% duty cycle range for the designed 100MHz boost convert er. It occupie s 0.11mm2 die area and dissipates 1.2mW at 100MHz. Fig. 5 1 4 demonstrate the jitter histogram while boost converter is operational and D DLL s sigma delta modulator is on or off. With the sigma -delta active, the D DLL output clock indicates a 1 2.1 ps rms and 9 0 .9 ps peak-to -peak jitter. Without the sigma delta, the rms and peak to peak jitter are 15.5ps and 100ps respectively indicating approximately 20% and 10% difference.

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126 Table 5 1 D -DLL p erformance summary Frequency Range 50~100MHz Duty Cycle Range 10% 90% RMS Jitter 12.1 ps@100MHz Peak to peak Jitter 90.9 ps@100MHz Power 1.2mW@100MHz Area 0.11mm 2 (a) (b) Fig ure 5 1 4 Measured jitter whi le boost converter is operational and DDLL s sigma -delta modulator is (a) on and (b) off. 5 5 2 Efficiency The measured power efficiency versus load current for different step up ratio is shown in Fig. 5 1 5 T he 4 -phase converter delivers a maximum load of 80mA at 3V or an output power of 240mW The pe ak efficiency of 64% is achieved for a load current of 6 0m A at 3V. At higher output voltages of 4V/5V the efficiency degrades due to higher switching losses. In DCM operation, the duty cycle of the converter is strongly dependent on both the step up ration and the

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127 load current level. Therefore, the maximum duty cycle of the converter limits the achievable output power. Fig. 5 1 5 shows that higher output voltages of 4V/5V achieve a maximum out put power of ~200mW with 60% efficiency. 20 30 40 50 60 70 0 20 40 60 80 100 Efficiency (%) Load Current (mA) Vo=3V Vo=4V Vo=5V Four -phase Boost Converter Figure 5 1 5 Measured efficiency 5 5 3 Transient Response Fig. 5 1 6 shows t he transient response for a 50% load step and input voltage of 1 2 V The current step was generated using an on -chip load with a simulat ed rise /fall tim e of ~ 200 p s. The same stacked NMOS structure is used in the on -chip load to sustain high voltage output level. In all cases the worst -case voltage variation caused by current step is less than 7%.

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128 0 2 4 6 8 2.5 3 3.5 4 4.5 Time (us) Voltage (V) Voltage (V)20mA current step 40mA current step Fig ure 5 1 6 Measured load response for 50% current step L=22nH/phase and C= 25nF over 3V/4V output voltages 5 5 4 Performance Summary Table 3 2 summarizes the measured boost converter performance. Because the power input VIN is not directly connec ted to the on -chip circuit VDD, we can measure the converter with higher input voltage while powering the on -chip c ircuit with 1.2V VDD. The output range is 3 5V with 1.2V 2V input range. Higher input voltage s result in an output v oltage larger than 5V and cause reliability issues due to possible breakdown of the stacked switch, as presented in Section 5.2.3 With 1.2V/3V input/output voltage, t he converter can deliver up to 80mA/240mW to the load and achieve peak efficiency of 64% at the load of 60mA/180mW [52] In addition, this converter achieve high -frequency switching and DCM operation without dead time control, and with an output voltage range of 3 5V which is equivalent to ~4x the rated voltage of the process, enabling integrated boost converters topologies in standard CMOS designs without additional processing steps. Table 3 3 show s a performance comparison with previously reported integrated

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129 h igh frequency DCM boost converters in 180nm CMOS process in [72] [74] Compared to the 100MHz single phase converter in [74] the 100MHz 4 phase converter in this work [86] shows higher step up ratio and power level. A nd c ompared to 6 0MHz converter in [72] th is work has much higher power level and efficiency with comparable step up ratio Table 5 2. Performance summary Technology Input Range 1.2V 2V Output Range 3V 5V Converter Area 0.42mm 2 Controller Area 0.13mm 2 Total Area 0.55mm 2 Inductor 22nH / phase Output Capacitor 2 5 nF Output Ripple <200mV Max. Current @ 1.2V Input 80mA @ V O =3V Peak Efficiency @ 1. 2V Input 6 4 % @ V O =3V Table 5 3 Performance c omparison [74] [72] This Work [86] Technology 180nm 180nm 130nm Rectifier Type Stacked PMOS PN Junction SBD Phases 1 1 4 Input Range 1.6V 2V 1.8V 1.2V 2V Output Range 2.5V 4V 6V 9V 3V 5V Frequency 100MHz 60MHz 100MHz Inductor 18nH 20nH 22nH X 4 Capacitor 1.3nF N/A 2 5 nF Output Ripple <200mV 450mV <200mV Max. Power 150mW N/A 240mW Max. step up ratio ~2.3@150mW 5@0. 81mW ~4@200mW Peak Efficiency 63%@80mW 28%@3.6mW 64% @ 180mW 5 6 Summary A D DLL based hysteretic control scheme for high -frequency multi -phase boost converters is presented. The controller generates multiphase synchronization signals with accurate dut y cycle control directly from a n independent single phase boost converter with current mode

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130 PWM The boost converter was implemented in 130m 1.2 V CMOS process. And integrated schottky diodes and stacked NMOS with ~10V breakdown voltages were utilized to e nable higher voltage output. Measurements indicate a wide voltage conversion range of 30% to 80% for 100MHz switching frequency The peak output power is 240m W and the peak efficiency is 64% at ~ 180m W for l .2V/3V of input/output conversion The proposed di gitally assisted multiphase synchronization scheme can be easily accommodate ultra high-frequency converters with different structure (buck or boost) and control loop (PWM / hysteretic) enabling fast and flexible power management design strategies in syst em on-chip application.

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131 CHAPTER 6 CONCLUSIONS AND FUTU RE WORKS 6 1 Summary and Contributions The focus of this dissertation is the design of integrated converter power supplies for use in modern microprocessors or battery powered portable sy stem These circuits have strict design requirements, such as near load converter insertion (on -chip or on -package), smaller filter sizes, faster response times, as well as operation at higher frequencies. Multiphase techniques and hysteretic control are t wo suitable options for achieving the near load converter and small size requirements. The formation of power converter circuits utilizing the combination of these two options is the subject of my dissertation Specifically, the primary topic is the use of several novel synchronization schemes to realize multiphase and fixed-frequency operation of the current mode hysteretic controller. In addition, multiphase control for current mode PWM, digitally assisted controller design and high voltage device for boo st converter are also investigated and verified in this work. A delay locked loop (DLL) based hysteretic control scheme for high frequency multiphase buck converters is presented in Chapter 3 The DLL control loop employs the switching frequency from a hys teretic comparator to automatically synchronize the remaining phases and eliminate the need for external synchronization. A dedicated duty cycle control loop is used to enable current sharing and ripple cancellation. We demonstrate a 4 -phase high switching frequency (2570MHz) buck converter, with fast hysteretic control and output conversion range of 17.5 % 80% The converter achiev es a peak efficiency of 83% at 2Watts and peak ripple of 20mV A DPLL based frequency locking technique for high frequency hysteretic controlled dc -dc buck converters is presented in Chapter 4 The DPLL locks the converter operating frequency to

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132 a clock reference, eliminating the dependence of switching frequency on conversion ratio In addition, an analysis of how the dc dc converter can be modeled as a VCO is presented. The proposed DPLL converter operates over a wide frequency range of 90 240MHz and achieves a conversion range of 33% to 80%, or 0.4V to 0.96V. Using a single 8.2nH inductor and a 2 5 nF external decoupling capacitance, the converter achieves a load response of 40ns to a 120mA step and ripple voltage less than 25mV. The dc -dc converter was implemented in 130nm 1.2V digital CMOS process and achieves a peak efficiency of 80% at 180MHz f or load current of 200mA. A D D LL based frequency locking technique for high frequency multiphase current mode PWM boost converters is presented in Chapter 5 The proposed controller generates multiphase synchronization signals with accurate duty cycle cont rol directly from an independent single phase boost converter with current mode PWM In addition, integrated schottky diodes and stacked NMOS with ~10V breakdown voltages were utilized to enable higher voltage output The proposed D D LL operates over a wid e frequency range of 5 0 100MHz and achieves a 12.1ps rms jitter when the converter is operational. Using 2 2nH inductor per phase and a 2 5 nF external decoupling capacitance, the converter achieves a load response of ~300ns to a 50% load step and ripple volt age less than 2 00mV. The dc -dc converter was implemented in 130nm 1.2V digital CMOS process and achieves a peak efficiency of 64% at 1 0 0MHz for load voltage/ current of 3V/8 0mA. 6 2 Future Works This dissertation has explored some high frequency synchroniz ation s olution s for hysteretic or PWM dc -dc converters. The provided solutions has enabled conventional hysteretic controller to operate in multiph ase configuration or in fixed frequency mode. Suggested future works includes the following.

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133 In this work, th e present ed dc -dc converters can operate with 100200MHz switching frequency resulting in on-board inductor values between 8 22nH per phase and onboard capacitor values around 25nF. I n further works these small passive devices can be integrate d on the s ame package or on the same die together with the converter. New issue s will emerge includ ing the device area device variation and modeling, and the system efficiency problems This will be a challenging and interesting research topic. A nother potential research direction is to further improve the hysteretic control ler s capability based on the ideas proposed in this work In Chapter 4, the DPLL synchronization schem e is applied in a current -mode hysteretic control loop, which is typically used in CCM buck converter s In CCM converter s the duty cycle and the switching frequency are mainly determined by the voltage conversion ratio and slightly dependent on the load current. In contrast the duty cycle and the switching frequency in DCM converter s strongly depend on the load current. For instance, in a DCM converter with a voltage -mode hysteretic controller, the switching frequency is proportional to the load current, as introduced in Section 2.3.2.2. Then one research topic can be comb in ing this type of converter with the proposed DPLL synchronization scheme in Chapter 4 In this case wh en ever the varying load current changes the switching frequency, the DPLL can lock the frequency to a fixed reference freque ncy or its subharmonic frequencies pr oviding better frequency control capability for light load efficiency improvement and noise spectrum shaping In addition, assuming the voltage conversion ratio is fixed, the DPLL s control words is then proportional to the load current providing indirect ly current sensing capability for further system monitoring or real -time reconfiguration.

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141 BIOGRAPHICAL SKETCH Pengfei Li received the B.S. degree in electrical engineering from Tsinghua University, Beijing, China, in 2004 and the M.S. degree from University of Florida, Gainesville, FL, in 2006. He re ceived his Ph.D. from University of Florida in the fall of 2009. His research interests include low power analog circuits, integrated power converters, biomedical circuits and wireless interfaces. He is the recipient of a 2007 Outstanding Student Designer Award from Analog Devices, Inc