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PAGE 1 1 MODELING, DESIGN, AND PERFORMANCE OF NANOSCALE DOUBLEGATE CMOS By SIDDHARTH CHOUKSEY A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2009 PAGE 2 2 2009 Siddharth Chouksey PAGE 3 3 To my family, friends, and the almighty PAGE 4 4 ACKNOWLEDGEMENTS Being where I am today is literally a dream come true. I believe success happens when talent meets an opportunity. Numerous opportunities came my way, many times indirectly and disguised,thatmadeallthispossible.Idonotknowwhatmadethoseopportunitiescomemyway, if not, the supreme force guiding our lives God. Therefore, rst of all I would like to thank God formakingthisPh.D.apartofhisplan.Idonotthinkitswithinmycapabilitytofullyexpressmy senseofaweandgratitudetowardmyadvisor,Dr.JerryG.Fossum.Workingwithhimhasbeena tremendous learning experience from me. He taught me not only through the classes, feedbacks, and discussions, but many times when he was not even intending! I have learned a lot just by watchinghimwork;hisenthusiasmforwork,patience,andanalyticalskillsareexemplary.Ithank Dr. Fossum for his support and guidance throughout my work. I would like to thank Dr. Scott Thompson, Dr. Jing Guo, and Dr. Selman Hersheld for agreeing to be on my committee as well as for helpful discussions during my research work. I would like to acknowledge Freescale Semiconductor for their support, and thank Intel Corp. for giving me opportunity to intern with them twice. I would like to thank my mother for her undiminished condence in me, and for all her prayers. I will not be surprised if this Ph.D. means more to her than what it means to me. I wouldliketothankmyfatherforhissupport,andmybrother,sisterinlaw,sister,brotherinlaw, my niece and nephew for their encouragement. I was fortunate to have Murshed Chowdhury, Shishir Agrawal, Zhichao Lu, Zhenming Zhou, Weimin Zhang, SuengHwan Kim, and Dabraj Sarkar as my colleagues. I would like to thank them for all the help they extended to me throughout my work. I would like to thank my numerous friends, in and out of Gainesville, for their companionship through these years. PAGE 5 5 TABLE OF CONTENTS page ACKNOWLEDGEMENTS............................................................................................................4 LIST OF TABLES................................................................................................................ ..........7 LIST OF FIGURES............................................................................................................... .........8 LIST OF ABBREVIATIONS.......................................................................................................10 ABSTRACT...................................................................................................................... ............11 CHAPTER 1 INTRODUCTION..............................................................................................................1 3 2 DICE: A BENEFICIAL SHORTCHANNEL EFFECT IN DOUBLEGATE MOSFETs........................................................................................................................ .... 18 21 Introduction............................................................................................................... ..18 22 Modeling................................................................................................................... ...18 23 Model Corroboration and Predicted DICE Impacts....................................................23 24 Summary.................................................................................................................... ..26 3 THRESHOLD VOLTAGE ADJUSTMENT IN NANOSCALE DG FINFETS VIA LIMITED SOURCE/DRAIN DOPANTS IN THE CHANNEL..........................................38 31 Introduction............................................................................................................... ..38 32 S/D DopingDependent Vt...........................................................................................39 33 Demonstration and Verication of Design Approach..................................................42 34 Sensitivity and RDF Analyses.....................................................................................43 35 Summary.................................................................................................................... ..45 4 PHYSICAL INSIGHTS ON ANALOG/RF PERFORMANCE OF DOUBLEGATE FINFETS, WITH COMPARISION TO BULKSILICON MOSFETS................................51 41 Introduction............................................................................................................... ..51 42 Device Characteristics.................................................................................................52 43 RF FinFET Scaling......................................................................................................57 44 Summary.................................................................................................................... ..60 5 INSIGHTS ON DESIGN AND SCALABILITY OF THINBOX FD/SOI CMOS............68 51 Introduction............................................................................................................... .....68 52 LP Devices................................................................................................................. .....69 PAGE 6 6 53 HP Devices................................................................................................................. ....74 54 Comparisons with FinFETs............................................................................................76 55 Conclusions................................................................................................................ ....78 6 SUMMARY AND FUTURE WORK..................................................................................87 61 Summary.................................................................................................................... .....87 62 Future Work................................................................................................................ ....89 APPENDIX UFDG MODEL REFINEMENTS.......................................................................................90 A1 Introduction............................................................................................................... .....90 A2 StrongInversion Intrinsic Charge Modeling.................................................................90 A3 WeakInversion Inner Fringe Charge Model.................................................................93 A4 DIBLDependent Denition of VTW............................................................................93 LIST OF REFERENCES............................................................................................................ ..96 BIOGRAPHICAL SKETCH......................................................................................................100 PAGE 7 7 LIST OF TABLES T able page 21UFDGpredictedDICEandDIBLinanLg=18nmnMOSFETwithvaryingUTB thickness, with and without a 2nm gatesource/drain underlap.........................................28 31MedicipredictedsensitivityofIofftovariationsin sLofNSD(y)intheLg=18nmLPand HP DG FinFETs................................................................................................................46 32MedicipredictedstandarddeviationofVtwandassociatedIoffbasedyieldduetotheRDF of NSD(x,y) in the Lg = 18nm LP and HP DG FinFETs...................................................46 41ComparisonofUFDGpredictedfTofanLg=28nmDGFinFEThavingaGS/Doverlap, withthatofFinFETshavingGS/Dunderlapoptimizedforlowpowerandhighfrequency RF applications................................................................................................................ ..61 51Tauruspredicted characteristics of Lg = 25nm (= Leff) FD/SOI nMOSFETs with midgap gate and tSi = 6nm..............................................................................................................80 52Tauruspredicted characteristics, vs. tSi, of Lg = 25nm thinBOX/GP nMOSFETs with 2.5nm GS/D underlap and midgap gate............................................................................80 53Tauruspredicted characteristics, vs. VGP, of Lg = 25nm thinBOX/GP nMOSFETs with 2.5nm GS/D underlap and midgap gate............................................................................81 54Tauruspredicted characteristics, vs. Leff, of thinBOX/GP nMOSFETs with VGP for strong accumulation and controlled DIBL.........................................................................81 55Tauruspredicted characteristics, vs. Leff, of thinBOX/GP nMOSFETs with VGP for strong accumulation...........................................................................................................8 2 56Tauruspredicted LP and HP scaling limits dened by tSi = 5nm, for thinBOX/GP MOSFETs and DG nFinFETs............................................................................................82 PAGE 8 8 LIST OF FIGURES Figure page 11StructureofaFinFETwithgatewrappedovertheverticalfin,formingtwosidewallgates. ............................................................................................................................... .............17 21Results of calibrating UFDG to an undoped Lg = 60nm DG pFinFET (fin aspect ratio hSi/ tSi = 100nm/17nm), with and without DICE.....................................................................29 22IllustrationofaDGMOSFETbiasedinthesaturationregion,showingthebody/channel divided into a gradual channel and a highfield portion....................................................30 23UFDGpredictedgradualchannellength,relativetoLg=18nm,versusdrainvoltagefora DG nMOSFET, with and without DICE............................................................................31 24MedicipredictedinversionelectrondensityacrosstheUTBatthevirtualsourceofa simple 18nm DG nMOSFET for low and high drain voltages..........................................32 25UFDGpredicteddraincurrentversusvoltagecharacteristics,withandwithoutDICE,of an 18nm DG nMOSFET....................................................................................................33 26UFDGandMEDICIpredicteddraincurrentversusvoltagecharacteristicsofthe18nm DG nMOSFET...................................................................................................................34 27UFDGpredicteddraincurrentversusvoltagecharacteristics,withandwithoutDICE,for the18nmDGnMOSFET,butwiththeproperseriesresistance,mobility,andvelocityovershoot modeling............................................................................................................3 5 28UFDGpredictedgatecapacitanceversusvoltagecharacteristicsofthe18nmDG nMOSFET at low and high drain voltages, with and without DICE.................................36 29UFDG/Spice3predictedoutputvoltagetransientofatwostage18nmDGCMOSinverter chain,withtheinputvoltagepulsingshowntorevealthe(pulldownpluspullup) propagation delay.............................................................................................................. .37 31S/DextensionlateraldopingprolesinanundopedDGFinFET,showingvariable encroachment into the channel.......................................................................................... 47 32Measured(a)stronginversionand(b)subthresholdcurrentvoltagecharacteristicsoftwo Lg=70nmundopedDGnFinFETs,whichhavedifferentNSD(y)duetovariationsintheS/ D processing................................................................................................................... ....48 33UFDGpredicted (a) subthreshold and (b) stronginversion currentvoltage characteristics of the 18nm LP and HP DG FinFETs................................................................................49 PAGE 9 9 34TheDGFinFETstructureshowinghowtheS/Dextensionandchannelregionswere partitioned to account for the RDF of NSD(x,y) in the Medici domain.............................50 41UFDGpredicted gDS of a 28nm DG FinFET....................................................................62 42UFDGpredictedCG(normalizedtohSi)versusVGSatVDS=1.2V,withandwithoutGS/ D underlap..................................................................................................................... .....63 43UFDGpredicted gm versus Lg of DG FinFETs with an abrupt S/D doping profile.........64 44UFDFpredictedgDSversusLgfortheFinFETs,withandwithoutconsiderationofquasiballistic limit................................................................................................................ ......65 45UFDGpredicted Avo versus Lg of DG FinFETs...............................................................66 46UFDGpredicted fT versus Lg of DG FinFETs..................................................................67 51Basic thinBOX FD/SOI nMOSFET structure, with P+ GP..............................................83 52TauruspredictedweakinversioncharacteristicsofathinBOXdevicealongwithUFDG calibration.................................................................................................................... ......84 53ComparisonofTauruspredictedIDSVGScharacteristicsofthinBOXFD/SOIdevicesw/ and w/o GP..................................................................................................................... ....85 54ComparisonofTauruspredictedIDSVGScharacteristicsofthinBOXFD/SOInMOSFET with that of DG nFinFET...................................................................................................86 PAGE 10 10 LIST OF ABBREVIATIONS MOSFETMetalOxideSemiconductor FieldEffect Transistor CMOSComplementary MOS SOISilicononInsulator FDFully Depleted PDPartially Depleted UTBUltraThin Body UFDGUniversity of Florida DoubleGate SCEShortChannel Effect DIBLDrainInduced Barrier Lowering DICEDrainInduced Charge Enhancement QMQuantumMechanical SDESource/Drain Extension SGSingle Gate SSubthreshold Slope RFRadio Frequency TBOXThin Back Oxide GPGround Plane LPLow Power HPHigh Performance PAGE 11 11 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulllment of the Requirements for the Degree of Doctor of Philosophy MODELING, DESIGN, AND PERFORMANCE OF NANOSCALE DOUBLEGATE CMOS By Siddharth Chouksey December 2009 Chair: Jerry G. Fossum Major: Electrical and Computer Engineering This dissertation seeks to understand the unique physics of, to explore nonconventional ways of designing, and to gain insights on the performance of nanoscale doublegate (DG) MOSFETs, particularly the quasiplanar FinFET structure. Our work includes modeling of draininduced charge enhancement, suggesting a novel way of adjusting the threshold voltage of nanoscale DG MOSFETs via limited source/drain dopants in the channel, comparing the analog/ RF performance of DG FinFETs and bulksilicon MOSFETs, and studying and designing ultrathinBOX FD/SOI MOSFETs with comparisons to DG FinFETs. Draininduced charge enhancement (DICE) is a shortchannel effect which is unique to nanoscaleDGMOSFETswithundopedbodiesbecauseoftheirsignicantlyhighcarriermobility. Wemodelthiseffect,andstudyitseffectonthecurrent,charge,capacitance,andtranscapacitance of DG MOSFETs. We nd that DICE is a benecial effect because it increases current without signicantly affecting gate capacitance. AdjustingthethresholdvoltageofDGMOSFETswithundopedbodiesforlowpowerand highperformance applications is a challenging task. We propose a design approach in which limited densities of source/drain dopants in the channel can be used to effect an adjustment of PAGE 12 12 threshold voltage in DG MOSFETs, while maintaining low sensitivities to randomdoping uctuations. Mostofthecurrentliteratureontheanalog/RFperformanceofDGMOSFETsisbasedon experimentalresults,withlittlephysicsbasedexplanationoftheresults.Wegivephysicalinsights on the design and performance of DG MOSFETs for analog/RF applications, and compare them with bulksilicon MOSFETs. We nd that like for digital applications, DG MOSFETs have superior analog performance than that of conventional planar bulksilicon MOSFETs. Recently, there has emerged a considerable interest in planar FD/SOI MOSFETs with ultrathin BOX. We give our physical insights, based on device simulations, on the design and performance of ultrathinBOX FD/SOI MOSFETs, and check their scalability toward the end of the CMOS roadmap compared with DG FinFETs. PAGE 13 13 CHAPTER 1 INTRODUCTION Scaling conventional MOSFETs, i.e., bulksilicon and partially depleted (PD)/SOI MOSFETs, to gate lengths (Lg) < ~40nm has become increasingly challenging because the channeldopingdensityrequiredhasbecomeveryhigh.ConventionalMOSFETsrelyonchanneldoping density to control threshold voltage (Vt) and shortchannel effects (SCEs). As these devicesarescaled,thelatterarecontrolledbyreducingthedepletionwidthbyincreasingchanneldopingdensity.ForLg<~40nm,therequiredchanneldopingdensityhasbecomesohighthatthe variationinVtduetorandomvariationsinthechanneldopingdensityhasbecomeaseriousissue. At such short Lg, reliable control of channel doping density is virtually impossible. Under this scenario, doublegate (DG) MOSFETs, e.g. FinFETs, have emerged as a most promising candidate to replace the bulkSi MOSFET [1]. The primary advantage of the FinFET is the excellent control of SCEs [2] without relying on channel doping, which makes it potentially scalable to the end of the SIA ITRS roadmap [1]. Since FinFETs rely on undoped ultrathin bodies (UTB) to control SCEs, random variations in threshold voltage (Vt) and other device characteristics due to process variations can be greatly reduced [3]. In Fig. 1.1 we show the basic structure of a FinFET. The gate is wrapped over the thin vertical n, forming two sidewall gates. The top of the n could be gated, forming a triplegate device [4], but we focus on the DG structure which is more pragmatic [2]. DGFinFET technology has not yet received complete acceptance by the integratedcircuits manufacturing companies because of some of the challenges associated with the DGFinFET technology like higher cost of SOI wafers, control of the nanoscale n, and lack of reliablewaysofengineeringthesource/draindopingprole.HighercostofSOIwafershasledto some interest in the bulkSi FinFETs [5], [6]. However, due to signicantly high, controlled PAGE 14 14 substratedoping density required to suppress source/drainleakage current, and need to precisely match the depth of source and drain regions to the substrate doping, the viability of bulkSi FinFETsisdoubtful[7].InordertoscaleDGFinFETstotheendoftheroadmap,reliablewaysof engineering the source/drain prole will have to be developed. This task is particularly challenging because the UTB thickness tends to be about 5nm near the scaling limit of Lg. The diffusion of source/drain dopants through such thin bodies is not well understood. As we will show through comprehensive studies in this dissertation, DG FinFETs tend to have signicantly better performance for both digital and analog/RF applications. But, in order for DG FinFETs to replacebulkSiMOSFETs,thetechnologicalchallengeslikethosementionedherewillhavetobe overcome. ThephysicsofDGMOSFETs,withcoupledgatesandUTB,issignicantlydifferentfrom bulkSi MOSFETs. Also, designing them for various applications is signicantly different from designing bulkSi MOSFETs. Designing circuits with independently controlled bias on the two gates of DG MOSFETs [8], using the space between two ns on the Si substrate to enhance the drive current (ITFET [9]), and engineering the S/D extension region to realize a biasdependent effective channel length (Leff) [2] are some of the unique possibilities that exist with DG MOSFETs.Therefore,needlesstosay,inordertorealizethefullpotentialofDGMOSFETs,their physicshastobebetterunderstood,andnonconventionalwaysofdesigningthemwillhavetobe explored.Inthisdissertationwediscussourcontributionstowardsthesegoals.SinceDGFinFETs are most prospective among all the contemporary DG MOSFETs, we use them as the representative DG MOSFET structure in our studies, although most of the discussion in this dissertation is generically applicable to all kinds of DG MOSFET structures. InFinFETs,theundopedUTBbetweenthetwo(connected)gatesresultsinunusuallylow transverse electric eld and quite high carrier mobility ( meff) [10], [11]. This produces signicant PAGE 15 15 saturationregion effects [12] that are not prevalent in the conventional devices, e.g., carriervelocity overshoot [13] and nearballistic transport [11]. Draininduced charge enhancement (DICE), which is a stronginversion counterpart to the draininduced barrier lowering (DIBL) in weakinversion,issuchaneffectthatheretoforehasnotbeengenerallyacknowledged.InChapter 2,thesignicanceofDICEinDGMOSFETsisrevealedviaanalyticalmodeling,implementedin our physicsbased compact model UFDG [14], [15], [16] and supported by numerical device simulations. Because of the undoped body, there is no pragmatic way of tuning Vt of DG MOSFETs forlowpower(LP)andhighperformance(HP)applications.However,theundopedbodyenables the design of DG MOSFETs with GS/D underlap. It has been shown that incorporating GS/D underlap in the DG MOSFET design yields Leff that decreases with increasing gate bias (VGS), and that can hence be used to effect a design tradeoff between SCE control, or offstate current (Ioff) for LP applications, and S/D series resistance (RS/D), or onstate current (Ion) for HP applications [17]. In Chapter 3, we show how this IoffIon design tradeoff can be extended by allowing limited densities of S/D dopants to diffuse into the FinFET channel for direct Vtadjustment in HP versus LP applications. While CMOS scaling is predominantly driven by digital applications, analog performance can benet from scaling [1]. For bulkSi MOSFETs, for example, the transconductance (gm) increases with scaling. And, scaling is the primary way of improving the cutoff frequency [fT = gm/(2 p CG) where CG is the total gate capacitance] of analog devices. However, these benets come with a cost of enhanced SCEs that undermine the output conductance (gDS) and voltage gain (Avo = gm/gDS) of the bulkSi MOSFETs. Therefore, there is considerable interest in exploring the possibility of using FinFETs, which have better Lg scalability than bulkSi PAGE 16 16 MOSFETs, for RF applications. In Chapter 4 we use our physical insights, supplemented with published numerical simulation and experimental results, to check the analog guresofmerit (FOMs) of DG FinFETs, and compare them with those of bulkSi MOSFETs. Recently, there has been a noticeable interest in the planar ultrathinbox fully depleted (FD)/SOIMOSFET[18]asanalternativetotheconventionalbulkSiMOSFET,andinlieuofthe quasiplanarFinFET.ThemotivationforthiskindofMOSFETarchitectureisthebettercontrolof SOI UTB thickness as compared to that of the nUTB thickness, in addition to the close similaritiesofFD/SOIandPD/SOIprocessing.InChapter5,wedoathorough,simulationbased evalutation of ultrathinbox FD/SOI CMOS, projecting LP and HP scaling limits and noting needed process complexities, with comparisons to FinFET CMOS. In Chapter 6 we conclude this dissertation with a summary and suggestions for future work. In Appendix A we describe the UFDG model renements done for more reliable predictions of nanoscale DG MOSFET characteristics, as discussed herein. PAGE 17 17.Figure11.StructureofaFinFETwithgatewrappedovertheverticaln,forming two sidewall gates. PAGE 18 18 CHAPTER 2 DICE: A BENEFICIAL SHORTCHANNEL EFFECT IN DOUBLEGATE MOSFETs 21 Introduction Draininducedbarrierlowering(DIBL)[19]isawellpublicizedSCEinscaledMOSFETs. In accord with the 2D Poisson equation in the weakly inverted channel/body, high drain bias (VDS) lowers the potential barrier height at the virtual source, thereby allowing increased carrier diffusion from the source to the channel, causing higher Ioff, and lowering the (saturation) Vt. Draininduced charge enhancement (DICE) is the counterpart effect in strong inversion, which wasanalyzedforclassicalSOIMOSFETsabout20yearsago[20]butwhichheretoforehasbeen insignificant.WorkbasedonnumericalsimulationsofbulkSiMOSFETspublishedin1980[21] revealed the effect, also showing it to be insignificant. However, we show in this chapter, and explain why, this is not the case for nanoscale DG MOSFETs, in which DICE can significantly benefit the drive, or saturationregion current (IDS(sat)) and CMOS speed, with little effect on the gate capacitance. 22 Modeling Calibrations of UFDG to fabricated nanoscale FinFETs, with undoped UTBs, have tended to give results like the IDSVGS characteristics of an Lg = 60nm device [22] shown in Fig. 2.1. Note that the UFDG predictions agree well with the measured data, except for high VDS, i.e., in the saturation region where UFDG underpredicts IDS(sat) (by about 7% for this 60nm FinFET). We have inferred from such results, complemented by numerical device simulations, that DICE can signicantly affect the saturationregion current of nanoscale DG MOSFETs. The saturation region of the nanoscale MOSFET is characterized, as illustrated in Fig. 2.2, by a UTB/channel that can be divided into a gradual [19] portion (0 < y < Lgch) adjacent to the source and a highelectric eld (i.e., Ey) portion (Lgch < y < Lg) adjacent to the drain in which PAGE 19 19 carrier velocity is saturated. (Below saturation, for VDS < VDS(sat), Lgch = Lg.) Actually, when velocity (v) overshoot occurs, v @ vsat(eff)> vsat in the highEy region, where vsat(eff) depends on the MOSFET bias (VGS > Vt and VDS > VDS(sat)) [13]. DICE is literally an enhancement of the channelinversionchargedensity(Qch),whichincreasesIDS(sat)asweshowherein.Furthermore, it is signicant in dening Lgch and the MOSFET terminal charges, although CG is not affected much. Without DICE, the classical (2D Gauss lawbased) analysis [19], [20] of the highEy portion of the channel is erroneous, predicting a too short Lgchas we will show. We model DICE via an approximate solution of the 2D Poisson equation in the rectangular UTB/gradual channel (see Fig. 2.2) of a generic undoped DG MOSFET. Previously, such an analysis was done [20] for singlegate devices based on the inversion chargesheet approximation, neglecting bulk inversion. Here we account for two gates and bulk inversion, which is quite signicant in DG MOSFETs with undoped UTBs [23], making no assumption about the inversioncharge distribution in the body. Letting f0(x,y) be the potential in the undoped UTB/gradual channel for VDS = 0 under a stronginversion condition (VGS > Vt), we note from Poissons equation that VDS > 0 denes f (x,y) = f0(x,y) + Df (x,y), where the perturbation Df (x,y) is related to the VDSinduced change in Qch: (2.1) where the integrations are done over the UTB thickness tSi. The rst integral (<0 for an nMOSFET) in (2.1) reects the pinchoff tendency, and, in the classical gradualchannel approximation [19], the second integral is assumed to be negligible. However, for nanoscale DG MOSFETs this assumption can be invalid, and the second integral can be signicant DICE ( D Qch DICE < 0 for an nMOSFET), as we characterize herein. D Q ch y ()e Si x 2 2 Df xy (,) xd0 t Si e Si y 2 2 Df xy (,) xd0 t Si = PAGE 20 20 Numerical. simulations of DG MOSFETs done with Medici [24] reveal that (2.2) inthegradualchannelportionoftheUTB,where h isaspatialconstant;thatis,theVDSinduced perturbationintheelectriceldalongthechannelisnearlylineariny.Thisapproximationobtains because, for high meff, the electron velocity is close to being saturated, and hence not varying muchiny,andsotheaddedchargedensity,associatedwith,isnearlyconstant(for continuous current). Integrating (2.2) twice along Lgch, with boundary conditions Df (x, 0) = 0 (due to strong inversion) and Df (x, Lgch) = VDS(eff), yields h @ 2VDS(eff)/Lgch 2, where VDS(eff)( ~ VDS(sat)) is the effective bias at the end of the gradual channel. Using (2.2) in (2.1) then yields .(2.3) This simple, but physical model shows that DICE manifests as a nearly uniform enhancement of theinversionchargedensityeverywherealongthegradualchannel,andinthehighEyportionas well because of the velocity saturation. Both (2.2) and (2.3) are consistent with the empirical result derived from stronginversion numerical simulations in [21] of a Vt shift linearly proportional to VDS. Extending the basic DG MOSFET analysis in UFDG [25] accordingly, we use (2.1) and (2.3) to express the total inversioncharge density along the channel as ,(2.4) where Qch0 is the VDS = 0 charge density; Coxf= eox/toxf and Coxb= eox/toxb are the frontand backgate oxide capacitances. Prior to saturation, i.e., for VDS < VDS(sat) (=VDS(eff) at the onset of saturation), (2.3) and (2.4) still apply, but with VDS(eff) and Lgch replaced with VDS and Lg (assumed here to be the y 2 2 Df xy (,) h @ eSiD Ey() y D Q ch DICE e Si t Si 2 V DSeff () L gch 2  @ Q ch y () Q ch 0 C + oxf Df 0 y (,) C oxb Df t si y (,) + D Q ch DICE + = PAGE 21 21 channel length as indicated in Fig. 2.2), respectively. For the UFDG DICE upgrade, affecting channelcurrentandterminalcharges,theexistingformalism[25]isrevised,inaccordwith(2.4), bysimplyreplacingQchwith(Qch+ D Qch DICE).(Inthemodelcode,becauseofuncertaintyinLgand tSi, we actually use ( DICE x D Qch DICE), where DICE is a tuning parameter that is typically @ 1.) Note that this revision alters the model characterization of the biasdependent Lgch, which inuences the terminal charges (and device capacitances and transcapacitances) as well as the channel current. The UFDG model for channel current [25] is upgraded for DICE directly, using (2.4) and the altered characterization of Lgch. The impact of DICE on the terminal charge modeling (discussed in Appendix A2) is a bit more involved since D Qch DICE and the new Lgchcharacterization affect the charge partitioning. The basic 2D analysis [19], [25] of the highEy region that denes Lgch is extended to include the DICE charge. Application of the 2D Gauss law yields a secondorder differential equation for the VDSinduced perturbation of potential: ,(2.5) from which we get (2.6) where h conveys the DICE effect; lc = [ eSitSi/(Coxf + Coxb)]1/2 and Esat = 2vsat(eff)/ meff is Ey(Lgch) [25]. Evaluating (2.6) at y = Lg, where Df = VDS, yields following expression of Lgch. .(2.7) y 2 2 d d Df y () Df y () V DSeff () l c 2 h + = Df y () V DSeff () h l c 2 + l c E sat yL gch l c sinh h l c 2 yL gch l c cosh + = V DS V DSeff () h l c 2 + l c E sat L g L gch l c sinh h l c 2 L g L gch l c cosh + = PAGE 22 22 Now, the component of frontgate charge dened by (2.6) is (2.8) FGfB is the gatebody workfunction difference and Wg is the device width. The backgate chargeisdenedsimilarly,andforasymmetricalDGdevice,QGb=QGf.NotethatEy(Lg),given by the derivative of (2.6) evaluated at y = Lg, denes, via Gausss law, a depletionregion component of the drain charge: (2.9) which includes charge linked to the gradual channel as well as the highEy portion. The upgraded charge model reects directly the charge neutrality, (2.10) (with the undopedbody charge QB = 0), where the source (QS) and drain (QD) charges include partitioned components of Qch in (2.4) integrated along the channel. All the terminal charge components, and the channel current, depend on Lgch, implied by (2.6), and on VDS(eff). The latter is obtained from the current analysis of the gradual channel [19], [25], upgraded with DICE, i.e., with Qch including D Qch DICEas in (2.4): .(2.11) UFDG solves (2.11) and the nonlinear expression for Lgch from (2.7) iteratively via NewtonRaphson, and then the current and the terminal charges are evaluated. Figure 2.3 shows Lgch vs. VDS predicted by UFDG for an 18nm DG nMOSFET, with and without the DICE upgrade. Note thatwithoutDICE,LgchissubstantivelyunderpredictedforhighVDS,whichresultsinerroneous current and terminalcharge predictions. Q Gf sat W g C oxf V GfS F GfBf 0 0 y ()Df y () [] ydL gch L g= Q Ddep () Wl c 2 C oxf C oxb + () E sat L g L gch l c cosh h l c L g L gch l c sinh + = Q Gf Q Gb Q S Q D +++0 = V DSeff () Q ch 0 () E sat L gch Q ch 0 () C of C ob + () E sat L gch = PAGE 23 23 The modied 2D analysis of the highEy region, with D Qch DICE, changes all the terminal charges without DICE [20], [25] due to the perturbations in VDS(eff) and Lgch. These changes are only loosely coupled to the gate because VDS(eff) in (2.11) and Lgch given by (2.7) are weakly dependent on VGS. This implies that the gate capacitance (CG = dQG/dVGS) is nearly independent of DICE. Our analysis shows that a portion of draindepletion charge is imaged in the gate via an inner fringe eld, and that the rest is imaged in the channel as the DICE charge ( D Qch DICEWgLg). Hence, the DICE charge in the channel is supported mainly by the drain. Indeed,DICEisverysignicantindeningalltheterminalchargesofnanoscaleDGMOSFETs, and is therefore important in predicting the various device capacitances and transcapacitances, as well as channel current. We demonstrate this signicance in the next section. OuranalysisalsoexplainstheemergingsignicanceofDICEinnanoscaleDGMOSFETs, and why it is negligible in conventional devices. The high mobility in the undoped channel of DGMOSFETs,whileloweringVDS(eff)in(2.3)and(2.11),decreasesLgchasgivenby(2.7).The latter effect is predominant in (2.3), making D Qch DICE in nanoscale DG MOSFETs signicant. Further, the high meff tends to yield signicant velocity overshoot (vsat(eff) > vsat), which renders DICE even more signicant by increasing VDS(sat), and thereby increasing VDS(eff) for a given Lgch. Our analysis also shows that Lgch scales faster than VDS(eff), and for welltempered Lgscaling, Lgch scales faster than Lg, and hence faster than tSiand tox. Thus, D Qch DICE ,as modeled by (2.3), becomes more signicant with scaling. 23 Model Corroboration and Predicted DICE Impacts We include in Fig. 2.1 the UFDGpredicted current for the 60nm pFinFET with our DICE modeling incorporated. Note now the excellent match with the highVDS measured data. To further verify the DICE model, which we have also noted to be consistent with [21], and to corroborate the signicance of DICE in nanoscale DG devices, we simulate a simplied Lg = PAGE 24 24 18nm symmetrical DG nMOSFET with Medici [24], and compare the DICE predicted by it to that predicted by UFDG. Series resistance was kept low to avoid any discrepancy in the effective gate and drain biases due to possible disagreement in currents. And, since the physical modeling in Medici can differ from that in UFDG, additional simplications were made. In particular, we xed the lowEy meff to be 300cm2/Vs (which is comparable to onstate electron mobilities measured in DG FinFETs [10], [11]) in both the simulations, and we turned off the velocityovershootmodels,i.e.,wesetvsat(eff)=107cm/s( @ vsat).Further,weinitiallylettSi=12nm(which is not thin enough for Lg = 18nm to adequately suppress the unwanted SCEs [26]) to avoid anomalously high n(x) for thin tSi that Medici predicts. Later we check devices with thinner tSi. Figure2.4showstheMedicipredictedvariationofinversionelectrondensityacrosstheUTB(tSi=12nm)atthevirtualsource(i.e.,where f isminimumalongy)forlow(50mV)andhigh(1.0V) drain biases, with VGS = 1.0V. Note the strong bulk inversion (which would be enhanced by quantization [27]). The VDSinduced enhancement in the areal density of inversion charge at the virtualsource,i.e.,DICE,reectedbyFig.2.4isabout20%.Figure2.5showstheenhancementin the VGS = 1.0V current due to DICE in the same device as predicted by UFDG. Because of the high meff,thehighVDScurrentisrestrainedbytheballisticlimit[11];thatis,thecurrent(perWg) isnearlyQch(0)timesthethermalinjectionvelocityatthevirtualsource.Hence,theenhancement in the current in Fig. 2.5 virtually reects D Qch DICE, which, indeed, is close to that predicted by MediciinFig.2.4atVDS=1.0V.Tofurthershowthenearequalityofthesesimulations,weshow inFig.2.6thecurrentpredictedbyUFDGforthesamedeviceasinFig.2.5,butwiththeballisticcurrent limit turned off, and compare it with that predicted by MEDICI, which does not account for the ballistic limit. Note that the predicted currents match very well. InFig.2.7weshowUFDGpredictedIDSvs.VDS,atVGS=1.0V,forthesymmetrical18nm DG nMOSFET (tSi = 12nm, toxf = toxb = 1.2nm, midgap gate), but now with the proper series PAGE 25 25 resistance,andmobility[10],[11],velocityovershoot[13],andquantization[27]modeling,with andwithoutDICE.ThecurrentatVDS=1.0Visenhanced24%byDICE(morethanthe @ 20%in Fig. 2.5 mainly because of the velocity overshoot), which is quite substantial because the current isattheballisticlimitandthusdirectlyreects D Qch DICE.Westressthatthecurrentenhancement due to DICE is smaller for devices in which the current is not ballistically limited (like the pFinFET in Fig. 2.1) because it would be undermined some by the increase in Lgch caused by DICE(seeFig.2.3).NotealsoinFig.2.7thatDICEismuchlesssignicantforVDS PAGE 26 26 (2.3),impliedby(2.7)andillustratedinFig.2.3,isthemainreasonforthenitegDSduetoDICE. WenotethatforlowerVGS,gDSisaboutthesameasthat(withDICE)inFig.2.7since D Qch DICEin (2.3) is only weakly dependent on VGS. However, for moderate inversion (e.g., at typical operating points for lowpower RF transistors today), gDS tends to be lower, controlled by channellength modulation, as DIBL tends to preempt DICE. AsdiscussedinSec.2.2,thegatecapacitanceisnearlyindependentofDICE.Thisisshown by the UFDGpredicted CG(VGS) curves in Fig. 2.8 for the same 18nm DG nMOSFET at high andlowVDS,withandwithoutDICE.(TheUFDGpredictedCG(VGS)isingoodaccordwiththe Medicipredicted characteristic at low VDS. However, at high VDS there is some discrepancy, which we believe is due to nonphysical dependences of carrier transport on high Ey used in Medici for weak inversion.) So, since DICE gives enhanced current without increased gate capacitance, should it yield faster CMOS? The answer is yes, as shown by the UFDG/Spice3predictedCMOSinverterchaindelayrevealedinFig.2.9.With18nmDGMOSFETs,likethatin Figs. 2.7 and 2.8 (with the proper hole mobility [10] assumed for the pMOSFET), the average propagation delay per stage is reduced by about 18% by DICE (less than the 24% Ionenhancement in Fig. 2.7 because of the VDS dependence of the DICE benet, and because of secondorder increases in drain capacitance and gatedrain transcapacitance due to DICE). 24 Summary Draininduced charge enhancement, the stronginversion counterpart to DIBL, has been modeled analytically, with numerical support, and shown to be a signicant shortchannel effect in nanoscale DG MOSFETs. Further, it becomes more signicant with welltempered scaling. DICE substantially increases the inversioncharge density, without affecting the gate capacitance signicantly since the added charge is supported mainly by the drain. It therefore is benecial to digital CMOS speed, as we demonstrated via UFDG/Spice3 simulations. However, it increases PAGE 27 27 drain conductance, and hence could be problematic in analog applications, although it does subside in moderate inversion where todays lowpower RF transistors operate. Our analysis further demonstrates that physical compact models for nanoscale DG MOSFETs should account for DICE to ensure valid terminal charge (and capacitance and transcapacitance) as well as current modeling. PAGE 28 28 Table 21. UFDGpredicted DICE and DIBL in an Lg = 18nm nMOSFET with varying UTB thickness, with and without a 2nm gatesource/drain underlap. tSi (nm)DICE (%)DIBL (mV/V) DIBL (mV/V) w/ underlap 1224260150 1019180100 81511060 PAGE 29 29.Figure 21.Results of calibratingUFDG to an undoped Lg = 60nm DG pFinFET (fin aspect ratio hSi/tSi = 100nm/17nm) [22], with and without DICE. 1.21.00.80.60.40.2VGS [V] 0.00 0.02 0.04 0.06 0.08IDS [mA] Measured Data UFDG w/o DICE UFDG w/ DICE 0.0VDS = 1.2V 50mV0.09 0.07 0.05 0.03 0.01 PAGE 30 30.Figure 22. Illustration of a DG MOSFET biased in the saturation region, showing the body/channel divided into a gradual channel (Lgch) and a higheld (Ey) portion (Lg Lgch). The effective channel length is assumed to equal the gate length here. S Gf Gb x LgchtoxftoxbtsiLgDy PAGE 31 31.Figure23.UFDGpredictedgradualchannellength,relativetoLg=18nm,versus drain voltage for a DG nMOSFET, with and without DICE; tSi = 12nm, toxf = toxb = 1.2nm, midgap gate. 0.00.51.01.52.0VDS [V] 0.0 0.2 0.4 0.6 0.8 1.0Lgch / Lg UFDG w/o DICE UFDG w/ DICE VGS = 1.0V PAGE 32 32.Figure 24. Medicipredicted inversionelectron density across the UTB at the virtualsourceofasimple18nmDGnMOSFETforlowandhighdrain voltages; tSi = 12nm, toxf = toxb = 1.2nm, midgap gate. The high VDSincreases the integrated electron density (in the bulk) by about 20%. 0.02.04.06.08.010.012.0x [nm] 101810191020n [cm3] 50mV VDS = 1.0V VGS = 1.0V PAGE 33 33.Figure 25. UFDGpredicted drain current versus voltage characteristics, with and without DICE, of an 18nm DG nMOSFET simplied to correspond to the Medici simulation of Fig. 2.4. At VDS = 1.0V, DICE increases the nearballistic current by about 20%, in accord with the inversioncharge enhancement indicated in Fig. 2.4. 0.00.20.40.60.81.0VDS [V] 0.0 0.5 1.0 1.5 2.0IDS [mA/ m m] UFDG w/o DICE UFDG w/ DICE VGS = 1.0V PAGE 34 34 0.00.20.40.60.81.0VDS [V] 0.0 1.0 2.0 3.0IDS [mA/ m m] MEDICI UFDG VGS = 1.0V Figure 26. UFDGand MEDICIpredicted drain current versus voltage characteristics of the 18nm DG nMOSFET of Figs. 2.4 and 2.5. The ballisticcurrentlimitwasturnedoffinUFDGtocorrespondtoMEDICI, which does not account for it. PAGE 35 35.Figure 27. UFDGpredicted drain current versus voltage characteristics, with and without DICE, for the 18nm DG nMOSFET of Fig. 2.5, but with the properseriesresistance,mobility,andvelocityovershootmodeling;tSi= 12nm, toxf = toxb = 1.2nm, midgap gate. At VDS = 1.0V, with VGS = 1.0V,DICEincreasesthenearballisticIDSby24%.Thepredicteddrain conductance, which is increased by DICE, is also shown. 0.00.20.40.60.81.01.2VDS [V] 0.0 0.5 1.0 1.5 2.0IDS [mA/ m m] UFDG w/ DICE UFDG w/o DICE 0.00.20.40.60.81.01.2 1.0 0.0 1.0 2.0 3.0 4.0 5.0gDS [mS/ m m] VGS = 1.0V PAGE 36 36.Figure 28.UFDGpredicted gate capacitance versus voltage characteristics of the 18nm DG nMOSFET of Fig. 2.7 at low and high drain voltages, with and without DICE. Note that not accounting for DICE results in a nonphysical dip (dCG/dVGS< 0) in moderate inversion. DICE effectively removesthisdipbyincreasingthestronginversiongatecharge(because of longer Lgch) without affecting CG (=dQG/dVGS) significantly. 0.20.00.20.40.60.81.01.21.41.61.82.0VGS [V] 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10CG [fF/ m m] UFDG w/ DICE UFDG w/o DICE 50mV VDS = 1.0V PAGE 37 37.Figure 29. UFDG/Spice3predicted output voltage transient of a twostage 18nm DGCMOSinverterchain,withtheinputvoltagepulsingshowntoreveal the (pulldown plus pullup) propagation delay; VDD = 1.0V. The DG MOSFETs were designed like that in Figs. 2.7 and 2.8; the output was loadedwithacapacitorwithvaluecomparabletothegatecapacitanceof the MOSFETs. 0.010.020.030.040.050.060.0 0.5 0.0 0.5 1.0 1.5 w/o DICE w/ DICE t [ps] VinVout[V] PAGE 38 38 CHAPTER 3 THRESHOLD VOLTAGE ADJUSTMENT IN NANOSCALE DG FINFETS VIA LIMITED SOURCE/DRAIN DOPANTS IN THE CHANNEL 31 Introduction AsmentionedinChapter1,fornanoscaleFinFETs,thefinbody/channelmustbeultrathin, and hence must be left undoped to avoid randomdoping effects on Vt. Adjusting Vt for different CMOS applications, i.e., LP and HP, is thus a design problem; varying Vt via nearmidgapgate workfunctionengineeringhasnotbeenshowntobeaviableoption.Inthischapter,weproposea design approach in which S/D dopants are allowed to diffuse into the FinFET channel for Vtadjustment in HP versus LP applications. We demonstrate and verify, via simulations and measurement results, that such engineering of the lateral S/D doping profile [NSD(y)] can be controlled to reliably lower Vt in strong inversion (for higher Ion) while not affecting it significantly in weak inversion (for lower Ioff with negligible processinduced variations). We furthershow,viarigorousrandomdopinganalyses,thattheeffectsofrandomdopantfluctuations (RDF) are acceptable in such FinFET design. We have previously put forth the idea of pragmatic FinFETCMOS design [2], which uses only one, nearmidgap gate metal for the nMOS and pMOS devices and retains the (relatively thick) SiON gate dielectric. In this context, we showed that incorporating a GS/D underlap can be used to effect an IoffIon tradeoff via a Leff that decreases with increasing VGS [26]. We demonstrated this idea for nanoscaleFinFET SRAM design [17]. The new design approach proposedhereinaugmentstheutilityofS/DengineeringforGS/Dunderlap[26],enablingwider Vt adjustment for different CMOS applications, and, unlike gate workfunction engineering, allowing independent adjustment of Vt for Ioff and Ion. PAGE 39 39 32 S/D DopingDependent VtTheviabilityofourproposeddesignforVtadjustmentstemsfromthedependenceofVton the distribution of S/D dopants in the UTB/channel, which we rst analyze. Possible doping proles, assumed to be gaussian {NSD(y) = N0exp[(y+Lext)2/ sL 2] where N0 is the density at the S/D end of the S/D extension and sL is the lateral straggle}, are illustrated in Fig. 3.1. For weak inversion,thecurrentisdeterminedbydiffusionofcarriersinaportionofthechanneloverwhich the electric potential is relatively invariant in y, and the threshold voltage (Vtw) is dened at the point of minimum potential [19] within this region. Because of negligible longitudinal (in y) electric eld in this region, Vtw can be expressed based on a 1D (in x) analysis. For an undoped (negligible acceptor dopants) nchannel DG FinFET with a midgap gate, ,(3.1) where fcisthecharacteristicsurfacepotentialatthreshold( @ 0.4V)[3]and D Vt DIBLrepresentsthe reductioninVtwduetoDIBL[19];tSiisthesiliconnthicknessandCox= eox/tox.TheNSDterm in(3.1)denesthereductioninVtwduetoS/Ddonordepletioncharge(assumedtobeuniformin x) in the channel. This term is dened at y = Lg/2 because, in nanoscale FinFETs, the noted diffusioncurrent region is short and located near the center of the channel [19]. Note then that NSD(Lg/2) is most critical in dening Vtw, and Ioff. For nanoscale FinFETs, we note that the depletionchargetermwilltypicallybenegligibleunlessNSD(Lg/2)>~1018cm3[3].Wealsonote thatNSDawayfromthecenterofthechannelcanalsoaffectIoffbyperturbingthesolutionofthe 2DPoissonequationintheUTB,whichdenes D Vt DIBL[19].However,thisperturbation,which increases D Vt DIBL due to more encroachment of the S/D electric eld, is typically small when NSD(Lg/2) < 1018cm3. We have neglected the Vtw increase due to quantization; this increase is small in symmetrical undoped DG MOSFETs for tSi > 4nm [28]. V tw f @ c qN SD L g 2 () t Si 2 C ox D V t DIBL PAGE 40 40 Forstronginversion,thecurrentisdriftandisdeterminedbytheaverageconductivityofthe (gradual) channel. The (aerial) inversioncharge density (Qch is magnitude) in the channel, with NSD(y), can be expressed as [19] (3.2) where Qch0 = 2Cox(VGS fs) is the inversioncharge density at the (virtual) source for NSD = 0, with fs being the surface potential ( >fc due to nite inversionlayer capacitance) there, Df is the VDSinducedperturbationinthepotentialalongthechannel,and D Qch DICEistheenhancementin theinversionchargedensityduetoDICE.NotethatQchincreaseslinearlywithNSD.Thecurrent is dened by integrating (3.2) along the gradual channel (Lch) [19], and it is increased by NSDaccordingly. Based on the integration, Qch0 is effectively increased to (Qch0+ q NSDtSi), where (3.3) istheaveragedensityofS/Ddopantsinthegradualchannel.The(extrapolated)thresholdvoltage (Vts) can hence be dened by ,(3.4) or ,(3.5) where D Vt DICE represents the reduction in Vts due to DICE. Note that Lch depends on both VDSand VGS, and hence so do NSD and Vts. Note how Vtw in (3.1) [where Ioff exp(qVtw/kT)] and Vts in (3.5) [where Ion (VGS Vts)] differ. For weak inversion, D Vt DIBL is signicant, and Vtw is lowered by the depletionQ ch y () Q ch 0 2 C ox Df y () qN SD y () t Si D Q ch DICE ++ = N SD 1 L ch N SD y () y d 0 L ch= Q ch 0 qN SD t Si +2 C ox V GS V ts () @ V ts f @ s qN SD t Si 2 C ox  D V t DICE PAGE 41 41 charge term near the center of the channel where the carrier transport is predominantly diffusion [19].Thus,NSD(y~Lg/2)mustbedesignedtobelessthan~1018cm3toavoidexcessiverandomdoping effects on Ioff. For strong inversion, D Vt DIBL is small because of the large transverse electric eld [2], however D Vt DICE could be signicant, and Vts is lowered by the integrated depletion charge. Thus, if NSD is greater than ~1018cm3, and NSD(y ~ Lg/2) is negligible as noted, then Ion can be enhanced by a lowered Vts, and Ioff and Vtw will not be affected signicantly, provided the noted D Vt DIBL(NSD) increase is limited (which may require an IonIoffdesign tradeoff). The NSD(y) labeled HP in Fig. 3.1 is such a doping prole. The NSD(y) labeled LP in Fig. 3.1 shows negligible NSD everywhere in the channel, but yields a signicantly benecial GS/D underlap. The underlap yields Leff > Lg in weak inversion, and thereby reduces the SCEs [26] and parasitic capacitance as well [29]. The essence of our S/D engineeringbased design, including the extension for Vt adjustment, is thereby dened. We show in Fig. 3.2 measuredIDSVGScharacteristicsoftwoLg=70nmDGFinFETshavingdifferentNSD(y).From our UFDG [16]calibration results, we nd that the doping proles in devices 2J and 1G are like HP and LP proles, respectively, albeit nonoptimal since these devices were fabricated [22] withoutemphasisonS/Dengineering.ThedifferenceofthestronginversionVtsbetweenthetwo devices shown in Fig. 3.2(a), which is due to different NSD in the channels, is signicant. (Note that Vts can decrease with increasing VGSdue to the previously noted bias dependence of NSD in (3.3).) The Vtwvariation between the two devices in Fig. 3.2(b) ( @ 200mV) is due largely ( @ 100mV as inferred from the data) to different SCEs as dened by Leff. Note that the corresponding values of Ion and Ioff, interpreted based on our physical insights from (3.1)(3.5), experimentallyconrmtheefcacyoftheproposedVtdesignapproachforrelativelylong(70nm) DG FinFETs. For shorter devices, the approach should still be valid as long as Lg is not short enough (<20nm as implied by UFDG projections [11]) such that Ion is limited by ballistic PAGE 42 42 transport. For such short devices, Ioff will still be dened by Vtw in (3.1), and Ion will be dened by Qch(0) in (3.2) which will increase with NSD(0). Therefore, our proposed design approach is generally useful for future LP/HP applications of nanoscale DG FinFETs. (We would like to thank Shishir Agrawal, a Ph.D. student at the University Florida, for calibrating measured characteristics with UFDG.) 33 Demonstration and Verication of Design Approach WefurtherchecktheproposedS/DengineeringforLP(lowIoff)andHP(highIon)FinFETCMOS applications using our process/physicsbased compact model for DG MOSFETs, UFDG (with physical modeling of carrier mobility, velocity overshoot, quasiballistic transport, and quantization)[16],linked[17]to2DnumericaldevicesimulationsdonewithMedici[24].ForLg=18nm(HP45nmnode[1]),withamidgapgateandtox=1.0nm,weassumeLext=12nm,andan undoped UTB with tSi = 10nm for adequate SCE control. We dene NSD(y) with different straggle, as in Fig. 3.1, for an LP ( sL = 5.5nm, which yields weakinversion Leff = 24nm and negligible NSD in the channel) and an HP ( sL = 8.5nm, which yields Leff = 18nm, NSD = 4x1018cm3,andNSD(y~Lg/2)=5x1017cm3)application.Weassumeanominal(doable[22])S/ DseriesresistanceRSD=100 W m m,and,fortheLPdesign,increaseitby D RSD=25 W m mdueto the underlap [17]. Fig. 3.3(a) shows UFDGpredicted subthreshold IDSVGS characteristics of the two FinFETs, which reect a Vtw difference of @ 180mV (at 100nA/ m m/Lg). We stress that the lower VtwoftheHPdeviceisduemainlytotheshorterLeff(=Lg)andlargerSCEs.(A~20mVreduction in the HP Vtwcaused by NSD in the channel was ignored.) So, the longer Leff for the LP device yields the (1/300) x decrease in Ioff, relative to the HP device, evident in Fig. 3.3(a). (For the HP design,wedidnotaccountforthereductioninsubthresholdmobility[~ x (1/2.5)]duetoCoulomb scattering by the S/D dopants [10]; Ioff would thus be lowered accordingly, tending to offset the PAGE 43 43 small increase due to the noted 20mVlower Vtw.) UFDGpredicted stronginversion IDSVGScharacteristics(pernheight),atVDS=VDD=1.0V,oftheLPandHPDGnFinFETsareplotted inFig.3.3(b).NotethatVtsoftheHPdeviceisconsiderablylowerthanthatoftheLPdevice[by @ 100mV, as dened by NSD = 4x1018cm3 in (3.5)]. The HP Ion in Fig. 3.3(b) is 29% higher than that of the LP device; about 20% of this increase is due to the lower Vts, and rest is due to the lowerRSD.(FortheHPdevice,weevaluated NSDatlowVDS,butwenotethatitsvalueatVDS= 1.0V could be lower due to reduction in Lch with increasing VDS. Due to uncertainty in Lch at VDS = 1.0V, NSD is difcult to evaluate accurately. However, we estimate that the worstcase enhancement in Ion due to the Vts lowering is about 15%.) To solidify the NSD(y)based design approach,wealsoshowinFig.3.3theUFDGpredictedIDSVGScharacteristicsoftheLPdevice with Lg increased to 28nm, as projected (for LSTP) in the SIA roadmap [1] for the 45nm node. The longer Lg yields an acceptable Ioff@ 10pA/ m m, more than fourorders of magnitude lower than that of the HP device. UFDG/Spice3predicted RO delays for this LP and the HP design are 3.6psand1.9ps,respectively,atVDD=1.0V.ThedelayfortheHPdeviceatthesamebiaswithout Vts reduction is 2.4ps; the limited S/D doping in the channel reduces the HP delay by more than 20%. 34 Sensitivity and RDF Analyses ToabsolutelyconrmtheviabilityofourproposedVtadjustmentdesign,wemustconsider sensitivitiestoprocessvariationsandRDFeffects.Fortheformer,wedidaMedici/UFDGbased analysis, results of which are shown in Table 3.1. We nd from the simulations that letting sLvary by +/18% in both designs of Figs. 3.1 and 3.3 does not cause prohibitive variations in Ioff: 1.5 x /(1/1.3) x for LP and 80 x /(1/20) x for HP. And, sensitivity to variation in the local number of dopants is acceptable as well. The HP prole in Fig. 3.1 shows NSD(Lg/2) =5x1017cm3, which impliesonly~1dopantnearthecenterofthechannel.Thisnumbercouldrandomlyincreaseto3, PAGE 44 44 and the lowered Vtw, given by (3.1) with the implied NSD(y ~ Lg/2), would not prohibitively increaseIoff(<100 x ).(Theseweakinversionresultsarevalid,butwehavefoundthatforundoped UTB devices with GS/D underlap, Medicipredicted stronginversion currents are not reliable due to inadequate UTBtransport modeling.) In Table 3.1 we also show the UFDGpredicted variationsinIon.ThevariationsinIonaremuchlowerthanthoseinIoffbecauseIonvarieslinearly with NSD as implied by (3.2), whereas Ioff is exponentially dependent on NSD. Also, Ion depends on NSD and not directly on NSD, and so the exact position of dopants in the channel is not important for Ion. ThemainconcernabouttheRDFsistheeffectonVtw[31]andIoff,asimpliedbyTable3.1. Therefore, we did a more detailed Medicibased study of the variations in Ioff due to RDFs. As illustrated in Fig. 3.4, we divided the S/Dextension and the channel/UTB regions via grids with equal spacings, and assumed for this analysis that the height of the n (width of the FinFET) is equal to the grid spacing (2nm as in [31]). For each lattice site in every cube thus formed, the probability of having a S/D dopant at that location is calculated based on the NSD(y)dened dopingdensityatthatlocation,andthenasiliconatomordopantatomisrandomlyplacedatthat location, following the method described in [32]. The number of dopants randomly placed in the cube,dividedbythevolumeofthecube,denesthedopingdensityassignedtothecorresponding region in the Medici domain. Once the doping density is specied every where in the S/Dextension and channel regions, Ioff and Vtw are extracted from the Medicipredicted currentvoltage characteristics. The process is repeated a sufciently large number of times, and the variations are noted. Because of the large number of simulations used, the RDF along the actual height of the FinFET is implicitly accounted for [31], thereby enabling use of the noted (unrealistically) small n height and 2D Medici simulations for computational efciency. (We wouldliketothankAskhanBehnam,aPh.D.studentattheUniversityofFlorida,forhelpingwith PAGE 45 45 the above simulations.) Table 3.2 shows the predicted standard deviation of Vtw [ s( Vtw)], and device yield for 18nmLPandHPDGFinFETsbasedonacceptablevariationsinIoff(<100 x) .FortheHPdevice, the 95% yield indicates the viability of our design approach. The yield increases, and s( Vtw) decreases, as we limit the S/D dopants in the channel by decreasing sL. Insignicantly small s( Vtw) in the LP device implies negligible variations in Ioff, which is crucial for LP applications. NotethatsinceweconsideredtherandomvariationsofdopantsintheS/Dextensionregions,our simulation results in Table 3.2 account for the effect of variation in Leff as well. Based on our resultsinTables3.1and3.2then,weconcludethatRDFeffectsarevirtuallynonexistentintheLP design, and are adequately controlled in HP design when NSD(y~Lg/2) is limited as noted. 35 Summary An extended approach to nanoscale DG FinFET design for LP and HP nanoscaleCMOS applications via S/D engineering [i.e., control of NSD(y) for GS/D underlap and Vt adjustment] wasproposed,anddemonstratedtobeviablebydevicemeasurementsandsimulations,including sensitivity and RDFeffects studies. The approach exploits the idea of allowing limited S/D dopants properly distributed in the channel for HPVt design. We demonstrated the design approachatthe45nmnode.ScalingLgto<10nm,asprojectedattheendoftheSIAroadmap[1], will require the lateral straggle of NSD(y) to be reduced by about a factor of two, which appears feasible with acceptable sensitivities via new processing such as laser annealing. However, additionalanalysesincludingquantizationeffects,mobilitydegradation,andballistictransportare called for. Our work extends the utility of S/D engineering in the design of nanoscale FinFETs, now for Vt adjustment as well as GS/D underlap. But, additional work on S/D processing for control of NSD(y) in the thinn extensions and channel is needed to effect this utility. PAGE 46 46 Table31.MedicipredictedsensitivityofIofftovariationsin sL(+/ 18% of the nominal sL0 noted) of NSD(y) in the Lg = 18nm LP and HP DG FinFETs. sL+18%18% LP ( sL0=5.5nm) 1.5 x (1/1.3) x HP ( sL0=8.5nm) 80 x (1/20) x Table 32. Medicipredicted standard deviation of Vtwand associated Ioffbased yield due to the RDF of NSD(x,y) in the Lg = 18nm LP and HP DG FinFETs. Application s (Vtw)Yield HP ( sL=8.5nm)100mV95% LP ( sL=5.5nm)18mV100% PAGE 47 47 Figure 31.S/Dextension lateral doping proles in an undoped DG FinFET, showing variable encroachment into the channel. The HP prole exemplies one which lowersVtsviaS/Ddopantsinthechannel,butdoesnotaffectVtw;theLPprole does not affect Vtw nor Vts, but does yield an effective GS/D underlap. The FinFET structure corresponding to the doping proles is indicated. 12.06.006.012.018.024.030.0y [nm] 10131014101510161017101810191020 HP LP Lg LextLextNSD [cm3] LextLextx y LgtSiS D G G PAGE 48 48 Figure 32.Measured currentvoltage characteristics of two Lg = 70nm undoped DG nFinFETs [30], which have different NSD(y) due to variations in the S/D processing. The D Vts and D Vtw indicated reect LP (~device 1G) and HP (~device 2J) features of the respective devices, governed by NSD(y) as dened by (3.1)(3.5). A) Stronginversion characteristics. Note the strong D Vts(VGS) dependence, which indicates overly excessive densities of S/D dopants in the channel of device 2J ( i.e., GS/D overla p) B ) Subthreshold characteristics. 0.00.10.20.30.40.50.60.70.80.91.01.1 0.00 0.05 0.10 0.15 0.20 1G 2J 1.2VGS [V] VDS = 1.2V D VtsIDS [mA] 0.00.10.20.30.40.50.60.70.80.91.01.1 10111010109108107106105104103 1G 2J VGS [V] VDS = 1.2V1.2 D VtwIDS [A]A B PAGE 49 49 Figure33.UFDGpredictedcurrentvoltagecharacteristics(pernheight)ofthe18nmLP and HP DG FinFETs, and of the LP device with longer Lg = 28nm as projected in the SIA roadmap [37]. A) Subthreshold Characteristics. B) Stronginversion Characteristics. The stronginversion characteristic of the HP device is approximate; the gate work function was decreased to account for the lowered Vts due to S/D dopants in the channel. 0.00.10.20.30.40.5VGS [V] 101210111010109108107106105104103IDS [A/ m m] HP LP Lg = 28nm VDS = 1.0V 0.500.600.700.800.90 1.00VGS [V] 0.0 0.5 1.0 1.5 2.0IDS [mA/ m m] HP LP Lg = 28nm VDS = 1.0VA B PAGE 50 50 Figure 34. The DG FinFET structure showing how the S/Dextension and channel regions were partitioned (into 2nm cubes) to account for the RDF of NSD(x,y) in the (2D) Medici domain. G G D S LextLextLgtSi PAGE 51 51 CHAPTER 4 PHYSICAL INSIGHTS ON ANALOG/RF PERFORMANCE OF DOUBLEGATE FINFETS, WITH COMPARISION TO BULKSILICON MOSFETS 41 Introduction DG MOSFETs have been shown to be much better suited than bulkSi MOSFETs for nanoscaledigitalapplications[33],primarilybecauseoftheirinherentlybetterimmunitytoSCEs and higher meff. The high meff [10], due mainly to low transverse electric eld in the undoped ultrathin nbody (UTB), tends to produce signicant saturationregion effects that are not observed in conventional devices, for example, carriervelocity overshoot [13], quasiballistic transport [10], and draininduced charge enhancement (DICE) [12] which can affect analog performance. In this chapter, we use our physical understanding of nanoscale FinFETs, and UFDG [14], [15], [16], supplemented with published numericalsimulation and experimental data, to compare the analog/RF performance of undoped DG FinFETs with that of conventional bulkSi MOSFETs, for both lowpower and highfrequency RF applications. Further, we give insights on the optimal design of FinFETs for RF applications, and discuss the effects of scaling on analog FOMs of FinFETs. In order to make a fair comparison of the two devices, we consider FinFETs and planar bulkSi MOSFETs that occupy nearly equal layout areas. For FinFETs, we assume Lg is about P/ 4,wherePisthepitchofthetechnology.ForpropercontrolofSCEsinDGFinFETs,tSimustbe about Lg/2 ~ P/8. Technologically, an aspect ratio of n height (hSi) to tSi of 4 is reliably achievable. Therefore, hSi ~ P/2. So, for comparison to bulkSi MOSFETs with gate width (W) equal to P, we assume onen (per pitch) FinFETs with effective width 2hSi = W, which is consistent with the noted structure for SCE control. PAGE 52 52 42 Device Characteristics For qualitative insight, we begin by writing simple yet physical expressions for IDS, and deriving expressions for gm and fT. Based on these expressions we check and compare the RF performancesoftheDGFinFETsandbulkSiMOSFETs.Inordertosimplifythediscussion,we derive the expressions assuming low VDS, and later we discuss their utility at high VDS. We also assume strong inversion, or moderate inversion near the onset of strong inversion. Forbothdevices,wecanwriteagenericexpressionforIDSintermsofaneffectivewidthof the device (Weff), equal to W for bulkSi MOSFETs and 2hSi for FinFETs, as (4.1) where u represents the average carrier velocity in the channel and Qch here is the (aerial) inversioncharge density for bulkSi MOSFETs, or half of it for (symmetrical) DG FinFETs. From the basic MOS equation [19], Qch (magnitude) can be expressed as ,(4.2) where FMS is the gatebody workfunction difference. Note, for low VDS, Qch [ @ QG(int), where QG(int) is the magnitude of the intrinsic charge density on the gate) will be nearly constant along the channel. From (4.1), we derive (4.3) where the intrinsic (per unit area, excluding parasitics) gate capacitance CG(int)is dQG(int)/dVGS, which from (4.2) can be expressed as ,(4.4) intermsoftheinversionlayercapacitanceCinv=dQch/d fs.[Thebodycapacitancepresentinbulk devices,whichisabsentinFinFETsduetothetwocoupledgates,isneglectedin(4.2)and(4.4)]. I DS W eff Q ch u = Q ch C ox V GS F MS f s () @ g m W eff C Gint () u = 1 C Gint () 1 C ox 1 C inv + = PAGE 53 53 If Cp is the parasitic gate capacitance per unit width, then the total gate capacitance is CG = CG(int)(WeffLg) + CpWeff, and hence, with (4.3), fT can be expressed as .(4.5) NotethatathighVDS,Qchwillbeafunctionofpositioninthechannel,andwillbedifferent from Qch in (4.2). Typically, this VDSinduced perturbation is only loosely coupled to the gate. Therefore, (4.3) and (4.5) capture the predominant dependences, even at high VDS, of the two dened analog FOMs, and are hence useful for general comparison of DG FinFETs and bulksiliconMOSFETs.Notein(4.5)howscalingLgtendstoincreasefT,asmentionedearlier,butalso note the dependences on u CG(int) [or on Cinv in (4.4)], and Cp, which underlie performance differences between DG FinFETs and bulkSi MOSFETs. A. LowPower RF Applications CMOS devices for lowpower RF applications are generally biased in the moderateinversion region [34], where both drift and diffusion current components are important. In FinFETs,becauseofthehigh meff,signicantvelocityovershoot[13]istypicallyobserved,which leadstosubstantiallyhighercarrierdriftvelocity.Also,becauseofhigh meff,carriersdiffusefaster inFinFETs.Therefore,forlowpowerRFapplications, u issignicantlyhigherforFinFETsthan for bulkSi MOSFETs. The inversioncharge centroid in FinFETs is farther away from the surface than in bulkSi MOSFETsbecauseofbulkinversion[23]intheundopedUTB,especiallyformoderateinversion. This leads to lower Cinv in FinFETs, and hence lower CG(int) in (4.4). The parasitic (inner and outer)fringecapacitance(Cf)andtheoverlapcapacitance(Cov)willbeaboutthesameinthetwo devicesforequalWeff(iftheFinFETdoesnothaveGS/Dunderlap[26],[29]),thusrenderingCpinbothdevicescomparable.Hence,CGinFinFETs(evenwithoutunderlap)willbelowerthanin f T u 2 p L g C + p C Gint () () = PAGE 54 54 bulkSi MOSFETs. However, for FinFETs with GS/D underlap [26], [29] (which cannot be incorporated into bulkSi MOSFETs with doped channels), there is no Cov and Cf is reduced, implying an added advantage as we discuss later. Since the inversionlayer thickness in FinFETs, with the noted bulk inversion [23], is ~tox, and (electron) meff is ~3xhigher than in bulkSi MOSFETs [10], (4.3) suggests that the FinFET gm is comparable to that of the bulkSi MOSFET. Signicant velocity overshoot [13] in FinFETs willtendtobenetgm,however.ThelowerCG(int),withcomparablegm,implieshigherfTin(4.5) for FinFETs than for bulkSi MOSFETs. Further, a big advantage of FinFETs over bulkSi MOSFETs is their much lower gDS. In bulkSi MOSFETs, gDS is much higher than in undoped FinFETs[35]mainlybecauseofthepresenceofhalo(pocket)implantsinthebulkdevices,which introduce VDSdependent barriers at the source and the drain [36]. For bias in the moderateinversion region, we note that draininduced barrier lowering (DIBL), a SCE, is important in dening gDS. Therefore, even in the absence of halo implants, the gDS in bulkSi MOSFETs will tendtobehigherthanthatinFinFETsbecauseofbetterSCEcontrolinFinFETs.ThelowergDS, with comparable gm, makes Avo in FinFETs larger than in bulkSi MOSFETs. Thequalitativecomparisonsmadeabove,whichsuggestFinFETsuperiorityforlowpower RF applications, are generally consistent with the experimental results in [35], although comparable fTwas measured for the FinFETs and bulkSi MOSFETs examined. This inconsistency could very well be due to higher Cov in the FinFETs. Since they were fabricated with undoped UTBs, but without GS/D underlap, excessive overlap is quite likely. We show now that the FinFET superiority can be enhanced by incorporating GS/D underlapinthedesign,whichisnotafeasibleoptionforbulkSiMOSFETs[26].Asnotedbefore, DIBL is important in dening gDS in the moderateinversion region. Therefore, an underlap, which has been shown to be effective in controlling SCEs [26], will improve the analog PAGE 55 55 performance.Figure4.1showstheUFDGpredictedimpactofanunderlapongDSatVGS=0.4V for a 28nm DG FinFET, with Vt = 0.16V at low VDS. For this device, UFDG predicts that the underlap reduces DIBL from 120mV/V to 50mV/V, which translates to 75% reduction in gDS at VDS = 1.2V. A GS/D underlap can also minimize Cp signicantly, and thus increase fT in (4.5). The underlap eliminates Cov, and reduces both the inner and outer Cf components [29]. Thus, even withthedoublingofCfintheDGdevice,Cpislower.Theunderlapwillincreaseparasiticsource/ drain resistance (RS/D), but that will not be overly important in the moderateinversion region because of the low current levels. Therefore, underlap increases fT by reducing CG without signicantly affecting gm. Indeed, for the FinFET in Fig. 4.1, UFDG predicts, as shown in Fig. 4.2,thattheunderlapreducesCGby28%atVGS=0.4V,whileitpredictsnegligibledeterioration in gm. The net result is a 40% enhancement in fT. More elaborate discussion on the effect of underlap on fTis given in [34]. As mentioned before, experimental data presented in [35] show comparable values of fT for suboptimally designed FinFETs (i.e., without underlap) and bulkSi MOSFETs. However, our results and those in [34] clearly show that a well designed GS/D underlap in undoped DG FinFETs can lead to much higher fT than in bulkSi MOSFETs. B. HighFrequency RF Applications The relative performances for highfrequency RF applications can be assessed by comparing the FinFETs and bulkSi MOSFETs biased where gm is maximum. This bias point is generally in the stronginversion region, where, unlike in moderate inversion, RS/D is signicant. For example, it tends to reduce gm because of reduced effective gate bias, and hence lower fT. WithsimilarS/Ddopingdensity,FinFETstendtohavehigherRS/DthanbulkSiMOSFETs,even without GS/D underlap which tends to increase it. In general, the resistance of a S/D extension region can be expressed as PAGE 56 56 (4.6) where rextis the resistivity of the extension region, and Aext is its crosssectional area. For FinFETs, Aext = hSitSi (unless the n is ared), and is typically less than Aext = Wxj of bulkSi MOSFETs,wherexjisthejunctiondepth.FortSi@ xj,whichisreasonable,W=2hSiimpliesthat Rext in FinFETs is about a factoroftwo higher than that in bulkSi MOSFETs. Indeed, the experimental data presented in [35] show lower fT in the FinFETs than in bulkSi MOSFETs, whichwasattributedtohigherRS/D.However,theFinFETRS/Dreportedin[35](~1000 W m m)is abnormally high; in fact, RS/D@ 100 W m m has been recently achieved [22]. As noted previously, FinFETs tend to have higher u and lower CG(int) than bulkSi MOSFETs,whichimplyhigherfT.However,forhighfrequencyRFapplicationswiththedevices biasedinstronginversion,thehigherRS/DoftheFinFETswillunderminefTsome.Weassessthis effectofRS/DusingUFDGtopredicthowmuchfTwouldbeincreasedifRS/Dwerereducedfrom anominalvalueof100 W m mtohalfofthisvalue.Forthe28nmDGFinFETofFigs.4.1and4.2, UFDG predicts that fT increases by 14%. We can infer then that the inherently higher RS/D in nanoscale FinFETs will cause only about a 15% reduction in fT relative to that in bulkSi MOSFETs (which is much lower than that reported in [35]). And, the reduction will be even less forlongerLg.ThissmalleffectofRS/DonfTisexplainedbythefactthatwhileitdecreasesgmby lowering the effective gate bias, it also decreases CG. The effect of higher FinFET RS/D on Avo is also not overly substantive. For the 28nm DG FinFET of Figs. 4.1 and 4.2, UFDG predicts that Avo increases by about 20% when RS/D is reduced from its nominal value of 100 W m m to half of this value. As noted previously, based on [36], gDS in FinFETs tends to be lower than in bulkSi MOSFETs, by as much as an order of magnitude[35].Therefore,evenwithtwiceasmuchRS/D,AvoinFinFETsshouldbesubstantially R ext r ext L ext A ext = PAGE 57 57 higher than in bulkSi MOSFETs. Unlike in the moderateinversion region, GS/D underlap is ineffective in reducing Cp in the stronginversion region [29]. Also, GS/D underlap is insignicant in dening gDS because DIBL tends to subside in strong inversion. However, we noted that GS/D underlap will tend to reduce CG by eliminating Cov. Therefore, it could be benecial for highfrequency RF applications, even though it would increase RS/D. As shown in Table 4.1, the 28nm DG FinFET with a GS/D overlap of 2.8nm (10% of Lg) has a lower UFDGpredicted fT than that of the FinFET with a GS/D underlap optimized for lowpower RF applications in accord with [34]. This GS/D underlap introduces an extra RS/D of 60 W m m. However, elimination of Cov has a more signicant effect on fT, leading to a higher value for the FinFETdesignedwithGS/Dunderlap.ThisdemonstratesourdesigninsightthatGS/Dunderlap could be benecial for highfrequency RF applications. The design of GS/D underlap for highfrequency RF applications will involve trading off RS/D for Cov. The optimal design will be the oneinwhichCoviseliminatedwithminimumextraRS/D.Therefore,thedesignchallengewillbe to maximize the doping concentration in the S/Dextension region near the gate edge, without diffusing signicant dopants in the UTB. This implies that the optimal GS/D underlap for highfrequencyRFapplicationswillbesmallerthanthatforlowpowerRFapplications.Thisisshown in Table. 4.1, where the UFDGpredicted fT of a 28nm DG FinFET designed with a short GS/D underlap (~2nm) is higher than that of the FinFET with a GS/D underlap (~4.5nm), which is optimal for lowpower RF applications 43 RF FinFET Scaling In Section 4.2 we concluded that analog/RF performance of FinFETs is superior to that of bulkSiMOSFETs.Therefore,inthissectionwefocusonlyonFinFETs,anddiscusstheeffectof theirscalingonanalogFOMs.Thescalingeffectwasdiscussedin[35],withFinFETsscaledfrom 1 m m to 60nm. For FinFETs with such large gate lengths, IDS is dened by Qch at the position in PAGE 58 58 channel where the velocity saturates, times the saturation velocity (vsat), or times a higher effective velocity (vsat(eff) > vsat) due to overshoot [13]. But, as Lg is scaled, vsat(eff) increases for a given VDS because of more overshoot, and this quasiballistic transport becomes quite signicant. Ultimately then, IDS becomes so high that it is limited by the maximum thermal velocity (vinj) with which carriers can enter the channel from the source [10], and the transport appearsballistic,withIDSdenedbyQchatthe(virtual)sourcetimesvinj.Therefore,asweshow in this section, the effect of scaling on analog FOMs of FinFETs as they are scaled to the gate lengths (<30nm) where quasiballistic transport becomes signicant could differ substantially from that discussed in [35]. We discuss the effect of scaling on analog FOMs of FinFETs as they are scaled from 65nm to 18nm, with proper accounting for quasiballistic transport. UFDG predicts that the limitation of the current due to quasiballistic transport will onset at Lg ~ 30nm. Since the effect of quasiballistic transport is most noticeable in the stronginversion region, we look at the analog FOMs in this bias region. We assume undoped DG FinFETs, with tSi = Lg/2 and a pragmatic [2] SiON tox = 1.3nm. UFDG predictions of the FinFET gm versus Lg are plotted in Fig. 4.3. We see a steady increase of gm down to Lg@ 30nm, below which gm tends to saturate. For Lg > 30nm, IDS is not limited by vinj, and the quasiballistic transport improves with decreasing Lg due to increasing vsat(eff);gm,dependenton u in(4.3),increaseswithdecreasingLg.ForLg<30nm, u atthesource approaches vinj, which is virtually biasindependent, and hence gm ultimately saturates. This is not good for RF. TheUFDGpredictionsplottedinFig.4.4showtheeffectofscalingLgontheFinFETgDS, withandwithouttheballisticcurrentlimitinthemodel.Ingeneral,gDSincreaseswithdecreasing Lg. For increasing VDS, the magnitude of Qch is reduced because of the pinchoff tendency, but this reduction is compensated by DICE [12], with the charge enhancement being comparable to PAGE 59 59 the pinchoff charge loss. Therefore, gDS is predominantly determined by the increase in vsat(eff)with VDS, and hence increases with decreasing Lg until IDS reaches the ballistic limit. When IDSis limited by vinj, gDS tends become independent of Lg; it does increase some for very short Lgbecause of DICE and virtually no pinchoff, however. Note in Fig. 4.4 how much gDS is reduced bytheeffectofvinj.Thebiasindependentnatureofvinjisthemainreasonforthisreduction.This is benecial for RF. UFDGpredictionsoftheFinFETAvoversusscaledLgareplottedinFig.4.5.Theseresults reectthegmandgDStrendsinFigs.4.3and4.4.ForlongerLgwheretheballisticcurrentlimitis not so important, Avo decreases signicantly with scaling. However, when ballistic limit sets in, becauseofthesaturationtendenciesofgmandgDS,Avovirtuallysaturates.Thisisalsobenecial for RF. Finally,UFDGpredictionsoftheeffectofscalingonfTareplottedinFig.4.6.Ingeneral,fTincreases with scaling, which is good for RF. When the ballistic current limit is not important, fTincreases with decreasing Lg because of both the Lg and u dependences in (4.5), with the latter increasingwithvsat(eff).WhenvinjbeginstolimitIDS,fTincreasesonlybecauseofdecreasingLg, and this increase can be quite signicant if the Cp/CG(int) ratio in (4.5) is limited. Based on our simulations, we can project that fT > 500GHz is attainable for Lg = 18nm FinFETs. The UFDGpredicted results in Fig. 4.34.6 suggest that DG FinFETs in RF applications canindeedbescaledtoatleast18nmgatelengths,withverygoodperformanceprojected.Below 18nm, their RF performance tends to be undermined by the quasiballistic transport, which also tends to limit their digital performance. We note however that the effect of quasiballistic transport on analog FOMs in the moderateinversion region, for lowpower RF applications, will not be as signicant as in the stronginversion region discussed herein. PAGE 60 60 44 Summary Most of the literature discussing the analog/RF performance of DG FinFETs and bulkSi MOSFETs is based on numericalsimulation and experimental results, with little emphasis on physical explanations. In this chapter, analog/RF performances of FinFETs and bulkSi MOSFETs have been insightfully compared, and FinFETs have been shown to be superior to bulkSi MOSFETs. We showed and discussed the benecial effect of GS/D underlap on analog/ RF performance of FinFETs, for both lowpower and highfrequency applications. We also gave insights on optimal design of GS/D underlap. Our analysis also showed that the effect of higher RS/D in FinFETs, as compared to that in bulkSi MOSFETs, does not signicantly affect the analog FOMs. Finally, we showed that the undermining effect on analog FOMs of scaling FinFETs to gate lengths below ~30nm, where UFDG predicts that quasiballistic transport will limit the current. This trend is signicantly different from that for FinFETs with longer gate lengths,forwhichweshowedhowtheyaresuperiortobulkSiMOSFETsinRFapplications.We note, therefore, that simulation and analysis of nanoscale FinFETs in RF applications must account for the quasiballistic transport. PAGE 61 61 Table41.ComparisonofUFDGpredictedfTofanLg=28nmDG FinFEThavingaGS/Doverlap,withthatofFinFETs havingGS/Dunderlapoptimizedforlowpowerandhighfrequency RF applications. DesignRS/D ( W m m)fT (GHz) GS/D Overlap100322 GS/DUnderlapfor LowPower RF 160332 GS/DUnderlapfor HighFrequency RF 120363 PAGE 62 62 Figure41.UFDGpredictedgDSofa28nmDGFinFETwithtSi=14nmandtox=1.3nm. The values have been normalized to hSi. For the device with GS/D underlap, a guassian doping profile with straggle of 11.4nm was used, and Lext = Lg. This doping profile leads to a GS/D underlap of about 4.5nm, which is optimal for lowpower RF applications [34]. 0.00.10.20.30.40.50.60.70.80.91.01.11.2 VDS [V] 0.0 25.0 50.0 75.0 100.0 125.0 150.0gDS [ m S/ m m] w/o underlap w/ underlap VGS = 0.4V PAGE 63 63 Figure 42.UFDGpredicted CG (normalized to hSi) versus VGS at VDS = 1.2V, with and without GS/D underlap. The S/D doping profile is same as for Fig. 4.1. This S/D doping profile introduces an extra RS/D of about 60 W m m. Note the decreasing benefit of GS/D underlap with increasing VGS. The difference in the two plots at high VGS is mainly due to the difference in RS/D. 0.00.10.20.30.40.50.60.70.80.91.01.11.2 VGS [V] 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2CG [fF/ m m] w/o underlap w/ underlap VDS = 1.2V PAGE 64 64 Figure 43.UFDGpredicted gm versus Lg of DG FinFETs with tSi= 0.5Lg, tox = 1.3nm, and abrupt S/D doping profiles (no underlap); VGS = 1.0V and VDS = 1.2V. 15.025.035.045.055.065.0 Lg [nm] 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7gm [mS/ m m] PAGE 65 65 Figure 44.UFDFpredicted gDS versus Lg for the FinFETs of Fig. 4.3, with andwithoutconsiderationofquasiballisticlimit;VGS=1.0Vand VDS = 1.2V. 15.025.035.045.055.065.0 Lg [nm] 0.00 0.10 0.20 0.30 0.40 0.50gDS [mS/ m m] w/ Ballistic limit w/o Ballistic limit PAGE 66 66 Figure45.UFDGpredictedAvoversusLgfortheFinFETsofFig.4.3;VGS=1.0V and VDS = 1.2V. 15.025.035.045.055.065.0 Lg [nm] 0.0 50.0 100.0 150.0 200.0Avo PAGE 67 67 Figure 46.UFDGpredicted fT versus Lg for the FinFETs of Fig. 4.3; VGS = 1.0V and VDS = 1.2V. 15.025.035.045.055.065.0 Lg [nm] 100.0 200.0 300.0 400.0 500.0 600.0fT [GHz] PAGE 68 68 CHAPTER 5 INSIGHTS ON DESIGN AND SCALABILITY OF THINBOX FD/SOI CMOS 51 Introduction MOSFETswithundoped,fullydepleted(FD)ultrathinbodies(UTBs)willhavetoreplace the conventional (bulkSi and partially depleted (PD) SOI) devices if CMOS technology is to be scaled to the end of the SIA roadmap [37] where gate lengths (Lg) are projected to be less than 10nm.NointentionaldopingintheUTB/channeleliminatestheproblemofthresholdvoltage(Vt) variation,whichplaguesconventionalnanoscaleMOSFETs.CandidateFDdevicesincludequasiplanardoublegate(DG)FinFETs[38],whichwehaveaddressedinpreviouschapters,andplanar singlegateFD/SOIMOSFETs,whichhaverecentlyevolvedtothinBOX(TBOX)structureswith heavy groundplane (GP) doping in the substrate under the device [39][42] as illustrated in Fig. 5.1. The GP, with proper doping (p+ for nMOS and n+ for pMOS), provides a backgate work function which, with thin BOX, tends to accumulate the back surface of the UTB, thereby increasing the transverse electric eld (Ex) and ameliorating the shortchannel effects (SCEs). Also, the GP can be properly biased (negatively for nMOS and positively for pMOS) to enhance the amelioration as well as adjust Vt. Note, though, the added CMOS process and layout complexity that the selective GPs imply.Unlike conventional devices, where the channel doping densitysimultaneouslyaffectsSCEsandVtofthedevice,itisbelievedthatTBOXdevicescanbe designedwithindependentcontrolofSCEsandVt;UTBthicknessdenesSCEs,andGPbiascan be used to tune Vt [43]. However, as we will show in this chapter, this in not the case, and signicantly complex processing is required to scale TBOX device toward the end of the CMOS roadmap. AnobviousdesignissueoftheTBOXMOSFETisthehighVtimpliedbytheincreasedEx. From the 1D Gausss law at the front surface of an undopedbody TBOX MOSFET, we get [3] PAGE 69 69 ,(5.1) where fsf and fsb are the potential at the front and back surfaces, respectively, and FGfS is the workfunction difference between the front gate and the undoped body. Without SCEs (or, for long Lg) and with midgap gate (as commonly presumed for undoped UTBs), we can, for (hole) accumulation (in the nMOSFET) at the back surface, derive from (5.1) ,(5.2) where fc~0.4Visthecharacteristicsurfacepotentialat(inversionandaccumulation)thresholdin an undoped body, and tSi and toxf are the UTB and frontoxide thicknesses, respectively. The Vt(long) expression in (5.2) is an approximation because we assumed eSi/ eox@ 3 and fsb@ fc for holeaccumulationatthebacksurface,andignoredniteFermipotentialduetonaturaldopingin the body. For tSi ~ 10nm and toxf ~ 1nm, (5.2) gives Vt(long)@ 0.6V. And, Vt(long) will increase signicantlywiththelevelofaccumulation(untilitisverystrong)andwithdecreasingtSi;fortSi=5nm,(5.2)givesVt(long)@ 0.9V!TheSCEswilllowerVt,butnonethelessittendstobetoohigh for HP applications; LP applications have thus been the recent focus of TBOX FD/SOI CMOS studies[41],[42].WethereforerstdesignandexaminenanoscaleTBOXdevicesforLP,i.e.,low Ioff, and then consider the possibility of HP applications. We use Taurus [44] for 2D numerical simulations,andphysicallyinterpretresults,withsupportfromourphysicsbasedcompactmodel UFDG [16], to gain insights on design and scalability. 52 LP Devices Forlatercomparisons,werstdesignandsimulateaTBOXFD/SOInMOSFETthatcanbe relatedtorecentmeasuredandsimulatedLPdeviceresultsin[41]and[42].ForLg=25nm(=Leff V GfS F GfS 1 e Si t oxf e oxf t Si + f sf e Si t oxf e oxf t Si f sb + = Vtlong ()16 toxftSi+ fc@ PAGE 70 70 due to assumed abrupt source/drain junctions without gate underlap/overlap), we assume toxf = 1.2nm (=EOT), tBOX = 10nm, unbiased (grounded) p+ GP, midgap gate, and undoped UTB with thickness (tSi) tuned to get adequate SCE control, or DIBL @ 100mV/V for VDD = 1.0V. Our Taurus simulations show that tSi = 6nm (=Lg/4.2) is needed, which is signicantly more aggressiveUTBscalingthanthat(~Lg/3)speciedin[41]and[42].(OurassumptionofabruptS/ D junctions leads to worstcase SCEs for a given Leff, but it is not the reason for this inconsistency.) Predicted device characteristics are given in Table 5.1, where they are compared with results for the same nMOSFET without the GP (DIBL = 120mV/V) and with thick BOX (DIBL = 220mV/V). Note the benet of the thin BOX even without the GP. The signicant reduction in DIBL yielded by the thin BOX alone is due to, rst, better control of the electric potentialintheUTBbythe(grounded)substrate,orbackgate,second,theenhancedEx,which tends to move the inversioncharge centroid towards the (front) gate [3], [45], and, third, amelioration of the electric eldfringing effect in the thin BOX [45], [46]. The reduced DIBL lowers Ioff, but the dramatic decrease of Ioff shown in Table 5.1 reects a signicant increase of Vt(long)in (5.2) due to the thin BOX as well. (In our Taurus simulations, we are neglecting quantization, the effect of which on Vt is, for thick BOX and reasonable tSi > 4nm, indeed negligible [28] due to low Ex. For TBOX devices with(unbiasedorbiased)GP,ExishigherforlongLg,butfornanoscaleLg,Exisreducedby2D effects, as shown by Taurus, such that the quantization effect on Vt is still small.) As mentioned, the thin tBOX = 10nm ameliorates the eld fringing in the BOX, but it does not completely suppress its effects. In Fig. 5.2 we show Taurusand UFDGpredicted weakinversion currentvoltage characteristics of an Lg = 30nm TBOX nMOSFET, with tBOX = 10nm and tSi = 6nm. The UFDG results, with BOX eldfringing modeling [46] tuned to the Taurus results,andwithouttheeldfringingmodelingactivated,clearlyshowsignicantdegradationof PAGE 71 71 the subthreshold characteristics, or SCEs, due to the fringing even for 10nm BOX. (We thank Shishir Agrawal, a postdoctoral student at the University of Florida, for doing the simulation in Fig. 5.2.) Contrary to expectation [39][42], our simulation results in Table 5.1 (for the nMOSFET) showthattheadditionoftheunbiasedGPonlyslightlyreducesDIBLandIofffurther.Thep+GP benetissmallbecauseitonlyincreasesthebackgateworkfunctionby~200mV(foratypicalpsubstrate), which does not increase Ex much for tBOX = 10nm. However, for the TBOX pMOSFET, the n+ GP will decrease the backgate workfunction by ~700mV, which will impact the device characteristics much more. Simulations show that for the TBOX pMOS counterpart to thenMOSFETinTable5.1,theGPreducesDIBLfrom140mV/Vto120mV/V,butdecreasesIoffby a factor of ~100. We note that the effect of the higher Ex is negligible with regard to DIBL becauseofthethintSi,butisdramaticwithregardtoIoffviathemuchhigherVt(long).Toillustrate this point further, we show in Fig. 5.3 Tauruspredicted weakinversion currentvoltage characteristics of TBOX CMOS devices, with and without GPs. We thank Shishir Agrawal for doing this simulation. Note that the GP effect (especially the increased Vt) is dramatic for the pMOSFET, but much less signicant for the nMOSFET. We thus might question whether the (unbiased) GP, with its process complexity, is worthwhile for the TBOX nMOSFET. (We show later that it is needed, with bias, for scalability, however.) Even with it, the predicted Ioff ~ 1000pA/ m m is much too high for LP, even though the SCEs are controlled; Ironically; Vt is too low. Our simulation results in Table 5.1 are in general accord with measured DIBL and Ioff vs. Lg and tSi for thickBOX nanoscale FD/SOI MOSFETs in [47]. The inconsistency of our results withthosein[41]and[42],regardingSCEcontrolandLPdesign,couldbeduetoGS/Dunderlap [26] in the devices examined in [41] and [42], which renders Leff > Lg and yields better SCE PAGE 72 72 control(andwhichisessentialfornanoscaleUTBdevicedesign[48]).Tocheck,weredesignour Lg = 25nm thinBOX/GP nMOSFET with underlap; we increase tSi = 8nm (~Lg/3 in line with [41]and[42]),andnowtunetheunderlap(LeSD)togetDIBL=100mV/V.Oursimulationsreveal that LeSD = 2.5nm is needed, meaning Leff = Lg + 2LeSD = 30nm. Part of the inconsistency is possibly explained, but our predicted Vt is still too low and Ioff is too high for LP. TogetanacceptableLg=25nmLPdesign,wemustdecreaseIoffto~10pA/ m m,irrespective ofDIBL.BecauseofthelessereffectoftheGPinthenMOSFET,thedesignofthisdeviceismore demanding, and hence we focus on it. We include the GP because biasing it is one way of decreasing Ioff. Another way is thinning tSi, as implied by (5.2), which we check rst. We begin with the device having the 2.5nm underlap, and we now tune tSi to get acceptable Vt and Ioff at VDD = 1.0V. We nd that tSi = 6nm (=Lg/4.2 = Leff/5) is needed, and we get Ioff@ 30pA/ m m. We note that the predominant effect of thinning tSi here is to increase Vt(long). Interestingly, we get DIBL = 60mV/V for this device, meaning that DIBL alone is not an acceptable design criterion for LP thinBOX FD/SOI MOSFETs. This new insight is reected in Table 5.2, where we give TauruspredictedIoffandDIBLforourLPnMOSFET,comparedwithpredictionsforvariabletSi. Note that thicker tSi = 7nm, which yields Ioff@ 100pA/ m m and DIBL = 80mV/V, could be an acceptableLPdeviceaswell.ButalsonotethatthedesignsoftheseLPTBOX/GPMOSFETsare much more stringent (i.e., much lower tSi/Lg ~ 1/4 is needed) than suggested in [41] and [42]. Perhaps a GP bias (for which the selective p+ and n+ GPs are necessary in the CMOS technology),whichincreasesEx,canloosenthedesigncriteria(i.e.,enableuseofthickertSi)and give a more optimistic scaling outlook, albeit with added technology and layout complexity. Focusing on Ioff as the main LP design criterion, we give simulation results in Table 5.3 derived by tuning tSi to get Ioff ~ 10pA/ m m for GP bias (VGP) ranging from 0V (as in Table 5.2) to 5.0V, which ensures strong backsurface accumulation and thus maximizes Ex. Indeed, the tSi PAGE 73 73 requirement can be relaxed signicantly with GP bias. For the strongaccumulation case (which requiresasizeableVGPmagnitude),agoodLPdesignisachievedwithtSi=15nm(=Lg/1.7=Leff/ 2withthe2.5nmunderlap),asopposedto6nmfornoGPbias.Interestingly,noteinTable5.3the anticorrelation of Ioff and DIBL for decreasing VGP; as we relax the tSi requirement for Ioffcontrol with decreasing VGP, DIBL increases whereas Ioff decreases. This surprising result is due to the fact that Vt(long) is being increased, while the SCEs worsen, with the former effect being predominantwithrespecttoIoff.NotethatdecreasingVGPwilltendtoincreaseIoffbyincreasing junction tunneling at the back surface, but the effect of increase in Vt(long) due increase in Expredominates, and therefore, there is a net decrease in Ioff with decreasing VGP. TheencouragingresultsinTable5.3concerninguseofGPbiassuggestthat,withit,TBOX FD/SOICMOSmaybescaledconsiderably.Wecheckthescalability,intermsofLefffordevices withunderlap,bytryingtotunetSiforIoff~10pA/ m m,withacceptableDIBL,asLeffisshortened (from30nmasinTable5.3)andVGPissettoensurestrongaccumulation.(ThisVGPwilltendto become more negative with decreasing Leff due to increase in Ex, as dened by decreasing tSirequired for SCE control.) We still let toxf = 1.2nm and tBOX = 10nm. The simulation results are giveninTable5.4.InlinewiththeabovenoteabouttheimportanceofVt(long)vs.tSi,wendthat Vt becomes too high when DIBL @ 100mV/V, leading to extremely low Ioff and reecting poor Ion.GateworkfunctiontuningtodecreaseVtisthuscalledfor,whichaddsevenmorecomplexity tothefabricationprocess.WeincludeinTable5.4thedecreaseintheworkfunction( DFGfbelow midgap)neededtoincreaseIoffto~10pA/ m m,andtherebygetacceptableIonforLPperformance. Further, we stop the scaling when tSi reaches ~5nm, which thus denes the scaling limit of Leff@ 18nm for LP thinBOX/GP (with sizeable VGP) CMOS; the needed gate work function is near conductionbandedgeforthenchanneldevice.TheassumedminimumSOIthicknessisbasedon thequantizationeffect[28],whichbecomesprohibitivelysevereforthinnertSi,aswellastheSOI PAGE 74 74 technology. Additional simulations reveal that without GP bias, the LP scaling limit, set by tSi = 5nm with a midgap gate, is Leff =28nm. From (5.1), the Vt of a TBOX MOSFET can be expressed as ,(5.3) where fsf t and fsb t are the potential at the front and back surfaces at threshold, respectively. UnlikeinthederivationofthesimpleexpressionforVt(long)in(5.2),herewedoamorethorough analysisbyconsideringtheniteFermipotential( fF)duetonaturalptypedoping(~1015cm3)in the unintentionally doped UTB [3]. We assume for the nMOSFET with strong backsurface accumulation, fsf t = fc + fF and fsb t = fa + fF, where fa@ fcis the strongaccumulation counterpartto fc.SimilarlyforthepMOSFETwithstrongbacksurfaceaccumulation,weassume fsf t= fc+ fFand fsb t= fa+ fF.Withtheabove fsf tand fsb tfornMOSFETandpMOSFET,and noting that FGfS = fF for a midgap gate, we nd that the nite fF does not affect Vt when the back surface is accumulated, and so the CMOS devices are symmetric in this regard. Therefore, the TBOX pMOSFET for LP applications can be designed and scaled in a manner similar to that of the TBOX nMOSFET. 53 HP Devices TochecktheHPapplication,anditsscalability,werstpresumethatVGPmustbenegative enoughforstrongaccumulationtoensureSCEcontrol.WebeginwiththeLeff=30nmnMOSFET in Table 5.4, and tune DFGf to increase Ioff to an acceptable ~100nA/ m m, which implies acceptableIon(iftheexternalS/DseriesresistanceintheUTBdeviceisadequatelylimited[47]). WethenscaleLeff,tuningtSiand DFGftogetDIBL @ 100mV/VaswellasIoff~100nA/ m m.The simulation results, in Table 5.5, are discouraging. They show, for a specic Leff, that the DFGfrequired to tune Ioff for HP is much larger than that required for LP, being near conduction bandV t F GfS f sf t 3 t oxf t Si ++ f sf t f sb t @ PAGE 75 75 edgeforLeff=25nmandperhapsbeingimpossibleforLeff=18nm.Therequired DFGfincreases with decreasing Leff due to the increase in Vt(long) in (5.2) dened by the thinner tSi needed for SCE control. Thus, as indicated in Table 5.5, the HP scaling limit could be longer than the Leff = 18nmdenedbytSi=5nm,whereanunacceptablyhigh[49] DFGf=850mVwouldbenecessary. Without GP bias (VGP = 0V), the HP scalability dened by tSi = 5nm is Leff = 25nm, with a required DFGf = 200mV. These results then suggest that, for the nMOSFET, the realistic scaling limitisreachableevenwithoutaGPbias,andthusevenwithouttheGP,aswehaveintimated,but is not close to the end of the ITRS roadmap. The same analysis of the TBOX pMOSFET for HP applications leads to a similar noGP design.ItsSCEswillbevirtuallythesameasinthenoGPnMOSFET,andhenceitsscalinglimit isalsoLeff@ 25nm.InaTBOXwithoutGPbias(andnoGP)andwithdepletedbacksurface,from the 1D analysis in [3] we get ,(5.4) whereCb= eSi/tSiandCoxb= eox/toxb.Assumingthat fsf t= fc+ fFforthenMOSFET,and fsf t=fc + fF for the pMOSFET, with fsb t dened by (5.4), we get from (5.3) ,(5.5) where Vtn and Vtp are the threshold voltages of the TBOX HP nMOSFET and pMOSFET, respectively, and r is the body factor [3]. Therefore, TBOX CMOS for the HP application is not symmetric. For the TBOX pMOSFET, the needed DFGf due to the fF term in (5.5) is negative (above midgap), and its magnitude is about 50mV (in worst case, as implied by (5.5)) less than that for the nMOSFET. f sb t C b C b C oxb +  f sf t = V tp V tn 2 r f F + = PAGE 76 76 54 Comparisons with FinFETs In this section we compare potential performances of nanoscale thinBOX FD/SOI MOSFETsandDGFinFETsinordertogainmoreinsightsontheviabilityoftheformer.Since,as discussed, the performance and design challenges of the TBOX nMOSFET and pMOSFET are similar,wefocusonthenchanneldevice.InTable5.6,wesummarizeourprojectedscalinglimits (intermsofLeff=Lg+2LeSD)ofthinBOX/GPnMOSFETsforLPandHPCMOSasdenedby tSi = 5nm, and compare them with Taurus predictions for DG nFinFETs with the same tSi, or n thickness.ThescalabilityofthethinBOX/GPdevicewithnoVGPandmidgapgateisworstofall. NegativeVGPforstrongbackaccumulationtendstoimproveit,butalsobringsintherequirement of tuned DFGf. For LP applications, we project a scaling limit Leff = 18nm, which, with GS/D underlap, implies Lg ~ 10nm. The projected HP scaling limit of Leff@ 18nm in Table 5.6 is questionable because of the very large DFGf required to get acceptable Ioff and Ion, as noted before. A scaling limit of Leff@ 25nm, with tSi = 10nm, is probably more realistic; as shown in Table 5.5, it requires a near conduction bandedge gate work function. Coincidently, as shown in Table 5.6, the projected HP scaling limit without VGP for tSi = 5nm is also 25nm. Therefore, for HPthinBOXFD/SOICMOS,VGPseemsunnecessary,andthussodotheGPs,butthescalability is not good. DG FinFETs yield the most relaxed tSi requirement for SCE control due to the two gates [48]. Therefore, for HP applications where the scalability is limited by SCE requirements, the FinFET, with midgap gate, is most scalable. The Leff@ 15nm limit noted in Table 5.6 implies, with GS/D underlap [26], an Lg scaling limit near the end of the ITRS. Note that our simulation results in Table 5.6 indicate that near the scaling limit, for adequate SCE control in the DG FinFET,tSi/Leff@ 1/3willbeneeded,whichissmallerthangenerallypresumedtSi/Leff@ 1/2[50]. This is because toxf is not being scaled due to gateleakage considerations. For LP applications, PAGE 77 77 thescalabilityoftheDGFinFET,withmidgapgate,islimitedbytheIoffrequirement.Therefore, it is less scalable than the thinBOX/GP MOSFET with VGP, for which the noted workfunction tuning is necessary to get acceptable Ioff. Of course, such tuning could be used for the FinFET as well.Withanearvalencebandedgegate,asshowninTable5.6,theDGnFinFETcouldbescaled to Leff@ 15nm (Lg < 10nm), limited by the SCE requirements, rendering it most scalable for LP applications also. ThecomparisonofthetwoFDdevicesmustinvolvemore.ThenegativeVGPappliedtothe thinBOX/GP nMOSFET increases the connement of electrons towards the front surface, leading to higher inversionlayer capacitance (Ci) than in the DG FinFET, which is subject to signicant bulk inversion [48]. This difference is reected in Fig. 5.4, where we show a comparison of Tauruspredicted lowVDS stronginversion currents in the Leff = 30nm thinBOX/ GP nMOSFET in Table 5.5 and in an Leff = 30nm DG nFinFET with tSi (=15nm) tuned to get similar DIBL and DFGf (=60mV) tuned to get similar Ioff. The simulation results in Fig. 5.4 imply,atVGS=1.0V,thathigherCiinthethinBOX/GPMOSFETleadsto17%higherinversion chargedensity(Qi=qNinv)thanthatsupportedbyeachgateintheDGFinFET.Thistranslatesto less than 2 x (1.7 x for low VDS) current in the FinFET relative to that in the FD/SOI MOSFET. (The external S/D series resistance was kept low in the simulations in order to avoid any discrepancy in effective biases due to different current levels, and a constant meff model was used so that the difference in currents reected directly the different Qi and Ci.) The higher Ci due to Ex is a benecial effect for the thinBOX/GP MOSFET. However, Exalsoimplieslower meffduetomoresurfaceroughnessscattering,whichtendstonegatethehigher Qi with regard to Ion. For a typical Ninv in strong inversion, the surface electric eld in the thinBOX/GP MOSFET is higher than that in the DG FinFET not only because of the GP, but also because the entire inversion charge is supported by one gate, as opposed to two gates in the PAGE 78 78 FinFET.Thus,stronginversioncarriermobilitycanbehigherintheFinFETbyafactoroftwo,or more[48].Further,thehighExalsounderliesanenhancedquantizationeffectinstronginversion, which lowers Ninv at a given VGS. Due to thin box, source/drainsubstrate capacitance could be signicant in TBOX CMOS, and, unlike in DG FinFETs, there is a nonzero (effective) body capacitance (Cb(eff)) associated with TBOX MOSFETs [3], which tends to increase the subthresholdslope(S)andIoff(althoughtheSCEsusuallydeneS),aswellasundermineCMOS speed. Also, heavily doped GP may lead to signicant depletion in the S/D extension regions whichwouldincreasetheseriesresistanceandaccentuateSCEs[51].However,TBOXMOSFETs may have some advantage over FinFETs because of their planar structure; e.g., controlling UTB thicknessintheTBOXdeviceiseasierthaninFinFETs,whichimpliesthatyieldofTBOXbased SRAM is higher than that of FinFETbased SRAM [52][53]. 55 Conclusions Wehaveusednumericaldevicesimulations,withphysicsbasedinterpretationsofresults,to design and study thinBOX FD/SOI CMOS, and to assess its scalability, for both LP and HP applications, relative to that of DGFinFET CMOS. For LP, we found that both Ioff and DIBL must be considered as design criteria, and that they are not necessarily correlated. We found that, with the complex processing and layout (due to selective, sizable GP biasing and tunable gate work function for different Lg), the LP thinBOX/GP MOSFET scalability, with GS/D underlap (Leff > Lg), is Lg ~10nm; whereas, with gate workfunction tuning and GS/D underlap, the LP DG FinFET can be scaled to the end of the SIA roadmap where Lg < 10nm is projected. For HP applications, the DG FinFET is clearly the winner in terms of scalability. Our simulation results showthatwithoutanyrequiredworkfunctiontuning,i.e.,withamidgapgate,theHPDGFinFET can also be scaled to the end of the roadmap; whereas, because of implausible workfunction engineering required, the scalability of the HP thinBOX MOSFET is severely limited, although PAGE 79 79 the GP can be eliminated and the processing signicantly simplied. ThinBOXFD/SOIMOSFETshavetheadvantageofbeingplanarand,therefore,similarto conventional PD/SOI devices in terms of processing. However, the added process complexities noted herein, with less potential HP scalability than DG FinFETs, make them less attractive. Hence, thinBOX FD/SOI CMOS could be a viable interim technology, bridging conventional CMOSandDGFinFETCMOS.Thelattertechnology,whichcanbepragmaticallydesigned[48], is potentially scalable to the end of the SIA roadmap for both HP and LP applications. PAGE 80 80 Table51.TauruspredictedcharacteristicsofLg=25nm(=Leff)FD/SOI nMOSFETs with midgap gate and tSi = 6nm. DesignDIBL (mV/V)Ioff (pA/ m m) Thin BOX w/ GP100103Thin BOX1203 x 103Thick BOX (200nm)220106Table 52. Tauruspredicted characteristics, vs. tSi, of Lg = 25nm TBOX/GP nMOSFETs with 2.5nm GS/D underlap and midgap gate. tSi (nm)DIBL (mV/V)Ioff (pA/ m m) 66030 780100 81001000 PAGE 81 81 Table53.Tauruspredictedcharacteristics,vs.VGP,ofLg=25nmTBOXGP nMOSFETs with 2.5nm GS/D underlap and midgap gate. VGP (V)tSi (nm)DIBL (mV/V)Ioff (pA/ m m) 066030 1.099020 5.01510010 Table 54. Tauruspredicted characteristics, vs. Leff, of TBOX/GP nMOSFETs with VGP for strong accumulation and controlled DIBL. The workfunction reduction below midgap required to increase Ioff as shown to ~10pA/ m m for feasible LP is given. Leff (nm)tSi (nm)Ioff (pA/ m m) DFGf (mV) 3015100 25101100 l85103450 PAGE 82 82 Table 55. Tauruspredicted characteristics, vs. Leff, of TBOX/GP nMOSFETs with VGP for strong accumulation. The workfunction reduction below midgap required to increase Ioff to ~100nA/ m m for acceptable Ion and viable HP is given. Leff (nm)tSi (nm)DIBL (mV/V) DFGf (mV) 3015100380 2510100500 l85110850 Table56.TauruspredictedLPandHPscalinglimits(Leff,which,withGS/D underlap,canbe510nmlongerthanLg),denedbytSi=5nm,for thinBOX/GP nMOSFETs (tBOX = 10nm) and DG nFinFETs (all with toxf = 1.2nm). The devices have been designed for Ioff ~ 10pA/ m m and ~100nA/ m m for LP and HP applications, respectively, with DIBL 100mV/V. The 18nm limit for the HP thinBOX/GP device with VGP (for strong accumulation) is questionable due to the very large DFGf needed; the scaling limit of 25nm without VGP (and without GP) is more realistic and pragmatic. LP ThinBOX/GP w/o VGPThinBOX/GP w/ VGPDG FinFET Leff (nm)281825/15 DFGf (mV)04500/450 HP ThinBOX/GP w/o VGPThinBOX/GP w/ VGPDG FinFET Leff (nm)2518?15 DFGf (mV)2008500 PAGE 83 83 Figure 51. Basic thinBOX FD/SOI nMOSFET structure, with P+ GP. n+Gf pn+BOX STI STIp+GPSi Substrate PAGE 84 84 Figure 52. Taurusand UFDGpredicted weakinversion currentvoltage characteristics of a TBOXFD/SOInMOSFET(Lg=30nm,tSi=6nm,tBOX=10nm,noGP).TheUFDG prediction, with the electriceld fringing parameters tuned to t Taurus data, is contrasted to a UFDG prediction with the eld fringing modeling deactivated. A constant electron mobility ( mn=300cm2/Vs) was assumed in both the Taurus and UFDGsimulations.TheTaurusUFDGdiscrepanciesinstronginversionareduetono signicant series resistance in the Taurus domain. VGS(V)IDS (A/ m m) 0.20.00.20.40.60.8 101510141013101210111010109108107106105104103 Taurus UFDG w/ electricfield fringing ON UFDG w/ electricfield fringing OFF VDS = 50mV, 1.0V 1.0 PAGE 85 85 Figure 53. Comparison of Tauruspredicted currentvoltage characteristics of TBOX FD/SOI CMOS devices, with and without GPs. The devices were designed with Lg = 25nm, tSi=5.5nm,S/Dspacerwidth=15nm,andGaussianS/Ddopingprole,whichgives Leff=30nm,i.e.,2.5nmGS/Dunderlap.ThesubstrateforboththenMOSandpMOS devices was assumed to be ptype, which underlies the dramatic GP impact in the latter and lesser impact in the former. A) nMOSFET. B) pMOSFET. 1.00.80.60.40.20.0 101510141013101210111010109108107106105104103102 pMOSFET w/o GP pMOSFET w/ GP 0.20.00.20.40.60.8 101510141013101210111010109108107106105104103102101100 nMOSFET w/o GP nMOSFET w/ GP VGS (V) VGS (V)IDS (A/ m m) IDS (A/ m m)1.0 0.2A B PAGE 86 86 0.00.10.20.30.4 0.5VGS (V) 109108107106105104103102IDS (A/ m m) 00.20.4 0.6 0.81VGS [V] 0 0.2 0.4 0.6 0.8 1 1.2 1.4IDS [mA/ m m] Figure 54. Comparison of Tauruspredicted currentvoltage characteristics of a TBOX nMOSFETwiththatofaDGnFinFETcounterpart.TheTBOXdeviceisthesameas Leff = 30nm TBOX device in Table 5.5; the DG FinFET was designed with Leff = 30nm,tSi=15nm,andtoxf=1.2nm.A)Comparisonofweakinversioncharacteristics ofthetwodevices; DFGfandtSioftheFinFETweretunedtogetIoffandDIBLclose to that of the TBOX device. B) Comparison of stronginversion characteristics of the two devices at low VDS (50mV), showing less than 2x current in FinFET relative to that of the TBOX MOSFET.DG FinFET TBOX DG FinFET TBOXA B PAGE 87 87 CHAPTER 6 SUMMARY AND FUTURE WORK 61 Summary This dissertation is focused on physicsbased modeling, optimal design, and performance of nanoscale DG FinFET CMOS for both digital and analog/RF applications. The major contributions of the research are summarized as follows. InChapter2,wemodeledDICEinnanoscaledoublegateMOSFETs,andimplementedit inourprocess/physicsbasedcompactmodelUFDG.TheeffectofDICEonthetransistorcurrent, terminal charge, capacitance, and transcapacitance was studied, and veried via numerical and UFDG simulations. We found that DICE is a benecial effect because it signicantly increases inversionchargedensity,andhencecurrent,withoutsignicantlyaffectinggatecapacitance.This is because the enhanced inversion charge is primarily supported by the drain. Its benecial effect was demonstrated by the speed enhancement of DG FinFET CMOS via UFDG/Spice3 simulations. We showed that the current enhancement due to DICE is signicantly larger for devicesinwhichquasiballistictransportisimportant.Forsuchdevices,thecurrentenhancement duetoDICEisdirectlyproportionaltotheenhancementininversionchargedensity,whereas,for devices in which quasiballistic transport is not important, the enhancement in current due to DICE is undermined by the increase in the gradualchannel length caused by DICE. In Chapter 3, we proposed a design approach in which S/D engineering can be used to adjust the Vt of nanoscale DG MOSFETs for lowpower and highperformance digital applications via limited densities of S/D dopants in the channel. The design approach was demonstratedandveriedvianumericalandUFDGsimulations,andexperimentalresults.Itwas shownthattheproposeddesignapproachaugmentstheutilityoftheGS/Dunderlap.Theissueof randomdoping effects was duly addressed by comprehensive Medicibased numerical PAGE 88 88 simulations.Oursimulationsconsideredtherandomdopingeffectsintheultrathinbody,aswell asintheS/Dextensionregions.Therefore,oursensitivityresultsincluderandomvariationsinVt, and also the random variations in Leff. It was argued that the design approach will be viable and benecial even in sub10nm regime. It was noted, however, that at such short Lg, additional analyses of quantization effects, mobility degradation, and ballistic transport will be called for. Also, source/drain engineering techniques to support this design approach will have to be developed. In Chapter 4, we compared the analog/RF performance of doublegate FinFETs with that of conventional planar bulk MOSFETs, and showed that the FinFET performance is better. Optimal design of FinFETs with GS/D underlap, and the effect of higher RS/D in FinFETs on performance were discussed. We showed that GS/D underlap signicantly benets the lowpower analog/RF performance of DG FinFETs by reducing DIBL and GS/D parasitic capacitances.Sincelowpowerdevicesarebiasedinthemoderateinversionregion,wherethegm/ ID ratio tends to be maximum, the increase in RS/D is not important due to low operatingcurrent levels. Devices for highfrequency applications, on the other hand, are biased in the stronginversion region, where gm is maximum. Therefore, for highfrequency applications, increase in RS/D due to underlap could be important due to high operatingcurrent levels, and could be detrimental to the device performance. However, it was shown that small GS/D underlap would still be desirable because it will benet the performance by eliminating GS/D overlap capacitance, the effect of which was found to be more signicant than that of the associated increase in RS/D. And nally, the effect of scaling on the analog/RF performance of FinFETs, as Lg is scaled below ~30nm where quasiballistic transport becomes important, was discussed. In Chapter 5, we studied the design of thinBOX FD/SOI MOSFETs for lowpower and highperformancedigitalapplications,andcomparedtheirscalabilitytothatofFinFETs.Forlow PAGE 89 89 power applications we found that, with complex processing and layout, thinbox FD/SOI MOSFETs can be scaled to Lg ~ 10nm; whereas FinFETs can be scaled to Lg < 10nm with signicantlysimplerprocessing.Forhighperformanceapplications,thescalabilityofFinFETsis signicantlybetterthanthatofthinBOXFD/SOIMOSFETs.WenotedthatthinBOXFD/SOIis similartoconventionalplanarMOSFETsintermsoftheprocessing,thereforeitcouldbeaviable interim technology, bridging conventional CMOS and DGFinFET CMOS. 62 Future Work In Chapter 3, we proposed, and demonstrated using Medici/UFDG simulations, a design approach in which limited densities of source/drain dopants in the channel can be used for Vtadjustment in nanoscale DG MOSFETs. This design approach will be viable only if reliable source/drainengineeringtechniquesaresuccessfullyrealized.Inordertorealizethesetechniques, the diffusion of dopants through thin lms should be modeled and experimentally veried. Also, the proposed design approach should be corroborated by additional analyses of quantization effect, mobility degradation, and ballistic transport for Lg ~ 10nm. In Chapter 4, we discussed the optimal design of DG FinFETs for lowpower and highfrequency analog/RF applications. This study was done at the device level with the emphasis on optimizing basic FOMs. The study should be further corroborated by demonstrative circuit simulations and analyses. In Chapter 5, we studied the design of thinBOX FD/SOI MOSFETs for lowpower and highperformance applications. The study is primarily based on weakinversion region analysis. In the stronginversion region, UFDG is incapable of predicting the characteristics of thinBOX devices with backgate bias because of carrier accumulation. For a more comprehensive study, strong inversion analyses of UFDG should be upgraded to render the model fully applicable to thinBOX FD/SOI devices with backgate bias. PAGE 90 90 APPENDIX AAUFDG MODEL REFINEMENTS A1 Introduction UFDG [16] is a process/physics based generic compact model which is applicable to diverse SOIbased DG MOSFETs. UFDG very effectively captures the unique physics of DG MOSFETs with UTB via robust modeling of terminal charge and carrier transport. UFDG has been veried by numerical device simulations and measured experimental results, and has been shown to reliably predict the characteristics of DG MOSFETs with Lg as short as ~30nm. For shorterLg,duetolackofexperimentalresultsandinadequatemodelingofcarriertransportinthe commercially available device simulators, there is no direct way of verifying the accuracy of UFDG, for example, that of its quasiballistic/ballistic carrier transport modeling. More than likely,futureUFDGupgradeswillbeneededasCMOStechnologyisfurtherscaled.Suchmodel upgrading is exemplied by this appendix, in which we discuss the renements we did in UFDG to make it more robust for reliable prediction of nanoscale DG MOSFETs studied in this dissertation. A2 StrongInversion Intrinsic Charge Modeling The voltagedependent terminal charges of the DG MOSFET is characterized in order to model the charge dynamics for largesignal transient simulations. The terminal charges are assumedquasistatic,andareindividuallyintegratedbasedonspatialdependenceintheMOSFET which follow from the analyses in [25], modied by the DICE analyses discussed in Chapter 2. Charge neutrality, which is important for the stability and convergence of a compact model, is satised due to physicsbased treatment of all the terminal charges. The charge modeling in UFDG is divided into two parts: triode and saturation regions, which are eventually merged for a continuous model. PAGE 91 91 In the triode region, frontgate charge (QGf) is characterized by the integral: .(A1) Backgate charge (QGb) is characterized by a similar integral at the back surface. Next, the integrated charge in the channel is evaluated by the integral: ,(A2) where Qch(y) is given by (2.4), which includes the DICE charge in the channel. The integrated inversionchargeisthenpartitionedbetweenthesourceandthedrain.Theportionoftheinversion charge assigned to the drain is evaluated by the integral: ,(A3) and rest is assigned to the source, .(A4) Finally, bodydepletion charge (QB) is dened as, .(A5) Typically QB is negligible because of undoped body. Note that in the previous [25] charge modeling, the draindepletion charge in the triode region was ignored. However, as we discussed in Chapter 2, DICE charge is signicant in nanoscale DG MOSFETs, and is primarily supported by the drain. Therefore, a corresponding depletion charge is assigned to the drain in order to maintain the charge neutrality. In saturation region, the charges dened for the triode region will still be valid with Lgreplaced by Lgch, and VDS replaced by VDS(eff), and they will be augmented by the charges Q Gf W g C oxf V GfS F GfB f 0 0 y ()Df y () [] yd0 L g= Q ch W g Q ch y () yd0 L g= Q Dch () W g y L g Q ch y () yd0 L g= Q Sch () Q ch Q Dch () = Q B W g L g qN A t Si = PAGE 92 92 associated with the highEy region. With Lgch and VDS(eff) solved as discussed in Chapter 2, we dene the saturationregion component of the frontgate charge (QGf sat) by the integral: ,(A6) andthesaturationregioncomponentofthebackgatecharge(QGb sat)willbedenedbyasimilar integral at the back surface. Since the carrier velocity is saturated in the highEy region, based on the current continuity, the charge density will be nearly uniform along y, and channel charge is dened by simple integral: .(A7) Analogous to the scheme in the triode region, Qch sat is partitioned between the source (QS(ch) sat) and the drain (QD(ch) sat). As dened in Chapter 2, the draindepletion charge is assigned to the drain, which includes charge components of both triode region and saturation region, hence thereby charge neutrality is followed. All evaluated charge components associated with the saturation region is added to their respective trioderegion components to give the total charge associated with the terminal, as follows: ,(A8) ,(A9) ,,(A10) .(A11) Q Gf sat W g C oxf V GfS F GfB f 0 0 y ()Df y () [] ydL gch L g= Q ch sat W g Q ch y () yd0 L g= W g L g L gch () Q ch L gch () @ Q Gf Q Gf L g V DSeff () () Q Gf sat + = Q Sch () Q Sch () L g V DSeff () () Q Sch () sat + = Q Dch () Q Dch () L g V DSeff () () Q Dch () sat Q Ddep () ++ = Q Gb Q Gf Q Sch () Q Dch () Q B +++ () = PAGE 93 93 A3 WeakInversion Inner Fringe Charge Model UFDGsbasicfringecapacitancemodel[29]isbasedonthesolutionofLaplaceequation between two conducting plates separated by an angle. For example, UFDG calculates the innerfringecapacitancebetweensourceandthegatebyassumingsourceandgatetobetwoconducting plates,andsolvingtheLaplaceequationbetweenthetwointheweakinversionregion.However, in nanoscale DG MOSFETs, the electricelds originating from the depletion charge in the drain can signicantly inuence the solution of Laplaces equation between the source and the gate. This inadequacy in the innerfringe capacitance model was identied by the VDSdependent nonphysical dip in the UFDGpredicted CGVGS characteristics in the moderateinversion region. UFDG xes this inadequacy by quasiphysically assigning a depletion charge to the drain, and imaging it in the gate. This draindepletion charge is modeled as, .(A12) Thedraindepletionchargein(A12)isimagedinthefrontandbackgateequally.Qifisa tuning parameter, and Leff is the effective channel length of the MOSFET [26] in the weakinversion region. This formalism effectively removes the dip in the CGVGS characteristics and signicantly improves the spline linking the weakand stronginversion region formalism. A4 DIBLDependent Denition of VTWInUFDG,anovelcubicsplineintermsofboththefrontandbackgatebiasisusedtolink the rigorous weakand stronginversion formalism. For physicsbased compact modeling, the MOSFET IDSVGS characteristics are generally partitioned into four regions of operation: accumulation, weak inversion, moderate inversion, and strong inversion. This division of the IDSVGS characteristics facilitates developing rigorous analytical models based on approximations valid only in the given region. Because both the 2D effects and the inversion carrier density are Q Ddep () if Q if W g e Si t Si V DS L eff = PAGE 94 94 important in the moderateinversion region, analytical modeling of this region is formidable. Hence, in general, it is modeled via smoothing functions or a polynomial spline that link the rigorous weakand stronginversion region formalisms. For a polynomial spline, one needs to know the gate voltages at the boundaries of the moderateinversion region, and IDS and gm at those gate voltages. For classical devices, Tsividis quantitatively characterized the noted boundaries of the moderateinversion region in terms of the inversion capacitance, depletion capacitance, and the gateoxide capacitance. It is based on the exponential dependence of the inversion charge on the gate bias for the weakinversion region, and on the linear dependence for the stronginversion region. In UFDG we modify this characterization for the nonclassical devices. The gate bias at the boundary corresponding to the weak inversion (VTW) and strong inversion (VTS), must always be evaluated rst in order to determine which region of operation a given gate bias corresponds to. In UFDG we model boundaries of the moderateinversion region byequatingtwoexpressionoftheinversionregionchargedensityattheboundaries.Therstone is dened by the (1D) Gausss law in the intrinsic body, and the second expression is an approximationbasedonthelinearpotentialdistributiongivenbythespatiallyconstanttransverse electric eld for the undoped body/channel. However, we have discovered that for nanoscale DG MOSFETs, 1D analysis does not adequately characterizes the inversioncharge density in the channel, and DIBL must be accounted for in the model. TomodelDIBL[45],wewrite f (x,y)= f0(x,y)+ Df (x,y),where f0(x,y)isthesolution of the potential with VDS = 0, and Df (x, y) is the perturbation in the potential due to drain bias, which, for weak inversion, with undoped body, satises .(A13) x 2 2 Df xy (,) y 2 2 Df xy (,) +0 = PAGE 95 95 We separate the two partial derivatives assuming, ,(A14) where h0 is a spatial constant. Then, integrating twice along the channel, with the boundary conditions Df (y = 0) = 0 and Df (y = Leff) = VDS yields h0 = 2VDS/Leff 2, where Leff is the effectivechannellengthofthedevicethatgovernsthe2DeffectsintheUTB,andthatisdened by the source/drain doping prole. Then by integrating (A14) twice along the lm we obtain, ,(A15) and, ,(A16) where Df(sf)and Df(sb)aretheperturbationsoftheminimumsurfacepotentials(iny)atthefront and back surfaces. In UFDG we account for DIBL in the denition of VTW by perturbing Df (0) by(A15)and(A16).NotethatSCEstendtosubsideatthemoderate/stronginversionboundary duetostrongtransverseelectriceld.Therefore,modelforevaluationofVTSdoesnotneedstobe altered. x 2 2 Df xy (,) y 2 2 Df xy (,) h 0 == Df sb () C b C ob C b + Df sf () 1 C ob C b + e Si t Si h 0 2 + = Df sf () C ob2C b+C b C ofCob+ CobCof+ e Si t Si h 0 2 = PAGE 96 96 LIST OF REFERENCES [1]International Technology Roadmap for Semiconductors, Semiconductor Industry Association, Austin, TX, 2005. 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Tech. Dig., pp. 2733, 2003. [53]C.Shin etal. ,SRAMYieldenhancementwithThinBOXFDSOI IEEESOIConf. Tech. Dig., pp. 3738, 2003. PAGE 100 100 BIOGRAPHICAL SKETCH Siddharth Chouksey was born in Betul, India in 1983. He received the Bachelor of Technology in information and communication technology from Dhirubhai Ambani Institute of InformationandCommunicationTechnology(DAIICT),Gandhinagar,Indiain2005.Hedidhis Doctor of Philosophy in electrical and computer engineering at the University of Florida, Gainesville. His research interest concerns device theory, modeling and design of nonclassical silicononinsulator (SOI) and multigate MOSFET, for both digital and analog applications. In summer of 2008 and 2009, he interned in the Components Research Group at Intel, Hillsboro, OR,wherehewasactivelyinvolvedinthedesignofnovelnanoscaleoatingbodymemorycells. 