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Modeling, Design, and Performance of Double-Gate CMOS

Permanent Link: http://ufdc.ufl.edu/UFE0041075/00001

Material Information

Title: Modeling, Design, and Performance of Double-Gate CMOS
Physical Description: 1 online resource (100 p.)
Language: english
Creator: Chouksey, Siddharth
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: dibl, dice, performance, scalability
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: MODELING, DESIGN, AND PERFORMANCE OF NANOSCALE DOUBLE-GATE CMOS This dissertation seeks to understand the unique physics of, to explore non-conventional ways of designing, and to gain insights on the performance of nanoscale double-gate (DG) MOSFETs, particularly the quasi-planar FinFET structure. Our work includes modeling of drain-induced charge enhancement, suggesting a novel way of adjusting the threshold voltage of nanoscale DG MOSFETs via limited source/drain dopants in the channel, comparing the analog/RF performance of DG FinFETs and bulk-silicon MOSFETs, and studying and designing ultra-thin-BOX FD/SOI MOSFETs with comparisons to DG FinFETs. Drain-induced charge enhancement (DICE) is a short-channel effect which is unique to nanoscale DG MOSFETs with undoped bodies because of their signi?cantly high carrier mobility. We model this effect, and study its effect on the current, charge, capacitance, and transcapacitance of DG MOSFETs. We ?nd that DICE is a bene?cial effect because it increases current without signi?cantly affecting gate capacitance. Adjusting the threshold voltage of DGMOSFETs with undoped bodies for low-power and high performance applications is a challenging task. We propose a design approach in which limited densities of source/drain dopants in the channel can be used to effect an adjustment of threshold voltage in DG MOSFETs, while maintaining low sensitivities to random-doping ?uctuations. Most of the current literature on the analog/RF performance of DGMOSFETs is based on experimental results, with little physics-based explanation of the results. We give physical insights on the design and performance of DG MOSFETs for analog/RF applications, and compare them with bulk-silicon MOSFETs. We ?nd that like for digital applications, DG MOSFETs have superior analog performance than that of conventional planar bulk-silicon MOSFETs. Recently, there has emerged a considerable interest in planar FD/SOI MOSFETs with ultra-thin BOX. We give our physical insights, based on device simulations, on the design and performance of ultra-thin-BOX FD/SOI MOSFETs, and check their scalability toward the end of the CMOS roadmap compared with DG FinFETs.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Siddharth Chouksey.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Fossum, Jerry G.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0041075:00001

Permanent Link: http://ufdc.ufl.edu/UFE0041075/00001

Material Information

Title: Modeling, Design, and Performance of Double-Gate CMOS
Physical Description: 1 online resource (100 p.)
Language: english
Creator: Chouksey, Siddharth
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: dibl, dice, performance, scalability
Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: MODELING, DESIGN, AND PERFORMANCE OF NANOSCALE DOUBLE-GATE CMOS This dissertation seeks to understand the unique physics of, to explore non-conventional ways of designing, and to gain insights on the performance of nanoscale double-gate (DG) MOSFETs, particularly the quasi-planar FinFET structure. Our work includes modeling of drain-induced charge enhancement, suggesting a novel way of adjusting the threshold voltage of nanoscale DG MOSFETs via limited source/drain dopants in the channel, comparing the analog/RF performance of DG FinFETs and bulk-silicon MOSFETs, and studying and designing ultra-thin-BOX FD/SOI MOSFETs with comparisons to DG FinFETs. Drain-induced charge enhancement (DICE) is a short-channel effect which is unique to nanoscale DG MOSFETs with undoped bodies because of their signi?cantly high carrier mobility. We model this effect, and study its effect on the current, charge, capacitance, and transcapacitance of DG MOSFETs. We ?nd that DICE is a bene?cial effect because it increases current without signi?cantly affecting gate capacitance. Adjusting the threshold voltage of DGMOSFETs with undoped bodies for low-power and high performance applications is a challenging task. We propose a design approach in which limited densities of source/drain dopants in the channel can be used to effect an adjustment of threshold voltage in DG MOSFETs, while maintaining low sensitivities to random-doping ?uctuations. Most of the current literature on the analog/RF performance of DGMOSFETs is based on experimental results, with little physics-based explanation of the results. We give physical insights on the design and performance of DG MOSFETs for analog/RF applications, and compare them with bulk-silicon MOSFETs. We ?nd that like for digital applications, DG MOSFETs have superior analog performance than that of conventional planar bulk-silicon MOSFETs. Recently, there has emerged a considerable interest in planar FD/SOI MOSFETs with ultra-thin BOX. We give our physical insights, based on device simulations, on the design and performance of ultra-thin-BOX FD/SOI MOSFETs, and check their scalability toward the end of the CMOS roadmap compared with DG FinFETs.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Siddharth Chouksey.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Fossum, Jerry G.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0041075:00001


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1 MODELING, DESIGN, AND PERFORMANCE OF NANOSCALE DOUBLE-GATE CMOS By SIDDHARTH CHOUKSEY A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2009

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2 2009 Siddharth Chouksey

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3 To my family, friends, and the almighty

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4 ACKNOWLEDGEMENTS Being where I am today is literally a dream come true. I believe success happens when talent meets an opportunity. Numerous opportunities came my way, many times indirectly and disguised,thatmadeallthispossible.Idonotknowwhatmadethoseopportunitiescomemyway, if not, the supreme force guiding our lives God. Therefore, rst of all I would like to thank God formakingthisPh.D.apartofhisplan.Idonotthinkitswithinmycapabilitytofullyexpressmy senseofaweandgratitudetowardmyadvisor,Dr.JerryG.Fossum.Workingwithhimhasbeena tremendous learning experience from me. He taught me not only through the classes, feedbacks, and discussions, but many times when he was not even intending! I have learned a lot just by watchinghimwork;hisenthusiasmforwork,patience,andanalyticalskillsareexemplary.Ithank Dr. Fossum for his support and guidance throughout my work. I would like to thank Dr. Scott Thompson, Dr. Jing Guo, and Dr. Selman Hersheld for agreeing to be on my committee as well as for helpful discussions during my research work. I would like to acknowledge Freescale Semiconductor for their support, and thank Intel Corp. for giving me opportunity to intern with them twice. I would like to thank my mother for her undiminished condence in me, and for all her prayers. I will not be surprised if this Ph.D. means more to her than what it means to me. I wouldliketothankmyfatherforhissupport,andmybrother,sister-in-law,sister,brother-in-law, my niece and nephew for their encouragement. I was fortunate to have Murshed Chowdhury, Shishir Agrawal, Zhichao Lu, Zhenming Zhou, Weimin Zhang, Sueng-Hwan Kim, and Dabraj Sarkar as my colleagues. I would like to thank them for all the help they extended to me throughout my work. I would like to thank my numerous friends, in and out of Gainesville, for their companionship through these years.

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5 TABLE OF CONTENTS page ACKNOWLEDGEMENTS............................................................................................................4 LIST OF TABLES................................................................................................................ ..........7 LIST OF FIGURES............................................................................................................... .........8 LIST OF ABBREVIATIONS.......................................................................................................10 ABSTRACT...................................................................................................................... ............11 CHAPTER 1 INTRODUCTION..............................................................................................................1 3 2 DICE: A BENEFICIAL SHORT-CHANNEL EFFECT IN DOUBLE-GATE MOSFETs........................................................................................................................ .... 18 2-1 Introduction............................................................................................................... ..18 2-2 Modeling................................................................................................................... ...18 2-3 Model Corroboration and Predicted DICE Impacts....................................................23 2-4 Summary.................................................................................................................... ..26 3 THRESHOLD VOLTAGE ADJUSTMENT IN NANOSCALE DG FINFETS VIA LIMITED SOURCE/DRAIN DOPANTS IN THE CHANNEL..........................................38 3-1 Introduction............................................................................................................... ..38 3-2 S/D Doping-Dependent Vt...........................................................................................39 3-3 Demonstration and Verication of Design Approach..................................................42 3-4 Sensitivity and RDF Analyses.....................................................................................43 3-5 Summary.................................................................................................................... ..45 4 PHYSICAL INSIGHTS ON ANALOG/RF PERFORMANCE OF DOUBLE-GATE FINFETS, WITH COMPARISION TO BULK-SILICON MOSFETS................................51 4-1 Introduction............................................................................................................... ..51 4-2 Device Characteristics.................................................................................................52 4-3 RF FinFET Scaling......................................................................................................57 4-4 Summary.................................................................................................................... ..60 5 INSIGHTS ON DESIGN AND SCALABILITY OF THIN-BOX FD/SOI CMOS............68 5-1 Introduction............................................................................................................... .....68 5-2 LP Devices................................................................................................................. .....69

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6 5-3 HP Devices................................................................................................................. ....74 5-4 Comparisons with FinFETs............................................................................................76 5-5 Conclusions................................................................................................................ ....78 6 SUMMARY AND FUTURE WORK..................................................................................87 6-1 Summary.................................................................................................................... .....87 6-2 Future Work................................................................................................................ ....89 APPENDIX UFDG MODEL REFINEMENTS.......................................................................................90 A-1 Introduction............................................................................................................... .....90 A-2 Strong-Inversion Intrinsic Charge Modeling.................................................................90 A-3 Weak-Inversion Inner Fringe Charge Model.................................................................93 A-4 DIBL-Dependent Denition of VTW............................................................................93 LIST OF REFERENCES............................................................................................................ ..96 BIOGRAPHICAL SKETCH......................................................................................................100

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7 LIST OF TABLES T able page 2-1UFDG-predictedDICEandDIBLinanLg=18nmnMOSFETwithvaryingUTB thickness, with and without a 2nm gate-source/drain underlap.........................................28 3-1Medici-predictedsensitivityofIofftovariationsin sLofNSD(y)intheLg=18nmLPand HP DG FinFETs................................................................................................................46 3-2Medici-predictedstandarddeviationofVtwandassociatedIoff-basedyieldduetotheRDF of NSD(x,y) in the Lg = 18nm LP and HP DG FinFETs...................................................46 4-1ComparisonofUFDG-predictedfTofanLg=28nmDGFinFEThavingaG-S/Doverlap, withthatofFinFETshavingG-S/Dunderlapoptimizedforlow-powerandhigh-frequency RF applications................................................................................................................ ..61 5-1Taurus-predicted characteristics of Lg = 25nm (= Leff) FD/SOI nMOSFETs with midgap gate and tSi = 6nm..............................................................................................................80 5-2Taurus-predicted characteristics, vs. tSi, of Lg = 25nm thin-BOX/GP nMOSFETs with 2.5nm G-S/D underlap and midgap gate............................................................................80 5-3Taurus-predicted characteristics, vs. VGP, of Lg = 25nm thin-BOX/GP nMOSFETs with 2.5nm G-S/D underlap and midgap gate............................................................................81 5-4Taurus-predicted characteristics, vs. Leff, of thin-BOX/GP nMOSFETs with VGP for strong accumulation and controlled DIBL.........................................................................81 5-5Taurus-predicted characteristics, vs. Leff, of thin-BOX/GP nMOSFETs with VGP for strong accumulation...........................................................................................................8 2 5-6Taurus-predicted LP and HP scaling limits dened by tSi = 5nm, for thin-BOX/GP MOSFETs and DG nFinFETs............................................................................................82

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8 LIST OF FIGURES Figure page 1-1StructureofaFinFETwithgatewrappedovertheverticalfin,formingtwosidewallgates. ............................................................................................................................... .............17 2-1Results of calibrating UFDG to an undoped Lg = 60nm DG pFinFET (fin aspect ratio hSi/ tSi = 100nm/17nm), with and without DICE.....................................................................29 2-2IllustrationofaDGMOSFETbiasedinthesaturationregion,showingthebody/channel divided into a gradual channel and a high-field portion....................................................30 2-3UFDG-predictedgradual-channellength,relativetoLg=18nm,versusdrainvoltagefora DG nMOSFET, with and without DICE............................................................................31 2-4Medici-predictedinversion-electrondensityacrosstheUTBatthevirtualsourceofa simple 18nm DG nMOSFET for low and high drain voltages..........................................32 2-5UFDG-predicteddraincurrentversusvoltagecharacteristics,withandwithoutDICE,of an 18nm DG nMOSFET....................................................................................................33 2-6UFDG-andMEDICI-predicteddraincurrentversusvoltagecharacteristicsofthe18nm DG nMOSFET...................................................................................................................34 2-7UFDG-predicteddraincurrentversusvoltagecharacteristics,withandwithoutDICE,for the18nmDGnMOSFET,butwiththeproperseriesresistance,mobility,andvelocityovershoot modeling............................................................................................................3 5 2-8UFDG-predictedgatecapacitanceversusvoltagecharacteristicsofthe18nmDG nMOSFET at low and high drain voltages, with and without DICE.................................36 2-9UFDG/Spice3-predictedoutputvoltagetransientofatwo-stage18nmDGCMOSinverter chain,withtheinputvoltagepulsingshowntorevealthe(pull-downpluspull-up) propagation delay.............................................................................................................. .37 3-1S/D-extensionlateraldopingprolesinanundopedDGFinFET,showingvariable encroachment into the channel.......................................................................................... 47 3-2Measured(a)strong-inversionand(b)subthresholdcurrent-voltagecharacteristicsoftwo Lg=70nmundopedDGnFinFETs,whichhavedifferentNSD(y)duetovariationsintheS/ D processing................................................................................................................... ....48 3-3UFDG-predicted (a) subthreshold and (b) strong-inversion current-voltage characteristics of the 18nm LP and HP DG FinFETs................................................................................49

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9 3-4TheDGFinFETstructureshowinghowtheS/D-extensionandchannelregionswere partitioned to account for the RDF of NSD(x,y) in the Medici domain.............................50 4-1UFDG-predicted gDS of a 28nm DG FinFET....................................................................62 4-2UFDG-predictedCG(normalizedtohSi)versusVGSatVDS=1.2V,withandwithoutG-S/ D underlap..................................................................................................................... .....63 4-3UFDG-predicted gm versus Lg of DG FinFETs with an abrupt S/D doping profile.........64 4-4UFDF-predictedgDSversusLgfortheFinFETs,withandwithoutconsiderationofquasiballistic limit................................................................................................................ ......65 4-5UFDG-predicted Avo versus Lg of DG FinFETs...............................................................66 4-6UFDG-predicted fT versus Lg of DG FinFETs..................................................................67 5-1Basic thin-BOX FD/SOI nMOSFET structure, with P+ GP..............................................83 5-2Taurus-predictedweak-inversioncharacteristicsofathin-BOXdevicealongwithUFDG calibration.................................................................................................................... ......84 5-3ComparisonofTaurus-predictedIDS-VGScharacteristicsofthin-BOXFD/SOIdevicesw/ and w/o GP..................................................................................................................... ....85 5-4ComparisonofTaurus-predictedIDS-VGScharacteristicsofthin-BOXFD/SOInMOSFET with that of DG nFinFET...................................................................................................86

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10 LIST OF ABBREVIATIONS MOSFETMetal-Oxide-Semiconductor Field-Effect Transistor CMOSComplementary MOS SOISilicon-on-Insulator FDFully Depleted PDPartially Depleted UTBUltra-Thin Body UFDGUniversity of Florida Double-Gate SCEShort-Channel Effect DIBLDrain-Induced Barrier Lowering DICEDrain-Induced Charge Enhancement QMQuantum-Mechanical SDESource/Drain Extension SGSingle Gate SSubthreshold Slope RFRadio Frequency TBOXThin Back Oxide GPGround Plane LPLow Power HPHigh Performance

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11 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulllment of the Requirements for the Degree of Doctor of Philosophy MODELING, DESIGN, AND PERFORMANCE OF NANOSCALE DOUBLE-GATE CMOS By Siddharth Chouksey December 2009 Chair: Jerry G. Fossum Major: Electrical and Computer Engineering This dissertation seeks to understand the unique physics of, to explore non-conventional ways of designing, and to gain insights on the performance of nanoscale double-gate (DG) MOSFETs, particularly the quasi-planar FinFET structure. Our work includes modeling of draininduced charge enhancement, suggesting a novel way of adjusting the threshold voltage of nanoscale DG MOSFETs via limited source/drain dopants in the channel, comparing the analog/ RF performance of DG FinFETs and bulk-silicon MOSFETs, and studying and designing ultrathin-BOX FD/SOI MOSFETs with comparisons to DG FinFETs. Drain-induced charge enhancement (DICE) is a short-channel effect which is unique to nanoscaleDGMOSFETswithundopedbodiesbecauseoftheirsignicantlyhighcarriermobility. Wemodelthiseffect,andstudyitseffectonthecurrent,charge,capacitance,andtranscapacitance of DG MOSFETs. We nd that DICE is a benecial effect because it increases current without signicantly affecting gate capacitance. AdjustingthethresholdvoltageofDGMOSFETswithundopedbodiesforlow-powerand high-performance applications is a challenging task. We propose a design approach in which limited densities of source/drain dopants in the channel can be used to effect an adjustment of

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12 threshold voltage in DG MOSFETs, while maintaining low sensitivities to random-doping uctuations. Mostofthecurrentliteratureontheanalog/RFperformanceofDGMOSFETsisbasedon experimentalresults,withlittlephysics-basedexplanationoftheresults.Wegivephysicalinsights on the design and performance of DG MOSFETs for analog/RF applications, and compare them with bulk-silicon MOSFETs. We nd that like for digital applications, DG MOSFETs have superior analog performance than that of conventional planar bulk-silicon MOSFETs. Recently, there has emerged a considerable interest in planar FD/SOI MOSFETs with ultra-thin BOX. We give our physical insights, based on device simulations, on the design and performance of ultra-thin-BOX FD/SOI MOSFETs, and check their scalability toward the end of the CMOS roadmap compared with DG FinFETs.

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13 CHAPTER 1 INTRODUCTION Scaling conventional MOSFETs, i.e., bulk-silicon and partially depleted (PD)/SOI MOSFETs, to gate lengths (Lg) < ~40nm has become increasingly challenging because the channel-dopingdensityrequiredhasbecomeveryhigh.ConventionalMOSFETsrelyonchanneldoping density to control threshold voltage (Vt) and short-channel effects (SCEs). As these devicesarescaled,thelatterarecontrolledbyreducingthedepletionwidthbyincreasingchanneldopingdensity.ForLg<~40nm,therequiredchannel-dopingdensityhasbecomesohighthatthe variationinVtduetorandomvariationsinthechannel-dopingdensityhasbecomeaseriousissue. At such short Lg, reliable control of channel doping density is virtually impossible. Under this scenario, double-gate (DG) MOSFETs, e.g. FinFETs, have emerged as a most promising candidate to replace the bulk-Si MOSFET [1]. The primary advantage of the FinFET is the excellent control of SCEs [2] without relying on channel doping, which makes it potentially scalable to the end of the SIA ITRS roadmap [1]. Since FinFETs rely on undoped ultra-thin bodies (UTB) to control SCEs, random variations in threshold voltage (Vt) and other device characteristics due to process variations can be greatly reduced [3]. In Fig. 1.1 we show the basic structure of a FinFET. The gate is wrapped over the thin vertical n, forming two sidewall gates. The top of the n could be gated, forming a triple-gate device [4], but we focus on the DG structure which is more pragmatic [2]. DG-FinFET technology has not yet received complete acceptance by the integratedcircuits manufacturing companies because of some of the challenges associated with the DGFinFET technology like higher cost of SOI wafers, control of the nanoscale n, and lack of reliablewaysofengineeringthesource/draindopingprole.HighercostofSOIwafershasledto some interest in the bulk-Si FinFETs [5], [6]. However, due to signicantly high, controlled

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14 substrate-doping density required to suppress source/drain-leakage current, and need to precisely match the depth of source and drain regions to the substrate doping, the viability of bulk-Si FinFETsisdoubtful[7].InordertoscaleDGFinFETstotheendoftheroadmap,reliablewaysof engineering the source/drain prole will have to be developed. This task is particularly challenging because the UTB thickness tends to be about 5nm near the scaling limit of Lg. The diffusion of source/drain dopants through such thin bodies is not well understood. As we will show through comprehensive studies in this dissertation, DG FinFETs tend to have signicantly better performance for both digital and analog/RF applications. But, in order for DG FinFETs to replacebulk-SiMOSFETs,thetechnologicalchallengeslikethosementionedherewillhavetobe overcome. ThephysicsofDGMOSFETs,withcoupledgatesandUTB,issignicantlydifferentfrom bulk-Si MOSFETs. Also, designing them for various applications is signicantly different from designing bulk-Si MOSFETs. Designing circuits with independently controlled bias on the two gates of DG MOSFETs [8], using the space between two ns on the Si substrate to enhance the drive current (ITFET [9]), and engineering the S/D extension region to realize a bias-dependent effective channel length (Leff) [2] are some of the unique possibilities that exist with DG MOSFETs.Therefore,needlesstosay,inordertorealizethefullpotentialofDGMOSFETs,their physicshastobebetterunderstood,andnon-conventionalwaysofdesigningthemwillhavetobe explored.Inthisdissertationwediscussourcontributionstowardsthesegoals.SinceDGFinFETs are most prospective among all the contemporary DG MOSFETs, we use them as the representative DG MOSFET structure in our studies, although most of the discussion in this dissertation is generically applicable to all kinds of DG MOSFET structures. InFinFETs,theundopedUTBbetweenthetwo(connected)gatesresultsinunusuallylow transverse electric eld and quite high carrier mobility ( meff) [10], [11]. This produces signicant

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15 saturation-region effects [12] that are not prevalent in the conventional devices, e.g., carriervelocity overshoot [13] and near-ballistic transport [11]. Drain-induced charge enhancement (DICE), which is a strong-inversion counterpart to the drain-induced barrier lowering (DIBL) in weakinversion,issuchaneffectthatheretoforehasnotbeengenerallyacknowledged.InChapter 2,thesignicanceofDICEinDGMOSFETsisrevealedviaanalyticalmodeling,implementedin our physics-based compact model UFDG [14], [15], [16] and supported by numerical device simulations. Because of the undoped body, there is no pragmatic way of tuning Vt of DG MOSFETs forlow-power(LP)andhigh-performance(HP)applications.However,theundopedbodyenables the design of DG MOSFETs with G-S/D underlap. It has been shown that incorporating G-S/D underlap in the DG MOSFET design yields Leff that decreases with increasing gate bias (VGS), and that can hence be used to effect a design tradeoff between SCE control, or off-state current (Ioff) for LP applications, and S/D series resistance (RS/D), or on-state current (Ion) for HP applications [17]. In Chapter 3, we show how this Ioff-Ion design tradeoff can be extended by allowing limited densities of S/D dopants to diffuse into the FinFET channel for direct Vtadjustment in HP versus LP applications. While CMOS scaling is predominantly driven by digital applications, analog performance can benet from scaling [1]. For bulk-Si MOSFETs, for example, the transconductance (gm) increases with scaling. And, scaling is the primary way of improving the cut-off frequency [fT = gm/(2 p CG) where CG is the total gate capacitance] of analog devices. However, these benets come with a cost of enhanced SCEs that undermine the output conductance (gDS) and voltage gain (Avo = gm/gDS) of the bulk-Si MOSFETs. Therefore, there is considerable interest in exploring the possibility of using FinFETs, which have better Lg scalability than bulk-Si

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16 MOSFETs, for RF applications. In Chapter 4 we use our physical insights, supplemented with published numerical simulation and experimental results, to check the analog gures-of-merit (FOMs) of DG FinFETs, and compare them with those of bulk-Si MOSFETs. Recently, there has been a noticeable interest in the planar ultra-thin-box fully depleted (FD)/SOIMOSFET[18]asanalternativetotheconventionalbulk-SiMOSFET,andinlieuofthe quasi-planarFinFET.ThemotivationforthiskindofMOSFETarchitectureisthebettercontrolof SOI UTB thickness as compared to that of the n-UTB thickness, in addition to the close similaritiesofFD/SOIandPD/SOIprocessing.InChapter5,wedoathorough,simulation-based evalutation of ultra-thin-box FD/SOI CMOS, projecting LP and HP scaling limits and noting needed process complexities, with comparisons to FinFET CMOS. In Chapter 6 we conclude this dissertation with a summary and suggestions for future work. In Appendix A we describe the UFDG model renements done for more reliable predictions of nanoscale DG MOSFET characteristics, as discussed herein.

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17.Figure1-1.StructureofaFinFETwithgatewrappedovertheverticaln,forming two sidewall gates.

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18 CHAPTER 2 DICE: A BENEFICIAL SHORT-CHANNEL EFFECT IN DOUBLE-GATE MOSFETs 2-1 Introduction Drain-inducedbarrierlowering(DIBL)[19]isawell-publicizedSCEinscaledMOSFETs. In accord with the 2-D Poisson equation in the weakly inverted channel/body, high drain bias (VDS) lowers the potential barrier height at the virtual source, thereby allowing increased carrier diffusion from the source to the channel, causing higher Ioff, and lowering the (saturation) Vt. Drain-induced charge enhancement (DICE) is the counterpart effect in strong inversion, which wasanalyzedforclassicalSOIMOSFETsabout20yearsago[20]butwhichheretoforehasbeen insignificant.Workbasedonnumericalsimulationsofbulk-SiMOSFETspublishedin1980[21] revealed the effect, also showing it to be insignificant. However, we show in this chapter, and explain why, this is not the case for nanoscale DG MOSFETs, in which DICE can significantly benefit the drive, or saturation-region current (IDS(sat)) and CMOS speed, with little effect on the gate capacitance. 2-2 Modeling Calibrations of UFDG to fabricated nanoscale FinFETs, with undoped UTBs, have tended to give results like the IDS-VGS characteristics of an Lg = 60nm device [22] shown in Fig. 2.1. Note that the UFDG predictions agree well with the measured data, except for high VDS, i.e., in the saturation region where UFDG underpredicts IDS(sat) (by about 7% for this 60nm FinFET). We have inferred from such results, complemented by numerical device simulations, that DICE can signicantly affect the saturation-region current of nanoscale DG MOSFETs. The saturation region of the nanoscale MOSFET is characterized, as illustrated in Fig. 2.2, by a UTB/channel that can be divided into a gradual [19] portion (0 < y < Lgch) adjacent to the source and a high-electric eld (i.e., |Ey|) portion (Lgch < y < Lg) adjacent to the drain in which

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19 carrier velocity is saturated. (Below saturation, for VDS < VDS(sat), Lgch = Lg.) Actually, when velocity (v) overshoot occurs, v @ vsat(eff)> vsat in the high-|Ey| region, where vsat(eff) depends on the MOSFET bias (VGS > Vt and VDS > VDS(sat)) [13]. DICE is literally an enhancement of the channelinversion-chargedensity(Qch),whichincreasesIDS(sat)asweshowherein.Furthermore, it is signicant in dening Lgch and the MOSFET terminal charges, although CG is not affected much. Without DICE, the classical (2-D Gauss law-based) analysis [19], [20] of the high-|Ey| portion of the channel is erroneous, predicting a too short Lgchas we will show. We model DICE via an approximate solution of the 2-D Poisson equation in the rectangular UTB/gradual channel (see Fig. 2.2) of a generic undoped DG MOSFET. Previously, such an analysis was done [20] for single-gate devices based on the inversion charge-sheet approximation, neglecting bulk inversion. Here we account for two gates and bulk inversion, which is quite signicant in DG MOSFETs with undoped UTBs [23], making no assumption about the inversion-charge distribution in the body. Letting f0(x,y) be the potential in the undoped UTB/gradual channel for VDS = 0 under a strong-inversion condition (VGS > Vt), we note from Poissons equation that VDS > 0 denes f (x,y) = f0(x,y) + Df (x,y), where the perturbation Df (x,y) is related to the VDS-induced change in Qch: (2.1) where the integrations are done over the UTB thickness tSi. The rst integral (<0 for an nMOSFET) in (2.1) reects the pinch-off tendency, and, in the classical gradual-channel approximation [19], the second integral is assumed to be negligible. However, for nanoscale DG MOSFETs this assumption can be invalid, and the second integral can be signicant DICE ( D Qch DICE < 0 for an nMOSFET), as we characterize herein. D Q ch y ()e Si x 2 2 Df xy (,) xd0 t Si e Si y 2 2 Df xy (,) xd0 t Si =

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20 Numerical. simulations of DG MOSFETs done with Medici [24] reveal that (2.2) inthegradual-channelportionoftheUTB,where h isaspatialconstant;thatis,theVDS-induced perturbationintheelectriceldalongthechannelisnearlylineariny.Thisapproximationobtains because, for high meff, the electron velocity is close to being saturated, and hence not varying muchiny,andsotheaddedchargedensity,associatedwith,isnearlyconstant(for continuous current). Integrating (2.2) twice along Lgch, with boundary conditions Df (x, 0) = 0 (due to strong inversion) and Df (x, Lgch) = VDS(eff), yields h @ 2VDS(eff)/Lgch 2, where VDS(eff)( ~ VDS(sat)) is the effective bias at the end of the gradual channel. Using (2.2) in (2.1) then yields .(2.3) This simple, but physical model shows that DICE manifests as a nearly uniform enhancement of theinversion-chargedensityeverywherealongthegradualchannel,andinthehigh-|Ey|portionas well because of the velocity saturation. Both (2.2) and (2.3) are consistent with the empirical result derived from strong-inversion numerical simulations in [21] of a Vt shift linearly proportional to VDS. Extending the basic DG MOSFET analysis in UFDG [25] accordingly, we use (2.1) and (2.3) to express the total inversion-charge density along the channel as ,(2.4) where Qch0 is the VDS = 0 charge density; Coxf= eox/toxf and Coxb= eox/toxb are the frontand back-gate oxide capacitances. Prior to saturation, i.e., for VDS < VDS(sat) (=VDS(eff) at the onset of saturation), (2.3) and (2.4) still apply, but with VDS(eff) and Lgch replaced with VDS and Lg (assumed here to be the y 2 2 Df xy (,) h @ eSiD Ey() y D Q ch DICE e Si t Si 2 V DSeff () L gch 2 --------------------------- @ Q ch y () Q ch 0 C + oxf Df 0 y (,) C oxb Df t si y (,) + D Q ch DICE + =

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21 channel length as indicated in Fig. 2.2), respectively. For the UFDG DICE upgrade, affecting channelcurrentandterminalcharges,theexistingformalism[25]isrevised,inaccordwith(2.4), bysimplyreplacingQchwith(Qch+ D Qch DICE).(Inthemodelcode,becauseofuncertaintyinLgand tSi, we actually use ( DICE x D Qch DICE), where DICE is a tuning parameter that is typically @ 1.) Note that this revision alters the model characterization of the bias-dependent Lgch, which inuences the terminal charges (and device capacitances and transcapacitances) as well as the channel current. The UFDG model for channel current [25] is upgraded for DICE directly, using (2.4) and the altered characterization of Lgch. The impact of DICE on the terminal charge modeling (discussed in Appendix A-2) is a bit more involved since D Qch DICE and the new Lgchcharacterization affect the charge partitioning. The basic 2-D analysis [19], [25] of the high-|Ey| region that denes Lgch is extended to include the DICE charge. Application of the 2-D Gauss law yields a second-order differential equation for the VDS-induced perturbation of potential: ,(2.5) from which we get (2.6) where h conveys the DICE effect; lc = [ eSitSi/(Coxf + Coxb)]1/2 and Esat = 2vsat(eff)/ meff is |Ey(Lgch)| [25]. Evaluating (2.6) at y = Lg, where Df = VDS, yields following expression of Lgch. .(2.7) y 2 2 d d Df y () Df y () V DSeff () l c 2 --------------------------------------------h + = Df y () V DSeff () h l c 2 + l c E sat yL gch l c --------------------sinh h l c 2 yL gch l c --------------------cosh + = V DS V DSeff () h l c 2 + l c E sat L g L gch l c ------------------------sinh h l c 2 L g L gch l c ------------------------cosh + =

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22 Now, the component of front-gate charge dened by (2.6) is (2.8) FGfB is the gate-body work-function difference and Wg is the device width. The back-gate chargeisdenedsimilarly,andforasymmetricalDGdevice,QGb=QGf.NotethatEy(Lg),given by the derivative of (2.6) evaluated at y = Lg, denes, via Gausss law, a depletion-region component of the drain charge: (2.9) which includes charge linked to the gradual channel as well as the high-|Ey| portion. The upgraded charge model reects directly the charge neutrality, (2.10) (with the undoped-body charge QB = 0), where the source (QS) and drain (QD) charges include partitioned components of Qch in (2.4) integrated along the channel. All the terminal charge components, and the channel current, depend on Lgch, implied by (2.6), and on VDS(eff). The latter is obtained from the current analysis of the gradual channel [19], [25], upgraded with DICE, i.e., with Qch including D Qch DICEas in (2.4): .(2.11) UFDG solves (2.11) and the nonlinear expression for Lgch from (2.7) iteratively via NewtonRaphson, and then the current and the terminal charges are evaluated. Figure 2.3 shows Lgch vs. VDS predicted by UFDG for an 18nm DG nMOSFET, with and without the DICE upgrade. Note thatwithoutDICE,LgchissubstantivelyunderpredictedforhighVDS,whichresultsinerroneous current and terminal-charge predictions. Q Gf sat W g C oxf V GfS F GfBf 0 0 y ()Df y () [] ydL gch L g= Q Ddep () Wl c 2 C oxf C oxb + () E sat L g L gch l c ------------------------cosh h l c L g L gch l c ------------------------sinh + = Q Gf Q Gb Q S Q D +++0 = V DSeff () Q ch 0 () E sat L gch Q ch 0 () C of C ob + () E sat L gch ---------------------------------------------------------------------------------=

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23 The modied 2-D analysis of the high-|Ey| region, with D Qch DICE, changes all the terminal charges without DICE [20], [25] due to the perturbations in VDS(eff) and Lgch. These changes are only loosely coupled to the gate because VDS(eff) in (2.11) and Lgch given by (2.7) are weakly dependent on VGS. This implies that the gate capacitance (CG = dQG/dVGS) is nearly independent of DICE. Our analysis shows that a portion of drain-depletion charge is imaged in the gate via an inner fringe eld, and that the rest is imaged in the channel as the DICE charge ( D Qch DICEWgLg). Hence, the DICE charge in the channel is supported mainly by the drain. Indeed,DICEisverysignicantindeningalltheterminalchargesofnanoscaleDGMOSFETs, and is therefore important in predicting the various device capacitances and transcapacitances, as well as channel current. We demonstrate this signicance in the next section. OuranalysisalsoexplainstheemergingsignicanceofDICEinnanoscaleDGMOSFETs, and why it is negligible in conventional devices. The high mobility in the undoped channel of DGMOSFETs,whileloweringVDS(eff)in(2.3)and(2.11),decreasesLgchasgivenby(2.7).The latter effect is predominant in (2.3), making D Qch DICE in nanoscale DG MOSFETs signicant. Further, the high meff tends to yield signicant velocity overshoot (vsat(eff) > vsat), which renders DICE even more signicant by increasing VDS(sat), and thereby increasing VDS(eff) for a given Lgch. Our analysis also shows that Lgch scales faster than VDS(eff), and for well-tempered Lgscaling, Lgch scales faster than Lg, and hence faster than tSiand tox. Thus, D Qch DICE ,as modeled by (2.3), becomes more signicant with scaling. 2-3 Model Corroboration and Predicted DICE Impacts We include in Fig. 2.1 the UFDG-predicted current for the 60nm pFinFET with our DICE modeling incorporated. Note now the excellent match with the high-VDS measured data. To further verify the DICE model, which we have also noted to be consistent with [21], and to corroborate the signicance of DICE in nanoscale DG devices, we simulate a simplied Lg =

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24 18nm symmetrical DG nMOSFET with Medici [24], and compare the DICE predicted by it to that predicted by UFDG. Series resistance was kept low to avoid any discrepancy in the effective gate and drain biases due to possible disagreement in currents. And, since the physical modeling in Medici can differ from that in UFDG, additional simplications were made. In particular, we xed the low-|Ey| meff to be 300cm2/V-s (which is comparable to on-state electron mobilities measured in DG FinFETs [10], [11]) in both the simulations, and we turned off the velocityovershootmodels,i.e.,wesetvsat(eff)=107cm/s( @ vsat).Further,weinitiallylettSi=12nm(which is not thin enough for Lg = 18nm to adequately suppress the unwanted SCEs [26]) to avoid anomalously high n(x) for thin tSi that Medici predicts. Later we check devices with thinner tSi. Figure2.4showstheMedici-predictedvariationofinversion-electrondensityacrosstheUTB(tSi=12nm)atthevirtualsource(i.e.,where f isminimumalongy)forlow(50mV)andhigh(1.0V) drain biases, with VGS = 1.0V. Note the strong bulk inversion (which would be enhanced by quantization [27]). The VDS-induced enhancement in the areal density of inversion charge at the virtualsource,i.e.,DICE,reectedbyFig.2.4isabout20%.Figure2.5showstheenhancementin the VGS = 1.0V current due to DICE in the same device as predicted by UFDG. Because of the high meff,thehigh-VDScurrentisrestrainedbytheballisticlimit[11];thatis,thecurrent(perWg) isnearlyQch(0)timesthethermalinjectionvelocityatthevirtualsource.Hence,theenhancement in the current in Fig. 2.5 virtually reects D Qch DICE, which, indeed, is close to that predicted by MediciinFig.2.4atVDS=1.0V.Tofurthershowthenearequalityofthesesimulations,weshow inFig.2.6thecurrentpredictedbyUFDGforthesamedeviceasinFig.2.5,butwiththeballisticcurrent limit turned off, and compare it with that predicted by MEDICI, which does not account for the ballistic limit. Note that the predicted currents match very well. InFig.2.7weshowUFDG-predictedIDSvs.VDS,atVGS=1.0V,forthesymmetrical18nm DG nMOSFET (tSi = 12nm, toxf = toxb = 1.2nm, midgap gate), but now with the proper series

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25 resistance,andmobility[10],[11],velocity-overshoot[13],andquantization[27]modeling,with andwithoutDICE.ThecurrentatVDS=1.0Visenhanced24%byDICE(morethanthe @ 20%in Fig. 2.5 mainly because of the velocity overshoot), which is quite substantial because the current isattheballisticlimitandthusdirectlyreects D Qch DICE.Westressthatthecurrentenhancement due to DICE is smaller for devices in which the current is not ballistically limited (like the pFinFET in Fig. 2.1) because it would be undermined some by the increase in Lgch caused by DICE(seeFig.2.3).NotealsoinFig.2.7thatDICEismuchlesssignicantforVDS
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26 (2.3),impliedby(2.7)andillustratedinFig.2.3,isthemainreasonforthenitegDSduetoDICE. WenotethatforlowerVGS,gDSisaboutthesameasthat(withDICE)inFig.2.7since D Qch DICEin (2.3) is only weakly dependent on VGS. However, for moderate inversion (e.g., at typical operating points for low-power RF transistors today), gDS tends to be lower, controlled by channel-length modulation, as DIBL tends to preempt DICE. AsdiscussedinSec.2.2,thegatecapacitanceisnearlyindependentofDICE.Thisisshown by the UFDG-predicted CG(VGS) curves in Fig. 2.8 for the same 18nm DG nMOSFET at high andlowVDS,withandwithoutDICE.(TheUFDG-predictedCG(VGS)isingoodaccordwiththe Medici-predicted characteristic at low VDS. However, at high VDS there is some discrepancy, which we believe is due to non-physical dependences of carrier transport on high |Ey| used in Medici for weak inversion.) So, since DICE gives enhanced current without increased gate capacitance, should it yield faster CMOS? The answer is yes, as shown by the UFDG/Spice3predictedCMOSinverter-chaindelayrevealedinFig.2.9.With18nmDGMOSFETs,likethatin Figs. 2.7 and 2.8 (with the proper hole mobility [10] assumed for the pMOSFET), the average propagation delay per stage is reduced by about 18% by DICE (less than the 24% Ionenhancement in Fig. 2.7 because of the VDS dependence of the DICE benet, and because of second-order increases in drain capacitance and gate-drain transcapacitance due to DICE). 2-4 Summary Drain-induced charge enhancement, the strong-inversion counterpart to DIBL, has been modeled analytically, with numerical support, and shown to be a signicant short-channel effect in nanoscale DG MOSFETs. Further, it becomes more signicant with well-tempered scaling. DICE substantially increases the inversion-charge density, without affecting the gate capacitance signicantly since the added charge is supported mainly by the drain. It therefore is benecial to digital CMOS speed, as we demonstrated via UFDG/Spice3 simulations. However, it increases

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27 drain conductance, and hence could be problematic in analog applications, although it does subside in moderate inversion where todays low-power RF transistors operate. Our analysis further demonstrates that physical compact models for nanoscale DG MOSFETs should account for DICE to ensure valid terminal charge (and capacitance and transcapacitance) as well as current modeling.

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28 Table 2-1. UFDG-predicted DICE and DIBL in an Lg = 18nm nMOSFET with varying UTB thickness, with and without a 2nm gatesource/drain underlap. tSi (nm)DICE (%)DIBL (mV/V) DIBL (mV/V) w/ underlap 1224260150 1019180100 81511060

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29.Figure 2-1.Results of calibratingUFDG to an undoped Lg = 60nm DG pFinFET (fin aspect ratio hSi/tSi = 100nm/17nm) [22], with and without DICE. -1.2-1.0-0.8-0.6-0.4-0.2VGS [V] 0.00 0.02 0.04 0.06 0.08IDS [mA] Measured Data UFDG w/o DICE UFDG w/ DICE 0.0VDS = 1.2V 50mV0.09 0.07 0.05 0.03 0.01

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30.Figure 2-2. Illustration of a DG MOSFET biased in the saturation region, showing the body/channel divided into a gradual channel (Lgch) and a high-eld (|Ey|) portion (Lg Lgch). The effective channel length is assumed to equal the gate length here. S Gf Gb x LgchtoxftoxbtsiLgDy

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31.Figure2-3.UFDG-predictedgradual-channellength,relativetoLg=18nm,versus drain voltage for a DG nMOSFET, with and without DICE; tSi = 12nm, toxf = toxb = 1.2nm, midgap gate. 0.00.51.01.52.0VDS [V] 0.0 0.2 0.4 0.6 0.8 1.0Lgch / Lg UFDG w/o DICE UFDG w/ DICE VGS = 1.0V

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32.Figure 2-4. Medici-predicted inversion-electron density across the UTB at the virtualsourceofasimple18nmDGnMOSFETforlowandhighdrain voltages; tSi = 12nm, toxf = toxb = 1.2nm, midgap gate. The high VDSincreases the integrated electron density (in the bulk) by about 20%. 0.02.04.06.08.010.012.0x [nm] 101810191020n [cm-3] 50mV VDS = 1.0V VGS = 1.0V

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33.Figure 2-5. UFDG-predicted drain current versus voltage characteristics, with and without DICE, of an 18nm DG nMOSFET simplied to correspond to the Medici simulation of Fig. 2.4. At VDS = 1.0V, DICE increases the near-ballistic current by about 20%, in accord with the inversion-charge enhancement indicated in Fig. 2.4. 0.00.20.40.60.81.0VDS [V] 0.0 0.5 1.0 1.5 2.0IDS [mA/ m m] UFDG w/o DICE UFDG w/ DICE VGS = 1.0V

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34 0.00.20.40.60.81.0VDS [V] 0.0 1.0 2.0 3.0IDS [mA/ m m] MEDICI UFDG VGS = 1.0V Figure 2-6. UFDGand MEDICI-predicted drain current versus voltage characteristics of the 18nm DG nMOSFET of Figs. 2.4 and 2.5. The ballisticcurrentlimitwasturnedoffinUFDGtocorrespondtoMEDICI, which does not account for it.

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35.Figure 2-7. UFDG-predicted drain current versus voltage characteristics, with and without DICE, for the 18nm DG nMOSFET of Fig. 2.5, but with the properseriesresistance,mobility,andvelocity-overshootmodeling;tSi= 12nm, toxf = toxb = 1.2nm, midgap gate. At VDS = 1.0V, with VGS = 1.0V,DICEincreasesthenear-ballisticIDSby24%.Thepredicteddrain conductance, which is increased by DICE, is also shown. 0.00.20.40.60.81.01.2VDS [V] 0.0 0.5 1.0 1.5 2.0IDS [mA/ m m] UFDG w/ DICE UFDG w/o DICE 0.00.20.40.60.81.01.2 -1.0 0.0 1.0 2.0 3.0 4.0 5.0gDS [mS/ m m] VGS = 1.0V

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36.Figure 2-8.UFDG-predicted gate capacitance versus voltage characteristics of the 18nm DG nMOSFET of Fig. 2.7 at low and high drain voltages, with and without DICE. Note that not accounting for DICE results in a nonphysical dip (dCG/dVGS< 0) in moderate inversion. DICE effectively removesthisdipbyincreasingthestrong-inversiongatecharge(because of longer Lgch) without affecting CG (=dQG/dVGS) significantly. -0.20.00.20.40.60.81.01.21.41.61.82.0VGS [V] 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10CG [fF/ m m] UFDG w/ DICE UFDG w/o DICE 50mV VDS = 1.0V

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37.Figure 2-9. UFDG/Spice3-predicted output voltage transient of a two-stage 18nm DGCMOSinverterchain,withtheinputvoltagepulsingshowntoreveal the (pull-down plus pull-up) propagation delay; VDD = 1.0V. The DG MOSFETs were designed like that in Figs. 2.7 and 2.8; the output was loadedwithacapacitorwithvaluecomparabletothegatecapacitanceof the MOSFETs. 0.010.020.030.040.050.060.0 -0.5 0.0 0.5 1.0 1.5 w/o DICE w/ DICE t [ps] VinVout[V]

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38 CHAPTER 3 THRESHOLD VOLTAGE ADJUSTMENT IN NANOSCALE DG FINFETS VIA LIMITED SOURCE/DRAIN DOPANTS IN THE CHANNEL 3-1 Introduction AsmentionedinChapter1,fornanoscaleFinFETs,thefin-body/channelmustbeultra-thin, and hence must be left undoped to avoid random-doping effects on Vt. Adjusting Vt for different CMOS applications, i.e., LP and HP, is thus a design problem; varying Vt via near-midgap-gate work-functionengineeringhasnotbeenshowntobeaviableoption.Inthischapter,weproposea design approach in which S/D dopants are allowed to diffuse into the FinFET channel for Vtadjustment in HP versus LP applications. We demonstrate and verify, via simulations and measurement results, that such engineering of the lateral S/D doping profile [NSD(y)] can be controlled to reliably lower Vt in strong inversion (for higher Ion) while not affecting it significantly in weak inversion (for lower Ioff with negligible process-induced variations). We furthershow,viarigorousrandom-dopinganalyses,thattheeffectsofrandom-dopantfluctuations (RDF) are acceptable in such FinFET design. We have previously put forth the idea of pragmatic FinFET-CMOS design [2], which uses only one, near-midgap gate metal for the nMOS and pMOS devices and retains the (relatively thick) SiON gate dielectric. In this context, we showed that incorporating a G-S/D underlap can be used to effect an Ioff-Ion tradeoff via a Leff that decreases with increasing VGS [26]. We demonstrated this idea for nanoscale-FinFET SRAM design [17]. The new design approach proposedhereinaugmentstheutilityofS/DengineeringforG-S/Dunderlap[26],enablingwider Vt adjustment for different CMOS applications, and, unlike gate work-function engineering, allowing independent adjustment of Vt for Ioff and Ion.

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39 3-2 S/D Doping-Dependent VtTheviabilityofourproposeddesignforVtadjustmentstemsfromthedependenceofVton the distribution of S/D dopants in the UTB/channel, which we rst analyze. Possible doping proles, assumed to be gaussian {NSD(y) = N0exp[-(y+Lext)2/ sL 2] where N0 is the density at the S/D end of the S/D extension and sL is the lateral straggle}, are illustrated in Fig. 3.1. For weak inversion,thecurrentisdeterminedbydiffusionofcarriersinaportionofthechanneloverwhich the electric potential is relatively invariant in y, and the threshold voltage (Vtw) is dened at the point of minimum potential [19] within this region. Because of negligible longitudinal (in y) electric eld in this region, Vtw can be expressed based on a 1-D (in x) analysis. For an undoped (negligible acceptor dopants) n-channel DG FinFET with a midgap gate, ,(3.1) where fcisthecharacteristicsurfacepotentialatthreshold( @ 0.4V)[3]and D Vt DIBLrepresentsthe reductioninVtwduetoDIBL[19];tSiisthesilicon-nthicknessandCox= eox/tox.TheNSDterm in(3.1)denesthereductioninVtwduetoS/D-donordepletioncharge(assumedtobeuniformin x) in the channel. This term is dened at y = Lg/2 because, in nanoscale FinFETs, the noted diffusion-current region is short and located near the center of the channel [19]. Note then that NSD(Lg/2) is most critical in dening Vtw, and Ioff. For nanoscale FinFETs, we note that the depletion-chargetermwilltypicallybenegligibleunlessNSD(Lg/2)>~1018cm-3[3].Wealsonote thatNSDawayfromthecenterofthechannelcanalsoaffectIoffbyperturbingthesolutionofthe 2-DPoissonequationintheUTB,whichdenes D Vt DIBL[19].However,thisperturbation,which increases D Vt DIBL due to more encroachment of the S/D electric eld, is typically small when NSD(Lg/2) < 1018cm-3. We have neglected the Vtw increase due to quantization; this increase is small in symmetrical undoped DG MOSFETs for tSi > 4nm [28]. V tw f @ c qN SD L g 2 () t Si 2 C ox ----------------------------------------D V t DIBL

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40 Forstronginversion,thecurrentisdriftandisdeterminedbytheaverageconductivityofthe (gradual) channel. The (aerial) inversion-charge density (Qch is magnitude) in the channel, with NSD(y), can be expressed as [19] (3.2) where Qch0 = 2Cox(VGS fs) is the inversion-charge density at the (virtual) source for NSD = 0, with fs being the surface potential ( >fc due to nite inversion-layer capacitance) there, Df is the VDS-inducedperturbationinthepotentialalongthechannel,and D Qch DICEistheenhancementin theinversion-chargedensityduetoDICE.NotethatQchincreaseslinearlywithNSD.Thecurrent is dened by integrating (3.2) along the gradual channel (Lch) [19], and it is increased by NSDaccordingly. Based on the integration, Qch0 is effectively increased to (Qch0+ q NSDtSi), where (3.3) istheaveragedensityofS/Ddopantsinthegradualchannel.The(extrapolated)thresholdvoltage (Vts) can hence be dened by ,(3.4) or ,(3.5) where D Vt DICE represents the reduction in Vts due to DICE. Note that Lch depends on both VDSand VGS, and hence so do NSD and Vts. Note how Vtw in (3.1) [where Ioff exp(-qVtw/kT)] and Vts in (3.5) [where Ion (VGS Vts)] differ. For weak inversion, D Vt DIBL is signicant, and Vtw is lowered by the depletionQ ch y () Q ch 0 2 C ox Df y () qN SD y () t Si D Q ch DICE ++ = N SD 1 L ch --------N SD y () y d 0 L ch= Q ch 0 qN SD t Si +2 C ox V GS V ts () @ V ts f @ s qN SD t Si 2 C ox ---------------------- D V t DICE

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41 charge term near the center of the channel where the carrier transport is predominantly diffusion [19].Thus,NSD(y~Lg/2)mustbedesignedtobelessthan~1018cm-3toavoidexcessiverandomdoping effects on Ioff. For strong inversion, D Vt DIBL is small because of the large transverse electric eld [2], however D Vt DICE could be signicant, and Vts is lowered by the integrated depletion charge. Thus, if NSD is greater than ~1018cm-3, and NSD(y ~ Lg/2) is negligible as noted, then Ion can be enhanced by a lowered Vts, and Ioff and Vtw will not be affected signicantly, provided the noted D Vt DIBL(NSD) increase is limited (which may require an Ion-Ioffdesign tradeoff). The NSD(y) labeled HP in Fig. 3.1 is such a doping prole. The NSD(y) labeled LP in Fig. 3.1 shows negligible NSD everywhere in the channel, but yields a signicantly benecial G-S/D underlap. The underlap yields Leff > Lg in weak inversion, and thereby reduces the SCEs [26] and parasitic capacitance as well [29]. The essence of our S/D engineering-based design, including the extension for Vt adjustment, is thereby dened. We show in Fig. 3.2 measuredIDS-VGScharacteristicsoftwoLg=70nmDGFinFETshavingdifferentNSD(y).From our UFDG [16]-calibration results, we nd that the doping proles in devices 2J and 1G are like HP and LP proles, respectively, albeit nonoptimal since these devices were fabricated [22] withoutemphasisonS/Dengineering.Thedifferenceofthestrong-inversionVtsbetweenthetwo devices shown in Fig. 3.2(a), which is due to different NSD in the channels, is signicant. (Note that Vts can decrease with increasing VGSdue to the previously noted bias dependence of NSD in (3.3).) The Vtwvariation between the two devices in Fig. 3.2(b) ( @ 200mV) is due largely ( @ 100mV as inferred from the data) to different SCEs as dened by Leff. Note that the corresponding values of Ion and Ioff, interpreted based on our physical insights from (3.1)-(3.5), experimentallyconrmtheefcacyoftheproposedVtdesignapproachforrelativelylong(70nm) DG FinFETs. For shorter devices, the approach should still be valid as long as Lg is not short enough (<20nm as implied by UFDG projections [11]) such that Ion is limited by ballistic

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42 transport. For such short devices, Ioff will still be dened by Vtw in (3.1), and Ion will be dened by Qch(0) in (3.2) which will increase with NSD(0). Therefore, our proposed design approach is generally useful for future LP/HP applications of nanoscale DG FinFETs. (We would like to thank Shishir Agrawal, a Ph.D. student at the University Florida, for calibrating measured characteristics with UFDG.) 3-3 Demonstration and Verication of Design Approach WefurtherchecktheproposedS/DengineeringforLP(lowIoff)andHP(highIon)FinFETCMOS applications using our process/physics-based compact model for DG MOSFETs, UFDG (with physical modeling of carrier mobility, velocity overshoot, quasi-ballistic transport, and quantization)[16],linked[17]to2-DnumericaldevicesimulationsdonewithMedici[24].ForLg=18nm(HP45nmnode[1]),withamidgapgateandtox=1.0nm,weassumeLext=12nm,andan undoped UTB with tSi = 10nm for adequate SCE control. We dene NSD(y) with different straggle, as in Fig. 3.1, for an LP ( sL = 5.5nm, which yields weak-inversion Leff = 24nm and negligible NSD in the channel) and an HP ( sL = 8.5nm, which yields Leff = 18nm, NSD = 4x1018cm-3,andNSD(y~Lg/2)=5x1017cm-3)application.Weassumeanominal(doable[22])S/ DseriesresistanceRSD=100 W m m,and,fortheLPdesign,increaseitby D RSD=25 W m mdueto the underlap [17]. Fig. 3.3(a) shows UFDG-predicted subthreshold IDS-VGS characteristics of the two FinFETs, which reect a Vtw difference of @ 180mV (at 100nA/ m m/Lg). We stress that the lower VtwoftheHPdeviceisduemainlytotheshorterLeff(=Lg)andlargerSCEs.(A~20mVreduction in the HP Vtwcaused by NSD in the channel was ignored.) So, the longer Leff for the LP device yields the (1/300) x decrease in Ioff, relative to the HP device, evident in Fig. 3.3(a). (For the HP design,wedidnotaccountforthereductioninsubthresholdmobility[~ x (1/2.5)]duetoCoulomb scattering by the S/D dopants [10]; Ioff would thus be lowered accordingly, tending to offset the

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43 small increase due to the noted 20mV-lower Vtw.) UFDG-predicted strong-inversion IDS-VGScharacteristics(pernheight),atVDS=VDD=1.0V,oftheLPandHPDGnFinFETsareplotted inFig.3.3(b).NotethatVtsoftheHPdeviceisconsiderablylowerthanthatoftheLPdevice[by @ 100mV, as dened by NSD = 4x1018cm-3 in (3.5)]. The HP Ion in Fig. 3.3(b) is 29% higher than that of the LP device; about 20% of this increase is due to the lower Vts, and rest is due to the lowerRSD.(FortheHPdevice,weevaluated NSDatlowVDS,butwenotethatitsvalueatVDS= 1.0V could be lower due to reduction in Lch with increasing VDS. Due to uncertainty in Lch at VDS = 1.0V, NSD is difcult to evaluate accurately. However, we estimate that the worst-case enhancement in Ion due to the Vts lowering is about 15%.) To solidify the NSD(y)-based design approach,wealsoshowinFig.3.3theUFDG-predictedIDS-VGScharacteristicsoftheLPdevice with Lg increased to 28nm, as projected (for LSTP) in the SIA roadmap [1] for the 45nm node. The longer Lg yields an acceptable Ioff@ 10pA/ m m, more than four-orders of magnitude lower than that of the HP device. UFDG/Spice3-predicted RO delays for this LP and the HP design are 3.6psand1.9ps,respectively,atVDD=1.0V.ThedelayfortheHPdeviceatthesamebiaswithout Vts reduction is 2.4ps; the limited S/D doping in the channel reduces the HP delay by more than 20%. 3-4 Sensitivity and RDF Analyses ToabsolutelyconrmtheviabilityofourproposedVt-adjustmentdesign,wemustconsider sensitivitiestoprocessvariationsandRDFeffects.Fortheformer,wedidaMedici/UFDG-based analysis, results of which are shown in Table 3.1. We nd from the simulations that letting sLvary by +/-18% in both designs of Figs. 3.1 and 3.3 does not cause prohibitive variations in Ioff: 1.5 x /(1/1.3) x for LP and 80 x /(1/20) x for HP. And, sensitivity to variation in the local number of dopants is acceptable as well. The HP prole in Fig. 3.1 shows NSD(Lg/2) =5x1017cm-3, which impliesonly~1dopantnearthecenterofthechannel.Thisnumbercouldrandomlyincreaseto3,

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44 and the lowered Vtw, given by (3.1) with the implied NSD(y ~ Lg/2), would not prohibitively increaseIoff(<100 x ).(Theseweak-inversionresultsarevalid,butwehavefoundthatforundoped UTB devices with G-S/D underlap, Medici-predicted strong-inversion currents are not reliable due to inadequate UTB-transport modeling.) In Table 3.1 we also show the UFDG-predicted variationsinIon.ThevariationsinIonaremuchlowerthanthoseinIoffbecauseIonvarieslinearly with NSD as implied by (3.2), whereas Ioff is exponentially dependent on NSD. Also, Ion depends on NSD and not directly on NSD, and so the exact position of dopants in the channel is not important for Ion. ThemainconcernabouttheRDFsistheeffectonVtw[31]andIoff,asimpliedbyTable3.1. Therefore, we did a more detailed Medici-based study of the variations in Ioff due to RDFs. As illustrated in Fig. 3.4, we divided the S/D-extension and the channel/UTB regions via grids with equal spacings, and assumed for this analysis that the height of the n (width of the FinFET) is equal to the grid spacing (2nm as in [31]). For each lattice site in every cube thus formed, the probability of having a S/D dopant at that location is calculated based on the NSD(y)-dened dopingdensityatthatlocation,andthenasiliconatomordopantatomisrandomlyplacedatthat location, following the method described in [32]. The number of dopants randomly placed in the cube,dividedbythevolumeofthecube,denesthedopingdensityassignedtothecorresponding region in the Medici domain. Once the doping density is specied every where in the S/Dextension and channel regions, Ioff and Vtw are extracted from the Medici-predicted currentvoltage characteristics. The process is repeated a sufciently large number of times, and the variations are noted. Because of the large number of simulations used, the RDF along the actual height of the FinFET is implicitly accounted for [31], thereby enabling use of the noted (unrealistically) small n height and 2-D Medici simulations for computational efciency. (We wouldliketothankAskhanBehnam,aPh.D.studentattheUniversityofFlorida,forhelpingwith

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45 the above simulations.) Table 3.2 shows the predicted standard deviation of Vtw [ s( Vtw)], and device yield for 18nmLPandHPDGFinFETsbasedonacceptablevariationsinIoff(<100 x) .FortheHPdevice, the 95% yield indicates the viability of our design approach. The yield increases, and s( Vtw) decreases, as we limit the S/D dopants in the channel by decreasing sL. Insignicantly small s( Vtw) in the LP device implies negligible variations in Ioff, which is crucial for LP applications. NotethatsinceweconsideredtherandomvariationsofdopantsintheS/D-extensionregions,our simulation results in Table 3.2 account for the effect of variation in Leff as well. Based on our resultsinTables3.1and3.2then,weconcludethatRDFeffectsarevirtuallynonexistentintheLP design, and are adequately controlled in HP design when NSD(y~Lg/2) is limited as noted. 3-5 Summary An extended approach to nanoscale DG FinFET design for LP and HP nanoscale-CMOS applications via S/D engineering [i.e., control of NSD(y) for G-S/D underlap and Vt adjustment] wasproposed,anddemonstratedtobeviablebydevicemeasurementsandsimulations,including sensitivity and RDF-effects studies. The approach exploits the idea of allowing limited S/D dopants properly distributed in the channel for HP-Vt design. We demonstrated the design approachatthe45nmnode.ScalingLgto<10nm,asprojectedattheendoftheSIAroadmap[1], will require the lateral straggle of NSD(y) to be reduced by about a factor of two, which appears feasible with acceptable sensitivities via new processing such as laser annealing. However, additionalanalysesincludingquantizationeffects,mobilitydegradation,andballistictransportare called for. Our work extends the utility of S/D engineering in the design of nanoscale FinFETs, now for Vt adjustment as well as G-S/D underlap. But, additional work on S/D processing for control of NSD(y) in the thin-n extensions and channel is needed to effect this utility.

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46 Table3-1.Medici-predictedsensitivityofIofftovariationsin sL(+/ -18% of the nominal sL0 noted) of NSD(y) in the Lg = 18nm LP and HP DG FinFETs. sL+18%-18% LP ( sL0=5.5nm) 1.5 x (1/1.3) x HP ( sL0=8.5nm) 80 x (1/20) x Table 3-2. Medici-predicted standard deviation of Vtwand associated Ioff-based yield due to the RDF of NSD(x,y) in the Lg = 18nm LP and HP DG FinFETs. Application s (Vtw)Yield HP ( sL=8.5nm)100mV95% LP ( sL=5.5nm)18mV100%

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47 Figure 3-1.S/D-extension lateral doping proles in an undoped DG FinFET, showing variable encroachment into the channel. The HP prole exemplies one which lowersVtsviaS/Ddopantsinthechannel,butdoesnotaffectVtw;theLPprole does not affect Vtw nor Vts, but does yield an effective G-S/D underlap. The FinFET structure corresponding to the doping proles is indicated. -12.0-6.006.012.018.024.030.0y [nm] 10131014101510161017101810191020 HP LP Lg LextLextNSD [cm-3] LextLextx y LgtSiS D G G

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48 Figure 3-2.Measured current-voltage characteristics of two Lg = 70nm undoped DG nFinFETs [30], which have different NSD(y) due to variations in the S/D processing. The D Vts and D Vtw indicated reect LP (~device 1G) and HP (~device 2J) features of the respective devices, governed by NSD(y) as dened by (3.1)-(3.5). A) Strong-inversion characteristics. Note the strong D Vts(VGS) dependence, which indicates overly excessive densities of S/D dopants in the channel of device 2J ( i.e., G-S/D overla p) B ) Subthreshold characteristics. 0.00.10.20.30.40.50.60.70.80.91.01.1 0.00 0.05 0.10 0.15 0.20 1G 2J 1.2VGS [V] VDS = 1.2V D VtsIDS [mA] 0.00.10.20.30.40.50.60.70.80.91.01.1 10-1110-1010-910-810-710-610-510-410-3 1G 2J VGS [V] VDS = 1.2V1.2 D VtwIDS [A]A B

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49 Figure3-3.UFDG-predictedcurrent-voltagecharacteristics(pernheight)ofthe18nmLP and HP DG FinFETs, and of the LP device with longer Lg = 28nm as projected in the SIA roadmap [37]. A) Subthreshold Characteristics. B) Strong-inversion Characteristics. The strong-inversion characteristic of the HP device is approximate; the gate work function was decreased to account for the lowered Vts due to S/D dopants in the channel. 0.00.10.20.30.40.5VGS [V] 10-1210-1110-1010-910-810-710-610-510-410-3IDS [A/ m m] HP LP Lg = 28nm VDS = 1.0V 0.500.600.700.800.90 1.00VGS [V] 0.0 0.5 1.0 1.5 2.0IDS [mA/ m m] HP LP Lg = 28nm VDS = 1.0VA B

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50 Figure 3-4. The DG FinFET structure showing how the S/D-extension and channel regions were partitioned (into 2nm cubes) to account for the RDF of NSD(x,y) in the (2D) Medici domain. G G D S LextLextLgtSi

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51 CHAPTER 4 PHYSICAL INSIGHTS ON ANALOG/RF PERFORMANCE OF DOUBLE-GATE FINFETS, WITH COMPARISION TO BULK-SILICON MOSFETS 4-1 Introduction DG MOSFETs have been shown to be much better suited than bulk-Si MOSFETs for nanoscaledigitalapplications[33],primarilybecauseoftheirinherentlybetterimmunitytoSCEs and higher meff. The high meff [10], due mainly to low transverse electric eld in the undoped ultra-thin n-body (UTB), tends to produce signicant saturation-region effects that are not observed in conventional devices, for example, carrier-velocity overshoot [13], quasi-ballistic transport [10], and drain-induced charge enhancement (DICE) [12] which can affect analog performance. In this chapter, we use our physical understanding of nanoscale FinFETs, and UFDG [14], [15], [16], supplemented with published numerical-simulation and experimental data, to compare the analog/RF performance of undoped DG FinFETs with that of conventional bulk-Si MOSFETs, for both low-power and high-frequency RF applications. Further, we give insights on the optimal design of FinFETs for RF applications, and discuss the effects of scaling on analog FOMs of FinFETs. In order to make a fair comparison of the two devices, we consider FinFETs and planar bulk-Si MOSFETs that occupy nearly equal layout areas. For FinFETs, we assume Lg is about P/ 4,wherePisthepitchofthetechnology.ForpropercontrolofSCEsinDGFinFETs,tSimustbe about Lg/2 ~ P/8. Technologically, an aspect ratio of n height (hSi) to tSi of 4 is reliably achievable. Therefore, hSi ~ P/2. So, for comparison to bulk-Si MOSFETs with gate width (W) equal to P, we assume one-n (per pitch) FinFETs with effective width 2hSi = W, which is consistent with the noted structure for SCE control.

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52 4-2 Device Characteristics For qualitative insight, we begin by writing simple yet physical expressions for IDS, and deriving expressions for gm and fT. Based on these expressions we check and compare the RF performancesoftheDGFinFETsandbulk-SiMOSFETs.Inordertosimplifythediscussion,we derive the expressions assuming low VDS, and later we discuss their utility at high VDS. We also assume strong inversion, or moderate inversion near the onset of strong inversion. Forbothdevices,wecanwriteagenericexpressionforIDSintermsofaneffectivewidthof the device (Weff), equal to W for bulk-Si MOSFETs and 2hSi for FinFETs, as (4.1) where u represents the average carrier velocity in the channel and Qch here is the (aerial) inversion-charge density for bulk-Si MOSFETs, or half of it for (symmetrical) DG FinFETs. From the basic MOS equation [19], Qch (magnitude) can be expressed as ,(4.2) where FMS is the gate-body work-function difference. Note, for low VDS, Qch [ @ QG(int), where QG(int) is the magnitude of the intrinsic charge density on the gate) will be nearly constant along the channel. From (4.1), we derive (4.3) where the intrinsic (per unit area, excluding parasitics) gate capacitance CG(int)is dQG(int)/dVGS, which from (4.2) can be expressed as ,(4.4) intermsoftheinversion-layercapacitanceCinv=dQch/d fs.[Thebodycapacitancepresentinbulk devices,whichisabsentinFinFETsduetothetwocoupledgates,isneglectedin(4.2)and(4.4)]. I DS W eff Q ch u = Q ch C ox V GS F MS f s () @ g m W eff C Gint () u = 1 C Gint () -------------------1 C ox --------1 C inv ----------+ =

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53 If Cp is the parasitic gate capacitance per unit width, then the total gate capacitance is CG = CG(int)(WeffLg) + CpWeff, and hence, with (4.3), fT can be expressed as .(4.5) NotethatathighVDS,Qchwillbeafunctionofpositioninthechannel,andwillbedifferent from Qch in (4.2). Typically, this VDS-induced perturbation is only loosely coupled to the gate. Therefore, (4.3) and (4.5) capture the predominant dependences, even at high VDS, of the two dened analog FOMs, and are hence useful for general comparison of DG FinFETs and bulksiliconMOSFETs.Notein(4.5)howscalingLgtendstoincreasefT,asmentionedearlier,butalso note the dependences on u CG(int) [or on Cinv in (4.4)], and Cp, which underlie performance differences between DG FinFETs and bulk-Si MOSFETs. A. Low-Power RF Applications CMOS devices for low-power RF applications are generally biased in the moderateinversion region [34], where both drift and diffusion current components are important. In FinFETs,becauseofthehigh meff,signicantvelocityovershoot[13]istypicallyobserved,which leadstosubstantiallyhighercarrierdriftvelocity.Also,becauseofhigh meff,carriersdiffusefaster inFinFETs.Therefore,forlow-powerRFapplications, u issignicantlyhigherforFinFETsthan for bulk-Si MOSFETs. The inversion-charge centroid in FinFETs is farther away from the surface than in bulk-Si MOSFETsbecauseofbulkinversion[23]intheundopedUTB,especiallyformoderateinversion. This leads to lower Cinv in FinFETs, and hence lower CG(int) in (4.4). The parasitic (inner and outer)fringecapacitance(Cf)andtheoverlapcapacitance(Cov)willbeaboutthesameinthetwo devicesforequalWeff(iftheFinFETdoesnothaveG-S/Dunderlap[26],[29]),thusrenderingCpinbothdevicescomparable.Hence,CGinFinFETs(evenwithoutunderlap)willbelowerthanin f T u 2 p L g C + p C Gint () () --------------------------------------------------------=

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54 bulk-Si MOSFETs. However, for FinFETs with G-S/D underlap [26], [29] (which cannot be incorporated into bulk-Si MOSFETs with doped channels), there is no Cov and Cf is reduced, implying an added advantage as we discuss later. Since the inversion-layer thickness in FinFETs, with the noted bulk inversion [23], is ~tox, and (electron) meff is ~3x-higher than in bulk-Si MOSFETs [10], (4.3) suggests that the FinFET gm is comparable to that of the bulk-Si MOSFET. Signicant velocity overshoot [13] in FinFETs willtendtobenetgm,however.ThelowerCG(int),withcomparablegm,implieshigherfTin(4.5) for FinFETs than for bulk-Si MOSFETs. Further, a big advantage of FinFETs over bulk-Si MOSFETs is their much lower gDS. In bulk-Si MOSFETs, gDS is much higher than in undoped FinFETs[35]mainlybecauseofthepresenceofhalo(pocket)implantsinthebulkdevices,which introduce VDS-dependent barriers at the source and the drain [36]. For bias in the moderateinversion region, we note that drain-induced barrier lowering (DIBL), a SCE, is important in dening gDS. Therefore, even in the absence of halo implants, the gDS in bulk-Si MOSFETs will tendtobehigherthanthatinFinFETsbecauseofbetterSCEcontrolinFinFETs.ThelowergDS, with comparable gm, makes Avo in FinFETs larger than in bulk-Si MOSFETs. Thequalitativecomparisonsmadeabove,whichsuggestFinFETsuperiorityforlow-power RF applications, are generally consistent with the experimental results in [35], although comparable fTwas measured for the FinFETs and bulk-Si MOSFETs examined. This inconsistency could very well be due to higher Cov in the FinFETs. Since they were fabricated with undoped UTBs, but without G-S/D underlap, excessive overlap is quite likely. We show now that the FinFET superiority can be enhanced by incorporating G-S/D underlapinthedesign,whichisnotafeasibleoptionforbulk-SiMOSFETs[26].Asnotedbefore, DIBL is important in dening gDS in the moderate-inversion region. Therefore, an underlap, which has been shown to be effective in controlling SCEs [26], will improve the analog

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55 performance.Figure4.1showstheUFDG-predictedimpactofanunderlapongDSatVGS=0.4V for a 28nm DG FinFET, with Vt = 0.16V at low VDS. For this device, UFDG predicts that the underlap reduces DIBL from 120mV/V to 50mV/V, which translates to 75% reduction in gDS at VDS = 1.2V. A G-S/D underlap can also minimize Cp signicantly, and thus increase fT in (4.5). The underlap eliminates Cov, and reduces both the inner and outer Cf components [29]. Thus, even withthedoublingofCfintheDGdevice,Cpislower.Theunderlapwillincreaseparasiticsource/ drain resistance (RS/D), but that will not be overly important in the moderate-inversion region because of the low current levels. Therefore, underlap increases fT by reducing CG without signicantly affecting gm. Indeed, for the FinFET in Fig. 4.1, UFDG predicts, as shown in Fig. 4.2,thattheunderlapreducesCGby28%atVGS=0.4V,whileitpredictsnegligibledeterioration in gm. The net result is a 40% enhancement in fT. More elaborate discussion on the effect of underlap on fTis given in [34]. As mentioned before, experimental data presented in [35] show comparable values of fT for sub-optimally designed FinFETs (i.e., without underlap) and bulk-Si MOSFETs. However, our results and those in [34] clearly show that a well designed G-S/D underlap in undoped DG FinFETs can lead to much higher fT than in bulk-Si MOSFETs. B. High-Frequency RF Applications The relative performances for high-frequency RF applications can be assessed by comparing the FinFETs and bulk-Si MOSFETs biased where gm is maximum. This bias point is generally in the strong-inversion region, where, unlike in moderate inversion, RS/D is signicant. For example, it tends to reduce gm because of reduced effective gate bias, and hence lower fT. WithsimilarS/Ddopingdensity,FinFETstendtohavehigherRS/Dthanbulk-SiMOSFETs,even without G-S/D underlap which tends to increase it. In general, the resistance of a S/D extension region can be expressed as

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56 (4.6) where rextis the resistivity of the extension region, and Aext is its cross-sectional area. For FinFETs, Aext = hSitSi (unless the n is ared), and is typically less than Aext = Wxj of bulk-Si MOSFETs,wherexjisthejunctiondepth.FortSi@ xj,whichisreasonable,W=2hSiimpliesthat Rext in FinFETs is about a factor-of-two higher than that in bulk-Si MOSFETs. Indeed, the experimental data presented in [35] show lower fT in the FinFETs than in bulk-Si MOSFETs, whichwasattributedtohigherRS/D.However,theFinFETRS/Dreportedin[35](~1000 W m m)is abnormally high; in fact, RS/D@ 100 W m m has been recently achieved [22]. As noted previously, FinFETs tend to have higher u and lower CG(int) than bulk-Si MOSFETs,whichimplyhigherfT.However,forhigh-frequencyRFapplicationswiththedevices biasedinstronginversion,thehigherRS/DoftheFinFETswillunderminefTsome.Weassessthis effectofRS/DusingUFDGtopredicthowmuchfTwouldbeincreasedifRS/Dwerereducedfrom anominalvalueof100 W m mtohalfofthisvalue.Forthe28nmDGFinFETofFigs.4.1and4.2, UFDG predicts that fT increases by 14%. We can infer then that the inherently higher RS/D in nanoscale FinFETs will cause only about a 15% reduction in fT relative to that in bulk-Si MOSFETs (which is much lower than that reported in [35]). And, the reduction will be even less forlongerLg.ThissmalleffectofRS/DonfTisexplainedbythefactthatwhileitdecreasesgmby lowering the effective gate bias, it also decreases CG. The effect of higher FinFET RS/D on Avo is also not overly substantive. For the 28nm DG FinFET of Figs. 4.1 and 4.2, UFDG predicts that Avo increases by about 20% when RS/D is reduced from its nominal value of 100 W m m to half of this value. As noted previously, based on [36], gDS in FinFETs tends to be lower than in bulk-Si MOSFETs, by as much as an order of magnitude[35].Therefore,evenwithtwiceasmuchRS/D,AvoinFinFETsshouldbesubstantially R ext r ext L ext A ext ----------=

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57 higher than in bulk-Si MOSFETs. Unlike in the moderate-inversion region, G-S/D underlap is ineffective in reducing Cp in the strong-inversion region [29]. Also, G-S/D underlap is insignicant in dening gDS because DIBL tends to subside in strong inversion. However, we noted that G-S/D underlap will tend to reduce CG by eliminating Cov. Therefore, it could be benecial for high-frequency RF applications, even though it would increase RS/D. As shown in Table 4.1, the 28nm DG FinFET with a G-S/D overlap of 2.8nm (10% of Lg) has a lower UFDGpredicted fT than that of the FinFET with a G-S/D underlap optimized for low-power RF applications in accord with [34]. This G-S/D underlap introduces an extra RS/D of 60 W m m. However, elimination of Cov has a more signicant effect on fT, leading to a higher value for the FinFETdesignedwithG-S/Dunderlap.ThisdemonstratesourdesigninsightthatG-S/Dunderlap could be benecial for high-frequency RF applications. The design of G-S/D underlap for highfrequency RF applications will involve trading off RS/D for Cov. The optimal design will be the oneinwhichCoviseliminatedwithminimumextraRS/D.Therefore,thedesignchallengewillbe to maximize the doping concentration in the S/D-extension region near the gate edge, without diffusing signicant dopants in the UTB. This implies that the optimal G-S/D underlap for highfrequencyRFapplicationswillbesmallerthanthatforlow-powerRFapplications.Thisisshown in Table. 4.1, where the UFDG-predicted fT of a 28nm DG FinFET designed with a short G-S/D underlap (~2nm) is higher than that of the FinFET with a G-S/D underlap (~4.5nm), which is optimal for low-power RF applications 4-3 RF FinFET Scaling In Section 4.2 we concluded that analog/RF performance of FinFETs is superior to that of bulk-SiMOSFETs.Therefore,inthissectionwefocusonlyonFinFETs,anddiscusstheeffectof theirscalingonanalogFOMs.Thescalingeffectwasdiscussedin[35],withFinFETsscaledfrom 1 m m to 60nm. For FinFETs with such large gate lengths, IDS is dened by Qch at the position in

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58 channel where the velocity saturates, times the saturation velocity (vsat), or times a higher effective velocity (vsat(eff) > vsat) due to overshoot [13]. But, as Lg is scaled, vsat(eff) increases for a given VDS because of more overshoot, and this quasi-ballistic transport becomes quite signicant. Ultimately then, IDS becomes so high that it is limited by the maximum thermal velocity (vinj) with which carriers can enter the channel from the source [10], and the transport appearsballistic,withIDSdenedbyQchatthe(virtual)sourcetimesvinj.Therefore,asweshow in this section, the effect of scaling on analog FOMs of FinFETs as they are scaled to the gate lengths (<30nm) where quasi-ballistic transport becomes signicant could differ substantially from that discussed in [35]. We discuss the effect of scaling on analog FOMs of FinFETs as they are scaled from 65nm to 18nm, with proper accounting for quasi-ballistic transport. UFDG predicts that the limitation of the current due to quasi-ballistic transport will onset at Lg ~ 30nm. Since the effect of quasi-ballistic transport is most noticeable in the strong-inversion region, we look at the analog FOMs in this bias region. We assume undoped DG FinFETs, with tSi = Lg/2 and a pragmatic [2] SiON tox = 1.3nm. UFDG predictions of the FinFET gm versus Lg are plotted in Fig. 4.3. We see a steady increase of gm down to Lg@ 30nm, below which gm tends to saturate. For Lg > 30nm, IDS is not limited by vinj, and the quasi-ballistic transport improves with decreasing Lg due to increasing vsat(eff);gm,dependenton u in(4.3),increaseswithdecreasingLg.ForLg<30nm, u atthesource approaches vinj, which is virtually bias-independent, and hence gm ultimately saturates. This is not good for RF. TheUFDGpredictionsplottedinFig.4.4showtheeffectofscalingLgontheFinFETgDS, withandwithouttheballisticcurrentlimitinthemodel.Ingeneral,gDSincreaseswithdecreasing Lg. For increasing VDS, the magnitude of Qch is reduced because of the pinch-off tendency, but this reduction is compensated by DICE [12], with the charge enhancement being comparable to

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59 the pinch-off charge loss. Therefore, gDS is predominantly determined by the increase in vsat(eff)with VDS, and hence increases with decreasing Lg until IDS reaches the ballistic limit. When IDSis limited by vinj, gDS tends become independent of Lg; it does increase some for very short Lgbecause of DICE and virtually no pinch-off, however. Note in Fig. 4.4 how much gDS is reduced bytheeffectofvinj.Thebias-independentnatureofvinjisthemainreasonforthisreduction.This is benecial for RF. UFDGpredictionsoftheFinFETAvoversusscaledLgareplottedinFig.4.5.Theseresults reectthegmandgDStrendsinFigs.4.3and4.4.ForlongerLgwheretheballisticcurrentlimitis not so important, Avo decreases signicantly with scaling. However, when ballistic limit sets in, becauseofthesaturationtendenciesofgmandgDS,Avovirtuallysaturates.Thisisalsobenecial for RF. Finally,UFDGpredictionsoftheeffectofscalingonfTareplottedinFig.4.6.Ingeneral,fTincreases with scaling, which is good for RF. When the ballistic current limit is not important, fTincreases with decreasing Lg because of both the Lg and u dependences in (4.5), with the latter increasingwithvsat(eff).WhenvinjbeginstolimitIDS,fTincreasesonlybecauseofdecreasingLg, and this increase can be quite signicant if the Cp/CG(int) ratio in (4.5) is limited. Based on our simulations, we can project that fT > 500GHz is attainable for Lg = 18nm FinFETs. The UFDG-predicted results in Fig. 4.3-4.6 suggest that DG FinFETs in RF applications canindeedbescaledtoatleast18nmgatelengths,withverygoodperformanceprojected.Below 18nm, their RF performance tends to be undermined by the quasi-ballistic transport, which also tends to limit their digital performance. We note however that the effect of quasi-ballistic transport on analog FOMs in the moderate-inversion region, for low-power RF applications, will not be as signicant as in the strong-inversion region discussed herein.

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60 4-4 Summary Most of the literature discussing the analog/RF performance of DG FinFETs and bulk-Si MOSFETs is based on numerical-simulation and experimental results, with little emphasis on physical explanations. In this chapter, analog/RF performances of FinFETs and bulk-Si MOSFETs have been insightfully compared, and FinFETs have been shown to be superior to bulk-Si MOSFETs. We showed and discussed the benecial effect of G-S/D underlap on analog/ RF performance of FinFETs, for both low-power and high-frequency applications. We also gave insights on optimal design of G-S/D underlap. Our analysis also showed that the effect of higher RS/D in FinFETs, as compared to that in bulk-Si MOSFETs, does not signicantly affect the analog FOMs. Finally, we showed that the undermining effect on analog FOMs of scaling FinFETs to gate lengths below ~30nm, where UFDG predicts that quasi-ballistic transport will limit the current. This trend is signicantly different from that for FinFETs with longer gate lengths,forwhichweshowedhowtheyaresuperiortobulk-SiMOSFETsinRFapplications.We note, therefore, that simulation and analysis of nanoscale FinFETs in RF applications must account for the quasi-ballistic transport.

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61 Table4-1.ComparisonofUFDG-predictedfTofanLg=28nmDG FinFEThavingaG-S/Doverlap,withthatofFinFETs havingG-S/Dunderlapoptimizedforlow-powerandhighfrequency RF applications. DesignRS/D ( W m m)fT (GHz) G-S/D Overlap100322 G-S/DUnderlapfor Low-Power RF 160332 G-S/DUnderlapfor High-Frequency RF 120363

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62 Figure4-1.UFDG-predictedgDSofa28nmDGFinFETwithtSi=14nmandtox=1.3nm. The values have been normalized to hSi. For the device with G-S/D underlap, a guassian doping profile with straggle of 11.4nm was used, and Lext = Lg. This doping profile leads to a G-S/D underlap of about 4.5nm, which is optimal for low-power RF applications [34]. 0.00.10.20.30.40.50.60.70.80.91.01.11.2 VDS [V] 0.0 25.0 50.0 75.0 100.0 125.0 150.0gDS [ m S/ m m] w/o underlap w/ underlap VGS = 0.4V

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63 Figure 4-2.UFDG-predicted CG (normalized to hSi) versus VGS at VDS = 1.2V, with and without G-S/D underlap. The S/D doping profile is same as for Fig. 4.1. This S/D doping profile introduces an extra RS/D of about 60 W m m. Note the decreasing benefit of G-S/D underlap with increasing VGS. The difference in the two plots at high VGS is mainly due to the difference in RS/D. 0.00.10.20.30.40.50.60.70.80.91.01.11.2 VGS [V] 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2CG [fF/ m m] w/o underlap w/ underlap VDS = 1.2V

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64 Figure 4-3.UFDG-predicted gm versus Lg of DG FinFETs with tSi= 0.5Lg, tox = 1.3nm, and abrupt S/D doping profiles (no underlap); VGS = 1.0V and VDS = 1.2V. 15.025.035.045.055.065.0 Lg [nm] 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7gm [mS/ m m]

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65 Figure 4-4.UFDF-predicted gDS versus Lg for the FinFETs of Fig. 4.3, with andwithoutconsiderationofquasi-ballisticlimit;VGS=1.0Vand VDS = 1.2V. 15.025.035.045.055.065.0 Lg [nm] 0.00 0.10 0.20 0.30 0.40 0.50gDS [mS/ m m] w/ Ballistic limit w/o Ballistic limit

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66 Figure4-5.UFDG-predictedAvoversusLgfortheFinFETsofFig.4.3;VGS=1.0V and VDS = 1.2V. 15.025.035.045.055.065.0 Lg [nm] 0.0 50.0 100.0 150.0 200.0Avo

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67 Figure 4-6.UFDG-predicted fT versus Lg for the FinFETs of Fig. 4.3; VGS = 1.0V and VDS = 1.2V. 15.025.035.045.055.065.0 Lg [nm] 100.0 200.0 300.0 400.0 500.0 600.0fT [GHz]

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68 CHAPTER 5 INSIGHTS ON DESIGN AND SCALABILITY OF THIN-BOX FD/SOI CMOS 5-1 Introduction MOSFETswithundoped,fullydepleted(FD)ultra-thinbodies(UTBs)willhavetoreplace the conventional (bulk-Si and partially depleted (PD) SOI) devices if CMOS technology is to be scaled to the end of the SIA roadmap [37] where gate lengths (Lg) are projected to be less than 10nm.NointentionaldopingintheUTB/channeleliminatestheproblemofthreshold-voltage(Vt) variation,whichplaguesconventionalnanoscaleMOSFETs.CandidateFDdevicesincludequasiplanardouble-gate(DG)FinFETs[38],whichwehaveaddressedinpreviouschapters,andplanar single-gateFD/SOIMOSFETs,whichhaverecentlyevolvedtothin-BOX(TBOX)structureswith heavy ground-plane (GP) doping in the substrate under the device [39]-[42] as illustrated in Fig. 5.1. The GP, with proper doping (p+ for nMOS and n+ for pMOS), provides a back-gate work function which, with thin BOX, tends to accumulate the back surface of the UTB, thereby increasing the transverse electric eld (Ex) and ameliorating the short-channel effects (SCEs). Also, the GP can be properly biased (negatively for nMOS and positively for pMOS) to enhance the amelioration as well as adjust Vt. Note, though, the added CMOS process and layout complexity that the selective GPs imply.Unlike conventional devices, where the channel doping densitysimultaneouslyaffectsSCEsandVtofthedevice,itisbelievedthatTBOXdevicescanbe designedwithindependentcontrolofSCEsandVt;UTBthicknessdenesSCEs,andGPbiascan be used to tune Vt [43]. However, as we will show in this chapter, this in not the case, and signicantly complex processing is required to scale TBOX device toward the end of the CMOS roadmap. AnobviousdesignissueoftheTBOXMOSFETisthehighVtimpliedbytheincreasedEx. From the 1-D Gausss law at the front surface of an undoped-body TBOX MOSFET, we get [3]

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69 ,(5.1) where fsf and fsb are the potential at the front and back surfaces, respectively, and FGfS is the work-function difference between the front gate and the undoped body. Without SCEs (or, for long Lg) and with mid-gap gate (as commonly presumed for undoped UTBs), we can, for (hole) accumulation (in the nMOSFET) at the back surface, derive from (5.1) ,(5.2) where fc~0.4Visthecharacteristicsurfacepotentialat(inversionandaccumulation)thresholdin an undoped body, and tSi and toxf are the UTB and front-oxide thicknesses, respectively. The Vt(long) expression in (5.2) is an approximation because we assumed eSi/ eox@ 3 and fsb@ fc for holeaccumulationatthebacksurface,andignoredniteFermipotentialduetonaturaldopingin the body. For tSi ~ 10nm and toxf ~ 1nm, (5.2) gives Vt(long)@ 0.6V. And, Vt(long) will increase signicantlywiththelevelofaccumulation(untilitisverystrong)andwithdecreasingtSi;fortSi=5nm,(5.2)givesVt(long)@ 0.9V!TheSCEswilllowerVt,butnonethelessittendstobetoohigh for HP applications; LP applications have thus been the recent focus of TBOX FD/SOI CMOS studies[41],[42].WethereforerstdesignandexaminenanoscaleTBOXdevicesforLP,i.e.,low Ioff, and then consider the possibility of HP applications. We use Taurus [44] for 2-D numerical simulations,andphysicallyinterpretresults,withsupportfromourphysics-basedcompactmodel UFDG [16], to gain insights on design and scalability. 5-2 LP Devices Forlatercomparisons,werstdesignandsimulateaTBOXFD/SOInMOSFETthatcanbe relatedtorecentmeasuredandsimulatedLP-deviceresultsin[41]and[42].ForLg=25nm(=Leff V GfS F GfS 1 e Si t oxf e oxf t Si -----------------+ f sf e Si t oxf e oxf t Si -----------------f sb + = Vtlong ()16 toxftSi-------+ fc@

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70 due to assumed abrupt source/drain junctions without gate underlap/overlap), we assume toxf = 1.2nm (=EOT), tBOX = 10nm, unbiased (grounded) p+ GP, midgap gate, and undoped UTB with thickness (tSi) tuned to get adequate SCE control, or DIBL @ 100mV/V for VDD = 1.0V. Our Taurus simulations show that tSi = 6nm (=Lg/4.2) is needed, which is signicantly more aggressiveUTBscalingthanthat(~Lg/3)speciedin[41]and[42].(OurassumptionofabruptS/ D junctions leads to worst-case SCEs for a given Leff, but it is not the reason for this inconsistency.) Predicted device characteristics are given in Table 5.1, where they are compared with results for the same nMOSFET without the GP (DIBL = 120mV/V) and with thick BOX (DIBL = 220mV/V). Note the benet of the thin BOX even without the GP. The signicant reduction in DIBL yielded by the thin BOX alone is due to, rst, better control of the electric potentialintheUTBbythe(grounded)substrate,orbackgate,second,theenhancedEx,which tends to move the inversion-charge centroid towards the (front) gate [3], [45], and, third, amelioration of the electric eld-fringing effect in the thin BOX [45], [46]. The reduced DIBL lowers Ioff, but the dramatic decrease of Ioff shown in Table 5.1 reects a signicant increase of Vt(long)in (5.2) due to the thin BOX as well. (In our Taurus simulations, we are neglecting quantization, the effect of which on Vt is, for thick BOX and reasonable tSi > 4nm, indeed negligible [28] due to low Ex. For TBOX devices with(unbiasedorbiased)GP,ExishigherforlongLg,butfornanoscaleLg,Exisreducedby2-D effects, as shown by Taurus, such that the quantization effect on Vt is still small.) As mentioned, the thin tBOX = 10nm ameliorates the eld fringing in the BOX, but it does not completely suppress its effects. In Fig. 5.2 we show Taurusand UFDG-predicted weakinversion current-voltage characteristics of an Lg = 30nm TBOX nMOSFET, with tBOX = 10nm and tSi = 6nm. The UFDG results, with BOX eld-fringing modeling [46] tuned to the Taurus results,andwithouttheeld-fringingmodelingactivated,clearlyshowsignicantdegradationof

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71 the subthreshold characteristics, or SCEs, due to the fringing even for 10nm BOX. (We thank Shishir Agrawal, a post-doctoral student at the University of Florida, for doing the simulation in Fig. 5.2.) Contrary to expectation [39]-[42], our simulation results in Table 5.1 (for the nMOSFET) showthattheadditionoftheunbiasedGPonlyslightlyreducesDIBLandIofffurther.Thep+-GP benetissmallbecauseitonlyincreasestheback-gateworkfunctionby~200mV(foratypicalpsubstrate), which does not increase Ex much for tBOX = 10nm. However, for the TBOX pMOSFET, the n+ GP will decrease the back-gate workfunction by ~700mV, which will impact the device characteristics much more. Simulations show that for the TBOX pMOS counterpart to thenMOSFETinTable5.1,theGPreducesDIBLfrom140mV/Vto120mV/V,butdecreasesIoffby a factor of ~100. We note that the effect of the higher Ex is negligible with regard to DIBL becauseofthethintSi,butisdramaticwithregardtoIoffviathemuchhigherVt(long).Toillustrate this point further, we show in Fig. 5.3 Taurus-predicted weak-inversion current-voltage characteristics of TBOX CMOS devices, with and without GPs. We thank Shishir Agrawal for doing this simulation. Note that the GP effect (especially the increased Vt) is dramatic for the pMOSFET, but much less signicant for the nMOSFET. We thus might question whether the (unbiased) GP, with its process complexity, is worthwhile for the TBOX nMOSFET. (We show later that it is needed, with bias, for scalability, however.) Even with it, the predicted Ioff ~ 1000pA/ m m is much too high for LP, even though the SCEs are controlled; Ironically; Vt is too low. Our simulation results in Table 5.1 are in general accord with measured DIBL and Ioff vs. Lg and tSi for thick-BOX nanoscale FD/SOI MOSFETs in [47]. The inconsistency of our results withthosein[41]and[42],regardingSCEcontrolandLPdesign,couldbeduetoG-S/Dunderlap [26] in the devices examined in [41] and [42], which renders Leff > Lg and yields better SCE

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72 control(andwhichisessentialfornanoscaleUTB-devicedesign[48]).Tocheck,weredesignour Lg = 25nm thin-BOX/GP nMOSFET with underlap; we increase tSi = 8nm (~Lg/3 in line with [41]and[42]),andnowtunetheunderlap(LeSD)togetDIBL=100mV/V.Oursimulationsreveal that LeSD = 2.5nm is needed, meaning Leff = Lg + 2LeSD = 30nm. Part of the inconsistency is possibly explained, but our predicted Vt is still too low and Ioff is too high for LP. TogetanacceptableLg=25nmLPdesign,wemustdecreaseIoffto~10pA/ m m,irrespective ofDIBL.BecauseofthelessereffectoftheGPinthenMOSFET,thedesignofthisdeviceismore demanding, and hence we focus on it. We include the GP because biasing it is one way of decreasing Ioff. Another way is thinning tSi, as implied by (5.2), which we check rst. We begin with the device having the 2.5nm underlap, and we now tune tSi to get acceptable Vt and Ioff at VDD = 1.0V. We nd that tSi = 6nm (=Lg/4.2 = Leff/5) is needed, and we get Ioff@ 30pA/ m m. We note that the predominant effect of thinning tSi here is to increase Vt(long). Interestingly, we get DIBL = 60mV/V for this device, meaning that DIBL alone is not an acceptable design criterion for LP thin-BOX FD/SOI MOSFETs. This new insight is reected in Table 5.2, where we give Taurus-predictedIoffandDIBLforourLPnMOSFET,comparedwithpredictionsforvariabletSi. Note that thicker tSi = 7nm, which yields Ioff@ 100pA/ m m and DIBL = 80mV/V, could be an acceptableLPdeviceaswell.ButalsonotethatthedesignsoftheseLPTBOX/GPMOSFETsare much more stringent (i.e., much lower tSi/Lg ~ 1/4 is needed) than suggested in [41] and [42]. Perhaps a GP bias (for which the selective p+ and n+ GPs are necessary in the CMOS technology),whichincreasesEx,canloosenthedesigncriteria(i.e.,enableuseofthickertSi)and give a more optimistic scaling outlook, albeit with added technology and layout complexity. Focusing on Ioff as the main LP design criterion, we give simulation results in Table 5.3 derived by tuning tSi to get Ioff ~ 10pA/ m m for GP bias (VGP) ranging from 0V (as in Table 5.2) to -5.0V, which ensures strong back-surface accumulation and thus maximizes Ex. Indeed, the tSi

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73 requirement can be relaxed signicantly with GP bias. For the strong-accumulation case (which requiresasizeableVGPmagnitude),agoodLPdesignisachievedwithtSi=15nm(=Lg/1.7=Leff/ 2withthe2.5nmunderlap),asopposedto6nmfornoGPbias.Interestingly,noteinTable5.3the anti-correlation of Ioff and DIBL for decreasing VGP; as we relax the tSi requirement for Ioffcontrol with decreasing VGP, DIBL increases whereas Ioff decreases. This surprising result is due to the fact that Vt(long) is being increased, while the SCEs worsen, with the former effect being predominantwithrespecttoIoff.NotethatdecreasingVGPwilltendtoincreaseIoffbyincreasing junction tunneling at the back surface, but the effect of increase in Vt(long) due increase in Expredominates, and therefore, there is a net decrease in Ioff with decreasing VGP. TheencouragingresultsinTable5.3concerninguseofGPbiassuggestthat,withit,TBOX FD/SOICMOSmaybescaledconsiderably.Wecheckthescalability,intermsofLefffordevices withunderlap,bytryingtotunetSiforIoff~10pA/ m m,withacceptableDIBL,asLeffisshortened (from30nmasinTable5.3)andVGPissettoensurestrongaccumulation.(ThisVGPwilltendto become more negative with decreasing Leff due to increase in Ex, as dened by decreasing tSirequired for SCE control.) We still let toxf = 1.2nm and tBOX = 10nm. The simulation results are giveninTable5.4.InlinewiththeabovenoteabouttheimportanceofVt(long)vs.tSi,wendthat Vt becomes too high when DIBL @ 100mV/V, leading to extremely low Ioff and reecting poor Ion.Gatework-functiontuningtodecreaseVtisthuscalledfor,whichaddsevenmorecomplexity tothefabricationprocess.WeincludeinTable5.4thedecreaseintheworkfunction( DFGfbelow midgap)neededtoincreaseIoffto~10pA/ m m,andtherebygetacceptableIonforLPperformance. Further, we stop the scaling when tSi reaches ~5nm, which thus denes the scaling limit of Leff@ 18nm for LP thin-BOX/GP (with sizeable VGP) CMOS; the needed gate work function is near conductionband-edgeforthen-channeldevice.TheassumedminimumSOIthicknessisbasedon thequantizationeffect[28],whichbecomesprohibitivelysevereforthinnertSi,aswellastheSOI

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74 technology. Additional simulations reveal that without GP bias, the LP scaling limit, set by tSi = 5nm with a midgap gate, is Leff =28nm. From (5.1), the Vt of a TBOX MOSFET can be expressed as ,(5.3) where fsf t and fsb t are the potential at the front and back surfaces at threshold, respectively. UnlikeinthederivationofthesimpleexpressionforVt(long)in(5.2),herewedoamorethorough analysisbyconsideringtheniteFermipotential( fF)duetonaturalp-typedoping(~1015cm-3)in the unintentionally doped UTB [3]. We assume for the nMOSFET with strong back-surface accumulation, fsf t = fc + fF and fsb t = fa + fF, where fa@ fcis the strong-accumulation counterpartto fc.SimilarlyforthepMOSFETwithstrongback-surfaceaccumulation,weassume fsf t= -fc+ fFand fsb t= fa+ fF.Withtheabove fsf tand fsb tfornMOSFETandpMOSFET,and noting that FGfS = fF for a midgap gate, we nd that the nite fF does not affect Vt when the back surface is accumulated, and so the CMOS devices are symmetric in this regard. Therefore, the TBOX pMOSFET for LP applications can be designed and scaled in a manner similar to that of the TBOX nMOSFET. 5-3 HP Devices TochecktheHPapplication,anditsscalability,werstpresumethatVGPmustbenegative enoughforstrongaccumulationtoensureSCEcontrol.WebeginwiththeLeff=30nmnMOSFET in Table 5.4, and tune DFGf to increase Ioff to an acceptable ~100nA/ m m, which implies acceptableIon(iftheexternalS/DseriesresistanceintheUTBdeviceisadequatelylimited[47]). WethenscaleLeff,tuningtSiand DFGftogetDIBL @ 100mV/VaswellasIoff~100nA/ m m.The simulation results, in Table 5.5, are discouraging. They show, for a specic Leff, that the DFGfrequired to tune Ioff for HP is much larger than that required for LP, being near conduction bandV t F GfS f sf t 3 t oxf t Si ---------++ f sf t f sb t @

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75 edgeforLeff=25nmandperhapsbeingimpossibleforLeff=18nm.Therequired DFGfincreases with decreasing Leff due to the increase in Vt(long) in (5.2) dened by the thinner tSi needed for SCE control. Thus, as indicated in Table 5.5, the HP scaling limit could be longer than the Leff = 18nmdenedbytSi=5nm,whereanunacceptablyhigh[49] DFGf=850mVwouldbenecessary. Without GP bias (VGP = 0V), the HP scalability dened by tSi = 5nm is Leff = 25nm, with a required DFGf = 200mV. These results then suggest that, for the nMOSFET, the realistic scaling limitisreachableevenwithoutaGPbias,andthusevenwithouttheGP,aswehaveintimated,but is not close to the end of the ITRS roadmap. The same analysis of the TBOX pMOSFET for HP applications leads to a similar no-GP design.ItsSCEswillbevirtuallythesameasintheno-GPnMOSFET,andhenceitsscalinglimit isalsoLeff@ 25nm.InaTBOXwithoutGPbias(andnoGP)andwithdepletedbacksurface,from the 1-D analysis in [3] we get ,(5.4) whereCb= eSi/tSiandCoxb= eox/toxb.Assumingthat fsf t= fc+ fFforthenMOSFET,and fsf t=fc + fF for the pMOSFET, with fsb t dened by (5.4), we get from (5.3) ,(5.5) where Vtn and Vtp are the threshold voltages of the TBOX HP nMOSFET and pMOSFET, respectively, and r is the body factor [3]. Therefore, TBOX CMOS for the HP application is not symmetric. For the TBOX pMOSFET, the needed DFGf due to the fF term in (5.5) is negative (above midgap), and its magnitude is about 50mV (in worst case, as implied by (5.5)) less than that for the nMOSFET. f sb t C b C b C oxb + -------------------------- f sf t = V tp V tn 2 r f F + =

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76 5-4 Comparisons with FinFETs In this section we compare potential performances of nanoscale thin-BOX FD/SOI MOSFETsandDGFinFETsinordertogainmoreinsightsontheviabilityoftheformer.Since,as discussed, the performance and design challenges of the TBOX nMOSFET and pMOSFET are similar,wefocusonthen-channeldevice.InTable5.6,wesummarizeourprojectedscalinglimits (intermsofLeff=Lg+2LeSD)ofthin-BOX/GPnMOSFETsforLPandHPCMOSasdenedby tSi = 5nm, and compare them with Taurus predictions for DG nFinFETs with the same tSi, or n thickness.Thescalabilityofthethin-BOX/GPdevicewithnoVGPandmidgapgateisworstofall. NegativeVGPforstrongbackaccumulationtendstoimproveit,butalsobringsintherequirement of tuned DFGf. For LP applications, we project a scaling limit Leff = 18nm, which, with G-S/D underlap, implies Lg ~ 10nm. The projected HP scaling limit of Leff@ 18nm in Table 5.6 is questionable because of the very large DFGf required to get acceptable Ioff and Ion, as noted before. A scaling limit of Leff@ 25nm, with tSi = 10nm, is probably more realistic; as shown in Table 5.5, it requires a near conduction band-edge gate work function. Coincidently, as shown in Table 5.6, the projected HP scaling limit without VGP for tSi = 5nm is also 25nm. Therefore, for HPthin-BOXFD/SOICMOS,VGPseemsunnecessary,andthussodotheGPs,butthescalability is not good. DG FinFETs yield the most relaxed tSi requirement for SCE control due to the two gates [48]. Therefore, for HP applications where the scalability is limited by SCE requirements, the FinFET, with midgap gate, is most scalable. The Leff@ 15nm limit noted in Table 5.6 implies, with G-S/D underlap [26], an Lg scaling limit near the end of the ITRS. Note that our simulation results in Table 5.6 indicate that near the scaling limit, for adequate SCE control in the DG FinFET,tSi/Leff@ 1/3willbeneeded,whichissmallerthangenerallypresumedtSi/Leff@ 1/2[50]. This is because toxf is not being scaled due to gate-leakage considerations. For LP applications,

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77 thescalabilityoftheDGFinFET,withmidgapgate,islimitedbytheIoffrequirement.Therefore, it is less scalable than the thin-BOX/GP MOSFET with VGP, for which the noted work-function tuning is necessary to get acceptable Ioff. Of course, such tuning could be used for the FinFET as well.Withanearvalenceband-edgegate,asshowninTable5.6,theDGnFinFETcouldbescaled to Leff@ 15nm (Lg < 10nm), limited by the SCE requirements, rendering it most scalable for LP applications also. ThecomparisonofthetwoFDdevicesmustinvolvemore.ThenegativeVGPappliedtothe thin-BOX/GP nMOSFET increases the connement of electrons towards the front surface, leading to higher inversion-layer capacitance (Ci) than in the DG FinFET, which is subject to signicant bulk inversion [48]. This difference is reected in Fig. 5.4, where we show a comparison of Taurus-predicted low-VDS strong-inversion currents in the Leff = 30nm thin-BOX/ GP nMOSFET in Table 5.5 and in an Leff = 30nm DG nFinFET with tSi (=15nm) tuned to get similar DIBL and DFGf (=60mV) tuned to get similar Ioff. The simulation results in Fig. 5.4 imply,atVGS=1.0V,thathigherCiinthethin-BOX/GPMOSFETleadsto17%higherinversion chargedensity(Qi=qNinv)thanthatsupportedbyeachgateintheDGFinFET.Thistranslatesto less than 2 x (1.7 x for low VDS) current in the FinFET relative to that in the FD/SOI MOSFET. (The external S/D series resistance was kept low in the simulations in order to avoid any discrepancy in effective biases due to different current levels, and a constant meff model was used so that the difference in currents reected directly the different Qi and Ci.) The higher Ci due to Ex is a benecial effect for the thin-BOX/GP MOSFET. However, Exalsoimplieslower meffduetomoresurface-roughnessscattering,whichtendstonegatethehigher Qi with regard to Ion. For a typical Ninv in strong inversion, the surface electric eld in the thinBOX/GP MOSFET is higher than that in the DG FinFET not only because of the GP, but also because the entire inversion charge is supported by one gate, as opposed to two gates in the

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78 FinFET.Thus,strong-inversioncarriermobilitycanbehigherintheFinFETbyafactoroftwo,or more[48].Further,thehighExalsounderliesanenhancedquantizationeffectinstronginversion, which lowers Ninv at a given VGS. Due to thin box, source/drain-substrate capacitance could be signicant in TBOX CMOS, and, unlike in DG FinFETs, there is a non-zero (effective) body capacitance (Cb(eff)) associated with TBOX MOSFETs [3], which tends to increase the subthresholdslope(S)andIoff(althoughtheSCEsusuallydeneS),aswellasundermineCMOS speed. Also, heavily doped GP may lead to signicant depletion in the S/D extension regions whichwouldincreasetheseriesresistanceandaccentuateSCEs[51].However,TBOXMOSFETs may have some advantage over FinFETs because of their planar structure; e.g., controlling UTB thicknessintheTBOXdeviceiseasierthaninFinFETs,whichimpliesthatyieldofTBOX-based SRAM is higher than that of FinFET-based SRAM [52]-[53]. 5-5 Conclusions Wehaveusednumericaldevicesimulations,withphysics-basedinterpretationsofresults,to design and study thin-BOX FD/SOI CMOS, and to assess its scalability, for both LP and HP applications, relative to that of DG-FinFET CMOS. For LP, we found that both Ioff and DIBL must be considered as design criteria, and that they are not necessarily correlated. We found that, with the complex processing and layout (due to selective, sizable GP biasing and tunable gate work function for different Lg), the LP thin-BOX/GP MOSFET scalability, with G-S/D underlap (Leff > Lg), is Lg ~10nm; whereas, with gate work-function tuning and G-S/D underlap, the LP DG FinFET can be scaled to the end of the SIA roadmap where Lg < 10nm is projected. For HP applications, the DG FinFET is clearly the winner in terms of scalability. Our simulation results showthatwithoutanyrequiredwork-functiontuning,i.e.,withamidgapgate,theHPDGFinFET can also be scaled to the end of the roadmap; whereas, because of implausible work-function engineering required, the scalability of the HP thin-BOX MOSFET is severely limited, although

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79 the GP can be eliminated and the processing signicantly simplied. Thin-BOXFD/SOIMOSFETshavetheadvantageofbeingplanarand,therefore,similarto conventional PD/SOI devices in terms of processing. However, the added process complexities noted herein, with less potential HP scalability than DG FinFETs, make them less attractive. Hence, thin-BOX FD/SOI CMOS could be a viable interim technology, bridging conventional CMOSandDG-FinFETCMOS.Thelattertechnology,whichcanbepragmaticallydesigned[48], is potentially scalable to the end of the SIA roadmap for both HP and LP applications.

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80 Table5-1.Taurus-predictedcharacteristicsofLg=25nm(=Leff)FD/SOI nMOSFETs with midgap gate and tSi = 6nm. DesignDIBL (mV/V)Ioff (pA/ m m) Thin BOX w/ GP100103Thin BOX1203 x 103Thick BOX (200nm)220106Table 5-2. Taurus-predicted characteristics, vs. tSi, of Lg = 25nm TBOX/GP nMOSFETs with 2.5nm G-S/D underlap and midgap gate. tSi (nm)DIBL (mV/V)Ioff (pA/ m m) 66030 780100 81001000

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81 Table5-3.Taurus-predictedcharacteristics,vs.VGP,ofLg=25nmTBOXGP nMOSFETs with 2.5nm G-S/D underlap and midgap gate. VGP (V)tSi (nm)DIBL (mV/V)Ioff (pA/ m m) 066030 -1.099020 -5.01510010 Table 5-4. Taurus-predicted characteristics, vs. Leff, of TBOX/GP nMOSFETs with VGP for strong accumulation and controlled DIBL. The work-function reduction below midgap required to increase Ioff as shown to ~10pA/ m m for feasible LP is given. Leff (nm)tSi (nm)Ioff (pA/ m m) DFGf (mV) 3015100 25101100 l8510-3450

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82 Table 5-5. Taurus-predicted characteristics, vs. Leff, of TBOX/GP nMOSFETs with VGP for strong accumulation. The workfunction reduction below midgap required to increase Ioff to ~100nA/ m m for acceptable Ion and viable HP is given. Leff (nm)tSi (nm)DIBL (mV/V) DFGf (mV) 3015100380 2510100500 l85110850 Table5-6.Taurus-predictedLPandHPscalinglimits(Leff,which,withG-S/D underlap,canbe5-10nmlongerthanLg),denedbytSi=5nm,for thin-BOX/GP nMOSFETs (tBOX = 10nm) and DG nFinFETs (all with toxf = 1.2nm). The devices have been designed for Ioff ~ 10pA/ m m and ~100nA/ m m for LP and HP applications, respectively, with DIBL 100mV/V. The 18nm limit for the HP thin-BOX/GP device with VGP (for strong accumulation) is questionable due to the very large DFGf needed; the scaling limit of 25nm without VGP (and without GP) is more realistic and pragmatic. LP Thin-BOX/GP w/o VGPThin-BOX/GP w/ VGPDG FinFET Leff (nm)281825/15 DFGf (mV)04500/-450 HP Thin-BOX/GP w/o VGPThin-BOX/GP w/ VGPDG FinFET Leff (nm)2518?15 DFGf (mV)2008500

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83 Figure 5-1. Basic thin-BOX FD/SOI nMOSFET structure, with P+ GP. n+Gf pn+BOX STI STIp+GPSi Substrate

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84 Figure 5-2. Taurusand UFDG-predicted weak-inversion current-voltage characteristics of a TBOXFD/SOInMOSFET(Lg=30nm,tSi=6nm,tBOX=10nm,noGP).TheUFDG prediction, with the electric-eld fringing parameters tuned to t Taurus data, is contrasted to a UFDG prediction with the eld fringing modeling deactivated. A constant electron mobility ( mn=300cm2/Vs) was assumed in both the Taurus and UFDGsimulations.TheTaurus-UFDGdiscrepanciesinstronginversionareduetono signicant series resistance in the Taurus domain. VGS(V)IDS (A/ m m) -0.20.00.20.40.60.8 10-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-3 Taurus UFDG w/ electric-field fringing ON UFDG w/ electric-field fringing OFF VDS = 50mV, 1.0V 1.0

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85 Figure 5-3. Comparison of Taurus-predicted current-voltage characteristics of TBOX FD/SOI CMOS devices, with and without GPs. The devices were designed with Lg = 25nm, tSi=5.5nm,S/Dspacerwidth=15nm,andGaussianS/Ddopingprole,whichgives Leff=30nm,i.e.,2.5nmG-S/Dunderlap.ThesubstrateforboththenMOSandpMOS devices was assumed to be p--type, which underlies the dramatic GP impact in the latter and lesser impact in the former. A) nMOSFET. B) pMOSFET. -1.0-0.8-0.6-0.4-0.20.0 10-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-310-2 pMOSFET w/o GP pMOSFET w/ GP -0.20.00.20.40.60.8 10-1510-1410-1310-1210-1110-1010-910-810-710-610-510-410-310-210-1100 nMOSFET w/o GP nMOSFET w/ GP VGS (V) VGS (V)IDS (A/ m m) IDS (A/ m m)1.0 0.2A B

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86 0.00.10.20.30.4 0.5VGS (V) 10-910-810-710-610-510-410-310-2IDS (A/ m m) 00.20.4 0.6 0.81VGS [V] 0 0.2 0.4 0.6 0.8 1 1.2 1.4IDS [mA/ m m] Figure 5-4. Comparison of Taurus-predicted current-voltage characteristics of a TBOX nMOSFETwiththatofaDGnFinFETcounterpart.TheTBOXdeviceisthesameas Leff = 30nm TBOX device in Table 5.5; the DG FinFET was designed with Leff = 30nm,tSi=15nm,andtoxf=1.2nm.A)Comparisonofweak-inversioncharacteristics ofthetwodevices; DFGfandtSioftheFinFETweretunedtogetIoffandDIBLclose to that of the TBOX device. B) Comparison of strong-inversion characteristics of the two devices at low VDS (50mV), showing less than 2x current in FinFET relative to that of the TBOX MOSFET.DG FinFET TBOX DG FinFET TBOXA B

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87 CHAPTER 6 SUMMARY AND FUTURE WORK 6-1 Summary This dissertation is focused on physics-based modeling, optimal design, and performance of nanoscale DG FinFET CMOS for both digital and analog/RF applications. The major contributions of the research are summarized as follows. InChapter2,wemodeledDICEinnanoscaledouble-gateMOSFETs,andimplementedit inourprocess/physics-basedcompactmodelUFDG.TheeffectofDICEonthetransistorcurrent, terminal charge, capacitance, and transcapacitance was studied, and veried via numerical and UFDG simulations. We found that DICE is a benecial effect because it signicantly increases inversion-chargedensity,andhencecurrent,withoutsignicantlyaffectinggatecapacitance.This is because the enhanced inversion charge is primarily supported by the drain. Its benecial effect was demonstrated by the speed enhancement of DG FinFET CMOS via UFDG/Spice3 simulations. We showed that the current enhancement due to DICE is signicantly larger for devicesinwhichquasi-ballistictransportisimportant.Forsuchdevices,thecurrentenhancement duetoDICEisdirectlyproportionaltotheenhancementininversion-chargedensity,whereas,for devices in which quasi-ballistic transport is not important, the enhancement in current due to DICE is undermined by the increase in the gradual-channel length caused by DICE. In Chapter 3, we proposed a design approach in which S/D engineering can be used to adjust the Vt of nanoscale DG MOSFETs for low-power and high-performance digital applications via limited densities of S/D dopants in the channel. The design approach was demonstratedandveriedvianumericalandUFDGsimulations,andexperimentalresults.Itwas shownthattheproposeddesignapproachaugmentstheutilityoftheG-S/Dunderlap.Theissueof random-doping effects was duly addressed by comprehensive Medici-based numerical

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88 simulations.Oursimulationsconsideredtherandom-dopingeffectsintheultra-thinbody,aswell asintheS/Dextensionregions.Therefore,oursensitivityresultsincluderandomvariationsinVt, and also the random variations in Leff. It was argued that the design approach will be viable and benecial even in sub-10nm regime. It was noted, however, that at such short Lg, additional analyses of quantization effects, mobility degradation, and ballistic transport will be called for. Also, source/drain engineering techniques to support this design approach will have to be developed. In Chapter 4, we compared the analog/RF performance of double-gate FinFETs with that of conventional planar bulk MOSFETs, and showed that the FinFET performance is better. Optimal design of FinFETs with G-S/D underlap, and the effect of higher RS/D in FinFETs on performance were discussed. We showed that G-S/D underlap signicantly benets the lowpower analog/RF performance of DG FinFETs by reducing DIBL and G-S/D parasitic capacitances.Sincelow-powerdevicesarebiasedinthemoderate-inversionregion,wherethegm/ ID ratio tends to be maximum, the increase in RS/D is not important due to low operating-current levels. Devices for high-frequency applications, on the other hand, are biased in the stronginversion region, where gm is maximum. Therefore, for high-frequency applications, increase in RS/D due to underlap could be important due to high operating-current levels, and could be detrimental to the device performance. However, it was shown that small G-S/D underlap would still be desirable because it will benet the performance by eliminating G-S/D overlap capacitance, the effect of which was found to be more signicant than that of the associated increase in RS/D. And nally, the effect of scaling on the analog/RF performance of FinFETs, as Lg is scaled below ~30nm where quasi-ballistic transport becomes important, was discussed. In Chapter 5, we studied the design of thin-BOX FD/SOI MOSFETs for low-power and high-performancedigitalapplications,andcomparedtheirscalabilitytothatofFinFETs.Forlow-

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89 power applications we found that, with complex processing and layout, thin-box FD/SOI MOSFETs can be scaled to Lg ~ 10nm; whereas FinFETs can be scaled to Lg < 10nm with signicantlysimplerprocessing.Forhigh-performanceapplications,thescalabilityofFinFETsis signicantlybetterthanthatofthin-BOXFD/SOIMOSFETs.Wenotedthatthin-BOXFD/SOIis similartoconventionalplanarMOSFETsintermsoftheprocessing,thereforeitcouldbeaviable interim technology, bridging conventional CMOS and DG-FinFET CMOS. 6-2 Future Work In Chapter 3, we proposed, and demonstrated using Medici/UFDG simulations, a design approach in which limited densities of source/drain dopants in the channel can be used for Vtadjustment in nanoscale DG MOSFETs. This design approach will be viable only if reliable source/drainengineeringtechniquesaresuccessfullyrealized.Inordertorealizethesetechniques, the diffusion of dopants through thin lms should be modeled and experimentally veried. Also, the proposed design approach should be corroborated by additional analyses of quantization effect, mobility degradation, and ballistic transport for Lg ~ 10nm. In Chapter 4, we discussed the optimal design of DG FinFETs for low-power and highfrequency analog/RF applications. This study was done at the device level with the emphasis on optimizing basic FOMs. The study should be further corroborated by demonstrative circuit simulations and analyses. In Chapter 5, we studied the design of thin-BOX FD/SOI MOSFETs for low-power and high-performance applications. The study is primarily based on weak-inversion region analysis. In the strong-inversion region, UFDG is incapable of predicting the characteristics of thin-BOX devices with back-gate bias because of carrier accumulation. For a more comprehensive study, strong inversion analyses of UFDG should be upgraded to render the model fully applicable to thin-BOX FD/SOI devices with back-gate bias.

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90 APPENDIX AAUFDG MODEL REFINEMENTS A-1 Introduction UFDG [16] is a process/physics based generic compact model which is applicable to diverse SOI-based DG MOSFETs. UFDG very effectively captures the unique physics of DG MOSFETs with UTB via robust modeling of terminal charge and carrier transport. UFDG has been veried by numerical device simulations and measured experimental results, and has been shown to reliably predict the characteristics of DG MOSFETs with Lg as short as ~30nm. For shorterLg,duetolackofexperimentalresultsandinadequatemodelingofcarriertransportinthe commercially available device simulators, there is no direct way of verifying the accuracy of UFDG, for example, that of its quasi-ballistic/ballistic carrier transport modeling. More than likely,futureUFDGupgradeswillbeneededasCMOStechnologyisfurtherscaled.Suchmodel upgrading is exemplied by this appendix, in which we discuss the renements we did in UFDG to make it more robust for reliable prediction of nanoscale DG MOSFETs studied in this dissertation. A-2 Strong-Inversion Intrinsic Charge Modeling The voltage-dependent terminal charges of the DG MOSFET is characterized in order to model the charge dynamics for large-signal transient simulations. The terminal charges are assumedquasi-static,andareindividuallyintegratedbasedonspatialdependenceintheMOSFET which follow from the analyses in [25], modied by the DICE analyses discussed in Chapter 2. Charge neutrality, which is important for the stability and convergence of a compact model, is satised due to physics-based treatment of all the terminal charges. The charge modeling in UFDG is divided into two parts: triode and saturation regions, which are eventually merged for a continuous model.

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91 In the triode region, front-gate charge (QGf) is characterized by the integral: .(A-1) Back-gate charge (QGb) is characterized by a similar integral at the back surface. Next, the integrated charge in the channel is evaluated by the integral: ,(A-2) where Qch(y) is given by (2.4), which includes the DICE charge in the channel. The integrated inversionchargeisthenpartitionedbetweenthesourceandthedrain.Theportionoftheinversion charge assigned to the drain is evaluated by the integral: ,(A-3) and rest is assigned to the source, .(A-4) Finally, body-depletion charge (QB) is dened as, .(A-5) Typically QB is negligible because of undoped body. Note that in the previous [25] charge modeling, the drain-depletion charge in the triode region was ignored. However, as we discussed in Chapter 2, DICE charge is signicant in nanoscale DG MOSFETs, and is primarily supported by the drain. Therefore, a corresponding depletion charge is assigned to the drain in order to maintain the charge neutrality. In saturation region, the charges dened for the triode region will still be valid with Lgreplaced by Lgch, and VDS replaced by VDS(eff), and they will be augmented by the charges Q Gf W g C oxf V GfS F GfB f 0 0 y ()Df y () [] yd0 L g= Q ch W g Q ch y () yd0 L g= Q Dch () W g y L g -----Q ch y () yd0 L g= Q Sch () Q ch Q Dch () = Q B W g L g qN A t Si =

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92 associated with the high-Ey region. With Lgch and VDS(eff) solved as discussed in Chapter 2, we dene the saturation-region component of the front-gate charge (QGf sat) by the integral: ,(A-6) andthesaturation-regioncomponentoftheback-gatecharge(QGb sat)willbedenedbyasimilar integral at the back surface. Since the carrier velocity is saturated in the high-Ey region, based on the current continuity, the charge density will be nearly uniform along y, and channel charge is dened by simple integral: .(A-7) Analogous to the scheme in the triode region, Qch sat is partitioned between the source (QS(ch) sat) and the drain (QD(ch) sat). As dened in Chapter 2, the drain-depletion charge is assigned to the drain, which includes charge components of both triode region and saturation region, hence thereby charge neutrality is followed. All evaluated charge components associated with the saturation region is added to their respective triode-region components to give the total charge associated with the terminal, as follows: ,(A-8) ,(A-9) ,,(A-10) .(A-11) Q Gf sat W g C oxf V GfS F GfB f 0 0 y ()Df y () [] ydL gch L g= Q ch sat W g Q ch y () yd0 L g= W g L g L gch () Q ch L gch () @ Q Gf Q Gf L g V DSeff () () Q Gf sat + = Q Sch () Q Sch () L g V DSeff () () Q Sch () sat + = Q Dch () Q Dch () L g V DSeff () () Q Dch () sat Q Ddep () ++ = Q Gb Q Gf Q Sch () Q Dch () Q B +++ () =

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93 A-3 Weak-Inversion Inner Fringe Charge Model UFDGsbasicfringe-capacitancemodel[29]isbasedonthesolutionofLaplaceequation between two conducting plates separated by an angle. For example, UFDG calculates the innerfringecapacitancebetweensourceandthegatebyassumingsourceandgatetobetwoconducting plates,andsolvingtheLaplaceequationbetweenthetwointheweak-inversionregion.However, in nanoscale DG MOSFETs, the electric-elds originating from the depletion charge in the drain can signicantly inuence the solution of Laplaces equation between the source and the gate. This inadequacy in the inner-fringe capacitance model was identied by the VDS-dependent nonphysical dip in the UFDG-predicted CG-VGS characteristics in the moderate-inversion region. UFDG xes this inadequacy by quasi-physically assigning a depletion charge to the drain, and imaging it in the gate. This drain-depletion charge is modeled as, .(A-12) Thedrain-depletionchargein(A-12)isimagedinthefrontandbackgateequally.Qifisa tuning parameter, and Leff is the effective channel length of the MOSFET [26] in the weakinversion region. This formalism effectively removes the dip in the CG-VGS characteristics and signicantly improves the spline linking the weakand strong-inversion region formalism. A-4 DIBL-Dependent Denition of VTWInUFDG,anovelcubicsplineintermsofboththefront-andback-gatebiasisusedtolink the rigorous weakand strong-inversion formalism. For physics-based compact modeling, the MOSFET IDS-VGS characteristics are generally partitioned into four regions of operation: accumulation, weak inversion, moderate inversion, and strong inversion. This division of the IDSVGS characteristics facilitates developing rigorous analytical models based on approximations valid only in the given region. Because both the 2-D effects and the inversion carrier density are Q Ddep () if Q if W g e Si t Si V DS L eff --------------------------------------------=

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94 important in the moderate-inversion region, analytical modeling of this region is formidable. Hence, in general, it is modeled via smoothing functions or a polynomial spline that link the rigorous weakand strong-inversion region formalisms. For a polynomial spline, one needs to know the gate voltages at the boundaries of the moderate-inversion region, and IDS and gm at those gate voltages. For classical devices, Tsividis quantitatively characterized the noted boundaries of the moderate-inversion region in terms of the inversion capacitance, depletion capacitance, and the gate-oxide capacitance. It is based on the exponential dependence of the inversion charge on the gate bias for the weak-inversion region, and on the linear dependence for the strong-inversion region. In UFDG we modify this characterization for the nonclassical devices. The gate bias at the boundary corresponding to the weak inversion (VTW) and strong inversion (VTS), must always be evaluated rst in order to determine which region of operation a given gate bias corresponds to. In UFDG we model boundaries of the moderate-inversion region byequatingtwoexpressionoftheinversion-regionchargedensityattheboundaries.Therstone is dened by the (1-D) Gausss law in the intrinsic body, and the second expression is an approximationbasedonthelinearpotentialdistributiongivenbythespatiallyconstanttransverse electric eld for the undoped body/channel. However, we have discovered that for nanoscale DG MOSFETs, 1-D analysis does not adequately characterizes the inversion-charge density in the channel, and DIBL must be accounted for in the model. TomodelDIBL[45],wewrite f (x,y)= f0(x,y)+ Df (x,y),where f0(x,y)isthesolution of the potential with VDS = 0, and Df (x, y) is the perturbation in the potential due to drain bias, which, for weak inversion, with undoped body, satises .(A-13) x 2 2 Df xy (,) y 2 2 Df xy (,) +0 =

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95 We separate the two partial derivatives assuming, ,(A-14) where h0 is a spatial constant. Then, integrating twice along the channel, with the boundary conditions Df (y = 0) = 0 and Df (y = Leff) = VDS yields h0 = 2VDS/Leff 2, where Leff is the effectivechannellengthofthedevicethatgovernsthe2-DeffectsintheUTB,andthatisdened by the source/drain doping prole. Then by integrating (A-14) twice along the lm we obtain, ,(A-15) and, ,(A-16) where Df(sf)and Df(sb)aretheperturbationsoftheminimumsurfacepotentials(iny)atthefront and back surfaces. In UFDG we account for DIBL in the denition of VTW by perturbing Df (0) by(A-15)and(A-16).NotethatSCEstendtosubsideatthemoderate/strong-inversionboundary duetostrongtransverseelectriceld.Therefore,modelforevaluationofVTSdoesnotneedstobe altered. x 2 2 Df xy (,) y 2 2 Df xy (,) h 0 == Df sb () C b C ob C b + ----------------------Df sf () 1 C ob C b + ----------------------e Si t Si h 0 2 --------------------+ = Df sf () C ob2C b+C b C ofCob+ CobCof+ ------------------------------------------------------------------------e Si t Si h 0 2 --------------------=

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96 LIST OF REFERENCES [1]International Technology Roadmap for Semiconductors, Semiconductor Industry Association, Austin, TX, 2005. [2]J.G.Fossum,L.Q.Wang,J-W.Yang,S.-H.Kim,andV.P.Trivedi,Pragmaticdesign of nanoscale multi-gate CMOS, IEDM Tech. Dig. pp. 613-616, Dec. 2004. [3]Itr05V. P. Trivedi, J. G. Fossum, and W. Zhang, Threshold voltage and bulk inversion effects in nonclassical CMOS devices with undoped ultra-thin bodies, Solid-State Electronics pp. 170-178, Jan 2007. [4]D.Boyle etal. ,Tri-GateFully-DepletedCMOSTransistor:Fabrication,Design,Layout, Symp. VLSI Tech. Dig., pp. 133-134, 2003. [5]T.-S.Park,E.Yoon,andJ.-H.Lee.A40nmbody-tiedFinFET(OMEGAMOSFET) using bulk Si wafer. Physica E vol 19, no. 1, pp. 6-12, Jul 2003. [6]T.-S.Park etal. ,Fabricationofbody-tiedFinFETs(OMEGAMOSFET)usingbulk Si wafer. in VLSI Symp. Tech. Dig., pp. 135-136, 2003. [7]M. Poljak, V. Jovanovic, and T. Suligoj, Technological constraintes of bulk FinFET structure in comparision with SOI FinFET, ISDRS Tech. Dig., pp. 1-2, Dec 2007. [8]W. Zhang, J. G. Fossum, L. Mathew, and D. Yang, Physical Insights Regarding Desing and Performance of Independent-Gate FinFETs, IEEE Trans. Electron Devices vol. 52, pp. 2198-2206, Oct 2005. [9]W. Zhang, J. G. Fossum, and L. Mathew, The ITFET: A Noverl FinFET-Based Hybrid Device, IEEE Trans. Electron Devices vol. 53, pp. 2335-2343, Sept 2006. [10]M. M. Chowdhury and J. G. Fossum, Physical Insights on Electron Mobility in Contemporary FinFETs, IEEE Electron Device Lett. vol. 27, pp. 482-485, June 2006. [11]His98M. M. Chowdhury, V. P. Trivedi, J. G. Fossum, and L. Mathew, Carrier mobility/ transport in undoped-UTB DG FinFETs, IEEE Trans. Electron Devices vol. 54, pp. 1125-1131, May 2007. [12]Hua99J. G. Fossum and S. Chouksey, Modeling of Saturation-Region Characteristics of NanoscaleDouble-GateMOSFETs, Tech.Proc.2007NanotechnologyConf.(Vol.3WCM) pp. 510-511, May 2007. [13]Zha06L.Ge,J.G.FossumandB.Liu,Physicalcompactmodelingandanalysisofvelocity overshoot in extremely scaled CMOS devices and circuits, IEEE Trans. Electron Devices vol. 48, pp. 2074-2080, Sept. 2001. [14]Mat06aJ. G. Fossum et al. A Process/Physics-Based Compact Model for Nonclassical CMOS Device and Circuit Design, Solid-State Electronics. vol. 48, pp. 919-926, June 2004.

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97 [15]J. G. Fossum et al. Recent Upgrades and Applications of UFDG, Tech. Proc. 2006 Nanotechnology Conf. (WCM) pp. 674-679, May 2006. [16]J.G.Fossum,UFDGMOSFETMODEL(Ver.3.7)UsersGuide,SOIGroup,Univ. Florida, Gainesville, July 2007. [17]S. -H. Kim, and J. G. Fossum, Design Optimization and Performance Projections of Double-Gate FinFETs With Gate-Source/Drain Underlap for SRAM Application, IEEE Trans. Electron Devices vol. 54, pp. 1934-1942, Aug 2007. [18]H. -Yu Chen et al. Novel 20nm Hybrid SOI/Bulk CMOS Technology with 0.183mm2 6T-SRAM Cell by Immersion Lithography, Symp. VLSI Tech. Dig., pp. 16-17, 2005. [19]Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices New York: Cambridge University Press, 1998. [20]Ngu08S. Veeraraghavan and J. G. Fossum, A Physical Short-Channel Model for the ThinFilm SOI MOSFET Applicable to Device and Circuit CAD, IEEE Trans. Electron Devices vol. 35, pp. 1866-1875, Nov. 1988. [21]F.M.KlaassenandW.C.J.deGroot,ModellingofScaled-DownMOSTransistors, Solid-State Electronics vol. 23, pp. 237-242, Mar. 1980. [22]L. Mathew (Freescale Semiconductor), private communication, Dec. 2006. [23]Tri03S.-H Kim, J. G. Fossum, and V. P. Trivedi, Bulk inversion in FinFETs and implied insights on effective gate width, IEEE Trans. Electron Devices vol. 52, pp. 19931997, Sept 2005. [24] Medici-4.0 Users Manual Synopsys, Inc., Durham, NC, 2004. [25]Tri05bM.-H. Chiang, Process-Based Compact Modeling and Analysis of Silicon-on-Insulator CMOS Devices and Circuits, Including Double-Gate MOSFETs Ph.D. Dissertation, Univ. Florida, Gainesville, 2001. [26]V.P.TrivediandJ.G.Fossum,NanoscaleFinFETswithgate-source/drainunderlap, IEEE Trans. Electron Devices vol. 52, pp. 56-62, Jan 2005. [27]Lee05L.GeandJ.G.Fossum,Analyticalmodelingofquantizationandvolumeinversionin thinSi-lmDGMOSFETs, IEEETrans.ElectronDevices ,vol.49,pp.287-294,Feb. 2002. [28]Kim06V. P. Trivedi and J. G. Fossum, Quantum-mechanical effects on threshold voltage of undobed double-gate MOSFETs, IEEE Electron Device Lett. vol. 26, p. 579-582, Aug. 2005. [29]Man07S.-H. Kim, J. G. Fossum, and J. Yang, Modeling and signicance of fringe capacitance in nonclassical CMOS devices with gate-source/drain underlap, IEEE Trans. Electron Devices vol. 53, pp. 2143-2150, Sept. 2006.

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98 [30]Moh03L. Mathew et al. Double-Gate CMOS Technology with Sub-Lithographic (<20nm), 100nm Tall, Undoped Channel, TiN+HfxZr1-xO2 Gate, Multiple Silicided Source/ Drain with Record PMOS Ion/Ioff, Proc. IEEE Si Nanoelectronics Workshop June 2007, pp. 100-101. [31]Zhu04M.-H. Chiang, J.-N. Lin, K. Kim, and C.-T. Chuang, Random Dopant Fluctuation in Limited-Width FinFET Technologies, IEEE Trans. Electron Devices vol. 54, pp. 2055-2060, Aug 2007. [32]Fis01D.J.Frank,Y.Taur,M.Ieong,andH.-S.P.Wong,MonteCarloModelingofThreshold Variation Due to Dopant Fluctuations, Symp. VLSI Tech. Dig., pp. 169-170, June 1999. [33]J. G. Fossum, L. Ge, and M.-H Chiang, Speed Superiority of Scaled Double-Gate CMOS, IEEE Trans. Electron Devices vol. 49, pp. 808-811, May. 2002. [34]T. C. Lim, and G. A. Armstrong, Scaling issues for analogue circuits using Double Gate SOI transistors, Solid-State Electronics. vol. 51, pp. 320-327, Feb 2007. [35]V. Subramaniam et al. Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective, IEEE Trans. Electron Devices vol. 53, pp. 3071-3079, Dec 2006. [36]A. Chatterjee et al. Transistor Design Issues in Integrating Analog Functions with High performance Digital CMOS, Proc. VLSI Symp. Tech. pp. 147-148, June 1999. [37] Internat. Tech. Roadmap for Semiconductors Semiconductor Industry Assoc., http:// public.itrs.net, 2008. [38]J. Kedzierski et al. High-performance symmetric-gate and CMOS-compatible Vtassymteric-gate FinFET devices, IEDM Tech. Dig. p. 437-440, Dec. 2001. [39]Tau98R.Tsuchiya et al. Silicon on Thin Box: a new paradigm of the CMOSFET for lowpowerhigh-performanceapplicationsfeaturingwide-rangeback-biascontrol, IEDM Tech. Dig. p. 631-634, Dec. 2004. [40]Rib05O.Weber etal. ,Highimmunitytothresholdvoltagevariabilityinundopesultra-thin FDSOI MOSFETs and its physical understandins, IEDM Tech. Dig., p. 245-248, Dec. 2008. [41]S. Monfray et al. Proc. EUROSOI Conf. p. 107-108, Jan. 2009. [42]P. Scheiblin et al. Proc. EUROSOI Conf. p. 109-110, Jan. 2009. [43]G. G. Shahidi, FDSOI for Low Power CMOS, IEEE SOI Conf. Tech. Dig. ,p. 1-2, Oct. 2009. [44] Taurus-2006 Users Manual Synopsys, Inc., Durham, NC, 2006. [45]V. P. Trivedi and J. G. Fossum, Scaling fully depleted SOI CMOS, IEEE Trans. Electron Devices vol. 50, p. 2095-2103, Oct. 2003.

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99 [46]P.C.YehandJ.G.Fossum,Physicalsubthresholdmodelingappliedtoviabledesign deepsubmicrometerfullydepletedSOIlow-voltageCMOStechnology, IEEETrans. Electron Devices vol. 42, p. 1605-1613, Sept. 1995. [47]Yin05A. Majumdar et al. Gate Length and Performace Scaling of Undoped-Body Extremely Thin SOI MOSFETS, IEEE Electron Device Lett. vol. 30, p. 413-415, Apr. 2009. [48]J.G.Fossum,PhysicalInsightsonnanosclaemulte-gateCMOSdesign, Solid-State Electronics vol. 51, p. 188, Feb. 2007. [49]J. Kedzierski et al. Multi-gate FinFET and fully-depleted SOI devices using total gate silicidation, IEDM Tech. Dig. p. 247, Dec. 2002. [50]J. -W Yang and J. G. Fossum,. On the Feasibility of Nanoscale Triple-Gate CMOS Transistors, IEEE Trans. Electron Devices vol. 52, pp. 1159-1164, Jun 2005. [51]R. Yan et al. LDD Depletion Effects in Thin-BOX FDSOI Devices with a Ground Plane IEEE SOI Conf. Tech. Dig., pp. 53-54, 2003. [52]T. -J. K. Liu et al. SRAM Cell Design Considerations for SOI Technology IEEE SOI Conf. Tech. Dig., pp. 27-33, 2003. [53]C.Shin etal. ,SRAMYieldenhancementwithThin-BOXFD-SOI IEEESOIConf. Tech. Dig., pp. 37-38, 2003.

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100 BIOGRAPHICAL SKETCH Siddharth Chouksey was born in Betul, India in 1983. He received the Bachelor of Technology in information and communication technology from Dhirubhai Ambani Institute of InformationandCommunicationTechnology(DA-IICT),Gandhinagar,Indiain2005.Hedidhis Doctor of Philosophy in electrical and computer engineering at the University of Florida, Gainesville. His research interest concerns device theory, modeling and design of non-classical silicon-on-insulator (SOI) and multi-gate MOSFET, for both digital and analog applications. In summer of 2008 and 2009, he interned in the Components Research Group at Intel, Hillsboro, OR,wherehewasactivelyinvolvedinthedesignofnovelnanoscaleoating-bodymemorycells.