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Fabrication and Characterization of Oxide-Based Thin Film Transistors and Process Development for Oxide Heterostructures

Permanent Link: http://ufdc.ufl.edu/UFE0024252/00001

Material Information

Title: Fabrication and Characterization of Oxide-Based Thin Film Transistors and Process Development for Oxide Heterostructures
Physical Description: 1 online resource (146 p.)
Language: english
Creator: Lim, Wantae
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: etching, icp, ingazno, ohmic, plasma, sputtering, tft
Materials Science and Engineering -- Dissertations, Academic -- UF
Genre: Materials Science and Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation is focused on the development of thin film transistors (TFTs) using oxide materials composed of post-transitional cations with (n-1)d10ns0 (n > 4). The goal is to achieve high performance oxide-based TFTs fabricated at low processing temperature on either glass or flexible substrates for next generation display applications. In addition, etching mechanism and Ohmic contact formation for oxide heterostructure (ZnO/CuCrO2) system is demonstrated. The deposition and characterization of oxide semiconductors (In2O3-ZnO, and InGaZnO4) using a RF-magnetron sputtering system are studied. The main influence on the resistivity of the films is found to be the oxygen partial pressure in the sputtering ambient. The films remained amorphous and transparent ( > 70%) at all process conditions. These films showed good transmittance at suitable conductivity for transistor fabrication. The electrical characteristics of both top- and bottom-gate type Indium Zinc Oxide (InZnO) and Indium Gallium Zinc Oxide (InGaZnO4)-based TFTs are reported. The InZnO films were favorable for depletion-mode TFTs due to their tendency to form oxygen vacancies, while enhancement-mode devices were realized with InGaZnO4 films. The InGaZnO4-based TFTs fabricated on either glass or plastic substrates at low temperature ( < 100degreeC) exhibit good electrical properties: the saturation mobility of 5-12 cm2.V-1.s-1 and threshold voltage of 0.5-2.5V. The devices are also examined as a function of aging time in order to verify long-term stability in air. The effect of gate dielectric materials on electrical properties of InGaZnO4-based TFTs was investigated. The use of SiNx film as a gate dielectric reduces the trap density and the roughness at the channel/gate dielectric interface compared to SiO2 gate dielectric, resulting in an improvement of device parameters by reducing scattering of trapped charges at the interface. The quality of interface is shown to have large effect on TFT performance. Plasma etching process of ZnO was carried out using a variety of plasma chemistries: CH4/H2-, C2H6/H2-, Cl2-, IBr-, ICl-, BI3- and BBr3/Ar. High fidelity pattern transfer can be achieved with practical etch rate and very smooth surface in methane-based chemistries, although the sidewall is not completely vertical. Threshold energy as low as 60 ? 20 eV for all plasma chemistries was achieved, confirming that etching is driven by ion-assisted mechanism over the whole range of ion energy. Ohmic contacts to p-CuCrO2 are examined using borides (CrB2 and W2B5), nitrides (TaN and ZrN) and a high temperature metal (Ir). These materials are used as a diffusion barrier in Ni/Au based contacts, i.e., Ni/Au/X/Ti/Au metallization scheme, where X is the refractory material. A minimum specific contact resistance of ~ 5?10-4 ?.cm2 was achieved for the Ir-containing contacts after annealing at temperature of 500-800degreeC for 60s in O2 ambient. The presence of Ir diffusion barrier increase the thermal stability of the contacts by ~ 200 degreeC compared to conventional Ni/Au contacts. By sharp contrast, the use of other refractory materials led to the poorer thermal stability, with the contact resistance increasing sharply above 400degreeC.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Wantae Lim.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Pearton, Stephen J.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0024252:00001

Permanent Link: http://ufdc.ufl.edu/UFE0024252/00001

Material Information

Title: Fabrication and Characterization of Oxide-Based Thin Film Transistors and Process Development for Oxide Heterostructures
Physical Description: 1 online resource (146 p.)
Language: english
Creator: Lim, Wantae
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: etching, icp, ingazno, ohmic, plasma, sputtering, tft
Materials Science and Engineering -- Dissertations, Academic -- UF
Genre: Materials Science and Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Abstract: This dissertation is focused on the development of thin film transistors (TFTs) using oxide materials composed of post-transitional cations with (n-1)d10ns0 (n > 4). The goal is to achieve high performance oxide-based TFTs fabricated at low processing temperature on either glass or flexible substrates for next generation display applications. In addition, etching mechanism and Ohmic contact formation for oxide heterostructure (ZnO/CuCrO2) system is demonstrated. The deposition and characterization of oxide semiconductors (In2O3-ZnO, and InGaZnO4) using a RF-magnetron sputtering system are studied. The main influence on the resistivity of the films is found to be the oxygen partial pressure in the sputtering ambient. The films remained amorphous and transparent ( > 70%) at all process conditions. These films showed good transmittance at suitable conductivity for transistor fabrication. The electrical characteristics of both top- and bottom-gate type Indium Zinc Oxide (InZnO) and Indium Gallium Zinc Oxide (InGaZnO4)-based TFTs are reported. The InZnO films were favorable for depletion-mode TFTs due to their tendency to form oxygen vacancies, while enhancement-mode devices were realized with InGaZnO4 films. The InGaZnO4-based TFTs fabricated on either glass or plastic substrates at low temperature ( < 100degreeC) exhibit good electrical properties: the saturation mobility of 5-12 cm2.V-1.s-1 and threshold voltage of 0.5-2.5V. The devices are also examined as a function of aging time in order to verify long-term stability in air. The effect of gate dielectric materials on electrical properties of InGaZnO4-based TFTs was investigated. The use of SiNx film as a gate dielectric reduces the trap density and the roughness at the channel/gate dielectric interface compared to SiO2 gate dielectric, resulting in an improvement of device parameters by reducing scattering of trapped charges at the interface. The quality of interface is shown to have large effect on TFT performance. Plasma etching process of ZnO was carried out using a variety of plasma chemistries: CH4/H2-, C2H6/H2-, Cl2-, IBr-, ICl-, BI3- and BBr3/Ar. High fidelity pattern transfer can be achieved with practical etch rate and very smooth surface in methane-based chemistries, although the sidewall is not completely vertical. Threshold energy as low as 60 ? 20 eV for all plasma chemistries was achieved, confirming that etching is driven by ion-assisted mechanism over the whole range of ion energy. Ohmic contacts to p-CuCrO2 are examined using borides (CrB2 and W2B5), nitrides (TaN and ZrN) and a high temperature metal (Ir). These materials are used as a diffusion barrier in Ni/Au based contacts, i.e., Ni/Au/X/Ti/Au metallization scheme, where X is the refractory material. A minimum specific contact resistance of ~ 5?10-4 ?.cm2 was achieved for the Ir-containing contacts after annealing at temperature of 500-800degreeC for 60s in O2 ambient. The presence of Ir diffusion barrier increase the thermal stability of the contacts by ~ 200 degreeC compared to conventional Ni/Au contacts. By sharp contrast, the use of other refractory materials led to the poorer thermal stability, with the contact resistance increasing sharply above 400degreeC.
General Note: In the series University of Florida Digital Collections.
General Note: Includes vita.
Bibliography: Includes bibliographical references.
Source of Description: Description based on online resource; title from PDF title page.
Source of Description: This bibliographic record is available under the Creative Commons CC0 public domain dedication. The University of Florida Libraries, as creator of this bibliographic record, has waived all rights to it worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law.
Statement of Responsibility: by Wantae Lim.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: Pearton, Stephen J.

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0024252:00001


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1 FABRICATION AND CHARACTERIZATION OF OXIDE BASED THIN FILM TRANSISTORS, AND PROCESS DEVELOPMENT FOR OXIDE HETEROSTRUCTURES By WANTAE LIM A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTI AL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2009

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2 2009 Wantae Lim

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3 To my parents, wife Hyekyung and loving daughter, Kate and son, Kaden

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4 ACKNOWLEDG MENTS First and foremost, I would like to thank my advisor and committee chairman Dr. Stephen J. Pearton for all the opportunit ies guidance and support that enabled me to improve in all areas both professionally and personally I am really honored to hav e been a member of his research group and to have worked with him. His advice and encouragement regarding this research were invaluable to me. I also thank Dr. David P. Norton, Dr. Brent P. Gila and Dr. Rajiv Singh for serving on my supervisory committee m embers and for their time and help. I especially thank Dr. Fan Ren for serving as my external committee member. I am very grateful for his support and advice on my professional development. Many thanks go to Dr. Jewon Lee for introducing me to the field o f semiconductor s during my undergraduate days in Korea and for recommending Materials Science and Engineering as a potential area of graduate study. I would like to thank members of Dr. Pearton, Dr. Norton, and Dr. Ren research groups for their help and friendship especially Dr. Luc Stafford, Rohit Khanna, Lars Voss, Jon Wright, Erica Douglas, David Cheney, Mat hew Ivill Patrick Sadick, Hyunsik Kim, Dr. Byungsam Kang, Jau Jiun Chen, Soohwan Jang, HungTa Wang, Travis Anderson, Yu Lin Wang, Chih Yang Chan g, Ke Hung Chen, Byung Hwan Chu, and Chien-Fong Lo. I also acknowledge Ms. Paula Mathis for helping me with a lot of paperwork on purchase orders and travel arrangements, and Dr. Ivan Kravchenko and Bill Lewis for their support in UF Nanofabrication facili ty. Special thanks go to SeungYong Son and Junhan Yuh for their camaraderie throughout my graduate school experience, e specially for all of the hours of fun we have shared. I also thank all of the Korean students (Junghoon Jang, Jaewon Lee, and many othe rs) I had a wonderful time to work and play with while in Gainesville.

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5 Finally, and most importantly, I express my deepest gratitude to my family for their undying love and encouragement I especially thank my wife Hyekyung Koo for her support and trust that have given me great self -confidence. If not for her help, I would never have ended up at UF. Half of all of my research is her achievement. Thanks also go to my lovely daughter, Kat herin e, and my son, Kaden.

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6 TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................................... 4 LIST OF TABLES ................................................................................................................................ 9 LIST OF FIGURES ............................................................................................................................ 10 ABSTRACT ........................................................................................................................................ 14 CHAPTER 1 INTRODUCTION ....................................................................................................................... 16 2 BACKGROUND ......................................................................................................................... 19 2.1 Transparent Conducting Oxides ........................................................................................... 19 2.1.1 Zinc Oxide .................................................................................................................. 20 2.1.2 Copper Chromium Oxide ........................................................................................... 21 2.2 Amorphous Oxide Semiconductors ..................................................................................... 22 2.2.1 Indium Gallium Zinc Oxide ....................................................................................... 23 2.2.2 Indium Zinc Oxide ..................................................................................................... 23 2.3 Amorphous Oxide -based Thin Film Transistors ................................................................. 24 2.4 Processing Techniques .......................................................................................................... 26 2.4.1 Plasma Etching ........................................................................................................... 26 2.4.2 Ohmic Contacts .......................................................................................................... 29 2.4.3 Sputtering System ....................................................................................................... 31 2.4.4. E Beam Evaporator system ...................................................................................... 32 2.4.5. Rapid Thermal Annealing ......................................................................................... 32 2.5 Characterization Techniques ................................................................................................ 33 2.5.1. Hall Effect Measurement .......................................................................................... 33 2.5.2 Stylus Profilometry .................................................................................................... 34 2.5.3 Scanning Electron Microscopy.................................................................................. 34 2.5.4 Atomic Force Microscopy ......................................................................................... 35 2.5.5 Auger Electron Spectroscopy .................................................................................... 35 2.4.6 Photoluminescence ..................................................................................................... 35 2.4.7 Electrical Measurements ............................................................................................ 36 3 HIGH DENSITY INDUCTI VELY COUPLED PLASMA ETCHING OF BULK ZINC OXIDE AND INDIUM ZINC OXIDE FILM ........................................................................... 46 3.1 Introduction ........................................................................................................................... 46 3.2 Experimental ......................................................................................................................... 47 3.3 Results and Discussion ......................................................................................................... 48 3.4 Conclusions ........................................................................................................................... 52

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7 4 OHMIC CONTACTS TO p CuCrO2......................................................................................... 62 4.1 Introduction ........................................................................................................................... 62 4.2 Experimental ......................................................................................................................... 63 4.3 Ni/Au Ohmic Co ntacts ......................................................................................................... 64 4.3.1 Results and Discussion............................................................................................... 64 4.3.2 Conclusions ................................................................................................................. 66 4 .4 Ir Diffusion Barrier in Ni/Au Ohmic Contacts ................................................................... 66 4.4.1 Results and Discussion............................................................................................... 66 4.4.2 Conclusions ................................................................................................................. 68 5 ROOM TEMPERATURE DEPOSITED INDIUM ZINC OXIDE THIN FILMS WITH CONTROLLED CONDUCTIVITY .......................................................................................... 80 5.1 Introduction ........................................................................................................................... 80 5.2 Experimental ......................................................................................................................... 81 5.3 Results and Discussion ......................................................................................................... 81 5.4 Conclusions ........................................................................................................................... 83 6 InGaZnO BASED THIN FILM TRANSISTORS FABRICATED ON GLASS SUBSTRATE AT LOW TEMPERATURE .............................................................................. 88 6.1 Introduction ........................................................................................................................... 88 6.2 Experimental ......................................................................................................................... 89 6.3 Results and Discussion ......................................................................................................... 90 6.3.1 TFTs with SiNx Gate Dielectric ................................................................................ 90 6.3.2 TFTs with HfO2 Gate Dielectric ................................................................................ 92 6.4 Conclusions ........................................................................................................................... 93 7 INTERFACE DEPENDENT ELECTRICAL P ROPERTIES OF AMORPHOUS InGaZnO THIN FILM TRANSISTORS ................................................................................. 102 7.1 Introduction ......................................................................................................................... 102 7.2 Experimental ....................................................................................................................... 103 7.3 Results and Discussion ....................................................................................................... 104 7.4 Conclusions ......................................................................................................................... 106 8 FABRICATION OF THIN FILM TRANSISTORS ON FLEXIBLE SUBSTRATES ........ 113 8.1 Introduction ......................................................................................................................... 113 8.2 InGaZnO TFTs on PET substrates ..................................................................................... 114 8.2.1 Experimental ............................................................................................................. 114 8.2.2 Results and Discussion............................................................................................. 114 8.2.3 Conclusions ............................................................................................................... 116 8.3 InGaZnO TFTs on Polyimide Clean Room Tape ............................................................. 117 8.3.1 Experimental ............................................................................................................. 117 8.3.2 Results and Dis cussion ............................................................................................. 117 8.3.3 Conclusions ............................................................................................................... 118

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8 8.4 InGaZnO TFTs on C ellulose P aper ................................................................................... 119 8.4. 1 Experimental ............................................................................................................. 119 8.4.2 Results and Discussion............................................................................................. 120 8.4.3 Conclusions ............................................................................................................... 121 9 CONCLUSIONS ....................................................................................................................... 135 LIST OF REFERENCES ................................................................................................................. 138 BIOGRAPHICAL SKETCH ........................................................................................................... 146

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9 LIST OF TABLES Table page 2 1 Properties of n -type transparent conducting oxides ............................................................. 37 2 2 Properties of p -type transparent co nducting oxides ............................................................. 38 2 3 Basic physical properties of ZnO .......................................................................................... 39 3 1 Characteristics of as -deposited InZnO layers ....................................................................... 54 4 1 Concentration and elements detected on the surface (in At. %) ......................................... 69 7 1 The fitted XRR results of different gate dielectrics/InGaZnO .......................................... 107

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10 LIST OF FIGURES Figure page 2 1 Crystal structure of ZnO. ....................................................................................................... 40 2 2 CuMO2 in delafossite stru cture, where Cu is small dark spheres coordinated to two oxygen atoms (large dark spheres) and M is a trivalent cation (small light spheres). ....... 41 2 3 Schematic of ICP reactor. ...................................................................................................... 42 2 4 Electric and magnetic filed inside the reactor ...................................................................... 42 2 5 Chemical etching process. (a) Generation of reactive species. (b) Diffusion (c) Ads orption (d) Chemical reaction (e) Desorption (f) Diffusion of byproducts ................. 43 2 6 Physical etching process (left) and combination of chemical and physical etching process (right). ........................................................................................................................ 43 2 7 Ideal nonrectifying contacts between a metal and n or p type semiconductor. ............... 44 2 8 A schematic of Hall effect. .................................................................................................... 45 2 9 AES process: (a) inner core level electron dislodged (b) an outer level electron fills the vacancy and releases energy (c) the excess energy ejects an Auger electron. ............. 45 3 1 Etch rate of ZnO and InZnO as a function of Ar concentration in (a) Ar/IBr and (b) Ar/BI3. ..................................................................................................................................... 55 3 2 Etch rate of ZnO and InZnO as a function of ICP source power in (a) Ar/IBr and (b) Ar/BI3 ...................................................................................................................................... 56 3 3 Etch rate of ZnO as a function of the square root of ion energy in Ar/IBr and Ar/BI3. ... 57 3 4 Etch rate of I nZnO 1 as a function of the square root of the ion energy in Ar/IBr and Ar/BI3.. .................................................................................................................................... 58 3 5 AFM scans from ZnO surfaces before and after etching in Ar/IBr for different RF powers : 1 00 W, 150 W, and 300 W. .................................................................................... 59 3 6 AES depth profiles of ZnO before and after etching in Ar/IBr for different RF powers : 100 W, 150 W, and 300 W. .................................................................................... 60 3 7 SEM images of etched ZnO using CH4/H2/Ar discharge. The mask is a SiNx layer deposited by PECVD and patterned by photolithography and reactive ion etching. ......... 61 4 1 Influen ce of annealing temperature on I -V characteristics from (a) Ti/Au and (b) Ni/Au contacts. The inset shows I -V characteristics of sample annealed at 600 C. ........ 70

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11 4 2 Influence of annealing temper ature (bottom scale) and measurement temperature (top scale) on the specific contact resistance of Ni/Au contacts. ................................................ 71 4 3 Surface morphology of Ni/Au contacts: as deposited, 300 C, 500 C, an d 600 C annealing. ................................................................................................................................ 72 4 4 AES depth profiles from as deposited (top) and 600 C annealed (bottom) Ni/Au contacts ................................................................................................................................... 73 4 5 Specifi c contact resistance as a function of annealing temperature for Ni/Au/Ir/Au contacts on p type CuCrO2. ................................................................................................... 74 4 6 Measurement temperature dependence of the specific contact resistance for Ni/Au/Ir /Au contacts annealed at 800C. ............................................................................. 75 4 7 Optical micrographs of Ni/Au/Ir/Au contacts annealed at various temperature. ............... 76 4 8 SEM m icrographs of Ni/Au/Ir/Au contacts as -deposited and after annealing at 500C or 800 C. ................................................................................................................................ 77 4 9 AES surface scans of Ni/Au/Ir/Au contacts as -deposited and after annealing at 500 C or 800 C. ................................................................................................................... 78 4 10 AES depth profiles of Ni/Au/Ir/Au contacts as deposited and after annealing at 500 C or 800 C. ................................................................................................................... 79 5 1 Sputter depositio n rate and In/Zn ratio in InZnO films as a function of In2O3 target power or chamber working pressure. .................................................................................... 84 5 2 2O3 and InZnO films deposited at room temperature and effect of In2O3 target power on the XRD spectra from InZnO films. ........................................... 85 5 3 Resistivity,carrier concentration and electro n mobility in I n Z n O films as a function of In2O3 target power or oxygen percentage in the O2+Ar sputtering ambient. ................. 86 5 4 Specific contact resistance and sheet resistance under the contact ar ea of Ni/Au and Ti/Au Ohmic contacts on I n Z n O films deposited under different conditions .................... 87 6 1 I n G a Z n O channel transistor and an optical micrograph plan view of competed device. .................................................................................................................... 94 6 2 In G a Z n O films as a function of depositi on power. ................................................................................................................... 95 6 3 IDS-VDS characteristics and transfer characteristics -In G a Z n O transistors with 90 nm thick SiNx gate dielectric. ........................................................................................... 96 6 4 I n G a Z n O TFT as a function of W/L. .......... 97

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12 6 5 I n G a Z n O TFT as a function of a ging time. ........................................................................................................... 98 6 7 IDS-VDS characteristics and IDS and (IDS)0.5 -In G a Z n O TFT with 100 nm thick HFO2 gate dielectric. ............................................................................................................ 100 6 8 InGaZnO TFTs as a function of time. ................................................................................................................... 101 7 1 InGaZnO thin film transistor and photograph of the device. ............... 108 7 2 Refractive index and RMS roughness of three different gate dielectrics. ........................ 109 7 3 Current density -electric field characteristics of thre e different gate dielectrics measured in MIM structure. ................................................................................................ 110 7 4 InGaZnO4 TFTs with different gate dielectrics at a fixed VDS = 7V. ..................................................................................................................... 111 7 5 InGaZnO4 TFTs with SiNx gate dielectric. ..................................................................................................... 112 8 1 P hotographs of the competed device ................................................................................. 122 8 2 InGaZnO TFTs with SiO2 or SiNx gate dielectric. ............................................................................................................................... 123 8 3 InGaZnO TFTs at a fixed VDS=5V. ............................. 124 8 4 Chan InGaZnO TFTs with SiO2 gate dielectric as a function of aging time at room temperature and transfer characteristics after 500 aging time. ................................................................................... 125 8 5 InGaZnO thin film transistor and photographs of the device. ................ 126 8 6 InGaZnO TFTs with SiNx gate dielectr ic. .............................................................................................................. 127 8 7 Plan -view optical micrographs of the device before and after roll up .............................. 128 8 8 InGaZnO T FTs before and after roll up (the inset shows the output characteristics after roll up). .............................................................................. 129 8 9 InGaZnO thin film transistor and SEM plan -view image of the device. ................................................................................................................................... 130 8 10 Surface images of cellulose paper before and after channel deposition. .......................... 131

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13 8 11 The typical output characteristics of InGaZnO TFTs with 150 m -thick paper gate dielectric ................................................................................................................................ 132 8 12 InGaZnO TFTs. VGS was swept from 10 to 40V at a fixed VDS = 40V. .................................................................................................................... 133 8 13 SEM cross -section images of cellulose paper with thickness of 150 m. ........................ 134

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14 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy FABRICATIONN AND CHARACTERIZATION OF OXIDE B ASED THIN FILM TRANSISTORS, AND PROCESS DEVELOPMENT FOR OXIDE HETEROSTRUCTURES By Wantae Lim May 2009 Chair: Stephen J. Pearton Major: Materials Science and Engineering This dissertation is focused on the development of thin film transistors (TFTs) usin g oxide materials composed of post transitional cations with (n 1)d10ns0 (n 4). The goal is to achieve high performance oxide -based TFTs fabricated at low processing temperature on either glass or flexible substrates for next generation display applications In addition, etching mechanism and Ohmic contact formation for oxide heterostructure (ZnO/CuCrO2) system is demonstrated. T he deposition and characterization of oxide semiconductors (In2O3ZnO, and InGaZnO4) using a RF -magnetron sputtering system are s tudied The main influence on the resistivity of the films is found to be the oxygen partial pressure in the sputtering ambient The films remained amorphous and transparent (> 70%) at all process conditions. These films show ed good transmittance at suitab le conductivity for transistor fabrication. The electrical characteristics of both top and bottom -gate type Indium Zinc Oxide (InZnO) and Indium Gallium Zinc Oxide (InGaZnO4) -based TFTs are reported. The InZnO films were favorable for depletion -mode TFTs due to their tendency to form oxygen vacancies while enhancement -mode devices were realized with InGaZnO4 films The InGaZnO4-based TFTs fabricated on either glass or plastic substrates at low temperature (<100 C) exhibit good electrical properties: the s aturation mobility of 5 12 cm2.V1.s1 and threshold voltage of 0.5 2.5V.

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15 The devices are also examined as a function of aging time in order to verify long -term stability in air. The effect of gate dielectric materials on electrical properties of InGaZnO4based TFTs was investigated. The use of SiNx film as a gate dielectric reduce s the trap density and the roughness at the channel/gate dielectric interface compared to SiO2 gate dielectric resulting in an improvement of device parameters by reducing scat tering of trapped charges at the interface. The quality of interface is shown to have large effect on TFT performance. Plasma etching process of ZnO was carried out using a variety of plasma chemistries : CH4/H2, C2H6/H2, Cl2, IBr -, ICl -, BI3and BBr3/A r. High fidelity pattern transfer can be achieved with practical etch rate and very smooth surface in methane based chemistries, although the sidewall is not completely vertical. Threshold energy as low as 60 20 eV for all plasma chemistries was achieved confirming that etching is driven by ion assisted mechanism over the whole range of ion energy. Ohmic contacts to p -CuCrO2 are examined using borides (CrB2 and W2B5) nitrides (TaN and ZrN) and a high temperature metal (Ir). These materials are used as a diffusion barrier in Ni/Au based contact s, i.e., Ni/Au/X/Ti/Au metallization scheme, where X is the refractory material. A minimum specific contact resistance of ~ 5 104 .cm2 was achieved for the Ir containing contacts after annealing at temperature of 500800 C for 60s in O2 ambient The presence of Ir diffusion barrier increase the thermal stability of the contacts by ~ 200 C compared to conventional Ni/Au contacts. By sharp contrast, the use of other refractory materials led to the poorer thermal st ability, with the contact resistance increasing sharply above 400 C.

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16 CHAPTER 1 INTRODUCTION Beginning with the first transistor developed in 1947 at AT&T Bell Labs, the semiconductor technology has grown progressively, fabricating faster, smaller and more powerful devices Silicon (Si) -based technology has come to dominate an over whelming share of semiconductor market and for good reasons: high melting point and stable oxide that displays low leakage current even though the first transistor was made f rom Germanium (Ge) Nevertheless Si has some limitation for certain areas of applications. For high -speed and optoelectronic devices, Gallium Arsenide (GaAs) is an acceptable material. It exhibits superior electron transport properties (higher electron mo bility and effective carrier velocity than Si) and optical properties. In addition, GaAs is a direct bandgap semiconductor which is suitable for optoelectronic applications, whereas Si is indirect. However, physical properties required for high power high temperature electronics and UV/blue emitter applications are beyond the limits of Si and GaAs. It is therefore necessary to develop alternative materials and their processing techniques to achieve these devices [1, 2 ]. The wide bandgap oxide semiconductor s are promising for high temperature applications because their intrinsic carrier concentration stays at very low level at higher temperature relative to Si and GaAs. Furthermore, they exhibit inherent properties such as high breakdown field strength and high electron mobility. Recently, oxide -based semiconductors have attracted much attention because of their unique combination of electrical and optical properties. As an oxide -based wide bandgap semiconductor, ZnO (Eg ~3.37 eV) is a candidate material for blue/UV optoelect ronics, transparent electronics spintronics, and sensor applications. ZnO has the advantage of a relative low growth temperature which is suitable for deposition on cheap glass substrates and much higher excition binding energy (~ 60meV) than GaN (25meV). The excitons in the ZnO

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17 semiconductor will not dissociate into free electrons or holes due to heat at room temperature or the scattering between the excitons. ZnO system also has a simpler processing relative to GaN which can not be wet -etched in conventional acid mixture at safe temperature. Some groups have published n doped or p -doped ZnO -based p -n junction or MIS LEDs [3, 4 ]. Tsukazaki et al. studied ZnO p i -n homojunction structure on (0001) ScAlMgO4 grown by laser MBE [ 5, 6 ]. Lim et al have made p -n homojunction ZnO LED on sapphire by r -f sputtering [ 7 ]. Jiao et al have demonstrated ZnO p -n junction LED on a -plane Al2O3 substrate by plasma -assisted MBE [8]. However, much more work is needed on all aspects of ZnO -based LEDs and mate rials technology because of difficulties in obtaining robust ptype doping [6, 7, 9 -1 2 ]. Increasingly, alternative p type injection layers are being examined, including SiC, GaN, AlGaN or Cu2O. Mg -doped CuCrO2 is promising p type transparent conducting oxi de for formation of all -oxide pn junctions with numerous n-type semiconducting oxides including ZnO. It has also low resistivity, decent mobility and excellent transmission characteristics [1 3 1 6 ]. While many challenges still exist to realizing high quali ty p type oxide materials it is important to develop improved contact structures which are able to withstand high temperatures without degradation of device characteristics for longer life times In addition to the optimization of metallization the integ ration of oxide structures in devices also requires the development of high resolution pattern transfer. Among the various patterning techniques, dry etching methods produce a reliable pattern transfer in sophisticated device structures. S ignificant effort s in the last few years have been aimed at developing high efficiency blue/UV light emitters while the use of wide bandgap oxide semiconductors in display technology has allow ed for commercialization of transparent electronics. Hosono et al reported on n ovel amorphous oxide semiconductors (AOSs) such as zinc oxide (ZnO), indium gallium

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18 oxide (InGaO), indium zinc oxide (InZnO), and indium gallium zinc oxide (InGaZnO) composed of heavy metal cations with an electronic configuration of (n1)d10ns0 (n 4) [1 7 ]. Besides their transparency in the visible range, the most attractive feature is relatively high electron mobility (> 10 cm2.V1.s1) even for amorphous films deposited at room temperature. These characteristics show possible solutions to the limitations of Si -based TFTs which has some limitations, including primarily low field effect mobility (< 1 cm2.V1.s1), light sensitivity as well as device instability (china ref) In addition, t he fabrication of TFTs at temperature compatible with flexible substrates (e.g. polymer or paper) is a key technique to realize next generation electronics. The motivation s of this work are to develop reliable oxide based TFTs and to optimize plasma etching processes and Ohmic contact formation for oxide -based optoelectronic devices. The properties of transparent conducting oxides (TCOs) as well as overview of semiconductor processing and characterization are reviewed in Chapter 2. High density inductively coupled plasma etching of n type ZnO and Ohmic contacts to p type CuCr O2 are considered in Chapter 3 and Chapter 4, respectively The electrical properties of InZnO as a function of sputtering condition (power, working pressure and oxygen partial pressure) are discussed in Chapter 5. The demonstration of thin film transistor s using amorphous oxide semiconductor is given in next three chapters (6, 7 and 8)

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19 CHAPTER 2 BACKGROUND 2.1 Transparent Conducting Oxide s Transparent Conducting Oxides (TCOs) constitute a class of materials which exhibit remarkable combination of o ptical and electrical properties: high optical transparency (>80%) in the visible range as well as high electrical conductivity (~104 S .cm1) [1 8 3 5 ]. Thus, TCO materials suitable for use as thin -film transparent electrodes should have a carrier concentrat ion of the order of 1020 cm3 or higher and a large bandgap above approximately 3 eV: i.e., degenerated n type or ptype semiconductors. In these materials, n type conduction is derived from two sources : the creation of p oint defects (such as oxygen vacanc ies and/or metal interstitials) and extrinsic substitutional doping (typically on the cation site). The intrinsic defects as a primary source of conduction can be modified by appropriate selection of processing parameters such as oxygen partial pressure T COs are widely used as passive applications: transparent electrodes in various optoelectronic devices such as liquid crystal displays (LCDs), organic LEDs and solar cells. Table 2 1 contains some basic properties of various n type TCO materials. Although the TCOs have a vast range of applications as mentioned above, very little work has been done on active device fabrication using TCOs because of the inherent nature of TCO semiconductors [3 6 3 7 ]. But in 1997, Kawazoe et al from Tokyo Institute of Technol ogy reported p type conductivity in a highly transparent thin film of copper aluminum oxide (CuAlO2 + x) [ 3 8 ]. This has opened up a new field in optoelectronics device technology, the so called Transparent Electronics or Invisible Electronics [39]. p type conducting thin film of nickel oxide (NiO) was published in 1993 by Sato et al. [40] from Kanazawa Institute of Technology, Japan. They observed about 40% transmittance of the

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20 NiO films in the visible region and when they tried to fabricate an all T CO p i -n diode of the form p NiO/i NiO/i ZnO/n ZnO, the visible transmittance further reduced to almost 20%. Although this low transmittance was not favorable for superior device applications, nevertheless the report was an important milestone in the field of Transparent Electronics and in the development of TCO technology. Table 2 2 represents the optoelectrical properties of p type TCO materials. 2.1.1 Zinc Oxide Zinc oxide is one of the most widely used oxide semiconductors. In addition to its utilization as a TCO material, ZnO has numerous attractive characteristics for electronic and optoelectronic devices. It has a direct and wide bandgap of 3.37 eV, which makes it transparent in the visible range and operates in the UV/blue wave length. The exci ton binding energy is ~ 60 meV for ZnO, as compare to GaN ~ 25 meV; the higher exciton binding energy enhances the luminescence efficiency of light emission. One of the most attractive feature s of ZnO is the ability to bandgap tuning via divalent substitut ion on the cation site to form heterostructure. Bandgap energy of ~ 3 eV can be achieved by doping with Cd2+, while Mg2+ increases the bandgap energy to ~ 4 eV. ZnO has wurtzite crystal structure with a lattice constant a = 3.253 and c = 5.211 giving c / a ratio of 1.602, as depicted in Figure 2 1. Zinc oxide is composed of alternate layers of zinc and oxygen atoms in the (0001) direction ( c axis) of the crystal. The bonding between zinc and oxygen atoms is highly ionic due to the large difference in th eir electronegative values (1.65 for Zn and 3.44 for O). Its physical pr operties are listed in Table 2 3 Commercial bulk crystalline ZnO is available. These high quality films are grown using a chemical vapor phase transport method, melt grown technique, or hydrothermal method. ZnO

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21 thin films also can be deposited using a number of methods: sputtering (DC or RF), spray pyrolysis, metalorganic chemical vapor deposition (MOCVD), and spin coating. ZnO is typically n type semiconductor, due to its inherent n ature to form oxygen deficient films. The electron mobility at room temperature in single crystal n type ZnO is ~ 200 cm2.V1.s1, slightly lower than that of GaN; reported electron mobility for ZnO thin film is typically 20 30 cm2.V1.s1. Even though rec ent reports have demonstrated p -type doping of the material, robust and reproducible p type ZnO remain elusive because of self -compensation and low solubility of the acceptor dopants thus hall mobility and effective masses are still in debate. 2.1.2 Coppe r Chromium Oxide Doped p type TCO materials have been reported which include iron doped copper gallium oxide (CuGaO2:Fe), calcium doped copper indium oxide (CuInO2:Ca), magnesium doped copper scandium oxide (CuScO2:Mg), magnesium doped copper chromium oxid e (CuCrO2:Mg), and copper calcium doped copper yttrium oxide (CuYO2:Ca). Recently, CuCr1 xMgxO2 bas been shown to exhibit relatively high conductivity and good optical transparency in the visible range. T he majority phase is the delaffosite structure as sh own f ig ure 2 2 although minority phases like spinel crystal structure are often observed [1 6 4 1 ]. Patrick et al. also has shown that p hase -pure delafossite material was found at relatively narrow temperature window of 650 to 700 C [41] The electrical properties of CuCrxMg1xO2 have been examined by Nagarajan et al. using RF magnetron sputtering from a single target. While u ndoped CuCrO2 films deposited on a morphous quartz at 400 700 C had a resistivity slightly less than about 1 cm 5% -Mg doped film s deposited under the same conditions had much lower as -deposited resistivities, ~ 4.5 102 cm, corresponding to a conductivity of 220 S cm1. The transparency of such films about 250 nm thick was about 4 0% in the visible range.

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22 The first all TCO diodes were reported by Sato et al. [ 4 0 ]. They fabricated a semi transparent thin film of p -i n structure consisting of pNiO/i NiO/i ZnO/n ZnO:Al. The rectifying properties of the structure confirmed the formation of the junction. Similarly, fabrication of all TCO p -n heterojunction diode (pCuCrO2:Mg/n ZnO) by pulsed laser deposition (PLD) was reported by Tonooka et al. [4 2 ]. The rectifying characteristics demonstrated that u ndoped and Mg doped CuCrO2 films were suitable for the p type semiconductor layer in di ode applications This 0.4 m thick junction exhibited an optical transparency of greater than 80% in the visible range 2. 2 Amorphous Oxide Semiconductors Amorphous oxide semiconductors (AOSs) composed of post transition metal cations with electronic con figuration of (n 1)d10ns0 (n 4) constitute an interesting subc ategory of transparent conducting oxides because they exhibit surprisingly high electron mobility ( 10 50 cm2.V1.s1), showing an order of magnitude higher than conventional amorphous materials (< 1 cm2.V1.s1), even for the films deposited at room temperature. In these oxide based materials, the electrical behavior is a consequence of a conduction band primarily derived from spherically symmetric heavy -metal cation ns orbitals with large radi i and large overlap between adjacent orbitals resulting in giving an efficient transport path for carriers and high mobilities even in the amorphous phase Hence, there is substantially less difference in the mobility between crystalline and amorphous sta tes. There are several potential amorphous oxide semiconductors such as InZnO, InGaO, InSnO, ZnSnO, and InGaZnO which have been reported in the literatures [ 1 8 3 5 4357]. Among these materials, InZnO and InGaZnO are discussed here.

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23 2.2. 1 Indium Gallium Z inc Oxide Indium gallium zinc oxide (IGZO) composed of In2O3, Ga2O3 and ZnO, is a wide band gap ( ~ 3.5 eV), n type semiconductor The base constituent, In2O3, shows a high electron mobility of ~35 cm2.V1.s1. However, In2O3 has an invariable property like a high electron concentration due to its tendency to form oxygen vacancies in the film. T o suppress oxygen vacancy generation, Ga2O3 with a strong metal oxygen bond is utilized. ZnO is characterized by a small atomic distance between Zn atoms, which help s the conduction band of InGaZnO to spread out in energy, leading to the increase in electron mobility. As a result, InGaZnO exhibits a wide range of controllable carrier concentration and shows good stability in air. The s toichiometry of InGaZnO can be generally described as In2 xGa22x(ZnO)k, where 0 < x < 1 and k is an integer [5865]. Single crystal indium gallium zinc oxide is composed of alternating layers of InO2 and GaZnO4 +; In3 + ion has octahedral coordination, the Ga3 + ion has pentagonal coordinatio n, and the Zn2 + has tetragonal coordination [59, 61, 62]. From t he structure of single crystal and amorphous InGaZnO4 thin films t he nearest -neighbor distances for In O, Ga O and Zn O in the amorphous film are 0.211, 0. 200, and 0.195 nm, respectively Th e values are similar to those of the single crystal structure (0.218, 0.193, and 0.193 nm respectively) although InO6 and InO5 are more dispersed than in the crystal and close to a random cation distribution. Nomura et al. calculated InGaZnO band structu re and found that the effective mass is as small as 0.2me. 2.2. 2 Indium Zinc Oxide Over the last two decades, numerous studies on Sn doped In2O3 (I nSnO) film s as a transparent oxide semiconductor have been investigated due to their advantages such as low internal stress and easy etching for micro -patterning. However, fully amorphous ITO films could be deposited only at rather high pressure at room temperature [66 68]. Ito et al. reported that

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24 indium zinc oxide ( I n Z n O ) films (In2O3/ZnO = 89.3:10.7 by wt.%) with entirely amorphous structure could be obtained with high reproducibility under the wide range of the deposition conditions such as pressure or substrate temperature up to 300 C [68]. Several previous reports have demonstrated that amorphous InZnO fi lms ( 10 wt. %ZnO 90 wt. % In2O3, and homogeneous In2ZnkOk+3, k =2, 3, 4, 5, 6, 7, 9, 11, 13, and 15) have attracted significant attention as new candidates for transparent electrodes due to their good conductivity, high optical transparency, excellent surfa ce smoothness, and low depos ition temperature [6971]. Park et al. reported that I n Z n O films containing 10 wt. % ZnO showed either amorphous or a crystallized In2O3 phase depending on the growth conditions [25] The crystal structure of h omogeneous In2ZnkOk+3 (k =2, 3, 4, 5, 6, 7, 9, 11, 13, and 15) compounds consists of either a rhombohedral unit cell (R 3 m ) for odd k values or a hexagonal unit cell (P 63 / mmc) for even k values [72, 73]. Other authors have shown that InZnO thin films can be synthesized thr ough a variety of methods including metalorganic chemical vapor deposition (MOCVD), sputtering, pulsed laser deposition (PLD), and sol -gel processing [21 24, 74, 75]. The films allow for high mobility and controllable conductivity as discussed above. Such behaviors permit it to be used either a transparent semiconductor (active layer) or a conductor (passive layer). The use of InZnO for active device applications has been somewhat limited due to its high conductivity and sensitivity to moisture that deteriorates the film properties, while InGaZnO films are relatively stable in air even without passivation layer. 2.3 Amorphous Oxide based Thin Film Transistors The development of the first thin -film transistor (TFT) with CdS channel layer was invented by P. K. Weimer in 1962 [76]. The TFTs were fabricated using thermally grown SiO and gold as a gate dielectric and metal electrodes, respectively. The device exhibited the field

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25 effect mobility of 1.1 cm2.V1.s1 and drain current onto off ration of 101. Since Weimers initial work, TFTs based on a variety of channel materials, including CdS, CdSe, amorphous and polycrystalline silicon, have been developed. Currently, the most dominant TFT technology is based on hydrogenated amorphous silicon ( Si:H), which are commonly employed as pixel drivers in active -matrix liquid crystal displays (AMLCDs). High performance Si:H TFTs typically have field -effect mo bilities of approximately 1.5 to 2.0 cm2.V1.s1. Recently, organic materials have been empl oyed as channel materials because of low cost deposition methods such as spin coating or printing. In addition, low processing temperature (< 100 C) allows for realization of flexible electronics. However, organic TFTs (OTFTs) performance and chemical inst ability are not sufficient for practical applications: field effect mobility (1031 cm2.V1.s1) is too low to drive high resolution and high speed O light emitting diode (OLED) displays. Since the introduction of crystalline and amorphous oxide semicon ductor based thin-film transistors in 2003 and 2004, respectively, a wide variety of n type oxide materials have appeared to be the promising candidates for channel layer including binary oxides (ZnO, SnO2, and In2O3) and several amorphous multi -component oxides ( ZnSnO, InZnO, InGaO, and InGaZnO) These amorphous oxide -based TFTs operate in both depletion and enhancement mode and exhibit excellent saturation drain currents with good electrical and optical properties (high on to -off ratio, low subthreshold gate voltage swing, large mobility high transparency) [ref] The high performances presented by these TTFTs associated to a high electron mobility, at least two orders of magnitude higher than that of conventional amorphous silicon TFTs and a low threshol d voltage, opens new doors for applications in flexible, wearable, disposable portable electronics as well as battery powered applications

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26 2.4 Processing Techniques 2.4.1 Plasma Etching Etching refers to the crucial IC fabrication process of transferring pattern by removing specified areas. Wet chemical etching was widely used in manufacturing until the 1960s. Even though this technique is inexpensive, the feature size is limited to about 3 microns. The isotropic etching r esults in sloped sidewall and u ndercutting of the mask material. As feature dimension decreases to microns and submicrons and device density per chip increases, anisotropic etching is necessary. Dry etching techniques using gases as primary etch medium were developed to meet this need In addition to anisotropic pattern transfer, dry etching provides better uniformity across the wafer, higher reproducibility, smoother surface morphology, and better control capability than wet chemical etching. Three general types of dry etching inclu de plasma etching, ion beam milling, and reactive ion etch (RIE) [77, 78]. Inductively coupled plasma (ICP) etching was used in this study and will be discussed in detail. ICP etching is a dry etching technique where high -density plasmas are formed in a d ielectric vessel encircled by inductive coils as shown in Figures 2 3 and 2 -4 When an rf power is applied to the coil, commonly referred to as the ICP source power, the time -varying current flowing through the coil creates a magnetic flux along the axis of the cylindrical vessel. This magnetic flux induces an electric field inside the vacuum vessel. The electrons are accelerated and collide with the neutral operating gas, causing the gas molecules to be ionized, excited or fragmented, forming high -densi ty plasma. The electrons in circular path are confined and only have a small chance of being lost to the chamber walls, thus the dc self -bias remains low. The plasma generated as described above consists of two kinds of active species, neutrals and ions. The material to be etched sits on top of a small electrode that acts as parallel plate capacitor along with the chamber as the second electrode. When an rf power, also known as electrode

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27 power or chuck power, is applied to the sample stage, the electron s in the plasma accelerate back and forth in the plasma from the changes in the sinusoidal field. Since electrons have much lighter mass compared to the other species in the plasma, they respond more rapidly to the frequency change than the other species. As the electrons impinge the chamber surfaces, the chamber becomes slightly negative relative to the plasma. The surface area of the chamber is larger than the sample stage, thus the negative charge is concentrated on the sample stage. This bias attrac ts the ions toward the sample, bombarding the surface to remove material. In an ICP system, the plasma density and the ion energy and are effectively decoupled in order to achieve uniform density and energy distributions and maintain low ion and electron energy low. This enables ICP etching to reduce plasma damage while achieving fast etch rates. The plasma generated as described above consists of two kinds of active species: neutrals and ions. Neutrals are chemically reactive and etch the material by chemical reactions, while ions are usually less reactive and are responsible for removing material by physically bombarding the sample surface. The kinetic energy of the ions is controlled by electrode bias. The electron density and ion density are equal on average, but the density of neutrals, known as the plasma density, is typically higher. Anisotropic profiles are obtained by superimposing an rf bias on the sample to independently control ion energy and by using low pressure conditions to minimize io n scattering and lateral etching. The plasma is neutral but is positive relative to the electrode. It appears to glow due the ion excitation from the electron movements. The recombination of charges at the boundary surfaces surrounding the plasma creates a charge depletion layer, also known as a sheath, dark space or dark region, resulting in diffusion of carriers to the boundaries. The diffusion of electrons is faster than ions initially, thus an excess of positive ions is left in the plasma and

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28 assumes a plasma potential, Vp, with respect to the grounded walls. The plasma and substrate potentials generate drift current to enhance the ion motions and hinder the electron motions until steady state condition is achieved. The difference in electron and io n mobility also generates a sheath near the powered electrode. The dark region, a small region in the plasma immediately above the sample, keeps the electrons away due to the negatively charged electrode. The powered electrode reaches a self -bias negativ e voltage, Vdc, with respect to the ground. Even though the voltage drop controls the ion bombardment energy across the plasma sheath, it is difficult to measure; therefore, it is common to monitor the Vdc. Note that the dc bias is not a basic parameter and is characteristic to a particular piece of equipment. Etching is accomplished by the interaction of the plasma to the substrate. The three basic etching mechanisms, chemical etch process, physical etch process, and a combination of both chemical and p hysical etching process, are shown in Figure 2 5 and 2 6 respectively. Chemical etch process is the chemical reaction that etches the substrate when active species (neutrals) from the gas phase are absorbed on the surface material and react with it to form a volatile product. The chemical etch rate is limited by the chemical reaction rate or diffusion rate that depends on the volatility of the etch products since undesorbed products coat the surface and prevent or hinder further reactions. Chemical etch ing is a purely chemical process therefore etches isotropically, or equally in all directions. Physical process, also known as sputtering, occurs when positive ions impinge normal to the substrate surface. If the ions have sufficiently high energy, atoms molecules or ions are ejected from the substrate surface to achieve a vertical etch profile. The etch rate of sputtering is slow, and the surface is often damaged from the ion bombardment. A combination of both chemical and physical etching process, al so known as energy driven, ion -enhanced mechanism, takes advantage of the effect of ion bombardment in

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29 the presence of reactive neutral species. The energetic ions damage the surface and leave the surface more reactive toward incident neutrals, leading to removal rates that exceed the sum of separate sputtering and chemical etching. This process produces very fast etch rates and anisotropic profile; therefore, it is desirable in high fidelity pattern transfer. 2.4.2 Ohmic Contacts It is imperative that a semiconductor device be connected to the outside world without any change in input and output characteristics of signal. Electrical contacts are required to energize or collect electrical information from a device. Ideally, these contacts should have a low resistance to enhance electron flow to and from the device. There are two types of O hmic contact: The first type is the ideal non -rectifying barrier, and the second is the tunneling barrier. Fig ure 2 7 shows ideal non rectifying contacts between a metal and an n type semiconductor or a p -type semiconductor. If a positive voltage is applied to metal relative to n type semiconductor, there is no barrier height to conduct electrons from the semiconductor into the metal. If a positive voltage is applied to th e n type semiconductor, the effective barrier height for electrons flowing from the metal to the semiconductor will be fairly small for a moderately to heavily doped semiconductor For this bias condition, electrons can easily flow from the metal into the semiconductor. In the case of a metal and a p type semiconductor junction, when m >s, ohmic contact formation is provided at the same voltage condition. The space charge width in a rectifying metal -semiconductor contact is inversely proportional to the square root of the semiconductor doping. The width of the depletion region decreases as the doping concentration in the semiconductor increases; thus, as the doping concentration increases, the probability of tunneling through the barrier increases. The tu nneling current is governed by equation 2.1.

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30 ) exp(oo Bn tE e J (2.1) where, *2 m N e Es d oo The tunneling current increases exponentially with doping concentration. The contact resistivity, c, is defined as the reciprocal of the derivative of current density with respect to voltage evaluated at zero bias. ) ( ) (2 0 1cm V JV c (2. 2 ) c will be as small as possible for an ohmic contact. For a rectifying contact with a low to moderate semiconductor d oping concentration, the current voltage relation is as follows: ] 1 ) )[exp( exp(2 kT eV kT e T A JBn (2.3) w here *A is the Richardson s constant, e is electronic charge, T is temperature in Kelvin, k is the Bo ltzmann s constant and Bn is the barrier height. T he thermionic emission current is dominant in this junction. Equation 2.4 describes t he specific contact resistance for this case kT e T eA kBn C exp* (2.4) The sp ecific contact resistance decreases rapidly as the barrier height decreases. For a metal -semiconductor junction with a high impurity doping concentration, the tunneling process will dominant. From tunneling current equation, the specific contact resistanc e is obtained from equation 2.5.

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31 ) 2 exp(d Bn s cN m (2.5) which shows that the specific contact resistance is a very strong function of semiconductor doping. The theory of forming ohmic contacts is straightforward To form a good O hmic contact we need to create a low barrier and use a highly doped semiconductor at the surface. However, the actual technology of fabricating good, reliable O hmic contact is not as easy in practice as in theory. It is more difficult to fabricate good Ohmic contact s on wide bandgap materials. In general, low barriers are not possible on these materials, so a heavily doped semiconductor at the surface must be used to form a tunneling contact. 2.4.3 Sputtering System Sputtering is a process in which atoms are removed from the surface of a solid by high energy ion impacts [79, 80]. The material removal is a product of the momentum exchange between the incoming ion and the target material. P lasma consisting of argon ions and electrons is ignited between the source and the substrate. The target material is placed on the electrode with the voltage set to maximize the ion flux at the target. As the positively charged argon ions bombard the target surface, the target material is removed from the surface. These atoms impinge o n the sample surface, forming a thin film. The sputter yield depends on the direction of the incident ions, target material, mass ratio of the target material to the bombarding ions, and energy of the bombarding ions. Sputter deposition has multiple advant ages over other techniques, including improved film uniformity and an enhanced ability to produce layers of compound materials and alloys.

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32 2.4.4. E -Beam Evaporator system In an e -beam evaporator, the high -energy electron beam emitted from a hot filament is accelerated to a voltage of 10 keV [79, 80]. The beam is then directed toward the target to be evaporated. The material heats up and begins to evaporate as it is bombarded by the electron beam. To grow the film, a substrate is placed in line with the e -be am target. Typically, the sample vapor pressure should be at least 10 m T orr to obtain reasonable deposition rates. The evaporator must be operated at low rates to achieve the best uniformity; however, care must be taken since low evaporation rates require extremely high vacuums to minimize film contamination. 2.4.5. Rapid Thermal Annealing Annealing is a thermal process used for repairing the ion implantation damage, diffusing dopants and alloying metal contacts. After ion implantation, annealing is employ ed to repair the crystal damages caused by the highenergy ion bombardment that degrade carrier lifetime and mobility. Since the majority of the implanted dopants reside in the interstitial sites, the as implanted materials have poor electrical properties. Annealing provides thermal energy for the dopants to migrate to the substitutional sites and contribute to the carrier concentration [80, 81]. Traditionally, tube furnaces were used for annealing after ion implantation. However, furnace annealing causes t he implanted atoms to diffuse laterally and requires relatively long anneal time. Rapid thermal annealing was developed in order to overcome these drawbacks. Rapid thermal annealing (RTA) utilizes radiation heating from arc lamps or tungsten -halogen lamps to heat the wafer in an inert atmosphere such as N2 or O2. It can attain higher temperature at a shorter time period than a conventional tube furnace, and the overall anneal time is relatively short, usually taking seconds as compared to several minutes to hours in a conventional tube furnace. RTA

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33 allows uniform heating and cooling that reduces thermal gradients that can lead to warping and stress induced defects, enabling more dense design and fewer failures due to dislocations. 2.5 Characterization Techni ques 2.5.1. Hall Effect Measurement The Hall effect, discovered in 1879, can be used to determine the resistivity, carrier type and concentration, and mobility of a sample. The principle underlining the Hall effect is Lorenz force which is defined as a for ce exerted on a charged particle in an electromagnetic field. Figure 2 8 shows a schematic of Hall effect. It is assumed that a constant current flows along the xaxis from left to right in the presence of a z -directed magnetic field. Under Lorenz force el ectrons drift toward the negative y axis and accumulate on the side of the sample to produce an electrical surface charge. As a result, a potential drop across the sample called Hall voltage is formed. The induced electric field increases until it countera cts to the opposite Lorenz force. In this case, ne eBj B ev eEx x y/ (2.6) w here yeE is the induced electric field force, B evx is the Lorenz force, x xnev j is the total current den sity. The Hall coefficient RH is defined as in equation 2.7. ne RH1 (2.7) The mobility is defined as the coefficient of proportionality between v and E and measured as follows: H x x xR neE j E v (2.8)

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34 where is the conductivity. For p type semiconductors, a hole has a positive charge e Therefore, the Hall coefficient is positive in sign. The Van der Pauw technique which requires no dimension measured for the calculation of sheet resistance or sheet carrier density solves the potential p roblem in a thin layer of arbitrary shape. Thus, this method has increased in popularity relative to the Hall bar configuration. The validity of the V an der Pauw method requires that the sample 2.5. 2 Stylus Profilometry Stylu s profilometry is used to measure the topographical features of a specimen surface, such as roughness, step height, width and spacing. A probe, or stylus, contacts the surface of the specimen and follows height variation as it scans across the surface. The height variations are converted into electrical signals, providing a cross -sectional topographical profile of the specimen. In this work, the etch rate was calculated by the depth, as measured by the profilometer, over a specified period of time. 2.5. 3 Sc anning Electron Microscopy Scanning electron microscopy (SEM) generates images from electrons instead of light. A beam of electron is produced and accelerated from an electron gun. The electron beam passes through a series of condenser and objective lenses which focus the electron beam. A scanning coil moves the beam across the specimen surface. The electron beam interacts with the specimen, and electrons from the surface interaction volume, such as backscattered, secondary, characteristic x ray continuous x ray, and Auger, are emitted. The signals are collected, amplified and converted to a cathode ray tube image. Depending on the specimen and the equipment setup, the contrast in the final image provides information on the specimen composition, topography and morphology. The main advantages of using electrons for image formation are high magnification, high resolution and large depth of fields [ 82]

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35 2.5. 4 Atomic Force Microscopy Atomic force microscopy (AFM) employs a microscopic tip on a cantilever that de flects a laser beam depending on surface morphology and properties through an interaction between the tip and the surface. The signal is measured with a photodetector, amplified and converted into an image display on a cathode ray tube. Depending on the ty pe of surface, AFM can be performed in contact mode and tapping mode. 2.5. 5 Auger Electron Spectroscopy Auger electron spectroscopy (AES) determines the elemental composition of the few outermost atomic layers of materials. A focused beam of electrons wit h energies from 3 keV to 30 keV bombards the surface of a specimen. The core level electrons are ejected from approximately 1 level. As the atom relaxes, an outer -level electron fills the core vacancy and releases excess energy, which in turn, ejects an outer electron, known as an Auger electron. This process is illustrated in Figure 2 9 The kinetic energy of the Auger electrons is characteristic of each element, with the exception of hydrogen and helium. Therefore, by measuring the energies of the Auger electrons, the near surface composition of a specimen can be identifie d. In addition, AES can provide compositional depth profile from relative intensities of the elements present if the system is equipped with an ion gun to sputter away material [82]. 2.4. 6 Photoluminescence Photoluminescence (PL) is an analytical technique that provides information about the optical properties of a substrate. A light source, such as He Cd, Ar and Kr lasers, with energy larger than the bandgap energy of the semiconductor being studied, generates electronhole pairs within the semiconductor. The excess carriers can recombine via radiative and non radiative

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36 recombination. Photoluminescence, the light emitted from radiative recombination, is detected. The wavelength associated with the different recombination mechanism is measured. The luminesce nce from excitons, electrons and holes bound to each other, is observed only at low temperatures in highly pure materials. As the temperature increases, the exciton breaks up into free carriers from the thermal energy. Increase in doping also causes the di ssociation of excitons under local electric fields. Under these conditions, the electrons and holes recombine via the band to -band process. Since some of the electrons may not lie at the bottom of the conduction band, their recombination and holes will pro duce a high -energy tail in the luminescence spectrum. On the other hand, the bandto -band recombination will yield a sharp cutoff at the wavelength corresponding to the band gap of the material [ 91]. 2.4. 7 Electrical Measurements Current -voltage (I -V) measurements were taken to characterize the elect rical properties of the devices including thin film transistors These measurements are performed on an Agilent 4156C Semiconductor Parameter Analyzer connected to a micromanipulator probe station.

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37 Ta ble 2 1. Properties of n type transparent conducting oxides [ CuAlO In 2 O 3 InGaO 3 In 2 Zn 2 O 5 InGaZnO 4 SnO ZnO ZnSnO 3 B andgap (eV) 3.49 3.7 3.3 2.9 3.5 3.6 3.3 3.5 M obility (cm 2 .V 1 .s 1 ) 10 1040 10 103 0 5 20 5 30 5 50 5 10 C arrier concentration (cm3) ~ 1018 <1021 1020 5 1020 ~1020 1020 1021 1020 R esistivity ( .cm) 1 104 2 103 1 103 2 103 103 104 5 103 references [38] [125] [126] [126] [58 60] [125] [125, 126] [126, 127]

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38 Table 2 2. Properties of p type transparent conducting oxides CuAlO 2 CuGa 1x Fe x O 2 CuIn 1x Ca x O 2 CuCr 1x Mg x O 2 CuY 1x Ca x O 2 Dopant undoped Fe Ca Mg Ca B andgap (eV) 3.5 3.4 3.9 3.1 3.5 Transmittance (%) 70 60 70 50 50 Conductivity (S.cm1) 0.34 1 0.028 220 1.05 references [128] [14] [129] [14, 16] [14]

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39 Table 2 3. Bas ic physical properties of ZnO Properties Values Lattice parameters at 300 K (nm) a 0 : 0.32495 c 0 : 0.52069 Density (g/cm 3 ) 5.606 Stable phase at 300 K Wurtzite M elting point ( C) 1975 T hermal conductivity 0.6, 1 1.2 L inear thermal expansion coefficient a 0 : 6.5 10 6 c 0 : 3.0 10 6 S tatic dielectric constant 8.656 R efractive index 2.008, 2.029 E nergy bandgap (E g ) D irect, 3.37 Intrinsic carrier concentration (/cm3) n type doping: ~ 10 20 p type doping: ~ 10 17 E xciton binding energy (meV) 60 E l ectron effective mass 0.24 E lectron Hall mobility: n type at 300 K 200 Hole effective mass 0.59 Hole Hall mobility: p type at 300 K 5 50

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40 Figure 2 1. Crystal structure of ZnO

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41 Figure 2 2. CuMO2 in delafossite structure, where Cu is small dark spheres coordinated to two oxygen atoms (large dark spheres) and M is a trivalent cation (small light spheres)

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42 13.56 MHzPlasmaPowered Electrode (Chuck) Sample Reactor 2 MHz RF -coil 13.56 MHzPlasmaPowered Electrode (Chuck) Sample Reactor 2 MHz RF -coil Figure 2 3. Schematic of ICP reactor. Figure 2 4. Electric and magnetic filed inside the reactor

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43 Fig ure 2 5. Chemical etching process. (a) Generation of reactive species (b) Diffusion (c) Adsorption (d) Chemical reaction (e) Desorption (f) Diffusion of byproducts Figure 2 6. Physical etching process (left) and combination of chemical and physical etching process (right).

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44 Figure 2 7. Ideal non-rectifying contacts between a metal and n or p type semiconductor.

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45 Figure 2 8. A schematic of Hall effect. Figure 2 9 AES process: (a) inner core level electron dislodged (b) an ou ter level electron fills the vacancy and releases energy ( c ) the excess energy ejects an Auger electron.

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46 CHAPTER 3 HIGH DENSITY INDUCTIVELY COUPLED PLASMA ETCHING OF BULK ZINC OXIDE AND INDIUM ZINC OXIDE FILM 3.1 Introduction Over the last decade, zinc -oxide (ZnO) has emerged as a very promising semiconductor material for blue/UV light emitting diodes (LEDs), transparent electronics, spintronics devices, and gas sensor applications [83 91] The interest in ZnO for short -wavelength LEDs is largely due to its wide direct band gap ( Eg=3.37 eV) and large exciton binding energy of 60 meV, which is much higher than that of other wide bandgap semiconductors like GaN (25 meV). In addition, ZnO can be grown at low deposition temperatures on inexpensive substrates such as glass. While ZnO can easily be doped n -type, recent progress in the fabrication of ZnO layers with p type conductivity have also been reported [3, 92, 93] Another attractive feature of ZnO for LEDs is the ability to form heterostructures by using MgZnO ( Eg~3 eV) or CdZnO ( Eg~ 4 eV) alloys [94, 95] The fabrication of high -performance LEDs using ZnO also needs the formation of reliable and low resistance ohmic contacts with low light absorption. While the most common schemes for ohmic contacts to Z nO involve metals and are therefore opaque, low resistance ohmic contacts based on Transparent Conductive Oxides (TCOs) have also been reported. Among TCOs, indium -zinc -oxide ( I nZnO ) is a very attractive material for ohmic contacts to ZnO -based LEDs due to its good electrical conductivity, wide transmittance window, excellent surface smoothness, and low deposition temperature. In addition to the optimization of the growth conditions, the integration of ZnO and InZnO films in devices also requires the develo pment of high resolution pattern transfer processes. Among the various patterning techniques, dry etching methods produce a reliable pattern transfer in sophisticated device structures. While several plasma chemistries have been investigated for

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47 the dry et ching of ZnO, only CH4/H2/Ar and Cl2/Ar have been examined for InZnO It is found that CH4/H2-, Cl2, and BCl3containing plasmas are capable of etching ZnO at slow (<0.4 m/min) but practical etch rates at room temperature. For I nZnO initial results indicate that CH4/H2/Ar plasmas lead to etch rates higher than those of ZnO, whereas the surface presents particle like features resulting from the preferential desorption of Inand O -containing products. In the search of an optimized pattern transfer proces s, we examine in this section the potential of IBr and BI3-containing plasmas for the dry etching of bulk single -crystal ZnO and RF -sputtered I nZnO films. A parametric study of the influence of the discharge chemistry on the etch rate, post -etched surface morphology, and near -surface stoichiometry is presented. The interest in these unusual plasma chemistries essentially results from their expected high dissociation degrees (i.e. high reactive neutral density), even at very moderate power levels. Previous investigations in IBr and BI3-containing plasmas include etching of III nitrides, III -Vs, and magnetic materials. 3.2 Experimental The bulk wurtzite (0001) ZnO crystals from Cermet were nominally undoped (n ~8 1016 cm3, mobility 190 cm2/V s at 300 K from Hall measurements). As for the InZnO films, they were deposited on glass substrates (Coning EAGLE2000) using RF magnetron sputtering. The I nZnO targets were fabricated using high purity In2O3 (99.99% ) and ZnO(99.9%) by a conventional ceramic processing te chnique. The substrates were cleaned in an ultrasonic bath with trichloroethylene, acetone, and ethanol prior to loading in the deposition chamber. The targets were pre -sputtered for 10 min. before growth. Sputtering was carried out at an argon pressure o f 10 mTorr with a sputtering power in the 50150 W range. The distance between target and substrate was fixed at 70 mm. The deposition temperature was varied from

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48 room temperature (RT) to 500 C. The characteristics of the as deposited ntype InZnO samples are summarized in Table 3 1 High -density plasma etching of bulk single crystal ZnO and RF sputtered InZnO films was realized using an UNAXIS 790 Inductively Coupled Plasma (ICP) reactor. In the present work, the 2 MHz power applied to the ICP source and t he RF (13.56 MHz) chuck power were varied between 0 and 500 W. Note that the source power essentially controls the ion and reactive neutral density, whereas the RF chuck power mainly affects the ion energy. Etching was performed in Ar/BI3 and Ar/IBr plasma chemistries. Prior to their injection in the etching chamber, the BI3 and IBr crystalline solids (melting temperatures in the 40 45C range) were contained in a stainless steel vacuum vessel heated up to ~45C to increase their vapor pressure. The Ar conc entration in Ar/BI3 and Ar/IBr was controlled by varying the Ar mass flow rate between 0 and 20 sccm while keeping the BI3 and IBr mass flow rates constant (~8 sccm). The total gas pressure before plasma ignition was set to 5 mTorr. The ZnO and InZnO etch rates were determined from stylus profilometry measurements, the plasma exposure time being set to 5 minutes. Atomic Force Microscopy (AFM) was employed to measure the as deposited and post -etched surface roughness. As for the near -surface stoichiometry, i t was analyzed using Auger Electron Spectroscopy (AES). 3.3 Results and Discussion Figures 3 1 present s the etch rate of ZnO and I nZnO as a function of the argon concentration in Ar/IBr ( fig ure 3 1a) and Ar/BI3 ( f ig ure 3 1b). For both set of experiments, t he ICP and RF powers were kept constant at 300 W and 150 W respectively. In both plasma chemistries, it can be seen that the etch rate of I nZnO nearly follows that of ZnO, except in pure argon. The influence of the indium concentration fraction on the sput ter -etching characteristics of I nZnO films is the subject of another paper and is therefore not discussed here. In the IBr and

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49 BI3containing plasmas, the presence of indium in the sample does not significantly influences the plasma etching dynamics. This is in sharp contrast to the etching in the CH4/H2/Ar discharge for which preferential desorption of In -containing reaction products led to much higher I nZnO etch rates in comparison to that of ZnO. The data displayed in figure 3 1 also point out that the e tch rate of amorphous InZnO layers ( I nZnO 1, I nZnO 3) is very similar to that of crystalline films ( I nZnO 2). Crystallization quality is thus not a very critical parameter during I nZnO etching in Ar/IBr and Ar/BI3. On the other hand, the effect of adding I Br or BI3 to the Ar plasma is a very strong decrease of the ZnO and I nZnO etch rates. Boron usually plays a key role during oxide etching by forming volatile reaction products like boron dioxide (BO2). Several works have indeed reported enhancement of the etch rate of metal -oxides with boron -containing plasmas Bromine and iodine also lead to the formation of volatile oxygen reaction products such as IO2 and BrO2. The detrimental influence of IBr and BI3 chemistries presented in fig ure 3 1 must therefore b e related to a less efficient desorption of metal -bromides and metal iodides. This is consistent with the very high boiling points (650 750C range) of the expected group II and group III etch products, namely InBr, ZnBr2, InI, and ZnI2. Desorption of indi um and zinc -containing products is thus the rate limiting step during InZnO and ZnO etching in Ar/IBr and Ar/BI3 plasmas. Figure 3 2 show s the influence of the ICP source power on the I nZnO and ZnO etch rate for 60%IBr 40%Ar ( figure 3 2 a) and 60%BI340%A r (f ig ure 3 2b ). The influence of the ICP source power on the DC self -bias on the sample chuck ( VDC) is also shown. Even though the RF power was maintained at 150 W, it can be seen in the figures that VDC decreases with increasing ICP power, suggesting tha t the positive ion density increases under these conditions. Figure 3 2 further indicate s that the etch rate of all materials increases with ICP source power in a very

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50 similar manner. This implies that etching of ZnO and I nZnO is governed by the same mecha nism over the whole range of ICP source powers investigated. In general, an increase in ICP source power leads to an increase of both the reactive neutral density (through an increase of the dissociation degree of the reactive molecular species) and the p ositive ion density. Moreover, the ion energy which is given by the sum of DC self -bias voltage and sheath potential (about 25 V for ICP sources) also depends on the ICP source power. In order to identify which parameter is most likely responsible for the etch rate dependence displayed in figure 3 2 recall that during etching in reactive plasmas, the ion assisted chemical etch rate can usually be written by the equation [96, 97] t satN Y J ER (3.1) w here J+ is the positive ion flux, Ysa t is the ion assisted chemical etch yield on a saturated surface, and Nt is the atomic density. In equation 3.1, 1) / 1 ( n n satJ S Y J is the surface coverage by reactive neutral species (0<<1), where Jn is the flux of reactive neutral species, Sn is the reaction probability, and is the number of reactive atoms desorbed per reaction product. In the subkeV range, Ysat is given by the equation 3.2 [98] ) (th sat satE E A Y (3.2) w here Asat is a proportionality constants that depends on the s pecific plasma -material combination, E is the ion energy, and Eth is the threshold energy. According to equation 3.1 and 3.2 the etch rate should increase linearly with E provided etching is ion-flux limited, i.e n n satJ S Y J / << 1

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51 We have investigated the influence of the ion energy on the etch rate of ZnO and I nZnO in Ar/IBr and Ar/BI3 plasmas. Etching was carried out at various RF powers, the ICP source power being held constant at 300 W. The results for ZnO are displayed in figure 3 -3 for 60%IBr 40%Ar and 60%BI340%Ar. For comparison, the results previously obtained in Ar/CH4/H2, Ar/C2H6/H2, and Ar/Cl2 plasmas are also shown. Above some threshold, the etch rate for all plasma chemistries presented increases linearly with E Eth being ~80 eV for both Ar/IBr and Ar/BI3. These results clearly indicate that etching is driven by the same ion assisted mechanism over the whole range of ion energies investigated. According to equation 3.1 and 3.2, this specific energy dependence corresponds to the ion -flux limited regime for which the etch rate reduces to t th sat t satN E E A J N Y J ER / ) ( / (3.3) While equation 3. 3 shows that the etch rate is independent of the reactive neural flux in the ionflux limited re gime, a decrease of the ion energy with increasing ICP source power would lead to a decrease of the etch rate (see e quation 3.3). One therefore concludes that the increase of the ZnO and I nZnO etch rates with ICP source power presented in figure 3 2 essent ially results from an increase of the positive ion density. Figure 3 3 also points out that the etch rate of ZnO in Ar/IBr and Ar/BI3 is much lower than that achieved in other plasma chemistries like CH4/H2/Ar, C2H6/H2/Ar, and Ar/Cl2. For example, the hig hest etch rate obtained in C2H6/H2/Ar is ~55 nm/min for E ~400 eV whereas ER~15 and 10 nm/min for this energy value in Ar/IBr and Ar/BI3 respectively. As shown in figure 3 4 similar results are obtained for the etching of I nZnO Despite the fact that Ar/IB r and Ar/BI3 chemistries lead to relatively low plasma -induced damages, the etch rate data obtained in such plasmas are clearly too low for efficient pattern transfer processes. CH4/H2/Ar, C2H6/H2/Ar,

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52 and Ar/Cl2 plasmas thus appear more prospective for ZnO and I nZnO etching in device fabrication. Our analysis of the post etched I nZnO and ZnO surfaces have indicated that there was no apparent surface roughening during etching of InZnO and ZnO in any of the IBr and BI3 plasma conditions investigated. For exam ple, figure 3 5 shows that the root -mean -square roughness of the etched ZnO surface was comparable to that of the unetched control sample. This observation is consistent with the AES depth profiles presented in figure 3 6 Indeed, the concentration fractio n of Zn and O is similar to that on the as received sample, which indicates low plasma induced damages. Fig ure 3 7 shows some typical features produced in ZnO with a CH4/H2/Ar process and SiNx layer masking. Clearly, high fidelity pattern transfer can be a chieved with a very smooth surface, although the sidewalls were not completely vertical. Fig ure 3 7 further shows some trenching near the sidewall profiles. These are likely to result from charging of the ZnO surface during ion bombardment, leading to devi ation of the ion trajectory [ 99]. The use of lower ion energies and fluxes or pulse time -modulated plasmas may help in reducing charging damage [100]. 3.4 Conclusions The dry etching characteristics of bulk single crystal ZnO and RF -sputtered InZnO films h ave been investigated using an inductively coupled highdensity plasma in Ar/IBr and Ar/BI3. In both plasma chemistries, it is found that ( i ) the etch rate is independent of the presence of indium in the sample, ( ii ) the etch rate exhibits no enhancement o ver physical sputtering in pure argon in the same experimental conditions, (iii) the etched surface morphologies are smooth, independent of plasma chemistry, and ( iv ) the near -surface stoichiometry after etching is similar to that on the as received sample Comparison of these results to other etching investigations

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53 reported in the literature suggests that C2H6/H2/Ar, CH4/H2/Ar, and Ar/Cl2 plasma chemistries are more attractive than Ar/IBr and Ar/BI3 for ZnO and I nZnO etching for the fabrication of devices like ZnO based LEDs.

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54 Table 3 1. Characteristics of as deposited InZnO layers S ample In/Zn Crystallization T hickness ( ) M obility (cm 2 .V 1 .s 1 ) C arrier density (10 20 cm 3 ) InZnO 1 0.67 amorphous 2480 35.6 1.25 InZnO 2 1.44 crystalline 1852 23.5 3.24 InZnO 3 0.33 crystalline 2266 32.1 3.4

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55 Figure 3 1. Etch rate of ZnO and InZnO as a function of Ar concentration in (a) Ar/IBr and (b) Ar/BI3.

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56 Figure 3 2. Etch rate of ZnO and InZnO as a fu nction of ICP source power in (a) Ar/IBr and (b) Ar/BI3

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57 Figure 3 3. Etch rate of ZnO as a function of the square root of ion energy in Ar/IBr and Ar/BI3.

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58 Figure 3 4. Etch rate of I nZnO 1 as a function of the square root of the ion energy in Ar/IBr and Ar/BI3.

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59 Figure 3 5. AFM scans from ZnO surfaces before and after etching in Ar/IBr for different RF powers : 100 W, 150 W, and 300 W.

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60 Figure 3 6. AES depth profiles of ZnO before and after etching in Ar/IBr for differe nt RF powers : 100 W, 150 W, and 300 W.

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61 Figure 3 7. SEM images of etched ZnO using CH4/H2/Ar discharge. The mask is a SiNx layer deposited by PECVD and patterned by photolithography and reactive ion etching.

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62 CHAPTER 4 OHMIC CONTACTS T O P CUCRO2 4.1 Introduction There is a strong interest in the development of short wavelength ultraviolet (UV ) light emitters and transparent thin film transistors based on oxide semiconductors. GaN is the dominant material for blue/UV emitters, but ZnO h as a number of advantages, including relatively low growth temperatures on cheap substrates such as glass. For photonic applications, ZnO has a much larger exciton binding energy (~ 60 meV ) than GaN (~ 25 meV ), indicating that it should be a superior light e mitting semiconductor. However, the progress on ZnO -based photonics has been limited because of difficulties in obtaining robust p type doping [6, 7, 912] Alternative p type injection layers for oxide photonics have been reported, including SiC, GaN, AlG aN, or Cu2O. Mg -doped CuCrO2 is a promising p type transparent conducting oxide for the formation of all -oxide p -n junctions with n -type semiconducting oxides, including ZnO. It has low resistivity, relatively good hole mobility, and excellent transmission characteristics. This transparent conducting oxide possesses the delafossite ( hexagonal ) crystal structure with a =2.97 c =17.12 and a band gap of ~ 3.5 eV [13 16] Despite the promising characteristics of Mg -doped CuCrO2 layers, the realization of al l oxide p -n junctions using these films requires the development of Ohmic contacts that have both low resistance and are thermally stable and reliable. So far, several promising metallization schemes have been reported for n type semiconducting oxides such as ZnO. In this section we examine the Ohmic contact formation on p type Mg -doped CuCrO2 epitaxial layers grown by pulsed laser deposition. T he Ni/Au metallization scheme exhibits a minimum specific contact resistance of ~ 1 104 cm2 in the as -deposited state and is stable to annealing temperatures up to 400 C. We also report on the use of Ir diffusion barriers in Ni/Au Ohmic contacts to p -type

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63 CuCrO2 to improve the thermal stability of the contacts. The best results were obtained using Ir. Combined wit h the recent progress in metallization schemes for n -type and ptype ZnO the approach of using Ir as the diffusion barrier looks promising for producing low contact resistances on oxide heterojunctions Other materials that were tried for the diffusion ba rrier, including TaN, ZrN, and W2B5, did not improve the stability of the contacts. 4.2 Experimental The Mg -doped CuCrO2 layers investigated in this work were grown by pulsed -laser deposition on c plane sapphire substrates. The deposition temperature was m aintained at 600 C while the oxygen background pressure was set to 10 mTorr. The films were typically 200300 nm thick and Hall measurements showed them to have p -type conductivities of ~ 1 S cm 1. The carrier concentration and mobility were 2 1019 cm3 and 3 cm2. V1. s1, respectively. X ray diffraction confirmed epitaxy on the c -plane sapphire surface with a 30 rotation between the in plane sapphire and CuCrO2 planes. Contact metallurgy of Ti (200 )/Au (800 ), Ni (200 )/Au (800 ), Ni (200 )/Au (800 ) /Ir (500 )/Au (800 ), and Ni (200 )/Au (800 )/ X (5 00 )/ T i (200 )/ Au (800 ), where X was TaN, ZrN, and W2B5, was deposited by electron -beam evaporation (for the conventional metals) o r sputtering (for the diffusion barrier metals) and patterned by photoresist and liftoff. The samples were patterned with circular transmission line method ( C TLM ) patterns. The pads had an inner radius between 75 and 115 m, and the outer radius being 120 m for each set of pads. The current -voltage characteristics were recorded using an Agilent 4156C parameter analyzer. For C TLM, the total resistance between two contact pads can be written as RT= (Rs/2 R1) ( L +2 LT) C where Rs is the sheet resistance of t he semiconductor under the contact, L is the pad spacing, LT is the transfer length, and C = (R2 / L ) ln (R1 / R2) is a correction factor, R1 and R2 being the inner and outer radii, respectively [101] The

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64 specific contact resistance c was obtained from the relation c = RsLT 2 where Rs and LT were determined from the slope and intercept of a plot of RTR1 / C vs L Some samples were subjected to 60 s annealing in the 100600 C range in a flowing nitrogen ambient in a rapid thermal annealing furnace. Auger ele ctron spectroscopy ( AES ) depth profiling was performed using a Physical Electronics 660 scanning Auger microprobe. For the data collection, the electron beam conditions were 10 keV, 0.3 A, and 30 from sample normal while for profiling, the ion beam condi tions were 3 keV Ar+, 2.0 A, and (4 mm )2 raster with sputter etch rate of 86 min1 (SiO2 ). 4.3 Ni/Au Ohmic Contacts 4.3.1 Results and Discussion Figure 4 1 shows the evolution of the I -V after subsequent rapid thermal annealing in the 100600 C range f or Ti/Au (a) and Ni/Au (b) contacts. Over the whole range of annealing temperature investigated, the current voltage characteristics from Ti/Au contacts show back to back Schottky behavior. By sharp contrast, the Ni/Au contacts display an Ohmic behavior, e ven in the as -deposited state. This indicates that the Ni/CuCrO2 interface is characterized by a relatively low intrinsic barrier height. Based on the Schottky -Mott model this suggests that the electron affinity of CuCrO2 layers is very similar to the work function of Ni, indicating that research efforts on the formation of Ohmic contacts to CuCrO2 should be devoted to metals with similar work functions ( e.g., Ni, Au, Pt, and Pd ) [102] The influence of the annealing temperature on the specific contact res istance of Ni/Au contacts is displayed in figure 4 2 For Ni/Au contacts, a minimum specific contact resistance of ~ 1 104 cm2 was achieved in the as deposited state. The contact resistance is stable up to 400 C. As shown in figure 1b ( inset ) annealing above 400 C resulted in rectifying behavior.

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65 Figure 4 2 also presents the influence of the measurement temperature on th e specific contact resistance of Ni/Au contacts. It can be seen that within the uncertainties, c is fairly independent of temperature. This suggests that tunneling is the dominant mechanism of current flow. Under such conditions, the specific contact resi stance is a strong function of doping concentration through the relation c exp [2 (sm )1/2B/ (N)1/2], where B is the barrier height, s is the semiconductor permittivity, m is the effective mass of the carrier, is Plancks constant, and N is the carrier concentration. Considering the relatively high Mg concentration in the pulsed laser deposited CuCrO2 films investigated in this work, one would expect a very low specific contact resistance. However, the presence of donorlike defects such as oxygen vacancies in the near -surface region possibly arising from the growth, the processing, or the formation of metallurgical reactions between the contact metal and the CuCrO2 layer could decrease the net p carrier concentration at the metal -semiconductor int erface, thus greatly reducing the tunneling probability. Therefore, despite the relatively high dop ing level expected deep into the CuCrO2 film, a precise control of the topmost surface properties may be an important issue to further improve the specific contact resistivity on p type CuCrO2 layers. The surface morphologies of as -deposited 300, 500, and 600 C annealed samples are shown in figure 4 3 While as -deposited 300 and 500 C annealed samples show featureless morphology, there is considerable surf ace roughening after annealing at 600 C. This can probably be attributed to the evaporation of oxygen from the CuCrO2 surface, producing metal droplets, as reported previously for bulk, single crystal ZnO. The AES depth profiles of the as deposited and 600 C annealed contacts are shown in figure 4 4 While the as -deposited layers exhibit relatively sharp interfaces, high temperature annealing shows that all three layers have completely intermixed.

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66 4. 3.2 Conclusions Ohmic contact formation on p type CuCrO2 layers was examined High work function metals such as Ni with an overlayer of Au produced a minimum specific contact resistance of ~ 1 104 cm2 in the as -deposited state and an excellent stability following annealing up to 400 C. There was a serious degradation after 500 C annealing due to both decomposition of the CuCrO2 layer and in -diffusion of Ni and Au. 4.4 Ir Diffusion Barrier in Ni/Au Ohmic Contacts 4.4.1 Results and Discussion Figure 4 5 shows the dependence of the specific contact resistivity on the annealing temperature for the contacts with the Ir diffusion barrier in the contact metallurgy. As with standard Ni/Au for material with this doping level, the contacts were rectifying in the as deposited state and became Ohmic at temperatures abov e ~ 400 C. It is common for contacts on wide bandgap semiconductors to show this type of transition. At this stage we do not know the physical mechanism for the rectifying -to Ohmic transition but, in analogy to other systems, we expect it to involve forma tion of a low resistance phase, possibly involving Ni and O. However, this must be confirmed by careful transmission electron microscopy to identify the interfacial phases. At some higher annealing temperature the contacts metals become completely intermix ed with the CuCrO2, but this is delayed by several hundreds of degrees by the presence of the Ir. A specific contact resistance of ~ 5 104 cm2 was achieved after annealing at 500 C and a relatively low contact resistance was still obtained up to 800 C In comparing the morphology of the annealed contacts to those obtained with Ni/Au only, it is clear that the inclusion of the Ir diffusion barrier increases the thermal stability of the contact metallurgy by at least 200 C. By sharp contrast, the use of some of the other high temperature available diffusion barriers available to us, including TaN, ZrN, and W2B5, did not improve the thermal stability relative to

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67 Ni/Au alone. Since the Ir -based contacts provided superior thermal stability compared to the o ther diffusion barrier materials investigated, we focused on the properties of those contacts. Figure 4 6 shows the effect of the measurement temperature on the specific contact resistance of Ni/Au/Ir/Au contacts annealed at 800 C. Within experimental err or, c is basically independent of temperature. This suggests that tunneling is the dominant mechanism of current flow, as was found for Ni/Au contacts annealed at lower temperatures. When tunneling is the dominant transport mechanism, the specific contact res istance is a strong function of doping concentration through the relation c exp [2 (sm )1/2B/ (N)1/2], where B is the barrier height, s is the semiconductor permittivity, m is the effective mass of the carrier, is Plancks constant, and N is the carrier concentration During both growth of the epifilms and subsequent processing to deposit the contact metals and anneal to form a low resistance contact, however, the formation of donor like defects like oxygen vacancies in the near -surface region co uld decrease the net p carrier concentration at the metal -semiconductor interface, reducing the tunneling probability. As with other oxide semiconductors, it is necessary to avoid changes in near -surface stoichiometry for achievement of reproducible contac t properties. The surface morphology of as -deposited, 400 C, 500 C, and 800 C annealed samples are shown in figure 4 7 While the as -deposited and 400_C annealed samples show similar morphology, there is considerable surface roughening after annealing at 500 C. There is additional reaction of the contact metallurgy at 800 C, but the root -mean -square roughness of the contacts remained below 15 nm, as measured by Atomic Force Microscopy. The scanning electron microscopy (SEM) pictures in figure 4 8 conf irm that the morphology remains reasonably smooth even after annealing at 800 C.

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68 AES surface scans of the Ir based contacts both before and after annealing are shown in figure 4 9 After annealing at 500 C, Ni has diffused to the surface and oxidized. Af ter annealing at 800 C, some of the Cu from the CuCrO2 diffuses all the way through the overlying metal stack and appears on the surface. Table 4 1 summarizes the near -surface concentration of elements in the contact stacks as a function of annealing temp erature. The corresponding AES depth profiles of the as -deposited and annealed contacts are shown in figure 4 10. While the as deposited layers exhibit relatively sharp interfaces, hightemperature annealing produces intermixing of the contact metals first ly by the out -diffusion of Ni by 500 C and then Cu at the highest temperatures. 4.4.2 Conclusions We have examined the effect of different diffusion barriers in Ni/Au Ohmic contacts on p type CuCrO2 layers. TaN, ZrN, and W2B5 diffusion barriers in Ni/Au O hmic contacts did not produce any significant improvement in thermal stability relative to Ni/Au alone. However, the use of Ir as the diffusion barrier increased the thermal stability by ~ 200 C, and a minimum specific contact resistance of ~ 5 104 cm2 w as achieved after annealing at 500 C. These contacts still exhibited low contact resistance after annealing at 800 C, although the contacts annealed at this temperature showed significant out -diffusion of both Ni and Cu.

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69 Table 4 1. Concentration and elements detected on the surface (in At. %) S ample C O Ni Cu Au C ontrol 55 nd nd nd 45 500 C anneal 35 37 28 nd nd 8 00 C anneal 33 38 19 11 nd nd: not detected

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70 Figure 4 1. Influence of annealing temperature on I -V characteris tics from (a) Ti/Au and (b) Ni/Au contacts. The inset shows I -V characteristics of sample annealed at 600 C.

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71 Figure 4 2. Influence of annealing temperature (bottom scale) and measurement temperature (top scale) on the specific contact resistance o f Ni/Au contacts.

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72 Figure 4 3. Surface morphology of Ni/Au contacts: as -deposited, 300 C, 500 C, and 600 C annealing.

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73 Figure 4 4. AES depth profiles from as -deposited (top) and 600 C annealed (bottom) Ni/Au contacts

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74 Figur e 4 5. Specific contact resistance as a function of annealing temperature for Ni/Au/Ir/Au contacts on p type CuCrO2.

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75 Figure 4 6. Measurement temperature dependence of the specific contact resistance for Ni/Au/Ir/Au contacts annealed at 800 C.

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76 Figure 4 7. Optical micrographs of Ni/Au/Ir/Au contacts annealed at various temperature.

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77 Figure 4 8. SEM micrographs of Ni/Au/Ir/Au contacts as deposited and after annealing at 500 C or 800 C.

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78 Figure 4 9. AES surface scans of Ni/ Au/Ir/Au contacts as -deposited and after annealing at 500 C or 800 C.

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79 Figure 4 10. AES depth profiles of Ni/Au/Ir/Au contacts as deposited and after annealing at 500 C or 800 C.

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80 CHAPTER 5 ROOM TEMPERATURE DEP OSITED INDIUM ZINC O XIDE TH IN FILMS WITH CONTROLLED CONDUCTIV ITY 5.1 Introduction There is strong interest in new forms of transparent, flexible or wearable electronics that utilize non Si materials deposited at low temperature on cheap substrates. While Si -based thin film transisto rs (TFTs) are widely used in displays, there are some drawbacks such as light sensitivity and light degradation and low field effect mobility (<1 cm2/Vs). One of the promising alternatives involves amorphous or nanocrystalline n -type oxide semiconductors [43 57] For example, there have also been promising results with zinc oxide, indium gallium oxide and zinc tin oxide channels The maximum channel mobilities are surprisingly high for these materials (~10 cm2 V 1 s 1) even for amorphous films deposited at room temperature. In some cases, the mobility may also increase with increasing carrier c oncentration, in contrast to Si One of the main advantages of TFTs based on conducting oxides is the higher carrier mobi lity and electron channel mobility leading to higher drive currents and faster device operating speeds. A major challenge in the development of transparent thin-film transistors is to control the carrier concentration with high transparency in the active c hannel. Transparent conducting oxides are also needed as electrodes in flat -panel display devices. The most commonly used material is indium tin oxide (ITO) which exhibits good conductivity and stability and is readily patterned in simple wet etch solution s. An alternative material is I n Z n O, which has a larger work function and higher transmission in the 1 1.5 m range [19] In this section, we report on the sputter deposition of amorphous I n Z n O films on glass substrates near room temperature. The main infl uence on the resistivity of the films is found to be the oxygen partial pressure during deposition. The amorphous films exhibit carrier mobilities in the range 5 20 cm2.V1.s1.

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81 5.2 Experimental The films were deposited on glass substrates (Corning 2947) a t room temperature by rf magnetron sputtering using targets of In2O3 and ZnO. The working pressure was varied from 3 15 mTorr in a mixed ambient of O2/Ar.The percentage of O2 in the mixture was varied from 0 3%. In most cases the sputtering power on the Zn O target was held constant at 125W, while the power on the In2O3 target was varied from 50 200W to investigate the effect of changing In/Zn ratio in the films. The typical thickness of the I n Z n O films deposited was 2000.The sputter deposition rate was der ived from stylus profilometry measurements of film thickness. The crystallinity of the films was examined by powder xray diffraction while the resistivity and carrier mobility in the films was obtained from Hall measurements performed with soldered In con tacts. The In/Zn ratio was measured by x -ray microprobe, while the optical transmittance was also measured in the visible region. The contact properties of e bema evaporated Ni(200)/Au(800) and Ti(200)/Au(800) Ohmic contacts on the IZO films were obtai ned from linear transmission line method (TLM) measurements on 100100 m pads with spacing 1, 5, 6, 10, 16, 20, 36, 40, 76 and 80 m. The contact resistance RC was obtained from the relation RC = (RTs d / Z )/2, where RT is the total resistance between two pads, s is the sheet resistivity of the semiconductor under the contact, d is the pad spacing, and Z is the contact width. The specific contact resistance, c is then obtained C = RCLTZ where LT is the transfer length obtained from the intercept o f a plot of RT vs d 5.3 Results and Discussion Figure 5 1 shows the effect of In2O3 target power (top) or chamber working pressure (bottom) on the deposition rate of the I n Z n O films and the resulting In/Zn ratio in the films. Both the deposition rate and In/Zn ratio depended linearly on In2O3 target power at fixed ZnO target power, in the latter case varying from ~0.3 0.6 over the range of powers investigated. The films

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82 were smooth over the whole power range, with root -mean -square (RMS) roughness measured by tapping mode Atomic Force Microscopy (AFM) of ~ 1 nm. The deposition rate was inversely dependent on working pressure and was independent of the oxygen partial pressure over the range we investigated while the In/Zn ratio was independent of both paramete rs. The I n Z n O films were amorphous over the entire set of deposition conditions we examined at room temperature. Similarly, In2O3 films deposited using only that target were also amorphous. By sharp contrast, ZnO films deposited under the same conditions u sing only the ZnO target always showed evidence of polycrystallinity, as seen in the XRD scans in figure 5 2 (top). The bottom of f igure 5 2 shows that the In2O3 target power had no effect on the XRD spectrum from the I n Z n O films. The optical transmittance in the visible region was >70% for all of the I n Z n O films investigated. Figure 5 3 (top) shows the results of Hall measurements on the I n Z n O as a function of In2O3 target power during the depositions at fixed working pressure of 5mTorr. The n-type c arrier density increased from ~ 4x1019 cm3 at low In2O3 target power to ~8x1020 cm3 for the highest power conditions used. The mobility showed a maximum value of ~16 cm2.V1.s1 for moderate powers. The resulting resistivity was in the range of 2x1028x 104 increasing the working pressure was an increase in carrier density (to 2x1021 at 15 mTorr) and a resulting increase in resistivity of about an order of magnitude between 3 and 15 mTorr. The biggest influence on the electrical properties of the I n Z n O was the oxygen partial pressure during the deposition. As shown at the bottom of f igure 5 3, the carrier density dropped dramatically at higher percentages of oxygen, in concert with the carrier mobility, resulting in a rapid increase in fil m resistivity. The resistivity changed by approximately 6 orders of magnitude when changing from 2.5 to 3 % O2 in the O2/Ar gas sputtering mixture. This is consistent with the native

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83 background n -type doping being due to oxygen vacancies, as reported previ ously [25] The maximum mobility achieved was ~20 cm2.V1.s1. For TFT applications, it is important to have a high enough conductivity in the channel to achieve good drive currents, but the conductivity must be low enough to be able to modulate the curren t through the gate voltage and achieve pinch -off. Another necessary feature of the use of IZO layers for TFTs on glass or flexible substrates is the need for good Ohmic contacts processed at room temperature. Figure 5 4 shows the specific contact r esistance and sheet resistance under the contacts of both types of metal contacts on I n Z n O films deposited under different conditions. Specific contact resistances in the range 3 8 x105 2 were obtained for these contacts without any annealing. This is an attractive result if TFTs on flexible substrates that cannot be heated are envisioned. 5.4 Conclusions In Z n O films with conductivity controlled over a range of approximately six orders of magnitude have been deposited at room temperature by sputtering. The most important parameter in controlling the conductivity is the oxygen partial pressure in the sputtering ambient. The electron mobility in the films is typically in the range 5 20 cm2.V1.s1.These films looks promising for TFT applications on low co st substrates.

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84 Figure 5 1. Sputter deposition rate and In/Zn ratio in I n Z n O films as a function of In2O3 target power or chamber working pressure.

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85 Figure 5 2. XRD 2 scans of In2O3 and InZnO films deposited at room temperature and effect of In2O3 target power on the XRD spectra from InZnO films.

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86 Figure 5 3. Resistivity,carrier concentration and electron mobility in I n Z n O films as a function of In2O3 target power or oxygen percentage in the O2+Ar sputtering ambient.

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87 Figure 5 4 Specific contact resistance and sheet resistance under the contact area of Ni/Au and Ti/Au Ohmic contacts on I n Z n O films deposited under different conditions

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88 CHAPTER 6 INGAZNO BASED THIN FILM TRAN SISTORS FABRICATED O N GLASS SUBSTRATE AT LOW TEMPERATURE 6.1 Introduction Transparent conducting oxides (TCOs) are attracting interest for applications like transparent thin film transistors (TFTs), transparent electrodes in various optoelectronic devices, UV detection and chemical sensors because of thei r high electrical conductivit y and high optical transparency In particular, there has been much interest in new materials for transparent electronics that utilize non Si materials deposited at low temperature on cheap (e g. glass) and/or flexible (e g. pl astic or paper) substrates. Most conventional thin -film transistors in display application use a hydrogenated amorphous silicon ( -Si:H) or an organic semiconductor layer as a channel. However, device performance is sometimes limited by the relatively low fie l d effect mobilit ies (<1 cm2.V1.s1 for -Si:H, ~ 2.7 cm2.V1.s1 for pentacene single crystal s and ~ 1.5 cm2.V1.s1 for pentacene thin film s ). In addition, Si -based TFTs have limitation s in some applications, including light sensitivity and opaquen ess. One of the promising alternatives involves amorphous or nanocrystalline n-type oxide semiconductors such as zinc oxide, indium gallium oxide, zinc tin oxide and indium zinc oxide [43 57] These materials show surprisingly high electron mobilties (~ 10 cm2.V1.s1) even for amorphous films deposited at room temperature or slightly above. High electron mobilities in the TFT channe l translate to higher switching speeds Furthermore, the amorphous films have the potential for better TFT performance and sta bility than polycrystalline films because of the lack of grain boundaries in the channel. One issue to date with amorphous ZnO -based TFTs has been device stability. In this section we investigate on the dc performance and long-term stability of In G a Z n O thin film transistors fabricated on glass substrates near room temperature using a single target. The resistivity and carrier concentration of channel in TFTs were controlled by deposition power.

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89 The gate dielectric s used were SiNx and HfO2 deposited by P E CVD at ~ 70 and sputter at room temperature, respectively The I n G a Z n O films are shown to be attractive candidates as channel materials for enhancement -mode TFTs with good mobility. 6.2 Experimental The films were deposited on glass substrates (Corning EAGLE 2947) by RF magnetron sputtering using a 3 inch diameter single target of InGaZnO4 near room temperature. The temperature at the substrate was ~ 40 after the I n G a Z n O deposition, as determined from temperature indicators attached to reference gla ss substrates during film deposition. The deposition power was varied from 75 to 300W, while the working pressure was held constant at 10 mTorr in a pure Ar ambient. At a deposition power of 140W, we obtained film s with carrier concentration of 6.5x1017 cm3 and resistivity of ~ 1 -cm obtained from Hall measurements. The typical thickness of I n G a Z n O films deposited was 50 nm, with root mean square roughness of ~ 1 nm measured over a 5 x 5 m2 area by tapping mode Atomic Force Microscopy (AFM). The films were amorphous as determined by powder x-ray diffraction (XRD). The bottom gate -type TFTs using In G a Z n O channel and different gate dielectrics ( 90 nm thick SiNx deposited at ~70 by PECVD and 100 nm thick HfO2 deposited at room temperature by sputter) were fabricated on glass sub strates, as shown schematically in f igure 6 1(top). The I n Z n O layers (150nm) served as the TFT electrodes (gate, source and drain) which were formed by RF magnetron sputtering near room temperature. The I n Z n O electrodes have a resistivity of <103 .cm with a carrier concentration of ~ 5x1020 cm3. An optical micrograph plan view of a TFT with a gate length of 6 m and a gate width of 100 m is also shown in f igure 6 1(bottom). The TFT structure was defined using photolithography and lift off processes. In order to evaluate dc characteristics of the TFTs, an Agilent 41 56C parameter analyzer was

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90 used. The long-term stability of the TFTs was confirmed by measuring the device characteristics in air at room temperature 6.3 Results and Discussion 6.3.1 TFT s with SiNx G ate D ielectric The effect of deposition power on electrical resistivity of the sputtered I n G a Z n O films is shown in figure 6 2. The film thickness was 100 nm, and working pressure was fixed at 10 mTorr, and no post annealing was carried out on the samples. The resistivity shows a sharp decrease with increasing deposition power (75W to 150W) and less change at higher power. The resistivity varied in the range from ~101 to 103 .cm with RMS roughness of ~ 1 nm. It is well established that an i ncrease of deposition power results in increase of film density [103] The decrease in resistivity may correspond to the higher kinetic energy of sputtered I n G a Z n O atoms arriving at the film surface, resulting in a higher film density and less dangling bo nds Figure 6 3 (top) shows IDS-VDS characteristics from I n G a Z n O TFTs with a 90 nm -thick SiNx gate dielectric. The transistor operates in enhancement -mode (i.e., positive gate voltage is required to turn on the drain current) and shows good saturation drain current. The channel in the transistor was deposited at a deposition power of 140W. VGS was increased from 0V to 4V in 1V steps, and IDS reaches ~ 0.17 mA at a VGS of 4V. Note that the curves do not show any evidence of decreasing separation between IDS curves at larger currents. Such effects are commonly ob served in oxide TFTs and are attributed to either an electron injection barrier at the source electrode or mobility degradation due to interface roughness scattering as channel electrons are brought into closer physical proximity to I n G a Z n O/SiNx interface with increasing VGS [34] We measured ~30 TFTs out of 240 TFTs on one glass substrate. More than 90% of TFTs showed excellent transistor operation with drain current onto off ratio of >104.

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91 Figure 6 3 (bottom) presents IDS and (IDS)0.5 as a function of VG S at a fixed VDS of 8V The transfer characteristic displays a low off -current of ~ 109A, drain current on to off ratio of >105, and the subthreshold voltage swing of ~ 0.5V.decade1. T hreshold voltage and saturation mobility, sat in the saturation regi on (VDS > VGS-Vth) w ere estimated from the intercept and slope of (IDS)0.5-VGS curve using the following saturation current equation: 22th GS ox sat DSV V L WC I (6.1) where FE is the saturation mobility, Cox is the capaci tance of the gate oxide, W is the gate width and L is the gate length. The threshold voltage and saturation mobility were ~ 2.1 V and ~ 17 cm2.V1.s1, respectively. The value of mobility is superior to that of the I n Z n O channel TFT s we have fabricated previously on sputter -deposited films [104] The influence of W/L on saturation mobility ( sat ) is shown in figure 6 4 The results show an increase of sat as W/L is decreased [105, 106] T h e maximum mobility was ~35 cm2.V1.s1 in the channel length of 76 m It is well known that the presence of source/drain parasitic resistance (RS and RD, respectively) results in a reduction of the mobility with decreasing channel length. T his is due to a relatively large fraction of the applied source/drain voltage drop over the parasitic resistance in short channel TFTs, as compared to long channel TFTs. To verify the longterm stability of the TFTs, saturation mobility and threshold voltage from a TFT with gate length of 6 m and gate width of 100m as a function of aging time is shown in f igure 6 5 Both sat and Vth display excellent stability for the measurement duration of more than 500 hours. Especially, Vth remains almost constant at least within experimental

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92 error ( 1.5%). The average saturation mobility and threshold voltage were ~ 6.1 cm2.V1.s1and 2.13 V, respectively. 6.3.2 TFTs with HfO2 G ate D ielectric To investigate the crystallinity of the channel deposit ed on a glass substrate, X ray diffraction pattern was measured ( f igure 6 6 ). The film was amorphous and optically transparent in the visible range, as seen in the inset of f igure 6 6 The optical transmittance in the visible range was ~ 80% for the film i nvestigated, including the reflection and absorption associated with the film and glass substrate. In transparent conducting oxide films there is always some trade off between transparency and conductivity, but these films retained good transmittance at co nductivities suitable for transistor fabrication. The typical IDS-VDS I n G a Z n O TFTs with 100 nm -thick HfO2 gate dielectrics are shown in f igure 6 7 (top) It is observed that the transistor operates in enhancement -mode due to little drain current at zero gate voltage. Enhancement -mode operation is preferable to depletion -mode since it is not necessary to apply a gate voltage to turn off the transistor, which significantly reduces power consumption of the TFTs. The saturation current w as ~ 0.12 mA at a VGS of 2.5V. Figure 6 7 (bottom) shows the corresponding transfer characteristic, IDS and (IDS)0.5, as a function of VGS at a fixed VDS of 4V. The drain current on-to off ratio was ~105 with a low off -current of ~ 109 A, and the subthres hold gate -voltage swing was 0.25 V.decade1. The threshold voltage (Vth) and saturation mobility (sat) in the saturation region (VDS > VGS-Vth) were estimated from the intercept and slope of (IDS)0.5-VGS curve using the saturation current equation The th reshold voltage and saturation mobility were ~ 0.44 V and ~ 7.18 cm2.V1.s1, respectively. Figure 6 8 shows saturation mobility of the TFT as a function of aging time. The sample was maintained at room ambient for 500 hours at room temperature and measur ed for another

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93 500 hours. The mobility remained almost constant within experimental error even after 1000 hours. The average saturation mobility was 7.65 cm2.V1.s1. Figure 6 8 also presents the effect of aging time on threshold voltage of the TFT. The Vt h shows always positive values and is slightly increased with time under the experiment. This demonstrates that the TFT remains in enhancement -mode operation. The threshold voltage shift may be caused by the bias stress during measurement, resulting in the defect state creation in the channel. Powell et al. suggested that deep -state defect creation is dependent on stress time and strongly affected by temperature in Si:H TFTs [107] For our devices, th is influenced by stress time because measurement tem perature was kept constant. However, the most important thing in the figure 6 8 is that th after 1000 hours was as small as 460 mV 6.4 Conclusions W e have examined enhancement -mode TFTs based on amorphous I n G a Z n O channel and SiNx or HfO2 gate dielectric s. Both devices showed high saturation mobility low threshold voltage (< 2.5 V) low subthreshold gate -voltage swing (< 0.5 V.decade1) and high drain current on -to -off ratio (> 104). After 1000 hours aging time a t room temperature, the saturation mobility of TFTs with HfO2 gate dielectrics was almost constant while the threshold voltage shift was as small as 460 mV The I n G a Z n O TFTs fabricated at low processing temperature are suitable for application s on organic flexible substrates.

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94 Figure 6 1. Schematic of I n G a Z n O channel transistor and an optical micrograph plan view of competed device.

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95 Figure 6 2. Change of electrical resistivity of sputtered I n G a Z n O films as a function of deposition power.

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96 Figure 6 3. IDS-VDS chara cteristics and transfer characteristics from I n G a Z n O transistors with 90 nm thick SiNx gate dielectric.

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97 Figure 6 4. Dependence of the saturation mobility for I n G a Z n O TFT as a function of W/L.

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98 Figure 6 5. The change of saturation mobili ty and threshold voltage for -In G a Z n O TFT as a function of aging time.

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99 Figure 6 6. n G a Z n O film deposited at 140W RF power.

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100 Figure 6 7. IDS-VDS characteristics and IDS and (IDS)0.5 of I n G a Z n O T FT with 100 nm thick HFO2 gate dielectric.

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101 Figure 6 8. Change of saturation mobility and threshold voltage for InGaZnO TFTs as a function of time.

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102 CHAPTER 7 INTERFACE DEPENDENT ELECTRICAL PROPERTIE S OF AMORPHOUS INGAZ NO THIN FILM TRANSISTOR S 7.1 Introduction Recently, InGaZnO4 films have attracted much attention as an active channel layer for applications in flexible electronic devices. Th is material show s high electron mobility (> 10 cm2.V1.s1) even for amorphous ( -) films deposited near room temperature. High electron mobilities in the channel translate to high switching speeds of the devices -films have the potential for better TFT performance and stability than polycrystalline films because of the lack of grain boundarie s in the channel [108] A key aspect to achieving good performance of these TFTs is the choice of gate dielectrics. T he quality of dielectric/oxide interface plays an important role in TFT characteristics. A p oor interface between the channel and gate -diel ectric leads to large interface trap density and reduced carrier transport properties which causes a degradation of device p arameters such as leakage current, saturation mobility, and subthreshold gate voltage swing [109112]. While some previous reports have examined electrical characteristics of InGaZnO4 TFTs with different gate dielectrics, including silicon dioxide (SiO2), titanium silicon dioxide (TiSiO2), aluminum titanium oxide (ATO), silicon nitride (SiNx), hafnium oxide (HfO2), yttrium oxide (Y2O3) and MgO BST, there has been very little research on the properties of channel and gate dielectric interface [56, 113116] In this section we report on the electrical properties of InGaZnO4-based TFTs fabricated on glass substrates with SiO2, SiON or SiNx deposited by PECVD at 250 C as gate dielectrics for the transistors. The thickness of gate dielectrics was fixed at 100 nm. The effect of different gate dielectrics on the perform ance of InGaZnO4 TFTs is described in detail.

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103 7.2 Experimental The channel layer was deposited on glass substrates by RF magnetron sputtering at room temperature using a 3 inch diameter InGaZnO4 single target (99.9%, Kurt J. Lesker). For the film depositio n, RF power of 150W and working pressure of 10 mTorr were employed in a mixed ambient of Ar/O2. The typical thickness of the channel layer was 40 nm, with RMS roughness of ~ 1 nm measured over a 5 5 m2 area by tapping -mode AFM. 100 nm thick gate dielectric films were prepared on the InGaZnO4/glass substrates using a Unaxis SLR 730 PECVD at RF power of 50W. During the deposition, working pressure and substrate temperature were held constant at 900 mTo rr and 250 C, respectively. Different film compositions (SiO2, SiON and SiNx) were obtained by changing the flow rates of SiH4, N2O and NH3 gases. The refractive index, dielectric constant and leakage current of the gate dielectrics were characterized with Ellipsometer, C -V and I -V measurement system, respectively. To investigate the interface roughness of channel and gate dielectrics, X -ray reflectivity (XRR) measurement was performed. For XRR spectra, an X ray mirror and parallel plate collimator were use d as the primary and secondary optics, respectively. The scan conditions for the sample were 0.005 step. The topgate InGaZnO4 TFTs with a gate length of 16 m and a gate width of 100 m were fabricated on glass substrate s, as shown schematically in figure 7 1 (top). RF -sputtered Ti (10nm)/Au (40nm) metals were used as the gate, source and drain for the TFTs. The TFT structure was defined by standard photolithography and lift -off processes. The photograph of the device fabricated here is also shown in figure 7 1 (bottom). The device characterization was carried out at room temperature using an Agilent 4156C parameter analyzer.

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104 7.3 Results and Discussion Figure 7 2 (top) shows the refractive index of gate dielectric films as a function of N2O flow rate in the precursor gas mixture (SiH4/N2O/NH3). The refractive indexes were changed from 1.46 0.01 to 1.76 0.0 1 as N2O flow rate was decreased from 200 to 0 sccm. At N2O flow rate of 200 sccm, the film showed a refractive index cl ose to that of silicon dioxide, while it was similar to silicon nitride at N2O flow rate of 0 sccm. This is attributed to the more chemically active nature of oxygen radicals which react with SiH4 radicals, thereby suppressing the formation of Si N bonds i n the films. The corresponding RMS roughnesses of SiO2, SiON and SiNx films were 3.79 nm, 2.69 nm, and 1.65 nm, respectively as shown in figure 7 2 (bottom). Fig ure 7 3 shows the current density-electric field characteristics of three different gate diel ectrics measured in metal insulator -metal (MIM) structure s A wide band gap insulator is expected to significantly reduce the leakage current due to it s low dielectric constant. However, our analysis of the gate dielectrics in the structure has indicated t hat there was no apparent change of current density with increasing electric field. The measured leakage current densities of the gate dielectrics were in the range of 4 106 1 105 A.cm2 at 1 MV.cm1. Based on the above results, the optimum gate dielectric was SiNx film which has a reasonably low leakage current and relatively high dielectric constant (~6.9), resulting in low operation voltage for TFTs. The effect of channel/gate -dielectric interface on TFT performance, the transfer characteristics at a fixed VDS of 7 V are shown in the transfer characteristics in figure 7 4. The TFTs with three different gate dielectrics were fabricated under the same processing conditions. It is evident that the subthreshold slope ( S ) of the nitride dielectric device is steeper than that of the oxide dielectric device. The S values for TFTs with SiO2, SiON and SiNx gate dielectrics were 0.9, 0.63 and 0.42 V.decade1, respectively. This indicates that the trap density at

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105 InGaZnO4/SiO2 interface is larger than that of IG ZnO4/SiNx interface. In order to confirm this, the interface trap density was calculated by the equation 7.1, assuming the traps are isotropic18: q C q KT S e NOX t 1 / ) log( (7.1) where, k is Boltzmann s constant, T is the temperature, q is t he electric charge, S is the s ubthreshold gate -voltage swing, and Cox is the capacitance of gate dielectrics (38.1, 45.9 and 61.1 nF.cm2 for SiO2, SiON and SiNx, respectively). The values of Nt were ~ 3.38 1012 cm2 for SiO2, 2.76 1012 cm2 for SiON, and 2.33 1012 cm2 for SiNx. In some cases, the interface of channel and gate dielectric override s the effect of dielectric constant on TFT performance. One of the most important parameters for TFTs is the saturation mobility which is correlated with interfac e roughness of channel/gate dielectric. To clarify the influence of interface roughness on saturation mobility, XRR measurement was performed using multi -layer model. The thickness and roughness of the InGaZnO/gate -dielectric layers were obtained using the Wingixa software from PANanalytical. Table 7 1 summarizes the fitted results. The simulated interface roughnesses of the layers were found to be in good agreement with surface roughnesses of the films measured from AFM shown in figure 7 2 (bottom) The in terface roughnesses were 4.46 nm for InGaZnO4SiO2 and 1.94 nm for InGaZnO4-SiNx, which suggests that there is significant scattering of carriers by trapped charges at the InGaZnO4/SiO2 interface. The resulting saturation mobilities were 5.2 cm2.V1.s1 fo r SiNx and 1.75 cm2.V1.s1 for SiO2. Therefore, it is concluded that the quality of interface has a large effect on TFT performance. Fig ure 7 5 (top) shows typical output characteristics ( IDS-VDS) for -InGaZnO4 TFTs with SiNx gate dielectric. The gate l ength and width of the TFTs were 16 m and 100 m, respectively

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106 The transistors operated in enhancement -mode with little drain current at zero gate bias, and exhibited clear pinch -off voltage and current saturation. The corresponding transfer characteristic s for the TFTs are shown in figure 7 5 (bottom). The subthreshold gate -voltage swing was 0.42V.decade1 and given by the maximum slope in the log( IDS) VGS curve. The threshold voltage was 2.37 V, saturation mobility was 5.2 cm2.V 1.s1, and drain current o n -to off ratio was 8 104 with low off -off current of 6 1010 A. Note that the device leakage current is very small, in the 109 1010 A range. This demonstrates that SiNx gate dielectric is a good candidate for producing high performance InGaZnO4 TFTs with better quality interface. 7.4 Conclusions W e investigated the effect of different gate dielectrics on electrical properties of InGaZnO4 TFTs. SiNx as a gate dielectric was shown to significantly improve the device performance, resulting in the enhanceme nt of saturation mobility, drain current on -to -off ratio and subthreshold gate voltage swing. This is ascribed to the reduction of the interface trap density and smoother interface roughness between InGaZnO4/SiNx.

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107 Table 7 1. The fitted XR R results of different gate dielectrics/InGaZnO S ample T hickness (nm) R oughness (nm) SiO 2 /InGaZnO 102/35 4.46 SiON/InGaZnO 104/35 2.69 SiN x /InGaZnO 107/35 1.94

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108 Figure 7 1. A sc I n G a Z n O thin film transistor and photograph of the device.

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109 Figure 7 2. Refractive index and RMS roughness of three different gate dielectrics.

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110 Figure 7 3. Current density -electric field characteristics of three different gat e dielectrics measured in MIM structure.

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111 Figure 7 4. The transfer characteristics for InGaZnO4 TFTs with different gate dielectrics at a fixed VDS = 7V.

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112 Figure 7 5. The typical output characteristics and transfer characteristics of InGaZnO4 TFTs with SiNx gate dielectric.

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113 CHAPTER 8 FABRICATION OF THIN FILM TRANSISTORS ON FLEXIBLE SUBSTRATES 8.1 Introduction Thin film transistors (TFTs) are widely used in electronic devices such as liquid crystal displays (LCDs) and radio frequen cy identification (RFID) tags The fabrication of TFTs on flexible substrates at low temperature is a key issue for potential applications such electronic paper that displays text and images, very large area solar cell s and television screen s capable of b eing rolled up for transport and storage Recently, there has been a strong interest in the use of InGaZnO4 film as a channel layer of TFTs. Th is material show s uniform structure, smooth surface (RMS roughness ~ 1 nm), and high electron mobility (> 10 cm2.V1.s1) even for an amorphous film deposited at room temperature or slightly above. A s mooth sur face of the channel layer is favorable for TFTs because the scattering effect by trapped charges at channel/gate dielectric interface can be reduced, and h igh electron mobilit y in the channel translate s to high switching speed of the devices In addition it is possible to control the In G a Z n O channel conductivity by changing the oxygen partial pressure in the Ar/O2 gas mixture during film deposition. Some previous reports on InGaZnO4 TFTs have been p resented using glass substrates flexible substrates (PEN or polyimide) [117, 118] and even paper [119, 120] However there are no reports on InGaZnO4 TFTs fabricated on polyimide tape. The clean room tape has a low tack adhesive which enables it to be easily attached and removed without leaving marks and residue s. In this section we report on the electrical performance of InGaZnO4 TFTs fabricated on two different substrates ( polyethylene terephthalate and polyimide clean -room tape ) at low temperature (<100 C). The TFTs showed good electrical properties (low threshold voltage, high

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114 saturation mobility), indicating that fle xible -transparent displays should be feasible on a number of cheap substrates 8.2 InGaZnO TFTs on PET substrates 8.2.1 Experimental The channel was deposited on PET substrates by RF magnetron sputtering at room temperature using a 3 inch diameter InGaZnO4 single target The film was amorphous as determined by powder x ray diffraction (XRD), and showed optical transmittance of ~80% in the visible range. The thickness, roughness and density of the layers were identified by X ray reflectivity (XRR). The bott om gate -type TFTs were fabricated I n G a Z n O channel sputtered at room temperature and different gate dielectrics (130nm thick SiO2 and 80nm thick SiNx) deposited by PECVD at 90 C In2O3 and In Z n O layers served as the TFT electrodes ( gate, sou rce and drain) which were formed by RF magnetron sputtering at room temperature. T h e sheet resistances of In2O3 and InZnO electrodes were <20 1 and ~60 1, respectively. The TFT structure was defined using standard photolithography and lift -off p rocesses. Photographs of the device fabricated here are shown in figure 8 DC characteristics and long -term stability of the TFTs were measured using an Agilent 4156C parameter analyzer. 8.2.2 Results and Discussion Figure 8 2 shows typical output characte ristics (IDS-VDS) for InGaZnO TFTs with SiO2 (top) or SiNx (bottom) gate dielectric. Both transistors operate in enhancement -mode with little drain current at zero gate voltage. It is also observed that the drain currents exhibit clear pinchoff voltages and current saturatio n, which means that the TFTs follow the standard field effect transistor characteristics. The saturation currents were ~0.023 mA for SiO2 gate dielectric and ~0.027 mA for SiNx gate dielectric at the bias conditions of VDS=5V and VGS=2.5V. The

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115 corresponding transfer characteristics at a fixed VDS=5V are shown in fi gure 8 3. There are a few observations from the IDS and ( IDS)0.5 versus VGS curves. Both TFTs showed the drain current on to -off ratio of >105 with a low off current of <109A. It demonstrates tha t these are promising for the applications on high resolution flexible displays which are required to have a relatively large on -current to drive pixels and small off-current to minimize power consumption. For InGaZnO TFTs with SiNx gate dielectric, the subthreshold gate -voltage swing (S) was 0.35V.decade1 and given by the maximum slope in the transfer characteristic curve. The capacitance per unit area (Cox,SiNx) of SiNx gate dielectric was determined to be 88nF.cm2. The threshold voltage ( Vth) and sat uration mobility ( sat) in the saturation region were 1.25V and 12.1 cm2.V1.s1, respectively. This is comparable to the mobility reported for the InGaZnO TFTs fabricated on glass substrates [116, 121] The choice of g ate dielectric materials and the channel/gate dielectri c interface are essential parameters which directly relate to transistor performance. T h e higher dielectric constant increases the transistor capacitance so that the transistor can switch properly between on and off states at low operating voltage beca use the high carrier density in the channel layer can be induced at a relatively low voltage range. From the transfer characteristics in Figure 3, we observed that the SiO2 TFTs showed somewhat inferior electrical properties ( sat ~11.5 cm2.V1.s1, Vth ~1.32V and S ~0.42V.decade1) to the SiNx TFTs. This result is attributed to the lower dielectric constant ( ,SiO2 ~4.6 and ,SiNx ~8), resulting in lower capacitance ( Cox,SiO2 ~31nF.cm2) and thereby lower on-current and threshold voltage. In order to investigate the effect of interface roughness of the channel /gate dielectric on the device performance, XRR measurement was performed using multi -layer model. The interface roughness es (2.4 8 nm and 2.46nm, respectively ) of I n G a Z n O S iO2 and InGaZnO -SiNx w ere close to the surface roughness

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116 (2. 27 nm) of I n G a Z n O film (not shown here) which can significantly reduce the scattering effect of carriers by trapped charges at the I n G a Z n O /gate dielectric interface. Therefore, the main influence on electrical properties of InGaZnO TFTs in this study could be the gate dielectric material. Figure 8 4 (top) shows threshold voltage and saturation mobility of the TFT s with SiO2 gate dielectric as a function of aging time at room temperature The TFTs displayed reasonable stability at room temperature, lasting for nearly 500 hours. For our TFTs, sat remained almost constant within experimental error during the measurement duration, while Vth was slightly increased with aging time and its shift rate was 30mV/100h as also shown in Figure 8 4 (top and bottom). This may have been due to the bias stre ss during measurement, resulting in the defect state creation at channel/gate dielectric interface (25). The average sat was 11.1 cm2.V1.s1 and the Vth shift was 150mV after 500 hours aging time. In addition, the subthreshold gate voltage swing and dra in current on -to -off ratio were almost unchanged at ~0.4/decade and ~105, respectively. 8.2.3 Conclusions E nhancement -mode -InGaZnO channel TFTs with SiO2 or SiNx gate dielectric fabricated on flexible PET substrates exhibited high saturation mobility of >11cm2.V1.s1 and high drain current on to -off ratio of >105. The saturation mobility was almost constant while threshold voltage shift of the TFTs with SiO2 gate dielectric was 150mV after more than 500 hours aging time at room temperature. IG ZO TFTs fabricated at low processing temperature are promising for transparent flexible electronics applications with longterm stability

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117 8.3 InGaZnO TFTs on Polyimide Clean Room Tape 8.3.1 Experimental InGaZnO4-based TFTs were fabricated on a 3M polyimide clean room tape at low temperature. Prior to the fabrication, the clean -room tape was attached to a glass carrier for mechanical support. A 120nm thick indium tin oxide (ITO) served as a gate electrode which was deposited by RF magnetron sputtering at room tempe rature. The sheet resistance of ITO film was ~100 1. The SiNx gate dielectric was prepared on ITO/polyimide tape using a Unaxis SLR 730 PECVD at 90 C. Then, a 50nm thick channel layer was formed by RF sputtering at room temperature using a 3 inch diamet er InGaZnO4 single target. The Ti (20nm)/Au(80nm) source and drain electrodes were patterned on the channel layer using standard photolithography and lift -off processes. Figure 8 5 shows photographs of the TFTs The device characterization was carried out in air at room temperature using an Agilent 4156C parameter analyzer. 8.3.2 Results and Discussion Figure 8 6 (top) shows the typical output characteristics ( VDS-IDS) for -InGaZnO4 TFTs with a channel width of 100 m and a channel length of 6 m. The VGS was varied from 0 to 4V in 1V steps. The transistor operated in enhancement -mode with little drain current at zero gate voltage and exhibited good drain current saturation. A high saturation current was 42 A under the bias condition of VDS =5V and VGS =4V. The curves did not show any evidence of current crow d ing at low VDS, indicating low resistivity of source and drain contacts. The field effect mobility ( FE) was estimated from the linear region in IDSVDS curve using the saturation equation The estimated value of the field effect mobility was 5.36 cm2.V1.s1 at VDS =0.5V. The corresponding transfer characteristics at fixed VDS =5V are shown in figure 8 6 (bottom). Note th at these electrical characteristics are comparable to those of the oxide TFTs we have fabricated previously on either glass or PET substrates under the same conditions [116, 121, 122] The TFT

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118 displayed subthreshold gate -voltage swing (S) of 0.55V.decade1 and drain current on -to -off ratio of approximately 105 with a n off-current of 3 109A. The saturation mobility and threshold voltage were 5.28 cm2.V1.s1 and 1.1V, respectively calculated from the slope and intercept of the ( IDS)0.5 versus VGS curve in the saturation region Th is mobility value is in good agreement with the field effect mobility obtained from the linear region in the IDS-VDS curve. The transfer curves were also recorded while attaching and detaching the device from the glass substrate. A ll device parameters were almost identical except that off -current was slightly increased. These results demonstrate that TFTs fabricated on a polyimide clean room tape can be used for flexible adhesive displays and electronic papers. In order to compare electrical properties of the device before and after roll up, it was intentionally bent and completely rolled up. Figure 8 7 shows plan view optical micrographs of the device before (left) and after (right) roll up. While the as -fabricated TFT shows relati vely smooth morphology, there was considerable surface crack ing over the entire device after roll up. This result s in degradation of device performance. The transfer characteristics of the TFT before and after roll up are shown in f igure 8 8 The device ch aracteristics ( sat= 0.05cm2.V1.s1 and Vth= 2.5V) were severely degraded after roll up compared to as -fabricated TFT. Although the drain current was still modulated by the gate voltage, as shown in the inset Figure 4, the off current of the device was significantly in creased up to ~107A. Thus, the device reliability after roll up is a n issue that should be further address ed for adhesiverollable display applications. 8.3.3 Conclusions Amorphous InGaZnO4 TFTs fabricated on polyimide clean -room tape at <100 C show surpr isingly good dc performance, demonstrating their potential for inexpensive -flexible -

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119 adhesive transparent electronics and display applications. Future work will focus on achieving mechanically and electrically reliable TFTs for next generation display s. 8. 4. InGaZnO TFTs on C ellulose P aper 8.4. 1 Experimental InGaZnO4-based TFTs were fabricated by RF -magnetron sputtering at room temperature using cellulose paper. The 150 m thick cellulose paper was used as both a substrate and gate dielectric in the TFT str ucture as reported previously [ 119] and as shown schematically in figure 8 9 (top). T he device was constructed on both sides of the paper. To define the gate electrode, a 120 nm thick ITO (In2O3-SnO2) film was first deposited by sputtering at room tempera ture on one side of the paper. The sheet resistance of ITO was ~ 100 1. Then, the IZGO channel layer with thickness of ~ 50 nm was deposited on the other side of the paper at room temperature using a 3-inch single target. For the channel layer depositi on, the RF power and working pressure were 150 W and 10 mTorr in a mixed ambient of Ar/O2, respectively. The n -type carrier concentration in the film was ~ 1016 cm3. Finally, sputtered Ti (20 nm)/Au (80 nm) source and drain electrodes were formed on the c hannel layer using standard photolithography and a lift -off process. A scanning electron microscopy (SEM) plan -view image of the competed device is also shown in figure 8 9 (bottom). The channel length and length to -width ratio were 6 m and 1:20, respectiv ely. To determine the dielectric constant of the cellulose paper, C -V measurement s w ere performed at 1 MHz. For the metal -insulator -metal (MIM) structure, Al was evaporated through a metallic shadow mask on both sides of the paper. The device dc characte rization was carried out in air at room temperature using an Agilent 4156C parameter analyzer

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120 8.4.2 Results and Discussion The surface images of a cellulose paper before and after channel deposition are shown in figure 8 10. The InGaZnO4 film deposited on the paper was somewhat rough to the eye, which is attributed to the relatively high surface roughness of the control paper. One of the most important factors for high performance TFTs is the quality of the interface between the channel and gate dielectric The existing surface morphology of the paper, acting as a gate dielectric in this study, obviously affects the interface roughness, suggesting that the device performance will be degraded due to a large interface trap density and high interface roughness between channel and gate dielectric [123] Fig ure 8 11 shows the typical output characteristics ( VDSIDS) for InGaZnO4 TFTs with a 150 m thick -cellulose -paper gate dielectric at different gate voltages ( VGS). The channel length (L ) and channel width ( W ) were 6 m and 120 m, respectively. The transistors operated in enhancement -mode with little drain current at zero gate voltage. A saturation current of 23 A was obtained at a VGS =40V. In the low drain voltage region current -crowding behavior was obs erved, indicating a relatively high resist ance of the source and drain contacts. The absorption of developer chemicals by the cellulose paper during the photolithography process leads to uneven surfaces resulting in poor O hmic contact reproducibility on t he channel layer. The corresponding transfer characteristics ( VGS IDS) for the device in the saturation region ( VDS =40V) are shown in figure 8 12. The device exhibited a low off -current of ~ 109A and drain current on to -off ratio (ION/IOFF) of ~ 104. For tunato et al. suggested that the open structure of the cellulose paper can cause the severe degradation of off -current in the transistor [119] However, the cellulose paper used in this study has a relatively compact structure, as shown in figure 8 13. As a result, the low off -current was improved by two orders of magnitude relative to devices reported previously on other cellulose papers. Note that the subthreshold gate -voltage swing ( S )

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121 for the paper -based TFT was relatively high ( S =2.4 V.decade1), indi cating that there was considerable carrier scattering by trapped charges at the InGaZnO4/paper interface. The high value of S may have resulted from both the poor O hmic contact and rough surface of the paper as discussed above. The saturation mobility ( sat) and threshold voltage ( VTH) were estimated from the slope and x axis intercept of VGS (IDS)0.5 curve using the standard saturation current equation. The sat and VTH were 35 cm2.V1.s1 and 3.75 V, respectively, where the capacitance per unit area wa s 40.48 pF.cm2. The corresponding effective dielectric constant ( keff) of the paper was ~ 6.8. All device parameters obtained here were comparable to those of InGaZnO4 TFT s fabricated previously on glass or flexible substrates (PET or Polyimide) [122, 124]. Although there is still problem s of chemical absorption during wet process steps such as lithography, cellulose paper appears to be a promising candidate as a gate dielectric for low -cost flexible electronic applications. 8.4.3 Conclusions We have exami ned the electrical characteristics of InGaZnO4 TFTs fabricated on a cellulose paper at room temperature. The cellulose paper was used as both a gate dielectric and a substrate for mechanical support. The transistor showed good performance: low threshold voltage (3.75 V) and high saturation mobility (~ 35 cm2.V1.s1). This demonstrates that a cellulose paper is promising for a gate dielectric in low -cost display applications.

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122 Figure 8 1. P hotographs of the competed device

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123 Figure 8 2. The typical output characteristics of InGaZnO TFTs with SiO2 or SiNx gate dielectric.

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124 Figure 8 3. The transfer characteristics I n G a Z n O TFT s at a fixed VDS=5V.

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125 Figure 8 4. Change of saturation mobility and threshold voltage for In G a Z n O TFT s with SiO2 gate dielectric as a function of aging time at room temperature and transfer characteristics after 500 aging time

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126 Figure 8 5. S c I n G a Z n O thin film transistor and photographs of the device.

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127 Figure 8 6. T ypical output characteristics and transf er characteristics of InGaZnO TFTs with SiNx gate dielectric.

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128 Figure 8 7. Plan view optical micrographs of the device before and after roll up

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129 Figure 8 8. T ransfer characteristics of InGaZnO TFTs before and after roll up (the inset shows the output characteristics after roll up).

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130 Figure 8 9. S c I n G a Z n O thin film transistor and SEM plan -view image of the device.

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131 Figure 8 10. S urface images of cellulose paper before and after channel deposition.

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132 Figure 8 11. The typical output characteristics of InGaZnO TFTs with 150 m thick paper gate dielectric

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133 Figure 8 12. The transfer characteristics of InGaZnO TFTs VGS was swept from 10 to 40V at a fixed VDS = 40V.

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134 Figure 8 13. SEM cross -section images of cellulose paper with thickness of 150 m.

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135 CHAPTER 9 CONCLUSIONS The development of transparent oxides for thin -film field effect transistors and the room temperature fabrication of the devices having low volta ge operation offer flexibility in designing the devices and contribute to the progress in next generation display technologies based on transparent displays and flexible displays. The focus of this research is toward commercialization of oxide -based thin f ilm transistors The topics included fabrication of long -term -stable oxide based thin film transistors (TFTs) on either glass or flexible substrates (PET, Polymide, and paper) and the effect of gate dielectrics on device performance. In addition, process d evelopment such as plasma etching and Ohmic contact formation for oxide heterostructures was also investigated. The etch mechanism for ZnO and InZnO in various plasma chemistries such as CH4/H2/Ar, C2H6/H2/Ar, Cl2/Ar, IBr/Ar, BI3/Ar, and ICl/Ar has been examined. For all plasma chemistries, etch rates of ZnO and InZnO increased with ion energy as predicted from an ion assisted chemical etching process. It was also found that etch rate in ethane (C2H6) -based chemistries was faster than methane, chlorine, or interhalogens -containing chemistries because of volatile etch by -products. T he near -surface stoichiometry after etching is similar to that on the as received sample independent of plasma chemistries, and h igh fidelity pattern transfer in CH4/H2/Ar chemi stry can be achieved with a very smooth surface, although the sidewalls were not completely vertical. These results demonstrated that C2H6/H2/Ar, CH4/H2/Ar, and Ar/Cl2 plasma chemistries are more attractive than Ar/IBr and Ar/BI3 for ZnO and I nZnO etching for the fabrication of devices like ZnO -based LEDs. Ni/Au (200 /800 ), Ni/Au/Ir/Au ( 200 / 800 / 500 /800 ) and Ni/Au/X/Ti/Au (200 /800 /500 /200 /800 ) metallization was considered for Ohmic contacts to p CuCrO2,

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136 where X is TaN, ZrN, W2B5 or CrB2. The minimum specific contact resistance of 5 104 .cm2 for moderate ly doped film was obtained after annealing at 500 C and the resistance was 1 104 .cm2 for the heavily doped film, even in the as -deposited state. While t here was a serious degradation after 500 C annealing due to both decomposition of the CuCrO2 layer and in diffusion of Ni and Au the use of Ir as the diffusion barrier increased the thermal stability by ~ 200 C The deposition and characterization of transparent conducting oxides (InZnO, InGaZnO) for transparent electrodes in optoelectronic device appl ications were examined as a function of sputtering power, working pressure and oxygen partial pressure in the sputtering ambient The most important parameter in controlling the resistivity w hich was varied from 103 to 103 is the oxygen partial pressure The corresponding electron mobilities were 5 20 cm2. V1. s1. The optical transmittance of the IZO films was ~ 70% in all cases. Ohmic contact resistances in the range of 3 8 105 cm were obtained with both Ni/Au and Ti/Au deposited by electron beam evaporation Enhancement -mode TFTs based on amorphous InGaZnO channel were fabricated on either glass or plastic substrates at low temperature (< 100 C). The InGaZnO TFTs operated in enhanceme nt mode and showed low operati ng voltage s in the range of 0.5 2.5 V, drain current on -to -off ratio s of ~ 105, sub threshold gate -voltage swing of 0.25 0.5 V.decade1, and high saturation mobilities of 5 12 cm2.V1.s1. The device characteristics exhibited small shifts during 1000 hours aging time at room temperature. It is also demonstrated that SiNx as a gate dielectric deposited by PECVD at 250 C was shown to significantly improve the device performance such as the enhancement of saturation mobility, drai n current onto off ratio and subthreshold gate voltage swing relative to SiO2 or SiON due to the reduction of the interface trap density and

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137 smoother interface roughness between InGaZnO4/SiNx. Significant challenges remain, including improving the stabili ty of the devices under bias, lowering the operating voltages, replacing metal contacts with conducting polymers that should be more resistant to cracking on rolling up of flexible substrates and developing large area printing processes that are compatible with manufacturing these devices on very large areas.

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138 LIST OF REFERENCES 1 J.C. Bean, in High -Speed Semiconductor Devices, edited by S.M. Sze, John Wiley & Sons, New York, NY, 1990. 2 S.M. Sze, Physics of Semiconductor Device s, John Wiley & Sons, New York, NY, 1981. 3 D. C. Look, D. C. Reynolds, C. W. Litton, R. L. Jones, D. B. Eason, and G. Cantwell, App. Phys. Lett. 81, 1830 (2002). 4 D. C. Look, D. C. Reynolds, J. R. Sizelove, R. L. Jones, C. W. Litton, G. Cantwell, and W. C. Harsch, Solid -State Commun 105, 399 (1998). 5 A. Tsukazaki, A. Ohtomo, T. Onuma, M. Ohtani, T. Makino, M. Sumiya, K. Ohtani, S. F. Chichibu, S. Fuke, Y. Segawa, H. Ohno, H. Koinuma, and M. Kawasaki, Nature Materials 4 42 (2005). 6 A. Tsukazaki, M. Kubota, A. Ohtomo, T. Onuma, K. Ohtani, H. Ohno, S. F. Chichibu, and M. Kawasaki, Jpn. J. Appl. Phys. Part 2 -Lett ers & Express Letters 44, L643 (2005). 7 J. H. Lim, K. -K. Kim, D. -K. Hwang, H. -S. Kim, J. Y. Oh and S. J. Park, J. Electrochem. Soc. 152, G179 (2005). 8 S. J. Jiao, Z. Z. Zhang, Y. M. Lu, D. Z. Shen, B. Yao, J. Y. Zhang, B. H. Li, D. X. Zhao, X. W. Fan, and Z. K. Tang, Appl. Phys. Lett. 88, 031911 (2006). 9 H. Ohta, K. Kawamura, M. Orita, M. Hirano, N. Sarukura, and H. Hosono, Appl. Phys. Lett. 77, 475 (2000). 10. Y. R. Ryu, T. S. Lee, J. H. Leem, and H. W. White, Appl. Phys. Lett. 83, 4032 (2003). 11. X. -L. Guo, J. H. Choi, H. Tabata, and T. Kawai, Jpn. J. Appl. Phys., Part 2 40, L177 (2001). 12. Y. I. Alivov, E. V. Kalinina, A. E. Cherenkov, D. C. Look, B. M. Ataev, A. K Omaev, M. V. Chukichev, and D. M. Bagnall, Appl. Phys. Lett. 83, 4719 (2003). 13. T. Minami, H. Tanaka, T. Shimakawa, and T. Miyata, Proc. SPIE 5274, 399 (2004). 14. J. Tate, M. K. Jayaraj, A. D. Draeseke, T. Ulbrich, A. W. Sleight, K. A. Vanaja, R. Nagarajan, J F. Wager, and R. L. Hoffman, Thin Solid Film s 411, 119 (2002). 15. R. Nagarajan, N. Duan, M. K. Jayaraj, J. Li, K. A. Vanaja, A. Yokochi, A. Draeseke, J. Tate, and A. W. Sleight, Int. J. Inorg. Mater. 3 265 (2001). 16. R. Nagarajan, A. Draeseke, A. W. Sleight, and J. Tate, J. Appl. Phys. 89, 8022 (2001). 17. H. Hosono, J. of Non-Cryst. Solids 352, 851 (2006).

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146 BIOGRAPHICAL SKETCH Wantae Lim was born in Gyungju, South Korea in 1976. After graduating high school in 1995, he enrolled at Inje University where he earned a Bachelor of Science in E lectronic E ngineering in February 2002. During his undergraduate studies, he had the opportunity to conduct undergraduate research in the semic onductor field. He then received his Master of Science in n ano e ngineering from the same university in 2005. In 2005, Wantae enrolled in T he D epartment of Materials Science and Engineering at the University of Florida and joined Prof. Stephen J. Pearton s group. He continued his studies in the doctorate program under Prof. Pearton. His research focus concerned semiconductor processing for sensor and LEDs and transparent thin film transistors for flexible display. He received his Ph.D. from the University of Florida in the spring of 2009 and has authored more than 40 technical papers in international journal and over 10 conference papers.