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Record for a UF thesis. Title & abstract won't display until thesis is accessible after 2011-08-31.

Permanent Link: http://ufdc.ufl.edu/UFE0024222/00001

Material Information

Title: Record for a UF thesis. Title & abstract won't display until thesis is accessible after 2011-08-31.
Physical Description: Book
Language: english
Creator: Wu, Hsin-Ta
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Statement of Responsibility: by Hsin-Ta Wu.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: O, Kenneth K.
Electronic Access: INACCESSIBLE UNTIL 2011-08-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0024222:00001

Permanent Link: http://ufdc.ufl.edu/UFE0024222/00001

Material Information

Title: Record for a UF thesis. Title & abstract won't display until thesis is accessible after 2011-08-31.
Physical Description: Book
Language: english
Creator: Wu, Hsin-Ta
Publisher: University of Florida
Place of Publication: Gainesville, Fla.
Publication Date: 2009

Subjects

Subjects / Keywords: Electrical and Computer Engineering -- Dissertations, Academic -- UF
Genre: Electrical and Computer Engineering thesis, Ph.D.
bibliography   ( marcgt )
theses   ( marcgt )
government publication (state, provincial, terriorial, dependent)   ( marcgt )
born-digital   ( sobekcm )
Electronic Thesis or Dissertation

Notes

Statement of Responsibility: by Hsin-Ta Wu.
Thesis: Thesis (Ph.D.)--University of Florida, 2009.
Local: Adviser: O, Kenneth K.
Electronic Access: INACCESSIBLE UNTIL 2011-08-31

Record Information

Source Institution: UFRGP
Rights Management: Applicable rights reserved.
Classification: lcc - LD1780 2009
System ID: UFE0024222:00001


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1 TRANSMITTER FOR WIRELESS IN TER-CHIP DATA COMMUNICATIONS By HSIN-TA WU A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLOR IDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2009

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2 2009 Hsin-Ta Wu

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3 To my parents and my sister

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4 ACKNOWLEDGMENTS I would like to begin by thanking m y advisor, Professor Kenneth K. O, whose constant encouragement and patient guidanc e provided a clear path for my research. I would also like to thank Dr. Jenshan Lin, Dr. William Eisenstadt, a nd Dr. Oscar Crisalle for helpful suggestions and their time commitment in serving on my committee. Much appreciation goes to Defense Advan ced Research Projects Agency (DARPA), National Science Foundation (NSF) and TOYOTA Motor Corporation for funding this work. Special thanks go to MOSIS for chip fabrication and Eric Schwartz at Agilent Technologies for debugging the measurement equipments. I have been quite fortunate to have worked with my colleagues in the Node and Toyota projects, Jau-Jr Lin, Swaminathan Sankaran, Ch anghua Cao, Yu Su, Yanping Ding, Kyujin Oh, Wuttichai Lerdsitsomboon, and Ruonan Han, whose helpful discussions, recommendations and friendship have speeded up my rese arch. Especially, I learned a lot from Jau-Jr Lin when we did the antenna measurements together for 2 years. Also, I would like to thank my former and current colleagues at University of Florida for their helpful advice and discussions, Chikuang Yu, Xiaoling Guo, Haifeng Xu, Eunyoung Seok, Se onho Hwang, Dongha Shim, Chuying Mao, Tie Sun, Shashank Nallani Kiron, and Ning Zhang. I am most pleased to acknowledge the love a nd encouragement of my parents, my sister, my uncle and aunt, to whom I dedicate this work.

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5 TABLE OF CONTENTS page ACKNOWLEDGMENTS...............................................................................................................4 LIST OF TABLES................................................................................................................. ..........7 LIST OF FIGURES.........................................................................................................................8 ABSTRACT...................................................................................................................................13 CHAP TER 1 INTRODUCTION..................................................................................................................15 1.1 An Overview of a H ybrid Control Board System .......................................................... 15 1.1.1 Challenge to Replace Photo-Couplers.................................................................. 15 1.1.2 Potential Solutions................................................................................................16 1.2 An Overview of Bond Wire Antennas............................................................................ 17 1.3 Organization of the Dissertation.....................................................................................18 2 ELECTRONIC ISOLATOR DESIGN................................................................................... 21 2.1 Introduction............................................................................................................. ........21 2.2 Transformer Design....................................................................................................... .21 2.3 Circular Triple-Well Design........................................................................................... 23 2.4 Circuit Architecture and Measurement Results.............................................................. 25 2.5 Summary and Discussions..............................................................................................29 3 CHANNEL CHARACTERISTICS........................................................................................ 31 3.1 Introduction............................................................................................................. ........31 3.2 Review of On-Chip Dipole Antennas............................................................................. 32 3.3 PCB Environment and Measurement Setup................................................................... 34 3.4 Measurement Results and Discussions...........................................................................37 3.5 Summary.........................................................................................................................42 4 CDMA TX CHAIN DESIGN................................................................................................. 43 4.1 Introduction............................................................................................................. ........43 4.2 Sub-Blocks of Transmitter Chain................................................................................... 46 4.2.1 Power Amplifier................................................................................................... 46 4.2.2 Duplexer...............................................................................................................59 4.2.3 Mixer....................................................................................................................59 4.2.4 Divider Chain....................................................................................................... 62 4.3 Simulation Results: Multi-Level Signal at PA Output ................................................... 64 4.4 Measurement Results...................................................................................................... 67

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6 4.4.1 Duplexer...............................................................................................................67 4.4.2 24-GHz Phase-Locked Loop (PLL).....................................................................69 4.4.3 4-mm On-Chip Dipole Antenna........................................................................... 72 4.4.4 Multi-Level Power Amplifier............................................................................... 72 4.4.5 CDMA Transmitter Chain.................................................................................... 77 4.5 Summary.........................................................................................................................88 5 BOND WIRE ANTENNA DESIGN...................................................................................... 90 5.1 Introduction............................................................................................................. ........90 5.2 Measurement Setup, Test chips, and Test Boards.......................................................... 93 5.3 Measurement Results and Discussions...........................................................................98 5.4 Summary.......................................................................................................................112 6 SUMMARY AND Future work...........................................................................................113 6.1 Summary.......................................................................................................................113 6.2 Suggested Future Work................................................................................................ 114 APPENDIX A..............................................................................................................................116 APPENDIX B..............................................................................................................................117 LIST OF REFERENCES.............................................................................................................122 BIOGRAPHICAL SKETCH.......................................................................................................129

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7 LIST OF TABLES Table page 1-1 Link margin analyses for CDMA link...............................................................................17 4-1 Frequency plan for each motor and dead-t im e controller (frequency band unit: GHz)..... 46 4-2 Comparisons of power amp lifiers operating near 20 GHz ................................................ 52 4-3 Truth table of coding and the ratios between levels at TX side and after RX detection ... 56 4-4 Specification of the on-chip duplexer................................................................................60 4-5 Mismatch simulation results.............................................................................................. 64 4-6 Simulation results of ratio between leve l N and level 1, where N equals to 2, 3, 4, 5 and 6. ..................................................................................................................................65 4-7 Measurement results summary of static case..................................................................... 75 4-8 Bidirectional 3-bit bus se ttings for different tests. .............................................................78 4-9 TX static measurement results at the duplexer output (cable a nd external balun loss are 4 dB). ..................................................................................................................... .......83 4-10 Power consumption of TX blocks...................................................................................... 88 5-1 Link margin analysis using Frequenc y Division Multip le Access (FDMA) scheme and direct conversion tr ansceiver architecture................................................................. 108

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8 LIST OF FIGURES Figure page 1-1 Toyota hybrid engine controller board (25 15 6 cm3)...................................................16 1-2 Wireless links can be used to form a bus in which multiple devices can communicate at the sam e time. Use of this can also l ead to smaller package area, fewer I/O pins and lower cost....................................................................................................................18 2-1 Double-layer inductors are used for the transformer design.............................................. 22 2-2 Triple well structure Cross-sectional view. ..................................................................... 24 2-3 Circular triple well structure P lane view......................................................................... 24 2-4 Theoretical plot of breakdown voltage.............................................................................. 25 2-5 Circuit schematic.......................................................................................................... .....26 2-6 Simulated waveforms of 160 MHz at differe nt nodes of the circ uit. (Node nam es are shown in Figure 2-5) The floati ng ground potential equals to 300 V................................26 2-7 Measurem ent setup .......................................................................................................... ..27 2-8 Ground potential difference between 2 bu ildings or 2 vendors, which could be happened for RS-232 or IEEE 1394 co mmunication schemes.......................................... 28 2-9 Die micrograph of the electronic isolator.......................................................................... 29 2-10 Output waveform of 160 MHz, fl oating ground potential equals to 60 V ......................... 29 3-1 On-chip 3-mm long zigzag dipole antennas are fabricated using alum inum on a 20-cm and 670m thick silicon substrate with 3m thick oxide layer and 1.5m aluminum thickness and 30m aluminum width.............................................................. 32 3-2 Antenna pair gain versus distance in the lobby at 24 GHz.. .............................................. 33 3-3 3-mm zigzag antenna radiat ion pattern at 24 GHz [40] .....................................................33 3-4 Numerous electronic com ponents on a PCB such as transform ers, capacitors, and heat sinks, are 1.2 to 2.5 cm high....................................................................................... 34 3-5 Measurement setup with a vector network analyzer (VNA) for m easuring the impulse response of communication channels................................................................... 36 3-6 Measurement points chosen on the PCB........................................................................... 36 3-7 Large scale fading channel measurement results............................................................... 37

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9 3-8 Time delay spread measurement results for probes landing on a thru calibration structure, P CB without and with a meta l cover at 15-cm and 10-cm separation............... 39 4-1 Board showing dead-time and motors (D1, D2: dead-tim e controller, M1-M12: motor).................................................................................................................................44 4-2 Downlink and uplink modulation schemes, and frequency allocation.............................. 45 4-3 Block diagram for the transcei ver in a dead-tim e controller............................................. 47 4-4 Block diagram for the digi tal coder of TX chain [45] ....................................................... 47 4-5 Schematic of the common source power amplifier............................................................ 48 4-6 Transistor drain curre nt and conduction angle, for class A and B power am plifiers..... 50 4-7 Schematic of a class E power amplifier............................................................................. 51 4-8 Kahn envelope elimination and restorat ion schem e with using a dc-dc converter............ 53 4-9 Modulate transistor gate bias............................................................................................. 54 4-10 PA using attenuators for output power c ontrol and CDMA TX chain block diagram ...... 55 4-11 Schematic of a single-ended five-s tage class-E CMOS power am plifier..........................55 4-12 Small signal model of the last PA stage (comm on source amplifier)................................ 57 4-13 Lumped circuit models with the attenuator switched ON and OFF.................................. 58 4-14 On-chip duplexer using two band stop filters [40]............................................................60 4-15 Schematic of the single-ended on-chip duplexer [40]....................................................... 60 4-16 Die micrograph of the differential on-c hip duplexer fabricated in the UMC 130-nm technology..................................................................................................................... .....61 4-17. Schematic of double balanced Gilbert cell up-c onversion m ixer........................................ 61 4-18. Schematic of multiplyby-2 and phase-shift blocks ............................................................63 4-19 Simulation results of multi-level signals at differential PA output and TX chain sim ulation up to 180 ns...................................................................................................... 66 4-20 Plots of insertion loss an d return loss between antenna (ANT) port and PA port. (TX band: 15.6-18 GHz) ...........................................................................................................67 4-21 Plots of insertion loss an d return loss between antenna (ANT) port and LNA port. (RX band: 24.2-27 GHz)....................................................................................................68

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10 4-22. Measured insertion loss between PA port and LNA por t.................................................... 69 4-23 Micrograph of the integer-N PLL...................................................................................... 70 4-24 Integer-N PLL block diagram............................................................................................ 70 4-25 Measured PLL output spectrum (Span=1 MHz, RBW =3 kHz, VBW=100 Hz)............... 71 4-26 The PLL phase noise plot measured using an Agilent E4448A spectrum analyzer.......... 71 4-27 |S11| and input impedance for 4-mm on-chip dipole antenna............................................. 73 4-28 PA measurement setup for fr equency dom ain and time domain....................................... 74 4-29 Output power vs. input power at VDD=1.5 V for the driver stages and 1.2-V supply for the PA stage............................................................................................................... ...74 4-30 Static and dynamic time dom ain measurement results...................................................... 76 4-31 Die micrograph of the differen tial m ulti-level power amplifier........................................ 77 4-32 Bidirectional 3-bit bus design be tween the adder and the decoder. ................................... 78 4-33 Micrograph of the CDMA TX chain and the PCB............................................................ 79 4-34 CDMA TX chain block diagram for the real measurement............................................... 79 4-35 Output spectrum at duplexer output without m ulti-level amplitude modulation............... 81 4-36 The CDMA TRX simulation block diagram and the spectrum at the TX output, and the base band output of the CDMA receiver for two cases............................................... 82 4-37 Time domain and frequency domain measur e ments when the digital coder inputs are 111111, which corresponds to the dynamic output, 62333322......................................... 85 4-38 Time domain and frequency domain measur e ments when the digital coder inputs are 000001, which corresponds to the dynamic output, 13424253......................................... 86 4-39 Time domain and frequency domain measur e ments when the digital coder inputs are 111000, which corresponds to the dynamic output, 3344043........................................... 87 5-1 Multi-Chip Module package cross-sectional view............................................................ 91 5-2 On-chip dipole antenna vs. slot ante nna. The E-fields are both on x-y plane ................... 92 5-3 Frequency division multiple access (FDM A) is used to rep lace M I/Os by a transmitter or a receiver with one antenna to lower the I/O pin count.............................. 92

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11 5-4 Gold bond wire co-designs with an onchip bond pad and a floating bond pad on the PCB and the photograph showing the side vi ew of the silicon chip and a gold bond wire ....................................................................................................................................94 5-5 Antenna measurement setup.............................................................................................. 95 5-6 Side view of bond wire antenna and phot ographs of test chip and PCB and bond pad design .................................................................................................................................95 5-7 Antenna PCB with and without a cover.............................................................................96 5-8 Test PCB for antenna pattern measurem ent and the mobile setup for pattern measurement.................................................................................................................... ..98 5-9 Test PCB and chips for bond wire antenna investigation of the effects of adjacen t bond wires on antenna performance.................................................................................. 99 5-10 |S11| of bond wire antennas...............................................................................................100 5-11 Simulated |S11| of bond wire antennas with +/150m length variation (HFSS) in log scale and in the smith chart........................................................................................ 102 5-12 |S11| of the 870m bond wire antenna: HFSS simulated |S11| vs. measurements. |S11| of bond wire antennas with +/50m length variation (HFSS simulation results)........ 103 5-13 Antenna pair gain at 55 GHz, Ga vs. sepa ration (up to 10 cm ) plots of with a metal cover, without a metal cover, and calc ulated path loss from Friis formula..................... 104 5-14 Measured |S11| of bond wire antennas for the case s with and without an aluminum cover. (cover height: 2 mm from PCB)........................................................................... 105 5-15 HFSS 3-D pattern simulation results for the case of bond wire length = 870 m at 55 GHz (without a metal cover)............................................................................................ 106 5-16 Radiation pattern (normalized) of a bond wire antenna m easured using the PCB in Figure 5-9..................................................................................................................... ....106 5-17 HFSS simulation structure for a bond wire antenna coupling study. Circuit m odel for the bond wire antenna coupling. HFSS vs. circuit simulation results for the 300m separation case. HFSS simulations of isolation between bond wire antennas at varying separations..........................................................................................................108 5-18 Interference measurement results (cover height 2 mm from PCB)................................. 111 6-1 CDMA TX chain block diagram...................................................................................... 114 6-2 Suggested measurement setup fo r the CDMA link dem onstration.................................. 115

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12 A-1 Ring type calibration structures on the CS-8 calibration substrate .................................. 116 B-1 Die micrograph showing internal testing nodes............................................................... 117 B-2 TX chain testing PCB showing possible landing directions ............................................ 118 B-3 Double row bonding design with the prope r pad arrangem ent on the chip side.............. 119 B-4 Double row bonding design with a proper finger length on the PCB side ......................120

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13 Abstract of Dissertation Pres ented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy TRANSMITTER FOR WIRELESS IN TER-CHIP DATA COMMUNICATIONS By Hsin-Ta Wu August 2009 Chair: Kenneth K. O Major: Electrical and Computer Engineering The dramatic fluctuation of gasoline price is a major concern for all. Hybrid electric vehicles with ~ 2 times higher fuel efficiency have drawn lots of attention in the last few years. In order to replace costly photo-couplers used in hybrid engine controller boards, silicon based solutions are utilized to sugge st the feasibility to lower cost and increase data rate. This dissertation presents the design of an electronic isolator using inductive coupling fabricated in the UMC 130-nm mixed mode CMOS process. It can achie ve 70-V DC isolation and around 160-MHz data transmission rate while drawing ~ 22 mA. It only occupies 0.52 mm2, which is 3 times smaller, compared to the is olators using a capaciti ve coupling method. The electronic isolator is designed to provide sufficient isolation of high and low voltages coexisting in the same board. It can be used in RS-232 and IEEE 1394 applications. The channel characteristics including antenna pair gain and delay spreads at 24-GHz in a printed circuit board for cont rolling hybrid engines with a nd without a metal cover are characterized using a 3-mm on-chip dipole antenna pair. At a 15-cm separation, the antenna pair gain can be improved by ~10 dB with a metal cover ~ 3.5 cm above the PCB and the maximum excess delay can be reduced to ~ 1.1 ns from ~ 16.5 ns, which is acceptable for recovery of clock

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14 and data for a 400 Mchip/sec system. It has been verified that on-chi p dipole antennas can be used for wireless communication in the hybrid engine controller board. Wireless interconnection using tw o separate wireless transcei vers can operate with two different ground potentials that have large difference. A fully-integrated CDMA transmitter with an on-chip dipole antenna operating at 16.8 GHz fabricated in the UMC 130-nm CMOS process is demonstrated. It supports 7 signal levels with a 16.8-GHz carrier and 40 0-Mbps data rate. It includes a PLL, divider chains, a double balanc ed Gilbert cell up-conversion mixer, a power amplifier (PA), attenuators, a di gital coder, a duplex er, and a 4-mm on-chip dipole antenna. The PA used in the transmitter chain can achie ve 10-dBm saturated output power and ~ 22-% maximum PAE. Most of the rise and fall times are around 200 ps. The worst case is 800 ps for the level 0 to level 2 transition. The CDMA transmitter occupies ~ 5.2 mm2 and consumes 198 mW. A bus interconnected with wireless links on a pr inted circuit board in which multiple sets of devices/chips can simultane ously communicate and control signals can be broadcasted to multiple devices has been presented in the diss ertation. A gold bond wire with ~ 1-mil diameter is co-optimized with a bond pad to resonate at ~ 60 GHz. With a metal cover representing an enclosure for an electronic system (2-mm from a pr inted circuit board), the antenna pair gain at 10-cm separation is ~ -53 dB including the effects of two nearby bond wires located 300 m away. This is sufficient for building an inter-chi p 1-Gbps radio link with bit error rate of 10-12. The bond wire antennas should also be useful for general purpos e over the air communication in the 60-GHz unlicensed band.

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15 CHAPTER 1 INTRODUCTION 1.1 An Overview of a Hybrid Control Board System The dramatic fluctuation of gasoline price is a major concern for all. Hybrid electric vehicles (HEVs) with ~ 2X higher fuel efficiency have drawn lots of attention in the last few years [1]-[4]. Use of HEVs also reduces carbon dioxide emission, which is good for environment. However, hybrid vehicles are usually more expensive than regular vehicles, which slows their adoption. Lowering the ma nufacture cost is the key to cut down the selling price of HEVs. The hybrid engine controlle r board (also called as inverter board) is a part of HEVs. The main goal of this research is to find a way to replace photo-couplers used in the board by using complementary metal oxide semiconductor (CMO S) technology, which will alleviate the cost problem, and increase data transmission rate. 1.1.1 Challenge to Replace Photo-Couplers A hybrid engine controller board shown in Figure 1-1 is 25 15 6 cm3. High voltage (>300 volt (V)) motor driver section and low voltage (3-12 V) control section coexist in the same board. Presently, high-low voltage interface is isolated by photo-couplers. Usually, the data transmission rate for photo-couplers is 1 Mbps or 10 Mbps. It is lower than the speed of on-chip isolators, which can achieve data transmission ra te of 100 Mbps or even higher. A photo-coupler with cost of ~ $1 or higher is significantly costly compared with silicon based solutions. However, photo-couplers usually can handle high isolation vo ltage up to few thousand volts, which is challenging to achieve using pure CMOS approaches. Nevertheless, the higher data rate, higher integration level, and lowe r cost are attractive. Approaches for handling the high isolation voltage is need for CMOS implementation.

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16 Figure 1-1. Toyota hybrid engi ne controller board (25 15 6 cm3). 1.1.2 Potential Solutions The m ain concern for replacing photo-couplers using mainstream CMOS technology is the breakdown voltage. A potential solution is to increase the brea kdown voltage. For this particular application, a CMOS isolator must be able to withstand 300-V ground potential difference between high and low vol tage sections in the board. Us ing CMOS isolators can reduce cost by a factor of 4 times or even higher. The second potential solution is use of wir eless interconnects. An on-chip antenna is the key to implement this. On-chip antennas have been extensively studied [5]-[7] in both indoor and outdoor environment and are integrated with other circuit blocks to form receiver and transmitter chains for wireless communications above 20 GHz [8] [9]. Two separate wireless

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17 Table 1-1. Link margin analyses for CDMA link. CDMA Link Transmission range 15 cm TX power/Channel (Total power ~ 10 dBm) 2 dBm Propagation Loss @ 16.8 GHz ( /4 R) 2 41 dB Antenna Gain (0.25 = 3.2 mm) -7 dB Received power -53 dBm Thermal Noise [kT (oK)] -173.8 dBm/Hz Bandwidth (50 MHz) 77 dB Eb/No for BER of 1x10-13 for ASK 14.5 dB RX noise figure 8 dB Sensitivity -74.3 dBm Link margin 21.3 dB transceiver integrated circuits can operate with two different ground potentials to handle the large voltage difference. Using wireless interconn ects can also increase data transmission rate, lead to smaller chip area, and eliminate wiring tr aces on the board. Of course, they can also cost less. The inverter board is used with a metallic enclosure on the top. The wireless channel on the PC board will be a multi-path rich environment, which is expected to be difficult for wireless communications. The performance of on-chip di pole antennas should be re-evaluated in the inverter board in a metallic enclosure to dete rmine the feasibility of the approach. Table 1-1 shows the link margin analysis, typically used for conventional channels. This should be acceptable, however, it does not account for the multip le path effects. The multi-path effects are discussed in Chapter 3. 1.2 An Overview of Bond Wire Antennas It has been dem onstrated that CMOS technolog y is suitable for a wide range of wireless applications, such as wireless clock distribution [10]-[18], wireless interconnects [19] [20], and inter and intra-chip communications [5], etc. However, as the operating frequency increases, package may have more significant impact on th e wireless transceiver pe rformance. When the operating frequency is increased to 60 GHz or highe r, bond wire lengths become comparable to

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18 that of wavelengths. This will make bond wire to be an efficient radiator and could be used for inter-chip data communication. The wireless interconnects could be used to relieve the packaging cost problem of integrated circuits with a large number of I/ O pins. Referring to the 2003 SIAs International Technology Roadmap for Semiconduc tor (ITRS), at 35-nm technology generation or in year 2012, the number of pins in packaged chip will be on the order of 1000-5000. Of these, ~35%, or ~350 to 1750 pins will be I/O pi ns. Use of wireless interconn ects by reducing the number of traces in printed circuit boards (PCBs) can simplify the PCB construction, and reduce size and cost [5], shown in Figure 1-2. Figure 1-2. Wireless links can be used to form a bus in which multiple devices can communicate at the same time. Use of this can also lead to smaller package area, fewer I/O pins and lower cost. 1.3 Organization of the Dissertation This research focuses on replacing photo-coup lers in the hybrid engi ne controller board using mainstream CMOS technology. The solutions should provide the advantages of lower cost, higher data transmission rate, easy to use, smalle r area consumption, and hi gher integration level. The electronic isolator design is discussed in Chapter 2. On-chip transformers design, circular triple-well technique, an d circuit architecture are presented. Double-layer inductors are used to

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19 achieve higher inductance per unit area to impl ement transformers in limited space. On-chip isolators using mixed-mode 130nm CMOS technology that can ach ieve higher data transmission rate of ~ 160 MHz with 70-V is olation voltage is described. Chapter 3 describes the channel characteristic s in the hybrid engine controller board. A 3mm on-chip dipole antenna pair is used to charact erize antenna pair power gains and time delay spreads. These are used to model the multiple path effects at 24 GHz. The wave propagation behavior in the board has been investigated for two cases, with and without a metal cover. The maximum excess delay is ~ 1.1 ns at 15-cm separati on for the case with a metal cover, which is acceptable for recovery of clock and data for a 400-Mchip/sec system, which suggests that wireless communication using on-chip dipole an tennas in the inverter board is feasible. Chapter 4 discusses the code division mu ltiple access (CDMA) transmitter chain design. It includes a mixer, a power amp lifier (PA), a digital coder, a Phase-Locked Loop (PLL), divider chains, a duplexer, attenuators, and a 4-mm on-chip dipole antenna. The multi-level PA capable of supporting 7 levels with 400-Mbps wireless da ta transmission rate is presented. The singleended PA fabricated in the 130nm CMOS foundry process can ach ieve 10-dBm saturated output power with ~ 22-% maximum PAE while c onsuming 45.75 mW. The transmitter chain is characterized in frequency and time domains se parately. The measurement results demonstrate that it is feasible to build the radio link to transmit CDMA signals using an amplitude shift keying (ASK) modulation scheme. Chapter 5 presents bond wire antennas operating at ~ 60 GHz. A gold bond wire with ~ 1-mil diameter is co-optimized with a bond pad to resonate at ~ 60 GHz. With a metal cover representing an enclosure for an electronic sy stem (2-mm from a printed circuit board), the antenna pair gain at 10-cm separation is ~ -53 dB including the effects of two nearby bond wires

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20 located 300 m away. This is sufficient for building an inter-chip 1-Gbps radio link with bit error rate (BER) of 10-12. The bond wire antennas should also be useful for general purpose over the air communication in the 60-GHz unlicensed band Finally, the summary and suggested future work is described in Chapter 6.

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21 CHAPTER 2 ELECTRONIC ISOLATOR DESIGN 2.1 Introduction In order to develop an alternative to more co stly photo couplers, an el ectronic isolator that can im plement in CMOS has been investigat ed. Photo-couplers are conventional components used for data transmission and isolation of high-low voltages coexisting in the same board. Electronic isolators should be ab le to support a higher data transmission rate and help to reduce cost by a factor of 4 times or even higher. The grounds can be isolated by coupling signals. There are two ways. One is capacitive coupling and th e other is inductive coupling. Several papers using capacitive coupling method in silicon on insulator (SOI) technology are reported in [21][23]. It has been shown that the isolator can achieve 2.3kV ac isol ation and 100-MHz signal transmission in an area of 1.5 mm2 [23]. This approach however, requ ires a larger space than the isolators using an inductive coupling method. Inductive coupl ed interconnects have been proposed for inter-chip data communication as we ll as that in 3D system [24]. This chapter presents the design of an electr onic isolator using inductive co upling fabricated in the UMC 130nm mixed mode CMOS process for lower cost. Th e isolator can achieve 70-V DC isolation and around 160-MHz data transmission rate while drawing ~ 22 mA. It only occupies 0.52 mm2, which is 3X smaller, compared to the isolators using capacitive coupling method. 2.2 Transformer Design The elec tronic isolator design includes a transformer, a transmitter and a receiver. The 1:1 transformer is designed to use double-layer i nductors. By using double-layer inductors, higher inductance per unit area can be achieved [25]. The lower inductor needs to be connected with upper inductor in a way such that the currents pr oduced by both inductors flowing in the same direction [26], shown in Figur e 2-1. In transformer design, th e magnetic coupling coefficient

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22 depends strongly on the separati on distance between primary and secondary inductors. A closer separation increases the coupling coefficient. M7 (metal 7 layer) and M8 are designed to be used in series to form the primary inductor and M56 (shunt M5 and M6) and M34 (shunt M3 and M4) are used in series to form the secondary inducto r. Lower metal layers us ually have higher sheet resistance due to their thinner thickness. Th erefore, metal conduction loss can be reduced by shunting 2 metal layers together, which is the ot her key to improve the transformer performance. The vertical separation be tween M6 and M7 is 0.615 m, which is fixed by the chosen technology. Besides the high couplin g coefficient for the transformer, a high breakdown junction voltage is needed for high voltage isolation. Th e isolation voltage between the windings of the transformer is determined by the dielectric, SiO2, thickness between them. Theoretically, a 1m thick SiO2 layer can withstand 1000 V. 0.615m SiO2 thickness should be sufficient to provide 300-V DC isolation. Figure 2-1. Double-layer inductors ar e used for the transformer design. Metal 8 Metal 7 Metal 3,4 Metal 5,6 8 turns for every layer, 2m spacing, 8m metal width

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23 2.3 Circular Triple-Well Design In order to support floating grounds, which can be around 300 V, it is im portant to have junctions with breakdown voltage greater than 3 00 V in 130-nm CMOS process. Therefore, the triple well structure, shown in Figure 2-2, has been used for this particular application. There is a T-well region inside the n-well region. Therefore, NMOS transistor s can be placed in the T-well instead of in a regular p-well in p-type substrat e. For this application, high breakdown voltage is required for the junction between deep n-well an d substrate. On the other hand, the junction between T-well and deep n-well only has to ha ndle 1.2-V difference, so there is no serious breakdown voltage requirement for this junction. If the junction between the deep n-well and substrate is smoother, the breakdown voltage wi ll be higher [27]-[29]. He nce, a circular well structure is used to improve the junction br eakdown voltage, shown in Figure 2-3. We also separate p-well region far away from deep n-well region (40m separation), shown in Figure 22 to prevent the breakdown between deep n-well and p-well occurring before the deep n-well to substrate breakdown. At the same time, p-well bl ock layer (PWBLK) is used to form an undoped substrate region, shown in Figure 23, for increasing the breakdown voltage. According to Eq. (2-1) [30], 75.0 16 5.1101.1 60 B g BN E V (2-1) where VB is the breakdown voltage, NB is the impurity density, and Eg is the silicon energy gap, which equals to 1.12 eV. It is possible to achieve breakdown voltage exceeding 300 V by having an un-doped substrate region with 20-cm resistivity, shown in Figure 2-4. In addition to having triple well and the structure with a 20-cm substrate region, another structure with a polysilicon layer for potentially gatin g the surface is fabricated to investigate the possibility for

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24 further improving the breakdown voltage. The idea is to adjust the field strength underneath polysilicon gate area to possibl y increase the breakdown voltage. Figure 2-2. Triple well structure Cross-sectional view. Figure 2-3. Circular triple well structure Plane view. T-Well PWBLK N-Well Diff9 m 40 m 2 m NMOS PMOS Poly area 40 m 40 m 20-cm substrate Deep N-Well ( 20-cm ~ 1015 cm-3 ) p-well contact p-well contact n+ contact breakdown T-Well

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25 Figure 2-4. Theoretical plot of breakdown voltage. 2.4 Circuit Architectu re and Measurement Results Figure 2-5 shows the circuits built in the triple well structure. It is possible to have 0-V ground potential at the transmitter side and have 300-V ground potential at th e receiver side, or vice versa. Therefore, circular triple well technique is applied for both transmitter and receiver sides. All NMOS transistors are placed in the T-well region and all PMOS transistors are placed in the n-well region. Metal connections are us ed to connect NMOS and PMOS transistors. Sinusoidal signal is applied at the transmitter inpu t and passes through an inverter chain to form a square wave before applied to the transformer. Two inverter chains with 3 and 4 stages are used to generate 180-degree phase difference at the transformer input. The AC signal would be coupled inductively from the primary to the se condary. The coupled signal passes through a DC bias circuitry to be biased between 0 to 1.2 V or 300 to 301.2 V depending on the floating ground potential, and amplified by a sense amplifier. Finally, an inverter chain and a latch hold the signal from transformer to recover the sq uare waveform. Figure 2-6 shows the simulated waveforms at different nodes of the circuits. VB versus Impurity Density Impurity Density (cm-3) 346.6 VB (V)

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26 Figure 2-5. Circuit schematic. Figure 2-6. Simulated waveforms of 160 MHz at different nodes of the circuit. (Node names are shown in Figure 2-5) The floati ng ground potential equals to 300 V. 0 1 2 3 4 5 6 7 8 0 1 0 1 2 3 4 5 6 7 8 300 301 0 1 2 3 4 5 6 7 8 Time (ns) 300 301 in-neg in-pos ind-pos ind-neg out rx-latch-out(V) (V) (V) Inverter chain Input DC bias circuitry Sense Amplifier Inverter chain + Latch Oscilloscope load 1:1 transformer Applying triple well technique Applying triple well technique in-pos in-neg ind-neg ind-pos rx-latch-out out

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27 Figure 2-7. Measurement setup. Due to the floating ground potential, a special differential probe is used to protect the equipment (Tektronix TDS 430A). For example, if the 300-V ground potential is applied at the receiver (RX) side, the high volta ge differential probe is placed at the RX output to protect an oscilloscope. The measurement setup is shown in Figure 2-7. The measurements show the isolator has ar ound 70-V DC isolation, which is lower than the target. The reason for lower breakdown voltage performance is probably due to the small vertical junction depth. A lthough large separations of 40 m and 52 m are maintained horizontally between p-well region and deep nwell region, and n+ well contact and p-well region, the breakdown can still occur at the bottom side of deep n-well (with depth of ~ a few m), as shown in Figure 2-2. The polysilicon ga ting was found to be not helpful for increasing breakdown, which is consistent with the breakdo wn limited by the small vertical junction depth. The electronic isolator fabricated in UMC 130-nm mixed mode CMOS process is demonstrated to be not suitable for the hybrid en gine controller board ap plication. However, 70V DC isolation is still exciting for bulk CMOS circuits. This chapter only presents circuits operating for 1.2-V voltage diffe rence between supply voltage (VDD) and reference ground potential, which could be 0 V or up to 70 V. If a high voltage MOSFET process is used, data level of higher voltage, like 3 V or 5 V, can be also applied. Incidentally, the 70-V DC isolation 301.2 V High Voltage Differential Probes (Tektronix P5205) TX RX Chip 301.2 V 1.2 V 300 V 0 V

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28 Figure 2-8. Ground potential difference between 2 buildings or 2 vendors, which could be happened for RS-232 or IEEE 1394 communication schemes. is sufficient for RS-232 and IEEE 1394 applications. RS-232 and IEEE 1394 are used for communications between 2 systems supplied by different vendors, located in two widely separated buildings, which may possibly have different ground potentials, shown in Figure 2-8 [31]. With the unknown ground potenti al difference, it is not only likely to damage equipment, but also make communications unreliable. Therefore, the on-chip isolators fabricated in 130-nm CMOS process can be utili zed to provide DC isolation up to 70 V. The die photo is shown in Figure 2-9, which only occupies 0.52 mm2 (1.15 mm x 451 m). Figure 2-10 shows the measurement results fo r circuits operating at 160-MHz frequency with 60-V floating ground potential. A high voltage different ial probe modeled as 4-M resistance in parallel with 7-pF capacitance is used at the circuit output to protect instruments from floating ground potential (Figure 2-7). Due to the large load of differential probe, the output waveform is not square. A larger driver should be added to drive the load. For actual use in a system, the load should be smaller and the squa re output waveform shoul d be preserved. The data rate of 160 MHz is also significantly higher than the us ual data rate of photo-couplers Data Cable ( RS-232 or IEEE 1394 ) Power Supply A Power Supply B Ground potential difference Building A Building B

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29 (usually 1 Mbps to 10 Mbps). For the 130-nm CM OS process, data rate higher than 200 MHz should be possible. Figure 2-9. Die micrograph of the electronic isolator. Figure 2-10. Output waveform of 160 MHz, floating ground potential equals to 60 V. 2.5 Summary and Discussions An electronic isolator fabricated in CMOS process with 70-V DC isolation and around 160-MHz data rate is presented. A transforme r using double-layer inducto rs was designed to -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.0E+005.0E-091.0E-081.5E-082.0E-082.5E-08 time(s)(V) 1.15 mm 451 m

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30 reduce area. A circular triple well design and the large separa tion between p-well region and deep n-well region were both us ed to increase breakdown voltage. Polysilicon gating of the surface was found to be not helpfu l for increasing breakdown voltage. Finally, a bias circuitry, a sense amplifier, an inverter chain, and a latc h were built to recover the signal. Although the isolators breakdown voltage is too low for use in the hybrid engine controller board, such isolation can be used in RS -232 and IEEE 1394 applications.

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31 CHAPTER 3 CHANNEL CHARACTERISTICS 3.1 Introduction As discussed in Chapter 2, the electronic is olators fabricated in 130-nm CMOS process only achieve 70-V DC isolation, which is not su itable for the hybrid en gine controller board. Therefore, the second solution, w ireless interconnects, mentioned in Chapter 1 is investigated. On-chip antennas are a key to realize such a system. On-chip dipol e antennas have been integrated in a 20-GHz down-converter [8] and a 24-GHz transmitter [9] as part of an effort to realize a true single chip radio which can en able radical reduction of communication system costs through simplification of de sign and manufacture. The wire less interconnects formed using single-chip radios will not only be lower cost but will also support much higher data rate potentially greater than 100s of Mbits/sec. Use of wireless interconnects will also eliminate the PCB area of metal traces for making connect ions to and from the photo-couplers. In order to determine the feasibility of the wireless communication scheme in the board, the channel characteristics must be understood in advance. Channel characteristics are widely studied [5]-[7], [20], [32]-[36]. Most of them focus on transmission in the free space. However, inside an electronic system, there have not been any reports except the work at 2-12 GHz for a vertically mounted chip antenna on a mother board of a computer [37]. This chapter presents the characteristics of signal transm ission at 24 GHz for waves from a horizontally polarized zigzag dipole antenna which is much easier to integrate. The measurements are made with and without a metal cover. The time delay spreads are measured to quantify the multiple path effects. The antenna pair gain can be improved by around 10 dB and the maximum excess delay spread can be reduced by around 15X when a metal cover is placed above the PCB.

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32 3.2 Review of On-Chip Dipole Antennas The study of antennas fabricated on semi-conducti ng substrate goes back to late 1980s. In 1986, an on-chip antenna integrated with a 95-GHz IMPATT diode oscillator on a highresistivity silicon substrat e was reported [38]. In 1988, an on-ch ip antenna integrated with a 43.4GHz IMPATT diode oscillator on a GaAs substrate was reported [39]. As the circuit operating frequency increases, inte gration of antennas is becoming mo re compelling to circumvent the packaging problem. Instead of using high-resistivity or GaAs substrate, it is preferable to use mainstream CMOS technology because of its lower cost and higher integrat ion level. However, lossy silicon substrates cause performance degrad ation. This and the methods to improve on-chip antenna efficiency have been both investigated in [40]. The on-chip dipol e antennas are designed to be 3-mm long and zigzag shape, which is shown to have higher gain [16]. It is fabricated with an aluminum layer on a 20 cm and 670m thick silicon substrate with 3m thick oxide layer and 1.5m aluminum thickness and 30m aluminum width, shown in Figure 3-1. At 24 GHz, the on-chip dipole antenna pair gain versus distance plots are shown in Figure 3-2 [40] and the antenna pattern is sh own in Figure 3-3 [40]. Figure 3-1. On-chip 3-mm long zigzag dipole antennas are fabricated using aluminum on a 20-cm and 670m thick silicon substrate with 3m thick oxide layer and 1.5m aluminum thickness and 30m aluminum width.

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33 Figure 3-2. Antenna pair gain versus dist ance in the lobby at 24 GHz 3-mm on-chip zigzag dipole antennas fabricated on a 20 cm substrate with a 3m oxide layer are used for these measurements at 50-cm height from the ground [40]. The substrate thickness is designed to be 50, 100, and 670 m. Figure 3-3. 3-mm zigzag antenna radiation pattern at 24 GHz [40]. By thinning the silic on substrate to 100 m, the antenna pair gain can be improved by 10 dB [40]. The antenna performance would be better by transmitting at the 90degree direction. For the wireless link in the hybrid engine controlle r board, the channel characteristics will be

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34 strongly influenced by the components on the PCB. It is expected to be very different from the propagation in the free space. Therefore, PCB envi ronment is described in detail in the next section. 3.3 PCB Environment and Measurement Setup There are lots of obstacles in the PCB (25 15 6 cm3). It, for example, includes transformers, capacitors, heat sinks, and socket connectors, as shown in Figure 3-4. Some capacitors and transformers are 2.5 cm high. Compared to the thin and small on-chip dipole antennas, those obstacles are relatively large. Th e transmitted signal will be scattered, attenuated, and multiple reflected while traveling through the obs tacles. This is expected to be a challenging environment for wireless communication. Figure 3-4. Numerous electr onic components on a PCB such as transformers, capacitors, and heat sinks, are 1.2 to 2.5 cm high. Th ese make the wireless communication on the PCB challenging. Transformer (1.2 cm high) Capacitor (2.5 cm high) Heat sink (2.5 cm high)

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35 The measurements were made without taking out any components of PCB. In [37], the antenna was placed vertically using a right angl e connector with a heat sink and a CPU fan removed, which alters the channel characterist ics. The on-chip dipole antenna measurements reported in this chapter, to emulate the eventual use scenario are made by either directly placing an antenna on the PCB surface or on the top surf ace of discrete IC components, which is ~ 2 mm above the PCB. From the free space measurement experience [40], on-chip dipole antennas close to ground have significantly degraded performan ce. However, this is necessary in this application. Large scale fading channel character istics and time delay spread measurement are both used to characterize th e channel characteristics. The antenna pair gain measurement setup is shown in Figure 3-5. Antenna pair gain, Ga [5], is defined as 2 2 22 2 11 2 214 11 R GG SS S Grt a (3-1) where is the wavelength in free space, R is th e distance between the antenna pair, and Gt and Gr are the transmitting and receiving antenna gains. It includes probe chucks, cable connections, a signal generator, off-chip baluns, SS probes, and a vector network analyzer (VNA) [34]. The measured channel frequency response is converted into time domain (time delay spread) waveforms using inverse discrete Fourie r transformation (IDFT) [41]. By using these time delay spread measurements, multi-path eff ects are quantified. The multi-path effects are expected to be particularly severe in the PCB. The measurement points on the PCB are shown in Figure 3-6. The points are chosen based on the fe asibility for landing the high frequency probes. The separations between a pair of sampling points range from 6.5 to 25 cm. The time delay spread measurements are made at ~ 10-cm and ~ 15-cm separations with and without a metal

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36 cover located ~ 3.5 cm on top of the PCB. The large scale fading channel characteristics are measured using the setup including a signa l generator and a spectrum analyzer [34]. Figure 3-5. Measurement setup with a vector network analyzer (VNA) for measuring the impulse response of communication channels. Figure 3-6. Measurement points chosen on the PCB.

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37 3.4 Measurement Results and Discussions Figure 3-7 shows Ga versus separation plot which repres ents the large scale fading channel characteristics measured using a setup with a signal generator and a spectrum analyzer. Without a metal cover, Ga can be as much as 20 dB below that fo r free space propagation. On the average, adding a metal cover leads to around 10-dB Ga improvement. If a transmitter is placed at the center of PCB, then the maximum required transmission range is around 15 cm to any point on this PCB. Table 1-1, shown in Chapter 1, summarizes the link margin analyses. The 24-GHz receiver sensitivity is around 74.3 dBm for 50 Mbits/sec Amplitude Shift Keying (ASK) modulated data at bit error rate (BER) of 10-13. The system will use spread spectrum with a chip rate of 400 Mchip/sec. Nois e figure of 8 dB is reasonable based on [8]. The Figure 3-7. Large scale fading channel measur ement results. (11-15 means TX is placed at sampling point 11 and RX is placed at sampling point 15.) Theoretical value is calculated based on Friis formula and using the measured on-chip dipole antenna gains of -12 dB. -85 -80 -75 -70 -65 -60 -55 -50 -45w/ cover w/o cover theoretical value in the free space 4_5 1_3 1_3 1_3 1_3 4_5 1_2 1_2 1_2 5_6 5_6 5_6 4_7 4_7 4_7 6_7 6_7 6_7 6_7 12_14 11_13 12_14 11_13 12_14 12_14 11_13 11_13 11_15 11_15 11_15 11_15 8_9 8_9 8_9 8_9 8_9 2 21 4 RR GG P Prt t r f = 24 GHz, = 12.5 mm 5 10 15 20 Distance (cm) 8_10 8_10 8_10 8_10 8_10 Ga (dB)

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38 lowest power level for the case wi th a metal cover is around -68 dB m, which is greater than the sensitivity. There is around 6-dB margin in the real operating envi ronment. The antenna performance can be improved by thinning the silic on substrate, which should increase the link margin. A concern for the Ga measurements is that the phase information is not included. In particular, signals from multi-paths could add to result in larger power. Especially, in the presence of a metal cover, the number of multi-paths contributing to the received power could be increased. If the time delays among the signals traveling on different paths exceed the tolerance for the clock data recovery (CDR) circuit in th e receiver, CDR will not be able to recover the signal. To better quantify this, the time delay sp reads have been measured and shown in Figure 3-8 for the cases with and without a metal cove r at 10-cm and 15-cm separations. The channel response was measured between 15 and 26.5 GHz, and converted into the time domain waveform using IDFT. Figure 3-8(a) shows the time domain measurement results w ith probes landing on a thru calibration structure. There is a single well defined peak with almost no time delay. The time domain channel characteristic measured in the PCB without a metal cover at 15-cm separation (point 1 to 10 in Figure 3-6) is shown in Figure 3-8(b). There ar e two dominant peaks at 0.63 and 1.05 ns. The second peak is slightly higher in magnitude. There are thr ee additional peaks with magnitude that is approximately 50% of the dom inant peak. In addition to these, there are numerous peaks with magnitude that is around 20 % of the dominant peak up to 30 ns. The PCB is clearly a multiple path rich environment. In free space, 24-GHz signals transmission time should be around 0.5 ns for 15-cm separation. The mean excess delay, defined in Eq. (3-2) [41], is 1.86 ns, and rms delay spread, defined in Eq. (3-3) [41], is 2.75 ns.

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39 Figure 3-8(a). Time delay spread measurement re sults probes landing on a thru calibration structure (almost negligible time delay). k k k kk k k k kkP P a a 2 2 (3-2) 2 2 (3-3) k k k kk k k k kkP P a a 2 2 22 2 where ak is the relative amplitude of the detectable signal and P(k) is the power level of the power delay profile at timek. It will be challenging to implement a robust simple wireless communication system with 400-Mchi ps/sec chip rate for the channel with such characteristics. The chip period is 2.5 ns. Managing the rms excess delay of 2.75 ns will complicate the receiver design. 0 5 10 15 20 25 30 35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Time (ns)|ifft(S21)| t = 0 ns

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40 Figure 3-8(b). Time delay spread measurement results PCB without a metal cover at 15-cm separation Figure 3-8(c) shows the measurements for the case with a metal cover at 15-cm separation. Explicitly, there is one dominant peak at 0.63 ns and its amplitude is around 3-4 times higher than the case without a cover. Like the case without the cover, there are three additional peaks with magnitude that is appr oximately 50% of the dominant peak. Beyond 5 ns, there are no significant peaks. This channel is much simpler. The mean excess delay and rms delay spread are 0.35 and 0.41 ns, which are actually 81.2% and 85.1% smaller than the case without a cover. This is probably due to the fact that the signals reflected by the metal cover have an un-obstructed path and is significantly str onger than the signals propagating near the surface of the PCB with numerous electr onic components. At 15-cm sepa ration with a metal cover, the maximum excess delay from measurement is around 1.1 ns (4th peak in Figure 3-8(c)). The 1.1ns maximum excess delay is acceptable for prop er CDR operation of the system with 4000 5 10 15 20 25 30 35 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 x 104 |ifft(S21)| Time (ns) 15-cm separation t = 1. 05 n s t = 0 63 n s t = 1.2 6 n s t = 1. 8 1 n s t = 2. 58 n s t = 16.66 ns t = 3 .42 n s

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41 Figure 3-8(c). Time delay spread measurement results PCB with a metal cover at 15-cm separation Mchips/sec chip rate. Figure 3-8(d) shows the measurement results for the case with a metal cover at 10-cm separation (point 4 to 7 in Fi gure 3-6). Once again, a single do minant peak is observed. The amplitude is approximately 4 times larger than that at 15-cm separation. The time delay of the maximum peak is 0.49 ns. The mean excess delay and rms delay spread are 0.11 and 0.18 ns. These measurements indicate that by properly se lecting the transmitter and receiver positions in a PCB, reflections from a metal cover can be u tilized to improve received power level and to reduce the delay spread thus relaxing the link margin. 0 5 10 15 20 25 30 35 0 1 2 3 4 5 6 7 8 x 104 Time (ns)|ifft(S21)| 15-cm separation 0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 6 7 8 x 104 (ns) t = 0 63 n s t = 0.91 ns t = 1.2 6 n s t = 1.74 ns

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42 Figure 3-8(d). Time delay spread measurement results PCB with a metal cover at 10-cm separation 3.5 Summary Large scale fading channel characteristics and ti me delay spread in a printed circuit board for a hybrid engine motor controller have been measured at 24 GHz using 3-mm zigzag dipole antennas fabricated on 20--cm silicon substrates. With a metal cover located around 3.5 cm above the PCB, the antenna pair gain, Ga can be improved by ~ 10 dB. Furthermore the excess delay and rms delay can also be reduced. The maximum excess delay is around 1.1 ns at 15-cm separation, which is acceptable for recovery of clock and data for a 400-Mchip/sec system. By thinning the silicon substrate, the on-chip dipole antenna perf ormance could be improved and further improve the link margin. It has been verifi ed that on-chip dipole antennas can be used for wireless communication in the hyb rid engine controller board. 0 5 10 15 20 25 30 35 0 0.5 1 1.5 2 2.5 3 Time (ns)|ifft(S21)| x 103 10-cm separation 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 x 103 (ns) t = 0.49 ns t = 0.7 ns t = 1.12 ns

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43 CHAPTER 4 CDMA TX CHAIN DESIGN 4.1 Introduction The hybrid engine controller boa rd shown in Figure 4-1, has 2 dead-time controllers (D1 and D2) and 12 motor control nodes (M1, M2 M12). Each dead-time controller communicates with 6 motor control nodes. For example, D1 needs to communicate with M1, M2, and M6. In order to handle the multi-path rich environment, shown in Chapter 3, CDMA (code division multiple access) has been chosen fo r downlink (dead-time controller to motors) to simplify the transmitter design [42]. The uplink (mo tors to dead-time controller) uses FDMA (frequency division multiple access) to avoid th e synchronization problem of CDMA [42] as shown in Figure 4-2. There is an additional ch annel assigned for temperature information from the motor. Usually, CDMA has to deal with the near-far problem [43], [44]. The near-far problem is due to the varying received signal strengths resu lting from distance variat ion between a receiver and several transmitters. The larger signal from a transmitter located nearer becomes a strong interferer to the signal from radios farther away In addition, the signals from the transmitters also need to be synchronized in the presence of near-far problem. Mitigating these requires power control circuitry and significant digital base band proc essing. Using FDMA for uplink eliminates these problems. Since there are a CDMA transmitter and a FDMA receiver (RX) on the same chip at the dead-time controller side, the frequency plan is especially important. The downlink (CDMA path) frequency band is between 15.6 GHz and 18 GHz, and the uplink (FDMA path) frequency band is between 24.2 GHz and 27 GHz (Figure 4-2). Th e 6-GHz frequency offset between the TX and RX is intentionally chosen to improve isolation. Table 4-1 shows the frequency allocation for

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44 Figure 4-1. Board showing dead-time and motors (D1, D2: dead-time controller, M1-M12: motor). the downlink and uplink. Using frequency bands above 15 GHz allows integration of a compact on-chip antenna with the circuit blocks. This enables a higher integration level, mitigates the packaging problems, and lowers the manufactur ing cost. The spread spectrum technique is applied in the TX chain. Walsh codes are us ed to generate 8 or thogonal 8-bit codes for supporting up to 8 channels. For the present appli cation, only 6 channels are needed, as shown in Table 4-1. Figure 4-3 shows the block diagram for TX and RX chains for a dead-time controller. The TX chain includes a PLL, divider chains, a mixer, a power amplifier (PA), attenuators, a digital coder, a duplexer, and an on-chip dipol e antenna. The PLL generates a 24-GHz carrier. D1 D2 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M12 M11

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45 The signal is frequency divided down to 12 GHz a nd 4.8 GHz to generate the IF and LO inputs of the mixer. Following the mixer, the signal is up-converted to 16.8 GHz and passed through pre-drivers and a differential PA stage. The unwanted signals below or above the desired frequency band (15.6-18 GHz) would be filte red by the duplexer. Finally, the signal are transmitted out using a 4-mm on-chip dipole antenna. Based on the link margin analysis (Table 1-1), the power delivered to th e antenna needs to be ~ 10 dBm, which can provide ~ 21-dB link margin. A digital coder is the control block, wh ich provides the modulation control signal for the TX chain. It includes f lip-flops, XNORs, an adder, and an address decoder, shown in Figure 4-4 [45]. After the adder and address decoder, contro l signals are used for CDMA modulation. These are used to control the pre-driver stage to modulate the 16.8-GHz carrier. Details will be described in section 4.2.1. Figure 4-2. Downlink and uplink modulation schemes, and frequency allocation. FDMA Ch. 7F D M A C h 1 Dead-time Controller Motor Phase 1 C D M A C h 1 F D M A C h 2 C D M A C h 2 F D M A C h 6 C D M A C h 6 Motor Phase 2 Motor Phase 3 Motor Phase 4 Motor Phase 5 Motor Phase 6 Motor Temp. FDMA path Dead-time Controller CDMA path Motors 15.6-GHz ~ 18-GHz 24.2-GHz ~ 27-GHz Dead-time Controller Motors & Temperature FDMA Ch. 7F D M A C h 1 Dead-time Controller Motor Phase 1 C D M A C h 1 F D M A C h 2 C D M A C h 2 F D M A C h 6 C D M A C h 6 Motor Phase 2 Motor Phase 3 Motor Phase 4 Motor Phase 5 Motor Phase 6 Motor Temp. FDMA Ch. 7F D M A C h 1 Dead-time Controller Dead-time Controller Motor Phase 1 Motor Phase 1 C D M A C h 1 F D M A C h 2 C D M A C h 2 F D M A C h 6 C D M A C h 6 Motor Phase 2 Motor Phase 2 Motor Phase 3 Motor Phase 3 Motor Phase 4 Motor Phase 4 Motor Phase 5 Motor Phase 5 Motor Phase 6 Motor Phase 6 Motor Temp. Motor Temp. FDMA path Dead-time Controller CDMA path Motors 15.6-GHz ~ 18-GHz 24.2-GHz ~ 27-GHz Dead-time Controller Motors & Temperature FDMA path Dead-time Controller CDMA path Motors 15.6-GHz ~ 18-GHz 24.2-GHz ~ 27-GHz Dead-time Controller Motors & Temperature FDMA path Dead-time Controller Dead-time Controller CDMA path Motors Motors 15.6-GHz ~ 18-GHz 24.2-GHz ~ 27-GHz Dead-time Controller Dead-time Controller Motors & Temperature

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46 Table 4-1. Frequency plan for each motor and dead-time controller (frequency band unit: GHz) TX Channel Freq. Band RX Channel Freq. Band Chip Motor 1 24.2-24.6 1 15.6-18, C1 1 2 24.6-25.0 2 15.6-18, C2 2 3 25.0-25.4 3 15.6-18, C3 3 4 25.4-25.8 4 15.6-18, C4 4 5 25.8-26.2 5 15.6-18, C5 5 6 26.2-26.6 6 15.6-18, C6 6 7 26.6-27.0 7 Dead-time controller 1 15.6-18, C1 1 24.2-24.6 1 2 15.6-18, C2 2 24.6-25.0 1 3 15.6-18, C3 3 25.0-25.4 1 4 15.6-18, C4 4 25.4-25.8 1 5 15.6-18, C5 5 25.8-26.2 1 6 15.6-18, C6 6 26.2-26.6 1 7 26.6-27.0 1 4.2 Sub-Blocks of Transmitter Chain 4.2.1 Power Amplifier A power amplifier (PA) is a key block for the TX chain. Usually, a CMOS PA suffering from the lower breakdown voltage due to a th in gate oxide layer of mainstream CMOS technologies has lower output power compared to the PAs in III-V a nd bipolar technologies [46]-[50]. Achieving 10-dBm output power and good efficiency is challenging. There are different types of power amplifiers, such as class A, B, C, D, E, and F. Figure 4-5 shows a typical schematic of class A power amplifier, which operates linearly across the entire input and output range. An RFC (RF choke) is used to provide the connection to the voltage supply. The matching network transforms the load impedance, 50 to lower impedance, RT, at the drain node. The maximum voltage of drain node is 2VDD. The power delivered to the matching network (Pdel) is

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47 Figure 4-3. Block diagram for the tr ansceiver in a dead-time controller. Figure 4-4. Block diagram for the digital coder of TX chain [45]. Coder Frequency Divider VCO PLL Digital Clock 4.8 GHz LOR 24 GHz LOT 12 GHz BPF Duplexer Filter 24.2 GHz LNA Duplexer Gain ~ 12 dB 2.8 GHz Bandwidth RF Amplifier Gain ~ 15 dB 15.6 GHz LPF Baseband Amp LPF LPF 400 MHz 800 MHz 2.8 GHz Baseband Amp Baseband Amp IF Amp 1.6 GHz G ~ 8 dB LOR 24 GHz TX chains RX chains Data to Deadtime controller Crystal Reference Data from Deadtime controller Chip boundary Buffer Buffer Buffer PA Transceiver at dead-time controller

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48 Figure 4-5. Schematic of the common source power amplifier. T DD T DD delR V R V P 2 22 2 (4-1) A current of (VDD/RT) can be provided by the RFC. Therefore, the power consumption (PDC) is (VDD/RT)VDD=VDD 2/RT. Consequently, the maximu m drain efficiency is 2 1 22 2T DD T DD DC delR V R V P P (4-2) For class A PA, the maximum drain efficiency is just 50%. The low efficiency is due to the conduction angle for M1, of class A PA is 360 shown in Figure 4-6(a). If the conduction angle can be reduced, less power is dissipated. For example, the conduction angle of class B PA is only 180 which means the drain current is sinusoidal for one half cycle and zero for the other half cycle, as shown in Figure 4-6(b). It can lower the power consumption and improve PA efficiency. Assume the current (Figure 4-6(b)) is Matching Network Vin VDDRFC M1 RL RT

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49 ,cosmax Ii 22 (4-3) ,0 i 2 2 The total current is ...2cos cos2 10 aaai (4-4) dcI I dI a max 2 2 max 0cos 2 1 1 max 2 2 2 max 12 cos 1 I I d I a ...21 maxIIIIdc The average drain current drawn from VDD is given by T DD DDR VI aI2max 0 (4-5) The power consumption is (2VDD 2/ RT). Therefore, the Pdel is T DD T delR V R I P 2 22 2 1 (4-6) Thus, maximum efficiency is 4 2 22 2 T DD T DD DC delR V R V P P (4-7) The other type of PA called class AB conducts between 50% and 100% of the cycle. It has the intermediate performance for efficiency and linearity, between cla ss A and class B PAs.

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50 Figure 4-6. Transistor drai n current and conduction angle, for class A and B power amplifiers. However, class A, B, and AB power amplifiers all use active devices as a controlled current source. There is another type of PA, in which an active device acts as a switch. Theoretically, switching type PAs should consume no power and achieve 100% efficiency. For instance, class E and class F PAs are switching type. The simple schematic is similar to that shown in Figure 45. The difference between class A and class E PAs is that the input sign al for class E PA is expected to have a rectangular waveform. To reduce power dissi pation, there should be small current when the drain voltage is finite, and small voltage when the current is large. Both conditions minimize the product of voltage and cu rrent, which reduces the power consumption. Figure 4-7 shows a typical schematic of class E PA. It consists of a transistor, a capacitor C1 shunted to ground, and a series network C2 and L1. The value of C1, C2, and L1 are chosen such that Vx satisfies three conditions [51]: (1) As the switch turns off, Vx remains low long enough for the current to drop to zero. (2) Vx reaches zero just before the switch turns on. (3) dVx/dt is also near zero when the switch turns on. (a) Class A type (=360) (b) Class B type (=180) Imax/ 2 / 2 0

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51 From [51], the values of C1, C2, and L1 can be chosen as, RQ LL1 (4-8) R R C 447.5 1 2 1 4 12 1 (4-9) 08.2 42.1 1 447.512L LQQ CC (4-10) The inductor quality factor QL should be as large as possi ble. On the other hand, RFC used in Figure 4-7 has to be implemented by a regular on-chip i nductor. Therefore, QL of on-chip inductors is a factor which limits the class E PA efficiency. The transistor of course has on resistance and finite switching time, which also limit the efficiency. Nevertheless, class E PA is still an attractive option for high frequency circuit design due to its high efficiency. It is suitable for communication systems with a constant envelop modulation. Back to the hybrid engine controller board, the amplitude modulation scheme (ASK) is needed for the CDMA downlink, which means a linear PA should be used. At 20 GHz using Figure 4-7. Schematic of a class E power amplifier. VDDM1 C1C2L1RL RFC Vin VoutX

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52 single-ended class E PA with 9-dBm output P1dB was reported [52]. It is possible to use the linear portion of a class E PA for this purpose. Due to the integration with an on-chip dipole antenna, a differential PA structure is a dopted. Based on the specification me ntioned previously, the output P1dB should be around 10 dBm. High er efficiency and lower power consumption can be possibly achieved compared with using a class A linear PA [53]-[55]. The comparisons of power amplifiers operating near 20 GHz is summarized in Table 4-2. In general, class E PA can achieve higher PAE performance. Due to the diode detection process used in th e RX chain at the moto r side, the square-law operation of diode has to be considered [42]. Th erefore, the desired multi-level signals at PA output should follow a square-root relation among N levels, where N equals to 2, 3, 4, 5 and 6. At RX side, these result in a constant voltage step between levels after diode detection. There are several ways to real ize multi-level amplitude modulation at the PA stage. One way is to modulate the supply voltage to contro l output power of PA, sh own in Figure 4-8 [56], [57]. It has the disadvantage of sensitive to s upply variation and requi res a feedback loop for tracking and adjusting the PA envelope. Many ap proaches to improve efficiency by using nonlinear PAs with a linear ization circuit or linear PAs with an efficiency-enhancement circuit have been discussed in the litera ture [58]-[61]. However, use of a dc-dc converter to implement a dynamic voltage supply is needed. The dc-dc convert er may be a boost, buck, or buck-boost type. Table 4-2. Comparisons of power amplifiers operating near 20 GHz. Freq. Technology ClassificationVDD Gain Pout PAE [52] 18 GHz 0.13m CMOS Class E 1.5 V > 30dB 10.9 dBm 23.5 % [52] 20 GHz 0.13m CMOS Class E 1.5 V 26 dB 10.2 dBm 20.5 % [53] 17 GHz 0.13m CMOS Class A 1.5 V 11 dB 5 dBm (@OP1dB) 2.4% (@OP1dB) [54] 17 GHz 0.13m CMOS Class B 1.5 V 14.5 dB17.1 dBm 9.3 % [55] 24 GHz 0.18m CMOS N/A 2.8 V 7 dB 14.5 dBm 5~6 %

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53 It usually occupies a large area and leads to higher cost. On to p of this, a chip rate of 200 Mchips/sec needs to be supported for the wireless interconnects sy stem. This is challenging for the dc-dc converter. The second way is to use a current-steering te chnique [62] to modulate the gate bias of pre-drivers, which can change PA output as shown in Figure 4-9. A similar idea was used to lower quiescent current at low output power to improve PA effici ency (adaptive bias control) [60], [61]. However, based on simu lations, it has long fall time and precise gain control is also difficult by only adjusting gate bi as without closed-loop control. This will make the design more complicated. A simple solution and architecture are required for a PA operating at higher frequencies (above 15 GHz), compared to WC DMA PA operating at a lower frequency band [63], [64]. Figure 4-8. Kahn envelope elimination and rest oration scheme with using a dc-dc converter. Envelope detector Envelope detector Error amplifier Error amplifier DC-DC converter Limiter PA and drivers RF Input RF Output

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54 Figure 4-9. Modulate tr ansistor gate bias. Another method to modulate a PA and achieve multi-level signals at a PA output is to incorporate an attenuator. As shown in Figure 410, the attenuator can be placed at the signal path to adjust the signal strength. The single-ended class E PA structure and attenuators are shown in Figure 4-11. It has 4 pre-diver stages and one last PA stage. There are 7 attenuators with different transistor size to control 7 levels at PA output. The gate node of each attenuator is connected to corresponding coder output. There are 6 attenuators connected at the gate of 4th predriver stage. And there is one at tenuator connected at the gate of second stage. The idea is that coder would increase or decrea se the number of switches turn ed on to set the output power. Since the signal swing at the second stage is smaller than that at the 4th stage, the attenuator size for level 0 could be smaller if it is placed at an earlier pre-amplifier st age. This effectively minimizes the transistor size needed to control level 0 and mitigates the drivability requirement for the digital coder. Table 4-3 shows the truth table for the coding scheme For level 6, only one attenuator is turned on. On the other hand, for le vel 0, all attenuators are turned on. The control scheme leads to smaller rise and fall time duri ng transitions, because it turns on or turns off necessary attenuators only. It minimizes the capacitance change during transitions. The coder load Coder control signal Input (transistor gate) Pre-drivers PA output -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.50.00E+002.00E-094.00E-096.00E-098.00E-091.00E-081.20E-08time ( V ) VDD

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55 Figure 4-10. PA using attenuators for output po wer control and CDMA TX chain block diagram. Figure 4-11. Schematic of a single-ended fi ve-stage class-E CMOS power amplifier. coder V DD 1 V DD3 V b1 V b2 V b3 10 p F 14 m 14 m 24 m 100 m V DD2 40 m V b4 M 1 M 7 M 3 M 5 M 4 M 2 M 8 Driver Output stage Pre-amplifier 0 12345 6 Vg M 6 attenuato r Zs On-chip Antenna Multi-level CDMA co n t r o l s i g n a lIF Power Amplifier Duplex Filter PLL (24-GHz) Digital Coder 12 GHz 4.8 GHz Pre amplifier Attenuator LO 2 5 2 16.8 GHz

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56 Table 4-3. Truth table of coding and the ratios between levels at TX side and after RX detection. att_0 att_1 att_2 att_3 att_4 att_5 att_6 Level 6 0 0 0 0 0 0 1 Level 5 0 0 0 0 0 1 1 Level 4 0 0 0 0 1 1 1 Level 3 0 0 0 1 1 1 1 Level 2 0 0 1 1 1 1 1 Level 1 0 1 1 1 1 1 1 Level 0 1 1 1 1 1 1 1 Ideal ratio at TX side After RX detection Level 2 / Level 1 2 2 Level 3 / Level 1 3 3 Level 4 / Level 1 4 4 Level 5 / Level 1 5 5 Level 6 / Level 1 6 6 requires a 400-MHz clock and input data rate is 50 Mbps. The PA output ought to have a 16.8GHz carrier with an 400-Mbps envelope. The mi nimum output duration at an output is 2.5 ns. The target for rise and fall time of the envelope is 10 %, which is 250 ps. In order to provide the ability to adjust the level ratio after fabrication, five small switches with AND gates are added. It will provide extra flexibility for the measurements. D-flip flops added at the output of binary thermometer decoder help the synchronization of output signals. As shown in Figure 4-11, the bias of class E PA (Vb4) is applied through an inductor. The inductor resonates with Cgd of last PA stage, which increases PA gain [52]. The pre-driver stages are designed to achieve high volta ge gain. Meanwhile, the last PA stage is designed to maximize output power and efficiency. The concern for th e inductive biasing technique is the self oscillation of last PA stage. Figure 4-12 shows th e small signal model of the last PA stage [52]. The attenuators are placed at the input of 4th common source amplifier. By turning on different combinations of attenuators, the impedan ce looking back toward the drain of 4th pre-driver stage

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57 Figure 4-12. Small signal model of the la st PA stage (common source amplifier). (shown in the Figure 4-11) can be ch anged, which is represented as Zs. The open loop gain of the PA stage is gd sg sg gd sgdmsC ZZ ZZ sC ZZZgsT 1 // // 1 //// )( (4-11) The term, (Zg // Zs) affects the open loop gain and phase. The oscillation starts when the loop gain is greater than 1 and the phase change must equal to 360 degree [52]. The circuit is near oscillation condition without any RF input (16.8 GHz sinusoidal sign al). With the RF input, the self oscillation is suppressed. In the frequency domain, only one si ngle desired frequency peak is observed. The attenuators placed along the signal path change the signal swing at the input of last PA stage. Especially for level 0, the signal stre ngth is dramatically atte nuated by the attenuators. Suppressing the self osci llation is a critical concern for this design to guarantee to have zero amplitude level 0. The key factor for this is properly setting Zs. The other design concern is the rise and fa ll time of output envelope. The rise time for level 0 to level N (N=6, 5, 4, 3, 2, 1) is dominated by the gate bias resistor at the second pre-Zs Zg Cgd Zd Vg gmVg

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58 driver stage. The gate bias resistor is 5 k which is large to preven t the loading of 16.8-GHz carrier signal. However, the rise or fall time largely depends on the RC time constant of the equivalent network at the gate of second pre-driver. The attenuator settings change the equivalent RC network, shown in Figure 4-13. When the switc h is OFF, the parasitic capacitance is only (Cgd+Cdb). When the switch is ON, the para sitic capacitance is still around (Cgd+Cdb). However, the on resistance of the switch is much smaller compared to the 5-k bias resistor. The equivalent capacitance is relatively c onstant, which is roughly the sum of Cdbs of attenuators and Cgg of the pre-driver. It can be represented as Ceq. When the transition happened from level 0 to level N, the equivalent resistance changes from few tens ohms to 5 k Therefore, the RC time constant is eqeqCR (4-12) In the above equation, Req is the equivalent resistance of the equivalent network. In simulations, the RC time constant is ~ 800 ps. Figure 4-13. Lumped circuit models with the at tenuator switched ON and OFF. The rise and fall times depend on the RC time constant of equi valent network at the gate node of second pre-driver. V DD1 V b1 14 m 14 m M3M4ON Cdb + Cgd RON Cgg 5 k V DD1 V b1 14 m 14 m M3 M4 OFF 5 k Cdb + Cgd Cgg Attenuator Attenuator

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59 In section 4.3, simulation results of the multi-level PA as well as the CDMA transmitter chain will be presented. Measurement setup and results will be presen ted in section 4.4.4. 4.2.2 Duplexer For modern cellular phone systems, SAW (surface acoustic wave) filters are usually used to implement the duplexer function. However, the common working frequency band for SAW filters is only from around 20 MHz to 3 GHz, which is much lower than the frequencies needed for the hybrid engine controller board. An on-chip duplexer is designed based on the specifications in Table 4-4. The insertion lo ss targets of TX band (from 15.6 GHz to 18 GHz) and RX band (from 24.2 GHz to 27 GHz) are 3 dB. The other criterion is isolation between TX and RX should be 30 dB or better. It is challengi ng to realize the low inse rtion loss target using on-chip inductors. Two 3rd order Chebyshev band stop filters (BSF) ar e also used to achieve lower insertion loss and sharper notch response at rejection bands (Figure 4-14 [40]). Figure 4-15 shows the schematic of the single-ended on-chip duplexer. It includes 3 inductors an d 3 capacitors at TX and RX sides. La1, La2, and Ca3 form a low pass filter (LPF) and Ca1, Ca2, and La3 form a high pass filter (HPF). At TX side, the stopbands of LPF and HPF are overlapped to notch out RX signals, vice versa. Figure 416 is the micrograph of differen tial on-chip duplexer, which is fabricated in UMC 130-nm technology. The measurement results are discussed in section 4.4.1. 4.2.3 Mixer Figure 4-17 shows a schematic of the double ba lanced Gilbert cell up-conversion mixer. Usually, LO power is large. A double balanced st ructure can alleviate th e LO leakage problem due to the opposite phases. The i nput signals at IF and LO ports are provided from the PLL and divider chains, which are discussed in section 4.2.4. A 50input matching network of IF port is included for testing.

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60 Table 4-4. Specification of the on-chip duplexer. Performance target Insertion loss Below 3 dB for 15.6 ~ 18 GHz TX band (PA port) Return loss Below 10 dB for 15.6 ~ 18 GHz Insertion loss Below 3 dB for 24.2 ~ 27 GHz RX band (LNA port) Return loss Below 10 dB for 24.2 ~ 27 GHz Antenna port Return loss Below 10 dB for 15.6 ~ 18 GHz and 24.2 ~ 27 GHz PA and LNA Isolation (Rejection) Below 30 dB for 15.6 ~ 18 GHz and 24.2 ~ 27 GHz Figure 4-14. On-chip duplexer using two band stop filters [40]. Figure 4-15. Schematic of the si ngle-ended on-chip duplexer [40]. PA LNA Antenna TX side RX side La1 Ca2La3 Ca1 La2 Ca3 Lb1Cb2Lb3Cb1Lb2Cb3 TX RX Duplexer BSF BSF Antenna

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61 Figure 4-16. Die micrograph of the differential on-chip duplexer fabricated in the UMC 130-nm technology. Figure 4-17. Schematic of double balan ced Gilbert cell up-conversion mixer. LNA port PA port ANT port 1.01 mm 560 m IF+ IFLOLO+ LO+ VDD RFRF+

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62 4.2.4 Divider Chain As shown in Figure 4-10, a divider chain fo llows the PLL, which provides the 24-GHz carrier. The divider chain genera tes 12-GHz and 4.8-GHz signals fo r LO and IF signals for the mixer. The divider chain include s a divide-by-2 synchronous circ uit, a divide-by-5 synchronous circuit, a multiply-by-2, and buffer stages. The mo st challenging block is the first divide-by-2 circuit, which has to work at 24 GHz [65]. The divider can operate up to 26 GHz with a 1.5-V power supply in the 130-nm CMOS technology. A divide-by-5 circuit is placed following the divide-by-2 circuit. It is the ot her challenging block [66]. The out put load of divide-by-5 circuit has to be small to keep the loading of first di vide-by-2 circuit. The divide-by-5 circuit should operate at 12 GHz [66]. Multiply-by-2 and phase-shift blocks are show n in Figure 4-18. The input of multiply-by2 comes from the divide-by-5 output. One DCVS L buffer and three-stage inverter buffers are used to re-shape the waveform from the divi de-by-5 block. The synchronous divide-by-5 is sensitive to the output load due to the fact that the 12-GHz input signal is connected to the output to form a loop. The output load is seen by the input 12-GHz signal. Therefore, the design challenge is to keep the load small for the divide-by-5 block to guarantee proper operation. A 2.4-GHz square wave is applied at M1 and M2 gates of frequency doubler. M1 and M2 will be turned on (linear region) and o ff (cut-off region) alternatively, like a switch. Therefore, the signals at node X will have frequency that is 2 times the input frequency, which is 4.8 GHz. 5k resistors are used to properl y manage charging and discharg ing time constants, which are required to maintain sufficient amplitude at nod e X. The signal at node X is fed to an active balun to convert single ended signal to differential. The schematic of an ac tive balun is shown in Figure 4-18 [67]-[69]. The differential 4.8-GHz signal is generated at the output of phase-shifter.

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63 Two inductively loaded differen tial cascode buffers are used to amplify the signal before the mixer IF port. The tuned buffers band pass filter to knock down unwanted signals. The divide-by-5 circuit output doe s not have 50% duty cycle. It has the ratio of T1 to T2 of 2:3, shown in Figure 4-18. The unequal duty cy cle causes a mismatch problem and generates additional unwanted harmonics. In simulations, the widths of M3 and M4 have been intentionally mismatched as well as the load resistance R has been varied to account fo r +/20% variation to evaluate the robustness of design. By changing the widths of M3 or M4 from 16 m to 12 m or 20 m, the mismatch of currents flowing through the two branches can be increased +/8.5%. This is significantly larger than the 3.5-% current mismatch expected for the process. In addition to the 4.8-GHz signal, 2.4, 7.2, and 9.6-GHz signals as well as 2.4-GHz input signal mix with LO at 12 GHz, which generate 14 .4, 19.2, and 21.6 GHz at the PA output. Table 4-5 shows the mismatch simulation results. It summarizes the signal stre ngth difference between 2.4 and 4.8 GHz, 4.8 and 7.2 GHz, as well as 4.8 and 9.6 GH. It shows smaller signal strength Figure 4-18. Schematic of multiply-by-2 and phase-shift blocks. tomixer x2 output 4.8GHz 2.4GHz Vdd Vgate 5k 5k 0.5V 10pF 5k 5k(Right=16 m) (Left=16 m) (T1) 2 : (T2) 3 (T1) 2 : (T2) 3 M1 M2 X M3M4R=500 PLL 2 5 24GHz DCVSL buffer

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64 Table 4-5. Mismatch simulation results. Cases 2.4-4.8 GHz4.8-7.2 GHz4.8-9.6 GHz 1x R, 16 m (Right), 16 m (Left) 43.93 dB 18.30 dB 46.46 dB +20% R, 16 m (Right), 16 m (Left) 43.49 dB 18.39 dB 45.56 dB -20% R, 16 m (Right), 16 m (Left) 44.46 dB 18.15 dB 47.51 dB 1x R, 16 m (Right), 12 m (Left) 44.12 dB 18.28 dB 50.46 dB +20% R, 16 m (Right), 12 m (Left) 43.70 dB 18.38 dB 49.92 dB -20% R, 16 m (Right), 12 m (Left) 44.63 dB 18.15 dB 50.98 dB 1x R, 12 m (Right), 16 m (Left) 44.11 dB 18.22 dB 42.78 dB +20% R, 12 m (Right), 16 m (Left) 43.66 dB 18.31 dB 41.34 dB -20% R, 12 m (Right), 16 m (Left) 44.67 dB 18.09 dB 44.57 dB 1x R, 16 m (Right), 20 m (Left) 43.82 dB 18.31 dB 44.52 dB +20% R, 16 m (Right), 20 m (Left) 43.39 dB 18.39 dB 43.47 dB -20% R, 16 m (Right), 20 m (Left) 44.38 dB 18.20 dB 45.76 dB 1x R, 20 m (Right), 16 m (Left) 43.82 dB 18.36 dB 49.12 dB +20% R, 20 m (Right), 16 m (Left) 43.40 dB 18.45 dB 48.31 dB -20% R, 20 m (Right), 16 m (Left) 44.36 dB 18.23 dB 49.48 dB difference between 4.8 and 7.2 GHz. After the up -conversion mixer, 7.2-GHz signal will become 19.2 GHz, which is close to the desired freque ncy band (from 15.6 GHz to 18 GHz). Since there is a duplexer following the PA stage, the 19. 2-GHz signal is attenuated by 3.7 dB. The interference concern from the mism atch should be taken in to c onsideration, which is discussed in section 4.4.5. 4.3 Simulation Results: Mult i-Level Signal at PA Output Figure 4-19 shows the TX chain simulation results of multi-level signals at the differential PA output. The target levels are 0.63, 0.93, 1.15, 1.34, 1.48, and 1.62 V. Although the desired output power is ~ 10 dBm, higher simulated output power is needed for margin. Although the inductor gate bi as technique has been applied, th e self oscillation is suppressed by the source impedance change as discussed in sec tion 4.2.1. The level 0 switch is placed at the gate of second pre-driver st age to lower the drivability requirement for the coder. As mentioned earlier, additive/subtractive coding scheme is used to reduce the rise and fall time of the output envelope. The output at le vel 0 can be minimized to close to 0 V (shown

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65 in Figure 4-19(a)). Table 4-6 summarizes the si mulated ratio between the output levels and attenuator sizes. The error percenta ge is calculated compared to the targets. The worst cases are the level 2 to level 1, and level 4 to level 1 ratio s, which have ~ 7.0-% error. The biggest load for the attenuators is due to the level 0 switches, which is ~ 12 fF. Figure 4-19(a) shows the simulation results for the differential PA with a decoder from 5 ns to 30 ns. The level information is (0241353246). Th e rise time and fall time at PA output are related to the equivalent RC network time constant. In the simulations, larger interconnection parasitics than actual are included to over-estimat e the load for the coder. The simulation results shown in Figure 4-19(a) has ~ 32-% rise time (800 ps) from level 0 to level 2. It decreases the level-2 period to 1.6 ns instead of 2 ns simulatio n target (250-ps rise and fall times). Most of the rise and fall time for other transitions are within 10 %. This shows that it is feasible to achieve the multi-level PA outputs with a 16.8-GHz carri er and a 400-Mbps envelope. The measurement results as well as further discussions are presen ted in section 4.4.4. Figure 4-19(b) shows the simulated CDMA waveform at the TX output up to 180 ns. Table 4-6. Simulation results of ratio between leve l N and level 1, where N equals to 2, 3, 4, 5 and 6. Ideal ratio Simulated value Simulated ratio Error (%) Level6 / Level1 2.450 1.62 (L6) / 0.625 (L1)2.59 5.7 Level5 / Level1 2.236 1.48 (L5) / 0.625 (L1)2.37 6.0 Level4 / Level1 2.000 1.34 (L4) / 0.625 (L1)2.14 7.0 Level3 / Level1 1.732 1.15 (L3) / 0.625 (L1)1.84 6.2 Level2 / Level1 1.414 0.93 (L2) / 0.625 (L1)1.49 7.0 Switch size (transistor width and length) Level 6 (0.25 m / 120 nm) x 1 => differential loading: 0.50-m width Level 5 (0.25 m / 120 nm) x 3 => differential loading: 1.50-m width Level 4 (0.25 m / 120 nm) x 5 => differential loading: 2.50-m width Level 3 (0.25 m / 120 nm) x 6 => differential loading: 3.00-m width Level 2 (0.25 m / 120 nm) x 6 => differential loading: 3.00-m width Level 1 (0.25 m / 120 nm) x 9 => differential loading: 4.50-m width Level 0 (0.25 m / 120 nm) x 36 => differential loading: 18.0-m width

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66 Figure 4-19(a). Simulation results of mu lti-level signals at differential PA output. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 x 10-7 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Time (s)Voltage (V) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 x 10-7 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Time (s)Voltage (V) Figure 4-19(b). TX chain simulation up to 180 ns. 0.5 1 1.5 2 2.5 3 x 108 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 Time (s) Volta g e ( V ) 32 % 2 4 1 3 5 3 2 4 6 0

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67 4.4 Measurement Results 4.4.1 Duplexer Figure 4-20. Plots of inserti on loss and return loss between antenna (ANT) port and PA port. (TX band: 15.6-18 GHz) Figure 4-20 shows the measured 2-port S-pa rameters between the duplexer PA and ANT ports. It shows that the insertion loss is ~ 3 dB from ~ 15.6 GHz to ~ 18 GHz. Return loss of the PA port and antenna port are be low 10 dB within the desired band (from 15.6 GHz to 18 GHz). The insertion loss performan ce meets the specification. Figure 4-21 shows the measured 2-port Sparameters between duplexer LNA and ANT ports. It shows that the insertion loss is ~ 6 dB at 25.6 GHz. The lowest in sertion loss is ~ 3.3 dB at 30 GHz, which is higher than the target frequency of 25.6 GHz. Return loss of the LNA port 14 16 18 20 22 24 26 28 30 -25 -20 -15 -10 -5 0 Frequency (GHz)(dB) ANT port, |S11| ANT-PA, |S21| PA port, |S22| TX band -3.3 dB (15.6 GHz) -3 dB (16.8 GHz) -3.2 dB (18 GHz)

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68 Figure 4-21. Plots of inserti on loss and return loss between antenna (ANT) port and LNA port. (RX band: 24.2-27 GHz) and antenna port are all around 10 dB within th e desired band (from 24.2 GHz to 27 GHz). The insertion loss performance meets the specifica tion except the frequency needs to be re-tuned from 30 GHz to 25.6 GHz. PA output power is usually much larger than the received power at LNA port. Hence, the isolation between PA and LNA ports is importa nt. High transmitted power can not affect LNA operation if the duplexer can pr ovide good isolation between the two ports. As shown in Figure 4-22, the rejection is ~ 23 dB at ~ 16.8 GHz a nd 25.6 GHz. It is smaller than the 30-dB target. By more precisely modeling the interconnect ion parasitics betw een on-chip passive components, the newly designed duplexer has better insertion loss performa nce at both TX and 23 24 25 26 27 28 29 30 31 32 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 Frequency (GHz)(dB) ANT port, |S11| ANT-LNA, |S21| LNA port, |S22| RX band -4.6 dB (27 GHz) -5.77 dB (25.6 GHz) -8.04 dB (24.2 GHz) -3.3 dB (30 GHz)

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69 Figure 4-22. Measured insertion lo ss between PA port and LNA port. RX bands. Especially, the insertion loss gets impr oved by 3 dB (improve from 6 dB to 3 dB) at TX band compared with the first design. The is olation between LNA and PA ports shows 5-dB degradation (degrade from 28 dB to 23 dB). Th e key factor improving th e insertion loss is to arrange passive components close to each other, which leads to shorter interconnects (smaller parasitics). The compact design not only improves the insertion lo ss performance, but also saves the chip area. 4.4.2 24-GHz Phase-Locked Loop (PLL) Figure 4-23 shows a die micrograph of the integer-N PLL. Its area is 1.2 by 0.6 mm2. Figure 4-24 shows a block diagram of the integer-N PLL [66]. It consists of an LC-VCO, a 256 14 16 18 20 22 24 26 28 30 -35 -30 -25 -20 -15 -10 (dB) RX band TX band -16.73 dB -29.21 dB -23.78 dB -23 dB Frequency (GHz)

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70 prescaler, a phase frequency detector (PFD), a ch arge pump, and a thirdorder passive loop filter. The output frequency is from 23.5 GHz to 24.5 GHz at digital tuning bits of 111. The measured PLL output spectrum is show n in Figure 4-25. Figure 4-26 shows the measured phase noise at PLL out put frequency of 24.01 GHz. The in -band noise at 50-kHz offset is -76.75 dBc/Hz. The phase noise at 1-MHz offs et is -93.55 dBc/Hz a nd the out-of-band phase noise at 10-MHz offset is -114.03 dBc/Hz. Th e output spectrum was measured when the reference frequency is 93.75 MHz. Figure 4-23. Micrograph of the integer-N PLL. Figure 4-24. Integer-N PLL block diagram. PFD Charge Pump Prescaler ( ) VCO Output buffe r VCO buffe r Prescaler buffe r Reference buffe r Reference 93.75 MHz PLL Output 24 GHz Loo p Filte r 1.2mm 0.6 mm

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71 Figure 4-25. Measured PLL output spectrum (Span=1 MHz, RBW=3 kHz, VBW=100 Hz). Figure 4-26. The PLL phase noise plot measur ed using an Agilent E4448A spectrum analyzer. (dBm) Frequency (GHz) 23.999824.000024.0003 23.999524.0005 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -60 -5

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72 4.4.3 4-mm On-Chip Dipole Antenna Figure 4-27 shows the 4-mm dipole antenna input impedance measurement results. Figure 4-27(a) shows |S11|. Figure 4-27(b) shows the real pa rt and imaginary part of input impedance. The imaginary part approaches zero at around 16.9 GHz and the real part is about 220 It means the 4-mm on-chip dipole antenna is resonant at the desi red frequency band and well suited for use at 16.8 GHz. If the measured impedance is used for the duplexer simulation instead of using 50-port impedance, the insertion loss between the PA and ANT ports and LNA to ANT ports degrade by less than 1 dB. Th e design for conjugate ma tching network at the interfaces requires more inductors and capacito rs. It turns out that the matching network introduces more loss, while consuming a larger die area. Therefor e, the duplexer is designed and implemented assuming a 50system. 4.4.4 Multi-Level Power Amplifier Figure 4-28 shows the large si gnal measurement setup for frequency and time domains characterization. For frequency domain measuremen ts, the output is connected to a power meter with a HP8485A power sensor. For the time domain measurement, the output is connected to an Agilent 86100B wide bandwidth oscilloscope. In order to characterize the time domain response of the multi-level PA, an on-chip divide-by-32 block is built-in to generate low frequency divided signal for oscilloscope tr iggering. The address decoders inputs are fed from a Tektronix HFS 9009 Stimulus System, which can provide 4 synchronized signals up to 400 MHz. The clock is 400 MHz and the fre quency of inputs for the addr ess decoder is 200 MHz. At 1.5-V supply for the driver stages and 1.2-V supply fo r the PA stage, Figure 4-29 shows the single-ended PA is able to achieve 10-dBm saturated power and ~ 22% PAE at 16.8 GHz while drawing 30.5 mA and co nsuming 45.75 mW. The output P1dB (OP1dB) is ~7.5 dBm,

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73 Figure 4-27(a). |S11| for 4-mm on-chip dipole antenna. Figure 4-27(b). Input impedan ce for 4-mm on-chip dipole antenna. 10 12 14 16 18 20 -20 -15 -10 -5 0 |S11| (dB) Frequency (GHz) 10 12 14 16 18 20 -150 -100 -50 0 50 100 150 200 250 Frequency (GHz) ( ) real part imaginary part

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74 Figure 4-28. PA measurement setup for frequency domain and time domain. Figure 4-29. Output power vs. input power at VDD=1.5 V for the driver stages and 1.2-V supply for the PA stage. which corresponds to ~ 10.5-dBm OP1dB for a differential PA structure. The idea is to use the linear portion below OP1dB point for multi-level amplitude modulation. Figure 4-29 shows that it is po ssible to provide enough linear power and lead to ~ 21-dB link margin based on the CDMA system analysis, shown in Table 1-1. The link margin analysis is for a fully differential transmitter structure, and receiver noise figure of 8 dB and sensitivity of -74.3 dBm. -15 -10 -5 0 5 10 15 -45 -40 -35 -30-25-20-15-10 -5 0 5 Pin (dBm)Pout (dBm) Linear portion Agilent 8254A DUT Agilent 86100B HP 8485A HP 437B Power sensor Power meter Oscilloscope or DC supply Tektronix HFS 9009 Stimulus System

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75 By applying constant DC inputs to the address decoder, static level test can be performed. Figure 4-30(a) shows the static ti me domain measurement results for level 0 and level 6. Level 2 to level 5 measurement results are summarized in Table 4-7. After de -embedding the probe and cable loss, the corresponding output power for leve l 6 is ~7 dBm, which means the single-ended PA operates close to the OP1dB point This is consistent with the original design. Figure 4-30(b) is the dynamic measurement results of a randomly chosen pattern (0241353246). The inputs and clock for the address decoder are generated fr om a Tektronix HFS 9009 Stimulus System. The rise and fall time of the 3 inputs and clock are set to be 200 ps, which is lim ited by the equipment. There are built-in inverter buffer chains for re-s haping the input waveform to be more square. Each level has ~ 2.5-ns period, which corre sponds to the 400-Mbps data rate. Table 4-7 summarizes the measurement results of level ratio be tween level N (N=6, 5, 4, 3, 2) and level 1, and error percentage compared with the original specification. The maximu m error percentage is ~ 16 % for the case level 3 to level 1. From th e measurements, the worst rise time is ~ 800 ps from level 0 to level 2, which is consistent with the result of circuit analysis mentioned in section 4.2. If the bias resistor at the gate of second pre-amplifier stage decreases to 2.5 k, the rise time Table 4-7. Measurement results summary of static case. Vpeak (mV) Power (dBm) Level 0 31.01 -20.17 Level 1 268.23 -1.43 Level 2 331.51 0.41 Level 3 390.39 1.83 Level 4 478.63 3.6 Level 5 577.43 5.23 Level 6 692.63 6.81 Ideal ratio Measured ratio results Error (%) Level 2 / Level 1 2 1.24 -12.30 Level 3 / Level 1 3 1.45 -16.00 Level 4 / Level 1 4 1.79 -10.75 Level 5 / Level 1 5 2.15 -3.85 Level 6 / Level 1 6 2.58 5.3

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76 Figure 4-30(a). Static time do main measurement results for leve l 0 and level 6 operating at 16.8 GHz. Figure 4-30(b). Dynamic time domain measurement results for pattern 0241353246. (level 0 to level 2) can be improved to ~ 400 ps according to simulations. Other rise and fall times are all around 200 ps. Figure 4-31 shows the die micrograph. The differential class-E PA with an address decoder occupies ~ 1.37 mm2 including pads. Level 6 (V pp =648 mV) Level 0 (V pp =29 mV) 5 n s 85 m V 2 4 0 1 3 5 3 2 4 6

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77 Figure 4-31. Die micrograph of the differential mu lti-level power amplifier. Chip size is 1.14 mm x 1.2 mm. 4.4.5 CDMA Transmitter Chain A standalone coder, and the second one inte grated with a full tran smitter chain [45] are fabricated. To reduce the die area, these two code rs share the same input, clock, and reset pads. The output of the standalone code r test structure is connected to its own output pads. The one integrated with TX chain is connected to the attenuator switches to provide the control signals. By inserting a simple bidirectional 3-bit bus be tween the adder and the d ecoder, shown in Figure 4-32, it is possible to apply input signals directly from an exte rnal signal generator and bypass the coder core blocks [45]. This provides flexibi lity for testing. The inte rnal node, like the adder outputs can also be monitored th rough the 3-bit bus. This is critical for debugging the CDMA TX chain. Table 4-8 shows the control signal se tup of the 3-bit bus. The coder occupies 336 m2. The TX chain testing is done on a PCB. Th e design considerations for the TX PCB are described in Appendix B.

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78 Figure 4-32. Bidirectional 3-b it bus design between the adder a nd the decoder. The read-out path is turned on when the RD is 1, while the write-in path is turned on when the RD is 0. Table 4-8. Bidirectional 3-bit bus settings for different tests. RD_SLRD_TX Standalone: Read Out 1 0 Standalone: Write In 0 0 Coder with TX: Read Out0 1 Coder with TX: Write In 0 0 Figure 4-33 shows the die micrograph and th e PCB used in the transmitter chain measurements. The TX chain measurement was made by applying an external 24-GHz source due to the insufficient drivabi lity at the interface between the PLL output and following divideby-2 block. The buffer stages at th is interface have to be re-tuned in the next tapeout. The tested blocks are shown in Figure 4-34. The dotted bloc k, PLL, is bypassed. As mentioned in section 4.1, the 24-GHz signal is frequency divided down to 12 GHz and 4.8 GHz to generate the IF and

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79 Figure 4-33. Micrograph of the CDMA TX chain and the PCB. Figure 4-34. CDMA TX chain block diagram. Th e measurement was done using an external 24GHz source due to the insufficient drivab ility at the interf ace between the PLL output and following di vide-by-2 block. On-chip Antenna Multi-level CDMA co n t r o l s i g n a lIF Power Amplifier Duplex Filter PLL (24-GHz) Digital Coder 12 GHz 4.8 GHz Pre amplifier Attenuator LO 2 5 2 16.8 GHz

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80 LO inputs of the mixer. During the frequency di vision, unwanted harmonics are also generated, which show up at the TX output. For example, due to the inverter buffers at the output of divideby-5 block, the odd-order harmonics of 2.4 GHz would be produced, like that at 7.2 GHz. Even order harmonics are also generate d because the duty cycle is not 50 % at the divide-by-5 output (mentioned in section 4.2.4). All the harmonics will be up-converted with the 12-GHz LO signal. Therefore, lots of unwanted harmonics can be ob served at the PA output, shown in Figure 4-35. By observing the harmonic frequencies at the TX output, it is possible to infer that the divider chains and the mixer stage are properly functional. For example, the 12-GHz signal is generated from the divide-by-2 block and amplified by the LO buffers. The signal can couple through the other circuit blocks or ground plane and show up at the TX output. If the 12-GHz signal is shown at the TX output, that means the divide-by-2 circu it and LO buffers are operational. Based on this approach, multiply-by2, divide-by-5, and mixer stages are all functional. Therefore, correct harmonic frequencies can be seen in the TX output spectrum (Figure 4-35). The TX band is from 15.6 to 18 GHz. The highest and closest unwanted signal is at 19.2 GHz, which comes from the 12-GHz LO mixing with the 7.2-GHz harmonic. The difference between the desired 16.8-GHz signal and 19.2-GHz unwanted interferer is ~ 10 dB, which is measured at duplexer output without the on-chip antenna connected. Since the antenna is tuned for use in 16.8 GHz, the 19.2-GHz interfe rer should be attenuated by 0.5 dB more due to the 4-mm on-chip dipole antenna There are two small peaks besides the 16.8 and 19.2 GHz peaks. Those peaks are 400 MHz away from the ma in peaks. It comes from the leakage of the 400-MHz clock for the coder. In order to verify the effect of the unwant ed 19.2-GHz signal, the system simulation of the CDMA transceiver is perfor med in Advanced Design System (ADS) simulator. Figure 4-

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81 Figure 4-35. Output spectrum at duplexer ou tput without multi-level amplitude modulation. 36(a) shows the block diagram for the CDMA TRX simulation and the spectrum at the TX output. It includes a desired 16.8GHz carrier and an unwanted 19.2GHz interferer (10 dB lower than the 16.8-GHz signal) with data modulated. The simulation re sults in Figure 4-36(b) show that the base band output of the CDMA receiver is the same for two cases (pure 16.8-GHz carrier at TX output; a 16.8-GHz carrier with an unwante d 19.2-GHz interferer). This implies that the effect from the 19.2-GHz in terferer is tolerable. 5.010.015.020.0 0.0 25.0 -65 -45 -25 -5 -85 10 Frequency (GHz)Output (dBm) 16.8 GHz 14.4 GHz 12 GHz 9.6 GHz 7.2 GHz 19.2 GHz 21.6 GHz 24 GHz 4.8 GHz IF PLL 2 2 24-GHz 12GHz 5 LO 12-GHz 2.4-GHz 2.4-GHz, 4.8-GHz, 7.2-GHz, 9.6-GHz 4.8-GHz (desired), 7.2-GHz, 9.6-GHz 2.4-GHz, 4.8-GHz, 7.2-GHz, 9.6-GHz, 12-GHz, 14.4-GHz, 16.8-GHz (desired), 19.2-GHz, 21.6-GHz 24-GHz

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82 Figure 4-36(a). The CDMA TRX simulation bloc k diagram and the spectrum at the TX output. Figure 4-36(b). The base band output of th e CDMA receiver for two cases (pure 16.8-GHz carrier at TX output; a 16.8-GHz carrier with an unwanted 19.2-GHz interferer). TX Channel loss RX Base band output 16.8 GHz + 19.2 GHz Frequency (GHz) (dBm) 16171819 1520 -30 -80 20 16.8 GHz 19.2 GHz 10 dB 20406080 0 100 0.05 0.10 0.15 0.20 0.00 0.25 Time ( s ) (V) 20406080 0 100 0.05 0.10 0.15 0.20 0.00 0.25 Time ( s ) (V) ( Pure 16.8-GHz carrier ) (16.8-GHz carrier + 19.2-GHz interferer)

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83 In the TX chain characterization, the coder integrated with the 3-bit bus design has the option for testing with static levels before th e dynamic measurement. The same method as the PA characterization is used. Constant external DC inputs for the address decoder are applied to check the static level performance with the prope r settings for the 3-bit bus. The differential measurement results at duplexer output are summa rized in Table 4-9. The level 6 is ~ 3.5 dBm, which is lower than the individual PA measurement result. This is probably due to the fact that input power is lower than expect ed at the input of first pre-am plifier. The similar results are observed in the PA standalone measurement if sm aller input power is applied. The lower power and level ratio errors can be corrected by ch anging the attenuator sizes and re-tuning the interface at the mixer output a nd first pre-amplifier stage. When the transmitter successfully operates with the digital coder, multi-level signals can be generated at the duplexer out put. The measurement setup for the time domain measurement is the same as the one mentioned in Figure 4-28. The spectrum analyzer are used for the frequency domain measurements. Once again, in order to monitor the time domain multilevel signals, the on-chip built-in divide-by-32 block generates low frequency triggering signals (525 MHz). Table 4-9. TX static measurement results at th e duplexer output (cable and external balun loss are 4 dB). Power (using S.A.) (dBm) Add back ~ 4 dB (dBm) Vpeak (mV) L0 -39.5 -35.5 5.3 L1 -13.5 -9.5 105.9 L2 -12.0 -9.0 112.2 L3 -11.0 -7.0 141.3 L4 -9.5 -5.5 167.9 L5 -7.0 -3.0 223.9 L6 -0.5 3.5 473.2 Ideal ratio Measured ratio results Error (%) Level 2 / Level 1 2 4.47 OFF Level 3 / Level 1 3 2.11 -5.6 Level 4 / Level 1 4 1.59 -20.5 Level 5 / Level 1 5 1.33 -23.2 Level 6 / Level 1 6 1.06 -25.0

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84 Incidentally, for proper triggering, a periodic waveform is needed. Constant inputs to the digital coder are applied and XNORed with the output fr om the Walsh Code generator. Therefore, a periodic multi-level waveform is generated at the transmitter output. Figure 4-37(a) shows the differential time domain measurement results when the digital coder inputs are 111111. This corresponds to the dynamic output, 62333322. The out put is AC-coupled. The waveform shown in Figure 4-37(a) is symmetrical with respect to the time axis. Alt hough, there are lots of harmonics as described in Figure 4-35, the prope r multi-level signal can still be triggered using the on-chip generated triggering signal. Each level has a 2.5-ns data period with 16.8-GHz carrier. The diode detection rece iver will pick up the negative portion of waveforms and the 400Mbps data will be fed into an ADC for de-modulating. The corresponding output spectrum for the same case (constant coder inputs = 111111) is shown in Figure 4-37(b). There are lots of harmonics with modulating data coming with every harmonic peak, which can be clearly seen in the output spectrum. From the measurements, the spr eading effect is clearly observed. In the plot, the average power is captured. Different coder inputs are also applied. Figure 4-38(a)-(b) shows the time domain and frequency domain measurements when the digital coder inputs are 000001. This corresponds to the dynamic output, 13424253. Figure 4-39(a)-(b) shows the time domain and frequency domain measurements when the digita l coder inputs are 111000. This corresponds to the dynamic output, 33440433. For all the dynamic measurements, the cl ock frequency of the digital coder is 400 MHz, which is the original specification. The c oder is fully functional and can be operated at the full rate. All the 7 levels can be recognized in Figure 4-37, 4-38, and 4-39. Especially, the level 0 is close to zero as expected. That means the self oscillation of the last PA stage can be effectively

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85 Figure 4-37(a). Time domain measurement wh en the digital coder inputs are 111111, which corresponds to the dynamic output, 62333322. Figure 4-37(b). Frequency domain measuremen t when the digital coder inputs are 111111, which corresponds to the dynamic output, 62333322. 6 2 33 33 2 2 Coder CLK=400 MHz 5.010.015.020.0 0.025.0 -80 -60 -40 -20 -100 0 Fre q uenc y ( GHz ) Out p ut ( dBm ) 9.5 dB

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86 Figure 4-38(a). Time domain measurement wh en the digital coder inputs are 000001, which corresponds to the dynamic output, 13424253. Figure 4-38(b). Frequency domain measuremen t when the digital coder inputs are 000001, which corresponds to the dynamic output, 13424253. Coder CLK=400 MHz 1 3 44 22 5 3 5.010.015.020.0 0.0 25.0 -80 -60 -40 -20 1 00 0 Fre q uenc y ( GHz ) Out p ut ( dBm ) 9.5 dB

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87 Figure 4-39(a). Time domain measurement wh en the digital coder inputs are 111000, which corresponds to the dynamic output, 3344043. Figure 4-39(b). Frequency domain measuremen t when the digital coder inputs are 111000, which corresponds to the dynamic output, 3344043. Coder CLK=400 MHz 3 3 4 0 4 4 3 3 5.010.015.020.0 0.025.0 -80 -60 -40 -20 -100 0 Fre q uenc y ( GHz ) Out p ut ( dBm ) 9.2 dB

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88 Table 4-10. Power consumption of TX blocks. Component Power Consumption Performance PLL 26.75 mW Generating 24 GHz signal. Locking range: 23.5 24.5 GHz (digital tuning bits 111) At 50-kHz, phase noise is -76.75 dBc/Hz. At 1-MHz, phase noise is -93.55 dBc/Hz. At 10-MHz, phase noise is -114.03 dBc/Hz. Mixer 6.03 mW Working fine. LO buffer 13.81 mW Working fine. PLL output buffer + Divider chain (outside PLL) + Multiply-by-2 + IF buffer 56.41 mW Working fine except PLL output buffer has to be re-tuned to provide bigger drivability for the following divide-by-2 block. Pre-drivers (differential) 64.24 mW PA (differential) 29.64 mW At PA output, it can successfully generate 7 multi-level signals when coder clock is 400 MHz. Coder 1 mW Working fine. Total Power Consumption 197.88 mW suppressed. The CDMA TX chai n can support 7 signal levels w ith a 16.8-GHz carrier and at 400-Mbps data rate. It occupies ~ 5.2 mm2 and consumes 198 mW. Table 4-10 summarizes the power consumption of every block. Small modifi cations are needed to improve the TX chain overall performance. First, the PLL output buffe rs have to be re-tuned. Second, the interface between the mixer output and the input of first pre-amplifier has to be re-tuned. Finally, attenuator sizes need to be re-sized. Higher output power is expected after decreasing the attenuator sizes. 4.5 Summary In this chapter, wireless interconnects concept is described. The simulation and measurement results of TX chain are presented. The CMOS PA with a dig ital coder can be used to implement multi-level ASK modulation at 400 Mbps The PLL can successfully generate a 24-GHz carrier with reasonable phase noise performance. The re ference 24-GHz signal from the PLL is divided down to 12 GHz and 4.8 GHz and up-converted to generate the 16.8-GHz carrier.

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89 The measurement results of the single-ended PA i ndicate that it is feasible to provide sufficient linear power at 16.8 GHz. By using the linear por tion of the class E PA, higher efficiency and lower power consumption can be achieved. The d uplexer achieves ~ 3-dB insertion loss at 16.8 GHz, which already satisfies the specification. Th e return loss of PA port and antenna port are below 10 dB within the desired band (from 15. 6 GHz to 18 GHz). The rejection between LNA and PA ports is ~ 23 dB at ~ 16.8 GHz and 25.6 GHz, which is smaller than the 30-dB target but should be still acceptable. The CDMA TX chain is fully functional except th e drivability issue at the interface between the PLL output and divide-by-2 block. It can support 7 signal levels with a 16.8-GHz carrier. Some modifications are needed to improve the TX chain overall performance in a future tapeout.

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90 CHAPTER 5 BOND WIRE ANTENNA DESIGN 5.1 Introduction The demand for ever increasing functionality of ICs has been met by reducing the sizes of electronic devices and interconn ections between them [70]. By having smaller and more advanced devices, circuits opera ting at higher frequencies can be realized. However, it requires corresponding improved technology for packaging. More and more off-chip connections are needed to satisfy the increased demand for func tionality [71], which ma kes the chip-on-board (COB) package for ICs more challenging. But COB package is still a pref erred choice due to its robustness and low cost. It also better tolerates die thermal expansion and placement uncertainty [72]. Lots of efforts have been made to predic t and analyze inductance of bond wires [73]-[75]. The parasitic inductance of bond wires is likely to affect circuit tuning network and significantly affect overall circuit performance. Therefore, other advanced packaging techniques, such as BGA and Flip Chip, are being used [76], [77]. Ho wever, in terms of the cost point of view, packages using bond wires are sti ll the cheapest. This is the motivation for developing other possible ways to achieve low cost, reasonable performance and mitigate parasitic effects. As discussed in Chapter 1, at millimeter wave fr equencies, typical bond wire lengths approach a wavelength and a bond wire is expected to be a reasonable radiator, whic h could be used for inter-chip data communications. Figure 5-1 shows a cross-section of a Multi-Chip Module (MCM) package. It shows 2 chips mounted on th e same substrate and both having bond wire connections to a PCB. Use of bond wire antennas for wireless inter-chip data communications or general purpose wireless communi cations may be possible.

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91 Figure 5-1. Multi-Chip Module package cross-sectional view. As discussed in Chapter 3, the propagation me dium is a parallel-plate waveguide, which is formed by the top metal layer of PCB and an alumin um metal cover which repr esents a part of an electronic system enclosure. A lthough on-chip dipole antennas ha ve been extensively studied [5]-[7] in various environment, the radiation performance should be re-evalu ated in this parallelplate waveguide system. The other choice is to use slot antennas, which can also be fabricated on chip. But both of them as shown in Figure 5-2 ideally have E-field on the x-y plane and have weak vertical E-field [78], which is not optimal for use in a narrow-gap parallel-plate waveguide. Therefore, a bond wire acting like a monopole may be better because of higher vertical E-field. A bus interconnected with wireless links, in which multiple sets of devices/chips on a PCB can simultaneously communicate and control sign als can be broadcasted to multiple devices is proposed. The 60-GHz ISM band is a good choice because of its large available bandwidth, which is beneficial for high data rate comm unication at multi-giga bits per second (Gbps). Frequency division multiple access (FDMA) can be used to replace multiple I/Os by a transmitter or a receiver with one antenna. As shown in Figure 5-3, this should lead to area reduction and lower cost. This chapter shows that when the bond wire le ngth is properly (~1mm) chosen, it should be well suited for implementing antennas operating around 60 GHz. In fact, the measurements Au wire Si chip Si chip via PCB wireless link Metal cover (a part of the system enclosure) PCB top metal layer PCB bottom metal layer

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92 Figure 5-2. On-chip dipole an tenna vs. slot antenna. The E-fi elds are both on x-y plane. Figure 5-3. Frequency divisi on multiple access (FDMA) is used to replace M I/Os by a transmitter or a receiver with one antenna to lower the I/O pin count. show that bond wire antennas in the presence of a metal cover (2-mm gap to the PCB) should be sufficient for building a 1-Gbps radio link operating near 60 GHz with BER (Bit error rate) of 10-12 and 10-cm range. A potential problem with bond wire antennas is the length variation (~ E E Dipole antenna Slot antenna x y z Metal Metal Silicon substrate Silicon substrate

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93 +/ 50 m) during manufacture, which causes match and e fficiency to vary. The impact of this is bounded. The details of measurement setup and m easurement results as well as discussion are presented in sections 5.2 and 5.3. 5.2 Measurement Setup, Test chips, and Test Boards As shown in Figure 5-4, an antenna consis ts of a bond wire, a bond pad on a chip, and a bond pad on a PCB. The bond pads anchor a bond wire The location of bond pad is a key factor determining the length of bond wire; hence, the characteristics of bond wir e antennas. At 60 GHz, a wavelength ( ) is 5 mm in free space. The target bond wire length of 720 m is only 0.144 and the antenna is expected to behave lik e a short monopole, which ideally has 4.77-dBi directivity [78]. The parasitic capacitance and resistance associated with the bond pads also are critical factors determining the matching and resonant be havior of antennas. In order to increase the distance between the top metal layer and on-ch ip ground shield, thus lowering the parasitic capacitance of bond pad, a gr ound shield is formed with the poly silicon layer instead of the metal 1 layer. The separation between the top metal layer and polys ilicon ground shield is 3.5 m. On the PCB side, the distance between the top and bottom metal layers is ~ 500 m. Therefore, the parasitic capacitance of bond pad in PCB is ~ 80X smaller than that of an on-chip bond pad. These as mentioned make the antenna behave like a monopole. The measurement setup in Figure 5-5 include s a signal generator, cable connections, GSG and GS probes, a harmonic mixer (50-75 GHz), a high power amplifier (55-65 GHz), and a spectrum analyzer [76]. The mixer, power amplifier, and spectrum analyzer can be replaced with a network analyzer for 2-port S-parameter meas urements. Using these, antenna pair gain, Ga defined in Eq. (3-1) is measured. The antenna pair gain accounts fo r the input impedance

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94 Figure 5-4. (a) Gold bond wire co-designs w ith an on-chip bond pad and a floating bond pad on the PCB. (b) Photograph showing the side view of the silicon chip and a gold bond wire. The estimated bond wire length is around 870 m. mismatch, gain of individual antenna and propagation loss. Three types of test structures have been fabricated for the antenna pair gain measurement, antenna pattern measurement, and studying the effects of adjacent bond wires on antenna performance. Figure 5-6(a) shows a bond wire antenna test structure, a PCB and the corresponding HFSS simulation structure. The se parations between transmitting and receiving antennas on the PCB are 1, 2, 4, 8, and 10 cm. Th e width of a gold-plated plane on the PCB is 1 cm. In order to characterize the bond wire antennas, a chip with 60 x 100 m2 pads shown in Figure 5-6(b) is also fabricated. All the test structures are fabricated in the AMI 0.6-m CMOS process using 0.007--cm substrates with an 18--cm epitaxial layer with 3 metal layers. The total dielectric thickness (the top metal layer to substrate) is 3.8 m. A ball bond only occupies two-thirds of th e bond pad area. The other one-third of bond pad is reserved for landing a high frequency probe, which is critical for good contact and simplification of de-embedding. Th e target bond wire length is 720 m (bonded to a ~ 100 x 100 Floatin g bond p ad ( PCB side ) Bond p ad ( chi p side ) A u wire Si chi p 250 m Sichi p A u wire ( a ) ( b )

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95 Figure 5-5. Antenna measurement setup. A ball bond only occupies tw o-third of the bond pad area. GSG and GS probes are landed on the area not occupied by the ball bond. (HPA: High power amplifier) Figure 5-6(a). Side view of a bond wire antenna and photographs of test chip and PCB. The bond wire length is ~ 720 m. The chip thickness is ~ 250 m. Each antenna pair has 1-cm wide gold-plated metal trace on the PCB between transmitting and receiving antennas.

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96 Figure 5-6(b). Bond pad design. Two-thirds of the bond pad area is for ball bonding and onethird is for probe landing. Figure 5-7. Antenna PCB with and without a cover. w/o cover with cover Au wire Si chip via PCB Metal cover (a part of a system enclosure) PCB top metal layer ~ 2 mm w/ cover (cross-sectional view) 1 cm Chip side: Bond pad : 60 m x100 m PCB side: Bond pad : 100 m x100 m 60 m x 40 m probe landing area 60 m x 60 m Bonding area 60 m 100 m 1/3 2/3

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97 m2 floating pad on the PCB), which re sonates with an on-chip 60 x 100 m2 bond pad at ~ 60 GHz. FR4 is used for board fabrication because of its low cost and wide availability. The high frequency wave penetrating into FR4 is a concer n because of its loss. However, a large metal ground plane usually present on PCBs mitigates this problem. As mentioned earlier, the thickness of FR4 board is ~ 500 m. Together with an aluminum metal cover, they form a parallel-plate waveguide channel, shown in Figure 5-7. In real applicatio ns, the aluminum metal cover will be replaced by an enclosure for electronic systems. Two bond wires are used to connect the PCB ground and on-ch ip ground. There is also an option to have more ground bond wires to lower the parasitic inductance. Figure 5-8(a) shows the PCB fo r antenna radiation pattern measurement. The board has a 2-cm radius semicircle with 9 measurement poi nts at varying angles. The transmitting bond wire antenna is at the origin of semicircle. In order to reduce the eff ects from the surrounding environment during the pattern measurements, a m obile setup [79], shown in Figure 5-8(b), was placed in a ~ 7 m x 7 m room instead of us ing a shielded cage to emulate open space. Figure 5-9 shows the PCB and chip for st udying the effects of adjacent bond wires on antenna performance. The chip is the same as the one used in Figure 5-6. But there are two floating bond wires intenti onally designed to sit 300-m away from the center bond wire antenna. These are intended to emulate close by bond wires that are inevitable. The bond wire may not necessary to be used as an antenna but it may be used for DC supply or ground connections. The structure is used to characteri ze how floating wires can degrade antenna characteristic. It is critical to quantify this in advance during the step of system design. For instance, higher PA output power will be needed to compensate the loss in the transmitter design. The measurement results are shown in section 5.3.

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98 Figure 5-8(a). Test PCB for an tenna pattern measurements. It has 9 measurement points on a 2cm radius semicircle. The transmitting bond wire antenna is at the origin of semicircle. Figure 5-8(b). Mobile setup fo r antenna pattern measurement. 5.3 Measurement Results and Discussions Input reflection coefficient, |S11| of bond wire antennas is a critical performance parameter. Figure 5-10 shows that the bond wire antennas resonate at ~ 55 GHz. The tuned Mobile probe chunk probe Signal input

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99 Figure 5-9. Test PCB and chips for bond wire an tenna investigation of the effects of adjacent bond wires on antenna performance. There are two floating bond wires adjacent to the antenna. (The separation between the floating bond wire and the bond wire antenna is 300 m.) response can be adjusted by controlling the bond wire length. Lengthening tunes down the resonant frequency because of larger inductan ce. For frequencies between 55 to 64 GHz (~ 9 GHz), |S11| is less than 4 dB. At |S11| of dB, ~ 60 % of incident power is delivered to the antenna for radiation. The corresponding mismatch power loss is ~ 2.2 dB. The tuned response can also be adjusted by varying the bond pad size. Figure 5-11(a) shows the HFSS simulation result s of tuned response sh ift due to the bond wire length variation of +/150 m around 720 m. As the bond wire length increases by 150 m, the tuned frequency lowers to 56 GHz co rresponding to that for the measurement results shown in Figure 5-12(a). The bond wi re diameter is set to be 16 m in the simulation. As the bond wire length decreases by 150 m, the tuned frequenc y stays around 61 GHz. The bandwidth also becomes broader. This may be due to the fact that the antenna is becoming

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100 Figure 5-10. |S11| of bond wire antennas. shorter, and |S11|s move away from the center of smith chart as shown in Figure 5-11(b). The capacitive tuned response implies that the reduced inductance of a shorter bond wire can not completely tune out the pad capacitance. A longer bond wire length and thinner bond wire diameter make the input impedance more inductive in the smith chart as the arrow shown in the plot indicates. In orde r to match the variation in Figure 5-10, the bond wire length must vary from 720 to 890 m. This is significantly larger than that specified by the assembly company. A photograph of side view of a bond wire is shown in Figure 5-4(b). The estimated bond wire length is ~ 870 m, which is consistent with th e 56-GHz resonant frequency. The simulation and measurement results in Figure 5-12(a) have the same resonant frequency. Despite the larger bond wire length variation than the +/50 m specification by the assembly companies, 52 54 56 58 60 62 64 -30 -25 -20 -15 -10 -5 0 Frequency (GHz)|S11| (dB) Antenna 1 Antenna 2 Antenna 3 Antenna 4 Antenna 5 Antenna 6 Antenna 7 Antenna 8 Antenna 9 Antenna 10

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101 bond wire antennas could be practical for the use in the 57-64 GHz band a pplications if the 2.2dB mismatch loss can be tolerated. When th e bond wire length are controlled within +/50 m as specified by the assembly houses, the tune d frequency is expected to be 58-61 GHz as suggested by the simulated plots in Figure 512(b). The corresponding mismatch loss is below 0.4 dB. To further reduce the mismatch loss and increase the antenna bandwidth, a varactor may be added in parallel with the on-chip bond pad to adju st the frequency tuning. Figure 5-13 shows the antenna pair gains (Ga) versus separation at 55 GHz. The loss in the measurement setup is measured using a thru structure on a calibration s ubstrate, and is used to de-embed the loss of antenna measurement se tup [80]. The figure shows the computed path loss based on the Friis formula [81] and measur ed antenna pair gain with and without an aluminum cover. The gap between the alumin um cover and PCB was 2 mm. Such a gap is relevant for systems with a form factor similar to that of PCMCIA and some wireless local area network cards. For the case without a cover, Ga of the bond wire antenna pair is around 6 to 8 dB lower than the computed path loss for separati ons between 1 and 4 cm. This suggests that the gain of bond wire antenna is ~ -3 to -4 dBi. Th is is especially outstan ding considering the fact that the bond pads are fabricated on a low resistivity substrate (0.007--cm).For the case with a cover, the waves are guided and the loss is lowe r as expected. At antenna separations greater than 4 cm, Ga for the case with a cover is at least 10 dB higher than that without. At 10 cm separation, Ga for the case with a cover is -41 dB. The Friis formula used in Figure 5-13 is given by 24 R GG P Prt t r (5-1) where (/4R)2 is the path loss.

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102 Figure 5-11(a). Simulated |S11| of bond wire antennas with +/150-m length variation (HFSS). Figure 5-11(b). Simulated |S11| of bond wire antennas with +/150-m length variation (HFSS) in a smith chart. A longer bond wire le ngth and thinner bond wire diameter make the impedance more inductive. Inductive L=570 m ( D=16 m ) xL=720 m ( D=16 m ) L=870 m ( D=16 m ) ( D: bond wire diameter ) ( L: bond wire len g th ) o L=870 m ( D=25 m ) Measurement result 54 56 58 60 62 64 -30 -25 -20 -15 -10 -5 0 Frequency (GHz)|S11| (dB) Variation = +150 m Target length = ~720 m Variation = -150 m

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103 Figure 5-12(a). |S11| of the 870-m bond wire antenna: HFSS simulated |S11| vs. measurements. Figure 5-12(b). |S11| of bond wire antennas with +/50-m length variation (HFSS simulation results). 54 56 58 60 62 64 -30 -25 -20 -15 -10 -5 0 |S11| (dB) Variation= +50 m Target length=~720m Variation= -50 m 54 56 58 60 62 64 65 -20 -15 -10 -5 |S11| (dB) Measurement result HFSS simulation result Frequency (GHz) Frequency (GHz)

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104 Figure 5-13. Antenna pair gain at 55 GHz, Ga vs. separation (up to 10 cm) plots of with a metal cover, without a metal cover, and calculated path loss from the Friis formula. (cover height: 2 mm from PCB) The characteristic impedance of the parallel waveguide is w d Z0 (5-2) where d is the gap between the top and bo ttom plates, w is the plate width, and is the free space characteristic impedance, 377 [82]. The characteristic impeda nce of parallel waveguide used in the measurement is ~ 75 which is close to the 50input impedance of antenna. If the gap is lowered to 1.33mm, the characteristic im pedance of the waveguide can approach ~ 50 Based on the measurements, the input impeda nce of bond wire antennas shows similar |S11| characteristics for the case with and without an aluminum cover as shown in Figure 5-14. The solid line (with a metal cover) and dotted line (without a metal cover) almost overlap. 1 2 3 4 5 6 7 8 9 10 -60 -55 -50 -45 -40 -35 -30 -25 Distance (cm)Ga (dB) w/o cover w/ cover path loss (computed from Friis formula)

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105 Figure 5-15 shows the HFSS 3-D pattern simu lation results for the case of bond wire length = 870 m at 55 GHz (without a metal cover), which indicates at =40 degree, =60 degree, the bond wire antenna has the highest antenna gain of ~ 0.4 dBi. The effective antenna gain is -3.2 dBi at =90 degree, =90 degree. This is close to the measurement mentioned in the previous paragraph. The radia tion pattern without a cover in Fi gure 5-16 is measured using the PCB in Figure 5-8. The HFSS simulation used the structure shown in Figure 5-4(a), which includes a 720-m bond wire, an on-chip 60 x 100 m2 bond pad, and a 100 x 100 m2 floating pad on the PCB (silicon substrate thickness is 250-m and FR4 PCB thickness is ~ 500 m). Between 60 to 120 degrees, the Ga is almost constant and matches well with the HFSS simulations shown in Figure 5-16. The measured pa ttern shows slight asymmetry. A reason for Figure 5-14. Measured |S11| of bond wire antennas for the case s with and without an aluminum cover. (cover height: 2 mm from PCB) 54 56 58 60 62 64 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 Frequency (GHz)|S11| (dB) No metal cover with a metal cove r

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106 Figure 5-15. HFSS 3-D pattern simulati on results when bond wire length = 870 m at 55 GHz (without a metal cover). Figure 5-16. Radiation pattern (normalized) of a bond wire antenna measured using the PCB in Figure 5-9. The antenna has better Ga performance between 60 to 120. (HFSS simulation results when =90, =0 to 180) -30 -20 -10 0 30 60 90 120 150 1800 -30 -20 -10 0 30 60 90 120 150 1800 HFSS simulation (60 GHz) Measurement ( 60 GHz ) =60 =40

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107 this may be that the transmitting bond wire antenn a is not symmetrically placed with respect to the receiving antenna locations in Figure 5-8(a). In addition, the measured Gas are 10 to 15 dB lower than that of simulations for angular posit ions outside the 60 to 120 degree range. This is probably due to the ground bond wires sitting on the sides of center tr ansmitting antenna shown in Figure 5-8(b). The HFSS simulations incl uding these ground bond wires show ~ 5-dB Ga degradation at 0 and 180 degree compared with that at 90 degree, which are in qualitative agreement with the measurements. Despite these, the antenna should still be useful for wireless interconnect applications. Table 5-1 summarizes the link margin analysis for a 1-Gbps link operating at ~ 60 GHz using a frequency division multiple acce ss (FDMA) scheme with BER of 10-12. When the receiver sensitivity is -60 dBm or receiver noise figure is 10 dB, and the power delivered to the transmitting antenna is 3 dBm, the link margin at 10 cm is 22 dB. The transceiver requirements are modest and the margin is acceptabl e, which indicate that the measured Ga with a metal cover (2-mm gap) at 10 cm separation of ~ dB is adequate. The bond wires adjacent to an antenna degrade the antenna pair gain (Ga). For instance, two floating bond wires located 300 m away from the center bond wire antenna degrade the antenna pair gain at 10-cm separation by 12 dB to -53 dB. The measurement results are shown in Figure 5-18. Ev en if the degradation of Ga is 20 dB, it should be possible to es tablish a communication link. Figure 5-17(a) shows the HFSS simulation st ructure used to study coupling between adjacent bond wire antennas. It includes 2 adja cent bond wires and the separations between them are varied (150, 300, and 600 m). The dominant mechanism is th e near field coupling and the structure can be modeled using circuit elements as shown in Figure 517(b). A distributed inductor model is used to represent the bond wire antenna. A coupling coefficient, k is the mutual

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108 Table 5-1. Link margin analys is using Frequency Division Mu ltiple Access (FDMA) scheme and direct conversion tr ansceiver architecture. Wireless I/O Data Path number 3 Data Rate/Data Path (Gbps) 1 Bit Error Rate (BER) 10-12 Multiple Access Scheme FDMA Duplex Scheme TDD Frequency Channel number 3 Channel Bandwidth (GHz) 2 Channel Spacing (GHz) 3 Carrier Frequencies (GHz) 60, 63, 66 Modulation Scheme DBPSK Wireless Channel Length (cm) 10 Antenna pair gain at 10-cm separation (dB) -41 Noise figure (dB) 10 Receiver Sensitivity (dBm) -60 Transmitter Output Power (dBm) 3 Link Margin (dB) 22 Figure 5-17(a). HFSS simulation structure for a bond wire antenna coupling study. The separations between two bond wires are 150, 300, and 600 m. GND bond wire Bond wire ANT 1 Bond wire ANT 2 X=150, 300, 600 m Si

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109 Figure 5-17(b). Circuit model for the bond wire antenna coupling. A distributed inductor model is used to represent the bond wire antenna. inductive coupling factor. Figure 5-17(c) shows the HFSS and lumped circuit model simulation results of |S11|, |S22|, and |S21| for the 300-m separation case. The bond wi re antenna is tuned at ~ 60 GHz. The |S21| represents the coupling between two bond wire antennas. It increases from 58 to 62 GHz due to an increase of mutual inductive coupling. It st arts to decrease above 62 GHz k k k 6 segments R R RRsubRsub C p ad C p adLsegLsegLsegC2 C2 C1 C C Cpara Cpara Cpara Cpara Cpara Cpara Port1 Port2 C

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110 Figure 5-17(c). HFSS vs. circu it simulation results for the 300-m separation case. The circuit model based simulations show a qualitative agreement with the HFSS simulations. Figure 5-17(d). HFSS simulations of isola tion between bond wire antennas at varying separations. 58 60 62 64 66 68 70 -30 -25 -20 -15 -10 -5 0 Frequency (GHz)(dB) |S11| (HFSS simulation result) |S21| (HFSS simulation result) |S21| (Lumped model simulation result) |S11| (Lumped model simulation result) 0 2 4 6 8 10 12 14 16 0 100 200300400500600700 Separation (m)Isolation (dB) 58 GHz 60 GHz 62 GHz 64 GHz

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111 Figure 5-18. Interference measurement results (cover height 2 mm from PCB) because the parasitic capacitance, Cpad, shunts the port to ground [83] The lumped circuit model qualitatively agrees with the HFSS simulati ons. Figure 5-17(d) show s the HFSS simulated isolation versus different separa tions at various frequencies. Th e simulations indicate that a larger separation improves isolat ion. When the separation is 300 m, the isolation is ~ 6 dB at 60 GHz. If the separation is increased to 600 m, the isolation can be improved to ~ 13 dB. By offsetting the operating frequenc ies for adjacent bond wire antenna s, it should be possible to further improve the isolation. The bond wires adjacent to an antenna can also modify the antenna characteristics. Figure 5-18 shows that there is on the average, ~ 12 dB Ga drop due to the floating bond wires 300-m away for the case with a cover. When this a nd the efficiency degradation due to the match variations are included, Ga is reduced to ~ -53 dB at 10-cm separation, and the link margin for a 55 56 57 58 59 60 61 -60 -50 -40 -30 -20 -10 0 Frequency (GHz)(dB) |S11| for Fig.5-6 2-cm pair |S22| for Fig.5-6 2-cm pair |S11| for Fig.5-9 2-cm pair |S22| for Fig.5-9 2-cm pair Ga for Fig.5-9 2-cm pair w/ cove r Ga for Fig.5-6 2-cm pair w/ cove r

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112 1-Gbps radio link operating at ~ 60 GHz with BER of 10-12 is estimated to be ~ 10 dB, which is still acceptable. 5.4 Summary This chapter demonstrated that a bond wire an tenna is a realistic option for wireless interchip data communication. At 10-cm separation with a metal cover (2 mm gap), antenna pair gain, Ga of dB provides link margin of more than 22 dB for a 1-Gbps radio link operating at ~ 60 GHz with BER of 10-12. Isolation between two adjacent bond wire antennas separated by ~ 300 m is ~ 6 dB. By offsetting the operating frequency of the antennas, isolation can be improved. It should also be possible to use bond wire an tennas for general purpose over the air communication in the 60-GHz unlicensed band.

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113 CHAPTER 6 SUMMARY AND FUTURE WORK 6.1 Summary An electronic isolator using mainstream CMOS technology has been shown to be able to sustain 70 V. However, this is not sufficient for use in a hybrid engine controller board, which needs to handle at least 300-V DC isolation. To support 300 V and higher, wireless interconnects concept has been adopted. On-c hip dipole antenna characteristics have been evaluated in a hybrid engine controller board which is a multi-path rich environment. The antenna pair gain and delay spre ad appear to be acceptable for the application, when a metal cover representing the system enclosure is presen t. The system block diagram of the CDMA TX chain shown in Figure 6-1 has been demonstrated. The PLL can successfully generate a 24-GHz carrier and the duplexer can provide reasonable insertion loss between PA and antenna ports and reasonable isolation between PA and LNA ports at the same time. The 4-mm on-chip dipole antenna is well suited for use at 16.8 GHz. A multi-level PA capable of supporting 7 levels at 400-Mbps data rate is demonstrated. The single-ended PA fabricated in the 130-nm CMOS foundry process can achieve 10-dBm saturated output power with 22% maxi mum PAE while consuming 45.75 mW. A TX chain with a digital coder can also succe ssfully generate 7 signa l levels with a 16.8GHz carrier and 400-Mbps data rate. The whole CDMA transmitter occupies ~ 5.2 mm2 and consumes 198 mW. Some modifica tions are needed to further improve the performance, which are described in section 6.2. Based on the measurements, it should be feasible to realize a CDMA transmitter for wireless interconnects to replace phot o-couplers in the hybrid engine controller board. Lower cost and higher data rate can both be achieved.

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114 Figure 6-1. CDMA TX chain block diagram. Bond wires have been shown to be a useful radiator at 60 GHz. The measurements and simulations are in qualitative agreement. It shoul d be possible to use them for inter-chip data communication over free space to solve the packaging cost problem. 6.2 Suggested Future Work (a) PLL output buffers have to be re-tuned. The interface between the mixer output and input of first pre-amplifier has also to be re-tuned. Finall y, attenuator sizes need to be better optimized. Better output power performance and more accura te level ratios are expected after these modifications. (b) Figure 6-2 shows the suggested measurement setup for the CDMA link demonstration. For the initial testing step, direct wire connection should be used. Ev entually, the link demonstration should be performed by using on-chip dipole antennas. The first step is to see if the proper multilevel signal can be observed at the receiver base band output. Afterwards, the multi-level signal should be fed into the ADC block for final data de-modulation. BER test should be performed to compare the demodulated data with that applied at the inputs of CDMA TX At the same time, a On-chip Antenna Multi-level CDMA control signal IF Power Amplifier Duplex Filter PLL (24-GHz) Digital Coder 12 GHz 4.8 GHz Pre-amplifier Attenuator LO 2 5 2 16.8 GHz

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115 CDR should be able to recover the 400-MHz clock that is suitable for use as a reference clock in the transmitter chain of motor side. (c) Integrate the RF receiver circuits into a transceiver in the dead-time controller side. Full duplex system demonstration should be performed. Figure 6-2. Suggested measurement se tup for the CDMA link demonstration. RX PCB DC Power Supply Oscilloscope TX PCB Signal Generator DC Power Supply Probe Probe cables On-chip dipole antenna Wireless link On-chip dipole antenna or

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116 APPENDIX A 90 DEGREE ANGLE CALIBRATION FOR GS (SG) PROBES Figure A-1 shows a calibration substrate CS-8 from GGB Industries Inc. There is a ring type calibration structure. This is the structur e used for 90 degree angle calibration, which is required for duplexer characteri zation. There are open, short, load, and th rough calibration structures. By using the standard calibration steps, 90 degree angle calibration for GS (SG) probes can be accomplished. Figure A-1. Ring type calib ration structures on the CS-8 calibration substrate. OPEN SHORT LOAD THRU

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117 APPENDIX B CDMA TRANSMITTER PRINTED CIRCUIT BOARD DESIGN CONSIDERATIONS There are several design considerations fo r the CDMA TX PCB. It has to have the flexibility to support multiple test scenarios. This is critical if certain blocks malfunction and need to be bypassed. Figure B-1 shows the la yout of TX chain. Seve ral internal nodes are brought out to GSSG pads for on-chip measurements and signal injection. For example, the PLL output pads are reserved for checking if the PLL is functional. An external source can also be used to drive the divider chain bl ocks and bypass the PLL block. Figure B-1. Die micrograph s howing internal testing nodes. PLL output Mixer IF port PA output Duplexer output

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118 The internal node, mixer IF input, can be used to apply an external 4.8-GHz signal if the IF divider chain is malfunctions. The PA output pa ds are reserved for checking the output power level without the duplexer. The connection betwee n the PA output pads and duplexer uses metal 8, which is convenient for laser cutting after fabri cation. Similarly, the duplexer output pads are also reserved for checking th e output power without the antenna. The TX chain should be carefully designed to account for the pad parasitics (Figure B-1). For testing scenarios other than the full transmitter, some bond wires have to be re moved. Therefore, careful pad arrangement is also critical at the chip design phase. The design of PCB also needs to take these issues into account to accommodate all the testing scenarios. Probe landing di rections must have a clean PCB surface, which means the offchip components could not be present along the landing path, shown in Figure B-2 (arrow Figure B-2. TX chain testing PCB showing possible landing directions. There should not be offchip components on the PCB su rface along the landing direction. GSSG Probe Landing direction (No off-chip components)

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119 direction means landing direction). Since the die is placed at a corn er of the PCB, the concern for the probe landing is mitigated. The only design is sue is to accommodate the lading for the mixer IF ports. As shown in Figure B-2, the landing di rection is from the left. The PCB surface is specially design to not have off-ch ip components along the landing path. Since there are over 50 bond wires for the transm itter chain, a careful pad arrangement is critical. In this work, a double row bonding scheme is adopted to save die area, shown in Figure B-3. The requirement for the double row bonding is to reserve sufficient separation between pads and rows. The reasonable separation between rows is 65 m. The separation between pads is 25 m. The pad size is 75 x 63 m2. Under this specific design, 0.8mil gold wire is used for wire Figure B-3. Double row bonding design with th e proper pad arrangement on the chip side.

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120 bonding. The total bond wire number is 77. One im portant requirement for pad arrangement on the chip side is to put ground bond pads at th e outer row. Since the ground bond pads on the PCB is closer to the chip edge than the other bond pads, shown in Figure B-4. The ground bond wires need to be bonded out first. The inner row bonding can have higher loop hei ght to avoid touching the ground bond wires. On the PCB side, a common finger length is 20 mil (5-mil finger width). In order to use double row bonding, 40-mil finger length is suggested by the bonding co mpany for better Figure B-4. Double row bonding design with a proper finger length on the PCB side. Chip GND

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121 bonding flexibility and may be able to tolerate slightly poor gold-plated surface shown in Figure B-4. Because there are lots of bond wires at the left hand side and bottom side, a larger separation between the chip edge and bond pads on the PCB is recommended. The separation is at least 3 mm, which is needed to properly angl e bond wires so that they do not touch each other. The last concern here is the trace width. The assembly house has the minimum specification of 5-mil trace width. If the over-etching is happened, it is safer to design the PCB metal traces to be 6 mil.

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122 LIST OF REFERENCES [1] D. Hermance, and S. Sasaki, Hybrid Electric Vehicles Take to The Streets, IEEE Spectrum, Vol. 35, Issue 11, pp. 48-52, Nov. 1998. [2] Floyd A Wyczalek, Market Mature 1998 Hybrid Electric Vehicles, IEEE Aerospace and Electronic Systems Magazine, Vol. 14, Issue 3, pp. 41-44, March 1999. [3] A kira Kawahashi, A New-Generation Hybrid Electric Vehicle and Its Supporting Power Semiconductor Devices, IEEE Power Semiconductor Devi ces and ICs Symp. Dig. Tech. Papers, pp. 23-29, 24-27 May 2004. [4] T. P. Bohn, R.D. Lorenz, and E. R. Olson, Measurement of In-Situ Currents in a Hybrid Electric Vehicle Integrated Power Module Using Giant Magnetoresistive Sensors, IEEE Power Electronics in Transportation, pp. 55-59, 2004. [5] K. K. O, K. Kim, B. Floyd, J. Mehta, H. Yoon, C.-M. Hung, D. Bravo, T. Dickson, X. Guo, R. Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, D.-J. Yang, J. Bohorquez, E. Seok, L. Gao, A. Sugavanam, J.-J. Lin, J. Chen, F. Martin, and J. E. Brewer, On-Chip Antennas in Silicon ICs and Their Application, IEEE Trans. Electron Devices, Vol. 52, Issue 7, pp. 1312-1323, July 2005. [6] K. Kim. H. Yoon, and K. K. O, On-chip wi reless interconnection with integrated antennas, Tech. Digest of IEDM, pp. 485-488, San Francisco, 2000. [7] Y. P. Zhang, M. Sun, and L. H. Guo, On-chip antennas for 60-GHz radios in silicon technology, IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1664-1668, July, 2005. [8] Y. Su, J.-J. Lin, and K. K. O, A 20GHz CMOS RF down-converter with an on-chip antenna, IEEE Int. Solid-State Circuits Conf Dig. Tech. Papers, pp. 270-271, Feb. 2005. [9] C. Cao, Y. Ding, X. Yang, J.-J. Lin, A. K. Verma, J. Lin, F. Martin, and K. K. O, A 24GHz transmitter with an on-chip antenna in 130-nm CMOS, in Symp. VLSI Circuits Dig. Tech. Papers, pp. 184-185, June 2006. [10] R. Li, Xi. Guo, Dong-Jun Yang, and K. K. O, Initialization of a wireless clock distribution system using an external antenna, IEEE CICC Dig. Tech. Papers, pp. 1051080, 18-21 Sept. 2005. [11] Xi. Guo, Dong-Jun Yang, R. Li, and K. K. O, A Receiver with Start-up Initialization and Programmable Delays for Wireless Clock Distribution, IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 1530-1539, Feb. 2006. [12] R. Li, Xi. Guo, Dong-Jun Yang, and K. K. O, Wireless Clock Distribution System Using an External Antenna, IEEE J. Solid-State Circuits, Vol. 42, no. 10, pp. 2283-2292, Oct. 2007.

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129 BIOGRAPHICAL SKETCH Hsin-Ta W u was born in Tainan, Taiwan, R.O.C., in December 1978. He received his Bachelor of Engineering degree in electrical engineering from National Taiwan University, Taipei, Taiwan in June 2001. After his two year military service (2001-2003), he went to the University of Florida for his Master degree. He received his Master of Science degree from the department of electrical and comput er engineering, University of Florida, Gainesville, Florida in May 2005. Currently, Mr. Wu is a Ph.D. candidate in the same department. Since 2004, he has been a member of the Silicon Microwave Integrated Circuits and Systems (SiMICS) research group. His research focuses on on-chip antenn as characteristics, electromagnetic wave propagation, wireless channel modeling, and microwave/RF CMOS ICs design.